block/IPCC:
  description: IPCC
  items:
  - name: CPU
    description: CPU specific registers
    array:
      len: 2
      stride: 16
    byte_offset: 0
    block: IPCC_CPU
block/IPCC_CPU:
  description: IPCC
  items:
  - name: CR
    description: Control register CPUx
    byte_offset: 0
    fieldset: CxCR
  - name: MR
    description: Mask register CPUx
    byte_offset: 4
    fieldset: CxMR
  - name: SCR
    description: Status Set or Clear register CPUx
    byte_offset: 8
    access: Write
    fieldset: CxSCR
  - name: SR
    description: CPUx to CPUy status register
    byte_offset: 12
    access: Read
    fieldset: CxTOySR
fieldset/CxCR:
  description: Control register CPUx
  fields:
  - name: RXOIE
    description: processor x Receive channel occupied interrupt enable
    bit_offset: 0
    bit_size: 1
  - name: TXFIE
    description: processor x Transmit channel free interrupt enable
    bit_offset: 16
    bit_size: 1
fieldset/CxMR:
  description: Mask register CPUx
  fields:
  - name: CHOM
    description: processor x Receive channel y occupied interrupt enable
    bit_offset: 0
    bit_size: 1
    array:
      len: 6
      stride: 1
  - name: CHFM
    description: processor x Transmit channel y free interrupt mask
    bit_offset: 16
    bit_size: 1
    array:
      len: 6
      stride: 1
fieldset/CxSCR:
  description: Status Set or Clear register CPUx
  fields:
  - name: CHC
    description: processor x Receive channel y status clear
    bit_offset: 0
    bit_size: 1
    array:
      len: 6
      stride: 1
  - name: CHS
    description: processor x Transmit channel y status set
    bit_offset: 16
    bit_size: 1
    array:
      len: 6
      stride: 1
fieldset/CxTOySR:
  description: CPUx to CPUy status register
  fields:
  - name: CHF
    description: processor x transmit to process y Receive channel z status flag
    bit_offset: 0
    bit_size: 1
    array:
      len: 6
      stride: 1