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stm32-data/data/registers/rcc_f7.yaml
eZio Pan 7419be3902 make compile pass
2024-01-08 16:31:06 +08:00

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block/RCC:
description: Reset and clock control
items:
- name: CR
description: clock control register
byte_offset: 0
fieldset: CR
- name: PLLCFGR
description: PLL configuration register
byte_offset: 4
fieldset: PLLCFGR
- name: CFGR
description: clock configuration register
byte_offset: 8
fieldset: CFGR
- name: CIR
description: clock interrupt register
byte_offset: 12
fieldset: CIR
- name: AHB1RSTR
description: AHB1 peripheral reset register
byte_offset: 16
fieldset: AHB1RSTR
- name: AHB2RSTR
description: AHB2 peripheral reset register
byte_offset: 20
fieldset: AHB2RSTR
- name: AHB3RSTR
description: AHB3 peripheral reset register
byte_offset: 24
fieldset: AHB3RSTR
- name: APB1RSTR
description: APB1 peripheral reset register
byte_offset: 32
fieldset: APB1RSTR
- name: APB2RSTR
description: APB2 peripheral reset register
byte_offset: 36
fieldset: APB2RSTR
- name: AHB1ENR
description: AHB1 peripheral clock register
byte_offset: 48
fieldset: AHB1ENR
- name: AHB2ENR
description: AHB2 peripheral clock enable register
byte_offset: 52
fieldset: AHB2ENR
- name: AHB3ENR
description: AHB3 peripheral clock enable register
byte_offset: 56
fieldset: AHB3ENR
- name: APB1ENR
description: APB1 peripheral clock enable register
byte_offset: 64
fieldset: APB1ENR
- name: APB2ENR
description: APB2 peripheral clock enable register
byte_offset: 68
fieldset: APB2ENR
- name: AHB1LPENR
description: AHB1 peripheral clock enable in low power mode register
byte_offset: 80
fieldset: AHB1LPENR
- name: AHB2LPENR
description: AHB2 peripheral clock enable in low power mode register
byte_offset: 84
fieldset: AHB2LPENR
- name: AHB3LPENR
description: AHB3 peripheral clock enable in low power mode register
byte_offset: 88
fieldset: AHB3LPENR
- name: APB1LPENR
description: APB1 peripheral clock enable in low power mode register
byte_offset: 96
fieldset: APB1LPENR
- name: APB2LPENR
description: APB2 peripheral clock enabled in low power mode register
byte_offset: 100
fieldset: APB2LPENR
- name: BDCR
description: Backup domain control register
byte_offset: 112
fieldset: BDCR
- name: CSR
description: clock control & status register
byte_offset: 116
fieldset: CSR
- name: SSCGR
description: spread spectrum clock generation register
byte_offset: 128
fieldset: SSCGR
- name: PLLI2SCFGR
description: PLLI2S configuration register
byte_offset: 132
fieldset: PLLI2SCFGR
- name: PLLSAICFGR
description: PLL configuration register
byte_offset: 136
fieldset: PLLSAICFGR
- name: DCKCFGR1
description: dedicated clocks configuration register
byte_offset: 140
fieldset: DCKCFGR1
- name: DCKCFGR2
description: dedicated clocks configuration register
byte_offset: 144
fieldset: DCKCFGR2
fieldset/AHB1ENR:
description: AHB1 peripheral clock register
fields:
- name: GPIOAEN
description: IO port A clock enable
bit_offset: 0
bit_size: 1
- name: GPIOBEN
description: IO port B clock enable
bit_offset: 1
bit_size: 1
- name: GPIOCEN
description: IO port C clock enable
bit_offset: 2
bit_size: 1
- name: GPIODEN
description: IO port D clock enable
bit_offset: 3
bit_size: 1
- name: GPIOEEN
description: IO port E clock enable
bit_offset: 4
bit_size: 1
- name: GPIOFEN
description: IO port F clock enable
bit_offset: 5
bit_size: 1
- name: GPIOGEN
description: IO port G clock enable
bit_offset: 6
bit_size: 1
- name: GPIOHEN
description: IO port H clock enable
bit_offset: 7
bit_size: 1
- name: GPIOIEN
description: IO port I clock enable
bit_offset: 8
bit_size: 1
- name: GPIOJEN
description: IO port J clock enable
bit_offset: 9
bit_size: 1
- name: GPIOKEN
description: IO port K clock enable
bit_offset: 10
bit_size: 1
- name: CRCEN
description: CRC clock enable
bit_offset: 12
bit_size: 1
- name: BKPSRAMEN
description: Backup SRAM interface clock enable
bit_offset: 18
bit_size: 1
- name: DTCMRAMEN
description: CCM data RAM clock enable
bit_offset: 20
bit_size: 1
- name: DMA1EN
description: DMA1 clock enable
bit_offset: 21
bit_size: 1
- name: DMA2EN
description: DMA2 clock enable
bit_offset: 22
bit_size: 1
- name: DMA2DEN
description: DMA2D clock enable
bit_offset: 23
bit_size: 1
- name: ETHEN
description: Ethernet MAC clock enable
bit_offset: 25
bit_size: 1
- name: ETHTXEN
description: Ethernet Transmission clock enable
bit_offset: 26
bit_size: 1
- name: ETHRXEN
description: Ethernet Reception clock enable
bit_offset: 27
bit_size: 1
- name: ETHPTPEN
description: Ethernet PTP clock enable
bit_offset: 28
bit_size: 1
- name: USB_OTG_HSEN
description: USB OTG HS clock enable
bit_offset: 29
bit_size: 1
- name: USB_OTG_HSULPIEN
description: USB OTG HSULPI clock enable
bit_offset: 30
bit_size: 1
fieldset/AHB1LPENR:
description: AHB1 peripheral clock enable in low power mode register
fields:
- name: GPIOALPEN
description: IO port A clock enable during sleep mode
bit_offset: 0
bit_size: 1
- name: GPIOBLPEN
description: IO port B clock enable during Sleep mode
bit_offset: 1
bit_size: 1
- name: GPIOCLPEN
description: IO port C clock enable during Sleep mode
bit_offset: 2
bit_size: 1
- name: GPIODLPEN
description: IO port D clock enable during Sleep mode
bit_offset: 3
bit_size: 1
- name: GPIOELPEN
description: IO port E clock enable during Sleep mode
bit_offset: 4
bit_size: 1
- name: GPIOFLPEN
description: IO port F clock enable during Sleep mode
bit_offset: 5
bit_size: 1
- name: GPIOGLPEN
description: IO port G clock enable during Sleep mode
bit_offset: 6
bit_size: 1
- name: GPIOHLPEN
description: IO port H clock enable during Sleep mode
bit_offset: 7
bit_size: 1
- name: GPIOILPEN
description: IO port I clock enable during Sleep mode
bit_offset: 8
bit_size: 1
- name: GPIOJLPEN
description: IO port J clock enable during Sleep mode
bit_offset: 9
bit_size: 1
- name: GPIOKLPEN
description: IO port K clock enable during Sleep mode
bit_offset: 10
bit_size: 1
- name: CRCLPEN
description: CRC clock enable during Sleep mode
bit_offset: 12
bit_size: 1
- name: AXILPEN
description: AXI to AHB bridge clock enable during Sleep mode
bit_offset: 13
bit_size: 1
- name: FLASHLPEN
description: Flash interface clock enable during Sleep mode
bit_offset: 15
bit_size: 1
- name: SRAM1LPEN
description: SRAM 1interface clock enable during Sleep mode
bit_offset: 16
bit_size: 1
- name: SRAM2LPEN
description: SRAM 2 interface clock enable during Sleep mode
bit_offset: 17
bit_size: 1
- name: BKPSRAMLPEN
description: Backup SRAM interface clock enable during Sleep mode
bit_offset: 18
bit_size: 1
- name: SRAM3LPEN
description: SRAM 3 interface clock enable during Sleep mode
bit_offset: 19
bit_size: 1
- name: DTCMLPEN
description: DTCM RAM interface clock enable during Sleep mode
bit_offset: 20
bit_size: 1
- name: DMA1LPEN
description: DMA1 clock enable during Sleep mode
bit_offset: 21
bit_size: 1
- name: DMA2LPEN
description: DMA2 clock enable during Sleep mode
bit_offset: 22
bit_size: 1
- name: DMA2DLPEN
description: DMA2D clock enable during Sleep mode
bit_offset: 23
bit_size: 1
- name: ETHLPEN
description: Ethernet MAC clock enable during Sleep mode
bit_offset: 25
bit_size: 1
- name: ETHTXLPEN
description: Ethernet transmission clock enable during Sleep mode
bit_offset: 26
bit_size: 1
- name: ETHRXLPEN
description: Ethernet reception clock enable during Sleep mode
bit_offset: 27
bit_size: 1
- name: ETHPTPLPEN
description: Ethernet PTP clock enable during Sleep mode
bit_offset: 28
bit_size: 1
- name: USB_OTG_HSLPEN
description: USB OTG HS clock enable during Sleep mode
bit_offset: 29
bit_size: 1
- name: USB_OTG_HSULPILPEN
description: USB OTG HS ULPI clock enable during Sleep mode
bit_offset: 30
bit_size: 1
fieldset/AHB1RSTR:
description: AHB1 peripheral reset register
fields:
- name: GPIOARST
description: IO port A reset
bit_offset: 0
bit_size: 1
- name: GPIOBRST
description: IO port B reset
bit_offset: 1
bit_size: 1
- name: GPIOCRST
description: IO port C reset
bit_offset: 2
bit_size: 1
- name: GPIODRST
description: IO port D reset
bit_offset: 3
bit_size: 1
- name: GPIOERST
description: IO port E reset
bit_offset: 4
bit_size: 1
- name: GPIOFRST
description: IO port F reset
bit_offset: 5
bit_size: 1
- name: GPIOGRST
description: IO port G reset
bit_offset: 6
bit_size: 1
- name: GPIOHRST
description: IO port H reset
bit_offset: 7
bit_size: 1
- name: GPIOIRST
description: IO port I reset
bit_offset: 8
bit_size: 1
- name: GPIOJRST
description: IO port J reset
bit_offset: 9
bit_size: 1
- name: GPIOKRST
description: IO port K reset
bit_offset: 10
bit_size: 1
- name: CRCRST
description: CRC reset
bit_offset: 12
bit_size: 1
- name: DMA1RST
description: DMA2 reset
bit_offset: 21
bit_size: 1
- name: DMA2RST
description: DMA2 reset
bit_offset: 22
bit_size: 1
- name: DMA2DRST
description: DMA2D reset
bit_offset: 23
bit_size: 1
- name: ETHRST
description: Ethernet MAC reset
bit_offset: 25
bit_size: 1
- name: USB_OTG_HSRST
description: USB OTG HS module reset
bit_offset: 29
bit_size: 1
fieldset/AHB2ENR:
description: AHB2 peripheral clock enable register
fields:
- name: DCMIEN
description: Camera interface enable
bit_offset: 0
bit_size: 1
- name: JPEGEN
description: JPEG enable
bit_offset: 1
bit_size: 1
- name: AESEN
description: AES module clock enable
bit_offset: 4
bit_size: 1
- name: CRYPEN
description: Cryptographic modules clock enable
bit_offset: 4
bit_size: 1
- name: HASHEN
description: Hash modules clock enable
bit_offset: 5
bit_size: 1
- name: RNGEN
description: Random number generator clock enable
bit_offset: 6
bit_size: 1
- name: USB_OTG_FSEN
description: USB OTG FS clock enable
bit_offset: 7
bit_size: 1
fieldset/AHB2LPENR:
description: AHB2 peripheral clock enable in low power mode register
fields:
- name: DCMILPEN
description: Camera interface enable during Sleep mode
bit_offset: 0
bit_size: 1
- name: JPEGLPEN
description: JPEG module enabled during Sleep mode
bit_offset: 1
bit_size: 1
- name: AESLPEN
description: AES module clock enable during Sleep mode
bit_offset: 4
bit_size: 1
- name: CRYPLPEN
description: Cryptography modules clock enable during Sleep mode
bit_offset: 4
bit_size: 1
- name: HASHLPEN
description: Hash modules clock enable during Sleep mode
bit_offset: 5
bit_size: 1
- name: RNGLPEN
description: Random number generator clock enable during Sleep mode
bit_offset: 6
bit_size: 1
- name: USB_OTG_FSLPEN
description: USB OTG FS clock enable during Sleep mode
bit_offset: 7
bit_size: 1
fieldset/AHB2RSTR:
description: AHB2 peripheral reset register
fields:
- name: DCMIRST
description: Camera interface reset
bit_offset: 0
bit_size: 1
- name: AESRST
description: AES module reset
bit_offset: 4
bit_size: 1
- name: CRYPRST
description: Cryptographic module reset
bit_offset: 4
bit_size: 1
- name: HSAHRST
description: Hash module reset
bit_offset: 5
bit_size: 1
- name: RNGRST
description: Random number generator module reset
bit_offset: 6
bit_size: 1
- name: USB_OTG_FSRST
description: USB OTG FS module reset
bit_offset: 7
bit_size: 1
fieldset/AHB3ENR:
description: AHB3 peripheral clock enable register
fields:
- name: FMCEN
description: Flexible memory controller module clock enable
bit_offset: 0
bit_size: 1
- name: QUADSPIEN
description: Quad SPI memory controller clock enable
bit_offset: 1
bit_size: 1
fieldset/AHB3LPENR:
description: AHB3 peripheral clock enable in low power mode register
fields:
- name: FMCLPEN
description: Flexible memory controller module clock enable during Sleep mode
bit_offset: 0
bit_size: 1
- name: QUADSPILPEN
description: Quand SPI memory controller clock enable during Sleep mode
bit_offset: 1
bit_size: 1
fieldset/AHB3RSTR:
description: AHB3 peripheral reset register
fields:
- name: FMCRST
description: Flexible memory controller module reset
bit_offset: 0
bit_size: 1
- name: QUADSPIRST
description: Quad SPI memory controller reset
bit_offset: 1
bit_size: 1
fieldset/APB1ENR:
description: APB1 peripheral clock enable register
fields:
- name: TIM2EN
description: TIM2 clock enable
bit_offset: 0
bit_size: 1
- name: TIM3EN
description: TIM3 clock enable
bit_offset: 1
bit_size: 1
- name: TIM4EN
description: TIM4 clock enable
bit_offset: 2
bit_size: 1
- name: TIM5EN
description: TIM5 clock enable
bit_offset: 3
bit_size: 1
- name: TIM6EN
description: TIM6 clock enable
bit_offset: 4
bit_size: 1
- name: TIM7EN
description: TIM7 clock enable
bit_offset: 5
bit_size: 1
- name: TIM12EN
description: TIM12 clock enable
bit_offset: 6
bit_size: 1
- name: TIM13EN
description: TIM13 clock enable
bit_offset: 7
bit_size: 1
- name: TIM14EN
description: TIM14 clock enable
bit_offset: 8
bit_size: 1
- name: LPTIM1EN
description: Low power timer 1 clock enable
bit_offset: 9
bit_size: 1
- name: RTCEN
description: RTCAPB clock enable
bit_offset: 10
bit_size: 1
- name: WWDGEN
description: Window watchdog clock enable
bit_offset: 11
bit_size: 1
- name: CAN3EN
description: CAN 3 enable
bit_offset: 13
bit_size: 1
- name: SPI2EN
description: SPI2 clock enable
bit_offset: 14
bit_size: 1
- name: SPI3EN
description: SPI3 clock enable
bit_offset: 15
bit_size: 1
- name: SPDIFRXEN
description: SPDIF-RX clock enable
bit_offset: 16
bit_size: 1
- name: USART2EN
description: USART 2 clock enable
bit_offset: 17
bit_size: 1
- name: USART3EN
description: USART3 clock enable
bit_offset: 18
bit_size: 1
- name: UART4EN
description: UART4 clock enable
bit_offset: 19
bit_size: 1
- name: UART5EN
description: UART5 clock enable
bit_offset: 20
bit_size: 1
- name: I2C1EN
description: I2C1 clock enable
bit_offset: 21
bit_size: 1
- name: I2C2EN
description: I2C2 clock enable
bit_offset: 22
bit_size: 1
- name: I2C3EN
description: I2C3 clock enable
bit_offset: 23
bit_size: 1
- name: I2C4EN
description: I2C4 clock enable
bit_offset: 24
bit_size: 1
- name: CAN1EN
description: CAN 1 clock enable
bit_offset: 25
bit_size: 1
- name: CAN2EN
description: CAN 2 clock enable
bit_offset: 26
bit_size: 1
- name: CECEN
description: HDMI-CEN clock enable
bit_offset: 27
bit_size: 1
- name: PWREN
description: Power interface clock enable
bit_offset: 28
bit_size: 1
- name: DACEN
description: DAC interface clock enable
bit_offset: 29
bit_size: 1
- name: UART7EN
description: UART7 clock enable
bit_offset: 30
bit_size: 1
- name: UART8EN
description: UART8 clock enable
bit_offset: 31
bit_size: 1
fieldset/APB1LPENR:
description: APB1 peripheral clock enable in low power mode register
fields:
- name: TIM2LPEN
description: TIM2 clock enable during Sleep mode
bit_offset: 0
bit_size: 1
- name: TIM3LPEN
description: TIM3 clock enable during Sleep mode
bit_offset: 1
bit_size: 1
- name: TIM4LPEN
description: TIM4 clock enable during Sleep mode
bit_offset: 2
bit_size: 1
- name: TIM5LPEN
description: TIM5 clock enable during Sleep mode
bit_offset: 3
bit_size: 1
- name: TIM6LPEN
description: TIM6 clock enable during Sleep mode
bit_offset: 4
bit_size: 1
- name: TIM7LPEN
description: TIM7 clock enable during Sleep mode
bit_offset: 5
bit_size: 1
- name: TIM12LPEN
description: TIM12 clock enable during Sleep mode
bit_offset: 6
bit_size: 1
- name: TIM13LPEN
description: TIM13 clock enable during Sleep mode
bit_offset: 7
bit_size: 1
- name: TIM14LPEN
description: TIM14 clock enable during Sleep mode
bit_offset: 8
bit_size: 1
- name: LPTIM1LPEN
description: low power timer 1 clock enable during Sleep mode
bit_offset: 9
bit_size: 1
- name: RTCLPEN
description: RTCAPB clock enable during Sleep mode
bit_offset: 10
bit_size: 1
- name: WWDGLPEN
description: Window watchdog clock enable during Sleep mode
bit_offset: 11
bit_size: 1
- name: CAN3LPEN
description: CAN 3 clock enable during Sleep mode
bit_offset: 13
bit_size: 1
- name: SPI2LPEN
description: SPI2 clock enable during Sleep mode
bit_offset: 14
bit_size: 1
- name: SPI3LPEN
description: SPI3 clock enable during Sleep mode
bit_offset: 15
bit_size: 1
- name: SPDIFRXLPEN
description: SPDIF-RX clock enable during sleep mode
bit_offset: 16
bit_size: 1
- name: USART2LPEN
description: USART2 clock enable during Sleep mode
bit_offset: 17
bit_size: 1
- name: USART3LPEN
description: USART3 clock enable during Sleep mode
bit_offset: 18
bit_size: 1
- name: UART4LPEN
description: UART4 clock enable during Sleep mode
bit_offset: 19
bit_size: 1
- name: UART5LPEN
description: UART5 clock enable during Sleep mode
bit_offset: 20
bit_size: 1
- name: I2C1LPEN
description: I2C1 clock enable during Sleep mode
bit_offset: 21
bit_size: 1
- name: I2C2LPEN
description: I2C2 clock enable during Sleep mode
bit_offset: 22
bit_size: 1
- name: I2C3LPEN
description: I2C3 clock enable during Sleep mode
bit_offset: 23
bit_size: 1
- name: I2C4LPEN
description: I2C4 clock enable during Sleep mode
bit_offset: 24
bit_size: 1
- name: CAN1LPEN
description: CAN 1 clock enable during Sleep mode
bit_offset: 25
bit_size: 1
- name: CAN2LPEN
description: CAN 2 clock enable during Sleep mode
bit_offset: 26
bit_size: 1
- name: CECLPEN
description: HDMI-CEN clock enable during Sleep mode
bit_offset: 27
bit_size: 1
- name: PWRLPEN
description: Power interface clock enable during Sleep mode
bit_offset: 28
bit_size: 1
- name: DACLPEN
description: DAC interface clock enable during Sleep mode
bit_offset: 29
bit_size: 1
- name: UART7LPEN
description: UART7 clock enable during Sleep mode
bit_offset: 30
bit_size: 1
- name: UART8LPEN
description: UART8 clock enable during Sleep mode
bit_offset: 31
bit_size: 1
fieldset/APB1RSTR:
description: APB1 peripheral reset register
fields:
- name: TIM2RST
description: TIM2 reset
bit_offset: 0
bit_size: 1
- name: TIM3RST
description: TIM3 reset
bit_offset: 1
bit_size: 1
- name: TIM4RST
description: TIM4 reset
bit_offset: 2
bit_size: 1
- name: TIM5RST
description: TIM5 reset
bit_offset: 3
bit_size: 1
- name: TIM6RST
description: TIM6 reset
bit_offset: 4
bit_size: 1
- name: TIM7RST
description: TIM7 reset
bit_offset: 5
bit_size: 1
- name: TIM12RST
description: TIM12 reset
bit_offset: 6
bit_size: 1
- name: TIM13RST
description: TIM13 reset
bit_offset: 7
bit_size: 1
- name: TIM14RST
description: TIM14 reset
bit_offset: 8
bit_size: 1
- name: LPTIM1RST
description: Low power timer 1 reset
bit_offset: 9
bit_size: 1
- name: WWDGRST
description: Window watchdog reset
bit_offset: 11
bit_size: 1
- name: CAN3RST
description: CAN 3 reset
bit_offset: 13
bit_size: 1
- name: SPI2RST
description: SPI 2 reset
bit_offset: 14
bit_size: 1
- name: SPI3RST
description: SPI 3 reset
bit_offset: 15
bit_size: 1
- name: SPDIFRXRST
description: SPDIF-RX reset
bit_offset: 16
bit_size: 1
- name: USART2RST
description: USART 2 reset
bit_offset: 17
bit_size: 1
- name: USART3RST
description: USART 3 reset
bit_offset: 18
bit_size: 1
- name: UART4RST
description: USART 4 reset
bit_offset: 19
bit_size: 1
- name: UART5RST
description: USART 5 reset
bit_offset: 20
bit_size: 1
- name: I2C1RST
description: I2C 1 reset
bit_offset: 21
bit_size: 1
- name: I2C2RST
description: I2C 2 reset
bit_offset: 22
bit_size: 1
- name: I2C3RST
description: I2C3 reset
bit_offset: 23
bit_size: 1
- name: I2C4RST
description: I2C 4 reset
bit_offset: 24
bit_size: 1
- name: CAN1RST
description: CAN1 reset
bit_offset: 25
bit_size: 1
- name: CAN2RST
description: CAN2 reset
bit_offset: 26
bit_size: 1
- name: CECRST
description: HDMI-CEC reset
bit_offset: 27
bit_size: 1
- name: PWRRST
description: Power interface reset
bit_offset: 28
bit_size: 1
- name: DACRST
description: DAC reset
bit_offset: 29
bit_size: 1
- name: UART7RST
description: UART7 reset
bit_offset: 30
bit_size: 1
- name: UART8RST
description: UART8 reset
bit_offset: 31
bit_size: 1
fieldset/APB2ENR:
description: APB2 peripheral clock enable register
fields:
- name: TIM1EN
description: TIM1 clock enable
bit_offset: 0
bit_size: 1
- name: TIM8EN
description: TIM8 clock enable
bit_offset: 1
bit_size: 1
- name: USART1EN
description: USART1 clock enable
bit_offset: 4
bit_size: 1
- name: USART6EN
description: USART6 clock enable
bit_offset: 5
bit_size: 1
- name: SDMMC2EN
description: SDMMC2 clock enable
bit_offset: 7
bit_size: 1
- name: ADC1EN
description: ADC1 clock enable
bit_offset: 8
bit_size: 1
- name: ADC2EN
description: ADC2 clock enable
bit_offset: 9
bit_size: 1
- name: ADC3EN
description: ADC3 clock enable
bit_offset: 10
bit_size: 1
- name: SDMMC1EN
description: SDMMC1 clock enable
bit_offset: 11
bit_size: 1
- name: SPI1EN
description: SPI1 clock enable
bit_offset: 12
bit_size: 1
- name: SPI4EN
description: SPI4 clock enable
bit_offset: 13
bit_size: 1
- name: SYSCFGEN
description: System configuration controller clock enable
bit_offset: 14
bit_size: 1
- name: TIM9EN
description: TIM9 clock enable
bit_offset: 16
bit_size: 1
- name: TIM10EN
description: TIM10 clock enable
bit_offset: 17
bit_size: 1
- name: TIM11EN
description: TIM11 clock enable
bit_offset: 18
bit_size: 1
- name: SPI5EN
description: SPI5 clock enable
bit_offset: 20
bit_size: 1
- name: SPI6EN
description: SPI6 clock enable
bit_offset: 21
bit_size: 1
- name: SAI1EN
description: SAI1 clock enable
bit_offset: 22
bit_size: 1
- name: SAI2EN
description: SAI2 clock enable
bit_offset: 23
bit_size: 1
- name: LTDCEN
description: LTDC clock enable
bit_offset: 26
bit_size: 1
- name: DSIEN
description: DSI clock enable
bit_offset: 27
bit_size: 1
- name: DFSDM1EN
description: DFSDM1 clock enable
bit_offset: 29
bit_size: 1
- name: MDIOSEN
description: MDIO clock enable
bit_offset: 30
bit_size: 1
- name: USBPHYCEN
description: USB OTG HS PHY controller clock enable
bit_offset: 31
bit_size: 1
fieldset/APB2LPENR:
description: APB2 peripheral clock enabled in low power mode register
fields:
- name: TIM1LPEN
description: TIM1 clock enable during Sleep mode
bit_offset: 0
bit_size: 1
- name: TIM8LPEN
description: TIM8 clock enable during Sleep mode
bit_offset: 1
bit_size: 1
- name: USART1LPEN
description: USART1 clock enable during Sleep mode
bit_offset: 4
bit_size: 1
- name: USART6LPEN
description: USART6 clock enable during Sleep mode
bit_offset: 5
bit_size: 1
- name: SDMMC2LPEN
description: SDMMC2 clock enable during Sleep mode
bit_offset: 7
bit_size: 1
- name: ADC1LPEN
description: ADC1 clock enable during Sleep mode
bit_offset: 8
bit_size: 1
- name: ADC2LPEN
description: ADC2 clock enable during Sleep mode
bit_offset: 9
bit_size: 1
- name: ADC3LPEN
description: ADC 3 clock enable during Sleep mode
bit_offset: 10
bit_size: 1
- name: SDMMC1LPEN
description: SDMMC1 clock enable during Sleep mode
bit_offset: 11
bit_size: 1
- name: SPI1LPEN
description: SPI 1 clock enable during Sleep mode
bit_offset: 12
bit_size: 1
- name: SPI4LPEN
description: SPI 4 clock enable during Sleep mode
bit_offset: 13
bit_size: 1
- name: SYSCFGLPEN
description: System configuration controller clock enable during Sleep mode
bit_offset: 14
bit_size: 1
- name: TIM9LPEN
description: TIM9 clock enable during sleep mode
bit_offset: 16
bit_size: 1
- name: TIM10LPEN
description: TIM10 clock enable during Sleep mode
bit_offset: 17
bit_size: 1
- name: TIM11LPEN
description: TIM11 clock enable during Sleep mode
bit_offset: 18
bit_size: 1
- name: SPI5LPEN
description: SPI 5 clock enable during Sleep mode
bit_offset: 20
bit_size: 1
- name: SPI6LPEN
description: SPI 6 clock enable during Sleep mode
bit_offset: 21
bit_size: 1
- name: SAI1LPEN
description: SAI1 clock enable during sleep mode
bit_offset: 22
bit_size: 1
- name: SAI2LPEN
description: SAI2 clock enable during sleep mode
bit_offset: 23
bit_size: 1
- name: LTDCLPEN
description: LTDC clock enable during sleep mode
bit_offset: 26
bit_size: 1
- name: DSILPEN
description: DSI clock enable during Sleep mode
bit_offset: 27
bit_size: 1
- name: DFSDM1LPEN
description: DFSDM1 clock enable during Sleep mode
bit_offset: 29
bit_size: 1
- name: MDIOSLPEN
description: MDIO clock enable during Sleep mode
bit_offset: 30
bit_size: 1
fieldset/APB2RSTR:
description: APB2 peripheral reset register
fields:
- name: TIM1RST
description: TIM1 reset
bit_offset: 0
bit_size: 1
- name: TIM8RST
description: TIM8 reset
bit_offset: 1
bit_size: 1
- name: USART1RST
description: USART1 reset
bit_offset: 4
bit_size: 1
- name: USART6RST
description: USART6 reset
bit_offset: 5
bit_size: 1
- name: SDMMC2RST
description: SDMMC2 reset
bit_offset: 7
bit_size: 1
- name: ADCRST
description: ADC interface reset (common to all ADCs)
bit_offset: 8
bit_size: 1
- name: SDMMC1RST
description: SDMMC1 reset
bit_offset: 11
bit_size: 1
- name: SPI1RST
description: SPI 1 reset
bit_offset: 12
bit_size: 1
- name: SPI4RST
description: SPI4 reset
bit_offset: 13
bit_size: 1
- name: SYSCFGRST
description: System configuration controller reset
bit_offset: 14
bit_size: 1
- name: TIM9RST
description: TIM9 reset
bit_offset: 16
bit_size: 1
- name: TIM10RST
description: TIM10 reset
bit_offset: 17
bit_size: 1
- name: TIM11RST
description: TIM11 reset
bit_offset: 18
bit_size: 1
- name: SPI5RST
description: SPI5 reset
bit_offset: 20
bit_size: 1
- name: SPI6RST
description: SPI6 reset
bit_offset: 21
bit_size: 1
- name: SAI1RST
description: SAI1 reset
bit_offset: 22
bit_size: 1
- name: SAI2RST
description: SAI2 reset
bit_offset: 23
bit_size: 1
- name: LTDCRST
description: LTDC reset
bit_offset: 26
bit_size: 1
- name: DSIRST
description: DSI reset
bit_offset: 27
bit_size: 1
- name: DFSDM1RST
description: DFSDM 1 reset
bit_offset: 29
bit_size: 1
- name: MDIOSRST
description: MDIOS reset
bit_offset: 30
bit_size: 1
- name: USBPHYCRST
description: USB OTG HS PHY controller reset
bit_offset: 31
bit_size: 1
fieldset/BDCR:
description: Backup domain control register
fields:
- name: LSEON
description: External low-speed oscillator enable
bit_offset: 0
bit_size: 1
- name: LSERDY
description: External low-speed oscillator ready
bit_offset: 1
bit_size: 1
- name: LSEBYP
description: External low-speed oscillator bypass
bit_offset: 2
bit_size: 1
- name: LSEDRV
description: LSE oscillator drive capability
bit_offset: 3
bit_size: 2
enum: LSEDRV
- name: RTCSEL
description: RTC clock source selection
bit_offset: 8
bit_size: 2
enum: RTCSEL
- name: RTCEN
description: RTC clock enable
bit_offset: 15
bit_size: 1
- name: BDRST
description: Backup domain software reset
bit_offset: 16
bit_size: 1
fieldset/CFGR:
description: clock configuration register
fields:
- name: SW
description: System clock switch
bit_offset: 0
bit_size: 2
enum: SW
- name: SWS
description: System clock switch status
bit_offset: 2
bit_size: 2
enum: SW
- name: HPRE
description: AHB prescaler
bit_offset: 4
bit_size: 4
enum: HPRE
- name: PPRE1
description: APB Low speed prescaler (APB1)
bit_offset: 10
bit_size: 3
enum: PPRE
- name: PPRE2
description: APB high-speed prescaler (APB2)
bit_offset: 13
bit_size: 3
enum: PPRE
- name: RTCPRE
description: HSE division factor for RTC clock
bit_offset: 16
bit_size: 5
- name: MCO1SEL
description: Microcontroller clock output 1
bit_offset: 21
bit_size: 2
enum: MCO1SEL
- name: I2SSRC
description: I2S clock selection
bit_offset: 23
bit_size: 1
enum: ISSRC
- name: MCO1PRE
description: MCO1 prescaler
bit_offset: 24
bit_size: 3
enum: MCOPRE
- name: MCO2PRE
description: MCO2 prescaler
bit_offset: 27
bit_size: 3
enum: MCOPRE
- name: MCO2SEL
description: Microcontroller clock output 2
bit_offset: 30
bit_size: 2
enum: MCO2SEL
fieldset/CIR:
description: clock interrupt register
fields:
- name: LSIRDYF
description: LSI ready interrupt flag
bit_offset: 0
bit_size: 1
- name: LSERDYF
description: LSE ready interrupt flag
bit_offset: 1
bit_size: 1
- name: HSIRDYF
description: HSI ready interrupt flag
bit_offset: 2
bit_size: 1
- name: HSERDYF
description: HSE ready interrupt flag
bit_offset: 3
bit_size: 1
- name: PLLRDYF
description: PLL ready interrupt flag
bit_offset: 4
bit_size: 1
- name: PLLI2SRDYF
description: PLLI2S ready interrupt flag
bit_offset: 5
bit_size: 1
- name: PLLSAIRDYF
description: PLLSAI ready interrupt flag
bit_offset: 6
bit_size: 1
- name: CSSF
description: Clock security system interrupt flag
bit_offset: 7
bit_size: 1
- name: LSIRDYIE
description: LSI ready interrupt enable
bit_offset: 8
bit_size: 1
- name: LSERDYIE
description: LSE ready interrupt enable
bit_offset: 9
bit_size: 1
- name: HSIRDYIE
description: HSI ready interrupt enable
bit_offset: 10
bit_size: 1
- name: HSERDYIE
description: HSE ready interrupt enable
bit_offset: 11
bit_size: 1
- name: PLLRDYIE
description: PLL ready interrupt enable
bit_offset: 12
bit_size: 1
- name: PLLI2SRDYIE
description: PLLI2S ready interrupt enable
bit_offset: 13
bit_size: 1
- name: PLLSAIRDYIE
description: PLLSAI Ready Interrupt Enable
bit_offset: 14
bit_size: 1
- name: LSIRDYC
description: LSI ready interrupt clear
bit_offset: 16
bit_size: 1
- name: LSERDYC
description: LSE ready interrupt clear
bit_offset: 17
bit_size: 1
- name: HSIRDYC
description: HSI ready interrupt clear
bit_offset: 18
bit_size: 1
- name: HSERDYC
description: HSE ready interrupt clear
bit_offset: 19
bit_size: 1
- name: PLLRDYC
description: Main PLL(PLL) ready interrupt clear
bit_offset: 20
bit_size: 1
- name: PLLI2SRDYC
description: PLLI2S ready interrupt clear
bit_offset: 21
bit_size: 1
- name: PLLSAIRDYC
description: PLLSAI Ready Interrupt Clear
bit_offset: 22
bit_size: 1
- name: CSSC
description: Clock security system interrupt clear
bit_offset: 23
bit_size: 1
fieldset/CR:
description: clock control register
fields:
- name: HSION
description: Internal high-speed clock enable
bit_offset: 0
bit_size: 1
- name: HSIRDY
description: Internal high-speed clock ready flag
bit_offset: 1
bit_size: 1
- name: HSITRIM
description: Internal high-speed clock trimming
bit_offset: 3
bit_size: 5
- name: HSICAL
description: Internal high-speed clock calibration
bit_offset: 8
bit_size: 8
- name: HSEON
description: HSE clock enable
bit_offset: 16
bit_size: 1
- name: HSERDY
description: HSE clock ready flag
bit_offset: 17
bit_size: 1
- name: HSEBYP
description: HSE clock bypass
bit_offset: 18
bit_size: 1
- name: CSSON
description: Clock security system enable
bit_offset: 19
bit_size: 1
- name: PLLON
description: PLL enable
bit_offset: 24
bit_size: 1
- name: PLLRDY
description: PLL clock ready flag
bit_offset: 25
bit_size: 1
- name: PLLI2SON
description: PLLI2S enable
bit_offset: 26
bit_size: 1
- name: PLLI2SRDY
description: PLLI2S clock ready flag
bit_offset: 27
bit_size: 1
- name: PLLSAION
description: PLLSAI enable
bit_offset: 28
bit_size: 1
- name: PLLSAIRDY
description: PLLSAI clock ready flag
bit_offset: 29
bit_size: 1
fieldset/CSR:
description: clock control & status register
fields:
- name: LSION
description: Internal low-speed oscillator enable
bit_offset: 0
bit_size: 1
- name: LSIRDY
description: Internal low-speed oscillator ready
bit_offset: 1
bit_size: 1
- name: RMVF
description: Remove reset flag
bit_offset: 24
bit_size: 1
- name: BORRSTF
description: BOR reset flag
bit_offset: 25
bit_size: 1
- name: PADRSTF
description: PIN reset flag
bit_offset: 26
bit_size: 1
- name: PORRSTF
description: POR/PDR reset flag
bit_offset: 27
bit_size: 1
- name: SFTRSTF
description: Software reset flag
bit_offset: 28
bit_size: 1
- name: WDGRSTF
description: Independent watchdog reset flag
bit_offset: 29
bit_size: 1
- name: WWDGRSTF
description: Window watchdog reset flag
bit_offset: 30
bit_size: 1
- name: LPWRRSTF
description: Low-power reset flag
bit_offset: 31
bit_size: 1
fieldset/DCKCFGR1:
description: dedicated clocks configuration register
fields:
- name: PLLI2SDIVQ
description: PLLI2S division factor for SAI1 clock
bit_offset: 0
bit_size: 5
enum: PLLI2SDIVQ
- name: PLLSAIDIVQ
description: PLLSAI division factor for SAI1 clock
bit_offset: 8
bit_size: 5
enum: PLLSAIDIVQ
- name: PLLSAIDIVR
description: division factor for LCD_CLK
bit_offset: 16
bit_size: 2
enum: PLLSAIDIVR
- name: SAI1SEL
description: SAI1 clock source selection
bit_offset: 20
bit_size: 2
enum: SAISEL
- name: SAI2SEL
description: SAI2 clock source selection
bit_offset: 22
bit_size: 2
enum: SAISEL
- name: TIMPRE
description: Timers clocks prescalers selection
bit_offset: 24
bit_size: 1
enum: TIMPRE
- name: DFSDM1SEL
description: DFSDM1 clock source selection
bit_offset: 25
bit_size: 1
enum: DFSDMSEL
- name: ADFSDM1SEL
description: DFSDM1 AUDIO clock source selection
bit_offset: 26
bit_size: 1
enum: ADFSDMSEL
fieldset/DCKCFGR2:
description: dedicated clocks configuration register
fields:
- name: USART1SEL
description: USART 1 clock source selection
bit_offset: 0
bit_size: 2
enum: USART1SEL
- name: USART2SEL
description: USART 2 clock source selection
bit_offset: 2
bit_size: 2
enum: USART2SEL
- name: USART3SEL
description: USART 3 clock source selection
bit_offset: 4
bit_size: 2
enum: USART2SEL
- name: UART4SEL
description: UART 4 clock source selection
bit_offset: 6
bit_size: 2
enum: USART2SEL
- name: UART5SEL
description: UART 5 clock source selection
bit_offset: 8
bit_size: 2
enum: USART2SEL
- name: USART6SEL
description: USART 6 clock source selection
bit_offset: 10
bit_size: 2
enum: USART1SEL
- name: UART7SEL
description: UART 7 clock source selection
bit_offset: 12
bit_size: 2
enum: USART2SEL
- name: UART8SEL
description: UART 8 clock source selection
bit_offset: 14
bit_size: 2
enum: USART2SEL
- name: I2C1SEL
description: I2C1 clock source selection
bit_offset: 16
bit_size: 2
enum: ICSEL
- name: I2C2SEL
description: I2C2 clock source selection
bit_offset: 18
bit_size: 2
enum: ICSEL
- name: I2C3SEL
description: I2C3 clock source selection
bit_offset: 20
bit_size: 2
enum: ICSEL
- name: I2C4SEL
description: I2C4 clock source selection
bit_offset: 22
bit_size: 2
enum: ICSEL
- name: LPTIM1SEL
description: Low power timer 1 clock source selection
bit_offset: 24
bit_size: 2
enum: LPTIMSEL
- name: CECSEL
description: HDMI-CEC clock source selection
bit_offset: 26
bit_size: 1
enum: CECSEL
- name: CLK48SEL
description: 48MHz clock source selection
bit_offset: 27
bit_size: 1
enum: CKMSEL
- name: SDMMC1SEL
description: SDMMC1 clock source selection
bit_offset: 28
bit_size: 1
enum: SDMMCSEL
- name: SDMMC2SEL
description: SDMMC2 clock source selection
bit_offset: 29
bit_size: 1
enum: SDMMCSEL
- name: DSISEL
description: DSI clock source selection
bit_offset: 30
bit_size: 1
enum: DSISEL
fieldset/PLLCFGR:
description: PLL configuration register
fields:
- name: PLLM
description: Division factor for the PLL and audio PLL (PLLI2S) input clock
bit_offset: 0
bit_size: 6
enum: PLLM
- name: PLLN
description: PLL multiplication factor for VCO
bit_offset: 6
bit_size: 9
enum: PLLN
- name: PLLP
description: PLL division factor for main system clock
bit_offset: 16
bit_size: 2
enum: PLLP
- name: PLLSRC
description: PLL and audio PLL (PLLI2S, PLLSAI) entry clock source
bit_offset: 22
bit_size: 1
enum: PLLSRC
- name: PLLQ
description: PLL division factor for USB OTG FS, SDIO and random number generator clocks
bit_offset: 24
bit_size: 4
enum: PLLQ
- name: PLLR
description: PLL division factor for DSI clock
bit_offset: 28
bit_size: 3
enum: PLLR
fieldset/PLLI2SCFGR:
description: PLLI2S configuration register
fields:
- name: PLLN
description: PLL multiplication factor for VCO
bit_offset: 6
bit_size: 9
enum: PLLN
- name: PLLP
description: PLL division factor for main system clock
bit_offset: 16
bit_size: 2
enum: PLLP
- name: PLLQ
description: PLL division factor for USB OTG FS, SDIO and random number generator clocks
bit_offset: 24
bit_size: 4
enum: PLLQ
- name: PLLR
description: PLL division factor for DSI clock
bit_offset: 28
bit_size: 3
enum: PLLR
fieldset/PLLSAICFGR:
description: PLL configuration register
fields:
- name: PLLN
description: PLL multiplication factor for VCO
bit_offset: 6
bit_size: 9
enum: PLLN
- name: PLLP
description: PLL division factor for main system clock
bit_offset: 16
bit_size: 2
enum: PLLP
- name: PLLQ
description: PLL division factor for USB OTG FS, SDIO and random number generator clocks
bit_offset: 24
bit_size: 4
enum: PLLQ
- name: PLLR
description: PLL division factor for DSI clock
bit_offset: 28
bit_size: 3
enum: PLLR
fieldset/SSCGR:
description: spread spectrum clock generation register
fields:
- name: MODPER
description: Modulation period
bit_offset: 0
bit_size: 13
- name: INCSTEP
description: Incrementation step
bit_offset: 13
bit_size: 15
- name: SPREADSEL
description: Spread Select
bit_offset: 30
bit_size: 1
enum: SPREADSEL
- name: SSCGEN
description: Spread spectrum modulation enable
bit_offset: 31
bit_size: 1
enum/ADFSDMSEL:
bit_size: 1
variants:
- name: SAI1
description: SAI1 clock selected as DFSDM1 Audio clock source
value: 0
- name: SAI2
description: SAI2 clock selected as DFSDM1 Audio clock source
value: 1
enum/CECSEL:
bit_size: 1
variants:
- name: LSE
description: LSE clock is selected as HDMI-CEC clock
value: 0
- name: HSI_Div488
description: HSI divided by 488 clock is selected as HDMI-CEC clock
value: 1
enum/CKMSEL:
bit_size: 1
variants:
- name: PLL
description: 48MHz clock from PLL is selected
value: 0
- name: PLLSAI
description: 48MHz clock from PLLSAI is selected
value: 1
enum/DFSDMSEL:
bit_size: 1
variants:
- name: PCLK2
description: APB2 clock (PCLK2) selected as DFSDM1 Kernel clock source
value: 0
- name: SYS
description: System clock (SYSCLK) clock selected as DFSDM1 Kernel clock source
value: 1
enum/DSISEL:
bit_size: 1
variants:
- name: DSI_PHY
description: DSI-PHY used as DSI byte lane clock source (usual case)
value: 0
- name: PLLR
description: PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)
value: 1
enum/HPRE:
bit_size: 4
variants:
- name: Div1
description: SYSCLK not divided
value: 0
- name: Div2
description: SYSCLK divided by 2
value: 8
- name: Div4
description: SYSCLK divided by 4
value: 9
- name: Div8
description: SYSCLK divided by 8
value: 10
- name: Div16
description: SYSCLK divided by 16
value: 11
- name: Div64
description: SYSCLK divided by 64
value: 12
- name: Div128
description: SYSCLK divided by 128
value: 13
- name: Div256
description: SYSCLK divided by 256
value: 14
- name: Div512
description: SYSCLK divided by 512
value: 15
enum/ICSEL:
bit_size: 2
variants:
- name: APB
description: APB clock selected as I2C clock
value: 0
- name: SYS
description: System clock selected as I2C clock
value: 1
- name: HSI
description: HSI clock selected as I2C clock
value: 2
enum/ISSRC:
bit_size: 1
variants:
- name: PLLI2S
description: PLLI2S clock used as I2S clock source
value: 0
- name: CKIN
description: External clock mapped on the I2S_CKIN pin used as I2S clock source
value: 1
enum/LPTIMSEL:
bit_size: 2
variants:
- name: PCLK1
description: APB1 clock (PCLK1) selected as LPTILM1 clock
value: 0
- name: LSI
description: LSI clock is selected as LPTILM1 clock
value: 1
- name: HSI
description: HSI clock is selected as LPTILM1 clock
value: 2
- name: LSE
description: LSE clock is selected as LPTILM1 clock
value: 3
enum/LSEDRV:
bit_size: 2
variants:
- name: Low
description: Low driving capability
value: 0
- name: MediumHigh
description: Medium high driving capability
value: 1
- name: MediumLow
description: Medium low driving capability
value: 2
- name: High
description: High driving capability
value: 3
enum/MCO1SEL:
bit_size: 2
variants:
- name: HSI
description: HSI clock selected
value: 0
- name: LSE
description: LSE oscillator selected
value: 1
- name: HSE
description: HSE oscillator clock selected
value: 2
- name: PLL
description: PLL clock selected
value: 3
enum/MCO2SEL:
bit_size: 2
variants:
- name: SYS
description: System clock (SYSCLK) selected
value: 0
- name: PLLI2S
description: PLLI2S clock selected
value: 1
- name: HSE
description: HSE oscillator clock selected
value: 2
- name: PLL
description: PLL clock selected
value: 3
enum/MCOPRE:
bit_size: 3
variants:
- name: Div1
description: No division
value: 0
- name: Div2
description: Division by 2
value: 4
- name: Div3
description: Division by 3
value: 5
- name: Div4
description: Division by 4
value: 6
- name: Div5
description: Division by 5
value: 7
enum/PLLI2SDIVQ:
bit_size: 5
variants:
- name: Div1
description: PLLI2SDIVQ = /1
value: 0
- name: Div2
description: PLLI2SDIVQ = /2
value: 1
- name: Div3
description: PLLI2SDIVQ = /3
value: 2
- name: Div4
description: PLLI2SDIVQ = /4
value: 3
- name: Div5
description: PLLI2SDIVQ = /5
value: 4
- name: Div6
description: PLLI2SDIVQ = /6
value: 5
- name: Div7
description: PLLI2SDIVQ = /7
value: 6
- name: Div8
description: PLLI2SDIVQ = /8
value: 7
- name: Div9
description: PLLI2SDIVQ = /9
value: 8
- name: Div10
description: PLLI2SDIVQ = /10
value: 9
- name: Div11
description: PLLI2SDIVQ = /11
value: 10
- name: Div12
description: PLLI2SDIVQ = /12
value: 11
- name: Div13
description: PLLI2SDIVQ = /13
value: 12
- name: Div14
description: PLLI2SDIVQ = /14
value: 13
- name: Div15
description: PLLI2SDIVQ = /15
value: 14
- name: Div16
description: PLLI2SDIVQ = /16
value: 15
- name: Div17
description: PLLI2SDIVQ = /17
value: 16
- name: Div18
description: PLLI2SDIVQ = /18
value: 17
- name: Div19
description: PLLI2SDIVQ = /19
value: 18
- name: Div20
description: PLLI2SDIVQ = /20
value: 19
- name: Div21
description: PLLI2SDIVQ = /21
value: 20
- name: Div22
description: PLLI2SDIVQ = /22
value: 21
- name: Div23
description: PLLI2SDIVQ = /23
value: 22
- name: Div24
description: PLLI2SDIVQ = /24
value: 23
- name: Div25
description: PLLI2SDIVQ = /25
value: 24
- name: Div26
description: PLLI2SDIVQ = /26
value: 25
- name: Div27
description: PLLI2SDIVQ = /27
value: 26
- name: Div28
description: PLLI2SDIVQ = /28
value: 27
- name: Div29
description: PLLI2SDIVQ = /29
value: 28
- name: Div30
description: PLLI2SDIVQ = /30
value: 29
- name: Div31
description: PLLI2SDIVQ = /31
value: 30
- name: Div32
description: PLLI2SDIVQ = /32
value: 31
enum/PLLM:
bit_size: 6
variants:
- name: Div2
value: 2
- name: Div3
value: 3
- name: Div4
value: 4
- name: Div5
value: 5
- name: Div6
value: 6
- name: Div7
value: 7
- name: Div8
value: 8
- name: Div9
value: 9
- name: Div10
value: 10
- name: Div11
value: 11
- name: Div12
value: 12
- name: Div13
value: 13
- name: Div14
value: 14
- name: Div15
value: 15
- name: Div16
value: 16
- name: Div17
value: 17
- name: Div18
value: 18
- name: Div19
value: 19
- name: Div20
value: 20
- name: Div21
value: 21
- name: Div22
value: 22
- name: Div23
value: 23
- name: Div24
value: 24
- name: Div25
value: 25
- name: Div26
value: 26
- name: Div27
value: 27
- name: Div28
value: 28
- name: Div29
value: 29
- name: Div30
value: 30
- name: Div31
value: 31
- name: Div32
value: 32
- name: Div33
value: 33
- name: Div34
value: 34
- name: Div35
value: 35
- name: Div36
value: 36
- name: Div37
value: 37
- name: Div38
value: 38
- name: Div39
value: 39
- name: Div40
value: 40
- name: Div41
value: 41
- name: Div42
value: 42
- name: Div43
value: 43
- name: Div44
value: 44
- name: Div45
value: 45
- name: Div46
value: 46
- name: Div47
value: 47
- name: Div48
value: 48
- name: Div49
value: 49
- name: Div50
value: 50
- name: Div51
value: 51
- name: Div52
value: 52
- name: Div53
value: 53
- name: Div54
value: 54
- name: Div55
value: 55
- name: Div56
value: 56
- name: Div57
value: 57
- name: Div58
value: 58
- name: Div59
value: 59
- name: Div60
value: 60
- name: Div61
value: 61
- name: Div62
value: 62
- name: Div63
value: 63
enum/PLLN:
bit_size: 9
variants:
- name: Mul50
value: 50
- name: Mul51
value: 51
- name: Mul52
value: 52
- name: Mul53
value: 53
- name: Mul54
value: 54
- name: Mul55
value: 55
- name: Mul56
value: 56
- name: Mul57
value: 57
- name: Mul58
value: 58
- name: Mul59
value: 59
- name: Mul60
value: 60
- name: Mul61
value: 61
- name: Mul62
value: 62
- name: Mul63
value: 63
- name: Mul64
value: 64
- name: Mul65
value: 65
- name: Mul66
value: 66
- name: Mul67
value: 67
- name: Mul68
value: 68
- name: Mul69
value: 69
- name: Mul70
value: 70
- name: Mul71
value: 71
- name: Mul72
value: 72
- name: Mul73
value: 73
- name: Mul74
value: 74
- name: Mul75
value: 75
- name: Mul76
value: 76
- name: Mul77
value: 77
- name: Mul78
value: 78
- name: Mul79
value: 79
- name: Mul80
value: 80
- name: Mul81
value: 81
- name: Mul82
value: 82
- name: Mul83
value: 83
- name: Mul84
value: 84
- name: Mul85
value: 85
- name: Mul86
value: 86
- name: Mul87
value: 87
- name: Mul88
value: 88
- name: Mul89
value: 89
- name: Mul90
value: 90
- name: Mul91
value: 91
- name: Mul92
value: 92
- name: Mul93
value: 93
- name: Mul94
value: 94
- name: Mul95
value: 95
- name: Mul96
value: 96
- name: Mul97
value: 97
- name: Mul98
value: 98
- name: Mul99
value: 99
- name: Mul100
value: 100
- name: Mul101
value: 101
- name: Mul102
value: 102
- name: Mul103
value: 103
- name: Mul104
value: 104
- name: Mul105
value: 105
- name: Mul106
value: 106
- name: Mul107
value: 107
- name: Mul108
value: 108
- name: Mul109
value: 109
- name: Mul110
value: 110
- name: Mul111
value: 111
- name: Mul112
value: 112
- name: Mul113
value: 113
- name: Mul114
value: 114
- name: Mul115
value: 115
- name: Mul116
value: 116
- name: Mul117
value: 117
- name: Mul118
value: 118
- name: Mul119
value: 119
- name: Mul120
value: 120
- name: Mul121
value: 121
- name: Mul122
value: 122
- name: Mul123
value: 123
- name: Mul124
value: 124
- name: Mul125
value: 125
- name: Mul126
value: 126
- name: Mul127
value: 127
- name: Mul128
value: 128
- name: Mul129
value: 129
- name: Mul130
value: 130
- name: Mul131
value: 131
- name: Mul132
value: 132
- name: Mul133
value: 133
- name: Mul134
value: 134
- name: Mul135
value: 135
- name: Mul136
value: 136
- name: Mul137
value: 137
- name: Mul138
value: 138
- name: Mul139
value: 139
- name: Mul140
value: 140
- name: Mul141
value: 141
- name: Mul142
value: 142
- name: Mul143
value: 143
- name: Mul144
value: 144
- name: Mul145
value: 145
- name: Mul146
value: 146
- name: Mul147
value: 147
- name: Mul148
value: 148
- name: Mul149
value: 149
- name: Mul150
value: 150
- name: Mul151
value: 151
- name: Mul152
value: 152
- name: Mul153
value: 153
- name: Mul154
value: 154
- name: Mul155
value: 155
- name: Mul156
value: 156
- name: Mul157
value: 157
- name: Mul158
value: 158
- name: Mul159
value: 159
- name: Mul160
value: 160
- name: Mul161
value: 161
- name: Mul162
value: 162
- name: Mul163
value: 163
- name: Mul164
value: 164
- name: Mul165
value: 165
- name: Mul166
value: 166
- name: Mul167
value: 167
- name: Mul168
value: 168
- name: Mul169
value: 169
- name: Mul170
value: 170
- name: Mul171
value: 171
- name: Mul172
value: 172
- name: Mul173
value: 173
- name: Mul174
value: 174
- name: Mul175
value: 175
- name: Mul176
value: 176
- name: Mul177
value: 177
- name: Mul178
value: 178
- name: Mul179
value: 179
- name: Mul180
value: 180
- name: Mul181
value: 181
- name: Mul182
value: 182
- name: Mul183
value: 183
- name: Mul184
value: 184
- name: Mul185
value: 185
- name: Mul186
value: 186
- name: Mul187
value: 187
- name: Mul188
value: 188
- name: Mul189
value: 189
- name: Mul190
value: 190
- name: Mul191
value: 191
- name: Mul192
value: 192
- name: Mul193
value: 193
- name: Mul194
value: 194
- name: Mul195
value: 195
- name: Mul196
value: 196
- name: Mul197
value: 197
- name: Mul198
value: 198
- name: Mul199
value: 199
- name: Mul200
value: 200
- name: Mul201
value: 201
- name: Mul202
value: 202
- name: Mul203
value: 203
- name: Mul204
value: 204
- name: Mul205
value: 205
- name: Mul206
value: 206
- name: Mul207
value: 207
- name: Mul208
value: 208
- name: Mul209
value: 209
- name: Mul210
value: 210
- name: Mul211
value: 211
- name: Mul212
value: 212
- name: Mul213
value: 213
- name: Mul214
value: 214
- name: Mul215
value: 215
- name: Mul216
value: 216
- name: Mul217
value: 217
- name: Mul218
value: 218
- name: Mul219
value: 219
- name: Mul220
value: 220
- name: Mul221
value: 221
- name: Mul222
value: 222
- name: Mul223
value: 223
- name: Mul224
value: 224
- name: Mul225
value: 225
- name: Mul226
value: 226
- name: Mul227
value: 227
- name: Mul228
value: 228
- name: Mul229
value: 229
- name: Mul230
value: 230
- name: Mul231
value: 231
- name: Mul232
value: 232
- name: Mul233
value: 233
- name: Mul234
value: 234
- name: Mul235
value: 235
- name: Mul236
value: 236
- name: Mul237
value: 237
- name: Mul238
value: 238
- name: Mul239
value: 239
- name: Mul240
value: 240
- name: Mul241
value: 241
- name: Mul242
value: 242
- name: Mul243
value: 243
- name: Mul244
value: 244
- name: Mul245
value: 245
- name: Mul246
value: 246
- name: Mul247
value: 247
- name: Mul248
value: 248
- name: Mul249
value: 249
- name: Mul250
value: 250
- name: Mul251
value: 251
- name: Mul252
value: 252
- name: Mul253
value: 253
- name: Mul254
value: 254
- name: Mul255
value: 255
- name: Mul256
value: 256
- name: Mul257
value: 257
- name: Mul258
value: 258
- name: Mul259
value: 259
- name: Mul260
value: 260
- name: Mul261
value: 261
- name: Mul262
value: 262
- name: Mul263
value: 263
- name: Mul264
value: 264
- name: Mul265
value: 265
- name: Mul266
value: 266
- name: Mul267
value: 267
- name: Mul268
value: 268
- name: Mul269
value: 269
- name: Mul270
value: 270
- name: Mul271
value: 271
- name: Mul272
value: 272
- name: Mul273
value: 273
- name: Mul274
value: 274
- name: Mul275
value: 275
- name: Mul276
value: 276
- name: Mul277
value: 277
- name: Mul278
value: 278
- name: Mul279
value: 279
- name: Mul280
value: 280
- name: Mul281
value: 281
- name: Mul282
value: 282
- name: Mul283
value: 283
- name: Mul284
value: 284
- name: Mul285
value: 285
- name: Mul286
value: 286
- name: Mul287
value: 287
- name: Mul288
value: 288
- name: Mul289
value: 289
- name: Mul290
value: 290
- name: Mul291
value: 291
- name: Mul292
value: 292
- name: Mul293
value: 293
- name: Mul294
value: 294
- name: Mul295
value: 295
- name: Mul296
value: 296
- name: Mul297
value: 297
- name: Mul298
value: 298
- name: Mul299
value: 299
- name: Mul300
value: 300
- name: Mul301
value: 301
- name: Mul302
value: 302
- name: Mul303
value: 303
- name: Mul304
value: 304
- name: Mul305
value: 305
- name: Mul306
value: 306
- name: Mul307
value: 307
- name: Mul308
value: 308
- name: Mul309
value: 309
- name: Mul310
value: 310
- name: Mul311
value: 311
- name: Mul312
value: 312
- name: Mul313
value: 313
- name: Mul314
value: 314
- name: Mul315
value: 315
- name: Mul316
value: 316
- name: Mul317
value: 317
- name: Mul318
value: 318
- name: Mul319
value: 319
- name: Mul320
value: 320
- name: Mul321
value: 321
- name: Mul322
value: 322
- name: Mul323
value: 323
- name: Mul324
value: 324
- name: Mul325
value: 325
- name: Mul326
value: 326
- name: Mul327
value: 327
- name: Mul328
value: 328
- name: Mul329
value: 329
- name: Mul330
value: 330
- name: Mul331
value: 331
- name: Mul332
value: 332
- name: Mul333
value: 333
- name: Mul334
value: 334
- name: Mul335
value: 335
- name: Mul336
value: 336
- name: Mul337
value: 337
- name: Mul338
value: 338
- name: Mul339
value: 339
- name: Mul340
value: 340
- name: Mul341
value: 341
- name: Mul342
value: 342
- name: Mul343
value: 343
- name: Mul344
value: 344
- name: Mul345
value: 345
- name: Mul346
value: 346
- name: Mul347
value: 347
- name: Mul348
value: 348
- name: Mul349
value: 349
- name: Mul350
value: 350
- name: Mul351
value: 351
- name: Mul352
value: 352
- name: Mul353
value: 353
- name: Mul354
value: 354
- name: Mul355
value: 355
- name: Mul356
value: 356
- name: Mul357
value: 357
- name: Mul358
value: 358
- name: Mul359
value: 359
- name: Mul360
value: 360
- name: Mul361
value: 361
- name: Mul362
value: 362
- name: Mul363
value: 363
- name: Mul364
value: 364
- name: Mul365
value: 365
- name: Mul366
value: 366
- name: Mul367
value: 367
- name: Mul368
value: 368
- name: Mul369
value: 369
- name: Mul370
value: 370
- name: Mul371
value: 371
- name: Mul372
value: 372
- name: Mul373
value: 373
- name: Mul374
value: 374
- name: Mul375
value: 375
- name: Mul376
value: 376
- name: Mul377
value: 377
- name: Mul378
value: 378
- name: Mul379
value: 379
- name: Mul380
value: 380
- name: Mul381
value: 381
- name: Mul382
value: 382
- name: Mul383
value: 383
- name: Mul384
value: 384
- name: Mul385
value: 385
- name: Mul386
value: 386
- name: Mul387
value: 387
- name: Mul388
value: 388
- name: Mul389
value: 389
- name: Mul390
value: 390
- name: Mul391
value: 391
- name: Mul392
value: 392
- name: Mul393
value: 393
- name: Mul394
value: 394
- name: Mul395
value: 395
- name: Mul396
value: 396
- name: Mul397
value: 397
- name: Mul398
value: 398
- name: Mul399
value: 399
- name: Mul400
value: 400
- name: Mul401
value: 401
- name: Mul402
value: 402
- name: Mul403
value: 403
- name: Mul404
value: 404
- name: Mul405
value: 405
- name: Mul406
value: 406
- name: Mul407
value: 407
- name: Mul408
value: 408
- name: Mul409
value: 409
- name: Mul410
value: 410
- name: Mul411
value: 411
- name: Mul412
value: 412
- name: Mul413
value: 413
- name: Mul414
value: 414
- name: Mul415
value: 415
- name: Mul416
value: 416
- name: Mul417
value: 417
- name: Mul418
value: 418
- name: Mul419
value: 419
- name: Mul420
value: 420
- name: Mul421
value: 421
- name: Mul422
value: 422
- name: Mul423
value: 423
- name: Mul424
value: 424
- name: Mul425
value: 425
- name: Mul426
value: 426
- name: Mul427
value: 427
- name: Mul428
value: 428
- name: Mul429
value: 429
- name: Mul430
value: 430
- name: Mul431
value: 431
- name: Mul432
value: 432
enum/PLLP:
bit_size: 2
variants:
- name: Div2
description: PLLP=2
value: 0
- name: Div4
description: PLLP=4
value: 1
- name: Div6
description: PLLP=6
value: 2
- name: Div8
description: PLLP=8
value: 3
enum/PLLQ:
bit_size: 4
variants:
- name: Div2
value: 2
- name: Div3
value: 3
- name: Div4
value: 4
- name: Div5
value: 5
- name: Div6
value: 6
- name: Div7
value: 7
- name: Div8
value: 8
- name: Div9
value: 9
- name: Div10
value: 10
- name: Div11
value: 11
- name: Div12
value: 12
- name: Div13
value: 13
- name: Div14
value: 14
- name: Div15
value: 15
enum/PLLR:
bit_size: 3
variants:
- name: Div2
value: 2
- name: Div3
value: 3
- name: Div4
value: 4
- name: Div5
value: 5
- name: Div6
value: 6
- name: Div7
value: 7
enum/PLLSAIDIVQ:
bit_size: 5
variants:
- name: Div1
description: PLLSAIDIVQ = /1
value: 0
- name: Div2
description: PLLSAIDIVQ = /2
value: 1
- name: Div3
description: PLLSAIDIVQ = /3
value: 2
- name: Div4
description: PLLSAIDIVQ = /4
value: 3
- name: Div5
description: PLLSAIDIVQ = /5
value: 4
- name: Div6
description: PLLSAIDIVQ = /6
value: 5
- name: Div7
description: PLLSAIDIVQ = /7
value: 6
- name: Div8
description: PLLSAIDIVQ = /8
value: 7
- name: Div9
description: PLLSAIDIVQ = /9
value: 8
- name: Div10
description: PLLSAIDIVQ = /10
value: 9
- name: Div11
description: PLLSAIDIVQ = /11
value: 10
- name: Div12
description: PLLSAIDIVQ = /12
value: 11
- name: Div13
description: PLLSAIDIVQ = /13
value: 12
- name: Div14
description: PLLSAIDIVQ = /14
value: 13
- name: Div15
description: PLLSAIDIVQ = /15
value: 14
- name: Div16
description: PLLSAIDIVQ = /16
value: 15
- name: Div17
description: PLLSAIDIVQ = /17
value: 16
- name: Div18
description: PLLSAIDIVQ = /18
value: 17
- name: Div19
description: PLLSAIDIVQ = /19
value: 18
- name: Div20
description: PLLSAIDIVQ = /20
value: 19
- name: Div21
description: PLLSAIDIVQ = /21
value: 20
- name: Div22
description: PLLSAIDIVQ = /22
value: 21
- name: Div23
description: PLLSAIDIVQ = /23
value: 22
- name: Div24
description: PLLSAIDIVQ = /24
value: 23
- name: Div25
description: PLLSAIDIVQ = /25
value: 24
- name: Div26
description: PLLSAIDIVQ = /26
value: 25
- name: Div27
description: PLLSAIDIVQ = /27
value: 26
- name: Div28
description: PLLSAIDIVQ = /28
value: 27
- name: Div29
description: PLLSAIDIVQ = /29
value: 28
- name: Div30
description: PLLSAIDIVQ = /30
value: 29
- name: Div31
description: PLLSAIDIVQ = /31
value: 30
- name: Div32
description: PLLSAIDIVQ = /32
value: 31
enum/PLLSAIDIVR:
bit_size: 2
variants:
- name: Div2
description: PLLSAIDIVR = /2
value: 0
- name: Div4
description: PLLSAIDIVR = /4
value: 1
- name: Div8
description: PLLSAIDIVR = /8
value: 2
- name: Div16
description: PLLSAIDIVR = /16
value: 3
enum/PLLSRC:
bit_size: 1
variants:
- name: HSI
description: HSI clock selected as PLL and PLLI2S clock entry
value: 0
- name: HSE
description: HSE oscillator clock selected as PLL and PLLI2S clock entry
value: 1
enum/PPRE:
bit_size: 3
variants:
- name: Div1
description: HCLK not divided
value: 0
- name: Div2
description: HCLK divided by 2
value: 4
- name: Div4
description: HCLK divided by 4
value: 5
- name: Div8
description: HCLK divided by 8
value: 6
- name: Div16
description: HCLK divided by 16
value: 7
enum/RTCSEL:
bit_size: 2
variants:
- name: DISABLE
description: No clock
value: 0
- name: LSE
description: LSE oscillator clock used as RTC clock
value: 1
- name: LSI
description: LSI oscillator clock used as RTC clock
value: 2
- name: HSE
description: HSE oscillator clock divided by a prescaler used as RTC clock
value: 3
enum/SAISEL:
bit_size: 2
variants:
- name: PLLSAI
description: SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ
value: 0
- name: PLLI2S
description: SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ
value: 1
- name: AFIF
description: SAI2 clock frequency = Alternate function input frequency
value: 2
- name: HSI_HSE
description: SAI2 clock frequency = HSI or HSE
value: 3
enum/SDMMCSEL:
bit_size: 1
variants:
- name: CLK48
description: 48 MHz clock is selected as SD clock
value: 0
- name: SYS
description: System clock is selected as SD clock
value: 1
enum/SPREADSEL:
bit_size: 1
variants:
- name: Center
description: Center spread
value: 0
- name: Down
description: Down spread
value: 1
enum/SW:
bit_size: 2
variants:
- name: HSI
description: HSI oscillator used as system clock
value: 0
- name: HSE
description: HSE oscillator used as system clock
value: 1
- name: PLL1_P
description: PLL used as system clock
value: 2
enum/TIMPRE:
bit_size: 1
variants:
- name: Mul2
description: If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx
value: 0
- name: Mul4
description: If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx
value: 1
enum/USART1SEL:
bit_size: 2
variants:
- name: PCLK2
description: APB2 clock (PCLK2) is selected as USART clock
value: 0
- name: SYS
description: System clock is selected as USART clock
value: 1
- name: HSI
description: HSI clock is selected as USART clock
value: 2
- name: LSE
description: LSE clock is selected as USART clock
value: 3
enum/USART2SEL:
bit_size: 2
variants:
- name: PCLK1
description: APB1 clock (PCLK1) is selected as USART clock
value: 0
- name: SYS
description: System clock is selected as USART clock
value: 1
- name: HSI
description: HSI clock is selected as USART clock
value: 2
- name: LSE
description: LSE clock is selected as USART clock
value: 3
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