Merge branch 'master' into lptim-basic
This commit is contained in:
xoviat
commit
1b39301d8c
33
.github/ci/build.sh
vendored
33
.github/ci/build.sh
vendored
@ -2,7 +2,7 @@
|
||||
## on push branch~=gh-readonly-queue/main/.*
|
||||
## on pull_request
|
||||
|
||||
set -euo pipefail
|
||||
set -euxo pipefail
|
||||
|
||||
export RUSTUP_HOME=/ci/cache/rustup
|
||||
export CARGO_HOME=/ci/cache/cargo
|
||||
@ -13,4 +13,35 @@ hashtime save /ci/cache/filetime.json
|
||||
|
||||
cargo fmt -- --check
|
||||
|
||||
# clone stm32-data-generated at the merge base
|
||||
# so the diff will show this PR's effect
|
||||
git remote add upstream https://github.com/embassy-rs/stm32-data
|
||||
git fetch --depth 1 upstream main
|
||||
git clone --depth 1 --branch stm32-data-$(git merge-base HEAD upstream/main) https://github.com/embassy-rs/stm32-data-generated/ build
|
||||
|
||||
./d ci
|
||||
|
||||
# upload diff
|
||||
(
|
||||
cd build
|
||||
git add .
|
||||
git diff --staged --color data | aha --black > /ci/artifacts/diff.html
|
||||
)
|
||||
|
||||
# upload generated data to a fake git repo at
|
||||
# https://ci.embassy.dev/jobs/$ID/artifacts/generated.git
|
||||
# this allows testing the corresponding embassy-stm32 PR before merging the stm32-data one.
|
||||
(
|
||||
cd build
|
||||
rm -rf .git
|
||||
git init
|
||||
git add .
|
||||
git commit -m 'generated'
|
||||
git gc # makes cloning faster
|
||||
git update-server-info # generate .git/info/refs
|
||||
mv .git /ci/artifacts/generated.git
|
||||
)
|
||||
|
||||
cat > /ci/comment.md <<EOF
|
||||
diff: https://ci.embassy.dev/jobs/$(jq -r .id < /ci/job.json)/artifacts/diff.html
|
||||
EOF
|
||||
|
||||
2
.github/ci/generated.sh
vendored
2
.github/ci/generated.sh
vendored
@ -12,7 +12,7 @@ export CARGO_TARGET_DIR=/ci/cache/target
|
||||
hashtime restore /ci/cache/filetime.json || true
|
||||
hashtime save /ci/cache/filetime.json
|
||||
|
||||
git clone https://github.com/embassy-rs/stm32-data-generated/ build
|
||||
git clone --depth 1 https://github.com/embassy-rs/stm32-data-generated/ build
|
||||
./d ci
|
||||
|
||||
COMMIT=$(git rev-parse HEAD)
|
||||
|
||||
@ -97,7 +97,7 @@ are only interested in one. It's easier than it looks, and doing all families at
|
||||
- Cleanup the register yamls (see below).
|
||||
- Minimize the diff between each pair of versions. For example between `lpuart_v1.yaml` and `lpuart_v2.yaml`. If one is missing enums or descriptions, copy it from another.
|
||||
- Make sure the block
|
||||
- Add entries to [`perimap`](https://github.com/embassy-rs/stm32-data/blob/main/stm32data/__main__.py#L84), see below.
|
||||
- Add entries to [`perimap`](https://github.com/embassy-rs/stm32-data/blob/main/stm32-data-gen/src/chips.rs#L109), see below.
|
||||
- Regen, check `data/chips/*.yaml` has the right `block: lpuart_vX/LPUART` fields
|
||||
|
||||
Please separate manual changes and changes resulting from regen in separate commits. It helps tremendously with review and rebasing/merging.
|
||||
|
||||
2
d
2
d
@ -11,7 +11,7 @@ case "$CMD" in
|
||||
rm -rf ./sources/
|
||||
git clone https://github.com/embassy-rs/stm32-data-sources.git ./sources/
|
||||
cd ./sources/
|
||||
git checkout ca89656b
|
||||
git checkout a2062c088cf299bd3dc5128eeaa96e07fff2087c
|
||||
;;
|
||||
install-chiptool)
|
||||
cargo install --git https://github.com/embassy-rs/chiptool
|
||||
|
||||
2
d.ps1
2
d.ps1
@ -12,7 +12,7 @@ Switch ($CMD)
|
||||
rm -r -Force ./sources/ -ErrorAction SilentlyContinue
|
||||
git clone https://github.com/embassy-rs/stm32-data-sources.git ./sources/
|
||||
cd ./sources/
|
||||
git checkout ca89656b
|
||||
git checkout a2062c088cf299bd3dc5128eeaa96e07fff2087c
|
||||
cd ..
|
||||
}
|
||||
"install-chiptool" {
|
||||
|
||||
50
data/dmamux/WBA_GPDMA1.yaml
Normal file
50
data/dmamux/WBA_GPDMA1.yaml
Normal file
@ -0,0 +1,50 @@
|
||||
ADC4: 0
|
||||
SPI1_RX: 1
|
||||
SPI1_TX: 2
|
||||
SPI3_RX: 3
|
||||
SPI3_TX: 4
|
||||
I2C1_RX: 5
|
||||
I2C1_TX: 6
|
||||
I2C1_EVC: 7
|
||||
I2C3_RX: 8
|
||||
I2C3_TX: 9
|
||||
I2C3_EVC: 10
|
||||
USART1_RX: 11
|
||||
USART1_TX: 12
|
||||
USART2_RX: 13
|
||||
USART2_TX: 14
|
||||
LPUART1_RX: 15
|
||||
LPUART1_TX: 16
|
||||
TIM1_CC1: 19
|
||||
TIM1_CC2: 20
|
||||
TIM1_CC3: 21
|
||||
TIM1_CC4: 22
|
||||
TIM1_UPD: 23
|
||||
TIM1_TRG: 24
|
||||
TIM1_COM: 25
|
||||
TIM2_CC1: 26
|
||||
TIM2_CC2: 27
|
||||
TIM2_CC3: 28
|
||||
TIM2_CC4: 29
|
||||
TIM2_UPD: 30
|
||||
TIM3_CC1: 31
|
||||
TIM3_CC2: 32
|
||||
TIM3_CC3: 33
|
||||
TIM3_CC4: 34
|
||||
TIM3_UPD: 35
|
||||
TIM3_TRG: 36
|
||||
TIM16_CC1: 37
|
||||
TIM16_UPD: 38
|
||||
TIM17_CC1: 39
|
||||
TIM17_UPD: 40
|
||||
AES_IN: 41
|
||||
AES_OUT: 42
|
||||
HASH_IN: 43
|
||||
SAES_IN: 44
|
||||
SAES_OUT: 45
|
||||
LPTIM1_IC1: 46
|
||||
LPTIM1_IC2: 47
|
||||
LPTIM1_UE: 48
|
||||
LPTIM2_IC1: 49
|
||||
LPTIM2_IC2: 50
|
||||
LPTIM2_UE: 51
|
||||
8
data/extra/family/STM32F3.yaml
Normal file
8
data/extra/family/STM32F3.yaml
Normal file
@ -0,0 +1,8 @@
|
||||
---
|
||||
peripherals:
|
||||
- name: VREFINTCAL
|
||||
address: 0x1FFFF7BA
|
||||
registers:
|
||||
kind: vrefintcal
|
||||
version: v1
|
||||
block: VREFINTCAL
|
||||
@ -1,400 +1,399 @@
|
||||
---
|
||||
block/ADC:
|
||||
description: Analog-to-digital converter
|
||||
items:
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 0
|
||||
fieldset: SR
|
||||
- name: CR1
|
||||
description: control register 1
|
||||
byte_offset: 4
|
||||
fieldset: CR1
|
||||
- name: CR2
|
||||
description: control register 2
|
||||
byte_offset: 8
|
||||
fieldset: CR2
|
||||
- name: SMPR1
|
||||
description: sample time register 1
|
||||
byte_offset: 12
|
||||
fieldset: SMPR1
|
||||
- name: SMPR2
|
||||
description: sample time register 2
|
||||
byte_offset: 16
|
||||
fieldset: SMPR2
|
||||
- name: JOFR
|
||||
description: injected channel data offset register x
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 20
|
||||
fieldset: JOFR
|
||||
- name: HTR
|
||||
description: watchdog higher threshold register
|
||||
byte_offset: 36
|
||||
fieldset: HTR
|
||||
- name: LTR
|
||||
description: watchdog lower threshold register
|
||||
byte_offset: 40
|
||||
fieldset: LTR
|
||||
- name: SQR1
|
||||
description: regular sequence register 1
|
||||
byte_offset: 44
|
||||
fieldset: SQR1
|
||||
- name: SQR2
|
||||
description: regular sequence register 2
|
||||
byte_offset: 48
|
||||
fieldset: SQR2
|
||||
- name: SQR3
|
||||
description: regular sequence register 3
|
||||
byte_offset: 52
|
||||
fieldset: SQR3
|
||||
- name: JSQR
|
||||
description: injected sequence register
|
||||
byte_offset: 56
|
||||
fieldset: JSQR
|
||||
- name: JDR
|
||||
description: injected data register x
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 60
|
||||
access: Read
|
||||
fieldset: JDR
|
||||
- name: DR
|
||||
description: regular data register
|
||||
byte_offset: 76
|
||||
access: Read
|
||||
fieldset: DR
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 0
|
||||
fieldset: SR
|
||||
- name: CR1
|
||||
description: control register 1
|
||||
byte_offset: 4
|
||||
fieldset: CR1
|
||||
- name: CR2
|
||||
description: control register 2
|
||||
byte_offset: 8
|
||||
fieldset: CR2
|
||||
- name: SMPR1
|
||||
description: sample time register 1
|
||||
byte_offset: 12
|
||||
fieldset: SMPR1
|
||||
- name: SMPR2
|
||||
description: sample time register 2
|
||||
byte_offset: 16
|
||||
fieldset: SMPR2
|
||||
- name: JOFR
|
||||
description: injected channel data offset register x
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 20
|
||||
fieldset: JOFR
|
||||
- name: HTR
|
||||
description: watchdog higher threshold register
|
||||
byte_offset: 36
|
||||
fieldset: HTR
|
||||
- name: LTR
|
||||
description: watchdog lower threshold register
|
||||
byte_offset: 40
|
||||
fieldset: LTR
|
||||
- name: SQR1
|
||||
description: regular sequence register 1
|
||||
byte_offset: 44
|
||||
fieldset: SQR1
|
||||
- name: SQR2
|
||||
description: regular sequence register 2
|
||||
byte_offset: 48
|
||||
fieldset: SQR2
|
||||
- name: SQR3
|
||||
description: regular sequence register 3
|
||||
byte_offset: 52
|
||||
fieldset: SQR3
|
||||
- name: JSQR
|
||||
description: injected sequence register
|
||||
byte_offset: 56
|
||||
fieldset: JSQR
|
||||
- name: JDR
|
||||
description: injected data register x
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 60
|
||||
access: Read
|
||||
fieldset: JDR
|
||||
- name: DR
|
||||
description: regular data register
|
||||
byte_offset: 76
|
||||
access: Read
|
||||
fieldset: DR
|
||||
fieldset/CR1:
|
||||
description: control register 1
|
||||
fields:
|
||||
- name: AWDCH
|
||||
description: Analog watchdog channel select bits
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: EOCIE
|
||||
description: Interrupt enable for EOC
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: AWDIE
|
||||
description: Analog watchdog interrupt enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: JEOCIE
|
||||
description: Interrupt enable for injected channels
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: SCAN
|
||||
description: Scan mode
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: AWDSGL
|
||||
description: Enable the watchdog on a single channel in scan mode
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: JAUTO
|
||||
description: Automatic injected group conversion
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DISCEN
|
||||
description: Discontinuous mode on regular channels
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: JDISCEN
|
||||
description: Discontinuous mode on injected channels
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DISCNUM
|
||||
description: Discontinuous mode channel count
|
||||
bit_offset: 13
|
||||
bit_size: 3
|
||||
- name: DUALMOD
|
||||
description: Dual mode selection
|
||||
bit_offset: 16
|
||||
bit_size: 4
|
||||
enum: DUALMOD
|
||||
- name: JAWDEN
|
||||
description: Analog watchdog enable on injected channels
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: AWDEN
|
||||
description: Analog watchdog enable on regular channels
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: AWDCH
|
||||
description: Analog watchdog channel select bits
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: EOCIE
|
||||
description: Interrupt enable for EOC
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: AWDIE
|
||||
description: Analog watchdog interrupt enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: JEOCIE
|
||||
description: Interrupt enable for injected channels
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: SCAN
|
||||
description: Scan mode
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: AWDSGL
|
||||
description: Enable the watchdog on a single channel in scan mode
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: JAUTO
|
||||
description: Automatic injected group conversion
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DISCEN
|
||||
description: Discontinuous mode on regular channels
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: JDISCEN
|
||||
description: Discontinuous mode on injected channels
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DISCNUM
|
||||
description: Discontinuous mode channel count
|
||||
bit_offset: 13
|
||||
bit_size: 3
|
||||
- name: DUALMOD
|
||||
description: Dual mode selection
|
||||
bit_offset: 16
|
||||
bit_size: 4
|
||||
enum: DUALMOD
|
||||
- name: JAWDEN
|
||||
description: Analog watchdog enable on injected channels
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: AWDEN
|
||||
description: Analog watchdog enable on regular channels
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/CR2:
|
||||
description: control register 2
|
||||
fields:
|
||||
- name: ADON
|
||||
description: A/D Converter ON / OFF
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: CONT
|
||||
description: Continuous conversion
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: CAL
|
||||
description: A/D Calibration
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: RSTCAL
|
||||
description: Reset calibration
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DMA
|
||||
description: Direct memory access mode (for single ADC mode)
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ALIGN
|
||||
description: Data alignment
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: JEXTSEL
|
||||
description: External event select for injected group
|
||||
bit_offset: 12
|
||||
bit_size: 3
|
||||
enum: EXTSEL
|
||||
- name: JEXTTRIG
|
||||
description: External trigger conversion mode for injected channels
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: EXTSEL
|
||||
description: External event select for regular group
|
||||
bit_offset: 17
|
||||
bit_size: 3
|
||||
enum: EXTSEL
|
||||
- name: EXTTRIG
|
||||
description: External trigger conversion mode for regular channels
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: JSWSTART
|
||||
description: Start conversion of injected channels
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: SWSTART
|
||||
description: Start conversion of regular channels
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TSVREFE
|
||||
description: Temperature sensor and VREFINT enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: ADON
|
||||
description: A/D Converter ON / OFF
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: CONT
|
||||
description: Continuous conversion
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: CAL
|
||||
description: A/D Calibration
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: RSTCAL
|
||||
description: Reset calibration
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DMA
|
||||
description: Direct memory access mode (for single ADC mode)
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ALIGN
|
||||
description: Data alignment
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: JEXTSEL
|
||||
description: External event select for injected group
|
||||
bit_offset: 12
|
||||
bit_size: 3
|
||||
enum: EXTSEL
|
||||
- name: JEXTTRIG
|
||||
description: External trigger conversion mode for injected channels
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: EXTSEL
|
||||
description: External event select for regular group
|
||||
bit_offset: 17
|
||||
bit_size: 3
|
||||
enum: EXTSEL
|
||||
- name: EXTTRIG
|
||||
description: External trigger conversion mode for regular channels
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: JSWSTART
|
||||
description: Start conversion of injected channels
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: SWSTART
|
||||
description: Start conversion of regular channels
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TSVREFE
|
||||
description: Temperature sensor and VREFINT enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/DR:
|
||||
description: regular data register
|
||||
fields:
|
||||
- name: DATA
|
||||
description: Regular data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: ADC2DATA
|
||||
description: ADC2 data
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: DATA
|
||||
description: Regular data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: ADC2DATA
|
||||
description: ADC2 data
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/HTR:
|
||||
description: watchdog higher threshold register
|
||||
fields:
|
||||
- name: HT
|
||||
description: Analog watchdog higher threshold
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: HT
|
||||
description: Analog watchdog higher threshold
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/JDR:
|
||||
description: injected data register x
|
||||
fields:
|
||||
- name: JDATA
|
||||
description: Injected data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: JDATA
|
||||
description: Injected data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/JOFR:
|
||||
description: injected channel data offset register x
|
||||
fields:
|
||||
- name: JOFFSET
|
||||
description: Data offset for injected channel x
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: JOFFSET
|
||||
description: Data offset for injected channel x
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/JSQR:
|
||||
description: injected sequence register
|
||||
fields:
|
||||
- name: JSQ
|
||||
description: 1st conversion in injected sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 4
|
||||
stride: 5
|
||||
- name: JL
|
||||
description: Injected sequence length
|
||||
bit_offset: 20
|
||||
bit_size: 2
|
||||
- name: JSQ
|
||||
description: 1st conversion in injected sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 4
|
||||
stride: 5
|
||||
- name: JL
|
||||
description: Injected sequence length
|
||||
bit_offset: 20
|
||||
bit_size: 2
|
||||
fieldset/LTR:
|
||||
description: watchdog lower threshold register
|
||||
fields:
|
||||
- name: LT
|
||||
description: Analog watchdog lower threshold
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: LT
|
||||
description: Analog watchdog lower threshold
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/SMPR1:
|
||||
description: sample time register 1
|
||||
fields:
|
||||
- name: SMP
|
||||
description: Channel x sample time selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 8
|
||||
stride: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP
|
||||
description: Channel x sample time selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 8
|
||||
stride: 3
|
||||
enum: SAMPLE_TIME
|
||||
fieldset/SMPR2:
|
||||
description: sample time register 2
|
||||
fields:
|
||||
- name: SMP
|
||||
description: Channel 0 sampling time selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 10
|
||||
stride: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP
|
||||
description: Channel 0 sampling time selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 10
|
||||
stride: 3
|
||||
enum: SAMPLE_TIME
|
||||
fieldset/SQR1:
|
||||
description: regular sequence register 1
|
||||
fields:
|
||||
- name: SQ
|
||||
description: 13th to 16th conversion in regular sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 4
|
||||
stride: 5
|
||||
- name: L
|
||||
description: Regular channel sequence length
|
||||
bit_offset: 20
|
||||
bit_size: 4
|
||||
- name: SQ
|
||||
description: 13th to 16th conversion in regular sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 4
|
||||
stride: 5
|
||||
- name: L
|
||||
description: Regular channel sequence length
|
||||
bit_offset: 20
|
||||
bit_size: 4
|
||||
fieldset/SQR2:
|
||||
description: regular sequence register 2
|
||||
fields:
|
||||
- name: SQ
|
||||
description: 7th to 12th conversion in regular sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 6
|
||||
stride: 5
|
||||
- name: SQ
|
||||
description: 7th to 12th conversion in regular sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 6
|
||||
stride: 5
|
||||
fieldset/SQR3:
|
||||
description: regular sequence register 3
|
||||
fields:
|
||||
- name: SQ
|
||||
description: 1st to 6th conversion in regular sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 6
|
||||
stride: 5
|
||||
- name: SQ
|
||||
description: 1st to 6th conversion in regular sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 6
|
||||
stride: 5
|
||||
fieldset/SR:
|
||||
description: status register
|
||||
fields:
|
||||
- name: AWD
|
||||
description: Analog watchdog flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOC
|
||||
description: Regular channel end of conversion
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: JEOC
|
||||
description: Injected channel end of conversion
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: JSTRT
|
||||
description: Injected channel start flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: STRT
|
||||
description: Regular channel start flag
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: AWD
|
||||
description: Analog watchdog flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOC
|
||||
description: Regular channel end of conversion
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: JEOC
|
||||
description: Injected channel end of conversion
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: JSTRT
|
||||
description: Injected channel start flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: STRT
|
||||
description: Regular channel start flag
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum/DUALMOD:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Independent
|
||||
description: Independent mode.
|
||||
value: 0
|
||||
- name: RegularInjected
|
||||
description: Combined regular simultaneous + injected simultaneous mode
|
||||
value: 1
|
||||
- name: RegularAlternateTrigger
|
||||
description: Combined regular simultaneous + alternate trigger mode
|
||||
value: 2
|
||||
- name: InjectedFastInterleaved
|
||||
description: Combined injected simultaneous + fast interleaved mode
|
||||
value: 3
|
||||
- name: InjectedSlowInterleaved
|
||||
description: Combined injected simultaneous + slow Interleaved mode
|
||||
value: 4
|
||||
- name: Injected
|
||||
description: Injected simultaneous mode only
|
||||
value: 5
|
||||
- name: Regular
|
||||
description: Regular simultaneous mode only
|
||||
value: 6
|
||||
- name: FastInterleaved
|
||||
description: Fast interleaved mode only
|
||||
value: 7
|
||||
- name: SlowInterleaved
|
||||
description: Slow interleaved mode only
|
||||
value: 8
|
||||
- name: AlternateTrigger
|
||||
description: Alternate trigger mode only
|
||||
value: 9
|
||||
- name: Independent
|
||||
description: Independent mode.
|
||||
value: 0
|
||||
- name: RegularInjected
|
||||
description: Combined regular simultaneous + injected simultaneous mode
|
||||
value: 1
|
||||
- name: RegularAlternateTrigger
|
||||
description: Combined regular simultaneous + alternate trigger mode
|
||||
value: 2
|
||||
- name: InjectedFastInterleaved
|
||||
description: Combined injected simultaneous + fast interleaved mode
|
||||
value: 3
|
||||
- name: InjectedSlowInterleaved
|
||||
description: Combined injected simultaneous + slow Interleaved mode
|
||||
value: 4
|
||||
- name: Injected
|
||||
description: Injected simultaneous mode only
|
||||
value: 5
|
||||
- name: Regular
|
||||
description: Regular simultaneous mode only
|
||||
value: 6
|
||||
- name: FastInterleaved
|
||||
description: Fast interleaved mode only
|
||||
value: 7
|
||||
- name: SlowInterleaved
|
||||
description: Slow interleaved mode only
|
||||
value: 8
|
||||
- name: AlternateTrigger
|
||||
description: Alternate trigger mode only
|
||||
value: 9
|
||||
enum/EXTSEL:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: TIM1TRGO
|
||||
description: Timer 1 TRGO event
|
||||
value: 0
|
||||
- name: TIM1CC4
|
||||
description: Timer 1 CC4 event
|
||||
value: 1
|
||||
- name: TIM2TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 2
|
||||
- name: TIM2CC1
|
||||
description: Timer 2 CC1 event
|
||||
value: 3
|
||||
- name: TIM3CC4
|
||||
description: Timer 3 CC4 event
|
||||
value: 4
|
||||
- name: TIM4TRGO
|
||||
description: Timer 4 TRGO event
|
||||
value: 5
|
||||
- name: TIM8CC4
|
||||
description: EXTI line 15/Timer 8 CC4 event
|
||||
value: 6
|
||||
- name: SWSTART
|
||||
description: SWSTART
|
||||
value: 7
|
||||
- name: TIM1TRGO
|
||||
description: Timer 1 TRGO event
|
||||
value: 0
|
||||
- name: TIM1CC4
|
||||
description: Timer 1 CC4 event
|
||||
value: 1
|
||||
- name: TIM2TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 2
|
||||
- name: TIM2CC1
|
||||
description: Timer 2 CC1 event
|
||||
value: 3
|
||||
- name: TIM3CC4
|
||||
description: Timer 3 CC4 event
|
||||
value: 4
|
||||
- name: TIM4TRGO
|
||||
description: Timer 4 TRGO event
|
||||
value: 5
|
||||
- name: TIM8CC4
|
||||
description: EXTI line 15/Timer 8 CC4 event
|
||||
value: 6
|
||||
- name: SWSTART
|
||||
description: SWSTART
|
||||
value: 7
|
||||
enum/SAMPLE_TIME:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Cycles1_5
|
||||
description: 1.5 cycles
|
||||
value: 0
|
||||
- name: Cycles7_5
|
||||
description: 7.5 cycles
|
||||
value: 1
|
||||
- name: Cycles13_5
|
||||
description: 13.5 cycles
|
||||
value: 2
|
||||
- name: Cycles28_5
|
||||
description: 28.5 cycles
|
||||
value: 3
|
||||
- name: Cycles41_5
|
||||
description: 41.5 cycles
|
||||
value: 4
|
||||
- name: Cycles55_5
|
||||
description: 55.5 cycles
|
||||
value: 5
|
||||
- name: Cycles71_5
|
||||
description: 71.5 cycles
|
||||
value: 6
|
||||
- name: Cycles239_5
|
||||
description: 239.5 cycles
|
||||
value: 7
|
||||
- name: Cycles1_5
|
||||
description: 1.5 cycles
|
||||
value: 0
|
||||
- name: Cycles7_5
|
||||
description: 7.5 cycles
|
||||
value: 1
|
||||
- name: Cycles13_5
|
||||
description: 13.5 cycles
|
||||
value: 2
|
||||
- name: Cycles28_5
|
||||
description: 28.5 cycles
|
||||
value: 3
|
||||
- name: Cycles41_5
|
||||
description: 41.5 cycles
|
||||
value: 4
|
||||
- name: Cycles55_5
|
||||
description: 55.5 cycles
|
||||
value: 5
|
||||
- name: Cycles71_5
|
||||
description: 71.5 cycles
|
||||
value: 6
|
||||
- name: Cycles239_5
|
||||
description: 239.5 cycles
|
||||
value: 7
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
610
data/registers/adc_f3_v2.yaml
Normal file
610
data/registers/adc_f3_v2.yaml
Normal file
@ -0,0 +1,610 @@
|
||||
block/ADC:
|
||||
description: Analog-to-Digital Converter
|
||||
items:
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 0
|
||||
fieldset: SR
|
||||
- name: CR1
|
||||
description: control register 1
|
||||
byte_offset: 4
|
||||
fieldset: CR1
|
||||
- name: CR2
|
||||
description: control register 2
|
||||
byte_offset: 8
|
||||
fieldset: CR2
|
||||
- name: SMPR1
|
||||
description: sample time register 1
|
||||
byte_offset: 12
|
||||
fieldset: SMPR1
|
||||
- name: SMPR2
|
||||
description: sample time register 2
|
||||
byte_offset: 16
|
||||
fieldset: SMPR2
|
||||
- name: JOFR1
|
||||
description: injected channel data offset register 1
|
||||
byte_offset: 20
|
||||
fieldset: JOFR1
|
||||
- name: JOFR2
|
||||
description: injected channel data offset register 2
|
||||
byte_offset: 24
|
||||
fieldset: JOFR2
|
||||
- name: JOFR3
|
||||
description: injected channel data offset register 3
|
||||
byte_offset: 28
|
||||
fieldset: JOFR3
|
||||
- name: JOFR4
|
||||
description: injected channel data offset register 4
|
||||
byte_offset: 32
|
||||
fieldset: JOFR4
|
||||
- name: HTR
|
||||
description: watchdog higher threshold register
|
||||
byte_offset: 36
|
||||
fieldset: HTR
|
||||
- name: LTR
|
||||
description: watchdog lower threshold register
|
||||
byte_offset: 40
|
||||
fieldset: LTR
|
||||
- name: SQR1
|
||||
description: regular sequence register 1
|
||||
byte_offset: 44
|
||||
fieldset: SQR1
|
||||
- name: SQR2
|
||||
description: regular sequence register 2
|
||||
byte_offset: 48
|
||||
fieldset: SQR2
|
||||
- name: SQR3
|
||||
description: regular sequence register 3
|
||||
byte_offset: 52
|
||||
fieldset: SQR3
|
||||
- name: JSQR
|
||||
description: injected sequence register
|
||||
byte_offset: 56
|
||||
fieldset: JSQR
|
||||
- name: JDR1
|
||||
description: injected data register 1
|
||||
byte_offset: 60
|
||||
access: Read
|
||||
fieldset: JDR1
|
||||
- name: JDR2
|
||||
description: injected data register 2
|
||||
byte_offset: 64
|
||||
access: Read
|
||||
fieldset: JDR2
|
||||
- name: JDR3
|
||||
description: injected data register 3
|
||||
byte_offset: 68
|
||||
access: Read
|
||||
fieldset: JDR3
|
||||
- name: JDR4
|
||||
description: injected data register 4
|
||||
byte_offset: 72
|
||||
access: Read
|
||||
fieldset: JDR4
|
||||
- name: DR
|
||||
description: regular data register
|
||||
byte_offset: 76
|
||||
access: Read
|
||||
fieldset: DR
|
||||
fieldset/CR1:
|
||||
description: control register 1
|
||||
fields:
|
||||
- name: AWDCH
|
||||
description: analog watchdog channel select bits
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: EOCIE
|
||||
description: interrupt enable for EOC
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: AWDIE
|
||||
description: analog watchdog interrupt enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: JEOCIE
|
||||
description: interrupt enable for injected channels
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: SCAN
|
||||
description: scan mode
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: AWDSGL
|
||||
description: enable the watchdog on a single channel in scan mode
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: JAUTO
|
||||
description: automatic injected group conversion
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DISCEN
|
||||
description: discontinuous mode on regular channels
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: JDISCEN
|
||||
description: discontinuous mode on injected channels
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DISCNUM
|
||||
description: discontinuous mode channel count
|
||||
bit_offset: 13
|
||||
bit_size: 3
|
||||
enum: DISCNUM
|
||||
- name: JAWDEN
|
||||
description: analog watchdog enable on injected channels
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: AWDEN
|
||||
description: analog watchdog enable on regular channels
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/CR2:
|
||||
description: control register 2
|
||||
fields:
|
||||
- name: ADON
|
||||
description: A/D converter ON / OFF
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: CONT
|
||||
description: continuous conversion
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: CAL
|
||||
description: A/D calibration
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: RSTCAL
|
||||
description: reset calibration
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DMA
|
||||
description: DMA disable selection (for single ADC mode)
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ALIGN
|
||||
description: data alignment
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: JEXTSEL
|
||||
description: external event select for injected group
|
||||
bit_offset: 12
|
||||
bit_size: 3
|
||||
enum: JEXTSEL
|
||||
- name: JEXTTRIG
|
||||
description: external trigger conversion mode for injected channels
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: EXTSEL
|
||||
description: external event select for regular group
|
||||
bit_offset: 17
|
||||
bit_size: 3
|
||||
enum: EXTSEL
|
||||
- name: EXTTRIG
|
||||
description: external trigger conversion mode for regular channels
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: JSWSTART
|
||||
description: start conversion of injected channels
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: SWSTART
|
||||
description: start conversion of regular channels
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TSVREFE
|
||||
description: temperature sensor and VREFINT enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/DR:
|
||||
description: regular data register
|
||||
fields:
|
||||
- name: DATA
|
||||
description: Regular data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/HTR:
|
||||
description: watchdog higher threshold register
|
||||
fields:
|
||||
- name: HT
|
||||
description: Analog watchdog high threshold
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/JDR1:
|
||||
description: injected data register 1
|
||||
fields:
|
||||
- name: JDATA1
|
||||
description: Injected data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/JDR2:
|
||||
description: injected data register 2
|
||||
fields:
|
||||
- name: JDATA2
|
||||
description: Injected data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/JDR3:
|
||||
description: injected data register 3
|
||||
fields:
|
||||
- name: JDATA3
|
||||
description: Injected data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/JDR4:
|
||||
description: injected data register 4
|
||||
fields:
|
||||
- name: JDATA4
|
||||
description: Injected data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/JOFR1:
|
||||
description: injected channel data offset register 1
|
||||
fields:
|
||||
- name: JOFFSET1
|
||||
description: data offset for injected channel 1
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/JOFR2:
|
||||
description: injected channel data offset register 2
|
||||
fields:
|
||||
- name: JOFFSET2
|
||||
description: data offset for injected channel 2
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/JOFR3:
|
||||
description: injected channel data offset register 3
|
||||
fields:
|
||||
- name: JOFFSET3
|
||||
description: data offset for injected channel 3
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/JOFR4:
|
||||
description: injected channel data offset register 4
|
||||
fields:
|
||||
- name: JOFFSET4
|
||||
description: data offset for injected channel 4
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/JSQR:
|
||||
description: injected sequence register
|
||||
fields:
|
||||
- name: JSQ1
|
||||
description: 1st conversion in injected sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: JSQ2
|
||||
description: 2nd conversion in injected sequence
|
||||
bit_offset: 5
|
||||
bit_size: 5
|
||||
- name: JSQ3
|
||||
description: 3rd conversion in injected sequence
|
||||
bit_offset: 10
|
||||
bit_size: 5
|
||||
- name: JSQ4
|
||||
description: 4th conversion in injected sequence
|
||||
bit_offset: 15
|
||||
bit_size: 5
|
||||
- name: JL
|
||||
description: injected sequence length
|
||||
bit_offset: 20
|
||||
bit_size: 2
|
||||
fieldset/LTR:
|
||||
description: watchdog lower threshold register
|
||||
fields:
|
||||
- name: LT
|
||||
description: Analog watchdog low threshold
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/SMPR1:
|
||||
description: sample time register 1
|
||||
fields:
|
||||
- name: SMP10
|
||||
description: channel 10 sampling time selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP11
|
||||
description: channel 11 sampling time selection
|
||||
bit_offset: 3
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP12
|
||||
description: channel 12 sampling time selection
|
||||
bit_offset: 6
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP13
|
||||
description: channel 13 sampling time selection
|
||||
bit_offset: 9
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP14
|
||||
description: channel 14 sampling time selection
|
||||
bit_offset: 12
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP15
|
||||
description: channel 15 sampling time selection
|
||||
bit_offset: 15
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP16
|
||||
description: channel 16 sampling time selection
|
||||
bit_offset: 18
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP17
|
||||
description: channel 17 sampling time selection
|
||||
bit_offset: 21
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP18
|
||||
description: channel 18 sampling time selection
|
||||
bit_offset: 24
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
fieldset/SMPR2:
|
||||
description: sample time register 2
|
||||
fields:
|
||||
- name: SMP0
|
||||
description: channel 0 sampling time selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP1
|
||||
description: channel 1 sampling time selection
|
||||
bit_offset: 3
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP2
|
||||
description: channel 2 sampling time selection
|
||||
bit_offset: 6
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP3
|
||||
description: channel 3 sampling time selection
|
||||
bit_offset: 9
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP4
|
||||
description: channel 4 sampling time selection
|
||||
bit_offset: 12
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP5
|
||||
description: channel 5 sampling time selection
|
||||
bit_offset: 15
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP6
|
||||
description: channel 6 sampling time selection
|
||||
bit_offset: 18
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP7
|
||||
description: channel 7 sampling time selection
|
||||
bit_offset: 21
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP8
|
||||
description: channel 8 sampling time selection
|
||||
bit_offset: 24
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP9
|
||||
description: channel 9 sampling time selection
|
||||
bit_offset: 27
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
fieldset/SQR1:
|
||||
description: regular sequence register 1
|
||||
fields:
|
||||
- name: SQ13
|
||||
description: 13th conversion in regular sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: SQ14
|
||||
description: 14th conversion in regular sequence
|
||||
bit_offset: 5
|
||||
bit_size: 5
|
||||
- name: SQ15
|
||||
description: 15th conversion in regular sequence
|
||||
bit_offset: 10
|
||||
bit_size: 5
|
||||
- name: SQ16
|
||||
description: 16th conversion in regular sequence
|
||||
bit_offset: 15
|
||||
bit_size: 5
|
||||
- name: L
|
||||
description: regular channel sequence length
|
||||
bit_offset: 20
|
||||
bit_size: 4
|
||||
fieldset/SQR2:
|
||||
description: regular sequence register 2
|
||||
fields:
|
||||
- name: SQ7
|
||||
description: 7th conversion in regular sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: SQ8
|
||||
description: 8th conversion in regular sequence
|
||||
bit_offset: 5
|
||||
bit_size: 5
|
||||
- name: SQ9
|
||||
description: 9th conversion in regular sequence
|
||||
bit_offset: 10
|
||||
bit_size: 5
|
||||
- name: SQ10
|
||||
description: 10th conversion in regular sequence
|
||||
bit_offset: 15
|
||||
bit_size: 5
|
||||
- name: SQ11
|
||||
description: 11th conversion in regular sequence
|
||||
bit_offset: 20
|
||||
bit_size: 5
|
||||
- name: SQ12
|
||||
description: 12th conversion in regular sequence
|
||||
bit_offset: 25
|
||||
bit_size: 5
|
||||
fieldset/SQR3:
|
||||
description: regular sequence register 3
|
||||
fields:
|
||||
- name: SQ1
|
||||
description: 1st conversion in regular sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: SQ2
|
||||
description: 2nd conversion in regular sequence
|
||||
bit_offset: 5
|
||||
bit_size: 5
|
||||
- name: SQ3
|
||||
description: 3rd conversion in regular sequence
|
||||
bit_offset: 10
|
||||
bit_size: 5
|
||||
- name: SQ4
|
||||
description: 4th conversion in regular sequence
|
||||
bit_offset: 15
|
||||
bit_size: 5
|
||||
- name: SQ5
|
||||
description: 5th conversion in regular sequence
|
||||
bit_offset: 20
|
||||
bit_size: 5
|
||||
- name: SQ6
|
||||
description: 6th conversion in regular sequence
|
||||
bit_offset: 25
|
||||
bit_size: 5
|
||||
fieldset/SR:
|
||||
description: status register
|
||||
fields:
|
||||
- name: AWD
|
||||
description: analog watchdog flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOC
|
||||
description: end of conversion
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: JEOC
|
||||
description: injected channel end of conversion
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: JSTRT
|
||||
description: injected channel start flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: STRT
|
||||
description: regular channel start flag
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: OVR
|
||||
description: overrun
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum/DISCNUM:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: DISCNUM_1
|
||||
description: 1 conversions are discontinued and the conversion is carried out on one channel
|
||||
value: 0
|
||||
- name: DISCNUM_2
|
||||
description: 2 conversion is discontinued and the conversions are carried out on 2 channels
|
||||
value: 1
|
||||
- name: DISCNUM_3
|
||||
description: 3 conversions are discontinued and the conversions are carried out on 3 channels
|
||||
value: 2
|
||||
- name: DISCNUM_4
|
||||
description: 4 conversions are discontinued and the conversions are carried out on 4 channels
|
||||
value: 3
|
||||
- name: DISCNUM_5
|
||||
description: 5 conversions are discontinued and the conversions are carried out on 5 channels
|
||||
value: 4
|
||||
- name: DISCNUM_6
|
||||
description: 6 conversions are discontinued and the conversions are carried out on 6 channels
|
||||
value: 5
|
||||
- name: DISCNUM_7
|
||||
description: 7 conversions are discontinued and the conversions are carried out on 7 channels
|
||||
value: 6
|
||||
- name: DISCNUM_8
|
||||
description: 8 conversions are discontinued and the conversions are carried out on 8 channels
|
||||
value: 7
|
||||
enum/EXTSEL:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: TIM19_TRGO
|
||||
description: Timer 19 TRGO event
|
||||
value: 0
|
||||
- name: TIM19_CC3
|
||||
description: Timer 19 CC3 event
|
||||
value: 1
|
||||
- name: TIM19_CC4
|
||||
description: Timer 19 CC4 event
|
||||
value: 2
|
||||
- name: TIM2_CC2
|
||||
description: Timer 2 CC2 event
|
||||
value: 3
|
||||
- name: TIM3_TRGO
|
||||
description: Timer 3 TRGO event
|
||||
value: 4
|
||||
- name: TIM4_CC4
|
||||
description: Timer 4 CC4 event
|
||||
value: 5
|
||||
- name: EXTI_LINE11
|
||||
description: External interrupt line 11
|
||||
value: 6
|
||||
- name: SWSTART
|
||||
description: SWSTART bit
|
||||
value: 7
|
||||
enum/JEXTSEL:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: TIM19_CC1
|
||||
description: Timer 19 CC1 event
|
||||
value: 0
|
||||
- name: TIM19_CC2
|
||||
description: Timer 19 CC2 event
|
||||
value: 1
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 2
|
||||
- name: TIM2_CC1
|
||||
description: Timer 2 CC1 event
|
||||
value: 3
|
||||
- name: TIM3_CC4
|
||||
description: Timer 3 CC4 event
|
||||
value: 4
|
||||
- name: TIM4_TRGO
|
||||
description: Timer 4 TRGO event
|
||||
value: 5
|
||||
- name: EXTI_LINE15
|
||||
description: External interrupt line 15
|
||||
value: 6
|
||||
- name: JSWSTART
|
||||
description: JSWSTART bit
|
||||
value: 7
|
||||
enum/SAMPLE_TIME:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Cycles1_5
|
||||
description: 1.5 ADC clock cycles
|
||||
value: 0
|
||||
- name: Cycles7_5
|
||||
description: 7.5 ADC clock cycles
|
||||
value: 1
|
||||
- name: Cycles13_5
|
||||
description: 13.5 ADC clock cycles
|
||||
value: 2
|
||||
- name: Cycles28_5
|
||||
description: 28.5 ADC clock cycles
|
||||
value: 3
|
||||
- name: Cycles41_5
|
||||
description: 41.5 ADC clock cycles
|
||||
value: 4
|
||||
- name: Cycles55_5
|
||||
description: 55.5 ADC clock cycles
|
||||
value: 5
|
||||
- name: Cycles71_5
|
||||
description: 71.5 ADC clock cycles
|
||||
value: 6
|
||||
- name: Cycles239_5
|
||||
description: 239.5 ADC clock cycles
|
||||
value: 7
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,384 +1,383 @@
|
||||
---
|
||||
block/ADC:
|
||||
description: Analog-to-digital converter
|
||||
items:
|
||||
- name: ISR
|
||||
description: interrupt and status register
|
||||
byte_offset: 0
|
||||
fieldset: ISR
|
||||
- name: IER
|
||||
description: interrupt enable register
|
||||
byte_offset: 4
|
||||
fieldset: IER
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 8
|
||||
fieldset: CR
|
||||
- name: CFGR1
|
||||
description: configuration register 1
|
||||
byte_offset: 12
|
||||
fieldset: CFGR1
|
||||
- name: CFGR2
|
||||
description: configuration register 2
|
||||
byte_offset: 16
|
||||
fieldset: CFGR2
|
||||
- name: SMPR
|
||||
description: sampling time register
|
||||
byte_offset: 20
|
||||
fieldset: SMPR
|
||||
- name: TR
|
||||
description: watchdog threshold register
|
||||
byte_offset: 32
|
||||
fieldset: TR
|
||||
- name: CHSELR
|
||||
description: channel selection register
|
||||
byte_offset: 40
|
||||
fieldset: CHSELR
|
||||
- name: DR
|
||||
description: data register
|
||||
byte_offset: 64
|
||||
access: Read
|
||||
fieldset: DR
|
||||
- name: CCR
|
||||
description: common configuration register
|
||||
byte_offset: 776
|
||||
fieldset: CCR
|
||||
- name: ISR
|
||||
description: interrupt and status register
|
||||
byte_offset: 0
|
||||
fieldset: ISR
|
||||
- name: IER
|
||||
description: interrupt enable register
|
||||
byte_offset: 4
|
||||
fieldset: IER
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 8
|
||||
fieldset: CR
|
||||
- name: CFGR1
|
||||
description: configuration register 1
|
||||
byte_offset: 12
|
||||
fieldset: CFGR1
|
||||
- name: CFGR2
|
||||
description: configuration register 2
|
||||
byte_offset: 16
|
||||
fieldset: CFGR2
|
||||
- name: SMPR
|
||||
description: sampling time register
|
||||
byte_offset: 20
|
||||
fieldset: SMPR
|
||||
- name: TR
|
||||
description: watchdog threshold register
|
||||
byte_offset: 32
|
||||
fieldset: TR
|
||||
- name: CHSELR
|
||||
description: channel selection register
|
||||
byte_offset: 40
|
||||
fieldset: CHSELR
|
||||
- name: DR
|
||||
description: data register
|
||||
byte_offset: 64
|
||||
access: Read
|
||||
fieldset: DR
|
||||
- name: CCR
|
||||
description: common configuration register
|
||||
byte_offset: 776
|
||||
fieldset: CCR
|
||||
fieldset/CCR:
|
||||
description: common configuration register
|
||||
fields:
|
||||
- name: VREFEN
|
||||
description: Temperature sensor and VREFINT enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TSEN
|
||||
description: Temperature sensor enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: VBATEN
|
||||
description: VBAT enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: VREFEN
|
||||
description: Temperature sensor and VREFINT enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TSEN
|
||||
description: Temperature sensor enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: VBATEN
|
||||
description: VBAT enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/CFGR1:
|
||||
description: configuration register 1
|
||||
fields:
|
||||
- name: DMAEN
|
||||
description: Direct memory access enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DMACFG
|
||||
description: Direct memery access configuration
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
enum: DMACFG
|
||||
- name: SCANDIR
|
||||
description: Scan sequence direction
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum: SCANDIR
|
||||
- name: RES
|
||||
description: Data resolution
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
enum: RES
|
||||
- name: ALIGN
|
||||
description: Data alignment
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: ALIGN
|
||||
- name: EXTSEL
|
||||
description: External trigger selection
|
||||
bit_offset: 6
|
||||
bit_size: 3
|
||||
enum: EXTSEL
|
||||
- name: EXTEN
|
||||
description: External trigger enable and polarity selection
|
||||
bit_offset: 10
|
||||
bit_size: 2
|
||||
enum: EXTEN
|
||||
- name: OVRMOD
|
||||
description: Overrun management mode
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
enum: OVRMOD
|
||||
- name: CONT
|
||||
description: Single / continuous conversion mode
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: WAIT
|
||||
description: Wait conversion mode
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: AUTOFF
|
||||
description: Auto-off mode
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: DISCEN
|
||||
description: Discontinuous mode
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: AWDSGL
|
||||
description: Enable the watchdog on a single channel or on all channels
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
enum: AWDSGL
|
||||
- name: AWDEN
|
||||
description: Analog watchdog enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: AWDCH
|
||||
description: Analog watchdog channel selection
|
||||
bit_offset: 26
|
||||
bit_size: 5
|
||||
- name: DMAEN
|
||||
description: Direct memory access enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DMACFG
|
||||
description: Direct memery access configuration
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
enum: DMACFG
|
||||
- name: SCANDIR
|
||||
description: Scan sequence direction
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum: SCANDIR
|
||||
- name: RES
|
||||
description: Data resolution
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
enum: RES
|
||||
- name: ALIGN
|
||||
description: Data alignment
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: ALIGN
|
||||
- name: EXTSEL
|
||||
description: External trigger selection
|
||||
bit_offset: 6
|
||||
bit_size: 3
|
||||
enum: EXTSEL
|
||||
- name: EXTEN
|
||||
description: External trigger enable and polarity selection
|
||||
bit_offset: 10
|
||||
bit_size: 2
|
||||
enum: EXTEN
|
||||
- name: OVRMOD
|
||||
description: Overrun management mode
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
enum: OVRMOD
|
||||
- name: CONT
|
||||
description: Single / continuous conversion mode
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: WAIT
|
||||
description: Wait conversion mode
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: AUTOFF
|
||||
description: Auto-off mode
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: DISCEN
|
||||
description: Discontinuous mode
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: AWDSGL
|
||||
description: Enable the watchdog on a single channel or on all channels
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
enum: AWDSGL
|
||||
- name: AWDEN
|
||||
description: Analog watchdog enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: AWDCH
|
||||
description: Analog watchdog channel selection
|
||||
bit_offset: 26
|
||||
bit_size: 5
|
||||
fieldset/CFGR2:
|
||||
description: configuration register 2
|
||||
fields:
|
||||
- name: CKMODE
|
||||
description: ADC clock mode
|
||||
bit_offset: 30
|
||||
bit_size: 2
|
||||
enum: CKMODE
|
||||
- name: CKMODE
|
||||
description: ADC clock mode
|
||||
bit_offset: 30
|
||||
bit_size: 2
|
||||
enum: CKMODE
|
||||
fieldset/CHSELR:
|
||||
description: channel selection register
|
||||
fields:
|
||||
- name: CHSEL x
|
||||
description: Channel-x selection
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 19
|
||||
stride: 1
|
||||
- name: CHSEL x
|
||||
description: Channel-x selection
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 19
|
||||
stride: 1
|
||||
fieldset/CR:
|
||||
description: control register
|
||||
fields:
|
||||
- name: ADEN
|
||||
description: ADC enable command
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: ADDIS
|
||||
description: ADC disable command
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ADSTART
|
||||
description: ADC start conversion command
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: ADSTP
|
||||
description: ADC stop conversion command
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: ADCAL
|
||||
description: ADC calibration
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: ADEN
|
||||
description: ADC enable command
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: ADDIS
|
||||
description: ADC disable command
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ADSTART
|
||||
description: ADC start conversion command
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: ADSTP
|
||||
description: ADC stop conversion command
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: ADCAL
|
||||
description: ADC calibration
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/DR:
|
||||
description: data register
|
||||
fields:
|
||||
- name: DATA
|
||||
description: Converted data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: DATA
|
||||
description: Converted data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/IER:
|
||||
description: interrupt enable register
|
||||
fields:
|
||||
- name: ADRDYIE
|
||||
description: ADC ready interrupt enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMPIE
|
||||
description: End of sampling flag interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: EOCIE
|
||||
description: End of conversion interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOSEQIE
|
||||
description: End of conversion sequence interrupt enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: OVRIE
|
||||
description: Overrun interrupt enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: AWDIE
|
||||
description: Analog watchdog interrupt enable
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: ADRDYIE
|
||||
description: ADC ready interrupt enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMPIE
|
||||
description: End of sampling flag interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: EOCIE
|
||||
description: End of conversion interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOSEQIE
|
||||
description: End of conversion sequence interrupt enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: OVRIE
|
||||
description: Overrun interrupt enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: AWDIE
|
||||
description: Analog watchdog interrupt enable
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
fieldset/ISR:
|
||||
description: interrupt and status register
|
||||
fields:
|
||||
- name: ADRDY
|
||||
description: ADC ready
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMP
|
||||
description: End of sampling flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: EOC
|
||||
description: End of conversion flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOSEQ
|
||||
description: End of sequence flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: OVR
|
||||
description: ADC overrun
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: AWD
|
||||
description: Analog watchdog flag
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: ADRDY
|
||||
description: ADC ready
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMP
|
||||
description: End of sampling flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: EOC
|
||||
description: End of conversion flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOSEQ
|
||||
description: End of sequence flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: OVR
|
||||
description: ADC overrun
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: AWD
|
||||
description: Analog watchdog flag
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
fieldset/SMPR:
|
||||
description: sampling time register
|
||||
fields:
|
||||
- name: SMP
|
||||
description: Sampling time selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP
|
||||
description: Sampling time selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
fieldset/TR:
|
||||
description: watchdog threshold register
|
||||
fields:
|
||||
- name: LT
|
||||
description: Analog watchdog lower threshold
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: HT
|
||||
description: Analog watchdog higher threshold
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
- name: LT
|
||||
description: Analog watchdog lower threshold
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: HT
|
||||
description: Analog watchdog higher threshold
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
enum/ALIGN:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Right
|
||||
description: Right alignment
|
||||
value: 0
|
||||
- name: Left
|
||||
description: Left alignment
|
||||
value: 1
|
||||
- name: Right
|
||||
description: Right alignment
|
||||
value: 0
|
||||
- name: Left
|
||||
description: Left alignment
|
||||
value: 1
|
||||
enum/AWDSGL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: AllChannels
|
||||
description: Analog watchdog enabled on all channels
|
||||
value: 0
|
||||
- name: SingleChannel
|
||||
description: Analog watchdog enabled on a single channel
|
||||
value: 1
|
||||
- name: AllChannels
|
||||
description: Analog watchdog enabled on all channels
|
||||
value: 0
|
||||
- name: SingleChannel
|
||||
description: Analog watchdog enabled on a single channel
|
||||
value: 1
|
||||
enum/CKMODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: ADCCLK
|
||||
description: Asynchronous clock mode
|
||||
value: 0
|
||||
- name: PCLK_Div2
|
||||
description: Synchronous clock mode (PCLK/2)
|
||||
value: 1
|
||||
- name: PCLK_Div4
|
||||
description: Sychronous clock mode (PCLK/4)
|
||||
value: 2
|
||||
- name: ADCCLK
|
||||
description: Asynchronous clock mode
|
||||
value: 0
|
||||
- name: PCLK_Div2
|
||||
description: Synchronous clock mode (PCLK/2)
|
||||
value: 1
|
||||
- name: PCLK_Div4
|
||||
description: Sychronous clock mode (PCLK/4)
|
||||
value: 2
|
||||
enum/DMACFG:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: OneShot
|
||||
description: DMA one shot mode
|
||||
value: 0
|
||||
- name: Circular
|
||||
description: DMA circular mode
|
||||
value: 1
|
||||
- name: OneShot
|
||||
description: DMA one shot mode
|
||||
value: 0
|
||||
- name: Circular
|
||||
description: DMA circular mode
|
||||
value: 1
|
||||
enum/EXTEN:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Trigger detection disabled
|
||||
value: 0
|
||||
- name: RisingEdge
|
||||
description: Trigger detection on the rising edge
|
||||
value: 1
|
||||
- name: FallingEdge
|
||||
description: Trigger detection on the falling edge
|
||||
value: 2
|
||||
- name: BothEdges
|
||||
description: Trigger detection on both the rising and falling edges
|
||||
value: 3
|
||||
- name: Disabled
|
||||
description: Trigger detection disabled
|
||||
value: 0
|
||||
- name: RisingEdge
|
||||
description: Trigger detection on the rising edge
|
||||
value: 1
|
||||
- name: FallingEdge
|
||||
description: Trigger detection on the falling edge
|
||||
value: 2
|
||||
- name: BothEdges
|
||||
description: Trigger detection on both the rising and falling edges
|
||||
value: 3
|
||||
enum/EXTSEL:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: TIM1_TRGO
|
||||
description: Timer 1 TRGO Event
|
||||
value: 0
|
||||
- name: TIM1_CC4
|
||||
description: Timer 1 CC4 event
|
||||
value: 1
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 2
|
||||
- name: TIM3_TRGO
|
||||
description: Timer 3 TRGO event
|
||||
value: 3
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 4
|
||||
- name: TIM1_TRGO
|
||||
description: Timer 1 TRGO Event
|
||||
value: 0
|
||||
- name: TIM1_CC4
|
||||
description: Timer 1 CC4 event
|
||||
value: 1
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 2
|
||||
- name: TIM3_TRGO
|
||||
description: Timer 3 TRGO event
|
||||
value: 3
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 4
|
||||
enum/OVRMOD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Preserved
|
||||
description: ADC_DR register is preserved with the old data when an overrun is detected
|
||||
value: 0
|
||||
- name: Overwritten
|
||||
description: ADC_DR register is overwritten with the last conversion result when an overrun is detected
|
||||
value: 1
|
||||
- name: Preserved
|
||||
description: ADC_DR register is preserved with the old data when an overrun is detected
|
||||
value: 0
|
||||
- name: Overwritten
|
||||
description: ADC_DR register is overwritten with the last conversion result when an overrun is detected
|
||||
value: 1
|
||||
enum/RES:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: TwelveBit
|
||||
description: 12-bit (14 ADCCLK cycles)
|
||||
value: 0
|
||||
- name: TenBit
|
||||
description: 10-bit (13 ADCCLK cycles)
|
||||
value: 1
|
||||
- name: EightBit
|
||||
description: 8-bit (11 ADCCLK cycles)
|
||||
value: 2
|
||||
- name: SixBit
|
||||
description: 6-bit (9 ADCCLK cycles)
|
||||
value: 3
|
||||
- name: TwelveBit
|
||||
description: 12-bit (14 ADCCLK cycles)
|
||||
value: 0
|
||||
- name: TenBit
|
||||
description: 10-bit (13 ADCCLK cycles)
|
||||
value: 1
|
||||
- name: EightBit
|
||||
description: 8-bit (11 ADCCLK cycles)
|
||||
value: 2
|
||||
- name: SixBit
|
||||
description: 6-bit (9 ADCCLK cycles)
|
||||
value: 3
|
||||
enum/SAMPLE_TIME:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Cycles1_5
|
||||
description: 1.5 cycles
|
||||
value: 0
|
||||
- name: Cycles7_5
|
||||
description: 7.5 cycles
|
||||
value: 1
|
||||
- name: Cycles13_5
|
||||
description: 13.5 cycles
|
||||
value: 2
|
||||
- name: Cycles28_5
|
||||
description: 28.5 cycles
|
||||
value: 3
|
||||
- name: Cycles41_5
|
||||
description: 41.5 cycles
|
||||
value: 4
|
||||
- name: Cycles55_5
|
||||
description: 55.5 cycles
|
||||
value: 5
|
||||
- name: Cycles71_5
|
||||
description: 71.5 cycles
|
||||
value: 6
|
||||
- name: Cycles239_5
|
||||
description: 239.5 cycles
|
||||
value: 7
|
||||
- name: Cycles1_5
|
||||
description: 1.5 cycles
|
||||
value: 0
|
||||
- name: Cycles7_5
|
||||
description: 7.5 cycles
|
||||
value: 1
|
||||
- name: Cycles13_5
|
||||
description: 13.5 cycles
|
||||
value: 2
|
||||
- name: Cycles28_5
|
||||
description: 28.5 cycles
|
||||
value: 3
|
||||
- name: Cycles41_5
|
||||
description: 41.5 cycles
|
||||
value: 4
|
||||
- name: Cycles55_5
|
||||
description: 55.5 cycles
|
||||
value: 5
|
||||
- name: Cycles71_5
|
||||
description: 71.5 cycles
|
||||
value: 6
|
||||
- name: Cycles239_5
|
||||
description: 239.5 cycles
|
||||
value: 7
|
||||
enum/SCANDIR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Upward
|
||||
description: Upward scan (from CHSEL0 to CHSEL18)
|
||||
value: 0
|
||||
- name: Backward
|
||||
description: Backward scan (from CHSEL18 to CHSEL0)
|
||||
value: 1
|
||||
- name: Upward
|
||||
description: Upward scan (from CHSEL0 to CHSEL18)
|
||||
value: 0
|
||||
- name: Backward
|
||||
description: Backward scan (from CHSEL18 to CHSEL0)
|
||||
value: 1
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,525 +1,524 @@
|
||||
---
|
||||
block/ADC:
|
||||
description: Analog-to-Digital Converter
|
||||
items:
|
||||
- name: ISR
|
||||
description: interrupt and status register
|
||||
byte_offset: 0
|
||||
fieldset: ISR
|
||||
- name: IER
|
||||
description: interrupt enable register
|
||||
byte_offset: 4
|
||||
fieldset: IER
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 8
|
||||
fieldset: CR
|
||||
- name: CFGR
|
||||
description: configuration register
|
||||
byte_offset: 12
|
||||
fieldset: CFGR
|
||||
- name: CFGR2
|
||||
description: configuration register
|
||||
byte_offset: 16
|
||||
fieldset: CFGR2
|
||||
- name: SMPR
|
||||
description: sample time register 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 20
|
||||
fieldset: SMPR
|
||||
- name: TR
|
||||
description: watchdog threshold register 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 4
|
||||
byte_offset: 32
|
||||
fieldset: TR
|
||||
- name: SQR1
|
||||
description: regular sequence register 1
|
||||
byte_offset: 48
|
||||
fieldset: SQR1
|
||||
- name: SQR2
|
||||
description: regular sequence register 2
|
||||
byte_offset: 52
|
||||
fieldset: SQR2
|
||||
- name: SQR3
|
||||
description: regular sequence register 3
|
||||
byte_offset: 56
|
||||
fieldset: SQR3
|
||||
- name: SQR4
|
||||
description: regular sequence register 4
|
||||
byte_offset: 60
|
||||
fieldset: SQR4
|
||||
- name: DR
|
||||
description: regular Data Register
|
||||
byte_offset: 64
|
||||
access: Read
|
||||
fieldset: DR
|
||||
- name: JSQR
|
||||
description: injected sequence register
|
||||
byte_offset: 76
|
||||
fieldset: JSQR
|
||||
- name: OFR
|
||||
description: offset register 1
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 96
|
||||
fieldset: OFR
|
||||
- name: JDR
|
||||
description: injected data registers
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 128
|
||||
access: Read
|
||||
fieldset: JDR
|
||||
- name: AWD2CR
|
||||
description: Analog Watchdog 2 Configuration Register
|
||||
byte_offset: 160
|
||||
fieldset: AWD2CR
|
||||
- name: AWD3CR
|
||||
description: Analog Watchdog 3 Configuration Register
|
||||
byte_offset: 164
|
||||
fieldset: AWD3CR
|
||||
- name: DIFSEL
|
||||
description: Differential Mode Selection Register 2
|
||||
byte_offset: 176
|
||||
fieldset: DIFSEL
|
||||
- name: CALFACT
|
||||
description: Calibration Factors
|
||||
byte_offset: 180
|
||||
fieldset: CALFACT
|
||||
- name: ISR
|
||||
description: interrupt and status register
|
||||
byte_offset: 0
|
||||
fieldset: ISR
|
||||
- name: IER
|
||||
description: interrupt enable register
|
||||
byte_offset: 4
|
||||
fieldset: IER
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 8
|
||||
fieldset: CR
|
||||
- name: CFGR
|
||||
description: configuration register
|
||||
byte_offset: 12
|
||||
fieldset: CFGR
|
||||
- name: CFGR2
|
||||
description: configuration register
|
||||
byte_offset: 16
|
||||
fieldset: CFGR2
|
||||
- name: SMPR
|
||||
description: sample time register 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 20
|
||||
fieldset: SMPR
|
||||
- name: TR
|
||||
description: watchdog threshold register 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 4
|
||||
byte_offset: 32
|
||||
fieldset: TR
|
||||
- name: SQR1
|
||||
description: regular sequence register 1
|
||||
byte_offset: 48
|
||||
fieldset: SQR1
|
||||
- name: SQR2
|
||||
description: regular sequence register 2
|
||||
byte_offset: 52
|
||||
fieldset: SQR2
|
||||
- name: SQR3
|
||||
description: regular sequence register 3
|
||||
byte_offset: 56
|
||||
fieldset: SQR3
|
||||
- name: SQR4
|
||||
description: regular sequence register 4
|
||||
byte_offset: 60
|
||||
fieldset: SQR4
|
||||
- name: DR
|
||||
description: regular Data Register
|
||||
byte_offset: 64
|
||||
access: Read
|
||||
fieldset: DR
|
||||
- name: JSQR
|
||||
description: injected sequence register
|
||||
byte_offset: 76
|
||||
fieldset: JSQR
|
||||
- name: OFR
|
||||
description: offset register 1
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 96
|
||||
fieldset: OFR
|
||||
- name: JDR
|
||||
description: injected data registers
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 128
|
||||
access: Read
|
||||
fieldset: JDR
|
||||
- name: AWD2CR
|
||||
description: Analog Watchdog 2 Configuration Register
|
||||
byte_offset: 160
|
||||
fieldset: AWD2CR
|
||||
- name: AWD3CR
|
||||
description: Analog Watchdog 3 Configuration Register
|
||||
byte_offset: 164
|
||||
fieldset: AWD3CR
|
||||
- name: DIFSEL
|
||||
description: Differential Mode Selection Register 2
|
||||
byte_offset: 176
|
||||
fieldset: DIFSEL
|
||||
- name: CALFACT
|
||||
description: Calibration Factors
|
||||
byte_offset: 180
|
||||
fieldset: CALFACT
|
||||
fieldset/AWD2CR:
|
||||
description: Analog Watchdog 2 Configuration Register
|
||||
fields:
|
||||
- name: AWD2CH
|
||||
description: AWD2CH
|
||||
bit_offset: 1
|
||||
bit_size: 18
|
||||
- name: AWD2CH
|
||||
description: AWD2CH
|
||||
bit_offset: 1
|
||||
bit_size: 18
|
||||
fieldset/AWD3CR:
|
||||
description: Analog Watchdog 3 Configuration Register
|
||||
fields:
|
||||
- name: AWD3CH
|
||||
description: AWD3CH
|
||||
bit_offset: 1
|
||||
bit_size: 18
|
||||
- name: AWD3CH
|
||||
description: AWD3CH
|
||||
bit_offset: 1
|
||||
bit_size: 18
|
||||
fieldset/CALFACT:
|
||||
description: Calibration Factors
|
||||
fields:
|
||||
- name: CALFACT_S
|
||||
description: CALFACT_S
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: CALFACT_D
|
||||
description: CALFACT_D
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
- name: CALFACT_S
|
||||
description: CALFACT_S
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: CALFACT_D
|
||||
description: CALFACT_D
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
fieldset/CFGR:
|
||||
description: configuration register
|
||||
fields:
|
||||
- name: DMAEN
|
||||
description: DMAEN
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DMACFG
|
||||
description: DMACFG
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: RES
|
||||
description: RES
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
enum: RES
|
||||
- name: ALIGN
|
||||
description: ALIGN
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: EXTSEL
|
||||
description: EXTSEL
|
||||
bit_offset: 6
|
||||
bit_size: 4
|
||||
- name: EXTEN
|
||||
description: EXTEN
|
||||
bit_offset: 10
|
||||
bit_size: 2
|
||||
- name: OVRMOD
|
||||
description: OVRMOD
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: CONT
|
||||
description: CONT
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: AUTDLY
|
||||
description: AUTDLY
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: AUTOFF
|
||||
description: AUTOFF
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: DISCEN
|
||||
description: DISCEN
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: DISCNUM
|
||||
description: DISCNUM
|
||||
bit_offset: 17
|
||||
bit_size: 3
|
||||
- name: JDISCEN
|
||||
description: JDISCEN
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: JQM
|
||||
description: JQM
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: AWD1SGL
|
||||
description: AWD1SGL
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: AWD1EN
|
||||
description: AWD1EN
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: JAWD1EN
|
||||
description: JAWD1EN
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: JAUTO
|
||||
description: JAUTO
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: AWDCH1CH
|
||||
description: AWDCH1CH
|
||||
bit_offset: 26
|
||||
bit_size: 5
|
||||
- name: DMAEN
|
||||
description: DMAEN
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DMACFG
|
||||
description: DMACFG
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: RES
|
||||
description: RES
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
enum: RES
|
||||
- name: ALIGN
|
||||
description: ALIGN
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: EXTSEL
|
||||
description: EXTSEL
|
||||
bit_offset: 6
|
||||
bit_size: 4
|
||||
- name: EXTEN
|
||||
description: EXTEN
|
||||
bit_offset: 10
|
||||
bit_size: 2
|
||||
- name: OVRMOD
|
||||
description: OVRMOD
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: CONT
|
||||
description: CONT
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: AUTDLY
|
||||
description: AUTDLY
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: AUTOFF
|
||||
description: AUTOFF
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: DISCEN
|
||||
description: DISCEN
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: DISCNUM
|
||||
description: DISCNUM
|
||||
bit_offset: 17
|
||||
bit_size: 3
|
||||
- name: JDISCEN
|
||||
description: JDISCEN
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: JQM
|
||||
description: JQM
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: AWD1SGL
|
||||
description: AWD1SGL
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: AWD1EN
|
||||
description: AWD1EN
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: JAWD1EN
|
||||
description: JAWD1EN
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: JAUTO
|
||||
description: JAUTO
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: AWDCH1CH
|
||||
description: AWDCH1CH
|
||||
bit_offset: 26
|
||||
bit_size: 5
|
||||
fieldset/CFGR2:
|
||||
description: configuration register
|
||||
fields:
|
||||
- name: ROVSE
|
||||
description: DMAEN
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: JOVSE
|
||||
description: DMACFG
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: OVSR
|
||||
description: RES
|
||||
bit_offset: 2
|
||||
bit_size: 3
|
||||
- name: OVSS
|
||||
description: ALIGN
|
||||
bit_offset: 5
|
||||
bit_size: 4
|
||||
- name: TOVS
|
||||
description: EXTSEL
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ROVSM
|
||||
description: EXTEN
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ROVSE
|
||||
description: DMAEN
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: JOVSE
|
||||
description: DMACFG
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: OVSR
|
||||
description: RES
|
||||
bit_offset: 2
|
||||
bit_size: 3
|
||||
- name: OVSS
|
||||
description: ALIGN
|
||||
bit_offset: 5
|
||||
bit_size: 4
|
||||
- name: TOVS
|
||||
description: EXTSEL
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ROVSM
|
||||
description: EXTEN
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: control register
|
||||
fields:
|
||||
- name: ADEN
|
||||
description: ADEN
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: ADDIS
|
||||
description: ADDIS
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ADSTART
|
||||
description: ADSTART
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: JADSTART
|
||||
description: JADSTART
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: ADSTP
|
||||
description: ADSTP
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: JADSTP
|
||||
description: JADSTP
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: ADVREGEN
|
||||
description: ADVREGEN
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: DEEPPWD
|
||||
description: DEEPPWD
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: ADCALDIF
|
||||
description: ADCALDIF
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: ADCAL
|
||||
description: ADCAL
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: ADEN
|
||||
description: ADEN
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: ADDIS
|
||||
description: ADDIS
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ADSTART
|
||||
description: ADSTART
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: JADSTART
|
||||
description: JADSTART
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: ADSTP
|
||||
description: ADSTP
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: JADSTP
|
||||
description: JADSTP
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: ADVREGEN
|
||||
description: ADVREGEN
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: DEEPPWD
|
||||
description: DEEPPWD
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: ADCALDIF
|
||||
description: ADCALDIF
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: ADCAL
|
||||
description: ADCAL
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/DIFSEL:
|
||||
description: Differential Mode Selection Register 2
|
||||
fields:
|
||||
- name: DIFSEL_1_15
|
||||
description: Differential mode for channels 15 to 1
|
||||
bit_offset: 1
|
||||
bit_size: 15
|
||||
- name: DIFSEL_16_18
|
||||
description: Differential mode for channels 18 to 16
|
||||
bit_offset: 16
|
||||
bit_size: 3
|
||||
- name: DIFSEL_1_15
|
||||
description: Differential mode for channels 15 to 1
|
||||
bit_offset: 1
|
||||
bit_size: 15
|
||||
- name: DIFSEL_16_18
|
||||
description: Differential mode for channels 18 to 16
|
||||
bit_offset: 16
|
||||
bit_size: 3
|
||||
fieldset/DR:
|
||||
description: regular Data Register
|
||||
fields:
|
||||
- name: regularDATA
|
||||
description: regularDATA
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: regularDATA
|
||||
description: regularDATA
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/IER:
|
||||
description: interrupt enable register
|
||||
fields:
|
||||
- name: ADRDYIE
|
||||
description: ADRDYIE
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMPIE
|
||||
description: EOSMPIE
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: EOCIE
|
||||
description: EOCIE
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOSIE
|
||||
description: EOSIE
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: OVRIE
|
||||
description: OVRIE
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: JEOCIE
|
||||
description: JEOCIE
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: JEOSIE
|
||||
description: JEOSIE
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: AWD1IE
|
||||
description: AWD1IE
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: AWD2IE
|
||||
description: AWD2IE
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: AWD3IE
|
||||
description: AWD3IE
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: JQOVFIE
|
||||
description: JQOVFIE
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ADRDYIE
|
||||
description: ADRDYIE
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMPIE
|
||||
description: EOSMPIE
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: EOCIE
|
||||
description: EOCIE
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOSIE
|
||||
description: EOSIE
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: OVRIE
|
||||
description: OVRIE
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: JEOCIE
|
||||
description: JEOCIE
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: JEOSIE
|
||||
description: JEOSIE
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: AWD1IE
|
||||
description: AWD1IE
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: AWD2IE
|
||||
description: AWD2IE
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: AWD3IE
|
||||
description: AWD3IE
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: JQOVFIE
|
||||
description: JQOVFIE
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
fieldset/ISR:
|
||||
description: interrupt and status register
|
||||
fields:
|
||||
- name: ADRDY
|
||||
description: ADRDY
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMP
|
||||
description: EOSMP
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: EOC
|
||||
description: EOC
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOS
|
||||
description: EOS
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: OVR
|
||||
description: OVR
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: JEOC
|
||||
description: JEOC
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: JEOS
|
||||
description: JEOS
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: AWD
|
||||
description: AWD1
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 1
|
||||
- name: JQOVF
|
||||
description: JQOVF
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ADRDY
|
||||
description: ADRDY
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMP
|
||||
description: EOSMP
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: EOC
|
||||
description: EOC
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOS
|
||||
description: EOS
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: OVR
|
||||
description: OVR
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: JEOC
|
||||
description: JEOC
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: JEOS
|
||||
description: JEOS
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: AWD
|
||||
description: AWD1
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 1
|
||||
- name: JQOVF
|
||||
description: JQOVF
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
fieldset/JDR:
|
||||
description: injected data register 1
|
||||
fields:
|
||||
- name: JDATA
|
||||
description: JDATA1
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: JDATA
|
||||
description: JDATA1
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/JSQR:
|
||||
description: injected sequence register
|
||||
fields:
|
||||
- name: JL
|
||||
description: JL
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
- name: JEXTSEL
|
||||
description: JEXTSEL
|
||||
bit_offset: 2
|
||||
bit_size: 4
|
||||
- name: JEXTEN
|
||||
description: JEXTEN
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
- name: JSQ
|
||||
description: JSQ1
|
||||
bit_offset: 8
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 4
|
||||
stride: 6
|
||||
- name: JL
|
||||
description: JL
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
- name: JEXTSEL
|
||||
description: JEXTSEL
|
||||
bit_offset: 2
|
||||
bit_size: 4
|
||||
- name: JEXTEN
|
||||
description: JEXTEN
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
- name: JSQ
|
||||
description: JSQ1
|
||||
bit_offset: 8
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 4
|
||||
stride: 6
|
||||
fieldset/OFR:
|
||||
description: offset register
|
||||
fields:
|
||||
- name: OFFSET
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: OFFSET_CH
|
||||
bit_offset: 26
|
||||
bit_size: 5
|
||||
- name: OFFSET_EN
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: OFFSET
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: OFFSET_CH
|
||||
bit_offset: 26
|
||||
bit_size: 5
|
||||
- name: OFFSET_EN
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SMPR:
|
||||
description: sample time register 1
|
||||
fields:
|
||||
- name: SMP
|
||||
description: Channel 0 sampling time selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 10
|
||||
stride: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP
|
||||
description: Channel 0 sampling time selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 10
|
||||
stride: 3
|
||||
enum: SAMPLE_TIME
|
||||
fieldset/SQR1:
|
||||
description: regular sequence register 1
|
||||
fields:
|
||||
- name: L
|
||||
description: Regular channel sequence length
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: SQ
|
||||
description: SQ1
|
||||
bit_offset: 6
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 4
|
||||
stride: 6
|
||||
- name: L
|
||||
description: Regular channel sequence length
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: SQ
|
||||
description: SQ1
|
||||
bit_offset: 6
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 4
|
||||
stride: 6
|
||||
fieldset/SQR2:
|
||||
description: regular sequence register 2
|
||||
fields:
|
||||
- name: SQ
|
||||
description: SQ5
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 5
|
||||
stride: 6
|
||||
- name: SQ
|
||||
description: SQ5
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 5
|
||||
stride: 6
|
||||
fieldset/SQR3:
|
||||
description: regular sequence register 3
|
||||
fields:
|
||||
- name: SQ
|
||||
description: SQ10
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 5
|
||||
stride: 6
|
||||
- name: SQ
|
||||
description: SQ10
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 5
|
||||
stride: 6
|
||||
fieldset/SQR4:
|
||||
description: regular sequence register 4
|
||||
fields:
|
||||
- name: SQ
|
||||
description: SQ15
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 2
|
||||
stride: 6
|
||||
- name: SQ
|
||||
description: SQ15
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 2
|
||||
stride: 6
|
||||
fieldset/TR:
|
||||
description: watchdog threshold register
|
||||
fields:
|
||||
- name: LT
|
||||
description: LT1
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: HT
|
||||
description: HT1
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
- name: LT
|
||||
description: LT1
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: HT
|
||||
description: HT1
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
enum/RES:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: TwelveBit
|
||||
description: 12-bit resolution
|
||||
value: 0
|
||||
- name: TenBit
|
||||
description: 10-bit resolution
|
||||
value: 1
|
||||
- name: EightBit
|
||||
description: 8-bit resolution
|
||||
value: 2
|
||||
- name: SixBit
|
||||
description: 6-bit resolution
|
||||
value: 3
|
||||
- name: TwelveBit
|
||||
description: 12-bit resolution
|
||||
value: 0
|
||||
- name: TenBit
|
||||
description: 10-bit resolution
|
||||
value: 1
|
||||
- name: EightBit
|
||||
description: 8-bit resolution
|
||||
value: 2
|
||||
- name: SixBit
|
||||
description: 6-bit resolution
|
||||
value: 3
|
||||
enum/SAMPLE_TIME:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Cycles2_5
|
||||
description: 2.5 ADC cycles
|
||||
value: 0
|
||||
- name: Cycles6_5
|
||||
description: 6.5 ADC cycles
|
||||
value: 1
|
||||
- name: Cycles12_5
|
||||
description: 12.5 ADC cycles
|
||||
value: 2
|
||||
- name: Cycles24_5
|
||||
description: 24.5 ADC cycles
|
||||
value: 3
|
||||
- name: Cycles47_5
|
||||
description: 47.5 ADC cycles
|
||||
value: 4
|
||||
- name: Cycles92_5
|
||||
description: 92.5 ADC cycles
|
||||
value: 5
|
||||
- name: Cycles247_5
|
||||
description: 247.5 ADC cycles
|
||||
value: 6
|
||||
- name: Cycles640_5
|
||||
description: 640.5 ADC cycles
|
||||
value: 7
|
||||
- name: Cycles2_5
|
||||
description: 2.5 ADC cycles
|
||||
value: 0
|
||||
- name: Cycles6_5
|
||||
description: 6.5 ADC cycles
|
||||
value: 1
|
||||
- name: Cycles12_5
|
||||
description: 12.5 ADC cycles
|
||||
value: 2
|
||||
- name: Cycles24_5
|
||||
description: 24.5 ADC cycles
|
||||
value: 3
|
||||
- name: Cycles47_5
|
||||
description: 47.5 ADC cycles
|
||||
value: 4
|
||||
- name: Cycles92_5
|
||||
description: 92.5 ADC cycles
|
||||
value: 5
|
||||
- name: Cycles247_5
|
||||
description: 247.5 ADC cycles
|
||||
value: 6
|
||||
- name: Cycles640_5
|
||||
description: 640.5 ADC cycles
|
||||
value: 7
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
284
data/registers/adccommon_f3.yaml
Normal file
284
data/registers/adccommon_f3.yaml
Normal file
@ -0,0 +1,284 @@
|
||||
block/ADC_COMMON:
|
||||
description: ADC common registers
|
||||
items:
|
||||
- name: CSR
|
||||
description: ADC Common status register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: CSR
|
||||
- name: CCR
|
||||
description: ADC common control register
|
||||
byte_offset: 8
|
||||
fieldset: CCR
|
||||
- name: CDR
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
byte_offset: 12
|
||||
access: Read
|
||||
fieldset: CDR
|
||||
fieldset/CCR:
|
||||
description: ADC common control register
|
||||
fields:
|
||||
- name: DUAL
|
||||
description: Dual ADC mode selection
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
enum: DUAL
|
||||
- name: DELAY
|
||||
description: Delay between 2 sampling phases
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
- name: DMACFG
|
||||
description: DMA configuration (for multi-ADC mode)
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
enum: DMACFG
|
||||
- name: MDMA
|
||||
description: Direct memory access mode for multi ADC mode
|
||||
bit_offset: 14
|
||||
bit_size: 2
|
||||
enum: MDMA
|
||||
- name: CKMODE
|
||||
description: ADC clock mode
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: CKMODE
|
||||
- name: VREFEN
|
||||
description: VREFINT enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TSEN
|
||||
description: Temperature sensor enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: VBATEN
|
||||
description: VBAT enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/CDR:
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
fields:
|
||||
- name: RDATA_MST
|
||||
description: Regular data of the master ADC
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: RDATA_SLV
|
||||
description: Regular data of the master ADC
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/CSR:
|
||||
fields:
|
||||
- name: ADRDY_MST
|
||||
description: Master ADC ready
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMP_MST
|
||||
description: End of sampling phase flag of the master ADC
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: EOC_MST
|
||||
description: End of regular conversion of the master ADC
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: EOS_MST
|
||||
description: End of regular sequence flag of the master ADC
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: OVR_MST
|
||||
description: Overrun flag of the master ADC
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: OVR
|
||||
- name: JEOC_MST
|
||||
description: End of injected conversion of the master ADC
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: JEOS
|
||||
description: End of injected sequence flag of the master ADC
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: AWD1_MST
|
||||
description: Analog watchdog 1 flag of the master ADC
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: AWD
|
||||
- name: AWD2_MST
|
||||
description: Analog watchdog 2 flag of the master ADC
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: AWD
|
||||
- name: AWD3_MST
|
||||
description: Analog watchdog 3 flag of the master ADC
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: AWD
|
||||
- name: JQOVF_MST
|
||||
description: Injected context queue overflow flag of the master ADC
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: JQOVF
|
||||
- name: ADRDY_SLV
|
||||
description: Slave ADC ready
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOSMP_SLV
|
||||
description: End of sampling phase flag of the slave ADC
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: EOC_SLV
|
||||
description: End of regular conversion of the slave ADC
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: EOS_SLV
|
||||
description: End of regular sequence flag of the slave ADC
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: OVR_SLV
|
||||
description: Overrun flag of the slave ADC
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
enum: OVR
|
||||
- name: JEOC_SLV
|
||||
description: End of injected conversion of the slave ADC
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: JEOS_SLV
|
||||
description: End of injected sequence flag of the slave ADC
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: AWD1_SLV
|
||||
description: Analog watchdog 1 flag of the slave ADC
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
enum: AWD
|
||||
- name: AWD2_SLV
|
||||
description: Analog watchdog 2 flag of the slave ADC
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
enum: AWD
|
||||
- name: AWD3_SLV
|
||||
description: Analog watchdog 3 flag of the slave ADC
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
enum: AWD
|
||||
- name: JQOVF_SLV
|
||||
description: Injected context queue overflow flag of the slave ADC
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
enum: JQOVF
|
||||
enum/AWD:
|
||||
description: Analog watchdog flag
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoEvent
|
||||
description: No analog watchdog event occurred
|
||||
value: 0
|
||||
- name: Event
|
||||
description: Analog watchdog event occurred
|
||||
value: 1
|
||||
enum/CKMODE:
|
||||
description: ADC clock mode
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Asynchronous
|
||||
description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous mode
|
||||
value: 0
|
||||
- name: SyncDiv1
|
||||
description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck.
|
||||
value: 1
|
||||
- name: SyncDiv2
|
||||
description: Use AHB clock rcc_hclk3 divided by 2.
|
||||
value: 2
|
||||
- name: SyncDiv4
|
||||
description: Use AHB clock rcc_hclk3 divided by 4.
|
||||
value: 3
|
||||
enum/DMACFG:
|
||||
description: DMA configuration (for multi-ADC mode)
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: OneShot
|
||||
description: DMA one shot mode selected
|
||||
value: 0
|
||||
- name: Circulator
|
||||
description: DMA circular mode selected
|
||||
value: 1
|
||||
enum/DUAL:
|
||||
description: Dual ADC mode selection
|
||||
bit_size: 5
|
||||
variants:
|
||||
- name: Independent
|
||||
description: Independent mode
|
||||
value: 0
|
||||
- name: DualRJ
|
||||
description: Dual, combined regular simultaneous + injected simultaneous mode
|
||||
value: 1
|
||||
- name: DualRA
|
||||
description: Dual, combined regular simultaneous + alternate trigger mode
|
||||
value: 2
|
||||
- name: DualIJ
|
||||
description: Dual, combined injected simultaneous + fast interleaved mode
|
||||
value: 3
|
||||
- name: DualJ
|
||||
description: Dual, injected simultaneous mode only
|
||||
value: 5
|
||||
- name: DualR
|
||||
description: Dual, regular simultaneous mode only
|
||||
value: 6
|
||||
- name: DualI
|
||||
description: dual, interleaved mode only
|
||||
value: 7
|
||||
- name: DualA
|
||||
description: Dual, alternate trigger mode only
|
||||
value: 9
|
||||
enum/ENDED:
|
||||
description: End of operation
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotEnded
|
||||
description: Operation is not ended
|
||||
value: 0
|
||||
- name: Ended
|
||||
description: Operation is ended
|
||||
value: 1
|
||||
enum/JQOVF:
|
||||
description: Injected context queue overflow flag
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoOverflow
|
||||
description: No injected context queue overflow
|
||||
value: 0
|
||||
- name: Overflow
|
||||
description: Injected context queue overflow
|
||||
value: 1
|
||||
enum/MDMA:
|
||||
description: Direct memory access mode for multi ADC mode
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: MDMA mode disabled
|
||||
value: 0
|
||||
- name: Bits12_10
|
||||
description: MDMA mode enabled for 12 and 10-bit resolution
|
||||
value: 2
|
||||
- name: Bit8_6
|
||||
description: MDMA mode enabled for 8 and 6-bit resolution
|
||||
value: 3
|
||||
enum/OVR:
|
||||
description: Overrun flag
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoOverrun
|
||||
description: No overrun occurred
|
||||
value: 0
|
||||
- name: Overrun
|
||||
description: Overrun occurred
|
||||
value: 1
|
||||
@ -1,269 +1,248 @@
|
||||
---
|
||||
block/ADC_COMMON:
|
||||
description: ADC common registers
|
||||
items:
|
||||
- name: CSR
|
||||
description: ADC Common status register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: CSR
|
||||
- name: CCR
|
||||
description: ADC common control register
|
||||
byte_offset: 4
|
||||
fieldset: CCR
|
||||
- name: CDR
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
byte_offset: 8
|
||||
access: Read
|
||||
fieldset: CDR
|
||||
- name: CSR
|
||||
description: ADC Common status register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: CSR
|
||||
- name: CCR
|
||||
description: ADC common control register
|
||||
byte_offset: 4
|
||||
fieldset: CCR
|
||||
- name: CDR
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
byte_offset: 8
|
||||
access: Read
|
||||
fieldset: CDR
|
||||
fieldset/CCR:
|
||||
description: ADC common control register
|
||||
fields:
|
||||
- name: MULTI
|
||||
description: Multi ADC mode selection
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
enum: MULTI
|
||||
- name: DELAY
|
||||
description: Delay between 2 sampling phases
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
- name: DDS
|
||||
description: DMA disable selection for multi-ADC mode
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
enum: DDS
|
||||
- name: DMA
|
||||
description: Direct memory access mode for multi ADC mode
|
||||
bit_offset: 14
|
||||
bit_size: 2
|
||||
enum: DMA
|
||||
- name: ADCPRE
|
||||
description: ADC prescaler
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: ADCPRE
|
||||
- name: VBATE
|
||||
description: VBAT enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
enum: VBATE
|
||||
- name: TSVREFE
|
||||
description: Temperature sensor and VREFINT enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
enum: TSVREFE
|
||||
- name: MULTI
|
||||
description: Multi ADC mode selection
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
enum: MULTI
|
||||
- name: DELAY
|
||||
description: Delay between 2 sampling phases
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
- name: DDS
|
||||
description: DMA disable selection for multi-ADC mode
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
enum: DDS
|
||||
- name: DMA
|
||||
description: Direct memory access mode for multi ADC mode
|
||||
bit_offset: 14
|
||||
bit_size: 2
|
||||
enum: DMA
|
||||
- name: ADCPRE
|
||||
description: ADC prescaler
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: ADCPRE
|
||||
- name: VBATE
|
||||
description: VBAT enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TSVREFE
|
||||
description: Temperature sensor and VREFINT enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/CDR:
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
fields:
|
||||
- name: DATA
|
||||
description: 1st data item of a pair of regular conversions
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DATA
|
||||
description: 1st data item of a pair of regular conversions
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/CSR:
|
||||
description: ADC common status register
|
||||
fields:
|
||||
- name: AWD
|
||||
description: Analog watchdog flag of ADC 1
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 8
|
||||
enum: AWD
|
||||
- name: EOC
|
||||
description: End of conversion of ADC 1
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 8
|
||||
enum: EOC
|
||||
- name: JEOC
|
||||
description: Injected channel end of conversion of ADC 1
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 8
|
||||
enum: JEOC
|
||||
- name: JSTRT
|
||||
description: Injected channel Start flag of ADC 1
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 8
|
||||
enum: JSTRT
|
||||
- name: STRT
|
||||
description: Regular channel Start flag of ADC 1
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 8
|
||||
enum: STRT
|
||||
- name: OVR
|
||||
description: Overrun flag of ADC 1
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 8
|
||||
enum: OVR
|
||||
- name: AWD
|
||||
description: Analog watchdog flag of ADC 1
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 8
|
||||
enum: AWD
|
||||
- name: EOC
|
||||
description: End of conversion of ADC 1
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 8
|
||||
enum: EOC
|
||||
- name: JEOC
|
||||
description: Injected channel end of conversion of ADC 1
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 8
|
||||
enum: JEOC
|
||||
- name: JSTRT
|
||||
description: Injected channel Start flag of ADC 1
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 8
|
||||
enum: JSTRT
|
||||
- name: STRT
|
||||
description: Regular channel Start flag of ADC 1
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 8
|
||||
enum: STRT
|
||||
- name: OVR
|
||||
description: Overrun flag of ADC 1
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 8
|
||||
enum: OVR
|
||||
enum/ADCPRE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Div2
|
||||
description: PCLK2 divided by 2
|
||||
value: 0
|
||||
- name: Div4
|
||||
description: PCLK2 divided by 4
|
||||
value: 1
|
||||
- name: Div6
|
||||
description: PCLK2 divided by 6
|
||||
value: 2
|
||||
- name: Div8
|
||||
description: PCLK2 divided by 8
|
||||
value: 3
|
||||
- name: Div2
|
||||
description: PCLK2 divided by 2
|
||||
value: 0
|
||||
- name: Div4
|
||||
description: PCLK2 divided by 4
|
||||
value: 1
|
||||
- name: Div6
|
||||
description: PCLK2 divided by 6
|
||||
value: 2
|
||||
- name: Div8
|
||||
description: PCLK2 divided by 8
|
||||
value: 3
|
||||
enum/AWD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoEvent
|
||||
description: No analog watchdog event occurred
|
||||
value: 0
|
||||
- name: Event
|
||||
description: Analog watchdog event occurred
|
||||
value: 1
|
||||
- name: NoEvent
|
||||
description: No analog watchdog event occurred
|
||||
value: 0
|
||||
- name: Event
|
||||
description: Analog watchdog event occurred
|
||||
value: 1
|
||||
enum/DDS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Single
|
||||
description: No new DMA request is issued after the last transfer
|
||||
value: 0
|
||||
- name: Continuous
|
||||
description: "DMA requests are issued as long as data are converted and DMA=01, 10 or 11"
|
||||
value: 1
|
||||
- name: Single
|
||||
description: No new DMA request is issued after the last transfer
|
||||
value: 0
|
||||
- name: Continuous
|
||||
description: DMA requests are issued as long as data are converted and DMA=01, 10 or 11
|
||||
value: 1
|
||||
enum/DMA:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: DMA mode disabled
|
||||
value: 0
|
||||
- name: Mode1
|
||||
description: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)
|
||||
value: 1
|
||||
- name: Mode2
|
||||
description: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
|
||||
value: 2
|
||||
- name: Mode3
|
||||
description: DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
|
||||
value: 3
|
||||
- name: Disabled
|
||||
description: DMA mode disabled
|
||||
value: 0
|
||||
- name: Mode1
|
||||
description: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)
|
||||
value: 1
|
||||
- name: Mode2
|
||||
description: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
|
||||
value: 2
|
||||
- name: Mode3
|
||||
description: DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
|
||||
value: 3
|
||||
enum/EOC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotComplete
|
||||
description: Conversion is not complete
|
||||
value: 0
|
||||
- name: Complete
|
||||
description: Conversion complete
|
||||
value: 1
|
||||
- name: NotComplete
|
||||
description: Conversion is not complete
|
||||
value: 0
|
||||
- name: Complete
|
||||
description: Conversion complete
|
||||
value: 1
|
||||
enum/JEOC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotComplete
|
||||
description: Conversion is not complete
|
||||
value: 0
|
||||
- name: Complete
|
||||
description: Conversion complete
|
||||
value: 1
|
||||
- name: NotComplete
|
||||
description: Conversion is not complete
|
||||
value: 0
|
||||
- name: Complete
|
||||
description: Conversion complete
|
||||
value: 1
|
||||
enum/JSTRT:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotStarted
|
||||
description: No injected channel conversion started
|
||||
value: 0
|
||||
- name: Started
|
||||
description: Injected channel conversion has started
|
||||
value: 1
|
||||
- name: NotStarted
|
||||
description: No injected channel conversion started
|
||||
value: 0
|
||||
- name: Started
|
||||
description: Injected channel conversion has started
|
||||
value: 1
|
||||
enum/MULTI:
|
||||
bit_size: 5
|
||||
variants:
|
||||
- name: Independent
|
||||
description: "All the ADCs independent: independent mode"
|
||||
value: 0
|
||||
- name: DualRJ
|
||||
description: "Dual ADC1 and ADC2, combined regular and injected simultaneous mode"
|
||||
value: 1
|
||||
- name: DualRA
|
||||
description: "Dual ADC1 and ADC2, combined regular and alternate trigger mode"
|
||||
value: 2
|
||||
- name: DualJ
|
||||
description: "Dual ADC1 and ADC2, injected simultaneous mode only"
|
||||
value: 5
|
||||
- name: DualR
|
||||
description: "Dual ADC1 and ADC2, regular simultaneous mode only"
|
||||
value: 6
|
||||
- name: DualI
|
||||
description: "Dual ADC1 and ADC2, interleaved mode only"
|
||||
value: 7
|
||||
- name: DualA
|
||||
description: "Dual ADC1 and ADC2, alternate trigger mode only"
|
||||
value: 9
|
||||
- name: TripleRJ
|
||||
description: "Triple ADC, regular and injected simultaneous mode"
|
||||
value: 17
|
||||
- name: TripleRA
|
||||
description: "Triple ADC, regular and alternate trigger mode"
|
||||
value: 18
|
||||
- name: TripleJ
|
||||
description: "Triple ADC, injected simultaneous mode only"
|
||||
value: 21
|
||||
- name: TripleR
|
||||
description: "Triple ADC, regular simultaneous mode only"
|
||||
value: 22
|
||||
- name: TripleI
|
||||
description: "Triple ADC, interleaved mode only"
|
||||
value: 23
|
||||
- name: TripleA
|
||||
description: "Triple ADC, alternate trigger mode only"
|
||||
value: 24
|
||||
- name: Independent
|
||||
description: 'All the ADCs independent: independent mode'
|
||||
value: 0
|
||||
- name: DualRJ
|
||||
description: Dual ADC1 and ADC2, combined regular and injected simultaneous mode
|
||||
value: 1
|
||||
- name: DualRA
|
||||
description: Dual ADC1 and ADC2, combined regular and alternate trigger mode
|
||||
value: 2
|
||||
- name: DualJ
|
||||
description: Dual ADC1 and ADC2, injected simultaneous mode only
|
||||
value: 5
|
||||
- name: DualR
|
||||
description: Dual ADC1 and ADC2, regular simultaneous mode only
|
||||
value: 6
|
||||
- name: DualI
|
||||
description: Dual ADC1 and ADC2, interleaved mode only
|
||||
value: 7
|
||||
- name: DualA
|
||||
description: Dual ADC1 and ADC2, alternate trigger mode only
|
||||
value: 9
|
||||
- name: TripleRJ
|
||||
description: Triple ADC, regular and injected simultaneous mode
|
||||
value: 17
|
||||
- name: TripleRA
|
||||
description: Triple ADC, regular and alternate trigger mode
|
||||
value: 18
|
||||
- name: TripleJ
|
||||
description: Triple ADC, injected simultaneous mode only
|
||||
value: 21
|
||||
- name: TripleR
|
||||
description: Triple ADC, regular simultaneous mode only
|
||||
value: 22
|
||||
- name: TripleI
|
||||
description: Triple ADC, interleaved mode only
|
||||
value: 23
|
||||
- name: TripleA
|
||||
description: Triple ADC, alternate trigger mode only
|
||||
value: 24
|
||||
enum/OVR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoOverrun
|
||||
description: No overrun occurred
|
||||
value: 0
|
||||
- name: Overrun
|
||||
description: Overrun occurred
|
||||
value: 1
|
||||
- name: NoOverrun
|
||||
description: No overrun occurred
|
||||
value: 0
|
||||
- name: Overrun
|
||||
description: Overrun occurred
|
||||
value: 1
|
||||
enum/STRT:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotStarted
|
||||
description: No regular channel conversion started
|
||||
value: 0
|
||||
- name: Started
|
||||
description: Regular channel conversion has started
|
||||
value: 1
|
||||
enum/TSVREFE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Temperature sensor and V_REFINT channel disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Temperature sensor and V_REFINT channel enabled
|
||||
value: 1
|
||||
enum/VBATE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: V_BAT channel disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: V_BAT channel enabled
|
||||
value: 1
|
||||
- name: NotStarted
|
||||
description: No regular channel conversion started
|
||||
value: 0
|
||||
- name: Started
|
||||
description: Regular channel conversion has started
|
||||
value: 1
|
||||
|
||||
@ -1,155 +1,154 @@
|
||||
---
|
||||
block/ADC_COMMON:
|
||||
description: Analog-to-Digital Converter
|
||||
items:
|
||||
- name: CSR
|
||||
description: ADC Common status register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: CSR
|
||||
- name: CCR
|
||||
description: ADC common control register
|
||||
byte_offset: 8
|
||||
fieldset: CCR
|
||||
- name: CDR
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
byte_offset: 12
|
||||
access: Read
|
||||
fieldset: CDR
|
||||
- name: CSR
|
||||
description: ADC Common status register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: CSR
|
||||
- name: CCR
|
||||
description: ADC common control register
|
||||
byte_offset: 8
|
||||
fieldset: CCR
|
||||
- name: CDR
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
byte_offset: 12
|
||||
access: Read
|
||||
fieldset: CDR
|
||||
fieldset/CCR:
|
||||
description: ADC common control register
|
||||
fields:
|
||||
- name: MULT
|
||||
description: Multi ADC mode selection
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: DELAY
|
||||
description: Delay between 2 sampling phases
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
- name: DMACFG
|
||||
description: DMA configuration (for multi-ADC mode)
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: MDMA
|
||||
description: Direct memory access mode for multi ADC mode
|
||||
bit_offset: 14
|
||||
bit_size: 2
|
||||
- name: CKMODE
|
||||
description: ADC clock mode
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
- name: VREFEN
|
||||
description: VREFINT enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: CH18SEL
|
||||
description: CH18 selection (Vbat)
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: CH17SEL
|
||||
description: CH17 selection (temperature)
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: MULT
|
||||
description: Multi ADC mode selection
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: DELAY
|
||||
description: Delay between 2 sampling phases
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
- name: DMACFG
|
||||
description: DMA configuration (for multi-ADC mode)
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: MDMA
|
||||
description: Direct memory access mode for multi ADC mode
|
||||
bit_offset: 14
|
||||
bit_size: 2
|
||||
- name: CKMODE
|
||||
description: ADC clock mode
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
- name: VREFEN
|
||||
description: VREFINT enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: CH18SEL
|
||||
description: CH18 selection (Vbat)
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: CH17SEL
|
||||
description: CH17 selection (temperature)
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/CDR:
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
fields:
|
||||
- name: RDATA_MST
|
||||
description: Regular data of the master ADC
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: RDATA_SLV
|
||||
description: Regular data of the slave ADC
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: RDATA_MST
|
||||
description: Regular data of the master ADC
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: RDATA_SLV
|
||||
description: Regular data of the slave ADC
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/CSR:
|
||||
description: ADC Common status register
|
||||
fields:
|
||||
- name: ADDRDY_MST
|
||||
description: ADDRDY_MST
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMP_MST
|
||||
description: EOSMP_MST
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: EOC_MST
|
||||
description: EOC_MST
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOS_MST
|
||||
description: EOS_MST
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: OVR_MST
|
||||
description: OVR_MST
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: JEOC_MST
|
||||
description: JEOC_MST
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: JEOS_MST
|
||||
description: JEOS_MST
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: AWD1_MST
|
||||
description: AWD1_MST
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: AWD2_MST
|
||||
description: AWD2_MST
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: AWD3_MST
|
||||
description: AWD3_MST
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: JQOVF_MST
|
||||
description: JQOVF_MST
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ADRDY_SLV
|
||||
description: ADRDY_SLV
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOSMP_SLV
|
||||
description: EOSMP_SLV
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: EOC_SLV
|
||||
description: End of regular conversion of the slave ADC
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: EOS_SLV
|
||||
description: End of regular sequence flag of the slave ADC
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: OVR_SLV
|
||||
description: Overrun flag of the slave ADC
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: JEOC_SLV
|
||||
description: End of injected conversion flag of the slave ADC
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: JEOS_SLV
|
||||
description: End of injected sequence flag of the slave ADC
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: AWD1_SLV
|
||||
description: Analog watchdog 1 flag of the slave ADC
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: AWD2_SLV
|
||||
description: Analog watchdog 2 flag of the slave ADC
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: AWD3_SLV
|
||||
description: Analog watchdog 3 flag of the slave ADC
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: JQOVF_SLV
|
||||
description: Injected Context Queue Overflow flag of the slave ADC
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: ADDRDY_MST
|
||||
description: ADDRDY_MST
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMP_MST
|
||||
description: EOSMP_MST
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: EOC_MST
|
||||
description: EOC_MST
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOS_MST
|
||||
description: EOS_MST
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: OVR_MST
|
||||
description: OVR_MST
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: JEOC_MST
|
||||
description: JEOC_MST
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: JEOS_MST
|
||||
description: JEOS_MST
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: AWD1_MST
|
||||
description: AWD1_MST
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: AWD2_MST
|
||||
description: AWD2_MST
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: AWD3_MST
|
||||
description: AWD3_MST
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: JQOVF_MST
|
||||
description: JQOVF_MST
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ADRDY_SLV
|
||||
description: ADRDY_SLV
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOSMP_SLV
|
||||
description: EOSMP_SLV
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: EOC_SLV
|
||||
description: End of regular conversion of the slave ADC
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: EOS_SLV
|
||||
description: End of regular sequence flag of the slave ADC
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: OVR_SLV
|
||||
description: Overrun flag of the slave ADC
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: JEOC_SLV
|
||||
description: End of injected conversion flag of the slave ADC
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: JEOS_SLV
|
||||
description: End of injected sequence flag of the slave ADC
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: AWD1_SLV
|
||||
description: Analog watchdog 1 flag of the slave ADC
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: AWD2_SLV
|
||||
description: Analog watchdog 2 flag of the slave ADC
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: AWD3_SLV
|
||||
description: Analog watchdog 3 flag of the slave ADC
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: JQOVF_SLV
|
||||
description: Injected Context Queue Overflow flag of the slave ADC
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
|
||||
@ -1,367 +1,366 @@
|
||||
---
|
||||
block/ADC_COMMON:
|
||||
description: Analog-to-Digital Converter
|
||||
items:
|
||||
- name: CSR
|
||||
description: ADC Common status register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: CSR
|
||||
- name: CCR
|
||||
description: ADC common control register
|
||||
byte_offset: 8
|
||||
fieldset: CCR
|
||||
- name: CDR
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
byte_offset: 12
|
||||
access: Read
|
||||
fieldset: CDR
|
||||
- name: CDR2
|
||||
description: ADC x common regular data register for 32-bit dual mode
|
||||
byte_offset: 16
|
||||
access: Read
|
||||
fieldset: CDR2
|
||||
- name: CSR
|
||||
description: ADC Common status register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: CSR
|
||||
- name: CCR
|
||||
description: ADC common control register
|
||||
byte_offset: 8
|
||||
fieldset: CCR
|
||||
- name: CDR
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
byte_offset: 12
|
||||
access: Read
|
||||
fieldset: CDR
|
||||
- name: CDR2
|
||||
description: ADC x common regular data register for 32-bit dual mode
|
||||
byte_offset: 16
|
||||
access: Read
|
||||
fieldset: CDR2
|
||||
fieldset/CCR:
|
||||
description: ADC common control register
|
||||
fields:
|
||||
- name: DUAL
|
||||
description: Dual ADC mode selection
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
enum: DUAL
|
||||
- name: DELAY
|
||||
description: Delay between 2 sampling phases
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
- name: DAMDF
|
||||
description: Dual ADC Mode Data Format
|
||||
bit_offset: 14
|
||||
bit_size: 2
|
||||
enum: DAMDF
|
||||
- name: CKMODE
|
||||
description: ADC clock mode
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: CKMODE
|
||||
- name: PRESC
|
||||
description: ADC prescaler
|
||||
bit_offset: 18
|
||||
bit_size: 4
|
||||
enum: PRESC
|
||||
- name: VREFEN
|
||||
description: VREFINT enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: VSENSEEN
|
||||
description: Temperature sensor enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: VBATEN
|
||||
description: VBAT enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: DUAL
|
||||
description: Dual ADC mode selection
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
enum: DUAL
|
||||
- name: DELAY
|
||||
description: Delay between 2 sampling phases
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
- name: DAMDF
|
||||
description: Dual ADC Mode Data Format
|
||||
bit_offset: 14
|
||||
bit_size: 2
|
||||
enum: DAMDF
|
||||
- name: CKMODE
|
||||
description: ADC clock mode
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: CKMODE
|
||||
- name: PRESC
|
||||
description: ADC prescaler
|
||||
bit_offset: 18
|
||||
bit_size: 4
|
||||
enum: PRESC
|
||||
- name: VREFEN
|
||||
description: VREFINT enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: VSENSEEN
|
||||
description: Temperature sensor enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: VBATEN
|
||||
description: VBAT enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/CDR:
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
fields:
|
||||
- name: RDATA_MST
|
||||
description: Regular data of the master ADC
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: RDATA_SLV
|
||||
description: Regular data of the slave ADC
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: RDATA_MST
|
||||
description: Regular data of the master ADC
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: RDATA_SLV
|
||||
description: Regular data of the slave ADC
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/CDR2:
|
||||
description: ADC x common regular data register for 32-bit dual mode
|
||||
fields:
|
||||
- name: RDATA_ALT
|
||||
description: Regular data of the master/slave alternated ADCs
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: RDATA_ALT
|
||||
description: Regular data of the master/slave alternated ADCs
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/CSR:
|
||||
description: ADC Common status register
|
||||
fields:
|
||||
- name: ADRDY_MST
|
||||
description: Master ADC ready
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
enum: ADRDY_MST
|
||||
- name: EOSMP_MST
|
||||
description: End of Sampling phase flag of the master ADC
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
enum: EOSMP_MST
|
||||
- name: EOC_MST
|
||||
description: End of regular conversion of the master ADC
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum: EOC_MST
|
||||
- name: EOS_MST
|
||||
description: End of regular sequence flag of the master ADC
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
enum: EOS_MST
|
||||
- name: OVR_MST
|
||||
description: Overrun flag of the master ADC
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: OVR_MST
|
||||
- name: JEOC_MST
|
||||
description: End of injected conversion flag of the master ADC
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: JEOC_MST
|
||||
- name: JEOS_MST
|
||||
description: End of injected sequence flag of the master ADC
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
enum: JEOS_MST
|
||||
- name: AWD1_MST
|
||||
description: Analog watchdog 1 flag of the master ADC
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: AWD2_MST
|
||||
description: Analog watchdog 2 flag of the master ADC
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: AWD3_MST
|
||||
description: Analog watchdog 3 flag of the master ADC
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: JQOVF_MST
|
||||
description: Injected Context Queue Overflow flag of the master ADC
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: JQOVF_MST
|
||||
- name: ADRDY_SLV
|
||||
description: Slave ADC ready
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
enum: ADRDY_MST
|
||||
- name: EOSMP_SLV
|
||||
description: End of Sampling phase flag of the slave ADC
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
enum: EOSMP_MST
|
||||
- name: EOC_SLV
|
||||
description: End of regular conversion of the slave ADC
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
enum: EOC_MST
|
||||
- name: EOS_SLV
|
||||
description: End of regular sequence flag of the slave ADC
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
enum: EOS_MST
|
||||
- name: OVR_SLV
|
||||
description: Overrun flag of the slave ADC
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
enum: OVR_MST
|
||||
- name: JEOC_SLV
|
||||
description: End of injected conversion flag of the slave ADC
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
enum: JEOC_MST
|
||||
- name: JEOS_SLV
|
||||
description: End of injected sequence flag of the slave ADC
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
enum: JEOS_MST
|
||||
- name: AWD1_SLV
|
||||
description: Analog watchdog 1 flag of the slave ADC
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: AWD2_SLV
|
||||
description: Analog watchdog 2 flag of the slave ADC
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: AWD3_SLV
|
||||
description: Analog watchdog 3 flag of the slave ADC
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: JQOVF_SLV
|
||||
description: Injected Context Queue Overflow flag of the slave ADC
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
enum: JQOVF_MST
|
||||
- name: ADRDY_MST
|
||||
description: Master ADC ready
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
enum: ADRDY_MST
|
||||
- name: EOSMP_MST
|
||||
description: End of Sampling phase flag of the master ADC
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
enum: EOSMP_MST
|
||||
- name: EOC_MST
|
||||
description: End of regular conversion of the master ADC
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum: EOC_MST
|
||||
- name: EOS_MST
|
||||
description: End of regular sequence flag of the master ADC
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
enum: EOS_MST
|
||||
- name: OVR_MST
|
||||
description: Overrun flag of the master ADC
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: OVR_MST
|
||||
- name: JEOC_MST
|
||||
description: End of injected conversion flag of the master ADC
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: JEOC_MST
|
||||
- name: JEOS_MST
|
||||
description: End of injected sequence flag of the master ADC
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
enum: JEOS_MST
|
||||
- name: AWD1_MST
|
||||
description: Analog watchdog 1 flag of the master ADC
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: AWD2_MST
|
||||
description: Analog watchdog 2 flag of the master ADC
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: AWD3_MST
|
||||
description: Analog watchdog 3 flag of the master ADC
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: JQOVF_MST
|
||||
description: Injected Context Queue Overflow flag of the master ADC
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: JQOVF_MST
|
||||
- name: ADRDY_SLV
|
||||
description: Slave ADC ready
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
enum: ADRDY_MST
|
||||
- name: EOSMP_SLV
|
||||
description: End of Sampling phase flag of the slave ADC
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
enum: EOSMP_MST
|
||||
- name: EOC_SLV
|
||||
description: End of regular conversion of the slave ADC
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
enum: EOC_MST
|
||||
- name: EOS_SLV
|
||||
description: End of regular sequence flag of the slave ADC
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
enum: EOS_MST
|
||||
- name: OVR_SLV
|
||||
description: Overrun flag of the slave ADC
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
enum: OVR_MST
|
||||
- name: JEOC_SLV
|
||||
description: End of injected conversion flag of the slave ADC
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
enum: JEOC_MST
|
||||
- name: JEOS_SLV
|
||||
description: End of injected sequence flag of the slave ADC
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
enum: JEOS_MST
|
||||
- name: AWD1_SLV
|
||||
description: Analog watchdog 1 flag of the slave ADC
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: AWD2_SLV
|
||||
description: Analog watchdog 2 flag of the slave ADC
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: AWD3_SLV
|
||||
description: Analog watchdog 3 flag of the slave ADC
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: JQOVF_SLV
|
||||
description: Injected Context Queue Overflow flag of the slave ADC
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
enum: JQOVF_MST
|
||||
enum/ADRDY_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotReady
|
||||
description: ADC is not ready to start conversion
|
||||
value: 0
|
||||
- name: Ready
|
||||
description: ADC is ready to start conversion
|
||||
value: 1
|
||||
- name: NotReady
|
||||
description: ADC is not ready to start conversion
|
||||
value: 0
|
||||
- name: Ready
|
||||
description: ADC is ready to start conversion
|
||||
value: 1
|
||||
enum/AWD1_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoEvent
|
||||
description: No analog watchdog event occurred
|
||||
value: 0
|
||||
- name: Event
|
||||
description: Analog watchdog event occurred
|
||||
value: 1
|
||||
- name: NoEvent
|
||||
description: No analog watchdog event occurred
|
||||
value: 0
|
||||
- name: Event
|
||||
description: Analog watchdog event occurred
|
||||
value: 1
|
||||
enum/CKMODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Asynchronous
|
||||
description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
|
||||
value: 0
|
||||
- name: SyncDiv1
|
||||
description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
|
||||
value: 1
|
||||
- name: SyncDiv2
|
||||
description: Use AHB clock rcc_hclk3 divided by 2
|
||||
value: 2
|
||||
- name: SyncDiv4
|
||||
description: Use AHB clock rcc_hclk3 divided by 4
|
||||
value: 3
|
||||
- name: Asynchronous
|
||||
description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
|
||||
value: 0
|
||||
- name: SyncDiv1
|
||||
description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
|
||||
value: 1
|
||||
- name: SyncDiv2
|
||||
description: Use AHB clock rcc_hclk3 divided by 2
|
||||
value: 2
|
||||
- name: SyncDiv4
|
||||
description: Use AHB clock rcc_hclk3 divided by 4
|
||||
value: 3
|
||||
enum/DAMDF:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: NoPack
|
||||
description: "Without data packing, CDR/CDR2 not used"
|
||||
value: 0
|
||||
- name: Format32to10
|
||||
description: CDR formatted for 32-bit down to 10-bit resolution
|
||||
value: 2
|
||||
- name: Format8
|
||||
description: CDR formatted for 8-bit resolution
|
||||
value: 3
|
||||
- name: NoPack
|
||||
description: Without data packing, CDR/CDR2 not used
|
||||
value: 0
|
||||
- name: Format32to10
|
||||
description: CDR formatted for 32-bit down to 10-bit resolution
|
||||
value: 2
|
||||
- name: Format8
|
||||
description: CDR formatted for 8-bit resolution
|
||||
value: 3
|
||||
enum/DUAL:
|
||||
bit_size: 5
|
||||
variants:
|
||||
- name: Independent
|
||||
description: Independent mode
|
||||
value: 0
|
||||
- name: DualRJ
|
||||
description: "Dual, combined regular simultaneous + injected simultaneous mode"
|
||||
value: 1
|
||||
- name: DualRA
|
||||
description: "Dual, combined regular simultaneous + alternate trigger mode"
|
||||
value: 2
|
||||
- name: DualIJ
|
||||
description: "Dual, combined interleaved mode + injected simultaneous mode"
|
||||
value: 3
|
||||
- name: DualJ
|
||||
description: "Dual, injected simultaneous mode only"
|
||||
value: 5
|
||||
- name: DualR
|
||||
description: "Dual, regular simultaneous mode only"
|
||||
value: 6
|
||||
- name: DualI
|
||||
description: "Dual, interleaved mode only"
|
||||
value: 7
|
||||
- name: DualA
|
||||
description: "Dual, alternate trigger mode only"
|
||||
value: 9
|
||||
- name: Independent
|
||||
description: Independent mode
|
||||
value: 0
|
||||
- name: DualRJ
|
||||
description: Dual, combined regular simultaneous + injected simultaneous mode
|
||||
value: 1
|
||||
- name: DualRA
|
||||
description: Dual, combined regular simultaneous + alternate trigger mode
|
||||
value: 2
|
||||
- name: DualIJ
|
||||
description: Dual, combined interleaved mode + injected simultaneous mode
|
||||
value: 3
|
||||
- name: DualJ
|
||||
description: Dual, injected simultaneous mode only
|
||||
value: 5
|
||||
- name: DualR
|
||||
description: Dual, regular simultaneous mode only
|
||||
value: 6
|
||||
- name: DualI
|
||||
description: Dual, interleaved mode only
|
||||
value: 7
|
||||
- name: DualA
|
||||
description: Dual, alternate trigger mode only
|
||||
value: 9
|
||||
enum/EOC_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotComplete
|
||||
description: Regular conversion is not complete
|
||||
value: 0
|
||||
- name: Complete
|
||||
description: Regular conversion complete
|
||||
value: 1
|
||||
- name: NotComplete
|
||||
description: Regular conversion is not complete
|
||||
value: 0
|
||||
- name: Complete
|
||||
description: Regular conversion complete
|
||||
value: 1
|
||||
enum/EOSMP_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotEnded
|
||||
description: End of sampling phase no yet reached
|
||||
value: 0
|
||||
- name: Ended
|
||||
description: End of sampling phase reached
|
||||
value: 1
|
||||
- name: NotEnded
|
||||
description: End of sampling phase no yet reached
|
||||
value: 0
|
||||
- name: Ended
|
||||
description: End of sampling phase reached
|
||||
value: 1
|
||||
enum/EOS_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotComplete
|
||||
description: Regular sequence is not complete
|
||||
value: 0
|
||||
- name: Complete
|
||||
description: Regular sequence complete
|
||||
value: 1
|
||||
- name: NotComplete
|
||||
description: Regular sequence is not complete
|
||||
value: 0
|
||||
- name: Complete
|
||||
description: Regular sequence complete
|
||||
value: 1
|
||||
enum/JEOC_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotComplete
|
||||
description: Injected conversion is not complete
|
||||
value: 0
|
||||
- name: Complete
|
||||
description: Injected conversion complete
|
||||
value: 1
|
||||
- name: NotComplete
|
||||
description: Injected conversion is not complete
|
||||
value: 0
|
||||
- name: Complete
|
||||
description: Injected conversion complete
|
||||
value: 1
|
||||
enum/JEOS_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotComplete
|
||||
description: Injected sequence is not complete
|
||||
value: 0
|
||||
- name: Complete
|
||||
description: Injected sequence complete
|
||||
value: 1
|
||||
- name: NotComplete
|
||||
description: Injected sequence is not complete
|
||||
value: 0
|
||||
- name: Complete
|
||||
description: Injected sequence complete
|
||||
value: 1
|
||||
enum/JQOVF_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoOverflow
|
||||
description: No injected context queue overflow has occurred
|
||||
value: 0
|
||||
- name: Overflow
|
||||
description: Injected context queue overflow has occurred
|
||||
value: 1
|
||||
- name: NoOverflow
|
||||
description: No injected context queue overflow has occurred
|
||||
value: 0
|
||||
- name: Overflow
|
||||
description: Injected context queue overflow has occurred
|
||||
value: 1
|
||||
enum/OVR_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoOverrun
|
||||
description: No overrun occurred
|
||||
value: 0
|
||||
- name: Overrun
|
||||
description: Overrun occurred
|
||||
value: 1
|
||||
- name: NoOverrun
|
||||
description: No overrun occurred
|
||||
value: 0
|
||||
- name: Overrun
|
||||
description: Overrun occurred
|
||||
value: 1
|
||||
enum/PRESC:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Div1
|
||||
description: adc_ker_ck_input not divided
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: adc_ker_ck_input divided by 2
|
||||
value: 1
|
||||
- name: Div4
|
||||
description: adc_ker_ck_input divided by 4
|
||||
value: 2
|
||||
- name: Div6
|
||||
description: adc_ker_ck_input divided by 6
|
||||
value: 3
|
||||
- name: Div8
|
||||
description: adc_ker_ck_input divided by 8
|
||||
value: 4
|
||||
- name: Div10
|
||||
description: adc_ker_ck_input divided by 10
|
||||
value: 5
|
||||
- name: Div12
|
||||
description: adc_ker_ck_input divided by 12
|
||||
value: 6
|
||||
- name: Div16
|
||||
description: adc_ker_ck_input divided by 16
|
||||
value: 7
|
||||
- name: Div32
|
||||
description: adc_ker_ck_input divided by 32
|
||||
value: 8
|
||||
- name: Div64
|
||||
description: adc_ker_ck_input divided by 64
|
||||
value: 9
|
||||
- name: Div128
|
||||
description: adc_ker_ck_input divided by 128
|
||||
value: 10
|
||||
- name: Div256
|
||||
description: adc_ker_ck_input divided by 256
|
||||
value: 11
|
||||
- name: Div1
|
||||
description: adc_ker_ck_input not divided
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: adc_ker_ck_input divided by 2
|
||||
value: 1
|
||||
- name: Div4
|
||||
description: adc_ker_ck_input divided by 4
|
||||
value: 2
|
||||
- name: Div6
|
||||
description: adc_ker_ck_input divided by 6
|
||||
value: 3
|
||||
- name: Div8
|
||||
description: adc_ker_ck_input divided by 8
|
||||
value: 4
|
||||
- name: Div10
|
||||
description: adc_ker_ck_input divided by 10
|
||||
value: 5
|
||||
- name: Div12
|
||||
description: adc_ker_ck_input divided by 12
|
||||
value: 6
|
||||
- name: Div16
|
||||
description: adc_ker_ck_input divided by 16
|
||||
value: 7
|
||||
- name: Div32
|
||||
description: adc_ker_ck_input divided by 32
|
||||
value: 8
|
||||
- name: Div64
|
||||
description: adc_ker_ck_input divided by 64
|
||||
value: 9
|
||||
- name: Div128
|
||||
description: adc_ker_ck_input divided by 128
|
||||
value: 10
|
||||
- name: Div256
|
||||
description: adc_ker_ck_input divided by 256
|
||||
value: 11
|
||||
|
||||
204
data/registers/aes_f7.yaml
Normal file
204
data/registers/aes_f7.yaml
Normal file
@ -0,0 +1,204 @@
|
||||
block/AES:
|
||||
description: Advanced encryption standard hardware accelerator
|
||||
items:
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 4
|
||||
fieldset: SR
|
||||
- name: DINR
|
||||
description: Data input register
|
||||
byte_offset: 8
|
||||
fieldset: DINR
|
||||
- name: DOUTR
|
||||
description: Data output register
|
||||
byte_offset: 12
|
||||
fieldset: DOUTR
|
||||
- name: KEYR
|
||||
description: Key register
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 4
|
||||
- 8
|
||||
- 12
|
||||
- 32
|
||||
- 36
|
||||
- 40
|
||||
- 44
|
||||
byte_offset: 16
|
||||
fieldset: KEYR
|
||||
- name: IVR
|
||||
description: Initialization vector register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 32
|
||||
fieldset: IVR
|
||||
- name: SUSPR
|
||||
description: Suspend register
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
byte_offset: 64
|
||||
fieldset: SUSPR
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: AES enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DATATYPE
|
||||
description: Data type selection
|
||||
bit_offset: 1
|
||||
bit_size: 2
|
||||
enum: DATATYPE
|
||||
- name: MODE
|
||||
description: Operating mode
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
enum: MODE
|
||||
- name: CHMOD10
|
||||
description: Chaining mode bit1 bit0
|
||||
bit_offset: 5
|
||||
bit_size: 2
|
||||
- name: CCFC
|
||||
description: Computation Complete Flag Clear
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: ERRC
|
||||
description: Error clear
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: CCFIE
|
||||
description: CCF flag interrupt enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DMAINEN
|
||||
description: Enable DMA management of data input phase
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DMAOUTEN
|
||||
description: Enable DMA management of data output phase
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: GCMPH
|
||||
description: GCM or CCM phase selection
|
||||
bit_offset: 13
|
||||
bit_size: 2
|
||||
enum: GCMPH
|
||||
- name: CHMOD2
|
||||
description: Chaining mode bit2
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: KEYSIZE
|
||||
description: Key size selection
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/DINR:
|
||||
description: Data input register
|
||||
fields:
|
||||
- name: DIN
|
||||
description: Input data word
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/DOUTR:
|
||||
description: Data output register
|
||||
fields:
|
||||
- name: DOUT
|
||||
description: Output data word
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/IVR:
|
||||
description: Initialization vector register
|
||||
fields:
|
||||
- name: IVI
|
||||
description: Initialization vector input
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/KEYR:
|
||||
description: Key register
|
||||
fields:
|
||||
- name: KEY
|
||||
description: Cryptographic key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: CCF
|
||||
description: Computation complete flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: Read error flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WRERR
|
||||
description: Write error flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: BUSY
|
||||
description: Busy flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
fieldset/SUSPR:
|
||||
description: Suspend register
|
||||
fields:
|
||||
- name: SUSP
|
||||
description: AES suspend
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
enum/DATATYPE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: None
|
||||
description: Word
|
||||
value: 0
|
||||
- name: HalfWord
|
||||
description: Half-word (16-bit)
|
||||
value: 1
|
||||
- name: Byte
|
||||
description: Byte (8-bit)
|
||||
value: 2
|
||||
- name: Bit
|
||||
description: Bit
|
||||
value: 3
|
||||
enum/GCMPH:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Init phase
|
||||
description: Init phase
|
||||
value: 0
|
||||
- name: Header phase
|
||||
description: Header phase
|
||||
value: 1
|
||||
- name: Payload phase
|
||||
description: Payload phase
|
||||
value: 2
|
||||
- name: Final phase
|
||||
description: Final phase
|
||||
value: 3
|
||||
enum/MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Mode1
|
||||
description: Encryption
|
||||
value: 0
|
||||
- name: Mode2
|
||||
description: Key derivation (or key preparation for ECB/CBC decryption)
|
||||
value: 1
|
||||
- name: Mode3
|
||||
description: Decryption
|
||||
value: 2
|
||||
- name: Mode4
|
||||
description: Key derivation then single decryption
|
||||
value: 3
|
||||
258
data/registers/aes_u5.yaml
Normal file
258
data/registers/aes_u5.yaml
Normal file
@ -0,0 +1,258 @@
|
||||
block/AES:
|
||||
description: Advanced encryption standard hardware accelerator
|
||||
items:
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 4
|
||||
fieldset: SR
|
||||
- name: DINR
|
||||
description: Data input register
|
||||
byte_offset: 8
|
||||
fieldset: DINR
|
||||
- name: DOUTR
|
||||
description: Data output register
|
||||
byte_offset: 12
|
||||
fieldset: DOUTR
|
||||
- name: KEYR
|
||||
description: Key register
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 4
|
||||
- 8
|
||||
- 12
|
||||
- 32
|
||||
- 36
|
||||
- 40
|
||||
- 44
|
||||
byte_offset: 16
|
||||
fieldset: KEYR
|
||||
- name: IVR
|
||||
description: Initialization vector register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 32
|
||||
fieldset: IVR
|
||||
- name: SUSPR
|
||||
description: Suspend register
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
byte_offset: 64
|
||||
fieldset: SUSPR
|
||||
- name: IER
|
||||
description: interrupt enable register
|
||||
byte_offset: 768
|
||||
fieldset: IER
|
||||
- name: ISR
|
||||
description: interrupt status register
|
||||
byte_offset: 772
|
||||
fieldset: ISR
|
||||
- name: ICR
|
||||
description: interrupt clear register
|
||||
byte_offset: 776
|
||||
fieldset: ICR
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: AES enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DATATYPE
|
||||
description: Data type selection
|
||||
bit_offset: 1
|
||||
bit_size: 2
|
||||
enum: DATATYPE
|
||||
- name: MODE
|
||||
description: Operating mode
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
enum: MODE
|
||||
- name: CHMOD10
|
||||
description: Chaining mode bit1 bit0
|
||||
bit_offset: 5
|
||||
bit_size: 2
|
||||
- name: DMAINEN
|
||||
description: Enable DMA management of data input phase
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DMAOUTEN
|
||||
description: Enable DMA management of data output phase
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: GCMPH
|
||||
description: GCM or CCM phase selection
|
||||
bit_offset: 13
|
||||
bit_size: 2
|
||||
enum: GCMPH
|
||||
- name: CHMOD2
|
||||
description: Chaining mode bit2
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: KEYSIZE
|
||||
description: Key size selection
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: NPBLB
|
||||
description: Number of padding bytes in last block of payload
|
||||
bit_offset: 20
|
||||
bit_size: 4
|
||||
- name: KMOD
|
||||
description: Key mode selection
|
||||
bit_offset: 24
|
||||
bit_size: 2
|
||||
- name: IPRST
|
||||
description: AES peripheral software reset
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/DINR:
|
||||
description: Data input register
|
||||
fields:
|
||||
- name: DIN
|
||||
description: Input data word
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/DOUTR:
|
||||
description: Data output register
|
||||
fields:
|
||||
- name: DOUT
|
||||
description: Output data word
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/ICR:
|
||||
description: Interrupt clear register
|
||||
fields:
|
||||
- name: CCF
|
||||
description: Computation complete flag clear
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RWEIF
|
||||
description: Read or write error interrupt flag clear
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: KEIF
|
||||
description: Key error interrupt flag clear
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
fieldset/IER:
|
||||
description: Interrupt enable register
|
||||
fields:
|
||||
- name: CCFIE
|
||||
description: Computation complete flag interrupt enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RWEIE
|
||||
description: Read or write error interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: KEIE
|
||||
description: Key error interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
fieldset/ISR:
|
||||
description: Interrupt status register
|
||||
fields:
|
||||
- name: CCF
|
||||
description: Computation complete flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RWEIF
|
||||
description: Read or write error interrupt flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: KEIF
|
||||
description: Key error interrupt flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
fieldset/IVR:
|
||||
description: Initialization vector register
|
||||
fields:
|
||||
- name: IVI
|
||||
description: Initialization vector input
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/KEYR:
|
||||
description: Key register
|
||||
fields:
|
||||
- name: KEY
|
||||
description: Cryptographic key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: CCF
|
||||
description: Computation complete flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: Read error flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WRERR
|
||||
description: Write error flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: BUSY
|
||||
description: Busy flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: KEYVALID
|
||||
description: Key valid flag
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
fieldset/SUSPR:
|
||||
description: Suspend register
|
||||
fields:
|
||||
- name: SUSP
|
||||
description: AES suspend
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
enum/DATATYPE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: None
|
||||
description: Word
|
||||
value: 0
|
||||
- name: HalfWord
|
||||
description: Half-word (16-bit)
|
||||
value: 1
|
||||
- name: Byte
|
||||
description: Byte (8-bit)
|
||||
value: 2
|
||||
- name: Bit
|
||||
description: Bit
|
||||
value: 3
|
||||
enum/GCMPH:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Init phase
|
||||
description: Init phase
|
||||
value: 0
|
||||
- name: Header phase
|
||||
description: Header phase
|
||||
value: 1
|
||||
- name: Payload phase
|
||||
description: Payload phase
|
||||
value: 2
|
||||
- name: Final phase
|
||||
description: Final phase
|
||||
value: 3
|
||||
enum/MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Mode1
|
||||
description: Encryption
|
||||
value: 0
|
||||
- name: Mode2
|
||||
description: Key derivation (or key preparation for ECB/CBC decryption)
|
||||
value: 1
|
||||
- name: Mode3
|
||||
description: Decryption
|
||||
value: 2
|
||||
151
data/registers/aes_v1.yaml
Normal file
151
data/registers/aes_v1.yaml
Normal file
@ -0,0 +1,151 @@
|
||||
block/AES:
|
||||
description: Advanced encryption standard hardware accelerator
|
||||
items:
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 4
|
||||
fieldset: SR
|
||||
- name: DINR
|
||||
description: Data input register
|
||||
byte_offset: 8
|
||||
fieldset: DINR
|
||||
- name: DOUTR
|
||||
description: Data output register
|
||||
byte_offset: 12
|
||||
fieldset: DOUTR
|
||||
- name: KEYR
|
||||
description: Key register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 16
|
||||
fieldset: KEYR
|
||||
- name: IVR
|
||||
description: Initialization vector register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 32
|
||||
fieldset: IVR
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: AES enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DATATYPE
|
||||
description: Data type selection
|
||||
bit_offset: 1
|
||||
bit_size: 2
|
||||
enum: DATATYPE
|
||||
- name: MODE
|
||||
description: Operating mode
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
enum: MODE
|
||||
- name: CHMOD10
|
||||
description: Chaining mode bit1 bit0
|
||||
bit_offset: 5
|
||||
bit_size: 2
|
||||
- name: CCFC
|
||||
description: Computation Complete Flag Clear
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: ERRC
|
||||
description: Error clear
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: CCFIE
|
||||
description: CCF flag interrupt enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DMAINEN
|
||||
description: Enable DMA management of data input phase
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DMAOUTEN
|
||||
description: Enable DMA management of data output phase
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
fieldset/DINR:
|
||||
description: Data input register
|
||||
fields:
|
||||
- name: DIN
|
||||
description: Input data word
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/DOUTR:
|
||||
description: Data output register
|
||||
fields:
|
||||
- name: DOUT
|
||||
description: Output data word
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/IVR:
|
||||
description: Initialization vector register
|
||||
fields:
|
||||
- name: IVI
|
||||
description: Initialization vector input
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/KEYR:
|
||||
description: Key register
|
||||
fields:
|
||||
- name: KEY
|
||||
description: Cryptographic key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: CCF
|
||||
description: Computation complete flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: Read error flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WRERR
|
||||
description: Write error flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum/DATATYPE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: None
|
||||
description: Word
|
||||
value: 0
|
||||
- name: HalfWord
|
||||
description: Half-word (16-bit)
|
||||
value: 1
|
||||
- name: Byte
|
||||
description: Byte (8-bit)
|
||||
value: 2
|
||||
- name: Bit
|
||||
description: Bit
|
||||
value: 3
|
||||
enum/MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Mode1
|
||||
description: Encryption
|
||||
value: 0
|
||||
- name: Mode2
|
||||
description: Key derivation (or key preparation for ECB/CBC decryption)
|
||||
value: 1
|
||||
- name: Mode3
|
||||
description: Decryption
|
||||
value: 2
|
||||
- name: Mode4
|
||||
description: Key derivation then single decryption
|
||||
value: 3
|
||||
208
data/registers/aes_v2.yaml
Normal file
208
data/registers/aes_v2.yaml
Normal file
@ -0,0 +1,208 @@
|
||||
block/AES:
|
||||
description: Advanced encryption standard hardware accelerator
|
||||
items:
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 4
|
||||
fieldset: SR
|
||||
- name: DINR
|
||||
description: Data input register
|
||||
byte_offset: 8
|
||||
fieldset: DINR
|
||||
- name: DOUTR
|
||||
description: Data output register
|
||||
byte_offset: 12
|
||||
fieldset: DOUTR
|
||||
- name: KEYR
|
||||
description: Key register
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 4
|
||||
- 8
|
||||
- 12
|
||||
- 32
|
||||
- 36
|
||||
- 40
|
||||
- 44
|
||||
byte_offset: 16
|
||||
fieldset: KEYR
|
||||
- name: IVR
|
||||
description: Initialization vector register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 32
|
||||
fieldset: IVR
|
||||
- name: SUSPR
|
||||
description: Suspend register
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
byte_offset: 64
|
||||
fieldset: SUSPR
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: AES enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DATATYPE
|
||||
description: Data type selection
|
||||
bit_offset: 1
|
||||
bit_size: 2
|
||||
enum: DATATYPE
|
||||
- name: MODE
|
||||
description: Operating mode
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
enum: MODE
|
||||
- name: CHMOD10
|
||||
description: Chaining mode bit1 bit0
|
||||
bit_offset: 5
|
||||
bit_size: 2
|
||||
- name: CCFC
|
||||
description: Computation Complete Flag Clear
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: ERRC
|
||||
description: Error clear
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: CCFIE
|
||||
description: CCF flag interrupt enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DMAINEN
|
||||
description: Enable DMA management of data input phase
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DMAOUTEN
|
||||
description: Enable DMA management of data output phase
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: GCMPH
|
||||
description: GCM or CCM phase selection
|
||||
bit_offset: 13
|
||||
bit_size: 2
|
||||
enum: GCMPH
|
||||
- name: CHMOD2
|
||||
description: Chaining mode bit2
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: KEYSIZE
|
||||
description: Key size selection
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: NPBLB
|
||||
description: Number of padding bytes in last block of payload
|
||||
bit_offset: 20
|
||||
bit_size: 4
|
||||
fieldset/DINR:
|
||||
description: Data input register
|
||||
fields:
|
||||
- name: DIN
|
||||
description: Input data word
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/DOUTR:
|
||||
description: Data output register
|
||||
fields:
|
||||
- name: DOUT
|
||||
description: Output data word
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/IVR:
|
||||
description: Initialization vector register
|
||||
fields:
|
||||
- name: IVI
|
||||
description: Initialization vector input
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/KEYR:
|
||||
description: Key register
|
||||
fields:
|
||||
- name: KEY
|
||||
description: Cryptographic key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: CCF
|
||||
description: Computation complete flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: Read error flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WRERR
|
||||
description: Write error flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: BUSY
|
||||
description: Busy flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
fieldset/SUSPR:
|
||||
description: Suspend register
|
||||
fields:
|
||||
- name: SUSP
|
||||
description: AES suspend
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
enum/DATATYPE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: None
|
||||
description: Word
|
||||
value: 0
|
||||
- name: HalfWord
|
||||
description: Half-word (16-bit)
|
||||
value: 1
|
||||
- name: Byte
|
||||
description: Byte (8-bit)
|
||||
value: 2
|
||||
- name: Bit
|
||||
description: Bit
|
||||
value: 3
|
||||
enum/GCMPH:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Init phase
|
||||
description: Init phase
|
||||
value: 0
|
||||
- name: Header phase
|
||||
description: Header phase
|
||||
value: 1
|
||||
- name: Payload phase
|
||||
description: Payload phase
|
||||
value: 2
|
||||
- name: Final phase
|
||||
description: Final phase
|
||||
value: 3
|
||||
enum/MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Mode1
|
||||
description: Encryption
|
||||
value: 0
|
||||
- name: Mode2
|
||||
description: Key derivation (or key preparation for ECB/CBC decryption)
|
||||
value: 1
|
||||
- name: Mode3
|
||||
description: Decryption
|
||||
value: 2
|
||||
- name: Mode4
|
||||
description: Key derivation then single decryption
|
||||
value: 3
|
||||
@ -1,202 +1,201 @@
|
||||
---
|
||||
block/AFIO:
|
||||
description: Alternate function I/O
|
||||
items:
|
||||
- name: EVCR
|
||||
description: Event Control Register (AFIO_EVCR)
|
||||
byte_offset: 0
|
||||
fieldset: EVCR
|
||||
- name: MAPR
|
||||
description: AF remap and debug I/O configuration register (AFIO_MAPR)
|
||||
byte_offset: 4
|
||||
fieldset: MAPR
|
||||
- name: EXTICR
|
||||
description: External interrupt configuration register 1 (AFIO_EXTICR1)
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 8
|
||||
fieldset: EXTICR
|
||||
- name: MAPR2
|
||||
description: AF remap and debug I/O configuration register
|
||||
byte_offset: 28
|
||||
fieldset: MAPR2
|
||||
- name: EVCR
|
||||
description: Event Control Register (AFIO_EVCR)
|
||||
byte_offset: 0
|
||||
fieldset: EVCR
|
||||
- name: MAPR
|
||||
description: AF remap and debug I/O configuration register (AFIO_MAPR)
|
||||
byte_offset: 4
|
||||
fieldset: MAPR
|
||||
- name: EXTICR
|
||||
description: External interrupt configuration register 1 (AFIO_EXTICR1)
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 8
|
||||
fieldset: EXTICR
|
||||
- name: MAPR2
|
||||
description: AF remap and debug I/O configuration register
|
||||
byte_offset: 28
|
||||
fieldset: MAPR2
|
||||
fieldset/EVCR:
|
||||
description: Event Control Register (AFIO_EVCR)
|
||||
fields:
|
||||
- name: PIN
|
||||
description: Pin selection
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: PORT
|
||||
description: Port selection
|
||||
bit_offset: 4
|
||||
bit_size: 3
|
||||
- name: EVOE
|
||||
description: Event Output Enable
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: PIN
|
||||
description: Pin selection
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: PORT
|
||||
description: Port selection
|
||||
bit_offset: 4
|
||||
bit_size: 3
|
||||
- name: EVOE
|
||||
description: Event Output Enable
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
fieldset/EXTICR:
|
||||
description: External interrupt configuration register 3 (AFIO_EXTICR3)
|
||||
fields:
|
||||
- name: EXTI
|
||||
description: EXTI12 configuration
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
- name: EXTI
|
||||
description: EXTI12 configuration
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
fieldset/MAPR:
|
||||
description: AF remap and debug I/O configuration register (AFIO_MAPR)
|
||||
fields:
|
||||
- name: SPI1_REMAP
|
||||
description: SPI1 remapping
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: I2C1_REMAP
|
||||
description: I2C1 remapping
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: USART1_REMAP
|
||||
description: USART1 remapping
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: USART2_REMAP
|
||||
description: USART2 remapping
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: USART3_REMAP
|
||||
description: USART3 remapping
|
||||
bit_offset: 4
|
||||
bit_size: 2
|
||||
- name: TIM1_REMAP
|
||||
description: TIM1 remapping
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
- name: TIM2_REMAP
|
||||
description: TIM2 remapping
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
- name: TIM3_REMAP
|
||||
description: TIM3 remapping
|
||||
bit_offset: 10
|
||||
bit_size: 2
|
||||
- name: TIM4_REMAP
|
||||
description: TIM4 remapping
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: CAN1_REMAP
|
||||
description: CAN1 remapping
|
||||
bit_offset: 13
|
||||
bit_size: 2
|
||||
- name: PD01_REMAP
|
||||
description: Port D0/Port D1 mapping on OSCIN/OSCOUT
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: TIM5CH4_IREMAP
|
||||
description: Set and cleared by software
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: ADC1_ETRGINJ_REMAP
|
||||
description: ADC 1 External trigger injected conversion remapping
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: ADC1_ETRGREG_REMAP
|
||||
description: ADC 1 external trigger regular conversion remapping
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: ADC2_ETRGINJ_REMAP
|
||||
description: ADC 2 external trigger injected conversion remapping
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: ADC2_ETRGREG_REMAP
|
||||
description: ADC 2 external trigger regular conversion remapping
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: ETH_REMAP
|
||||
description: Ethernet MAC I/O remapping
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: CAN2_REMAP
|
||||
description: CAN2 I/O remapping
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: MII_RMII_SEL
|
||||
description: MII or RMII selection
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: SWJ_CFG
|
||||
description: Serial wire JTAG configuration
|
||||
bit_offset: 24
|
||||
bit_size: 3
|
||||
- name: SPI3_REMAP
|
||||
description: SPI3/I2S3 remapping
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: TIM2ITR1_IREMAP
|
||||
description: TIM2 internal trigger 1 remapping
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: PTP_PPS_REMAP
|
||||
description: Ethernet PTP PPS remapping
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: SPI1_REMAP
|
||||
description: SPI1 remapping
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: I2C1_REMAP
|
||||
description: I2C1 remapping
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: USART1_REMAP
|
||||
description: USART1 remapping
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: USART2_REMAP
|
||||
description: USART2 remapping
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: USART3_REMAP
|
||||
description: USART3 remapping
|
||||
bit_offset: 4
|
||||
bit_size: 2
|
||||
- name: TIM1_REMAP
|
||||
description: TIM1 remapping
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
- name: TIM2_REMAP
|
||||
description: TIM2 remapping
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
- name: TIM3_REMAP
|
||||
description: TIM3 remapping
|
||||
bit_offset: 10
|
||||
bit_size: 2
|
||||
- name: TIM4_REMAP
|
||||
description: TIM4 remapping
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: CAN1_REMAP
|
||||
description: CAN1 remapping
|
||||
bit_offset: 13
|
||||
bit_size: 2
|
||||
- name: PD01_REMAP
|
||||
description: Port D0/Port D1 mapping on OSCIN/OSCOUT
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: TIM5CH4_IREMAP
|
||||
description: Set and cleared by software
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: ADC1_ETRGINJ_REMAP
|
||||
description: ADC 1 External trigger injected conversion remapping
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: ADC1_ETRGREG_REMAP
|
||||
description: ADC 1 external trigger regular conversion remapping
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: ADC2_ETRGINJ_REMAP
|
||||
description: ADC 2 external trigger injected conversion remapping
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: ADC2_ETRGREG_REMAP
|
||||
description: ADC 2 external trigger regular conversion remapping
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: ETH_REMAP
|
||||
description: Ethernet MAC I/O remapping
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: CAN2_REMAP
|
||||
description: CAN2 I/O remapping
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: MII_RMII_SEL
|
||||
description: MII or RMII selection
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: SWJ_CFG
|
||||
description: Serial wire JTAG configuration
|
||||
bit_offset: 24
|
||||
bit_size: 3
|
||||
- name: SPI3_REMAP
|
||||
description: SPI3/I2S3 remapping
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: TIM2ITR1_IREMAP
|
||||
description: TIM2 internal trigger 1 remapping
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: PTP_PPS_REMAP
|
||||
description: Ethernet PTP PPS remapping
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
fieldset/MAPR2:
|
||||
description: AF remap and debug I/O configuration register
|
||||
fields:
|
||||
- name: TIM15_REMAP
|
||||
description: TIM15 remapping
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM16_REMAP
|
||||
description: TIM16 remapping
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM17_REMAP
|
||||
description: TIM17 remapping
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: CEC_REMAP
|
||||
description: CEC remapping
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM1_DMA_REMAP
|
||||
description: TIM1 DMA remapping
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM9_REMAP
|
||||
description: TIM9 remapping
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM10_REMAP
|
||||
description: TIM10 remapping
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM11_REMAP
|
||||
description: TIM11 remapping
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM13_REMAP
|
||||
description: TIM13 remapping
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: TIM14_REMAP
|
||||
description: TIM14 remapping
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: FSMC_NADV
|
||||
description: NADV connect/disconnect
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: TIM67_DAC_DMA_REMAP
|
||||
description: TIM67_DAC DMA remapping
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM12_REMAP
|
||||
description: TIM12 remapping
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: MISC_REMAP
|
||||
description: Miscellaneous features remapping
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: TIM15_REMAP
|
||||
description: TIM15 remapping
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM16_REMAP
|
||||
description: TIM16 remapping
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM17_REMAP
|
||||
description: TIM17 remapping
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: CEC_REMAP
|
||||
description: CEC remapping
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM1_DMA_REMAP
|
||||
description: TIM1 DMA remapping
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM9_REMAP
|
||||
description: TIM9 remapping
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM10_REMAP
|
||||
description: TIM10 remapping
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM11_REMAP
|
||||
description: TIM11 remapping
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM13_REMAP
|
||||
description: TIM13 remapping
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: TIM14_REMAP
|
||||
description: TIM14 remapping
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: FSMC_NADV
|
||||
description: NADV connect/disconnect
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: TIM67_DAC_DMA_REMAP
|
||||
description: TIM67_DAC DMA remapping
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM12_REMAP
|
||||
description: TIM12 remapping
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: MISC_REMAP
|
||||
description: Miscellaneous features remapping
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
|
||||
@ -1,198 +1,197 @@
|
||||
---
|
||||
block/CH:
|
||||
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
|
||||
description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
|
||||
items:
|
||||
- name: CR
|
||||
description: DMA channel configuration register (DMA_CCR)
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: NDTR
|
||||
description: DMA channel 1 number of data register
|
||||
byte_offset: 4
|
||||
fieldset: NDTR
|
||||
- name: PAR
|
||||
description: DMA channel 1 peripheral address register
|
||||
byte_offset: 8
|
||||
- name: MAR
|
||||
description: DMA channel 1 memory address register
|
||||
byte_offset: 12
|
||||
- name: CR
|
||||
description: DMA channel configuration register (DMA_CCR)
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: NDTR
|
||||
description: DMA channel 1 number of data register
|
||||
byte_offset: 4
|
||||
fieldset: NDTR
|
||||
- name: PAR
|
||||
description: DMA channel 1 peripheral address register
|
||||
byte_offset: 8
|
||||
- name: MAR
|
||||
description: DMA channel 1 memory address register
|
||||
byte_offset: 12
|
||||
block/DMA:
|
||||
description: DMA controller
|
||||
items:
|
||||
- name: ISR
|
||||
description: DMA interrupt status register (DMA_ISR)
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: ISR
|
||||
- name: IFCR
|
||||
description: DMA interrupt flag clear register (DMA_IFCR)
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: ISR
|
||||
- name: CH
|
||||
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
|
||||
array:
|
||||
len: 8
|
||||
stride: 20
|
||||
byte_offset: 8
|
||||
block: CH
|
||||
- name: ISR
|
||||
description: DMA interrupt status register (DMA_ISR)
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: ISR
|
||||
- name: IFCR
|
||||
description: DMA interrupt flag clear register (DMA_IFCR)
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: ISR
|
||||
- name: CH
|
||||
description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
|
||||
array:
|
||||
len: 8
|
||||
stride: 20
|
||||
byte_offset: 8
|
||||
block: CH
|
||||
fieldset/CR:
|
||||
description: DMA channel configuration register (DMA_CCR)
|
||||
fields:
|
||||
- name: EN
|
||||
description: Channel enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TCIE
|
||||
description: Transfer complete interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: HTIE
|
||||
description: Half Transfer interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TEIE
|
||||
description: Transfer error interrupt enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DIR
|
||||
description: Data transfer direction
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: DIR
|
||||
- name: CIRC
|
||||
description: Circular mode
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: CIRC
|
||||
- name: PINC
|
||||
description: Peripheral increment mode
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: MINC
|
||||
description: Memory increment mode
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: PSIZE
|
||||
description: Peripheral size
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
enum: SIZE
|
||||
- name: MSIZE
|
||||
description: Memory size
|
||||
bit_offset: 10
|
||||
bit_size: 2
|
||||
enum: SIZE
|
||||
- name: PL
|
||||
description: Channel Priority level
|
||||
bit_offset: 12
|
||||
bit_size: 2
|
||||
enum: PL
|
||||
- name: MEM2MEM
|
||||
description: Memory to memory mode
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
enum: MEMMEM
|
||||
- name: EN
|
||||
description: Channel enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TCIE
|
||||
description: Transfer complete interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: HTIE
|
||||
description: Half Transfer interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TEIE
|
||||
description: Transfer error interrupt enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DIR
|
||||
description: Data transfer direction
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: DIR
|
||||
- name: CIRC
|
||||
description: Circular mode
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: CIRC
|
||||
- name: PINC
|
||||
description: Peripheral increment mode
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: MINC
|
||||
description: Memory increment mode
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: PSIZE
|
||||
description: Peripheral size
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
enum: SIZE
|
||||
- name: MSIZE
|
||||
description: Memory size
|
||||
bit_offset: 10
|
||||
bit_size: 2
|
||||
enum: SIZE
|
||||
- name: PL
|
||||
description: Channel Priority level
|
||||
bit_offset: 12
|
||||
bit_size: 2
|
||||
enum: PL
|
||||
- name: MEM2MEM
|
||||
description: Memory to memory mode
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
enum: MEMMEM
|
||||
fieldset/ISR:
|
||||
description: DMA interrupt status register (DMA_ISR)
|
||||
fields:
|
||||
- name: GIF
|
||||
description: Channel 1 Global interrupt flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
- name: TCIF
|
||||
description: Channel 1 Transfer Complete flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
- name: HTIF
|
||||
description: Channel 1 Half Transfer Complete flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
- name: TEIF
|
||||
description: Channel 1 Transfer Error flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
- name: GIF
|
||||
description: Channel 1 Global interrupt flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
- name: TCIF
|
||||
description: Channel 1 Transfer Complete flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
- name: HTIF
|
||||
description: Channel 1 Half Transfer Complete flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
- name: TEIF
|
||||
description: Channel 1 Transfer Error flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
fieldset/NDTR:
|
||||
description: DMA channel 1 number of data register
|
||||
fields:
|
||||
- name: NDT
|
||||
description: Number of data to transfer
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: NDT
|
||||
description: Number of data to transfer
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
enum/CIRC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Circular buffer disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Circular buffer enabled
|
||||
value: 1
|
||||
- name: Disabled
|
||||
description: Circular buffer disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Circular buffer enabled
|
||||
value: 1
|
||||
enum/DIR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: FromPeripheral
|
||||
description: Read from peripheral
|
||||
value: 0
|
||||
- name: FromMemory
|
||||
description: Read from memory
|
||||
value: 1
|
||||
- name: FromPeripheral
|
||||
description: Read from peripheral
|
||||
value: 0
|
||||
- name: FromMemory
|
||||
description: Read from memory
|
||||
value: 1
|
||||
enum/INC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Increment mode disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Increment mode enabled
|
||||
value: 1
|
||||
- name: Disabled
|
||||
description: Increment mode disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Increment mode enabled
|
||||
value: 1
|
||||
enum/MEMMEM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Memory to memory mode disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Memory to memory mode enabled
|
||||
value: 1
|
||||
- name: Disabled
|
||||
description: Memory to memory mode disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Memory to memory mode enabled
|
||||
value: 1
|
||||
enum/PL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Low
|
||||
description: Low priority
|
||||
value: 0
|
||||
- name: Medium
|
||||
description: Medium priority
|
||||
value: 1
|
||||
- name: High
|
||||
description: High priority
|
||||
value: 2
|
||||
- name: VeryHigh
|
||||
description: Very high priority
|
||||
value: 3
|
||||
- name: Low
|
||||
description: Low priority
|
||||
value: 0
|
||||
- name: Medium
|
||||
description: Medium priority
|
||||
value: 1
|
||||
- name: High
|
||||
description: High priority
|
||||
value: 2
|
||||
- name: VeryHigh
|
||||
description: Very high priority
|
||||
value: 3
|
||||
enum/SIZE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Bits8
|
||||
description: 8-bit size
|
||||
value: 0
|
||||
- name: Bits16
|
||||
description: 16-bit size
|
||||
value: 1
|
||||
- name: Bits32
|
||||
description: 32-bit size
|
||||
value: 2
|
||||
- name: Bits8
|
||||
description: 8-bit size
|
||||
value: 0
|
||||
- name: Bits16
|
||||
description: 16-bit size
|
||||
value: 1
|
||||
- name: Bits32
|
||||
description: 32-bit size
|
||||
value: 2
|
||||
|
||||
@ -1,212 +1,211 @@
|
||||
---
|
||||
block/CH:
|
||||
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
|
||||
description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
|
||||
items:
|
||||
- name: CR
|
||||
description: DMA channel configuration register (DMA_CCR)
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: NDTR
|
||||
description: DMA channel 1 number of data register
|
||||
byte_offset: 4
|
||||
fieldset: NDTR
|
||||
- name: PAR
|
||||
description: DMA channel 1 peripheral address register
|
||||
byte_offset: 8
|
||||
- name: MAR
|
||||
description: DMA channel 1 memory address register
|
||||
byte_offset: 12
|
||||
- name: CR
|
||||
description: DMA channel configuration register (DMA_CCR)
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: NDTR
|
||||
description: DMA channel 1 number of data register
|
||||
byte_offset: 4
|
||||
fieldset: NDTR
|
||||
- name: PAR
|
||||
description: DMA channel 1 peripheral address register
|
||||
byte_offset: 8
|
||||
- name: MAR
|
||||
description: DMA channel 1 memory address register
|
||||
byte_offset: 12
|
||||
block/DMA:
|
||||
description: DMA controller
|
||||
items:
|
||||
- name: ISR
|
||||
description: DMA interrupt status register (DMA_ISR)
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: ISR
|
||||
- name: IFCR
|
||||
description: DMA interrupt flag clear register (DMA_IFCR)
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: ISR
|
||||
- name: CH
|
||||
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
|
||||
array:
|
||||
len: 8
|
||||
stride: 20
|
||||
byte_offset: 8
|
||||
block: CH
|
||||
- name: CSELR
|
||||
description: channel selection register
|
||||
byte_offset: 168
|
||||
fieldset: CSELR
|
||||
- name: ISR
|
||||
description: DMA interrupt status register (DMA_ISR)
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: ISR
|
||||
- name: IFCR
|
||||
description: DMA interrupt flag clear register (DMA_IFCR)
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: ISR
|
||||
- name: CH
|
||||
description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
|
||||
array:
|
||||
len: 8
|
||||
stride: 20
|
||||
byte_offset: 8
|
||||
block: CH
|
||||
- name: CSELR
|
||||
description: channel selection register
|
||||
byte_offset: 168
|
||||
fieldset: CSELR
|
||||
fieldset/CR:
|
||||
description: DMA channel configuration register (DMA_CCR)
|
||||
fields:
|
||||
- name: EN
|
||||
description: Channel enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TCIE
|
||||
description: Transfer complete interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: HTIE
|
||||
description: Half Transfer interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TEIE
|
||||
description: Transfer error interrupt enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DIR
|
||||
description: Data transfer direction
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: DIR
|
||||
- name: CIRC
|
||||
description: Circular mode
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: CIRC
|
||||
- name: PINC
|
||||
description: Peripheral increment mode
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: MINC
|
||||
description: Memory increment mode
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: PSIZE
|
||||
description: Peripheral size
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
enum: SIZE
|
||||
- name: MSIZE
|
||||
description: Memory size
|
||||
bit_offset: 10
|
||||
bit_size: 2
|
||||
enum: SIZE
|
||||
- name: PL
|
||||
description: Channel Priority level
|
||||
bit_offset: 12
|
||||
bit_size: 2
|
||||
enum: PL
|
||||
- name: MEM2MEM
|
||||
description: Memory to memory mode
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
enum: MEMMEM
|
||||
- name: EN
|
||||
description: Channel enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TCIE
|
||||
description: Transfer complete interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: HTIE
|
||||
description: Half Transfer interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TEIE
|
||||
description: Transfer error interrupt enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DIR
|
||||
description: Data transfer direction
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: DIR
|
||||
- name: CIRC
|
||||
description: Circular mode
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: CIRC
|
||||
- name: PINC
|
||||
description: Peripheral increment mode
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: MINC
|
||||
description: Memory increment mode
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: PSIZE
|
||||
description: Peripheral size
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
enum: SIZE
|
||||
- name: MSIZE
|
||||
description: Memory size
|
||||
bit_offset: 10
|
||||
bit_size: 2
|
||||
enum: SIZE
|
||||
- name: PL
|
||||
description: Channel Priority level
|
||||
bit_offset: 12
|
||||
bit_size: 2
|
||||
enum: PL
|
||||
- name: MEM2MEM
|
||||
description: Memory to memory mode
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
enum: MEMMEM
|
||||
fieldset/CSELR:
|
||||
description: channel selection register
|
||||
fields:
|
||||
- name: CS
|
||||
description: DMA channel selection
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
- name: CS
|
||||
description: DMA channel selection
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
fieldset/ISR:
|
||||
description: DMA interrupt status register (DMA_ISR)
|
||||
fields:
|
||||
- name: GIF
|
||||
description: Channel 1 Global interrupt flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
- name: TCIF
|
||||
description: Channel 1 Transfer Complete flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
- name: HTIF
|
||||
description: Channel 1 Half Transfer Complete flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
- name: TEIF
|
||||
description: Channel 1 Transfer Error flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
- name: GIF
|
||||
description: Channel 1 Global interrupt flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
- name: TCIF
|
||||
description: Channel 1 Transfer Complete flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
- name: HTIF
|
||||
description: Channel 1 Half Transfer Complete flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
- name: TEIF
|
||||
description: Channel 1 Transfer Error flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
fieldset/NDTR:
|
||||
description: DMA channel 1 number of data register
|
||||
fields:
|
||||
- name: NDT
|
||||
description: Number of data to transfer
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: NDT
|
||||
description: Number of data to transfer
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
enum/CIRC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Circular buffer disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Circular buffer enabled
|
||||
value: 1
|
||||
- name: Disabled
|
||||
description: Circular buffer disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Circular buffer enabled
|
||||
value: 1
|
||||
enum/DIR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: FromPeripheral
|
||||
description: Read from peripheral
|
||||
value: 0
|
||||
- name: FromMemory
|
||||
description: Read from memory
|
||||
value: 1
|
||||
- name: FromPeripheral
|
||||
description: Read from peripheral
|
||||
value: 0
|
||||
- name: FromMemory
|
||||
description: Read from memory
|
||||
value: 1
|
||||
enum/INC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Increment mode disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Increment mode enabled
|
||||
value: 1
|
||||
- name: Disabled
|
||||
description: Increment mode disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Increment mode enabled
|
||||
value: 1
|
||||
enum/MEMMEM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Memory to memory mode disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Memory to memory mode enabled
|
||||
value: 1
|
||||
- name: Disabled
|
||||
description: Memory to memory mode disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Memory to memory mode enabled
|
||||
value: 1
|
||||
enum/PL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Low
|
||||
description: Low priority
|
||||
value: 0
|
||||
- name: Medium
|
||||
description: Medium priority
|
||||
value: 1
|
||||
- name: High
|
||||
description: High priority
|
||||
value: 2
|
||||
- name: VeryHigh
|
||||
description: Very high priority
|
||||
value: 3
|
||||
- name: Low
|
||||
description: Low priority
|
||||
value: 0
|
||||
- name: Medium
|
||||
description: Medium priority
|
||||
value: 1
|
||||
- name: High
|
||||
description: High priority
|
||||
value: 2
|
||||
- name: VeryHigh
|
||||
description: Very high priority
|
||||
value: 3
|
||||
enum/SIZE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Bits8
|
||||
description: 8-bit size
|
||||
value: 0
|
||||
- name: Bits16
|
||||
description: 16-bit size
|
||||
value: 1
|
||||
- name: Bits32
|
||||
description: 32-bit size
|
||||
value: 2
|
||||
- name: Bits8
|
||||
description: 8-bit size
|
||||
value: 0
|
||||
- name: Bits16
|
||||
description: 16-bit size
|
||||
value: 1
|
||||
- name: Bits32
|
||||
description: 32-bit size
|
||||
value: 2
|
||||
|
||||
@ -1,144 +1,143 @@
|
||||
---
|
||||
block/BKP:
|
||||
description: Backup registers
|
||||
items:
|
||||
- name: DR
|
||||
description: Data register
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 4
|
||||
- 8
|
||||
- 12
|
||||
- 16
|
||||
- 20
|
||||
- 24
|
||||
- 28
|
||||
- 32
|
||||
- 36
|
||||
- 60
|
||||
- 64
|
||||
- 68
|
||||
- 72
|
||||
- 76
|
||||
- 80
|
||||
- 84
|
||||
- 88
|
||||
- 92
|
||||
- 96
|
||||
- 100
|
||||
- 104
|
||||
- 108
|
||||
- 112
|
||||
- 116
|
||||
- 120
|
||||
- 124
|
||||
- 128
|
||||
- 132
|
||||
- 136
|
||||
- 140
|
||||
- 144
|
||||
- 148
|
||||
- 152
|
||||
- 156
|
||||
- 160
|
||||
- 164
|
||||
- 168
|
||||
- 172
|
||||
- 176
|
||||
- 180
|
||||
- 184
|
||||
byte_offset: 0
|
||||
fieldset: DR
|
||||
- name: RTCCR
|
||||
description: RTC clock calibration register
|
||||
byte_offset: 40
|
||||
fieldset: RTCCR
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 44
|
||||
fieldset: CR
|
||||
- name: CSR
|
||||
description: Control/status register
|
||||
byte_offset: 48
|
||||
fieldset: CSR
|
||||
- name: DR
|
||||
description: Data register
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 4
|
||||
- 8
|
||||
- 12
|
||||
- 16
|
||||
- 20
|
||||
- 24
|
||||
- 28
|
||||
- 32
|
||||
- 36
|
||||
- 60
|
||||
- 64
|
||||
- 68
|
||||
- 72
|
||||
- 76
|
||||
- 80
|
||||
- 84
|
||||
- 88
|
||||
- 92
|
||||
- 96
|
||||
- 100
|
||||
- 104
|
||||
- 108
|
||||
- 112
|
||||
- 116
|
||||
- 120
|
||||
- 124
|
||||
- 128
|
||||
- 132
|
||||
- 136
|
||||
- 140
|
||||
- 144
|
||||
- 148
|
||||
- 152
|
||||
- 156
|
||||
- 160
|
||||
- 164
|
||||
- 168
|
||||
- 172
|
||||
- 176
|
||||
- 180
|
||||
- 184
|
||||
byte_offset: 0
|
||||
fieldset: DR
|
||||
- name: RTCCR
|
||||
description: RTC clock calibration register
|
||||
byte_offset: 40
|
||||
fieldset: RTCCR
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 44
|
||||
fieldset: CR
|
||||
- name: CSR
|
||||
description: Control/status register
|
||||
byte_offset: 48
|
||||
fieldset: CSR
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
- name: TPE
|
||||
description: Tamper pin enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TPAL
|
||||
description: Tamper pin active level
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
enum: TPAL
|
||||
- name: TPE
|
||||
description: Tamper pin enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TPAL
|
||||
description: Tamper pin active level
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
enum: TPAL
|
||||
fieldset/CSR:
|
||||
description: Control/status register
|
||||
fields:
|
||||
- name: CTE
|
||||
description: Clear Tamper event
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: CTI
|
||||
description: Clear Tamper Interrupt
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TPIE
|
||||
description: Tamper Pin interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TEF
|
||||
description: Tamper Event Flag
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: TIF
|
||||
description: Tamper Interrupt Flag
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: CTE
|
||||
description: Clear Tamper event
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: CTI
|
||||
description: Clear Tamper Interrupt
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TPIE
|
||||
description: Tamper Pin interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TEF
|
||||
description: Tamper Event Flag
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: TIF
|
||||
description: Tamper Interrupt Flag
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
fieldset/DR:
|
||||
description: Data register
|
||||
fields:
|
||||
- name: D
|
||||
description: Backup data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: D
|
||||
description: Backup data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/RTCCR:
|
||||
description: RTC clock calibration register
|
||||
fields:
|
||||
- name: CAL
|
||||
description: Calibration value
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: CCO
|
||||
description: Calibration Clock Output
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: ASOE
|
||||
description: Alarm or second output enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ASOS
|
||||
description: Alarm or second output selection
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: ASOS
|
||||
- name: CAL
|
||||
description: Calibration value
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: CCO
|
||||
description: Calibration Clock Output
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: ASOE
|
||||
description: Alarm or second output enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ASOS
|
||||
description: Alarm or second output selection
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: ASOS
|
||||
enum/ASOS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Alarm
|
||||
description: RTC Alarm pulse output selected
|
||||
value: 0
|
||||
- name: Second
|
||||
description: RTC Second pulse output selected
|
||||
value: 1
|
||||
- name: Alarm
|
||||
description: RTC Alarm pulse output selected
|
||||
value: 0
|
||||
- name: Second
|
||||
description: RTC Second pulse output selected
|
||||
value: 1
|
||||
enum/TPAL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: High
|
||||
description: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set)
|
||||
value: 0
|
||||
- name: Low
|
||||
description: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set)
|
||||
value: 1
|
||||
- name: High
|
||||
description: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set)
|
||||
value: 0
|
||||
- name: Low
|
||||
description: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set)
|
||||
value: 1
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,21 +1,20 @@
|
||||
---
|
||||
block/CRC:
|
||||
description: Cyclic Redundancy Check calculation unit
|
||||
items:
|
||||
- name: DR
|
||||
description: Data register
|
||||
byte_offset: 0
|
||||
- name: IDR
|
||||
description: Independent Data register
|
||||
byte_offset: 4
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 8
|
||||
fieldset: CR
|
||||
- name: DR
|
||||
description: Data register
|
||||
byte_offset: 0
|
||||
- name: IDR
|
||||
description: Independent Data register
|
||||
byte_offset: 4
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 8
|
||||
fieldset: CR
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
- name: RESET
|
||||
description: RESET bit
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RESET
|
||||
description: RESET bit
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
|
||||
@ -1,86 +1,85 @@
|
||||
---
|
||||
block/CRC:
|
||||
description: Cyclic Redundancy Check calculation unit
|
||||
items:
|
||||
- name: DR
|
||||
description: Data register
|
||||
byte_offset: 0
|
||||
- name: DR16
|
||||
description: Data register - half-word sized
|
||||
byte_offset: 0
|
||||
bit_size: 16
|
||||
- name: DR8
|
||||
description: Data register - byte sized
|
||||
byte_offset: 0
|
||||
bit_size: 8
|
||||
- name: IDR
|
||||
description: Independent Data register
|
||||
byte_offset: 4
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 8
|
||||
fieldset: CR
|
||||
- name: INIT
|
||||
description: Initial CRC value
|
||||
byte_offset: 16
|
||||
- name: DR
|
||||
description: Data register
|
||||
byte_offset: 0
|
||||
- name: DR16
|
||||
description: Data register - half-word sized
|
||||
byte_offset: 0
|
||||
bit_size: 16
|
||||
- name: DR8
|
||||
description: Data register - byte sized
|
||||
byte_offset: 0
|
||||
bit_size: 8
|
||||
- name: IDR
|
||||
description: Independent Data register
|
||||
byte_offset: 4
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 8
|
||||
fieldset: CR
|
||||
- name: INIT
|
||||
description: Initial CRC value
|
||||
byte_offset: 16
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
- name: RESET
|
||||
description: RESET bit
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: POLYSIZE
|
||||
description: Polynomial size
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
enum: POLYSIZE
|
||||
- name: REV_IN
|
||||
description: Reverse input data
|
||||
bit_offset: 5
|
||||
bit_size: 2
|
||||
enum: REV_IN
|
||||
- name: REV_OUT
|
||||
description: Reverse output data
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: REV_OUT
|
||||
- name: RESET
|
||||
description: RESET bit
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: POLYSIZE
|
||||
description: Polynomial size
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
enum: POLYSIZE
|
||||
- name: REV_IN
|
||||
description: Reverse input data
|
||||
bit_offset: 5
|
||||
bit_size: 2
|
||||
enum: REV_IN
|
||||
- name: REV_OUT
|
||||
description: Reverse output data
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: REV_OUT
|
||||
enum/POLYSIZE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Polysize32
|
||||
description: 32-bit polynomial
|
||||
value: 0
|
||||
- name: Polysize16
|
||||
description: 16-bit polynomial
|
||||
value: 1
|
||||
- name: Polysize8
|
||||
description: 8-bit polynomial
|
||||
value: 2
|
||||
- name: Polysize7
|
||||
description: 7-bit polynomial
|
||||
value: 3
|
||||
- name: Polysize32
|
||||
description: 32-bit polynomial
|
||||
value: 0
|
||||
- name: Polysize16
|
||||
description: 16-bit polynomial
|
||||
value: 1
|
||||
- name: Polysize8
|
||||
description: 8-bit polynomial
|
||||
value: 2
|
||||
- name: Polysize7
|
||||
description: 7-bit polynomial
|
||||
value: 3
|
||||
enum/REV_IN:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Normal
|
||||
description: Bit order not affected
|
||||
value: 0
|
||||
- name: Byte
|
||||
description: Bit reversal done by byte
|
||||
value: 1
|
||||
- name: HalfWord
|
||||
description: Bit reversal done by half-word
|
||||
value: 2
|
||||
- name: Word
|
||||
description: Bit reversal done by word
|
||||
value: 3
|
||||
- name: Normal
|
||||
description: Bit order not affected
|
||||
value: 0
|
||||
- name: Byte
|
||||
description: Bit reversal done by byte
|
||||
value: 1
|
||||
- name: HalfWord
|
||||
description: Bit reversal done by half-word
|
||||
value: 2
|
||||
- name: Word
|
||||
description: Bit reversal done by word
|
||||
value: 3
|
||||
enum/REV_OUT:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Normal
|
||||
description: Bit order not affected
|
||||
value: 0
|
||||
- name: Reversed
|
||||
description: Bit reversed output
|
||||
value: 1
|
||||
- name: Normal
|
||||
description: Bit order not affected
|
||||
value: 0
|
||||
- name: Reversed
|
||||
description: Bit reversed output
|
||||
value: 1
|
||||
|
||||
@ -1,89 +1,88 @@
|
||||
---
|
||||
block/CRC:
|
||||
description: Cyclic Redundancy Check calculation unit
|
||||
items:
|
||||
- name: DR
|
||||
description: Data register
|
||||
byte_offset: 0
|
||||
- name: DR16
|
||||
description: Data register - half-word sized
|
||||
byte_offset: 0
|
||||
bit_size: 16
|
||||
- name: DR8
|
||||
description: Data register - byte sized
|
||||
byte_offset: 0
|
||||
bit_size: 8
|
||||
- name: IDR
|
||||
description: Independent Data register
|
||||
byte_offset: 4
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 8
|
||||
fieldset: CR
|
||||
- name: INIT
|
||||
description: Initial CRC value
|
||||
byte_offset: 16
|
||||
- name: POL
|
||||
description: CRC polynomial
|
||||
byte_offset: 20
|
||||
- name: DR
|
||||
description: Data register
|
||||
byte_offset: 0
|
||||
- name: DR16
|
||||
description: Data register - half-word sized
|
||||
byte_offset: 0
|
||||
bit_size: 16
|
||||
- name: DR8
|
||||
description: Data register - byte sized
|
||||
byte_offset: 0
|
||||
bit_size: 8
|
||||
- name: IDR
|
||||
description: Independent Data register
|
||||
byte_offset: 4
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 8
|
||||
fieldset: CR
|
||||
- name: INIT
|
||||
description: Initial CRC value
|
||||
byte_offset: 16
|
||||
- name: POL
|
||||
description: CRC polynomial
|
||||
byte_offset: 20
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
- name: RESET
|
||||
description: RESET bit
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: POLYSIZE
|
||||
description: Polynomial size
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
enum: POLYSIZE
|
||||
- name: REV_IN
|
||||
description: Reverse input data
|
||||
bit_offset: 5
|
||||
bit_size: 2
|
||||
enum: REV_IN
|
||||
- name: REV_OUT
|
||||
description: Reverse output data
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: REV_OUT
|
||||
- name: RESET
|
||||
description: RESET bit
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: POLYSIZE
|
||||
description: Polynomial size
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
enum: POLYSIZE
|
||||
- name: REV_IN
|
||||
description: Reverse input data
|
||||
bit_offset: 5
|
||||
bit_size: 2
|
||||
enum: REV_IN
|
||||
- name: REV_OUT
|
||||
description: Reverse output data
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: REV_OUT
|
||||
enum/POLYSIZE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Polysize32
|
||||
description: 32-bit polynomial
|
||||
value: 0
|
||||
- name: Polysize16
|
||||
description: 16-bit polynomial
|
||||
value: 1
|
||||
- name: Polysize8
|
||||
description: 8-bit polynomial
|
||||
value: 2
|
||||
- name: Polysize7
|
||||
description: 7-bit polynomial
|
||||
value: 3
|
||||
- name: Polysize32
|
||||
description: 32-bit polynomial
|
||||
value: 0
|
||||
- name: Polysize16
|
||||
description: 16-bit polynomial
|
||||
value: 1
|
||||
- name: Polysize8
|
||||
description: 8-bit polynomial
|
||||
value: 2
|
||||
- name: Polysize7
|
||||
description: 7-bit polynomial
|
||||
value: 3
|
||||
enum/REV_IN:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Normal
|
||||
description: Bit order not affected
|
||||
value: 0
|
||||
- name: Byte
|
||||
description: Bit reversal done by byte
|
||||
value: 1
|
||||
- name: HalfWord
|
||||
description: Bit reversal done by half-word
|
||||
value: 2
|
||||
- name: Word
|
||||
description: Bit reversal done by word
|
||||
value: 3
|
||||
- name: Normal
|
||||
description: Bit order not affected
|
||||
value: 0
|
||||
- name: Byte
|
||||
description: Bit reversal done by byte
|
||||
value: 1
|
||||
- name: HalfWord
|
||||
description: Bit reversal done by half-word
|
||||
value: 2
|
||||
- name: Word
|
||||
description: Bit reversal done by word
|
||||
value: 3
|
||||
enum/REV_OUT:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Normal
|
||||
description: Bit order not affected
|
||||
value: 0
|
||||
- name: Reversed
|
||||
description: Bit reversed output
|
||||
value: 1
|
||||
- name: Normal
|
||||
description: Bit order not affected
|
||||
value: 0
|
||||
- name: Reversed
|
||||
description: Bit reversed output
|
||||
value: 1
|
||||
|
||||
@ -1,150 +1,149 @@
|
||||
---
|
||||
block/CRS:
|
||||
description: Clock recovery system
|
||||
items:
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: CFGR
|
||||
description: configuration register
|
||||
byte_offset: 4
|
||||
fieldset: CFGR
|
||||
- name: ISR
|
||||
description: interrupt and status register
|
||||
byte_offset: 8
|
||||
access: Read
|
||||
fieldset: ISR
|
||||
- name: ICR
|
||||
description: interrupt flag clear register
|
||||
byte_offset: 12
|
||||
fieldset: ICR
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: CFGR
|
||||
description: configuration register
|
||||
byte_offset: 4
|
||||
fieldset: CFGR
|
||||
- name: ISR
|
||||
description: interrupt and status register
|
||||
byte_offset: 8
|
||||
access: Read
|
||||
fieldset: ISR
|
||||
- name: ICR
|
||||
description: interrupt flag clear register
|
||||
byte_offset: 12
|
||||
fieldset: ICR
|
||||
fieldset/CFGR:
|
||||
description: configuration register
|
||||
fields:
|
||||
- name: RELOAD
|
||||
description: Counter reload value
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: FELIM
|
||||
description: Frequency error limit
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: SYNCDIV
|
||||
description: SYNC divider
|
||||
bit_offset: 24
|
||||
bit_size: 3
|
||||
- name: SYNCSRC
|
||||
description: SYNC signal source selection
|
||||
bit_offset: 28
|
||||
bit_size: 2
|
||||
enum: SYNCSRC
|
||||
- name: SYNCPOL
|
||||
description: SYNC polarity selection
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: RELOAD
|
||||
description: Counter reload value
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: FELIM
|
||||
description: Frequency error limit
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: SYNCDIV
|
||||
description: SYNC divider
|
||||
bit_offset: 24
|
||||
bit_size: 3
|
||||
- name: SYNCSRC
|
||||
description: SYNC signal source selection
|
||||
bit_offset: 28
|
||||
bit_size: 2
|
||||
enum: SYNCSRC
|
||||
- name: SYNCPOL
|
||||
description: SYNC polarity selection
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: control register
|
||||
fields:
|
||||
- name: SYNCOKIE
|
||||
description: SYNC event OK interrupt enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SYNCWARNIE
|
||||
description: SYNC warning interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Synchronization or trimming error interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: ESYNCIE
|
||||
description: Expected SYNC interrupt enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: CEN
|
||||
description: Frequency error counter enable
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: AUTOTRIMEN
|
||||
description: Automatic trimming enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: SWSYNC
|
||||
description: Generate software SYNC event
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TRIM
|
||||
description: HSI48 oscillator smooth trimming
|
||||
bit_offset: 8
|
||||
bit_size: 6
|
||||
- name: SYNCOKIE
|
||||
description: SYNC event OK interrupt enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SYNCWARNIE
|
||||
description: SYNC warning interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Synchronization or trimming error interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: ESYNCIE
|
||||
description: Expected SYNC interrupt enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: CEN
|
||||
description: Frequency error counter enable
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: AUTOTRIMEN
|
||||
description: Automatic trimming enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: SWSYNC
|
||||
description: Generate software SYNC event
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TRIM
|
||||
description: HSI48 oscillator smooth trimming
|
||||
bit_offset: 8
|
||||
bit_size: 6
|
||||
fieldset/ICR:
|
||||
description: interrupt flag clear register
|
||||
fields:
|
||||
- name: SYNCOKC
|
||||
description: SYNC event OK clear flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SYNCWARNC
|
||||
description: SYNC warning clear flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ERRC
|
||||
description: Error clear flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: ESYNCC
|
||||
description: Expected SYNC clear flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: SYNCOKC
|
||||
description: SYNC event OK clear flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SYNCWARNC
|
||||
description: SYNC warning clear flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ERRC
|
||||
description: Error clear flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: ESYNCC
|
||||
description: Expected SYNC clear flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
fieldset/ISR:
|
||||
description: interrupt and status register
|
||||
fields:
|
||||
- name: SYNCOKF
|
||||
description: SYNC event OK flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SYNCWARNF
|
||||
description: SYNC warning flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ERRF
|
||||
description: Error flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: ESYNCF
|
||||
description: Expected SYNC flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: SYNCERR
|
||||
description: SYNC error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: SYNCMISS
|
||||
description: SYNC missed
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: TRIMOVF
|
||||
description: Trimming overflow or underflow
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: FEDIR
|
||||
description: Frequency error direction
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: FECAP
|
||||
description: Frequency error capture
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: SYNCOKF
|
||||
description: SYNC event OK flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SYNCWARNF
|
||||
description: SYNC warning flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ERRF
|
||||
description: Error flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: ESYNCF
|
||||
description: Expected SYNC flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: SYNCERR
|
||||
description: SYNC error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: SYNCMISS
|
||||
description: SYNC missed
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: TRIMOVF
|
||||
description: Trimming overflow or underflow
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: FEDIR
|
||||
description: Frequency error direction
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: FECAP
|
||||
description: Frequency error capture
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
enum/SYNCSRC:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: GPIO
|
||||
description: GPIO selected as SYNC signal source
|
||||
value: 0
|
||||
- name: LSE
|
||||
description: LSE selected as SYNC signal source
|
||||
value: 1
|
||||
- name: USB
|
||||
description: USB SOF selected as SYNC signal source
|
||||
value: 2
|
||||
- name: GPIO
|
||||
description: GPIO selected as SYNC signal source
|
||||
value: 0
|
||||
- name: LSE
|
||||
description: LSE selected as SYNC signal source
|
||||
value: 1
|
||||
- name: USB
|
||||
description: USB SOF selected as SYNC signal source
|
||||
value: 2
|
||||
|
||||
@ -1,262 +1,261 @@
|
||||
---
|
||||
block/DAC:
|
||||
description: Digital-to-analog converter
|
||||
items:
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SWTRIGR
|
||||
description: software trigger register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: SWTRIGR
|
||||
- name: DHR12R
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 8
|
||||
fieldset: DHR12R
|
||||
- name: DHR12L
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 12
|
||||
fieldset: DHR12L
|
||||
- name: DHR8R
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 16
|
||||
fieldset: DHR8R
|
||||
- name: DHR12RD
|
||||
description: Dual DAC 12-bit right-aligned data holding register
|
||||
byte_offset: 32
|
||||
fieldset: DHR12RD
|
||||
- name: DHR12LD
|
||||
description: DUAL DAC 12-bit left aligned data holding register
|
||||
byte_offset: 36
|
||||
fieldset: DHR12LD
|
||||
- name: DHR8RD
|
||||
description: DUAL DAC 8-bit right aligned data holding register
|
||||
byte_offset: 40
|
||||
fieldset: DHR8RD
|
||||
- name: DOR
|
||||
description: channel data output register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 44
|
||||
access: Read
|
||||
fieldset: DOR
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 52
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SWTRIGR
|
||||
description: software trigger register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: SWTRIGR
|
||||
- name: DHR12R
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 8
|
||||
fieldset: DHR12R
|
||||
- name: DHR12L
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 12
|
||||
fieldset: DHR12L
|
||||
- name: DHR8R
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 16
|
||||
fieldset: DHR8R
|
||||
- name: DHR12RD
|
||||
description: Dual DAC 12-bit right-aligned data holding register
|
||||
byte_offset: 32
|
||||
fieldset: DHR12RD
|
||||
- name: DHR12LD
|
||||
description: DUAL DAC 12-bit left aligned data holding register
|
||||
byte_offset: 36
|
||||
fieldset: DHR12LD
|
||||
- name: DHR8RD
|
||||
description: DUAL DAC 8-bit right aligned data holding register
|
||||
byte_offset: 40
|
||||
fieldset: DHR8RD
|
||||
- name: DOR
|
||||
description: channel data output register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 44
|
||||
access: Read
|
||||
fieldset: DOR
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 52
|
||||
fieldset: SR
|
||||
fieldset/CR:
|
||||
description: control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: DAC channel enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: BOFF
|
||||
description: DAC channel output buffer disable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TEN
|
||||
description: DAC channel trigger enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL1
|
||||
description: DAC channel 1 trigger selection
|
||||
bit_offset: 3
|
||||
bit_size: 3
|
||||
enum: TSEL1
|
||||
- name: WAVE
|
||||
description: DAC channel noise/triangle wave generation enable
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
enum: WAVE
|
||||
- name: MAMP
|
||||
description: DAC channel mask/amplitude selector
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAEN
|
||||
description: DAC channel DMA enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAUDRIE
|
||||
description: DAC channel DMA Underrun Interrupt enable
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL2
|
||||
description: DAC channel 2 trigger selection
|
||||
bit_offset: 19
|
||||
bit_size: 3
|
||||
enum: TSEL2
|
||||
- name: EN
|
||||
description: DAC channel enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: BOFF
|
||||
description: DAC channel output buffer disable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TEN
|
||||
description: DAC channel trigger enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL1
|
||||
description: DAC channel 1 trigger selection
|
||||
bit_offset: 3
|
||||
bit_size: 3
|
||||
enum: TSEL1
|
||||
- name: WAVE
|
||||
description: DAC channel noise/triangle wave generation enable
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
enum: WAVE
|
||||
- name: MAMP
|
||||
description: DAC channel mask/amplitude selector
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAEN
|
||||
description: DAC channel DMA enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAUDRIE
|
||||
description: DAC channel DMA Underrun Interrupt enable
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL2
|
||||
description: DAC channel 2 trigger selection
|
||||
bit_offset: 19
|
||||
bit_size: 3
|
||||
enum: TSEL2
|
||||
fieldset/DHR12L:
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
fieldset/DHR12LD:
|
||||
description: DUAL DAC 12-bit left aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/DHR12R:
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/DHR12RD:
|
||||
description: Dual DAC 12-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/DHR8R:
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: DHR
|
||||
description: DAC channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/DHR8RD:
|
||||
description: DUAL DAC 8-bit right aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 8
|
||||
- name: DHR
|
||||
description: DAC channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 8
|
||||
fieldset/DOR:
|
||||
description: channel data output register
|
||||
fields:
|
||||
- name: DOR
|
||||
description: DAC channel data output
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: DOR
|
||||
description: DAC channel data output
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/SR:
|
||||
description: status register
|
||||
fields:
|
||||
- name: DMAUDR
|
||||
description: DAC channel DMA underrun flag
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAUDR
|
||||
description: DAC channel DMA underrun flag
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SWTRIGR:
|
||||
description: software trigger register
|
||||
fields:
|
||||
- name: SWTRIG
|
||||
description: DAC channel software trigger
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
- name: SWTRIG
|
||||
description: DAC channel software trigger
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
enum/TSEL1:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 0
|
||||
- name: TIM3_TRGO
|
||||
description: Timer 3 TRGO event
|
||||
value: 1
|
||||
- name: TIM7_TRGO
|
||||
description: Timer 7 TRGO event
|
||||
value: 2
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 3
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 4
|
||||
- name: EXTI9
|
||||
description: EXTI line9
|
||||
value: 6
|
||||
- name: SOFTWARE
|
||||
description: Software trigger
|
||||
value: 7
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 0
|
||||
- name: TIM3_TRGO
|
||||
description: Timer 3 TRGO event
|
||||
value: 1
|
||||
- name: TIM7_TRGO
|
||||
description: Timer 7 TRGO event
|
||||
value: 2
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 3
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 4
|
||||
- name: EXTI9
|
||||
description: EXTI line9
|
||||
value: 6
|
||||
- name: SOFTWARE
|
||||
description: Software trigger
|
||||
value: 7
|
||||
enum/TSEL2:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 0
|
||||
- name: TIM8_TRGO
|
||||
description: Timer 8 TRGO event
|
||||
value: 1
|
||||
- name: TIM7_TRGO
|
||||
description: Timer 7 TRGO event
|
||||
value: 2
|
||||
- name: TIM5_TRGO
|
||||
description: Timer 5 TRGO event
|
||||
value: 3
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 4
|
||||
- name: TIM4_TRGO
|
||||
description: Timer 4 TRGO event
|
||||
value: 5
|
||||
- name: EXTI9
|
||||
description: EXTI line9
|
||||
value: 6
|
||||
- name: SOFTWARE
|
||||
description: Software trigger
|
||||
value: 7
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 0
|
||||
- name: TIM8_TRGO
|
||||
description: Timer 8 TRGO event
|
||||
value: 1
|
||||
- name: TIM7_TRGO
|
||||
description: Timer 7 TRGO event
|
||||
value: 2
|
||||
- name: TIM5_TRGO
|
||||
description: Timer 5 TRGO event
|
||||
value: 3
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 4
|
||||
- name: TIM4_TRGO
|
||||
description: Timer 4 TRGO event
|
||||
value: 5
|
||||
- name: EXTI9
|
||||
description: EXTI line9
|
||||
value: 6
|
||||
- name: SOFTWARE
|
||||
description: Software trigger
|
||||
value: 7
|
||||
enum/WAVE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Wave generation disabled
|
||||
value: 0
|
||||
- name: Noise
|
||||
description: Noise wave generation enabled
|
||||
value: 1
|
||||
- name: Triangle
|
||||
description: Triangle wave generation enabled
|
||||
value: 2
|
||||
- name: Disabled
|
||||
description: Wave generation disabled
|
||||
value: 0
|
||||
- name: Noise
|
||||
description: Noise wave generation enabled
|
||||
value: 1
|
||||
- name: Triangle
|
||||
description: Triangle wave generation enabled
|
||||
value: 2
|
||||
|
||||
@ -1,347 +1,346 @@
|
||||
---
|
||||
block/DAC:
|
||||
description: Digital-to-analog converter
|
||||
items:
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SWTRIGR
|
||||
description: software trigger register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: SWTRIGR
|
||||
- name: DHR12R
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 8
|
||||
fieldset: DHR12R
|
||||
- name: DHR12L
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 12
|
||||
fieldset: DHR12L
|
||||
- name: DHR8R
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 16
|
||||
fieldset: DHR8R
|
||||
- name: DHR12RD
|
||||
description: Dual DAC 12-bit right-aligned data holding register
|
||||
byte_offset: 32
|
||||
fieldset: DHR12RD
|
||||
- name: DHR12LD
|
||||
description: DUAL DAC 12-bit left aligned data holding register
|
||||
byte_offset: 36
|
||||
fieldset: DHR12LD
|
||||
- name: DHR8RD
|
||||
description: DUAL DAC 8-bit right aligned data holding register
|
||||
byte_offset: 40
|
||||
fieldset: DHR8RD
|
||||
- name: DOR
|
||||
description: channel data output register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 44
|
||||
access: Read
|
||||
fieldset: DOR
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 52
|
||||
fieldset: SR
|
||||
- name: CCR
|
||||
description: calibration control register
|
||||
byte_offset: 56
|
||||
fieldset: CCR
|
||||
- name: MCR
|
||||
description: mode control register
|
||||
byte_offset: 60
|
||||
fieldset: MCR
|
||||
- name: SHSR1
|
||||
description: Sample and Hold sample time register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 64
|
||||
fieldset: SHSR
|
||||
- name: SHHR
|
||||
description: Sample and Hold hold time register
|
||||
byte_offset: 72
|
||||
fieldset: SHHR
|
||||
- name: SHRR
|
||||
description: Sample and Hold refresh time register
|
||||
byte_offset: 76
|
||||
fieldset: SHRR
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SWTRIGR
|
||||
description: software trigger register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: SWTRIGR
|
||||
- name: DHR12R
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 8
|
||||
fieldset: DHR12R
|
||||
- name: DHR12L
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 12
|
||||
fieldset: DHR12L
|
||||
- name: DHR8R
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 16
|
||||
fieldset: DHR8R
|
||||
- name: DHR12RD
|
||||
description: Dual DAC 12-bit right-aligned data holding register
|
||||
byte_offset: 32
|
||||
fieldset: DHR12RD
|
||||
- name: DHR12LD
|
||||
description: DUAL DAC 12-bit left aligned data holding register
|
||||
byte_offset: 36
|
||||
fieldset: DHR12LD
|
||||
- name: DHR8RD
|
||||
description: DUAL DAC 8-bit right aligned data holding register
|
||||
byte_offset: 40
|
||||
fieldset: DHR8RD
|
||||
- name: DOR
|
||||
description: channel data output register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 44
|
||||
access: Read
|
||||
fieldset: DOR
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 52
|
||||
fieldset: SR
|
||||
- name: CCR
|
||||
description: calibration control register
|
||||
byte_offset: 56
|
||||
fieldset: CCR
|
||||
- name: MCR
|
||||
description: mode control register
|
||||
byte_offset: 60
|
||||
fieldset: MCR
|
||||
- name: SHSR1
|
||||
description: Sample and Hold sample time register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 64
|
||||
fieldset: SHSR
|
||||
- name: SHHR
|
||||
description: Sample and Hold hold time register
|
||||
byte_offset: 72
|
||||
fieldset: SHHR
|
||||
- name: SHRR
|
||||
description: Sample and Hold refresh time register
|
||||
byte_offset: 76
|
||||
fieldset: SHRR
|
||||
fieldset/CCR:
|
||||
description: calibration control register
|
||||
fields:
|
||||
- name: OTRIM1
|
||||
description: DAC Channel 1 offset trimming value
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: OTRIM2
|
||||
description: DAC Channel 2 offset trimming value
|
||||
bit_offset: 16
|
||||
bit_size: 5
|
||||
- name: OTRIM1
|
||||
description: DAC Channel 1 offset trimming value
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: OTRIM2
|
||||
description: DAC Channel 2 offset trimming value
|
||||
bit_offset: 16
|
||||
bit_size: 5
|
||||
fieldset/CR:
|
||||
description: control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: DAC channel enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TEN
|
||||
description: DAC channel trigger enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL1
|
||||
description: DAC channel 1 trigger selection
|
||||
bit_offset: 3
|
||||
bit_size: 3
|
||||
enum: TSEL1
|
||||
- name: WAVE
|
||||
description: DAC channel noise/triangle wave generation enable
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
enum: WAVE
|
||||
- name: MAMP
|
||||
description: DAC channel mask/amplitude selector
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAEN
|
||||
description: DAC channel DMA enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAUDRIE
|
||||
description: DAC channel DMA Underrun Interrupt enable
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CEN
|
||||
description: DAC channel calibration enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL2
|
||||
description: DAC channel 2 trigger selection
|
||||
bit_offset: 19
|
||||
bit_size: 3
|
||||
enum: TSEL2
|
||||
- name: EN
|
||||
description: DAC channel enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TEN
|
||||
description: DAC channel trigger enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL1
|
||||
description: DAC channel 1 trigger selection
|
||||
bit_offset: 3
|
||||
bit_size: 3
|
||||
enum: TSEL1
|
||||
- name: WAVE
|
||||
description: DAC channel noise/triangle wave generation enable
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
enum: WAVE
|
||||
- name: MAMP
|
||||
description: DAC channel mask/amplitude selector
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAEN
|
||||
description: DAC channel DMA enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAUDRIE
|
||||
description: DAC channel DMA Underrun Interrupt enable
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CEN
|
||||
description: DAC channel calibration enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL2
|
||||
description: DAC channel 2 trigger selection
|
||||
bit_offset: 19
|
||||
bit_size: 3
|
||||
enum: TSEL2
|
||||
fieldset/DHR12L:
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
fieldset/DHR12LD:
|
||||
description: DUAL DAC 12-bit left aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/DHR12R:
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/DHR12RD:
|
||||
description: Dual DAC 12-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/DHR8R:
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: DHR
|
||||
description: DAC channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/DHR8RD:
|
||||
description: DUAL DAC 8-bit right aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 8
|
||||
- name: DHR
|
||||
description: DAC channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 8
|
||||
fieldset/DOR:
|
||||
description: channel data output register
|
||||
fields:
|
||||
- name: DOR
|
||||
description: DAC channel data output
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: DOR
|
||||
description: DAC channel data output
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/MCR:
|
||||
description: mode control register
|
||||
fields:
|
||||
- name: MODE
|
||||
description: DAC channel mode
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: MODE
|
||||
description: DAC channel mode
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHHR:
|
||||
description: Sample and Hold hold time register
|
||||
fields:
|
||||
- name: THOLD
|
||||
description: DAC channel hold Time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: THOLD
|
||||
description: DAC channel hold Time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHRR:
|
||||
description: Sample and Hold refresh time register
|
||||
fields:
|
||||
- name: TREFRESH
|
||||
description: DAC channel refresh Time
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TREFRESH
|
||||
description: DAC channel refresh Time
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHSR:
|
||||
description: Sample and Hold sample time register
|
||||
fields:
|
||||
- name: TSAMPLE
|
||||
description: DAC channel sample Time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
- name: TSAMPLE
|
||||
description: DAC channel sample Time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
fieldset/SR:
|
||||
description: status register
|
||||
fields:
|
||||
- name: DMAUDR
|
||||
description: DAC channel DMA underrun flag
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CAL_FLAG
|
||||
description: DAC channel calibration offset status
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: BWST
|
||||
description: DAC channel busy writing sample time flag
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAUDR
|
||||
description: DAC channel DMA underrun flag
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CAL_FLAG
|
||||
description: DAC channel calibration offset status
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: BWST
|
||||
description: DAC channel busy writing sample time flag
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SWTRIGR:
|
||||
description: software trigger register
|
||||
fields:
|
||||
- name: SWTRIG
|
||||
description: DAC channel software trigger
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
- name: SWTRIG
|
||||
description: DAC channel software trigger
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
enum/TSEL1:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 0
|
||||
- name: TIM3_TRGO
|
||||
description: Timer 3 TRGO event
|
||||
value: 1
|
||||
- name: TIM7_TRGO
|
||||
description: Timer 7 TRGO event
|
||||
value: 2
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 3
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 4
|
||||
- name: EXTI9
|
||||
description: EXTI line9
|
||||
value: 6
|
||||
- name: SOFTWARE
|
||||
description: Software trigger
|
||||
value: 7
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 0
|
||||
- name: TIM3_TRGO
|
||||
description: Timer 3 TRGO event
|
||||
value: 1
|
||||
- name: TIM7_TRGO
|
||||
description: Timer 7 TRGO event
|
||||
value: 2
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 3
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 4
|
||||
- name: EXTI9
|
||||
description: EXTI line9
|
||||
value: 6
|
||||
- name: SOFTWARE
|
||||
description: Software trigger
|
||||
value: 7
|
||||
enum/TSEL2:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 0
|
||||
- name: TIM8_TRGO
|
||||
description: Timer 8 TRGO event
|
||||
value: 1
|
||||
- name: TIM7_TRGO
|
||||
description: Timer 7 TRGO event
|
||||
value: 2
|
||||
- name: TIM5_TRGO
|
||||
description: Timer 5 TRGO event
|
||||
value: 3
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 4
|
||||
- name: TIM4_TRGO
|
||||
description: Timer 4 TRGO event
|
||||
value: 5
|
||||
- name: EXTI9
|
||||
description: EXTI line9
|
||||
value: 6
|
||||
- name: SOFTWARE
|
||||
description: Software trigger
|
||||
value: 7
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 0
|
||||
- name: TIM8_TRGO
|
||||
description: Timer 8 TRGO event
|
||||
value: 1
|
||||
- name: TIM7_TRGO
|
||||
description: Timer 7 TRGO event
|
||||
value: 2
|
||||
- name: TIM5_TRGO
|
||||
description: Timer 5 TRGO event
|
||||
value: 3
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 4
|
||||
- name: TIM4_TRGO
|
||||
description: Timer 4 TRGO event
|
||||
value: 5
|
||||
- name: EXTI9
|
||||
description: EXTI line9
|
||||
value: 6
|
||||
- name: SOFTWARE
|
||||
description: Software trigger
|
||||
value: 7
|
||||
enum/WAVE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Wave generation disabled
|
||||
value: 0
|
||||
- name: Noise
|
||||
description: Noise wave generation enabled
|
||||
value: 1
|
||||
- name: Triangle
|
||||
description: Triangle wave generation enabled
|
||||
value: 2
|
||||
- name: Disabled
|
||||
description: Wave generation disabled
|
||||
value: 0
|
||||
- name: Noise
|
||||
description: Noise wave generation enabled
|
||||
value: 1
|
||||
- name: Triangle
|
||||
description: Triangle wave generation enabled
|
||||
value: 2
|
||||
|
||||
@ -1,394 +1,391 @@
|
||||
---
|
||||
block/DAC:
|
||||
description: Digital-to-analog converter
|
||||
items:
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SWTRIGR
|
||||
description: software trigger register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: SWTRIGR
|
||||
- name: DHR12R
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 8
|
||||
fieldset: DHR12R
|
||||
- name: DHR12L
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 12
|
||||
fieldset: DHR12L
|
||||
- name: DHR8R
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 16
|
||||
fieldset: DHR8R
|
||||
- name: DHR12RD
|
||||
description: Dual DAC 12-bit right-aligned data holding register
|
||||
byte_offset: 32
|
||||
fieldset: DHR12RD
|
||||
- name: DHR12LD
|
||||
description: DUAL DAC 12-bit left aligned data holding register
|
||||
byte_offset: 36
|
||||
fieldset: DHR12LD
|
||||
- name: DHR8RD
|
||||
description: DUAL DAC 8-bit right aligned data holding register
|
||||
byte_offset: 40
|
||||
fieldset: DHR8RD
|
||||
- name: DOR
|
||||
description: channel data output register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 44
|
||||
access: Read
|
||||
fieldset: DOR
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 52
|
||||
fieldset: SR
|
||||
- name: CCR
|
||||
description: calibration control register
|
||||
byte_offset: 56
|
||||
fieldset: CCR
|
||||
- name: MCR
|
||||
description: mode control register
|
||||
byte_offset: 60
|
||||
fieldset: MCR
|
||||
- name: SHSR1
|
||||
description: Sample and Hold sample time register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 64
|
||||
fieldset: SHSR
|
||||
- name: SHHR
|
||||
description: Sample and Hold hold time register
|
||||
byte_offset: 72
|
||||
fieldset: SHHR
|
||||
- name: SHRR
|
||||
description: Sample and Hold refresh time register
|
||||
byte_offset: 76
|
||||
fieldset: SHRR
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SWTRIGR
|
||||
description: software trigger register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: SWTRIGR
|
||||
- name: DHR12R
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 8
|
||||
fieldset: DHR12R
|
||||
- name: DHR12L
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 12
|
||||
fieldset: DHR12L
|
||||
- name: DHR8R
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 16
|
||||
fieldset: DHR8R
|
||||
- name: DHR12RD
|
||||
description: Dual DAC 12-bit right-aligned data holding register
|
||||
byte_offset: 32
|
||||
fieldset: DHR12RD
|
||||
- name: DHR12LD
|
||||
description: DUAL DAC 12-bit left aligned data holding register
|
||||
byte_offset: 36
|
||||
fieldset: DHR12LD
|
||||
- name: DHR8RD
|
||||
description: DUAL DAC 8-bit right aligned data holding register
|
||||
byte_offset: 40
|
||||
fieldset: DHR8RD
|
||||
- name: DOR
|
||||
description: channel data output register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 44
|
||||
access: Read
|
||||
fieldset: DOR
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 52
|
||||
fieldset: SR
|
||||
- name: CCR
|
||||
description: calibration control register
|
||||
byte_offset: 56
|
||||
fieldset: CCR
|
||||
- name: MCR
|
||||
description: mode control register
|
||||
byte_offset: 60
|
||||
fieldset: MCR
|
||||
- name: SHSR1
|
||||
description: Sample and Hold sample time register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 64
|
||||
fieldset: SHSR
|
||||
- name: SHHR
|
||||
description: Sample and Hold hold time register
|
||||
byte_offset: 72
|
||||
fieldset: SHHR
|
||||
- name: SHRR
|
||||
description: Sample and Hold refresh time register
|
||||
byte_offset: 76
|
||||
fieldset: SHRR
|
||||
fieldset/CCR:
|
||||
description: calibration control register
|
||||
fields:
|
||||
- name: OTRIM1
|
||||
description: DAC Channel 1 offset trimming value
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: OTRIM2
|
||||
description: DAC Channel 2 offset trimming value
|
||||
bit_offset: 16
|
||||
bit_size: 5
|
||||
- name: OTRIM1
|
||||
description: DAC Channel 1 offset trimming value
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: OTRIM2
|
||||
description: DAC Channel 2 offset trimming value
|
||||
bit_offset: 16
|
||||
bit_size: 5
|
||||
fieldset/CR:
|
||||
description: control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: DAC channel enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TEN
|
||||
description: DAC channel trigger enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL1
|
||||
description: DAC channel 1 trigger selection
|
||||
bit_offset: 2
|
||||
bit_size: 4
|
||||
enum: TSEL1
|
||||
- name: WAVE
|
||||
description: DAC channel noise/triangle wave generation enable
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
enum: WAVE
|
||||
- name: MAMP
|
||||
description: DAC channel mask/amplitude selector
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAEN
|
||||
description: DAC channel DMA enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAUDRIE
|
||||
description: DAC channel DMA Underrun Interrupt enable
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CEN
|
||||
description: DAC channel calibration enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL2
|
||||
description: DAC channel 2 trigger selection
|
||||
bit_offset: 18
|
||||
bit_size: 4
|
||||
enum: TSEL2
|
||||
- name: EN
|
||||
description: DAC channel enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TEN
|
||||
description: DAC channel trigger enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL1
|
||||
description: DAC channel 1 trigger selection
|
||||
bit_offset: 2
|
||||
bit_size: 4
|
||||
enum: TSEL1
|
||||
- name: WAVE
|
||||
description: DAC channel noise/triangle wave generation enable
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
enum: WAVE
|
||||
- name: MAMP
|
||||
description: DAC channel mask/amplitude selector
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAEN
|
||||
description: DAC channel DMA enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAUDRIE
|
||||
description: DAC channel DMA Underrun Interrupt enable
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CEN
|
||||
description: DAC channel calibration enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL2
|
||||
description: DAC channel 2 trigger selection
|
||||
bit_offset: 18
|
||||
bit_size: 4
|
||||
enum: TSEL2
|
||||
fieldset/DHR12L:
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
fieldset/DHR12LD:
|
||||
description: DUAL DAC 12-bit left aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/DHR12R:
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/DHR12RD:
|
||||
description: Dual DAC 12-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/DHR8R:
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: DHR
|
||||
description: DAC channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/DHR8RD:
|
||||
description: DUAL DAC 8-bit right aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 8
|
||||
- name: DHR
|
||||
description: DAC channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 8
|
||||
fieldset/DOR:
|
||||
description: channel data output register
|
||||
fields:
|
||||
- name: DOR
|
||||
description: DAC channel data output
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: DOR
|
||||
description: DAC channel data output
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/MCR:
|
||||
description: mode control register
|
||||
fields:
|
||||
- name: MODE
|
||||
description: DAC channel mode
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: MODE
|
||||
description: DAC channel mode
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHHR:
|
||||
description: Sample and Hold hold time register
|
||||
fields:
|
||||
- name: THOLD
|
||||
description: DAC channel hold Time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: THOLD
|
||||
description: DAC channel hold Time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHRR:
|
||||
description: Sample and Hold refresh time register
|
||||
fields:
|
||||
- name: TREFRESH
|
||||
description: DAC channel refresh Time
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TREFRESH
|
||||
description: DAC channel refresh Time
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHSR:
|
||||
description: Sample and Hold sample time register
|
||||
fields:
|
||||
- name: TSAMPLE
|
||||
description: DAC channel sample Time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
- name: TSAMPLE
|
||||
description: DAC channel sample Time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
fieldset/SR:
|
||||
description: status register
|
||||
fields:
|
||||
- name: DMAUDR
|
||||
description: DAC channel DMA underrun flag
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CAL_FLAG
|
||||
description: DAC channel calibration offset status
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: BWST
|
||||
description: DAC channel busy writing sample time flag
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAUDR
|
||||
description: DAC channel DMA underrun flag
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CAL_FLAG
|
||||
description: DAC channel calibration offset status
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: BWST
|
||||
description: DAC channel busy writing sample time flag
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SWTRIGR:
|
||||
description: software trigger register
|
||||
fields:
|
||||
- name: SWTRIG
|
||||
description: DAC channel software trigger
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
- name: SWTRIG
|
||||
description: DAC channel software trigger
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
enum/TSEL1:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: SOFTWARE
|
||||
description: Software trigger
|
||||
value: 0
|
||||
- name: TIM1_TRGO
|
||||
description: Timer 1 TRGO event
|
||||
value: 1
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 2
|
||||
- name: TIM4_TRGO
|
||||
description: Timer 4 TRGO event
|
||||
value: 3
|
||||
- name: TIM5_TRGO
|
||||
description: Timer 5 TRGO event
|
||||
value: 4
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 5
|
||||
- name: TIM7_TRGO
|
||||
description: Timer 7 TRGO event
|
||||
value: 6
|
||||
- name: TIM8_TRGO
|
||||
description: Timer 8 TRGO event
|
||||
value: 7
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 8
|
||||
- name: HRTIM1_DACTRG1
|
||||
description: High resolution timer 1 DACTRG1 event
|
||||
value: 9
|
||||
- name: HRTIM1_DACTRG2
|
||||
description: High resolution timer 1 DACTRG2 event
|
||||
value: 10
|
||||
- name: LPTIM1_OUT
|
||||
description: Low-power timer 1 OUT event
|
||||
value: 11
|
||||
- name: LPTIM2_OUT
|
||||
description: Low-power timer 2 OUT event
|
||||
value: 12
|
||||
- name: EXTI9
|
||||
description: EXTI line9
|
||||
value: 13
|
||||
- name: LPTIM3_OUT
|
||||
description: Low-power timer 3 OUT event
|
||||
value: 14
|
||||
|
||||
- name: SOFTWARE
|
||||
description: Software trigger
|
||||
value: 0
|
||||
- name: TIM1_TRGO
|
||||
description: Timer 1 TRGO event
|
||||
value: 1
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 2
|
||||
- name: TIM4_TRGO
|
||||
description: Timer 4 TRGO event
|
||||
value: 3
|
||||
- name: TIM5_TRGO
|
||||
description: Timer 5 TRGO event
|
||||
value: 4
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 5
|
||||
- name: TIM7_TRGO
|
||||
description: Timer 7 TRGO event
|
||||
value: 6
|
||||
- name: TIM8_TRGO
|
||||
description: Timer 8 TRGO event
|
||||
value: 7
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 8
|
||||
- name: HRTIM1_DACTRG1
|
||||
description: High resolution timer 1 DACTRG1 event
|
||||
value: 9
|
||||
- name: HRTIM1_DACTRG2
|
||||
description: High resolution timer 1 DACTRG2 event
|
||||
value: 10
|
||||
- name: LPTIM1_OUT
|
||||
description: Low-power timer 1 OUT event
|
||||
value: 11
|
||||
- name: LPTIM2_OUT
|
||||
description: Low-power timer 2 OUT event
|
||||
value: 12
|
||||
- name: EXTI9
|
||||
description: EXTI line9
|
||||
value: 13
|
||||
- name: LPTIM3_OUT
|
||||
description: Low-power timer 3 OUT event
|
||||
value: 14
|
||||
enum/TSEL2:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: SOFTWARE
|
||||
description: Software trigger
|
||||
value: 0
|
||||
- name: TIM1_TRGO
|
||||
description: Timer 1 TRGO event
|
||||
value: 1
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 2
|
||||
- name: TIM4_TRGO
|
||||
description: Timer 4 TRGO event
|
||||
value: 3
|
||||
- name: TIM5_TRGO
|
||||
description: Timer 5 TRGO event
|
||||
value: 4
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 5
|
||||
- name: TIM7_TRGO
|
||||
description: Timer 7 TRGO event
|
||||
value: 6
|
||||
- name: TIM8_TRGO
|
||||
description: Timer 8 TRGO event
|
||||
value: 7
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 8
|
||||
- name: HRTIM1_DACTRG1
|
||||
description: High resolution timer 1 DACTRG1 event
|
||||
value: 9
|
||||
- name: HRTIM1_DACTRG2
|
||||
description: High resolution timer 1 DACTRG2 event
|
||||
value: 10
|
||||
- name: LPTIM1_OUT
|
||||
description: Low-power timer 1 OUT event
|
||||
value: 11
|
||||
- name: LPTIM2_OUT
|
||||
description: Low-power timer 2 OUT event
|
||||
value: 12
|
||||
- name: EXTI9
|
||||
description: EXTI line9
|
||||
value: 13
|
||||
- name: LPTIM3_OUT
|
||||
description: Low-power timer 3 OUT event
|
||||
value: 14
|
||||
|
||||
- name: SOFTWARE
|
||||
description: Software trigger
|
||||
value: 0
|
||||
- name: TIM1_TRGO
|
||||
description: Timer 1 TRGO event
|
||||
value: 1
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 2
|
||||
- name: TIM4_TRGO
|
||||
description: Timer 4 TRGO event
|
||||
value: 3
|
||||
- name: TIM5_TRGO
|
||||
description: Timer 5 TRGO event
|
||||
value: 4
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 5
|
||||
- name: TIM7_TRGO
|
||||
description: Timer 7 TRGO event
|
||||
value: 6
|
||||
- name: TIM8_TRGO
|
||||
description: Timer 8 TRGO event
|
||||
value: 7
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 8
|
||||
- name: HRTIM1_DACTRG1
|
||||
description: High resolution timer 1 DACTRG1 event
|
||||
value: 9
|
||||
- name: HRTIM1_DACTRG2
|
||||
description: High resolution timer 1 DACTRG2 event
|
||||
value: 10
|
||||
- name: LPTIM1_OUT
|
||||
description: Low-power timer 1 OUT event
|
||||
value: 11
|
||||
- name: LPTIM2_OUT
|
||||
description: Low-power timer 2 OUT event
|
||||
value: 12
|
||||
- name: EXTI9
|
||||
description: EXTI line9
|
||||
value: 13
|
||||
- name: LPTIM3_OUT
|
||||
description: Low-power timer 3 OUT event
|
||||
value: 14
|
||||
enum/WAVE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Wave generation disabled
|
||||
value: 0
|
||||
- name: Noise
|
||||
description: Noise wave generation enabled
|
||||
value: 1
|
||||
- name: Triangle
|
||||
description: Triangle wave generation enabled
|
||||
value: 2
|
||||
- name: Disabled
|
||||
description: Wave generation disabled
|
||||
value: 0
|
||||
- name: Noise
|
||||
description: Noise wave generation enabled
|
||||
value: 1
|
||||
- name: Triangle
|
||||
description: Triangle wave generation enabled
|
||||
value: 2
|
||||
|
||||
@ -1,85 +1,84 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR
|
||||
description: DBG APB freeze register 1
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR
|
||||
- name: APB2FZR
|
||||
description: DBG APB freeze register 2
|
||||
byte_offset: 12
|
||||
fieldset: APB2FZR
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR
|
||||
description: DBG APB freeze register 1
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR
|
||||
- name: APB2FZR
|
||||
description: DBG APB freeze register 2
|
||||
byte_offset: 12
|
||||
fieldset: APB2FZR
|
||||
fieldset/APB1FZR:
|
||||
description: DBG APB freeze register 1
|
||||
fields:
|
||||
- name: TIM3
|
||||
description: TIM3 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: Debug RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Debug Window Wachdog stopped when Core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Debug Independent Wachdog stopped when Core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: Debug RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Debug Window Wachdog stopped when Core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Debug Independent Wachdog stopped when Core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: DBG APB freeze register 2
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM1
|
||||
description: TIM1
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Debug MCU Configuration Register
|
||||
fields:
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
fieldset/IDCODE:
|
||||
description: MCU Device ID Code Register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
|
||||
@ -1,109 +1,108 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1_FZ
|
||||
description: Debug MCU APB1 freeze register
|
||||
byte_offset: 8
|
||||
fieldset: APB1_FZ
|
||||
- name: APB2_FZ
|
||||
description: Debug MCU APB2 freeze register
|
||||
byte_offset: 12
|
||||
fieldset: APB2_FZ
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1_FZ
|
||||
description: Debug MCU APB1 freeze register
|
||||
byte_offset: 8
|
||||
fieldset: APB1_FZ
|
||||
- name: APB2_FZ
|
||||
description: Debug MCU APB2 freeze register
|
||||
byte_offset: 12
|
||||
fieldset: APB2_FZ
|
||||
fieldset/APB1_FZ:
|
||||
description: Debug MCU APB1 freeze register
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: TIM2 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6 counter stopped when core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14 counter stopped when core is halted
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: Debug RTC stopped when core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Debug window watchdog stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Debug independent watchdog stopped when core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DBG_I2C1_SMBUS_TIMEOUT
|
||||
description: SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: CAN
|
||||
description: CAN stopped when core is halted
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: TIM2
|
||||
description: TIM2 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6 counter stopped when core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14 counter stopped when core is halted
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: Debug RTC stopped when core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Debug window watchdog stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Debug independent watchdog stopped when core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DBG_I2C1_SMBUS_TIMEOUT
|
||||
description: SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: CAN
|
||||
description: CAN stopped when core is halted
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
fieldset/APB2_FZ:
|
||||
description: Debug MCU APB2 freeze register
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: TIM15 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: TIM15 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Debug MCU Configuration Register
|
||||
fields:
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
fieldset/IDCODE:
|
||||
description: MCU Device ID Code Register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: DIV_ID
|
||||
description: Division Identifier
|
||||
bit_offset: 12
|
||||
bit_size: 4
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: DIV_ID
|
||||
description: Division Identifier
|
||||
bit_offset: 12
|
||||
bit_size: 4
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
|
||||
@ -1,127 +1,126 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: DBGMCU_IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: DBGMCU_CR
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: IDCODE
|
||||
description: DBGMCU_IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: DBGMCU_CR
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
fieldset/CR:
|
||||
description: DBGMCU_CR
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: DBG_SLEEP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: DBG_STOP
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: DBG_STANDBY
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: TRACE_IOEN
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: TRACE_MODE
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
- name: IWDG
|
||||
description: IWDG
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: WWDG
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: TIM1
|
||||
description: TIM1
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: TIM2
|
||||
description: TIM2
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: CAN1
|
||||
description: CAN1
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: DBG_I2C1_SMBUS_TIMEOUT
|
||||
description: DBG_I2C1_SMBUS_TIMEOUT
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: DBG_I2C2_SMBUS_TIMEOUT
|
||||
description: DBG_I2C2_SMBUS_TIMEOUT
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: CAN2
|
||||
description: CAN2
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: TIM15
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: TIM12
|
||||
description: TIM12
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: TIM13
|
||||
description: TIM13
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: DBG_SLEEP
|
||||
description: DBG_SLEEP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: DBG_STOP
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: DBG_STANDBY
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: TRACE_IOEN
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: TRACE_MODE
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
- name: IWDG
|
||||
description: IWDG
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: WWDG
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: TIM1
|
||||
description: TIM1
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: TIM2
|
||||
description: TIM2
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: CAN1
|
||||
description: CAN1
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: DBG_I2C1_SMBUS_TIMEOUT
|
||||
description: DBG_I2C1_SMBUS_TIMEOUT
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: DBG_I2C2_SMBUS_TIMEOUT
|
||||
description: DBG_I2C2_SMBUS_TIMEOUT
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: CAN2
|
||||
description: CAN2
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: TIM15
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: TIM12
|
||||
description: TIM12
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: TIM13
|
||||
description: TIM13
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
fieldset/IDCODE:
|
||||
description: DBGMCU_IDCODE
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: DEV_ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: REV_ID
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: DEV_ID
|
||||
description: DEV_ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: REV_ID
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
|
||||
@ -1,149 +1,148 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Control Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1_FZ
|
||||
description: Debug MCU APB1 Freeze registe
|
||||
byte_offset: 8
|
||||
fieldset: APB1_FZ
|
||||
- name: APB2_FZ
|
||||
description: Debug MCU APB2 Freeze registe
|
||||
byte_offset: 12
|
||||
fieldset: APB2_FZ
|
||||
- name: IDCODE
|
||||
description: IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Control Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1_FZ
|
||||
description: Debug MCU APB1 Freeze registe
|
||||
byte_offset: 8
|
||||
fieldset: APB1_FZ
|
||||
- name: APB2_FZ
|
||||
description: Debug MCU APB2 Freeze registe
|
||||
byte_offset: 12
|
||||
fieldset: APB2_FZ
|
||||
fieldset/APB1_FZ:
|
||||
description: Debug MCU APB1 Freeze registe
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: TIM2
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM12
|
||||
description: TIM12
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM13
|
||||
description: TIM13
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: WWDG
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDEG
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1_SMBUS_TIMEOUT
|
||||
description: I2C1_SMBUS_TIMEOUT
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2_SMBUS_TIMEOUT
|
||||
description: I2C2_SMBUS_TIMEOUT
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C3_SMBUS_TIMEOUT
|
||||
description: I2C3_SMBUS_TIMEOUT
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: CAN1
|
||||
description: CAN1
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: CAN2
|
||||
description: CAN2
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: TIM2
|
||||
description: TIM2
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM12
|
||||
description: TIM12
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM13
|
||||
description: TIM13
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: WWDG
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDEG
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1_SMBUS_TIMEOUT
|
||||
description: I2C1_SMBUS_TIMEOUT
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2_SMBUS_TIMEOUT
|
||||
description: I2C2_SMBUS_TIMEOUT
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C3_SMBUS_TIMEOUT
|
||||
description: I2C3_SMBUS_TIMEOUT
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: CAN1
|
||||
description: CAN1
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: CAN2
|
||||
description: CAN2
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
fieldset/APB2_FZ:
|
||||
description: Debug MCU APB2 Freeze registe
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM9
|
||||
description: TIM9 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM10
|
||||
description: TIM10 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM11
|
||||
description: TIM11 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM9
|
||||
description: TIM9 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM10
|
||||
description: TIM10 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM11
|
||||
description: TIM11 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Control Register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: DBG_SLEEP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: DBG_STOP
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: DBG_STANDBY
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: TRACE_IOEN
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: TRACE_MODE
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
- name: DBG_SLEEP
|
||||
description: DBG_SLEEP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: DBG_STOP
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: DBG_STANDBY
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: TRACE_IOEN
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: TRACE_MODE
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
fieldset/IDCODE:
|
||||
description: IDCODE
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: DEV_ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: REV_ID
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: DEV_ID
|
||||
description: DEV_ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: REV_ID
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
|
||||
@ -1,141 +1,140 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR
|
||||
description: APB Low Freeze Register
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR
|
||||
- name: APB2FZR
|
||||
description: APB High Freeze Register
|
||||
byte_offset: 12
|
||||
fieldset: APB2FZR
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR
|
||||
description: APB Low Freeze Register
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR
|
||||
- name: APB2FZR
|
||||
description: APB High Freeze Register
|
||||
byte_offset: 12
|
||||
fieldset: APB2FZR
|
||||
fieldset/APB1FZR:
|
||||
description: APB Low Freeze Register
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: Debug Timer 2 stopped when Core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: Debug Timer 3 stopped when Core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: Debug Timer 4 stopped when Core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: Debug Timer 5 stopped when Core is halted
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: Debug Timer 6 stopped when Core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: Debug Timer 7 stopped when Core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM12
|
||||
description: Debug Timer 12 stopped when Core is halted
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM13
|
||||
description: Debug Timer 13 stopped when Core is halted
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: Debug Timer 14 stopped when Core is halted
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: TIM18
|
||||
description: Debug Timer 18 stopped when Core is halted
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: Debug RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Debug Window Wachdog stopped when Core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Debug Independent Wachdog stopped when Core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1_SMBUS_TIMEOUT
|
||||
description: SMBUS timeout mode stopped when Core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2_SMBUS_TIMEOUT
|
||||
description: SMBUS timeout mode stopped when Core is halted
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: CAN
|
||||
description: Debug CAN stopped when core is halted
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: TIM2
|
||||
description: Debug Timer 2 stopped when Core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: Debug Timer 3 stopped when Core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: Debug Timer 4 stopped when Core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: Debug Timer 5 stopped when Core is halted
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: Debug Timer 6 stopped when Core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: Debug Timer 7 stopped when Core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM12
|
||||
description: Debug Timer 12 stopped when Core is halted
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM13
|
||||
description: Debug Timer 13 stopped when Core is halted
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: Debug Timer 14 stopped when Core is halted
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: TIM18
|
||||
description: Debug Timer 18 stopped when Core is halted
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: Debug RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Debug Window Wachdog stopped when Core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Debug Independent Wachdog stopped when Core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1_SMBUS_TIMEOUT
|
||||
description: SMBUS timeout mode stopped when Core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2_SMBUS_TIMEOUT
|
||||
description: SMBUS timeout mode stopped when Core is halted
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: CAN
|
||||
description: Debug CAN stopped when core is halted
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: APB High Freeze Register
|
||||
fields:
|
||||
- name: TIM15
|
||||
description: Debug Timer 15 stopped when Core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: Debug Timer 16 stopped when Core is halted
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: Debug Timer 17 stopped when Core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM19
|
||||
description: Debug Timer 19 stopped when Core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: Debug Timer 15 stopped when Core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: Debug Timer 16 stopped when Core is halted
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: Debug Timer 17 stopped when Core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM19
|
||||
description: Debug Timer 19 stopped when Core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Debug MCU Configuration Register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
fieldset/IDCODE:
|
||||
description: MCU Device ID Code Register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
|
||||
@ -1,153 +1,152 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Control Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR
|
||||
description: Debug MCU APB1 Freeze registe
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR
|
||||
- name: APB2FZR
|
||||
description: Debug MCU APB2 Freeze registe
|
||||
byte_offset: 12
|
||||
fieldset: APB2FZR
|
||||
- name: IDCODE
|
||||
description: IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Control Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR
|
||||
description: Debug MCU APB1 Freeze registe
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR
|
||||
- name: APB2FZR
|
||||
description: Debug MCU APB2 Freeze registe
|
||||
byte_offset: 12
|
||||
fieldset: APB2FZR
|
||||
fieldset/APB1FZR:
|
||||
description: Debug MCU APB1 Freeze registe
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: TIM2
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM12
|
||||
description: TIM12
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM13
|
||||
description: TIM13
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: WWDG
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDEG
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1_SMBUS_TIMEOUT
|
||||
description: I2C1_SMBUS_TIMEOUT
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2_SMBUS_TIMEOUT
|
||||
description: I2C2_SMBUS_TIMEOUT
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C3_SMBUS_TIMEOUT
|
||||
description: I2C3SMBUS_TIMEOUT
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: I2CFMP_SMBUS_TIMEOUT
|
||||
description: SMBUS timeout mode stopped when Core is halted
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: CAN1
|
||||
description: CAN1
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: CAN2
|
||||
description: CAN2
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: TIM2
|
||||
description: TIM2
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM12
|
||||
description: TIM12
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM13
|
||||
description: TIM13
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: WWDG
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDEG
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1_SMBUS_TIMEOUT
|
||||
description: I2C1_SMBUS_TIMEOUT
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2_SMBUS_TIMEOUT
|
||||
description: I2C2_SMBUS_TIMEOUT
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C3_SMBUS_TIMEOUT
|
||||
description: I2C3SMBUS_TIMEOUT
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: I2CFMP_SMBUS_TIMEOUT
|
||||
description: SMBUS timeout mode stopped when Core is halted
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: CAN1
|
||||
description: CAN1
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: CAN2
|
||||
description: CAN2
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: Debug MCU APB2 Freeze registe
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM9
|
||||
description: TIM9 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM10
|
||||
description: TIM10 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM11
|
||||
description: TIM11 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM9
|
||||
description: TIM9 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM10
|
||||
description: TIM10 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM11
|
||||
description: TIM11 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Control Register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: DBG_SLEEP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: DBG_STOP
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: DBG_STANDBY
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: TRACE_IOEN
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: TRACE_MODE
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
- name: DBG_SLEEP
|
||||
description: DBG_SLEEP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: DBG_STOP
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: DBG_STANDBY
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: TRACE_IOEN
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: TRACE_MODE
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
fieldset/IDCODE:
|
||||
description: IDCODE
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: DEV_ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: REV_ID
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: DEV_ID
|
||||
description: DEV_ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: REV_ID
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
|
||||
@ -1,161 +1,160 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Control Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR
|
||||
description: Debug MCU APB1 Freeze register
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR
|
||||
- name: APB2FZR
|
||||
description: Debug MCU APB2 Freeze register
|
||||
byte_offset: 12
|
||||
fieldset: APB2FZR
|
||||
- name: IDCODE
|
||||
description: IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Control Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR
|
||||
description: Debug MCU APB1 Freeze register
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR
|
||||
- name: APB2FZR
|
||||
description: Debug MCU APB2 Freeze register
|
||||
byte_offset: 12
|
||||
fieldset: APB2FZR
|
||||
fieldset/APB1FZR:
|
||||
description: Debug MCU APB1 Freeze register
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: TIM2
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM12
|
||||
description: TIM12
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM13
|
||||
description: TIM13
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: LPTIM1
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: WWDG
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDG
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: CAN3
|
||||
description: CAN3
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: DBG_I2C1_SMBUS_TIMEOUT
|
||||
description: DBG_I2C1_SMBUS_TIMEOUT
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: DBG_I2C2_SMBUS_TIMEOUT
|
||||
description: DBG_I2C2_SMBUS_TIMEOUT
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: DBG_I2C3_SMBUS_TIMEOUT
|
||||
description: DBG_I2C3_SMBUS_TIMEOUT
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: DBG_I2C4_SMBUS_TIMEOUT
|
||||
description: DBG_I2C4SMBUS_TIMEOUT
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: CAN1
|
||||
description: CAN1
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: CAN2
|
||||
description: CAN2
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: TIM2
|
||||
description: TIM2
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM12
|
||||
description: TIM12
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM13
|
||||
description: TIM13
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: LPTIM1
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: WWDG
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDG
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: CAN3
|
||||
description: CAN3
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: DBG_I2C1_SMBUS_TIMEOUT
|
||||
description: DBG_I2C1_SMBUS_TIMEOUT
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: DBG_I2C2_SMBUS_TIMEOUT
|
||||
description: DBG_I2C2_SMBUS_TIMEOUT
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: DBG_I2C3_SMBUS_TIMEOUT
|
||||
description: DBG_I2C3_SMBUS_TIMEOUT
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: DBG_I2C4_SMBUS_TIMEOUT
|
||||
description: DBG_I2C4SMBUS_TIMEOUT
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: CAN1
|
||||
description: CAN1
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: CAN2
|
||||
description: CAN2
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: Debug MCU APB2 Freeze register
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM9
|
||||
description: TIM9 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM10
|
||||
description: TIM10 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM11
|
||||
description: TIM11 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM9
|
||||
description: TIM9 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM10
|
||||
description: TIM10 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM11
|
||||
description: TIM11 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Control Register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: DBG_SLEEP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: DBG_STOP
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: DBG_STANDBY
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: TRACE_IOEN
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: TRACE_MODE
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
- name: DBG_SLEEP
|
||||
description: DBG_SLEEP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: DBG_STOP
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: DBG_STANDBY
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: TRACE_IOEN
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: TRACE_MODE
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
fieldset/IDCODE:
|
||||
description: IDCODE
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: DEV_ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: REV_ID
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: DEV_ID
|
||||
description: DEV_ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: REV_ID
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
|
||||
@ -1,109 +1,108 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR
|
||||
description: DBG APB freeze register 1
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR
|
||||
- name: APB2FZR
|
||||
description: DBG APB freeze register 2
|
||||
byte_offset: 12
|
||||
fieldset: APB2FZR
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR
|
||||
description: DBG APB freeze register 1
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR
|
||||
- name: APB2FZR
|
||||
description: DBG APB freeze register 2
|
||||
byte_offset: 12
|
||||
fieldset: APB2FZR
|
||||
fieldset/APB1FZR:
|
||||
description: DBG APB freeze register 1
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: Debug Timer 2 stopped when Core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: Debug Timer 6 stopped when Core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: Debug RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Debug Window Wachdog stopped when Core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Debug Independent Wachdog stopped when Core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: LPTIM2
|
||||
description: Clocking of LPTIMER2 counter when the core is halted
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: Clocking of LPTIMER1 counter when the core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: TIM2
|
||||
description: Debug Timer 2 stopped when Core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: Debug Timer 6 stopped when Core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: Debug RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Debug Window Wachdog stopped when Core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Debug Independent Wachdog stopped when Core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: LPTIM2
|
||||
description: Clocking of LPTIMER2 counter when the core is halted
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: Clocking of LPTIMER1 counter when the core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: DBG APB freeze register 2
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: TIM15
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM1
|
||||
description: TIM1
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: TIM15
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Debug MCU Configuration Register
|
||||
fields:
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
fieldset/IDCODE:
|
||||
description: MCU Device ID Code Register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
|
||||
@ -1,164 +1,163 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1LFZR
|
||||
description: APB Low Freeze Register 1
|
||||
byte_offset: 8
|
||||
fieldset: APB1LFZR
|
||||
- name: APB1HFZR
|
||||
description: APB Low Freeze Register 2
|
||||
byte_offset: 12
|
||||
fieldset: APB1HFZR
|
||||
- name: APB2FZR
|
||||
description: APB High Freeze Register
|
||||
byte_offset: 16
|
||||
fieldset: APB2FZR
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1LFZR
|
||||
description: APB Low Freeze Register 1
|
||||
byte_offset: 8
|
||||
fieldset: APB1LFZR
|
||||
- name: APB1HFZR
|
||||
description: APB Low Freeze Register 2
|
||||
byte_offset: 12
|
||||
fieldset: APB1HFZR
|
||||
- name: APB2FZR
|
||||
description: APB High Freeze Register
|
||||
byte_offset: 16
|
||||
fieldset: APB2FZR
|
||||
fieldset/APB1HFZR:
|
||||
description: APB Low Freeze Register 2
|
||||
fields:
|
||||
- name: I2C4
|
||||
description: I2C4
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: I2C4
|
||||
description: I2C4
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
fieldset/APB1LFZR:
|
||||
description: APB Low Freeze Register 1
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: Debug Timer 2 stopped when Core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4 counter stopped when core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5 counter stopped when core is halted
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: Debug Timer 6 stopped when Core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: Debug RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Debug Window Wachdog stopped when Core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Debug Independent Wachdog stopped when Core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2
|
||||
description: I2C2 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: I2C3 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LPTIMER
|
||||
description: LPTIM1 counter stopped when core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: TIM2
|
||||
description: Debug Timer 2 stopped when Core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4 counter stopped when core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5 counter stopped when core is halted
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: Debug Timer 6 stopped when Core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: Debug RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Debug Window Wachdog stopped when Core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Debug Independent Wachdog stopped when Core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2
|
||||
description: I2C2 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: I2C3 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LPTIMER
|
||||
description: LPTIM1 counter stopped when core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: APB High Freeze Register
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8 counter stopped when core is halted
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: TIM15 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM20
|
||||
description: TIM20counter stopped when core is halted
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: HRTIM0
|
||||
description: HRTIM0
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: HRTIM1
|
||||
description: HRTIM0
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: HRTIM2
|
||||
description: HRTIM0
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: HRTIM3
|
||||
description: HRTIM0
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8 counter stopped when core is halted
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: TIM15 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM20
|
||||
description: TIM20counter stopped when core is halted
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: HRTIM0
|
||||
description: HRTIM0
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: HRTIM1
|
||||
description: HRTIM0
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: HRTIM2
|
||||
description: HRTIM0
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: HRTIM3
|
||||
description: HRTIM0
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Debug MCU Configuration Register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep Mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep Mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
fieldset/IDCODE:
|
||||
description: MCU Device ID Code Register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
|
||||
@ -1,191 +1,190 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDC
|
||||
description: Identity code
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDC
|
||||
- name: CR
|
||||
description: Configuration register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB3FZR1
|
||||
description: APB3 peripheral freeze register
|
||||
byte_offset: 52
|
||||
fieldset: APB3FZR1
|
||||
- name: APB1LFZR1
|
||||
description: APB1L peripheral freeze register
|
||||
byte_offset: 60
|
||||
fieldset: APB1LFZR1
|
||||
- name: APB2FZR1
|
||||
description: APB2 peripheral freeze register
|
||||
byte_offset: 76
|
||||
fieldset: APB2FZR1
|
||||
- name: APB4FZR1
|
||||
description: APB4 peripheral freeze register
|
||||
byte_offset: 84
|
||||
fieldset: APB4FZR1
|
||||
- name: IDC
|
||||
description: Identity code
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDC
|
||||
- name: CR
|
||||
description: Configuration register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB3FZR1
|
||||
description: APB3 peripheral freeze register
|
||||
byte_offset: 52
|
||||
fieldset: APB3FZR1
|
||||
- name: APB1LFZR1
|
||||
description: APB1L peripheral freeze register
|
||||
byte_offset: 60
|
||||
fieldset: APB1LFZR1
|
||||
- name: APB2FZR1
|
||||
description: APB2 peripheral freeze register
|
||||
byte_offset: 76
|
||||
fieldset: APB2FZR1
|
||||
- name: APB4FZR1
|
||||
description: APB4 peripheral freeze register
|
||||
byte_offset: 84
|
||||
fieldset: APB4FZR1
|
||||
fieldset/APB1LFZR1:
|
||||
description: APB1L peripheral freeze register
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: TIM2 stop in debug mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3 stop in debug mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4 stop in debug mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5 stop in debug mode
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6 stop in debug mode
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7 stop in debug mode
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM12
|
||||
description: TIM12 stop in debug mode
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM13
|
||||
description: TIM13 stop in debug mode
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14 stop in debug mode
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: LPTIM1 stop in debug mode
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout stop in debug mode
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2
|
||||
description: I2C2 SMBUS timeout stop in debug mode
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: I2C3 SMBUS timeout stop in debug mode
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: TIM2
|
||||
description: TIM2 stop in debug mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3 stop in debug mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4 stop in debug mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5 stop in debug mode
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6 stop in debug mode
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7 stop in debug mode
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM12
|
||||
description: TIM12 stop in debug mode
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM13
|
||||
description: TIM13 stop in debug mode
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14 stop in debug mode
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: LPTIM1 stop in debug mode
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout stop in debug mode
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2
|
||||
description: I2C2 SMBUS timeout stop in debug mode
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: I2C3 SMBUS timeout stop in debug mode
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR1:
|
||||
description: APB2 peripheral freeze register
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1 stop in debug mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8 stop in debug mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: TIM15 stop in debug mode
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16 stop in debug mode
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17 stop in debug mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: HRTIM
|
||||
description: HRTIM stop in debug mode
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: TIM1
|
||||
description: TIM1 stop in debug mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8 stop in debug mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: TIM15 stop in debug mode
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16 stop in debug mode
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17 stop in debug mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: HRTIM
|
||||
description: HRTIM stop in debug mode
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
fieldset/APB3FZR1:
|
||||
description: APB3 peripheral freeze register
|
||||
fields:
|
||||
- name: WWDG1
|
||||
description: WWDG1 stop in debug mode
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: WWDG1
|
||||
description: WWDG1 stop in debug mode
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/APB4FZR1:
|
||||
description: APB4 peripheral freeze register
|
||||
fields:
|
||||
- name: I2C4
|
||||
description: I2C4 SMBUS timeout stop in debug mode
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: LPTIM2
|
||||
description: LPTIM2 stop in debug mode
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: LPTIM3
|
||||
description: LPTIM3 stop in debug mode
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: LPTIM4
|
||||
description: LPTIM4 stop in debug mode
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: LPTIM5
|
||||
description: LPTIM5 stop in debug mode
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC stop in debug mode
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: IWDG1
|
||||
description: Independent watchdog for D1 stop in debug mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: I2C4
|
||||
description: I2C4 SMBUS timeout stop in debug mode
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: LPTIM2
|
||||
description: LPTIM2 stop in debug mode
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: LPTIM3
|
||||
description: LPTIM3 stop in debug mode
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: LPTIM4
|
||||
description: LPTIM4 stop in debug mode
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: LPTIM5
|
||||
description: LPTIM5 stop in debug mode
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC stop in debug mode
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: IWDG1
|
||||
description: Independent watchdog for D1 stop in debug mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Configuration register
|
||||
fields:
|
||||
- name: DBGSLEEP_D1
|
||||
description: Allow debug in D1 Sleep mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBGSTOP_D1
|
||||
description: Allow debug in D1 Stop mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBGSTBY_D1
|
||||
description: Allow debug in D1 Standby mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACECLKEN
|
||||
description: Trace clock enable enable
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: D1DBGCKEN
|
||||
description: D1 debug clock enable enable
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: D3DBGCKEN
|
||||
description: D3 debug clock enable enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TRGOEN
|
||||
description: External trigger output enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: DBGSLEEP_D1
|
||||
description: Allow debug in D1 Sleep mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBGSTOP_D1
|
||||
description: Allow debug in D1 Stop mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBGSTBY_D1
|
||||
description: Allow debug in D1 Standby mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACECLKEN
|
||||
description: Trace clock enable enable
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: D1DBGCKEN
|
||||
description: D1 debug clock enable enable
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: D3DBGCKEN
|
||||
description: D3 debug clock enable enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TRGOEN
|
||||
description: External trigger output enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
fieldset/IDC:
|
||||
description: Identity code
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision ID
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: DEV_ID
|
||||
description: Device ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision ID
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
|
||||
@ -1,93 +1,92 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR
|
||||
description: APB Low Freeze Register
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR
|
||||
- name: APB2FZR
|
||||
description: APB High Freeze Register
|
||||
byte_offset: 12
|
||||
fieldset: APB2FZR
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR
|
||||
description: APB Low Freeze Register
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR
|
||||
- name: APB2FZR
|
||||
description: APB High Freeze Register
|
||||
byte_offset: 12
|
||||
fieldset: APB2FZR
|
||||
fieldset/APB1FZR:
|
||||
description: APB Low Freeze Register
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: Debug Timer 2 stopped when Core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: Debug Timer 6 stopped when Core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: Debug RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Debug Window Wachdog stopped when Core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Debug Independent Wachdog stopped when Core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2
|
||||
description: I2C2 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: LPTIM
|
||||
description: LPTIM1 counter stopped when core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: TIM2
|
||||
description: Debug Timer 2 stopped when Core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: Debug Timer 6 stopped when Core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: Debug RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Debug Window Wachdog stopped when Core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Debug Independent Wachdog stopped when Core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2
|
||||
description: I2C2 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: LPTIM
|
||||
description: LPTIM1 counter stopped when core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: APB High Freeze Register
|
||||
fields:
|
||||
- name: TIM21
|
||||
description: Debug Timer 21 stopped when Core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM22
|
||||
description: Debug Timer 22 stopped when Core is halted
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM21
|
||||
description: Debug Timer 21 stopped when Core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM22
|
||||
description: Debug Timer 22 stopped when Core is halted
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Debug MCU Configuration Register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep Mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep Mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
fieldset/IDCODE:
|
||||
description: MCU Device ID Code Register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
|
||||
@ -1,117 +1,116 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: DBGMCU_IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU configuration register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1_FZ
|
||||
description: Debug MCU APB1 freeze register1
|
||||
byte_offset: 8
|
||||
fieldset: APB1_FZ
|
||||
- name: APB2_FZ
|
||||
description: Debug MCU APB1 freeze register 2
|
||||
byte_offset: 12
|
||||
fieldset: APB2_FZ
|
||||
- name: IDCODE
|
||||
description: DBGMCU_IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU configuration register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1_FZ
|
||||
description: Debug MCU APB1 freeze register1
|
||||
byte_offset: 8
|
||||
fieldset: APB1_FZ
|
||||
- name: APB2_FZ
|
||||
description: Debug MCU APB1 freeze register 2
|
||||
byte_offset: 12
|
||||
fieldset: APB2_FZ
|
||||
fieldset/APB1_FZ:
|
||||
description: Debug MCU APB1 freeze register1
|
||||
fields:
|
||||
- name: DBG_TIM2_STOP
|
||||
description: TIM2 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_TIM3_STOP
|
||||
description: TIM3 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_TIM4_STOP
|
||||
description: TIM4 counter stopped when core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: DBG_TIM5_STOP
|
||||
description: TIM5 counter stopped when core is halted
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DBG_TIM6_STOP
|
||||
description: TIM6 counter stopped when core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: DBG_TIM7_STOP
|
||||
description: TIM7 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: DBG_RTC_STOP
|
||||
description: Debug RTC stopped when core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DBG_WWDG_STOP
|
||||
description: Debug window watchdog stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DBG_IWDG_STOP
|
||||
description: Debug independent watchdog stopped when core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DBG_I2C1_SMBUS_TIMEOUT
|
||||
description: SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: DBG_I2C2_SMBUS_TIMEOUT
|
||||
description: SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: DBG_TIM2_STOP
|
||||
description: TIM2 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_TIM3_STOP
|
||||
description: TIM3 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_TIM4_STOP
|
||||
description: TIM4 counter stopped when core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: DBG_TIM5_STOP
|
||||
description: TIM5 counter stopped when core is halted
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DBG_TIM6_STOP
|
||||
description: TIM6 counter stopped when core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: DBG_TIM7_STOP
|
||||
description: TIM7 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: DBG_RTC_STOP
|
||||
description: Debug RTC stopped when core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DBG_WWDG_STOP
|
||||
description: Debug window watchdog stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DBG_IWDG_STOP
|
||||
description: Debug independent watchdog stopped when core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DBG_I2C1_SMBUS_TIMEOUT
|
||||
description: SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: DBG_I2C2_SMBUS_TIMEOUT
|
||||
description: SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
fieldset/APB2_FZ:
|
||||
description: Debug MCU APB1 freeze register 2
|
||||
fields:
|
||||
- name: DBG_TIM9_STOP
|
||||
description: TIM counter stopped when core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: DBG_TIM10_STOP
|
||||
description: TIM counter stopped when core is halted
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DBG_TIM11_STOP
|
||||
description: TIM counter stopped when core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: DBG_TIM9_STOP
|
||||
description: TIM counter stopped when core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: DBG_TIM10_STOP
|
||||
description: TIM counter stopped when core is halted
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DBG_TIM11_STOP
|
||||
description: TIM counter stopped when core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Debug MCU configuration register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
fieldset/IDCODE:
|
||||
description: DBGMCU_IDCODE
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device identifier
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision identifie
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: DEV_ID
|
||||
description: Device identifier
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision identifie
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
|
||||
@ -1,148 +1,147 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: MCU debug component
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: DBGMCU_IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU configuration register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR1
|
||||
description: Debug MCU APB1 freeze register1
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR1
|
||||
- name: APB1FZR2
|
||||
description: Debug MCU APB1 freeze register 2
|
||||
byte_offset: 12
|
||||
fieldset: APB1FZR2
|
||||
- name: APB2FZR
|
||||
description: Debug MCU APB2 freeze register
|
||||
byte_offset: 16
|
||||
fieldset: APB2FZR
|
||||
- name: IDCODE
|
||||
description: DBGMCU_IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU configuration register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR1
|
||||
description: Debug MCU APB1 freeze register1
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR1
|
||||
- name: APB1FZR2
|
||||
description: Debug MCU APB1 freeze register 2
|
||||
byte_offset: 12
|
||||
fieldset: APB1FZR2
|
||||
- name: APB2FZR
|
||||
description: Debug MCU APB2 freeze register
|
||||
byte_offset: 16
|
||||
fieldset: APB2FZR
|
||||
fieldset/APB1FZR1:
|
||||
description: Debug MCU APB1 freeze register1
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: TIM2 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4 counter stopped when core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5 counter stopped when core is halted
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6 counter stopped when core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC counter stopped when core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Window watchdog counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Independent watchdog counter stopped when core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout counter stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2
|
||||
description: I2C2 SMBUS timeout counter stopped when core is halted
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: I2C3 SMBUS timeout counter stopped when core is halted
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: CAN
|
||||
description: bxCAN stopped when core is halted
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: LPTIM1 counter stopped when core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: TIM2
|
||||
description: TIM2 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4 counter stopped when core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5 counter stopped when core is halted
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6 counter stopped when core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC counter stopped when core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Window watchdog counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Independent watchdog counter stopped when core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout counter stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2
|
||||
description: I2C2 SMBUS timeout counter stopped when core is halted
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: I2C3 SMBUS timeout counter stopped when core is halted
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: CAN
|
||||
description: bxCAN stopped when core is halted
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: LPTIM1 counter stopped when core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/APB1FZR2:
|
||||
description: Debug MCU APB1 freeze register 2
|
||||
fields:
|
||||
- name: LPTIM2
|
||||
description: LPTIM2 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: LPTIM2
|
||||
description: LPTIM2 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: Debug MCU APB2 freeze register
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8 counter stopped when core is halted
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: TIM15 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8 counter stopped when core is halted
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: TIM15 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Debug MCU configuration register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
fieldset/IDCODE:
|
||||
description: DBGMCU_IDCODE
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device identifier
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: REV_ID
|
||||
description: Revision identifie
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: DEV_ID
|
||||
description: Device identifier
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: REV_ID
|
||||
description: Revision identifie
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
|
||||
@ -1,429 +1,428 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: MCU debug component
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: DBGMCU_IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: "Debug MCU configuration\r register"
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1LFZR
|
||||
description: "Debug MCU APB1L peripheral freeze\r register"
|
||||
byte_offset: 8
|
||||
fieldset: APB1LFZR
|
||||
- name: APB1HFZR
|
||||
description: Debug MCU APB1H peripheral freeze register
|
||||
byte_offset: 12
|
||||
fieldset: APB1HFZR
|
||||
- name: APB2FZR
|
||||
description: Debug MCU APB2 peripheral freeze register
|
||||
byte_offset: 16
|
||||
fieldset: APB2FZR
|
||||
- name: APB3FZR
|
||||
description: Debug MCU APB3 peripheral freeze register
|
||||
byte_offset: 20
|
||||
fieldset: APB3FZR
|
||||
- name: AHB1FZR
|
||||
description: Debug MCU AHB1 peripheral freeze register
|
||||
byte_offset: 32
|
||||
fieldset: AHB1FZR
|
||||
- name: AHB3FZR
|
||||
description: Debug MCU AHB3 peripheral freeze register
|
||||
byte_offset: 40
|
||||
fieldset: AHB3FZR
|
||||
- name: DBGMCU_SR
|
||||
description: DBGMCU status register
|
||||
byte_offset: 252
|
||||
access: Read
|
||||
fieldset: DBGMCU_SR
|
||||
- name: DBGMCU_DBG_AUTH_HOST
|
||||
description: DBGMCU debug host authentication register
|
||||
byte_offset: 256
|
||||
access: Read
|
||||
fieldset: DBGMCU_DBG_AUTH_HOST
|
||||
- name: DBGMCU_DBG_AUTH_DEVICE
|
||||
description: DBGMCU debug device authentication register
|
||||
byte_offset: 260
|
||||
access: Read
|
||||
fieldset: DBGMCU_DBG_AUTH_DEVICE
|
||||
- name: PIDR4
|
||||
description: Debug MCU CoreSight peripheral identity register 4
|
||||
byte_offset: 4048
|
||||
access: Read
|
||||
fieldset: PIDR4
|
||||
- name: PIDR0
|
||||
description: Debug MCU CoreSight peripheral identity register 0
|
||||
byte_offset: 4064
|
||||
access: Read
|
||||
fieldset: PIDR0
|
||||
- name: PIDR1
|
||||
description: Debug MCU CoreSight peripheral identity register 1
|
||||
byte_offset: 4068
|
||||
access: Read
|
||||
fieldset: PIDR1
|
||||
- name: PIDR2
|
||||
description: Debug MCU CoreSight peripheral identity register 2
|
||||
byte_offset: 4072
|
||||
access: Read
|
||||
fieldset: PIDR2
|
||||
- name: PIDR3
|
||||
description: Debug MCU CoreSight peripheral identity register 3
|
||||
byte_offset: 4076
|
||||
access: Read
|
||||
fieldset: PIDR3
|
||||
- name: CIDR0
|
||||
description: Debug MCU CoreSight component identity register 0
|
||||
byte_offset: 4080
|
||||
access: Read
|
||||
fieldset: CIDR0
|
||||
- name: CIDR1
|
||||
description: Debug MCU CoreSight component identity register 1
|
||||
byte_offset: 4084
|
||||
access: Read
|
||||
fieldset: CIDR1
|
||||
- name: CIDR2
|
||||
description: Debug MCU CoreSight component identity register 2
|
||||
byte_offset: 4088
|
||||
access: Read
|
||||
fieldset: CIDR2
|
||||
- name: CIDR3
|
||||
description: Debug MCU CoreSight component identity register 3
|
||||
byte_offset: 4092
|
||||
access: Read
|
||||
fieldset: CIDR3
|
||||
- name: IDCODE
|
||||
description: DBGMCU_IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: "Debug MCU configuration\r register"
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1LFZR
|
||||
description: "Debug MCU APB1L peripheral freeze\r register"
|
||||
byte_offset: 8
|
||||
fieldset: APB1LFZR
|
||||
- name: APB1HFZR
|
||||
description: Debug MCU APB1H peripheral freeze register
|
||||
byte_offset: 12
|
||||
fieldset: APB1HFZR
|
||||
- name: APB2FZR
|
||||
description: Debug MCU APB2 peripheral freeze register
|
||||
byte_offset: 16
|
||||
fieldset: APB2FZR
|
||||
- name: APB3FZR
|
||||
description: Debug MCU APB3 peripheral freeze register
|
||||
byte_offset: 20
|
||||
fieldset: APB3FZR
|
||||
- name: AHB1FZR
|
||||
description: Debug MCU AHB1 peripheral freeze register
|
||||
byte_offset: 32
|
||||
fieldset: AHB1FZR
|
||||
- name: AHB3FZR
|
||||
description: Debug MCU AHB3 peripheral freeze register
|
||||
byte_offset: 40
|
||||
fieldset: AHB3FZR
|
||||
- name: DBGMCU_SR
|
||||
description: DBGMCU status register
|
||||
byte_offset: 252
|
||||
access: Read
|
||||
fieldset: DBGMCU_SR
|
||||
- name: DBGMCU_DBG_AUTH_HOST
|
||||
description: DBGMCU debug host authentication register
|
||||
byte_offset: 256
|
||||
access: Read
|
||||
fieldset: DBGMCU_DBG_AUTH_HOST
|
||||
- name: DBGMCU_DBG_AUTH_DEVICE
|
||||
description: DBGMCU debug device authentication register
|
||||
byte_offset: 260
|
||||
access: Read
|
||||
fieldset: DBGMCU_DBG_AUTH_DEVICE
|
||||
- name: PIDR4
|
||||
description: Debug MCU CoreSight peripheral identity register 4
|
||||
byte_offset: 4048
|
||||
access: Read
|
||||
fieldset: PIDR4
|
||||
- name: PIDR0
|
||||
description: Debug MCU CoreSight peripheral identity register 0
|
||||
byte_offset: 4064
|
||||
access: Read
|
||||
fieldset: PIDR0
|
||||
- name: PIDR1
|
||||
description: Debug MCU CoreSight peripheral identity register 1
|
||||
byte_offset: 4068
|
||||
access: Read
|
||||
fieldset: PIDR1
|
||||
- name: PIDR2
|
||||
description: Debug MCU CoreSight peripheral identity register 2
|
||||
byte_offset: 4072
|
||||
access: Read
|
||||
fieldset: PIDR2
|
||||
- name: PIDR3
|
||||
description: Debug MCU CoreSight peripheral identity register 3
|
||||
byte_offset: 4076
|
||||
access: Read
|
||||
fieldset: PIDR3
|
||||
- name: CIDR0
|
||||
description: Debug MCU CoreSight component identity register 0
|
||||
byte_offset: 4080
|
||||
access: Read
|
||||
fieldset: CIDR0
|
||||
- name: CIDR1
|
||||
description: Debug MCU CoreSight component identity register 1
|
||||
byte_offset: 4084
|
||||
access: Read
|
||||
fieldset: CIDR1
|
||||
- name: CIDR2
|
||||
description: Debug MCU CoreSight component identity register 2
|
||||
byte_offset: 4088
|
||||
access: Read
|
||||
fieldset: CIDR2
|
||||
- name: CIDR3
|
||||
description: Debug MCU CoreSight component identity register 3
|
||||
byte_offset: 4092
|
||||
access: Read
|
||||
fieldset: CIDR3
|
||||
fieldset/AHB1FZR:
|
||||
description: Debug MCU AHB1 peripheral freeze register
|
||||
fields:
|
||||
- name: DBG_GPDMA0_STOP
|
||||
description: GPDMA channel 0 stop in debug
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA1_STOP
|
||||
description: GPDMA channel 1 stop in debug
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA2_STOP
|
||||
description: GPDMA channel 2 stop in debug
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA3_STOP
|
||||
description: GPDMA channel 3 stop in debug
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA4_STOP
|
||||
description: GPDMA channel 4 stop in debug
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA5_STOP
|
||||
description: GPDMA channel 5 stop in debug
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA6_STOP
|
||||
description: GPDMA channel 6 stop in debug
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA7_STOP
|
||||
description: GPDMA channel 7 stop in debug
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA8_STOP
|
||||
description: GPDMA channel 8 stop in debug
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA9_STOP
|
||||
description: GPDMA channel 9 stop in debug
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA10_STOP
|
||||
description: GPDMA channel 10 stop in debug
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA11_STOP
|
||||
description: GPDMA channel 11 stop in debug
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA12_STOP
|
||||
description: GPDMA channel 12 stop in debug
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA13_STOP
|
||||
description: GPDMA channel 13 stop in debug
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA14_STOP
|
||||
description: GPDMA channel 14 stop in debug
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA15_STOP
|
||||
description: GPDMA channel 15 stop in debug
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA0_STOP
|
||||
description: GPDMA channel 0 stop in debug
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA1_STOP
|
||||
description: GPDMA channel 1 stop in debug
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA2_STOP
|
||||
description: GPDMA channel 2 stop in debug
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA3_STOP
|
||||
description: GPDMA channel 3 stop in debug
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA4_STOP
|
||||
description: GPDMA channel 4 stop in debug
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA5_STOP
|
||||
description: GPDMA channel 5 stop in debug
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA6_STOP
|
||||
description: GPDMA channel 6 stop in debug
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA7_STOP
|
||||
description: GPDMA channel 7 stop in debug
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA8_STOP
|
||||
description: GPDMA channel 8 stop in debug
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA9_STOP
|
||||
description: GPDMA channel 9 stop in debug
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA10_STOP
|
||||
description: GPDMA channel 10 stop in debug
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA11_STOP
|
||||
description: GPDMA channel 11 stop in debug
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA12_STOP
|
||||
description: GPDMA channel 12 stop in debug
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA13_STOP
|
||||
description: GPDMA channel 13 stop in debug
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA14_STOP
|
||||
description: GPDMA channel 14 stop in debug
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA15_STOP
|
||||
description: GPDMA channel 15 stop in debug
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
fieldset/AHB3FZR:
|
||||
description: Debug MCU AHB3 peripheral freeze register
|
||||
fields:
|
||||
- name: DBG_LPDMA0_STOP
|
||||
description: LPDMA channel 0 stop in debug
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_LPDMA1_STOP
|
||||
description: LPDMA channel 1 stop in debug
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_LPDMA2_STOP
|
||||
description: LPDMA channel 2 stop in debug
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: DBG_LPDMA3_STOP
|
||||
description: LPDMA channel 3 stop in debug
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DBG_LPDMA0_STOP
|
||||
description: LPDMA channel 0 stop in debug
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_LPDMA1_STOP
|
||||
description: LPDMA channel 1 stop in debug
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_LPDMA2_STOP
|
||||
description: LPDMA channel 2 stop in debug
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: DBG_LPDMA3_STOP
|
||||
description: LPDMA channel 3 stop in debug
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
fieldset/APB1HFZR:
|
||||
description: Debug MCU APB1H peripheral freeze register
|
||||
fields:
|
||||
- name: DBG_I2C4_STOP
|
||||
description: I2C4 stop in debug
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_LPTIM2_STOP
|
||||
description: LPTIM2 stop in debug
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: DBG_I2C4_STOP
|
||||
description: I2C4 stop in debug
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_LPTIM2_STOP
|
||||
description: LPTIM2 stop in debug
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/APB1LFZR:
|
||||
description: "Debug MCU APB1L peripheral freeze\r register"
|
||||
fields:
|
||||
- name: DBG_TIM2_STOP
|
||||
description: TIM2 stop in debug
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_TIM3_STOP
|
||||
description: TIM3 stop in debug
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_TIM4_STOP
|
||||
description: TIM4 stop in debug
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: DBG_TIM5_STOP
|
||||
description: TIM5 stop in debug
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DBG_TIM6_STOP
|
||||
description: TIM6 stop in debug
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: DBG_TIM7_STOP
|
||||
description: TIM7 stop in debug
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: DBG_WWDG_STOP
|
||||
description: Window watchdog counter stop in debug
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DBG_IWDG_STOP
|
||||
description: Independent watchdog counter stop in debug
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DBG_I2C1_STOP
|
||||
description: I2C1 SMBUS timeout stop in debug
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: DBG_I2C2_STOP
|
||||
description: I2C2 SMBUS timeout stop in debug
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: DBG_TIM2_STOP
|
||||
description: TIM2 stop in debug
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_TIM3_STOP
|
||||
description: TIM3 stop in debug
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_TIM4_STOP
|
||||
description: TIM4 stop in debug
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: DBG_TIM5_STOP
|
||||
description: TIM5 stop in debug
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DBG_TIM6_STOP
|
||||
description: TIM6 stop in debug
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: DBG_TIM7_STOP
|
||||
description: TIM7 stop in debug
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: DBG_WWDG_STOP
|
||||
description: Window watchdog counter stop in debug
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DBG_IWDG_STOP
|
||||
description: Independent watchdog counter stop in debug
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DBG_I2C1_STOP
|
||||
description: I2C1 SMBUS timeout stop in debug
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: DBG_I2C2_STOP
|
||||
description: I2C2 SMBUS timeout stop in debug
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: Debug MCU APB2 peripheral freeze register
|
||||
fields:
|
||||
- name: DBG_TIM1_STOP
|
||||
description: "TIM1 counter stopped when core is\r halted"
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DBG_TIM8_STOP
|
||||
description: TIM8 stop in debug
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: DBG_TIM15_STOP
|
||||
description: "TIM15 counter stopped when core is\r halted"
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: DBG_TIM16_STOP
|
||||
description: "TIM16 counter stopped when core is\r halted"
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: DBG_TIM17_STOP
|
||||
description: DBG_TIM17_STOP
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: DBG_TIM1_STOP
|
||||
description: "TIM1 counter stopped when core is\r halted"
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DBG_TIM8_STOP
|
||||
description: TIM8 stop in debug
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: DBG_TIM15_STOP
|
||||
description: "TIM15 counter stopped when core is\r halted"
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: DBG_TIM16_STOP
|
||||
description: "TIM16 counter stopped when core is\r halted"
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: DBG_TIM17_STOP
|
||||
description: DBG_TIM17_STOP
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/APB3FZR:
|
||||
description: Debug MCU APB3 peripheral freeze register
|
||||
fields:
|
||||
- name: DBG_I2C3_STOP
|
||||
description: I2C3 stop in debug
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DBG_LPTIM1_STOP
|
||||
description: LPTIM1 stop in debug
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: DBG_LPTIM3_STOP
|
||||
description: LPTIM3 stop in debug
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: DBG_LPTIM4_STOP
|
||||
description: LPTIM4 stop in debug
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: DBG_RTC_STOP
|
||||
description: RTC stop in debug
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: DBG_I2C3_STOP
|
||||
description: I2C3 stop in debug
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DBG_LPTIM1_STOP
|
||||
description: LPTIM1 stop in debug
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: DBG_LPTIM3_STOP
|
||||
description: LPTIM3 stop in debug
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: DBG_LPTIM4_STOP
|
||||
description: LPTIM4 stop in debug
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: DBG_RTC_STOP
|
||||
description: RTC stop in debug
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
fieldset/CIDR0:
|
||||
description: Debug MCU CoreSight component identity register 0
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: "component identification bits [7:0]"
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: PREAMBLE
|
||||
description: component identification bits [7:0]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/CIDR1:
|
||||
description: Debug MCU CoreSight component identity register 1
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: "component identification bits [11:8]"
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: CLASS
|
||||
description: "component identification bits [15:12] - component class"
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
- name: PREAMBLE
|
||||
description: component identification bits [11:8]
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: CLASS
|
||||
description: component identification bits [15:12] - component class
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/CIDR2:
|
||||
description: Debug MCU CoreSight component identity register 2
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: "component identification bits [23:16]"
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: PREAMBLE
|
||||
description: component identification bits [23:16]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/CIDR3:
|
||||
description: Debug MCU CoreSight component identity register 3
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: "component identification bits [31:24]"
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: PREAMBLE
|
||||
description: component identification bits [31:24]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/CR:
|
||||
description: "Debug MCU configuration\r register"
|
||||
fields:
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: "Trace pin assignment\r control"
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TRACE_EN
|
||||
description: "trace port and clock\r enable"
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: "Trace pin assignment\r control"
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: "Trace pin assignment\r control"
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TRACE_EN
|
||||
description: "trace port and clock\r enable"
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: "Trace pin assignment\r control"
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
fieldset/DBGMCU_DBG_AUTH_DEVICE:
|
||||
description: DBGMCU debug device authentication register
|
||||
fields:
|
||||
- name: AUTH_ID
|
||||
description: "Device specific ID\r \tDevice specific ID used for RDP regression."
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: AUTH_ID
|
||||
description: "Device specific ID\r \tDevice specific ID used for RDP regression."
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/DBGMCU_DBG_AUTH_HOST:
|
||||
description: DBGMCU debug host authentication register
|
||||
fields:
|
||||
- name: AUTH_KEY
|
||||
description: "Device authentication key\r \tThe device specific 64-bit authentication key (OEM key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory."
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: AUTH_KEY
|
||||
description: "Device authentication key\r \tThe device specific 64-bit authentication key (OEM key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory."
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/DBGMCU_SR:
|
||||
description: DBGMCU status register
|
||||
fields:
|
||||
- name: AP_PRESENT
|
||||
description: "Bit n identifies whether access port AP n is present in device\r \tBit n = 0: APn absent\r \tBit n = 1: APn present"
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: AP_LOCKED
|
||||
description: "DECLARATION TO BE CONFIRMED by PRODUCT OWNER! Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked)\r \tBit n = 0: APn locked\r \tBit n = 1: APn enabled"
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: AP_PRESENT
|
||||
description: "Bit n identifies whether access port AP n is present in device\r \tBit n = 0: APn absent\r \tBit n = 1: APn present"
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: AP_LOCKED
|
||||
description: "DECLARATION TO BE CONFIRMED by PRODUCT OWNER! Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked)\r \tBit n = 0: APn locked\r \tBit n = 1: APn enabled"
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
fieldset/IDCODE:
|
||||
description: DBGMCU_IDCODE
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device dentification
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: DEV_ID
|
||||
description: Device dentification
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/PIDR0:
|
||||
description: Debug MCU CoreSight peripheral identity register 0
|
||||
fields:
|
||||
- name: PARTNUM
|
||||
description: "part number bits [7:0]"
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: PARTNUM
|
||||
description: part number bits [7:0]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/PIDR1:
|
||||
description: Debug MCU CoreSight peripheral identity register 1
|
||||
fields:
|
||||
- name: PARTNUM
|
||||
description: "part number bits [11:8]"
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: JEP106ID
|
||||
description: "JEP106 identity code bits [3:0]"
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
- name: PARTNUM
|
||||
description: part number bits [11:8]
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: JEP106ID
|
||||
description: JEP106 identity code bits [3:0]
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/PIDR2:
|
||||
description: Debug MCU CoreSight peripheral identity register 2
|
||||
fields:
|
||||
- name: JEP106ID
|
||||
description: "JEP106 identity code bits [6:4]"
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
- name: JEDEC
|
||||
description: JEDEC assigned value
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: REVISION
|
||||
description: component revision number
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
- name: JEP106ID
|
||||
description: JEP106 identity code bits [6:4]
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
- name: JEDEC
|
||||
description: JEDEC assigned value
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: REVISION
|
||||
description: component revision number
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/PIDR3:
|
||||
description: Debug MCU CoreSight peripheral identity register 3
|
||||
fields:
|
||||
- name: CMOD
|
||||
description: customer modified
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: REVAND
|
||||
description: metal fix version
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
- name: CMOD
|
||||
description: customer modified
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: REVAND
|
||||
description: metal fix version
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/PIDR4:
|
||||
description: Debug MCU CoreSight peripheral identity register 4
|
||||
fields:
|
||||
- name: JEP106CON
|
||||
description: JEP106 continuation code
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: KCOUNT_4
|
||||
description: register file size
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
- name: JEP106CON
|
||||
description: JEP106 continuation code
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: KCOUNT_4
|
||||
description: register file size
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
|
||||
@ -1,173 +1,172 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR1
|
||||
description: APB1 Low Freeze Register CPU1
|
||||
byte_offset: 60
|
||||
fieldset: APB1FZR1
|
||||
- name: C2AP_B1FZR1
|
||||
description: APB1 Low Freeze Register CPU2
|
||||
byte_offset: 64
|
||||
fieldset: C2AP_B1FZR1
|
||||
- name: APB1FZR2
|
||||
description: APB1 High Freeze Register CPU1
|
||||
byte_offset: 68
|
||||
fieldset: APB1FZR2
|
||||
- name: C2APB1FZR2
|
||||
description: APB1 High Freeze Register CPU2
|
||||
byte_offset: 72
|
||||
fieldset: C2APB1FZR2
|
||||
- name: C2APB2FZR
|
||||
description: APB2 Freeze Register CPU2
|
||||
byte_offset: 72
|
||||
fieldset: C2APB2FZR
|
||||
- name: APB2FZR
|
||||
description: APB2 Freeze Register CPU1
|
||||
byte_offset: 76
|
||||
fieldset: APB2FZR
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR1
|
||||
description: APB1 Low Freeze Register CPU1
|
||||
byte_offset: 60
|
||||
fieldset: APB1FZR1
|
||||
- name: C2AP_B1FZR1
|
||||
description: APB1 Low Freeze Register CPU2
|
||||
byte_offset: 64
|
||||
fieldset: C2AP_B1FZR1
|
||||
- name: APB1FZR2
|
||||
description: APB1 High Freeze Register CPU1
|
||||
byte_offset: 68
|
||||
fieldset: APB1FZR2
|
||||
- name: C2APB1FZR2
|
||||
description: APB1 High Freeze Register CPU2
|
||||
byte_offset: 72
|
||||
fieldset: C2APB1FZR2
|
||||
- name: C2APB2FZR
|
||||
description: APB2 Freeze Register CPU2
|
||||
byte_offset: 72
|
||||
fieldset: C2APB2FZR
|
||||
- name: APB2FZR
|
||||
description: APB2 Freeze Register CPU1
|
||||
byte_offset: 76
|
||||
fieldset: APB2FZR
|
||||
fieldset/APB1FZR1:
|
||||
description: APB1 Low Freeze Register CPU1
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: Debug Timer 2 stopped when Core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC counter stopped when core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: WWDG counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDG counter stopped when core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: Debug I2C1 SMBUS timeout stopped when Core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: Debug I2C3 SMBUS timeout stopped when core is halted
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: Debug LPTIM1 stopped when Core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: TIM2
|
||||
description: Debug Timer 2 stopped when Core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC counter stopped when core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: WWDG counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDG counter stopped when core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: Debug I2C1 SMBUS timeout stopped when Core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: Debug I2C3 SMBUS timeout stopped when core is halted
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: Debug LPTIM1 stopped when Core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/APB1FZR2:
|
||||
description: APB1 High Freeze Register CPU1
|
||||
fields:
|
||||
- name: LPTIM2
|
||||
description: LPTIM2 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: LPTIM2
|
||||
description: LPTIM2 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: APB2 Freeze Register CPU1
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/C2APB1FZR2:
|
||||
description: APB1 High Freeze Register CPU2
|
||||
fields:
|
||||
- name: LPTIM2
|
||||
description: LPTIM2 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: LPTIM2
|
||||
description: LPTIM2 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/C2APB2FZR:
|
||||
description: APB2 Freeze Register CPU2
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/C2AP_B1FZR1:
|
||||
description: APB1 Low Freeze Register CPU2
|
||||
fields:
|
||||
- name: LPTIM2
|
||||
description: LPTIM2 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC counter stopped when core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDG stopped when core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: I2C3 SMBUS timeout stopped when core is halted
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: LPTIM1 counter stopped when core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: LPTIM2
|
||||
description: LPTIM2 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC counter stopped when core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDG stopped when core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: I2C3 SMBUS timeout stopped when core is halted
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: LPTIM1 counter stopped when core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Debug MCU Configuration Register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep Mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: Trace port and clock enable
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRGOEN
|
||||
description: External trigger output enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep Mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: Trace port and clock enable
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRGOEN
|
||||
description: External trigger output enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
fieldset/IDCODE:
|
||||
description: MCU Device ID Code Register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
|
||||
339
data/registers/dbgmcu_wba.yaml
Normal file
339
data/registers/dbgmcu_wba.yaml
Normal file
@ -0,0 +1,339 @@
|
||||
block/DBGMCU:
|
||||
description: Microcontroller debug unit
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: identity code register
|
||||
byte_offset: 0
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: status and configuration register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1LFZR
|
||||
description: APB1L peripheral freeze register
|
||||
byte_offset: 8
|
||||
fieldset: APB1LFZR
|
||||
- name: APB1HFZR
|
||||
description: APB1H peripheral freeze register
|
||||
byte_offset: 12
|
||||
fieldset: APB1HFZR
|
||||
- name: APB2FZR
|
||||
description: APB2 peripheral freeze register
|
||||
byte_offset: 16
|
||||
fieldset: APB2FZR
|
||||
- name: APB7FZR
|
||||
description: APB7 peripheral freeze register
|
||||
byte_offset: 36
|
||||
fieldset: APB7FZR
|
||||
- name: AHB1FZR
|
||||
description: AHB1 peripheral freeze register
|
||||
byte_offset: 40
|
||||
fieldset: AHB1FZR
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 252
|
||||
fieldset: SR
|
||||
- name: DBG_AUTH_HOST
|
||||
description: debug host authentication register
|
||||
byte_offset: 256
|
||||
fieldset: DBG_AUTH_HOST
|
||||
- name: DBG_AUTH_DEVICE
|
||||
description: debug device authentication register
|
||||
byte_offset: 260
|
||||
fieldset: DBG_AUTH_DEVICE
|
||||
- name: PNCR
|
||||
description: part number codification register
|
||||
byte_offset: 2012
|
||||
fieldset: PNCR
|
||||
- name: PIDR4
|
||||
description: CoreSight peripheral identity register 4
|
||||
byte_offset: 4048
|
||||
fieldset: PIDR4
|
||||
- name: PIDR0
|
||||
description: CoreSight peripheral identity register 0
|
||||
byte_offset: 4064
|
||||
fieldset: PIDR0
|
||||
- name: PIDR1
|
||||
description: CoreSight peripheral identity register 1
|
||||
byte_offset: 4068
|
||||
fieldset: PIDR1
|
||||
- name: PIDR2
|
||||
description: CoreSight peripheral identity register 2
|
||||
byte_offset: 4072
|
||||
fieldset: PIDR2
|
||||
- name: PIDR3
|
||||
description: CoreSight peripheral identity register 3
|
||||
byte_offset: 4076
|
||||
fieldset: PIDR3
|
||||
- name: CIDR0
|
||||
description: CoreSight component identity register 0
|
||||
byte_offset: 4080
|
||||
fieldset: CIDR0
|
||||
- name: CIDR1
|
||||
description: CoreSight peripheral identity register 1
|
||||
byte_offset: 4084
|
||||
fieldset: CIDR1
|
||||
- name: CIDR2
|
||||
description: CoreSight component identity register 2
|
||||
byte_offset: 4088
|
||||
fieldset: CIDR2
|
||||
- name: CIDR3
|
||||
description: CoreSight component identity register 3
|
||||
byte_offset: 4092
|
||||
fieldset: CIDR3
|
||||
fieldset/AHB1FZR:
|
||||
description: AHB1 peripheral freeze register
|
||||
fields:
|
||||
- name: DBG_GPDMA1_CH0_STOP
|
||||
description: "GPDMA 1 channel 0 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC0."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA1_CH1_STOP
|
||||
description: "GPDMA 1 channel 1 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC1."
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA1_CH2_STOP
|
||||
description: "GPDMA 1 channel 2 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC2."
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA1_CH3_STOP
|
||||
description: "GPDMA 1 channel 3 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC3."
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA1_CH4_STOP
|
||||
description: "GPDMA 1 channel 4 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC4."
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA1_CH5_STOP
|
||||
description: "GPDMA 1 channel 5 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC5."
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA1_CH6_STOP
|
||||
description: "GPDMA 1 channel 6 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC6."
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA1_CH7_STOP
|
||||
description: "GPDMA 1 channel 7 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC7."
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
fieldset/APB1HFZR:
|
||||
description: APB1H peripheral freeze register
|
||||
fields:
|
||||
- name: DBG_LPTIM2_STOP
|
||||
description: "LPTIM2 stop in CPU debug\r Write access can be protected by GTZC_TZSC.LPTIM2SEC."
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/APB1LFZR:
|
||||
description: APB1L peripheral freeze register
|
||||
fields:
|
||||
- name: DBG_TIM2_STOP
|
||||
description: "TIM2 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM2SEC."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_TIM3_STOP
|
||||
description: "TIM3 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM3SEC."
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_WWDG_STOP
|
||||
description: "WWDG stop in CPU debug\r Write access can be protected by GTZC_TZSC.WWDGSEC"
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DBG_IWDG_STOP
|
||||
description: "IWDG stop in CPU debug\r Write access can be protected by GTZC_TZSC.IWDGSEC."
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DBG_I2C1_STOP
|
||||
description: "I2C1 SMBUS timeout stop in CPU debug\r Write access can be protected by GTZC_TZSC.I2C1SEC."
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: APB2 peripheral freeze register
|
||||
fields:
|
||||
- name: DBG_TIM1_STOP
|
||||
description: "TIM1 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM1SEC."
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DBG_TIM16_STOP
|
||||
description: "TIM16 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM16SEC."
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: DBG_TIM17_STOP
|
||||
description: "TIM17 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM17SEC."
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/APB7FZR:
|
||||
description: APB7 peripheral freeze register
|
||||
fields:
|
||||
- name: DBG_I2C3_STOP
|
||||
description: "I2C3 stop in CPU debug\r Access can be protected by GTZC_TZSC.I2C3SEC."
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DBG_LPTIM1_STOP
|
||||
description: "LPTIM1 stop in CPU debug\r Access can be protected by GTZC_TZSC.LPTIM1SEC."
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: DBG_RTC_STOP
|
||||
description: "RTC stop in CPU debug\r Access can be protected by GTZC_TZSC.TIM17SEC.\r Can only be accessed secure when one or more features in the RTC or TAMP is/are secure."
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
fieldset/CIDR0:
|
||||
description: CoreSight component identity register 0
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: Component ID bits [7:0]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/CIDR1:
|
||||
description: CoreSight peripheral identity register 1
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: Component ID bits [11:8]
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: CLASS
|
||||
description: Component ID bits [15:12] - component class
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/CIDR2:
|
||||
description: CoreSight component identity register 2
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: Component ID bits [23:16]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/CIDR3:
|
||||
description: CoreSight component identity register 3
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: Component ID bits [31:24]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/CR:
|
||||
description: status and configuration register
|
||||
fields:
|
||||
- name: DBG_STOP
|
||||
description: "Allows debug in Stop mode\r Write access can be protected by PWR_SECCFGR.LPMSEC.\r The CPU debug and clocks remain active and the HSI16 oscillators is used as system clock during Stop debug mode, allowing CPU debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state."
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: "Allows debug in Standby mode\r Write access can be protected by PWR_SECCFGR.LPMSEC.\r The CPU debug and clocks remain active and the HSI16 oscillator is used as system clock, the supply and SRAM memory content is maintained during Standby debug mode, allowing CPU debug capability. On exit from Standby mode, a standby reset is performed."
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: LPMS
|
||||
description: "Device low power mode selected\r 10x: Standby mode\r others reserved"
|
||||
bit_offset: 16
|
||||
bit_size: 3
|
||||
- name: STOPF
|
||||
description: Device Stop flag
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: SBF
|
||||
description: Device Standby flag
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: CS
|
||||
description: CPU Sleep
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: CDS
|
||||
description: CPU DeepSleep
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
fieldset/DBG_AUTH_DEVICE:
|
||||
description: debug device authentication register
|
||||
fields:
|
||||
- name: AUTH_ID
|
||||
description: "Device specific ID\r Device specific ID used for RDP regression."
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/DBG_AUTH_HOST:
|
||||
description: debug host authentication register
|
||||
fields:
|
||||
- name: AUTH_KEY
|
||||
description: "Device authentication key\r The device specific 64-bit authentication key (OEMn key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory."
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/IDCODE:
|
||||
description: identity code register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision ID
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/PIDR0:
|
||||
description: CoreSight peripheral identity register 0
|
||||
fields:
|
||||
- name: PARTNUM
|
||||
description: Part number bits [7:0]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/PIDR1:
|
||||
description: CoreSight peripheral identity register 1
|
||||
fields:
|
||||
- name: PARTNUM
|
||||
description: Part number bits [11:8]
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: JEP106ID
|
||||
description: JEP106 identity code bits [3:0]
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/PIDR2:
|
||||
description: CoreSight peripheral identity register 2
|
||||
fields:
|
||||
- name: JEP106ID
|
||||
description: JEP106 identity code bits [6:4]
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
- name: JEDEC
|
||||
description: JEDEC assigned value
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: REVISION
|
||||
description: Component revision number
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/PIDR3:
|
||||
description: CoreSight peripheral identity register 3
|
||||
fields:
|
||||
- name: CMOD
|
||||
description: Customer modified
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: REVAND
|
||||
description: Metal fix version
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/PIDR4:
|
||||
description: CoreSight peripheral identity register 4
|
||||
fields:
|
||||
- name: JEP106CON
|
||||
description: JEP106 continuation code
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: F4KCOUNT
|
||||
description: Register file size
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/PNCR:
|
||||
description: part number codification register
|
||||
fields:
|
||||
- name: CODIFICATION
|
||||
description: Part number codification
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: status register
|
||||
fields:
|
||||
- name: AP_PRESENT
|
||||
description: "Bit n identifies whether access port APn is present in device \r Bit n<>=<3D>0: APn absent \r Bit n<>=<3D>1: APn present"
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: AP_ENABLED
|
||||
description: "Bit n identifies whether access port APn is open (can be accessed via the debug port) or locked (debug access to the APn is blocked, except for access) \r Bit n<>=<3D>0: APn locked (except for access to DBGMCU)\r Bit n<>=<3D>1: APn enabled"
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
@ -1,181 +1,180 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Microcontroller Debug Unit
|
||||
items:
|
||||
- name: IDCODER
|
||||
description: Identity Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODER
|
||||
- name: CR
|
||||
description: Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR1
|
||||
description: CPU1 APB1 Peripheral Freeze Register 1
|
||||
byte_offset: 60
|
||||
fieldset: APB1FZR1
|
||||
- name: C2APB1FZR1
|
||||
description: "CPU2 APB1 Peripheral Freeze Register 1 [dual core device"
|
||||
byte_offset: 64
|
||||
fieldset: C2APB1FZR1
|
||||
- name: APB1FZR2
|
||||
description: CPU1 APB1 Peripheral Freeze Register 2
|
||||
byte_offset: 68
|
||||
fieldset: APB1FZR2
|
||||
- name: C2APB1FZR2
|
||||
description: "CPU2 APB1 Peripheral Freeze Register 2 [dual core device"
|
||||
byte_offset: 72
|
||||
fieldset: C2APB1FZR2
|
||||
- name: APB2FZR
|
||||
description: CPU1 APB2 Peripheral Freeze Register
|
||||
byte_offset: 76
|
||||
fieldset: APB2FZR
|
||||
- name: C2APB2FZR
|
||||
description: "CPU2 APB2 Peripheral Freeze Register [dual core device"
|
||||
byte_offset: 80
|
||||
fieldset: C2APB2FZR
|
||||
- name: IDCODER
|
||||
description: Identity Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODER
|
||||
- name: CR
|
||||
description: Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR1
|
||||
description: CPU1 APB1 Peripheral Freeze Register 1
|
||||
byte_offset: 60
|
||||
fieldset: APB1FZR1
|
||||
- name: C2APB1FZR1
|
||||
description: CPU2 APB1 Peripheral Freeze Register 1 [dual core device
|
||||
byte_offset: 64
|
||||
fieldset: C2APB1FZR1
|
||||
- name: APB1FZR2
|
||||
description: CPU1 APB1 Peripheral Freeze Register 2
|
||||
byte_offset: 68
|
||||
fieldset: APB1FZR2
|
||||
- name: C2APB1FZR2
|
||||
description: CPU2 APB1 Peripheral Freeze Register 2 [dual core device
|
||||
byte_offset: 72
|
||||
fieldset: C2APB1FZR2
|
||||
- name: APB2FZR
|
||||
description: CPU1 APB2 Peripheral Freeze Register
|
||||
byte_offset: 76
|
||||
fieldset: APB2FZR
|
||||
- name: C2APB2FZR
|
||||
description: CPU2 APB2 Peripheral Freeze Register [dual core device
|
||||
byte_offset: 80
|
||||
fieldset: C2APB2FZR
|
||||
fieldset/APB1FZR1:
|
||||
description: CPU1 APB1 Peripheral Freeze Register 1
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: TIM2 stop in CPU1 debug
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC stop in CPU1 debug
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: WWDG stop in CPU1 debug
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDG stop in CPU1 debug
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout stop in CPU1 debug
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2
|
||||
description: I2C2 SMBUS timeout stop in CPU1 debug
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: I2C3 SMBUS timeout stop in CPU1 debug
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: LPTIM1 stop in CPU1 debug
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: TIM2
|
||||
description: TIM2 stop in CPU1 debug
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC stop in CPU1 debug
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: WWDG stop in CPU1 debug
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDG stop in CPU1 debug
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout stop in CPU1 debug
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2
|
||||
description: I2C2 SMBUS timeout stop in CPU1 debug
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: I2C3 SMBUS timeout stop in CPU1 debug
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: LPTIM1 stop in CPU1 debug
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/APB1FZR2:
|
||||
description: CPU1 APB1 Peripheral Freeze Register 2
|
||||
fields:
|
||||
- name: LPTIM2
|
||||
description: LPTIM2
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: LPTIM3
|
||||
description: LPTIM3
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: LPTIM2
|
||||
description: LPTIM2
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: LPTIM3
|
||||
description: LPTIM3
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: CPU1 APB2 Peripheral Freeze Register
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM1
|
||||
description: TIM1
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/C2APB1FZR1:
|
||||
description: "CPU2 APB1 Peripheral Freeze Register 1 [dual core device"
|
||||
description: CPU2 APB1 Peripheral Freeze Register 1 [dual core device
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: TIM2
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDG
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2
|
||||
description: I2C2
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: I2C3
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: LPTIM1
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: TIM2
|
||||
description: TIM2
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDG
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2
|
||||
description: I2C2
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: I2C3
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: LPTIM1
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/C2APB1FZR2:
|
||||
description: "CPU2 APB1 Peripheral Freeze Register 2 [dual core device"
|
||||
description: CPU2 APB1 Peripheral Freeze Register 2 [dual core device
|
||||
fields:
|
||||
- name: LPTIM2
|
||||
description: LPTIM2
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: LPTIM3
|
||||
description: LPTIM3
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: LPTIM2
|
||||
description: LPTIM2
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: LPTIM3
|
||||
description: LPTIM3
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/C2APB2FZR:
|
||||
description: "CPU2 APB2 Peripheral Freeze Register [dual core device"
|
||||
description: CPU2 APB2 Peripheral Freeze Register [dual core device
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM1
|
||||
description: TIM1
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Configuration Register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: Allow debug in SLEEP mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Allow debug in STOP mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Allow debug in STANDBY mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: DBG_SLEEP
|
||||
description: Allow debug in SLEEP mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Allow debug in STOP mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Allow debug in STANDBY mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
fieldset/IDCODER:
|
||||
description: Identity Code Register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: DEV_ID
|
||||
description: Device ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
|
||||
@ -1,286 +1,285 @@
|
||||
---
|
||||
block/DCMI:
|
||||
description: Digital camera interface
|
||||
items:
|
||||
- name: CR
|
||||
description: control register 1
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 4
|
||||
access: Read
|
||||
fieldset: SR
|
||||
- name: RIS
|
||||
description: raw interrupt status register
|
||||
byte_offset: 8
|
||||
access: Read
|
||||
fieldset: RIS
|
||||
- name: IER
|
||||
description: interrupt enable register
|
||||
byte_offset: 12
|
||||
fieldset: IER
|
||||
- name: MIS
|
||||
description: masked interrupt status register
|
||||
byte_offset: 16
|
||||
access: Read
|
||||
fieldset: MIS
|
||||
- name: ICR
|
||||
description: interrupt clear register
|
||||
byte_offset: 20
|
||||
access: Write
|
||||
fieldset: ICR
|
||||
- name: ESCR
|
||||
description: embedded synchronization code register
|
||||
byte_offset: 24
|
||||
fieldset: ESCR
|
||||
- name: ESUR
|
||||
description: embedded synchronization unmask register
|
||||
byte_offset: 28
|
||||
fieldset: ESUR
|
||||
- name: CWSTRT
|
||||
description: crop window start
|
||||
byte_offset: 32
|
||||
fieldset: CWSTRT
|
||||
- name: CWSIZE
|
||||
description: crop window size
|
||||
byte_offset: 36
|
||||
fieldset: CWSIZE
|
||||
- name: DR
|
||||
description: data register
|
||||
byte_offset: 40
|
||||
access: Read
|
||||
fieldset: DR
|
||||
- name: CR
|
||||
description: control register 1
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 4
|
||||
access: Read
|
||||
fieldset: SR
|
||||
- name: RIS
|
||||
description: raw interrupt status register
|
||||
byte_offset: 8
|
||||
access: Read
|
||||
fieldset: RIS
|
||||
- name: IER
|
||||
description: interrupt enable register
|
||||
byte_offset: 12
|
||||
fieldset: IER
|
||||
- name: MIS
|
||||
description: masked interrupt status register
|
||||
byte_offset: 16
|
||||
access: Read
|
||||
fieldset: MIS
|
||||
- name: ICR
|
||||
description: interrupt clear register
|
||||
byte_offset: 20
|
||||
access: Write
|
||||
fieldset: ICR
|
||||
- name: ESCR
|
||||
description: embedded synchronization code register
|
||||
byte_offset: 24
|
||||
fieldset: ESCR
|
||||
- name: ESUR
|
||||
description: embedded synchronization unmask register
|
||||
byte_offset: 28
|
||||
fieldset: ESUR
|
||||
- name: CWSTRT
|
||||
description: crop window start
|
||||
byte_offset: 32
|
||||
fieldset: CWSTRT
|
||||
- name: CWSIZE
|
||||
description: crop window size
|
||||
byte_offset: 36
|
||||
fieldset: CWSIZE
|
||||
- name: DR
|
||||
description: data register
|
||||
byte_offset: 40
|
||||
access: Read
|
||||
fieldset: DR
|
||||
fieldset/CR:
|
||||
description: control register 1
|
||||
fields:
|
||||
- name: CAPTURE
|
||||
description: Capture enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: CM
|
||||
description: Capture mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: CROP
|
||||
description: Crop feature
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: JPEG
|
||||
description: JPEG format
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: ESS
|
||||
description: Embedded synchronization select
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PCKPOL
|
||||
description: Pixel clock polarity
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: HSPOL
|
||||
description: Horizontal synchronization polarity
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: VSPOL
|
||||
description: Vertical synchronization polarity
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: FCRC
|
||||
description: Frame capture rate control
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
- name: EDM
|
||||
description: Extended data mode
|
||||
bit_offset: 10
|
||||
bit_size: 2
|
||||
- name: ENABLE
|
||||
description: DCMI enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: CAPTURE
|
||||
description: Capture enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: CM
|
||||
description: Capture mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: CROP
|
||||
description: Crop feature
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: JPEG
|
||||
description: JPEG format
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: ESS
|
||||
description: Embedded synchronization select
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PCKPOL
|
||||
description: Pixel clock polarity
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: HSPOL
|
||||
description: Horizontal synchronization polarity
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: VSPOL
|
||||
description: Vertical synchronization polarity
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: FCRC
|
||||
description: Frame capture rate control
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
- name: EDM
|
||||
description: Extended data mode
|
||||
bit_offset: 10
|
||||
bit_size: 2
|
||||
- name: ENABLE
|
||||
description: DCMI enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
fieldset/CWSIZE:
|
||||
description: crop window size
|
||||
fields:
|
||||
- name: CAPCNT
|
||||
description: Capture count
|
||||
bit_offset: 0
|
||||
bit_size: 14
|
||||
- name: VLINE
|
||||
description: Vertical line count
|
||||
bit_offset: 16
|
||||
bit_size: 14
|
||||
- name: CAPCNT
|
||||
description: Capture count
|
||||
bit_offset: 0
|
||||
bit_size: 14
|
||||
- name: VLINE
|
||||
description: Vertical line count
|
||||
bit_offset: 16
|
||||
bit_size: 14
|
||||
fieldset/CWSTRT:
|
||||
description: crop window start
|
||||
fields:
|
||||
- name: HOFFCNT
|
||||
description: Horizontal offset count
|
||||
bit_offset: 0
|
||||
bit_size: 14
|
||||
- name: VST
|
||||
description: Vertical start line count
|
||||
bit_offset: 16
|
||||
bit_size: 13
|
||||
- name: HOFFCNT
|
||||
description: Horizontal offset count
|
||||
bit_offset: 0
|
||||
bit_size: 14
|
||||
- name: VST
|
||||
description: Vertical start line count
|
||||
bit_offset: 16
|
||||
bit_size: 13
|
||||
fieldset/DR:
|
||||
description: data register
|
||||
fields:
|
||||
- name: Byte0
|
||||
description: Data byte 0
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: Byte1
|
||||
description: Data byte 1
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: Byte2
|
||||
description: Data byte 2
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: Byte3
|
||||
description: Data byte 3
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
- name: Byte0
|
||||
description: Data byte 0
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: Byte1
|
||||
description: Data byte 1
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: Byte2
|
||||
description: Data byte 2
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: Byte3
|
||||
description: Data byte 3
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
fieldset/ESCR:
|
||||
description: embedded synchronization code register
|
||||
fields:
|
||||
- name: FSC
|
||||
description: Frame start delimiter code
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: LSC
|
||||
description: Line start delimiter code
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: LEC
|
||||
description: Line end delimiter code
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: FEC
|
||||
description: Frame end delimiter code
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
- name: FSC
|
||||
description: Frame start delimiter code
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: LSC
|
||||
description: Line start delimiter code
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: LEC
|
||||
description: Line end delimiter code
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: FEC
|
||||
description: Frame end delimiter code
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
fieldset/ESUR:
|
||||
description: embedded synchronization unmask register
|
||||
fields:
|
||||
- name: FSU
|
||||
description: Frame start delimiter unmask
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: LSU
|
||||
description: Line start delimiter unmask
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: LEU
|
||||
description: Line end delimiter unmask
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: FEU
|
||||
description: Frame end delimiter unmask
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
- name: FSU
|
||||
description: Frame start delimiter unmask
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: LSU
|
||||
description: Line start delimiter unmask
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: LEU
|
||||
description: Line end delimiter unmask
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: FEU
|
||||
description: Frame end delimiter unmask
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
fieldset/ICR:
|
||||
description: interrupt clear register
|
||||
fields:
|
||||
- name: FRAME_ISC
|
||||
description: Capture complete interrupt status clear
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OVR_ISC
|
||||
description: Overrun interrupt status clear
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ERR_ISC
|
||||
description: Synchronization error interrupt status clear
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: VSYNC_ISC
|
||||
description: Vertical synch interrupt status clear
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: LINE_ISC
|
||||
description: line interrupt status clear
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: FRAME_ISC
|
||||
description: Capture complete interrupt status clear
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OVR_ISC
|
||||
description: Overrun interrupt status clear
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ERR_ISC
|
||||
description: Synchronization error interrupt status clear
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: VSYNC_ISC
|
||||
description: Vertical synch interrupt status clear
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: LINE_ISC
|
||||
description: line interrupt status clear
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
fieldset/IER:
|
||||
description: interrupt enable register
|
||||
fields:
|
||||
- name: FRAME_IE
|
||||
description: Capture complete interrupt enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OVR_IE
|
||||
description: Overrun interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ERR_IE
|
||||
description: Synchronization error interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: VSYNC_IE
|
||||
description: VSYNC interrupt enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: LINE_IE
|
||||
description: Line interrupt enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: FRAME_IE
|
||||
description: Capture complete interrupt enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OVR_IE
|
||||
description: Overrun interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ERR_IE
|
||||
description: Synchronization error interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: VSYNC_IE
|
||||
description: VSYNC interrupt enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: LINE_IE
|
||||
description: Line interrupt enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
fieldset/MIS:
|
||||
description: masked interrupt status register
|
||||
fields:
|
||||
- name: FRAME_MIS
|
||||
description: Capture complete masked interrupt status
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OVR_MIS
|
||||
description: Overrun masked interrupt status
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ERR_MIS
|
||||
description: Synchronization error masked interrupt status
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: VSYNC_MIS
|
||||
description: VSYNC masked interrupt status
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: LINE_MIS
|
||||
description: Line masked interrupt status
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: FRAME_MIS
|
||||
description: Capture complete masked interrupt status
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OVR_MIS
|
||||
description: Overrun masked interrupt status
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ERR_MIS
|
||||
description: Synchronization error masked interrupt status
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: VSYNC_MIS
|
||||
description: VSYNC masked interrupt status
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: LINE_MIS
|
||||
description: Line masked interrupt status
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
fieldset/RIS:
|
||||
description: raw interrupt status register
|
||||
fields:
|
||||
- name: FRAME_RIS
|
||||
description: Capture complete raw interrupt status
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OVR_RIS
|
||||
description: Overrun raw interrupt status
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ERR_RIS
|
||||
description: Synchronization error raw interrupt status
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: VSYNC_RIS
|
||||
description: VSYNC raw interrupt status
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: LINE_RIS
|
||||
description: Line raw interrupt status
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: FRAME_RIS
|
||||
description: Capture complete raw interrupt status
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OVR_RIS
|
||||
description: Overrun raw interrupt status
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ERR_RIS
|
||||
description: Synchronization error raw interrupt status
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: VSYNC_RIS
|
||||
description: VSYNC raw interrupt status
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: LINE_RIS
|
||||
description: Line raw interrupt status
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
fieldset/SR:
|
||||
description: status register
|
||||
fields:
|
||||
- name: HSYNC
|
||||
description: HSYNC
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: VSYNC
|
||||
description: VSYNC
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: FNE
|
||||
description: FIFO not empty
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: HSYNC
|
||||
description: HSYNC
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: VSYNC
|
||||
description: VSYNC
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: FNE
|
||||
description: FIFO not empty
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,378 +1,377 @@
|
||||
---
|
||||
block/DMA:
|
||||
description: DMA controller
|
||||
items:
|
||||
- name: ISR
|
||||
description: low interrupt status register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IXR
|
||||
- name: IFCR
|
||||
description: low interrupt flag clear register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: IXR
|
||||
- name: ST
|
||||
description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"
|
||||
array:
|
||||
len: 8
|
||||
stride: 24
|
||||
byte_offset: 16
|
||||
block: ST
|
||||
- name: ISR
|
||||
description: low interrupt status register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IXR
|
||||
- name: IFCR
|
||||
description: low interrupt flag clear register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: IXR
|
||||
- name: ST
|
||||
description: 'Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers'
|
||||
array:
|
||||
len: 8
|
||||
stride: 24
|
||||
byte_offset: 16
|
||||
block: ST
|
||||
block/ST:
|
||||
description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"
|
||||
description: 'Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers'
|
||||
items:
|
||||
- name: CR
|
||||
description: stream x configuration register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: NDTR
|
||||
description: stream x number of data register
|
||||
byte_offset: 4
|
||||
fieldset: NDTR
|
||||
- name: PAR
|
||||
description: stream x peripheral address register
|
||||
byte_offset: 8
|
||||
- name: M0AR
|
||||
description: stream x memory 0 address register
|
||||
byte_offset: 12
|
||||
- name: M1AR
|
||||
description: stream x memory 1 address register
|
||||
byte_offset: 16
|
||||
- name: FCR
|
||||
description: stream x FIFO control register
|
||||
byte_offset: 20
|
||||
fieldset: FCR
|
||||
- name: CR
|
||||
description: stream x configuration register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: NDTR
|
||||
description: stream x number of data register
|
||||
byte_offset: 4
|
||||
fieldset: NDTR
|
||||
- name: PAR
|
||||
description: stream x peripheral address register
|
||||
byte_offset: 8
|
||||
- name: M0AR
|
||||
description: stream x memory 0 address register
|
||||
byte_offset: 12
|
||||
- name: M1AR
|
||||
description: stream x memory 1 address register
|
||||
byte_offset: 16
|
||||
- name: FCR
|
||||
description: stream x FIFO control register
|
||||
byte_offset: 20
|
||||
fieldset: FCR
|
||||
fieldset/CR:
|
||||
description: stream x configuration register
|
||||
fields:
|
||||
- name: EN
|
||||
description: Stream enable / flag stream ready when read low
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DMEIE
|
||||
description: Direct mode error interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TEIE
|
||||
description: Transfer error interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: HTIE
|
||||
description: Half transfer interrupt enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TCIE
|
||||
description: Transfer complete interrupt enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PFCTRL
|
||||
description: Peripheral flow controller
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: PFCTRL
|
||||
- name: DIR
|
||||
description: Data transfer direction
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
enum: DIR
|
||||
- name: CIRC
|
||||
description: Circular mode
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: CIRC
|
||||
- name: PINC
|
||||
description: Peripheral increment mode
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: MINC
|
||||
description: Memory increment mode
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: PSIZE
|
||||
description: Peripheral data size
|
||||
bit_offset: 11
|
||||
bit_size: 2
|
||||
enum: SIZE
|
||||
- name: MSIZE
|
||||
description: Memory data size
|
||||
bit_offset: 13
|
||||
bit_size: 2
|
||||
enum: SIZE
|
||||
- name: PINCOS
|
||||
description: Peripheral increment offset size
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum: PINCOS
|
||||
- name: PL
|
||||
description: Priority level
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: PL
|
||||
- name: DBM
|
||||
description: Double buffer mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
enum: DBM
|
||||
- name: CT
|
||||
description: Current target (only in double buffer mode)
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
enum: CT
|
||||
- name: TRBUFF
|
||||
description: Enable bufferable transfers
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: PBURST
|
||||
description: Peripheral burst transfer configuration
|
||||
bit_offset: 21
|
||||
bit_size: 2
|
||||
enum: BURST
|
||||
- name: MBURST
|
||||
description: Memory burst transfer configuration
|
||||
bit_offset: 23
|
||||
bit_size: 2
|
||||
enum: BURST
|
||||
- name: EN
|
||||
description: Stream enable / flag stream ready when read low
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DMEIE
|
||||
description: Direct mode error interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TEIE
|
||||
description: Transfer error interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: HTIE
|
||||
description: Half transfer interrupt enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TCIE
|
||||
description: Transfer complete interrupt enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PFCTRL
|
||||
description: Peripheral flow controller
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: PFCTRL
|
||||
- name: DIR
|
||||
description: Data transfer direction
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
enum: DIR
|
||||
- name: CIRC
|
||||
description: Circular mode
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: CIRC
|
||||
- name: PINC
|
||||
description: Peripheral increment mode
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: MINC
|
||||
description: Memory increment mode
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: PSIZE
|
||||
description: Peripheral data size
|
||||
bit_offset: 11
|
||||
bit_size: 2
|
||||
enum: SIZE
|
||||
- name: MSIZE
|
||||
description: Memory data size
|
||||
bit_offset: 13
|
||||
bit_size: 2
|
||||
enum: SIZE
|
||||
- name: PINCOS
|
||||
description: Peripheral increment offset size
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum: PINCOS
|
||||
- name: PL
|
||||
description: Priority level
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: PL
|
||||
- name: DBM
|
||||
description: Double buffer mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
enum: DBM
|
||||
- name: CT
|
||||
description: Current target (only in double buffer mode)
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
enum: CT
|
||||
- name: TRBUFF
|
||||
description: Enable bufferable transfers
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: PBURST
|
||||
description: Peripheral burst transfer configuration
|
||||
bit_offset: 21
|
||||
bit_size: 2
|
||||
enum: BURST
|
||||
- name: MBURST
|
||||
description: Memory burst transfer configuration
|
||||
bit_offset: 23
|
||||
bit_size: 2
|
||||
enum: BURST
|
||||
fieldset/FCR:
|
||||
description: stream x FIFO control register
|
||||
fields:
|
||||
- name: FTH
|
||||
description: FIFO threshold selection
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
enum: FTH
|
||||
- name: DMDIS
|
||||
description: Direct mode disable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum: DMDIS
|
||||
- name: FS
|
||||
description: FIFO status
|
||||
bit_offset: 3
|
||||
bit_size: 3
|
||||
enum: FS
|
||||
- name: FEIE
|
||||
description: FIFO error interrupt enable
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: FTH
|
||||
description: FIFO threshold selection
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
enum: FTH
|
||||
- name: DMDIS
|
||||
description: Direct mode disable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum: DMDIS
|
||||
- name: FS
|
||||
description: FIFO status
|
||||
bit_offset: 3
|
||||
bit_size: 3
|
||||
enum: FS
|
||||
- name: FEIE
|
||||
description: FIFO error interrupt enable
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
fieldset/IXR:
|
||||
description: interrupt register
|
||||
fields:
|
||||
- name: FEIF
|
||||
description: Stream x FIFO error interrupt flag (x=3..0)
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: DMEIF
|
||||
description: Stream x direct mode error interrupt flag (x=3..0)
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: TEIF
|
||||
description: Stream x transfer error interrupt flag (x=3..0)
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: HTIF
|
||||
description: Stream x half transfer interrupt flag (x=3..0)
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: TCIF
|
||||
description: Stream x transfer complete interrupt flag (x = 3..0)
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: FEIF
|
||||
description: Stream x FIFO error interrupt flag (x=3..0)
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: DMEIF
|
||||
description: Stream x direct mode error interrupt flag (x=3..0)
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: TEIF
|
||||
description: Stream x transfer error interrupt flag (x=3..0)
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: HTIF
|
||||
description: Stream x half transfer interrupt flag (x=3..0)
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: TCIF
|
||||
description: Stream x transfer complete interrupt flag (x = 3..0)
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
fieldset/NDTR:
|
||||
description: stream x number of data register
|
||||
fields:
|
||||
- name: NDT
|
||||
description: Number of data items to transfer
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: NDT
|
||||
description: Number of data items to transfer
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
enum/BURST:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Single
|
||||
description: Single transfer
|
||||
value: 0
|
||||
- name: INCR4
|
||||
description: Incremental burst of 4 beats
|
||||
value: 1
|
||||
- name: INCR8
|
||||
description: Incremental burst of 8 beats
|
||||
value: 2
|
||||
- name: INCR16
|
||||
description: Incremental burst of 16 beats
|
||||
value: 3
|
||||
- name: Single
|
||||
description: Single transfer
|
||||
value: 0
|
||||
- name: INCR4
|
||||
description: Incremental burst of 4 beats
|
||||
value: 1
|
||||
- name: INCR8
|
||||
description: Incremental burst of 8 beats
|
||||
value: 2
|
||||
- name: INCR16
|
||||
description: Incremental burst of 16 beats
|
||||
value: 3
|
||||
enum/CIRC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Circular mode disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Circular mode enabled
|
||||
value: 1
|
||||
- name: Disabled
|
||||
description: Circular mode disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Circular mode enabled
|
||||
value: 1
|
||||
enum/CT:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Memory0
|
||||
description: The current target memory is Memory 0
|
||||
value: 0
|
||||
- name: Memory1
|
||||
description: The current target memory is Memory 1
|
||||
value: 1
|
||||
- name: Memory0
|
||||
description: The current target memory is Memory 0
|
||||
value: 0
|
||||
- name: Memory1
|
||||
description: The current target memory is Memory 1
|
||||
value: 1
|
||||
enum/DBM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: No buffer switching at the end of transfer
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Memory target switched at the end of the DMA transfer
|
||||
value: 1
|
||||
- name: Disabled
|
||||
description: No buffer switching at the end of transfer
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Memory target switched at the end of the DMA transfer
|
||||
value: 1
|
||||
enum/DIR:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: PeripheralToMemory
|
||||
description: Peripheral-to-memory
|
||||
value: 0
|
||||
- name: MemoryToPeripheral
|
||||
description: Memory-to-peripheral
|
||||
value: 1
|
||||
- name: MemoryToMemory
|
||||
description: Memory-to-memory
|
||||
value: 2
|
||||
- name: PeripheralToMemory
|
||||
description: Peripheral-to-memory
|
||||
value: 0
|
||||
- name: MemoryToPeripheral
|
||||
description: Memory-to-peripheral
|
||||
value: 1
|
||||
- name: MemoryToMemory
|
||||
description: Memory-to-memory
|
||||
value: 2
|
||||
enum/DMDIS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enabled
|
||||
description: Direct mode is enabled
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: Direct mode is disabled
|
||||
value: 1
|
||||
- name: Enabled
|
||||
description: Direct mode is enabled
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: Direct mode is disabled
|
||||
value: 1
|
||||
enum/FS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Quarter1
|
||||
description: 0 < fifo_level < 1/4
|
||||
value: 0
|
||||
- name: Quarter2
|
||||
description: 1/4 <= fifo_level < 1/2
|
||||
value: 1
|
||||
- name: Quarter3
|
||||
description: 1/2 <= fifo_level < 3/4
|
||||
value: 2
|
||||
- name: Quarter4
|
||||
description: 3/4 <= fifo_level < full
|
||||
value: 3
|
||||
- name: Empty
|
||||
description: FIFO is empty
|
||||
value: 4
|
||||
- name: Full
|
||||
description: FIFO is full
|
||||
value: 5
|
||||
- name: Quarter1
|
||||
description: 0 < fifo_level < 1/4
|
||||
value: 0
|
||||
- name: Quarter2
|
||||
description: 1/4 <= fifo_level < 1/2
|
||||
value: 1
|
||||
- name: Quarter3
|
||||
description: 1/2 <= fifo_level < 3/4
|
||||
value: 2
|
||||
- name: Quarter4
|
||||
description: 3/4 <= fifo_level < full
|
||||
value: 3
|
||||
- name: Empty
|
||||
description: FIFO is empty
|
||||
value: 4
|
||||
- name: Full
|
||||
description: FIFO is full
|
||||
value: 5
|
||||
enum/FTH:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Quarter
|
||||
description: 1/4 full FIFO
|
||||
value: 0
|
||||
- name: Half
|
||||
description: 1/2 full FIFO
|
||||
value: 1
|
||||
- name: ThreeQuarters
|
||||
description: 3/4 full FIFO
|
||||
value: 2
|
||||
- name: Full
|
||||
description: Full FIFO
|
||||
value: 3
|
||||
- name: Quarter
|
||||
description: 1/4 full FIFO
|
||||
value: 0
|
||||
- name: Half
|
||||
description: 1/2 full FIFO
|
||||
value: 1
|
||||
- name: ThreeQuarters
|
||||
description: 3/4 full FIFO
|
||||
value: 2
|
||||
- name: Full
|
||||
description: Full FIFO
|
||||
value: 3
|
||||
enum/INC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Fixed
|
||||
description: Address pointer is fixed
|
||||
value: 0
|
||||
- name: Incremented
|
||||
description: Address pointer is incremented after each data transfer
|
||||
value: 1
|
||||
- name: Fixed
|
||||
description: Address pointer is fixed
|
||||
value: 0
|
||||
- name: Incremented
|
||||
description: Address pointer is incremented after each data transfer
|
||||
value: 1
|
||||
enum/PFCTRL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: DMA
|
||||
description: The DMA is the flow controller
|
||||
value: 0
|
||||
- name: Peripheral
|
||||
description: The peripheral is the flow controller
|
||||
value: 1
|
||||
- name: DMA
|
||||
description: The DMA is the flow controller
|
||||
value: 0
|
||||
- name: Peripheral
|
||||
description: The peripheral is the flow controller
|
||||
value: 1
|
||||
enum/PINCOS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: PSIZE
|
||||
description: The offset size for the peripheral address calculation is linked to the PSIZE
|
||||
value: 0
|
||||
- name: Fixed4
|
||||
description: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)
|
||||
value: 1
|
||||
- name: PSIZE
|
||||
description: The offset size for the peripheral address calculation is linked to the PSIZE
|
||||
value: 0
|
||||
- name: Fixed4
|
||||
description: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)
|
||||
value: 1
|
||||
enum/PL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Low
|
||||
description: Low
|
||||
value: 0
|
||||
- name: Medium
|
||||
description: Medium
|
||||
value: 1
|
||||
- name: High
|
||||
description: High
|
||||
value: 2
|
||||
- name: VeryHigh
|
||||
description: Very high
|
||||
value: 3
|
||||
- name: Low
|
||||
description: Low
|
||||
value: 0
|
||||
- name: Medium
|
||||
description: Medium
|
||||
value: 1
|
||||
- name: High
|
||||
description: High
|
||||
value: 2
|
||||
- name: VeryHigh
|
||||
description: Very high
|
||||
value: 3
|
||||
enum/SIZE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Bits8
|
||||
description: Byte (8-bit)
|
||||
value: 0
|
||||
- name: Bits16
|
||||
description: Half-word (16-bit)
|
||||
value: 1
|
||||
- name: Bits32
|
||||
description: Word (32-bit)
|
||||
value: 2
|
||||
- name: Bits8
|
||||
description: Byte (8-bit)
|
||||
value: 0
|
||||
- name: Bits16
|
||||
description: Half-word (16-bit)
|
||||
value: 1
|
||||
- name: Bits32
|
||||
description: Word (32-bit)
|
||||
value: 2
|
||||
|
||||
@ -1,378 +1,377 @@
|
||||
---
|
||||
block/DMA:
|
||||
description: DMA controller
|
||||
items:
|
||||
- name: ISR
|
||||
description: low interrupt status register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IXR
|
||||
- name: IFCR
|
||||
description: low interrupt flag clear register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: IXR
|
||||
- name: ST
|
||||
description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"
|
||||
array:
|
||||
len: 8
|
||||
stride: 24
|
||||
byte_offset: 16
|
||||
block: ST
|
||||
- name: ISR
|
||||
description: low interrupt status register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IXR
|
||||
- name: IFCR
|
||||
description: low interrupt flag clear register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: IXR
|
||||
- name: ST
|
||||
description: 'Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers'
|
||||
array:
|
||||
len: 8
|
||||
stride: 24
|
||||
byte_offset: 16
|
||||
block: ST
|
||||
block/ST:
|
||||
description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"
|
||||
description: 'Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers'
|
||||
items:
|
||||
- name: CR
|
||||
description: stream x configuration register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: NDTR
|
||||
description: stream x number of data register
|
||||
byte_offset: 4
|
||||
fieldset: NDTR
|
||||
- name: PAR
|
||||
description: stream x peripheral address register
|
||||
byte_offset: 8
|
||||
- name: M0AR
|
||||
description: stream x memory 0 address register
|
||||
byte_offset: 12
|
||||
- name: M1AR
|
||||
description: stream x memory 1 address register
|
||||
byte_offset: 16
|
||||
- name: FCR
|
||||
description: stream x FIFO control register
|
||||
byte_offset: 20
|
||||
fieldset: FCR
|
||||
- name: CR
|
||||
description: stream x configuration register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: NDTR
|
||||
description: stream x number of data register
|
||||
byte_offset: 4
|
||||
fieldset: NDTR
|
||||
- name: PAR
|
||||
description: stream x peripheral address register
|
||||
byte_offset: 8
|
||||
- name: M0AR
|
||||
description: stream x memory 0 address register
|
||||
byte_offset: 12
|
||||
- name: M1AR
|
||||
description: stream x memory 1 address register
|
||||
byte_offset: 16
|
||||
- name: FCR
|
||||
description: stream x FIFO control register
|
||||
byte_offset: 20
|
||||
fieldset: FCR
|
||||
fieldset/CR:
|
||||
description: stream x configuration register
|
||||
fields:
|
||||
- name: EN
|
||||
description: Stream enable / flag stream ready when read low
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DMEIE
|
||||
description: Direct mode error interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TEIE
|
||||
description: Transfer error interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: HTIE
|
||||
description: Half transfer interrupt enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TCIE
|
||||
description: Transfer complete interrupt enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PFCTRL
|
||||
description: Peripheral flow controller
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: PFCTRL
|
||||
- name: DIR
|
||||
description: Data transfer direction
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
enum: DIR
|
||||
- name: CIRC
|
||||
description: Circular mode
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: CIRC
|
||||
- name: PINC
|
||||
description: Peripheral increment mode
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: MINC
|
||||
description: Memory increment mode
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: PSIZE
|
||||
description: Peripheral data size
|
||||
bit_offset: 11
|
||||
bit_size: 2
|
||||
enum: SIZE
|
||||
- name: MSIZE
|
||||
description: Memory data size
|
||||
bit_offset: 13
|
||||
bit_size: 2
|
||||
enum: SIZE
|
||||
- name: PINCOS
|
||||
description: Peripheral increment offset size
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum: PINCOS
|
||||
- name: PL
|
||||
description: Priority level
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: PL
|
||||
- name: DBM
|
||||
description: Double buffer mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
enum: DBM
|
||||
- name: CT
|
||||
description: Current target (only in double buffer mode)
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
enum: CT
|
||||
- name: PBURST
|
||||
description: Peripheral burst transfer configuration
|
||||
bit_offset: 21
|
||||
bit_size: 2
|
||||
enum: BURST
|
||||
- name: MBURST
|
||||
description: Memory burst transfer configuration
|
||||
bit_offset: 23
|
||||
bit_size: 2
|
||||
enum: BURST
|
||||
- name: CHSEL
|
||||
description: Channel selection
|
||||
bit_offset: 25
|
||||
bit_size: 4
|
||||
- name: EN
|
||||
description: Stream enable / flag stream ready when read low
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DMEIE
|
||||
description: Direct mode error interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TEIE
|
||||
description: Transfer error interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: HTIE
|
||||
description: Half transfer interrupt enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TCIE
|
||||
description: Transfer complete interrupt enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PFCTRL
|
||||
description: Peripheral flow controller
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: PFCTRL
|
||||
- name: DIR
|
||||
description: Data transfer direction
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
enum: DIR
|
||||
- name: CIRC
|
||||
description: Circular mode
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: CIRC
|
||||
- name: PINC
|
||||
description: Peripheral increment mode
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: MINC
|
||||
description: Memory increment mode
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: PSIZE
|
||||
description: Peripheral data size
|
||||
bit_offset: 11
|
||||
bit_size: 2
|
||||
enum: SIZE
|
||||
- name: MSIZE
|
||||
description: Memory data size
|
||||
bit_offset: 13
|
||||
bit_size: 2
|
||||
enum: SIZE
|
||||
- name: PINCOS
|
||||
description: Peripheral increment offset size
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum: PINCOS
|
||||
- name: PL
|
||||
description: Priority level
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: PL
|
||||
- name: DBM
|
||||
description: Double buffer mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
enum: DBM
|
||||
- name: CT
|
||||
description: Current target (only in double buffer mode)
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
enum: CT
|
||||
- name: PBURST
|
||||
description: Peripheral burst transfer configuration
|
||||
bit_offset: 21
|
||||
bit_size: 2
|
||||
enum: BURST
|
||||
- name: MBURST
|
||||
description: Memory burst transfer configuration
|
||||
bit_offset: 23
|
||||
bit_size: 2
|
||||
enum: BURST
|
||||
- name: CHSEL
|
||||
description: Channel selection
|
||||
bit_offset: 25
|
||||
bit_size: 4
|
||||
fieldset/FCR:
|
||||
description: stream x FIFO control register
|
||||
fields:
|
||||
- name: FTH
|
||||
description: FIFO threshold selection
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
enum: FTH
|
||||
- name: DMDIS
|
||||
description: Direct mode disable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum: DMDIS
|
||||
- name: FS
|
||||
description: FIFO status
|
||||
bit_offset: 3
|
||||
bit_size: 3
|
||||
enum: FS
|
||||
- name: FEIE
|
||||
description: FIFO error interrupt enable
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: FTH
|
||||
description: FIFO threshold selection
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
enum: FTH
|
||||
- name: DMDIS
|
||||
description: Direct mode disable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum: DMDIS
|
||||
- name: FS
|
||||
description: FIFO status
|
||||
bit_offset: 3
|
||||
bit_size: 3
|
||||
enum: FS
|
||||
- name: FEIE
|
||||
description: FIFO error interrupt enable
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
fieldset/IXR:
|
||||
description: interrupt register
|
||||
fields:
|
||||
- name: FEIF
|
||||
description: Stream x FIFO error interrupt flag (x=3..0)
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: DMEIF
|
||||
description: Stream x direct mode error interrupt flag (x=3..0)
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: TEIF
|
||||
description: Stream x transfer error interrupt flag (x=3..0)
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: HTIF
|
||||
description: Stream x half transfer interrupt flag (x=3..0)
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: TCIF
|
||||
description: Stream x transfer complete interrupt flag (x = 3..0)
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: FEIF
|
||||
description: Stream x FIFO error interrupt flag (x=3..0)
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: DMEIF
|
||||
description: Stream x direct mode error interrupt flag (x=3..0)
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: TEIF
|
||||
description: Stream x transfer error interrupt flag (x=3..0)
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: HTIF
|
||||
description: Stream x half transfer interrupt flag (x=3..0)
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
- name: TCIF
|
||||
description: Stream x transfer complete interrupt flag (x = 3..0)
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 16
|
||||
- 22
|
||||
fieldset/NDTR:
|
||||
description: stream x number of data register
|
||||
fields:
|
||||
- name: NDT
|
||||
description: Number of data items to transfer
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: NDT
|
||||
description: Number of data items to transfer
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
enum/BURST:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Single
|
||||
description: Single transfer
|
||||
value: 0
|
||||
- name: INCR4
|
||||
description: Incremental burst of 4 beats
|
||||
value: 1
|
||||
- name: INCR8
|
||||
description: Incremental burst of 8 beats
|
||||
value: 2
|
||||
- name: INCR16
|
||||
description: Incremental burst of 16 beats
|
||||
value: 3
|
||||
- name: Single
|
||||
description: Single transfer
|
||||
value: 0
|
||||
- name: INCR4
|
||||
description: Incremental burst of 4 beats
|
||||
value: 1
|
||||
- name: INCR8
|
||||
description: Incremental burst of 8 beats
|
||||
value: 2
|
||||
- name: INCR16
|
||||
description: Incremental burst of 16 beats
|
||||
value: 3
|
||||
enum/CIRC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Circular mode disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Circular mode enabled
|
||||
value: 1
|
||||
- name: Disabled
|
||||
description: Circular mode disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Circular mode enabled
|
||||
value: 1
|
||||
enum/CT:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Memory0
|
||||
description: The current target memory is Memory 0
|
||||
value: 0
|
||||
- name: Memory1
|
||||
description: The current target memory is Memory 1
|
||||
value: 1
|
||||
- name: Memory0
|
||||
description: The current target memory is Memory 0
|
||||
value: 0
|
||||
- name: Memory1
|
||||
description: The current target memory is Memory 1
|
||||
value: 1
|
||||
enum/DBM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: No buffer switching at the end of transfer
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Memory target switched at the end of the DMA transfer
|
||||
value: 1
|
||||
- name: Disabled
|
||||
description: No buffer switching at the end of transfer
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Memory target switched at the end of the DMA transfer
|
||||
value: 1
|
||||
enum/DIR:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: PeripheralToMemory
|
||||
description: Peripheral-to-memory
|
||||
value: 0
|
||||
- name: MemoryToPeripheral
|
||||
description: Memory-to-peripheral
|
||||
value: 1
|
||||
- name: MemoryToMemory
|
||||
description: Memory-to-memory
|
||||
value: 2
|
||||
- name: PeripheralToMemory
|
||||
description: Peripheral-to-memory
|
||||
value: 0
|
||||
- name: MemoryToPeripheral
|
||||
description: Memory-to-peripheral
|
||||
value: 1
|
||||
- name: MemoryToMemory
|
||||
description: Memory-to-memory
|
||||
value: 2
|
||||
enum/DMDIS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enabled
|
||||
description: Direct mode is enabled
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: Direct mode is disabled
|
||||
value: 1
|
||||
- name: Enabled
|
||||
description: Direct mode is enabled
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: Direct mode is disabled
|
||||
value: 1
|
||||
enum/FS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Quarter1
|
||||
description: 0 < fifo_level < 1/4
|
||||
value: 0
|
||||
- name: Quarter2
|
||||
description: 1/4 <= fifo_level < 1/2
|
||||
value: 1
|
||||
- name: Quarter3
|
||||
description: 1/2 <= fifo_level < 3/4
|
||||
value: 2
|
||||
- name: Quarter4
|
||||
description: 3/4 <= fifo_level < full
|
||||
value: 3
|
||||
- name: Empty
|
||||
description: FIFO is empty
|
||||
value: 4
|
||||
- name: Full
|
||||
description: FIFO is full
|
||||
value: 5
|
||||
- name: Quarter1
|
||||
description: 0 < fifo_level < 1/4
|
||||
value: 0
|
||||
- name: Quarter2
|
||||
description: 1/4 <= fifo_level < 1/2
|
||||
value: 1
|
||||
- name: Quarter3
|
||||
description: 1/2 <= fifo_level < 3/4
|
||||
value: 2
|
||||
- name: Quarter4
|
||||
description: 3/4 <= fifo_level < full
|
||||
value: 3
|
||||
- name: Empty
|
||||
description: FIFO is empty
|
||||
value: 4
|
||||
- name: Full
|
||||
description: FIFO is full
|
||||
value: 5
|
||||
enum/FTH:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Quarter
|
||||
description: 1/4 full FIFO
|
||||
value: 0
|
||||
- name: Half
|
||||
description: 1/2 full FIFO
|
||||
value: 1
|
||||
- name: ThreeQuarters
|
||||
description: 3/4 full FIFO
|
||||
value: 2
|
||||
- name: Full
|
||||
description: Full FIFO
|
||||
value: 3
|
||||
- name: Quarter
|
||||
description: 1/4 full FIFO
|
||||
value: 0
|
||||
- name: Half
|
||||
description: 1/2 full FIFO
|
||||
value: 1
|
||||
- name: ThreeQuarters
|
||||
description: 3/4 full FIFO
|
||||
value: 2
|
||||
- name: Full
|
||||
description: Full FIFO
|
||||
value: 3
|
||||
enum/INC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Fixed
|
||||
description: Address pointer is fixed
|
||||
value: 0
|
||||
- name: Incremented
|
||||
description: Address pointer is incremented after each data transfer
|
||||
value: 1
|
||||
- name: Fixed
|
||||
description: Address pointer is fixed
|
||||
value: 0
|
||||
- name: Incremented
|
||||
description: Address pointer is incremented after each data transfer
|
||||
value: 1
|
||||
enum/PFCTRL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: DMA
|
||||
description: The DMA is the flow controller
|
||||
value: 0
|
||||
- name: Peripheral
|
||||
description: The peripheral is the flow controller
|
||||
value: 1
|
||||
- name: DMA
|
||||
description: The DMA is the flow controller
|
||||
value: 0
|
||||
- name: Peripheral
|
||||
description: The peripheral is the flow controller
|
||||
value: 1
|
||||
enum/PINCOS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: PSIZE
|
||||
description: The offset size for the peripheral address calculation is linked to the PSIZE
|
||||
value: 0
|
||||
- name: Fixed4
|
||||
description: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)
|
||||
value: 1
|
||||
- name: PSIZE
|
||||
description: The offset size for the peripheral address calculation is linked to the PSIZE
|
||||
value: 0
|
||||
- name: Fixed4
|
||||
description: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)
|
||||
value: 1
|
||||
enum/PL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Low
|
||||
description: Low
|
||||
value: 0
|
||||
- name: Medium
|
||||
description: Medium
|
||||
value: 1
|
||||
- name: High
|
||||
description: High
|
||||
value: 2
|
||||
- name: VeryHigh
|
||||
description: Very high
|
||||
value: 3
|
||||
- name: Low
|
||||
description: Low
|
||||
value: 0
|
||||
- name: Medium
|
||||
description: Medium
|
||||
value: 1
|
||||
- name: High
|
||||
description: High
|
||||
value: 2
|
||||
- name: VeryHigh
|
||||
description: Very high
|
||||
value: 3
|
||||
enum/SIZE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Bits8
|
||||
description: Byte (8-bit)
|
||||
value: 0
|
||||
- name: Bits16
|
||||
description: Half-word (16-bit)
|
||||
value: 1
|
||||
- name: Bits32
|
||||
description: Word (32-bit)
|
||||
value: 2
|
||||
- name: Bits8
|
||||
description: Byte (8-bit)
|
||||
value: 0
|
||||
- name: Bits16
|
||||
description: Half-word (16-bit)
|
||||
value: 1
|
||||
- name: Bits32
|
||||
description: Word (32-bit)
|
||||
value: 2
|
||||
|
||||
@ -1,129 +1,128 @@
|
||||
---
|
||||
block/DMAMUX:
|
||||
description: DMAMUX
|
||||
items:
|
||||
- name: CCR
|
||||
description: DMAMux - DMA request line multiplexer channel x control register
|
||||
array:
|
||||
len: 16
|
||||
stride: 4
|
||||
byte_offset: 0
|
||||
fieldset: CCR
|
||||
- name: CSR
|
||||
description: DMAMUX request line multiplexer interrupt channel status register
|
||||
byte_offset: 128
|
||||
access: Read
|
||||
fieldset: CSR
|
||||
- name: CFR
|
||||
description: DMAMUX request line multiplexer interrupt clear flag register
|
||||
byte_offset: 132
|
||||
access: Write
|
||||
fieldset: CSR
|
||||
- name: RGCR
|
||||
description: DMAMux - DMA request generator channel x control register
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
byte_offset: 256
|
||||
fieldset: RGCR
|
||||
- name: RGSR
|
||||
description: DMAMux - DMA request generator status register
|
||||
byte_offset: 320
|
||||
access: Read
|
||||
fieldset: RGSR
|
||||
- name: RGCFR
|
||||
description: DMAMux - DMA request generator clear flag register
|
||||
byte_offset: 324
|
||||
access: Write
|
||||
fieldset: RGSR
|
||||
- name: CCR
|
||||
description: DMAMux - DMA request line multiplexer channel x control register
|
||||
array:
|
||||
len: 16
|
||||
stride: 4
|
||||
byte_offset: 0
|
||||
fieldset: CCR
|
||||
- name: CSR
|
||||
description: DMAMUX request line multiplexer interrupt channel status register
|
||||
byte_offset: 128
|
||||
access: Read
|
||||
fieldset: CSR
|
||||
- name: CFR
|
||||
description: DMAMUX request line multiplexer interrupt clear flag register
|
||||
byte_offset: 132
|
||||
access: Write
|
||||
fieldset: CSR
|
||||
- name: RGCR
|
||||
description: DMAMux - DMA request generator channel x control register
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
byte_offset: 256
|
||||
fieldset: RGCR
|
||||
- name: RGSR
|
||||
description: DMAMux - DMA request generator status register
|
||||
byte_offset: 320
|
||||
access: Read
|
||||
fieldset: RGSR
|
||||
- name: RGCFR
|
||||
description: DMAMux - DMA request generator clear flag register
|
||||
byte_offset: 324
|
||||
access: Write
|
||||
fieldset: RGSR
|
||||
fieldset/CCR:
|
||||
description: DMAMux - DMA request line multiplexer channel x control register
|
||||
fields:
|
||||
- name: DMAREQ_ID
|
||||
description: Input DMA request line selected
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: SOIE
|
||||
description: Interrupt enable at synchronization event overrun
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: EGE
|
||||
description: Event generation enable/disable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: SE
|
||||
description: Synchronous operating mode enable/disable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: SPOL
|
||||
description: "Synchronization event type selector Defines the synchronization event on the selected synchronization input:"
|
||||
bit_offset: 17
|
||||
bit_size: 2
|
||||
enum: POL
|
||||
- name: NBREQ
|
||||
description: "Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset."
|
||||
bit_offset: 19
|
||||
bit_size: 5
|
||||
- name: SYNC_ID
|
||||
description: Synchronization input selected
|
||||
bit_offset: 24
|
||||
bit_size: 5
|
||||
- name: DMAREQ_ID
|
||||
description: Input DMA request line selected
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: SOIE
|
||||
description: Interrupt enable at synchronization event overrun
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: EGE
|
||||
description: Event generation enable/disable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: SE
|
||||
description: Synchronous operating mode enable/disable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: SPOL
|
||||
description: 'Synchronization event type selector Defines the synchronization event on the selected synchronization input:'
|
||||
bit_offset: 17
|
||||
bit_size: 2
|
||||
enum: POL
|
||||
- name: NBREQ
|
||||
description: 'Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.'
|
||||
bit_offset: 19
|
||||
bit_size: 5
|
||||
- name: SYNC_ID
|
||||
description: Synchronization input selected
|
||||
bit_offset: 24
|
||||
bit_size: 5
|
||||
fieldset/CSR:
|
||||
description: DMAMUX request line multiplexer interrupt channel status register
|
||||
fields:
|
||||
- name: SOF
|
||||
description: Synchronization overrun event flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 16
|
||||
stride: 1
|
||||
- name: SOF
|
||||
description: Synchronization overrun event flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 16
|
||||
stride: 1
|
||||
fieldset/RGCR:
|
||||
description: DMAMux - DMA request generator channel x control register
|
||||
fields:
|
||||
- name: SIG_ID
|
||||
description: DMA request trigger input selected
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: OIE
|
||||
description: Interrupt enable at trigger event overrun
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: GE
|
||||
description: DMA request generator channel enable/disable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: GPOL
|
||||
description: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
|
||||
bit_offset: 17
|
||||
bit_size: 2
|
||||
enum: POL
|
||||
- name: GNBREQ
|
||||
description: "Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset."
|
||||
bit_offset: 19
|
||||
bit_size: 5
|
||||
- name: SIG_ID
|
||||
description: DMA request trigger input selected
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: OIE
|
||||
description: Interrupt enable at trigger event overrun
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: GE
|
||||
description: DMA request generator channel enable/disable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: GPOL
|
||||
description: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
|
||||
bit_offset: 17
|
||||
bit_size: 2
|
||||
enum: POL
|
||||
- name: GNBREQ
|
||||
description: 'Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.'
|
||||
bit_offset: 19
|
||||
bit_size: 5
|
||||
fieldset/RGSR:
|
||||
description: DMAMux - DMA request generator status register
|
||||
fields:
|
||||
- name: OF
|
||||
description: "Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 1
|
||||
- name: OF
|
||||
description: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 1
|
||||
enum/POL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: NoEdge
|
||||
description: "No event, i.e. no synchronization nor detection"
|
||||
value: 0
|
||||
- name: RisingEdge
|
||||
description: Rising edge
|
||||
value: 1
|
||||
- name: FallingEdge
|
||||
description: Falling edge
|
||||
value: 2
|
||||
- name: BothEdges
|
||||
description: Rising and falling edges
|
||||
value: 3
|
||||
- name: NoEdge
|
||||
description: No event, i.e. no synchronization nor detection
|
||||
value: 0
|
||||
- name: RisingEdge
|
||||
description: Rising edge
|
||||
value: 1
|
||||
- name: FallingEdge
|
||||
description: Falling edge
|
||||
value: 2
|
||||
- name: BothEdges
|
||||
description: Rising and falling edges
|
||||
value: 3
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,80 +1,79 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
- name: RTSR
|
||||
description: Rising Trigger selection register
|
||||
array:
|
||||
len: 1
|
||||
stride: 40
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: Falling Trigger selection register
|
||||
array:
|
||||
len: 1
|
||||
stride: 40
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: Software interrupt event register
|
||||
array:
|
||||
len: 1
|
||||
stride: 40
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: RPR
|
||||
description: Rising pending register
|
||||
array:
|
||||
len: 1
|
||||
stride: 40
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: FPR
|
||||
description: Falling pending register
|
||||
array:
|
||||
len: 1
|
||||
stride: 40
|
||||
byte_offset: 16
|
||||
fieldset: LINES
|
||||
- name: EXTICR
|
||||
description: Configuration register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 96
|
||||
fieldset: EXTICR
|
||||
- name: IMR
|
||||
description: Interrupt mask register
|
||||
array:
|
||||
len: 1
|
||||
stride: 16
|
||||
byte_offset: 128
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: Event mask register
|
||||
array:
|
||||
len: 1
|
||||
stride: 16
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
- name: RTSR
|
||||
description: Rising Trigger selection register
|
||||
array:
|
||||
len: 1
|
||||
stride: 40
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: Falling Trigger selection register
|
||||
array:
|
||||
len: 1
|
||||
stride: 40
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: Software interrupt event register
|
||||
array:
|
||||
len: 1
|
||||
stride: 40
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: RPR
|
||||
description: Rising pending register
|
||||
array:
|
||||
len: 1
|
||||
stride: 40
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: FPR
|
||||
description: Falling pending register
|
||||
array:
|
||||
len: 1
|
||||
stride: 40
|
||||
byte_offset: 16
|
||||
fieldset: LINES
|
||||
- name: EXTICR
|
||||
description: Configuration register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 96
|
||||
fieldset: EXTICR
|
||||
- name: IMR
|
||||
description: Interrupt mask register
|
||||
array:
|
||||
len: 1
|
||||
stride: 16
|
||||
byte_offset: 128
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: Event mask register
|
||||
array:
|
||||
len: 1
|
||||
stride: 16
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
fieldset/EXTICR:
|
||||
description: external interrupt configuration register 1
|
||||
fields:
|
||||
- name: EXTI
|
||||
description: EXTI configuration bits
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
- name: EXTI
|
||||
description: EXTI configuration bits
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
|
||||
@ -1,80 +1,79 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
- name: RTSR
|
||||
description: Rising Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 40
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: Falling Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 40
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: Software interrupt event register
|
||||
array:
|
||||
len: 2
|
||||
stride: 40
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: RPR
|
||||
description: Rising pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 40
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: FPR
|
||||
description: Falling pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 40
|
||||
byte_offset: 16
|
||||
fieldset: LINES
|
||||
- name: EXTICR
|
||||
description: Configuration register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 96
|
||||
fieldset: EXTICR
|
||||
- name: IMR
|
||||
description: Interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 128
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: Event mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
- name: RTSR
|
||||
description: Rising Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 40
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: Falling Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 40
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: Software interrupt event register
|
||||
array:
|
||||
len: 2
|
||||
stride: 40
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: RPR
|
||||
description: Rising pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 40
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: FPR
|
||||
description: Falling pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 40
|
||||
byte_offset: 16
|
||||
fieldset: LINES
|
||||
- name: EXTICR
|
||||
description: Configuration register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 96
|
||||
fieldset: EXTICR
|
||||
- name: IMR
|
||||
description: Interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 128
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: Event mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
fieldset/EXTICR:
|
||||
description: external interrupt configuration register 1
|
||||
fields:
|
||||
- name: EXTI
|
||||
description: EXTI configuration bits
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
- name: EXTI
|
||||
description: EXTI configuration bits
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
|
||||
@ -1,145 +1,144 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: Extended interrupt and event controller
|
||||
items:
|
||||
- name: RTSR
|
||||
description: rising trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: falling trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: software interrupt event register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: RPR
|
||||
description: rising edge pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: FPR
|
||||
description: falling edge pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 16
|
||||
fieldset: LINES
|
||||
- name: SECCFGR
|
||||
description: security configuration register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 20
|
||||
fieldset: SEC
|
||||
- name: PRIVCFGR
|
||||
description: privilege configuration register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 24
|
||||
fieldset: PRIV
|
||||
- name: EXTICR
|
||||
description: external interrupt selection register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 96
|
||||
fieldset: EXTI
|
||||
- name: LOCKR
|
||||
description: lock register
|
||||
byte_offset: 112
|
||||
fieldset: LOCKR
|
||||
- name: IMR
|
||||
description: CPU wakeup with interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 128
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: CPU wakeup with event mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
- name: RTSR
|
||||
description: rising trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: falling trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: software interrupt event register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: RPR
|
||||
description: rising edge pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: FPR
|
||||
description: falling edge pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 16
|
||||
fieldset: LINES
|
||||
- name: SECCFGR
|
||||
description: security configuration register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 20
|
||||
fieldset: SEC
|
||||
- name: PRIVCFGR
|
||||
description: privilege configuration register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 24
|
||||
fieldset: PRIV
|
||||
- name: EXTICR
|
||||
description: external interrupt selection register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 96
|
||||
fieldset: EXTI
|
||||
- name: LOCKR
|
||||
description: lock register
|
||||
byte_offset: 112
|
||||
fieldset: LOCKR
|
||||
- name: IMR
|
||||
description: CPU wakeup with interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 128
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: CPU wakeup with event mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
fieldset/EXTI:
|
||||
description: EXTI external interrupt selection register
|
||||
fields:
|
||||
- name: EXTI
|
||||
description: "EXTI12 GPIO port selection\r These bits are written by software to select the source input for EXTI12 external interrupt.\r When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded.\r Others: reserved"
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
- name: EXTI
|
||||
description: "EXTI12 GPIO port selection\r These bits are written by software to select the source input for EXTI12 external interrupt.\r When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded.\r Others: reserved"
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
fieldset/LOCKR:
|
||||
description: lock register
|
||||
fields:
|
||||
- name: LOCK
|
||||
description: "Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock \r This bit is written once after reset."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: "Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock \r This bit is written once after reset."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
fieldset/PRIV:
|
||||
description: privilege configuration register
|
||||
fields:
|
||||
- name: PRIV
|
||||
description: "Security enable on event input x\r When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access.\r When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
enum: PRIV
|
||||
- name: PRIV
|
||||
description: "Security enable on event input x\r When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access.\r When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
enum: PRIV
|
||||
fieldset/SEC:
|
||||
description: security configuration register
|
||||
fields:
|
||||
- name: SEC
|
||||
description: "Security enable on event input x\r When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
enum: SEC
|
||||
- name: SEC
|
||||
description: "Security enable on event input x\r When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
enum: SEC
|
||||
enum/PRIV:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Unprivileged
|
||||
description: Event privilege disabled (unprivileged)
|
||||
value: 0
|
||||
- name: Privileged
|
||||
description: Event privilege enabled (privileged)
|
||||
value: 1
|
||||
- name: Unprivileged
|
||||
description: Event privilege disabled (unprivileged)
|
||||
value: 0
|
||||
- name: Privileged
|
||||
description: Event privilege enabled (privileged)
|
||||
value: 1
|
||||
enum/SEC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NonSecure
|
||||
description: Event security disabled (non-secure)
|
||||
value: 0
|
||||
- name: Secure
|
||||
description: Event security enabled (secure)
|
||||
value: 1
|
||||
- name: NonSecure
|
||||
description: Event security disabled (non-secure)
|
||||
value: 0
|
||||
- name: Secure
|
||||
description: Event security enabled (secure)
|
||||
value: 1
|
||||
|
||||
@ -1,107 +1,106 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: Extended interrupt and event controller
|
||||
items:
|
||||
- name: RTSR
|
||||
description: rising trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: falling trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: software interrupt event register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: RPR
|
||||
description: rising edge pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: FPR
|
||||
description: falling edge pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 16
|
||||
fieldset: LINES
|
||||
- name: PRIVCFGR
|
||||
description: privilege configuration register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 24
|
||||
fieldset: PRIV
|
||||
- name: EXTICR
|
||||
description: external interrupt selection register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 96
|
||||
fieldset: EXTI
|
||||
- name: IMR
|
||||
description: CPU wakeup with interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 128
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: CPU wakeup with event mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
- name: RTSR
|
||||
description: rising trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: falling trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: software interrupt event register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: RPR
|
||||
description: rising edge pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: FPR
|
||||
description: falling edge pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 16
|
||||
fieldset: LINES
|
||||
- name: PRIVCFGR
|
||||
description: privilege configuration register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 24
|
||||
fieldset: PRIV
|
||||
- name: EXTICR
|
||||
description: external interrupt selection register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 96
|
||||
fieldset: EXTI
|
||||
- name: IMR
|
||||
description: CPU wakeup with interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 128
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: CPU wakeup with event mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
fieldset/EXTI:
|
||||
description: EXTI external interrupt selection register
|
||||
fields:
|
||||
- name: EXTI
|
||||
description: "EXTI12 GPIO port selection\r These bits are written by software to select the source input for EXTI12 external interrupt.\r When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded.\r Others: reserved"
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
- name: EXTI
|
||||
description: "EXTI12 GPIO port selection\r These bits are written by software to select the source input for EXTI12 external interrupt.\r When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded.\r Others: reserved"
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
fieldset/PRIV:
|
||||
description: privilege configuration register
|
||||
fields:
|
||||
- name: PRIV
|
||||
description: "Security enable on event input x\r When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access.\r When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
enum: PRIV
|
||||
- name: PRIV
|
||||
description: "Security enable on event input x\r When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access.\r When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
enum: PRIV
|
||||
enum/PRIV:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Unprivileged
|
||||
description: Event privilege disabled (unprivileged)
|
||||
value: 0
|
||||
- name: Privileged
|
||||
description: Event privilege enabled (privileged)
|
||||
value: 1
|
||||
- name: Unprivileged
|
||||
description: Event privilege disabled (unprivileged)
|
||||
value: 0
|
||||
- name: Privileged
|
||||
description: Event privilege enabled (privileged)
|
||||
value: 1
|
||||
|
||||
@ -1,56 +1,55 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
- name: RTSR
|
||||
description: Rising Trigger selection register
|
||||
array:
|
||||
len: 1
|
||||
stride: 0
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: Falling Trigger selection register
|
||||
array:
|
||||
len: 1
|
||||
stride: 0
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: Software interrupt event register
|
||||
array:
|
||||
len: 1
|
||||
stride: 0
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: IMR
|
||||
description: Interrupt mask register
|
||||
array:
|
||||
len: 1
|
||||
stride: 0
|
||||
byte_offset: 128
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: Event mask register
|
||||
array:
|
||||
len: 1
|
||||
stride: 0
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
- name: PR
|
||||
description: Pending register
|
||||
array:
|
||||
len: 1
|
||||
stride: 0
|
||||
byte_offset: 136
|
||||
fieldset: LINES
|
||||
- name: RTSR
|
||||
description: Rising Trigger selection register
|
||||
array:
|
||||
len: 1
|
||||
stride: 0
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: Falling Trigger selection register
|
||||
array:
|
||||
len: 1
|
||||
stride: 0
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: Software interrupt event register
|
||||
array:
|
||||
len: 1
|
||||
stride: 0
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: IMR
|
||||
description: Interrupt mask register
|
||||
array:
|
||||
len: 1
|
||||
stride: 0
|
||||
byte_offset: 128
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: Event mask register
|
||||
array:
|
||||
len: 1
|
||||
stride: 0
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
- name: PR
|
||||
description: Pending register
|
||||
array:
|
||||
len: 1
|
||||
stride: 0
|
||||
byte_offset: 136
|
||||
fieldset: LINES
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
|
||||
@ -1,125 +1,124 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
- name: RTSR
|
||||
description: Rising Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: Falling Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: Software interrupt event register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: RPR
|
||||
description: Rising pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: FPR
|
||||
description: Falling pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 16
|
||||
fieldset: LINES
|
||||
- name: SECCFGR
|
||||
description: Security configuration register
|
||||
array:
|
||||
len: 2
|
||||
stride: 36
|
||||
byte_offset: 20
|
||||
fieldset: SECCFGR
|
||||
- name: PRIVCFGR
|
||||
description: Privilege configuration register
|
||||
array:
|
||||
len: 2
|
||||
stride: 28
|
||||
byte_offset: 24
|
||||
fieldset: PRIVCFGR
|
||||
- name: EXTICR
|
||||
description: Configuration register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 96
|
||||
fieldset: EXTICR
|
||||
- name: LOCKRG
|
||||
description: EXTI lock register
|
||||
byte_offset: 112
|
||||
fieldset: LOCKRG
|
||||
- name: IMR
|
||||
description: Interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 128
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: Event mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
- name: RTSR
|
||||
description: Rising Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: Falling Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: Software interrupt event register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: RPR
|
||||
description: Rising pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: FPR
|
||||
description: Falling pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 16
|
||||
fieldset: LINES
|
||||
- name: SECCFGR
|
||||
description: Security configuration register
|
||||
array:
|
||||
len: 2
|
||||
stride: 36
|
||||
byte_offset: 20
|
||||
fieldset: SECCFGR
|
||||
- name: PRIVCFGR
|
||||
description: Privilege configuration register
|
||||
array:
|
||||
len: 2
|
||||
stride: 28
|
||||
byte_offset: 24
|
||||
fieldset: PRIVCFGR
|
||||
- name: EXTICR
|
||||
description: Configuration register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 96
|
||||
fieldset: EXTICR
|
||||
- name: LOCKRG
|
||||
description: EXTI lock register
|
||||
byte_offset: 112
|
||||
fieldset: LOCKRG
|
||||
- name: IMR
|
||||
description: Interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 128
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: Event mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
fieldset/EXTICR:
|
||||
description: external interrupt configuration register 1
|
||||
fields:
|
||||
- name: EXTI
|
||||
description: EXTI configuration bits
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
- name: EXTI
|
||||
description: EXTI configuration bits
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
fieldset/LOCKRG:
|
||||
description: EXTI lock register
|
||||
fields:
|
||||
- name: LOCK
|
||||
description: LOCK
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: LOCK
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
fieldset/PRIVCFGR:
|
||||
description: Privilege configuration register
|
||||
fields:
|
||||
- name: PRIV
|
||||
description: Security enable on event input x
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
- name: PRIV
|
||||
description: Security enable on event input x
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
fieldset/SECCFGR:
|
||||
description: Security configuration register
|
||||
fields:
|
||||
- name: SEC
|
||||
description: Security enable on event input x
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
- name: SEC
|
||||
description: Security enable on event input x
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
|
||||
@ -1,125 +1,124 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
- name: RTSR
|
||||
description: Rising Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: Falling Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: Software interrupt event register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: RPR
|
||||
description: Rising pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: FPR
|
||||
description: Falling pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 16
|
||||
fieldset: LINES
|
||||
- name: SECCFGR
|
||||
description: Security configuration register
|
||||
array:
|
||||
len: 2
|
||||
stride: 36
|
||||
byte_offset: 20
|
||||
fieldset: SECCFGR
|
||||
- name: PRIVCFGR
|
||||
description: Privilege configuration register
|
||||
array:
|
||||
len: 2
|
||||
stride: 28
|
||||
byte_offset: 24
|
||||
fieldset: PRIVCFGR
|
||||
- name: EXTICR
|
||||
description: Configuration register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 96
|
||||
fieldset: EXTICR
|
||||
- name: LOCKRG
|
||||
description: EXTI lock register
|
||||
byte_offset: 112
|
||||
fieldset: LOCKRG
|
||||
- name: IMR
|
||||
description: Interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 128
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: Event mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
- name: RTSR
|
||||
description: Rising Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: Falling Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: Software interrupt event register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: RPR
|
||||
description: Rising pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: FPR
|
||||
description: Falling pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 16
|
||||
fieldset: LINES
|
||||
- name: SECCFGR
|
||||
description: Security configuration register
|
||||
array:
|
||||
len: 2
|
||||
stride: 36
|
||||
byte_offset: 20
|
||||
fieldset: SECCFGR
|
||||
- name: PRIVCFGR
|
||||
description: Privilege configuration register
|
||||
array:
|
||||
len: 2
|
||||
stride: 28
|
||||
byte_offset: 24
|
||||
fieldset: PRIVCFGR
|
||||
- name: EXTICR
|
||||
description: Configuration register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 96
|
||||
fieldset: EXTICR
|
||||
- name: LOCKRG
|
||||
description: EXTI lock register
|
||||
byte_offset: 112
|
||||
fieldset: LOCKRG
|
||||
- name: IMR
|
||||
description: Interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 128
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: Event mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
fieldset/EXTICR:
|
||||
description: external interrupt configuration register 1
|
||||
fields:
|
||||
- name: EXTI
|
||||
description: EXTI configuration bits
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
- name: EXTI
|
||||
description: EXTI configuration bits
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
fieldset/LOCKRG:
|
||||
description: EXTI lock register
|
||||
fields:
|
||||
- name: LOCK
|
||||
description: LOCK
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: LOCK
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
fieldset/PRIVCFGR:
|
||||
description: Privilege configuration register
|
||||
fields:
|
||||
- name: PRIV
|
||||
description: Security enable on event input x
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
- name: PRIV
|
||||
description: Security enable on event input x
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
fieldset/SECCFGR:
|
||||
description: Security configuration register
|
||||
fields:
|
||||
- name: SEC
|
||||
description: Security enable on event input x
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
- name: SEC
|
||||
description: Security enable on event input x
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
|
||||
@ -1,56 +1,55 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
- name: IMR
|
||||
description: Interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: Interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: RTSR
|
||||
description: Rising Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: Falling Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: Software interrupt event register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 16
|
||||
fieldset: LINES
|
||||
- name: PR
|
||||
description: Pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 20
|
||||
fieldset: LINES
|
||||
- name: IMR
|
||||
description: Interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: Interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: RTSR
|
||||
description: Rising Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: Falling Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: Software interrupt event register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 16
|
||||
fieldset: LINES
|
||||
- name: PR
|
||||
description: Pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 20
|
||||
fieldset: LINES
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
|
||||
@ -1,66 +1,65 @@
|
||||
---
|
||||
block/CPU:
|
||||
description: CPU-specific registers
|
||||
items:
|
||||
- name: IMR
|
||||
description: CPU x interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: CPU x event mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: IMR
|
||||
description: CPU x interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: CPU x event mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
- name: RTSR
|
||||
description: rising trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: falling trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: software interrupt event register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: PR
|
||||
description: EXTI pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: CPU
|
||||
description: CPU specific registers
|
||||
array:
|
||||
len: 2
|
||||
stride: 64
|
||||
byte_offset: 128
|
||||
block: CPU
|
||||
- name: RTSR
|
||||
description: rising trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: falling trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: software interrupt event register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: PR
|
||||
description: EXTI pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: CPU
|
||||
description: CPU specific registers
|
||||
array:
|
||||
len: 2
|
||||
stride: 64
|
||||
byte_offset: 128
|
||||
block: CPU
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
|
||||
@ -1,56 +1,55 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
- name: RTSR
|
||||
description: Rising Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: Falling Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: Software interrupt event register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: PR
|
||||
description: Pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: IMR
|
||||
description: Interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 128
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: Event mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
- name: RTSR
|
||||
description: Rising Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 0
|
||||
fieldset: LINES
|
||||
- name: FTSR
|
||||
description: Falling Trigger selection register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 4
|
||||
fieldset: LINES
|
||||
- name: SWIER
|
||||
description: Software interrupt event register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 8
|
||||
fieldset: LINES
|
||||
- name: PR
|
||||
description: Pending register
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 12
|
||||
fieldset: LINES
|
||||
- name: IMR
|
||||
description: Interrupt mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 128
|
||||
fieldset: LINES
|
||||
- name: EMR
|
||||
description: Event mask register
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
|
||||
@ -1,424 +1,423 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
- name: ACR
|
||||
description: Access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Option byte key register
|
||||
byte_offset: 12
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 16
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Flash control register
|
||||
byte_offset: 20
|
||||
fieldset: CR
|
||||
- name: OPTR
|
||||
description: Flash option register
|
||||
byte_offset: 32
|
||||
fieldset: OPTR
|
||||
- name: PCROP1ASR
|
||||
description: Flash PCROP zone A Start address register
|
||||
byte_offset: 36
|
||||
access: Read
|
||||
fieldset: PCROP1ASR
|
||||
- name: PCROP1AER
|
||||
description: Flash PCROP zone A End address register
|
||||
byte_offset: 40
|
||||
access: Read
|
||||
fieldset: PCROP1AER
|
||||
- name: WRP1AR
|
||||
description: Flash WRP area A address register
|
||||
byte_offset: 44
|
||||
access: Read
|
||||
fieldset: WRP1AR
|
||||
- name: WRP1BR
|
||||
description: Flash WRP area B address register
|
||||
byte_offset: 48
|
||||
access: Read
|
||||
fieldset: WRP1BR
|
||||
- name: PCROP1BSR
|
||||
description: Flash PCROP zone B Start address register
|
||||
byte_offset: 52
|
||||
access: Read
|
||||
fieldset: PCROP1BSR
|
||||
- name: PCROP1BER
|
||||
description: Flash PCROP zone B End address register
|
||||
byte_offset: 56
|
||||
access: Read
|
||||
fieldset: PCROP1BER
|
||||
- name: SECR
|
||||
description: Flash Security register
|
||||
byte_offset: 128
|
||||
access: Read
|
||||
fieldset: SECR
|
||||
- name: ACR
|
||||
description: Access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Option byte key register
|
||||
byte_offset: 12
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 16
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Flash control register
|
||||
byte_offset: 20
|
||||
fieldset: CR
|
||||
- name: OPTR
|
||||
description: Flash option register
|
||||
byte_offset: 32
|
||||
fieldset: OPTR
|
||||
- name: PCROP1ASR
|
||||
description: Flash PCROP zone A Start address register
|
||||
byte_offset: 36
|
||||
access: Read
|
||||
fieldset: PCROP1ASR
|
||||
- name: PCROP1AER
|
||||
description: Flash PCROP zone A End address register
|
||||
byte_offset: 40
|
||||
access: Read
|
||||
fieldset: PCROP1AER
|
||||
- name: WRP1AR
|
||||
description: Flash WRP area A address register
|
||||
byte_offset: 44
|
||||
access: Read
|
||||
fieldset: WRP1AR
|
||||
- name: WRP1BR
|
||||
description: Flash WRP area B address register
|
||||
byte_offset: 48
|
||||
access: Read
|
||||
fieldset: WRP1BR
|
||||
- name: PCROP1BSR
|
||||
description: Flash PCROP zone B Start address register
|
||||
byte_offset: 52
|
||||
access: Read
|
||||
fieldset: PCROP1BSR
|
||||
- name: PCROP1BER
|
||||
description: Flash PCROP zone B End address register
|
||||
byte_offset: 56
|
||||
access: Read
|
||||
fieldset: PCROP1BER
|
||||
- name: SECR
|
||||
description: Flash Security register
|
||||
byte_offset: 128
|
||||
access: Read
|
||||
fieldset: SECR
|
||||
fieldset/ACR:
|
||||
description: Access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: LATENCY
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ICEN
|
||||
description: Instruction cache enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ICRST
|
||||
description: Instruction cache reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: EMPTY
|
||||
description: Flash User area empty
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: DBG_SWEN
|
||||
description: Debug access software enable
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: LATENCY
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ICEN
|
||||
description: Instruction cache enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ICRST
|
||||
description: Instruction cache reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: EMPTY
|
||||
description: Flash User area empty
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: DBG_SWEN
|
||||
description: Debug access software enable
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Flash control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Mass erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PNB
|
||||
description: Page number
|
||||
bit_offset: 3
|
||||
bit_size: 4
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: Options modification start
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: FSTPG
|
||||
description: Fast programming
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: RDERRIE
|
||||
description: PCROP read error interrupt enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: Force the option byte loading
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: SEC_PROT
|
||||
description: Securable memory area protection enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: Options Lock
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: FLASH_CR Lock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Mass erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PNB
|
||||
description: Page number
|
||||
bit_offset: 3
|
||||
bit_size: 4
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: Options modification start
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: FSTPG
|
||||
description: Fast programming
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: RDERRIE
|
||||
description: PCROP read error interrupt enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: Force the option byte loading
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: SEC_PROT
|
||||
description: Securable memory area protection enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: Options Lock
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: FLASH_CR Lock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/KEYR:
|
||||
description: Flash key register
|
||||
fields:
|
||||
- name: KEYR
|
||||
description: KEYR
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: KEYR
|
||||
description: KEYR
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTKEYR:
|
||||
description: Option byte key register
|
||||
fields:
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTR:
|
||||
description: Flash option register
|
||||
fields:
|
||||
- name: RDP
|
||||
description: Read protection level
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
enum: RDP
|
||||
- name: BOREN
|
||||
description: BOR reset Level
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: BORF_LEV
|
||||
description: These bits contain the VDD supply level threshold that activates the reset
|
||||
bit_offset: 9
|
||||
bit_size: 2
|
||||
enum: BORF_LEV
|
||||
- name: BORR_LEV
|
||||
description: These bits contain the VDD supply level threshold that releases the reset.
|
||||
bit_offset: 11
|
||||
bit_size: 2
|
||||
enum: BORR_LEV
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: nRSTS_HDW
|
||||
description: nRSTS_HDW
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: IDWG_SW
|
||||
description: Independent watchdog selection
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: IWDG_STOP
|
||||
description: Independent watchdog counter freeze in Stop mode
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: IWDG_STDBY
|
||||
description: Independent watchdog counter freeze in Standby mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: WWDG_SW
|
||||
description: Window watchdog selection
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: RAM_PARITY_CHECK
|
||||
description: SRAM parity check control
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: nBOOT_SEL
|
||||
description: nBOOT_SEL
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: nBOOT1
|
||||
description: Boot configuration
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: nBOOT0
|
||||
description: nBOOT0 option bit
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: NRST_MODE
|
||||
description: NRST_MODE
|
||||
bit_offset: 27
|
||||
bit_size: 2
|
||||
enum: NRST_MODE
|
||||
- name: IRHEN
|
||||
description: Internal reset holder enable bit
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: RDP
|
||||
description: Read protection level
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
enum: RDP
|
||||
- name: BOREN
|
||||
description: BOR reset Level
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: BORF_LEV
|
||||
description: These bits contain the VDD supply level threshold that activates the reset
|
||||
bit_offset: 9
|
||||
bit_size: 2
|
||||
enum: BORF_LEV
|
||||
- name: BORR_LEV
|
||||
description: These bits contain the VDD supply level threshold that releases the reset.
|
||||
bit_offset: 11
|
||||
bit_size: 2
|
||||
enum: BORR_LEV
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: nRSTS_HDW
|
||||
description: nRSTS_HDW
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: IDWG_SW
|
||||
description: Independent watchdog selection
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: IWDG_STOP
|
||||
description: Independent watchdog counter freeze in Stop mode
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: IWDG_STDBY
|
||||
description: Independent watchdog counter freeze in Standby mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: WWDG_SW
|
||||
description: Window watchdog selection
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: RAM_PARITY_CHECK
|
||||
description: SRAM parity check control
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: nBOOT_SEL
|
||||
description: nBOOT_SEL
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: nBOOT1
|
||||
description: Boot configuration
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: nBOOT0
|
||||
description: nBOOT0 option bit
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: NRST_MODE
|
||||
description: NRST_MODE
|
||||
bit_offset: 27
|
||||
bit_size: 2
|
||||
enum: NRST_MODE
|
||||
- name: IRHEN
|
||||
description: Internal reset holder enable bit
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
fieldset/PCROP1AER:
|
||||
description: Flash PCROP zone A End address register
|
||||
fields:
|
||||
- name: PCROP1A_END
|
||||
description: PCROP1A area end offset
|
||||
bit_offset: 0
|
||||
bit_size: 6
|
||||
- name: PCROP_RDP
|
||||
description: PCROP area preserved when RDP level decreased
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: PCROP1A_END
|
||||
description: PCROP1A area end offset
|
||||
bit_offset: 0
|
||||
bit_size: 6
|
||||
- name: PCROP_RDP
|
||||
description: PCROP area preserved when RDP level decreased
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/PCROP1ASR:
|
||||
description: Flash PCROP zone A Start address register
|
||||
fields:
|
||||
- name: PCROP1A_STRT
|
||||
description: PCROP1A area start offset
|
||||
bit_offset: 0
|
||||
bit_size: 6
|
||||
- name: PCROP1A_STRT
|
||||
description: PCROP1A area start offset
|
||||
bit_offset: 0
|
||||
bit_size: 6
|
||||
fieldset/PCROP1BER:
|
||||
description: Flash PCROP zone B End address register
|
||||
fields:
|
||||
- name: PCROP1B_END
|
||||
description: PCROP1B area end offset
|
||||
bit_offset: 0
|
||||
bit_size: 6
|
||||
- name: PCROP1B_END
|
||||
description: PCROP1B area end offset
|
||||
bit_offset: 0
|
||||
bit_size: 6
|
||||
fieldset/PCROP1BSR:
|
||||
description: Flash PCROP zone B Start address register
|
||||
fields:
|
||||
- name: PCROP1B_STRT
|
||||
description: PCROP1B area start offset
|
||||
bit_offset: 0
|
||||
bit_size: 6
|
||||
- name: PCROP1B_STRT
|
||||
description: PCROP1B area start offset
|
||||
bit_offset: 0
|
||||
bit_size: 6
|
||||
fieldset/SECR:
|
||||
description: Flash Security register
|
||||
fields:
|
||||
- name: SEC_SIZE
|
||||
description: Securable memory area size
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: BOOT_LOCK
|
||||
description: used to force boot from user area
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: SEC_SIZE
|
||||
description: Securable memory area size
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: BOOT_LOCK
|
||||
description: used to force boot from user area
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Operation error
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PROGERR
|
||||
description: Programming error
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protected error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: Size error
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: Programming sequence error
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: MISERR
|
||||
description: Fast programming data miss error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: FASTERR
|
||||
description: Fast programming error
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: PCROP read error
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: OPTVERR
|
||||
description: Option and Engineering bits loading validity error
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: CFGBSY
|
||||
description: Programming or erase configuration busy.
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Operation error
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PROGERR
|
||||
description: Programming error
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protected error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: Size error
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: Programming sequence error
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: MISERR
|
||||
description: Fast programming data miss error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: FASTERR
|
||||
description: Fast programming error
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: PCROP read error
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: OPTVERR
|
||||
description: Option and Engineering bits loading validity error
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: CFGBSY
|
||||
description: Programming or erase configuration busy.
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/WRP1AR:
|
||||
description: Flash WRP area A address register
|
||||
fields:
|
||||
- name: WRP1A_STRT
|
||||
description: WRP area A start offset
|
||||
bit_offset: 0
|
||||
bit_size: 6
|
||||
- name: WRP1A_END
|
||||
description: WRP area A end offset
|
||||
bit_offset: 16
|
||||
bit_size: 6
|
||||
- name: WRP1A_STRT
|
||||
description: WRP area A start offset
|
||||
bit_offset: 0
|
||||
bit_size: 6
|
||||
- name: WRP1A_END
|
||||
description: WRP area A end offset
|
||||
bit_offset: 16
|
||||
bit_size: 6
|
||||
fieldset/WRP1BR:
|
||||
description: Flash WRP area B address register
|
||||
fields:
|
||||
- name: WRP1B_STRT
|
||||
description: WRP area B start offset
|
||||
bit_offset: 0
|
||||
bit_size: 6
|
||||
- name: WRP1B_END
|
||||
description: WRP area B end offset
|
||||
bit_offset: 16
|
||||
bit_size: 6
|
||||
- name: WRP1B_STRT
|
||||
description: WRP area B start offset
|
||||
bit_offset: 0
|
||||
bit_size: 6
|
||||
- name: WRP1B_END
|
||||
description: WRP area B end offset
|
||||
bit_offset: 16
|
||||
bit_size: 6
|
||||
enum/BORF_LEV:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: FALLING_0
|
||||
description: BOR falling level 1 with threshold around 2.0V
|
||||
value: 0
|
||||
- name: FALLING_1
|
||||
description: BOR falling level 2 with threshold around 2.2V
|
||||
value: 1
|
||||
- name: FALLING_2
|
||||
description: BOR falling level 3 with threshold around 2.5V
|
||||
value: 2
|
||||
- name: FALLING_3
|
||||
description: BOR falling level 4 with threshold around 2.8V
|
||||
value: 3
|
||||
- name: FALLING_0
|
||||
description: BOR falling level 1 with threshold around 2.0V
|
||||
value: 0
|
||||
- name: FALLING_1
|
||||
description: BOR falling level 2 with threshold around 2.2V
|
||||
value: 1
|
||||
- name: FALLING_2
|
||||
description: BOR falling level 3 with threshold around 2.5V
|
||||
value: 2
|
||||
- name: FALLING_3
|
||||
description: BOR falling level 4 with threshold around 2.8V
|
||||
value: 3
|
||||
enum/BORR_LEV:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: RISING_0
|
||||
description: BOR rising level 1 with threshold around 2.1V
|
||||
value: 0
|
||||
- name: RISING_1
|
||||
description: BOR rising level 2 with threshold around 2.3V
|
||||
value: 1
|
||||
- name: RISING_2
|
||||
description: BOR rising level 3 with threshold around 2.6V
|
||||
value: 2
|
||||
- name: RISING_3
|
||||
description: BOR rising level 4 with threshold around 2.9V
|
||||
value: 3
|
||||
- name: RISING_0
|
||||
description: BOR rising level 1 with threshold around 2.1V
|
||||
value: 0
|
||||
- name: RISING_1
|
||||
description: BOR rising level 2 with threshold around 2.3V
|
||||
value: 1
|
||||
- name: RISING_2
|
||||
description: BOR rising level 3 with threshold around 2.6V
|
||||
value: 2
|
||||
- name: RISING_3
|
||||
description: BOR rising level 4 with threshold around 2.9V
|
||||
value: 3
|
||||
enum/LATENCY:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: WS0
|
||||
description: Zero wait states
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: One wait state
|
||||
value: 1
|
||||
- name: WS0
|
||||
description: Zero wait states
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: One wait state
|
||||
value: 1
|
||||
enum/NRST_MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: INPUT_ONLY
|
||||
description: Reset pin is in reset input mode only
|
||||
value: 1
|
||||
- name: GPIO
|
||||
description: Reset pin is in GPIO mode only
|
||||
value: 2
|
||||
- name: INPUT_OUTPUT
|
||||
description: Reset pin is in resety input and output mode
|
||||
value: 3
|
||||
- name: INPUT_ONLY
|
||||
description: Reset pin is in reset input mode only
|
||||
value: 1
|
||||
- name: GPIO
|
||||
description: Reset pin is in GPIO mode only
|
||||
value: 2
|
||||
- name: INPUT_OUTPUT
|
||||
description: Reset pin is in resety input and output mode
|
||||
value: 3
|
||||
enum/RDP:
|
||||
bit_size: 8
|
||||
variants:
|
||||
- name: LEVEL_0
|
||||
description: Read protection not active
|
||||
value: 170
|
||||
- name: LEVEL_1
|
||||
description: Memories read protection active
|
||||
value: 187
|
||||
- name: LEVEL_2
|
||||
description: Chip read protection active
|
||||
value: 204
|
||||
- name: LEVEL_0
|
||||
description: Read protection not active
|
||||
value: 170
|
||||
- name: LEVEL_1
|
||||
description: Memories read protection active
|
||||
value: 187
|
||||
- name: LEVEL_2
|
||||
description: Chip read protection active
|
||||
value: 204
|
||||
|
||||
@ -1,304 +1,303 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
- name: ACR
|
||||
description: Flash access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Flash option key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Flash status register
|
||||
byte_offset: 12
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Flash control register
|
||||
byte_offset: 16
|
||||
fieldset: CR
|
||||
- name: AR
|
||||
description: Flash address register
|
||||
byte_offset: 20
|
||||
access: Write
|
||||
fieldset: AR
|
||||
- name: OBR
|
||||
description: Option byte register
|
||||
byte_offset: 28
|
||||
access: Read
|
||||
fieldset: OBR
|
||||
- name: WRPR
|
||||
description: Write protection register
|
||||
byte_offset: 32
|
||||
access: Read
|
||||
fieldset: WRPR
|
||||
- name: ACR
|
||||
description: Flash access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Flash option key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Flash status register
|
||||
byte_offset: 12
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Flash control register
|
||||
byte_offset: 16
|
||||
fieldset: CR
|
||||
- name: AR
|
||||
description: Flash address register
|
||||
byte_offset: 20
|
||||
access: Write
|
||||
fieldset: AR
|
||||
- name: OBR
|
||||
description: Option byte register
|
||||
byte_offset: 28
|
||||
access: Read
|
||||
fieldset: OBR
|
||||
- name: WRPR
|
||||
description: Write protection register
|
||||
byte_offset: 32
|
||||
access: Read
|
||||
fieldset: WRPR
|
||||
fieldset/ACR:
|
||||
description: Flash access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: LATENCY
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: LATENCY
|
||||
- name: PRFTBE
|
||||
description: Prefetch buffer enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PRFTBS
|
||||
description: Prefetch buffer status
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: LATENCY
|
||||
description: LATENCY
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: LATENCY
|
||||
- name: PRFTBE
|
||||
description: Prefetch buffer enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PRFTBS
|
||||
description: Prefetch buffer status
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/AR:
|
||||
description: Flash address register
|
||||
fields:
|
||||
- name: FAR
|
||||
description: Flash address
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: FAR
|
||||
description: Flash address
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/CR:
|
||||
description: Flash control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Mass erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: OPTPG
|
||||
description: Option byte programming
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: OPTER
|
||||
description: Option byte erase
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: Lock
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: OPTWRE
|
||||
description: Option bytes write enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: FORCE_OPTLOAD
|
||||
description: Force option byte loading
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Mass erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: OPTPG
|
||||
description: Option byte programming
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: OPTER
|
||||
description: Option byte erase
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: Lock
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: OPTWRE
|
||||
description: Option bytes write enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: FORCE_OPTLOAD
|
||||
description: Force option byte loading
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
fieldset/KEYR:
|
||||
description: Flash key register
|
||||
fields:
|
||||
- name: FKEYR
|
||||
description: Flash Key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: FKEYR
|
||||
description: Flash Key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OBR:
|
||||
description: Option byte register
|
||||
fields:
|
||||
- name: OPTERR
|
||||
description: Option byte error
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RDPRT
|
||||
description: Read protection level status
|
||||
bit_offset: 1
|
||||
bit_size: 2
|
||||
enum: RDPRT
|
||||
- name: WDG_SW
|
||||
description: WDG_SW
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: WDG_SW
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: nRST_STOP
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: nRST_STDBY
|
||||
- name: nBOOT0
|
||||
description: nBOOT0
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
enum: nBOOT0
|
||||
- name: nBOOT1
|
||||
description: BOOT1
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
enum: nBOOT1
|
||||
- name: VDDA_MONITOR
|
||||
description: VDDA_MONITOR
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
enum: VDDA_MONITOR
|
||||
- name: RAM_PARITY_CHECK
|
||||
description: RAM_PARITY_CHECK
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
enum: RAM_PARITY_CHECK
|
||||
- name: BOOT_SEL
|
||||
description: BOOT_SEL
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum: BOOT_SEL
|
||||
- name: Data0
|
||||
description: Data0
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: Data1
|
||||
description: Data1
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
- name: OPTERR
|
||||
description: Option byte error
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RDPRT
|
||||
description: Read protection level status
|
||||
bit_offset: 1
|
||||
bit_size: 2
|
||||
enum: RDPRT
|
||||
- name: WDG_SW
|
||||
description: WDG_SW
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: WDG_SW
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: nRST_STOP
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: nRST_STDBY
|
||||
- name: nBOOT0
|
||||
description: nBOOT0
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
enum: nBOOT0
|
||||
- name: nBOOT1
|
||||
description: BOOT1
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
enum: nBOOT1
|
||||
- name: VDDA_MONITOR
|
||||
description: VDDA_MONITOR
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
enum: VDDA_MONITOR
|
||||
- name: RAM_PARITY_CHECK
|
||||
description: RAM_PARITY_CHECK
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
enum: RAM_PARITY_CHECK
|
||||
- name: BOOT_SEL
|
||||
description: BOOT_SEL
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum: BOOT_SEL
|
||||
- name: Data0
|
||||
description: Data0
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: Data1
|
||||
description: Data1
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
fieldset/OPTKEYR:
|
||||
description: Flash option key register
|
||||
fields:
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Flash status register
|
||||
fields:
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PGERR
|
||||
description: Programming error
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: WRPRT
|
||||
description: Write protection error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PGERR
|
||||
description: Programming error
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: WRPRT
|
||||
description: Write protection error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/WRPR:
|
||||
description: Write protection register
|
||||
fields:
|
||||
- name: WRP
|
||||
description: Write protect
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: WRP
|
||||
description: Write protect
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
enum/BOOT_SEL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: nBOOT0
|
||||
description: BOOT0 signal is defined by nBOOT0 option bit
|
||||
value: 0
|
||||
- name: BOOT0
|
||||
description: BOOT0 signal is defined by BOOT0 pin value (legacy mode)
|
||||
value: 1
|
||||
- name: nBOOT0
|
||||
description: BOOT0 signal is defined by nBOOT0 option bit
|
||||
value: 0
|
||||
- name: BOOT0
|
||||
description: BOOT0 signal is defined by BOOT0 pin value (legacy mode)
|
||||
value: 1
|
||||
enum/LATENCY:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: WS0
|
||||
description: 0 wait states
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: 1 wait state
|
||||
value: 1
|
||||
- name: WS0
|
||||
description: 0 wait states
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: 1 wait state
|
||||
value: 1
|
||||
enum/RAM_PARITY_CHECK:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enabled
|
||||
description: RAM parity check enabled
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: RAM parity check disabled
|
||||
value: 1
|
||||
- name: Enabled
|
||||
description: RAM parity check enabled
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: RAM parity check disabled
|
||||
value: 1
|
||||
enum/RDPRT:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Level0
|
||||
description: Level 0
|
||||
value: 0
|
||||
- name: Level1
|
||||
description: Level 1
|
||||
value: 1
|
||||
- name: Level2
|
||||
description: Level 2
|
||||
value: 3
|
||||
- name: Level0
|
||||
description: Level 0
|
||||
value: 0
|
||||
- name: Level1
|
||||
description: Level 1
|
||||
value: 1
|
||||
- name: Level2
|
||||
description: Level 2
|
||||
value: 3
|
||||
enum/VDDA_MONITOR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: VDDA power supply supervisor disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: VDDA power supply supervisor enabled
|
||||
value: 1
|
||||
- name: Disabled
|
||||
description: VDDA power supply supervisor disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: VDDA power supply supervisor enabled
|
||||
value: 1
|
||||
enum/WDG_SW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Hardware
|
||||
description: Hardware watchdog
|
||||
value: 0
|
||||
- name: Software
|
||||
description: Software watchdog
|
||||
value: 1
|
||||
- name: Hardware
|
||||
description: Hardware watchdog
|
||||
value: 0
|
||||
- name: Software
|
||||
description: Software watchdog
|
||||
value: 1
|
||||
enum/nBOOT0:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: "When BOOT_SEL is cleared, select the device boot mode"
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "When BOOT_SEL is cleared, select the device boot mode"
|
||||
value: 1
|
||||
- name: Disabled
|
||||
description: When BOOT_SEL is cleared, select the device boot mode
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: When BOOT_SEL is cleared, select the device boot mode
|
||||
value: 1
|
||||
enum/nBOOT1:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: "Together with BOOT0, select the device boot mode"
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "Together with BOOT0, select the device boot mode"
|
||||
value: 1
|
||||
- name: Disabled
|
||||
description: Together with BOOT0, select the device boot mode
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Together with BOOT0, select the device boot mode
|
||||
value: 1
|
||||
enum/nRST_STDBY:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Reset
|
||||
description: Reset generated when entering Standby mode
|
||||
value: 0
|
||||
- name: NoReset
|
||||
description: No reset generated
|
||||
value: 1
|
||||
- name: Reset
|
||||
description: Reset generated when entering Standby mode
|
||||
value: 0
|
||||
- name: NoReset
|
||||
description: No reset generated
|
||||
value: 1
|
||||
enum/nRST_STOP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Reset
|
||||
description: Reset generated when entering Stop mode
|
||||
value: 0
|
||||
- name: NoReset
|
||||
description: No reset generated
|
||||
value: 1
|
||||
- name: Reset
|
||||
description: Reset generated when entering Stop mode
|
||||
value: 0
|
||||
- name: NoReset
|
||||
description: No reset generated
|
||||
value: 1
|
||||
|
||||
@ -1,194 +1,193 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: FLASH
|
||||
items:
|
||||
- name: ACR
|
||||
description: Flash access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Flash option key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 12
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 16
|
||||
fieldset: CR
|
||||
- name: AR
|
||||
description: Flash address register
|
||||
byte_offset: 20
|
||||
access: Write
|
||||
fieldset: AR
|
||||
- name: OBR
|
||||
description: Option byte register
|
||||
byte_offset: 28
|
||||
access: Read
|
||||
fieldset: OBR
|
||||
- name: WRPR
|
||||
description: Write protection register
|
||||
byte_offset: 32
|
||||
access: Read
|
||||
fieldset: WRPR
|
||||
- name: ACR
|
||||
description: Flash access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Flash option key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 12
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 16
|
||||
fieldset: CR
|
||||
- name: AR
|
||||
description: Flash address register
|
||||
byte_offset: 20
|
||||
access: Write
|
||||
fieldset: AR
|
||||
- name: OBR
|
||||
description: Option byte register
|
||||
byte_offset: 28
|
||||
access: Read
|
||||
fieldset: OBR
|
||||
- name: WRPR
|
||||
description: Write protection register
|
||||
byte_offset: 32
|
||||
access: Read
|
||||
fieldset: WRPR
|
||||
fieldset/ACR:
|
||||
description: Flash access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: LATENCY
|
||||
- name: HLFCYA
|
||||
description: Flash half cycle access enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: PRFTBE
|
||||
description: Prefetch buffer enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PRFTBS
|
||||
description: Prefetch buffer status
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: LATENCY
|
||||
- name: HLFCYA
|
||||
description: Flash half cycle access enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: PRFTBE
|
||||
description: Prefetch buffer enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PRFTBS
|
||||
description: Prefetch buffer status
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/AR:
|
||||
description: Flash address register
|
||||
fields:
|
||||
- name: FAR
|
||||
description: Flash Address
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: FAR
|
||||
description: Flash Address
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Page Erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Mass Erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: OPTPG
|
||||
description: Option byte programming
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: OPTER
|
||||
description: Option byte erase
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: Lock
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: OPTWRE
|
||||
description: Option bytes write enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Page Erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Mass Erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: OPTPG
|
||||
description: Option byte programming
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: OPTER
|
||||
description: Option byte erase
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: Lock
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: OPTWRE
|
||||
description: Option bytes write enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
fieldset/KEYR:
|
||||
description: Flash key register
|
||||
fields:
|
||||
- name: KEY
|
||||
description: FPEC key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: KEY
|
||||
description: FPEC key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OBR:
|
||||
description: Option byte register
|
||||
fields:
|
||||
- name: OPTERR
|
||||
description: Option byte error
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RDPRT
|
||||
description: Read protection
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WDG_SW
|
||||
description: WDG_SW
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: Data0
|
||||
description: Data0
|
||||
bit_offset: 10
|
||||
bit_size: 8
|
||||
- name: Data1
|
||||
description: Data1
|
||||
bit_offset: 18
|
||||
bit_size: 8
|
||||
- name: OPTERR
|
||||
description: Option byte error
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RDPRT
|
||||
description: Read protection
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WDG_SW
|
||||
description: WDG_SW
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: Data0
|
||||
description: Data0
|
||||
bit_offset: 10
|
||||
bit_size: 8
|
||||
- name: Data1
|
||||
description: Data1
|
||||
bit_offset: 18
|
||||
bit_size: 8
|
||||
fieldset/OPTKEYR:
|
||||
description: Flash option key register
|
||||
fields:
|
||||
- name: OPTKEY
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: OPTKEY
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PGERR
|
||||
description: Programming error
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: WRPRTERR
|
||||
description: Write protection error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PGERR
|
||||
description: Programming error
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: WRPRTERR
|
||||
description: Write protection error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/WRPR:
|
||||
description: Write protection register
|
||||
fields:
|
||||
- name: WRP
|
||||
description: Write protect
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: WRP
|
||||
description: Write protect
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
enum/LATENCY:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: WS0
|
||||
description: "Zero wait state, if 0 < SYSCLK≤ 24 MHz"
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: "One wait state, if 24 MHz < SYSCLK ≤ 48 MHz"
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: "Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz"
|
||||
value: 2
|
||||
- name: WS0
|
||||
description: Zero wait state, if 0 < SYSCLK≤ 24 MHz
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: One wait state, if 24 MHz < SYSCLK ≤ 48 MHz
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz
|
||||
value: 2
|
||||
|
||||
@ -1,220 +1,219 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: FLASH
|
||||
items:
|
||||
- name: ACR
|
||||
description: Flash access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Flash option key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 12
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 16
|
||||
fieldset: CR
|
||||
- name: OPTCR
|
||||
description: Flash option control register
|
||||
byte_offset: 20
|
||||
fieldset: OPTCR
|
||||
- name: ACR
|
||||
description: Flash access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Flash option key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 12
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 16
|
||||
fieldset: CR
|
||||
- name: OPTCR
|
||||
description: Flash option control register
|
||||
byte_offset: 20
|
||||
fieldset: OPTCR
|
||||
fieldset/ACR:
|
||||
description: Flash access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: LATENCY
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ICEN
|
||||
description: Instruction cache enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: DCEN
|
||||
description: Data cache enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ICRST
|
||||
description: Instruction cache reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DCRST
|
||||
description: Data cache reset
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: LATENCY
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ICEN
|
||||
description: Instruction cache enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: DCEN
|
||||
description: Data cache enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ICRST
|
||||
description: Instruction cache reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DCRST
|
||||
description: Data cache reset
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SER
|
||||
description: Sector Erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Mass Erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: SNB
|
||||
description: Sector number
|
||||
bit_offset: 3
|
||||
bit_size: 4
|
||||
- name: PSIZE
|
||||
description: Program size
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
enum: PSIZE
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: Lock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SER
|
||||
description: Sector Erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Mass Erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: SNB
|
||||
description: Sector number
|
||||
bit_offset: 3
|
||||
bit_size: 4
|
||||
- name: PSIZE
|
||||
description: Program size
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
enum: PSIZE
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: Lock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/KEYR:
|
||||
description: Flash key register
|
||||
fields:
|
||||
- name: KEY
|
||||
description: FPEC key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: KEY
|
||||
description: FPEC key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTCR:
|
||||
description: Flash option control register
|
||||
fields:
|
||||
- name: OPTLOCK
|
||||
description: Option lock
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: Option start
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: BOR_LEV
|
||||
description: BOR reset Level
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
- name: WDG_SW
|
||||
description: WDG_SW User option bytes
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP User option bytes
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY User option bytes
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: RDP
|
||||
description: Read protect
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: nWRP
|
||||
description: Not write protect
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
- name: OPTLOCK
|
||||
description: Option lock
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: Option start
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: BOR_LEV
|
||||
description: BOR reset Level
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
- name: WDG_SW
|
||||
description: WDG_SW User option bytes
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP User option bytes
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY User option bytes
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: RDP
|
||||
description: Read protect
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: nWRP
|
||||
description: Not write protect
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
fieldset/OPTKEYR:
|
||||
description: Flash option key register
|
||||
fields:
|
||||
- name: OPTKEY
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: OPTKEY
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Operation error
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protection error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: PGPERR
|
||||
description: Programming parallelism error
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: Programming sequence error
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Operation error
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protection error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: PGPERR
|
||||
description: Programming parallelism error
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: Programming sequence error
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
enum/LATENCY:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: WS0
|
||||
description: 0 wait states
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: 1 wait states
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: 2 wait states
|
||||
value: 2
|
||||
- name: WS3
|
||||
description: 3 wait states
|
||||
value: 3
|
||||
- name: WS4
|
||||
description: 4 wait states
|
||||
value: 4
|
||||
- name: WS5
|
||||
description: 5 wait states
|
||||
value: 5
|
||||
- name: WS6
|
||||
description: 6 wait states
|
||||
value: 6
|
||||
- name: WS7
|
||||
description: 7 wait states
|
||||
value: 7
|
||||
- name: WS0
|
||||
description: 0 wait states
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: 1 wait states
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: 2 wait states
|
||||
value: 2
|
||||
- name: WS3
|
||||
description: 3 wait states
|
||||
value: 3
|
||||
- name: WS4
|
||||
description: 4 wait states
|
||||
value: 4
|
||||
- name: WS5
|
||||
description: 5 wait states
|
||||
value: 5
|
||||
- name: WS6
|
||||
description: 6 wait states
|
||||
value: 6
|
||||
- name: WS7
|
||||
description: 7 wait states
|
||||
value: 7
|
||||
enum/PSIZE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: PSIZE8
|
||||
description: Program x8
|
||||
value: 0
|
||||
- name: PSIZE16
|
||||
description: Program x16
|
||||
value: 1
|
||||
- name: PSIZE32
|
||||
description: Program x32
|
||||
value: 2
|
||||
- name: PSIZE64
|
||||
description: Program x64
|
||||
value: 3
|
||||
- name: PSIZE8
|
||||
description: Program x8
|
||||
value: 0
|
||||
- name: PSIZE16
|
||||
description: Program x16
|
||||
value: 1
|
||||
- name: PSIZE32
|
||||
description: Program x32
|
||||
value: 2
|
||||
- name: PSIZE64
|
||||
description: Program x64
|
||||
value: 3
|
||||
|
||||
@ -1,257 +1,256 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
- name: ACR
|
||||
description: Flash access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Flash option key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Flash status register
|
||||
byte_offset: 12
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Flash control register
|
||||
byte_offset: 16
|
||||
fieldset: CR
|
||||
- name: AR
|
||||
description: Flash address register
|
||||
byte_offset: 20
|
||||
access: Write
|
||||
fieldset: AR
|
||||
- name: OBR
|
||||
description: Option byte register
|
||||
byte_offset: 28
|
||||
access: Read
|
||||
fieldset: OBR
|
||||
- name: WRPR
|
||||
description: Write protection register
|
||||
byte_offset: 32
|
||||
access: Read
|
||||
fieldset: WRPR
|
||||
- name: ACR
|
||||
description: Flash access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Flash option key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Flash status register
|
||||
byte_offset: 12
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Flash control register
|
||||
byte_offset: 16
|
||||
fieldset: CR
|
||||
- name: AR
|
||||
description: Flash address register
|
||||
byte_offset: 20
|
||||
access: Write
|
||||
fieldset: AR
|
||||
- name: OBR
|
||||
description: Option byte register
|
||||
byte_offset: 28
|
||||
access: Read
|
||||
fieldset: OBR
|
||||
- name: WRPR
|
||||
description: Write protection register
|
||||
byte_offset: 32
|
||||
access: Read
|
||||
fieldset: WRPR
|
||||
fieldset/ACR:
|
||||
description: Flash access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: LATENCY
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: LATENCY
|
||||
- name: HLFCYA
|
||||
description: Flash half cycle access enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: PRFTBE
|
||||
description: PRFTBE
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PRFTBS
|
||||
description: PRFTBS
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: LATENCY
|
||||
description: LATENCY
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: LATENCY
|
||||
- name: HLFCYA
|
||||
description: Flash half cycle access enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: PRFTBE
|
||||
description: PRFTBE
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PRFTBS
|
||||
description: PRFTBS
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/AR:
|
||||
description: Flash address register
|
||||
fields:
|
||||
- name: FAR
|
||||
description: Flash address
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: FAR
|
||||
description: Flash address
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/CR:
|
||||
description: Flash control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Mass erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: OPTPG
|
||||
description: Option byte programming
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: OPTER
|
||||
description: Option byte erase
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: Lock
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: OPTWRE
|
||||
description: Option bytes write enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: Force option byte loading
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Mass erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: OPTPG
|
||||
description: Option byte programming
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: OPTER
|
||||
description: Option byte erase
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: Lock
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: OPTWRE
|
||||
description: Option bytes write enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: Force option byte loading
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
fieldset/KEYR:
|
||||
description: Flash key register
|
||||
fields:
|
||||
- name: FKEYR
|
||||
description: Flash Key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: FKEYR
|
||||
description: Flash Key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OBR:
|
||||
description: Option byte register
|
||||
fields:
|
||||
- name: OPTERR
|
||||
description: Option byte error
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RDPRT
|
||||
description: Read protection Level status
|
||||
bit_offset: 1
|
||||
bit_size: 2
|
||||
enum: RDPRT
|
||||
- name: WDG_SW
|
||||
description: WDG_SW
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: WDG_SW
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: nRST_STOP
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: nRST_STDBY
|
||||
- name: nBOOT1
|
||||
description: BOOT1
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: VDDA_MONITOR
|
||||
description: VDDA_MONITOR
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: SRAM_PARITY_CHECK
|
||||
description: SRAM_PARITY_CHECK
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: SDADC12_VDD_MONITOR
|
||||
description: SDADC12_VDD_MONITOR
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: Data0
|
||||
description: Data0
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: Data1
|
||||
description: Data1
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
- name: OPTERR
|
||||
description: Option byte error
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RDPRT
|
||||
description: Read protection Level status
|
||||
bit_offset: 1
|
||||
bit_size: 2
|
||||
enum: RDPRT
|
||||
- name: WDG_SW
|
||||
description: WDG_SW
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: WDG_SW
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: nRST_STOP
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: nRST_STDBY
|
||||
- name: nBOOT1
|
||||
description: BOOT1
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: VDDA_MONITOR
|
||||
description: VDDA_MONITOR
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: SRAM_PARITY_CHECK
|
||||
description: SRAM_PARITY_CHECK
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: SDADC12_VDD_MONITOR
|
||||
description: SDADC12_VDD_MONITOR
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: Data0
|
||||
description: Data0
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: Data1
|
||||
description: Data1
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
fieldset/OPTKEYR:
|
||||
description: Flash option key register
|
||||
fields:
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Flash status register
|
||||
fields:
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PGERR
|
||||
description: Programming error
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: WRPRTERR
|
||||
description: Write protection error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PGERR
|
||||
description: Programming error
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: WRPRTERR
|
||||
description: Write protection error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/WRPR:
|
||||
description: Write protection register
|
||||
fields:
|
||||
- name: WRP
|
||||
description: Write protect
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: WRP
|
||||
description: Write protect
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
enum/LATENCY:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: WS0
|
||||
description: "0 wait states, if 0 < HCLK <= 24 MHz"
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: "1 wait state, if 24 < HCLK <= 48 MHz"
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: "2 wait states, if 48 < HCLK <= 72 MHz"
|
||||
value: 2
|
||||
- name: WS0
|
||||
description: 0 wait states, if 0 < HCLK <= 24 MHz
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: 1 wait state, if 24 < HCLK <= 48 MHz
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: 2 wait states, if 48 < HCLK <= 72 MHz
|
||||
value: 2
|
||||
enum/RDPRT:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Level0
|
||||
description: Level 0
|
||||
value: 0
|
||||
- name: Level1
|
||||
description: Level 1
|
||||
value: 1
|
||||
- name: Level2
|
||||
description: Level 2
|
||||
value: 3
|
||||
- name: Level0
|
||||
description: Level 0
|
||||
value: 0
|
||||
- name: Level1
|
||||
description: Level 1
|
||||
value: 1
|
||||
- name: Level2
|
||||
description: Level 2
|
||||
value: 3
|
||||
enum/WDG_SW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Hardware
|
||||
description: Hardware watchdog
|
||||
value: 0
|
||||
- name: Software
|
||||
description: Software watchdog
|
||||
value: 1
|
||||
- name: Hardware
|
||||
description: Hardware watchdog
|
||||
value: 0
|
||||
- name: Software
|
||||
description: Software watchdog
|
||||
value: 1
|
||||
enum/nRST_STDBY:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Reset
|
||||
description: Reset generated when entering Standby mode
|
||||
value: 0
|
||||
- name: NoReset
|
||||
description: No reset generated
|
||||
value: 1
|
||||
- name: Reset
|
||||
description: Reset generated when entering Standby mode
|
||||
value: 0
|
||||
- name: NoReset
|
||||
description: No reset generated
|
||||
value: 1
|
||||
enum/nRST_STOP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Reset
|
||||
description: Reset generated when entering Stop mode
|
||||
value: 0
|
||||
- name: NoReset
|
||||
description: No reset generated
|
||||
value: 1
|
||||
- name: Reset
|
||||
description: Reset generated when entering Stop mode
|
||||
value: 0
|
||||
- name: NoReset
|
||||
description: No reset generated
|
||||
value: 1
|
||||
|
||||
@ -1,252 +1,251 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: FLASH
|
||||
items:
|
||||
- name: ACR
|
||||
description: Flash access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Flash option key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 12
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 16
|
||||
fieldset: CR
|
||||
- name: OPTCR
|
||||
description: Flash option control register
|
||||
byte_offset: 20
|
||||
fieldset: OPTCR
|
||||
- name: ACR
|
||||
description: Flash access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Flash option key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 12
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 16
|
||||
fieldset: CR
|
||||
- name: OPTCR
|
||||
description: Flash option control register
|
||||
byte_offset: 20
|
||||
fieldset: OPTCR
|
||||
fieldset/ACR:
|
||||
description: Flash access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: LATENCY
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ICEN
|
||||
description: Instruction cache enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: DCEN
|
||||
description: Data cache enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ICRST
|
||||
description: Instruction cache reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DCRST
|
||||
description: Data cache reset
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: LATENCY
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ICEN
|
||||
description: Instruction cache enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: DCEN
|
||||
description: Data cache enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ICRST
|
||||
description: Instruction cache reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DCRST
|
||||
description: Data cache reset
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SER
|
||||
description: Sector Erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Mass Erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: SNB
|
||||
description: Sector number
|
||||
bit_offset: 3
|
||||
bit_size: 5
|
||||
- name: PSIZE
|
||||
description: Program size
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
enum: PSIZE
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: Lock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SER
|
||||
description: Sector Erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Mass Erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: SNB
|
||||
description: Sector number
|
||||
bit_offset: 3
|
||||
bit_size: 5
|
||||
- name: PSIZE
|
||||
description: Program size
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
enum: PSIZE
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: Lock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/KEYR:
|
||||
description: Flash key register
|
||||
fields:
|
||||
- name: KEY
|
||||
description: FPEC key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: KEY
|
||||
description: FPEC key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTCR:
|
||||
description: Flash option control register
|
||||
fields:
|
||||
- name: OPTLOCK
|
||||
description: Option lock
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: Option start
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: BOR_LEV
|
||||
description: BOR reset Level
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
- name: WDG_SW
|
||||
description: WDG_SW User option bytes
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP User option bytes
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY User option bytes
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: RDP
|
||||
description: Read protect
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: nWRP
|
||||
description: Not write protect
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
- name: DB1M
|
||||
description: Dual-bank enable on 1 Mbyte Flash memory devices
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: SPRMOD
|
||||
description: Selection of protection mode for nWPRi bits
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: Option lock
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: Option start
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: BOR_LEV
|
||||
description: BOR reset Level
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
- name: WDG_SW
|
||||
description: WDG_SW User option bytes
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP User option bytes
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY User option bytes
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: RDP
|
||||
description: Read protect
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: nWRP
|
||||
description: Not write protect
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
- name: DB1M
|
||||
description: Dual-bank enable on 1 Mbyte Flash memory devices
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: SPRMOD
|
||||
description: Selection of protection mode for nWPRi bits
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/OPTKEYR:
|
||||
description: Flash option key register
|
||||
fields:
|
||||
- name: OPTKEY
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: OPTKEY
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Operation error
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protection error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: PGPERR
|
||||
description: Programming parallelism error
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: Programming sequence error
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Operation error
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protection error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: PGPERR
|
||||
description: Programming parallelism error
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: Programming sequence error
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
enum/LATENCY:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: WS0
|
||||
description: 0 wait states
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: 1 wait states
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: 2 wait states
|
||||
value: 2
|
||||
- name: WS3
|
||||
description: 3 wait states
|
||||
value: 3
|
||||
- name: WS4
|
||||
description: 4 wait states
|
||||
value: 4
|
||||
- name: WS5
|
||||
description: 5 wait states
|
||||
value: 5
|
||||
- name: WS6
|
||||
description: 6 wait states
|
||||
value: 6
|
||||
- name: WS7
|
||||
description: 7 wait states
|
||||
value: 7
|
||||
- name: WS8
|
||||
description: 8 wait states
|
||||
value: 8
|
||||
- name: WS9
|
||||
description: 9 wait states
|
||||
value: 9
|
||||
- name: WS10
|
||||
description: 10 wait states
|
||||
value: 10
|
||||
- name: WS11
|
||||
description: 11 wait states
|
||||
value: 11
|
||||
- name: WS12
|
||||
description: 12 wait states
|
||||
value: 12
|
||||
- name: WS13
|
||||
description: 13 wait states
|
||||
value: 13
|
||||
- name: WS14
|
||||
description: 14 wait states
|
||||
value: 14
|
||||
- name: WS15
|
||||
description: 15 wait states
|
||||
value: 15
|
||||
- name: WS0
|
||||
description: 0 wait states
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: 1 wait states
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: 2 wait states
|
||||
value: 2
|
||||
- name: WS3
|
||||
description: 3 wait states
|
||||
value: 3
|
||||
- name: WS4
|
||||
description: 4 wait states
|
||||
value: 4
|
||||
- name: WS5
|
||||
description: 5 wait states
|
||||
value: 5
|
||||
- name: WS6
|
||||
description: 6 wait states
|
||||
value: 6
|
||||
- name: WS7
|
||||
description: 7 wait states
|
||||
value: 7
|
||||
- name: WS8
|
||||
description: 8 wait states
|
||||
value: 8
|
||||
- name: WS9
|
||||
description: 9 wait states
|
||||
value: 9
|
||||
- name: WS10
|
||||
description: 10 wait states
|
||||
value: 10
|
||||
- name: WS11
|
||||
description: 11 wait states
|
||||
value: 11
|
||||
- name: WS12
|
||||
description: 12 wait states
|
||||
value: 12
|
||||
- name: WS13
|
||||
description: 13 wait states
|
||||
value: 13
|
||||
- name: WS14
|
||||
description: 14 wait states
|
||||
value: 14
|
||||
- name: WS15
|
||||
description: 15 wait states
|
||||
value: 15
|
||||
enum/PSIZE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: PSIZE8
|
||||
description: Program x8
|
||||
value: 0
|
||||
- name: PSIZE16
|
||||
description: Program x16
|
||||
value: 1
|
||||
- name: PSIZE32
|
||||
description: Program x32
|
||||
value: 2
|
||||
- name: PSIZE64
|
||||
description: Program x64
|
||||
value: 3
|
||||
- name: PSIZE8
|
||||
description: Program x8
|
||||
value: 0
|
||||
- name: PSIZE16
|
||||
description: Program x16
|
||||
value: 1
|
||||
- name: PSIZE32
|
||||
description: Program x32
|
||||
value: 2
|
||||
- name: PSIZE64
|
||||
description: Program x64
|
||||
value: 3
|
||||
|
||||
@ -1,294 +1,293 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: FLASH
|
||||
items:
|
||||
- name: ACR
|
||||
description: Flash access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Flash option key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 12
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 16
|
||||
fieldset: CR
|
||||
- name: OPTCR
|
||||
description: Flash option control register
|
||||
byte_offset: 20
|
||||
fieldset: OPTCR
|
||||
- name: OPTCR1
|
||||
description: Flash option control register 1
|
||||
byte_offset: 24
|
||||
fieldset: OPTCR1
|
||||
- name: OPTCR2
|
||||
description: Flash option control register
|
||||
byte_offset: 28
|
||||
fieldset: OPTCR2
|
||||
- name: ACR
|
||||
description: Flash access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Flash option key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 12
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 16
|
||||
fieldset: CR
|
||||
- name: OPTCR
|
||||
description: Flash option control register
|
||||
byte_offset: 20
|
||||
fieldset: OPTCR
|
||||
- name: OPTCR1
|
||||
description: Flash option control register 1
|
||||
byte_offset: 24
|
||||
fieldset: OPTCR1
|
||||
- name: OPTCR2
|
||||
description: Flash option control register
|
||||
byte_offset: 28
|
||||
fieldset: OPTCR2
|
||||
fieldset/ACR:
|
||||
description: Flash access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
enum: LATENCY
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ARTEN
|
||||
description: ART Accelerator Enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ARTRST
|
||||
description: ART Accelerator reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
enum: LATENCY
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ARTEN
|
||||
description: ART Accelerator Enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ARTRST
|
||||
description: ART Accelerator reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SER
|
||||
description: Sector Erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Mass Erase of sectors 0 to 11
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: SNB
|
||||
description: Sector number
|
||||
bit_offset: 3
|
||||
bit_size: 4
|
||||
- name: PSIZE
|
||||
description: Program size
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
enum: PSIZE
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: RDERRIE
|
||||
description: PCROP error interrupt enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: Lock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SER
|
||||
description: Sector Erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Mass Erase of sectors 0 to 11
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: SNB
|
||||
description: Sector number
|
||||
bit_offset: 3
|
||||
bit_size: 4
|
||||
- name: PSIZE
|
||||
description: Program size
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
enum: PSIZE
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: RDERRIE
|
||||
description: PCROP error interrupt enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: Lock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/KEYR:
|
||||
description: Flash key register
|
||||
fields:
|
||||
- name: KEY
|
||||
description: FPEC key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: KEY
|
||||
description: FPEC key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTCR:
|
||||
description: Flash option control register
|
||||
fields:
|
||||
- name: OPTLOCK
|
||||
description: Option lock
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: Option start
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: BOR_LEV
|
||||
description: BOR reset Level
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
- name: WWDG_SW
|
||||
description: User option bytes
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: IWDG_SW
|
||||
description: WDG_SW User option bytes
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP User option bytes
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY User option bytes
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: RDP
|
||||
description: Read protect
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: nWRP
|
||||
description: Not write protect
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: nDBOOT
|
||||
description: Dual Boot mode (valid only when nDBANK=0)
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: nDBANK
|
||||
description: Not dual bank mode
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: IWDG_STDBY
|
||||
description: Independent watchdog counter freeze in standby mode
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: IWDG_STOP
|
||||
description: Independent watchdog counter freeze in Stop mode
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: Option lock
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: Option start
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: BOR_LEV
|
||||
description: BOR reset Level
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
- name: WWDG_SW
|
||||
description: User option bytes
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: IWDG_SW
|
||||
description: WDG_SW User option bytes
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP User option bytes
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY User option bytes
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: RDP
|
||||
description: Read protect
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: nWRP
|
||||
description: Not write protect
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: nDBOOT
|
||||
description: Dual Boot mode (valid only when nDBANK=0)
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: nDBANK
|
||||
description: Not dual bank mode
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: IWDG_STDBY
|
||||
description: Independent watchdog counter freeze in standby mode
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: IWDG_STOP
|
||||
description: Independent watchdog counter freeze in Stop mode
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/OPTCR1:
|
||||
description: Flash option control register 1
|
||||
fields:
|
||||
- name: BOOT_ADD0
|
||||
description: Boot base address when Boot pin =0
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: BOOT_ADD1
|
||||
description: Boot base address when Boot pin =1
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
- name: BOOT_ADD0
|
||||
description: Boot base address when Boot pin =0
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: BOOT_ADD1
|
||||
description: Boot base address when Boot pin =1
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/OPTCR2:
|
||||
description: Flash option control register
|
||||
fields:
|
||||
- name: PCROPi
|
||||
description: PCROP option byte
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: PCROP_RDP
|
||||
description: PCROP zone preserved when RDP level decreased
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: PCROPi
|
||||
description: PCROP option byte
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: PCROP_RDP
|
||||
description: PCROP zone preserved when RDP level decreased
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/OPTKEYR:
|
||||
description: Flash option key register
|
||||
fields:
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Operation error
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protection error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: PGPERR
|
||||
description: Programming parallelism error
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: ERSERR
|
||||
description: Erase Sequence Error
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: RDERR
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Operation error
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protection error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: PGPERR
|
||||
description: Programming parallelism error
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: ERSERR
|
||||
description: Erase Sequence Error
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: RDERR
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
enum/LATENCY:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: WS0
|
||||
description: 0 wait states
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: 1 wait states
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: 2 wait states
|
||||
value: 2
|
||||
- name: WS3
|
||||
description: 3 wait states
|
||||
value: 3
|
||||
- name: WS4
|
||||
description: 4 wait states
|
||||
value: 4
|
||||
- name: WS5
|
||||
description: 5 wait states
|
||||
value: 5
|
||||
- name: WS6
|
||||
description: 6 wait states
|
||||
value: 6
|
||||
- name: WS7
|
||||
description: 7 wait states
|
||||
value: 7
|
||||
- name: WS8
|
||||
description: 8 wait states
|
||||
value: 8
|
||||
- name: WS9
|
||||
description: 9 wait states
|
||||
value: 9
|
||||
- name: WS10
|
||||
description: 10 wait states
|
||||
value: 10
|
||||
- name: WS11
|
||||
description: 11 wait states
|
||||
value: 11
|
||||
- name: WS12
|
||||
description: 12 wait states
|
||||
value: 12
|
||||
- name: WS13
|
||||
description: 13 wait states
|
||||
value: 13
|
||||
- name: WS14
|
||||
description: 14 wait states
|
||||
value: 14
|
||||
- name: WS15
|
||||
description: 15 wait states
|
||||
value: 15
|
||||
- name: WS0
|
||||
description: 0 wait states
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: 1 wait states
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: 2 wait states
|
||||
value: 2
|
||||
- name: WS3
|
||||
description: 3 wait states
|
||||
value: 3
|
||||
- name: WS4
|
||||
description: 4 wait states
|
||||
value: 4
|
||||
- name: WS5
|
||||
description: 5 wait states
|
||||
value: 5
|
||||
- name: WS6
|
||||
description: 6 wait states
|
||||
value: 6
|
||||
- name: WS7
|
||||
description: 7 wait states
|
||||
value: 7
|
||||
- name: WS8
|
||||
description: 8 wait states
|
||||
value: 8
|
||||
- name: WS9
|
||||
description: 9 wait states
|
||||
value: 9
|
||||
- name: WS10
|
||||
description: 10 wait states
|
||||
value: 10
|
||||
- name: WS11
|
||||
description: 11 wait states
|
||||
value: 11
|
||||
- name: WS12
|
||||
description: 12 wait states
|
||||
value: 12
|
||||
- name: WS13
|
||||
description: 13 wait states
|
||||
value: 13
|
||||
- name: WS14
|
||||
description: 14 wait states
|
||||
value: 14
|
||||
- name: WS15
|
||||
description: 15 wait states
|
||||
value: 15
|
||||
enum/PSIZE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: PSIZE8
|
||||
description: Program x8
|
||||
value: 0
|
||||
- name: PSIZE16
|
||||
description: Program x16
|
||||
value: 1
|
||||
- name: PSIZE32
|
||||
description: Program x32
|
||||
value: 2
|
||||
- name: PSIZE64
|
||||
description: Program x64
|
||||
value: 3
|
||||
- name: PSIZE8
|
||||
description: Program x8
|
||||
value: 0
|
||||
- name: PSIZE16
|
||||
description: Program x16
|
||||
value: 1
|
||||
- name: PSIZE32
|
||||
description: Program x32
|
||||
value: 2
|
||||
- name: PSIZE64
|
||||
description: Program x64
|
||||
value: 3
|
||||
|
||||
@ -1,454 +1,453 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
- name: ACR
|
||||
description: Access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Option byte key register
|
||||
byte_offset: 12
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 16
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Flash control register
|
||||
byte_offset: 20
|
||||
fieldset: CR
|
||||
- name: ECCR
|
||||
description: Flash ECC register
|
||||
byte_offset: 24
|
||||
fieldset: ECCR
|
||||
- name: OPTR
|
||||
description: Flash option register
|
||||
byte_offset: 32
|
||||
fieldset: OPTR
|
||||
- name: PCROP1ASR
|
||||
description: Flash PCROP zone A Start address register
|
||||
byte_offset: 36
|
||||
access: Read
|
||||
fieldset: PCROP1ASR
|
||||
- name: PCROP1AER
|
||||
description: Flash PCROP zone A End address register
|
||||
byte_offset: 40
|
||||
access: Read
|
||||
fieldset: PCROP1AER
|
||||
- name: WRP1AR
|
||||
description: Flash WRP area A address register
|
||||
byte_offset: 44
|
||||
access: Read
|
||||
fieldset: WRP1AR
|
||||
- name: WRP1BR
|
||||
description: Flash WRP area B address register
|
||||
byte_offset: 48
|
||||
access: Read
|
||||
fieldset: WRP1BR
|
||||
- name: PCROP1BSR
|
||||
description: Flash PCROP zone B Start address register
|
||||
byte_offset: 52
|
||||
access: Read
|
||||
fieldset: PCROP1BSR
|
||||
- name: PCROP1BER
|
||||
description: Flash PCROP zone B End address register
|
||||
byte_offset: 56
|
||||
access: Read
|
||||
fieldset: PCROP1BER
|
||||
- name: SECR
|
||||
description: Flash Security register
|
||||
byte_offset: 128
|
||||
access: Read
|
||||
fieldset: SECR
|
||||
- name: ACR
|
||||
description: Access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Option byte key register
|
||||
byte_offset: 12
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 16
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Flash control register
|
||||
byte_offset: 20
|
||||
fieldset: CR
|
||||
- name: ECCR
|
||||
description: Flash ECC register
|
||||
byte_offset: 24
|
||||
fieldset: ECCR
|
||||
- name: OPTR
|
||||
description: Flash option register
|
||||
byte_offset: 32
|
||||
fieldset: OPTR
|
||||
- name: PCROP1ASR
|
||||
description: Flash PCROP zone A Start address register
|
||||
byte_offset: 36
|
||||
access: Read
|
||||
fieldset: PCROP1ASR
|
||||
- name: PCROP1AER
|
||||
description: Flash PCROP zone A End address register
|
||||
byte_offset: 40
|
||||
access: Read
|
||||
fieldset: PCROP1AER
|
||||
- name: WRP1AR
|
||||
description: Flash WRP area A address register
|
||||
byte_offset: 44
|
||||
access: Read
|
||||
fieldset: WRP1AR
|
||||
- name: WRP1BR
|
||||
description: Flash WRP area B address register
|
||||
byte_offset: 48
|
||||
access: Read
|
||||
fieldset: WRP1BR
|
||||
- name: PCROP1BSR
|
||||
description: Flash PCROP zone B Start address register
|
||||
byte_offset: 52
|
||||
access: Read
|
||||
fieldset: PCROP1BSR
|
||||
- name: PCROP1BER
|
||||
description: Flash PCROP zone B End address register
|
||||
byte_offset: 56
|
||||
access: Read
|
||||
fieldset: PCROP1BER
|
||||
- name: SECR
|
||||
description: Flash Security register
|
||||
byte_offset: 128
|
||||
access: Read
|
||||
fieldset: SECR
|
||||
fieldset/ACR:
|
||||
description: Access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: LATENCY
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ICEN
|
||||
description: Instruction cache enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ICRST
|
||||
description: Instruction cache reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: EMPTY
|
||||
description: Flash User area empty
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: DBG_SWEN
|
||||
description: Debug access software enable
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: LATENCY
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ICEN
|
||||
description: Instruction cache enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ICRST
|
||||
description: Instruction cache reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: EMPTY
|
||||
description: Flash User area empty
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: DBG_SWEN
|
||||
description: Debug access software enable
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Flash control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Mass erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PNB
|
||||
description: Page number
|
||||
bit_offset: 3
|
||||
bit_size: 6
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: Options modification start
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: FSTPG
|
||||
description: Fast programming
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: RDERRIE
|
||||
description: PCROP read error interrupt enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: Force the option byte loading
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: SEC_PROT
|
||||
description: Securable memory area protection enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: Options Lock
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: FLASH_CR Lock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Mass erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PNB
|
||||
description: Page number
|
||||
bit_offset: 3
|
||||
bit_size: 6
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: Options modification start
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: FSTPG
|
||||
description: Fast programming
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: RDERRIE
|
||||
description: PCROP read error interrupt enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: Force the option byte loading
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: SEC_PROT
|
||||
description: Securable memory area protection enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: Options Lock
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: FLASH_CR Lock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/ECCR:
|
||||
description: Flash ECC register
|
||||
fields:
|
||||
- name: ADDR_ECC
|
||||
description: ECC fail address
|
||||
bit_offset: 0
|
||||
bit_size: 14
|
||||
- name: SYSF_ECC
|
||||
description: ECC fail for Corrected ECC Error or Double ECC Error in info block
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: ECCIE
|
||||
description: ECC correction interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ECCC
|
||||
description: ECC correction
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: ECCD
|
||||
description: ECC detection
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: ADDR_ECC
|
||||
description: ECC fail address
|
||||
bit_offset: 0
|
||||
bit_size: 14
|
||||
- name: SYSF_ECC
|
||||
description: ECC fail for Corrected ECC Error or Double ECC Error in info block
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: ECCIE
|
||||
description: ECC correction interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ECCC
|
||||
description: ECC correction
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: ECCD
|
||||
description: ECC detection
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/KEYR:
|
||||
description: Flash key register
|
||||
fields:
|
||||
- name: KEYR
|
||||
description: KEYR
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: KEYR
|
||||
description: KEYR
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTKEYR:
|
||||
description: Option byte key register
|
||||
fields:
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTR:
|
||||
description: Flash option register
|
||||
fields:
|
||||
- name: RDP
|
||||
description: Read protection level
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
enum: RDP
|
||||
- name: BOREN
|
||||
description: BOR reset Level
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: BORF_LEV
|
||||
description: These bits contain the VDD supply level threshold that activates the reset
|
||||
bit_offset: 9
|
||||
bit_size: 2
|
||||
enum: BORF_LEV
|
||||
- name: BORR_LEV
|
||||
description: These bits contain the VDD supply level threshold that releases the reset.
|
||||
bit_offset: 11
|
||||
bit_size: 2
|
||||
enum: BORR_LEV
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: nRSTS_HDW
|
||||
description: nRSTS_HDW
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: IDWG_SW
|
||||
description: Independent watchdog selection
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: IWDG_STOP
|
||||
description: Independent watchdog counter freeze in Stop mode
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: IWDG_STDBY
|
||||
description: Independent watchdog counter freeze in Standby mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: WWDG_SW
|
||||
description: Window watchdog selection
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: RAM_PARITY_CHECK
|
||||
description: SRAM parity check control
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: nBOOT_SEL
|
||||
description: nBOOT_SEL
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: nBOOT1
|
||||
description: Boot configuration
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: nBOOT0
|
||||
description: nBOOT0 option bit
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: NRST_MODE
|
||||
description: NRST_MODE
|
||||
bit_offset: 27
|
||||
bit_size: 2
|
||||
enum: NRST_MODE
|
||||
- name: IRHEN
|
||||
description: Internal reset holder enable bit
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: RDP
|
||||
description: Read protection level
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
enum: RDP
|
||||
- name: BOREN
|
||||
description: BOR reset Level
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: BORF_LEV
|
||||
description: These bits contain the VDD supply level threshold that activates the reset
|
||||
bit_offset: 9
|
||||
bit_size: 2
|
||||
enum: BORF_LEV
|
||||
- name: BORR_LEV
|
||||
description: These bits contain the VDD supply level threshold that releases the reset.
|
||||
bit_offset: 11
|
||||
bit_size: 2
|
||||
enum: BORR_LEV
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: nRSTS_HDW
|
||||
description: nRSTS_HDW
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: IDWG_SW
|
||||
description: Independent watchdog selection
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: IWDG_STOP
|
||||
description: Independent watchdog counter freeze in Stop mode
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: IWDG_STDBY
|
||||
description: Independent watchdog counter freeze in Standby mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: WWDG_SW
|
||||
description: Window watchdog selection
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: RAM_PARITY_CHECK
|
||||
description: SRAM parity check control
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: nBOOT_SEL
|
||||
description: nBOOT_SEL
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: nBOOT1
|
||||
description: Boot configuration
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: nBOOT0
|
||||
description: nBOOT0 option bit
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: NRST_MODE
|
||||
description: NRST_MODE
|
||||
bit_offset: 27
|
||||
bit_size: 2
|
||||
enum: NRST_MODE
|
||||
- name: IRHEN
|
||||
description: Internal reset holder enable bit
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
fieldset/PCROP1AER:
|
||||
description: Flash PCROP zone A End address register
|
||||
fields:
|
||||
- name: PCROP1A_END
|
||||
description: PCROP1A area end offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: PCROP_RDP
|
||||
description: PCROP area preserved when RDP level decreased
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: PCROP1A_END
|
||||
description: PCROP1A area end offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: PCROP_RDP
|
||||
description: PCROP area preserved when RDP level decreased
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/PCROP1ASR:
|
||||
description: Flash PCROP zone A Start address register
|
||||
fields:
|
||||
- name: PCROP1A_STRT
|
||||
description: PCROP1A area start offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: PCROP1A_STRT
|
||||
description: PCROP1A area start offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/PCROP1BER:
|
||||
description: Flash PCROP zone B End address register
|
||||
fields:
|
||||
- name: PCROP1B_END
|
||||
description: PCROP1B area end offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: PCROP1B_END
|
||||
description: PCROP1B area end offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/PCROP1BSR:
|
||||
description: Flash PCROP zone B Start address register
|
||||
fields:
|
||||
- name: PCROP1B_STRT
|
||||
description: PCROP1B area start offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: PCROP1B_STRT
|
||||
description: PCROP1B area start offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/SECR:
|
||||
description: Flash Security register
|
||||
fields:
|
||||
- name: SEC_SIZE
|
||||
description: Securable memory area size
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: BOOT_LOCK
|
||||
description: used to force boot from user area
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: SEC_SIZE
|
||||
description: Securable memory area size
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: BOOT_LOCK
|
||||
description: used to force boot from user area
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Operation error
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PROGERR
|
||||
description: Programming error
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protected error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: Size error
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: Programming sequence error
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: MISERR
|
||||
description: Fast programming data miss error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: FASTERR
|
||||
description: Fast programming error
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: PCROP read error
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: OPTVERR
|
||||
description: Option and Engineering bits loading validity error
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: CFGBSY
|
||||
description: Programming or erase configuration busy.
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Operation error
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PROGERR
|
||||
description: Programming error
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protected error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: Size error
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: Programming sequence error
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: MISERR
|
||||
description: Fast programming data miss error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: FASTERR
|
||||
description: Fast programming error
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: PCROP read error
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: OPTVERR
|
||||
description: Option and Engineering bits loading validity error
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: CFGBSY
|
||||
description: Programming or erase configuration busy.
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/WRP1AR:
|
||||
description: Flash WRP area A address register
|
||||
fields:
|
||||
- name: WRP1A_STRT
|
||||
description: WRP area A start offset
|
||||
bit_offset: 0
|
||||
bit_size: 6
|
||||
- name: WRP1A_END
|
||||
description: WRP area A end offset
|
||||
bit_offset: 16
|
||||
bit_size: 6
|
||||
- name: WRP1A_STRT
|
||||
description: WRP area A start offset
|
||||
bit_offset: 0
|
||||
bit_size: 6
|
||||
- name: WRP1A_END
|
||||
description: WRP area A end offset
|
||||
bit_offset: 16
|
||||
bit_size: 6
|
||||
fieldset/WRP1BR:
|
||||
description: Flash WRP area B address register
|
||||
fields:
|
||||
- name: WRP1B_STRT
|
||||
description: WRP area B start offset
|
||||
bit_offset: 0
|
||||
bit_size: 6
|
||||
- name: WRP1B_END
|
||||
description: WRP area B end offset
|
||||
bit_offset: 16
|
||||
bit_size: 6
|
||||
- name: WRP1B_STRT
|
||||
description: WRP area B start offset
|
||||
bit_offset: 0
|
||||
bit_size: 6
|
||||
- name: WRP1B_END
|
||||
description: WRP area B end offset
|
||||
bit_offset: 16
|
||||
bit_size: 6
|
||||
enum/BORF_LEV:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: FALLING_0
|
||||
description: BOR falling level 1 with threshold around 2.0V
|
||||
value: 0
|
||||
- name: FALLING_1
|
||||
description: BOR falling level 2 with threshold around 2.2V
|
||||
value: 1
|
||||
- name: FALLING_2
|
||||
description: BOR falling level 3 with threshold around 2.5V
|
||||
value: 2
|
||||
- name: FALLING_3
|
||||
description: BOR falling level 4 with threshold around 2.8V
|
||||
value: 3
|
||||
- name: FALLING_0
|
||||
description: BOR falling level 1 with threshold around 2.0V
|
||||
value: 0
|
||||
- name: FALLING_1
|
||||
description: BOR falling level 2 with threshold around 2.2V
|
||||
value: 1
|
||||
- name: FALLING_2
|
||||
description: BOR falling level 3 with threshold around 2.5V
|
||||
value: 2
|
||||
- name: FALLING_3
|
||||
description: BOR falling level 4 with threshold around 2.8V
|
||||
value: 3
|
||||
enum/BORR_LEV:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: RISING_0
|
||||
description: BOR rising level 1 with threshold around 2.1V
|
||||
value: 0
|
||||
- name: RISING_1
|
||||
description: BOR rising level 2 with threshold around 2.3V
|
||||
value: 1
|
||||
- name: RISING_2
|
||||
description: BOR rising level 3 with threshold around 2.6V
|
||||
value: 2
|
||||
- name: RISING_3
|
||||
description: BOR rising level 4 with threshold around 2.9V
|
||||
value: 3
|
||||
- name: RISING_0
|
||||
description: BOR rising level 1 with threshold around 2.1V
|
||||
value: 0
|
||||
- name: RISING_1
|
||||
description: BOR rising level 2 with threshold around 2.3V
|
||||
value: 1
|
||||
- name: RISING_2
|
||||
description: BOR rising level 3 with threshold around 2.6V
|
||||
value: 2
|
||||
- name: RISING_3
|
||||
description: BOR rising level 4 with threshold around 2.9V
|
||||
value: 3
|
||||
enum/LATENCY:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: WS0
|
||||
description: Zero wait states
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: One wait state
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: Two wait states
|
||||
value: 2
|
||||
- name: WS0
|
||||
description: Zero wait states
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: One wait state
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: Two wait states
|
||||
value: 2
|
||||
enum/NRST_MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: INPUT_ONLY
|
||||
description: Reset pin is in reset input mode only
|
||||
value: 1
|
||||
- name: GPIO
|
||||
description: Reset pin is in GPIO mode only
|
||||
value: 2
|
||||
- name: INPUT_OUTPUT
|
||||
description: Reset pin is in resety input and output mode
|
||||
value: 3
|
||||
- name: INPUT_ONLY
|
||||
description: Reset pin is in reset input mode only
|
||||
value: 1
|
||||
- name: GPIO
|
||||
description: Reset pin is in GPIO mode only
|
||||
value: 2
|
||||
- name: INPUT_OUTPUT
|
||||
description: Reset pin is in resety input and output mode
|
||||
value: 3
|
||||
enum/RDP:
|
||||
bit_size: 8
|
||||
variants:
|
||||
- name: LEVEL_0
|
||||
description: Read protection not active
|
||||
value: 170
|
||||
- name: LEVEL_1
|
||||
description: Memories read protection active
|
||||
value: 187
|
||||
- name: LEVEL_2
|
||||
description: Chip read protection active
|
||||
value: 204
|
||||
- name: LEVEL_0
|
||||
description: Read protection not active
|
||||
value: 170
|
||||
- name: LEVEL_1
|
||||
description: Memories read protection active
|
||||
value: 187
|
||||
- name: LEVEL_2
|
||||
description: Chip read protection active
|
||||
value: 204
|
||||
|
||||
@ -1,427 +1,426 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
- name: ACR
|
||||
description: Access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: PDKEYR
|
||||
description: Power down key register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: PDKEYR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Option byte key register
|
||||
byte_offset: 12
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 16
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Flash control register
|
||||
byte_offset: 20
|
||||
fieldset: CR
|
||||
- name: ECCR
|
||||
description: Flash ECC register
|
||||
byte_offset: 24
|
||||
fieldset: ECCR
|
||||
- name: OPTR
|
||||
description: Flash option register
|
||||
byte_offset: 32
|
||||
fieldset: OPTR
|
||||
- name: PCROP1SR
|
||||
description: Flash Bank 1 PCROP Start address register
|
||||
byte_offset: 36
|
||||
fieldset: PCROP1SR
|
||||
- name: PCROP1ER
|
||||
description: Flash Bank 1 PCROP End address register
|
||||
byte_offset: 40
|
||||
fieldset: PCROP1ER
|
||||
- name: WRP1AR
|
||||
description: Flash Bank 1 WRP area A address register
|
||||
byte_offset: 44
|
||||
fieldset: WRP1AR
|
||||
- name: WRP1BR
|
||||
description: Flash Bank 1 WRP area B address register
|
||||
byte_offset: 48
|
||||
fieldset: WRP1BR
|
||||
- name: SEC1R
|
||||
description: securable area bank1 register
|
||||
byte_offset: 112
|
||||
fieldset: SEC1R
|
||||
- name: ACR
|
||||
description: Access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: PDKEYR
|
||||
description: Power down key register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: PDKEYR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Option byte key register
|
||||
byte_offset: 12
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 16
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Flash control register
|
||||
byte_offset: 20
|
||||
fieldset: CR
|
||||
- name: ECCR
|
||||
description: Flash ECC register
|
||||
byte_offset: 24
|
||||
fieldset: ECCR
|
||||
- name: OPTR
|
||||
description: Flash option register
|
||||
byte_offset: 32
|
||||
fieldset: OPTR
|
||||
- name: PCROP1SR
|
||||
description: Flash Bank 1 PCROP Start address register
|
||||
byte_offset: 36
|
||||
fieldset: PCROP1SR
|
||||
- name: PCROP1ER
|
||||
description: Flash Bank 1 PCROP End address register
|
||||
byte_offset: 40
|
||||
fieldset: PCROP1ER
|
||||
- name: WRP1AR
|
||||
description: Flash Bank 1 WRP area A address register
|
||||
byte_offset: 44
|
||||
fieldset: WRP1AR
|
||||
- name: WRP1BR
|
||||
description: Flash Bank 1 WRP area B address register
|
||||
byte_offset: 48
|
||||
fieldset: WRP1BR
|
||||
- name: SEC1R
|
||||
description: securable area bank1 register
|
||||
byte_offset: 112
|
||||
fieldset: SEC1R
|
||||
fieldset/ACR:
|
||||
description: Access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
enum: LATENCY
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ICEN
|
||||
description: Instruction cache enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: DCEN
|
||||
description: Data cache enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ICRST
|
||||
description: Instruction cache reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DCRST
|
||||
description: Data cache reset
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: RUN_PD
|
||||
description: Flash Power-down mode during Low-power run mode
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: SLEEP_PD
|
||||
description: Flash Power-down mode during Low-power sleep mode
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: DBG_SWEN
|
||||
description: Debug software enable
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
enum: LATENCY
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ICEN
|
||||
description: Instruction cache enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: DCEN
|
||||
description: Data cache enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ICRST
|
||||
description: Instruction cache reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DCRST
|
||||
description: Data cache reset
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: RUN_PD
|
||||
description: Flash Power-down mode during Low-power run mode
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: SLEEP_PD
|
||||
description: Flash Power-down mode during Low-power sleep mode
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: DBG_SWEN
|
||||
description: Debug software enable
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Flash control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER1
|
||||
description: Bank 1 Mass erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PNB
|
||||
description: Page number
|
||||
bit_offset: 3
|
||||
bit_size: 7
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: Options modification start
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: FSTPG
|
||||
description: Fast programming
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: RDERRIE
|
||||
description: PCROP read error interrupt enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: Force the option byte loading
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: SEC_PROT1
|
||||
description: Securable memory area protection enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: Options Lock
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: FLASH_CR Lock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER1
|
||||
description: Bank 1 Mass erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PNB
|
||||
description: Page number
|
||||
bit_offset: 3
|
||||
bit_size: 7
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: Options modification start
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: FSTPG
|
||||
description: Fast programming
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: RDERRIE
|
||||
description: PCROP read error interrupt enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: Force the option byte loading
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: SEC_PROT1
|
||||
description: Securable memory area protection enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: Options Lock
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: FLASH_CR Lock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/ECCR:
|
||||
description: Flash ECC register
|
||||
fields:
|
||||
- name: ADDR_ECC
|
||||
description: ECC fail address
|
||||
bit_offset: 0
|
||||
bit_size: 19
|
||||
- name: BK_ECC
|
||||
description: ECC fail for Corrected ECC Error or Double ECC Error in info block
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: SYSF_ECC
|
||||
description: ECC fail for Corrected ECC Error or Double ECC Error in info block
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: ECCIE
|
||||
description: ECC correction interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ECCC2
|
||||
description: ECC correction
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: ECCD2
|
||||
description: ECC2 detection
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: ECCC
|
||||
description: ECC correction
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: ECCD
|
||||
description: ECC detection
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: ADDR_ECC
|
||||
description: ECC fail address
|
||||
bit_offset: 0
|
||||
bit_size: 19
|
||||
- name: BK_ECC
|
||||
description: ECC fail for Corrected ECC Error or Double ECC Error in info block
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: SYSF_ECC
|
||||
description: ECC fail for Corrected ECC Error or Double ECC Error in info block
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: ECCIE
|
||||
description: ECC correction interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ECCC2
|
||||
description: ECC correction
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: ECCD2
|
||||
description: ECC2 detection
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: ECCC
|
||||
description: ECC correction
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: ECCD
|
||||
description: ECC detection
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/KEYR:
|
||||
description: Flash key register
|
||||
fields:
|
||||
- name: KEYR
|
||||
description: KEYR
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: KEYR
|
||||
description: KEYR
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTKEYR:
|
||||
description: Option byte key register
|
||||
fields:
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTR:
|
||||
description: Flash option register
|
||||
fields:
|
||||
- name: RDP
|
||||
description: Read protection level
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
enum: RDP
|
||||
- name: BOR_LEV
|
||||
description: BOR reset Level
|
||||
bit_offset: 8
|
||||
bit_size: 3
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: nRST_SHDW
|
||||
description: nRST_SHDW
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: IDWG_SW
|
||||
description: Independent watchdog selection
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: IWDG_STOP
|
||||
description: Independent watchdog counter freeze in Stop mode
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: IWDG_STDBY
|
||||
description: Independent watchdog counter freeze in Standby mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: WWDG_SW
|
||||
description: Window watchdog selection
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: nBOOT1
|
||||
description: Boot configuration
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: SRAM2_PE
|
||||
description: SRAM2 parity check enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: SRAM2_RST
|
||||
description: SRAM2 Erase when system reset
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: nSWBOOT0
|
||||
description: nSWBOOT0
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: nBOOT0
|
||||
description: nBOOT0 option bit
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: NRST_MODE
|
||||
description: NRST_MODE
|
||||
bit_offset: 28
|
||||
bit_size: 2
|
||||
enum: NRST_MODE
|
||||
- name: IRHEN
|
||||
description: Internal reset holder enable bit
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: RDP
|
||||
description: Read protection level
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
enum: RDP
|
||||
- name: BOR_LEV
|
||||
description: BOR reset Level
|
||||
bit_offset: 8
|
||||
bit_size: 3
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: nRST_SHDW
|
||||
description: nRST_SHDW
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: IDWG_SW
|
||||
description: Independent watchdog selection
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: IWDG_STOP
|
||||
description: Independent watchdog counter freeze in Stop mode
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: IWDG_STDBY
|
||||
description: Independent watchdog counter freeze in Standby mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: WWDG_SW
|
||||
description: Window watchdog selection
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: nBOOT1
|
||||
description: Boot configuration
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: SRAM2_PE
|
||||
description: SRAM2 parity check enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: SRAM2_RST
|
||||
description: SRAM2 Erase when system reset
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: nSWBOOT0
|
||||
description: nSWBOOT0
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: nBOOT0
|
||||
description: nBOOT0 option bit
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: NRST_MODE
|
||||
description: NRST_MODE
|
||||
bit_offset: 28
|
||||
bit_size: 2
|
||||
enum: NRST_MODE
|
||||
- name: IRHEN
|
||||
description: Internal reset holder enable bit
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
fieldset/PCROP1ER:
|
||||
description: Flash Bank 1 PCROP End address register
|
||||
fields:
|
||||
- name: PCROP1_END
|
||||
description: Bank 1 PCROP area end offset
|
||||
bit_offset: 0
|
||||
bit_size: 15
|
||||
- name: PCROP_RDP
|
||||
description: PCROP area preserved when RDP level decreased
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: PCROP1_END
|
||||
description: Bank 1 PCROP area end offset
|
||||
bit_offset: 0
|
||||
bit_size: 15
|
||||
- name: PCROP_RDP
|
||||
description: PCROP area preserved when RDP level decreased
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/PCROP1SR:
|
||||
description: Flash Bank 1 PCROP Start address register
|
||||
fields:
|
||||
- name: PCROP1_STRT
|
||||
description: Bank 1 PCROP area start offset
|
||||
bit_offset: 0
|
||||
bit_size: 15
|
||||
- name: PCROP1_STRT
|
||||
description: Bank 1 PCROP area start offset
|
||||
bit_offset: 0
|
||||
bit_size: 15
|
||||
fieldset/PDKEYR:
|
||||
description: Power down key register
|
||||
fields:
|
||||
- name: PDKEYR
|
||||
description: RUN_PD in FLASH_ACR key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: PDKEYR
|
||||
description: RUN_PD in FLASH_ACR key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SEC1R:
|
||||
description: securable area bank1 register
|
||||
fields:
|
||||
- name: SEC_SIZE1
|
||||
description: SEC_SIZE1
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: BOOT_LOCK
|
||||
description: used to force boot from user area
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: SEC_SIZE1
|
||||
description: SEC_SIZE1
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: BOOT_LOCK
|
||||
description: used to force boot from user area
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Operation error
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PROGERR
|
||||
description: Programming error
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protected error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: Size error
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: Programming sequence error
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: MISERR
|
||||
description: Fast programming data miss error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: FASTERR
|
||||
description: Fast programming error
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: PCROP read error
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: OPTVERR
|
||||
description: Option validity error
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Operation error
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PROGERR
|
||||
description: Programming error
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protected error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: Size error
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: Programming sequence error
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: MISERR
|
||||
description: Fast programming data miss error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: FASTERR
|
||||
description: Fast programming error
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: PCROP read error
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: OPTVERR
|
||||
description: Option validity error
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
fieldset/WRP1AR:
|
||||
description: Flash Bank 1 WRP area A address register
|
||||
fields:
|
||||
- name: WRP1A_STRT
|
||||
description: Bank 1 WRP first area start offset
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: WRP1A_END
|
||||
description: Bank 1 WRP first area A end offset
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
- name: WRP1A_STRT
|
||||
description: Bank 1 WRP first area start offset
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: WRP1A_END
|
||||
description: Bank 1 WRP first area A end offset
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
fieldset/WRP1BR:
|
||||
description: Flash Bank 1 WRP area B address register
|
||||
fields:
|
||||
- name: WRP1B_STRT
|
||||
description: Bank 1 WRP second area B end offset
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: WRP1B_END
|
||||
description: Bank 1 WRP second area B start offset
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
- name: WRP1B_STRT
|
||||
description: Bank 1 WRP second area B end offset
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: WRP1B_END
|
||||
description: Bank 1 WRP second area B start offset
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
enum/LATENCY:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: WS0
|
||||
description: Zero wait states
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: One wait state
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: Two wait states
|
||||
value: 2
|
||||
- name: WS3
|
||||
description: Three wait states
|
||||
value: 3
|
||||
- name: WS4
|
||||
description: Four wait states
|
||||
value: 4
|
||||
- name: WS0
|
||||
description: Zero wait states
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: One wait state
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: Two wait states
|
||||
value: 2
|
||||
- name: WS3
|
||||
description: Three wait states
|
||||
value: 3
|
||||
- name: WS4
|
||||
description: Four wait states
|
||||
value: 4
|
||||
enum/NRST_MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: INPUT_ONLY
|
||||
description: Reset pin is in reset input mode only
|
||||
value: 1
|
||||
- name: GPIO
|
||||
description: Reset pin is in GPIO mode only
|
||||
value: 2
|
||||
- name: INPUT_OUTPUT
|
||||
description: Reset pin is in reset input and output mode
|
||||
value: 3
|
||||
- name: INPUT_ONLY
|
||||
description: Reset pin is in reset input mode only
|
||||
value: 1
|
||||
- name: GPIO
|
||||
description: Reset pin is in GPIO mode only
|
||||
value: 2
|
||||
- name: INPUT_OUTPUT
|
||||
description: Reset pin is in reset input and output mode
|
||||
value: 3
|
||||
enum/RDP:
|
||||
bit_size: 8
|
||||
variants:
|
||||
- name: LEVEL_0
|
||||
description: Read protection not active
|
||||
value: 170
|
||||
- name: LEVEL_1
|
||||
description: Memories read protection active
|
||||
value: 187
|
||||
- name: LEVEL_2
|
||||
description: Chip read protection active
|
||||
value: 204
|
||||
- name: LEVEL_0
|
||||
description: Read protection not active
|
||||
value: 170
|
||||
- name: LEVEL_1
|
||||
description: Memories read protection active
|
||||
value: 187
|
||||
- name: LEVEL_2
|
||||
description: Chip read protection active
|
||||
value: 204
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
648
data/registers/flash_h7ab.yaml
Normal file
648
data/registers/flash_h7ab.yaml
Normal file
@ -0,0 +1,648 @@
|
||||
block/BANK:
|
||||
description: Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R
|
||||
items:
|
||||
- name: KEYR
|
||||
description: FLASH key register for bank 1
|
||||
byte_offset: 0
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: CR
|
||||
description: FLASH control register for bank 1
|
||||
byte_offset: 8
|
||||
fieldset: CR
|
||||
- name: SR
|
||||
description: FLASH status register for bank 1
|
||||
byte_offset: 12
|
||||
fieldset: SR
|
||||
- name: CCR
|
||||
description: FLASH clear control register for bank 1
|
||||
byte_offset: 16
|
||||
fieldset: CCR
|
||||
- name: PRAR_CUR
|
||||
description: FLASH protection address for bank 1
|
||||
byte_offset: 36
|
||||
access: Read
|
||||
fieldset: PRAR_CUR
|
||||
- name: PRAR_PRG
|
||||
description: FLASH protection address for bank 1
|
||||
byte_offset: 40
|
||||
fieldset: PRAR_PRG
|
||||
- name: SCAR_CUR
|
||||
description: FLASH secure address for bank 1
|
||||
byte_offset: 44
|
||||
fieldset: SCAR_CUR
|
||||
- name: SCAR_PRG
|
||||
description: FLASH secure address for bank 1
|
||||
byte_offset: 48
|
||||
fieldset: SCAR_PRG
|
||||
- name: WPSN_CURR
|
||||
description: FLASH write sector protection for bank 1
|
||||
byte_offset: 52
|
||||
access: Read
|
||||
fieldset: WPSN_CURR
|
||||
- name: WPSN_PRGR
|
||||
description: FLASH write sector protection for bank 1
|
||||
byte_offset: 56
|
||||
fieldset: WPSN_PRGR
|
||||
- name: CRCCR
|
||||
description: FLASH CRC control register for bank 1
|
||||
byte_offset: 76
|
||||
fieldset: CRCCR
|
||||
- name: CRCSADDR
|
||||
description: FLASH CRC start address register for bank 1
|
||||
byte_offset: 80
|
||||
fieldset: CRCSADDR
|
||||
- name: CRCEADDR
|
||||
description: FLASH CRC end address register for bank 1
|
||||
byte_offset: 84
|
||||
fieldset: CRCEADDR
|
||||
- name: FAR
|
||||
description: FLASH ECC fail address for bank 1
|
||||
byte_offset: 92
|
||||
access: Read
|
||||
fieldset: FAR
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
- name: ACR
|
||||
description: Access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: BANK
|
||||
description: Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R
|
||||
array:
|
||||
len: 2
|
||||
stride: 256
|
||||
byte_offset: 4
|
||||
block: BANK
|
||||
- name: OPTKEYR
|
||||
description: FLASH option key register
|
||||
byte_offset: 8
|
||||
fieldset: OPTKEYR
|
||||
- name: OPTCR
|
||||
description: FLASH option control register
|
||||
byte_offset: 24
|
||||
fieldset: OPTCR
|
||||
- name: OPTSR_CUR
|
||||
description: FLASH option status register
|
||||
byte_offset: 28
|
||||
fieldset: OPTSR_CUR
|
||||
- name: OPTSR_PRG
|
||||
description: FLASH option status register
|
||||
byte_offset: 32
|
||||
fieldset: OPTSR_PRG
|
||||
- name: OPTCCR
|
||||
description: FLASH option clear control register
|
||||
byte_offset: 36
|
||||
access: Write
|
||||
fieldset: OPTCCR
|
||||
- name: BOOT_CURR
|
||||
description: FLASH register with boot address
|
||||
byte_offset: 64
|
||||
access: Read
|
||||
fieldset: BOOT_CURR
|
||||
- name: BOOT_PRGR
|
||||
description: FLASH register with boot address
|
||||
byte_offset: 68
|
||||
fieldset: BOOT_PRGR
|
||||
- name: CRCDATAR
|
||||
description: FLASH CRC data register
|
||||
byte_offset: 92
|
||||
fieldset: CRCDATAR
|
||||
fieldset/ACR:
|
||||
description: Access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: Read latency
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
- name: WRHIGHFREQ
|
||||
description: Flash signal delay
|
||||
bit_offset: 4
|
||||
bit_size: 2
|
||||
fieldset/BOOT_CURR:
|
||||
description: FLASH register with boot address
|
||||
fields:
|
||||
- name: BOOT_ADD0
|
||||
description: Boot address 0
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: BOOT_ADD1
|
||||
description: Boot address 1
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/BOOT_PRGR:
|
||||
description: FLASH register with boot address
|
||||
fields:
|
||||
- name: BOOT_ADD0
|
||||
description: Boot address 0
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: BOOT_ADD1
|
||||
description: Boot address 1
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/CCR:
|
||||
description: FLASH clear control register for bank 1
|
||||
fields:
|
||||
- name: CLR_EOP
|
||||
description: Bank 1 EOP1 flag clear bit
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: CLR_WRPERR
|
||||
description: Bank 1 WRPERR1 flag clear bit
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: CLR_PGSERR
|
||||
description: Bank 1 PGSERR1 flag clear bi
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: CLR_STRBERR
|
||||
description: Bank 1 STRBERR1 flag clear bit
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: CLR_INCERR
|
||||
description: Bank 1 INCERR1 flag clear bit
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: CLR_OPERR
|
||||
description: Bank 1 OPERR1 flag clear bit
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: CLR_RDPERR
|
||||
description: Bank 1 RDPERR1 flag clear bit
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: CLR_RDSERR
|
||||
description: Bank 1 RDSERR1 flag clear bit
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: CLR_SNECCERR
|
||||
description: Bank 1 SNECCERR1 flag clear bit
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: CLR_DBECCERR
|
||||
description: Bank 1 DBECCERR1 flag clear bit
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: CLR_CRCEND
|
||||
description: Bank 1 CRCEND1 flag clear bit
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: CLR_CRCRDERR
|
||||
description: Bank 1 CRC read error clear bit
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: FLASH control register for bank 1
|
||||
fields:
|
||||
- name: LOCK
|
||||
description: Bank 1 configuration lock bit
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PG
|
||||
description: Bank 1 program enable bit
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: SER
|
||||
description: Bank 1 sector erase request
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: BER
|
||||
description: Bank 1 erase request
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: FW
|
||||
description: Bank 1 write forcing control bit
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: START
|
||||
description: Bank 1 bank or sector erase start control bit
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SSN
|
||||
description: Bank 1 sector erase selection number
|
||||
bit_offset: 6
|
||||
bit_size: 7
|
||||
- name: CRC_EN
|
||||
description: Bank 1 CRC control bit
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: Bank 1 end-of-program interrupt control bit
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: WRPERRIE
|
||||
description: Bank 1 write protection error interrupt enable bit
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: PGSERRIE
|
||||
description: Bank 1 programming sequence error interrupt enable bit
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: STRBERRIE
|
||||
description: Bank 1 strobe error interrupt enable bit
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: INCERRIE
|
||||
description: Bank 1 inconsistency error interrupt enable bit
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: OPERRIE
|
||||
description: Bank 1 write/erase error interrupt enable bit
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: RDPERRIE
|
||||
description: Bank 1 read protection error interrupt enable bit
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: RDSERRIE
|
||||
description: Bank 1 secure error interrupt enable bit
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: SNECCERRIE
|
||||
description: Bank 1 ECC single correction error interrupt enable bit
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: DBECCERRIE
|
||||
description: Bank 1 ECC double detection error interrupt enable bit
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: CRCENDIE
|
||||
description: Bank 1 end of CRC calculation interrupt enable bit
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: CRCRDERRIE
|
||||
description: Bank 1 CRC read error interrupt enable bit
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
fieldset/CRCCR:
|
||||
description: FLASH CRC control register for bank 1
|
||||
fields:
|
||||
- name: CRC_SECT
|
||||
description: Bank 1 CRC sector number
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
- name: ALL_BANK
|
||||
description: Bank 1 CRC select bit
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: CRC_BY_SECT
|
||||
description: Bank 1 CRC sector mode select bit
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ADD_SECT
|
||||
description: Bank 1 CRC sector select bit
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: CLEAN_SECT
|
||||
description: Bank 1 CRC sector list clear bit
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: START_CRC
|
||||
description: Bank 1 CRC start bit
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: CLEAN_CRC
|
||||
description: Bank 1 CRC clear bit
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: CRC_BURST
|
||||
description: Bank 1 CRC burst size
|
||||
bit_offset: 20
|
||||
bit_size: 2
|
||||
fieldset/CRCDATAR:
|
||||
description: FLASH CRC data register
|
||||
fields:
|
||||
- name: CRC_DATA
|
||||
description: CRC result
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/CRCEADDR:
|
||||
description: FLASH CRC end address register for bank 1
|
||||
fields:
|
||||
- name: CRC_END_ADDR
|
||||
description: CRC end address on bank 1
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/CRCSADDR:
|
||||
description: FLASH CRC start address register for bank 1
|
||||
fields:
|
||||
- name: CRC_START_ADDR
|
||||
description: CRC start address on bank 1
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/FAR:
|
||||
description: FLASH ECC fail address for bank 1
|
||||
fields:
|
||||
- name: FAIL_ECC_ADDR
|
||||
description: Bank 1 ECC error address
|
||||
bit_offset: 0
|
||||
bit_size: 15
|
||||
fieldset/KEYR:
|
||||
description: FLASH key register for bank 1
|
||||
fields:
|
||||
- name: KEYR
|
||||
description: Bank 1 access configuration unlock key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTCCR:
|
||||
description: FLASH option clear control register
|
||||
fields:
|
||||
- name: CLR_OPTCHANGEERR
|
||||
description: OPTCHANGEERR reset bit
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
fieldset/OPTCR:
|
||||
description: FLASH option control register
|
||||
fields:
|
||||
- name: OPTLOCK
|
||||
description: FLASH_OPTCR lock option configuration bit
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPTSTART
|
||||
description: Option byte start change option configuration bit
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Flash mass erase enable bit
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PG_OTP
|
||||
description: OTP program control bit
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: OPTCHANGEERRIE
|
||||
description: Option byte change error interrupt enable bit
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: SWAP_BANK
|
||||
description: Bank swapping configuration bit
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/OPTKEYR:
|
||||
description: FLASH option key register
|
||||
fields:
|
||||
- name: OPTKEYR
|
||||
description: Unlock key option bytes
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTSR_CUR:
|
||||
description: FLASH option status register
|
||||
fields:
|
||||
- name: OPT_BUSY
|
||||
description: Option byte change ongoing flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: BOR_LEV
|
||||
description: Brownout level option status bit
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
- name: IWDG1_HW
|
||||
description: IWDG1 control option status bit
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: nRST_STOP_D1
|
||||
description: D1 DStop entry reset option status bit
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: nRST_STBY_D1
|
||||
description: D1 DStandby entry reset option status bit
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: RDP
|
||||
description: Readout protection level option status byte
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: FZ_IWDG_STOP
|
||||
description: IWDG Stop mode freeze option status bit
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: FZ_IWDG_SDBY
|
||||
description: IWDG Standby mode freeze option status bit
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: ST_RAM_SIZE
|
||||
description: DTCM RAM size option status
|
||||
bit_offset: 19
|
||||
bit_size: 2
|
||||
- name: SECURITY
|
||||
description: Security enable option status bit
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: RSS1
|
||||
description: User option bit 1
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: PERSO_OK
|
||||
description: Device personalization status bit
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: IO_HSLV
|
||||
description: I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V)
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: OPTCHANGEERR
|
||||
description: Option byte change error flag
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: SWAP_BANK_OPT
|
||||
description: Bank swapping option status bit
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/OPTSR_PRG:
|
||||
description: FLASH option status register
|
||||
fields:
|
||||
- name: BOR_LEV
|
||||
description: BOR reset level option configuration bits
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
- name: IWDG1_HW
|
||||
description: IWDG1 option configuration bit
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: nRST_STOP_D1
|
||||
description: Option byte erase after D1 DStop option configuration bit
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: nRST_STBY_D1
|
||||
description: Option byte erase after D1 DStandby option configuration bit
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: RDP
|
||||
description: Readout protection level option configuration byte
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: FZ_IWDG_STOP
|
||||
description: IWDG Stop mode freeze option configuration bit
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: FZ_IWDG_SDBY
|
||||
description: IWDG Standby mode freeze option configuration bit
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: ST_RAM_SIZE
|
||||
description: DTCM size select option configuration bits
|
||||
bit_offset: 19
|
||||
bit_size: 2
|
||||
- name: SECURITY
|
||||
description: Security option configuration bit
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: RSS1
|
||||
description: User option configuration bit 1
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: RSS2
|
||||
description: User option configuration bit 2
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: IO_HSLV
|
||||
description: I/O high-speed at low-voltage (PRODUCT_BELOW_25V)
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: SWAP_BANK_OPT
|
||||
description: Bank swapping option configuration bit
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/PRAR_CUR:
|
||||
description: FLASH protection address for bank 1
|
||||
fields:
|
||||
- name: PROT_AREA_START
|
||||
description: Bank 1 lowest PCROP protected address
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: PROT_AREA_END
|
||||
description: Bank 1 highest PCROP protected address
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
- name: DMEP
|
||||
description: Bank 1 PCROP protected erase enable option status bit
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/PRAR_PRG:
|
||||
description: FLASH protection address for bank 1
|
||||
fields:
|
||||
- name: PROT_AREA_START
|
||||
description: Bank 1 lowest PCROP protected address configuration
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: PROT_AREA_END
|
||||
description: Bank 1 highest PCROP protected address configuration
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
- name: DMEP
|
||||
description: Bank 1 PCROP protected erase enable option configuration bit
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SCAR_CUR:
|
||||
description: FLASH secure address for bank 1
|
||||
fields:
|
||||
- name: SEC_AREA_START
|
||||
description: Bank 1 lowest secure protected address
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: SEC_AREA_END
|
||||
description: Bank 1 highest secure protected address
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
- name: DMES
|
||||
description: Bank 1 secure protected erase enable option status bit
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SCAR_PRG:
|
||||
description: FLASH secure address for bank 1
|
||||
fields:
|
||||
- name: SEC_AREA_START
|
||||
description: Bank 1 lowest secure protected address configuration
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: SEC_AREA_END
|
||||
description: Bank 1 highest secure protected address configuration
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
- name: DMES
|
||||
description: Bank 1 secure protected erase enable option configuration bit
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SR:
|
||||
description: FLASH status register for bank 1
|
||||
fields:
|
||||
- name: BSY
|
||||
description: Bank 1 ongoing program flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: WBNE
|
||||
description: Bank 1 write buffer not empty flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: QW
|
||||
description: Bank 1 wait queue flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: CRC_BUSY
|
||||
description: Bank 1 CRC busy flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: Bank 1 end-of-program flag
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Bank 1 write protection error flag
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: Bank 1 programming sequence error flag
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: STRBERR
|
||||
description: Bank 1 strobe error flag
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: INCERR
|
||||
description: Bank 1 inconsistency error flag
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Bank 1 write/erase error flag
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: RDPERR
|
||||
description: Bank 1 read protection error flag
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: RDSERR
|
||||
description: Bank 1 secure error flag
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: SNECCERR1
|
||||
description: Bank 1 single correction error flag
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: DBECCERR
|
||||
description: Bank 1 ECC double detection error flag
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: CRCEND
|
||||
description: Bank 1 CRC-complete flag
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: CRCRDERR
|
||||
description: Bank 1 CRC read error flag
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
fieldset/WPSN_CURR:
|
||||
description: FLASH write sector protection for bank 1
|
||||
fields:
|
||||
- name: WRPSn
|
||||
description: Bank 1 sector write protection option status byte
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/WPSN_PRGR:
|
||||
description: FLASH write sector protection for bank 1
|
||||
fields:
|
||||
- name: WRPSn
|
||||
description: Bank 1 sector write protection configuration byte
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
@ -1,229 +1,228 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
- name: ACR
|
||||
description: Access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: PECR
|
||||
description: Program/erase control register
|
||||
byte_offset: 4
|
||||
fieldset: PECR
|
||||
- name: PDKEYR
|
||||
description: Power down key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: PDKEYR
|
||||
- name: PEKEYR
|
||||
description: Program/erase key register
|
||||
byte_offset: 12
|
||||
access: Write
|
||||
fieldset: PEKEYR
|
||||
- name: PRGKEYR
|
||||
description: Program memory key register
|
||||
byte_offset: 16
|
||||
access: Write
|
||||
fieldset: PRGKEYR
|
||||
- name: OPTKEYR
|
||||
description: Option byte key register
|
||||
byte_offset: 20
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 24
|
||||
fieldset: SR
|
||||
- name: OPTR
|
||||
description: Option byte register
|
||||
byte_offset: 28
|
||||
access: Read
|
||||
fieldset: OPTR
|
||||
- name: WRPROT
|
||||
description: Write Protection Register 1
|
||||
byte_offset: 32
|
||||
access: Read
|
||||
fieldset: WRPROT
|
||||
- name: WRPROT2
|
||||
description: Write Protection Register 2
|
||||
byte_offset: 128
|
||||
access: Read
|
||||
fieldset: WRPROT
|
||||
- name: ACR
|
||||
description: Access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: PECR
|
||||
description: Program/erase control register
|
||||
byte_offset: 4
|
||||
fieldset: PECR
|
||||
- name: PDKEYR
|
||||
description: Power down key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: PDKEYR
|
||||
- name: PEKEYR
|
||||
description: Program/erase key register
|
||||
byte_offset: 12
|
||||
access: Write
|
||||
fieldset: PEKEYR
|
||||
- name: PRGKEYR
|
||||
description: Program memory key register
|
||||
byte_offset: 16
|
||||
access: Write
|
||||
fieldset: PRGKEYR
|
||||
- name: OPTKEYR
|
||||
description: Option byte key register
|
||||
byte_offset: 20
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 24
|
||||
fieldset: SR
|
||||
- name: OPTR
|
||||
description: Option byte register
|
||||
byte_offset: 28
|
||||
access: Read
|
||||
fieldset: OPTR
|
||||
- name: WRPROT
|
||||
description: Write Protection Register 1
|
||||
byte_offset: 32
|
||||
access: Read
|
||||
fieldset: WRPROT
|
||||
- name: WRPROT2
|
||||
description: Write Protection Register 2
|
||||
byte_offset: 128
|
||||
access: Read
|
||||
fieldset: WRPROT
|
||||
fieldset/ACR:
|
||||
description: Access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: SLEEP_PD
|
||||
description: Flash mode during Sleep
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: RUN_PD
|
||||
description: Flash mode during Run
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: DISAB_BUF
|
||||
description: Disable Buffer
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: PRE_READ
|
||||
description: Pre-read data address
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: SLEEP_PD
|
||||
description: Flash mode during Sleep
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: RUN_PD
|
||||
description: Flash mode during Run
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: DISAB_BUF
|
||||
description: Disable Buffer
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: PRE_READ
|
||||
description: Pre-read data address
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/OPTKEYR:
|
||||
description: Option byte key register
|
||||
fields:
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTR:
|
||||
description: Option byte register
|
||||
fields:
|
||||
- name: RDPROT
|
||||
description: Read protection
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: WPRMOD
|
||||
description: Selection of protection mode of WPR bits
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: BOR_LEV
|
||||
description: BOR_LEV
|
||||
bit_offset: 16
|
||||
bit_size: 4
|
||||
- name: RDPROT
|
||||
description: Read protection
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: WPRMOD
|
||||
description: Selection of protection mode of WPR bits
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: BOR_LEV
|
||||
description: BOR_LEV
|
||||
bit_offset: 16
|
||||
bit_size: 4
|
||||
fieldset/PDKEYR:
|
||||
description: Power down key register
|
||||
fields:
|
||||
- name: PDKEYR
|
||||
description: RUN_PD in FLASH_ACR key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: PDKEYR
|
||||
description: RUN_PD in FLASH_ACR key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PECR:
|
||||
description: Program/erase control register
|
||||
fields:
|
||||
- name: PELOCK
|
||||
description: FLASH_PECR and data EEPROM lock
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PRGLOCK
|
||||
description: Program memory lock
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: Option bytes block lock
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PROG
|
||||
description: Program memory selection
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DATA
|
||||
description: Data EEPROM selection
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: FIX
|
||||
description: "Fixed time data write for Byte, Half Word and Word programming"
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ERASE
|
||||
description: Page or Double Word erase mode
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: FPRG
|
||||
description: Half Page/Double Word programming mode
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: PARALLELBANK
|
||||
description: Parallel bank mode
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of programming interrupt enable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: Launch the option byte loading
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: PELOCK
|
||||
description: FLASH_PECR and data EEPROM lock
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PRGLOCK
|
||||
description: Program memory lock
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: Option bytes block lock
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PROG
|
||||
description: Program memory selection
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DATA
|
||||
description: Data EEPROM selection
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: FIX
|
||||
description: Fixed time data write for Byte, Half Word and Word programming
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ERASE
|
||||
description: Page or Double Word erase mode
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: FPRG
|
||||
description: Half Page/Double Word programming mode
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: PARALLELBANK
|
||||
description: Parallel bank mode
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of programming interrupt enable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: Launch the option byte loading
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/PEKEYR:
|
||||
description: Program/erase key register
|
||||
fields:
|
||||
- name: PEKEYR
|
||||
description: FLASH_PEC and data EEPROM key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: PEKEYR
|
||||
description: FLASH_PEC and data EEPROM key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PRGKEYR:
|
||||
description: Program memory key register
|
||||
fields:
|
||||
- name: PRGKEYR
|
||||
description: Program memory key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: PRGKEYR
|
||||
description: Program memory key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: BSY
|
||||
description: Write/erase operations in progress
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ENDHV
|
||||
description: End of high voltage
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: READY
|
||||
description: Flash memory module ready after low power mode
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protected error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: Size error
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: OPTVERR
|
||||
description: Option validity error
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: RDERR
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: NOTZEROERR
|
||||
description: NOTZEROERR
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: FWWERR
|
||||
description: FWWERR
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Write/erase operations in progress
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ENDHV
|
||||
description: End of high voltage
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: READY
|
||||
description: Flash memory module ready after low power mode
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protected error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: Size error
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: OPTVERR
|
||||
description: Option validity error
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: RDERR
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: NOTZEROERR
|
||||
description: NOTZEROERR
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: FWWERR
|
||||
description: FWWERR
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
fieldset/WRPROT:
|
||||
description: Write Protection Register
|
||||
fields:
|
||||
- name: WRPROT
|
||||
description: Write Protection
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
- name: WRPROT
|
||||
description: Write Protection
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
|
||||
@ -1,242 +1,241 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
- name: ACR
|
||||
description: Access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: PECR
|
||||
description: Program/erase control register
|
||||
byte_offset: 4
|
||||
fieldset: PECR
|
||||
- name: PDKEYR
|
||||
description: Power down key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: PDKEYR
|
||||
- name: PEKEYR
|
||||
description: Program/erase key register
|
||||
byte_offset: 12
|
||||
access: Write
|
||||
fieldset: PEKEYR
|
||||
- name: PRGKEYR
|
||||
description: Program memory key register
|
||||
byte_offset: 16
|
||||
access: Write
|
||||
fieldset: PRGKEYR
|
||||
- name: OPTKEYR
|
||||
description: Option byte key register
|
||||
byte_offset: 20
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 24
|
||||
fieldset: SR
|
||||
- name: OBR
|
||||
description: Option byte register
|
||||
byte_offset: 28
|
||||
access: Read
|
||||
fieldset: OBR
|
||||
- name: WRPR1
|
||||
description: Write protection register
|
||||
byte_offset: 32
|
||||
fieldset: WRPR1
|
||||
- name: WRPR2
|
||||
description: Write protection register
|
||||
byte_offset: 128
|
||||
fieldset: WRPR2
|
||||
- name: WRPR3
|
||||
description: Write protection register
|
||||
byte_offset: 132
|
||||
fieldset: WRPR3
|
||||
- name: ACR
|
||||
description: Access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: PECR
|
||||
description: Program/erase control register
|
||||
byte_offset: 4
|
||||
fieldset: PECR
|
||||
- name: PDKEYR
|
||||
description: Power down key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: PDKEYR
|
||||
- name: PEKEYR
|
||||
description: Program/erase key register
|
||||
byte_offset: 12
|
||||
access: Write
|
||||
fieldset: PEKEYR
|
||||
- name: PRGKEYR
|
||||
description: Program memory key register
|
||||
byte_offset: 16
|
||||
access: Write
|
||||
fieldset: PRGKEYR
|
||||
- name: OPTKEYR
|
||||
description: Option byte key register
|
||||
byte_offset: 20
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 24
|
||||
fieldset: SR
|
||||
- name: OBR
|
||||
description: Option byte register
|
||||
byte_offset: 28
|
||||
access: Read
|
||||
fieldset: OBR
|
||||
- name: WRPR1
|
||||
description: Write protection register
|
||||
byte_offset: 32
|
||||
fieldset: WRPR1
|
||||
- name: WRPR2
|
||||
description: Write protection register
|
||||
byte_offset: 128
|
||||
fieldset: WRPR2
|
||||
- name: WRPR3
|
||||
description: Write protection register
|
||||
byte_offset: 132
|
||||
fieldset: WRPR3
|
||||
fieldset/ACR:
|
||||
description: Access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ACC64
|
||||
description: 64-bit access
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: SLEEP_PD
|
||||
description: Flash mode during Sleep
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: RUN_PD
|
||||
description: Flash mode during Run
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ACC64
|
||||
description: 64-bit access
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: SLEEP_PD
|
||||
description: Flash mode during Sleep
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: RUN_PD
|
||||
description: Flash mode during Run
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
fieldset/OBR:
|
||||
description: Option byte register
|
||||
fields:
|
||||
- name: RDPRT
|
||||
description: Read protection
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: BOR_LEV
|
||||
description: BOR_LEV
|
||||
bit_offset: 16
|
||||
bit_size: 4
|
||||
- name: IWDG_SW
|
||||
description: IWDG_SW
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: nRTS_STOP
|
||||
description: nRTS_STOP
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: BFB2
|
||||
description: Boot From Bank 2
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: RDPRT
|
||||
description: Read protection
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: BOR_LEV
|
||||
description: BOR_LEV
|
||||
bit_offset: 16
|
||||
bit_size: 4
|
||||
- name: IWDG_SW
|
||||
description: IWDG_SW
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: nRTS_STOP
|
||||
description: nRTS_STOP
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: BFB2
|
||||
description: Boot From Bank 2
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/OPTKEYR:
|
||||
description: Option byte key register
|
||||
fields:
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PDKEYR:
|
||||
description: Power down key register
|
||||
fields:
|
||||
- name: PDKEYR
|
||||
description: RUN_PD in FLASH_ACR key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: PDKEYR
|
||||
description: RUN_PD in FLASH_ACR key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PECR:
|
||||
description: Program/erase control register
|
||||
fields:
|
||||
- name: PELOCK
|
||||
description: FLASH_PECR and data EEPROM lock
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PRGLOCK
|
||||
description: Program memory lock
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: Option bytes block lock
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PROG
|
||||
description: Program memory selection
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DATA
|
||||
description: Data EEPROM selection
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: FTDW
|
||||
description: "Fixed time data write for Byte, Half Word and Word programming"
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ERASE
|
||||
description: Page or Double Word erase mode
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: FPRG
|
||||
description: Half Page/Double Word programming mode
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: PARALLELBANK
|
||||
description: Parallel bank mode
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of programming interrupt enable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: Launch the option byte loading
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: PELOCK
|
||||
description: FLASH_PECR and data EEPROM lock
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PRGLOCK
|
||||
description: Program memory lock
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: Option bytes block lock
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PROG
|
||||
description: Program memory selection
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DATA
|
||||
description: Data EEPROM selection
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: FTDW
|
||||
description: Fixed time data write for Byte, Half Word and Word programming
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ERASE
|
||||
description: Page or Double Word erase mode
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: FPRG
|
||||
description: Half Page/Double Word programming mode
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: PARALLELBANK
|
||||
description: Parallel bank mode
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of programming interrupt enable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: Launch the option byte loading
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/PEKEYR:
|
||||
description: Program/erase key register
|
||||
fields:
|
||||
- name: PEKEYR
|
||||
description: FLASH_PEC and data EEPROM key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: PEKEYR
|
||||
description: FLASH_PEC and data EEPROM key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PRGKEYR:
|
||||
description: Program memory key register
|
||||
fields:
|
||||
- name: PRGKEYR
|
||||
description: Program memory key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: PRGKEYR
|
||||
description: Program memory key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: BSY
|
||||
description: Write/erase operations in progress
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ENDHV
|
||||
description: End of high voltage
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: READY
|
||||
description: Flash memory module ready after low power mode
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protected error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: Size error
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: OPTVERR
|
||||
description: Option validity error
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: OPTVERRUSR
|
||||
description: Option UserValidity Error
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Write/erase operations in progress
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ENDHV
|
||||
description: End of high voltage
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: READY
|
||||
description: Flash memory module ready after low power mode
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protected error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: Size error
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: OPTVERR
|
||||
description: Option validity error
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: OPTVERRUSR
|
||||
description: Option UserValidity Error
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
fieldset/WRPR1:
|
||||
description: Write protection register
|
||||
fields:
|
||||
- name: WRP1
|
||||
description: Write protection
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: WRP1
|
||||
description: Write protection
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/WRPR2:
|
||||
description: Write protection register
|
||||
fields:
|
||||
- name: WRP2
|
||||
description: WRP2
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: WRP2
|
||||
description: WRP2
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/WRPR3:
|
||||
description: Write protection register
|
||||
fields:
|
||||
- name: WRP3
|
||||
description: WRP3
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: WRP3
|
||||
description: WRP3
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
|
||||
@ -1,406 +1,405 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
- name: ACR
|
||||
description: Access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: PDKEYR
|
||||
description: Power down key register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: PDKEYR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Option byte key register
|
||||
byte_offset: 12
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 16
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Flash control register
|
||||
byte_offset: 20
|
||||
fieldset: CR
|
||||
- name: ECCR
|
||||
description: Flash ECC register
|
||||
byte_offset: 24
|
||||
fieldset: ECCR
|
||||
- name: OPTR
|
||||
description: Flash option register
|
||||
byte_offset: 32
|
||||
fieldset: OPTR
|
||||
- name: PCROP1SR
|
||||
description: Flash Bank 1 PCROP Start address register
|
||||
byte_offset: 36
|
||||
fieldset: PCROP1SR
|
||||
- name: PCROP1ER
|
||||
description: Flash Bank 1 PCROP End address register
|
||||
byte_offset: 40
|
||||
fieldset: PCROP1ER
|
||||
- name: WRP1AR
|
||||
description: Flash Bank 1 WRP area A address register
|
||||
byte_offset: 44
|
||||
fieldset: WRP1AR
|
||||
- name: WRP1BR
|
||||
description: Flash Bank 1 WRP area B address register
|
||||
byte_offset: 48
|
||||
fieldset: WRP1BR
|
||||
- name: PCROP2SR
|
||||
description: Flash Bank 2 PCROP Start address register
|
||||
byte_offset: 68
|
||||
fieldset: PCROP2SR
|
||||
- name: PCROP2ER
|
||||
description: Flash Bank 2 PCROP End address register
|
||||
byte_offset: 72
|
||||
fieldset: PCROP2ER
|
||||
- name: WRP2AR
|
||||
description: Flash Bank 2 WRP area A address register
|
||||
byte_offset: 76
|
||||
fieldset: WRP2AR
|
||||
- name: WRP2BR
|
||||
description: Flash Bank 2 WRP area B address register
|
||||
byte_offset: 80
|
||||
fieldset: WRP2BR
|
||||
- name: ACR
|
||||
description: Access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: PDKEYR
|
||||
description: Power down key register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: PDKEYR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Option byte key register
|
||||
byte_offset: 12
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 16
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Flash control register
|
||||
byte_offset: 20
|
||||
fieldset: CR
|
||||
- name: ECCR
|
||||
description: Flash ECC register
|
||||
byte_offset: 24
|
||||
fieldset: ECCR
|
||||
- name: OPTR
|
||||
description: Flash option register
|
||||
byte_offset: 32
|
||||
fieldset: OPTR
|
||||
- name: PCROP1SR
|
||||
description: Flash Bank 1 PCROP Start address register
|
||||
byte_offset: 36
|
||||
fieldset: PCROP1SR
|
||||
- name: PCROP1ER
|
||||
description: Flash Bank 1 PCROP End address register
|
||||
byte_offset: 40
|
||||
fieldset: PCROP1ER
|
||||
- name: WRP1AR
|
||||
description: Flash Bank 1 WRP area A address register
|
||||
byte_offset: 44
|
||||
fieldset: WRP1AR
|
||||
- name: WRP1BR
|
||||
description: Flash Bank 1 WRP area B address register
|
||||
byte_offset: 48
|
||||
fieldset: WRP1BR
|
||||
- name: PCROP2SR
|
||||
description: Flash Bank 2 PCROP Start address register
|
||||
byte_offset: 68
|
||||
fieldset: PCROP2SR
|
||||
- name: PCROP2ER
|
||||
description: Flash Bank 2 PCROP End address register
|
||||
byte_offset: 72
|
||||
fieldset: PCROP2ER
|
||||
- name: WRP2AR
|
||||
description: Flash Bank 2 WRP area A address register
|
||||
byte_offset: 76
|
||||
fieldset: WRP2AR
|
||||
- name: WRP2BR
|
||||
description: Flash Bank 2 WRP area B address register
|
||||
byte_offset: 80
|
||||
fieldset: WRP2BR
|
||||
fieldset/ACR:
|
||||
description: Access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ICEN
|
||||
description: Instruction cache enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: DCEN
|
||||
description: Data cache enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ICRST
|
||||
description: Instruction cache reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DCRST
|
||||
description: Data cache reset
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: RUN_PD
|
||||
description: Flash Power-down mode during Low-power run mode
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: SLEEP_PD
|
||||
description: Flash Power-down mode during Low-power sleep mode
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ICEN
|
||||
description: Instruction cache enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: DCEN
|
||||
description: Data cache enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ICRST
|
||||
description: Instruction cache reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DCRST
|
||||
description: Data cache reset
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: RUN_PD
|
||||
description: Flash Power-down mode during Low-power run mode
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: SLEEP_PD
|
||||
description: Flash Power-down mode during Low-power sleep mode
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Flash control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Bank 1 Mass erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 13
|
||||
- name: PNB
|
||||
description: Page number
|
||||
bit_offset: 3
|
||||
bit_size: 8
|
||||
- name: BKER
|
||||
description: Bank erase
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: START
|
||||
description: Start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: Options modification start
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: FSTPG
|
||||
description: Fast programming
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: RDERRIE
|
||||
description: PCROP read error interrupt enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: Force the option byte loading
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: Options Lock
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: FLASH_CR Lock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Bank 1 Mass erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 13
|
||||
- name: PNB
|
||||
description: Page number
|
||||
bit_offset: 3
|
||||
bit_size: 8
|
||||
- name: BKER
|
||||
description: Bank erase
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: START
|
||||
description: Start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: Options modification start
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: FSTPG
|
||||
description: Fast programming
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: RDERRIE
|
||||
description: PCROP read error interrupt enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: Force the option byte loading
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: Options Lock
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: FLASH_CR Lock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/ECCR:
|
||||
description: Flash ECC register
|
||||
fields:
|
||||
- name: ADDR_ECC
|
||||
description: ECC fail address
|
||||
bit_offset: 0
|
||||
bit_size: 19
|
||||
- name: BK_ECC
|
||||
description: ECC fail bank
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: SYSF_ECC
|
||||
description: System Flash ECC fail
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: ECCIE
|
||||
description: ECC correction interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ECCC
|
||||
description: ECC correction
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: ECCD
|
||||
description: ECC detection
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: ADDR_ECC
|
||||
description: ECC fail address
|
||||
bit_offset: 0
|
||||
bit_size: 19
|
||||
- name: BK_ECC
|
||||
description: ECC fail bank
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: SYSF_ECC
|
||||
description: System Flash ECC fail
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: ECCIE
|
||||
description: ECC correction interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ECCC
|
||||
description: ECC correction
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: ECCD
|
||||
description: ECC detection
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/KEYR:
|
||||
description: Flash key register
|
||||
fields:
|
||||
- name: KEYR
|
||||
description: KEYR
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: KEYR
|
||||
description: KEYR
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTKEYR:
|
||||
description: Option byte key register
|
||||
fields:
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTR:
|
||||
description: Flash option register
|
||||
fields:
|
||||
- name: RDP
|
||||
description: Read protection level
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: BOR_LEV
|
||||
description: BOR reset Level
|
||||
bit_offset: 8
|
||||
bit_size: 3
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: IDWG_SW
|
||||
description: Independent watchdog selection
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: IWDG_STOP
|
||||
description: Independent watchdog counter freeze in Stop mode
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: IWDG_STDBY
|
||||
description: Independent watchdog counter freeze in Standby mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: WWDG_SW
|
||||
description: Window watchdog selection
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: BFB
|
||||
description: Dual-bank boot
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: DUALBANK
|
||||
description: Dual-Bank on 512 KB or 256 KB Flash memory devices
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: nBOOT1
|
||||
description: Boot configuration
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: SRAM2_PE
|
||||
description: SRAM2 parity check enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: SRAM2_RST
|
||||
description: SRAM2 Erase when system reset
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: nSWBOOT0
|
||||
description: Software BOOT0
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: nBOOT0
|
||||
description: nBOOT0 option bit
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: RDP
|
||||
description: Read protection level
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: BOR_LEV
|
||||
description: BOR reset Level
|
||||
bit_offset: 8
|
||||
bit_size: 3
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: IDWG_SW
|
||||
description: Independent watchdog selection
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: IWDG_STOP
|
||||
description: Independent watchdog counter freeze in Stop mode
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: IWDG_STDBY
|
||||
description: Independent watchdog counter freeze in Standby mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: WWDG_SW
|
||||
description: Window watchdog selection
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: BFB
|
||||
description: Dual-bank boot
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: DUALBANK
|
||||
description: Dual-Bank on 512 KB or 256 KB Flash memory devices
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: nBOOT1
|
||||
description: Boot configuration
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: SRAM2_PE
|
||||
description: SRAM2 parity check enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: SRAM2_RST
|
||||
description: SRAM2 Erase when system reset
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: nSWBOOT0
|
||||
description: Software BOOT0
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: nBOOT0
|
||||
description: nBOOT0 option bit
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
fieldset/PCROP1ER:
|
||||
description: Flash Bank 1 PCROP End address register
|
||||
fields:
|
||||
- name: PCROP1_END
|
||||
description: Bank 1 PCROP area end offset
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: PCROP_RDP
|
||||
description: PCROP area preserved when RDP level decreased
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: PCROP1_END
|
||||
description: Bank 1 PCROP area end offset
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: PCROP_RDP
|
||||
description: PCROP area preserved when RDP level decreased
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/PCROP1SR:
|
||||
description: Flash Bank 1 PCROP Start address register
|
||||
fields:
|
||||
- name: PCROP1_STRT
|
||||
description: Bank 1 PCROP area start offset
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: PCROP1_STRT
|
||||
description: Bank 1 PCROP area start offset
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/PCROP2ER:
|
||||
description: Flash Bank 2 PCROP End address register
|
||||
fields:
|
||||
- name: PCROP2_END
|
||||
description: Bank 2 PCROP area end offset
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: PCROP2_END
|
||||
description: Bank 2 PCROP area end offset
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/PCROP2SR:
|
||||
description: Flash Bank 2 PCROP Start address register
|
||||
fields:
|
||||
- name: PCROP2_STRT
|
||||
description: Bank 2 PCROP area start offset
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: PCROP2_STRT
|
||||
description: Bank 2 PCROP area start offset
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/PDKEYR:
|
||||
description: Power down key register
|
||||
fields:
|
||||
- name: PDKEYR
|
||||
description: RUN_PD in FLASH_ACR key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: PDKEYR
|
||||
description: RUN_PD in FLASH_ACR key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Operation error
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PROGERR
|
||||
description: Programming error
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protected error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: Size error
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: Programming sequence error
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: MISERR
|
||||
description: Fast programming data miss error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: FASTERR
|
||||
description: Fast programming error
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: PCROP read error
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: OPTVERR
|
||||
description: Option validity error
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Operation error
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PROGERR
|
||||
description: Programming error
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protected error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: Size error
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: Programming sequence error
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: MISERR
|
||||
description: Fast programming data miss error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: FASTERR
|
||||
description: Fast programming error
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: PCROP read error
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: OPTVERR
|
||||
description: Option validity error
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
fieldset/WRP1AR:
|
||||
description: Flash Bank 1 WRP area A address register
|
||||
fields:
|
||||
- name: WRP1A_STRT
|
||||
description: Bank 1 WRP first area tart offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: WRP1A_END
|
||||
description: Bank 1 WRP first area A end offset
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: WRP1A_STRT
|
||||
description: Bank 1 WRP first area tart offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: WRP1A_END
|
||||
description: Bank 1 WRP first area A end offset
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
fieldset/WRP1BR:
|
||||
description: Flash Bank 1 WRP area B address register
|
||||
fields:
|
||||
- name: WRP1B_STRT
|
||||
description: Bank 1 WRP second area B start offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: WRP1B_END
|
||||
description: Bank 1 WRP second area B end offset
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: WRP1B_STRT
|
||||
description: Bank 1 WRP second area B start offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: WRP1B_END
|
||||
description: Bank 1 WRP second area B end offset
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
fieldset/WRP2AR:
|
||||
description: Flash Bank 2 WRP area A address register
|
||||
fields:
|
||||
- name: WRP2A_STRT
|
||||
description: Bank 2 WRP first area A start offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: WRP2A_END
|
||||
description: Bank 2 WRP first area A end offset
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: WRP2A_STRT
|
||||
description: Bank 2 WRP first area A start offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: WRP2A_END
|
||||
description: Bank 2 WRP first area A end offset
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
fieldset/WRP2BR:
|
||||
description: Flash Bank 2 WRP area B address register
|
||||
fields:
|
||||
- name: WRP2B_STRT
|
||||
description: Bank 2 WRP second area B start offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: WRP2B_END
|
||||
description: Bank 2 WRP second area B end offset
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: WRP2B_STRT
|
||||
description: Bank 2 WRP second area B start offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: WRP2B_END
|
||||
description: Bank 2 WRP second area B end offset
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
643
data/registers/flash_wba.yaml
Normal file
643
data/registers/flash_wba.yaml
Normal file
@ -0,0 +1,643 @@
|
||||
block/FLASH:
|
||||
description: Embedded memory
|
||||
items:
|
||||
- name: ACR
|
||||
description: access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: NSKEYR
|
||||
description: key register
|
||||
byte_offset: 8
|
||||
fieldset: NSKEYR
|
||||
- name: SECKEYR
|
||||
description: secure key register
|
||||
byte_offset: 12
|
||||
fieldset: SECKEYR
|
||||
- name: OPTKEYR
|
||||
description: option key register
|
||||
byte_offset: 16
|
||||
fieldset: OPTKEYR
|
||||
- name: PDKEYR
|
||||
description: power-down key register
|
||||
byte_offset: 24
|
||||
fieldset: PDKEYR
|
||||
- name: NSSR
|
||||
description: status register
|
||||
byte_offset: 32
|
||||
fieldset: NSSR
|
||||
- name: SECSR
|
||||
description: secure status register
|
||||
byte_offset: 36
|
||||
fieldset: SECSR
|
||||
- name: NSCR1
|
||||
description: control register
|
||||
byte_offset: 40
|
||||
fieldset: NSCR1
|
||||
- name: SECCR1
|
||||
description: secure control register
|
||||
byte_offset: 44
|
||||
fieldset: SECCR1
|
||||
- name: ECCR
|
||||
description: ECC register
|
||||
byte_offset: 48
|
||||
fieldset: ECCR
|
||||
- name: OPSR
|
||||
description: operation status register
|
||||
byte_offset: 52
|
||||
fieldset: OPSR
|
||||
- name: NSCR2
|
||||
description: control 2 register
|
||||
byte_offset: 56
|
||||
fieldset: NSCR2
|
||||
- name: SECCR2
|
||||
description: secure control 2 register
|
||||
byte_offset: 60
|
||||
fieldset: SECCR2
|
||||
- name: OPTR
|
||||
description: option register
|
||||
byte_offset: 64
|
||||
fieldset: OPTR
|
||||
- name: NSBOOTADD0R
|
||||
description: boot address 0 register
|
||||
byte_offset: 68
|
||||
fieldset: NSBOOTADD0R
|
||||
- name: NSBOOTADD1R
|
||||
description: boot address 1 register
|
||||
byte_offset: 72
|
||||
fieldset: NSBOOTADD1R
|
||||
- name: SECBOOTADD0R
|
||||
description: secure boot address 0 register
|
||||
byte_offset: 76
|
||||
fieldset: SECBOOTADD0R
|
||||
- name: SECWMR1
|
||||
description: secure watermark register 1
|
||||
byte_offset: 80
|
||||
fieldset: SECWMR1
|
||||
- name: SECWMR2
|
||||
description: secure watermark register 2
|
||||
byte_offset: 84
|
||||
fieldset: SECWMR2
|
||||
- name: WRPAR
|
||||
description: WRP area A address register
|
||||
byte_offset: 88
|
||||
fieldset: WRPAR
|
||||
- name: WRPBR
|
||||
description: WRP area B address register
|
||||
byte_offset: 92
|
||||
fieldset: WRPBR
|
||||
- name: OEM1KEYR1
|
||||
description: OEM1 key register 1
|
||||
byte_offset: 112
|
||||
- name: OEM1KEYR2
|
||||
description: OEM1 key register 2
|
||||
byte_offset: 116
|
||||
- name: OEM2KEYR1
|
||||
description: OEM2 key register 1
|
||||
byte_offset: 120
|
||||
- name: OEM2KEYR2
|
||||
description: OEM2 key register 2
|
||||
byte_offset: 124
|
||||
- name: SECBBR
|
||||
description: secure block based register 1
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 128
|
||||
fieldset: BBR
|
||||
- name: SECHDPCR
|
||||
description: secure HDP control register
|
||||
byte_offset: 192
|
||||
fieldset: SECHDPCR
|
||||
- name: PRIFCFGR
|
||||
description: privilege configuration register
|
||||
byte_offset: 196
|
||||
fieldset: PRIFCFGR
|
||||
- name: PRIVBBR
|
||||
description: privilege block based register 1
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 208
|
||||
fieldset: BBR
|
||||
fieldset/ACR:
|
||||
description: access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: "Latency\r These bits represent the ratio between the AHB hclk1 clock period and the memory access time.\r Access to the bit can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r ...\r Note: Before entering Stop 1 mode software must set wait state latency to at least 1."
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: PRFTEN
|
||||
description: "Prefetch enable\r This bit enables the prefetch buffer in the embedded memory.\r This bit can be protected against unprivileged access by NSPRIV."
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: LPM
|
||||
description: "Low-power read mode\r This bit puts the memory in low-power read mode.\r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r This bit can’t be written when a program or erase operation is busy (BSY = 1) or when the write buffer is not empty (WDW = 1). Changing this bit while a program or erase operation is busy (BSY = 1) is rejected."
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: PDREQ
|
||||
description: "power-down mode request\r This bit requests to enter power-down mode. When enters power-down mode, this bit is cleared by hardware and the PDKEYR is locked.\r This bit is write-protected with PDKEYR. \r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: SLEEP_PD
|
||||
description: "memory power-down mode during Sleep mode\r This bit determines whether the memory is in power-down mode or Idle mode when the device is in Sleep mode.\r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r The must not be put in power-down while a program or an erase operation is ongoing."
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
fieldset/BBR:
|
||||
description: block based register
|
||||
fields:
|
||||
- name: BLOCK
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
fieldset/ECCR:
|
||||
description: ECC register
|
||||
fields:
|
||||
- name: ADDR_ECC
|
||||
description: "ECC fail address\r This field indicates which address is concerned by the ECC error correction or by the double ECC error detection. The address is given relative to base address, from offset 0x0<78>0000 to 0xF<78>FFF0.\r Note that bit 19 is reserved on STM32WBAxEx devices."
|
||||
bit_offset: 0
|
||||
bit_size: 20
|
||||
- name: SYSF_ECC
|
||||
description: "System memory ECC fail\r This bit indicates that the ECC error correction or double ECC error detection is located in the system memory."
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: ECCIE
|
||||
description: "ECC correction interrupt enable\r This bit enables the interrupt generation when the ECCC bit in the ECCR register is set."
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ECCC
|
||||
description: "ECC correction\r This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1."
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: ECCD
|
||||
description: "ECC detection\r This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1."
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/NSBOOTADD0R:
|
||||
description: boot address 0 register
|
||||
fields:
|
||||
- name: NSBOOTADD0
|
||||
description: "Non-secure boot base address 0\r This address is only used when TZEN = 0.\r The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state.\r Examples:\r NSBOOTADD0[24:0] = 0x0100000: Boot from memory (0x0800 0000)\r NSBOOTADD0[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000)\r NSBOOTADD0[24:0] = 0x0400200: Boot from SRAM2 on S-Bus (0x2001 0000)"
|
||||
bit_offset: 7
|
||||
bit_size: 25
|
||||
fieldset/NSBOOTADD1R:
|
||||
description: boot address 1 register
|
||||
fields:
|
||||
- name: NSBOOTADD1
|
||||
description: "Non-secure boot address 1\r This address is only used when TZEN = 0.\r The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. \r Examples:\r NSBOOTADD1[24:0] = 0x0100000: Boot from memory (0x0800 0000)\r NSBOOTADD1[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000)\r NSBOOTADD1[24:0] = 0x0400200: Boot from SRAM2 (0x2001 0000)"
|
||||
bit_offset: 7
|
||||
bit_size: 25
|
||||
fieldset/NSCR1:
|
||||
description: control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Non-secure programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Non-secure page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: "Non-secure mass erase\r This bit triggers the non-secure mass erase (all user pages) when set."
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PNB
|
||||
description: "Non-secure page number selection\r These bits select the page to erase.\r ...\r Note that bit 9 is reserved on STM32WBA5xEx devices."
|
||||
bit_offset: 3
|
||||
bit_size: 7
|
||||
- name: BWR
|
||||
description: "Non-secure burst write programming mode\r When set, this bit selects the burst write programming mode."
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: STRT
|
||||
description: "Non-secure operation start \r This bit triggers a non-secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR bit in NSSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in NSSR."
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: "Options modification start\r This bit triggers an option bytes erase and program operation when set. This bit is write-protected with OPTLOCK.. This bit is set only by software, and is cleared when the BSY bit is cleared in NSSR."
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: "Non-secure end of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in the NSSR is set to 1."
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: "Non-secure error interrupt enable\r This bit enables the interrupt generation when the OPERR bit in the NSSR is set to 1."
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: "Force the option byte loading\r When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. This bit is write-protected with OPTLOCK.\r Note: The LSE oscillator must be disabled, LSEON = 0 and LSERDY = 0, before starting OBL_LAUNCH."
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: "Option lock\r This bit is set only. When set, the NSCR1.OPTSRT and OBL_LAUNCH bits concerning user options write access is locked. This bit is cleared by hardware after detecting the unlock sequence in OPTKEYR. The NSCR1.LOCK bit must be cleared before doing the OPTKEYR unlock sequence.\r In case of an unsuccessful unlock operation, this bit remains set until the next reset."
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: "Non-secure lock\r This bit is set only.\r When set, the NSCR1 register write access is locked. This bit is cleared by hardware after detecting the unlock sequence in NSKEYR.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset."
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/NSCR2:
|
||||
description: control 2 register
|
||||
fields:
|
||||
- name: PS
|
||||
description: Program suspend request
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: ES
|
||||
description: Erase suspend request
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
fieldset/NSKEYR:
|
||||
description: key register
|
||||
fields:
|
||||
- name: NSKEY
|
||||
description: "memory non-secure key\r The following values must be written consecutively to unlock the NSCR1 register, allowing the memory non-secure programming/erasing operations:\r KEY1: 0x4567<36>0123\r KEY2: 0xCDEF<45>89AB"
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/NSSR:
|
||||
description: status register
|
||||
fields:
|
||||
- name: EOP
|
||||
description: "Non-secure end of operation\r This bit is set by hardware when one or more memory non-secure operation (program/erase) has been completed successfully. This bit is set only if the non-secure end of operation interrupts are enabled (EOPIE = 1 in NSCR1). This bit is cleared by writing<6E>1."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: "Non-secure operation error\r This bit is set by hardware when a memory non-secure operation (program/erase) completes unsuccessfully. This bit is set only if non-secure error interrupts are enabled (NSERRIE = 1). This bit is cleared by writing 1."
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PROGERR
|
||||
description: "Non-secure programming error\r This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1."
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: "Non-secure write protection error\r This bit is set by hardware when a non-secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: "Non-secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1."
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: "Non-secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1."
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: "Non-secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: OPTWERR
|
||||
description: "Option write error \r This bit is set by hardware when the options bytes are written with an invalid configuration or when modifying options in RDP level 2.. It is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: "Non-secure busy\r This indicates that a memory secure or non-secure operation is in progress. This bit is set at the beginning of a operation and reset when the operation finishes or when an error occurs."
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: WDW
|
||||
description: "Non-secure wait data to write\r This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory."
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: OEM1LOCK
|
||||
description: "OEM1 key RDP lock\r This bit indicates that the OEM1 key read during the OBL is not virgin. When set, the OEM1 key RDP lock mechanism is active."
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: OEM2LOCK
|
||||
description: "OEM2 key RDP lock\r This bit indicates that the OEM2 key read during the OBL is not virgin. When set, the OEM2 key RDP lock mechanism is active."
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: PD
|
||||
description: "in power-down mode\r This bit indicates that the memory is in power-down state. It is reset when is in normal mode or being awaken."
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
fieldset/OPSR:
|
||||
description: operation status register
|
||||
fields:
|
||||
- name: ADDR_OP
|
||||
description: "Interrupted operation address\r This field indicates which address in the memory was accessed when reset occurred. The address is given relative to the base address, from offset 0x0<78>0000 to 0xF<78>FFF0.\r Note that bit 19 is reserved on STM32WBAxEx devices."
|
||||
bit_offset: 0
|
||||
bit_size: 20
|
||||
- name: SYSF_OP
|
||||
description: "Operation in system memory interrupted\r This bit indicates that the reset occurred during an operation in the system memory."
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: CODE_OP
|
||||
description: "memory operation code\r This field indicates which memory operation has been interrupted by a system reset:"
|
||||
bit_offset: 29
|
||||
bit_size: 3
|
||||
enum: CODE_OP
|
||||
fieldset/OPTKEYR:
|
||||
description: option key register
|
||||
fields:
|
||||
- name: OPTKEY
|
||||
description: "Option byte key\r The LOCK bit in the NSCR1 must be cleared before doing the unlock sequence for OPTLOCK bit. The following values must be written consecutively to unlock the NSCR1.OPTSTRT and OBL_LAUNCH register bits concerning user option operations:\r KEY1: 0x0819<31>2A3B\r KEY2: 0x4C5D<35>6E7F"
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTR:
|
||||
description: option register
|
||||
fields:
|
||||
- name: RDP
|
||||
description: "Readout protection level\r Others: Level 1 (memories readout protection active)\r Note: Refer to Section<6F>7.6.2: Readout protection (RDP) for more details."
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
enum: RDP
|
||||
- name: BOR_LEV
|
||||
description: "BOR reset level\r These bits contain the V<sub>DD</sub> supply level threshold that activates/releases the reset."
|
||||
bit_offset: 8
|
||||
bit_size: 3
|
||||
enum: BOR_LEV
|
||||
- name: NRST_STOP
|
||||
description: Reset generation in Stop mode
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: NRST_STDBY
|
||||
description: Reset generation in Standby mode
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: SRAM1_RST
|
||||
description: SRAM1 erase upon system reset
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: IWDG_SW
|
||||
description: Independent watchdog enable selection
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: IWDG_STOP
|
||||
description: Independent watchdog counter freeze in Stop mode
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: IWDG_STDBY
|
||||
description: Independent watchdog counter freeze in Standby mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: WWDG_SW
|
||||
description: Window watchdog selection
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: SRAM2_PE
|
||||
description: SRAM2 parity check enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: SRAM2_RST
|
||||
description: SRAM2 erase when system reset
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: NSWBOOT0
|
||||
description: Software BOOT0
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: NBOOT0
|
||||
description: NBOOT0 option bit
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: TZEN
|
||||
description: Global TrustZone security enable
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/PDKEYR:
|
||||
description: power-down key register
|
||||
fields:
|
||||
- name: PDKEY1
|
||||
description: "power-down key\r The following values must be written consecutively to unlock the PDREQ bit in ACR:\r PDKEY_1: 0x0415<31>2637\r PDKEY_2: 0xFAFB<46>FCFD"
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PRIFCFGR:
|
||||
description: privilege configuration register
|
||||
fields:
|
||||
- name: SPRIV
|
||||
description: "Privileged protection for secure registers\r This bit is secure write protected. It can only be written by a secure privileged access when TrustZone is enabled (TZEN<45>=<3D>1)."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: NSPRIV
|
||||
description: Privileged protection for non-secure registers
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
fieldset/SECBOOTADD0R:
|
||||
description: secure boot address 0 register
|
||||
fields:
|
||||
- name: BOOT_LOCK
|
||||
description: "Boot lock\r This lock is only used when TZEN = 0.\r When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP regression level 1 to level 0."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SECBOOTADD0
|
||||
description: "Secure boot base address 0\r This address is only used when TZEN = 1.\r The secure boot memory address can be programmed to any address in the valid address range (see Table<6C>28: Boot space versus RDP protection) with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. \r Examples:\r SECBOOTADD0[24:0] = 0x018 0000: Boot from secure user memory (0x0C00 0000)\r SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS system memory (0x0FF8 0000)\r SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000)"
|
||||
bit_offset: 7
|
||||
bit_size: 25
|
||||
fieldset/SECCR1:
|
||||
description: secure control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Secure programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Secure page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: "Secure mass erase\r This bit triggers the secure mass erase (all user pages) when set."
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PNB
|
||||
description: "Secure page number selection\r These bits select the page to erase:\r ...\r Note that bit 9 is reserved on STM32WBA5xEx devices."
|
||||
bit_offset: 3
|
||||
bit_size: 7
|
||||
- name: BWR
|
||||
description: "Secure burst write programming mode\r When set, this bit selects the burst write programming mode."
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: STRT
|
||||
description: "Secure start \r This bit triggers a secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR in the SECSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in SECSR."
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: "Secure End of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in SECSR is set to 1."
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: "Secure error interrupt enable\r This bit enables the interrupt generation when the OPERR bit in SECSR is set to 1."
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: INV
|
||||
description: "memory security state invert\r This bit inverts the memory security state."
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: "Secure lock\r This bit is set only. When set, the SECCR1 register is locked. It is cleared by hardware after detecting the unlock sequence in SECKEYR register.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset."
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SECCR2:
|
||||
description: secure control 2 register
|
||||
fields:
|
||||
- name: PS
|
||||
description: Program suspend request
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: ES
|
||||
description: Erase suspend request
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
fieldset/SECHDPCR:
|
||||
description: secure HDP control register
|
||||
fields:
|
||||
- name: HDP_ACCDIS
|
||||
description: "Secure HDP area access disable \r When set, this bit is only cleared by a system reset."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
fieldset/SECKEYR:
|
||||
description: secure key register
|
||||
fields:
|
||||
- name: SECKEY
|
||||
description: "memory secure key\r The following values must be written consecutively to unlock the SECCR1 register, allowing the memory secure programming/erasing operations:\r KEY1: 0x4567<36>0123\r KEY2: 0xCDEF<45>89AB"
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SECSR:
|
||||
description: secure status register
|
||||
fields:
|
||||
- name: EOP
|
||||
description: "Secure end of operation\r This bit is set by hardware when one or more memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in SECCR1). This bit is cleared by writing<6E>1."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: "Secure operation error\r This bit is set by hardware when a memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1."
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PROGERR
|
||||
description: "Secure programming error\r This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1."
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: "Secure write protection error\r This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: "Secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1."
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: "Secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1."
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: "Secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: "Secure busy\r This bit indicates that a memory secure or non-secure operation is in progress. This is set on the beginning of a operation and reset when the operation finishes or when an error occurs."
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: WDW
|
||||
description: "Secure wait data to write\r This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory."
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
fieldset/SECWMR1:
|
||||
description: secure watermark register 1
|
||||
fields:
|
||||
- name: SECWM_PSTRT
|
||||
description: "Start page of secure area\r This field contains the first page of the secure area."
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: SECWM_PEND
|
||||
description: "End page of secure area\r This field contains the last page of the secure area."
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
fieldset/SECWMR2:
|
||||
description: secure watermark register 2
|
||||
fields:
|
||||
- name: HDP_PEND
|
||||
description: "End page of secure hide protection area\r This field contains the last page of the secure HDP area."
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
- name: HDPEN
|
||||
description: Secure Hide protection area enable
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/WRPAR:
|
||||
description: WRP area A address register
|
||||
fields:
|
||||
- name: WRPA_PSTRT
|
||||
description: "WPR area A start page\r This field contains the first page of the WPR area A.\r Note that bit 6 is reserved on STM32WBAxEx devices."
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: WRPA_PEND
|
||||
description: "WPR area A end page\r This field contains the last page of the WPR area A.\r Note that bit 22 is reserved on STM32WBAxEx devices."
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
- name: UNLOCK
|
||||
description: WPR area A unlock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/WRPBR:
|
||||
description: WRP area B address register
|
||||
fields:
|
||||
- name: WRPB_PSTRT
|
||||
description: "WRP area B start page\r This field contains the first page of the WRP area B.\r Note that bit 6 is reserved on STM32WBAxEx devices."
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: WRPB_PEND
|
||||
description: "WRP area B end page\r This field contains the last page of the WRP area B.\r Note that bit 22 is reserved on STM32WBAxEx devices."
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
- name: UNLOCK
|
||||
description: WPR area B unlock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
enum/BOR_LEV:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Level0
|
||||
description: BOR level 0 (reset level threshold around 1.7<EFBFBD>V)
|
||||
value: 0
|
||||
- name: Level1
|
||||
description: BOR level 1 (reset level threshold around 2.0<EFBFBD>V)
|
||||
value: 1
|
||||
- name: Level2
|
||||
description: BOR level 2 (reset level threshold around 2.2<EFBFBD>V)
|
||||
value: 2
|
||||
- name: Level3
|
||||
description: BOR level 3 (reset level threshold around 2.5<EFBFBD>V)
|
||||
value: 3
|
||||
- name: Level4
|
||||
description: BOR level 4 (reset level threshold around 2.8<EFBFBD>V)
|
||||
value: 4
|
||||
enum/CODE_OP:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: No operation interrupted by previous reset
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: Single write operation interrupted
|
||||
value: 1
|
||||
- name: B_0x2
|
||||
description: Burst write operation interrupted
|
||||
value: 2
|
||||
- name: B_0x3
|
||||
description: Page erase operation interrupted
|
||||
value: 3
|
||||
- name: B_0x4
|
||||
description: Reserved
|
||||
value: 4
|
||||
- name: B_0x5
|
||||
description: Mass erase operation interrupted
|
||||
value: 5
|
||||
- name: B_0x6
|
||||
description: Option change operation interrupted
|
||||
value: 6
|
||||
- name: B_0x7
|
||||
description: Reserved
|
||||
value: 7
|
||||
enum/RDP:
|
||||
bit_size: 8
|
||||
variants:
|
||||
- name: B_0x55
|
||||
description: Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1)
|
||||
value: 85
|
||||
- name: B_0xAA
|
||||
description: Level 0 (readout protection not active)
|
||||
value: 170
|
||||
- name: B_0xCC
|
||||
description: Level 2 (chip readout protection active)
|
||||
value: 204
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,179 +1,178 @@
|
||||
---
|
||||
block/FMAC:
|
||||
description: Filter math accelerator
|
||||
items:
|
||||
- name: X1BUFCFG
|
||||
description: X1 buffer configuration register
|
||||
byte_offset: 0
|
||||
fieldset: X1BUFCFG
|
||||
- name: X2BUFCFG
|
||||
description: X2 buffer configuration register
|
||||
byte_offset: 4
|
||||
fieldset: X2BUFCFG
|
||||
- name: YBUFCFG
|
||||
description: Y buffer configuration register
|
||||
byte_offset: 8
|
||||
fieldset: YBUFCFG
|
||||
- name: PARAM
|
||||
description: Parameter register
|
||||
byte_offset: 12
|
||||
fieldset: PARAM
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 16
|
||||
fieldset: CR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 20
|
||||
access: Read
|
||||
fieldset: SR
|
||||
- name: WDATA
|
||||
description: Write data register
|
||||
byte_offset: 24
|
||||
access: Write
|
||||
fieldset: WDATA
|
||||
- name: RDATA
|
||||
description: Read data register
|
||||
byte_offset: 28
|
||||
access: Read
|
||||
fieldset: RDATA
|
||||
- name: X1BUFCFG
|
||||
description: X1 buffer configuration register
|
||||
byte_offset: 0
|
||||
fieldset: X1BUFCFG
|
||||
- name: X2BUFCFG
|
||||
description: X2 buffer configuration register
|
||||
byte_offset: 4
|
||||
fieldset: X2BUFCFG
|
||||
- name: YBUFCFG
|
||||
description: Y buffer configuration register
|
||||
byte_offset: 8
|
||||
fieldset: YBUFCFG
|
||||
- name: PARAM
|
||||
description: Parameter register
|
||||
byte_offset: 12
|
||||
fieldset: PARAM
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 16
|
||||
fieldset: CR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 20
|
||||
access: Read
|
||||
fieldset: SR
|
||||
- name: WDATA
|
||||
description: Write data register
|
||||
byte_offset: 24
|
||||
access: Write
|
||||
fieldset: WDATA
|
||||
- name: RDATA
|
||||
description: Read data register
|
||||
byte_offset: 28
|
||||
access: Read
|
||||
fieldset: RDATA
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
- name: RIEN
|
||||
description: Enable read interrupt
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: WIEN
|
||||
description: Enable write interrupt
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: OVFLIEN
|
||||
description: Enable overflow error interrupts
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: UNFLIEN
|
||||
description: Enable underflow error interrupts
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: SATIEN
|
||||
description: Enable saturation error interrupts
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: DMAREN
|
||||
description: Enable DMA read channel requests
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: DMAWEN
|
||||
description: Enable DMA write channel requests
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: CLIPEN
|
||||
description: Enable clipping
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: RESET
|
||||
description: Reset FMAC unit
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: RIEN
|
||||
description: Enable read interrupt
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: WIEN
|
||||
description: Enable write interrupt
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: OVFLIEN
|
||||
description: Enable overflow error interrupts
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: UNFLIEN
|
||||
description: Enable underflow error interrupts
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: SATIEN
|
||||
description: Enable saturation error interrupts
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: DMAREN
|
||||
description: Enable DMA read channel requests
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: DMAWEN
|
||||
description: Enable DMA write channel requests
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: CLIPEN
|
||||
description: Enable clipping
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: RESET
|
||||
description: Reset FMAC unit
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
fieldset/PARAM:
|
||||
description: Parameter register
|
||||
fields:
|
||||
- name: P
|
||||
description: Input parameter P
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: Q
|
||||
description: Input parameter Q
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: R
|
||||
description: Input parameter R
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: FUNC
|
||||
description: Function
|
||||
bit_offset: 24
|
||||
bit_size: 7
|
||||
- name: START
|
||||
description: Enable execution
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
- name: P
|
||||
description: Input parameter P
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: Q
|
||||
description: Input parameter Q
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: R
|
||||
description: Input parameter R
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: FUNC
|
||||
description: Function
|
||||
bit_offset: 24
|
||||
bit_size: 7
|
||||
- name: START
|
||||
description: Enable execution
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/RDATA:
|
||||
description: Read data register
|
||||
fields:
|
||||
- name: RES
|
||||
description: Read data (contents of the Y output buffer at the address indicated by the READ pointer)
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: RES
|
||||
description: Read data (contents of the Y output buffer at the address indicated by the READ pointer)
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: YEMPTY
|
||||
description: Y buffer empty flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: X1FULL
|
||||
description: X1 buffer full flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: OVFL
|
||||
description: Overflow error flag
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: UNFL
|
||||
description: Underflow error flag
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: SAT
|
||||
description: Saturation error flag
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: YEMPTY
|
||||
description: Y buffer empty flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: X1FULL
|
||||
description: X1 buffer full flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: OVFL
|
||||
description: Overflow error flag
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: UNFL
|
||||
description: Underflow error flag
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: SAT
|
||||
description: Saturation error flag
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
fieldset/WDATA:
|
||||
description: Write data register
|
||||
fields:
|
||||
- name: WDATA
|
||||
description: Write data (write data are transferred to the address indicated by the write pointer)
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: WDATA
|
||||
description: Write data (write data are transferred to the address indicated by the write pointer)
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/X1BUFCFG:
|
||||
description: X1 buffer configuration register
|
||||
fields:
|
||||
- name: X1_BASE
|
||||
description: Base address of X1 buffer
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: X1_BUF_SIZE
|
||||
description: Allocated size of X1 buffer in 16-bit words
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: FULL_WM
|
||||
description: Watermark for buffer full flag
|
||||
bit_offset: 24
|
||||
bit_size: 2
|
||||
- name: X1_BASE
|
||||
description: Base address of X1 buffer
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: X1_BUF_SIZE
|
||||
description: Allocated size of X1 buffer in 16-bit words
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: FULL_WM
|
||||
description: Watermark for buffer full flag
|
||||
bit_offset: 24
|
||||
bit_size: 2
|
||||
fieldset/X2BUFCFG:
|
||||
description: X2 buffer configuration register
|
||||
fields:
|
||||
- name: X2_BASE
|
||||
description: Base address of X2 buffer
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: X2_BUF_SIZE
|
||||
description: Size of X2 buffer in 16-bit words
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: X2_BASE
|
||||
description: Base address of X2 buffer
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: X2_BUF_SIZE
|
||||
description: Size of X2 buffer in 16-bit words
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
fieldset/YBUFCFG:
|
||||
description: Y buffer configuration register
|
||||
fields:
|
||||
- name: Y_BASE
|
||||
description: Base address of Y buffer
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: Y_BUF_SIZE
|
||||
description: Size of Y buffer in 16-bit words
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: EMPTY_WM
|
||||
description: Watermark for buffer empty flag
|
||||
bit_offset: 24
|
||||
bit_size: 2
|
||||
- name: Y_BASE
|
||||
description: Base address of Y buffer
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: Y_BUF_SIZE
|
||||
description: Size of Y buffer in 16-bit words
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: EMPTY_WM
|
||||
description: Watermark for buffer empty flag
|
||||
bit_offset: 24
|
||||
bit_size: 2
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,224 +1,223 @@
|
||||
---
|
||||
block/FSMC:
|
||||
description: Flexible static memory controller
|
||||
items:
|
||||
- name: BCR
|
||||
description: SRAM/NOR-Flash chip-select control register 1-4
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
byte_offset: 0
|
||||
fieldset: BCR
|
||||
- name: BTR
|
||||
description: SRAM/NOR-Flash chip-select timing register 1-4
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
byte_offset: 4
|
||||
fieldset: BTR
|
||||
- name: BWTR
|
||||
description: SRAM/NOR-Flash write timing registers 1-4
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
byte_offset: 260
|
||||
fieldset: BWTR
|
||||
- name: BCR
|
||||
description: SRAM/NOR-Flash chip-select control register 1-4
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
byte_offset: 0
|
||||
fieldset: BCR
|
||||
- name: BTR
|
||||
description: SRAM/NOR-Flash chip-select timing register 1-4
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
byte_offset: 4
|
||||
fieldset: BTR
|
||||
- name: BWTR
|
||||
description: SRAM/NOR-Flash write timing registers 1-4
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
byte_offset: 260
|
||||
fieldset: BWTR
|
||||
fieldset/BCR:
|
||||
description: SRAM/NOR-Flash chip-select control register
|
||||
fields:
|
||||
- name: MBKEN
|
||||
description: Memory bank enable bit
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: MUXEN
|
||||
description: Address/data multiplexing enable bit
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MTYP
|
||||
description: Memory type
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
enum: MTYP
|
||||
- name: MWID
|
||||
description: Memory data bus width
|
||||
bit_offset: 4
|
||||
bit_size: 2
|
||||
enum: MWID
|
||||
- name: FACCEN
|
||||
description: Flash access enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: BURSTEN
|
||||
description: Burst enable bit
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: WAITPOL
|
||||
description: Wait signal polarity bit
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: WAITPOL
|
||||
- name: WRAPMOD
|
||||
description: WRAPMOD
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WAITCFG
|
||||
description: Wait timing configuration
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
enum: WAITCFG
|
||||
- name: WREN
|
||||
description: Write enable bit
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: WAITEN
|
||||
description: Wait enable bit
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: EXTMOD
|
||||
description: Extended mode enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: ASYNCWAIT
|
||||
description: Wait signal during asynchronous transfers
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: CPSIZE
|
||||
description: CRAM page size
|
||||
bit_offset: 16
|
||||
bit_size: 3
|
||||
enum: CPSIZE
|
||||
- name: CBURSTRW
|
||||
description: Write burst enable
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: MBKEN
|
||||
description: Memory bank enable bit
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: MUXEN
|
||||
description: Address/data multiplexing enable bit
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MTYP
|
||||
description: Memory type
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
enum: MTYP
|
||||
- name: MWID
|
||||
description: Memory data bus width
|
||||
bit_offset: 4
|
||||
bit_size: 2
|
||||
enum: MWID
|
||||
- name: FACCEN
|
||||
description: Flash access enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: BURSTEN
|
||||
description: Burst enable bit
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: WAITPOL
|
||||
description: Wait signal polarity bit
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: WAITPOL
|
||||
- name: WRAPMOD
|
||||
description: WRAPMOD
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WAITCFG
|
||||
description: Wait timing configuration
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
enum: WAITCFG
|
||||
- name: WREN
|
||||
description: Write enable bit
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: WAITEN
|
||||
description: Wait enable bit
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: EXTMOD
|
||||
description: Extended mode enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: ASYNCWAIT
|
||||
description: Wait signal during asynchronous transfers
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: CPSIZE
|
||||
description: CRAM page size
|
||||
bit_offset: 16
|
||||
bit_size: 3
|
||||
enum: CPSIZE
|
||||
- name: CBURSTRW
|
||||
description: Write burst enable
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
fieldset/BTR:
|
||||
description: SRAM/NOR-Flash chip-select timing register
|
||||
fields:
|
||||
- name: ADDSET
|
||||
description: Address setup phase duration
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: ADDHLD
|
||||
description: Address-hold phase duration
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
- name: DATAST
|
||||
description: Data-phase duration
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: BUSTURN
|
||||
description: Bus turnaround phase duration
|
||||
bit_offset: 16
|
||||
bit_size: 4
|
||||
- name: CLKDIV
|
||||
description: Clock divide ratio (for FMC_CLK signal)
|
||||
bit_offset: 20
|
||||
bit_size: 4
|
||||
- name: DATLAT
|
||||
description: Data latency for synchronous memory
|
||||
bit_offset: 24
|
||||
bit_size: 4
|
||||
- name: ACCMOD
|
||||
description: Access mode
|
||||
bit_offset: 28
|
||||
bit_size: 2
|
||||
enum: ACCMOD
|
||||
- name: ADDSET
|
||||
description: Address setup phase duration
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: ADDHLD
|
||||
description: Address-hold phase duration
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
- name: DATAST
|
||||
description: Data-phase duration
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: BUSTURN
|
||||
description: Bus turnaround phase duration
|
||||
bit_offset: 16
|
||||
bit_size: 4
|
||||
- name: CLKDIV
|
||||
description: Clock divide ratio (for FMC_CLK signal)
|
||||
bit_offset: 20
|
||||
bit_size: 4
|
||||
- name: DATLAT
|
||||
description: Data latency for synchronous memory
|
||||
bit_offset: 24
|
||||
bit_size: 4
|
||||
- name: ACCMOD
|
||||
description: Access mode
|
||||
bit_offset: 28
|
||||
bit_size: 2
|
||||
enum: ACCMOD
|
||||
fieldset/BWTR:
|
||||
description: SRAM/NOR-Flash write timing registers
|
||||
fields:
|
||||
- name: ADDSET
|
||||
description: Address setup phase duration
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: ADDHLD
|
||||
description: Address-hold phase duration
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
- name: DATAST
|
||||
description: Data-phase duration
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: BUSTURN
|
||||
description: Bus turnaround phase duration
|
||||
bit_offset: 16
|
||||
bit_size: 4
|
||||
- name: ACCMOD
|
||||
description: Access mode
|
||||
bit_offset: 28
|
||||
bit_size: 2
|
||||
enum: ACCMOD
|
||||
- name: ADDSET
|
||||
description: Address setup phase duration
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: ADDHLD
|
||||
description: Address-hold phase duration
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
- name: DATAST
|
||||
description: Data-phase duration
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: BUSTURN
|
||||
description: Bus turnaround phase duration
|
||||
bit_offset: 16
|
||||
bit_size: 4
|
||||
- name: ACCMOD
|
||||
description: Access mode
|
||||
bit_offset: 28
|
||||
bit_size: 2
|
||||
enum: ACCMOD
|
||||
enum/ACCMOD:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: A
|
||||
description: Access mode A
|
||||
value: 0
|
||||
- name: B
|
||||
description: Access mode B
|
||||
value: 1
|
||||
- name: C
|
||||
description: Access mode C
|
||||
value: 2
|
||||
- name: D
|
||||
description: Access mode D
|
||||
value: 3
|
||||
- name: A
|
||||
description: Access mode A
|
||||
value: 0
|
||||
- name: B
|
||||
description: Access mode B
|
||||
value: 1
|
||||
- name: C
|
||||
description: Access mode C
|
||||
value: 2
|
||||
- name: D
|
||||
description: Access mode D
|
||||
value: 3
|
||||
enum/CPSIZE:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: NoBurstSplit
|
||||
description: No burst split when crossing page boundary
|
||||
value: 0
|
||||
- name: Bytes128
|
||||
description: 128 bytes CRAM page size
|
||||
value: 1
|
||||
- name: Bytes256
|
||||
description: 256 bytes CRAM page size
|
||||
value: 2
|
||||
- name: Bytes512
|
||||
description: 512 bytes CRAM page size
|
||||
value: 3
|
||||
- name: Bytes1024
|
||||
description: 1024 bytes CRAM page size
|
||||
value: 4
|
||||
- name: NoBurstSplit
|
||||
description: No burst split when crossing page boundary
|
||||
value: 0
|
||||
- name: Bytes128
|
||||
description: 128 bytes CRAM page size
|
||||
value: 1
|
||||
- name: Bytes256
|
||||
description: 256 bytes CRAM page size
|
||||
value: 2
|
||||
- name: Bytes512
|
||||
description: 512 bytes CRAM page size
|
||||
value: 3
|
||||
- name: Bytes1024
|
||||
description: 1024 bytes CRAM page size
|
||||
value: 4
|
||||
enum/MTYP:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: SRAM
|
||||
description: SRAM memory type
|
||||
value: 0
|
||||
- name: PSRAM
|
||||
description: PSRAM (CRAM) memory type
|
||||
value: 1
|
||||
- name: Flash
|
||||
description: NOR Flash/OneNAND Flash
|
||||
value: 2
|
||||
- name: SRAM
|
||||
description: SRAM memory type
|
||||
value: 0
|
||||
- name: PSRAM
|
||||
description: PSRAM (CRAM) memory type
|
||||
value: 1
|
||||
- name: Flash
|
||||
description: NOR Flash/OneNAND Flash
|
||||
value: 2
|
||||
enum/MWID:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Bits8
|
||||
description: Memory data bus width 8 bits
|
||||
value: 0
|
||||
- name: Bits16
|
||||
description: Memory data bus width 16 bits
|
||||
value: 1
|
||||
- name: Bits32
|
||||
description: Memory data bus width 32 bits
|
||||
value: 2
|
||||
- name: Bits8
|
||||
description: Memory data bus width 8 bits
|
||||
value: 0
|
||||
- name: Bits16
|
||||
description: Memory data bus width 16 bits
|
||||
value: 1
|
||||
- name: Bits32
|
||||
description: Memory data bus width 32 bits
|
||||
value: 2
|
||||
enum/WAITCFG:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: BeforeWaitState
|
||||
description: NWAIT signal is active one data cycle before wait state
|
||||
value: 0
|
||||
- name: DuringWaitState
|
||||
description: NWAIT signal is active during wait state
|
||||
value: 1
|
||||
- name: BeforeWaitState
|
||||
description: NWAIT signal is active one data cycle before wait state
|
||||
value: 0
|
||||
- name: DuringWaitState
|
||||
description: NWAIT signal is active during wait state
|
||||
value: 1
|
||||
enum/WAITPOL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: ActiveLow
|
||||
description: NWAIT active low
|
||||
value: 0
|
||||
- name: ActiveHigh
|
||||
description: NWAIT active high
|
||||
value: 1
|
||||
- name: ActiveLow
|
||||
description: NWAIT active low
|
||||
value: 0
|
||||
- name: ActiveHigh
|
||||
description: NWAIT active high
|
||||
value: 1
|
||||
|
||||
@ -1,433 +1,432 @@
|
||||
---
|
||||
block/FSMC:
|
||||
description: Flexible static memory controller
|
||||
items:
|
||||
- name: BCR
|
||||
description: SRAM/NOR-Flash chip-select control register 1-4
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
byte_offset: 0
|
||||
fieldset: BCR
|
||||
- name: BTR
|
||||
description: SRAM/NOR-Flash chip-select timing register 1-4
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
byte_offset: 4
|
||||
fieldset: BTR
|
||||
- name: PCR
|
||||
description: PC Card/NAND Flash control register 2-4
|
||||
array:
|
||||
len: 3
|
||||
stride: 32
|
||||
byte_offset: 96
|
||||
fieldset: PCR
|
||||
- name: SR
|
||||
description: FIFO status and interrupt register 2-4
|
||||
array:
|
||||
len: 3
|
||||
stride: 32
|
||||
byte_offset: 100
|
||||
fieldset: SR
|
||||
- name: PMEM
|
||||
description: Common memory space timing register 2-4
|
||||
array:
|
||||
len: 3
|
||||
stride: 32
|
||||
byte_offset: 104
|
||||
fieldset: PMEM
|
||||
- name: PATT
|
||||
description: Attribute memory space timing register 2-4
|
||||
array:
|
||||
len: 3
|
||||
stride: 32
|
||||
byte_offset: 108
|
||||
fieldset: PATT
|
||||
- name: ECCR
|
||||
description: ECC result register 2-3
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 116
|
||||
access: Read
|
||||
fieldset: ECCR
|
||||
- name: PIO4
|
||||
description: I/O space timing register 4
|
||||
byte_offset: 176
|
||||
fieldset: PIO4
|
||||
- name: BWTR
|
||||
description: SRAM/NOR-Flash write timing registers 1-4
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
byte_offset: 260
|
||||
fieldset: BWTR
|
||||
- name: BCR
|
||||
description: SRAM/NOR-Flash chip-select control register 1-4
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
byte_offset: 0
|
||||
fieldset: BCR
|
||||
- name: BTR
|
||||
description: SRAM/NOR-Flash chip-select timing register 1-4
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
byte_offset: 4
|
||||
fieldset: BTR
|
||||
- name: PCR
|
||||
description: PC Card/NAND Flash control register 2-4
|
||||
array:
|
||||
len: 3
|
||||
stride: 32
|
||||
byte_offset: 96
|
||||
fieldset: PCR
|
||||
- name: SR
|
||||
description: FIFO status and interrupt register 2-4
|
||||
array:
|
||||
len: 3
|
||||
stride: 32
|
||||
byte_offset: 100
|
||||
fieldset: SR
|
||||
- name: PMEM
|
||||
description: Common memory space timing register 2-4
|
||||
array:
|
||||
len: 3
|
||||
stride: 32
|
||||
byte_offset: 104
|
||||
fieldset: PMEM
|
||||
- name: PATT
|
||||
description: Attribute memory space timing register 2-4
|
||||
array:
|
||||
len: 3
|
||||
stride: 32
|
||||
byte_offset: 108
|
||||
fieldset: PATT
|
||||
- name: ECCR
|
||||
description: ECC result register 2-3
|
||||
array:
|
||||
len: 2
|
||||
stride: 32
|
||||
byte_offset: 116
|
||||
access: Read
|
||||
fieldset: ECCR
|
||||
- name: PIO4
|
||||
description: I/O space timing register 4
|
||||
byte_offset: 176
|
||||
fieldset: PIO4
|
||||
- name: BWTR
|
||||
description: SRAM/NOR-Flash write timing registers 1-4
|
||||
array:
|
||||
len: 4
|
||||
stride: 8
|
||||
byte_offset: 260
|
||||
fieldset: BWTR
|
||||
fieldset/BCR:
|
||||
description: SRAM/NOR-Flash chip-select control register
|
||||
fields:
|
||||
- name: MBKEN
|
||||
description: Memory bank enable bit
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: MUXEN
|
||||
description: Address/data multiplexing enable bit
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MTYP
|
||||
description: Memory type
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
enum: MTYP
|
||||
- name: MWID
|
||||
description: Memory data bus width
|
||||
bit_offset: 4
|
||||
bit_size: 2
|
||||
enum: MWID
|
||||
- name: FACCEN
|
||||
description: Flash access enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: BURSTEN
|
||||
description: Burst enable bit
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: WAITPOL
|
||||
description: Wait signal polarity bit
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: WAITPOL
|
||||
- name: WRAPMOD
|
||||
description: WRAPMOD
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WAITCFG
|
||||
description: Wait timing configuration
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
enum: WAITCFG
|
||||
- name: WREN
|
||||
description: Write enable bit
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: WAITEN
|
||||
description: Wait enable bit
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: EXTMOD
|
||||
description: Extended mode enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: ASYNCWAIT
|
||||
description: Wait signal during asynchronous transfers
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: CPSIZE
|
||||
description: CRAM page size
|
||||
bit_offset: 16
|
||||
bit_size: 3
|
||||
enum: CPSIZE
|
||||
- name: CBURSTRW
|
||||
description: Write burst enable
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: MBKEN
|
||||
description: Memory bank enable bit
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: MUXEN
|
||||
description: Address/data multiplexing enable bit
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MTYP
|
||||
description: Memory type
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
enum: MTYP
|
||||
- name: MWID
|
||||
description: Memory data bus width
|
||||
bit_offset: 4
|
||||
bit_size: 2
|
||||
enum: MWID
|
||||
- name: FACCEN
|
||||
description: Flash access enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: BURSTEN
|
||||
description: Burst enable bit
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: WAITPOL
|
||||
description: Wait signal polarity bit
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: WAITPOL
|
||||
- name: WRAPMOD
|
||||
description: WRAPMOD
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WAITCFG
|
||||
description: Wait timing configuration
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
enum: WAITCFG
|
||||
- name: WREN
|
||||
description: Write enable bit
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: WAITEN
|
||||
description: Wait enable bit
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: EXTMOD
|
||||
description: Extended mode enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: ASYNCWAIT
|
||||
description: Wait signal during asynchronous transfers
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: CPSIZE
|
||||
description: CRAM page size
|
||||
bit_offset: 16
|
||||
bit_size: 3
|
||||
enum: CPSIZE
|
||||
- name: CBURSTRW
|
||||
description: Write burst enable
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
fieldset/BTR:
|
||||
description: SRAM/NOR-Flash chip-select timing register
|
||||
fields:
|
||||
- name: ADDSET
|
||||
description: Address setup phase duration
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: ADDHLD
|
||||
description: Address-hold phase duration
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
- name: DATAST
|
||||
description: Data-phase duration
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: BUSTURN
|
||||
description: Bus turnaround phase duration
|
||||
bit_offset: 16
|
||||
bit_size: 4
|
||||
- name: CLKDIV
|
||||
description: Clock divide ratio (for FMC_CLK signal)
|
||||
bit_offset: 20
|
||||
bit_size: 4
|
||||
- name: DATLAT
|
||||
description: Data latency for synchronous memory
|
||||
bit_offset: 24
|
||||
bit_size: 4
|
||||
- name: ACCMOD
|
||||
description: Access mode
|
||||
bit_offset: 28
|
||||
bit_size: 2
|
||||
enum: ACCMOD
|
||||
- name: ADDSET
|
||||
description: Address setup phase duration
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: ADDHLD
|
||||
description: Address-hold phase duration
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
- name: DATAST
|
||||
description: Data-phase duration
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: BUSTURN
|
||||
description: Bus turnaround phase duration
|
||||
bit_offset: 16
|
||||
bit_size: 4
|
||||
- name: CLKDIV
|
||||
description: Clock divide ratio (for FMC_CLK signal)
|
||||
bit_offset: 20
|
||||
bit_size: 4
|
||||
- name: DATLAT
|
||||
description: Data latency for synchronous memory
|
||||
bit_offset: 24
|
||||
bit_size: 4
|
||||
- name: ACCMOD
|
||||
description: Access mode
|
||||
bit_offset: 28
|
||||
bit_size: 2
|
||||
enum: ACCMOD
|
||||
fieldset/BWTR:
|
||||
description: SRAM/NOR-Flash write timing registers
|
||||
fields:
|
||||
- name: ADDSET
|
||||
description: Address setup phase duration
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: ADDHLD
|
||||
description: Address-hold phase duration
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
- name: DATAST
|
||||
description: Data-phase duration
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: BUSTURN
|
||||
description: Bus turnaround phase duration
|
||||
bit_offset: 16
|
||||
bit_size: 4
|
||||
- name: ACCMOD
|
||||
description: Access mode
|
||||
bit_offset: 28
|
||||
bit_size: 2
|
||||
enum: ACCMOD
|
||||
- name: ADDSET
|
||||
description: Address setup phase duration
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: ADDHLD
|
||||
description: Address-hold phase duration
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
- name: DATAST
|
||||
description: Data-phase duration
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: BUSTURN
|
||||
description: Bus turnaround phase duration
|
||||
bit_offset: 16
|
||||
bit_size: 4
|
||||
- name: ACCMOD
|
||||
description: Access mode
|
||||
bit_offset: 28
|
||||
bit_size: 2
|
||||
enum: ACCMOD
|
||||
fieldset/ECCR:
|
||||
description: ECC result register
|
||||
fields:
|
||||
- name: ECC
|
||||
description: ECC computation result value
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
- name: ECC
|
||||
description: ECC computation result value
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PATT:
|
||||
description: Attribute memory space timing register
|
||||
fields:
|
||||
- name: ATTSET
|
||||
description: Attribute memory setup time
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: ATTWAIT
|
||||
description: Attribute memory wait time
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: ATTHOLD
|
||||
description: Attribute memory hold time
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: ATTHIZ
|
||||
description: Attribute memory data bus Hi-Z time
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
- name: ATTSET
|
||||
description: Attribute memory setup time
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: ATTWAIT
|
||||
description: Attribute memory wait time
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: ATTHOLD
|
||||
description: Attribute memory hold time
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: ATTHIZ
|
||||
description: Attribute memory data bus Hi-Z time
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
fieldset/PCR:
|
||||
description: PC Card/NAND Flash control register
|
||||
fields:
|
||||
- name: PWAITEN
|
||||
description: Wait feature enable bit
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PBKEN
|
||||
description: NAND Flash memory bank enable bit
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PTYP
|
||||
description: Memory type
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
enum: PTYP
|
||||
- name: PWID
|
||||
description: Data bus width
|
||||
bit_offset: 4
|
||||
bit_size: 2
|
||||
enum: PWID
|
||||
- name: ECCEN
|
||||
description: ECC computation logic enable bit
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TCLR
|
||||
description: CLE to RE delay
|
||||
bit_offset: 9
|
||||
bit_size: 4
|
||||
- name: TAR
|
||||
description: ALE to RE delay
|
||||
bit_offset: 13
|
||||
bit_size: 4
|
||||
- name: ECCPS
|
||||
description: ECC page size
|
||||
bit_offset: 17
|
||||
bit_size: 3
|
||||
enum: ECCPS
|
||||
- name: PWAITEN
|
||||
description: Wait feature enable bit
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PBKEN
|
||||
description: NAND Flash memory bank enable bit
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PTYP
|
||||
description: Memory type
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
enum: PTYP
|
||||
- name: PWID
|
||||
description: Data bus width
|
||||
bit_offset: 4
|
||||
bit_size: 2
|
||||
enum: PWID
|
||||
- name: ECCEN
|
||||
description: ECC computation logic enable bit
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TCLR
|
||||
description: CLE to RE delay
|
||||
bit_offset: 9
|
||||
bit_size: 4
|
||||
- name: TAR
|
||||
description: ALE to RE delay
|
||||
bit_offset: 13
|
||||
bit_size: 4
|
||||
- name: ECCPS
|
||||
description: ECC page size
|
||||
bit_offset: 17
|
||||
bit_size: 3
|
||||
enum: ECCPS
|
||||
fieldset/PIO4:
|
||||
description: I/O space timing register 4
|
||||
fields:
|
||||
- name: IOSETx
|
||||
description: IOSETx
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: IOWAITx
|
||||
description: IOWAITx
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: IOHOLDx
|
||||
description: IOHOLDx
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: IOHIZx
|
||||
description: IOHIZx
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
- name: IOSETx
|
||||
description: IOSETx
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: IOWAITx
|
||||
description: IOWAITx
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: IOHOLDx
|
||||
description: IOHOLDx
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: IOHIZx
|
||||
description: IOHIZx
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
fieldset/PMEM:
|
||||
description: Common memory space timing register
|
||||
fields:
|
||||
- name: MEMSET
|
||||
description: Common memory x setup time
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: MEMWAIT
|
||||
description: Common memory wait time
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: MEMHOLD
|
||||
description: Common memory hold time
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: MEMHIZ
|
||||
description: Common memory x data bus Hi-Z time
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
- name: MEMSET
|
||||
description: Common memory x setup time
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: MEMWAIT
|
||||
description: Common memory wait time
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: MEMHOLD
|
||||
description: Common memory hold time
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: MEMHIZ
|
||||
description: Common memory x data bus Hi-Z time
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
fieldset/SR:
|
||||
description: FIFO status and interrupt register
|
||||
fields:
|
||||
- name: IRS
|
||||
description: Interrupt rising edge status
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: ILS
|
||||
description: Interrupt high-level status
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: IFS
|
||||
description: Interrupt falling edge status
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: IREN
|
||||
description: Interrupt rising edge detection enable bit
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: ILEN
|
||||
description: Interrupt high-level detection enable bit
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: IFEN
|
||||
description: Interrupt falling edge detection enable bit
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: FEMPT
|
||||
description: FIFO empty status
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: IRS
|
||||
description: Interrupt rising edge status
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: ILS
|
||||
description: Interrupt high-level status
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: IFS
|
||||
description: Interrupt falling edge status
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: IREN
|
||||
description: Interrupt rising edge detection enable bit
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: ILEN
|
||||
description: Interrupt high-level detection enable bit
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: IFEN
|
||||
description: Interrupt falling edge detection enable bit
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: FEMPT
|
||||
description: FIFO empty status
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
enum/ACCMOD:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: A
|
||||
description: Access mode A
|
||||
value: 0
|
||||
- name: B
|
||||
description: Access mode B
|
||||
value: 1
|
||||
- name: C
|
||||
description: Access mode C
|
||||
value: 2
|
||||
- name: D
|
||||
description: Access mode D
|
||||
value: 3
|
||||
- name: A
|
||||
description: Access mode A
|
||||
value: 0
|
||||
- name: B
|
||||
description: Access mode B
|
||||
value: 1
|
||||
- name: C
|
||||
description: Access mode C
|
||||
value: 2
|
||||
- name: D
|
||||
description: Access mode D
|
||||
value: 3
|
||||
enum/CPSIZE:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: NoBurstSplit
|
||||
description: No burst split when crossing page boundary
|
||||
value: 0
|
||||
- name: Bytes128
|
||||
description: 128 bytes CRAM page size
|
||||
value: 1
|
||||
- name: Bytes256
|
||||
description: 256 bytes CRAM page size
|
||||
value: 2
|
||||
- name: Bytes512
|
||||
description: 512 bytes CRAM page size
|
||||
value: 3
|
||||
- name: Bytes1024
|
||||
description: 1024 bytes CRAM page size
|
||||
value: 4
|
||||
- name: NoBurstSplit
|
||||
description: No burst split when crossing page boundary
|
||||
value: 0
|
||||
- name: Bytes128
|
||||
description: 128 bytes CRAM page size
|
||||
value: 1
|
||||
- name: Bytes256
|
||||
description: 256 bytes CRAM page size
|
||||
value: 2
|
||||
- name: Bytes512
|
||||
description: 512 bytes CRAM page size
|
||||
value: 3
|
||||
- name: Bytes1024
|
||||
description: 1024 bytes CRAM page size
|
||||
value: 4
|
||||
enum/ECCPS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Bytes256
|
||||
description: ECC page size 256 bytes
|
||||
value: 0
|
||||
- name: Bytes512
|
||||
description: ECC page size 512 bytes
|
||||
value: 1
|
||||
- name: Bytes1024
|
||||
description: ECC page size 1024 bytes
|
||||
value: 2
|
||||
- name: Bytes2048
|
||||
description: ECC page size 2048 bytes
|
||||
value: 3
|
||||
- name: Bytes4096
|
||||
description: ECC page size 4096 bytes
|
||||
value: 4
|
||||
- name: Bytes8192
|
||||
description: ECC page size 8192 bytes
|
||||
value: 5
|
||||
- name: Bytes256
|
||||
description: ECC page size 256 bytes
|
||||
value: 0
|
||||
- name: Bytes512
|
||||
description: ECC page size 512 bytes
|
||||
value: 1
|
||||
- name: Bytes1024
|
||||
description: ECC page size 1024 bytes
|
||||
value: 2
|
||||
- name: Bytes2048
|
||||
description: ECC page size 2048 bytes
|
||||
value: 3
|
||||
- name: Bytes4096
|
||||
description: ECC page size 4096 bytes
|
||||
value: 4
|
||||
- name: Bytes8192
|
||||
description: ECC page size 8192 bytes
|
||||
value: 5
|
||||
enum/MTYP:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: SRAM
|
||||
description: SRAM memory type
|
||||
value: 0
|
||||
- name: PSRAM
|
||||
description: PSRAM (CRAM) memory type
|
||||
value: 1
|
||||
- name: Flash
|
||||
description: NOR Flash/OneNAND Flash
|
||||
value: 2
|
||||
- name: SRAM
|
||||
description: SRAM memory type
|
||||
value: 0
|
||||
- name: PSRAM
|
||||
description: PSRAM (CRAM) memory type
|
||||
value: 1
|
||||
- name: Flash
|
||||
description: NOR Flash/OneNAND Flash
|
||||
value: 2
|
||||
enum/MWID:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Bits8
|
||||
description: Memory data bus width 8 bits
|
||||
value: 0
|
||||
- name: Bits16
|
||||
description: Memory data bus width 16 bits
|
||||
value: 1
|
||||
- name: Bits32
|
||||
description: Memory data bus width 32 bits
|
||||
value: 2
|
||||
- name: Bits8
|
||||
description: Memory data bus width 8 bits
|
||||
value: 0
|
||||
- name: Bits16
|
||||
description: Memory data bus width 16 bits
|
||||
value: 1
|
||||
- name: Bits32
|
||||
description: Memory data bus width 32 bits
|
||||
value: 2
|
||||
enum/PTYP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NANDFlash
|
||||
description: NAND Flash
|
||||
value: 1
|
||||
- name: NANDFlash
|
||||
description: NAND Flash
|
||||
value: 1
|
||||
enum/PWID:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Bits8
|
||||
description: External memory device width 8 bits
|
||||
value: 0
|
||||
- name: Bits16
|
||||
description: External memory device width 16 bits
|
||||
value: 1
|
||||
- name: Bits8
|
||||
description: External memory device width 8 bits
|
||||
value: 0
|
||||
- name: Bits16
|
||||
description: External memory device width 16 bits
|
||||
value: 1
|
||||
enum/WAITCFG:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: BeforeWaitState
|
||||
description: NWAIT signal is active one data cycle before wait state
|
||||
value: 0
|
||||
- name: DuringWaitState
|
||||
description: NWAIT signal is active during wait state
|
||||
value: 1
|
||||
- name: BeforeWaitState
|
||||
description: NWAIT signal is active one data cycle before wait state
|
||||
value: 0
|
||||
- name: DuringWaitState
|
||||
description: NWAIT signal is active during wait state
|
||||
value: 1
|
||||
enum/WAITPOL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: ActiveLow
|
||||
description: NWAIT active low
|
||||
value: 0
|
||||
- name: ActiveHigh
|
||||
description: NWAIT active high
|
||||
value: 1
|
||||
- name: ActiveLow
|
||||
description: NWAIT active low
|
||||
value: 0
|
||||
- name: ActiveHigh
|
||||
description: NWAIT active high
|
||||
value: 1
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user