diff --git a/.github/ci/build.sh b/.github/ci/build.sh index bdf7490..c667adc 100755 --- a/.github/ci/build.sh +++ b/.github/ci/build.sh @@ -2,7 +2,7 @@ ## on push branch~=gh-readonly-queue/main/.* ## on pull_request -set -euo pipefail +set -euxo pipefail export RUSTUP_HOME=/ci/cache/rustup export CARGO_HOME=/ci/cache/cargo @@ -13,4 +13,35 @@ hashtime save /ci/cache/filetime.json cargo fmt -- --check +# clone stm32-data-generated at the merge base +# so the diff will show this PR's effect +git remote add upstream https://github.com/embassy-rs/stm32-data +git fetch --depth 1 upstream main +git clone --depth 1 --branch stm32-data-$(git merge-base HEAD upstream/main) https://github.com/embassy-rs/stm32-data-generated/ build + ./d ci + +# upload diff +( + cd build + git add . + git diff --staged --color data | aha --black > /ci/artifacts/diff.html +) + +# upload generated data to a fake git repo at +# https://ci.embassy.dev/jobs/$ID/artifacts/generated.git +# this allows testing the corresponding embassy-stm32 PR before merging the stm32-data one. +( + cd build + rm -rf .git + git init + git add . + git commit -m 'generated' + git gc # makes cloning faster + git update-server-info # generate .git/info/refs + mv .git /ci/artifacts/generated.git +) + +cat > /ci/comment.md <DD voltage configuration bit.\r This bit can be set only with VDD below 2.7�V." - bit_offset: 16 - bit_size: 1 - enum: OPTSR_IO_VDD_HSLV - - name: IO_VDDIO2_HSLV - description: "High-speed IO at low VDDIO2 voltage configuration bit.\r This bit can be set only with VDDIO2 below 2.7�V." - bit_offset: 17 - bit_size: 1 - enum: OPTSR_IO_VDDIO_HSLV - - name: IWDG_STOP - description: "IWDG Stop mode freeze option status bit\r When set the independent watchdog IWDG is in system Stop mode." - bit_offset: 20 - bit_size: 1 - enum: OPTSR_IWDG_STOP - - name: IWDG_STDBY - description: "IWDG Standby mode freeze option status bit\r When set the independent watchdog IWDG is frozen in system Standby mode." - bit_offset: 21 - bit_size: 1 - enum: OPTSR_IWDG_STDBY - - name: BOOT_UBE - description: "Available only on cryptography enabled devices.\r Unique boot entry control, selects either ST or OEM iRoT for secure boot." - bit_offset: 22 - bit_size: 8 - enum: OPTSR_BOOT_UBE - - name: SWAP_BANK - description: "Bank swapping option status bit\r SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not. \r SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset." - bit_offset: 31 - bit_size: 1 - enum: OPTSR_SWAP_BANK + - name: BOR_LEV + description: "Brownout level option status bit\r These bits reflects the power level that generates a system reset.\r 00 or 11: BOR Level 1, the threshold level is low (around 2.1�V)" + bit_offset: 0 + bit_size: 2 + enum: OPTSR_BOR_LEV + - name: BORH_EN + description: Brownout high enable + bit_offset: 2 + bit_size: 1 + - name: IWDG_SW + description: IWDG control mode option status bit + bit_offset: 3 + bit_size: 1 + enum: OPTSR_IWDG_SW + - name: WWDG_SW + description: WWDG control mode option status bit + bit_offset: 4 + bit_size: 1 + enum: OPTSR_WWDG_SW + - name: NRST_STOP + description: Core domain Stop entry reset option status bit + bit_offset: 6 + bit_size: 1 + enum: OPTSR_NRST_STOP + - name: NRST_STDBY + description: Core domain Standby entry reset option status bit + bit_offset: 7 + bit_size: 1 + enum: OPTSR_NRST_STDBY + - name: PRODUCT_STATE + description: 'Life state code (based on Hamming 8,4). More information in Section�7.6.11: Product state transitions.' + bit_offset: 8 + bit_size: 8 + - name: IO_VDD_HSLV + description: "High-speed IO at low VDD voltage configuration bit.\r This bit can be set only with VDD below 2.7�V." + bit_offset: 16 + bit_size: 1 + enum: OPTSR_IO_VDD_HSLV + - name: IO_VDDIO2_HSLV + description: "High-speed IO at low VDDIO2 voltage configuration bit.\r This bit can be set only with VDDIO2 below 2.7�V." + bit_offset: 17 + bit_size: 1 + enum: OPTSR_IO_VDDIO_HSLV + - name: IWDG_STOP + description: "IWDG Stop mode freeze option status bit\r When set the independent watchdog IWDG is in system Stop mode." + bit_offset: 20 + bit_size: 1 + enum: OPTSR_IWDG_STOP + - name: IWDG_STDBY + description: "IWDG Standby mode freeze option status bit\r When set the independent watchdog IWDG is frozen in system Standby mode." + bit_offset: 21 + bit_size: 1 + enum: OPTSR_IWDG_STDBY + - name: BOOT_UBE + description: "Available only on cryptography enabled devices.\r Unique boot entry control, selects either ST or OEM iRoT for secure boot." + bit_offset: 22 + bit_size: 8 + enum: OPTSR_BOOT_UBE + - name: SWAP_BANK + description: "Bank swapping option status bit\r SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not. \r SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset." + bit_offset: 31 + bit_size: 1 + enum: OPTSR_SWAP_BANK fieldset/OPTSR2: description: FLASH option status register 2 fields: - - name: SRAM13_RST - description: SRAM1 and SRAM3 erase upon system reset - bit_offset: 2 - bit_size: 1 - - name: SRAM2_RST - description: SRAM2 erase when system reset - bit_offset: 3 - bit_size: 1 - - name: BKPRAM_ECC - description: Backup RAM ECC detection and correction disable - bit_offset: 4 - bit_size: 1 - enum: OPTSR_BKPRAM_ECC - - name: SRAM3_ECC - description: SRAM3 ECC detection and correction disable - bit_offset: 5 - bit_size: 1 - enum: OPTSR_SRAM_ECC - - name: SRAM2_ECC - description: SRAM2 ECC detection and correction disable - bit_offset: 6 - bit_size: 1 - enum: OPTSR_SRAM_ECC - - name: USBPD_DIS - description: USB power delivery configuration option bit - bit_offset: 8 - bit_size: 1 - - name: TZEN - description: "TrustZone enable configuration bits\r This bit enables the device is in TrustZone mode during an option byte change." - bit_offset: 24 - bit_size: 8 - enum: OPTSR_TZEN + - name: SRAM13_RST + description: SRAM1 and SRAM3 erase upon system reset + bit_offset: 2 + bit_size: 1 + - name: SRAM2_RST + description: SRAM2 erase when system reset + bit_offset: 3 + bit_size: 1 + - name: BKPRAM_ECC + description: Backup RAM ECC detection and correction disable + bit_offset: 4 + bit_size: 1 + enum: OPTSR_BKPRAM_ECC + - name: SRAM3_ECC + description: SRAM3 ECC detection and correction disable + bit_offset: 5 + bit_size: 1 + enum: OPTSR_SRAM_ECC + - name: SRAM2_ECC + description: SRAM2 ECC detection and correction disable + bit_offset: 6 + bit_size: 1 + enum: OPTSR_SRAM_ECC + - name: USBPD_DIS + description: USB power delivery configuration option bit + bit_offset: 8 + bit_size: 1 + - name: TZEN + description: "TrustZone enable configuration bits\r This bit enables the device is in TrustZone mode during an option byte change." + bit_offset: 24 + bit_size: 8 + enum: OPTSR_TZEN fieldset/OTPBLR: description: FLASH non-secure OTP block lock fields: - - name: LOCKBL - description: "OTP block lock \r Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31.\r LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR.\r LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked.\r When one block is locked, it’s not possible to remove the write protection.\r Also if not locked, it is not possible to erase OTP words." - bit_offset: 0 - bit_size: 32 + - name: LOCKBL + description: "OTP block lock \r Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31.\r LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR.\r LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked.\r When one block is locked, it’s not possible to remove the write protection.\r Also if not locked, it is not possible to erase OTP words." + bit_offset: 0 + bit_size: 32 fieldset/PRIVBB: description: FLASH privilege block-based register for Bank 2 fields: - - name: PRIVBB - description: Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute - bit_offset: 0 - bit_size: 32 - enum: PRIVBBR_PRIVBB + - name: PRIVBB + description: Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute + bit_offset: 0 + bit_size: 32 + enum: PRIVBBR_PRIVBB fieldset/PRIVCFGR: description: FLASH privilege configuration register fields: - - name: SPRIV - description: privilege attribute for secure registers - bit_offset: 0 - bit_size: 1 - enum: SPRIV - - name: NSPRIV - description: privilege attribute for non secure registers - bit_offset: 1 - bit_size: 1 - enum: NSPRIV + - name: SPRIV + description: privilege attribute for secure registers + bit_offset: 0 + bit_size: 1 + enum: SPRIV + - name: NSPRIV + description: privilege attribute for non secure registers + bit_offset: 1 + bit_size: 1 + enum: NSPRIV fieldset/SECBB: description: FLASH secure block-based register for Bank 2 fields: - - name: SECBB - description: Secure/non-secure flash Bank 2 sector attribute - bit_offset: 0 - bit_size: 32 - enum: SECBBR_SECBB + - name: SECBB + description: Secure/non-secure flash Bank 2 sector attribute + bit_offset: 0 + bit_size: 32 + enum: SECBBR_SECBB fieldset/SECBOOTR: description: FLASH secure boot register fields: - - name: SECBOOT_LOCK - description: "A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings." - bit_offset: 0 - bit_size: 8 - enum: SECBOOTR_SECBOOT_LOCK - - name: SECBOOTADD - description: "Unique boot entry secure address \r These bits reflect the Secure UBE address" - bit_offset: 8 - bit_size: 24 + - name: SECBOOT_LOCK + description: A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. + bit_offset: 0 + bit_size: 8 + enum: SECBOOTR_SECBOOT_LOCK + - name: SECBOOTADD + description: "Unique boot entry secure address \r These bits reflect the Secure UBE address" + bit_offset: 8 + bit_size: 24 fieldset/SECCCR: description: FLASH secure clear control register fields: - - name: CLR_EOP - description: "EOP flag clear bit\r Setting this bit to 1 resets to 0 EOP flag in FLASH_SECSR register." - bit_offset: 16 - bit_size: 1 - - name: CLR_WRPERR - description: "WRPERR flag clear bit\r Setting this bit to 1 resets to 0 WRPERR flag in FLASH_SECSR register." - bit_offset: 17 - bit_size: 1 - - name: CLR_PGSERR - description: "PGSERR flag clear bit\r Setting this bit to 1 resets to 0 PGSERR flag in FLASH_SECSR register." - bit_offset: 18 - bit_size: 1 - - name: CLR_STRBERR - description: "STRBERR flag clear bit\r Setting this bit to 1 resets to 0 STRBERR flag in FLASH_SECSR register." - bit_offset: 19 - bit_size: 1 - - name: CLR_INCERR - description: "INCERR flag clear bit\r Setting this bit to 1 resets to 0 INCERR flag in FLASH_SECSR register." - bit_offset: 20 - bit_size: 1 - - name: CLR_OBKERR - description: "OBKWERR flag clear bit\r Setting this bit to 1 resets to 0 OBKWERR flag in FLASH_SECSR register." - bit_offset: 21 - bit_size: 1 - - name: CLR_OBKWERR - description: "OBKWERR flag clear bit\r Setting this bit to 1 resets to 0 OBKWERR flag in FLASH_SECSR register." - bit_offset: 22 - bit_size: 1 + - name: CLR_EOP + description: "EOP flag clear bit\r Setting this bit to 1 resets to 0 EOP flag in FLASH_SECSR register." + bit_offset: 16 + bit_size: 1 + - name: CLR_WRPERR + description: "WRPERR flag clear bit\r Setting this bit to 1 resets to 0 WRPERR flag in FLASH_SECSR register." + bit_offset: 17 + bit_size: 1 + - name: CLR_PGSERR + description: "PGSERR flag clear bit\r Setting this bit to 1 resets to 0 PGSERR flag in FLASH_SECSR register." + bit_offset: 18 + bit_size: 1 + - name: CLR_STRBERR + description: "STRBERR flag clear bit\r Setting this bit to 1 resets to 0 STRBERR flag in FLASH_SECSR register." + bit_offset: 19 + bit_size: 1 + - name: CLR_INCERR + description: "INCERR flag clear bit\r Setting this bit to 1 resets to 0 INCERR flag in FLASH_SECSR register." + bit_offset: 20 + bit_size: 1 + - name: CLR_OBKERR + description: "OBKWERR flag clear bit\r Setting this bit to 1 resets to 0 OBKWERR flag in FLASH_SECSR register." + bit_offset: 21 + bit_size: 1 + - name: CLR_OBKWERR + description: "OBKWERR flag clear bit\r Setting this bit to 1 resets to 0 OBKWERR flag in FLASH_SECSR register." + bit_offset: 22 + bit_size: 1 fieldset/SECCR: description: FLASH secure control register fields: - - name: LOCK - description: "configuration lock bit \r This bit locks the FLASH_SECCR register. The correct write sequence to FLASH_SECKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset. \r LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_SECCR register do not change." - bit_offset: 0 - bit_size: 1 - - name: PG - description: "programming control bit\r PG can be programmed only when LOCK is cleared to 0. \r PG allows programming in Bank1 and Bank2." - bit_offset: 1 - bit_size: 1 - - name: SER - description: "sector erase request\r Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0. \r If BER and MER are also set, a PGSERR is raised." - bit_offset: 2 - bit_size: 1 - - name: BER - description: "erase request \r Setting BER bit to 1 requests a bank erase operation (user flash memory only). BER can be programmed only when LOCK is cleared to 0. \r If MER and SER are also set, a PGSERR is raised.\r Note: Write protection error is triggered when a bank erase is required and some sectors are protected." - bit_offset: 3 - bit_size: 1 - - name: FW - description: "write forcing control bit\r FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0. \r The embedded flash memory resets FW when the corresponding operation has been acknowledged. \r Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error.\r Write forcing is effective only if the write buffer is not empty and was filled by secure access (in particular, FW does not start several write operations when the force-write operations are performed consecutively). \r Since there is just one write buffer, FW can force a write in bank1 or bank2." - bit_offset: 4 - bit_size: 1 - - name: STRT - description: "erase start control bit\r STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0. \r STRT is reseted at the end of the operation or when an error occurs. It cannot be reset by software." - bit_offset: 5 - bit_size: 1 - - name: SNB - description: "sector erase selection number\r These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0.\r .." - bit_offset: 6 - bit_size: 7 - - name: MER - description: "mass erase request\r Setting MER bit to 1 requests a mass erase operation (user flash memory only). MER can be programmed only when LOCK is cleared to 0. \r If BER or SER are also set, a PGSERR is raised.\r Error is triggered when a mass erase is required and some sectors are protected." - bit_offset: 15 - bit_size: 1 - - name: EOPIE - description: "end of operation interrupt control bit\r Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program/erase operation. EOPIE can be programmed only when LOCK is cleared to 0." - bit_offset: 16 - bit_size: 1 - - name: WRPERRIE - description: "write protection error interrupt enable bit\r When WRPERRIE bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0." - bit_offset: 17 - bit_size: 1 - - name: PGSERRIE - description: "programming sequence error interrupt enable bit\r When PGSERRIE bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0." - bit_offset: 18 - bit_size: 1 - - name: STRBERRIE - description: "strobe error interrupt enable bit\r When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0." - bit_offset: 19 - bit_size: 1 - - name: INCERRIE - description: "inconsistency error interrupt enable bit\r When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0." - bit_offset: 20 - bit_size: 1 - - name: OBKERRIE - description: "OBK general error interrupt enable bit\r OBKERRIE enables generating an interrupt in case of OBK specific access error. OBKERRIE can be programmed only when LOCK is cleared to 0." - bit_offset: 21 - bit_size: 1 - - name: OBKWERRIE - description: "OBK write error interrupt enable bit\r OBKWERRIE enables generation of interrupt in case of OBK specific write error. OBKWERRIE can be programmed only when LOCK is cleared to 0." - bit_offset: 22 - bit_size: 1 - - name: INV - description: "Flash memory security state invert.\r This bit inverts the flash memory security state." - bit_offset: 29 - bit_size: 1 - - name: BKSEL - description: "bank selector bit\r BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored." - bit_offset: 31 - bit_size: 1 - enum: SECCR_BKSEL + - name: LOCK + description: "configuration lock bit \r This bit locks the FLASH_SECCR register. The correct write sequence to FLASH_SECKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset. \r LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_SECCR register do not change." + bit_offset: 0 + bit_size: 1 + - name: PG + description: "programming control bit\r PG can be programmed only when LOCK is cleared to 0. \r PG allows programming in Bank1 and Bank2." + bit_offset: 1 + bit_size: 1 + - name: SER + description: "sector erase request\r Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0. \r If BER and MER are also set, a PGSERR is raised." + bit_offset: 2 + bit_size: 1 + - name: BER + description: "erase request \r Setting BER bit to 1 requests a bank erase operation (user flash memory only). BER can be programmed only when LOCK is cleared to 0. \r If MER and SER are also set, a PGSERR is raised.\r Note: Write protection error is triggered when a bank erase is required and some sectors are protected." + bit_offset: 3 + bit_size: 1 + - name: FW + description: "write forcing control bit\r FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0. \r The embedded flash memory resets FW when the corresponding operation has been acknowledged. \r Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error.\r Write forcing is effective only if the write buffer is not empty and was filled by secure access (in particular, FW does not start several write operations when the force-write operations are performed consecutively). \r Since there is just one write buffer, FW can force a write in bank1 or bank2." + bit_offset: 4 + bit_size: 1 + - name: STRT + description: "erase start control bit\r STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0. \r STRT is reseted at the end of the operation or when an error occurs. It cannot be reset by software." + bit_offset: 5 + bit_size: 1 + - name: SNB + description: "sector erase selection number\r These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0.\r .." + bit_offset: 6 + bit_size: 7 + - name: MER + description: "mass erase request\r Setting MER bit to 1 requests a mass erase operation (user flash memory only). MER can be programmed only when LOCK is cleared to 0. \r If BER or SER are also set, a PGSERR is raised.\r Error is triggered when a mass erase is required and some sectors are protected." + bit_offset: 15 + bit_size: 1 + - name: EOPIE + description: "end of operation interrupt control bit\r Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program/erase operation. EOPIE can be programmed only when LOCK is cleared to 0." + bit_offset: 16 + bit_size: 1 + - name: WRPERRIE + description: "write protection error interrupt enable bit\r When WRPERRIE bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 17 + bit_size: 1 + - name: PGSERRIE + description: "programming sequence error interrupt enable bit\r When PGSERRIE bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 18 + bit_size: 1 + - name: STRBERRIE + description: "strobe error interrupt enable bit\r When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 19 + bit_size: 1 + - name: INCERRIE + description: "inconsistency error interrupt enable bit\r When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 20 + bit_size: 1 + - name: OBKERRIE + description: "OBK general error interrupt enable bit\r OBKERRIE enables generating an interrupt in case of OBK specific access error. OBKERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 21 + bit_size: 1 + - name: OBKWERRIE + description: "OBK write error interrupt enable bit\r OBKWERRIE enables generation of interrupt in case of OBK specific write error. OBKWERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 22 + bit_size: 1 + - name: INV + description: "Flash memory security state invert.\r This bit inverts the flash memory security state." + bit_offset: 29 + bit_size: 1 + - name: BKSEL + description: "bank selector bit\r BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored." + bit_offset: 31 + bit_size: 1 + enum: SECCR_BKSEL fieldset/SECEPOCHR: description: FLASH secure EPOCH register fields: - - name: SEC_EPOCH - description: Non-volatile secure EPOCH counter - bit_offset: 0 - bit_size: 24 + - name: SEC_EPOCH + description: Non-volatile secure EPOCH counter + bit_offset: 0 + bit_size: 24 fieldset/SECKEYR: description: FLASH secure key register fields: - - name: SECKEY - description: Non-volatile memory secure configuration access unlock key - bit_offset: 0 - bit_size: 32 + - name: SECKEY + description: Non-volatile memory secure configuration access unlock key + bit_offset: 0 + bit_size: 32 fieldset/SECOBKCFGR: description: FLASH secure OBK configuration register fields: - - name: LOCK - description: "OBKCFGR lock option configuration bit\r This bit locks the FLASH_OBKCFGR register. The correct write sequence to FLASH_SECOBKKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_SECOBKKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change." - bit_offset: 0 - bit_size: 1 - - name: SWAP_SECT_REQ - description: "OBK swap sector request bit\r When set, all the OBKs which have not been updated in the alternate sector is copied from current sector to alternate one.\r The SWAP_OFFSET value must be a certain minimum value in order for the swap to be launched in OBK-HDPL ≠ 0. Minimum value is 16 for OBK-HDPL = 1, 144 for OBK-HDPL = 2 and 192 for OBK-HDPL = 3." - bit_offset: 1 - bit_size: 1 - - name: ALT_SECT - description: "alternate sector bit\r This bit must not change while filling the write buffer, otherwise an error is generated" - bit_offset: 2 - bit_size: 1 - - name: ALT_SECT_ERASE - description: "alternate sector erase bit\r When ALT_SECT bit is set, use this bit to generate an erase command for the OBK alternate sector. It is set only by Software and cleared when the OBK swap operation is completed or an error occurs (PGSERR). It is reseted at the same time as the BUSY bit." - bit_offset: 3 - bit_size: 1 - - name: SWAP_OFFSET - description: "key index (offset /16 bits) pointing for next swap.\r …" - bit_offset: 16 - bit_size: 9 + - name: LOCK + description: "OBKCFGR lock option configuration bit\r This bit locks the FLASH_OBKCFGR register. The correct write sequence to FLASH_SECOBKKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_SECOBKKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change." + bit_offset: 0 + bit_size: 1 + - name: SWAP_SECT_REQ + description: "OBK swap sector request bit\r When set, all the OBKs which have not been updated in the alternate sector is copied from current sector to alternate one.\r The SWAP_OFFSET value must be a certain minimum value in order for the swap to be launched in OBK-HDPL ≠ 0. Minimum value is 16 for OBK-HDPL = 1, 144 for OBK-HDPL = 2 and 192 for OBK-HDPL = 3." + bit_offset: 1 + bit_size: 1 + - name: ALT_SECT + description: "alternate sector bit\r This bit must not change while filling the write buffer, otherwise an error is generated" + bit_offset: 2 + bit_size: 1 + - name: ALT_SECT_ERASE + description: "alternate sector erase bit\r When ALT_SECT bit is set, use this bit to generate an erase command for the OBK alternate sector. It is set only by Software and cleared when the OBK swap operation is completed or an error occurs (PGSERR). It is reseted at the same time as the BUSY bit." + bit_offset: 3 + bit_size: 1 + - name: SWAP_OFFSET + description: "key index (offset /16 bits) pointing for next swap.\r …" + bit_offset: 16 + bit_size: 9 fieldset/SECOBKKEYR: description: FLASH secure OBK key register fields: - - name: SECOBKKEY - description: FLASH secure option bytes keys control access unlock key - bit_offset: 0 - bit_size: 32 + - name: SECOBKKEY + description: FLASH secure option bytes keys control access unlock key + bit_offset: 0 + bit_size: 32 fieldset/SECSR: description: FLASH secure status register fields: - - name: BSY - description: "busy flag\r BSY flag indicates that a FLASH memory is busy (write, erase, option byte change, OBK operations). It is set at the beginning of a flash memory operation and cleared when the operation finishes or an error occurs." - bit_offset: 0 - bit_size: 1 - - name: WBNE - description: "write buffer not empty flag \r WBNE flag is set when the flash interface is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below:\r the application software forces the write operation using FW bit in FLASH_SECCR\r the flash interface detects an error that involves data loss\r This bit cannot be reset by writing 0 directly by software. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data." - bit_offset: 1 - bit_size: 1 - - name: DBNE - description: "data buffer not empty flag \r DBNE flag is set when the embedded flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free." - bit_offset: 3 - bit_size: 1 - - name: EOP - description: "end of operation flag\r EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_SECCCR register." - bit_offset: 16 - bit_size: 1 - - name: WRPERR - description: "write protection error flag\r WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_SECCCR register clears WRPERR." - bit_offset: 17 - bit_size: 1 - - name: PGSERR - description: "programming sequence error flag\r PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_SECCCR register clears PGSERR." - bit_offset: 18 - bit_size: 1 - - name: STRBERR - description: "strobe error flag \r STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_SECCCR register clears STRBERR." - bit_offset: 19 - bit_size: 1 - - name: INCERR - description: "inconsistency error flag\r INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_SECCCR register clears INCERR." - bit_offset: 20 - bit_size: 1 - - name: OBKERR - description: "OBK general error flag\r OBKERR flag is raised when the OBK-HDPL signal from the SBS does not match the HDPL value associated with the key slot during access to the key location. Alternatively also when the ALT_SECT is unexpectedly changed while the write buffer is being filled." - bit_offset: 21 - bit_size: 1 - - name: OBKWERR - description: "OBK write error flag\r OBKWERR flag is raised when the address is not virgin on a write access to the OBK storage. Alternatively also when the OBK selector in the alternate sector is not virgin during a swap operation." - bit_offset: 22 - bit_size: 1 + - name: BSY + description: "busy flag\r BSY flag indicates that a FLASH memory is busy (write, erase, option byte change, OBK operations). It is set at the beginning of a flash memory operation and cleared when the operation finishes or an error occurs." + bit_offset: 0 + bit_size: 1 + - name: WBNE + description: "write buffer not empty flag \r WBNE flag is set when the flash interface is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below:\r the application software forces the write operation using FW bit in FLASH_SECCR\r the flash interface detects an error that involves data loss\r This bit cannot be reset by writing 0 directly by software. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data." + bit_offset: 1 + bit_size: 1 + - name: DBNE + description: "data buffer not empty flag \r DBNE flag is set when the embedded flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free." + bit_offset: 3 + bit_size: 1 + - name: EOP + description: "end of operation flag\r EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_SECCCR register." + bit_offset: 16 + bit_size: 1 + - name: WRPERR + description: "write protection error flag\r WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_SECCCR register clears WRPERR." + bit_offset: 17 + bit_size: 1 + - name: PGSERR + description: "programming sequence error flag\r PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_SECCCR register clears PGSERR." + bit_offset: 18 + bit_size: 1 + - name: STRBERR + description: "strobe error flag \r STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_SECCCR register clears STRBERR." + bit_offset: 19 + bit_size: 1 + - name: INCERR + description: "inconsistency error flag\r INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_SECCCR register clears INCERR." + bit_offset: 20 + bit_size: 1 + - name: OBKERR + description: "OBK general error flag\r OBKERR flag is raised when the OBK-HDPL signal from the SBS does not match the HDPL value associated with the key slot during access to the key location. Alternatively also when the ALT_SECT is unexpectedly changed while the write buffer is being filled." + bit_offset: 21 + bit_size: 1 + - name: OBKWERR + description: "OBK write error flag\r OBKWERR flag is raised when the address is not virgin on a write access to the OBK storage. Alternatively also when the OBK selector in the alternate sector is not virgin during a swap operation." + bit_offset: 22 + bit_size: 1 fieldset/SECWM: description: FLASH security watermark for Bank 2 fields: - - name: SECWMSTRT - description: Bank2 security WM area start sector - bit_offset: 0 - bit_size: 7 - - name: SECWMEND - description: Bank2 security WM end sector - bit_offset: 16 - bit_size: 7 + - name: SECWMSTRT + description: Bank2 security WM area start sector + bit_offset: 0 + bit_size: 7 + - name: SECWMEND + description: Bank2 security WM end sector + bit_offset: 16 + bit_size: 7 fieldset/WRP: description: FLASH write sector group protection for Bank 1 fields: - - name: WRPSG - description: "Bank1 sector group protection option status byte\r Setting WRPSG1 bits to 0 write protects the corresponding group of four consecutive sectors in bank 1 (0: the group is write protected; 1: the group is not write protected)\r Bit 0: Group embedding sectors 0 to 3\r Bit 1: Group embedding sectors 4 to 7\r Bit N: Group embedding sectors 4 x N to 4 x N + 3\r Bit 31: Group embedding sectors 124 to 127" - bit_offset: 0 - bit_size: 32 + - name: WRPSG + description: "Bank1 sector group protection option status byte\r Setting WRPSG1 bits to 0 write protects the corresponding group of four consecutive sectors in bank 1 (0: the group is write protected; 1: the group is not write protected)\r Bit 0: Group embedding sectors 0 to 3\r Bit 1: Group embedding sectors 4 to 7\r Bit N: Group embedding sectors 4 x N to 4 x N + 3\r Bit 31: Group embedding sectors 124 to 127" + bit_offset: 0 + bit_size: 32 enum/BOOTR_SECBOOT_LOCK: bit_size: 8 variants: - - name: B_0xB4 - description: The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). - value: 180 - - name: B_0xC3 - description: "The BOOT_UBE, SWAP_ BANK and SECBOOTADD can still be modified following their individual rules." - value: 195 + - name: B_0xB4 + description: The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). + value: 180 + - name: B_0xC3 + description: The BOOT_UBE, SWAP_ BANK and SECBOOTADD can still be modified following their individual rules. + value: 195 enum/CODE_OP: bit_size: 3 variants: - - name: B_0x0 - description: No flash operation on going during previous reset - value: 0 - - name: B_0x1 - description: Single write operation interrupted - value: 1 - - name: B_0x2 - description: OBK alternate sector erase - value: 2 - - name: B_0x3 - description: Sector erase operation interrupted - value: 3 - - name: B_0x4 - description: Bank erase operation interrupted - value: 4 - - name: B_0x5 - description: Mass erase operation interrupted - value: 5 - - name: B_0x6 - description: Option change operation interrupted - value: 6 - - name: B_0x7 - description: OBK swap sector request - value: 7 + - name: B_0x0 + description: No flash operation on going during previous reset + value: 0 + - name: B_0x1 + description: Single write operation interrupted + value: 1 + - name: B_0x2 + description: OBK alternate sector erase + value: 2 + - name: B_0x3 + description: Sector erase operation interrupted + value: 3 + - name: B_0x4 + description: Bank erase operation interrupted + value: 4 + - name: B_0x5 + description: Mass erase operation interrupted + value: 5 + - name: B_0x6 + description: Option change operation interrupted + value: 6 + - name: B_0x7 + description: OBK swap sector request + value: 7 enum/NSBOOTR_NSBOOT_LOCK: bit_size: 8 variants: - - name: B_0xB4 - description: The NSBOOTADD is frozen. SWAP_ BANK can only be modified with TZEN set to 0xB4 (enabled). - value: 180 - - name: B_0xC3 - description: The SWAP_ BANK and NSBOOTADD can still be modified following their individual rules. - value: 195 + - name: B_0xB4 + description: The NSBOOTADD is frozen. SWAP_ BANK can only be modified with TZEN set to 0xB4 (enabled). + value: 180 + - name: B_0xC3 + description: The SWAP_ BANK and NSBOOTADD can still be modified following their individual rules. + value: 195 enum/NSCR_BKSEL: bit_size: 1 variants: - - name: B_0x0 - description: Bank1 is selected for Bank erase / sector erase / interrupt enable - value: 0 - - name: B_0x1 - description: Bank2 is selected for BER / SER - value: 1 + - name: B_0x0 + description: Bank1 is selected for Bank erase / sector erase / interrupt enable + value: 0 + - name: B_0x1 + description: Bank2 is selected for BER / SER + value: 1 enum/NSPRIV: bit_size: 1 variants: - - name: B_0x0 - description: access to non secure registers is always granted - value: 0 - - name: B_0x1 - description: access to non secure registers is denied in case of unprivileged access. - value: 1 + - name: B_0x0 + description: access to non secure registers is always granted + value: 0 + - name: B_0x1 + description: access to non secure registers is denied in case of unprivileged access. + value: 1 enum/OPTCR_SWAP_BANK: bit_size: 1 variants: - - name: B_0x0 - description: Bank1 and Bank2 not swapped - value: 0 - - name: B_0x1 - description: Bank1 and Bank2 swapped - value: 1 + - name: B_0x0 + description: Bank1 and Bank2 not swapped + value: 0 + - name: B_0x1 + description: Bank1 and Bank2 swapped + value: 1 enum/OPTSR_BKPRAM_ECC: bit_size: 1 variants: - - name: B_0x0 - description: BKPRAM ECC check enabled - value: 0 - - name: B_0x1 - description: BKPRAM ECC check disabled - value: 1 + - name: B_0x0 + description: BKPRAM ECC check enabled + value: 0 + - name: B_0x1 + description: BKPRAM ECC check disabled + value: 1 enum/OPTSR_BOOT_UBE: bit_size: 8 variants: - - name: B_0xB4 - description: OEM-iRoT (user flash) selected. In Open PRODUCT_STATE this value selects bootloader. Defaut value. - value: 180 - - name: B_0xC3 - description: ST-iRoT (system flash) selected - value: 195 + - name: B_0xB4 + description: OEM-iRoT (user flash) selected. In Open PRODUCT_STATE this value selects bootloader. Defaut value. + value: 180 + - name: B_0xC3 + description: ST-iRoT (system flash) selected + value: 195 enum/OPTSR_BOR_LEV: bit_size: 2 variants: - - name: B_0x1 - description: "BOR Level 2, the threshold level is medium (around 2.4 V)" - value: 1 - - name: B_0x2 - description: "BOR Level 3, the threshold level is high (around 2.7 V)" - value: 2 + - name: B_0x1 + description: BOR Level 2, the threshold level is medium (around 2.4 V) + value: 1 + - name: B_0x2 + description: BOR Level 3, the threshold level is high (around 2.7 V) + value: 2 enum/OPTSR_IO_VDDIO_HSLV: bit_size: 1 variants: - - name: B_0x0 - description: High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7�V) - value: 0 - - name: B_0x1 - description: High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7�V) - value: 1 + - name: B_0x0 + description: High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7�V) + value: 0 + - name: B_0x1 + description: High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7�V) + value: 1 enum/OPTSR_IO_VDD_HSLV: bit_size: 1 variants: - - name: B_0x0 - description: High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7�V) - value: 0 - - name: B_0x1 - description: High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7�V) - value: 1 + - name: B_0x0 + description: High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7�V) + value: 0 + - name: B_0x1 + description: High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7�V) + value: 1 enum/OPTSR_IWDG_STDBY: bit_size: 1 variants: - - name: B_0x0 - description: Independent watchdog frozen in Standby mode - value: 0 - - name: B_0x1 - description: Independent watchdog keep running in Standby mode. - value: 1 + - name: B_0x0 + description: Independent watchdog frozen in Standby mode + value: 0 + - name: B_0x1 + description: Independent watchdog keep running in Standby mode. + value: 1 enum/OPTSR_IWDG_STOP: bit_size: 1 variants: - - name: B_0x0 - description: Independent watchdog frozen in system Stop mode - value: 0 - - name: B_0x1 - description: Independent watchdog keep running in system Stop mode. - value: 1 + - name: B_0x0 + description: Independent watchdog frozen in system Stop mode + value: 0 + - name: B_0x1 + description: Independent watchdog keep running in system Stop mode. + value: 1 enum/OPTSR_IWDG_SW: bit_size: 1 variants: - - name: B_0x0 - description: IWDG watchdog is controlled by hardware - value: 0 - - name: B_0x1 - description: IWDG watchdog is controlled by software - value: 1 + - name: B_0x0 + description: IWDG watchdog is controlled by hardware + value: 0 + - name: B_0x1 + description: IWDG watchdog is controlled by software + value: 1 enum/OPTSR_NRST_STDBY: bit_size: 1 variants: - - name: B_0x0 - description: a reset is generated when entering Standby mode on core domain - value: 0 - - name: B_0x1 - description: no reset generated when entering Standby mode on core domain. - value: 1 + - name: B_0x0 + description: a reset is generated when entering Standby mode on core domain + value: 0 + - name: B_0x1 + description: no reset generated when entering Standby mode on core domain. + value: 1 enum/OPTSR_NRST_STOP: bit_size: 1 variants: - - name: B_0x0 - description: a reset is generated when entering Stop mode on core domain - value: 0 - - name: B_0x1 - description: no reset generated when entering Stop mode on core domain. - value: 1 + - name: B_0x0 + description: a reset is generated when entering Stop mode on core domain + value: 0 + - name: B_0x1 + description: no reset generated when entering Stop mode on core domain. + value: 1 enum/OPTSR_SRAM_ECC: bit_size: 1 variants: - - name: B_0x0 - description: SRAM2 ECC check enabled - value: 0 - - name: B_0x1 - description: SRAM2 ECC check disabled - value: 1 + - name: B_0x0 + description: SRAM2 ECC check enabled + value: 0 + - name: B_0x1 + description: SRAM2 ECC check disabled + value: 1 enum/OPTSR_SWAP_BANK: bit_size: 1 variants: - - name: B_0x0 - description: Bank1 and Bank2 not swapped - value: 0 - - name: B_0x1 - description: Bank1 and Bank2 swapped - value: 1 + - name: B_0x0 + description: Bank1 and Bank2 not swapped + value: 0 + - name: B_0x1 + description: Bank1 and Bank2 swapped + value: 1 enum/OPTSR_TZEN: bit_size: 8 variants: - - name: B_0xB4 - description: TrustZone enabled. - value: 180 - - name: B_0xC3 - description: TrustZone disabled - value: 195 + - name: B_0xB4 + description: TrustZone enabled. + value: 180 + - name: B_0xC3 + description: TrustZone disabled + value: 195 enum/OPTSR_WWDG_SW: bit_size: 1 variants: - - name: B_0x0 - description: WWDG watchdog is controlled by hardware - value: 0 - - name: B_0x1 - description: WWDG watchdog is controlled by software - value: 1 + - name: B_0x0 + description: WWDG watchdog is controlled by hardware + value: 0 + - name: B_0x1 + description: WWDG watchdog is controlled by software + value: 1 enum/PRIVBBR_PRIVBB: bit_size: 32 variants: - - name: B_0x0 - description: sectors (32 * (x-1) + y) in bank 2 is unprivileged - value: 0 - - name: B_0x1 - description: sector (32 * (x-1) + y) in bank 2 is privileged - value: 1 + - name: B_0x0 + description: sectors (32 * (x-1) + y) in bank 2 is unprivileged + value: 0 + - name: B_0x1 + description: sector (32 * (x-1) + y) in bank 2 is privileged + value: 1 enum/SECBBR_SECBB: bit_size: 32 variants: - - name: B_0x0 - description: sectors (32 * (x-1) + y) in bank 2 is non secure - value: 0 - - name: B_0x1 - description: sector (32 * (x-1) + y) in bank 2 is secure - value: 1 + - name: B_0x0 + description: sectors (32 * (x-1) + y) in bank 2 is non secure + value: 0 + - name: B_0x1 + description: sector (32 * (x-1) + y) in bank 2 is secure + value: 1 enum/SECBOOTR_SECBOOT_LOCK: bit_size: 8 variants: - - name: B_0xB4 - description: The BOOT_UBE and SECBOOTADD are frozen. SWAP_ BANK can only be modified with TZEN set to 0xC3 (disabled). - value: 180 - - name: B_0xC3 - description: "The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules." - value: 195 + - name: B_0xB4 + description: The BOOT_UBE and SECBOOTADD are frozen. SWAP_ BANK can only be modified with TZEN set to 0xC3 (disabled). + value: 180 + - name: B_0xC3 + description: The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules. + value: 195 enum/SECCR_BKSEL: bit_size: 1 variants: - - name: B_0x0 - description: Bank1 is selected for Bank erase / sector erase / interrupt enable - value: 0 - - name: B_0x1 - description: Bank2 is selected for BER / SER - value: 1 + - name: B_0x0 + description: Bank1 is selected for Bank erase / sector erase / interrupt enable + value: 0 + - name: B_0x1 + description: Bank2 is selected for BER / SER + value: 1 enum/SPRIV: bit_size: 1 variants: - - name: B_0x0 - description: access to secure registers is always granted - value: 0 - - name: B_0x1 - description: access to secure registers is denied in case of unprivileged access. - value: 1 + - name: B_0x0 + description: access to secure registers is always granted + value: 0 + - name: B_0x1 + description: access to secure registers is denied in case of unprivileged access. + value: 1 diff --git a/data/registers/flash_h50.yaml b/data/registers/flash_h50.yaml index 1ff0580..fb487cc 100644 --- a/data/registers/flash_h50.yaml +++ b/data/registers/flash_h50.yaml @@ -1,779 +1,778 @@ ---- block/FLASH: description: FLASH address block description items: - - name: ACR - description: FLASH access control register - byte_offset: 0 - fieldset: ACR - - name: NSKEYR - description: FLASH key register - byte_offset: 4 - fieldset: NSKEYR - - name: OPTKEYR - description: FLASH option key register - byte_offset: 12 - fieldset: OPTKEYR - - name: OPSR - description: FLASH operation status register - byte_offset: 24 - fieldset: OPSR - - name: OPTCR - description: FLASH option control register - byte_offset: 28 - fieldset: OPTCR - - name: NSSR - description: FLASH non-secure status register - byte_offset: 32 - fieldset: NSSR - - name: SECSR - description: FLASH secure status register - byte_offset: 36 - fieldset: SECSR - - name: NSCR - description: FLASH Non Secure control register - byte_offset: 40 - fieldset: NSCR - - name: NSCCR - description: FLASH non-secure clear control register - byte_offset: 48 - fieldset: NSCCR - - name: PRIVCFGR - description: FLASH privilege configuration register - byte_offset: 60 - fieldset: PRIVCFGR - - name: HDPEXTR - description: FLASH HDP extension register - byte_offset: 72 - fieldset: HDPEXTR - - name: OPTSR_CUR - description: FLASH option status register - byte_offset: 80 - fieldset: OPTSR - - name: OPTSR_PRG - description: FLASH option status register - byte_offset: 84 - fieldset: OPTSR - - name: OPTSR2_CUR - description: FLASH option status register 2 - byte_offset: 112 - fieldset: OPTSR2 - - name: OPTSR2_PRG - description: FLASH option status register 2 - byte_offset: 116 - fieldset: OPTSR2 - - name: NSBOOTR_CUR - description: FLASH non-secure unique boot entry register - byte_offset: 128 - fieldset: NSBOOTR - - name: NSBOOTR_PRG - description: FLASH non-secure unique boot entry address - byte_offset: 132 - fieldset: NSBOOTR - - name: OTPBLR_CUR - description: FLASH non-secure OTP block lock - byte_offset: 144 - fieldset: OTPBLR - - name: OTPBLR_PRG - description: FLASH non-secure OTP block lock - byte_offset: 148 - fieldset: OTPBLR - - name: PRIVBB1R - description: FLASH privilege register for bank 1 - byte_offset: 192 - fieldset: PRIVBB - - name: WRPSGN1R_CUR - description: FLASH write sector protection for Bank1 - byte_offset: 232 - fieldset: WRP - - name: WRPSGN1R_PRG - description: FLASH write sector protection for Bank1 - byte_offset: 236 - fieldset: WRP - - name: HDP1R_CUR - description: FLASH HDP Bank1 register - byte_offset: 248 - fieldset: HDP1R - - name: HDP1R_PRG - description: FLASH HDP Bank1 register - byte_offset: 252 - fieldset: HDP1R - - name: ECCCORR - description: FLASH Flash ECC correction register - byte_offset: 256 - fieldset: ECCCORR - - name: ECCDETR - description: FLASH ECC detection register - byte_offset: 260 - fieldset: ECCDETR - - name: ECCDR - description: FLASH ECC data - byte_offset: 264 - fieldset: ECCDR - - name: WRPSGN2R_CUR - description: FLASH write sector protection for Bank2 - byte_offset: 488 - fieldset: WRP - - name: WRPSGN2R_PRG - description: FLASH write sector protection for Bank2 - byte_offset: 492 - fieldset: WRP - - name: HDP2R_CUR - description: FLASH HDP Bank2 register - byte_offset: 504 - fieldset: HDP2R - - name: HDP2R_PRG - description: FLASH HDP Bank2 register - byte_offset: 508 - fieldset: HDP2R + - name: ACR + description: FLASH access control register + byte_offset: 0 + fieldset: ACR + - name: NSKEYR + description: FLASH key register + byte_offset: 4 + fieldset: NSKEYR + - name: OPTKEYR + description: FLASH option key register + byte_offset: 12 + fieldset: OPTKEYR + - name: OPSR + description: FLASH operation status register + byte_offset: 24 + fieldset: OPSR + - name: OPTCR + description: FLASH option control register + byte_offset: 28 + fieldset: OPTCR + - name: NSSR + description: FLASH non-secure status register + byte_offset: 32 + fieldset: NSSR + - name: SECSR + description: FLASH secure status register + byte_offset: 36 + fieldset: SECSR + - name: NSCR + description: FLASH Non Secure control register + byte_offset: 40 + fieldset: NSCR + - name: NSCCR + description: FLASH non-secure clear control register + byte_offset: 48 + fieldset: NSCCR + - name: PRIVCFGR + description: FLASH privilege configuration register + byte_offset: 60 + fieldset: PRIVCFGR + - name: HDPEXTR + description: FLASH HDP extension register + byte_offset: 72 + fieldset: HDPEXTR + - name: OPTSR_CUR + description: FLASH option status register + byte_offset: 80 + fieldset: OPTSR + - name: OPTSR_PRG + description: FLASH option status register + byte_offset: 84 + fieldset: OPTSR + - name: OPTSR2_CUR + description: FLASH option status register 2 + byte_offset: 112 + fieldset: OPTSR2 + - name: OPTSR2_PRG + description: FLASH option status register 2 + byte_offset: 116 + fieldset: OPTSR2 + - name: NSBOOTR_CUR + description: FLASH non-secure unique boot entry register + byte_offset: 128 + fieldset: NSBOOTR + - name: NSBOOTR_PRG + description: FLASH non-secure unique boot entry address + byte_offset: 132 + fieldset: NSBOOTR + - name: OTPBLR_CUR + description: FLASH non-secure OTP block lock + byte_offset: 144 + fieldset: OTPBLR + - name: OTPBLR_PRG + description: FLASH non-secure OTP block lock + byte_offset: 148 + fieldset: OTPBLR + - name: PRIVBB1R + description: FLASH privilege register for bank 1 + byte_offset: 192 + fieldset: PRIVBB + - name: WRPSGN1R_CUR + description: FLASH write sector protection for Bank1 + byte_offset: 232 + fieldset: WRP + - name: WRPSGN1R_PRG + description: FLASH write sector protection for Bank1 + byte_offset: 236 + fieldset: WRP + - name: HDP1R_CUR + description: FLASH HDP Bank1 register + byte_offset: 248 + fieldset: HDP1R + - name: HDP1R_PRG + description: FLASH HDP Bank1 register + byte_offset: 252 + fieldset: HDP1R + - name: ECCCORR + description: FLASH Flash ECC correction register + byte_offset: 256 + fieldset: ECCCORR + - name: ECCDETR + description: FLASH ECC detection register + byte_offset: 260 + fieldset: ECCDETR + - name: ECCDR + description: FLASH ECC data + byte_offset: 264 + fieldset: ECCDR + - name: WRPSGN2R_CUR + description: FLASH write sector protection for Bank2 + byte_offset: 488 + fieldset: WRP + - name: WRPSGN2R_PRG + description: FLASH write sector protection for Bank2 + byte_offset: 492 + fieldset: WRP + - name: HDP2R_CUR + description: FLASH HDP Bank2 register + byte_offset: 504 + fieldset: HDP2R + - name: HDP2R_PRG + description: FLASH HDP Bank2 register + byte_offset: 508 + fieldset: HDP2R fieldset/ACR: description: FLASH access control register fields: - - name: LATENCY - description: "Read latency\r These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions.\r ...\r Note: No check is performed by hardware to verify that the configuration is correct." - bit_offset: 0 - bit_size: 4 - - name: WRHIGHFREQ - description: "Flash signal delay\r These bits are used to control the delay between non-volatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded Flash memory interface frequency. Please refer to for details.\r Note: No check is performed to verify that the configuration is correct.\r Two WRHIGHFREQ values can be selected for some frequencies." - bit_offset: 4 - bit_size: 2 - - name: PRFTEN - description: "Prefetch enable. When bit value is modified, user must read back ACR register to be sure PRFTEN has been taken into account.\r Bits used to control the prefetch." - bit_offset: 8 - bit_size: 1 - - name: S_PRFTEN - description: "Smart prefetch enable. When bit value is modified, user must read back ACR register to be sure S_PRFTEN has been taken into account.\r Bits used to control the prefetch functionality." - bit_offset: 9 - bit_size: 1 + - name: LATENCY + description: "Read latency\r These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions.\r ...\r Note: No check is performed by hardware to verify that the configuration is correct." + bit_offset: 0 + bit_size: 4 + - name: WRHIGHFREQ + description: "Flash signal delay\r These bits are used to control the delay between non-volatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded Flash memory interface frequency. Please refer to for details.\r Note: No check is performed to verify that the configuration is correct.\r Two WRHIGHFREQ values can be selected for some frequencies." + bit_offset: 4 + bit_size: 2 + - name: PRFTEN + description: "Prefetch enable. When bit value is modified, user must read back ACR register to be sure PRFTEN has been taken into account.\r Bits used to control the prefetch." + bit_offset: 8 + bit_size: 1 + - name: S_PRFTEN + description: "Smart prefetch enable. When bit value is modified, user must read back ACR register to be sure S_PRFTEN has been taken into account.\r Bits used to control the prefetch functionality." + bit_offset: 9 + bit_size: 1 fieldset/ECCCORR: description: FLASH Flash ECC correction register fields: - - name: ADDR_ECC - description: "ECC error address\r When an ECC error occurs (for single correction) during a read operation, the ADDR_ECC contains the address that generated the error.\r ADDR_ECC is reset when the flag error is reset.\r The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved.\r The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area)." - bit_offset: 0 - bit_size: 16 - - name: BK_ECC - description: "ECC bank flag for corrected ECC error\r It indicates which bank is concerned by ECC error" - bit_offset: 22 - bit_size: 1 - - name: SYSF_ECC - description: "ECC flag for corrected ECC error in system FLASH\r It indicates if system Flash memory is concerned by ECC error." - bit_offset: 23 - bit_size: 1 - - name: OTP_ECC - description: "OTP ECC error bit\r This bit is set to 1 when one single ECC correction occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield." - bit_offset: 24 - bit_size: 1 - - name: ECCCIE - description: "ECC single correction error interrupt enable bit When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation." - bit_offset: 25 - bit_size: 1 - - name: ECCC - description: "ECC correction set by hardware when single ECC error has been detected and corrected.\r Cleared by writing 1." - bit_offset: 30 - bit_size: 1 + - name: ADDR_ECC + description: "ECC error address\r When an ECC error occurs (for single correction) during a read operation, the ADDR_ECC contains the address that generated the error.\r ADDR_ECC is reset when the flag error is reset.\r The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved.\r The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area)." + bit_offset: 0 + bit_size: 16 + - name: BK_ECC + description: "ECC bank flag for corrected ECC error\r It indicates which bank is concerned by ECC error" + bit_offset: 22 + bit_size: 1 + - name: SYSF_ECC + description: "ECC flag for corrected ECC error in system FLASH\r It indicates if system Flash memory is concerned by ECC error." + bit_offset: 23 + bit_size: 1 + - name: OTP_ECC + description: "OTP ECC error bit\r This bit is set to 1 when one single ECC correction occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield." + bit_offset: 24 + bit_size: 1 + - name: ECCCIE + description: ECC single correction error interrupt enable bit When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation. + bit_offset: 25 + bit_size: 1 + - name: ECCC + description: "ECC correction set by hardware when single ECC error has been detected and corrected.\r Cleared by writing 1." + bit_offset: 30 + bit_size: 1 fieldset/ECCDETR: description: FLASH ECC detection register fields: - - name: ADDR_ECC - description: "ECC error address\r When an ECC error occurs (double detection) during a read operation, the ADDR_ECC contains the address that generated the error.\r ADDR_ECC is reset when the flag error is reset.\r The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an double ECC error is saved.\r The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area)." - bit_offset: 0 - bit_size: 16 - - name: BK_ECC - description: "ECC fail bank for double ECC Error\r It indicates which bank is concerned by ECC error" - bit_offset: 22 - bit_size: 1 - - name: SYSF_ECC - description: "ECC fail for double ECC error in system Flash memory\r It indicates if system Flash memory is concerned by ECC error." - bit_offset: 23 - bit_size: 1 - - name: OTP_ECC - description: "OTP ECC error bit\r This bit is set to 1 when double ECC detection occurred during the last read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bit field." - bit_offset: 24 - bit_size: 1 - - name: ECCD - description: "ECC detection set by hardware when two ECC error has been detected.\r When this bit is set, a NMI is generated.\r Cleared by writing 1. Needs to be cleared in order to detect subsequent double ECC errors." - bit_offset: 31 - bit_size: 1 + - name: ADDR_ECC + description: "ECC error address\r When an ECC error occurs (double detection) during a read operation, the ADDR_ECC contains the address that generated the error.\r ADDR_ECC is reset when the flag error is reset.\r The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an double ECC error is saved.\r The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area)." + bit_offset: 0 + bit_size: 16 + - name: BK_ECC + description: "ECC fail bank for double ECC Error\r It indicates which bank is concerned by ECC error" + bit_offset: 22 + bit_size: 1 + - name: SYSF_ECC + description: "ECC fail for double ECC error in system Flash memory\r It indicates if system Flash memory is concerned by ECC error." + bit_offset: 23 + bit_size: 1 + - name: OTP_ECC + description: "OTP ECC error bit\r This bit is set to 1 when double ECC detection occurred during the last read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bit field." + bit_offset: 24 + bit_size: 1 + - name: ECCD + description: "ECC detection set by hardware when two ECC error has been detected.\r When this bit is set, a NMI is generated.\r Cleared by writing 1. Needs to be cleared in order to detect subsequent double ECC errors." + bit_offset: 31 + bit_size: 1 fieldset/ECCDR: description: FLASH ECC data fields: - - name: DATA_ECC - description: "ECC error data\r When an double detection ECC error occurs on special areas with 6-bit ECC on 16-bit of data (data area, read-only/OTP area), the failing data is read to this register.\r By checking if it is possible to determine whether the failure was on a real data, or due to access to uninitialized memory." - bit_offset: 0 - bit_size: 16 + - name: DATA_ECC + description: "ECC error data\r When an double detection ECC error occurs on special areas with 6-bit ECC on 16-bit of data (data area, read-only/OTP area), the failing data is read to this register.\r By checking if it is possible to determine whether the failure was on a real data, or due to access to uninitialized memory." + bit_offset: 0 + bit_size: 16 fieldset/HDP1R: description: FLASH HDP Bank1 register fields: - - name: HDP1_STRT - description: HDPL barrier start set in number of 8 Kbytes sectors - bit_offset: 0 - bit_size: 3 - - name: HDP1_END - description: HDPL barrier end set in number of 8 Kbytes sectors - bit_offset: 16 - bit_size: 3 + - name: HDP1_STRT + description: HDPL barrier start set in number of 8 Kbytes sectors + bit_offset: 0 + bit_size: 3 + - name: HDP1_END + description: HDPL barrier end set in number of 8 Kbytes sectors + bit_offset: 16 + bit_size: 3 fieldset/HDP2R: description: FLASH HDP Bank2 register fields: - - name: HDP2_STRT - description: Bank 2 HDPL barrier start set in number of 8 Kbytes sectors - bit_offset: 0 - bit_size: 3 - - name: HDP2_END - description: Bank 2 HDPL barrier end set in number of 8 Kbytes sectors - bit_offset: 16 - bit_size: 3 + - name: HDP2_STRT + description: Bank 2 HDPL barrier start set in number of 8 Kbytes sectors + bit_offset: 0 + bit_size: 3 + - name: HDP2_END + description: Bank 2 HDPL barrier end set in number of 8 Kbytes sectors + bit_offset: 16 + bit_size: 3 fieldset/HDPEXTR: description: FLASH HDP extension register fields: - - name: HDP1_EXT - description: HDP area extension in 8 Kbytes sectors in Bank1. Extension is added after the HDP1_END sector. - bit_offset: 0 - bit_size: 3 - - name: HDP2_EXT - description: HDP area extension in 8 Kbytes sectors in Bank2. Extension is added after the HDP2_END sector. - bit_offset: 16 - bit_size: 3 + - name: HDP1_EXT + description: HDP area extension in 8 Kbytes sectors in Bank1. Extension is added after the HDP1_END sector. + bit_offset: 0 + bit_size: 3 + - name: HDP2_EXT + description: HDP area extension in 8 Kbytes sectors in Bank2. Extension is added after the HDP2_END sector. + bit_offset: 16 + bit_size: 3 fieldset/NSBOOTR: description: FLASH non-secure unique boot entry register fields: - - name: NSBOOT_LOCK - description: "A field locking the values of SWAP_BANK, and NSBOOTADD settings." - bit_offset: 0 - bit_size: 8 - enum: NSBOOTR_NSBOOT_LOCK - - name: NSBOOTADD - description: "unique boot entry address\r These bits reflect the UBE address" - bit_offset: 8 - bit_size: 24 + - name: NSBOOT_LOCK + description: A field locking the values of SWAP_BANK, and NSBOOTADD settings. + bit_offset: 0 + bit_size: 8 + enum: NSBOOTR_NSBOOT_LOCK + - name: NSBOOTADD + description: "unique boot entry address\r These bits reflect the UBE address" + bit_offset: 8 + bit_size: 24 fieldset/NSCCR: description: FLASH non-secure clear control register fields: - - name: CLR_EOP - description: "EOP flag clear bit\r Setting this bit to 1 resets to 0 EOP flag in FLASH_NSSR register." - bit_offset: 16 - bit_size: 1 - - name: CLR_WRPERR - description: "WRPERR flag clear bit\r Setting this bit to 1 resets to 0 WRPERR flag in FLASH_NSSR register." - bit_offset: 17 - bit_size: 1 - - name: CLR_PGSERR - description: "PGSERR flag clear bit\r Setting this bit to 1 resets to 0 PGSERR flag in FLASH_NSSR register." - bit_offset: 18 - bit_size: 1 - - name: CLR_STRBERR - description: "STRBERR flag clear bit\r Setting this bit to 1 resets to 0 STRBERR flag in FLASH_NSSR register." - bit_offset: 19 - bit_size: 1 - - name: CLR_INCERR - description: "INCERR flag clear bit\r Setting this bit to 1 resets to 0 INCERR flag in FLASH_NSSR register." - bit_offset: 20 - bit_size: 1 - - name: CLR_OPTCHANGEERR - description: Clear the flag corresponding flag in FLASH_NSSR by writing this bit. - bit_offset: 23 - bit_size: 1 + - name: CLR_EOP + description: "EOP flag clear bit\r Setting this bit to 1 resets to 0 EOP flag in FLASH_NSSR register." + bit_offset: 16 + bit_size: 1 + - name: CLR_WRPERR + description: "WRPERR flag clear bit\r Setting this bit to 1 resets to 0 WRPERR flag in FLASH_NSSR register." + bit_offset: 17 + bit_size: 1 + - name: CLR_PGSERR + description: "PGSERR flag clear bit\r Setting this bit to 1 resets to 0 PGSERR flag in FLASH_NSSR register." + bit_offset: 18 + bit_size: 1 + - name: CLR_STRBERR + description: "STRBERR flag clear bit\r Setting this bit to 1 resets to 0 STRBERR flag in FLASH_NSSR register." + bit_offset: 19 + bit_size: 1 + - name: CLR_INCERR + description: "INCERR flag clear bit\r Setting this bit to 1 resets to 0 INCERR flag in FLASH_NSSR register." + bit_offset: 20 + bit_size: 1 + - name: CLR_OPTCHANGEERR + description: Clear the flag corresponding flag in FLASH_NSSR by writing this bit. + bit_offset: 23 + bit_size: 1 fieldset/NSCR: description: FLASH Non Secure control register fields: - - name: LOCK - description: "configuration lock bit\r This bit locks the FLASH_NSCR register. The correct write sequence to FLASH_NSKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset.\r LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change." - bit_offset: 0 - bit_size: 1 - - name: PG - description: "programming control bit\r PG can be programmed only when LOCK is cleared to 0.\r PG allows programming in Bank1 and Bank2." - bit_offset: 1 - bit_size: 1 - - name: SER - description: "sector erase request\r Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0.\r If MER and SER are also set, a PGSERR is raised." - bit_offset: 2 - bit_size: 1 - - name: BER - description: "erase request\r Setting BER bit to 1 requests a bank erase operation (user Flash memory only). BER can be programmed only when LOCK is cleared to 0.\r If MER and SER are also set, a PGSERR is raised.\r Note: Write protection error is triggered when a bank erase is required and some sectors are protected." - bit_offset: 3 - bit_size: 1 - - name: FW - description: "write forcing control bit\r FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0.\r The embedded Flash memory resets FW when the corresponding operation has been acknowledged.\r Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error.\r Write forcing is effective only if the write buffer is not empty (in particular, FW does not start several write operations when the force-write operations are performed consecutively).\r Since there is just one write buffer, FW can force a write in bank1 or bank2." - bit_offset: 4 - bit_size: 1 - - name: STRT - description: "erase start control bit\r STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0.\r STRT is reset at the end of the operation or when an error occurs. It cannot be reseted by software." - bit_offset: 5 - bit_size: 1 - - name: SNB - description: "sector erase selection number\r These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0.\r ..." - bit_offset: 6 - bit_size: 3 - - name: MER - description: "Mass erase request\r Setting MER bit to 1 requests a mass erase operation (user Flash memory only). MER can be programmed only when LOCK is cleared to 0.\r If BER or SER are both set, a PGSERR is raised.\r Error is triggered when a mass erase is required and some sectors are protected." - bit_offset: 15 - bit_size: 1 - - name: EOPIE - description: "end of operation interrupt control bit\r Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program or erase operation. EOPIE can be programmed only when LOCK is cleared to 0." - bit_offset: 16 - bit_size: 1 - - name: WRPERRIE - description: "write protection error interrupt enable bit\r When WRPERRIE bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0." - bit_offset: 17 - bit_size: 1 - - name: PGSERRIE - description: "programming sequence error interrupt enable bit\r When PGSERRIE bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0." - bit_offset: 18 - bit_size: 1 - - name: STRBERRIE - description: "strobe error interrupt enable bit\r When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0." - bit_offset: 19 - bit_size: 1 - - name: INCERRIE - description: "inconsistency error interrupt enable bit\r When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0." - bit_offset: 20 - bit_size: 1 - - name: OPTCHANGEERRIE - description: "Option byte change error interrupt enable bit\r OPTCHANGEERRIE bit controls if an interrupt has to be generated when an error occurs during an option byte change. This bit can be programmed only when LOCK bit is cleared to 0." - bit_offset: 23 - bit_size: 1 - - name: BKSEL - description: "Bank selector bit\r BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored." - bit_offset: 31 - bit_size: 1 - enum: BKSEL + - name: LOCK + description: "configuration lock bit\r This bit locks the FLASH_NSCR register. The correct write sequence to FLASH_NSKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset.\r LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change." + bit_offset: 0 + bit_size: 1 + - name: PG + description: "programming control bit\r PG can be programmed only when LOCK is cleared to 0.\r PG allows programming in Bank1 and Bank2." + bit_offset: 1 + bit_size: 1 + - name: SER + description: "sector erase request\r Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0.\r If MER and SER are also set, a PGSERR is raised." + bit_offset: 2 + bit_size: 1 + - name: BER + description: "erase request\r Setting BER bit to 1 requests a bank erase operation (user Flash memory only). BER can be programmed only when LOCK is cleared to 0.\r If MER and SER are also set, a PGSERR is raised.\r Note: Write protection error is triggered when a bank erase is required and some sectors are protected." + bit_offset: 3 + bit_size: 1 + - name: FW + description: "write forcing control bit\r FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0.\r The embedded Flash memory resets FW when the corresponding operation has been acknowledged.\r Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error.\r Write forcing is effective only if the write buffer is not empty (in particular, FW does not start several write operations when the force-write operations are performed consecutively).\r Since there is just one write buffer, FW can force a write in bank1 or bank2." + bit_offset: 4 + bit_size: 1 + - name: STRT + description: "erase start control bit\r STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0.\r STRT is reset at the end of the operation or when an error occurs. It cannot be reseted by software." + bit_offset: 5 + bit_size: 1 + - name: SNB + description: "sector erase selection number\r These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0.\r ..." + bit_offset: 6 + bit_size: 3 + - name: MER + description: "Mass erase request\r Setting MER bit to 1 requests a mass erase operation (user Flash memory only). MER can be programmed only when LOCK is cleared to 0.\r If BER or SER are both set, a PGSERR is raised.\r Error is triggered when a mass erase is required and some sectors are protected." + bit_offset: 15 + bit_size: 1 + - name: EOPIE + description: "end of operation interrupt control bit\r Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program or erase operation. EOPIE can be programmed only when LOCK is cleared to 0." + bit_offset: 16 + bit_size: 1 + - name: WRPERRIE + description: "write protection error interrupt enable bit\r When WRPERRIE bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 17 + bit_size: 1 + - name: PGSERRIE + description: "programming sequence error interrupt enable bit\r When PGSERRIE bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 18 + bit_size: 1 + - name: STRBERRIE + description: "strobe error interrupt enable bit\r When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 19 + bit_size: 1 + - name: INCERRIE + description: "inconsistency error interrupt enable bit\r When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0." + bit_offset: 20 + bit_size: 1 + - name: OPTCHANGEERRIE + description: "Option byte change error interrupt enable bit\r OPTCHANGEERRIE bit controls if an interrupt has to be generated when an error occurs during an option byte change. This bit can be programmed only when LOCK bit is cleared to 0." + bit_offset: 23 + bit_size: 1 + - name: BKSEL + description: "Bank selector bit\r BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored." + bit_offset: 31 + bit_size: 1 + enum: BKSEL fieldset/NSKEYR: description: FLASH key register fields: - - name: NSKEY - description: Non-volatile memory configuration access unlock key - bit_offset: 0 - bit_size: 32 + - name: NSKEY + description: Non-volatile memory configuration access unlock key + bit_offset: 0 + bit_size: 32 fieldset/NSSR: description: FLASH non-secure status register fields: - - name: BSY - description: "busy flag\r BSY flag indicates that a Flash memory is busy by an operation (write, erase, option byte change). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs." - bit_offset: 0 - bit_size: 1 - - name: WBNE - description: "write buffer not empty flag\r WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below:\r the application software forces the write operation using FW bit in FLASH_NSCR\r the embedded Flash memory detects an error that involves data loss\r This bit cannot be reset by software writing 0 directly. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data." - bit_offset: 1 - bit_size: 1 - - name: DBNE - description: "data buffer not empty flag\r DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free." - bit_offset: 3 - bit_size: 1 - - name: EOP - description: "end of operation flag\r EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to 1. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_NSCCR register." - bit_offset: 16 - bit_size: 1 - - name: WRPERR - description: "write protection error flag\r WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_NSCCR register clears WRPERR." - bit_offset: 17 - bit_size: 1 - - name: PGSERR - description: "programming sequence error flag\r PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_NSCCR register clears PGSERR." - bit_offset: 18 - bit_size: 1 - - name: STRBERR - description: "strobe error flag\r STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_NSCCR register clears STRBERR." - bit_offset: 19 - bit_size: 1 - - name: INCERR - description: "inconsistency error flag\r INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_NSCCR register clears INCERR." - bit_offset: 20 - bit_size: 1 - - name: OPTCHANGEERR - description: "Option byte change error flag\r OPTCHANGEERR flag indicates that an error occurred during an option byte change operation. When OPTCHANGEERR is set to 1, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTCHANGEERRIE bit of FLASH_NSCR register is set to 1.\r Writing 1 to CLR_OPTCHANGEERR of register FLASH_CCR clears OPTCHANGEERR.\r Note: The OPTSTRT bit in FLASH_OPTCR cannot be set while OPTCHANGEERR is set." - bit_offset: 23 - bit_size: 1 + - name: BSY + description: "busy flag\r BSY flag indicates that a Flash memory is busy by an operation (write, erase, option byte change). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs." + bit_offset: 0 + bit_size: 1 + - name: WBNE + description: "write buffer not empty flag\r WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below:\r the application software forces the write operation using FW bit in FLASH_NSCR\r the embedded Flash memory detects an error that involves data loss\r This bit cannot be reset by software writing 0 directly. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data." + bit_offset: 1 + bit_size: 1 + - name: DBNE + description: "data buffer not empty flag\r DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free." + bit_offset: 3 + bit_size: 1 + - name: EOP + description: "end of operation flag\r EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to 1. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_NSCCR register." + bit_offset: 16 + bit_size: 1 + - name: WRPERR + description: "write protection error flag\r WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_NSCCR register clears WRPERR." + bit_offset: 17 + bit_size: 1 + - name: PGSERR + description: "programming sequence error flag\r PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_NSCCR register clears PGSERR." + bit_offset: 18 + bit_size: 1 + - name: STRBERR + description: "strobe error flag\r STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_NSCCR register clears STRBERR." + bit_offset: 19 + bit_size: 1 + - name: INCERR + description: "inconsistency error flag\r INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_NSCCR register clears INCERR." + bit_offset: 20 + bit_size: 1 + - name: OPTCHANGEERR + description: "Option byte change error flag\r OPTCHANGEERR flag indicates that an error occurred during an option byte change operation. When OPTCHANGEERR is set to 1, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTCHANGEERRIE bit of FLASH_NSCR register is set to 1.\r Writing 1 to CLR_OPTCHANGEERR of register FLASH_CCR clears OPTCHANGEERR.\r Note: The OPTSTRT bit in FLASH_OPTCR cannot be set while OPTCHANGEERR is set." + bit_offset: 23 + bit_size: 1 fieldset/OPSR: description: FLASH operation status register fields: - - name: ADDR_OP - description: Interrupted operation address. - bit_offset: 0 - bit_size: 20 - - name: BK_OP - description: "Interrupted operation bank\r It indicates which bank was concerned by operation." - bit_offset: 22 - bit_size: 1 - - name: SYSF_OP - description: "Operation in system Flash memory interrupted\r Indicates that reset interrupted an ongoing operation in System Flash." - bit_offset: 23 - bit_size: 1 - - name: OTP_OP - description: "OTP operation interrupted\r Indicates that reset interrupted an ongoing operation in OTP area." - bit_offset: 24 - bit_size: 1 - - name: CODE_OP - description: Flash memory operation code - bit_offset: 29 - bit_size: 3 - enum: CODE_OP + - name: ADDR_OP + description: Interrupted operation address. + bit_offset: 0 + bit_size: 20 + - name: BK_OP + description: "Interrupted operation bank\r It indicates which bank was concerned by operation." + bit_offset: 22 + bit_size: 1 + - name: SYSF_OP + description: "Operation in system Flash memory interrupted\r Indicates that reset interrupted an ongoing operation in System Flash." + bit_offset: 23 + bit_size: 1 + - name: OTP_OP + description: "OTP operation interrupted\r Indicates that reset interrupted an ongoing operation in OTP area." + bit_offset: 24 + bit_size: 1 + - name: CODE_OP + description: Flash memory operation code + bit_offset: 29 + bit_size: 3 + enum: CODE_OP fieldset/OPTCR: description: FLASH option control register fields: - - name: OPTLOCK - description: "FLASH_OPTCR lock option configuration bit\r The OPTLOCK bit locks the FLASH_OPTCR register as well as all _PRG registers. The correct write sequence to FLASH_OPTKEYR register unlocks this bit. If a wrong sequence is executed, or the unlock sequence to FLASH_OPTKEYR is performed twice, this bit remains locked until next system reset.\r It is possible to set OPTLOCK by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When OPTLOCK changes from 0 to 1, the others bits of FLASH_OPTCR register do not change." - bit_offset: 0 - bit_size: 1 - - name: OPTSTRT - description: "Option byte start change option configuration bit\r OPTSTRT triggers an option byte change operation. The user can set OPTSTRT only when the OPTLOCK bit is cleared to 0. It’s set only by Software and cleared when the option byte change is completed or an error occurs (PGSERR or OPTCHANGEERR). It’s reseted at the same time as BSY bit.\r The user application cannot modify any FLASH_XXX_PRG embedded Flash memory register until the option change operation has been completed.\r Before setting this bit, the user has to write the required values in the FLASH_XXX_PRG registers. The FLASH_XXX_PRG registers are locked until the option byte change operation has been executed in non-volatile memory." - bit_offset: 1 - bit_size: 1 - - name: SWAP_BANK - description: "Bank swapping option configuration bit\r SWAP_BANK controls whether Bank1 and Bank2 are swapped or not. This bit is loaded with the SWAP_BANK bit of FLASH_OPTSR_CUR register only after reset or POR." - bit_offset: 31 - bit_size: 1 - enum: OPTCR_SWAP_BANK + - name: OPTLOCK + description: "FLASH_OPTCR lock option configuration bit\r The OPTLOCK bit locks the FLASH_OPTCR register as well as all _PRG registers. The correct write sequence to FLASH_OPTKEYR register unlocks this bit. If a wrong sequence is executed, or the unlock sequence to FLASH_OPTKEYR is performed twice, this bit remains locked until next system reset.\r It is possible to set OPTLOCK by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When OPTLOCK changes from 0 to 1, the others bits of FLASH_OPTCR register do not change." + bit_offset: 0 + bit_size: 1 + - name: OPTSTRT + description: "Option byte start change option configuration bit\r OPTSTRT triggers an option byte change operation. The user can set OPTSTRT only when the OPTLOCK bit is cleared to 0. It’s set only by Software and cleared when the option byte change is completed or an error occurs (PGSERR or OPTCHANGEERR). It’s reseted at the same time as BSY bit.\r The user application cannot modify any FLASH_XXX_PRG embedded Flash memory register until the option change operation has been completed.\r Before setting this bit, the user has to write the required values in the FLASH_XXX_PRG registers. The FLASH_XXX_PRG registers are locked until the option byte change operation has been executed in non-volatile memory." + bit_offset: 1 + bit_size: 1 + - name: SWAP_BANK + description: "Bank swapping option configuration bit\r SWAP_BANK controls whether Bank1 and Bank2 are swapped or not. This bit is loaded with the SWAP_BANK bit of FLASH_OPTSR_CUR register only after reset or POR." + bit_offset: 31 + bit_size: 1 + enum: OPTCR_SWAP_BANK fieldset/OPTKEYR: description: FLASH option key register fields: - - name: OPTKEY - description: FLASH option bytes control access unlock key - bit_offset: 0 - bit_size: 32 + - name: OPTKEY + description: FLASH option bytes control access unlock key + bit_offset: 0 + bit_size: 32 fieldset/OPTSR: description: FLASH option status register fields: - - name: BOR_LEV - description: "Brownout level option status bit\r These bits reflects the power level that generates a system reset." - bit_offset: 0 - bit_size: 2 - enum: OPTSR_BOR_LEV - - name: BORH_EN - description: Brownout high enable status bit - bit_offset: 2 - bit_size: 1 - - name: IWDG_SW - description: IWDG control mode option status bit - bit_offset: 3 - bit_size: 1 - enum: OPTSR_IWDG_SW - - name: WWDG_SW - description: WWDG control mode option status bit - bit_offset: 4 - bit_size: 1 - enum: OPTSR_WWDG_SW - - name: NRST_SHDW - description: Core domain Shutdown entry reset option status bit - bit_offset: 5 - bit_size: 1 - enum: OPTSR_NRST_SHDW - - name: NRST_STOP - description: Core domain Stop entry reset option status bit - bit_offset: 6 - bit_size: 1 - enum: OPTSR_NRST_STOP - - name: NRST_STDBY - description: Core domain Standby entry reset option status bit - bit_offset: 7 - bit_size: 1 - enum: OPTSR_NRST_STDBY - - name: PRODUCT_STATE - description: "Life state code (based on Hamming 8,4). More information in ." - bit_offset: 8 - bit_size: 8 - - name: IO_VDD_HSLV - description: High-speed IO at low VDD voltage status bit. This bit can be set only with VDD below 2.5 V. - bit_offset: 16 - bit_size: 1 - enum: OPTSR_IO_VDD_HSLV - - name: IO_VDDIO2_HSLV - description: High-speed IO at low VDDIO2 voltage status bit. This bit can be set only with VDDIO2 below 2.5 V. - bit_offset: 17 - bit_size: 1 - enum: OPTSR_IO_VDDIO_HSLV - - name: IWDG_STOP - description: "IWDG Stop mode freeze option status bit\r When set the independent watchdog IWDG is in system Stop mode." - bit_offset: 20 - bit_size: 1 - enum: OPTSR_IWDG_STOP - - name: IWDG_STDBY - description: "IWDG Standby mode freeze option status bit\r When set the independent watchdog IWDG is frozen in system Standby mode." - bit_offset: 21 - bit_size: 1 - enum: OPTSR_IWDG_STDBY - - name: SWAP_BANK - description: "Bank swapping option status bit\r SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not.\r SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset." - bit_offset: 31 - bit_size: 1 - enum: OPTSR_SWAP_BANK + - name: BOR_LEV + description: "Brownout level option status bit\r These bits reflects the power level that generates a system reset." + bit_offset: 0 + bit_size: 2 + enum: OPTSR_BOR_LEV + - name: BORH_EN + description: Brownout high enable status bit + bit_offset: 2 + bit_size: 1 + - name: IWDG_SW + description: IWDG control mode option status bit + bit_offset: 3 + bit_size: 1 + enum: OPTSR_IWDG_SW + - name: WWDG_SW + description: WWDG control mode option status bit + bit_offset: 4 + bit_size: 1 + enum: OPTSR_WWDG_SW + - name: NRST_SHDW + description: Core domain Shutdown entry reset option status bit + bit_offset: 5 + bit_size: 1 + enum: OPTSR_NRST_SHDW + - name: NRST_STOP + description: Core domain Stop entry reset option status bit + bit_offset: 6 + bit_size: 1 + enum: OPTSR_NRST_STOP + - name: NRST_STDBY + description: Core domain Standby entry reset option status bit + bit_offset: 7 + bit_size: 1 + enum: OPTSR_NRST_STDBY + - name: PRODUCT_STATE + description: Life state code (based on Hamming 8,4). More information in . + bit_offset: 8 + bit_size: 8 + - name: IO_VDD_HSLV + description: High-speed IO at low VDD voltage status bit. This bit can be set only with VDD below 2.5 V. + bit_offset: 16 + bit_size: 1 + enum: OPTSR_IO_VDD_HSLV + - name: IO_VDDIO2_HSLV + description: High-speed IO at low VDDIO2 voltage status bit. This bit can be set only with VDDIO2 below 2.5 V. + bit_offset: 17 + bit_size: 1 + enum: OPTSR_IO_VDDIO_HSLV + - name: IWDG_STOP + description: "IWDG Stop mode freeze option status bit\r When set the independent watchdog IWDG is in system Stop mode." + bit_offset: 20 + bit_size: 1 + enum: OPTSR_IWDG_STOP + - name: IWDG_STDBY + description: "IWDG Standby mode freeze option status bit\r When set the independent watchdog IWDG is frozen in system Standby mode." + bit_offset: 21 + bit_size: 1 + enum: OPTSR_IWDG_STDBY + - name: SWAP_BANK + description: "Bank swapping option status bit\r SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not.\r SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset." + bit_offset: 31 + bit_size: 1 + enum: OPTSR_SWAP_BANK fieldset/OPTSR2: description: FLASH option status register 2 fields: - - name: SRAM2_RST - description: SRAM2 erase when system reset - bit_offset: 3 - bit_size: 1 - - name: BKPRAM_ECC - description: Backup RAM ECC detection and correction disable - bit_offset: 4 - bit_size: 1 - enum: OPTSR_BKPRAM_ECC - - name: SRAM2_ECC - description: SRAM2 ECC detection and correction disable - bit_offset: 6 - bit_size: 1 - enum: OPTSR_SRAM_ECC - - name: SRAM1_RST - description: SRAM1 erase upon system reset - bit_offset: 9 - bit_size: 1 - - name: SRAM1_ECC - description: SRAM1 ECC detection and correction disable - bit_offset: 10 - bit_size: 1 - enum: OPTSR_SRAM_ECC + - name: SRAM2_RST + description: SRAM2 erase when system reset + bit_offset: 3 + bit_size: 1 + - name: BKPRAM_ECC + description: Backup RAM ECC detection and correction disable + bit_offset: 4 + bit_size: 1 + enum: OPTSR_BKPRAM_ECC + - name: SRAM2_ECC + description: SRAM2 ECC detection and correction disable + bit_offset: 6 + bit_size: 1 + enum: OPTSR_SRAM_ECC + - name: SRAM1_RST + description: SRAM1 erase upon system reset + bit_offset: 9 + bit_size: 1 + - name: SRAM1_ECC + description: SRAM1 ECC detection and correction disable + bit_offset: 10 + bit_size: 1 + enum: OPTSR_SRAM_ECC fieldset/OTPBLR: description: FLASH non-secure OTP block lock fields: - - name: LOCKBL - description: "OTP block lock\r Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31.\r LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR.\r LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked.\r When one block is locked, it is not possible to remove the write protection.\r LOCKBL bits can be set if the corresponding bit in FLASH_OTPBLR_CUR is cleared." - bit_offset: 0 - bit_size: 32 + - name: LOCKBL + description: "OTP block lock\r Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31.\r LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR.\r LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked.\r When one block is locked, it is not possible to remove the write protection.\r LOCKBL bits can be set if the corresponding bit in FLASH_OTPBLR_CUR is cleared." + bit_offset: 0 + bit_size: 32 fieldset/PRIVBB: description: FLASH privilege register for bank 1 fields: - - name: PRIVBB - description: Privileged / unprivileged 8 Kbytes Flash Bank1 sector attribute (y = 0 to 7) - bit_offset: 0 - bit_size: 8 - enum: PRIVBB + - name: PRIVBB + description: Privileged / unprivileged 8 Kbytes Flash Bank1 sector attribute (y = 0 to 7) + bit_offset: 0 + bit_size: 8 + enum: PRIVBB fieldset/PRIVCFGR: description: FLASH privilege configuration register fields: - - name: NSPRIV - description: privilege attribute for non secure registers - bit_offset: 1 - bit_size: 1 - enum: NSPRIV + - name: NSPRIV + description: privilege attribute for non secure registers + bit_offset: 1 + bit_size: 1 + enum: NSPRIV fieldset/SECSR: description: FLASH secure status register fields: - - name: SECBSY - description: "busy flag\r BSY flag indicates that a FLASH memory is busy by an operation (write, erase, option byte change, OBK operations, PUF operation). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs." - bit_offset: 0 - bit_size: 1 - - name: SECWBNE - description: "write buffer not empty flag\r WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below:\r the application software forces the write operation using FW bit in FLASH_SECCR\r the embedded Flash memory detects an error that involves data loss\r This bit cannot be reset by writing 0 directly by software. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data." - bit_offset: 1 - bit_size: 1 - - name: SECDBNE - description: "data buffer not empty flag\r DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free." - bit_offset: 3 - bit_size: 1 - - name: SECEOP - description: "end of operation flag\r EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_SECCCR register." - bit_offset: 16 - bit_size: 1 - - name: SECWRPERR - description: "write protection error flag\r WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_SECCCR register clears WRPERR." - bit_offset: 17 - bit_size: 1 - - name: SECPGSERR - description: "programming sequence error flag\r PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_SECCCR register clears PGSERR." - bit_offset: 18 - bit_size: 1 - - name: SECSTRBERR - description: "strobe error flag\r STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_SECCCR register clears STRBERR." - bit_offset: 19 - bit_size: 1 - - name: SECINCERR - description: "inconsistency error flag\r INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_SECCCR register clears INCERR." - bit_offset: 20 - bit_size: 1 + - name: SECBSY + description: "busy flag\r BSY flag indicates that a FLASH memory is busy by an operation (write, erase, option byte change, OBK operations, PUF operation). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs." + bit_offset: 0 + bit_size: 1 + - name: SECWBNE + description: "write buffer not empty flag\r WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below:\r the application software forces the write operation using FW bit in FLASH_SECCR\r the embedded Flash memory detects an error that involves data loss\r This bit cannot be reset by writing 0 directly by software. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data." + bit_offset: 1 + bit_size: 1 + - name: SECDBNE + description: "data buffer not empty flag\r DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free." + bit_offset: 3 + bit_size: 1 + - name: SECEOP + description: "end of operation flag\r EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_SECCCR register." + bit_offset: 16 + bit_size: 1 + - name: SECWRPERR + description: "write protection error flag\r WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_SECCCR register clears WRPERR." + bit_offset: 17 + bit_size: 1 + - name: SECPGSERR + description: "programming sequence error flag\r PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_SECCCR register clears PGSERR." + bit_offset: 18 + bit_size: 1 + - name: SECSTRBERR + description: "strobe error flag\r STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_SECCCR register clears STRBERR." + bit_offset: 19 + bit_size: 1 + - name: SECINCERR + description: "inconsistency error flag\r INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_SECCCR register clears INCERR." + bit_offset: 20 + bit_size: 1 fieldset/WRP: description: FLASH write sector protection for Bank2 fields: - - name: WRPSG - description: "Bank2 sector protection option status byte\r Setting WRPSG2 bits to 0 write protects the corresponding sectors in bank 2 (0: write protected; 1: not write protected)" - bit_offset: 0 - bit_size: 8 + - name: WRPSG + description: "Bank2 sector protection option status byte\r Setting WRPSG2 bits to 0 write protects the corresponding sectors in bank 2 (0: write protected; 1: not write protected)" + bit_offset: 0 + bit_size: 8 enum/BKSEL: bit_size: 1 variants: - - name: B_0x0 - description: Bank1 is selected for Bank erase / sector erase / interrupt enable - value: 0 - - name: B_0x1 - description: Bank2 is selected for BER / SER - value: 1 + - name: B_0x0 + description: Bank1 is selected for Bank erase / sector erase / interrupt enable + value: 0 + - name: B_0x1 + description: Bank2 is selected for BER / SER + value: 1 enum/CODE_OP: bit_size: 3 variants: - - name: B_0x0 - description: No Flash operation on going during previous reset - value: 0 - - name: B_0x1 - description: Single write operation interrupted - value: 1 - - name: B_0x3 - description: Sector erase operation interrupted - value: 3 - - name: B_0x4 - description: Bank erase operation interrupted - value: 4 - - name: B_0x5 - description: Mass erase operation interrupted - value: 5 - - name: B_0x6 - description: Option change operation interrupted - value: 6 + - name: B_0x0 + description: No Flash operation on going during previous reset + value: 0 + - name: B_0x1 + description: Single write operation interrupted + value: 1 + - name: B_0x3 + description: Sector erase operation interrupted + value: 3 + - name: B_0x4 + description: Bank erase operation interrupted + value: 4 + - name: B_0x5 + description: Mass erase operation interrupted + value: 5 + - name: B_0x6 + description: Option change operation interrupted + value: 6 enum/NSBOOTR_NSBOOT_LOCK: bit_size: 8 variants: - - name: B_0xB4 - description: The NSBOOTADD and SWAP_BANK are frozen. - value: 180 - - name: B_0xC3 - description: The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. - value: 195 + - name: B_0xB4 + description: The NSBOOTADD and SWAP_BANK are frozen. + value: 180 + - name: B_0xC3 + description: The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. + value: 195 enum/NSPRIV: bit_size: 1 variants: - - name: B_0x0 - description: access to non secure registers is always granted - value: 0 - - name: B_0x1 - description: access to non secure registers is denied in case of non privileged access. - value: 1 + - name: B_0x0 + description: access to non secure registers is always granted + value: 0 + - name: B_0x1 + description: access to non secure registers is denied in case of non privileged access. + value: 1 enum/OPTCR_SWAP_BANK: bit_size: 1 variants: - - name: B_0x0 - description: Bank1 and Bank2 not swapped - value: 0 - - name: B_0x1 - description: Bank1 and Bank2 swapped - value: 1 + - name: B_0x0 + description: Bank1 and Bank2 not swapped + value: 0 + - name: B_0x1 + description: Bank1 and Bank2 swapped + value: 1 enum/OPTSR_BKPRAM_ECC: bit_size: 1 variants: - - name: B_0x0 - description: BKPRAM ECC check enabled - value: 0 - - name: B_0x1 - description: BKPRAM ECC check disabled - value: 1 + - name: B_0x0 + description: BKPRAM ECC check enabled + value: 0 + - name: B_0x1 + description: BKPRAM ECC check disabled + value: 1 enum/OPTSR_BOR_LEV: bit_size: 2 variants: - - name: B_0x0 - description: "BOR OFF, POR/PDR reset threshold level is applied" - value: 0 - - name: B_0x1 - description: "BOR Level 1, the threshold level is low (around 2.1 V)" - value: 1 - - name: B_0x2 - description: "BOR Level 2, the threshold level is medium (around 2.4 V)" - value: 2 - - name: B_0x3 - description: "BOR Level 3, the threshold level is high (around 2.7 V)" - value: 3 + - name: B_0x0 + description: BOR OFF, POR/PDR reset threshold level is applied + value: 0 + - name: B_0x1 + description: BOR Level 1, the threshold level is low (around 2.1 V) + value: 1 + - name: B_0x2 + description: BOR Level 2, the threshold level is medium (around 2.4 V) + value: 2 + - name: B_0x3 + description: BOR Level 3, the threshold level is high (around 2.7 V) + value: 3 enum/OPTSR_IO_VDDIO_HSLV: bit_size: 1 variants: - - name: B_0x0 - description: High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) - value: 0 - - name: B_0x1 - description: High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - value: 1 + - name: B_0x0 + description: High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) + value: 0 + - name: B_0x1 + description: High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) + value: 1 enum/OPTSR_IO_VDD_HSLV: bit_size: 1 variants: - - name: B_0x0 - description: High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) - value: 0 - - name: B_0x1 - description: High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) - value: 1 + - name: B_0x0 + description: High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) + value: 0 + - name: B_0x1 + description: High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) + value: 1 enum/OPTSR_IWDG_STDBY: bit_size: 1 variants: - - name: B_0x0 - description: Independent watchdog frozen in Standby mode - value: 0 - - name: B_0x1 - description: Independent watchdog keep running in Standby mode. - value: 1 + - name: B_0x0 + description: Independent watchdog frozen in Standby mode + value: 0 + - name: B_0x1 + description: Independent watchdog keep running in Standby mode. + value: 1 enum/OPTSR_IWDG_STOP: bit_size: 1 variants: - - name: B_0x0 - description: Independent watchdog frozen in system Stop mode - value: 0 - - name: B_0x1 - description: Independent watchdog keep running in system Stop mode. - value: 1 + - name: B_0x0 + description: Independent watchdog frozen in system Stop mode + value: 0 + - name: B_0x1 + description: Independent watchdog keep running in system Stop mode. + value: 1 enum/OPTSR_IWDG_SW: bit_size: 1 variants: - - name: B_0x0 - description: IWDG watchdog is controlled by hardware - value: 0 - - name: B_0x1 - description: IWDG watchdog is controlled by software - value: 1 + - name: B_0x0 + description: IWDG watchdog is controlled by hardware + value: 0 + - name: B_0x1 + description: IWDG watchdog is controlled by software + value: 1 enum/OPTSR_NRST_SHDW: bit_size: 1 variants: - - name: B_0x0 - description: a reset is generated when entering Shutdown mode on core domain - value: 0 - - name: B_0x1 - description: no reset generated when entering Shutdown mode on core domain. - value: 1 + - name: B_0x0 + description: a reset is generated when entering Shutdown mode on core domain + value: 0 + - name: B_0x1 + description: no reset generated when entering Shutdown mode on core domain. + value: 1 enum/OPTSR_NRST_STDBY: bit_size: 1 variants: - - name: B_0x0 - description: a reset is generated when entering Standby mode on core domain - value: 0 - - name: B_0x1 - description: no reset generated when entering Standby mode on core domain. - value: 1 + - name: B_0x0 + description: a reset is generated when entering Standby mode on core domain + value: 0 + - name: B_0x1 + description: no reset generated when entering Standby mode on core domain. + value: 1 enum/OPTSR_NRST_STOP: bit_size: 1 variants: - - name: B_0x0 - description: a reset is generated when entering Stop mode on core domain - value: 0 - - name: B_0x1 - description: no reset generated when entering Stop mode on core domain. - value: 1 + - name: B_0x0 + description: a reset is generated when entering Stop mode on core domain + value: 0 + - name: B_0x1 + description: no reset generated when entering Stop mode on core domain. + value: 1 enum/OPTSR_SRAM_ECC: bit_size: 1 variants: - - name: B_0x0 - description: SRAM2 ECC check enabled - value: 0 - - name: B_0x1 - description: SRAM2 ECC check disabled - value: 1 + - name: B_0x0 + description: SRAM2 ECC check enabled + value: 0 + - name: B_0x1 + description: SRAM2 ECC check disabled + value: 1 enum/OPTSR_SWAP_BANK: bit_size: 1 variants: - - name: B_0x0 - description: Bank1 and Bank2 not swapped - value: 0 - - name: B_0x1 - description: Bank1 and Bank2 swapped - value: 1 + - name: B_0x0 + description: Bank1 and Bank2 not swapped + value: 0 + - name: B_0x1 + description: Bank1 and Bank2 swapped + value: 1 enum/OPTSR_WWDG_SW: bit_size: 1 variants: - - name: B_0x0 - description: WWDG watchdog is controlled by hardware - value: 0 - - name: B_0x1 - description: WWDG watchdog is controlled by software - value: 1 + - name: B_0x0 + description: WWDG watchdog is controlled by hardware + value: 0 + - name: B_0x1 + description: WWDG watchdog is controlled by software + value: 1 enum/PRIVBB: bit_size: 8 variants: - - name: B_0x0 - description: sectors y in bank 1 is non privileged - value: 0 - - name: B_0x1 - description: sector y in bank 1 is privileged - value: 1 + - name: B_0x0 + description: sectors y in bank 1 is non privileged + value: 0 + - name: B_0x1 + description: sector y in bank 1 is privileged + value: 1 diff --git a/data/registers/flash_h7.yaml b/data/registers/flash_h7.yaml index 28363b1..ae442bc 100644 --- a/data/registers/flash_h7.yaml +++ b/data/registers/flash_h7.yaml @@ -1,637 +1,648 @@ ---- block/BANK: - description: "Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R" + description: Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R items: - - name: KEYR - description: FLASH key register for bank 1 - byte_offset: 0 - access: Write - fieldset: KEYR - - name: CR - description: FLASH control register for bank 1 - byte_offset: 8 - fieldset: CR - - name: SR - description: FLASH status register for bank 1 - byte_offset: 12 - fieldset: SR - - name: CCR - description: FLASH clear control register for bank 1 - byte_offset: 16 - fieldset: CCR - - name: PRAR_CUR - description: FLASH protection address for bank 1 - byte_offset: 36 - access: Read - fieldset: PRAR_CUR - - name: PRAR_PRG - description: FLASH protection address for bank 1 - byte_offset: 40 - fieldset: PRAR_PRG - - name: SCAR_CUR - description: FLASH secure address for bank 1 - byte_offset: 44 - fieldset: SCAR_CUR - - name: SCAR_PRG - description: FLASH secure address for bank 1 - byte_offset: 48 - fieldset: SCAR_PRG - - name: WPSN_CURR - description: FLASH write sector protection for bank 1 - byte_offset: 52 - access: Read - fieldset: WPSN_CURR - - name: WPSN_PRGR - description: FLASH write sector protection for bank 1 - byte_offset: 56 - fieldset: WPSN_PRGR - - name: CRCCR - description: FLASH CRC control register for bank 1 - byte_offset: 76 - fieldset: CRCCR - - name: CRCSADDR - description: FLASH CRC start address register for bank 1 - byte_offset: 80 - fieldset: CRCSADDR - - name: CRCEADDR - description: FLASH CRC end address register for bank 1 - byte_offset: 84 - fieldset: CRCEADDR - - name: FAR - description: FLASH ECC fail address for bank 1 - byte_offset: 92 - access: Read - fieldset: FAR + - name: KEYR + description: FLASH key register for bank 1 + byte_offset: 0 + access: Write + fieldset: KEYR + - name: CR + description: FLASH control register for bank 1 + byte_offset: 8 + fieldset: CR + - name: SR + description: FLASH status register for bank 1 + byte_offset: 12 + fieldset: SR + - name: CCR + description: FLASH clear control register for bank 1 + byte_offset: 16 + fieldset: CCR + - name: PRAR_CUR + description: FLASH protection address for bank 1 + byte_offset: 36 + access: Read + fieldset: PRAR_CUR + - name: PRAR_PRG + description: FLASH protection address for bank 1 + byte_offset: 40 + fieldset: PRAR_PRG + - name: SCAR_CUR + description: FLASH secure address for bank 1 + byte_offset: 44 + fieldset: SCAR_CUR + - name: SCAR_PRG + description: FLASH secure address for bank 1 + byte_offset: 48 + fieldset: SCAR_PRG + - name: WPSN_CURR + description: FLASH write sector protection for bank 1 + byte_offset: 52 + access: Read + fieldset: WPSN_CURR + - name: WPSN_PRGR + description: FLASH write sector protection for bank 1 + byte_offset: 56 + fieldset: WPSN_PRGR + - name: CRCCR + description: FLASH CRC control register for bank 1 + byte_offset: 76 + fieldset: CRCCR + - name: CRCSADDR + description: FLASH CRC start address register for bank 1 + byte_offset: 80 + fieldset: CRCSADDR + - name: CRCEADDR + description: FLASH CRC end address register for bank 1 + byte_offset: 84 + fieldset: CRCEADDR + - name: FAR + description: FLASH ECC fail address for bank 1 + byte_offset: 92 + access: Read + fieldset: FAR block/FLASH: description: Flash items: - - name: ACR - description: Access control register - byte_offset: 0 - fieldset: ACR - - name: BANK - description: "Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R" - array: - len: 2 - stride: 256 - byte_offset: 4 - block: BANK - - name: OPTKEYR - description: FLASH option key register - byte_offset: 8 - fieldset: OPTKEYR - - name: OPTCR - description: FLASH option control register - byte_offset: 24 - fieldset: OPTCR - - name: OPTSR_CUR - description: FLASH option status register - byte_offset: 28 - fieldset: OPTSR_CUR - - name: OPTSR_PRG - description: FLASH option status register - byte_offset: 32 - fieldset: OPTSR_PRG - - name: OPTCCR - description: FLASH option clear control register - byte_offset: 36 - access: Write - fieldset: OPTCCR - - name: BOOT_CURR - description: FLASH register with boot address - byte_offset: 64 - access: Read - fieldset: BOOT_CURR - - name: BOOT_PRGR - description: FLASH register with boot address - byte_offset: 68 - fieldset: BOOT_PRGR - - name: CRCDATAR - description: FLASH CRC data register - byte_offset: 92 - fieldset: CRCDATAR + - name: ACR + description: Access control register + byte_offset: 0 + fieldset: ACR + - name: BANK + description: Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R + array: + len: 2 + stride: 256 + byte_offset: 4 + block: BANK + - name: OPTKEYR + description: FLASH option key register + byte_offset: 8 + fieldset: OPTKEYR + - name: OPTCR + description: FLASH option control register + byte_offset: 24 + fieldset: OPTCR + - name: OPTSR_CUR + description: FLASH option status register + byte_offset: 28 + fieldset: OPTSR_CUR + - name: OPTSR_PRG + description: FLASH option status register + byte_offset: 32 + fieldset: OPTSR_PRG + - name: OPTCCR + description: FLASH option clear control register + byte_offset: 36 + access: Write + fieldset: OPTCCR + - name: BOOT_CURR + description: FLASH register with boot address + byte_offset: 64 + access: Read + fieldset: BOOT_CURR + - name: BOOT_PRGR + description: FLASH register with boot address + byte_offset: 68 + fieldset: BOOT_PRGR + - name: CRCDATAR + description: FLASH CRC data register + byte_offset: 92 + fieldset: CRCDATAR fieldset/ACR: description: Access control register fields: - - name: LATENCY - description: Read latency - bit_offset: 0 - bit_size: 3 - - name: WRHIGHFREQ - description: Flash signal delay - bit_offset: 4 - bit_size: 2 + - name: LATENCY + description: Read latency + bit_offset: 0 + bit_size: 3 + - name: WRHIGHFREQ + description: Flash signal delay + bit_offset: 4 + bit_size: 2 fieldset/BOOT_CURR: description: FLASH register with boot address fields: - - name: BOOT_ADD0 - description: Boot address 0 - bit_offset: 0 - bit_size: 16 - - name: BOOT_ADD1 - description: Boot address 1 - bit_offset: 16 - bit_size: 16 + - name: BOOT_ADD0 + description: Boot address 0 + bit_offset: 0 + bit_size: 16 + - name: BOOT_ADD1 + description: Boot address 1 + bit_offset: 16 + bit_size: 16 fieldset/BOOT_PRGR: description: FLASH register with boot address fields: - - name: BOOT_ADD0 - description: Boot address 0 - bit_offset: 0 - bit_size: 16 - - name: BOOT_ADD1 - description: Boot address 1 - bit_offset: 16 - bit_size: 16 + - name: BOOT_ADD0 + description: Boot address 0 + bit_offset: 0 + bit_size: 16 + - name: BOOT_ADD1 + description: Boot address 1 + bit_offset: 16 + bit_size: 16 fieldset/CCR: description: FLASH clear control register for bank 1 fields: - - name: CLR_EOP - description: Bank 1 EOP1 flag clear bit - bit_offset: 16 - bit_size: 1 - - name: CLR_WRPERR - description: Bank 1 WRPERR1 flag clear bit - bit_offset: 17 - bit_size: 1 - - name: CLR_PGSERR - description: Bank 1 PGSERR1 flag clear bi - bit_offset: 18 - bit_size: 1 - - name: CLR_STRBERR - description: Bank 1 STRBERR1 flag clear bit - bit_offset: 19 - bit_size: 1 - - name: CLR_INCERR - description: Bank 1 INCERR1 flag clear bit - bit_offset: 21 - bit_size: 1 - - name: CLR_OPERR - description: Bank 1 OPERR1 flag clear bit - bit_offset: 22 - bit_size: 1 - - name: CLR_RDPERR - description: Bank 1 RDPERR1 flag clear bit - bit_offset: 23 - bit_size: 1 - - name: CLR_RDSERR - description: Bank 1 RDSERR1 flag clear bit - bit_offset: 24 - bit_size: 1 - - name: CLR_SNECCERR - description: Bank 1 SNECCERR1 flag clear bit - bit_offset: 25 - bit_size: 1 - - name: CLR_DBECCERR - description: Bank 1 DBECCERR1 flag clear bit - bit_offset: 26 - bit_size: 1 - - name: CLR_CRCEND - description: Bank 1 CRCEND1 flag clear bit - bit_offset: 27 - bit_size: 1 + - name: CLR_EOP + description: Bank 1 EOP1 flag clear bit + bit_offset: 16 + bit_size: 1 + - name: CLR_WRPERR + description: Bank 1 WRPERR1 flag clear bit + bit_offset: 17 + bit_size: 1 + - name: CLR_PGSERR + description: Bank 1 PGSERR1 flag clear bi + bit_offset: 18 + bit_size: 1 + - name: CLR_STRBERR + description: Bank 1 STRBERR1 flag clear bit + bit_offset: 19 + bit_size: 1 + - name: CLR_INCERR + description: Bank 1 INCERR1 flag clear bit + bit_offset: 21 + bit_size: 1 + - name: CLR_OPERR + description: Bank 1 OPERR1 flag clear bit + bit_offset: 22 + bit_size: 1 + - name: CLR_RDPERR + description: Bank 1 RDPERR1 flag clear bit + bit_offset: 23 + bit_size: 1 + - name: CLR_RDSERR + description: Bank 1 RDSERR1 flag clear bit + bit_offset: 24 + bit_size: 1 + - name: CLR_SNECCERR + description: Bank 1 SNECCERR1 flag clear bit + bit_offset: 25 + bit_size: 1 + - name: CLR_DBECCERR + description: Bank 1 DBECCERR1 flag clear bit + bit_offset: 26 + bit_size: 1 + - name: CLR_CRCEND + description: Bank 1 CRCEND1 flag clear bit + bit_offset: 27 + bit_size: 1 + - name: CLR_CRCRDERR + description: Bank 1 CRC read error clear bit + bit_offset: 28 + bit_size: 1 fieldset/CR: description: FLASH control register for bank 1 fields: - - name: LOCK - description: Bank 1 configuration lock bit - bit_offset: 0 - bit_size: 1 - - name: PG - description: Bank 1 program enable bit - bit_offset: 1 - bit_size: 1 - - name: SER - description: Bank 1 sector erase request - bit_offset: 2 - bit_size: 1 - - name: BER - description: Bank 1 erase request - bit_offset: 3 - bit_size: 1 - - name: PSIZE - description: Bank 1 program size - bit_offset: 4 - bit_size: 2 - - name: FW - description: Bank 1 write forcing control bit - bit_offset: 6 - bit_size: 1 - - name: START - description: Bank 1 bank or sector erase start control bit - bit_offset: 7 - bit_size: 1 - - name: SNB - description: Bank 1 sector erase selection number - bit_offset: 8 - bit_size: 3 - - name: CRC_EN - description: Bank 1 CRC control bit - bit_offset: 15 - bit_size: 1 - - name: EOPIE - description: Bank 1 end-of-program interrupt control bit - bit_offset: 16 - bit_size: 1 - - name: WRPERRIE - description: Bank 1 write protection error interrupt enable bit - bit_offset: 17 - bit_size: 1 - - name: PGSERRIE - description: Bank 1 programming sequence error interrupt enable bit - bit_offset: 18 - bit_size: 1 - - name: STRBERRIE - description: Bank 1 strobe error interrupt enable bit - bit_offset: 19 - bit_size: 1 - - name: INCERRIE - description: Bank 1 inconsistency error interrupt enable bit - bit_offset: 21 - bit_size: 1 - - name: OPERRIE - description: Bank 1 write/erase error interrupt enable bit - bit_offset: 22 - bit_size: 1 - - name: RDPERRIE - description: Bank 1 read protection error interrupt enable bit - bit_offset: 23 - bit_size: 1 - - name: RDSERRIE - description: Bank 1 secure error interrupt enable bit - bit_offset: 24 - bit_size: 1 - - name: SNECCERRIE - description: Bank 1 ECC single correction error interrupt enable bit - bit_offset: 25 - bit_size: 1 - - name: DBECCERRIE - description: Bank 1 ECC double detection error interrupt enable bit - bit_offset: 26 - bit_size: 1 - - name: CRCENDIE - description: Bank 1 end of CRC calculation interrupt enable bit - bit_offset: 27 - bit_size: 1 + - name: LOCK + description: Bank 1 configuration lock bit + bit_offset: 0 + bit_size: 1 + - name: PG + description: Bank 1 program enable bit + bit_offset: 1 + bit_size: 1 + - name: SER + description: Bank 1 sector erase request + bit_offset: 2 + bit_size: 1 + - name: BER + description: Bank 1 erase request + bit_offset: 3 + bit_size: 1 + - name: PSIZE + description: Bank 1 program size + bit_offset: 4 + bit_size: 2 + - name: FW + description: Bank 1 write forcing control bit + bit_offset: 6 + bit_size: 1 + - name: START + description: Bank 1 bank or sector erase start control bit + bit_offset: 7 + bit_size: 1 + - name: SNB + description: Bank 1 sector erase selection number + bit_offset: 8 + bit_size: 3 + - name: CRC_EN + description: Bank 1 CRC control bit + bit_offset: 15 + bit_size: 1 + - name: EOPIE + description: Bank 1 end-of-program interrupt control bit + bit_offset: 16 + bit_size: 1 + - name: WRPERRIE + description: Bank 1 write protection error interrupt enable bit + bit_offset: 17 + bit_size: 1 + - name: PGSERRIE + description: Bank 1 programming sequence error interrupt enable bit + bit_offset: 18 + bit_size: 1 + - name: STRBERRIE + description: Bank 1 strobe error interrupt enable bit + bit_offset: 19 + bit_size: 1 + - name: INCERRIE + description: Bank 1 inconsistency error interrupt enable bit + bit_offset: 21 + bit_size: 1 + - name: OPERRIE + description: Bank 1 write/erase error interrupt enable bit + bit_offset: 22 + bit_size: 1 + - name: RDPERRIE + description: Bank 1 read protection error interrupt enable bit + bit_offset: 23 + bit_size: 1 + - name: RDSERRIE + description: Bank 1 secure error interrupt enable bit + bit_offset: 24 + bit_size: 1 + - name: SNECCERRIE + description: Bank 1 ECC single correction error interrupt enable bit + bit_offset: 25 + bit_size: 1 + - name: DBECCERRIE + description: Bank 1 ECC double detection error interrupt enable bit + bit_offset: 26 + bit_size: 1 + - name: CRCENDIE + description: Bank 1 end of CRC calculation interrupt enable bit + bit_offset: 27 + bit_size: 1 + - name: CRCRDERRIE + description: Bank 1 CRC read error interrupt enable bit + bit_offset: 28 + bit_size: 1 fieldset/CRCCR: description: FLASH CRC control register for bank 1 fields: - - name: CRC_SECT - description: Bank 1 CRC sector number - bit_offset: 0 - bit_size: 3 - - name: ALL_BANK - description: Bank 1 CRC select bit - bit_offset: 7 - bit_size: 1 - - name: CRC_BY_SECT - description: Bank 1 CRC sector mode select bit - bit_offset: 8 - bit_size: 1 - - name: ADD_SECT - description: Bank 1 CRC sector select bit - bit_offset: 9 - bit_size: 1 - - name: CLEAN_SECT - description: Bank 1 CRC sector list clear bit - bit_offset: 10 - bit_size: 1 - - name: START_CRC - description: Bank 1 CRC start bit - bit_offset: 16 - bit_size: 1 - - name: CLEAN_CRC - description: Bank 1 CRC clear bit - bit_offset: 17 - bit_size: 1 - - name: CRC_BURST - description: Bank 1 CRC burst size - bit_offset: 20 - bit_size: 2 + - name: CRC_SECT + description: Bank 1 CRC sector number + bit_offset: 0 + bit_size: 3 + - name: ALL_BANK + description: Bank 1 CRC select bit + bit_offset: 7 + bit_size: 1 + - name: CRC_BY_SECT + description: Bank 1 CRC sector mode select bit + bit_offset: 8 + bit_size: 1 + - name: ADD_SECT + description: Bank 1 CRC sector select bit + bit_offset: 9 + bit_size: 1 + - name: CLEAN_SECT + description: Bank 1 CRC sector list clear bit + bit_offset: 10 + bit_size: 1 + - name: START_CRC + description: Bank 1 CRC start bit + bit_offset: 16 + bit_size: 1 + - name: CLEAN_CRC + description: Bank 1 CRC clear bit + bit_offset: 17 + bit_size: 1 + - name: CRC_BURST + description: Bank 1 CRC burst size + bit_offset: 20 + bit_size: 2 fieldset/CRCDATAR: description: FLASH CRC data register fields: - - name: CRC_DATA - description: CRC result - bit_offset: 0 - bit_size: 32 + - name: CRC_DATA + description: CRC result + bit_offset: 0 + bit_size: 32 fieldset/CRCEADDR: description: FLASH CRC end address register for bank 1 fields: - - name: CRC_END_ADDR - description: CRC end address on bank 1 - bit_offset: 0 - bit_size: 32 + - name: CRC_END_ADDR + description: CRC end address on bank 1 + bit_offset: 0 + bit_size: 32 fieldset/CRCSADDR: description: FLASH CRC start address register for bank 1 fields: - - name: CRC_START_ADDR - description: CRC start address on bank 1 - bit_offset: 0 - bit_size: 32 + - name: CRC_START_ADDR + description: CRC start address on bank 1 + bit_offset: 0 + bit_size: 32 fieldset/FAR: description: FLASH ECC fail address for bank 1 fields: - - name: FAIL_ECC_ADDR - description: Bank 1 ECC error address - bit_offset: 0 - bit_size: 15 + - name: FAIL_ECC_ADDR + description: Bank 1 ECC error address + bit_offset: 0 + bit_size: 15 fieldset/KEYR: description: FLASH key register for bank 1 fields: - - name: KEYR - description: Bank 1 access configuration unlock key - bit_offset: 0 - bit_size: 32 + - name: KEYR + description: Bank 1 access configuration unlock key + bit_offset: 0 + bit_size: 32 fieldset/OPTCCR: description: FLASH option clear control register fields: - - name: CLR_OPTCHANGEERR - description: OPTCHANGEERR reset bit - bit_offset: 30 - bit_size: 1 + - name: CLR_OPTCHANGEERR + description: OPTCHANGEERR reset bit + bit_offset: 30 + bit_size: 1 fieldset/OPTCR: description: FLASH option control register fields: - - name: OPTLOCK - description: FLASH_OPTCR lock option configuration bit - bit_offset: 0 - bit_size: 1 - - name: OPTSTART - description: Option byte start change option configuration bit - bit_offset: 1 - bit_size: 1 - - name: MER - description: Flash mass erase enable bit - bit_offset: 4 - bit_size: 1 - - name: OPTCHANGEERRIE - description: Option byte change error interrupt enable bit - bit_offset: 30 - bit_size: 1 - - name: SWAP_BANK - description: Bank swapping configuration bit - bit_offset: 31 - bit_size: 1 + - name: OPTLOCK + description: FLASH_OPTCR lock option configuration bit + bit_offset: 0 + bit_size: 1 + - name: OPTSTART + description: Option byte start change option configuration bit + bit_offset: 1 + bit_size: 1 + - name: MER + description: Flash mass erase enable bit + bit_offset: 4 + bit_size: 1 + - name: OPTCHANGEERRIE + description: Option byte change error interrupt enable bit + bit_offset: 30 + bit_size: 1 + - name: SWAP_BANK + description: Bank swapping configuration bit + bit_offset: 31 + bit_size: 1 fieldset/OPTKEYR: description: FLASH option key register fields: - - name: OPTKEYR - description: Unlock key option bytes - bit_offset: 0 - bit_size: 32 + - name: OPTKEYR + description: Unlock key option bytes + bit_offset: 0 + bit_size: 32 fieldset/OPTSR_CUR: description: FLASH option status register fields: - - name: OPT_BUSY - description: Option byte change ongoing flag - bit_offset: 0 - bit_size: 1 - - name: BOR_LEV - description: Brownout level option status bit - bit_offset: 2 - bit_size: 2 - - name: IWDG1_HW - description: IWDG1 control option status bit - bit_offset: 4 - bit_size: 1 - - name: nRST_STOP_D1 - description: D1 DStop entry reset option status bit - bit_offset: 6 - bit_size: 1 - - name: nRST_STBY_D1 - description: D1 DStandby entry reset option status bit - bit_offset: 7 - bit_size: 1 - - name: RDP - description: Readout protection level option status byte - bit_offset: 8 - bit_size: 8 - - name: FZ_IWDG_STOP - description: IWDG Stop mode freeze option status bit - bit_offset: 17 - bit_size: 1 - - name: FZ_IWDG_SDBY - description: IWDG Standby mode freeze option status bit - bit_offset: 18 - bit_size: 1 - - name: ST_RAM_SIZE - description: DTCM RAM size option status - bit_offset: 19 - bit_size: 2 - - name: SECURITY - description: Security enable option status bit - bit_offset: 21 - bit_size: 1 - - name: RSS1 - description: User option bit 1 - bit_offset: 26 - bit_size: 1 - - name: PERSO_OK - description: Device personalization status bit - bit_offset: 28 - bit_size: 1 - - name: IO_HSLV - description: I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V) - bit_offset: 29 - bit_size: 1 - - name: OPTCHANGEERR - description: Option byte change error flag - bit_offset: 30 - bit_size: 1 - - name: SWAP_BANK_OPT - description: Bank swapping option status bit - bit_offset: 31 - bit_size: 1 + - name: OPT_BUSY + description: Option byte change ongoing flag + bit_offset: 0 + bit_size: 1 + - name: BOR_LEV + description: Brownout level option status bit + bit_offset: 2 + bit_size: 2 + - name: IWDG1_HW + description: IWDG1 control option status bit + bit_offset: 4 + bit_size: 1 + - name: nRST_STOP_D1 + description: D1 DStop entry reset option status bit + bit_offset: 6 + bit_size: 1 + - name: nRST_STBY_D1 + description: D1 DStandby entry reset option status bit + bit_offset: 7 + bit_size: 1 + - name: RDP + description: Readout protection level option status byte + bit_offset: 8 + bit_size: 8 + - name: FZ_IWDG_STOP + description: IWDG Stop mode freeze option status bit + bit_offset: 17 + bit_size: 1 + - name: FZ_IWDG_SDBY + description: IWDG Standby mode freeze option status bit + bit_offset: 18 + bit_size: 1 + - name: ST_RAM_SIZE + description: DTCM RAM size option status + bit_offset: 19 + bit_size: 2 + - name: SECURITY + description: Security enable option status bit + bit_offset: 21 + bit_size: 1 + - name: RSS1 + description: User option bit 1 + bit_offset: 26 + bit_size: 1 + - name: PERSO_OK + description: Device personalization status bit + bit_offset: 28 + bit_size: 1 + - name: IO_HSLV + description: I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V) + bit_offset: 29 + bit_size: 1 + - name: OPTCHANGEERR + description: Option byte change error flag + bit_offset: 30 + bit_size: 1 + - name: SWAP_BANK_OPT + description: Bank swapping option status bit + bit_offset: 31 + bit_size: 1 fieldset/OPTSR_PRG: description: FLASH option status register fields: - - name: BOR_LEV - description: BOR reset level option configuration bits - bit_offset: 2 - bit_size: 2 - - name: IWDG1_HW - description: IWDG1 option configuration bit - bit_offset: 4 - bit_size: 1 - - name: nRST_STOP_D1 - description: Option byte erase after D1 DStop option configuration bit - bit_offset: 6 - bit_size: 1 - - name: nRST_STBY_D1 - description: Option byte erase after D1 DStandby option configuration bit - bit_offset: 7 - bit_size: 1 - - name: RDP - description: Readout protection level option configuration byte - bit_offset: 8 - bit_size: 8 - - name: FZ_IWDG_STOP - description: IWDG Stop mode freeze option configuration bit - bit_offset: 17 - bit_size: 1 - - name: FZ_IWDG_SDBY - description: IWDG Standby mode freeze option configuration bit - bit_offset: 18 - bit_size: 1 - - name: ST_RAM_SIZE - description: DTCM size select option configuration bits - bit_offset: 19 - bit_size: 2 - - name: SECURITY - description: Security option configuration bit - bit_offset: 21 - bit_size: 1 - - name: RSS1 - description: User option configuration bit 1 - bit_offset: 26 - bit_size: 1 - - name: RSS2 - description: User option configuration bit 2 - bit_offset: 27 - bit_size: 1 - - name: IO_HSLV - description: I/O high-speed at low-voltage (PRODUCT_BELOW_25V) - bit_offset: 29 - bit_size: 1 - - name: SWAP_BANK_OPT - description: Bank swapping option configuration bit - bit_offset: 31 - bit_size: 1 + - name: BOR_LEV + description: BOR reset level option configuration bits + bit_offset: 2 + bit_size: 2 + - name: IWDG1_HW + description: IWDG1 option configuration bit + bit_offset: 4 + bit_size: 1 + - name: nRST_STOP_D1 + description: Option byte erase after D1 DStop option configuration bit + bit_offset: 6 + bit_size: 1 + - name: nRST_STBY_D1 + description: Option byte erase after D1 DStandby option configuration bit + bit_offset: 7 + bit_size: 1 + - name: RDP + description: Readout protection level option configuration byte + bit_offset: 8 + bit_size: 8 + - name: FZ_IWDG_STOP + description: IWDG Stop mode freeze option configuration bit + bit_offset: 17 + bit_size: 1 + - name: FZ_IWDG_SDBY + description: IWDG Standby mode freeze option configuration bit + bit_offset: 18 + bit_size: 1 + - name: ST_RAM_SIZE + description: DTCM size select option configuration bits + bit_offset: 19 + bit_size: 2 + - name: SECURITY + description: Security option configuration bit + bit_offset: 21 + bit_size: 1 + - name: RSS1 + description: User option configuration bit 1 + bit_offset: 26 + bit_size: 1 + - name: RSS2 + description: User option configuration bit 2 + bit_offset: 27 + bit_size: 1 + - name: IO_HSLV + description: I/O high-speed at low-voltage (PRODUCT_BELOW_25V) + bit_offset: 29 + bit_size: 1 + - name: SWAP_BANK_OPT + description: Bank swapping option configuration bit + bit_offset: 31 + bit_size: 1 fieldset/PRAR_CUR: description: FLASH protection address for bank 1 fields: - - name: PROT_AREA_START - description: Bank 1 lowest PCROP protected address - bit_offset: 0 - bit_size: 12 - - name: PROT_AREA_END - description: Bank 1 highest PCROP protected address - bit_offset: 16 - bit_size: 12 - - name: DMEP - description: Bank 1 PCROP protected erase enable option status bit - bit_offset: 31 - bit_size: 1 + - name: PROT_AREA_START + description: Bank 1 lowest PCROP protected address + bit_offset: 0 + bit_size: 12 + - name: PROT_AREA_END + description: Bank 1 highest PCROP protected address + bit_offset: 16 + bit_size: 12 + - name: DMEP + description: Bank 1 PCROP protected erase enable option status bit + bit_offset: 31 + bit_size: 1 fieldset/PRAR_PRG: description: FLASH protection address for bank 1 fields: - - name: PROT_AREA_START - description: Bank 1 lowest PCROP protected address configuration - bit_offset: 0 - bit_size: 12 - - name: PROT_AREA_END - description: Bank 1 highest PCROP protected address configuration - bit_offset: 16 - bit_size: 12 - - name: DMEP - description: Bank 1 PCROP protected erase enable option configuration bit - bit_offset: 31 - bit_size: 1 + - name: PROT_AREA_START + description: Bank 1 lowest PCROP protected address configuration + bit_offset: 0 + bit_size: 12 + - name: PROT_AREA_END + description: Bank 1 highest PCROP protected address configuration + bit_offset: 16 + bit_size: 12 + - name: DMEP + description: Bank 1 PCROP protected erase enable option configuration bit + bit_offset: 31 + bit_size: 1 fieldset/SCAR_CUR: description: FLASH secure address for bank 1 fields: - - name: SEC_AREA_START - description: Bank 1 lowest secure protected address - bit_offset: 0 - bit_size: 12 - - name: SEC_AREA_END - description: Bank 1 highest secure protected address - bit_offset: 16 - bit_size: 12 - - name: DMES - description: Bank 1 secure protected erase enable option status bit - bit_offset: 31 - bit_size: 1 + - name: SEC_AREA_START + description: Bank 1 lowest secure protected address + bit_offset: 0 + bit_size: 12 + - name: SEC_AREA_END + description: Bank 1 highest secure protected address + bit_offset: 16 + bit_size: 12 + - name: DMES + description: Bank 1 secure protected erase enable option status bit + bit_offset: 31 + bit_size: 1 fieldset/SCAR_PRG: description: FLASH secure address for bank 1 fields: - - name: SEC_AREA_START - description: Bank 1 lowest secure protected address configuration - bit_offset: 0 - bit_size: 12 - - name: SEC_AREA_END - description: Bank 1 highest secure protected address configuration - bit_offset: 16 - bit_size: 12 - - name: DMES - description: Bank 1 secure protected erase enable option configuration bit - bit_offset: 31 - bit_size: 1 + - name: SEC_AREA_START + description: Bank 1 lowest secure protected address configuration + bit_offset: 0 + bit_size: 12 + - name: SEC_AREA_END + description: Bank 1 highest secure protected address configuration + bit_offset: 16 + bit_size: 12 + - name: DMES + description: Bank 1 secure protected erase enable option configuration bit + bit_offset: 31 + bit_size: 1 fieldset/SR: description: FLASH status register for bank 1 fields: - - name: BSY - description: Bank 1 ongoing program flag - bit_offset: 0 - bit_size: 1 - - name: WBNE - description: Bank 1 write buffer not empty flag - bit_offset: 1 - bit_size: 1 - - name: QW - description: Bank 1 wait queue flag - bit_offset: 2 - bit_size: 1 - - name: CRC_BUSY - description: Bank 1 CRC busy flag - bit_offset: 3 - bit_size: 1 - - name: EOP - description: Bank 1 end-of-program flag - bit_offset: 16 - bit_size: 1 - - name: WRPERR - description: Bank 1 write protection error flag - bit_offset: 17 - bit_size: 1 - - name: PGSERR - description: Bank 1 programming sequence error flag - bit_offset: 18 - bit_size: 1 - - name: STRBERR - description: Bank 1 strobe error flag - bit_offset: 19 - bit_size: 1 - - name: INCERR - description: Bank 1 inconsistency error flag - bit_offset: 21 - bit_size: 1 - - name: OPERR - description: Bank 1 write/erase error flag - bit_offset: 22 - bit_size: 1 - - name: RDPERR - description: Bank 1 read protection error flag - bit_offset: 23 - bit_size: 1 - - name: RDSERR - description: Bank 1 secure error flag - bit_offset: 24 - bit_size: 1 - - name: SNECCERR1 - description: Bank 1 single correction error flag - bit_offset: 25 - bit_size: 1 - - name: DBECCERR - description: Bank 1 ECC double detection error flag - bit_offset: 26 - bit_size: 1 - - name: CRCEND - description: Bank 1 CRC-complete flag - bit_offset: 27 - bit_size: 1 + - name: BSY + description: Bank 1 ongoing program flag + bit_offset: 0 + bit_size: 1 + - name: WBNE + description: Bank 1 write buffer not empty flag + bit_offset: 1 + bit_size: 1 + - name: QW + description: Bank 1 wait queue flag + bit_offset: 2 + bit_size: 1 + - name: CRC_BUSY + description: Bank 1 CRC busy flag + bit_offset: 3 + bit_size: 1 + - name: EOP + description: Bank 1 end-of-program flag + bit_offset: 16 + bit_size: 1 + - name: WRPERR + description: Bank 1 write protection error flag + bit_offset: 17 + bit_size: 1 + - name: PGSERR + description: Bank 1 programming sequence error flag + bit_offset: 18 + bit_size: 1 + - name: STRBERR + description: Bank 1 strobe error flag + bit_offset: 19 + bit_size: 1 + - name: INCERR + description: Bank 1 inconsistency error flag + bit_offset: 21 + bit_size: 1 + - name: OPERR + description: Bank 1 write/erase error flag + bit_offset: 22 + bit_size: 1 + - name: RDPERR + description: Bank 1 read protection error flag + bit_offset: 23 + bit_size: 1 + - name: RDSERR + description: Bank 1 secure error flag + bit_offset: 24 + bit_size: 1 + - name: SNECCERR1 + description: Bank 1 single correction error flag + bit_offset: 25 + bit_size: 1 + - name: DBECCERR + description: Bank 1 ECC double detection error flag + bit_offset: 26 + bit_size: 1 + - name: CRCEND + description: Bank 1 CRC-complete flag + bit_offset: 27 + bit_size: 1 + - name: CRCRDERR + description: Bank 1 CRC read error flag + bit_offset: 28 + bit_size: 1 fieldset/WPSN_CURR: description: FLASH write sector protection for bank 1 fields: - - name: WRPSn - description: Bank 1 sector write protection option status byte - bit_offset: 0 - bit_size: 8 + - name: WRPSn + description: Bank 1 sector write protection option status byte + bit_offset: 0 + bit_size: 8 fieldset/WPSN_PRGR: description: FLASH write sector protection for bank 1 fields: - - name: WRPSn - description: Bank 1 sector write protection configuration byte - bit_offset: 0 - bit_size: 8 + - name: WRPSn + description: Bank 1 sector write protection configuration byte + bit_offset: 0 + bit_size: 8 diff --git a/data/registers/flash_h7ab.yaml b/data/registers/flash_h7ab.yaml new file mode 100644 index 0000000..8e3b000 --- /dev/null +++ b/data/registers/flash_h7ab.yaml @@ -0,0 +1,648 @@ +block/BANK: + description: Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R + items: + - name: KEYR + description: FLASH key register for bank 1 + byte_offset: 0 + access: Write + fieldset: KEYR + - name: CR + description: FLASH control register for bank 1 + byte_offset: 8 + fieldset: CR + - name: SR + description: FLASH status register for bank 1 + byte_offset: 12 + fieldset: SR + - name: CCR + description: FLASH clear control register for bank 1 + byte_offset: 16 + fieldset: CCR + - name: PRAR_CUR + description: FLASH protection address for bank 1 + byte_offset: 36 + access: Read + fieldset: PRAR_CUR + - name: PRAR_PRG + description: FLASH protection address for bank 1 + byte_offset: 40 + fieldset: PRAR_PRG + - name: SCAR_CUR + description: FLASH secure address for bank 1 + byte_offset: 44 + fieldset: SCAR_CUR + - name: SCAR_PRG + description: FLASH secure address for bank 1 + byte_offset: 48 + fieldset: SCAR_PRG + - name: WPSN_CURR + description: FLASH write sector protection for bank 1 + byte_offset: 52 + access: Read + fieldset: WPSN_CURR + - name: WPSN_PRGR + description: FLASH write sector protection for bank 1 + byte_offset: 56 + fieldset: WPSN_PRGR + - name: CRCCR + description: FLASH CRC control register for bank 1 + byte_offset: 76 + fieldset: CRCCR + - name: CRCSADDR + description: FLASH CRC start address register for bank 1 + byte_offset: 80 + fieldset: CRCSADDR + - name: CRCEADDR + description: FLASH CRC end address register for bank 1 + byte_offset: 84 + fieldset: CRCEADDR + - name: FAR + description: FLASH ECC fail address for bank 1 + byte_offset: 92 + access: Read + fieldset: FAR +block/FLASH: + description: Flash + items: + - name: ACR + description: Access control register + byte_offset: 0 + fieldset: ACR + - name: BANK + description: Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R + array: + len: 2 + stride: 256 + byte_offset: 4 + block: BANK + - name: OPTKEYR + description: FLASH option key register + byte_offset: 8 + fieldset: OPTKEYR + - name: OPTCR + description: FLASH option control register + byte_offset: 24 + fieldset: OPTCR + - name: OPTSR_CUR + description: FLASH option status register + byte_offset: 28 + fieldset: OPTSR_CUR + - name: OPTSR_PRG + description: FLASH option status register + byte_offset: 32 + fieldset: OPTSR_PRG + - name: OPTCCR + description: FLASH option clear control register + byte_offset: 36 + access: Write + fieldset: OPTCCR + - name: BOOT_CURR + description: FLASH register with boot address + byte_offset: 64 + access: Read + fieldset: BOOT_CURR + - name: BOOT_PRGR + description: FLASH register with boot address + byte_offset: 68 + fieldset: BOOT_PRGR + - name: CRCDATAR + description: FLASH CRC data register + byte_offset: 92 + fieldset: CRCDATAR +fieldset/ACR: + description: Access control register + fields: + - name: LATENCY + description: Read latency + bit_offset: 0 + bit_size: 3 + - name: WRHIGHFREQ + description: Flash signal delay + bit_offset: 4 + bit_size: 2 +fieldset/BOOT_CURR: + description: FLASH register with boot address + fields: + - name: BOOT_ADD0 + description: Boot address 0 + bit_offset: 0 + bit_size: 16 + - name: BOOT_ADD1 + description: Boot address 1 + bit_offset: 16 + bit_size: 16 +fieldset/BOOT_PRGR: + description: FLASH register with boot address + fields: + - name: BOOT_ADD0 + description: Boot address 0 + bit_offset: 0 + bit_size: 16 + - name: BOOT_ADD1 + description: Boot address 1 + bit_offset: 16 + bit_size: 16 +fieldset/CCR: + description: FLASH clear control register for bank 1 + fields: + - name: CLR_EOP + description: Bank 1 EOP1 flag clear bit + bit_offset: 16 + bit_size: 1 + - name: CLR_WRPERR + description: Bank 1 WRPERR1 flag clear bit + bit_offset: 17 + bit_size: 1 + - name: CLR_PGSERR + description: Bank 1 PGSERR1 flag clear bi + bit_offset: 18 + bit_size: 1 + - name: CLR_STRBERR + description: Bank 1 STRBERR1 flag clear bit + bit_offset: 19 + bit_size: 1 + - name: CLR_INCERR + description: Bank 1 INCERR1 flag clear bit + bit_offset: 21 + bit_size: 1 + - name: CLR_OPERR + description: Bank 1 OPERR1 flag clear bit + bit_offset: 22 + bit_size: 1 + - name: CLR_RDPERR + description: Bank 1 RDPERR1 flag clear bit + bit_offset: 23 + bit_size: 1 + - name: CLR_RDSERR + description: Bank 1 RDSERR1 flag clear bit + bit_offset: 24 + bit_size: 1 + - name: CLR_SNECCERR + description: Bank 1 SNECCERR1 flag clear bit + bit_offset: 25 + bit_size: 1 + - name: CLR_DBECCERR + description: Bank 1 DBECCERR1 flag clear bit + bit_offset: 26 + bit_size: 1 + - name: CLR_CRCEND + description: Bank 1 CRCEND1 flag clear bit + bit_offset: 27 + bit_size: 1 + - name: CLR_CRCRDERR + description: Bank 1 CRC read error clear bit + bit_offset: 28 + bit_size: 1 +fieldset/CR: + description: FLASH control register for bank 1 + fields: + - name: LOCK + description: Bank 1 configuration lock bit + bit_offset: 0 + bit_size: 1 + - name: PG + description: Bank 1 program enable bit + bit_offset: 1 + bit_size: 1 + - name: SER + description: Bank 1 sector erase request + bit_offset: 2 + bit_size: 1 + - name: BER + description: Bank 1 erase request + bit_offset: 3 + bit_size: 1 + - name: FW + description: Bank 1 write forcing control bit + bit_offset: 4 + bit_size: 1 + - name: START + description: Bank 1 bank or sector erase start control bit + bit_offset: 5 + bit_size: 1 + - name: SSN + description: Bank 1 sector erase selection number + bit_offset: 6 + bit_size: 7 + - name: CRC_EN + description: Bank 1 CRC control bit + bit_offset: 15 + bit_size: 1 + - name: EOPIE + description: Bank 1 end-of-program interrupt control bit + bit_offset: 16 + bit_size: 1 + - name: WRPERRIE + description: Bank 1 write protection error interrupt enable bit + bit_offset: 17 + bit_size: 1 + - name: PGSERRIE + description: Bank 1 programming sequence error interrupt enable bit + bit_offset: 18 + bit_size: 1 + - name: STRBERRIE + description: Bank 1 strobe error interrupt enable bit + bit_offset: 19 + bit_size: 1 + - name: INCERRIE + description: Bank 1 inconsistency error interrupt enable bit + bit_offset: 21 + bit_size: 1 + - name: OPERRIE + description: Bank 1 write/erase error interrupt enable bit + bit_offset: 22 + bit_size: 1 + - name: RDPERRIE + description: Bank 1 read protection error interrupt enable bit + bit_offset: 23 + bit_size: 1 + - name: RDSERRIE + description: Bank 1 secure error interrupt enable bit + bit_offset: 24 + bit_size: 1 + - name: SNECCERRIE + description: Bank 1 ECC single correction error interrupt enable bit + bit_offset: 25 + bit_size: 1 + - name: DBECCERRIE + description: Bank 1 ECC double detection error interrupt enable bit + bit_offset: 26 + bit_size: 1 + - name: CRCENDIE + description: Bank 1 end of CRC calculation interrupt enable bit + bit_offset: 27 + bit_size: 1 + - name: CRCRDERRIE + description: Bank 1 CRC read error interrupt enable bit + bit_offset: 28 + bit_size: 1 +fieldset/CRCCR: + description: FLASH CRC control register for bank 1 + fields: + - name: CRC_SECT + description: Bank 1 CRC sector number + bit_offset: 0 + bit_size: 3 + - name: ALL_BANK + description: Bank 1 CRC select bit + bit_offset: 7 + bit_size: 1 + - name: CRC_BY_SECT + description: Bank 1 CRC sector mode select bit + bit_offset: 8 + bit_size: 1 + - name: ADD_SECT + description: Bank 1 CRC sector select bit + bit_offset: 9 + bit_size: 1 + - name: CLEAN_SECT + description: Bank 1 CRC sector list clear bit + bit_offset: 10 + bit_size: 1 + - name: START_CRC + description: Bank 1 CRC start bit + bit_offset: 16 + bit_size: 1 + - name: CLEAN_CRC + description: Bank 1 CRC clear bit + bit_offset: 17 + bit_size: 1 + - name: CRC_BURST + description: Bank 1 CRC burst size + bit_offset: 20 + bit_size: 2 +fieldset/CRCDATAR: + description: FLASH CRC data register + fields: + - name: CRC_DATA + description: CRC result + bit_offset: 0 + bit_size: 32 +fieldset/CRCEADDR: + description: FLASH CRC end address register for bank 1 + fields: + - name: CRC_END_ADDR + description: CRC end address on bank 1 + bit_offset: 0 + bit_size: 32 +fieldset/CRCSADDR: + description: FLASH CRC start address register for bank 1 + fields: + - name: CRC_START_ADDR + description: CRC start address on bank 1 + bit_offset: 0 + bit_size: 32 +fieldset/FAR: + description: FLASH ECC fail address for bank 1 + fields: + - name: FAIL_ECC_ADDR + description: Bank 1 ECC error address + bit_offset: 0 + bit_size: 15 +fieldset/KEYR: + description: FLASH key register for bank 1 + fields: + - name: KEYR + description: Bank 1 access configuration unlock key + bit_offset: 0 + bit_size: 32 +fieldset/OPTCCR: + description: FLASH option clear control register + fields: + - name: CLR_OPTCHANGEERR + description: OPTCHANGEERR reset bit + bit_offset: 30 + bit_size: 1 +fieldset/OPTCR: + description: FLASH option control register + fields: + - name: OPTLOCK + description: FLASH_OPTCR lock option configuration bit + bit_offset: 0 + bit_size: 1 + - name: OPTSTART + description: Option byte start change option configuration bit + bit_offset: 1 + bit_size: 1 + - name: MER + description: Flash mass erase enable bit + bit_offset: 4 + bit_size: 1 + - name: PG_OTP + description: OTP program control bit + bit_offset: 5 + bit_size: 1 + - name: OPTCHANGEERRIE + description: Option byte change error interrupt enable bit + bit_offset: 30 + bit_size: 1 + - name: SWAP_BANK + description: Bank swapping configuration bit + bit_offset: 31 + bit_size: 1 +fieldset/OPTKEYR: + description: FLASH option key register + fields: + - name: OPTKEYR + description: Unlock key option bytes + bit_offset: 0 + bit_size: 32 +fieldset/OPTSR_CUR: + description: FLASH option status register + fields: + - name: OPT_BUSY + description: Option byte change ongoing flag + bit_offset: 0 + bit_size: 1 + - name: BOR_LEV + description: Brownout level option status bit + bit_offset: 2 + bit_size: 2 + - name: IWDG1_HW + description: IWDG1 control option status bit + bit_offset: 4 + bit_size: 1 + - name: nRST_STOP_D1 + description: D1 DStop entry reset option status bit + bit_offset: 6 + bit_size: 1 + - name: nRST_STBY_D1 + description: D1 DStandby entry reset option status bit + bit_offset: 7 + bit_size: 1 + - name: RDP + description: Readout protection level option status byte + bit_offset: 8 + bit_size: 8 + - name: FZ_IWDG_STOP + description: IWDG Stop mode freeze option status bit + bit_offset: 17 + bit_size: 1 + - name: FZ_IWDG_SDBY + description: IWDG Standby mode freeze option status bit + bit_offset: 18 + bit_size: 1 + - name: ST_RAM_SIZE + description: DTCM RAM size option status + bit_offset: 19 + bit_size: 2 + - name: SECURITY + description: Security enable option status bit + bit_offset: 21 + bit_size: 1 + - name: RSS1 + description: User option bit 1 + bit_offset: 26 + bit_size: 1 + - name: PERSO_OK + description: Device personalization status bit + bit_offset: 28 + bit_size: 1 + - name: IO_HSLV + description: I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V) + bit_offset: 29 + bit_size: 1 + - name: OPTCHANGEERR + description: Option byte change error flag + bit_offset: 30 + bit_size: 1 + - name: SWAP_BANK_OPT + description: Bank swapping option status bit + bit_offset: 31 + bit_size: 1 +fieldset/OPTSR_PRG: + description: FLASH option status register + fields: + - name: BOR_LEV + description: BOR reset level option configuration bits + bit_offset: 2 + bit_size: 2 + - name: IWDG1_HW + description: IWDG1 option configuration bit + bit_offset: 4 + bit_size: 1 + - name: nRST_STOP_D1 + description: Option byte erase after D1 DStop option configuration bit + bit_offset: 6 + bit_size: 1 + - name: nRST_STBY_D1 + description: Option byte erase after D1 DStandby option configuration bit + bit_offset: 7 + bit_size: 1 + - name: RDP + description: Readout protection level option configuration byte + bit_offset: 8 + bit_size: 8 + - name: FZ_IWDG_STOP + description: IWDG Stop mode freeze option configuration bit + bit_offset: 17 + bit_size: 1 + - name: FZ_IWDG_SDBY + description: IWDG Standby mode freeze option configuration bit + bit_offset: 18 + bit_size: 1 + - name: ST_RAM_SIZE + description: DTCM size select option configuration bits + bit_offset: 19 + bit_size: 2 + - name: SECURITY + description: Security option configuration bit + bit_offset: 21 + bit_size: 1 + - name: RSS1 + description: User option configuration bit 1 + bit_offset: 26 + bit_size: 1 + - name: RSS2 + description: User option configuration bit 2 + bit_offset: 27 + bit_size: 1 + - name: IO_HSLV + description: I/O high-speed at low-voltage (PRODUCT_BELOW_25V) + bit_offset: 29 + bit_size: 1 + - name: SWAP_BANK_OPT + description: Bank swapping option configuration bit + bit_offset: 31 + bit_size: 1 +fieldset/PRAR_CUR: + description: FLASH protection address for bank 1 + fields: + - name: PROT_AREA_START + description: Bank 1 lowest PCROP protected address + bit_offset: 0 + bit_size: 12 + - name: PROT_AREA_END + description: Bank 1 highest PCROP protected address + bit_offset: 16 + bit_size: 12 + - name: DMEP + description: Bank 1 PCROP protected erase enable option status bit + bit_offset: 31 + bit_size: 1 +fieldset/PRAR_PRG: + description: FLASH protection address for bank 1 + fields: + - name: PROT_AREA_START + description: Bank 1 lowest PCROP protected address configuration + bit_offset: 0 + bit_size: 12 + - name: PROT_AREA_END + description: Bank 1 highest PCROP protected address configuration + bit_offset: 16 + bit_size: 12 + - name: DMEP + description: Bank 1 PCROP protected erase enable option configuration bit + bit_offset: 31 + bit_size: 1 +fieldset/SCAR_CUR: + description: FLASH secure address for bank 1 + fields: + - name: SEC_AREA_START + description: Bank 1 lowest secure protected address + bit_offset: 0 + bit_size: 12 + - name: SEC_AREA_END + description: Bank 1 highest secure protected address + bit_offset: 16 + bit_size: 12 + - name: DMES + description: Bank 1 secure protected erase enable option status bit + bit_offset: 31 + bit_size: 1 +fieldset/SCAR_PRG: + description: FLASH secure address for bank 1 + fields: + - name: SEC_AREA_START + description: Bank 1 lowest secure protected address configuration + bit_offset: 0 + bit_size: 12 + - name: SEC_AREA_END + description: Bank 1 highest secure protected address configuration + bit_offset: 16 + bit_size: 12 + - name: DMES + description: Bank 1 secure protected erase enable option configuration bit + bit_offset: 31 + bit_size: 1 +fieldset/SR: + description: FLASH status register for bank 1 + fields: + - name: BSY + description: Bank 1 ongoing program flag + bit_offset: 0 + bit_size: 1 + - name: WBNE + description: Bank 1 write buffer not empty flag + bit_offset: 1 + bit_size: 1 + - name: QW + description: Bank 1 wait queue flag + bit_offset: 2 + bit_size: 1 + - name: CRC_BUSY + description: Bank 1 CRC busy flag + bit_offset: 3 + bit_size: 1 + - name: EOP + description: Bank 1 end-of-program flag + bit_offset: 16 + bit_size: 1 + - name: WRPERR + description: Bank 1 write protection error flag + bit_offset: 17 + bit_size: 1 + - name: PGSERR + description: Bank 1 programming sequence error flag + bit_offset: 18 + bit_size: 1 + - name: STRBERR + description: Bank 1 strobe error flag + bit_offset: 19 + bit_size: 1 + - name: INCERR + description: Bank 1 inconsistency error flag + bit_offset: 21 + bit_size: 1 + - name: OPERR + description: Bank 1 write/erase error flag + bit_offset: 22 + bit_size: 1 + - name: RDPERR + description: Bank 1 read protection error flag + bit_offset: 23 + bit_size: 1 + - name: RDSERR + description: Bank 1 secure error flag + bit_offset: 24 + bit_size: 1 + - name: SNECCERR1 + description: Bank 1 single correction error flag + bit_offset: 25 + bit_size: 1 + - name: DBECCERR + description: Bank 1 ECC double detection error flag + bit_offset: 26 + bit_size: 1 + - name: CRCEND + description: Bank 1 CRC-complete flag + bit_offset: 27 + bit_size: 1 + - name: CRCRDERR + description: Bank 1 CRC read error flag + bit_offset: 28 + bit_size: 1 +fieldset/WPSN_CURR: + description: FLASH write sector protection for bank 1 + fields: + - name: WRPSn + description: Bank 1 sector write protection option status byte + bit_offset: 0 + bit_size: 8 +fieldset/WPSN_PRGR: + description: FLASH write sector protection for bank 1 + fields: + - name: WRPSn + description: Bank 1 sector write protection configuration byte + bit_offset: 0 + bit_size: 8 diff --git a/data/registers/flash_l0.yaml b/data/registers/flash_l0.yaml index 09cadbe..5677dfd 100644 --- a/data/registers/flash_l0.yaml +++ b/data/registers/flash_l0.yaml @@ -1,229 +1,228 @@ ---- block/FLASH: description: Flash items: - - name: ACR - description: Access control register - byte_offset: 0 - fieldset: ACR - - name: PECR - description: Program/erase control register - byte_offset: 4 - fieldset: PECR - - name: PDKEYR - description: Power down key register - byte_offset: 8 - access: Write - fieldset: PDKEYR - - name: PEKEYR - description: Program/erase key register - byte_offset: 12 - access: Write - fieldset: PEKEYR - - name: PRGKEYR - description: Program memory key register - byte_offset: 16 - access: Write - fieldset: PRGKEYR - - name: OPTKEYR - description: Option byte key register - byte_offset: 20 - access: Write - fieldset: OPTKEYR - - name: SR - description: Status register - byte_offset: 24 - fieldset: SR - - name: OPTR - description: Option byte register - byte_offset: 28 - access: Read - fieldset: OPTR - - name: WRPROT - description: Write Protection Register 1 - byte_offset: 32 - access: Read - fieldset: WRPROT - - name: WRPROT2 - description: Write Protection Register 2 - byte_offset: 128 - access: Read - fieldset: WRPROT + - name: ACR + description: Access control register + byte_offset: 0 + fieldset: ACR + - name: PECR + description: Program/erase control register + byte_offset: 4 + fieldset: PECR + - name: PDKEYR + description: Power down key register + byte_offset: 8 + access: Write + fieldset: PDKEYR + - name: PEKEYR + description: Program/erase key register + byte_offset: 12 + access: Write + fieldset: PEKEYR + - name: PRGKEYR + description: Program memory key register + byte_offset: 16 + access: Write + fieldset: PRGKEYR + - name: OPTKEYR + description: Option byte key register + byte_offset: 20 + access: Write + fieldset: OPTKEYR + - name: SR + description: Status register + byte_offset: 24 + fieldset: SR + - name: OPTR + description: Option byte register + byte_offset: 28 + access: Read + fieldset: OPTR + - name: WRPROT + description: Write Protection Register 1 + byte_offset: 32 + access: Read + fieldset: WRPROT + - name: WRPROT2 + description: Write Protection Register 2 + byte_offset: 128 + access: Read + fieldset: WRPROT fieldset/ACR: description: Access control register fields: - - name: LATENCY - description: Latency - bit_offset: 0 - bit_size: 1 - - name: PRFTEN - description: Prefetch enable - bit_offset: 1 - bit_size: 1 - - name: SLEEP_PD - description: Flash mode during Sleep - bit_offset: 3 - bit_size: 1 - - name: RUN_PD - description: Flash mode during Run - bit_offset: 4 - bit_size: 1 - - name: DISAB_BUF - description: Disable Buffer - bit_offset: 5 - bit_size: 1 - - name: PRE_READ - description: Pre-read data address - bit_offset: 6 - bit_size: 1 + - name: LATENCY + description: Latency + bit_offset: 0 + bit_size: 1 + - name: PRFTEN + description: Prefetch enable + bit_offset: 1 + bit_size: 1 + - name: SLEEP_PD + description: Flash mode during Sleep + bit_offset: 3 + bit_size: 1 + - name: RUN_PD + description: Flash mode during Run + bit_offset: 4 + bit_size: 1 + - name: DISAB_BUF + description: Disable Buffer + bit_offset: 5 + bit_size: 1 + - name: PRE_READ + description: Pre-read data address + bit_offset: 6 + bit_size: 1 fieldset/OPTKEYR: description: Option byte key register fields: - - name: OPTKEYR - description: Option byte key - bit_offset: 0 - bit_size: 32 + - name: OPTKEYR + description: Option byte key + bit_offset: 0 + bit_size: 32 fieldset/OPTR: description: Option byte register fields: - - name: RDPROT - description: Read protection - bit_offset: 0 - bit_size: 8 - - name: WPRMOD - description: Selection of protection mode of WPR bits - bit_offset: 8 - bit_size: 1 - - name: BOR_LEV - description: BOR_LEV - bit_offset: 16 - bit_size: 4 + - name: RDPROT + description: Read protection + bit_offset: 0 + bit_size: 8 + - name: WPRMOD + description: Selection of protection mode of WPR bits + bit_offset: 8 + bit_size: 1 + - name: BOR_LEV + description: BOR_LEV + bit_offset: 16 + bit_size: 4 fieldset/PDKEYR: description: Power down key register fields: - - name: PDKEYR - description: RUN_PD in FLASH_ACR key - bit_offset: 0 - bit_size: 32 + - name: PDKEYR + description: RUN_PD in FLASH_ACR key + bit_offset: 0 + bit_size: 32 fieldset/PECR: description: Program/erase control register fields: - - name: PELOCK - description: FLASH_PECR and data EEPROM lock - bit_offset: 0 - bit_size: 1 - - name: PRGLOCK - description: Program memory lock - bit_offset: 1 - bit_size: 1 - - name: OPTLOCK - description: Option bytes block lock - bit_offset: 2 - bit_size: 1 - - name: PROG - description: Program memory selection - bit_offset: 3 - bit_size: 1 - - name: DATA - description: Data EEPROM selection - bit_offset: 4 - bit_size: 1 - - name: FIX - description: "Fixed time data write for Byte, Half Word and Word programming" - bit_offset: 8 - bit_size: 1 - - name: ERASE - description: Page or Double Word erase mode - bit_offset: 9 - bit_size: 1 - - name: FPRG - description: Half Page/Double Word programming mode - bit_offset: 10 - bit_size: 1 - - name: PARALLELBANK - description: Parallel bank mode - bit_offset: 15 - bit_size: 1 - - name: EOPIE - description: End of programming interrupt enable - bit_offset: 16 - bit_size: 1 - - name: ERRIE - description: Error interrupt enable - bit_offset: 17 - bit_size: 1 - - name: OBL_LAUNCH - description: Launch the option byte loading - bit_offset: 18 - bit_size: 1 + - name: PELOCK + description: FLASH_PECR and data EEPROM lock + bit_offset: 0 + bit_size: 1 + - name: PRGLOCK + description: Program memory lock + bit_offset: 1 + bit_size: 1 + - name: OPTLOCK + description: Option bytes block lock + bit_offset: 2 + bit_size: 1 + - name: PROG + description: Program memory selection + bit_offset: 3 + bit_size: 1 + - name: DATA + description: Data EEPROM selection + bit_offset: 4 + bit_size: 1 + - name: FIX + description: Fixed time data write for Byte, Half Word and Word programming + bit_offset: 8 + bit_size: 1 + - name: ERASE + description: Page or Double Word erase mode + bit_offset: 9 + bit_size: 1 + - name: FPRG + description: Half Page/Double Word programming mode + bit_offset: 10 + bit_size: 1 + - name: PARALLELBANK + description: Parallel bank mode + bit_offset: 15 + bit_size: 1 + - name: EOPIE + description: End of programming interrupt enable + bit_offset: 16 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 17 + bit_size: 1 + - name: OBL_LAUNCH + description: Launch the option byte loading + bit_offset: 18 + bit_size: 1 fieldset/PEKEYR: description: Program/erase key register fields: - - name: PEKEYR - description: FLASH_PEC and data EEPROM key - bit_offset: 0 - bit_size: 32 + - name: PEKEYR + description: FLASH_PEC and data EEPROM key + bit_offset: 0 + bit_size: 32 fieldset/PRGKEYR: description: Program memory key register fields: - - name: PRGKEYR - description: Program memory key - bit_offset: 0 - bit_size: 32 + - name: PRGKEYR + description: Program memory key + bit_offset: 0 + bit_size: 32 fieldset/SR: description: Status register fields: - - name: BSY - description: Write/erase operations in progress - bit_offset: 0 - bit_size: 1 - - name: EOP - description: End of operation - bit_offset: 1 - bit_size: 1 - - name: ENDHV - description: End of high voltage - bit_offset: 2 - bit_size: 1 - - name: READY - description: Flash memory module ready after low power mode - bit_offset: 3 - bit_size: 1 - - name: WRPERR - description: Write protected error - bit_offset: 8 - bit_size: 1 - - name: PGAERR - description: Programming alignment error - bit_offset: 9 - bit_size: 1 - - name: SIZERR - description: Size error - bit_offset: 10 - bit_size: 1 - - name: OPTVERR - description: Option validity error - bit_offset: 11 - bit_size: 1 - - name: RDERR - description: RDERR - bit_offset: 14 - bit_size: 1 - - name: NOTZEROERR - description: NOTZEROERR - bit_offset: 16 - bit_size: 1 - - name: FWWERR - description: FWWERR - bit_offset: 17 - bit_size: 1 + - name: BSY + description: Write/erase operations in progress + bit_offset: 0 + bit_size: 1 + - name: EOP + description: End of operation + bit_offset: 1 + bit_size: 1 + - name: ENDHV + description: End of high voltage + bit_offset: 2 + bit_size: 1 + - name: READY + description: Flash memory module ready after low power mode + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: Write protected error + bit_offset: 8 + bit_size: 1 + - name: PGAERR + description: Programming alignment error + bit_offset: 9 + bit_size: 1 + - name: SIZERR + description: Size error + bit_offset: 10 + bit_size: 1 + - name: OPTVERR + description: Option validity error + bit_offset: 11 + bit_size: 1 + - name: RDERR + description: RDERR + bit_offset: 14 + bit_size: 1 + - name: NOTZEROERR + description: NOTZEROERR + bit_offset: 16 + bit_size: 1 + - name: FWWERR + description: FWWERR + bit_offset: 17 + bit_size: 1 fieldset/WRPROT: description: Write Protection Register fields: - - name: WRPROT - description: Write Protection - bit_offset: 0 - bit_size: 1 - array: - len: 32 - stride: 1 + - name: WRPROT + description: Write Protection + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 diff --git a/data/registers/flash_l1.yaml b/data/registers/flash_l1.yaml index ce0585a..67076c4 100644 --- a/data/registers/flash_l1.yaml +++ b/data/registers/flash_l1.yaml @@ -1,242 +1,241 @@ ---- block/FLASH: description: Flash items: - - name: ACR - description: Access control register - byte_offset: 0 - fieldset: ACR - - name: PECR - description: Program/erase control register - byte_offset: 4 - fieldset: PECR - - name: PDKEYR - description: Power down key register - byte_offset: 8 - access: Write - fieldset: PDKEYR - - name: PEKEYR - description: Program/erase key register - byte_offset: 12 - access: Write - fieldset: PEKEYR - - name: PRGKEYR - description: Program memory key register - byte_offset: 16 - access: Write - fieldset: PRGKEYR - - name: OPTKEYR - description: Option byte key register - byte_offset: 20 - access: Write - fieldset: OPTKEYR - - name: SR - description: Status register - byte_offset: 24 - fieldset: SR - - name: OBR - description: Option byte register - byte_offset: 28 - access: Read - fieldset: OBR - - name: WRPR1 - description: Write protection register - byte_offset: 32 - fieldset: WRPR1 - - name: WRPR2 - description: Write protection register - byte_offset: 128 - fieldset: WRPR2 - - name: WRPR3 - description: Write protection register - byte_offset: 132 - fieldset: WRPR3 + - name: ACR + description: Access control register + byte_offset: 0 + fieldset: ACR + - name: PECR + description: Program/erase control register + byte_offset: 4 + fieldset: PECR + - name: PDKEYR + description: Power down key register + byte_offset: 8 + access: Write + fieldset: PDKEYR + - name: PEKEYR + description: Program/erase key register + byte_offset: 12 + access: Write + fieldset: PEKEYR + - name: PRGKEYR + description: Program memory key register + byte_offset: 16 + access: Write + fieldset: PRGKEYR + - name: OPTKEYR + description: Option byte key register + byte_offset: 20 + access: Write + fieldset: OPTKEYR + - name: SR + description: Status register + byte_offset: 24 + fieldset: SR + - name: OBR + description: Option byte register + byte_offset: 28 + access: Read + fieldset: OBR + - name: WRPR1 + description: Write protection register + byte_offset: 32 + fieldset: WRPR1 + - name: WRPR2 + description: Write protection register + byte_offset: 128 + fieldset: WRPR2 + - name: WRPR3 + description: Write protection register + byte_offset: 132 + fieldset: WRPR3 fieldset/ACR: description: Access control register fields: - - name: LATENCY - description: Latency - bit_offset: 0 - bit_size: 1 - - name: PRFTEN - description: Prefetch enable - bit_offset: 1 - bit_size: 1 - - name: ACC64 - description: 64-bit access - bit_offset: 2 - bit_size: 1 - - name: SLEEP_PD - description: Flash mode during Sleep - bit_offset: 3 - bit_size: 1 - - name: RUN_PD - description: Flash mode during Run - bit_offset: 4 - bit_size: 1 + - name: LATENCY + description: Latency + bit_offset: 0 + bit_size: 1 + - name: PRFTEN + description: Prefetch enable + bit_offset: 1 + bit_size: 1 + - name: ACC64 + description: 64-bit access + bit_offset: 2 + bit_size: 1 + - name: SLEEP_PD + description: Flash mode during Sleep + bit_offset: 3 + bit_size: 1 + - name: RUN_PD + description: Flash mode during Run + bit_offset: 4 + bit_size: 1 fieldset/OBR: description: Option byte register fields: - - name: RDPRT - description: Read protection - bit_offset: 0 - bit_size: 8 - - name: BOR_LEV - description: BOR_LEV - bit_offset: 16 - bit_size: 4 - - name: IWDG_SW - description: IWDG_SW - bit_offset: 20 - bit_size: 1 - - name: nRTS_STOP - description: nRTS_STOP - bit_offset: 21 - bit_size: 1 - - name: nRST_STDBY - description: nRST_STDBY - bit_offset: 22 - bit_size: 1 - - name: BFB2 - description: Boot From Bank 2 - bit_offset: 23 - bit_size: 1 + - name: RDPRT + description: Read protection + bit_offset: 0 + bit_size: 8 + - name: BOR_LEV + description: BOR_LEV + bit_offset: 16 + bit_size: 4 + - name: IWDG_SW + description: IWDG_SW + bit_offset: 20 + bit_size: 1 + - name: nRTS_STOP + description: nRTS_STOP + bit_offset: 21 + bit_size: 1 + - name: nRST_STDBY + description: nRST_STDBY + bit_offset: 22 + bit_size: 1 + - name: BFB2 + description: Boot From Bank 2 + bit_offset: 23 + bit_size: 1 fieldset/OPTKEYR: description: Option byte key register fields: - - name: OPTKEYR - description: Option byte key - bit_offset: 0 - bit_size: 32 + - name: OPTKEYR + description: Option byte key + bit_offset: 0 + bit_size: 32 fieldset/PDKEYR: description: Power down key register fields: - - name: PDKEYR - description: RUN_PD in FLASH_ACR key - bit_offset: 0 - bit_size: 32 + - name: PDKEYR + description: RUN_PD in FLASH_ACR key + bit_offset: 0 + bit_size: 32 fieldset/PECR: description: Program/erase control register fields: - - name: PELOCK - description: FLASH_PECR and data EEPROM lock - bit_offset: 0 - bit_size: 1 - - name: PRGLOCK - description: Program memory lock - bit_offset: 1 - bit_size: 1 - - name: OPTLOCK - description: Option bytes block lock - bit_offset: 2 - bit_size: 1 - - name: PROG - description: Program memory selection - bit_offset: 3 - bit_size: 1 - - name: DATA - description: Data EEPROM selection - bit_offset: 4 - bit_size: 1 - - name: FTDW - description: "Fixed time data write for Byte, Half Word and Word programming" - bit_offset: 8 - bit_size: 1 - - name: ERASE - description: Page or Double Word erase mode - bit_offset: 9 - bit_size: 1 - - name: FPRG - description: Half Page/Double Word programming mode - bit_offset: 10 - bit_size: 1 - - name: PARALLELBANK - description: Parallel bank mode - bit_offset: 15 - bit_size: 1 - - name: EOPIE - description: End of programming interrupt enable - bit_offset: 16 - bit_size: 1 - - name: ERRIE - description: Error interrupt enable - bit_offset: 17 - bit_size: 1 - - name: OBL_LAUNCH - description: Launch the option byte loading - bit_offset: 18 - bit_size: 1 + - name: PELOCK + description: FLASH_PECR and data EEPROM lock + bit_offset: 0 + bit_size: 1 + - name: PRGLOCK + description: Program memory lock + bit_offset: 1 + bit_size: 1 + - name: OPTLOCK + description: Option bytes block lock + bit_offset: 2 + bit_size: 1 + - name: PROG + description: Program memory selection + bit_offset: 3 + bit_size: 1 + - name: DATA + description: Data EEPROM selection + bit_offset: 4 + bit_size: 1 + - name: FTDW + description: Fixed time data write for Byte, Half Word and Word programming + bit_offset: 8 + bit_size: 1 + - name: ERASE + description: Page or Double Word erase mode + bit_offset: 9 + bit_size: 1 + - name: FPRG + description: Half Page/Double Word programming mode + bit_offset: 10 + bit_size: 1 + - name: PARALLELBANK + description: Parallel bank mode + bit_offset: 15 + bit_size: 1 + - name: EOPIE + description: End of programming interrupt enable + bit_offset: 16 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 17 + bit_size: 1 + - name: OBL_LAUNCH + description: Launch the option byte loading + bit_offset: 18 + bit_size: 1 fieldset/PEKEYR: description: Program/erase key register fields: - - name: PEKEYR - description: FLASH_PEC and data EEPROM key - bit_offset: 0 - bit_size: 32 + - name: PEKEYR + description: FLASH_PEC and data EEPROM key + bit_offset: 0 + bit_size: 32 fieldset/PRGKEYR: description: Program memory key register fields: - - name: PRGKEYR - description: Program memory key - bit_offset: 0 - bit_size: 32 + - name: PRGKEYR + description: Program memory key + bit_offset: 0 + bit_size: 32 fieldset/SR: description: Status register fields: - - name: BSY - description: Write/erase operations in progress - bit_offset: 0 - bit_size: 1 - - name: EOP - description: End of operation - bit_offset: 1 - bit_size: 1 - - name: ENDHV - description: End of high voltage - bit_offset: 2 - bit_size: 1 - - name: READY - description: Flash memory module ready after low power mode - bit_offset: 3 - bit_size: 1 - - name: WRPERR - description: Write protected error - bit_offset: 8 - bit_size: 1 - - name: PGAERR - description: Programming alignment error - bit_offset: 9 - bit_size: 1 - - name: SIZERR - description: Size error - bit_offset: 10 - bit_size: 1 - - name: OPTVERR - description: Option validity error - bit_offset: 11 - bit_size: 1 - - name: OPTVERRUSR - description: Option UserValidity Error - bit_offset: 12 - bit_size: 1 + - name: BSY + description: Write/erase operations in progress + bit_offset: 0 + bit_size: 1 + - name: EOP + description: End of operation + bit_offset: 1 + bit_size: 1 + - name: ENDHV + description: End of high voltage + bit_offset: 2 + bit_size: 1 + - name: READY + description: Flash memory module ready after low power mode + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: Write protected error + bit_offset: 8 + bit_size: 1 + - name: PGAERR + description: Programming alignment error + bit_offset: 9 + bit_size: 1 + - name: SIZERR + description: Size error + bit_offset: 10 + bit_size: 1 + - name: OPTVERR + description: Option validity error + bit_offset: 11 + bit_size: 1 + - name: OPTVERRUSR + description: Option UserValidity Error + bit_offset: 12 + bit_size: 1 fieldset/WRPR1: description: Write protection register fields: - - name: WRP1 - description: Write protection - bit_offset: 0 - bit_size: 32 + - name: WRP1 + description: Write protection + bit_offset: 0 + bit_size: 32 fieldset/WRPR2: description: Write protection register fields: - - name: WRP2 - description: WRP2 - bit_offset: 0 - bit_size: 32 + - name: WRP2 + description: WRP2 + bit_offset: 0 + bit_size: 32 fieldset/WRPR3: description: Write protection register fields: - - name: WRP3 - description: WRP3 - bit_offset: 0 - bit_size: 32 + - name: WRP3 + description: WRP3 + bit_offset: 0 + bit_size: 32 diff --git a/data/registers/flash_l4.yaml b/data/registers/flash_l4.yaml index a4f63c1..01c251f 100644 --- a/data/registers/flash_l4.yaml +++ b/data/registers/flash_l4.yaml @@ -1,406 +1,405 @@ ---- block/FLASH: description: Flash items: - - name: ACR - description: Access control register - byte_offset: 0 - fieldset: ACR - - name: PDKEYR - description: Power down key register - byte_offset: 4 - access: Write - fieldset: PDKEYR - - name: KEYR - description: Flash key register - byte_offset: 8 - access: Write - fieldset: KEYR - - name: OPTKEYR - description: Option byte key register - byte_offset: 12 - access: Write - fieldset: OPTKEYR - - name: SR - description: Status register - byte_offset: 16 - fieldset: SR - - name: CR - description: Flash control register - byte_offset: 20 - fieldset: CR - - name: ECCR - description: Flash ECC register - byte_offset: 24 - fieldset: ECCR - - name: OPTR - description: Flash option register - byte_offset: 32 - fieldset: OPTR - - name: PCROP1SR - description: Flash Bank 1 PCROP Start address register - byte_offset: 36 - fieldset: PCROP1SR - - name: PCROP1ER - description: Flash Bank 1 PCROP End address register - byte_offset: 40 - fieldset: PCROP1ER - - name: WRP1AR - description: Flash Bank 1 WRP area A address register - byte_offset: 44 - fieldset: WRP1AR - - name: WRP1BR - description: Flash Bank 1 WRP area B address register - byte_offset: 48 - fieldset: WRP1BR - - name: PCROP2SR - description: Flash Bank 2 PCROP Start address register - byte_offset: 68 - fieldset: PCROP2SR - - name: PCROP2ER - description: Flash Bank 2 PCROP End address register - byte_offset: 72 - fieldset: PCROP2ER - - name: WRP2AR - description: Flash Bank 2 WRP area A address register - byte_offset: 76 - fieldset: WRP2AR - - name: WRP2BR - description: Flash Bank 2 WRP area B address register - byte_offset: 80 - fieldset: WRP2BR + - name: ACR + description: Access control register + byte_offset: 0 + fieldset: ACR + - name: PDKEYR + description: Power down key register + byte_offset: 4 + access: Write + fieldset: PDKEYR + - name: KEYR + description: Flash key register + byte_offset: 8 + access: Write + fieldset: KEYR + - name: OPTKEYR + description: Option byte key register + byte_offset: 12 + access: Write + fieldset: OPTKEYR + - name: SR + description: Status register + byte_offset: 16 + fieldset: SR + - name: CR + description: Flash control register + byte_offset: 20 + fieldset: CR + - name: ECCR + description: Flash ECC register + byte_offset: 24 + fieldset: ECCR + - name: OPTR + description: Flash option register + byte_offset: 32 + fieldset: OPTR + - name: PCROP1SR + description: Flash Bank 1 PCROP Start address register + byte_offset: 36 + fieldset: PCROP1SR + - name: PCROP1ER + description: Flash Bank 1 PCROP End address register + byte_offset: 40 + fieldset: PCROP1ER + - name: WRP1AR + description: Flash Bank 1 WRP area A address register + byte_offset: 44 + fieldset: WRP1AR + - name: WRP1BR + description: Flash Bank 1 WRP area B address register + byte_offset: 48 + fieldset: WRP1BR + - name: PCROP2SR + description: Flash Bank 2 PCROP Start address register + byte_offset: 68 + fieldset: PCROP2SR + - name: PCROP2ER + description: Flash Bank 2 PCROP End address register + byte_offset: 72 + fieldset: PCROP2ER + - name: WRP2AR + description: Flash Bank 2 WRP area A address register + byte_offset: 76 + fieldset: WRP2AR + - name: WRP2BR + description: Flash Bank 2 WRP area B address register + byte_offset: 80 + fieldset: WRP2BR fieldset/ACR: description: Access control register fields: - - name: LATENCY - description: Latency - bit_offset: 0 - bit_size: 3 - - name: PRFTEN - description: Prefetch enable - bit_offset: 8 - bit_size: 1 - - name: ICEN - description: Instruction cache enable - bit_offset: 9 - bit_size: 1 - - name: DCEN - description: Data cache enable - bit_offset: 10 - bit_size: 1 - - name: ICRST - description: Instruction cache reset - bit_offset: 11 - bit_size: 1 - - name: DCRST - description: Data cache reset - bit_offset: 12 - bit_size: 1 - - name: RUN_PD - description: Flash Power-down mode during Low-power run mode - bit_offset: 13 - bit_size: 1 - - name: SLEEP_PD - description: Flash Power-down mode during Low-power sleep mode - bit_offset: 14 - bit_size: 1 + - name: LATENCY + description: Latency + bit_offset: 0 + bit_size: 3 + - name: PRFTEN + description: Prefetch enable + bit_offset: 8 + bit_size: 1 + - name: ICEN + description: Instruction cache enable + bit_offset: 9 + bit_size: 1 + - name: DCEN + description: Data cache enable + bit_offset: 10 + bit_size: 1 + - name: ICRST + description: Instruction cache reset + bit_offset: 11 + bit_size: 1 + - name: DCRST + description: Data cache reset + bit_offset: 12 + bit_size: 1 + - name: RUN_PD + description: Flash Power-down mode during Low-power run mode + bit_offset: 13 + bit_size: 1 + - name: SLEEP_PD + description: Flash Power-down mode during Low-power sleep mode + bit_offset: 14 + bit_size: 1 fieldset/CR: description: Flash control register fields: - - name: PG - description: Programming - bit_offset: 0 - bit_size: 1 - - name: PER - description: Page erase - bit_offset: 1 - bit_size: 1 - - name: MER - description: Bank 1 Mass erase - bit_offset: 2 - bit_size: 1 - array: - len: 2 - stride: 13 - - name: PNB - description: Page number - bit_offset: 3 - bit_size: 8 - - name: BKER - description: Bank erase - bit_offset: 11 - bit_size: 1 - - name: START - description: Start - bit_offset: 16 - bit_size: 1 - - name: OPTSTRT - description: Options modification start - bit_offset: 17 - bit_size: 1 - - name: FSTPG - description: Fast programming - bit_offset: 18 - bit_size: 1 - - name: EOPIE - description: End of operation interrupt enable - bit_offset: 24 - bit_size: 1 - - name: ERRIE - description: Error interrupt enable - bit_offset: 25 - bit_size: 1 - - name: RDERRIE - description: PCROP read error interrupt enable - bit_offset: 26 - bit_size: 1 - - name: OBL_LAUNCH - description: Force the option byte loading - bit_offset: 27 - bit_size: 1 - - name: OPTLOCK - description: Options Lock - bit_offset: 30 - bit_size: 1 - - name: LOCK - description: FLASH_CR Lock - bit_offset: 31 - bit_size: 1 + - name: PG + description: Programming + bit_offset: 0 + bit_size: 1 + - name: PER + description: Page erase + bit_offset: 1 + bit_size: 1 + - name: MER + description: Bank 1 Mass erase + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 13 + - name: PNB + description: Page number + bit_offset: 3 + bit_size: 8 + - name: BKER + description: Bank erase + bit_offset: 11 + bit_size: 1 + - name: START + description: Start + bit_offset: 16 + bit_size: 1 + - name: OPTSTRT + description: Options modification start + bit_offset: 17 + bit_size: 1 + - name: FSTPG + description: Fast programming + bit_offset: 18 + bit_size: 1 + - name: EOPIE + description: End of operation interrupt enable + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 25 + bit_size: 1 + - name: RDERRIE + description: PCROP read error interrupt enable + bit_offset: 26 + bit_size: 1 + - name: OBL_LAUNCH + description: Force the option byte loading + bit_offset: 27 + bit_size: 1 + - name: OPTLOCK + description: Options Lock + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: FLASH_CR Lock + bit_offset: 31 + bit_size: 1 fieldset/ECCR: description: Flash ECC register fields: - - name: ADDR_ECC - description: ECC fail address - bit_offset: 0 - bit_size: 19 - - name: BK_ECC - description: ECC fail bank - bit_offset: 19 - bit_size: 1 - - name: SYSF_ECC - description: System Flash ECC fail - bit_offset: 20 - bit_size: 1 - - name: ECCIE - description: ECC correction interrupt enable - bit_offset: 24 - bit_size: 1 - - name: ECCC - description: ECC correction - bit_offset: 30 - bit_size: 1 - - name: ECCD - description: ECC detection - bit_offset: 31 - bit_size: 1 + - name: ADDR_ECC + description: ECC fail address + bit_offset: 0 + bit_size: 19 + - name: BK_ECC + description: ECC fail bank + bit_offset: 19 + bit_size: 1 + - name: SYSF_ECC + description: System Flash ECC fail + bit_offset: 20 + bit_size: 1 + - name: ECCIE + description: ECC correction interrupt enable + bit_offset: 24 + bit_size: 1 + - name: ECCC + description: ECC correction + bit_offset: 30 + bit_size: 1 + - name: ECCD + description: ECC detection + bit_offset: 31 + bit_size: 1 fieldset/KEYR: description: Flash key register fields: - - name: KEYR - description: KEYR - bit_offset: 0 - bit_size: 32 + - name: KEYR + description: KEYR + bit_offset: 0 + bit_size: 32 fieldset/OPTKEYR: description: Option byte key register fields: - - name: OPTKEYR - description: Option byte key - bit_offset: 0 - bit_size: 32 + - name: OPTKEYR + description: Option byte key + bit_offset: 0 + bit_size: 32 fieldset/OPTR: description: Flash option register fields: - - name: RDP - description: Read protection level - bit_offset: 0 - bit_size: 8 - - name: BOR_LEV - description: BOR reset Level - bit_offset: 8 - bit_size: 3 - - name: nRST_STOP - description: nRST_STOP - bit_offset: 12 - bit_size: 1 - - name: nRST_STDBY - description: nRST_STDBY - bit_offset: 13 - bit_size: 1 - - name: IDWG_SW - description: Independent watchdog selection - bit_offset: 16 - bit_size: 1 - - name: IWDG_STOP - description: Independent watchdog counter freeze in Stop mode - bit_offset: 17 - bit_size: 1 - - name: IWDG_STDBY - description: Independent watchdog counter freeze in Standby mode - bit_offset: 18 - bit_size: 1 - - name: WWDG_SW - description: Window watchdog selection - bit_offset: 19 - bit_size: 1 - - name: BFB - description: Dual-bank boot - bit_offset: 20 - bit_size: 1 - - name: DUALBANK - description: Dual-Bank on 512 KB or 256 KB Flash memory devices - bit_offset: 21 - bit_size: 1 - - name: nBOOT1 - description: Boot configuration - bit_offset: 23 - bit_size: 1 - - name: SRAM2_PE - description: SRAM2 parity check enable - bit_offset: 24 - bit_size: 1 - - name: SRAM2_RST - description: SRAM2 Erase when system reset - bit_offset: 25 - bit_size: 1 - - name: nSWBOOT0 - description: Software BOOT0 - bit_offset: 26 - bit_size: 1 - - name: nBOOT0 - description: nBOOT0 option bit - bit_offset: 27 - bit_size: 1 + - name: RDP + description: Read protection level + bit_offset: 0 + bit_size: 8 + - name: BOR_LEV + description: BOR reset Level + bit_offset: 8 + bit_size: 3 + - name: nRST_STOP + description: nRST_STOP + bit_offset: 12 + bit_size: 1 + - name: nRST_STDBY + description: nRST_STDBY + bit_offset: 13 + bit_size: 1 + - name: IDWG_SW + description: Independent watchdog selection + bit_offset: 16 + bit_size: 1 + - name: IWDG_STOP + description: Independent watchdog counter freeze in Stop mode + bit_offset: 17 + bit_size: 1 + - name: IWDG_STDBY + description: Independent watchdog counter freeze in Standby mode + bit_offset: 18 + bit_size: 1 + - name: WWDG_SW + description: Window watchdog selection + bit_offset: 19 + bit_size: 1 + - name: BFB + description: Dual-bank boot + bit_offset: 20 + bit_size: 1 + - name: DUALBANK + description: Dual-Bank on 512 KB or 256 KB Flash memory devices + bit_offset: 21 + bit_size: 1 + - name: nBOOT1 + description: Boot configuration + bit_offset: 23 + bit_size: 1 + - name: SRAM2_PE + description: SRAM2 parity check enable + bit_offset: 24 + bit_size: 1 + - name: SRAM2_RST + description: SRAM2 Erase when system reset + bit_offset: 25 + bit_size: 1 + - name: nSWBOOT0 + description: Software BOOT0 + bit_offset: 26 + bit_size: 1 + - name: nBOOT0 + description: nBOOT0 option bit + bit_offset: 27 + bit_size: 1 fieldset/PCROP1ER: description: Flash Bank 1 PCROP End address register fields: - - name: PCROP1_END - description: Bank 1 PCROP area end offset - bit_offset: 0 - bit_size: 16 - - name: PCROP_RDP - description: PCROP area preserved when RDP level decreased - bit_offset: 31 - bit_size: 1 + - name: PCROP1_END + description: Bank 1 PCROP area end offset + bit_offset: 0 + bit_size: 16 + - name: PCROP_RDP + description: PCROP area preserved when RDP level decreased + bit_offset: 31 + bit_size: 1 fieldset/PCROP1SR: description: Flash Bank 1 PCROP Start address register fields: - - name: PCROP1_STRT - description: Bank 1 PCROP area start offset - bit_offset: 0 - bit_size: 16 + - name: PCROP1_STRT + description: Bank 1 PCROP area start offset + bit_offset: 0 + bit_size: 16 fieldset/PCROP2ER: description: Flash Bank 2 PCROP End address register fields: - - name: PCROP2_END - description: Bank 2 PCROP area end offset - bit_offset: 0 - bit_size: 16 + - name: PCROP2_END + description: Bank 2 PCROP area end offset + bit_offset: 0 + bit_size: 16 fieldset/PCROP2SR: description: Flash Bank 2 PCROP Start address register fields: - - name: PCROP2_STRT - description: Bank 2 PCROP area start offset - bit_offset: 0 - bit_size: 16 + - name: PCROP2_STRT + description: Bank 2 PCROP area start offset + bit_offset: 0 + bit_size: 16 fieldset/PDKEYR: description: Power down key register fields: - - name: PDKEYR - description: RUN_PD in FLASH_ACR key - bit_offset: 0 - bit_size: 32 + - name: PDKEYR + description: RUN_PD in FLASH_ACR key + bit_offset: 0 + bit_size: 32 fieldset/SR: description: Status register fields: - - name: EOP - description: End of operation - bit_offset: 0 - bit_size: 1 - - name: OPERR - description: Operation error - bit_offset: 1 - bit_size: 1 - - name: PROGERR - description: Programming error - bit_offset: 3 - bit_size: 1 - - name: WRPERR - description: Write protected error - bit_offset: 4 - bit_size: 1 - - name: PGAERR - description: Programming alignment error - bit_offset: 5 - bit_size: 1 - - name: SIZERR - description: Size error - bit_offset: 6 - bit_size: 1 - - name: PGSERR - description: Programming sequence error - bit_offset: 7 - bit_size: 1 - - name: MISERR - description: Fast programming data miss error - bit_offset: 8 - bit_size: 1 - - name: FASTERR - description: Fast programming error - bit_offset: 9 - bit_size: 1 - - name: RDERR - description: PCROP read error - bit_offset: 14 - bit_size: 1 - - name: OPTVERR - description: Option validity error - bit_offset: 15 - bit_size: 1 - - name: BSY - description: Busy - bit_offset: 16 - bit_size: 1 + - name: EOP + description: End of operation + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: Operation error + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: Programming error + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: Write protected error + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: Programming alignment error + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: Size error + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: Programming sequence error + bit_offset: 7 + bit_size: 1 + - name: MISERR + description: Fast programming data miss error + bit_offset: 8 + bit_size: 1 + - name: FASTERR + description: Fast programming error + bit_offset: 9 + bit_size: 1 + - name: RDERR + description: PCROP read error + bit_offset: 14 + bit_size: 1 + - name: OPTVERR + description: Option validity error + bit_offset: 15 + bit_size: 1 + - name: BSY + description: Busy + bit_offset: 16 + bit_size: 1 fieldset/WRP1AR: description: Flash Bank 1 WRP area A address register fields: - - name: WRP1A_STRT - description: Bank 1 WRP first area tart offset - bit_offset: 0 - bit_size: 8 - - name: WRP1A_END - description: Bank 1 WRP first area A end offset - bit_offset: 16 - bit_size: 8 + - name: WRP1A_STRT + description: Bank 1 WRP first area tart offset + bit_offset: 0 + bit_size: 8 + - name: WRP1A_END + description: Bank 1 WRP first area A end offset + bit_offset: 16 + bit_size: 8 fieldset/WRP1BR: description: Flash Bank 1 WRP area B address register fields: - - name: WRP1B_STRT - description: Bank 1 WRP second area B start offset - bit_offset: 0 - bit_size: 8 - - name: WRP1B_END - description: Bank 1 WRP second area B end offset - bit_offset: 16 - bit_size: 8 + - name: WRP1B_STRT + description: Bank 1 WRP second area B start offset + bit_offset: 0 + bit_size: 8 + - name: WRP1B_END + description: Bank 1 WRP second area B end offset + bit_offset: 16 + bit_size: 8 fieldset/WRP2AR: description: Flash Bank 2 WRP area A address register fields: - - name: WRP2A_STRT - description: Bank 2 WRP first area A start offset - bit_offset: 0 - bit_size: 8 - - name: WRP2A_END - description: Bank 2 WRP first area A end offset - bit_offset: 16 - bit_size: 8 + - name: WRP2A_STRT + description: Bank 2 WRP first area A start offset + bit_offset: 0 + bit_size: 8 + - name: WRP2A_END + description: Bank 2 WRP first area A end offset + bit_offset: 16 + bit_size: 8 fieldset/WRP2BR: description: Flash Bank 2 WRP area B address register fields: - - name: WRP2B_STRT - description: Bank 2 WRP second area B start offset - bit_offset: 0 - bit_size: 8 - - name: WRP2B_END - description: Bank 2 WRP second area B end offset - bit_offset: 16 - bit_size: 8 + - name: WRP2B_STRT + description: Bank 2 WRP second area B start offset + bit_offset: 0 + bit_size: 8 + - name: WRP2B_END + description: Bank 2 WRP second area B end offset + bit_offset: 16 + bit_size: 8 diff --git a/data/registers/flash_l5.yaml b/data/registers/flash_l5.yaml index 20edc2a..8bce6ee 100644 --- a/data/registers/flash_l5.yaml +++ b/data/registers/flash_l5.yaml @@ -1,698 +1,697 @@ ---- block/FLASH: description: Flash items: - - name: ACR - description: Access control register - byte_offset: 0 - fieldset: ACR - - name: PDKEYR - description: Power down key register - byte_offset: 4 - access: Write - fieldset: PDKEYR - - name: NSKEYR - description: Flash non-secure key register - byte_offset: 8 - access: Write - fieldset: NSKEYR - - name: SECKEYR - description: Flash secure key register - byte_offset: 12 - access: Write - fieldset: SECKEYR - - name: OPTKEYR - description: Flash option key register - byte_offset: 16 - access: Write - fieldset: OPTKEYR - - name: LVEKEYR - description: Flash low voltage key register - byte_offset: 20 - access: Write - fieldset: LVEKEYR - - name: NSSR - description: Flash status register - byte_offset: 32 - fieldset: NSSR - - name: SECSR - description: Flash status register - byte_offset: 36 - fieldset: SECSR - - name: NSCR - description: Flash non-secure control register - byte_offset: 40 - fieldset: NSCR - - name: SECCR - description: Flash secure control register - byte_offset: 44 - fieldset: SECCR - - name: ECCR - description: Flash ECC register - byte_offset: 48 - fieldset: ECCR - - name: OPTR - description: Flash option register - byte_offset: 64 - fieldset: OPTR - - name: NSBOOTADD0R - description: Flash non-secure boot address 0 register - byte_offset: 68 - access: Write - fieldset: NSBOOTADD0R - - name: NSBOOTADD1R - description: Flash non-secure boot address 1 register - byte_offset: 72 - access: Write - fieldset: NSBOOTADD1R - - name: SECBOOTADD0R - description: FFlash secure boot address 0 register - byte_offset: 76 - fieldset: SECBOOTADD0R - - name: SECWM1R1 - description: Flash bank 1 secure watermak1 register - byte_offset: 80 - fieldset: SECWM1R1 - - name: SECWM1R2 - description: Flash secure watermak1 register 2 - byte_offset: 84 - fieldset: SECWM1R2 - - name: WRP1AR - description: Flash Bank 1 WRP area A address register - byte_offset: 88 - fieldset: WRP1AR - - name: WRP1BR - description: Flash Bank 1 WRP area B address register - byte_offset: 92 - fieldset: WRP1BR - - name: SECWM2R1 - description: Flash secure watermak2 register - byte_offset: 96 - fieldset: SECWM2R1 - - name: SECWM2R2 - description: Flash secure watermak2 register2 - byte_offset: 100 - fieldset: SECWM2R2 - - name: WRP2AR - description: Flash WPR2 area A address register - byte_offset: 104 - fieldset: WRP2AR - - name: WRP2BR - description: Flash WPR2 area B address register - byte_offset: 108 - fieldset: WRP2BR - - name: SECBB1R1 - description: FLASH secure block based bank 1 register - byte_offset: 128 - fieldset: SECBB1R1 - - name: SECBB1R2 - description: FLASH secure block based bank 1 register - byte_offset: 132 - fieldset: SECBB1R2 - - name: SECBB1R3 - description: FLASH secure block based bank 1 register - byte_offset: 136 - fieldset: SECBB1R3 - - name: SECBB1R4 - description: FLASH secure block based bank 1 register - byte_offset: 140 - fieldset: SECBB1R4 - - name: SECBB2R1 - description: FLASH secure block based bank 2 register - byte_offset: 160 - fieldset: SECBB2R1 - - name: SECBB2R2 - description: FLASH secure block based bank 2 register - byte_offset: 164 - fieldset: SECBB2R2 - - name: SECBB2R3 - description: FLASH secure block based bank 2 register - byte_offset: 168 - fieldset: SECBB2R3 - - name: SECBB2R4 - description: FLASH secure block based bank 2 register - byte_offset: 172 - fieldset: SECBB2R4 - - name: SECHDPCR - description: FLASH secure HDP control register - byte_offset: 192 - fieldset: SECHDPCR - - name: PRIVCFGR - description: Power privilege configuration register - byte_offset: 196 - fieldset: PRIVCFGR + - name: ACR + description: Access control register + byte_offset: 0 + fieldset: ACR + - name: PDKEYR + description: Power down key register + byte_offset: 4 + access: Write + fieldset: PDKEYR + - name: NSKEYR + description: Flash non-secure key register + byte_offset: 8 + access: Write + fieldset: NSKEYR + - name: SECKEYR + description: Flash secure key register + byte_offset: 12 + access: Write + fieldset: SECKEYR + - name: OPTKEYR + description: Flash option key register + byte_offset: 16 + access: Write + fieldset: OPTKEYR + - name: LVEKEYR + description: Flash low voltage key register + byte_offset: 20 + access: Write + fieldset: LVEKEYR + - name: NSSR + description: Flash status register + byte_offset: 32 + fieldset: NSSR + - name: SECSR + description: Flash status register + byte_offset: 36 + fieldset: SECSR + - name: NSCR + description: Flash non-secure control register + byte_offset: 40 + fieldset: NSCR + - name: SECCR + description: Flash secure control register + byte_offset: 44 + fieldset: SECCR + - name: ECCR + description: Flash ECC register + byte_offset: 48 + fieldset: ECCR + - name: OPTR + description: Flash option register + byte_offset: 64 + fieldset: OPTR + - name: NSBOOTADD0R + description: Flash non-secure boot address 0 register + byte_offset: 68 + access: Write + fieldset: NSBOOTADD0R + - name: NSBOOTADD1R + description: Flash non-secure boot address 1 register + byte_offset: 72 + access: Write + fieldset: NSBOOTADD1R + - name: SECBOOTADD0R + description: FFlash secure boot address 0 register + byte_offset: 76 + fieldset: SECBOOTADD0R + - name: SECWM1R1 + description: Flash bank 1 secure watermak1 register + byte_offset: 80 + fieldset: SECWM1R1 + - name: SECWM1R2 + description: Flash secure watermak1 register 2 + byte_offset: 84 + fieldset: SECWM1R2 + - name: WRP1AR + description: Flash Bank 1 WRP area A address register + byte_offset: 88 + fieldset: WRP1AR + - name: WRP1BR + description: Flash Bank 1 WRP area B address register + byte_offset: 92 + fieldset: WRP1BR + - name: SECWM2R1 + description: Flash secure watermak2 register + byte_offset: 96 + fieldset: SECWM2R1 + - name: SECWM2R2 + description: Flash secure watermak2 register2 + byte_offset: 100 + fieldset: SECWM2R2 + - name: WRP2AR + description: Flash WPR2 area A address register + byte_offset: 104 + fieldset: WRP2AR + - name: WRP2BR + description: Flash WPR2 area B address register + byte_offset: 108 + fieldset: WRP2BR + - name: SECBB1R1 + description: FLASH secure block based bank 1 register + byte_offset: 128 + fieldset: SECBB1R1 + - name: SECBB1R2 + description: FLASH secure block based bank 1 register + byte_offset: 132 + fieldset: SECBB1R2 + - name: SECBB1R3 + description: FLASH secure block based bank 1 register + byte_offset: 136 + fieldset: SECBB1R3 + - name: SECBB1R4 + description: FLASH secure block based bank 1 register + byte_offset: 140 + fieldset: SECBB1R4 + - name: SECBB2R1 + description: FLASH secure block based bank 2 register + byte_offset: 160 + fieldset: SECBB2R1 + - name: SECBB2R2 + description: FLASH secure block based bank 2 register + byte_offset: 164 + fieldset: SECBB2R2 + - name: SECBB2R3 + description: FLASH secure block based bank 2 register + byte_offset: 168 + fieldset: SECBB2R3 + - name: SECBB2R4 + description: FLASH secure block based bank 2 register + byte_offset: 172 + fieldset: SECBB2R4 + - name: SECHDPCR + description: FLASH secure HDP control register + byte_offset: 192 + fieldset: SECHDPCR + - name: PRIVCFGR + description: Power privilege configuration register + byte_offset: 196 + fieldset: PRIVCFGR fieldset/ACR: description: Access control register fields: - - name: LATENCY - description: Latency - bit_offset: 0 - bit_size: 4 - - name: RUN_PD - description: Flash Power-down mode during Low-power run mode - bit_offset: 13 - bit_size: 1 - - name: SLEEP_PD - description: Flash Power-down mode during Low-power sleep mode - bit_offset: 14 - bit_size: 1 - - name: LVEN - description: LVEN - bit_offset: 15 - bit_size: 1 + - name: LATENCY + description: Latency + bit_offset: 0 + bit_size: 4 + - name: RUN_PD + description: Flash Power-down mode during Low-power run mode + bit_offset: 13 + bit_size: 1 + - name: SLEEP_PD + description: Flash Power-down mode during Low-power sleep mode + bit_offset: 14 + bit_size: 1 + - name: LVEN + description: LVEN + bit_offset: 15 + bit_size: 1 fieldset/ECCR: description: Flash ECC register fields: - - name: ADDR_ECC - description: ECC fail address - bit_offset: 0 - bit_size: 19 - - name: BK_ECC - description: BK_ECC - bit_offset: 21 - bit_size: 1 - - name: SYSF_ECC - description: SYSF_ECC - bit_offset: 22 - bit_size: 1 - - name: ECCIE - description: ECC correction interrupt enable - bit_offset: 24 - bit_size: 1 - - name: ECCC2 - description: ECCC2 - bit_offset: 28 - bit_size: 1 - - name: ECCD2 - description: ECCD2 - bit_offset: 29 - bit_size: 1 - - name: ECCC - description: ECC correction - bit_offset: 30 - bit_size: 1 - - name: ECCD - description: ECC detection - bit_offset: 31 - bit_size: 1 + - name: ADDR_ECC + description: ECC fail address + bit_offset: 0 + bit_size: 19 + - name: BK_ECC + description: BK_ECC + bit_offset: 21 + bit_size: 1 + - name: SYSF_ECC + description: SYSF_ECC + bit_offset: 22 + bit_size: 1 + - name: ECCIE + description: ECC correction interrupt enable + bit_offset: 24 + bit_size: 1 + - name: ECCC2 + description: ECCC2 + bit_offset: 28 + bit_size: 1 + - name: ECCD2 + description: ECCD2 + bit_offset: 29 + bit_size: 1 + - name: ECCC + description: ECC correction + bit_offset: 30 + bit_size: 1 + - name: ECCD + description: ECC detection + bit_offset: 31 + bit_size: 1 fieldset/LVEKEYR: description: Flash low voltage key register fields: - - name: LVEKEYR - description: LVEKEYR - bit_offset: 0 - bit_size: 32 + - name: LVEKEYR + description: LVEKEYR + bit_offset: 0 + bit_size: 32 fieldset/NSBOOTADD0R: description: Flash non-secure boot address 0 register fields: - - name: NSBOOTADD0 - description: NSBOOTADD0 - bit_offset: 7 - bit_size: 25 + - name: NSBOOTADD0 + description: NSBOOTADD0 + bit_offset: 7 + bit_size: 25 fieldset/NSBOOTADD1R: description: Flash non-secure boot address 1 register fields: - - name: NSBOOTADD1 - description: NSBOOTADD1 - bit_offset: 7 - bit_size: 25 + - name: NSBOOTADD1 + description: NSBOOTADD1 + bit_offset: 7 + bit_size: 25 fieldset/NSCR: description: Flash non-secure control register fields: - - name: NSPG - description: NSPG - bit_offset: 0 - bit_size: 1 - - name: NSPER - description: NSPER - bit_offset: 1 - bit_size: 1 - - name: NSMER1 - description: NSMER1 - bit_offset: 2 - bit_size: 1 - - name: NSPNB - description: NSPNB - bit_offset: 3 - bit_size: 7 - - name: NSBKER - description: NSBKER - bit_offset: 11 - bit_size: 1 - - name: NSMER2 - description: NSMER2 - bit_offset: 15 - bit_size: 1 - - name: NSSTRT - description: Options modification start - bit_offset: 16 - bit_size: 1 - - name: OPTSTRT - description: Options modification start - bit_offset: 17 - bit_size: 1 - - name: NSEOPIE - description: NSEOPIE - bit_offset: 24 - bit_size: 1 - - name: NSERRIE - description: NSERRIE - bit_offset: 25 - bit_size: 1 - - name: OBL_LAUNCH - description: Force the option byte loading - bit_offset: 27 - bit_size: 1 - - name: OPTLOCK - description: Options Lock - bit_offset: 30 - bit_size: 1 - - name: NSLOCK - description: NSLOCK - bit_offset: 31 - bit_size: 1 + - name: NSPG + description: NSPG + bit_offset: 0 + bit_size: 1 + - name: NSPER + description: NSPER + bit_offset: 1 + bit_size: 1 + - name: NSMER1 + description: NSMER1 + bit_offset: 2 + bit_size: 1 + - name: NSPNB + description: NSPNB + bit_offset: 3 + bit_size: 7 + - name: NSBKER + description: NSBKER + bit_offset: 11 + bit_size: 1 + - name: NSMER2 + description: NSMER2 + bit_offset: 15 + bit_size: 1 + - name: NSSTRT + description: Options modification start + bit_offset: 16 + bit_size: 1 + - name: OPTSTRT + description: Options modification start + bit_offset: 17 + bit_size: 1 + - name: NSEOPIE + description: NSEOPIE + bit_offset: 24 + bit_size: 1 + - name: NSERRIE + description: NSERRIE + bit_offset: 25 + bit_size: 1 + - name: OBL_LAUNCH + description: Force the option byte loading + bit_offset: 27 + bit_size: 1 + - name: OPTLOCK + description: Options Lock + bit_offset: 30 + bit_size: 1 + - name: NSLOCK + description: NSLOCK + bit_offset: 31 + bit_size: 1 fieldset/NSKEYR: description: Flash non-secure key register fields: - - name: NSKEYR - description: NSKEYR - bit_offset: 0 - bit_size: 32 + - name: NSKEYR + description: NSKEYR + bit_offset: 0 + bit_size: 32 fieldset/NSSR: description: Flash status register fields: - - name: NSEOP - description: NSEOP - bit_offset: 0 - bit_size: 1 - - name: NSOPERR - description: NSOPERR - bit_offset: 1 - bit_size: 1 - - name: NSPROGERR - description: NSPROGERR - bit_offset: 3 - bit_size: 1 - - name: NSWRPERR - description: NSWRPERR - bit_offset: 4 - bit_size: 1 - - name: NSPGAERR - description: NSPGAERR - bit_offset: 5 - bit_size: 1 - - name: NSSIZERR - description: NSSIZERR - bit_offset: 6 - bit_size: 1 - - name: NSPGSERR - description: NSPGSERR - bit_offset: 7 - bit_size: 1 - - name: OPTWERR - description: OPTWERR - bit_offset: 13 - bit_size: 1 - - name: OPTVERR - description: OPTVERR - bit_offset: 15 - bit_size: 1 - - name: NSBSY - description: NSBusy - bit_offset: 16 - bit_size: 1 + - name: NSEOP + description: NSEOP + bit_offset: 0 + bit_size: 1 + - name: NSOPERR + description: NSOPERR + bit_offset: 1 + bit_size: 1 + - name: NSPROGERR + description: NSPROGERR + bit_offset: 3 + bit_size: 1 + - name: NSWRPERR + description: NSWRPERR + bit_offset: 4 + bit_size: 1 + - name: NSPGAERR + description: NSPGAERR + bit_offset: 5 + bit_size: 1 + - name: NSSIZERR + description: NSSIZERR + bit_offset: 6 + bit_size: 1 + - name: NSPGSERR + description: NSPGSERR + bit_offset: 7 + bit_size: 1 + - name: OPTWERR + description: OPTWERR + bit_offset: 13 + bit_size: 1 + - name: OPTVERR + description: OPTVERR + bit_offset: 15 + bit_size: 1 + - name: NSBSY + description: NSBusy + bit_offset: 16 + bit_size: 1 fieldset/OPTKEYR: description: Flash option key register fields: - - name: OPTKEYR - description: OPTKEYR - bit_offset: 0 - bit_size: 32 + - name: OPTKEYR + description: OPTKEYR + bit_offset: 0 + bit_size: 32 fieldset/OPTR: description: Flash option register fields: - - name: RDP - description: Read protection level - bit_offset: 0 - bit_size: 8 - - name: BOR_LEV - description: BOR reset Level - bit_offset: 8 - bit_size: 3 - - name: nRST_STOP - description: nRST_STOP - bit_offset: 12 - bit_size: 1 - - name: nRST_STDBY - description: nRST_STDBY - bit_offset: 13 - bit_size: 1 - - name: nRST_SHDW - description: nRST_SHDW - bit_offset: 14 - bit_size: 1 - - name: IWDG_SW - description: Independent watchdog selection - bit_offset: 16 - bit_size: 1 - - name: IWDG_STOP - description: Independent watchdog counter freeze in Stop mode - bit_offset: 17 - bit_size: 1 - - name: IWDG_STDBY - description: Independent watchdog counter freeze in Standby mode - bit_offset: 18 - bit_size: 1 - - name: WWDG_SW - description: Window watchdog selection - bit_offset: 19 - bit_size: 1 - - name: SWAP_BANK - description: SWAP_BANK - bit_offset: 20 - bit_size: 1 - - name: DB256K - description: DB256K - bit_offset: 21 - bit_size: 1 - - name: DBANK - description: DBANK - bit_offset: 22 - bit_size: 1 - - name: SRAM2_PE - description: SRAM2 parity check enable - bit_offset: 24 - bit_size: 1 - - name: SRAM2_RST - description: SRAM2 Erase when system reset - bit_offset: 25 - bit_size: 1 - - name: nSWBOOT0 - description: nSWBOOT0 - bit_offset: 26 - bit_size: 1 - - name: nBOOT0 - description: nBOOT0 - bit_offset: 27 - bit_size: 1 - - name: PA15_PUPEN - description: PA15_PUPEN - bit_offset: 28 - bit_size: 1 - - name: TZEN - description: TZEN - bit_offset: 31 - bit_size: 1 + - name: RDP + description: Read protection level + bit_offset: 0 + bit_size: 8 + - name: BOR_LEV + description: BOR reset Level + bit_offset: 8 + bit_size: 3 + - name: nRST_STOP + description: nRST_STOP + bit_offset: 12 + bit_size: 1 + - name: nRST_STDBY + description: nRST_STDBY + bit_offset: 13 + bit_size: 1 + - name: nRST_SHDW + description: nRST_SHDW + bit_offset: 14 + bit_size: 1 + - name: IWDG_SW + description: Independent watchdog selection + bit_offset: 16 + bit_size: 1 + - name: IWDG_STOP + description: Independent watchdog counter freeze in Stop mode + bit_offset: 17 + bit_size: 1 + - name: IWDG_STDBY + description: Independent watchdog counter freeze in Standby mode + bit_offset: 18 + bit_size: 1 + - name: WWDG_SW + description: Window watchdog selection + bit_offset: 19 + bit_size: 1 + - name: SWAP_BANK + description: SWAP_BANK + bit_offset: 20 + bit_size: 1 + - name: DB256K + description: DB256K + bit_offset: 21 + bit_size: 1 + - name: DBANK + description: DBANK + bit_offset: 22 + bit_size: 1 + - name: SRAM2_PE + description: SRAM2 parity check enable + bit_offset: 24 + bit_size: 1 + - name: SRAM2_RST + description: SRAM2 Erase when system reset + bit_offset: 25 + bit_size: 1 + - name: nSWBOOT0 + description: nSWBOOT0 + bit_offset: 26 + bit_size: 1 + - name: nBOOT0 + description: nBOOT0 + bit_offset: 27 + bit_size: 1 + - name: PA15_PUPEN + description: PA15_PUPEN + bit_offset: 28 + bit_size: 1 + - name: TZEN + description: TZEN + bit_offset: 31 + bit_size: 1 fieldset/PDKEYR: description: Power down key register fields: - - name: PDKEYR - description: RUN_PD in FLASH_ACR key - bit_offset: 0 - bit_size: 32 + - name: PDKEYR + description: RUN_PD in FLASH_ACR key + bit_offset: 0 + bit_size: 32 fieldset/PRIVCFGR: description: Power privilege configuration register fields: - - name: PRIV - description: PRIV - bit_offset: 0 - bit_size: 1 + - name: PRIV + description: PRIV + bit_offset: 0 + bit_size: 1 fieldset/SECBB1R1: description: FLASH secure block based bank 1 register fields: - - name: SECBB1 - description: SECBB1 - bit_offset: 0 - bit_size: 32 + - name: SECBB1 + description: SECBB1 + bit_offset: 0 + bit_size: 32 fieldset/SECBB1R2: description: FLASH secure block based bank 1 register fields: - - name: SECBB1 - description: SECBB1 - bit_offset: 0 - bit_size: 32 + - name: SECBB1 + description: SECBB1 + bit_offset: 0 + bit_size: 32 fieldset/SECBB1R3: description: FLASH secure block based bank 1 register fields: - - name: SECBB1 - description: SECBB1 - bit_offset: 0 - bit_size: 32 + - name: SECBB1 + description: SECBB1 + bit_offset: 0 + bit_size: 32 fieldset/SECBB1R4: description: FLASH secure block based bank 1 register fields: - - name: SECBB1 - description: SECBB1 - bit_offset: 0 - bit_size: 32 + - name: SECBB1 + description: SECBB1 + bit_offset: 0 + bit_size: 32 fieldset/SECBB2R1: description: FLASH secure block based bank 2 register fields: - - name: SECBB2 - description: SECBB2 - bit_offset: 0 - bit_size: 32 + - name: SECBB2 + description: SECBB2 + bit_offset: 0 + bit_size: 32 fieldset/SECBB2R2: description: FLASH secure block based bank 2 register fields: - - name: SECBB2 - description: SECBB2 - bit_offset: 0 - bit_size: 32 + - name: SECBB2 + description: SECBB2 + bit_offset: 0 + bit_size: 32 fieldset/SECBB2R3: description: FLASH secure block based bank 2 register fields: - - name: SECBB2 - description: SECBB2 - bit_offset: 0 - bit_size: 32 + - name: SECBB2 + description: SECBB2 + bit_offset: 0 + bit_size: 32 fieldset/SECBB2R4: description: FLASH secure block based bank 2 register fields: - - name: SECBB2 - description: SECBB2 - bit_offset: 0 - bit_size: 32 + - name: SECBB2 + description: SECBB2 + bit_offset: 0 + bit_size: 32 fieldset/SECBOOTADD0R: description: FFlash secure boot address 0 register fields: - - name: BOOT_LOCK - description: BOOT_LOCK - bit_offset: 0 - bit_size: 1 - - name: SECBOOTADD0 - description: SECBOOTADD0 - bit_offset: 7 - bit_size: 25 + - name: BOOT_LOCK + description: BOOT_LOCK + bit_offset: 0 + bit_size: 1 + - name: SECBOOTADD0 + description: SECBOOTADD0 + bit_offset: 7 + bit_size: 25 fieldset/SECCR: description: Flash secure control register fields: - - name: SECPG - description: SECPG - bit_offset: 0 - bit_size: 1 - - name: SECPER - description: SECPER - bit_offset: 1 - bit_size: 1 - - name: SECMER1 - description: SECMER1 - bit_offset: 2 - bit_size: 1 - - name: SECPNB - description: SECPNB - bit_offset: 3 - bit_size: 7 - - name: SECBKER - description: SECBKER - bit_offset: 11 - bit_size: 1 - - name: SECMER2 - description: SECMER2 - bit_offset: 15 - bit_size: 1 - - name: SECSTRT - description: SECSTRT - bit_offset: 16 - bit_size: 1 - - name: SECEOPIE - description: SECEOPIE - bit_offset: 24 - bit_size: 1 - - name: SECERRIE - description: SECERRIE - bit_offset: 25 - bit_size: 1 - - name: SECRDERRIE - description: SECRDERRIE - bit_offset: 26 - bit_size: 1 - - name: SECINV - description: SECINV - bit_offset: 29 - bit_size: 1 - - name: SECLOCK - description: SECLOCK - bit_offset: 31 - bit_size: 1 + - name: SECPG + description: SECPG + bit_offset: 0 + bit_size: 1 + - name: SECPER + description: SECPER + bit_offset: 1 + bit_size: 1 + - name: SECMER1 + description: SECMER1 + bit_offset: 2 + bit_size: 1 + - name: SECPNB + description: SECPNB + bit_offset: 3 + bit_size: 7 + - name: SECBKER + description: SECBKER + bit_offset: 11 + bit_size: 1 + - name: SECMER2 + description: SECMER2 + bit_offset: 15 + bit_size: 1 + - name: SECSTRT + description: SECSTRT + bit_offset: 16 + bit_size: 1 + - name: SECEOPIE + description: SECEOPIE + bit_offset: 24 + bit_size: 1 + - name: SECERRIE + description: SECERRIE + bit_offset: 25 + bit_size: 1 + - name: SECRDERRIE + description: SECRDERRIE + bit_offset: 26 + bit_size: 1 + - name: SECINV + description: SECINV + bit_offset: 29 + bit_size: 1 + - name: SECLOCK + description: SECLOCK + bit_offset: 31 + bit_size: 1 fieldset/SECHDPCR: description: FLASH secure HDP control register fields: - - name: HDP1_ACCDIS - description: HDP1_ACCDIS - bit_offset: 0 - bit_size: 1 - - name: HDP2_ACCDIS - description: HDP2_ACCDIS - bit_offset: 1 - bit_size: 1 + - name: HDP1_ACCDIS + description: HDP1_ACCDIS + bit_offset: 0 + bit_size: 1 + - name: HDP2_ACCDIS + description: HDP2_ACCDIS + bit_offset: 1 + bit_size: 1 fieldset/SECKEYR: description: Flash secure key register fields: - - name: SECKEYR - description: SECKEYR - bit_offset: 0 - bit_size: 32 + - name: SECKEYR + description: SECKEYR + bit_offset: 0 + bit_size: 32 fieldset/SECSR: description: Flash status register fields: - - name: SECEOP - description: SECEOP - bit_offset: 0 - bit_size: 1 - - name: SECOPERR - description: SECOPERR - bit_offset: 1 - bit_size: 1 - - name: SECPROGERR - description: SECPROGERR - bit_offset: 3 - bit_size: 1 - - name: SECWRPERR - description: SECWRPERR - bit_offset: 4 - bit_size: 1 - - name: SECPGAERR - description: SECPGAERR - bit_offset: 5 - bit_size: 1 - - name: SECSIZERR - description: SECSIZERR - bit_offset: 6 - bit_size: 1 - - name: SECPGSERR - description: SECPGSERR - bit_offset: 7 - bit_size: 1 - - name: SECRDERR - description: Secure read protection error - bit_offset: 14 - bit_size: 1 - - name: SECBSY - description: SECBusy - bit_offset: 16 - bit_size: 1 + - name: SECEOP + description: SECEOP + bit_offset: 0 + bit_size: 1 + - name: SECOPERR + description: SECOPERR + bit_offset: 1 + bit_size: 1 + - name: SECPROGERR + description: SECPROGERR + bit_offset: 3 + bit_size: 1 + - name: SECWRPERR + description: SECWRPERR + bit_offset: 4 + bit_size: 1 + - name: SECPGAERR + description: SECPGAERR + bit_offset: 5 + bit_size: 1 + - name: SECSIZERR + description: SECSIZERR + bit_offset: 6 + bit_size: 1 + - name: SECPGSERR + description: SECPGSERR + bit_offset: 7 + bit_size: 1 + - name: SECRDERR + description: Secure read protection error + bit_offset: 14 + bit_size: 1 + - name: SECBSY + description: SECBusy + bit_offset: 16 + bit_size: 1 fieldset/SECWM1R1: description: Flash bank 1 secure watermak1 register fields: - - name: SECWM1_PSTRT - description: SECWM1_PSTRT - bit_offset: 0 - bit_size: 7 - - name: SECWM1_PEND - description: SECWM1_PEND - bit_offset: 16 - bit_size: 7 + - name: SECWM1_PSTRT + description: SECWM1_PSTRT + bit_offset: 0 + bit_size: 7 + - name: SECWM1_PEND + description: SECWM1_PEND + bit_offset: 16 + bit_size: 7 fieldset/SECWM1R2: description: Flash secure watermak1 register 2 fields: - - name: PCROP1_PSTRT - description: PCROP1_PSTRT - bit_offset: 0 - bit_size: 7 - - name: PCROP1EN - description: PCROP1EN - bit_offset: 15 - bit_size: 1 - - name: HDP1_PEND - description: HDP1_PEND - bit_offset: 16 - bit_size: 7 - - name: HDP1EN - description: HDP1EN - bit_offset: 31 - bit_size: 1 + - name: PCROP1_PSTRT + description: PCROP1_PSTRT + bit_offset: 0 + bit_size: 7 + - name: PCROP1EN + description: PCROP1EN + bit_offset: 15 + bit_size: 1 + - name: HDP1_PEND + description: HDP1_PEND + bit_offset: 16 + bit_size: 7 + - name: HDP1EN + description: HDP1EN + bit_offset: 31 + bit_size: 1 fieldset/SECWM2R1: description: Flash secure watermak2 register fields: - - name: SECWM2_PSTRT - description: SECWM2_PSTRT - bit_offset: 0 - bit_size: 7 - - name: SECWM2_PEND - description: SECWM2_PEND - bit_offset: 16 - bit_size: 7 + - name: SECWM2_PSTRT + description: SECWM2_PSTRT + bit_offset: 0 + bit_size: 7 + - name: SECWM2_PEND + description: SECWM2_PEND + bit_offset: 16 + bit_size: 7 fieldset/SECWM2R2: description: Flash secure watermak2 register2 fields: - - name: PCROP2_PSTRT - description: PCROP2_PSTRT - bit_offset: 0 - bit_size: 7 - - name: PCROP2EN - description: PCROP2EN - bit_offset: 15 - bit_size: 1 - - name: HDP2_PEND - description: HDP2_PEND - bit_offset: 16 - bit_size: 7 - - name: HDP2EN - description: HDP2EN - bit_offset: 31 - bit_size: 1 + - name: PCROP2_PSTRT + description: PCROP2_PSTRT + bit_offset: 0 + bit_size: 7 + - name: PCROP2EN + description: PCROP2EN + bit_offset: 15 + bit_size: 1 + - name: HDP2_PEND + description: HDP2_PEND + bit_offset: 16 + bit_size: 7 + - name: HDP2EN + description: HDP2EN + bit_offset: 31 + bit_size: 1 fieldset/WRP1AR: description: Flash Bank 1 WRP area A address register fields: - - name: WRP1A_PSTRT - description: WRP1A_PSTRT - bit_offset: 0 - bit_size: 7 - - name: WRP1A_PEND - description: WRP1A_PEND - bit_offset: 16 - bit_size: 7 + - name: WRP1A_PSTRT + description: WRP1A_PSTRT + bit_offset: 0 + bit_size: 7 + - name: WRP1A_PEND + description: WRP1A_PEND + bit_offset: 16 + bit_size: 7 fieldset/WRP1BR: description: Flash Bank 1 WRP area B address register fields: - - name: WRP1B_PSTRT - description: WRP1B_PSTRT - bit_offset: 0 - bit_size: 7 - - name: WRP1B_PEND - description: WRP1B_PEND - bit_offset: 16 - bit_size: 7 + - name: WRP1B_PSTRT + description: WRP1B_PSTRT + bit_offset: 0 + bit_size: 7 + - name: WRP1B_PEND + description: WRP1B_PEND + bit_offset: 16 + bit_size: 7 fieldset/WRP2AR: description: Flash WPR2 area A address register fields: - - name: WRP2A_PSTRT - description: WRP2A_PSTRT - bit_offset: 0 - bit_size: 7 - - name: WRP2A_PEND - description: WRP2A_PEND - bit_offset: 16 - bit_size: 7 + - name: WRP2A_PSTRT + description: WRP2A_PSTRT + bit_offset: 0 + bit_size: 7 + - name: WRP2A_PEND + description: WRP2A_PEND + bit_offset: 16 + bit_size: 7 fieldset/WRP2BR: description: Flash WPR2 area B address register fields: - - name: WRP2B_PSTRT - description: WRP2B_PSTRT - bit_offset: 0 - bit_size: 7 - - name: WRP2B_PEND - description: WRP2B_PEND - bit_offset: 16 - bit_size: 7 + - name: WRP2B_PSTRT + description: WRP2B_PSTRT + bit_offset: 0 + bit_size: 7 + - name: WRP2B_PEND + description: WRP2B_PEND + bit_offset: 16 + bit_size: 7 diff --git a/data/registers/flash_u5.yaml b/data/registers/flash_u5.yaml index d31533f..8ad8908 100644 --- a/data/registers/flash_u5.yaml +++ b/data/registers/flash_u5.yaml @@ -1,3306 +1,3305 @@ ---- block/FLASH: description: Flash items: - - name: ACR - description: FLASH access control register - byte_offset: 0 - fieldset: ACR - - name: NSKEYR - description: FLASH non-secure key register - byte_offset: 8 - fieldset: NSKEYR - - name: SECKEYR - description: FLASH secure key register - byte_offset: 12 - fieldset: SECKEYR - - name: OPTKEYR - description: FLASH option key register - byte_offset: 16 - fieldset: OPTKEYR - - name: PDKEY1R - description: FLASH bank 1 power-down key register - byte_offset: 24 - fieldset: PDKEY1R - - name: PDKEY2R - description: FLASH bank 2 power-down key register - byte_offset: 28 - fieldset: PDKEY2R - - name: NSSR - description: FLASH non-secure status register - byte_offset: 32 - fieldset: NSSR - - name: SECSR - description: FLASH secure status register - byte_offset: 36 - fieldset: SECSR - - name: NSCR - description: FLASH non-secure control register - byte_offset: 40 - fieldset: NSCR - - name: SECCR - description: FLASH secure control register - byte_offset: 44 - fieldset: SECCR - - name: ECCR - description: FLASH ECC register - byte_offset: 48 - fieldset: ECCR - - name: OPSR - description: FLASH operation status register - byte_offset: 52 - fieldset: OPSR - - name: OPTR - description: FLASH option register - byte_offset: 64 - fieldset: OPTR - - name: NSBOOTADD0R - description: FLASH non-secure boot address 0 register - byte_offset: 68 - fieldset: NSBOOTADD0R - - name: NSBOOTADD1R - description: FLASH non-secure boot address 1 register - byte_offset: 72 - fieldset: NSBOOTADD1R - - name: SECBOOTADD0R - description: FLASH secure boot address 0 register - byte_offset: 76 - fieldset: SECBOOTADD0R - - name: SECWM1R1 - description: FLASH secure watermark1 register 1 - byte_offset: 80 - fieldset: SECWM1R1 - - name: SECWM1R2 - description: FLASH secure watermark1 register 2 - byte_offset: 84 - fieldset: SECWM1R2 - - name: WRP1AR - description: FLASH WRP1 area A address register - byte_offset: 88 - fieldset: WRP1AR - - name: WRP1BR - description: FLASH WRP1 area B address register - byte_offset: 92 - fieldset: WRP1BR - - name: SECWM2R1 - description: FLASH secure watermark2 register 1 - byte_offset: 96 - fieldset: SECWM2R1 - - name: SECWM2R2 - description: FLASH secure watermark2 register 2 - byte_offset: 100 - fieldset: SECWM2R2 - - name: WRP2AR - description: FLASH WPR2 area A address register - byte_offset: 104 - fieldset: WRP2AR - - name: WRP2BR - description: FLASH WPR2 area B address register - byte_offset: 108 - fieldset: WRP2BR - - name: OEM1KEYR1 - description: FLASH OEM1 key register 1 - byte_offset: 112 - fieldset: OEM1KEYR1 - - name: OEM1KEYR2 - description: FLASH OEM1 key register 2 - byte_offset: 116 - fieldset: OEM1KEYR2 - - name: OEM2KEYR1 - description: FLASH OEM2 key register 1 - byte_offset: 120 - fieldset: OEM2KEYR1 - - name: OEM2KEYR2 - description: FLASH OEM2 key register 2 - byte_offset: 124 - fieldset: OEM2KEYR2 - - name: SEC1BBR1 - description: FLASH secure block based bank 1 register 1 - byte_offset: 128 - fieldset: SEC1BBR1 - - name: SEC1BBR2 - description: FLASH secure block based bank 1 register 2 - byte_offset: 132 - fieldset: SEC1BBR2 - - name: SEC1BBR3 - description: FLASH secure block based bank 1 register 3 - byte_offset: 136 - fieldset: SEC1BBR3 - - name: SEC1BBR4 - description: FLASH secure block based bank 1 register 4 - byte_offset: 140 - fieldset: SEC1BBR4 - - name: SEC2BBR1 - description: FLASH secure block based bank 2 register 1 - byte_offset: 160 - fieldset: SEC2BBR1 - - name: SEC2BBR2 - description: FLASH secure block based bank 2 register 2 - byte_offset: 164 - fieldset: SEC2BBR2 - - name: SEC2BBR3 - description: FLASH secure block based bank 2 register 3 - byte_offset: 168 - fieldset: SEC2BBR3 - - name: SEC2BBR4 - description: FLASH secure block based bank 2 register 4 - byte_offset: 172 - fieldset: SEC2BBR4 - - name: SECHDPCR - description: FLASH secure HDP control register - byte_offset: 192 - fieldset: SECHDPCR - - name: PRIVCFGR - description: FLASH privilege configuration register - byte_offset: 196 - fieldset: PRIVCFGR - - name: PRIV1BBR1 - description: FLASH privilege block based bank 1 register 1 - byte_offset: 208 - fieldset: PRIV1BBR1 - - name: PRIV1BBR2 - description: FLASH privilege block based bank 1 register 2 - byte_offset: 212 - fieldset: PRIV1BBR2 - - name: PRIV1BBR3 - description: FLASH privilege block based bank 1 register 3 - byte_offset: 216 - fieldset: PRIV1BBR3 - - name: PRIV1BBR4 - description: FLASH privilege block based bank 1 register 4 - byte_offset: 220 - fieldset: PRIV1BBR4 - - name: PRIV2BBR1 - description: FLASH privilege block based bank 2 register 1 - byte_offset: 240 - fieldset: PRIV2BBR1 - - name: PRIV2BBR2 - description: FLASH privilege block based bank 2 register 2 - byte_offset: 244 - fieldset: PRIV2BBR2 - - name: PRIV2BBR3 - description: FLASH privilege block based bank 2 register 3 - byte_offset: 248 - fieldset: PRIV2BBR3 - - name: PRIV2BBR4 - description: FLASH privilege block based bank 2 register 4 - byte_offset: 252 - fieldset: PRIV2BBR4 + - name: ACR + description: FLASH access control register + byte_offset: 0 + fieldset: ACR + - name: NSKEYR + description: FLASH non-secure key register + byte_offset: 8 + fieldset: NSKEYR + - name: SECKEYR + description: FLASH secure key register + byte_offset: 12 + fieldset: SECKEYR + - name: OPTKEYR + description: FLASH option key register + byte_offset: 16 + fieldset: OPTKEYR + - name: PDKEY1R + description: FLASH bank 1 power-down key register + byte_offset: 24 + fieldset: PDKEY1R + - name: PDKEY2R + description: FLASH bank 2 power-down key register + byte_offset: 28 + fieldset: PDKEY2R + - name: NSSR + description: FLASH non-secure status register + byte_offset: 32 + fieldset: NSSR + - name: SECSR + description: FLASH secure status register + byte_offset: 36 + fieldset: SECSR + - name: NSCR + description: FLASH non-secure control register + byte_offset: 40 + fieldset: NSCR + - name: SECCR + description: FLASH secure control register + byte_offset: 44 + fieldset: SECCR + - name: ECCR + description: FLASH ECC register + byte_offset: 48 + fieldset: ECCR + - name: OPSR + description: FLASH operation status register + byte_offset: 52 + fieldset: OPSR + - name: OPTR + description: FLASH option register + byte_offset: 64 + fieldset: OPTR + - name: NSBOOTADD0R + description: FLASH non-secure boot address 0 register + byte_offset: 68 + fieldset: NSBOOTADD0R + - name: NSBOOTADD1R + description: FLASH non-secure boot address 1 register + byte_offset: 72 + fieldset: NSBOOTADD1R + - name: SECBOOTADD0R + description: FLASH secure boot address 0 register + byte_offset: 76 + fieldset: SECBOOTADD0R + - name: SECWM1R1 + description: FLASH secure watermark1 register 1 + byte_offset: 80 + fieldset: SECWM1R1 + - name: SECWM1R2 + description: FLASH secure watermark1 register 2 + byte_offset: 84 + fieldset: SECWM1R2 + - name: WRP1AR + description: FLASH WRP1 area A address register + byte_offset: 88 + fieldset: WRP1AR + - name: WRP1BR + description: FLASH WRP1 area B address register + byte_offset: 92 + fieldset: WRP1BR + - name: SECWM2R1 + description: FLASH secure watermark2 register 1 + byte_offset: 96 + fieldset: SECWM2R1 + - name: SECWM2R2 + description: FLASH secure watermark2 register 2 + byte_offset: 100 + fieldset: SECWM2R2 + - name: WRP2AR + description: FLASH WPR2 area A address register + byte_offset: 104 + fieldset: WRP2AR + - name: WRP2BR + description: FLASH WPR2 area B address register + byte_offset: 108 + fieldset: WRP2BR + - name: OEM1KEYR1 + description: FLASH OEM1 key register 1 + byte_offset: 112 + fieldset: OEM1KEYR1 + - name: OEM1KEYR2 + description: FLASH OEM1 key register 2 + byte_offset: 116 + fieldset: OEM1KEYR2 + - name: OEM2KEYR1 + description: FLASH OEM2 key register 1 + byte_offset: 120 + fieldset: OEM2KEYR1 + - name: OEM2KEYR2 + description: FLASH OEM2 key register 2 + byte_offset: 124 + fieldset: OEM2KEYR2 + - name: SEC1BBR1 + description: FLASH secure block based bank 1 register 1 + byte_offset: 128 + fieldset: SEC1BBR1 + - name: SEC1BBR2 + description: FLASH secure block based bank 1 register 2 + byte_offset: 132 + fieldset: SEC1BBR2 + - name: SEC1BBR3 + description: FLASH secure block based bank 1 register 3 + byte_offset: 136 + fieldset: SEC1BBR3 + - name: SEC1BBR4 + description: FLASH secure block based bank 1 register 4 + byte_offset: 140 + fieldset: SEC1BBR4 + - name: SEC2BBR1 + description: FLASH secure block based bank 2 register 1 + byte_offset: 160 + fieldset: SEC2BBR1 + - name: SEC2BBR2 + description: FLASH secure block based bank 2 register 2 + byte_offset: 164 + fieldset: SEC2BBR2 + - name: SEC2BBR3 + description: FLASH secure block based bank 2 register 3 + byte_offset: 168 + fieldset: SEC2BBR3 + - name: SEC2BBR4 + description: FLASH secure block based bank 2 register 4 + byte_offset: 172 + fieldset: SEC2BBR4 + - name: SECHDPCR + description: FLASH secure HDP control register + byte_offset: 192 + fieldset: SECHDPCR + - name: PRIVCFGR + description: FLASH privilege configuration register + byte_offset: 196 + fieldset: PRIVCFGR + - name: PRIV1BBR1 + description: FLASH privilege block based bank 1 register 1 + byte_offset: 208 + fieldset: PRIV1BBR1 + - name: PRIV1BBR2 + description: FLASH privilege block based bank 1 register 2 + byte_offset: 212 + fieldset: PRIV1BBR2 + - name: PRIV1BBR3 + description: FLASH privilege block based bank 1 register 3 + byte_offset: 216 + fieldset: PRIV1BBR3 + - name: PRIV1BBR4 + description: FLASH privilege block based bank 1 register 4 + byte_offset: 220 + fieldset: PRIV1BBR4 + - name: PRIV2BBR1 + description: FLASH privilege block based bank 2 register 1 + byte_offset: 240 + fieldset: PRIV2BBR1 + - name: PRIV2BBR2 + description: FLASH privilege block based bank 2 register 2 + byte_offset: 244 + fieldset: PRIV2BBR2 + - name: PRIV2BBR3 + description: FLASH privilege block based bank 2 register 3 + byte_offset: 248 + fieldset: PRIV2BBR3 + - name: PRIV2BBR4 + description: FLASH privilege block based bank 2 register 4 + byte_offset: 252 + fieldset: PRIV2BBR4 fieldset/ACR: description: FLASH access control register fields: - - name: LATENCY - description: "Latency\r These bits represent the ratio between the HCLK (AHB clock) period and the Flash memory access time.\r ..." - bit_offset: 0 - bit_size: 4 - - name: PRFTEN - description: "Prefetch enable\r This bit enables the prefetch buffer in the embedded Flash memory." - bit_offset: 8 - bit_size: 1 - - name: LPM - description: "Low-power read mode\r This bit puts the Flash memory in low-power read mode." - bit_offset: 11 - bit_size: 1 - enum: LPM - - name: PDREQ1 - description: "Bank 1 power-down mode request\r This bit is write-protected with FLASH_PDKEY1R. This bit requests bank 1 to enter power-down mode. When bank 1 enters power-down mode, this bit is cleared by hardware and the PDKEY1R is locked." - bit_offset: 12 - bit_size: 1 - enum: PDREQ - - name: PDREQ2 - description: "Bank 2 power-down mode request\r This bit is write-protected with FLASH_PDKEY2R. This bit requests bank 2 to enter power-down mode. When bank 2 enters power-down mode, this bit is cleared by hardware and the PDKEY2R is locked." - bit_offset: 13 - bit_size: 1 - enum: PDREQ - - name: SLEEP_PD - description: "Flash memory power-down mode during Sleep mode\r This bit determines whether the Flash memory is in power-down mode or Idle mode when the device is in Sleep mode.\r The Flash must not be put in power-down while a program or an erase operation is on-going." - bit_offset: 14 - bit_size: 1 - enum: SLEEP_PD + - name: LATENCY + description: "Latency\r These bits represent the ratio between the HCLK (AHB clock) period and the Flash memory access time.\r ..." + bit_offset: 0 + bit_size: 4 + - name: PRFTEN + description: "Prefetch enable\r This bit enables the prefetch buffer in the embedded Flash memory." + bit_offset: 8 + bit_size: 1 + - name: LPM + description: "Low-power read mode\r This bit puts the Flash memory in low-power read mode." + bit_offset: 11 + bit_size: 1 + enum: LPM + - name: PDREQ1 + description: "Bank 1 power-down mode request\r This bit is write-protected with FLASH_PDKEY1R. This bit requests bank 1 to enter power-down mode. When bank 1 enters power-down mode, this bit is cleared by hardware and the PDKEY1R is locked." + bit_offset: 12 + bit_size: 1 + enum: PDREQ + - name: PDREQ2 + description: "Bank 2 power-down mode request\r This bit is write-protected with FLASH_PDKEY2R. This bit requests bank 2 to enter power-down mode. When bank 2 enters power-down mode, this bit is cleared by hardware and the PDKEY2R is locked." + bit_offset: 13 + bit_size: 1 + enum: PDREQ + - name: SLEEP_PD + description: "Flash memory power-down mode during Sleep mode\r This bit determines whether the Flash memory is in power-down mode or Idle mode when the device is in Sleep mode.\r The Flash must not be put in power-down while a program or an erase operation is on-going." + bit_offset: 14 + bit_size: 1 + enum: SLEEP_PD fieldset/ECCR: description: FLASH ECC register fields: - - name: ADDR_ECC - description: ECC fail address - bit_offset: 0 - bit_size: 20 - - name: BK_ECC - description: ECC fail bank - bit_offset: 21 - bit_size: 1 - enum: BK_ECC - - name: SYSF_ECC - description: "System Flash memory ECC fail\r This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory." - bit_offset: 22 - bit_size: 1 - - name: ECCIE - description: "ECC correction interrupt enable\r This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR register is set." - bit_offset: 24 - bit_size: 1 - enum: ECCIE - - name: ECCC - description: "ECC correction\r This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1." - bit_offset: 30 - bit_size: 1 - - name: ECCD - description: "ECC detection\r This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1." - bit_offset: 31 - bit_size: 1 + - name: ADDR_ECC + description: ECC fail address + bit_offset: 0 + bit_size: 20 + - name: BK_ECC + description: ECC fail bank + bit_offset: 21 + bit_size: 1 + enum: BK_ECC + - name: SYSF_ECC + description: "System Flash memory ECC fail\r This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory." + bit_offset: 22 + bit_size: 1 + - name: ECCIE + description: "ECC correction interrupt enable\r This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR register is set." + bit_offset: 24 + bit_size: 1 + enum: ECCIE + - name: ECCC + description: "ECC correction\r This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1." + bit_offset: 30 + bit_size: 1 + - name: ECCD + description: "ECC detection\r This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1." + bit_offset: 31 + bit_size: 1 fieldset/NSBOOTADD0R: description: FLASH non-secure boot address 0 register fields: - - name: NSBOOTADD0 - description: "Non-secure boot base address 0\r The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state.\r Examples:\r NSBOOTADD0[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000)\r NSBOOTADD0[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000)\r NSBOOTADD0[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000)" - bit_offset: 7 - bit_size: 25 + - name: NSBOOTADD0 + description: "Non-secure boot base address 0\r The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state.\r Examples:\r NSBOOTADD0[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000)\r NSBOOTADD0[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000)\r NSBOOTADD0[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000)" + bit_offset: 7 + bit_size: 25 fieldset/NSBOOTADD1R: description: FLASH non-secure boot address 1 register fields: - - name: NSBOOTADD1 - description: "Non-secure boot address 1\r The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state.\r Examples:\r NSBOOTADD1[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000)\r NSBOOTADD1[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000)\r NSBOOTADD1[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000)" - bit_offset: 7 - bit_size: 25 + - name: NSBOOTADD1 + description: "Non-secure boot address 1\r The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state.\r Examples:\r NSBOOTADD1[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000)\r NSBOOTADD1[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000)\r NSBOOTADD1[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000)" + bit_offset: 7 + bit_size: 25 fieldset/NSCR: description: FLASH non-secure control register fields: - - name: PG - description: Non-secure programming - bit_offset: 0 - bit_size: 1 - enum: NSCR_PG - - name: PER - description: Non-secure page erase - bit_offset: 1 - bit_size: 1 - enum: NSCR_PER - - name: MER1 - description: "Non-secure bank 1 mass erase\r This bit triggers the bank 1 non-secure mass erase (all bank 1 user pages) when set." - bit_offset: 2 - bit_size: 1 - - name: PNB - description: "Non-secure page number selection\r These bits select the page to erase.\r ..." - bit_offset: 3 - bit_size: 7 - - name: BKER - description: Non-secure bank selection for page erase - bit_offset: 11 - bit_size: 1 - enum: NSCR_BKER - - name: BWR - description: "Non-secure burst write programming mode\r When set, this bit selects the burst write programming mode." - bit_offset: 14 - bit_size: 1 - - name: MER2 - description: "Non-secure bank 2 mass erase\r This bit triggers the bank 2 non-secure mass erase (all bank 2 user pages) when set." - bit_offset: 15 - bit_size: 1 - - name: STRT - description: "Non-secure start\r This bit triggers a non-secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR bit in FLASH_NSSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_NSSR." - bit_offset: 16 - bit_size: 1 - - name: OPTSTRT - description: "Options modification start\r This bit triggers an options operation when set. It can not be written if OPTLOCK bit is set. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_NSSR." - bit_offset: 17 - bit_size: 1 - - name: EOPIE - description: "Non-secure end of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in the FLASH_NSSR is set to 1." - bit_offset: 24 - bit_size: 1 - enum: NSCR_EOPIE - - name: ERRIE - description: "Non-secure error interrupt enable\r This bit enables the interrupt generation when the OPERR bit in the FLASH_NSSR is set to 1." - bit_offset: 25 - bit_size: 1 - enum: NSCR_ERRIE - - name: OBL_LAUNCH - description: "Force the option byte loading\r When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. It cannot be written if OPTLOCK is set." - bit_offset: 27 - bit_size: 1 - enum: OBL_LAUNCH - - name: OPTLOCK - description: "Option lock\r This bit is set only. When set, all bits concerning user options in FLASH_NSCR register are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit in the FLASH_NSCR must be cleared before doing the unlock sequence for OPTLOCK bit.\r In case of an unsuccessful unlock operation, this bit remains set until the next reset." - bit_offset: 30 - bit_size: 1 - - name: LOCK - description: "Non-secure lock\r This bit is set only. When set, the FLASH_NSCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_NSKEYR register.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset." - bit_offset: 31 - bit_size: 1 + - name: PG + description: Non-secure programming + bit_offset: 0 + bit_size: 1 + enum: NSCR_PG + - name: PER + description: Non-secure page erase + bit_offset: 1 + bit_size: 1 + enum: NSCR_PER + - name: MER1 + description: "Non-secure bank 1 mass erase\r This bit triggers the bank 1 non-secure mass erase (all bank 1 user pages) when set." + bit_offset: 2 + bit_size: 1 + - name: PNB + description: "Non-secure page number selection\r These bits select the page to erase.\r ..." + bit_offset: 3 + bit_size: 7 + - name: BKER + description: Non-secure bank selection for page erase + bit_offset: 11 + bit_size: 1 + enum: NSCR_BKER + - name: BWR + description: "Non-secure burst write programming mode\r When set, this bit selects the burst write programming mode." + bit_offset: 14 + bit_size: 1 + - name: MER2 + description: "Non-secure bank 2 mass erase\r This bit triggers the bank 2 non-secure mass erase (all bank 2 user pages) when set." + bit_offset: 15 + bit_size: 1 + - name: STRT + description: "Non-secure start\r This bit triggers a non-secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR bit in FLASH_NSSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_NSSR." + bit_offset: 16 + bit_size: 1 + - name: OPTSTRT + description: "Options modification start\r This bit triggers an options operation when set. It can not be written if OPTLOCK bit is set. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_NSSR." + bit_offset: 17 + bit_size: 1 + - name: EOPIE + description: "Non-secure end of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in the FLASH_NSSR is set to 1." + bit_offset: 24 + bit_size: 1 + enum: NSCR_EOPIE + - name: ERRIE + description: "Non-secure error interrupt enable\r This bit enables the interrupt generation when the OPERR bit in the FLASH_NSSR is set to 1." + bit_offset: 25 + bit_size: 1 + enum: NSCR_ERRIE + - name: OBL_LAUNCH + description: "Force the option byte loading\r When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. It cannot be written if OPTLOCK is set." + bit_offset: 27 + bit_size: 1 + enum: OBL_LAUNCH + - name: OPTLOCK + description: "Option lock\r This bit is set only. When set, all bits concerning user options in FLASH_NSCR register are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit in the FLASH_NSCR must be cleared before doing the unlock sequence for OPTLOCK bit.\r In case of an unsuccessful unlock operation, this bit remains set until the next reset." + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: "Non-secure lock\r This bit is set only. When set, the FLASH_NSCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_NSKEYR register.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset." + bit_offset: 31 + bit_size: 1 fieldset/NSKEYR: description: FLASH non-secure key register fields: - - name: NSKEY - description: Flash memory non-secure key - bit_offset: 0 - bit_size: 32 + - name: NSKEY + description: Flash memory non-secure key + bit_offset: 0 + bit_size: 32 fieldset/NSSR: description: FLASH non-secure status register fields: - - name: EOP - description: Non-secure end of operation - bit_offset: 0 - bit_size: 1 - - name: OPERR - description: Non-secure operation error - bit_offset: 1 - bit_size: 1 - - name: PROGERR - description: "Non-secure programming error\r This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1." - bit_offset: 3 - bit_size: 1 - - name: WRPERR - description: "Non-secure write protection error\r This bit is set by hardware when an non-secure address to be erased/programmed belongs to a write-protected part (by WRP, HDP or RDP level 1) of the Flash memory. This bit is cleared by writing 1.\r Refer to for full conditions of error flag setting." - bit_offset: 4 - bit_size: 1 - - name: PGAERR - description: "Non-secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1." - bit_offset: 5 - bit_size: 1 - - name: SIZERR - description: "Non-secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1." - bit_offset: 6 - bit_size: 1 - - name: PGSERR - description: "Non-secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to for full conditions of error flag setting." - bit_offset: 7 - bit_size: 1 - - name: OPTWERR - description: "Option write error\r This bit is set by hardware when the options bytes are written with an invalid configuration. It is cleared by writing 1.\r Refer to for full conditions of error flag setting." - bit_offset: 13 - bit_size: 1 - - name: BSY - description: "Non-secure busy\r This indicates that a Flash memory secure or non-secure operation is in progress. This bit is set at the beginning of a Flash operation and reset when the operation finishes or when an error occurs." - bit_offset: 16 - bit_size: 1 - - name: WDW - description: "Non-secure wait data to write\r This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory." - bit_offset: 17 - bit_size: 1 - - name: OEM1LOCK - description: "OEM1 lock\r This bit indicates that the OEM1 RDP key read during the OBL is not virgin. When set, the OEM1 RDP lock mechanism is active." - bit_offset: 18 - bit_size: 1 - - name: OEM2LOCK - description: "OEM2 lock\r This bit indicates that the OEM2 RDP key read during the OBL is not virgin. When set, the OEM2 RDP lock mechanism is active." - bit_offset: 19 - bit_size: 1 - - name: PD1 - description: "Bank 1 in power-down mode\r This bit indicates that the Flash memory bank 1 is in power-down state. It is reset when bank 1 is in normal mode or being awaken." - bit_offset: 20 - bit_size: 1 - - name: PD2 - description: "Bank 2 in power-down mode\r This bit indicates that the Flash memory bank 2 is in power-down state. It is reset when bank 2 is in normal mode or being awaken." - bit_offset: 21 - bit_size: 1 + - name: EOP + description: Non-secure end of operation + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: Non-secure operation error + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: "Non-secure programming error\r This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1." + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: "Non-secure write protection error\r This bit is set by hardware when an non-secure address to be erased/programmed belongs to a write-protected part (by WRP, HDP or RDP level 1) of the Flash memory. This bit is cleared by writing 1.\r Refer to for full conditions of error flag setting." + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: "Non-secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1." + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: "Non-secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1." + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: "Non-secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to for full conditions of error flag setting." + bit_offset: 7 + bit_size: 1 + - name: OPTWERR + description: "Option write error\r This bit is set by hardware when the options bytes are written with an invalid configuration. It is cleared by writing 1.\r Refer to for full conditions of error flag setting." + bit_offset: 13 + bit_size: 1 + - name: BSY + description: "Non-secure busy\r This indicates that a Flash memory secure or non-secure operation is in progress. This bit is set at the beginning of a Flash operation and reset when the operation finishes or when an error occurs." + bit_offset: 16 + bit_size: 1 + - name: WDW + description: "Non-secure wait data to write\r This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory." + bit_offset: 17 + bit_size: 1 + - name: OEM1LOCK + description: "OEM1 lock\r This bit indicates that the OEM1 RDP key read during the OBL is not virgin. When set, the OEM1 RDP lock mechanism is active." + bit_offset: 18 + bit_size: 1 + - name: OEM2LOCK + description: "OEM2 lock\r This bit indicates that the OEM2 RDP key read during the OBL is not virgin. When set, the OEM2 RDP lock mechanism is active." + bit_offset: 19 + bit_size: 1 + - name: PD1 + description: "Bank 1 in power-down mode\r This bit indicates that the Flash memory bank 1 is in power-down state. It is reset when bank 1 is in normal mode or being awaken." + bit_offset: 20 + bit_size: 1 + - name: PD2 + description: "Bank 2 in power-down mode\r This bit indicates that the Flash memory bank 2 is in power-down state. It is reset when bank 2 is in normal mode or being awaken." + bit_offset: 21 + bit_size: 1 fieldset/OEM1KEYR1: description: FLASH OEM1 key register 1 fields: - - name: OEM1KEY - description: OEM1 least significant bytes key - bit_offset: 0 - bit_size: 32 + - name: OEM1KEY + description: OEM1 least significant bytes key + bit_offset: 0 + bit_size: 32 fieldset/OEM1KEYR2: description: FLASH OEM1 key register 2 fields: - - name: OEM1KEY - description: OEM1 most significant bytes key - bit_offset: 0 - bit_size: 32 + - name: OEM1KEY + description: OEM1 most significant bytes key + bit_offset: 0 + bit_size: 32 fieldset/OEM2KEYR1: description: FLASH OEM2 key register 1 fields: - - name: OEM2KEY - description: OEM2 least significant bytes key - bit_offset: 0 - bit_size: 32 + - name: OEM2KEY + description: OEM2 least significant bytes key + bit_offset: 0 + bit_size: 32 fieldset/OEM2KEYR2: description: FLASH OEM2 key register 2 fields: - - name: OEM2KEY - description: OEM2 most significant bytes key - bit_offset: 0 - bit_size: 32 + - name: OEM2KEY + description: OEM2 most significant bytes key + bit_offset: 0 + bit_size: 32 fieldset/OPSR: description: FLASH operation status register fields: - - name: ADDR_OP - description: "Interrupted operation address\r This field indicates which address in the Flash memory was accessed when reset occurred. The address is given by bank from address 0x0 0000 to 0xF FFF0." - bit_offset: 0 - bit_size: 20 - - name: BK_OP - description: "Interrupted operation bank\r This bit indicates which Flash memory bank was accessed when reset occurred" - bit_offset: 21 - bit_size: 1 - enum: BK_OP - - name: SYSF_OP - description: "Operation in system Flash memory interrupted\r This bit indicates that the reset occurred during an operation in the system Flash memory." - bit_offset: 22 - bit_size: 1 - - name: CODE_OP - description: "Flash memory operation code\r This field indicates which Flash memory operation has been interrupted by a system reset:" - bit_offset: 29 - bit_size: 3 - enum: CODE_OP + - name: ADDR_OP + description: "Interrupted operation address\r This field indicates which address in the Flash memory was accessed when reset occurred. The address is given by bank from address 0x0 0000 to 0xF FFF0." + bit_offset: 0 + bit_size: 20 + - name: BK_OP + description: "Interrupted operation bank\r This bit indicates which Flash memory bank was accessed when reset occurred" + bit_offset: 21 + bit_size: 1 + enum: BK_OP + - name: SYSF_OP + description: "Operation in system Flash memory interrupted\r This bit indicates that the reset occurred during an operation in the system Flash memory." + bit_offset: 22 + bit_size: 1 + - name: CODE_OP + description: "Flash memory operation code\r This field indicates which Flash memory operation has been interrupted by a system reset:" + bit_offset: 29 + bit_size: 3 + enum: CODE_OP fieldset/OPTKEYR: description: FLASH option key register fields: - - name: OPTKEY - description: Option byte key - bit_offset: 0 - bit_size: 32 + - name: OPTKEY + description: Option byte key + bit_offset: 0 + bit_size: 32 fieldset/OPTR: description: FLASH option register fields: - - name: RDP - description: "Readout protection level\r Others: Level 1 (memories readout protection active)\r Note: Refer to for more details." - bit_offset: 0 - bit_size: 8 - enum: RDP - - name: BOR_LEV - description: "BOR reset level\r These bits contain the VDD supply level threshold that activates/releases the reset." - bit_offset: 8 - bit_size: 3 - enum: BOR_LEV - - name: nRST_STOP - description: Reset generation in Stop mode - bit_offset: 12 - bit_size: 1 - enum: nRST_STOP - - name: nRST_STDBY - description: Reset generation in Standby mode - bit_offset: 13 - bit_size: 1 - enum: nRST_STDBY - - name: nRST_SHDW - description: Reset generation in Shutdown mode - bit_offset: 14 - bit_size: 1 - enum: nRST_SHDW - - name: SRAM1345_RST - description: "SRAM1, SRAM3 and SRAM4 erase upon system reset" - bit_offset: 15 - bit_size: 1 - - name: IWDG_SW - description: Independent watchdog selection - bit_offset: 16 - bit_size: 1 - enum: IWDG_SW - - name: IWDG_STOP - description: Independent watchdog counter freeze in Stop mode - bit_offset: 17 - bit_size: 1 - enum: IWDG_STOP - - name: IWDG_STDBY - description: Independent watchdog counter freeze in Standby mode - bit_offset: 18 - bit_size: 1 - enum: IWDG_STDBY - - name: WWDG_SW - description: Window watchdog selection - bit_offset: 19 - bit_size: 1 - enum: WWDG_SW - - name: SWAP_BANK - description: Swap banks - bit_offset: 20 - bit_size: 1 - enum: SWAP_BANK - - name: DUALBANK - description: Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices - bit_offset: 21 - bit_size: 1 - enum: DUALBANK - - name: BKPSRAM_ECC - description: Backup RAM ECC detection and correction enable - bit_offset: 22 - bit_size: 1 - enum: BKPSRAM_ECC - - name: SRAM3_ECC - description: SRAM3 ECC detection and correction enable - bit_offset: 23 - bit_size: 1 - enum: SRAM_ECC - - name: SRAM2_ECC - description: SRAM2 ECC detection and correction enable - bit_offset: 24 - bit_size: 1 - enum: SRAM_ECC - - name: SRAM2_RST - description: SRAM2 erase when system reset - bit_offset: 25 - bit_size: 1 - - name: nSWBOOT0 - description: Software BOOT0 - bit_offset: 26 - bit_size: 1 - enum: nSWBOOT - - name: nBOOT0 - description: nBOOT0 option bit - bit_offset: 27 - bit_size: 1 - enum: nBOOT - - name: PA15_PUPEN - description: PA15 pull-up enable - bit_offset: 28 - bit_size: 1 - - name: IO_VDD_HSLV - description: "High-speed IO at low VDD voltage configuration bit\r This bit can be set only with VDD below 2.5V" - bit_offset: 29 - bit_size: 1 - enum: IO_VDD_HSLV - - name: IO_VDDIO2_HSLV - description: "High-speed IO at low VDDIO2 voltage configuration bit\r This bit can be set only with VDDIO2 below 2.5 V." - bit_offset: 30 - bit_size: 1 - enum: IO_VDDIO_HSLV - - name: TZEN - description: Global TrustZone security enable - bit_offset: 31 - bit_size: 1 + - name: RDP + description: "Readout protection level\r Others: Level 1 (memories readout protection active)\r Note: Refer to for more details." + bit_offset: 0 + bit_size: 8 + enum: RDP + - name: BOR_LEV + description: "BOR reset level\r These bits contain the VDD supply level threshold that activates/releases the reset." + bit_offset: 8 + bit_size: 3 + enum: BOR_LEV + - name: nRST_STOP + description: Reset generation in Stop mode + bit_offset: 12 + bit_size: 1 + enum: nRST_STOP + - name: nRST_STDBY + description: Reset generation in Standby mode + bit_offset: 13 + bit_size: 1 + enum: nRST_STDBY + - name: nRST_SHDW + description: Reset generation in Shutdown mode + bit_offset: 14 + bit_size: 1 + enum: nRST_SHDW + - name: SRAM1345_RST + description: SRAM1, SRAM3 and SRAM4 erase upon system reset + bit_offset: 15 + bit_size: 1 + - name: IWDG_SW + description: Independent watchdog selection + bit_offset: 16 + bit_size: 1 + enum: IWDG_SW + - name: IWDG_STOP + description: Independent watchdog counter freeze in Stop mode + bit_offset: 17 + bit_size: 1 + enum: IWDG_STOP + - name: IWDG_STDBY + description: Independent watchdog counter freeze in Standby mode + bit_offset: 18 + bit_size: 1 + enum: IWDG_STDBY + - name: WWDG_SW + description: Window watchdog selection + bit_offset: 19 + bit_size: 1 + enum: WWDG_SW + - name: SWAP_BANK + description: Swap banks + bit_offset: 20 + bit_size: 1 + enum: SWAP_BANK + - name: DUALBANK + description: Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices + bit_offset: 21 + bit_size: 1 + enum: DUALBANK + - name: BKPSRAM_ECC + description: Backup RAM ECC detection and correction enable + bit_offset: 22 + bit_size: 1 + enum: BKPSRAM_ECC + - name: SRAM3_ECC + description: SRAM3 ECC detection and correction enable + bit_offset: 23 + bit_size: 1 + enum: SRAM_ECC + - name: SRAM2_ECC + description: SRAM2 ECC detection and correction enable + bit_offset: 24 + bit_size: 1 + enum: SRAM_ECC + - name: SRAM2_RST + description: SRAM2 erase when system reset + bit_offset: 25 + bit_size: 1 + - name: nSWBOOT0 + description: Software BOOT0 + bit_offset: 26 + bit_size: 1 + enum: nSWBOOT + - name: nBOOT0 + description: nBOOT0 option bit + bit_offset: 27 + bit_size: 1 + enum: nBOOT + - name: PA15_PUPEN + description: PA15 pull-up enable + bit_offset: 28 + bit_size: 1 + - name: IO_VDD_HSLV + description: "High-speed IO at low VDD voltage configuration bit\r This bit can be set only with VDD below 2.5V" + bit_offset: 29 + bit_size: 1 + enum: IO_VDD_HSLV + - name: IO_VDDIO2_HSLV + description: "High-speed IO at low VDDIO2 voltage configuration bit\r This bit can be set only with VDDIO2 below 2.5 V." + bit_offset: 30 + bit_size: 1 + enum: IO_VDDIO_HSLV + - name: TZEN + description: Global TrustZone security enable + bit_offset: 31 + bit_size: 1 fieldset/PDKEY1R: description: FLASH bank 1 power-down key register fields: - - name: PDKEY1 - description: Bank 1 power-down key - bit_offset: 0 - bit_size: 32 + - name: PDKEY1 + description: Bank 1 power-down key + bit_offset: 0 + bit_size: 32 fieldset/PDKEY2R: description: FLASH bank 2 power-down key register fields: - - name: PDKEY2 - description: Bank 2 power-down key - bit_offset: 0 - bit_size: 32 + - name: PDKEY2 + description: Bank 2 power-down key + bit_offset: 0 + bit_size: 32 fieldset/PRIV1BBR1: description: FLASH privilege block based bank 1 register 1 fields: - - name: PRIV1BB0 - description: page privileged/unprivileged attribution - bit_offset: 0 - bit_size: 1 - - name: PRIV1BB1 - description: page privileged/unprivileged attribution - bit_offset: 1 - bit_size: 1 - - name: PRIV1BB2 - description: page privileged/unprivileged attribution - bit_offset: 2 - bit_size: 1 - - name: PRIV1BB3 - description: page privileged/unprivileged attribution - bit_offset: 3 - bit_size: 1 - - name: PRIV1BB4 - description: page privileged/unprivileged attribution - bit_offset: 4 - bit_size: 1 - - name: PRIV1BB5 - description: page privileged/unprivileged attribution - bit_offset: 5 - bit_size: 1 - - name: PRIV1BB6 - description: page privileged/unprivileged attribution - bit_offset: 6 - bit_size: 1 - - name: PRIV1BB7 - description: page privileged/unprivileged attribution - bit_offset: 7 - bit_size: 1 - - name: PRIV1BB8 - description: page privileged/unprivileged attribution - bit_offset: 8 - bit_size: 1 - - name: PRIV1BB9 - description: page privileged/unprivileged attribution - bit_offset: 9 - bit_size: 1 - - name: PRIV1BB10 - description: page privileged/unprivileged attribution - bit_offset: 10 - bit_size: 1 - - name: PRIV1BB11 - description: page privileged/unprivileged attribution - bit_offset: 11 - bit_size: 1 - - name: PRIV1BB12 - description: page privileged/unprivileged attribution - bit_offset: 12 - bit_size: 1 - - name: PRIV1BB13 - description: page privileged/unprivileged attribution - bit_offset: 13 - bit_size: 1 - - name: PRIV1BB14 - description: page privileged/unprivileged attribution - bit_offset: 14 - bit_size: 1 - - name: PRIV1BB15 - description: page privileged/unprivileged attribution - bit_offset: 15 - bit_size: 1 - - name: PRIV1BB16 - description: page privileged/unprivileged attribution - bit_offset: 16 - bit_size: 1 - - name: PRIV1BB17 - description: page privileged/unprivileged attribution - bit_offset: 17 - bit_size: 1 - - name: PRIV1BB18 - description: page privileged/unprivileged attribution - bit_offset: 18 - bit_size: 1 - - name: PRIV1BB19 - description: page privileged/unprivileged attribution - bit_offset: 19 - bit_size: 1 - - name: PRIV1BB20 - description: page privileged/unprivileged attribution - bit_offset: 20 - bit_size: 1 - - name: PRIV1BB21 - description: page privileged/unprivileged attribution - bit_offset: 21 - bit_size: 1 - - name: PRIV1BB22 - description: page privileged/unprivileged attribution - bit_offset: 22 - bit_size: 1 - - name: PRIV1BB23 - description: page privileged/unprivileged attribution - bit_offset: 23 - bit_size: 1 - - name: PRIV1BB24 - description: page privileged/unprivileged attribution - bit_offset: 24 - bit_size: 1 - - name: PRIV1BB25 - description: page privileged/unprivileged attribution - bit_offset: 25 - bit_size: 1 - - name: PRIV1BB26 - description: page privileged/unprivileged attribution - bit_offset: 26 - bit_size: 1 - - name: PRIV1BB27 - description: page privileged/unprivileged attribution - bit_offset: 27 - bit_size: 1 - - name: PRIV1BB28 - description: page privileged/unprivileged attribution - bit_offset: 28 - bit_size: 1 - - name: PRIV1BB29 - description: page privileged/unprivileged attribution - bit_offset: 29 - bit_size: 1 - - name: PRIV1BB30 - description: page privileged/unprivileged attribution - bit_offset: 30 - bit_size: 1 - - name: PRIV1BB31 - description: page privileged/unprivileged attribution - bit_offset: 31 - bit_size: 1 + - name: PRIV1BB0 + description: page privileged/unprivileged attribution + bit_offset: 0 + bit_size: 1 + - name: PRIV1BB1 + description: page privileged/unprivileged attribution + bit_offset: 1 + bit_size: 1 + - name: PRIV1BB2 + description: page privileged/unprivileged attribution + bit_offset: 2 + bit_size: 1 + - name: PRIV1BB3 + description: page privileged/unprivileged attribution + bit_offset: 3 + bit_size: 1 + - name: PRIV1BB4 + description: page privileged/unprivileged attribution + bit_offset: 4 + bit_size: 1 + - name: PRIV1BB5 + description: page privileged/unprivileged attribution + bit_offset: 5 + bit_size: 1 + - name: PRIV1BB6 + description: page privileged/unprivileged attribution + bit_offset: 6 + bit_size: 1 + - name: PRIV1BB7 + description: page privileged/unprivileged attribution + bit_offset: 7 + bit_size: 1 + - name: PRIV1BB8 + description: page privileged/unprivileged attribution + bit_offset: 8 + bit_size: 1 + - name: PRIV1BB9 + description: page privileged/unprivileged attribution + bit_offset: 9 + bit_size: 1 + - name: PRIV1BB10 + description: page privileged/unprivileged attribution + bit_offset: 10 + bit_size: 1 + - name: PRIV1BB11 + description: page privileged/unprivileged attribution + bit_offset: 11 + bit_size: 1 + - name: PRIV1BB12 + description: page privileged/unprivileged attribution + bit_offset: 12 + bit_size: 1 + - name: PRIV1BB13 + description: page privileged/unprivileged attribution + bit_offset: 13 + bit_size: 1 + - name: PRIV1BB14 + description: page privileged/unprivileged attribution + bit_offset: 14 + bit_size: 1 + - name: PRIV1BB15 + description: page privileged/unprivileged attribution + bit_offset: 15 + bit_size: 1 + - name: PRIV1BB16 + description: page privileged/unprivileged attribution + bit_offset: 16 + bit_size: 1 + - name: PRIV1BB17 + description: page privileged/unprivileged attribution + bit_offset: 17 + bit_size: 1 + - name: PRIV1BB18 + description: page privileged/unprivileged attribution + bit_offset: 18 + bit_size: 1 + - name: PRIV1BB19 + description: page privileged/unprivileged attribution + bit_offset: 19 + bit_size: 1 + - name: PRIV1BB20 + description: page privileged/unprivileged attribution + bit_offset: 20 + bit_size: 1 + - name: PRIV1BB21 + description: page privileged/unprivileged attribution + bit_offset: 21 + bit_size: 1 + - name: PRIV1BB22 + description: page privileged/unprivileged attribution + bit_offset: 22 + bit_size: 1 + - name: PRIV1BB23 + description: page privileged/unprivileged attribution + bit_offset: 23 + bit_size: 1 + - name: PRIV1BB24 + description: page privileged/unprivileged attribution + bit_offset: 24 + bit_size: 1 + - name: PRIV1BB25 + description: page privileged/unprivileged attribution + bit_offset: 25 + bit_size: 1 + - name: PRIV1BB26 + description: page privileged/unprivileged attribution + bit_offset: 26 + bit_size: 1 + - name: PRIV1BB27 + description: page privileged/unprivileged attribution + bit_offset: 27 + bit_size: 1 + - name: PRIV1BB28 + description: page privileged/unprivileged attribution + bit_offset: 28 + bit_size: 1 + - name: PRIV1BB29 + description: page privileged/unprivileged attribution + bit_offset: 29 + bit_size: 1 + - name: PRIV1BB30 + description: page privileged/unprivileged attribution + bit_offset: 30 + bit_size: 1 + - name: PRIV1BB31 + description: page privileged/unprivileged attribution + bit_offset: 31 + bit_size: 1 fieldset/PRIV1BBR2: description: FLASH privilege block based bank 1 register 2 fields: - - name: PRIV1BB0 - description: page privileged/unprivileged attribution - bit_offset: 0 - bit_size: 1 - - name: PRIV1BB1 - description: page privileged/unprivileged attribution - bit_offset: 1 - bit_size: 1 - - name: PRIV1BB2 - description: page privileged/unprivileged attribution - bit_offset: 2 - bit_size: 1 - - name: PRIV1BB3 - description: page privileged/unprivileged attribution - bit_offset: 3 - bit_size: 1 - - name: PRIV1BB4 - description: page privileged/unprivileged attribution - bit_offset: 4 - bit_size: 1 - - name: PRIV1BB5 - description: page privileged/unprivileged attribution - bit_offset: 5 - bit_size: 1 - - name: PRIV1BB6 - description: page privileged/unprivileged attribution - bit_offset: 6 - bit_size: 1 - - name: PRIV1BB7 - description: page privileged/unprivileged attribution - bit_offset: 7 - bit_size: 1 - - name: PRIV1BB8 - description: page privileged/unprivileged attribution - bit_offset: 8 - bit_size: 1 - - name: PRIV1BB9 - description: page privileged/unprivileged attribution - bit_offset: 9 - bit_size: 1 - - name: PRIV1BB10 - description: page privileged/unprivileged attribution - bit_offset: 10 - bit_size: 1 - - name: PRIV1BB11 - description: page privileged/unprivileged attribution - bit_offset: 11 - bit_size: 1 - - name: PRIV1BB12 - description: page privileged/unprivileged attribution - bit_offset: 12 - bit_size: 1 - - name: PRIV1BB13 - description: page privileged/unprivileged attribution - bit_offset: 13 - bit_size: 1 - - name: PRIV1BB14 - description: page privileged/unprivileged attribution - bit_offset: 14 - bit_size: 1 - - name: PRIV1BB15 - description: page privileged/unprivileged attribution - bit_offset: 15 - bit_size: 1 - - name: PRIV1BB16 - description: page privileged/unprivileged attribution - bit_offset: 16 - bit_size: 1 - - name: PRIV1BB17 - description: page privileged/unprivileged attribution - bit_offset: 17 - bit_size: 1 - - name: PRIV1BB18 - description: page privileged/unprivileged attribution - bit_offset: 18 - bit_size: 1 - - name: PRIV1BB19 - description: page privileged/unprivileged attribution - bit_offset: 19 - bit_size: 1 - - name: PRIV1BB20 - description: page privileged/unprivileged attribution - bit_offset: 20 - bit_size: 1 - - name: PRIV1BB21 - description: page privileged/unprivileged attribution - bit_offset: 21 - bit_size: 1 - - name: PRIV1BB22 - description: page privileged/unprivileged attribution - bit_offset: 22 - bit_size: 1 - - name: PRIV1BB23 - description: page privileged/unprivileged attribution - bit_offset: 23 - bit_size: 1 - - name: PRIV1BB24 - description: page privileged/unprivileged attribution - bit_offset: 24 - bit_size: 1 - - name: PRIV1BB25 - description: page privileged/unprivileged attribution - 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name: PRIV2BB27 + description: page privileged/unprivileged attribution + bit_offset: 27 + bit_size: 1 + - name: PRIV2BB28 + description: page privileged/unprivileged attribution + bit_offset: 28 + bit_size: 1 + - name: PRIV2BB29 + description: page privileged/unprivileged attribution + bit_offset: 29 + bit_size: 1 + - name: PRIV2BB30 + description: page privileged/unprivileged attribution + bit_offset: 30 + bit_size: 1 + - name: PRIV2BB31 + description: page privileged/unprivileged attribution + bit_offset: 31 + bit_size: 1 fieldset/PRIV2BBR2: description: FLASH privilege block based bank 2 register 2 fields: - - name: PRIV2BB0 - description: page privileged/unprivileged attribution - bit_offset: 0 - bit_size: 1 - - name: PRIV2BB1 - description: page privileged/unprivileged attribution - bit_offset: 1 - bit_size: 1 - - name: PRIV2BB2 - description: page privileged/unprivileged attribution - bit_offset: 2 - bit_size: 1 - - name: PRIV2BB3 - description: page privileged/unprivileged attribution - bit_offset: 3 - bit_size: 1 - - name: PRIV2BB4 - description: page privileged/unprivileged attribution - bit_offset: 4 - bit_size: 1 - - name: PRIV2BB5 - description: page privileged/unprivileged attribution - bit_offset: 5 - bit_size: 1 - - name: PRIV2BB6 - description: page privileged/unprivileged attribution - bit_offset: 6 - bit_size: 1 - - name: PRIV2BB7 - description: page privileged/unprivileged attribution - bit_offset: 7 - bit_size: 1 - - name: PRIV2BB8 - description: page privileged/unprivileged attribution - bit_offset: 8 - bit_size: 1 - - name: PRIV2BB9 - description: page privileged/unprivileged attribution - bit_offset: 9 - bit_size: 1 - - name: PRIV2BB10 - description: page privileged/unprivileged attribution - bit_offset: 10 - bit_size: 1 - - name: PRIV2BB11 - description: page privileged/unprivileged attribution - bit_offset: 11 - bit_size: 1 - - name: PRIV2BB12 - description: page privileged/unprivileged attribution - bit_offset: 12 - bit_size: 1 - - name: PRIV2BB13 - description: page privileged/unprivileged attribution - bit_offset: 13 - bit_size: 1 - - name: PRIV2BB14 - description: page privileged/unprivileged attribution - bit_offset: 14 - bit_size: 1 - - name: PRIV2BB15 - description: page privileged/unprivileged attribution - bit_offset: 15 - bit_size: 1 - - name: PRIV2BB16 - description: page privileged/unprivileged attribution - bit_offset: 16 - bit_size: 1 - - name: PRIV2BB17 - description: page privileged/unprivileged attribution - bit_offset: 17 - bit_size: 1 - - name: PRIV2BB18 - description: page privileged/unprivileged attribution - bit_offset: 18 - bit_size: 1 - - name: PRIV2BB19 - description: page privileged/unprivileged attribution - bit_offset: 19 - bit_size: 1 - - name: PRIV2BB20 - description: page privileged/unprivileged attribution - bit_offset: 20 - bit_size: 1 - - name: PRIV2BB21 - description: page privileged/unprivileged attribution - bit_offset: 21 - bit_size: 1 - - name: PRIV2BB22 - description: page privileged/unprivileged attribution - bit_offset: 22 - bit_size: 1 - - name: PRIV2BB23 - description: page privileged/unprivileged attribution - bit_offset: 23 - bit_size: 1 - - name: PRIV2BB24 - description: page privileged/unprivileged attribution - bit_offset: 24 - bit_size: 1 - - name: PRIV2BB25 - description: page privileged/unprivileged attribution - bit_offset: 25 - bit_size: 1 - - name: PRIV2BB26 - description: page privileged/unprivileged attribution - bit_offset: 26 - bit_size: 1 - - name: PRIV2BB27 - description: page privileged/unprivileged attribution - bit_offset: 27 - bit_size: 1 - - name: PRIV2BB28 - description: page privileged/unprivileged attribution - bit_offset: 28 - bit_size: 1 - - name: PRIV2BB29 - description: page privileged/unprivileged attribution - bit_offset: 29 - bit_size: 1 - - name: PRIV2BB30 - description: page privileged/unprivileged attribution - bit_offset: 30 - bit_size: 1 - - name: PRIV2BB31 - description: page privileged/unprivileged attribution - bit_offset: 31 - bit_size: 1 + - name: PRIV2BB0 + description: page privileged/unprivileged attribution + bit_offset: 0 + bit_size: 1 + - name: PRIV2BB1 + description: page privileged/unprivileged attribution + bit_offset: 1 + bit_size: 1 + - name: PRIV2BB2 + description: page privileged/unprivileged attribution + bit_offset: 2 + bit_size: 1 + - name: PRIV2BB3 + description: page privileged/unprivileged attribution + bit_offset: 3 + bit_size: 1 + - name: PRIV2BB4 + description: page privileged/unprivileged attribution + bit_offset: 4 + bit_size: 1 + - name: PRIV2BB5 + description: page privileged/unprivileged attribution + bit_offset: 5 + bit_size: 1 + - name: PRIV2BB6 + description: page privileged/unprivileged attribution + bit_offset: 6 + bit_size: 1 + - name: PRIV2BB7 + description: page privileged/unprivileged attribution + bit_offset: 7 + bit_size: 1 + - name: PRIV2BB8 + description: page privileged/unprivileged attribution + bit_offset: 8 + bit_size: 1 + - name: PRIV2BB9 + description: page privileged/unprivileged attribution + bit_offset: 9 + bit_size: 1 + - name: PRIV2BB10 + description: page privileged/unprivileged attribution + bit_offset: 10 + bit_size: 1 + - name: PRIV2BB11 + description: page privileged/unprivileged attribution + bit_offset: 11 + bit_size: 1 + - name: PRIV2BB12 + description: page privileged/unprivileged attribution + bit_offset: 12 + bit_size: 1 + - name: PRIV2BB13 + description: page privileged/unprivileged attribution + bit_offset: 13 + bit_size: 1 + - name: PRIV2BB14 + description: page privileged/unprivileged attribution + bit_offset: 14 + bit_size: 1 + - name: PRIV2BB15 + description: page privileged/unprivileged attribution + bit_offset: 15 + bit_size: 1 + - name: PRIV2BB16 + description: page privileged/unprivileged attribution + bit_offset: 16 + bit_size: 1 + - name: PRIV2BB17 + description: page privileged/unprivileged attribution + bit_offset: 17 + bit_size: 1 + - name: PRIV2BB18 + description: page privileged/unprivileged attribution + bit_offset: 18 + bit_size: 1 + - name: PRIV2BB19 + description: page privileged/unprivileged attribution + bit_offset: 19 + bit_size: 1 + - name: PRIV2BB20 + description: page privileged/unprivileged attribution + bit_offset: 20 + bit_size: 1 + - name: PRIV2BB21 + description: page privileged/unprivileged attribution + bit_offset: 21 + bit_size: 1 + - name: PRIV2BB22 + description: page privileged/unprivileged attribution + bit_offset: 22 + bit_size: 1 + - name: PRIV2BB23 + description: page privileged/unprivileged attribution + bit_offset: 23 + bit_size: 1 + - name: PRIV2BB24 + description: page privileged/unprivileged attribution + bit_offset: 24 + bit_size: 1 + - name: PRIV2BB25 + description: page privileged/unprivileged attribution + bit_offset: 25 + bit_size: 1 + - name: PRIV2BB26 + description: page privileged/unprivileged attribution + bit_offset: 26 + bit_size: 1 + - name: PRIV2BB27 + description: page privileged/unprivileged attribution + bit_offset: 27 + bit_size: 1 + - name: PRIV2BB28 + description: page privileged/unprivileged attribution + bit_offset: 28 + bit_size: 1 + - name: PRIV2BB29 + description: page privileged/unprivileged attribution + bit_offset: 29 + bit_size: 1 + - name: PRIV2BB30 + description: page privileged/unprivileged attribution + bit_offset: 30 + bit_size: 1 + - name: PRIV2BB31 + description: page privileged/unprivileged attribution + bit_offset: 31 + bit_size: 1 fieldset/PRIV2BBR3: description: FLASH privilege block based bank 2 register 3 fields: - - name: PRIV2BB0 - description: page privileged/unprivileged attribution - bit_offset: 0 - bit_size: 1 - - name: PRIV2BB1 - description: page privileged/unprivileged attribution - bit_offset: 1 - bit_size: 1 - - name: PRIV2BB2 - description: page privileged/unprivileged attribution - bit_offset: 2 - bit_size: 1 - - name: PRIV2BB3 - description: page privileged/unprivileged attribution - bit_offset: 3 - bit_size: 1 - - name: PRIV2BB4 - description: page privileged/unprivileged attribution - bit_offset: 4 - bit_size: 1 - - name: PRIV2BB5 - description: page privileged/unprivileged attribution - bit_offset: 5 - bit_size: 1 - - name: PRIV2BB6 - description: page privileged/unprivileged attribution - bit_offset: 6 - bit_size: 1 - - name: PRIV2BB7 - description: page privileged/unprivileged attribution - bit_offset: 7 - bit_size: 1 - - name: PRIV2BB8 - description: page privileged/unprivileged attribution - bit_offset: 8 - bit_size: 1 - - name: PRIV2BB9 - description: page privileged/unprivileged attribution - bit_offset: 9 - bit_size: 1 - - name: PRIV2BB10 - description: page privileged/unprivileged attribution - bit_offset: 10 - bit_size: 1 - - name: PRIV2BB11 - description: page privileged/unprivileged attribution - bit_offset: 11 - bit_size: 1 - - name: PRIV2BB12 - description: page privileged/unprivileged attribution - bit_offset: 12 - bit_size: 1 - - name: PRIV2BB13 - description: page privileged/unprivileged attribution - bit_offset: 13 - bit_size: 1 - - name: PRIV2BB14 - description: page privileged/unprivileged attribution - bit_offset: 14 - bit_size: 1 - - name: PRIV2BB15 - description: page privileged/unprivileged attribution - bit_offset: 15 - bit_size: 1 - - name: PRIV2BB16 - description: page privileged/unprivileged attribution - bit_offset: 16 - bit_size: 1 - - name: PRIV2BB17 - description: page privileged/unprivileged attribution - bit_offset: 17 - bit_size: 1 - - name: PRIV2BB18 - description: page privileged/unprivileged attribution - bit_offset: 18 - bit_size: 1 - - name: PRIV2BB19 - description: page privileged/unprivileged attribution - bit_offset: 19 - bit_size: 1 - - name: PRIV2BB20 - description: page privileged/unprivileged attribution - bit_offset: 20 - bit_size: 1 - - name: PRIV2BB21 - description: page privileged/unprivileged attribution - bit_offset: 21 - bit_size: 1 - - name: PRIV2BB22 - description: page privileged/unprivileged attribution - bit_offset: 22 - bit_size: 1 - - name: PRIV2BB23 - description: page privileged/unprivileged attribution - bit_offset: 23 - bit_size: 1 - - name: PRIV2BB24 - description: page privileged/unprivileged attribution - bit_offset: 24 - bit_size: 1 - - name: PRIV2BB25 - description: page privileged/unprivileged attribution - bit_offset: 25 - bit_size: 1 - - name: PRIV2BB26 - description: page privileged/unprivileged attribution - bit_offset: 26 - bit_size: 1 - - name: PRIV2BB27 - description: page privileged/unprivileged attribution - bit_offset: 27 - bit_size: 1 - - name: PRIV2BB28 - description: page privileged/unprivileged attribution - bit_offset: 28 - bit_size: 1 - - name: PRIV2BB29 - description: page privileged/unprivileged attribution - bit_offset: 29 - bit_size: 1 - - name: PRIV2BB30 - description: page privileged/unprivileged attribution - bit_offset: 30 - bit_size: 1 - - name: PRIV2BB31 - description: page privileged/unprivileged attribution - bit_offset: 31 - bit_size: 1 + - name: PRIV2BB0 + description: page privileged/unprivileged attribution + bit_offset: 0 + bit_size: 1 + - name: PRIV2BB1 + description: page privileged/unprivileged attribution + bit_offset: 1 + bit_size: 1 + - name: PRIV2BB2 + description: page privileged/unprivileged attribution + bit_offset: 2 + bit_size: 1 + - name: PRIV2BB3 + description: page privileged/unprivileged attribution + bit_offset: 3 + bit_size: 1 + - name: PRIV2BB4 + description: page privileged/unprivileged attribution + bit_offset: 4 + bit_size: 1 + - name: PRIV2BB5 + description: page privileged/unprivileged attribution + bit_offset: 5 + bit_size: 1 + - name: PRIV2BB6 + description: page privileged/unprivileged attribution + bit_offset: 6 + bit_size: 1 + - name: PRIV2BB7 + description: page privileged/unprivileged attribution + bit_offset: 7 + bit_size: 1 + - name: PRIV2BB8 + description: page privileged/unprivileged attribution + bit_offset: 8 + bit_size: 1 + - name: PRIV2BB9 + description: page privileged/unprivileged attribution + bit_offset: 9 + bit_size: 1 + - name: PRIV2BB10 + description: page privileged/unprivileged attribution + bit_offset: 10 + bit_size: 1 + - name: PRIV2BB11 + description: page privileged/unprivileged attribution + bit_offset: 11 + bit_size: 1 + - name: PRIV2BB12 + description: page privileged/unprivileged attribution + bit_offset: 12 + bit_size: 1 + - name: PRIV2BB13 + description: page privileged/unprivileged attribution + bit_offset: 13 + bit_size: 1 + - name: PRIV2BB14 + description: page privileged/unprivileged attribution + bit_offset: 14 + bit_size: 1 + - name: PRIV2BB15 + description: page privileged/unprivileged attribution + bit_offset: 15 + bit_size: 1 + - name: PRIV2BB16 + description: page privileged/unprivileged attribution + bit_offset: 16 + bit_size: 1 + - name: PRIV2BB17 + description: page privileged/unprivileged attribution + bit_offset: 17 + bit_size: 1 + - name: PRIV2BB18 + description: page privileged/unprivileged attribution + bit_offset: 18 + bit_size: 1 + - name: PRIV2BB19 + description: page privileged/unprivileged attribution + bit_offset: 19 + bit_size: 1 + - name: PRIV2BB20 + description: page privileged/unprivileged attribution + bit_offset: 20 + bit_size: 1 + - name: PRIV2BB21 + description: page privileged/unprivileged attribution + bit_offset: 21 + bit_size: 1 + - name: PRIV2BB22 + description: page privileged/unprivileged attribution + bit_offset: 22 + bit_size: 1 + - name: PRIV2BB23 + description: page privileged/unprivileged attribution + bit_offset: 23 + bit_size: 1 + - name: PRIV2BB24 + description: page privileged/unprivileged attribution + bit_offset: 24 + bit_size: 1 + - name: PRIV2BB25 + description: page privileged/unprivileged attribution + bit_offset: 25 + bit_size: 1 + - name: PRIV2BB26 + description: page privileged/unprivileged attribution + bit_offset: 26 + bit_size: 1 + - name: PRIV2BB27 + description: page privileged/unprivileged attribution + bit_offset: 27 + bit_size: 1 + - name: PRIV2BB28 + description: page privileged/unprivileged attribution + bit_offset: 28 + bit_size: 1 + - name: PRIV2BB29 + description: page privileged/unprivileged attribution + bit_offset: 29 + bit_size: 1 + - name: PRIV2BB30 + description: page privileged/unprivileged attribution + bit_offset: 30 + bit_size: 1 + - name: PRIV2BB31 + description: page privileged/unprivileged attribution + bit_offset: 31 + bit_size: 1 fieldset/PRIV2BBR4: description: FLASH privilege block based bank 2 register 4 fields: - - name: PRIV2BB0 - description: page privileged/unprivileged attribution - bit_offset: 0 - bit_size: 1 - - name: PRIV2BB1 - description: page privileged/unprivileged attribution - bit_offset: 1 - bit_size: 1 - - name: PRIV2BB2 - description: page privileged/unprivileged attribution - bit_offset: 2 - bit_size: 1 - - name: PRIV2BB3 - description: page privileged/unprivileged attribution - bit_offset: 3 - bit_size: 1 - - name: PRIV2BB4 - description: page privileged/unprivileged attribution - bit_offset: 4 - bit_size: 1 - - name: PRIV2BB5 - description: page privileged/unprivileged attribution - bit_offset: 5 - bit_size: 1 - - name: PRIV2BB6 - description: page privileged/unprivileged attribution - bit_offset: 6 - bit_size: 1 - - name: PRIV2BB7 - description: page privileged/unprivileged attribution - bit_offset: 7 - bit_size: 1 - - name: PRIV2BB8 - description: page privileged/unprivileged attribution - bit_offset: 8 - bit_size: 1 - - name: PRIV2BB9 - description: page privileged/unprivileged attribution - bit_offset: 9 - bit_size: 1 - - name: PRIV2BB10 - description: page privileged/unprivileged attribution - bit_offset: 10 - bit_size: 1 - - name: PRIV2BB11 - description: page privileged/unprivileged attribution - bit_offset: 11 - bit_size: 1 - - name: PRIV2BB12 - description: page privileged/unprivileged attribution - bit_offset: 12 - bit_size: 1 - - name: PRIV2BB13 - description: page privileged/unprivileged attribution - bit_offset: 13 - bit_size: 1 - - name: PRIV2BB14 - description: page privileged/unprivileged attribution - bit_offset: 14 - bit_size: 1 - - name: PRIV2BB15 - description: page privileged/unprivileged attribution - bit_offset: 15 - bit_size: 1 - - name: PRIV2BB16 - description: page privileged/unprivileged attribution - bit_offset: 16 - bit_size: 1 - - name: PRIV2BB17 - description: page privileged/unprivileged attribution - bit_offset: 17 - bit_size: 1 - - name: PRIV2BB18 - description: page privileged/unprivileged attribution - bit_offset: 18 - bit_size: 1 - - name: PRIV2BB19 - description: page privileged/unprivileged attribution - bit_offset: 19 - bit_size: 1 - - name: PRIV2BB20 - description: page privileged/unprivileged attribution - bit_offset: 20 - bit_size: 1 - - name: PRIV2BB21 - description: page privileged/unprivileged attribution - bit_offset: 21 - bit_size: 1 - - name: PRIV2BB22 - description: page privileged/unprivileged attribution - bit_offset: 22 - bit_size: 1 - - name: PRIV2BB23 - description: page privileged/unprivileged attribution - bit_offset: 23 - bit_size: 1 - - name: PRIV2BB24 - description: page privileged/unprivileged attribution - bit_offset: 24 - bit_size: 1 - - name: PRIV2BB25 - description: page privileged/unprivileged attribution - bit_offset: 25 - bit_size: 1 - - name: PRIV2BB26 - description: page privileged/unprivileged attribution - bit_offset: 26 - bit_size: 1 - - name: PRIV2BB27 - description: page privileged/unprivileged attribution - bit_offset: 27 - bit_size: 1 - - name: PRIV2BB28 - description: page privileged/unprivileged attribution - bit_offset: 28 - bit_size: 1 - - name: PRIV2BB29 - description: page privileged/unprivileged attribution - bit_offset: 29 - bit_size: 1 - - name: PRIV2BB30 - description: page privileged/unprivileged attribution - bit_offset: 30 - bit_size: 1 - - name: PRIV2BB31 - description: page privileged/unprivileged attribution - bit_offset: 31 - bit_size: 1 + - name: PRIV2BB0 + description: page privileged/unprivileged attribution + bit_offset: 0 + bit_size: 1 + - name: PRIV2BB1 + description: page privileged/unprivileged attribution + bit_offset: 1 + bit_size: 1 + - name: PRIV2BB2 + description: page privileged/unprivileged attribution + bit_offset: 2 + bit_size: 1 + - name: PRIV2BB3 + description: page privileged/unprivileged attribution + bit_offset: 3 + bit_size: 1 + - name: PRIV2BB4 + description: page privileged/unprivileged attribution + bit_offset: 4 + bit_size: 1 + - name: PRIV2BB5 + description: page privileged/unprivileged attribution + bit_offset: 5 + bit_size: 1 + - name: PRIV2BB6 + description: page privileged/unprivileged attribution + bit_offset: 6 + bit_size: 1 + - name: PRIV2BB7 + description: page privileged/unprivileged attribution + bit_offset: 7 + bit_size: 1 + - name: PRIV2BB8 + description: page privileged/unprivileged attribution + bit_offset: 8 + bit_size: 1 + - name: PRIV2BB9 + description: page privileged/unprivileged attribution + bit_offset: 9 + bit_size: 1 + - name: PRIV2BB10 + description: page privileged/unprivileged attribution + bit_offset: 10 + bit_size: 1 + - name: PRIV2BB11 + description: page privileged/unprivileged attribution + bit_offset: 11 + bit_size: 1 + - name: PRIV2BB12 + description: page privileged/unprivileged attribution + bit_offset: 12 + bit_size: 1 + - name: PRIV2BB13 + description: page privileged/unprivileged attribution + bit_offset: 13 + bit_size: 1 + - name: PRIV2BB14 + description: page privileged/unprivileged attribution + bit_offset: 14 + bit_size: 1 + - name: PRIV2BB15 + description: page privileged/unprivileged attribution + bit_offset: 15 + bit_size: 1 + - name: PRIV2BB16 + description: page privileged/unprivileged attribution + bit_offset: 16 + bit_size: 1 + - name: PRIV2BB17 + description: page privileged/unprivileged attribution + bit_offset: 17 + bit_size: 1 + - name: PRIV2BB18 + description: page privileged/unprivileged attribution + bit_offset: 18 + bit_size: 1 + - name: PRIV2BB19 + description: page privileged/unprivileged attribution + bit_offset: 19 + bit_size: 1 + - name: PRIV2BB20 + description: page privileged/unprivileged attribution + bit_offset: 20 + bit_size: 1 + - name: PRIV2BB21 + description: page privileged/unprivileged attribution + bit_offset: 21 + bit_size: 1 + - name: PRIV2BB22 + description: page privileged/unprivileged attribution + bit_offset: 22 + bit_size: 1 + - name: PRIV2BB23 + description: page privileged/unprivileged attribution + bit_offset: 23 + bit_size: 1 + - name: PRIV2BB24 + description: page privileged/unprivileged attribution + bit_offset: 24 + bit_size: 1 + - name: PRIV2BB25 + description: page privileged/unprivileged attribution + bit_offset: 25 + bit_size: 1 + - name: PRIV2BB26 + description: page privileged/unprivileged attribution + bit_offset: 26 + bit_size: 1 + - name: PRIV2BB27 + description: page privileged/unprivileged attribution + bit_offset: 27 + bit_size: 1 + - name: PRIV2BB28 + description: page privileged/unprivileged attribution + bit_offset: 28 + bit_size: 1 + - name: PRIV2BB29 + description: page privileged/unprivileged attribution + bit_offset: 29 + bit_size: 1 + - name: PRIV2BB30 + description: page privileged/unprivileged attribution + bit_offset: 30 + bit_size: 1 + - name: PRIV2BB31 + description: page privileged/unprivileged attribution + bit_offset: 31 + bit_size: 1 fieldset/PRIVCFGR: description: FLASH privilege configuration register fields: - - name: SPRIV - description: "Privileged protection for secure registers\r This bit can be accessed only when TrustZone is enabled (TZEN = 1). This bit can be read by both privileged or unprivileged, secure and non-secure access.\r The SPRIV bit can be written only by a secure privileged access. A non-secure write access on SPRIV bit is ignored. A secure unprivileged write access on SPRIV bit is ignored." - bit_offset: 0 - bit_size: 1 - enum: SPRIV - - name: NSPRIV - description: "Privileged protection for non-secure registers\r This bit can be read by both privileged or unprivileged, secure and non-secure access.\r The NSPRIV bit can be written by a secure or non-secure privileged access. A secure or non-secure unprivileged write access on NSPRIV bit is ignored." - bit_offset: 1 - bit_size: 1 - enum: NSPRIV + - name: SPRIV + description: "Privileged protection for secure registers\r This bit can be accessed only when TrustZone is enabled (TZEN = 1). This bit can be read by both privileged or unprivileged, secure and non-secure access.\r The SPRIV bit can be written only by a secure privileged access. A non-secure write access on SPRIV bit is ignored. A secure unprivileged write access on SPRIV bit is ignored." + bit_offset: 0 + bit_size: 1 + enum: SPRIV + - name: NSPRIV + description: "Privileged protection for non-secure registers\r This bit can be read by both privileged or unprivileged, secure and non-secure access.\r The NSPRIV bit can be written by a secure or non-secure privileged access. A secure or non-secure unprivileged write access on NSPRIV bit is ignored." + bit_offset: 1 + bit_size: 1 + enum: NSPRIV fieldset/SEC1BBR1: description: FLASH secure block based bank 1 register 1 fields: - - name: SEC1BB0 - description: page secure/non-secure attribution - bit_offset: 0 - bit_size: 1 - - name: SEC1BB1 - description: page secure/non-secure attribution - bit_offset: 1 - bit_size: 1 - - name: SEC1BB2 - description: page secure/non-secure attribution - bit_offset: 2 - bit_size: 1 - - name: SEC1BB3 - description: page secure/non-secure attribution - bit_offset: 3 - bit_size: 1 - - name: SEC1BB4 - description: page secure/non-secure attribution - bit_offset: 4 - bit_size: 1 - - name: SEC1BB5 - description: page secure/non-secure attribution - bit_offset: 5 - bit_size: 1 - - name: SEC1BB6 - description: page secure/non-secure attribution - bit_offset: 6 - bit_size: 1 - - name: SEC1BB7 - description: page secure/non-secure attribution - bit_offset: 7 - bit_size: 1 - - name: SEC1BB8 - description: page secure/non-secure attribution - bit_offset: 8 - bit_size: 1 - - name: SEC1BB9 - description: page secure/non-secure attribution - bit_offset: 9 - bit_size: 1 - - name: SEC1BB10 - description: page secure/non-secure attribution - bit_offset: 10 - bit_size: 1 - - name: SEC1BB11 - description: page secure/non-secure attribution - bit_offset: 11 - bit_size: 1 - - name: SEC1BB12 - description: page secure/non-secure attribution - bit_offset: 12 - bit_size: 1 - - name: SEC1BB13 - description: page secure/non-secure attribution - bit_offset: 13 - bit_size: 1 - - name: SEC1BB14 - description: page secure/non-secure attribution - bit_offset: 14 - bit_size: 1 - - name: SEC1BB15 - description: page secure/non-secure attribution - bit_offset: 15 - bit_size: 1 - - name: SEC1BB16 - description: page secure/non-secure attribution - bit_offset: 16 - bit_size: 1 - - name: SEC1BB17 - description: page secure/non-secure attribution - bit_offset: 17 - bit_size: 1 - - name: SEC1BB18 - description: page secure/non-secure attribution - bit_offset: 18 - bit_size: 1 - - name: SEC1BB19 - description: page secure/non-secure attribution - bit_offset: 19 - bit_size: 1 - - name: SEC1BB20 - description: page secure/non-secure attribution - bit_offset: 20 - bit_size: 1 - - name: SEC1BB21 - description: page secure/non-secure attribution - bit_offset: 21 - bit_size: 1 - - name: SEC1BB22 - description: page secure/non-secure attribution - bit_offset: 22 - bit_size: 1 - - name: SEC1BB23 - description: page secure/non-secure attribution - bit_offset: 23 - bit_size: 1 - - name: SEC1BB24 - description: page secure/non-secure attribution - bit_offset: 24 - bit_size: 1 - - name: SEC1BB25 - description: page secure/non-secure attribution - bit_offset: 25 - bit_size: 1 - - name: SEC1BB26 - description: page secure/non-secure attribution - bit_offset: 26 - bit_size: 1 - - name: SEC1BB27 - description: page secure/non-secure attribution - bit_offset: 27 - bit_size: 1 - - name: SEC1BB28 - description: page secure/non-secure attribution - bit_offset: 28 - bit_size: 1 - - name: SEC1BB29 - description: page secure/non-secure attribution - bit_offset: 29 - bit_size: 1 - - name: SEC1BB30 - description: page secure/non-secure attribution - bit_offset: 30 - bit_size: 1 - - name: SEC1BB31 - description: page secure/non-secure attribution - bit_offset: 31 - bit_size: 1 + - name: SEC1BB0 + description: page secure/non-secure attribution + bit_offset: 0 + bit_size: 1 + - name: SEC1BB1 + description: page secure/non-secure attribution + bit_offset: 1 + bit_size: 1 + - name: SEC1BB2 + description: page secure/non-secure attribution + bit_offset: 2 + bit_size: 1 + - name: SEC1BB3 + description: page secure/non-secure attribution + bit_offset: 3 + bit_size: 1 + - name: SEC1BB4 + description: page secure/non-secure attribution + bit_offset: 4 + bit_size: 1 + - name: SEC1BB5 + description: page secure/non-secure attribution + bit_offset: 5 + bit_size: 1 + - name: SEC1BB6 + description: page secure/non-secure attribution + bit_offset: 6 + bit_size: 1 + - name: SEC1BB7 + description: page secure/non-secure attribution + bit_offset: 7 + bit_size: 1 + - name: SEC1BB8 + description: page secure/non-secure attribution + bit_offset: 8 + bit_size: 1 + - name: SEC1BB9 + description: page secure/non-secure attribution + bit_offset: 9 + bit_size: 1 + - name: SEC1BB10 + description: page secure/non-secure attribution + bit_offset: 10 + bit_size: 1 + - name: SEC1BB11 + description: page secure/non-secure attribution + bit_offset: 11 + bit_size: 1 + - name: SEC1BB12 + description: page secure/non-secure attribution + bit_offset: 12 + bit_size: 1 + - name: SEC1BB13 + description: page secure/non-secure attribution + bit_offset: 13 + bit_size: 1 + - name: SEC1BB14 + description: page secure/non-secure attribution + bit_offset: 14 + bit_size: 1 + - name: SEC1BB15 + description: page secure/non-secure attribution + bit_offset: 15 + bit_size: 1 + - name: SEC1BB16 + description: page secure/non-secure attribution + bit_offset: 16 + bit_size: 1 + - name: SEC1BB17 + description: page secure/non-secure attribution + bit_offset: 17 + bit_size: 1 + - name: SEC1BB18 + description: page secure/non-secure attribution + bit_offset: 18 + bit_size: 1 + - name: SEC1BB19 + description: page secure/non-secure attribution + bit_offset: 19 + bit_size: 1 + - name: SEC1BB20 + description: page secure/non-secure attribution + bit_offset: 20 + bit_size: 1 + - name: SEC1BB21 + description: page secure/non-secure attribution + bit_offset: 21 + bit_size: 1 + - name: SEC1BB22 + description: page secure/non-secure attribution + bit_offset: 22 + bit_size: 1 + - name: SEC1BB23 + description: page secure/non-secure attribution + bit_offset: 23 + bit_size: 1 + - name: SEC1BB24 + description: page secure/non-secure attribution + bit_offset: 24 + bit_size: 1 + - name: SEC1BB25 + description: page secure/non-secure attribution + bit_offset: 25 + bit_size: 1 + - name: SEC1BB26 + description: page secure/non-secure attribution + bit_offset: 26 + bit_size: 1 + - name: SEC1BB27 + description: page secure/non-secure attribution + bit_offset: 27 + bit_size: 1 + - name: SEC1BB28 + description: page secure/non-secure attribution + bit_offset: 28 + bit_size: 1 + - name: SEC1BB29 + description: page secure/non-secure attribution + bit_offset: 29 + bit_size: 1 + - name: SEC1BB30 + description: page secure/non-secure attribution + bit_offset: 30 + bit_size: 1 + - name: SEC1BB31 + description: page secure/non-secure attribution + bit_offset: 31 + bit_size: 1 fieldset/SEC1BBR2: description: FLASH secure block based bank 1 register 2 fields: - - name: SEC1BB0 - description: page secure/non-secure attribution - bit_offset: 0 - bit_size: 1 - - name: SEC1BB1 - description: page secure/non-secure attribution - bit_offset: 1 - bit_size: 1 - - name: SEC1BB2 - description: page secure/non-secure attribution - bit_offset: 2 - bit_size: 1 - - name: SEC1BB3 - description: page secure/non-secure attribution - bit_offset: 3 - bit_size: 1 - - name: SEC1BB4 - description: page secure/non-secure attribution - bit_offset: 4 - bit_size: 1 - - name: SEC1BB5 - description: page secure/non-secure attribution - bit_offset: 5 - bit_size: 1 - - name: SEC1BB6 - description: page secure/non-secure attribution - bit_offset: 6 - bit_size: 1 - - name: SEC1BB7 - description: page secure/non-secure attribution - bit_offset: 7 - bit_size: 1 - - name: SEC1BB8 - description: page secure/non-secure attribution - bit_offset: 8 - bit_size: 1 - - name: SEC1BB9 - description: page secure/non-secure attribution - bit_offset: 9 - bit_size: 1 - - name: SEC1BB10 - description: page secure/non-secure attribution - bit_offset: 10 - bit_size: 1 - - name: SEC1BB11 - description: page secure/non-secure attribution - bit_offset: 11 - bit_size: 1 - - name: SEC1BB12 - description: page secure/non-secure attribution - bit_offset: 12 - bit_size: 1 - - name: SEC1BB13 - description: page secure/non-secure attribution - bit_offset: 13 - bit_size: 1 - - name: SEC1BB14 - description: page secure/non-secure attribution - bit_offset: 14 - bit_size: 1 - - name: SEC1BB15 - description: page secure/non-secure attribution - bit_offset: 15 - bit_size: 1 - - name: SEC1BB16 - description: page secure/non-secure attribution - bit_offset: 16 - bit_size: 1 - - name: SEC1BB17 - description: page secure/non-secure attribution - bit_offset: 17 - bit_size: 1 - - name: SEC1BB18 - description: page secure/non-secure attribution - bit_offset: 18 - bit_size: 1 - - name: SEC1BB19 - description: page secure/non-secure attribution - bit_offset: 19 - bit_size: 1 - - name: SEC1BB20 - description: page secure/non-secure attribution - bit_offset: 20 - bit_size: 1 - - name: SEC1BB21 - description: page secure/non-secure attribution - bit_offset: 21 - bit_size: 1 - - name: SEC1BB22 - description: page secure/non-secure attribution - bit_offset: 22 - bit_size: 1 - - name: SEC1BB23 - description: page secure/non-secure attribution - bit_offset: 23 - bit_size: 1 - - name: SEC1BB24 - description: page secure/non-secure attribution - bit_offset: 24 - bit_size: 1 - - name: SEC1BB25 - description: page secure/non-secure attribution - bit_offset: 25 - bit_size: 1 - - name: SEC1BB26 - description: page secure/non-secure attribution - bit_offset: 26 - bit_size: 1 - - name: SEC1BB27 - description: page secure/non-secure attribution - bit_offset: 27 - bit_size: 1 - - name: SEC1BB28 - description: page secure/non-secure attribution - bit_offset: 28 - bit_size: 1 - - name: SEC1BB29 - description: page secure/non-secure attribution - bit_offset: 29 - bit_size: 1 - - name: SEC1BB30 - description: page secure/non-secure attribution - bit_offset: 30 - bit_size: 1 - - name: SEC1BB31 - description: page secure/non-secure attribution - bit_offset: 31 - bit_size: 1 + - name: SEC1BB0 + description: page secure/non-secure attribution + bit_offset: 0 + bit_size: 1 + - name: SEC1BB1 + description: page secure/non-secure attribution + bit_offset: 1 + bit_size: 1 + - name: SEC1BB2 + description: page secure/non-secure attribution + bit_offset: 2 + bit_size: 1 + - name: SEC1BB3 + description: page secure/non-secure attribution + bit_offset: 3 + bit_size: 1 + - name: SEC1BB4 + description: page secure/non-secure attribution + bit_offset: 4 + bit_size: 1 + - name: SEC1BB5 + description: page secure/non-secure attribution + bit_offset: 5 + bit_size: 1 + - name: SEC1BB6 + description: page secure/non-secure attribution + bit_offset: 6 + bit_size: 1 + - name: SEC1BB7 + description: page secure/non-secure attribution + bit_offset: 7 + bit_size: 1 + - name: SEC1BB8 + description: page secure/non-secure attribution + bit_offset: 8 + bit_size: 1 + - name: SEC1BB9 + description: page secure/non-secure attribution + bit_offset: 9 + bit_size: 1 + - name: SEC1BB10 + description: page secure/non-secure attribution + bit_offset: 10 + bit_size: 1 + - name: SEC1BB11 + description: page secure/non-secure attribution + bit_offset: 11 + bit_size: 1 + - name: SEC1BB12 + description: page secure/non-secure attribution + bit_offset: 12 + bit_size: 1 + - name: SEC1BB13 + description: page secure/non-secure attribution + bit_offset: 13 + bit_size: 1 + - name: SEC1BB14 + description: page secure/non-secure attribution + bit_offset: 14 + bit_size: 1 + - name: SEC1BB15 + description: page secure/non-secure attribution + bit_offset: 15 + bit_size: 1 + - name: SEC1BB16 + description: page secure/non-secure attribution + bit_offset: 16 + bit_size: 1 + - name: SEC1BB17 + description: page secure/non-secure attribution + bit_offset: 17 + bit_size: 1 + - name: SEC1BB18 + description: page secure/non-secure attribution + bit_offset: 18 + bit_size: 1 + - name: SEC1BB19 + description: page secure/non-secure attribution + bit_offset: 19 + bit_size: 1 + - name: SEC1BB20 + description: page secure/non-secure attribution + bit_offset: 20 + bit_size: 1 + - name: SEC1BB21 + description: page secure/non-secure attribution + bit_offset: 21 + bit_size: 1 + - name: SEC1BB22 + description: page secure/non-secure attribution + bit_offset: 22 + bit_size: 1 + - name: SEC1BB23 + description: page secure/non-secure attribution + bit_offset: 23 + bit_size: 1 + - name: SEC1BB24 + description: page secure/non-secure attribution + bit_offset: 24 + bit_size: 1 + - name: SEC1BB25 + description: page secure/non-secure attribution + bit_offset: 25 + bit_size: 1 + - name: SEC1BB26 + description: page secure/non-secure attribution + bit_offset: 26 + bit_size: 1 + - name: SEC1BB27 + description: page secure/non-secure attribution + bit_offset: 27 + bit_size: 1 + - name: SEC1BB28 + description: page secure/non-secure attribution + bit_offset: 28 + bit_size: 1 + - name: SEC1BB29 + description: page secure/non-secure attribution + bit_offset: 29 + bit_size: 1 + - name: SEC1BB30 + description: page secure/non-secure attribution + bit_offset: 30 + bit_size: 1 + - name: SEC1BB31 + description: page secure/non-secure attribution + bit_offset: 31 + bit_size: 1 fieldset/SEC1BBR3: description: FLASH secure block based bank 1 register 3 fields: - - name: SEC1BB0 - description: page secure/non-secure attribution - bit_offset: 0 - bit_size: 1 - - name: SEC1BB1 - description: page secure/non-secure attribution - bit_offset: 1 - bit_size: 1 - - name: SEC1BB2 - description: page secure/non-secure attribution - bit_offset: 2 - bit_size: 1 - - name: SEC1BB3 - description: page secure/non-secure attribution - bit_offset: 3 - bit_size: 1 - - name: SEC1BB4 - description: page secure/non-secure attribution - bit_offset: 4 - bit_size: 1 - - name: SEC1BB5 - description: page secure/non-secure attribution - bit_offset: 5 - bit_size: 1 - - name: SEC1BB6 - description: page secure/non-secure attribution - bit_offset: 6 - bit_size: 1 - - name: SEC1BB7 - description: page secure/non-secure attribution - bit_offset: 7 - bit_size: 1 - - name: SEC1BB8 - description: page secure/non-secure attribution - bit_offset: 8 - bit_size: 1 - - name: SEC1BB9 - description: page secure/non-secure attribution - bit_offset: 9 - bit_size: 1 - - name: SEC1BB10 - description: page secure/non-secure attribution - bit_offset: 10 - bit_size: 1 - - name: SEC1BB11 - description: page secure/non-secure attribution - bit_offset: 11 - bit_size: 1 - - name: SEC1BB12 - description: page secure/non-secure attribution - bit_offset: 12 - bit_size: 1 - - name: SEC1BB13 - description: page secure/non-secure attribution - bit_offset: 13 - bit_size: 1 - - name: SEC1BB14 - description: page secure/non-secure attribution - bit_offset: 14 - bit_size: 1 - - name: SEC1BB15 - description: page secure/non-secure attribution - bit_offset: 15 - bit_size: 1 - - name: SEC1BB16 - description: page secure/non-secure attribution - bit_offset: 16 - bit_size: 1 - - name: SEC1BB17 - description: page secure/non-secure attribution - bit_offset: 17 - bit_size: 1 - - name: SEC1BB18 - description: page secure/non-secure attribution - bit_offset: 18 - bit_size: 1 - - name: SEC1BB19 - description: page secure/non-secure attribution - bit_offset: 19 - bit_size: 1 - - name: SEC1BB20 - description: page secure/non-secure attribution - bit_offset: 20 - bit_size: 1 - - name: SEC1BB21 - description: page secure/non-secure attribution - bit_offset: 21 - bit_size: 1 - - name: SEC1BB22 - description: page secure/non-secure attribution - bit_offset: 22 - bit_size: 1 - - name: SEC1BB23 - description: page secure/non-secure attribution - bit_offset: 23 - bit_size: 1 - - name: SEC1BB24 - description: page secure/non-secure attribution - bit_offset: 24 - bit_size: 1 - - name: SEC1BB25 - description: page secure/non-secure attribution - bit_offset: 25 - bit_size: 1 - - name: SEC1BB26 - description: page secure/non-secure attribution - bit_offset: 26 - bit_size: 1 - - name: SEC1BB27 - description: page secure/non-secure attribution - bit_offset: 27 - bit_size: 1 - - name: SEC1BB28 - description: page secure/non-secure attribution - bit_offset: 28 - bit_size: 1 - - name: SEC1BB29 - description: page secure/non-secure attribution - bit_offset: 29 - bit_size: 1 - - name: SEC1BB30 - description: page secure/non-secure attribution - bit_offset: 30 - bit_size: 1 - - name: SEC1BB31 - description: page secure/non-secure attribution - bit_offset: 31 - bit_size: 1 + - name: SEC1BB0 + description: page secure/non-secure attribution + bit_offset: 0 + bit_size: 1 + - name: SEC1BB1 + description: page secure/non-secure attribution + bit_offset: 1 + bit_size: 1 + - name: SEC1BB2 + description: page secure/non-secure attribution + bit_offset: 2 + bit_size: 1 + - name: SEC1BB3 + description: page secure/non-secure attribution + bit_offset: 3 + bit_size: 1 + - name: SEC1BB4 + description: page secure/non-secure attribution + bit_offset: 4 + bit_size: 1 + - name: SEC1BB5 + description: page secure/non-secure attribution + bit_offset: 5 + bit_size: 1 + - name: SEC1BB6 + description: page secure/non-secure attribution + bit_offset: 6 + bit_size: 1 + - name: SEC1BB7 + description: page secure/non-secure attribution + bit_offset: 7 + bit_size: 1 + - name: SEC1BB8 + description: page secure/non-secure attribution + bit_offset: 8 + bit_size: 1 + - name: SEC1BB9 + description: page secure/non-secure attribution + bit_offset: 9 + bit_size: 1 + - name: SEC1BB10 + description: page secure/non-secure attribution + bit_offset: 10 + bit_size: 1 + - name: SEC1BB11 + description: page secure/non-secure attribution + bit_offset: 11 + bit_size: 1 + - name: SEC1BB12 + description: page secure/non-secure attribution + bit_offset: 12 + bit_size: 1 + - name: SEC1BB13 + description: page secure/non-secure attribution + bit_offset: 13 + bit_size: 1 + - name: SEC1BB14 + description: page secure/non-secure attribution + bit_offset: 14 + bit_size: 1 + - name: SEC1BB15 + description: page secure/non-secure attribution + bit_offset: 15 + bit_size: 1 + - name: SEC1BB16 + description: page secure/non-secure attribution + bit_offset: 16 + bit_size: 1 + - name: SEC1BB17 + description: page secure/non-secure attribution + bit_offset: 17 + bit_size: 1 + - name: SEC1BB18 + description: page secure/non-secure attribution + bit_offset: 18 + bit_size: 1 + - name: SEC1BB19 + description: page secure/non-secure attribution + bit_offset: 19 + bit_size: 1 + - name: SEC1BB20 + description: page secure/non-secure attribution + bit_offset: 20 + bit_size: 1 + - name: SEC1BB21 + description: page secure/non-secure attribution + bit_offset: 21 + bit_size: 1 + - name: SEC1BB22 + description: page secure/non-secure attribution + bit_offset: 22 + bit_size: 1 + - name: SEC1BB23 + description: page secure/non-secure attribution + bit_offset: 23 + bit_size: 1 + - name: SEC1BB24 + description: page secure/non-secure attribution + bit_offset: 24 + bit_size: 1 + - name: SEC1BB25 + description: page secure/non-secure attribution + bit_offset: 25 + bit_size: 1 + - name: SEC1BB26 + description: page secure/non-secure attribution + bit_offset: 26 + bit_size: 1 + - name: SEC1BB27 + description: page secure/non-secure attribution + bit_offset: 27 + bit_size: 1 + - name: SEC1BB28 + description: page secure/non-secure attribution + bit_offset: 28 + bit_size: 1 + - name: SEC1BB29 + description: page secure/non-secure attribution + bit_offset: 29 + bit_size: 1 + - name: SEC1BB30 + description: page secure/non-secure attribution + bit_offset: 30 + bit_size: 1 + - name: SEC1BB31 + description: page secure/non-secure attribution + bit_offset: 31 + bit_size: 1 fieldset/SEC1BBR4: description: FLASH secure block based bank 1 register 4 fields: - - name: SEC1BB0 - description: page secure/non-secure attribution - bit_offset: 0 - bit_size: 1 - - name: SEC1BB1 - description: page secure/non-secure attribution - bit_offset: 1 - bit_size: 1 - - name: SEC1BB2 - description: page secure/non-secure attribution - bit_offset: 2 - bit_size: 1 - - name: SEC1BB3 - description: page secure/non-secure attribution - bit_offset: 3 - bit_size: 1 - - name: SEC1BB4 - description: page secure/non-secure attribution - bit_offset: 4 - bit_size: 1 - - name: SEC1BB5 - description: page secure/non-secure attribution - bit_offset: 5 - bit_size: 1 - - name: SEC1BB6 - description: page secure/non-secure attribution - bit_offset: 6 - bit_size: 1 - - name: SEC1BB7 - description: page secure/non-secure attribution - bit_offset: 7 - bit_size: 1 - - name: SEC1BB8 - description: page secure/non-secure attribution - bit_offset: 8 - bit_size: 1 - - name: SEC1BB9 - description: page secure/non-secure attribution - bit_offset: 9 - bit_size: 1 - - name: SEC1BB10 - description: page secure/non-secure attribution - bit_offset: 10 - bit_size: 1 - - name: SEC1BB11 - description: page secure/non-secure attribution - bit_offset: 11 - bit_size: 1 - - name: SEC1BB12 - description: page secure/non-secure attribution - bit_offset: 12 - bit_size: 1 - - name: SEC1BB13 - description: page secure/non-secure attribution - bit_offset: 13 - bit_size: 1 - - name: SEC1BB14 - description: page secure/non-secure attribution - bit_offset: 14 - bit_size: 1 - - name: SEC1BB15 - description: page secure/non-secure attribution - bit_offset: 15 - bit_size: 1 - - name: SEC1BB16 - description: page secure/non-secure attribution - bit_offset: 16 - bit_size: 1 - - name: SEC1BB17 - description: page secure/non-secure attribution - bit_offset: 17 - bit_size: 1 - - name: SEC1BB18 - description: page secure/non-secure attribution - bit_offset: 18 - bit_size: 1 - - name: SEC1BB19 - description: page secure/non-secure attribution - bit_offset: 19 - bit_size: 1 - - name: SEC1BB20 - description: page secure/non-secure attribution - bit_offset: 20 - bit_size: 1 - - name: SEC1BB21 - description: page secure/non-secure attribution - bit_offset: 21 - bit_size: 1 - - name: SEC1BB22 - description: page secure/non-secure attribution - bit_offset: 22 - bit_size: 1 - - name: SEC1BB23 - description: page secure/non-secure attribution - bit_offset: 23 - bit_size: 1 - - name: SEC1BB24 - description: page secure/non-secure attribution - bit_offset: 24 - bit_size: 1 - - name: SEC1BB25 - description: page secure/non-secure attribution - bit_offset: 25 - bit_size: 1 - - name: SEC1BB26 - description: page secure/non-secure attribution - bit_offset: 26 - bit_size: 1 - - name: SEC1BB27 - description: page secure/non-secure attribution - bit_offset: 27 - bit_size: 1 - - name: SEC1BB28 - description: page secure/non-secure attribution - bit_offset: 28 - bit_size: 1 - - name: SEC1BB29 - description: page secure/non-secure attribution - bit_offset: 29 - bit_size: 1 - - name: SEC1BB30 - description: page secure/non-secure attribution - bit_offset: 30 - bit_size: 1 - - name: SEC1BB31 - description: page secure/non-secure attribution - bit_offset: 31 - bit_size: 1 + - name: SEC1BB0 + description: page secure/non-secure attribution + bit_offset: 0 + bit_size: 1 + - name: SEC1BB1 + description: page secure/non-secure attribution + bit_offset: 1 + bit_size: 1 + - name: SEC1BB2 + description: page secure/non-secure attribution + bit_offset: 2 + bit_size: 1 + - name: SEC1BB3 + description: page secure/non-secure attribution + bit_offset: 3 + bit_size: 1 + - name: SEC1BB4 + description: page secure/non-secure attribution + bit_offset: 4 + bit_size: 1 + - name: SEC1BB5 + description: page secure/non-secure attribution + bit_offset: 5 + bit_size: 1 + - name: SEC1BB6 + description: page secure/non-secure attribution + bit_offset: 6 + bit_size: 1 + - name: SEC1BB7 + description: page secure/non-secure attribution + bit_offset: 7 + bit_size: 1 + - name: SEC1BB8 + description: page secure/non-secure attribution + bit_offset: 8 + bit_size: 1 + - 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name: SEC2BB7 + description: page secure/non-secure attribution + bit_offset: 7 + bit_size: 1 + - name: SEC2BB8 + description: page secure/non-secure attribution + bit_offset: 8 + bit_size: 1 + - name: SEC2BB9 + description: page secure/non-secure attribution + bit_offset: 9 + bit_size: 1 + - name: SEC2BB10 + description: page secure/non-secure attribution + bit_offset: 10 + bit_size: 1 + - name: SEC2BB11 + description: page secure/non-secure attribution + bit_offset: 11 + bit_size: 1 + - name: SEC2BB12 + description: page secure/non-secure attribution + bit_offset: 12 + bit_size: 1 + - name: SEC2BB13 + description: page secure/non-secure attribution + bit_offset: 13 + bit_size: 1 + - name: SEC2BB14 + description: page secure/non-secure attribution + bit_offset: 14 + bit_size: 1 + - name: SEC2BB15 + description: page secure/non-secure attribution + bit_offset: 15 + bit_size: 1 + - name: SEC2BB16 + description: page secure/non-secure attribution + bit_offset: 16 + bit_size: 1 + - name: SEC2BB17 + description: page secure/non-secure attribution + bit_offset: 17 + bit_size: 1 + - name: SEC2BB18 + description: page secure/non-secure attribution + bit_offset: 18 + bit_size: 1 + - name: SEC2BB19 + description: page secure/non-secure attribution + bit_offset: 19 + bit_size: 1 + - name: SEC2BB20 + description: page secure/non-secure attribution + bit_offset: 20 + bit_size: 1 + - name: SEC2BB21 + description: page secure/non-secure attribution + bit_offset: 21 + bit_size: 1 + - name: SEC2BB22 + description: page secure/non-secure attribution + bit_offset: 22 + bit_size: 1 + - name: SEC2BB23 + description: page secure/non-secure attribution + bit_offset: 23 + bit_size: 1 + - name: SEC2BB24 + description: page secure/non-secure attribution + bit_offset: 24 + bit_size: 1 + - name: SEC2BB25 + description: page secure/non-secure attribution + bit_offset: 25 + bit_size: 1 + - name: SEC2BB26 + description: page secure/non-secure attribution + bit_offset: 26 + bit_size: 1 + - name: SEC2BB27 + description: page secure/non-secure attribution + bit_offset: 27 + bit_size: 1 + - name: SEC2BB28 + description: page secure/non-secure attribution + bit_offset: 28 + bit_size: 1 + - name: SEC2BB29 + description: page secure/non-secure attribution + bit_offset: 29 + bit_size: 1 + - name: SEC2BB30 + description: page secure/non-secure attribution + bit_offset: 30 + bit_size: 1 + - name: SEC2BB31 + description: page secure/non-secure attribution + bit_offset: 31 + bit_size: 1 fieldset/SECBOOTADD0R: description: FLASH secure boot address 0 register fields: - - name: BOOT_LOCK - description: "Boot lock\r When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP at level 0." - bit_offset: 0 - bit_size: 1 - - name: SECBOOTADD0 - description: "Secure boot base address 0\r The secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state.\r Examples:\r SECBOOTADD0[24:0] = 0x018 0000: Boot from secure Flash memory (0x0C00 0000)\r SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS (0x0FF8 0000)\r SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000)" - bit_offset: 7 - bit_size: 25 + - name: BOOT_LOCK + description: "Boot lock\r When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP at level 0." + bit_offset: 0 + bit_size: 1 + - name: SECBOOTADD0 + description: "Secure boot base address 0\r The secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state.\r Examples:\r SECBOOTADD0[24:0] = 0x018 0000: Boot from secure Flash memory (0x0C00 0000)\r SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS (0x0FF8 0000)\r SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000)" + bit_offset: 7 + bit_size: 25 fieldset/SECCR: description: FLASH secure control register fields: - - name: PG - description: Secure programming - bit_offset: 0 - bit_size: 1 - enum: SECCR_PG - - name: PER - description: Secure page erase - bit_offset: 1 - bit_size: 1 - enum: SECCR_PER - - name: MER1 - description: "Secure bank 1 mass erase\r This bit triggers the bank 1 secure mass erase (all bank 1 user pages) when set." - bit_offset: 2 - bit_size: 1 - - name: PNB - description: "Secure page number selection\r These bits select the page to erase:\r ..." - bit_offset: 3 - bit_size: 7 - - name: BKER - description: Secure bank selection for page erase - bit_offset: 11 - bit_size: 1 - enum: SECCR_BKER - - name: BWR - description: "Secure burst write programming mode\r When set, this bit selects the burst write programming mode." - bit_offset: 14 - bit_size: 1 - - name: MER2 - description: "Secure bank 2 mass erase\r This bit triggers the bank 2 secure mass erase (all bank 2 user pages) when set." - bit_offset: 15 - bit_size: 1 - - name: STRT - description: "Secure start\r This bit triggers a secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR in the FLASH_SECSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_SECSR." - bit_offset: 16 - bit_size: 1 - - name: EOPIE - description: "Secure End of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in the FLASH_SECSR is set to 1." - bit_offset: 24 - bit_size: 1 - enum: SECCR_EOPIE - - name: ERRIE - description: Secure error interrupt enable - bit_offset: 25 - bit_size: 1 - enum: SECCR_ERRIE - - name: RDERRIE - description: Secure PCROP read error interrupt enable - bit_offset: 26 - bit_size: 1 - - name: INV - description: "Flash memory security state invert\r This bit inverts the Flash memory security state." - bit_offset: 29 - bit_size: 1 - - name: LOCK - description: "Secure lock\r This bit is set only. When set, the FLASH_SECCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_SECKEYR register.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset." - bit_offset: 31 - bit_size: 1 + - name: PG + description: Secure programming + bit_offset: 0 + bit_size: 1 + enum: SECCR_PG + - name: PER + description: Secure page erase + bit_offset: 1 + bit_size: 1 + enum: SECCR_PER + - name: MER1 + description: "Secure bank 1 mass erase\r This bit triggers the bank 1 secure mass erase (all bank 1 user pages) when set." + bit_offset: 2 + bit_size: 1 + - name: PNB + description: "Secure page number selection\r These bits select the page to erase:\r ..." + bit_offset: 3 + bit_size: 7 + - name: BKER + description: Secure bank selection for page erase + bit_offset: 11 + bit_size: 1 + enum: SECCR_BKER + - name: BWR + description: "Secure burst write programming mode\r When set, this bit selects the burst write programming mode." + bit_offset: 14 + bit_size: 1 + - name: MER2 + description: "Secure bank 2 mass erase\r This bit triggers the bank 2 secure mass erase (all bank 2 user pages) when set." + bit_offset: 15 + bit_size: 1 + - name: STRT + description: "Secure start\r This bit triggers a secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR in the FLASH_SECSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_SECSR." + bit_offset: 16 + bit_size: 1 + - name: EOPIE + description: "Secure End of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in the FLASH_SECSR is set to 1." + bit_offset: 24 + bit_size: 1 + enum: SECCR_EOPIE + - name: ERRIE + description: Secure error interrupt enable + bit_offset: 25 + bit_size: 1 + enum: SECCR_ERRIE + - name: RDERRIE + description: Secure PCROP read error interrupt enable + bit_offset: 26 + bit_size: 1 + - name: INV + description: "Flash memory security state invert\r This bit inverts the Flash memory security state." + bit_offset: 29 + bit_size: 1 + - name: LOCK + description: "Secure lock\r This bit is set only. When set, the FLASH_SECCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_SECKEYR register.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset." + bit_offset: 31 + bit_size: 1 fieldset/SECHDPCR: description: FLASH secure HDP control register fields: - - name: HDP1_ACCDIS - description: "HDP1 area access disable\r When set, this bit is only cleared by a system reset." - bit_offset: 0 - bit_size: 1 - enum: HDP_ACCDIS - - name: HDP2_ACCDIS - description: "HDP2 area access disable\r When set, this bit is only cleared by a system reset." - bit_offset: 1 - bit_size: 1 - enum: HDP_ACCDIS + - name: HDP1_ACCDIS + description: "HDP1 area access disable\r When set, this bit is only cleared by a system reset." + bit_offset: 0 + bit_size: 1 + enum: HDP_ACCDIS + - name: HDP2_ACCDIS + description: "HDP2 area access disable\r When set, this bit is only cleared by a system reset." + bit_offset: 1 + bit_size: 1 + enum: HDP_ACCDIS fieldset/SECKEYR: description: FLASH secure key register fields: - - name: SECKEY - description: Flash memory secure key - bit_offset: 0 - bit_size: 32 + - name: SECKEY + description: Flash memory secure key + bit_offset: 0 + bit_size: 32 fieldset/SECSR: description: FLASH secure status register fields: - - name: EOP - description: "Secure end of operation\r This bit is set by hardware when one or more Flash memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_SECCR). This bit is cleared by writing 1." - bit_offset: 0 - bit_size: 1 - - name: OPERR - description: "Secure operation error\r This bit is set by hardware when a Flash memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1." - bit_offset: 1 - bit_size: 1 - - name: PROGERR - description: "Secure programming error\r This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1." - bit_offset: 3 - bit_size: 1 - - name: WRPERR - description: "Secure write protection error\r This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP, PCROP, HDP or RDP level 1) of the Flash memory.This bit is cleared by writing 1.\r Refer to for full conditions of error flag setting." - bit_offset: 4 - bit_size: 1 - - name: PGAERR - description: "Secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1." - bit_offset: 5 - bit_size: 1 - - name: SIZERR - description: "Secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1." - bit_offset: 6 - bit_size: 1 - - name: PGSERR - description: "Secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to for full conditions of error flag setting." - bit_offset: 7 - bit_size: 1 - - name: BSY - description: "Secure busy\r This bit indicates that a Flash memory secure or non-secure operation is in progress. This is set on the beginning of a Flash operation and reset when the operation finishes or when an error occurs." - bit_offset: 16 - bit_size: 1 - - name: WDW - description: "Secure wait data to write\r This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory." - bit_offset: 17 - bit_size: 1 + - name: EOP + description: "Secure end of operation\r This bit is set by hardware when one or more Flash memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_SECCR). This bit is cleared by writing 1." + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: "Secure operation error\r This bit is set by hardware when a Flash memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1." + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: "Secure programming error\r This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1." + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: "Secure write protection error\r This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP, PCROP, HDP or RDP level 1) of the Flash memory.This bit is cleared by writing 1.\r Refer to for full conditions of error flag setting." + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: "Secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1." + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: "Secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1." + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: "Secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to for full conditions of error flag setting." + bit_offset: 7 + bit_size: 1 + - name: BSY + description: "Secure busy\r This bit indicates that a Flash memory secure or non-secure operation is in progress. This is set on the beginning of a Flash operation and reset when the operation finishes or when an error occurs." + bit_offset: 16 + bit_size: 1 + - name: WDW + description: "Secure wait data to write\r This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory." + bit_offset: 17 + bit_size: 1 fieldset/SECWM1R1: description: FLASH secure watermark1 register 1 fields: - - name: SECWM1_PSTRT - description: "Start page of first secure area\r This field contains the first page of the secure area in bank 1." - bit_offset: 0 - bit_size: 7 - - name: SECWM1_PEND - description: "End page of first secure area\r This field contains the last page of the secure area in bank 1." - bit_offset: 16 - bit_size: 7 + - name: SECWM1_PSTRT + description: "Start page of first secure area\r This field contains the first page of the secure area in bank 1." + bit_offset: 0 + bit_size: 7 + - name: SECWM1_PEND + description: "End page of first secure area\r This field contains the last page of the secure area in bank 1." + bit_offset: 16 + bit_size: 7 fieldset/SECWM1R2: description: FLASH secure watermark1 register 2 fields: - - name: HDP1_PEND - description: "End page of first hide protection area\r This field contains the last page of the HDP area in bank 1." - bit_offset: 16 - bit_size: 7 - - name: HDP1EN - description: Hide protection first area enable - bit_offset: 31 - bit_size: 1 + - name: HDP1_PEND + description: "End page of first hide protection area\r This field contains the last page of the HDP area in bank 1." + bit_offset: 16 + bit_size: 7 + - name: HDP1EN + description: Hide protection first area enable + bit_offset: 31 + bit_size: 1 fieldset/SECWM2R1: description: FLASH secure watermark2 register 1 fields: - - name: SECWM2_PSTRT - description: "Start page of second secure area\r This field contains the first page of the secure area in bank 2." - bit_offset: 0 - bit_size: 7 - - name: SECWM2_PEND - description: "End page of second secure area\r This field contains the last page of the secure area in bank 2." - bit_offset: 16 - bit_size: 7 + - name: SECWM2_PSTRT + description: "Start page of second secure area\r This field contains the first page of the secure area in bank 2." + bit_offset: 0 + bit_size: 7 + - name: SECWM2_PEND + description: "End page of second secure area\r This field contains the last page of the secure area in bank 2." + bit_offset: 16 + bit_size: 7 fieldset/SECWM2R2: description: FLASH secure watermark2 register 2 fields: - - name: HDP2_PEND - description: "End page of hide protection second area\r HDP2_PEND contains the last page of the HDP area in bank 2." - bit_offset: 16 - bit_size: 7 - - name: HDP2EN - description: Hide protection second area enable - bit_offset: 31 - bit_size: 1 + - name: HDP2_PEND + description: "End page of hide protection second area\r HDP2_PEND contains the last page of the HDP area in bank 2." + bit_offset: 16 + bit_size: 7 + - name: HDP2EN + description: Hide protection second area enable + bit_offset: 31 + bit_size: 1 fieldset/WRP1AR: description: FLASH WRP1 area A address register fields: - - name: WRP1A_PSTRT - description: "bank 1 WPR first area A start page\r This field contains the first page of the first WPR area for bank 1." - bit_offset: 0 - bit_size: 7 - - name: WRP1A_PEND - description: "Bank 1 WPR first area A end page\r This field contains the last page of the first WPR area in bank 1." - bit_offset: 16 - bit_size: 7 - - name: UNLOCK - description: Bank 1 WPR first area A unlock - bit_offset: 31 - bit_size: 1 - enum: WRPAR_UNLOCK + - name: WRP1A_PSTRT + description: "bank 1 WPR first area A start page\r This field contains the first page of the first WPR area for bank 1." + bit_offset: 0 + bit_size: 7 + - name: WRP1A_PEND + description: "Bank 1 WPR first area A end page\r This field contains the last page of the first WPR area in bank 1." + bit_offset: 16 + bit_size: 7 + - name: UNLOCK + description: Bank 1 WPR first area A unlock + bit_offset: 31 + bit_size: 1 + enum: WRPAR_UNLOCK fieldset/WRP1BR: description: FLASH WRP1 area B address register fields: - - name: WRP1B_PSTRT - description: "Bank 1 WRP second area B start page\r This field contains the first page of the second WRP area for bank 1." - bit_offset: 0 - bit_size: 7 - - name: WRP1B_PEND - description: "Bank 1 WRP second area B end page\r This field contains the last page of the second WRP area in bank 1." - bit_offset: 16 - bit_size: 7 - - name: UNLOCK - description: Bank 1 WPR second area B unlock - bit_offset: 31 - bit_size: 1 - enum: WRPBR_UNLOCK + - name: WRP1B_PSTRT + description: "Bank 1 WRP second area B start page\r This field contains the first page of the second WRP area for bank 1." + bit_offset: 0 + bit_size: 7 + - name: WRP1B_PEND + description: "Bank 1 WRP second area B end page\r This field contains the last page of the second WRP area in bank 1." + bit_offset: 16 + bit_size: 7 + - name: UNLOCK + description: Bank 1 WPR second area B unlock + bit_offset: 31 + bit_size: 1 + enum: WRPBR_UNLOCK fieldset/WRP2AR: description: FLASH WPR2 area A address register fields: - - name: WRP2A_PSTRT - description: "Bank 2 WPR first area A start page\r This field contains the first page of the first WRP area for bank 2." - bit_offset: 0 - bit_size: 7 - - name: WRP2A_PEND - description: "Bank 2 WPR first area A end page\r This field contains the last page of the first WRP area in bank 2." - bit_offset: 16 - bit_size: 7 - - name: UNLOCK - description: Bank 2 WPR first area A unlock - bit_offset: 31 - bit_size: 1 - enum: WRPAR_UNLOCK + - name: WRP2A_PSTRT + description: "Bank 2 WPR first area A start page\r This field contains the first page of the first WRP area for bank 2." + bit_offset: 0 + bit_size: 7 + - name: WRP2A_PEND + description: "Bank 2 WPR first area A end page\r This field contains the last page of the first WRP area in bank 2." + bit_offset: 16 + bit_size: 7 + - name: UNLOCK + description: Bank 2 WPR first area A unlock + bit_offset: 31 + bit_size: 1 + enum: WRPAR_UNLOCK fieldset/WRP2BR: description: FLASH WPR2 area B address register fields: - - name: WRP2B_PSTRT - description: "Bank 2 WPR second area B start page\r This field contains the first page of the second WRP area for bank 2." - bit_offset: 0 - bit_size: 7 - - name: WRP2B_PEND - description: "Bank 2 WPR second area B end page\r This field contains the last page of the second WRP area in bank 2." - bit_offset: 16 - bit_size: 7 - - name: UNLOCK - description: Bank 2 WPR second area B unlock - bit_offset: 31 - bit_size: 1 - enum: WRPBR_UNLOCK + - name: WRP2B_PSTRT + description: "Bank 2 WPR second area B start page\r This field contains the first page of the second WRP area for bank 2." + bit_offset: 0 + bit_size: 7 + - name: WRP2B_PEND + description: "Bank 2 WPR second area B end page\r This field contains the last page of the second WRP area in bank 2." + bit_offset: 16 + bit_size: 7 + - name: UNLOCK + description: Bank 2 WPR second area B unlock + bit_offset: 31 + bit_size: 1 + enum: WRPBR_UNLOCK enum/BKPSRAM_ECC: bit_size: 1 variants: - - name: B_0x0 - description: Backup RAM ECC check enabled - value: 0 - - name: B_0x1 - description: Backup RAM ECC check disabled - value: 1 + - name: B_0x0 + description: Backup RAM ECC check enabled + value: 0 + - name: B_0x1 + description: Backup RAM ECC check disabled + value: 1 enum/BK_ECC: bit_size: 1 variants: - - name: B_0x0 - description: Bank 1 - value: 0 - - name: B_0x1 - description: Bank 2 - value: 1 + - name: B_0x0 + description: Bank 1 + value: 0 + - name: B_0x1 + description: Bank 2 + value: 1 enum/BK_OP: bit_size: 1 variants: - - name: B_0x0 - description: Bank 1 - value: 0 - - name: B_0x1 - description: Bank 2 - value: 1 + - name: B_0x0 + description: Bank 1 + value: 0 + - name: B_0x1 + description: Bank 2 + value: 1 enum/BOR_LEV: bit_size: 3 variants: - - name: B_0x0 - description: BOR level 0 (reset level threshold around 1.7 V) - value: 0 - - name: B_0x1 - description: BOR level 1 (reset level threshold around 2.0 V) - value: 1 - - name: B_0x2 - description: BOR level 2 (reset level threshold around 2.2 V) - value: 2 - - name: B_0x3 - description: BOR level 3 (reset level threshold around 2.5 V) - value: 3 - - name: B_0x4 - description: BOR level 4 (reset level threshold around 2.8 V) - value: 4 + - name: B_0x0 + description: BOR level 0 (reset level threshold around 1.7 V) + value: 0 + - name: B_0x1 + description: BOR level 1 (reset level threshold around 2.0 V) + value: 1 + - name: B_0x2 + description: BOR level 2 (reset level threshold around 2.2 V) + value: 2 + - name: B_0x3 + description: BOR level 3 (reset level threshold around 2.5 V) + value: 3 + - name: B_0x4 + description: BOR level 4 (reset level threshold around 2.8 V) + value: 4 enum/CODE_OP: bit_size: 3 variants: - - name: B_0x0 - description: No Flash operation interrupted by previous reset - value: 0 - - name: B_0x1 - description: Single write operation interrupted - value: 1 - - name: B_0x2 - description: Burst write operation interrupted - value: 2 - - name: B_0x3 - description: Page erase operation interrupted - value: 3 - - name: B_0x4 - description: Bank erase operation interrupted - value: 4 - - name: B_0x5 - description: Mass erase operation interrupted - value: 5 - - name: B_0x6 - description: Option change operation interrupted - value: 6 + - name: B_0x0 + description: No Flash operation interrupted by previous reset + value: 0 + - name: B_0x1 + description: Single write operation interrupted + value: 1 + - name: B_0x2 + description: Burst write operation interrupted + value: 2 + - name: B_0x3 + description: Page erase operation interrupted + value: 3 + - name: B_0x4 + description: Bank erase operation interrupted + value: 4 + - name: B_0x5 + description: Mass erase operation interrupted + value: 5 + - name: B_0x6 + description: Option change operation interrupted + value: 6 enum/DUALBANK: bit_size: 1 variants: - - name: B_0x0 - description: Single bank Flash with contiguous address in bank 1 - value: 0 - - name: B_0x1 - description: Dual-bank Flash with contiguous addresses - value: 1 + - name: B_0x0 + description: Single bank Flash with contiguous address in bank 1 + value: 0 + - name: B_0x1 + description: Dual-bank Flash with contiguous addresses + value: 1 enum/ECCIE: bit_size: 1 variants: - - name: B_0x0 - description: ECCC interrupt disabled - value: 0 - - name: B_0x1 - description: ECCC interrupt enabled. - value: 1 + - name: B_0x0 + description: ECCC interrupt disabled + value: 0 + - name: B_0x1 + description: ECCC interrupt enabled. + value: 1 enum/HDP_ACCDIS: bit_size: 1 variants: - - name: B_0x0 - description: Access to HDP2 area granted - value: 0 - - name: B_0x1 - description: Access to HDP2 area denied (SECWM2Ry option bytes modification bocked -refer to ) - value: 1 + - name: B_0x0 + description: Access to HDP2 area granted + value: 0 + - name: B_0x1 + description: Access to HDP2 area denied (SECWM2Ry option bytes modification bocked -refer to ) + value: 1 enum/IO_VDDIO_HSLV: bit_size: 1 variants: - - name: B_0x0 - description: High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) - value: 0 - - name: B_0x1 - description: High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - value: 1 + - name: B_0x0 + description: High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) + value: 0 + - name: B_0x1 + description: High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) + value: 1 enum/IO_VDD_HSLV: bit_size: 1 variants: - - name: B_0x0 - description: High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) - value: 0 - - name: B_0x1 - description: High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) - value: 1 + - name: B_0x0 + description: High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) + value: 0 + - name: B_0x1 + description: High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) + value: 1 enum/IWDG_STDBY: bit_size: 1 variants: - - name: B_0x0 - description: Independent watchdog counter frozen in Standby mode - value: 0 - - name: B_0x1 - description: Independent watchdog counter running in Standby mode - value: 1 + - name: B_0x0 + description: Independent watchdog counter frozen in Standby mode + value: 0 + - name: B_0x1 + description: Independent watchdog counter running in Standby mode + value: 1 enum/IWDG_STOP: bit_size: 1 variants: - - name: B_0x0 - description: Independent watchdog counter frozen in Stop mode - value: 0 - - name: B_0x1 - description: Independent watchdog counter running in Stop mode - value: 1 + - name: B_0x0 + description: Independent watchdog counter frozen in Stop mode + value: 0 + - name: B_0x1 + description: Independent watchdog counter running in Stop mode + value: 1 enum/IWDG_SW: bit_size: 1 variants: - - name: B_0x0 - description: Hardware independent watchdog selected - value: 0 - - name: B_0x1 - description: Software independent watchdog selected - value: 1 + - name: B_0x0 + description: Hardware independent watchdog selected + value: 0 + - name: B_0x1 + description: Software independent watchdog selected + value: 1 enum/LPM: bit_size: 1 variants: - - name: B_0x0 - description: Flash not in low-power read mode - value: 0 - - name: B_0x1 - description: Flash in low-power read mode - value: 1 + - name: B_0x0 + description: Flash not in low-power read mode + value: 0 + - name: B_0x1 + description: Flash in low-power read mode + value: 1 enum/NSCR_BKER: bit_size: 1 variants: - - name: B_0x0 - description: Bank 1 selected for non-secure page erase - value: 0 - - name: B_0x1 - description: Bank 2 selected for non-secure page erase - value: 1 + - name: B_0x0 + description: Bank 1 selected for non-secure page erase + value: 0 + - name: B_0x1 + description: Bank 2 selected for non-secure page erase + value: 1 enum/NSCR_EOPIE: bit_size: 1 variants: - - name: B_0x0 - description: Non-secure EOP Interrupt disabled - value: 0 - - name: B_0x1 - description: Non-secure EOP Interrupt enabled - value: 1 + - name: B_0x0 + description: Non-secure EOP Interrupt disabled + value: 0 + - name: B_0x1 + description: Non-secure EOP Interrupt enabled + value: 1 enum/NSCR_ERRIE: bit_size: 1 variants: - - name: B_0x0 - description: Non-secure OPERR error interrupt disabled - value: 0 - - name: B_0x1 - description: Non-secure OPERR error interrupt enabled - value: 1 + - name: B_0x0 + description: Non-secure OPERR error interrupt disabled + value: 0 + - name: B_0x1 + description: Non-secure OPERR error interrupt enabled + value: 1 enum/NSCR_PER: bit_size: 1 variants: - - name: B_0x0 - description: Non-secure page erase disabled - value: 0 - - name: B_0x1 - description: Non-secure page erase enabled - value: 1 + - name: B_0x0 + description: Non-secure page erase disabled + value: 0 + - name: B_0x1 + description: Non-secure page erase enabled + value: 1 enum/NSCR_PG: bit_size: 1 variants: - - name: B_0x0 - description: Non-secure Flash programming disabled - value: 0 - - name: B_0x1 - description: Non-secure Flash programming enabled - value: 1 + - name: B_0x0 + description: Non-secure Flash programming disabled + value: 0 + - name: B_0x1 + description: Non-secure Flash programming enabled + value: 1 enum/NSPRIV: bit_size: 1 variants: - - name: B_0x0 - description: Non-secure Flash registers can be read and written by privileged or unprivileged access. - value: 0 - - name: B_0x1 - description: Non-secure Flash registers can be read and written by privileged access only. - value: 1 + - name: B_0x0 + description: Non-secure Flash registers can be read and written by privileged or unprivileged access. + value: 0 + - name: B_0x1 + description: Non-secure Flash registers can be read and written by privileged access only. + value: 1 enum/OBL_LAUNCH: bit_size: 1 variants: - - name: B_0x0 - description: Option byte loading complete - value: 0 - - name: B_0x1 - description: Option byte loading requested - value: 1 + - name: B_0x0 + description: Option byte loading complete + value: 0 + - name: B_0x1 + description: Option byte loading requested + value: 1 enum/PDREQ: bit_size: 1 variants: - - name: B_0x0 - description: No request for bank 2 to enter power-down mode - value: 0 - - name: B_0x1 - description: Bank 2 requested to enter power-down mode - value: 1 + - name: B_0x0 + description: No request for bank 2 to enter power-down mode + value: 0 + - name: B_0x1 + description: Bank 2 requested to enter power-down mode + value: 1 enum/RDP: bit_size: 8 variants: - - name: B_0x55 - description: "Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1)" - value: 85 - - name: B_0xAA - description: Level 0 (readout protection not active) - value: 170 - - name: B_0xCC - description: Level 2 (chip readout protection active) - value: 204 + - name: B_0x55 + description: Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1) + value: 85 + - name: B_0xAA + description: Level 0 (readout protection not active) + value: 170 + - name: B_0xCC + description: Level 2 (chip readout protection active) + value: 204 enum/SECCR_BKER: bit_size: 1 variants: - - name: B_0x0 - description: Bank 1 selected for secure page erase - value: 0 - - name: B_0x1 - description: Bank 2 selected for secure page erase - value: 1 + - name: B_0x0 + description: Bank 1 selected for secure page erase + value: 0 + - name: B_0x1 + description: Bank 2 selected for secure page erase + value: 1 enum/SECCR_EOPIE: bit_size: 1 variants: - - name: B_0x0 - description: Secure EOP Interrupt disabled - value: 0 - - name: B_0x1 - description: Secure EOP Interrupt enabled - value: 1 + - name: B_0x0 + description: Secure EOP Interrupt disabled + value: 0 + - name: B_0x1 + description: Secure EOP Interrupt enabled + value: 1 enum/SECCR_ERRIE: bit_size: 1 variants: - - name: B_0x0 - description: Secure OPERR error interrupt disabled - value: 0 - - name: B_0x1 - description: Secure OPERR error interrupt enabled - value: 1 + - name: B_0x0 + description: Secure OPERR error interrupt disabled + value: 0 + - name: B_0x1 + description: Secure OPERR error interrupt enabled + value: 1 enum/SECCR_PER: bit_size: 1 variants: - - name: B_0x0 - description: Secure page erase disabled - value: 0 - - name: B_0x1 - description: Secure page erase enabled - value: 1 + - name: B_0x0 + description: Secure page erase disabled + value: 0 + - name: B_0x1 + description: Secure page erase enabled + value: 1 enum/SECCR_PG: bit_size: 1 variants: - - name: B_0x0 - description: Secure Flash programming disabled - value: 0 - - name: B_0x1 - description: Secure Flash programming enabled - value: 1 + - name: B_0x0 + description: Secure Flash programming disabled + value: 0 + - name: B_0x1 + description: Secure Flash programming enabled + value: 1 enum/SLEEP_PD: bit_size: 1 variants: - - name: B_0x0 - description: Flash in Idle mode during Sleep mode - value: 0 - - name: B_0x1 - description: Flash in power-down mode during Sleep mode - value: 1 + - name: B_0x0 + description: Flash in Idle mode during Sleep mode + value: 0 + - name: B_0x1 + description: Flash in power-down mode during Sleep mode + value: 1 enum/SPRIV: bit_size: 1 variants: - - name: B_0x0 - description: Secure Flash registers can be read and written by privileged or unprivileged access. - value: 0 - - name: B_0x1 - description: Secure Flash registers can be read and written by privileged access only. - value: 1 + - name: B_0x0 + description: Secure Flash registers can be read and written by privileged or unprivileged access. + value: 0 + - name: B_0x1 + description: Secure Flash registers can be read and written by privileged access only. + value: 1 enum/SRAM_ECC: bit_size: 1 variants: - - name: B_0x0 - description: SRAM3 ECC check enabled - value: 0 - - name: B_0x1 - description: SRAM3 ECC check disabled - value: 1 + - name: B_0x0 + description: SRAM3 ECC check enabled + value: 0 + - name: B_0x1 + description: SRAM3 ECC check disabled + value: 1 enum/SWAP_BANK: bit_size: 1 variants: - - name: B_0x0 - description: Bank 1 and bank 2 addresses not swapped - value: 0 - - name: B_0x1 - description: Bank 1 and bank 2 addresses swapped - value: 1 + - name: B_0x0 + description: Bank 1 and bank 2 addresses not swapped + value: 0 + - name: B_0x1 + description: Bank 1 and bank 2 addresses swapped + value: 1 enum/WRPAR_UNLOCK: bit_size: 1 variants: - - name: B_0x0 - description: WRP2A start and end pages locked - value: 0 - - name: B_0x1 - description: WRP2A start and end pages unlocked - value: 1 + - name: B_0x0 + description: WRP2A start and end pages locked + value: 0 + - name: B_0x1 + description: WRP2A start and end pages unlocked + value: 1 enum/WRPBR_UNLOCK: bit_size: 1 variants: - - name: B_0x0 - description: WRP2B start and end pages locked - value: 0 - - name: B_0x1 - description: WRP2B start and end pages unlocked - value: 1 + - name: B_0x0 + description: WRP2B start and end pages locked + value: 0 + - name: B_0x1 + description: WRP2B start and end pages unlocked + value: 1 enum/WWDG_SW: bit_size: 1 variants: - - name: B_0x0 - description: Hardware window watchdog selected - value: 0 - - name: B_0x1 - description: Software window watchdog selected - value: 1 + - name: B_0x0 + description: Hardware window watchdog selected + value: 0 + - name: B_0x1 + description: Software window watchdog selected + value: 1 enum/nBOOT: bit_size: 1 variants: - - name: B_0x0 - description: nBOOT0 = 0 - value: 0 - - name: B_0x1 - description: nBOOT0 = 1 - value: 1 + - name: B_0x0 + description: nBOOT0 = 0 + value: 0 + - name: B_0x1 + description: nBOOT0 = 1 + value: 1 enum/nRST_SHDW: bit_size: 1 variants: - - name: B_0x0 - description: Reset generated when entering the Shutdown mode - value: 0 - - name: B_0x1 - description: No reset generated when entering the Shutdown mode - value: 1 + - name: B_0x0 + description: Reset generated when entering the Shutdown mode + value: 0 + - name: B_0x1 + description: No reset generated when entering the Shutdown mode + value: 1 enum/nRST_STDBY: bit_size: 1 variants: - - name: B_0x0 - description: Reset generated when entering the Standby mode - value: 0 - - name: B_0x1 - description: No reset generate when entering the Standby mode - value: 1 + - name: B_0x0 + description: Reset generated when entering the Standby mode + value: 0 + - name: B_0x1 + description: No reset generate when entering the Standby mode + value: 1 enum/nRST_STOP: bit_size: 1 variants: - - name: B_0x0 - description: Reset generated when entering the Stop mode - value: 0 - - name: B_0x1 - description: No reset generated when entering the Stop mode - value: 1 + - name: B_0x0 + description: Reset generated when entering the Stop mode + value: 0 + - name: B_0x1 + description: No reset generated when entering the Stop mode + value: 1 enum/nSWBOOT: bit_size: 1 variants: - - name: B_0x0 - description: BOOT0 taken from the option bit nBOOT0 - value: 0 - - name: B_0x1 - description: BOOT0 taken from PH3/BOOT0 pin - value: 1 + - name: B_0x0 + description: BOOT0 taken from the option bit nBOOT0 + value: 0 + - name: B_0x1 + description: BOOT0 taken from PH3/BOOT0 pin + value: 1 diff --git a/data/registers/flash_wb.yaml b/data/registers/flash_wb.yaml index da253b4..1d98476 100644 --- a/data/registers/flash_wb.yaml +++ b/data/registers/flash_wb.yaml @@ -1,559 +1,558 @@ ---- block/FLASH: description: Flash items: - - name: ACR - description: Access control register - byte_offset: 0 - fieldset: ACR - - name: KEYR - description: Flash key register - byte_offset: 8 - access: Write - fieldset: KEYR - - name: OPTKEYR - description: Option byte key register - byte_offset: 12 - access: Write - fieldset: OPTKEYR - - name: SR - description: Status register - byte_offset: 16 - fieldset: SR - - name: CR - description: Flash control register - byte_offset: 20 - fieldset: CR - - name: ECCR - description: Flash ECC register - byte_offset: 24 - fieldset: ECCR - - name: OPTR - description: Flash option register - byte_offset: 32 - fieldset: OPTR - - name: PCROP1ASR - description: Flash Bank 1 PCROP Start address zone A register - byte_offset: 36 - fieldset: PCROP1ASR - - name: PCROP1AER - description: Flash Bank 1 PCROP End address zone A register - byte_offset: 40 - fieldset: PCROP1AER - - name: WRP1AR - description: Flash Bank 1 WRP area A address register - byte_offset: 44 - fieldset: WRP1AR - - name: WRP1BR - description: Flash Bank 1 WRP area B address register - byte_offset: 48 - fieldset: WRP1BR - - name: PCROP1BSR - description: Flash Bank 1 PCROP Start address area B register - byte_offset: 52 - fieldset: PCROP1BSR - - name: PCROP1BER - description: Flash Bank 1 PCROP End address area B register - byte_offset: 56 - fieldset: PCROP1BER - - name: IPCCBR - description: IPCC mailbox data buffer address register - byte_offset: 60 - fieldset: IPCCBR - - name: C2ACR - description: CPU2 cortex M0 access control register - byte_offset: 92 - fieldset: C2ACR - - name: C2SR - description: CPU2 cortex M0 status register - byte_offset: 96 - fieldset: C2SR - - name: C2CR - description: CPU2 cortex M0 control register - byte_offset: 100 - fieldset: C2CR - - name: SFR - description: Secure flash start address register - byte_offset: 128 - fieldset: SFR - - name: SRRVR - description: Secure SRAM2 start address and cortex M0 reset vector register - byte_offset: 132 - fieldset: SRRVR + - name: ACR + description: Access control register + byte_offset: 0 + fieldset: ACR + - name: KEYR + description: Flash key register + byte_offset: 8 + access: Write + fieldset: KEYR + - name: OPTKEYR + description: Option byte key register + byte_offset: 12 + access: Write + fieldset: OPTKEYR + - name: SR + description: Status register + byte_offset: 16 + fieldset: SR + - name: CR + description: Flash control register + byte_offset: 20 + fieldset: CR + - name: ECCR + description: Flash ECC register + byte_offset: 24 + fieldset: ECCR + - name: OPTR + description: Flash option register + byte_offset: 32 + fieldset: OPTR + - name: PCROP1ASR + description: Flash Bank 1 PCROP Start address zone A register + byte_offset: 36 + fieldset: PCROP1ASR + - name: PCROP1AER + description: Flash Bank 1 PCROP End address zone A register + byte_offset: 40 + fieldset: PCROP1AER + - name: WRP1AR + description: Flash Bank 1 WRP area A address register + byte_offset: 44 + fieldset: WRP1AR + - name: WRP1BR + description: Flash Bank 1 WRP area B address register + byte_offset: 48 + fieldset: WRP1BR + - name: PCROP1BSR + description: Flash Bank 1 PCROP Start address area B register + byte_offset: 52 + fieldset: PCROP1BSR + - name: PCROP1BER + description: Flash Bank 1 PCROP End address area B register + byte_offset: 56 + fieldset: PCROP1BER + - name: IPCCBR + description: IPCC mailbox data buffer address register + byte_offset: 60 + fieldset: IPCCBR + - name: C2ACR + description: CPU2 cortex M0 access control register + byte_offset: 92 + fieldset: C2ACR + - name: C2SR + description: CPU2 cortex M0 status register + byte_offset: 96 + fieldset: C2SR + - name: C2CR + description: CPU2 cortex M0 control register + byte_offset: 100 + fieldset: C2CR + - name: SFR + description: Secure flash start address register + byte_offset: 128 + fieldset: SFR + - name: SRRVR + description: Secure SRAM2 start address and cortex M0 reset vector register + byte_offset: 132 + fieldset: SRRVR fieldset/ACR: description: Access control register fields: - - name: LATENCY - description: Latency - bit_offset: 0 - bit_size: 3 - - name: PRFTEN - description: Prefetch enable - bit_offset: 8 - bit_size: 1 - - name: ICEN - description: Instruction cache enable - bit_offset: 9 - bit_size: 1 - - name: DCEN - description: Data cache enable - bit_offset: 10 - bit_size: 1 - - name: ICRST - description: Instruction cache reset - bit_offset: 11 - bit_size: 1 - - name: DCRST - description: Data cache reset - bit_offset: 12 - bit_size: 1 - - name: PES - description: CPU1 CortexM4 program erase suspend request - bit_offset: 15 - bit_size: 1 - - name: EMPTY - description: Flash User area empty - bit_offset: 16 - bit_size: 1 + - name: LATENCY + description: Latency + bit_offset: 0 + bit_size: 3 + - name: PRFTEN + description: Prefetch enable + bit_offset: 8 + bit_size: 1 + - name: ICEN + description: Instruction cache enable + bit_offset: 9 + bit_size: 1 + - name: DCEN + description: Data cache enable + bit_offset: 10 + bit_size: 1 + - name: ICRST + description: Instruction cache reset + bit_offset: 11 + bit_size: 1 + - name: DCRST + description: Data cache reset + bit_offset: 12 + bit_size: 1 + - name: PES + description: CPU1 CortexM4 program erase suspend request + bit_offset: 15 + bit_size: 1 + - name: EMPTY + description: Flash User area empty + bit_offset: 16 + bit_size: 1 fieldset/C2ACR: description: CPU2 cortex M0 access control register fields: - - name: PRFTEN - description: CPU2 cortex M0 prefetch enable - bit_offset: 8 - bit_size: 1 - - name: ICEN - description: CPU2 cortex M0 instruction cache enable - bit_offset: 9 - bit_size: 1 - - name: ICRST - description: CPU2 cortex M0 instruction cache reset - bit_offset: 11 - bit_size: 1 - - name: PES - description: CPU2 cortex M0 program erase suspend request - bit_offset: 15 - bit_size: 1 + - name: PRFTEN + description: CPU2 cortex M0 prefetch enable + bit_offset: 8 + bit_size: 1 + - name: ICEN + description: CPU2 cortex M0 instruction cache enable + bit_offset: 9 + bit_size: 1 + - name: ICRST + description: CPU2 cortex M0 instruction cache reset + bit_offset: 11 + bit_size: 1 + - name: PES + description: CPU2 cortex M0 program erase suspend request + bit_offset: 15 + bit_size: 1 fieldset/C2CR: description: CPU2 cortex M0 control register fields: - - name: PG - description: Programming - bit_offset: 0 - bit_size: 1 - - name: PER - description: Page erase - bit_offset: 1 - bit_size: 1 - - name: MER - description: Masse erase - bit_offset: 2 - bit_size: 1 - - name: PNB - description: Page Number selection - bit_offset: 3 - bit_size: 8 - - name: STRT - description: Start - bit_offset: 16 - bit_size: 1 - - name: FSTPG - description: Fast programming - bit_offset: 18 - bit_size: 1 - - name: EOPIE - description: End of operation interrupt enable - bit_offset: 24 - bit_size: 1 - - name: ERRIE - description: Error interrupt enable - bit_offset: 25 - bit_size: 1 - - name: RDERRIE - description: PCROP read error interrupt enable - bit_offset: 26 - bit_size: 1 + - name: PG + description: Programming + bit_offset: 0 + bit_size: 1 + - name: PER + description: Page erase + bit_offset: 1 + bit_size: 1 + - name: MER + description: Masse erase + bit_offset: 2 + bit_size: 1 + - name: PNB + description: Page Number selection + bit_offset: 3 + bit_size: 8 + - name: STRT + description: Start + bit_offset: 16 + bit_size: 1 + - name: FSTPG + description: Fast programming + bit_offset: 18 + bit_size: 1 + - name: EOPIE + description: End of operation interrupt enable + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 25 + bit_size: 1 + - name: RDERRIE + description: PCROP read error interrupt enable + bit_offset: 26 + bit_size: 1 fieldset/C2SR: description: CPU2 cortex M0 status register fields: - - name: EOP - description: End of operation - bit_offset: 0 - bit_size: 1 - - name: OPERR - description: Operation error - bit_offset: 1 - bit_size: 1 - - name: PROGERR - description: Programming error - bit_offset: 3 - bit_size: 1 - - name: WRPERR - description: write protection error - bit_offset: 4 - bit_size: 1 - - name: PGAERR - description: Programming alignment error - bit_offset: 5 - bit_size: 1 - - name: SIZERR - description: Size error - bit_offset: 6 - bit_size: 1 - - name: PGSERR - description: Programming sequence error - bit_offset: 7 - bit_size: 1 - - name: MISSERR - description: Fast programming data miss error - bit_offset: 8 - bit_size: 1 - - name: FASTERR - description: Fast programming error - bit_offset: 9 - bit_size: 1 - - name: RDERR - description: PCROP read error - bit_offset: 14 - bit_size: 1 - - name: BSY - description: Busy - bit_offset: 16 - bit_size: 1 - - name: CFGBSY - description: Programming or erase configuration busy - bit_offset: 18 - bit_size: 1 - - name: PESD - description: Programming or erase operation suspended - bit_offset: 19 - bit_size: 1 + - name: EOP + description: End of operation + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: Operation error + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: Programming error + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: write protection error + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: Programming alignment error + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: Size error + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: Programming sequence error + bit_offset: 7 + bit_size: 1 + - name: MISSERR + description: Fast programming data miss error + bit_offset: 8 + bit_size: 1 + - name: FASTERR + description: Fast programming error + bit_offset: 9 + bit_size: 1 + - name: RDERR + description: PCROP read error + bit_offset: 14 + bit_size: 1 + - name: BSY + description: Busy + bit_offset: 16 + bit_size: 1 + - name: CFGBSY + description: Programming or erase configuration busy + bit_offset: 18 + bit_size: 1 + - name: PESD + description: Programming or erase operation suspended + bit_offset: 19 + bit_size: 1 fieldset/CR: description: Flash control register fields: - - name: PG - description: Programming - bit_offset: 0 - bit_size: 1 - - name: PER - description: Page erase - bit_offset: 1 - bit_size: 1 - - name: MER - description: This bit triggers the mass erase (all user pages) when set - bit_offset: 2 - bit_size: 1 - - name: PNB - description: Page number selection - bit_offset: 3 - bit_size: 8 - - name: STRT - description: Start - bit_offset: 16 - bit_size: 1 - - name: OPTSTRT - description: Options modification start - bit_offset: 17 - bit_size: 1 - - name: FSTPG - description: Fast programming - bit_offset: 18 - bit_size: 1 - - name: EOPIE - description: End of operation interrupt enable - bit_offset: 24 - bit_size: 1 - - name: ERRIE - description: Error interrupt enable - bit_offset: 25 - bit_size: 1 - - name: RDERRIE - description: PCROP read error interrupt enable - bit_offset: 26 - bit_size: 1 - - name: OBL_LAUNCH - description: Force the option byte loading - bit_offset: 27 - bit_size: 1 - - name: OPTLOCK - description: Options Lock - bit_offset: 30 - bit_size: 1 - - name: LOCK - description: FLASH_CR Lock - bit_offset: 31 - bit_size: 1 + - name: PG + description: Programming + bit_offset: 0 + bit_size: 1 + - name: PER + description: Page erase + bit_offset: 1 + bit_size: 1 + - name: MER + description: This bit triggers the mass erase (all user pages) when set + bit_offset: 2 + bit_size: 1 + - name: PNB + description: Page number selection + bit_offset: 3 + bit_size: 8 + - name: STRT + description: Start + bit_offset: 16 + bit_size: 1 + - name: OPTSTRT + description: Options modification start + bit_offset: 17 + bit_size: 1 + - name: FSTPG + description: Fast programming + bit_offset: 18 + bit_size: 1 + - name: EOPIE + description: End of operation interrupt enable + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 25 + bit_size: 1 + - name: RDERRIE + description: PCROP read error interrupt enable + bit_offset: 26 + bit_size: 1 + - name: OBL_LAUNCH + description: Force the option byte loading + bit_offset: 27 + bit_size: 1 + - name: OPTLOCK + description: Options Lock + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: FLASH_CR Lock + bit_offset: 31 + bit_size: 1 fieldset/ECCR: description: Flash ECC register fields: - - name: ADDR_ECC - description: ECC fail address - bit_offset: 0 - bit_size: 17 - - name: SYSF_ECC - description: System Flash ECC fail - bit_offset: 20 - bit_size: 1 - - name: ECCCIE - description: ECC correction interrupt enable - bit_offset: 24 - bit_size: 1 - - name: CPUID - description: CPU identification - bit_offset: 26 - bit_size: 3 - - name: ECCC - description: ECC correction - bit_offset: 30 - bit_size: 1 - - name: ECCD - description: ECC detection - bit_offset: 31 - bit_size: 1 + - name: ADDR_ECC + description: ECC fail address + bit_offset: 0 + bit_size: 17 + - name: SYSF_ECC + description: System Flash ECC fail + bit_offset: 20 + bit_size: 1 + - name: ECCCIE + description: ECC correction interrupt enable + bit_offset: 24 + bit_size: 1 + - name: CPUID + description: CPU identification + bit_offset: 26 + bit_size: 3 + - name: ECCC + description: ECC correction + bit_offset: 30 + bit_size: 1 + - name: ECCD + description: ECC detection + bit_offset: 31 + bit_size: 1 fieldset/IPCCBR: description: IPCC mailbox data buffer address register fields: - - name: IPCCDBA - description: PCC mailbox data buffer base address - bit_offset: 0 - bit_size: 14 + - name: IPCCDBA + description: PCC mailbox data buffer base address + bit_offset: 0 + bit_size: 14 fieldset/KEYR: description: Flash key register fields: - - name: KEYR - description: KEYR - bit_offset: 0 - bit_size: 32 + - name: KEYR + description: KEYR + bit_offset: 0 + bit_size: 32 fieldset/OPTKEYR: description: Option byte key register fields: - - name: OPTKEYR - description: Option byte key - bit_offset: 0 - bit_size: 32 + - name: OPTKEYR + description: Option byte key + bit_offset: 0 + bit_size: 32 fieldset/OPTR: description: Flash option register fields: - - name: RDP - description: Read protection level - bit_offset: 0 - bit_size: 8 - - name: ESE - description: Security enabled - bit_offset: 8 - bit_size: 1 - - name: BOR_LEV - description: BOR reset Level - bit_offset: 9 - bit_size: 3 - - name: nRST_STOP - description: nRST_STOP - bit_offset: 12 - bit_size: 1 - - name: nRST_STDBY - description: nRST_STDBY - bit_offset: 13 - bit_size: 1 - - name: nRST_SHDW - description: nRST_SHDW - bit_offset: 14 - bit_size: 1 - - name: IDWG_SW - description: Independent watchdog selection - bit_offset: 16 - bit_size: 1 - - name: IWDG_STOP - description: Independent watchdog counter freeze in Stop mode - bit_offset: 17 - bit_size: 1 - - name: IWDG_STDBY - description: Independent watchdog counter freeze in Standby mode - bit_offset: 18 - bit_size: 1 - - name: WWDG_SW - description: Window watchdog selection - bit_offset: 19 - bit_size: 1 - - name: nBOOT1 - description: Boot configuration - bit_offset: 23 - bit_size: 1 - - name: SRAM2_PE - description: SRAM2 parity check enable - bit_offset: 24 - bit_size: 1 - - name: SRAM2_RST - description: SRAM2 Erase when system reset - bit_offset: 25 - bit_size: 1 - - name: nSWBOOT0 - description: Software Boot0 - bit_offset: 26 - bit_size: 1 - - name: nBOOT0 - description: nBoot0 option bit - bit_offset: 27 - bit_size: 1 - - name: AGC_TRIM - description: Radio Automatic Gain Control Trimming - bit_offset: 29 - bit_size: 3 + - name: RDP + description: Read protection level + bit_offset: 0 + bit_size: 8 + - name: ESE + description: Security enabled + bit_offset: 8 + bit_size: 1 + - name: BOR_LEV + description: BOR reset Level + bit_offset: 9 + bit_size: 3 + - name: nRST_STOP + description: nRST_STOP + bit_offset: 12 + bit_size: 1 + - name: nRST_STDBY + description: nRST_STDBY + bit_offset: 13 + bit_size: 1 + - name: nRST_SHDW + description: nRST_SHDW + bit_offset: 14 + bit_size: 1 + - name: IDWG_SW + description: Independent watchdog selection + bit_offset: 16 + bit_size: 1 + - name: IWDG_STOP + description: Independent watchdog counter freeze in Stop mode + bit_offset: 17 + bit_size: 1 + - name: IWDG_STDBY + description: Independent watchdog counter freeze in Standby mode + bit_offset: 18 + bit_size: 1 + - name: WWDG_SW + description: Window watchdog selection + bit_offset: 19 + bit_size: 1 + - name: nBOOT1 + description: Boot configuration + bit_offset: 23 + bit_size: 1 + - name: SRAM2_PE + description: SRAM2 parity check enable + bit_offset: 24 + bit_size: 1 + - name: SRAM2_RST + description: SRAM2 Erase when system reset + bit_offset: 25 + bit_size: 1 + - name: nSWBOOT0 + description: Software Boot0 + bit_offset: 26 + bit_size: 1 + - name: nBOOT0 + description: nBoot0 option bit + bit_offset: 27 + bit_size: 1 + - name: AGC_TRIM + description: Radio Automatic Gain Control Trimming + bit_offset: 29 + bit_size: 3 fieldset/PCROP1AER: description: Flash Bank 1 PCROP End address zone A register fields: - - name: PCROP1A_END - description: Bank 1 PCROP area end offset - bit_offset: 0 - bit_size: 9 - - name: PCROP_RDP - description: PCROP area preserved when RDP level decreased - bit_offset: 31 - bit_size: 1 + - name: PCROP1A_END + description: Bank 1 PCROP area end offset + bit_offset: 0 + bit_size: 9 + - name: PCROP_RDP + description: PCROP area preserved when RDP level decreased + bit_offset: 31 + bit_size: 1 fieldset/PCROP1ASR: description: Flash Bank 1 PCROP Start address zone A register fields: - - name: PCROP1A_STRT - description: Bank 1 PCROPQ area start offset - bit_offset: 0 - bit_size: 9 + - name: PCROP1A_STRT + description: Bank 1 PCROPQ area start offset + bit_offset: 0 + bit_size: 9 fieldset/PCROP1BER: description: Flash Bank 1 PCROP End address area B register fields: - - name: PCROP1B_END - description: Bank 1 PCROP area end area B offset - bit_offset: 0 - bit_size: 9 + - name: PCROP1B_END + description: Bank 1 PCROP area end area B offset + bit_offset: 0 + bit_size: 9 fieldset/PCROP1BSR: description: Flash Bank 1 PCROP Start address area B register fields: - - name: PCROP1B_STRT - description: Bank 1 PCROP area B start offset - bit_offset: 0 - bit_size: 9 + - name: PCROP1B_STRT + description: Bank 1 PCROP area B start offset + bit_offset: 0 + bit_size: 9 fieldset/SFR: description: Secure flash start address register fields: - - name: SFSA - description: Secure flash start address - bit_offset: 0 - bit_size: 8 - - name: FSD - description: Flash security disable - bit_offset: 8 - bit_size: 1 - - name: DDS - description: Disable Cortex M0 debug access - bit_offset: 12 - bit_size: 1 + - name: SFSA + description: Secure flash start address + bit_offset: 0 + bit_size: 8 + - name: FSD + description: Flash security disable + bit_offset: 8 + bit_size: 1 + - name: DDS + description: Disable Cortex M0 debug access + bit_offset: 12 + bit_size: 1 fieldset/SR: description: Status register fields: - - name: EOP - description: End of operation - bit_offset: 0 - bit_size: 1 - - name: OPERR - description: Operation error - bit_offset: 1 - bit_size: 1 - - name: PROGERR - description: Programming error - bit_offset: 3 - bit_size: 1 - - name: WRPERR - description: Write protected error - bit_offset: 4 - bit_size: 1 - - name: PGAERR - description: Programming alignment error - bit_offset: 5 - bit_size: 1 - - name: SIZERR - description: Size error - bit_offset: 6 - bit_size: 1 - - name: PGSERR - description: Programming sequence error - bit_offset: 7 - bit_size: 1 - - name: MISERR - description: Fast programming data miss error - bit_offset: 8 - bit_size: 1 - - name: FASTERR - description: Fast programming error - bit_offset: 9 - bit_size: 1 - - name: OPTNV - description: User Option OPTVAL indication - bit_offset: 13 - bit_size: 1 - - name: RDERR - description: PCROP read error - bit_offset: 14 - bit_size: 1 - - name: OPTVERR - description: Option validity error - bit_offset: 15 - bit_size: 1 - - name: BSY - description: Busy - bit_offset: 16 - bit_size: 1 - - name: CFGBSY - description: Programming or erase configuration busy - bit_offset: 18 - bit_size: 1 - - name: PESD - description: Programming or erase operation suspended - bit_offset: 19 - bit_size: 1 + - name: EOP + description: End of operation + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: Operation error + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: Programming error + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: Write protected error + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: Programming alignment error + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: Size error + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: Programming sequence error + bit_offset: 7 + bit_size: 1 + - name: MISERR + description: Fast programming data miss error + bit_offset: 8 + bit_size: 1 + - name: FASTERR + description: Fast programming error + bit_offset: 9 + bit_size: 1 + - name: OPTNV + description: User Option OPTVAL indication + bit_offset: 13 + bit_size: 1 + - name: RDERR + description: PCROP read error + bit_offset: 14 + bit_size: 1 + - name: OPTVERR + description: Option validity error + bit_offset: 15 + bit_size: 1 + - name: BSY + description: Busy + bit_offset: 16 + bit_size: 1 + - name: CFGBSY + description: Programming or erase configuration busy + bit_offset: 18 + bit_size: 1 + - name: PESD + description: Programming or erase operation suspended + bit_offset: 19 + bit_size: 1 fieldset/SRRVR: description: Secure SRAM2 start address and cortex M0 reset vector register fields: - - name: SBRV - description: cortex M0 access control register - bit_offset: 0 - bit_size: 18 - - name: SBRSA - description: Secure backup SRAM2a start address - bit_offset: 18 - bit_size: 5 - - name: BRSD - description: backup SRAM2a security disable - bit_offset: 23 - bit_size: 1 - - name: SNBRSA - description: Secure non backup SRAM2a start address - bit_offset: 25 - bit_size: 5 - - name: NBRSD - description: non-backup SRAM2b security disable - bit_offset: 30 - bit_size: 1 - - name: C2OPT - description: CPU2 cortex M0 boot reset vector memory selection - bit_offset: 31 - bit_size: 1 + - name: SBRV + description: cortex M0 access control register + bit_offset: 0 + bit_size: 18 + - name: SBRSA + description: Secure backup SRAM2a start address + bit_offset: 18 + bit_size: 5 + - name: BRSD + description: backup SRAM2a security disable + bit_offset: 23 + bit_size: 1 + - name: SNBRSA + description: Secure non backup SRAM2a start address + bit_offset: 25 + bit_size: 5 + - name: NBRSD + description: non-backup SRAM2b security disable + bit_offset: 30 + bit_size: 1 + - name: C2OPT + description: CPU2 cortex M0 boot reset vector memory selection + bit_offset: 31 + bit_size: 1 fieldset/WRP1AR: description: Flash Bank 1 WRP area A address register fields: - - name: WRP1A_STRT - description: Bank 1 WRP first area A start offset - bit_offset: 0 - bit_size: 8 - - name: WRP1A_END - description: Bank 1 WRP first area A end offset - bit_offset: 16 - bit_size: 8 + - name: WRP1A_STRT + description: Bank 1 WRP first area A start offset + bit_offset: 0 + bit_size: 8 + - name: WRP1A_END + description: Bank 1 WRP first area A end offset + bit_offset: 16 + bit_size: 8 fieldset/WRP1BR: description: Flash Bank 1 WRP area B address register fields: - - name: WRP1B_END - description: Bank 1 WRP second area B start offset - bit_offset: 0 - bit_size: 8 - - name: WRP1B_STRT - description: Bank 1 WRP second area B end offset - bit_offset: 16 - bit_size: 8 + - name: WRP1B_END + description: Bank 1 WRP second area B start offset + bit_offset: 0 + bit_size: 8 + - name: WRP1B_STRT + description: Bank 1 WRP second area B end offset + bit_offset: 16 + bit_size: 8 diff --git a/data/registers/flash_wba.yaml b/data/registers/flash_wba.yaml new file mode 100644 index 0000000..21aa791 --- /dev/null +++ b/data/registers/flash_wba.yaml @@ -0,0 +1,643 @@ +block/FLASH: + description: Embedded memory + items: + - name: ACR + description: access control register + byte_offset: 0 + fieldset: ACR + - name: NSKEYR + description: key register + byte_offset: 8 + fieldset: NSKEYR + - name: SECKEYR + description: secure key register + byte_offset: 12 + fieldset: SECKEYR + - name: OPTKEYR + description: option key register + byte_offset: 16 + fieldset: OPTKEYR + - name: PDKEYR + description: power-down key register + byte_offset: 24 + fieldset: PDKEYR + - name: NSSR + description: status register + byte_offset: 32 + fieldset: NSSR + - name: SECSR + description: secure status register + byte_offset: 36 + fieldset: SECSR + - name: NSCR1 + description: control register + byte_offset: 40 + fieldset: NSCR1 + - name: SECCR1 + description: secure control register + byte_offset: 44 + fieldset: SECCR1 + - name: ECCR + description: ECC register + byte_offset: 48 + fieldset: ECCR + - name: OPSR + description: operation status register + byte_offset: 52 + fieldset: OPSR + - name: NSCR2 + description: control 2 register + byte_offset: 56 + fieldset: NSCR2 + - name: SECCR2 + description: secure control 2 register + byte_offset: 60 + fieldset: SECCR2 + - name: OPTR + description: option register + byte_offset: 64 + fieldset: OPTR + - name: NSBOOTADD0R + description: boot address 0 register + byte_offset: 68 + fieldset: NSBOOTADD0R + - name: NSBOOTADD1R + description: boot address 1 register + byte_offset: 72 + fieldset: NSBOOTADD1R + - name: SECBOOTADD0R + description: secure boot address 0 register + byte_offset: 76 + fieldset: SECBOOTADD0R + - name: SECWMR1 + description: secure watermark register 1 + byte_offset: 80 + fieldset: SECWMR1 + - name: SECWMR2 + description: secure watermark register 2 + byte_offset: 84 + fieldset: SECWMR2 + - name: WRPAR + description: WRP area A address register + byte_offset: 88 + fieldset: WRPAR + - name: WRPBR + description: WRP area B address register + byte_offset: 92 + fieldset: WRPBR + - name: OEM1KEYR1 + description: OEM1 key register 1 + byte_offset: 112 + - name: OEM1KEYR2 + description: OEM1 key register 2 + byte_offset: 116 + - name: OEM2KEYR1 + description: OEM2 key register 1 + byte_offset: 120 + - name: OEM2KEYR2 + description: OEM2 key register 2 + byte_offset: 124 + - name: SECBBR + description: secure block based register 1 + array: + len: 4 + stride: 4 + byte_offset: 128 + fieldset: BBR + - name: SECHDPCR + description: secure HDP control register + byte_offset: 192 + fieldset: SECHDPCR + - name: PRIFCFGR + description: privilege configuration register + byte_offset: 196 + fieldset: PRIFCFGR + - name: PRIVBBR + description: privilege block based register 1 + array: + len: 4 + stride: 4 + byte_offset: 208 + fieldset: BBR +fieldset/ACR: + description: access control register + fields: + - name: LATENCY + description: "Latency\r These bits represent the ratio between the AHB hclk1 clock period and the memory access time.\r Access to the bit can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r ...\r Note: Before entering Stop 1 mode software must set wait state latency to at least 1." + bit_offset: 0 + bit_size: 4 + - name: PRFTEN + description: "Prefetch enable\r This bit enables the prefetch buffer in the embedded memory.\r This bit can be protected against unprivileged access by NSPRIV." + bit_offset: 8 + bit_size: 1 + - name: LPM + description: "Low-power read mode\r This bit puts the memory in low-power read mode.\r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r This bit can’t be written when a program or erase operation is busy (BSY = 1) or when the write buffer is not empty (WDW = 1). Changing this bit while a program or erase operation is busy (BSY = 1) is rejected." + bit_offset: 11 + bit_size: 1 + - name: PDREQ + description: "power-down mode request\r This bit requests to enter power-down mode. When enters power-down mode, this bit is cleared by hardware and the PDKEYR is locked.\r This bit is write-protected with PDKEYR. \r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 12 + bit_size: 1 + - name: SLEEP_PD + description: "memory power-down mode during Sleep mode\r This bit determines whether the memory is in power-down mode or Idle mode when the device is in Sleep mode.\r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r The must not be put in power-down while a program or an erase operation is ongoing." + bit_offset: 14 + bit_size: 1 +fieldset/BBR: + description: block based register + fields: + - name: BLOCK + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 +fieldset/ECCR: + description: ECC register + fields: + - name: ADDR_ECC + description: "ECC fail address\r This field indicates which address is concerned by the ECC error correction or by the double ECC error detection. The address is given relative to base address, from offset 0x0�0000 to 0xF�FFF0.\r Note that bit 19 is reserved on STM32WBAxEx devices." + bit_offset: 0 + bit_size: 20 + - name: SYSF_ECC + description: "System memory ECC fail\r This bit indicates that the ECC error correction or double ECC error detection is located in the system memory." + bit_offset: 22 + bit_size: 1 + - name: ECCIE + description: "ECC correction interrupt enable\r This bit enables the interrupt generation when the ECCC bit in the ECCR register is set." + bit_offset: 24 + bit_size: 1 + - name: ECCC + description: "ECC correction\r This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1." + bit_offset: 30 + bit_size: 1 + - name: ECCD + description: "ECC detection\r This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1." + bit_offset: 31 + bit_size: 1 +fieldset/NSBOOTADD0R: + description: boot address 0 register + fields: + - name: NSBOOTADD0 + description: "Non-secure boot base address 0\r This address is only used when TZEN = 0.\r The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state.\r Examples:\r NSBOOTADD0[24:0] = 0x0100000: Boot from memory (0x0800 0000)\r NSBOOTADD0[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000)\r NSBOOTADD0[24:0] = 0x0400200: Boot from SRAM2 on S-Bus (0x2001 0000)" + bit_offset: 7 + bit_size: 25 +fieldset/NSBOOTADD1R: + description: boot address 1 register + fields: + - name: NSBOOTADD1 + description: "Non-secure boot address 1\r This address is only used when TZEN = 0.\r The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. \r Examples:\r NSBOOTADD1[24:0] = 0x0100000: Boot from memory (0x0800 0000)\r NSBOOTADD1[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000)\r NSBOOTADD1[24:0] = 0x0400200: Boot from SRAM2 (0x2001 0000)" + bit_offset: 7 + bit_size: 25 +fieldset/NSCR1: + description: control register + fields: + - name: PG + description: Non-secure programming + bit_offset: 0 + bit_size: 1 + - name: PER + description: Non-secure page erase + bit_offset: 1 + bit_size: 1 + - name: MER + description: "Non-secure mass erase\r This bit triggers the non-secure mass erase (all user pages) when set." + bit_offset: 2 + bit_size: 1 + - name: PNB + description: "Non-secure page number selection\r These bits select the page to erase.\r ...\r Note that bit 9 is reserved on STM32WBA5xEx devices." + bit_offset: 3 + bit_size: 7 + - name: BWR + description: "Non-secure burst write programming mode\r When set, this bit selects the burst write programming mode." + bit_offset: 14 + bit_size: 1 + - name: STRT + description: "Non-secure operation start \r This bit triggers a non-secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR bit in NSSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in NSSR." + bit_offset: 16 + bit_size: 1 + - name: OPTSTRT + description: "Options modification start\r This bit triggers an option bytes erase and program operation when set. This bit is write-protected with OPTLOCK.. This bit is set only by software, and is cleared when the BSY bit is cleared in NSSR." + bit_offset: 17 + bit_size: 1 + - name: EOPIE + description: "Non-secure end of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in the NSSR is set to 1." + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: "Non-secure error interrupt enable\r This bit enables the interrupt generation when the OPERR bit in the NSSR is set to 1." + bit_offset: 25 + bit_size: 1 + - name: OBL_LAUNCH + description: "Force the option byte loading\r When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. This bit is write-protected with OPTLOCK.\r Note: The LSE oscillator must be disabled, LSEON = 0 and LSERDY = 0, before starting OBL_LAUNCH." + bit_offset: 27 + bit_size: 1 + - name: OPTLOCK + description: "Option lock\r This bit is set only. When set, the NSCR1.OPTSRT and OBL_LAUNCH bits concerning user options write access is locked. This bit is cleared by hardware after detecting the unlock sequence in OPTKEYR. The NSCR1.LOCK bit must be cleared before doing the OPTKEYR unlock sequence.\r In case of an unsuccessful unlock operation, this bit remains set until the next reset." + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: "Non-secure lock\r This bit is set only.\r When set, the NSCR1 register write access is locked. This bit is cleared by hardware after detecting the unlock sequence in NSKEYR.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset." + bit_offset: 31 + bit_size: 1 +fieldset/NSCR2: + description: control 2 register + fields: + - name: PS + description: Program suspend request + bit_offset: 0 + bit_size: 1 + - name: ES + description: Erase suspend request + bit_offset: 1 + bit_size: 1 +fieldset/NSKEYR: + description: key register + fields: + - name: NSKEY + description: "memory non-secure key\r The following values must be written consecutively to unlock the NSCR1 register, allowing the memory non-secure programming/erasing operations:\r KEY1: 0x4567�0123\r KEY2: 0xCDEF�89AB" + bit_offset: 0 + bit_size: 32 +fieldset/NSSR: + description: status register + fields: + - name: EOP + description: "Non-secure end of operation\r This bit is set by hardware when one or more memory non-secure operation (program/erase) has been completed successfully. This bit is set only if the non-secure end of operation interrupts are enabled (EOPIE = 1 in NSCR1). This bit is cleared by writing�1." + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: "Non-secure operation error\r This bit is set by hardware when a memory non-secure operation (program/erase) completes unsuccessfully. This bit is set only if non-secure error interrupts are enabled (NSERRIE = 1). This bit is cleared by writing 1." + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: "Non-secure programming error\r This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1." + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: "Non-secure write protection error\r This bit is set by hardware when a non-secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1.\r Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting." + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: "Non-secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1." + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: "Non-secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1." + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: "Non-secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting." + bit_offset: 7 + bit_size: 1 + - name: OPTWERR + description: "Option write error \r This bit is set by hardware when the options bytes are written with an invalid configuration or when modifying options in RDP level 2.. It is cleared by writing 1.\r Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting." + bit_offset: 13 + bit_size: 1 + - name: BSY + description: "Non-secure busy\r This indicates that a memory secure or non-secure operation is in progress. This bit is set at the beginning of a operation and reset when the operation finishes or when an error occurs." + bit_offset: 16 + bit_size: 1 + - name: WDW + description: "Non-secure wait data to write\r This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory." + bit_offset: 17 + bit_size: 1 + - name: OEM1LOCK + description: "OEM1 key RDP lock\r This bit indicates that the OEM1 key read during the OBL is not virgin. When set, the OEM1 key RDP lock mechanism is active." + bit_offset: 18 + bit_size: 1 + - name: OEM2LOCK + description: "OEM2 key RDP lock\r This bit indicates that the OEM2 key read during the OBL is not virgin. When set, the OEM2 key RDP lock mechanism is active." + bit_offset: 19 + bit_size: 1 + - name: PD + description: "in power-down mode\r This bit indicates that the memory is in power-down state. It is reset when is in normal mode or being awaken." + bit_offset: 20 + bit_size: 1 +fieldset/OPSR: + description: operation status register + fields: + - name: ADDR_OP + description: "Interrupted operation address\r This field indicates which address in the memory was accessed when reset occurred. The address is given relative to the base address, from offset 0x0�0000 to 0xF�FFF0.\r Note that bit 19 is reserved on STM32WBAxEx devices." + bit_offset: 0 + bit_size: 20 + - name: SYSF_OP + description: "Operation in system memory interrupted\r This bit indicates that the reset occurred during an operation in the system memory." + bit_offset: 22 + bit_size: 1 + - name: CODE_OP + description: "memory operation code\r This field indicates which memory operation has been interrupted by a system reset:" + bit_offset: 29 + bit_size: 3 + enum: CODE_OP +fieldset/OPTKEYR: + description: option key register + fields: + - name: OPTKEY + description: "Option byte key\r The LOCK bit in the NSCR1 must be cleared before doing the unlock sequence for OPTLOCK bit. The following values must be written consecutively to unlock the NSCR1.OPTSTRT and OBL_LAUNCH register bits concerning user option operations:\r KEY1: 0x0819�2A3B\r KEY2: 0x4C5D�6E7F" + bit_offset: 0 + bit_size: 32 +fieldset/OPTR: + description: option register + fields: + - name: RDP + description: "Readout protection level\r Others: Level 1 (memories readout protection active)\r Note: Refer to Section�7.6.2: Readout protection (RDP) for more details." + bit_offset: 0 + bit_size: 8 + enum: RDP + - name: BOR_LEV + description: "BOR reset level\r These bits contain the VDD supply level threshold that activates/releases the reset." + bit_offset: 8 + bit_size: 3 + enum: BOR_LEV + - name: NRST_STOP + description: Reset generation in Stop mode + bit_offset: 12 + bit_size: 1 + - name: NRST_STDBY + description: Reset generation in Standby mode + bit_offset: 13 + bit_size: 1 + - name: SRAM1_RST + description: SRAM1 erase upon system reset + bit_offset: 15 + bit_size: 1 + - name: IWDG_SW + description: Independent watchdog enable selection + bit_offset: 16 + bit_size: 1 + - name: IWDG_STOP + description: Independent watchdog counter freeze in Stop mode + bit_offset: 17 + bit_size: 1 + - name: IWDG_STDBY + description: Independent watchdog counter freeze in Standby mode + bit_offset: 18 + bit_size: 1 + - name: WWDG_SW + description: Window watchdog selection + bit_offset: 19 + bit_size: 1 + - name: SRAM2_PE + description: SRAM2 parity check enable + bit_offset: 24 + bit_size: 1 + - name: SRAM2_RST + description: SRAM2 erase when system reset + bit_offset: 25 + bit_size: 1 + - name: NSWBOOT0 + description: Software BOOT0 + bit_offset: 26 + bit_size: 1 + - name: NBOOT0 + description: NBOOT0 option bit + bit_offset: 27 + bit_size: 1 + - name: TZEN + description: Global TrustZone security enable + bit_offset: 31 + bit_size: 1 +fieldset/PDKEYR: + description: power-down key register + fields: + - name: PDKEY1 + description: "power-down key\r The following values must be written consecutively to unlock the PDREQ bit in ACR:\r PDKEY_1: 0x0415�2637\r PDKEY_2: 0xFAFB�FCFD" + bit_offset: 0 + bit_size: 32 +fieldset/PRIFCFGR: + description: privilege configuration register + fields: + - name: SPRIV + description: "Privileged protection for secure registers\r This bit is secure write protected. It can only be written by a secure privileged access when TrustZone is enabled (TZEN�=�1)." + bit_offset: 0 + bit_size: 1 + - name: NSPRIV + description: Privileged protection for non-secure registers + bit_offset: 1 + bit_size: 1 +fieldset/SECBOOTADD0R: + description: secure boot address 0 register + fields: + - name: BOOT_LOCK + description: "Boot lock\r This lock is only used when TZEN = 0.\r When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP regression level 1 to level 0." + bit_offset: 0 + bit_size: 1 + - name: SECBOOTADD0 + description: "Secure boot base address 0\r This address is only used when TZEN = 1.\r The secure boot memory address can be programmed to any address in the valid address range (see Table�28: Boot space versus RDP protection) with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. \r Examples:\r SECBOOTADD0[24:0] = 0x018 0000: Boot from secure user memory (0x0C00 0000)\r SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS system memory (0x0FF8 0000)\r SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000)" + bit_offset: 7 + bit_size: 25 +fieldset/SECCR1: + description: secure control register + fields: + - name: PG + description: Secure programming + bit_offset: 0 + bit_size: 1 + - name: PER + description: Secure page erase + bit_offset: 1 + bit_size: 1 + - name: MER + description: "Secure mass erase\r This bit triggers the secure mass erase (all user pages) when set." + bit_offset: 2 + bit_size: 1 + - name: PNB + description: "Secure page number selection\r These bits select the page to erase:\r ...\r Note that bit 9 is reserved on STM32WBA5xEx devices." + bit_offset: 3 + bit_size: 7 + - name: BWR + description: "Secure burst write programming mode\r When set, this bit selects the burst write programming mode." + bit_offset: 14 + bit_size: 1 + - name: STRT + description: "Secure start \r This bit triggers a secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR in the SECSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in SECSR." + bit_offset: 16 + bit_size: 1 + - name: EOPIE + description: "Secure End of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in SECSR is set to 1." + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: "Secure error interrupt enable\r This bit enables the interrupt generation when the OPERR bit in SECSR is set to 1." + bit_offset: 25 + bit_size: 1 + - name: INV + description: "memory security state invert\r This bit inverts the memory security state." + bit_offset: 29 + bit_size: 1 + - name: LOCK + description: "Secure lock\r This bit is set only. When set, the SECCR1 register is locked. It is cleared by hardware after detecting the unlock sequence in SECKEYR register.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset." + bit_offset: 31 + bit_size: 1 +fieldset/SECCR2: + description: secure control 2 register + fields: + - name: PS + description: Program suspend request + bit_offset: 0 + bit_size: 1 + - name: ES + description: Erase suspend request + bit_offset: 1 + bit_size: 1 +fieldset/SECHDPCR: + description: secure HDP control register + fields: + - name: HDP_ACCDIS + description: "Secure HDP area access disable \r When set, this bit is only cleared by a system reset." + bit_offset: 0 + bit_size: 1 +fieldset/SECKEYR: + description: secure key register + fields: + - name: SECKEY + description: "memory secure key\r The following values must be written consecutively to unlock the SECCR1 register, allowing the memory secure programming/erasing operations:\r KEY1: 0x4567�0123\r KEY2: 0xCDEF�89AB" + bit_offset: 0 + bit_size: 32 +fieldset/SECSR: + description: secure status register + fields: + - name: EOP + description: "Secure end of operation\r This bit is set by hardware when one or more memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in SECCR1). This bit is cleared by writing�1." + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: "Secure operation error\r This bit is set by hardware when a memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1." + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: "Secure programming error\r This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1." + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: "Secure write protection error\r This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1.\r Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting." + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: "Secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1." + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: "Secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1." + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: "Secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting." + bit_offset: 7 + bit_size: 1 + - name: BSY + description: "Secure busy\r This bit indicates that a memory secure or non-secure operation is in progress. This is set on the beginning of a operation and reset when the operation finishes or when an error occurs." + bit_offset: 16 + bit_size: 1 + - name: WDW + description: "Secure wait data to write\r This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory." + bit_offset: 17 + bit_size: 1 +fieldset/SECWMR1: + description: secure watermark register 1 + fields: + - name: SECWM_PSTRT + description: "Start page of secure area\r This field contains the first page of the secure area." + bit_offset: 0 + bit_size: 7 + - name: SECWM_PEND + description: "End page of secure area\r This field contains the last page of the secure area." + bit_offset: 16 + bit_size: 7 +fieldset/SECWMR2: + description: secure watermark register 2 + fields: + - name: HDP_PEND + description: "End page of secure hide protection area\r This field contains the last page of the secure HDP area." + bit_offset: 16 + bit_size: 7 + - name: HDPEN + description: Secure Hide protection area enable + bit_offset: 31 + bit_size: 1 +fieldset/WRPAR: + description: WRP area A address register + fields: + - name: WRPA_PSTRT + description: "WPR area A start page\r This field contains the first page of the WPR area A.\r Note that bit 6 is reserved on STM32WBAxEx devices." + bit_offset: 0 + bit_size: 7 + - name: WRPA_PEND + description: "WPR area A end page\r This field contains the last page of the WPR area A.\r Note that bit 22 is reserved on STM32WBAxEx devices." + bit_offset: 16 + bit_size: 7 + - name: UNLOCK + description: WPR area A unlock + bit_offset: 31 + bit_size: 1 +fieldset/WRPBR: + description: WRP area B address register + fields: + - name: WRPB_PSTRT + description: "WRP area B start page\r This field contains the first page of the WRP area B.\r Note that bit 6 is reserved on STM32WBAxEx devices." + bit_offset: 0 + bit_size: 7 + - name: WRPB_PEND + description: "WRP area B end page\r This field contains the last page of the WRP area B.\r Note that bit 22 is reserved on STM32WBAxEx devices." + bit_offset: 16 + bit_size: 7 + - name: UNLOCK + description: WPR area B unlock + bit_offset: 31 + bit_size: 1 +enum/BOR_LEV: + bit_size: 3 + variants: + - name: Level0 + description: BOR level 0 (reset level threshold around 1.7�V) + value: 0 + - name: Level1 + description: BOR level 1 (reset level threshold around 2.0�V) + value: 1 + - name: Level2 + description: BOR level 2 (reset level threshold around 2.2�V) + value: 2 + - name: Level3 + description: BOR level 3 (reset level threshold around 2.5�V) + value: 3 + - name: Level4 + description: BOR level 4 (reset level threshold around 2.8�V) + value: 4 +enum/CODE_OP: + bit_size: 3 + variants: + - name: B_0x0 + description: No operation interrupted by previous reset + value: 0 + - name: B_0x1 + description: Single write operation interrupted + value: 1 + - name: B_0x2 + description: Burst write operation interrupted + value: 2 + - name: B_0x3 + description: Page erase operation interrupted + value: 3 + - name: B_0x4 + description: Reserved + value: 4 + - name: B_0x5 + description: Mass erase operation interrupted + value: 5 + - name: B_0x6 + description: Option change operation interrupted + value: 6 + - name: B_0x7 + description: Reserved + value: 7 +enum/RDP: + bit_size: 8 + variants: + - name: B_0x55 + description: Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1) + value: 85 + - name: B_0xAA + description: Level 0 (readout protection not active) + value: 170 + - name: B_0xCC + description: Level 2 (chip readout protection active) + value: 204 diff --git a/data/registers/flash_wl.yaml b/data/registers/flash_wl.yaml index da253b4..1d98476 100644 --- a/data/registers/flash_wl.yaml +++ b/data/registers/flash_wl.yaml @@ -1,559 +1,558 @@ ---- block/FLASH: description: Flash items: - - name: ACR - description: Access control register - byte_offset: 0 - fieldset: ACR - - name: KEYR - description: Flash key register - byte_offset: 8 - access: Write - fieldset: KEYR - - name: OPTKEYR - description: Option byte key register - byte_offset: 12 - access: Write - fieldset: OPTKEYR - - name: SR - description: Status register - byte_offset: 16 - fieldset: SR - - name: CR - description: Flash control register - byte_offset: 20 - fieldset: CR - - name: ECCR - description: Flash ECC register - byte_offset: 24 - fieldset: ECCR - - name: OPTR - description: Flash option register - byte_offset: 32 - fieldset: OPTR - - name: PCROP1ASR - description: Flash Bank 1 PCROP Start address zone A register - byte_offset: 36 - fieldset: PCROP1ASR - - name: PCROP1AER - description: Flash Bank 1 PCROP End address zone A register - byte_offset: 40 - fieldset: PCROP1AER - - name: WRP1AR - description: Flash Bank 1 WRP area A address register - byte_offset: 44 - fieldset: WRP1AR - - name: WRP1BR - description: Flash Bank 1 WRP area B address register - byte_offset: 48 - fieldset: WRP1BR - - name: PCROP1BSR - description: Flash Bank 1 PCROP Start address area B register - byte_offset: 52 - fieldset: PCROP1BSR - - name: PCROP1BER - description: Flash Bank 1 PCROP End address area B register - byte_offset: 56 - fieldset: PCROP1BER - - name: IPCCBR - description: IPCC mailbox data buffer address register - byte_offset: 60 - fieldset: IPCCBR - - name: C2ACR - description: CPU2 cortex M0 access control register - byte_offset: 92 - fieldset: C2ACR - - name: C2SR - description: CPU2 cortex M0 status register - byte_offset: 96 - fieldset: C2SR - - name: C2CR - description: CPU2 cortex M0 control register - byte_offset: 100 - fieldset: C2CR - - name: SFR - description: Secure flash start address register - byte_offset: 128 - fieldset: SFR - - name: SRRVR - description: Secure SRAM2 start address and cortex M0 reset vector register - byte_offset: 132 - fieldset: SRRVR + - name: ACR + description: Access control register + byte_offset: 0 + fieldset: ACR + - name: KEYR + description: Flash key register + byte_offset: 8 + access: Write + fieldset: KEYR + - name: OPTKEYR + description: Option byte key register + byte_offset: 12 + access: Write + fieldset: OPTKEYR + - name: SR + description: Status register + byte_offset: 16 + fieldset: SR + - name: CR + description: Flash control register + byte_offset: 20 + fieldset: CR + - name: ECCR + description: Flash ECC register + byte_offset: 24 + fieldset: ECCR + - name: OPTR + description: Flash option register + byte_offset: 32 + fieldset: OPTR + - name: PCROP1ASR + description: Flash Bank 1 PCROP Start address zone A register + byte_offset: 36 + fieldset: PCROP1ASR + - name: PCROP1AER + description: Flash Bank 1 PCROP End address zone A register + byte_offset: 40 + fieldset: PCROP1AER + - name: WRP1AR + description: Flash Bank 1 WRP area A address register + byte_offset: 44 + fieldset: WRP1AR + - name: WRP1BR + description: Flash Bank 1 WRP area B address register + byte_offset: 48 + fieldset: WRP1BR + - name: PCROP1BSR + description: Flash Bank 1 PCROP Start address area B register + byte_offset: 52 + fieldset: PCROP1BSR + - name: PCROP1BER + description: Flash Bank 1 PCROP End address area B register + byte_offset: 56 + fieldset: PCROP1BER + - name: IPCCBR + description: IPCC mailbox data buffer address register + byte_offset: 60 + fieldset: IPCCBR + - name: C2ACR + description: CPU2 cortex M0 access control register + byte_offset: 92 + fieldset: C2ACR + - name: C2SR + description: CPU2 cortex M0 status register + byte_offset: 96 + fieldset: C2SR + - name: C2CR + description: CPU2 cortex M0 control register + byte_offset: 100 + fieldset: C2CR + - name: SFR + description: Secure flash start address register + byte_offset: 128 + fieldset: SFR + - name: SRRVR + description: Secure SRAM2 start address and cortex M0 reset vector register + byte_offset: 132 + fieldset: SRRVR fieldset/ACR: description: Access control register fields: - - name: LATENCY - description: Latency - bit_offset: 0 - bit_size: 3 - - name: PRFTEN - description: Prefetch enable - bit_offset: 8 - bit_size: 1 - - name: ICEN - description: Instruction cache enable - bit_offset: 9 - bit_size: 1 - - name: DCEN - description: Data cache enable - bit_offset: 10 - bit_size: 1 - - name: ICRST - description: Instruction cache reset - bit_offset: 11 - bit_size: 1 - - name: DCRST - description: Data cache reset - bit_offset: 12 - bit_size: 1 - - name: PES - description: CPU1 CortexM4 program erase suspend request - bit_offset: 15 - bit_size: 1 - - name: EMPTY - description: Flash User area empty - bit_offset: 16 - bit_size: 1 + - name: LATENCY + description: Latency + bit_offset: 0 + bit_size: 3 + - name: PRFTEN + description: Prefetch enable + bit_offset: 8 + bit_size: 1 + - name: ICEN + description: Instruction cache enable + bit_offset: 9 + bit_size: 1 + - name: DCEN + description: Data cache enable + bit_offset: 10 + bit_size: 1 + - name: ICRST + description: Instruction cache reset + bit_offset: 11 + bit_size: 1 + - name: DCRST + description: Data cache reset + bit_offset: 12 + bit_size: 1 + - name: PES + description: CPU1 CortexM4 program erase suspend request + bit_offset: 15 + bit_size: 1 + - name: EMPTY + description: Flash User area empty + bit_offset: 16 + bit_size: 1 fieldset/C2ACR: description: CPU2 cortex M0 access control register fields: - - name: PRFTEN - description: CPU2 cortex M0 prefetch enable - bit_offset: 8 - bit_size: 1 - - name: ICEN - description: CPU2 cortex M0 instruction cache enable - bit_offset: 9 - bit_size: 1 - - name: ICRST - description: CPU2 cortex M0 instruction cache reset - bit_offset: 11 - bit_size: 1 - - name: PES - description: CPU2 cortex M0 program erase suspend request - bit_offset: 15 - bit_size: 1 + - name: PRFTEN + description: CPU2 cortex M0 prefetch enable + bit_offset: 8 + bit_size: 1 + - name: ICEN + description: CPU2 cortex M0 instruction cache enable + bit_offset: 9 + bit_size: 1 + - name: ICRST + description: CPU2 cortex M0 instruction cache reset + bit_offset: 11 + bit_size: 1 + - name: PES + description: CPU2 cortex M0 program erase suspend request + bit_offset: 15 + bit_size: 1 fieldset/C2CR: description: CPU2 cortex M0 control register fields: - - name: PG - description: Programming - bit_offset: 0 - bit_size: 1 - - name: PER - description: Page erase - bit_offset: 1 - bit_size: 1 - - name: MER - description: Masse erase - bit_offset: 2 - bit_size: 1 - - name: PNB - description: Page Number selection - bit_offset: 3 - bit_size: 8 - - name: STRT - description: Start - bit_offset: 16 - bit_size: 1 - - name: FSTPG - description: Fast programming - bit_offset: 18 - bit_size: 1 - - name: EOPIE - description: End of operation interrupt enable - bit_offset: 24 - bit_size: 1 - - name: ERRIE - description: Error interrupt enable - bit_offset: 25 - bit_size: 1 - - name: RDERRIE - description: PCROP read error interrupt enable - bit_offset: 26 - bit_size: 1 + - name: PG + description: Programming + bit_offset: 0 + bit_size: 1 + - name: PER + description: Page erase + bit_offset: 1 + bit_size: 1 + - name: MER + description: Masse erase + bit_offset: 2 + bit_size: 1 + - name: PNB + description: Page Number selection + bit_offset: 3 + bit_size: 8 + - name: STRT + description: Start + bit_offset: 16 + bit_size: 1 + - name: FSTPG + description: Fast programming + bit_offset: 18 + bit_size: 1 + - name: EOPIE + description: End of operation interrupt enable + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 25 + bit_size: 1 + - name: RDERRIE + description: PCROP read error interrupt enable + bit_offset: 26 + bit_size: 1 fieldset/C2SR: description: CPU2 cortex M0 status register fields: - - name: EOP - description: End of operation - bit_offset: 0 - bit_size: 1 - - name: OPERR - description: Operation error - bit_offset: 1 - bit_size: 1 - - name: PROGERR - description: Programming error - bit_offset: 3 - bit_size: 1 - - name: WRPERR - description: write protection error - bit_offset: 4 - bit_size: 1 - - name: PGAERR - description: Programming alignment error - bit_offset: 5 - bit_size: 1 - - name: SIZERR - description: Size error - bit_offset: 6 - bit_size: 1 - - name: PGSERR - description: Programming sequence error - bit_offset: 7 - bit_size: 1 - - name: MISSERR - description: Fast programming data miss error - bit_offset: 8 - bit_size: 1 - - name: FASTERR - description: Fast programming error - bit_offset: 9 - bit_size: 1 - - name: RDERR - description: PCROP read error - bit_offset: 14 - bit_size: 1 - - name: BSY - description: Busy - bit_offset: 16 - bit_size: 1 - - name: CFGBSY - description: Programming or erase configuration busy - bit_offset: 18 - bit_size: 1 - - name: PESD - description: Programming or erase operation suspended - bit_offset: 19 - bit_size: 1 + - name: EOP + description: End of operation + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: Operation error + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: Programming error + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: write protection error + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: Programming alignment error + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: Size error + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: Programming sequence error + bit_offset: 7 + bit_size: 1 + - name: MISSERR + description: Fast programming data miss error + bit_offset: 8 + bit_size: 1 + - name: FASTERR + description: Fast programming error + bit_offset: 9 + bit_size: 1 + - name: RDERR + description: PCROP read error + bit_offset: 14 + bit_size: 1 + - name: BSY + description: Busy + bit_offset: 16 + bit_size: 1 + - name: CFGBSY + description: Programming or erase configuration busy + bit_offset: 18 + bit_size: 1 + - name: PESD + description: Programming or erase operation suspended + bit_offset: 19 + bit_size: 1 fieldset/CR: description: Flash control register fields: - - name: PG - description: Programming - bit_offset: 0 - bit_size: 1 - - name: PER - description: Page erase - bit_offset: 1 - bit_size: 1 - - name: MER - description: This bit triggers the mass erase (all user pages) when set - bit_offset: 2 - bit_size: 1 - - name: PNB - description: Page number selection - bit_offset: 3 - bit_size: 8 - - name: STRT - description: Start - bit_offset: 16 - bit_size: 1 - - name: OPTSTRT - description: Options modification start - bit_offset: 17 - bit_size: 1 - - name: FSTPG - description: Fast programming - bit_offset: 18 - bit_size: 1 - - name: EOPIE - description: End of operation interrupt enable - bit_offset: 24 - bit_size: 1 - - name: ERRIE - description: Error interrupt enable - bit_offset: 25 - bit_size: 1 - - name: RDERRIE - description: PCROP read error interrupt enable - bit_offset: 26 - bit_size: 1 - - name: OBL_LAUNCH - description: Force the option byte loading - bit_offset: 27 - bit_size: 1 - - name: OPTLOCK - description: Options Lock - bit_offset: 30 - bit_size: 1 - - name: LOCK - description: FLASH_CR Lock - bit_offset: 31 - bit_size: 1 + - name: PG + description: Programming + bit_offset: 0 + bit_size: 1 + - name: PER + description: Page erase + bit_offset: 1 + bit_size: 1 + - name: MER + description: This bit triggers the mass erase (all user pages) when set + bit_offset: 2 + bit_size: 1 + - name: PNB + description: Page number selection + bit_offset: 3 + bit_size: 8 + - name: STRT + description: Start + bit_offset: 16 + bit_size: 1 + - name: OPTSTRT + description: Options modification start + bit_offset: 17 + bit_size: 1 + - name: FSTPG + description: Fast programming + bit_offset: 18 + bit_size: 1 + - name: EOPIE + description: End of operation interrupt enable + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 25 + bit_size: 1 + - name: RDERRIE + description: PCROP read error interrupt enable + bit_offset: 26 + bit_size: 1 + - name: OBL_LAUNCH + description: Force the option byte loading + bit_offset: 27 + bit_size: 1 + - name: OPTLOCK + description: Options Lock + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: FLASH_CR Lock + bit_offset: 31 + bit_size: 1 fieldset/ECCR: description: Flash ECC register fields: - - name: ADDR_ECC - description: ECC fail address - bit_offset: 0 - bit_size: 17 - - name: SYSF_ECC - description: System Flash ECC fail - bit_offset: 20 - bit_size: 1 - - name: ECCCIE - description: ECC correction interrupt enable - bit_offset: 24 - bit_size: 1 - - name: CPUID - description: CPU identification - bit_offset: 26 - bit_size: 3 - - name: ECCC - description: ECC correction - bit_offset: 30 - bit_size: 1 - - name: ECCD - description: ECC detection - bit_offset: 31 - bit_size: 1 + - name: ADDR_ECC + description: ECC fail address + bit_offset: 0 + bit_size: 17 + - name: SYSF_ECC + description: System Flash ECC fail + bit_offset: 20 + bit_size: 1 + - name: ECCCIE + description: ECC correction interrupt enable + bit_offset: 24 + bit_size: 1 + - name: CPUID + description: CPU identification + bit_offset: 26 + bit_size: 3 + - name: ECCC + description: ECC correction + bit_offset: 30 + bit_size: 1 + - name: ECCD + description: ECC detection + bit_offset: 31 + bit_size: 1 fieldset/IPCCBR: description: IPCC mailbox data buffer address register fields: - - name: IPCCDBA - description: PCC mailbox data buffer base address - bit_offset: 0 - bit_size: 14 + - name: IPCCDBA + description: PCC mailbox data buffer base address + bit_offset: 0 + bit_size: 14 fieldset/KEYR: description: Flash key register fields: - - name: KEYR - description: KEYR - bit_offset: 0 - bit_size: 32 + - name: KEYR + description: KEYR + bit_offset: 0 + bit_size: 32 fieldset/OPTKEYR: description: Option byte key register fields: - - name: OPTKEYR - description: Option byte key - bit_offset: 0 - bit_size: 32 + - name: OPTKEYR + description: Option byte key + bit_offset: 0 + bit_size: 32 fieldset/OPTR: description: Flash option register fields: - - name: RDP - description: Read protection level - bit_offset: 0 - bit_size: 8 - - name: ESE - description: Security enabled - bit_offset: 8 - bit_size: 1 - - name: BOR_LEV - description: BOR reset Level - bit_offset: 9 - bit_size: 3 - - name: nRST_STOP - description: nRST_STOP - bit_offset: 12 - bit_size: 1 - - name: nRST_STDBY - description: nRST_STDBY - bit_offset: 13 - bit_size: 1 - - name: nRST_SHDW - description: nRST_SHDW - bit_offset: 14 - bit_size: 1 - - name: IDWG_SW - description: Independent watchdog selection - bit_offset: 16 - bit_size: 1 - - name: IWDG_STOP - description: Independent watchdog counter freeze in Stop mode - bit_offset: 17 - bit_size: 1 - - name: IWDG_STDBY - description: Independent watchdog counter freeze in Standby mode - bit_offset: 18 - bit_size: 1 - - name: WWDG_SW - description: Window watchdog selection - bit_offset: 19 - bit_size: 1 - - name: nBOOT1 - description: Boot configuration - bit_offset: 23 - bit_size: 1 - - name: SRAM2_PE - description: SRAM2 parity check enable - bit_offset: 24 - bit_size: 1 - - name: SRAM2_RST - description: SRAM2 Erase when system reset - bit_offset: 25 - bit_size: 1 - - name: nSWBOOT0 - description: Software Boot0 - bit_offset: 26 - bit_size: 1 - - name: nBOOT0 - description: nBoot0 option bit - bit_offset: 27 - bit_size: 1 - - name: AGC_TRIM - description: Radio Automatic Gain Control Trimming - bit_offset: 29 - bit_size: 3 + - name: RDP + description: Read protection level + bit_offset: 0 + bit_size: 8 + - name: ESE + description: Security enabled + bit_offset: 8 + bit_size: 1 + - name: BOR_LEV + description: BOR reset Level + bit_offset: 9 + bit_size: 3 + - name: nRST_STOP + description: nRST_STOP + bit_offset: 12 + bit_size: 1 + - name: nRST_STDBY + description: nRST_STDBY + bit_offset: 13 + bit_size: 1 + - name: nRST_SHDW + description: nRST_SHDW + bit_offset: 14 + bit_size: 1 + - name: IDWG_SW + description: Independent watchdog selection + bit_offset: 16 + bit_size: 1 + - name: IWDG_STOP + description: Independent watchdog counter freeze in Stop mode + bit_offset: 17 + bit_size: 1 + - name: IWDG_STDBY + description: Independent watchdog counter freeze in Standby mode + bit_offset: 18 + bit_size: 1 + - name: WWDG_SW + description: Window watchdog selection + bit_offset: 19 + bit_size: 1 + - name: nBOOT1 + description: Boot configuration + bit_offset: 23 + bit_size: 1 + - name: SRAM2_PE + description: SRAM2 parity check enable + bit_offset: 24 + bit_size: 1 + - name: SRAM2_RST + description: SRAM2 Erase when system reset + bit_offset: 25 + bit_size: 1 + - name: nSWBOOT0 + description: Software Boot0 + bit_offset: 26 + bit_size: 1 + - name: nBOOT0 + description: nBoot0 option bit + bit_offset: 27 + bit_size: 1 + - name: AGC_TRIM + description: Radio Automatic Gain Control Trimming + bit_offset: 29 + bit_size: 3 fieldset/PCROP1AER: description: Flash Bank 1 PCROP End address zone A register fields: - - name: PCROP1A_END - description: Bank 1 PCROP area end offset - bit_offset: 0 - bit_size: 9 - - name: PCROP_RDP - description: PCROP area preserved when RDP level decreased - bit_offset: 31 - bit_size: 1 + - name: PCROP1A_END + description: Bank 1 PCROP area end offset + bit_offset: 0 + bit_size: 9 + - name: PCROP_RDP + description: PCROP area preserved when RDP level decreased + bit_offset: 31 + bit_size: 1 fieldset/PCROP1ASR: description: Flash Bank 1 PCROP Start address zone A register fields: - - name: PCROP1A_STRT - description: Bank 1 PCROPQ area start offset - bit_offset: 0 - bit_size: 9 + - name: PCROP1A_STRT + description: Bank 1 PCROPQ area start offset + bit_offset: 0 + bit_size: 9 fieldset/PCROP1BER: description: Flash Bank 1 PCROP End address area B register fields: - - name: PCROP1B_END - description: Bank 1 PCROP area end area B offset - bit_offset: 0 - bit_size: 9 + - name: PCROP1B_END + description: Bank 1 PCROP area end area B offset + bit_offset: 0 + bit_size: 9 fieldset/PCROP1BSR: description: Flash Bank 1 PCROP Start address area B register fields: - - name: PCROP1B_STRT - description: Bank 1 PCROP area B start offset - bit_offset: 0 - bit_size: 9 + - name: PCROP1B_STRT + description: Bank 1 PCROP area B start offset + bit_offset: 0 + bit_size: 9 fieldset/SFR: description: Secure flash start address register fields: - - name: SFSA - description: Secure flash start address - bit_offset: 0 - bit_size: 8 - - name: FSD - description: Flash security disable - bit_offset: 8 - bit_size: 1 - - name: DDS - description: Disable Cortex M0 debug access - bit_offset: 12 - bit_size: 1 + - name: SFSA + description: Secure flash start address + bit_offset: 0 + bit_size: 8 + - name: FSD + description: Flash security disable + bit_offset: 8 + bit_size: 1 + - name: DDS + description: Disable Cortex M0 debug access + bit_offset: 12 + bit_size: 1 fieldset/SR: description: Status register fields: - - name: EOP - description: End of operation - bit_offset: 0 - bit_size: 1 - - name: OPERR - description: Operation error - bit_offset: 1 - bit_size: 1 - - name: PROGERR - description: Programming error - bit_offset: 3 - bit_size: 1 - - name: WRPERR - description: Write protected error - bit_offset: 4 - bit_size: 1 - - name: PGAERR - description: Programming alignment error - bit_offset: 5 - bit_size: 1 - - name: SIZERR - description: Size error - bit_offset: 6 - bit_size: 1 - - name: PGSERR - description: Programming sequence error - bit_offset: 7 - bit_size: 1 - - name: MISERR - description: Fast programming data miss error - bit_offset: 8 - bit_size: 1 - - name: FASTERR - description: Fast programming error - bit_offset: 9 - bit_size: 1 - - name: OPTNV - description: User Option OPTVAL indication - bit_offset: 13 - bit_size: 1 - - name: RDERR - description: PCROP read error - bit_offset: 14 - bit_size: 1 - - name: OPTVERR - description: Option validity error - bit_offset: 15 - bit_size: 1 - - name: BSY - description: Busy - bit_offset: 16 - bit_size: 1 - - name: CFGBSY - description: Programming or erase configuration busy - bit_offset: 18 - bit_size: 1 - - name: PESD - description: Programming or erase operation suspended - bit_offset: 19 - bit_size: 1 + - name: EOP + description: End of operation + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: Operation error + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: Programming error + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: Write protected error + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: Programming alignment error + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: Size error + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: Programming sequence error + bit_offset: 7 + bit_size: 1 + - name: MISERR + description: Fast programming data miss error + bit_offset: 8 + bit_size: 1 + - name: FASTERR + description: Fast programming error + bit_offset: 9 + bit_size: 1 + - name: OPTNV + description: User Option OPTVAL indication + bit_offset: 13 + bit_size: 1 + - name: RDERR + description: PCROP read error + bit_offset: 14 + bit_size: 1 + - name: OPTVERR + description: Option validity error + bit_offset: 15 + bit_size: 1 + - name: BSY + description: Busy + bit_offset: 16 + bit_size: 1 + - name: CFGBSY + description: Programming or erase configuration busy + bit_offset: 18 + bit_size: 1 + - name: PESD + description: Programming or erase operation suspended + bit_offset: 19 + bit_size: 1 fieldset/SRRVR: description: Secure SRAM2 start address and cortex M0 reset vector register fields: - - name: SBRV - description: cortex M0 access control register - bit_offset: 0 - bit_size: 18 - - name: SBRSA - description: Secure backup SRAM2a start address - bit_offset: 18 - bit_size: 5 - - name: BRSD - description: backup SRAM2a security disable - bit_offset: 23 - bit_size: 1 - - name: SNBRSA - description: Secure non backup SRAM2a start address - bit_offset: 25 - bit_size: 5 - - name: NBRSD - description: non-backup SRAM2b security disable - bit_offset: 30 - bit_size: 1 - - name: C2OPT - description: CPU2 cortex M0 boot reset vector memory selection - bit_offset: 31 - bit_size: 1 + - name: SBRV + description: cortex M0 access control register + bit_offset: 0 + bit_size: 18 + - name: SBRSA + description: Secure backup SRAM2a start address + bit_offset: 18 + bit_size: 5 + - name: BRSD + description: backup SRAM2a security disable + bit_offset: 23 + bit_size: 1 + - name: SNBRSA + description: Secure non backup SRAM2a start address + bit_offset: 25 + bit_size: 5 + - name: NBRSD + description: non-backup SRAM2b security disable + bit_offset: 30 + bit_size: 1 + - name: C2OPT + description: CPU2 cortex M0 boot reset vector memory selection + bit_offset: 31 + bit_size: 1 fieldset/WRP1AR: description: Flash Bank 1 WRP area A address register fields: - - name: WRP1A_STRT - description: Bank 1 WRP first area A start offset - bit_offset: 0 - bit_size: 8 - - name: WRP1A_END - description: Bank 1 WRP first area A end offset - bit_offset: 16 - bit_size: 8 + - name: WRP1A_STRT + description: Bank 1 WRP first area A start offset + bit_offset: 0 + bit_size: 8 + - name: WRP1A_END + description: Bank 1 WRP first area A end offset + bit_offset: 16 + bit_size: 8 fieldset/WRP1BR: description: Flash Bank 1 WRP area B address register fields: - - name: WRP1B_END - description: Bank 1 WRP second area B start offset - bit_offset: 0 - bit_size: 8 - - name: WRP1B_STRT - description: Bank 1 WRP second area B end offset - bit_offset: 16 - bit_size: 8 + - name: WRP1B_END + description: Bank 1 WRP second area B start offset + bit_offset: 0 + bit_size: 8 + - name: WRP1B_STRT + description: Bank 1 WRP second area B end offset + bit_offset: 16 + bit_size: 8 diff --git a/data/registers/fmac_v1.yaml b/data/registers/fmac_v1.yaml index 707fb9a..1ed3dcc 100644 --- a/data/registers/fmac_v1.yaml +++ b/data/registers/fmac_v1.yaml @@ -1,179 +1,178 @@ ---- block/FMAC: description: Filter math accelerator items: - - name: X1BUFCFG - description: X1 buffer configuration register - byte_offset: 0 - fieldset: X1BUFCFG - - name: X2BUFCFG - description: X2 buffer configuration register - byte_offset: 4 - fieldset: X2BUFCFG - - name: YBUFCFG - description: Y buffer configuration register - byte_offset: 8 - fieldset: YBUFCFG - - name: PARAM - description: Parameter register - byte_offset: 12 - fieldset: PARAM - - name: CR - description: Control register - byte_offset: 16 - fieldset: CR - - name: SR - description: Status register - byte_offset: 20 - access: Read - fieldset: SR - - name: WDATA - description: Write data register - byte_offset: 24 - access: Write - fieldset: WDATA - - name: RDATA - description: Read data register - byte_offset: 28 - access: Read - fieldset: RDATA + - name: X1BUFCFG + description: X1 buffer configuration register + byte_offset: 0 + fieldset: X1BUFCFG + - name: X2BUFCFG + description: X2 buffer configuration register + byte_offset: 4 + fieldset: X2BUFCFG + - name: YBUFCFG + description: Y buffer configuration register + byte_offset: 8 + fieldset: YBUFCFG + - name: PARAM + description: Parameter register + byte_offset: 12 + fieldset: PARAM + - name: CR + description: Control register + byte_offset: 16 + fieldset: CR + - name: SR + description: Status register + byte_offset: 20 + access: Read + fieldset: SR + - name: WDATA + description: Write data register + byte_offset: 24 + access: Write + fieldset: WDATA + - name: RDATA + description: Read data register + byte_offset: 28 + access: Read + fieldset: RDATA fieldset/CR: description: Control register fields: - - name: RIEN - description: Enable read interrupt - bit_offset: 0 - bit_size: 1 - - name: WIEN - description: Enable write interrupt - bit_offset: 1 - bit_size: 1 - - name: OVFLIEN - description: Enable overflow error interrupts - bit_offset: 2 - bit_size: 1 - - name: UNFLIEN - description: Enable underflow error interrupts - bit_offset: 3 - bit_size: 1 - - name: SATIEN - description: Enable saturation error interrupts - bit_offset: 4 - bit_size: 1 - - name: DMAREN - description: Enable DMA read channel requests - bit_offset: 8 - bit_size: 1 - - name: DMAWEN - description: Enable DMA write channel requests - bit_offset: 9 - bit_size: 1 - - name: CLIPEN - description: Enable clipping - bit_offset: 15 - bit_size: 1 - - name: RESET - description: Reset FMAC unit - bit_offset: 16 - bit_size: 1 + - name: RIEN + description: Enable read interrupt + bit_offset: 0 + bit_size: 1 + - name: WIEN + description: Enable write interrupt + bit_offset: 1 + bit_size: 1 + - name: OVFLIEN + description: Enable overflow error interrupts + bit_offset: 2 + bit_size: 1 + - name: UNFLIEN + description: Enable underflow error interrupts + bit_offset: 3 + bit_size: 1 + - name: SATIEN + description: Enable saturation error interrupts + bit_offset: 4 + bit_size: 1 + - name: DMAREN + description: Enable DMA read channel requests + bit_offset: 8 + bit_size: 1 + - name: DMAWEN + description: Enable DMA write channel requests + bit_offset: 9 + bit_size: 1 + - name: CLIPEN + description: Enable clipping + bit_offset: 15 + bit_size: 1 + - name: RESET + description: Reset FMAC unit + bit_offset: 16 + bit_size: 1 fieldset/PARAM: description: Parameter register fields: - - name: P - description: Input parameter P - bit_offset: 0 - bit_size: 8 - - name: Q - description: Input parameter Q - bit_offset: 8 - bit_size: 8 - - name: R - description: Input parameter R - bit_offset: 16 - bit_size: 8 - - name: FUNC - description: Function - bit_offset: 24 - bit_size: 7 - - name: START - description: Enable execution - bit_offset: 31 - bit_size: 1 + - name: P + description: Input parameter P + bit_offset: 0 + bit_size: 8 + - name: Q + description: Input parameter Q + bit_offset: 8 + bit_size: 8 + - name: R + description: Input parameter R + bit_offset: 16 + bit_size: 8 + - name: FUNC + description: Function + bit_offset: 24 + bit_size: 7 + - name: START + description: Enable execution + bit_offset: 31 + bit_size: 1 fieldset/RDATA: description: Read data register fields: - - name: RES - description: Read data (contents of the Y output buffer at the address indicated by the READ pointer) - bit_offset: 0 - bit_size: 16 + - name: RES + description: Read data (contents of the Y output buffer at the address indicated by the READ pointer) + bit_offset: 0 + bit_size: 16 fieldset/SR: description: Status register fields: - - name: YEMPTY - description: Y buffer empty flag - bit_offset: 0 - bit_size: 1 - - name: X1FULL - description: X1 buffer full flag - bit_offset: 1 - bit_size: 1 - - name: OVFL - description: Overflow error flag - bit_offset: 8 - bit_size: 1 - - name: UNFL - description: Underflow error flag - bit_offset: 9 - bit_size: 1 - - name: SAT - description: Saturation error flag - bit_offset: 10 - bit_size: 1 + - name: YEMPTY + description: Y buffer empty flag + bit_offset: 0 + bit_size: 1 + - name: X1FULL + description: X1 buffer full flag + bit_offset: 1 + bit_size: 1 + - name: OVFL + description: Overflow error flag + bit_offset: 8 + bit_size: 1 + - name: UNFL + description: Underflow error flag + bit_offset: 9 + bit_size: 1 + - name: SAT + description: Saturation error flag + bit_offset: 10 + bit_size: 1 fieldset/WDATA: description: Write data register fields: - - name: WDATA - description: Write data (write data are transferred to the address indicated by the write pointer) - bit_offset: 0 - bit_size: 16 + - name: WDATA + description: Write data (write data are transferred to the address indicated by the write pointer) + bit_offset: 0 + bit_size: 16 fieldset/X1BUFCFG: description: X1 buffer configuration register fields: - - name: X1_BASE - description: Base address of X1 buffer - bit_offset: 0 - bit_size: 8 - - name: X1_BUF_SIZE - description: Allocated size of X1 buffer in 16-bit words - bit_offset: 8 - bit_size: 8 - - name: FULL_WM - description: Watermark for buffer full flag - bit_offset: 24 - bit_size: 2 + - name: X1_BASE + description: Base address of X1 buffer + bit_offset: 0 + bit_size: 8 + - name: X1_BUF_SIZE + description: Allocated size of X1 buffer in 16-bit words + bit_offset: 8 + bit_size: 8 + - name: FULL_WM + description: Watermark for buffer full flag + bit_offset: 24 + bit_size: 2 fieldset/X2BUFCFG: description: X2 buffer configuration register fields: - - name: X2_BASE - description: Base address of X2 buffer - bit_offset: 0 - bit_size: 8 - - name: X2_BUF_SIZE - description: Size of X2 buffer in 16-bit words - bit_offset: 8 - bit_size: 8 + - name: X2_BASE + description: Base address of X2 buffer + bit_offset: 0 + bit_size: 8 + - name: X2_BUF_SIZE + description: Size of X2 buffer in 16-bit words + bit_offset: 8 + bit_size: 8 fieldset/YBUFCFG: description: Y buffer configuration register fields: - - name: Y_BASE - description: Base address of Y buffer - bit_offset: 0 - bit_size: 8 - - name: Y_BUF_SIZE - description: Size of Y buffer in 16-bit words - bit_offset: 8 - bit_size: 8 - - name: EMPTY_WM - description: Watermark for buffer empty flag - bit_offset: 24 - bit_size: 2 + - name: Y_BASE + description: Base address of Y buffer + bit_offset: 0 + bit_size: 8 + - name: Y_BUF_SIZE + description: Size of Y buffer in 16-bit words + bit_offset: 8 + bit_size: 8 + - name: EMPTY_WM + description: Watermark for buffer empty flag + bit_offset: 24 + bit_size: 2 diff --git a/data/registers/fmc_v1x3.yaml b/data/registers/fmc_v1x3.yaml index 259d84b..af7a9f8 100644 --- a/data/registers/fmc_v1x3.yaml +++ b/data/registers/fmc_v1x3.yaml @@ -1,781 +1,780 @@ ---- block/FMC: description: Flexible memory controller items: - - name: BCR1 - description: SRAM/NOR-Flash chip-select control register 1 - byte_offset: 0 - fieldset: BCR1 - - name: BTR - description: SRAM/NOR-Flash chip-select timing register 1-4 - array: - len: 4 - stride: 8 - byte_offset: 4 - fieldset: BTR - - name: BCR - description: SRAM/NOR-Flash chip-select control register 2-4 - array: - len: 3 - stride: 8 - byte_offset: 8 - fieldset: BCR - - name: PCR - description: PC Card/NAND Flash control register 2-4 - array: - len: 3 - stride: 32 - byte_offset: 96 - fieldset: PCR - - name: SR - description: FIFO status and interrupt register 2-4 - array: - len: 3 - stride: 32 - byte_offset: 100 - fieldset: SR - - name: PMEM - description: Common memory space timing register 2-4 - array: - len: 3 - stride: 32 - byte_offset: 104 - fieldset: PMEM - - name: PATT - description: Attribute memory space timing register 2-4 - array: - len: 3 - stride: 32 - byte_offset: 108 - fieldset: PATT - - name: ECCR - description: ECC result register 2-3 - array: - len: 2 - stride: 32 - byte_offset: 116 - access: Read - fieldset: ECCR - - name: PIO4 - description: I/O space timing register 4 - byte_offset: 176 - fieldset: PIO4 - - name: BWTR - description: SRAM/NOR-Flash write timing registers 1-4 - array: - len: 4 - stride: 8 - byte_offset: 260 - fieldset: BWTR - - name: SDCR - description: SDRAM Control Register 1-2 - array: - len: 2 - stride: 4 - byte_offset: 320 - fieldset: SDCR - - name: SDTR - description: SDRAM Timing register 1-2 - array: - len: 2 - stride: 4 - byte_offset: 328 - fieldset: SDTR - - name: SDCMR - description: SDRAM Command Mode register - byte_offset: 336 - fieldset: SDCMR - - name: SDRTR - description: SDRAM Refresh Timer register - byte_offset: 340 - fieldset: SDRTR - - name: SDSR - description: SDRAM Status register - byte_offset: 344 - access: Read - fieldset: SDSR + - name: BCR1 + description: SRAM/NOR-Flash chip-select control register 1 + byte_offset: 0 + fieldset: BCR1 + - name: BTR + description: SRAM/NOR-Flash chip-select timing register 1-4 + array: + len: 4 + stride: 8 + byte_offset: 4 + fieldset: BTR + - name: BCR + description: SRAM/NOR-Flash chip-select control register 2-4 + array: + len: 3 + stride: 8 + byte_offset: 8 + fieldset: BCR + - name: PCR + description: PC Card/NAND Flash control register 2-4 + array: + len: 3 + stride: 32 + byte_offset: 96 + fieldset: PCR + - name: SR + description: FIFO status and interrupt register 2-4 + array: + len: 3 + stride: 32 + byte_offset: 100 + fieldset: SR + - name: PMEM + description: Common memory space timing register 2-4 + array: + len: 3 + stride: 32 + byte_offset: 104 + fieldset: PMEM + - name: PATT + description: Attribute memory space timing register 2-4 + array: + len: 3 + stride: 32 + byte_offset: 108 + fieldset: PATT + - name: ECCR + description: ECC result register 2-3 + array: + len: 2 + stride: 32 + byte_offset: 116 + access: Read + fieldset: ECCR + - name: PIO4 + description: I/O space timing register 4 + byte_offset: 176 + fieldset: PIO4 + - name: BWTR + description: SRAM/NOR-Flash write timing registers 1-4 + array: + len: 4 + stride: 8 + byte_offset: 260 + fieldset: BWTR + - name: SDCR + description: SDRAM Control Register 1-2 + array: + len: 2 + stride: 4 + byte_offset: 320 + fieldset: SDCR + - name: SDTR + description: SDRAM Timing register 1-2 + array: + len: 2 + stride: 4 + byte_offset: 328 + fieldset: SDTR + - name: SDCMR + description: SDRAM Command Mode register + byte_offset: 336 + fieldset: SDCMR + - name: SDRTR + description: SDRAM Refresh Timer register + byte_offset: 340 + fieldset: SDRTR + - name: SDSR + description: SDRAM Status register + byte_offset: 344 + access: Read + fieldset: SDSR fieldset/BCR: description: SRAM/NOR-Flash chip-select control register 2-4 fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WRAPMOD - description: WRAPMOD - bit_offset: 10 - bit_size: 1 - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WRAPMOD + description: WRAPMOD + bit_offset: 10 + bit_size: 1 + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 fieldset/BCR1: description: SRAM/NOR-Flash chip-select control register 1 fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WRAPMOD - description: WRAPMOD - bit_offset: 10 - bit_size: 1 - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 - - name: CCLKEN - description: Continuous clock enable - bit_offset: 20 - bit_size: 1 + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WRAPMOD + description: WRAPMOD + bit_offset: 10 + bit_size: 1 + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 + - name: CCLKEN + description: Continuous clock enable + bit_offset: 20 + bit_size: 1 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - - name: CLKDIV - description: Clock divide ratio (for FMC_CLK signal) - bit_offset: 20 - bit_size: 4 - - name: DATLAT - description: Data latency for synchronous memory - bit_offset: 24 - bit_size: 4 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 + - name: CLKDIV + description: Clock divide ratio (for FMC_CLK signal) + bit_offset: 20 + bit_size: 4 + - name: DATLAT + description: Data latency for synchronous memory + bit_offset: 24 + bit_size: 4 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD fieldset/BWTR: description: SRAM/NOR-Flash write timing registers fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD fieldset/ECCR: description: ECC result register fields: - - name: ECC - description: ECC computation result value - bit_offset: 0 - bit_size: 32 + - name: ECC + description: ECC computation result value + bit_offset: 0 + bit_size: 32 fieldset/PATT: description: Attribute memory space timing register fields: - - name: ATTSET - description: Attribute memory setup time - bit_offset: 0 - bit_size: 8 - - name: ATTWAIT - description: Attribute memory wait time - bit_offset: 8 - bit_size: 8 - - name: ATTHOLD - description: Attribute memory hold time - bit_offset: 16 - bit_size: 8 - - name: ATTHIZ - description: Attribute memory data bus Hi-Z time - bit_offset: 24 - bit_size: 8 + - name: ATTSET + description: Attribute memory setup time + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: Attribute memory wait time + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: Attribute memory hold time + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: Attribute memory data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/PCR: description: PC Card/NAND Flash control register fields: - - name: PWAITEN - description: Wait feature enable bit - bit_offset: 1 - bit_size: 1 - - name: PBKEN - description: NAND Flash memory bank enable bit - bit_offset: 2 - bit_size: 1 - - name: PTYP - description: Memory type - bit_offset: 3 - bit_size: 1 - enum: PTYP - - name: PWID - description: Data bus width - bit_offset: 4 - bit_size: 2 - enum: PWID - - name: ECCEN - description: ECC computation logic enable bit - bit_offset: 6 - bit_size: 1 - - name: TCLR - description: CLE to RE delay - bit_offset: 9 - bit_size: 4 - - name: TAR - description: ALE to RE delay - bit_offset: 13 - bit_size: 4 - - name: ECCPS - description: ECC page size - bit_offset: 17 - bit_size: 3 - enum: ECCPS + - name: PWAITEN + description: Wait feature enable bit + bit_offset: 1 + bit_size: 1 + - name: PBKEN + description: NAND Flash memory bank enable bit + bit_offset: 2 + bit_size: 1 + - name: PTYP + description: Memory type + bit_offset: 3 + bit_size: 1 + enum: PTYP + - name: PWID + description: Data bus width + bit_offset: 4 + bit_size: 2 + enum: PWID + - name: ECCEN + description: ECC computation logic enable bit + bit_offset: 6 + bit_size: 1 + - name: TCLR + description: CLE to RE delay + bit_offset: 9 + bit_size: 4 + - name: TAR + description: ALE to RE delay + bit_offset: 13 + bit_size: 4 + - name: ECCPS + description: ECC page size + bit_offset: 17 + bit_size: 3 + enum: ECCPS fieldset/PIO4: description: I/O space timing register 4 fields: - - name: IOSETx - description: IOSETx - bit_offset: 0 - bit_size: 8 - - name: IOWAITx - description: IOWAITx - bit_offset: 8 - bit_size: 8 - - name: IOHOLDx - description: IOHOLDx - bit_offset: 16 - bit_size: 8 - - name: IOHIZx - description: IOHIZx - bit_offset: 24 - bit_size: 8 + - name: IOSETx + description: IOSETx + bit_offset: 0 + bit_size: 8 + - name: IOWAITx + description: IOWAITx + bit_offset: 8 + bit_size: 8 + - name: IOHOLDx + description: IOHOLDx + bit_offset: 16 + bit_size: 8 + - name: IOHIZx + description: IOHIZx + bit_offset: 24 + bit_size: 8 fieldset/PMEM: description: Common memory space timing register fields: - - name: MEMSET - description: Common memory x setup time - bit_offset: 0 - bit_size: 8 - - name: MEMWAIT - description: Common memory wait time - bit_offset: 8 - bit_size: 8 - - name: MEMHOLD - description: Common memory hold time - bit_offset: 16 - bit_size: 8 - - name: MEMHIZ - description: Common memory x data bus Hi-Z time - bit_offset: 24 - bit_size: 8 + - name: MEMSET + description: Common memory x setup time + bit_offset: 0 + bit_size: 8 + - name: MEMWAIT + description: Common memory wait time + bit_offset: 8 + bit_size: 8 + - name: MEMHOLD + description: Common memory hold time + bit_offset: 16 + bit_size: 8 + - name: MEMHIZ + description: Common memory x data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/SDCMR: description: SDRAM Command Mode register fields: - - name: MODE - description: Command mode - bit_offset: 0 - bit_size: 3 - enum: MODE - - name: CTB2 - description: Command target bank 2 - bit_offset: 3 - bit_size: 1 - - name: CTB1 - description: Command target bank 1 - bit_offset: 4 - bit_size: 1 - - name: NRFS - description: Number of Auto-refresh - bit_offset: 5 - bit_size: 4 - - name: MRD - description: Mode Register definition - bit_offset: 9 - bit_size: 13 + - name: MODE + description: Command mode + bit_offset: 0 + bit_size: 3 + enum: MODE + - name: CTB2 + description: Command target bank 2 + bit_offset: 3 + bit_size: 1 + - name: CTB1 + description: Command target bank 1 + bit_offset: 4 + bit_size: 1 + - name: NRFS + description: Number of Auto-refresh + bit_offset: 5 + bit_size: 4 + - name: MRD + description: Mode Register definition + bit_offset: 9 + bit_size: 13 fieldset/SDCR: description: SDRAM Control Register fields: - - name: NC - description: Number of column address bits - bit_offset: 0 - bit_size: 2 - enum: NC - - name: NR - description: Number of row address bits - bit_offset: 2 - bit_size: 2 - enum: NR - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: NB - description: Number of internal banks - bit_offset: 6 - bit_size: 1 - enum: NB - - name: CAS - description: CAS latency - bit_offset: 7 - bit_size: 2 - enum: CAS - - name: WP - description: Write protection - bit_offset: 9 - bit_size: 1 - - name: SDCLK - description: SDRAM clock configuration - bit_offset: 10 - bit_size: 2 - enum: SDCLK - - name: RBURST - description: Burst read - bit_offset: 12 - bit_size: 1 - - name: RPIPE - description: Read pipe - bit_offset: 13 - bit_size: 2 - enum: RPIPE + - name: NC + description: Number of column address bits + bit_offset: 0 + bit_size: 2 + enum: NC + - name: NR + description: Number of row address bits + bit_offset: 2 + bit_size: 2 + enum: NR + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: NB + description: Number of internal banks + bit_offset: 6 + bit_size: 1 + enum: NB + - name: CAS + description: CAS latency + bit_offset: 7 + bit_size: 2 + enum: CAS + - name: WP + description: Write protection + bit_offset: 9 + bit_size: 1 + - name: SDCLK + description: SDRAM clock configuration + bit_offset: 10 + bit_size: 2 + enum: SDCLK + - name: RBURST + description: Burst read + bit_offset: 12 + bit_size: 1 + - name: RPIPE + description: Read pipe + bit_offset: 13 + bit_size: 2 + enum: RPIPE fieldset/SDRTR: description: SDRAM Refresh Timer register fields: - - name: CRE - description: Clear Refresh error flag - bit_offset: 0 - bit_size: 1 - - name: COUNT - description: Refresh Timer Count - bit_offset: 1 - bit_size: 13 - - name: REIE - description: RES Interrupt Enable - bit_offset: 14 - bit_size: 1 + - name: CRE + description: Clear Refresh error flag + bit_offset: 0 + bit_size: 1 + - name: COUNT + description: Refresh Timer Count + bit_offset: 1 + bit_size: 13 + - name: REIE + description: RES Interrupt Enable + bit_offset: 14 + bit_size: 1 fieldset/SDSR: description: SDRAM Status register fields: - - name: RE - description: Refresh error flag - bit_offset: 0 - bit_size: 1 - - name: MODES1 - description: Status Mode for Bank 1 - bit_offset: 1 - bit_size: 2 - enum: MODES - - name: MODES2 - description: Status Mode for Bank 2 - bit_offset: 3 - bit_size: 2 - enum: MODES - - name: BUSY - description: Busy status - bit_offset: 5 - bit_size: 1 + - name: RE + description: Refresh error flag + bit_offset: 0 + bit_size: 1 + - name: MODES1 + description: Status Mode for Bank 1 + bit_offset: 1 + bit_size: 2 + enum: MODES + - name: MODES2 + description: Status Mode for Bank 2 + bit_offset: 3 + bit_size: 2 + enum: MODES + - name: BUSY + description: Busy status + bit_offset: 5 + bit_size: 1 fieldset/SDTR: description: SDRAM Timing register fields: - - name: TMRD - description: Load Mode Register to Active - bit_offset: 0 - bit_size: 4 - - name: TXSR - description: Exit self-refresh delay - bit_offset: 4 - bit_size: 4 - - name: TRAS - description: Self refresh time - bit_offset: 8 - bit_size: 4 - - name: TRC - description: Row cycle delay - bit_offset: 12 - bit_size: 4 - - name: TWR - description: Recovery delay - bit_offset: 16 - bit_size: 4 - - name: TRP - description: Row precharge delay - bit_offset: 20 - bit_size: 4 - - name: TRCD - description: Row to column delay - bit_offset: 24 - bit_size: 4 + - name: TMRD + description: Load Mode Register to Active + bit_offset: 0 + bit_size: 4 + - name: TXSR + description: Exit self-refresh delay + bit_offset: 4 + bit_size: 4 + - name: TRAS + description: Self refresh time + bit_offset: 8 + bit_size: 4 + - name: TRC + description: Row cycle delay + bit_offset: 12 + bit_size: 4 + - name: TWR + description: Recovery delay + bit_offset: 16 + bit_size: 4 + - name: TRP + description: Row precharge delay + bit_offset: 20 + bit_size: 4 + - name: TRCD + description: Row to column delay + bit_offset: 24 + bit_size: 4 fieldset/SR: description: FIFO status and interrupt register fields: - - name: IRS - description: Interrupt rising edge status - bit_offset: 0 - bit_size: 1 - - name: ILS - description: Interrupt high-level status - bit_offset: 1 - bit_size: 1 - - name: IFS - description: Interrupt falling edge status - bit_offset: 2 - bit_size: 1 - - name: IREN - description: Interrupt rising edge detection enable bit - bit_offset: 3 - bit_size: 1 - - name: ILEN - description: Interrupt high-level detection enable bit - bit_offset: 4 - bit_size: 1 - - name: IFEN - description: Interrupt falling edge detection enable bit - bit_offset: 5 - bit_size: 1 - - name: FEMPT - description: FIFO empty status - bit_offset: 6 - bit_size: 1 + - name: IRS + description: Interrupt rising edge status + bit_offset: 0 + bit_size: 1 + - name: ILS + description: Interrupt high-level status + bit_offset: 1 + bit_size: 1 + - name: IFS + description: Interrupt falling edge status + bit_offset: 2 + bit_size: 1 + - name: IREN + description: Interrupt rising edge detection enable bit + bit_offset: 3 + bit_size: 1 + - name: ILEN + description: Interrupt high-level detection enable bit + bit_offset: 4 + bit_size: 1 + - name: IFEN + description: Interrupt falling edge detection enable bit + bit_offset: 5 + bit_size: 1 + - name: FEMPT + description: FIFO empty status + bit_offset: 6 + bit_size: 1 enum/ACCMOD: bit_size: 2 variants: - - name: A - description: Access mode A - value: 0 - - name: B - description: Access mode B - value: 1 - - name: C - description: Access mode C - value: 2 - - name: D - description: Access mode D - value: 3 + - name: A + description: Access mode A + value: 0 + - name: B + description: Access mode B + value: 1 + - name: C + description: Access mode C + value: 2 + - name: D + description: Access mode D + value: 3 enum/CAS: bit_size: 2 variants: - - name: Clocks1 - description: 1 cycle - value: 1 - - name: Clocks2 - description: 2 cycles - value: 2 - - name: Clocks3 - description: 3 cycles - value: 3 + - name: Clocks1 + description: 1 cycle + value: 1 + - name: Clocks2 + description: 2 cycles + value: 2 + - name: Clocks3 + description: 3 cycles + value: 3 enum/CPSIZE: bit_size: 3 variants: - - name: NoBurstSplit - description: No burst split when crossing page boundary - value: 0 - - name: Bytes128 - description: 128 bytes CRAM page size - value: 1 - - name: Bytes256 - description: 256 bytes CRAM page size - value: 2 - - name: Bytes512 - description: 512 bytes CRAM page size - value: 3 - - name: Bytes1024 - description: 1024 bytes CRAM page size - value: 4 + - name: NoBurstSplit + description: No burst split when crossing page boundary + value: 0 + - name: Bytes128 + description: 128 bytes CRAM page size + value: 1 + - name: Bytes256 + description: 256 bytes CRAM page size + value: 2 + - name: Bytes512 + description: 512 bytes CRAM page size + value: 3 + - name: Bytes1024 + description: 1024 bytes CRAM page size + value: 4 enum/ECCPS: bit_size: 3 variants: - - name: Bytes256 - description: ECC page size 256 bytes - value: 0 - - name: Bytes512 - description: ECC page size 512 bytes - value: 1 - - name: Bytes1024 - description: ECC page size 1024 bytes - value: 2 - - name: Bytes2048 - description: ECC page size 2048 bytes - value: 3 - - name: Bytes4096 - description: ECC page size 4096 bytes - value: 4 - - name: Bytes8192 - description: ECC page size 8192 bytes - value: 5 + - name: Bytes256 + description: ECC page size 256 bytes + value: 0 + - name: Bytes512 + description: ECC page size 512 bytes + value: 1 + - name: Bytes1024 + description: ECC page size 1024 bytes + value: 2 + - name: Bytes2048 + description: ECC page size 2048 bytes + value: 3 + - name: Bytes4096 + description: ECC page size 4096 bytes + value: 4 + - name: Bytes8192 + description: ECC page size 8192 bytes + value: 5 enum/MODE: bit_size: 3 variants: - - name: Normal - description: Normal Mode - value: 0 - - name: ClockConfigurationEnable - description: Clock Configuration Enable - value: 1 - - name: PALL - description: PALL (All Bank Precharge) command - value: 2 - - name: AutoRefreshCommand - description: Auto-refresh command - value: 3 - - name: LoadModeRegister - description: Load Mode Resgier - value: 4 - - name: SelfRefreshCommand - description: Self-refresh command - value: 5 - - name: PowerDownCommand - description: Power-down command - value: 6 + - name: Normal + description: Normal Mode + value: 0 + - name: ClockConfigurationEnable + description: Clock Configuration Enable + value: 1 + - name: PALL + description: PALL (All Bank Precharge) command + value: 2 + - name: AutoRefreshCommand + description: Auto-refresh command + value: 3 + - name: LoadModeRegister + description: Load Mode Resgier + value: 4 + - name: SelfRefreshCommand + description: Self-refresh command + value: 5 + - name: PowerDownCommand + description: Power-down command + value: 6 enum/MODES: bit_size: 2 variants: - - name: Normal - description: Normal Mode - value: 0 - - name: SelfRefresh - description: Self-refresh mode - value: 1 - - name: PowerDown - description: Power-down mode - value: 2 + - name: Normal + description: Normal Mode + value: 0 + - name: SelfRefresh + description: Self-refresh mode + value: 1 + - name: PowerDown + description: Power-down mode + value: 2 enum/MTYP: bit_size: 2 variants: - - name: SRAM - description: SRAM memory type - value: 0 - - name: PSRAM - description: PSRAM (CRAM) memory type - value: 1 - - name: Flash - description: NOR Flash/OneNAND Flash - value: 2 + - name: SRAM + description: SRAM memory type + value: 0 + - name: PSRAM + description: PSRAM (CRAM) memory type + value: 1 + - name: Flash + description: NOR Flash/OneNAND Flash + value: 2 enum/MWID: bit_size: 2 variants: - - name: Bits8 - description: Memory data bus width 8 bits - value: 0 - - name: Bits16 - description: Memory data bus width 16 bits - value: 1 - - name: Bits32 - description: Memory data bus width 32 bits - value: 2 + - name: Bits8 + description: Memory data bus width 8 bits + value: 0 + - name: Bits16 + description: Memory data bus width 16 bits + value: 1 + - name: Bits32 + description: Memory data bus width 32 bits + value: 2 enum/NB: bit_size: 1 variants: - - name: NB2 - description: Two internal Banks - value: 0 - - name: NB4 - description: Four internal Banks - value: 1 + - name: NB2 + description: Two internal Banks + value: 0 + - name: NB4 + description: Four internal Banks + value: 1 enum/NC: bit_size: 2 variants: - - name: Bits8 - description: 8 bits - value: 0 - - name: Bits9 - description: 9 bits - value: 1 - - name: Bits10 - description: 10 bits - value: 2 - - name: Bits11 - description: 11 bits - value: 3 + - name: Bits8 + description: 8 bits + value: 0 + - name: Bits9 + description: 9 bits + value: 1 + - name: Bits10 + description: 10 bits + value: 2 + - name: Bits11 + description: 11 bits + value: 3 enum/NR: bit_size: 2 variants: - - name: Bits11 - description: 11 bits - value: 0 - - name: Bits12 - description: 12 bits - value: 1 - - name: Bits13 - description: 13 bits - value: 2 + - name: Bits11 + description: 11 bits + value: 0 + - name: Bits12 + description: 12 bits + value: 1 + - name: Bits13 + description: 13 bits + value: 2 enum/PTYP: bit_size: 1 variants: - - name: NANDFlash - description: NAND Flash - value: 1 + - name: NANDFlash + description: NAND Flash + value: 1 enum/PWID: bit_size: 2 variants: - - name: Bits8 - description: External memory device width 8 bits - value: 0 - - name: Bits16 - description: External memory device width 16 bits - value: 1 + - name: Bits8 + description: External memory device width 8 bits + value: 0 + - name: Bits16 + description: External memory device width 16 bits + value: 1 enum/RPIPE: bit_size: 2 variants: - - name: NoDelay - description: No clock cycle delay - value: 0 - - name: Clocks1 - description: One clock cycle delay - value: 1 - - name: Clocks2 - description: Two clock cycles delay - value: 2 + - name: NoDelay + description: No clock cycle delay + value: 0 + - name: Clocks1 + description: One clock cycle delay + value: 1 + - name: Clocks2 + description: Two clock cycles delay + value: 2 enum/SDCLK: bit_size: 2 variants: - - name: Disabled - description: SDCLK clock disabled - value: 0 - - name: Div2 - description: SDCLK period = 2 x HCLK period - value: 2 - - name: Div3 - description: SDCLK period = 3 x HCLK period - value: 3 + - name: Disabled + description: SDCLK clock disabled + value: 0 + - name: Div2 + description: SDCLK period = 2 x HCLK period + value: 2 + - name: Div3 + description: SDCLK period = 3 x HCLK period + value: 3 enum/WAITCFG: bit_size: 1 variants: - - name: BeforeWaitState - description: NWAIT signal is active one data cycle before wait state - value: 0 - - name: DuringWaitState - description: NWAIT signal is active during wait state - value: 1 + - name: BeforeWaitState + description: NWAIT signal is active one data cycle before wait state + value: 0 + - name: DuringWaitState + description: NWAIT signal is active during wait state + value: 1 enum/WAITPOL: bit_size: 1 variants: - - name: ActiveLow - description: NWAIT active low - value: 0 - - name: ActiveHigh - description: NWAIT active high - value: 1 + - name: ActiveLow + description: NWAIT active low + value: 0 + - name: ActiveHigh + description: NWAIT active high + value: 1 diff --git a/data/registers/fmc_v2x1.yaml b/data/registers/fmc_v2x1.yaml index ad43c48..8b6e980 100644 --- a/data/registers/fmc_v2x1.yaml +++ b/data/registers/fmc_v2x1.yaml @@ -1,739 +1,738 @@ ---- block/FMC: description: Flexible memory controller items: - - name: BCR1 - description: SRAM/NOR-Flash chip-select control register 1 - byte_offset: 0 - fieldset: BCR1 - - name: BTR - description: SRAM/NOR-Flash chip-select timing register 1-4 - array: - len: 4 - stride: 8 - byte_offset: 4 - fieldset: BTR - - name: BCR - description: SRAM/NOR-Flash chip-select control register 2-4 - array: - len: 3 - stride: 8 - byte_offset: 8 - fieldset: BCR - - name: PCR - description: PC Card/NAND Flash control register - byte_offset: 128 - fieldset: PCR - - name: SR - description: FIFO status and interrupt register - byte_offset: 132 - fieldset: SR - - name: PMEM - description: Common memory space timing register - byte_offset: 136 - fieldset: PMEM - - name: PATT - description: Attribute memory space timing register - byte_offset: 140 - fieldset: PATT - - name: ECCR - description: ECC result register - byte_offset: 148 - access: Read - fieldset: ECCR - - name: BWTR - description: SRAM/NOR-Flash write timing registers 1-4 - array: - len: 4 - stride: 8 - byte_offset: 260 - fieldset: BWTR - - name: SDCR - description: SDRAM Control Register 1-2 - array: - len: 2 - stride: 4 - byte_offset: 320 - fieldset: SDCR - - name: SDTR - description: SDRAM Timing register 1-2 - array: - len: 2 - stride: 4 - byte_offset: 328 - fieldset: SDTR - - name: SDCMR - description: SDRAM Command Mode register - byte_offset: 336 - fieldset: SDCMR - - name: SDRTR - description: SDRAM Refresh Timer register - byte_offset: 340 - fieldset: SDRTR - - name: SDSR - description: SDRAM Status register - byte_offset: 344 - access: Read - fieldset: SDSR + - name: BCR1 + description: SRAM/NOR-Flash chip-select control register 1 + byte_offset: 0 + fieldset: BCR1 + - name: BTR + description: SRAM/NOR-Flash chip-select timing register 1-4 + array: + len: 4 + stride: 8 + byte_offset: 4 + fieldset: BTR + - name: BCR + description: SRAM/NOR-Flash chip-select control register 2-4 + array: + len: 3 + stride: 8 + byte_offset: 8 + fieldset: BCR + - name: PCR + description: PC Card/NAND Flash control register + byte_offset: 128 + fieldset: PCR + - name: SR + description: FIFO status and interrupt register + byte_offset: 132 + fieldset: SR + - name: PMEM + description: Common memory space timing register + byte_offset: 136 + fieldset: PMEM + - name: PATT + description: Attribute memory space timing register + byte_offset: 140 + fieldset: PATT + - name: ECCR + description: ECC result register + byte_offset: 148 + access: Read + fieldset: ECCR + - name: BWTR + description: SRAM/NOR-Flash write timing registers 1-4 + array: + len: 4 + stride: 8 + byte_offset: 260 + fieldset: BWTR + - name: SDCR + description: SDRAM Control Register 1-2 + array: + len: 2 + stride: 4 + byte_offset: 320 + fieldset: SDCR + - name: SDTR + description: SDRAM Timing register 1-2 + array: + len: 2 + stride: 4 + byte_offset: 328 + fieldset: SDTR + - name: SDCMR + description: SDRAM Command Mode register + byte_offset: 336 + fieldset: SDCMR + - name: SDRTR + description: SDRAM Refresh Timer register + byte_offset: 340 + fieldset: SDRTR + - name: SDSR + description: SDRAM Status register + byte_offset: 344 + access: Read + fieldset: SDSR fieldset/BCR: description: SRAM/NOR-Flash chip-select control register 2-4 fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 fieldset/BCR1: description: SRAM/NOR-Flash chip-select control register 1 fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 - - name: CCLKEN - description: Continuous clock enable - bit_offset: 20 - bit_size: 1 - - name: WFDIS - description: Write FIFO disable - bit_offset: 21 - bit_size: 1 + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 + - name: CCLKEN + description: Continuous clock enable + bit_offset: 20 + bit_size: 1 + - name: WFDIS + description: Write FIFO disable + bit_offset: 21 + bit_size: 1 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - - name: CLKDIV - description: Clock divide ratio (for FMC_CLK signal) - bit_offset: 20 - bit_size: 4 - - name: DATLAT - description: Data latency for synchronous memory - bit_offset: 24 - bit_size: 4 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 + - name: CLKDIV + description: Clock divide ratio (for FMC_CLK signal) + bit_offset: 20 + bit_size: 4 + - name: DATLAT + description: Data latency for synchronous memory + bit_offset: 24 + bit_size: 4 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD fieldset/BWTR: description: SRAM/NOR-Flash write timing registers fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD fieldset/ECCR: description: ECC result register fields: - - name: ECC - description: ECC computation result value - bit_offset: 0 - bit_size: 32 + - name: ECC + description: ECC computation result value + bit_offset: 0 + bit_size: 32 fieldset/PATT: description: Attribute memory space timing register fields: - - name: ATTSET - description: Attribute memory setup time - bit_offset: 0 - bit_size: 8 - - name: ATTWAIT - description: Attribute memory wait time - bit_offset: 8 - bit_size: 8 - - name: ATTHOLD - description: Attribute memory hold time - bit_offset: 16 - bit_size: 8 - - name: ATTHIZ - description: Attribute memory data bus Hi-Z time - bit_offset: 24 - bit_size: 8 + - name: ATTSET + description: Attribute memory setup time + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: Attribute memory wait time + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: Attribute memory hold time + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: Attribute memory data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/PCR: description: PC Card/NAND Flash control register fields: - - name: PWAITEN - description: Wait feature enable bit - bit_offset: 1 - bit_size: 1 - - name: PBKEN - description: NAND Flash memory bank enable bit - bit_offset: 2 - bit_size: 1 - - name: PTYP - description: Memory type - bit_offset: 3 - bit_size: 1 - enum: PTYP - - name: PWID - description: Data bus width - bit_offset: 4 - bit_size: 2 - enum: PWID - - name: ECCEN - description: ECC computation logic enable bit - bit_offset: 6 - bit_size: 1 - - name: TCLR - description: CLE to RE delay - bit_offset: 9 - bit_size: 4 - - name: TAR - description: ALE to RE delay - bit_offset: 13 - bit_size: 4 - - name: ECCPS - description: ECC page size - bit_offset: 17 - bit_size: 3 - enum: ECCPS + - name: PWAITEN + description: Wait feature enable bit + bit_offset: 1 + bit_size: 1 + - name: PBKEN + description: NAND Flash memory bank enable bit + bit_offset: 2 + bit_size: 1 + - name: PTYP + description: Memory type + bit_offset: 3 + bit_size: 1 + enum: PTYP + - name: PWID + description: Data bus width + bit_offset: 4 + bit_size: 2 + enum: PWID + - name: ECCEN + description: ECC computation logic enable bit + bit_offset: 6 + bit_size: 1 + - name: TCLR + description: CLE to RE delay + bit_offset: 9 + bit_size: 4 + - name: TAR + description: ALE to RE delay + bit_offset: 13 + bit_size: 4 + - name: ECCPS + description: ECC page size + bit_offset: 17 + bit_size: 3 + enum: ECCPS fieldset/PMEM: description: Common memory space timing register fields: - - name: MEMSET - description: Common memory x setup time - bit_offset: 0 - bit_size: 8 - - name: MEMWAIT - description: Common memory wait time - bit_offset: 8 - bit_size: 8 - - name: MEMHOLD - description: Common memory hold time - bit_offset: 16 - bit_size: 8 - - name: MEMHIZ - description: Common memory x data bus Hi-Z time - bit_offset: 24 - bit_size: 8 + - name: MEMSET + description: Common memory x setup time + bit_offset: 0 + bit_size: 8 + - name: MEMWAIT + description: Common memory wait time + bit_offset: 8 + bit_size: 8 + - name: MEMHOLD + description: Common memory hold time + bit_offset: 16 + bit_size: 8 + - name: MEMHIZ + description: Common memory x data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/SDCMR: description: SDRAM Command Mode register fields: - - name: MODE - description: Command mode - bit_offset: 0 - bit_size: 3 - enum: MODE - - name: CTB2 - description: Command target bank 2 - bit_offset: 3 - bit_size: 1 - - name: CTB1 - description: Command target bank 1 - bit_offset: 4 - bit_size: 1 - - name: NRFS - description: Number of Auto-refresh - bit_offset: 5 - bit_size: 4 - - name: MRD - description: Mode Register definition - bit_offset: 9 - bit_size: 13 + - name: MODE + description: Command mode + bit_offset: 0 + bit_size: 3 + enum: MODE + - name: CTB2 + description: Command target bank 2 + bit_offset: 3 + bit_size: 1 + - name: CTB1 + description: Command target bank 1 + bit_offset: 4 + bit_size: 1 + - name: NRFS + description: Number of Auto-refresh + bit_offset: 5 + bit_size: 4 + - name: MRD + description: Mode Register definition + bit_offset: 9 + bit_size: 13 fieldset/SDCR: description: SDRAM Control Register fields: - - name: NC - description: Number of column address bits - bit_offset: 0 - bit_size: 2 - enum: NC - - name: NR - description: Number of row address bits - bit_offset: 2 - bit_size: 2 - enum: NR - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: NB - description: Number of internal banks - bit_offset: 6 - bit_size: 1 - enum: NB - - name: CAS - description: CAS latency - bit_offset: 7 - bit_size: 2 - enum: CAS - - name: WP - description: Write protection - bit_offset: 9 - bit_size: 1 - - name: SDCLK - description: SDRAM clock configuration - bit_offset: 10 - bit_size: 2 - enum: SDCLK - - name: RBURST - description: Burst read - bit_offset: 12 - bit_size: 1 - - name: RPIPE - description: Read pipe - bit_offset: 13 - bit_size: 2 - enum: RPIPE + - name: NC + description: Number of column address bits + bit_offset: 0 + bit_size: 2 + enum: NC + - name: NR + description: Number of row address bits + bit_offset: 2 + bit_size: 2 + enum: NR + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: NB + description: Number of internal banks + bit_offset: 6 + bit_size: 1 + enum: NB + - name: CAS + description: CAS latency + bit_offset: 7 + bit_size: 2 + enum: CAS + - name: WP + description: Write protection + bit_offset: 9 + bit_size: 1 + - name: SDCLK + description: SDRAM clock configuration + bit_offset: 10 + bit_size: 2 + enum: SDCLK + - name: RBURST + description: Burst read + bit_offset: 12 + bit_size: 1 + - name: RPIPE + description: Read pipe + bit_offset: 13 + bit_size: 2 + enum: RPIPE fieldset/SDRTR: description: SDRAM Refresh Timer register fields: - - name: CRE - description: Clear Refresh error flag - bit_offset: 0 - bit_size: 1 - - name: COUNT - description: Refresh Timer Count - bit_offset: 1 - bit_size: 13 - - name: REIE - description: RES Interrupt Enable - bit_offset: 14 - bit_size: 1 + - name: CRE + description: Clear Refresh error flag + bit_offset: 0 + bit_size: 1 + - name: COUNT + description: Refresh Timer Count + bit_offset: 1 + bit_size: 13 + - name: REIE + description: RES Interrupt Enable + bit_offset: 14 + bit_size: 1 fieldset/SDSR: description: SDRAM Status register fields: - - name: RE - description: Refresh error flag - bit_offset: 0 - bit_size: 1 - - name: MODES1 - description: Status Mode for Bank 1 - bit_offset: 1 - bit_size: 2 - enum: MODES - - name: MODES2 - description: Status Mode for Bank 2 - bit_offset: 3 - bit_size: 2 - enum: MODES - - name: BUSY - description: Busy status - bit_offset: 5 - bit_size: 1 + - name: RE + description: Refresh error flag + bit_offset: 0 + bit_size: 1 + - name: MODES1 + description: Status Mode for Bank 1 + bit_offset: 1 + bit_size: 2 + enum: MODES + - name: MODES2 + description: Status Mode for Bank 2 + bit_offset: 3 + bit_size: 2 + enum: MODES + - name: BUSY + description: Busy status + bit_offset: 5 + bit_size: 1 fieldset/SDTR: description: SDRAM Timing register fields: - - name: TMRD - description: Load Mode Register to Active - bit_offset: 0 - bit_size: 4 - - name: TXSR - description: Exit self-refresh delay - bit_offset: 4 - bit_size: 4 - - name: TRAS - description: Self refresh time - bit_offset: 8 - bit_size: 4 - - name: TRC - description: Row cycle delay - bit_offset: 12 - bit_size: 4 - - name: TWR - description: Recovery delay - bit_offset: 16 - bit_size: 4 - - name: TRP - description: Row precharge delay - bit_offset: 20 - bit_size: 4 - - name: TRCD - description: Row to column delay - bit_offset: 24 - bit_size: 4 + - name: TMRD + description: Load Mode Register to Active + bit_offset: 0 + bit_size: 4 + - name: TXSR + description: Exit self-refresh delay + bit_offset: 4 + bit_size: 4 + - name: TRAS + description: Self refresh time + bit_offset: 8 + bit_size: 4 + - name: TRC + description: Row cycle delay + bit_offset: 12 + bit_size: 4 + - name: TWR + description: Recovery delay + bit_offset: 16 + bit_size: 4 + - name: TRP + description: Row precharge delay + bit_offset: 20 + bit_size: 4 + - name: TRCD + description: Row to column delay + bit_offset: 24 + bit_size: 4 fieldset/SR: description: FIFO status and interrupt register fields: - - name: IRS - description: Interrupt rising edge status - bit_offset: 0 - bit_size: 1 - - name: ILS - description: Interrupt high-level status - bit_offset: 1 - bit_size: 1 - - name: IFS - description: Interrupt falling edge status - bit_offset: 2 - bit_size: 1 - - name: IREN - description: Interrupt rising edge detection enable bit - bit_offset: 3 - bit_size: 1 - - name: ILEN - description: Interrupt high-level detection enable bit - bit_offset: 4 - bit_size: 1 - - name: IFEN - description: Interrupt falling edge detection enable bit - bit_offset: 5 - bit_size: 1 - - name: FEMPT - description: FIFO empty status - bit_offset: 6 - bit_size: 1 + - name: IRS + description: Interrupt rising edge status + bit_offset: 0 + bit_size: 1 + - name: ILS + description: Interrupt high-level status + bit_offset: 1 + bit_size: 1 + - name: IFS + description: Interrupt falling edge status + bit_offset: 2 + bit_size: 1 + - name: IREN + description: Interrupt rising edge detection enable bit + bit_offset: 3 + bit_size: 1 + - name: ILEN + description: Interrupt high-level detection enable bit + bit_offset: 4 + bit_size: 1 + - name: IFEN + description: Interrupt falling edge detection enable bit + bit_offset: 5 + bit_size: 1 + - name: FEMPT + description: FIFO empty status + bit_offset: 6 + bit_size: 1 enum/ACCMOD: bit_size: 2 variants: - - name: A - description: Access mode A - value: 0 - - name: B - description: Access mode B - value: 1 - - name: C - description: Access mode C - value: 2 - - name: D - description: Access mode D - value: 3 + - name: A + description: Access mode A + value: 0 + - name: B + description: Access mode B + value: 1 + - name: C + description: Access mode C + value: 2 + - name: D + description: Access mode D + value: 3 enum/CAS: bit_size: 2 variants: - - name: Clocks1 - description: 1 cycle - value: 1 - - name: Clocks2 - description: 2 cycles - value: 2 - - name: Clocks3 - description: 3 cycles - value: 3 + - name: Clocks1 + description: 1 cycle + value: 1 + - name: Clocks2 + description: 2 cycles + value: 2 + - name: Clocks3 + description: 3 cycles + value: 3 enum/CPSIZE: bit_size: 3 variants: - - name: NoBurstSplit - description: No burst split when crossing page boundary - value: 0 - - name: Bytes128 - description: 128 bytes CRAM page size - value: 1 - - name: Bytes256 - description: 256 bytes CRAM page size - value: 2 - - name: Bytes512 - description: 512 bytes CRAM page size - value: 3 - - name: Bytes1024 - description: 1024 bytes CRAM page size - value: 4 + - name: NoBurstSplit + description: No burst split when crossing page boundary + value: 0 + - name: Bytes128 + description: 128 bytes CRAM page size + value: 1 + - name: Bytes256 + description: 256 bytes CRAM page size + value: 2 + - name: Bytes512 + description: 512 bytes CRAM page size + value: 3 + - name: Bytes1024 + description: 1024 bytes CRAM page size + value: 4 enum/ECCPS: bit_size: 3 variants: - - name: Bytes256 - description: ECC page size 256 bytes - value: 0 - - name: Bytes512 - description: ECC page size 512 bytes - value: 1 - - name: Bytes1024 - description: ECC page size 1024 bytes - value: 2 - - name: Bytes2048 - description: ECC page size 2048 bytes - value: 3 - - name: Bytes4096 - description: ECC page size 4096 bytes - value: 4 - - name: Bytes8192 - description: ECC page size 8192 bytes - value: 5 + - name: Bytes256 + description: ECC page size 256 bytes + value: 0 + - name: Bytes512 + description: ECC page size 512 bytes + value: 1 + - name: Bytes1024 + description: ECC page size 1024 bytes + value: 2 + - name: Bytes2048 + description: ECC page size 2048 bytes + value: 3 + - name: Bytes4096 + description: ECC page size 4096 bytes + value: 4 + - name: Bytes8192 + description: ECC page size 8192 bytes + value: 5 enum/MODE: bit_size: 3 variants: - - name: Normal - description: Normal Mode - value: 0 - - name: ClockConfigurationEnable - description: Clock Configuration Enable - value: 1 - - name: PALL - description: PALL (All Bank Precharge) command - value: 2 - - name: AutoRefreshCommand - description: Auto-refresh command - value: 3 - - name: LoadModeRegister - description: Load Mode Resgier - value: 4 - - name: SelfRefreshCommand - description: Self-refresh command - value: 5 - - name: PowerDownCommand - description: Power-down command - value: 6 + - name: Normal + description: Normal Mode + value: 0 + - name: ClockConfigurationEnable + description: Clock Configuration Enable + value: 1 + - name: PALL + description: PALL (All Bank Precharge) command + value: 2 + - name: AutoRefreshCommand + description: Auto-refresh command + value: 3 + - name: LoadModeRegister + description: Load Mode Resgier + value: 4 + - name: SelfRefreshCommand + description: Self-refresh command + value: 5 + - name: PowerDownCommand + description: Power-down command + value: 6 enum/MODES: bit_size: 2 variants: - - name: Normal - description: Normal Mode - value: 0 - - name: SelfRefresh - description: Self-refresh mode - value: 1 - - name: PowerDown - description: Power-down mode - value: 2 + - name: Normal + description: Normal Mode + value: 0 + - name: SelfRefresh + description: Self-refresh mode + value: 1 + - name: PowerDown + description: Power-down mode + value: 2 enum/MTYP: bit_size: 2 variants: - - name: SRAM - description: SRAM memory type - value: 0 - - name: PSRAM - description: PSRAM (CRAM) memory type - value: 1 - - name: Flash - description: NOR Flash/OneNAND Flash - value: 2 + - name: SRAM + description: SRAM memory type + value: 0 + - name: PSRAM + description: PSRAM (CRAM) memory type + value: 1 + - name: Flash + description: NOR Flash/OneNAND Flash + value: 2 enum/MWID: bit_size: 2 variants: - - name: Bits8 - description: Memory data bus width 8 bits - value: 0 - - name: Bits16 - description: Memory data bus width 16 bits - value: 1 - - name: Bits32 - description: Memory data bus width 32 bits - value: 2 + - name: Bits8 + description: Memory data bus width 8 bits + value: 0 + - name: Bits16 + description: Memory data bus width 16 bits + value: 1 + - name: Bits32 + description: Memory data bus width 32 bits + value: 2 enum/NB: bit_size: 1 variants: - - name: NB2 - description: Two internal Banks - value: 0 - - name: NB4 - description: Four internal Banks - value: 1 + - name: NB2 + description: Two internal Banks + value: 0 + - name: NB4 + description: Four internal Banks + value: 1 enum/NC: bit_size: 2 variants: - - name: Bits8 - description: 8 bits - value: 0 - - name: Bits9 - description: 9 bits - value: 1 - - name: Bits10 - description: 10 bits - value: 2 - - name: Bits11 - description: 11 bits - value: 3 + - name: Bits8 + description: 8 bits + value: 0 + - name: Bits9 + description: 9 bits + value: 1 + - name: Bits10 + description: 10 bits + value: 2 + - name: Bits11 + description: 11 bits + value: 3 enum/NR: bit_size: 2 variants: - - name: Bits11 - description: 11 bits - value: 0 - - name: Bits12 - description: 12 bits - value: 1 - - name: Bits13 - description: 13 bits - value: 2 + - name: Bits11 + description: 11 bits + value: 0 + - name: Bits12 + description: 12 bits + value: 1 + - name: Bits13 + description: 13 bits + value: 2 enum/PTYP: bit_size: 1 variants: - - name: NANDFlash - description: NAND Flash - value: 1 + - name: NANDFlash + description: NAND Flash + value: 1 enum/PWID: bit_size: 2 variants: - - name: Bits8 - description: External memory device width 8 bits - value: 0 - - name: Bits16 - description: External memory device width 16 bits - value: 1 + - name: Bits8 + description: External memory device width 8 bits + value: 0 + - name: Bits16 + description: External memory device width 16 bits + value: 1 enum/RPIPE: bit_size: 2 variants: - - name: NoDelay - description: No clock cycle delay - value: 0 - - name: Clocks1 - description: One clock cycle delay - value: 1 - - name: Clocks2 - description: Two clock cycles delay - value: 2 + - name: NoDelay + description: No clock cycle delay + value: 0 + - name: Clocks1 + description: One clock cycle delay + value: 1 + - name: Clocks2 + description: Two clock cycles delay + value: 2 enum/SDCLK: bit_size: 2 variants: - - name: Disabled - description: SDCLK clock disabled - value: 0 - - name: Div2 - description: SDCLK period = 2 x HCLK period - value: 2 - - name: Div3 - description: SDCLK period = 3 x HCLK period - value: 3 + - name: Disabled + description: SDCLK clock disabled + value: 0 + - name: Div2 + description: SDCLK period = 2 x HCLK period + value: 2 + - name: Div3 + description: SDCLK period = 3 x HCLK period + value: 3 enum/WAITCFG: bit_size: 1 variants: - - name: BeforeWaitState - description: NWAIT signal is active one data cycle before wait state - value: 0 - - name: DuringWaitState - description: NWAIT signal is active during wait state - value: 1 + - name: BeforeWaitState + description: NWAIT signal is active one data cycle before wait state + value: 0 + - name: DuringWaitState + description: NWAIT signal is active during wait state + value: 1 enum/WAITPOL: bit_size: 1 variants: - - name: ActiveLow - description: NWAIT active low - value: 0 - - name: ActiveHigh - description: NWAIT active high - value: 1 + - name: ActiveLow + description: NWAIT active low + value: 0 + - name: ActiveHigh + description: NWAIT active high + value: 1 diff --git a/data/registers/fmc_v3x1.yaml b/data/registers/fmc_v3x1.yaml index bdac456..0edc212 100644 --- a/data/registers/fmc_v3x1.yaml +++ b/data/registers/fmc_v3x1.yaml @@ -1,732 +1,731 @@ ---- block/FMC: description: Flexible memory controller items: - - name: BCR1 - description: SRAM/NOR-Flash chip-select control register 1 - byte_offset: 0 - fieldset: BCR1 - - name: BTR - description: SRAM/NOR-Flash chip-select timing register 1-4 - array: - len: 4 - stride: 8 - byte_offset: 4 - fieldset: BTR - - name: BCR - description: SRAM/NOR-Flash chip-select control register 2-4 - array: - len: 3 - stride: 8 - byte_offset: 8 - fieldset: BCR - - name: PCR - description: PC Card/NAND Flash control register - byte_offset: 128 - fieldset: PCR - - name: SR - description: FIFO status and interrupt register - byte_offset: 132 - fieldset: SR - - name: PMEM - description: Common memory space timing register - byte_offset: 136 - fieldset: PMEM - - name: PATT - description: Attribute memory space timing register - byte_offset: 140 - fieldset: PATT - - name: ECCR - description: ECC result register - byte_offset: 148 - access: Read - fieldset: ECCR - - name: BWTR - description: SRAM/NOR-Flash write timing registers 1-4 - array: - len: 4 - stride: 8 - byte_offset: 260 - fieldset: BWTR - - name: SDCR - description: SDRAM Control Register 1-2 - array: - len: 2 - stride: 4 - byte_offset: 320 - fieldset: SDCR - - name: SDTR - description: SDRAM Timing register 1-2 - array: - len: 2 - stride: 4 - byte_offset: 328 - fieldset: SDTR - - name: SDCMR - description: SDRAM Command Mode register - byte_offset: 336 - fieldset: SDCMR - - name: SDRTR - description: SDRAM Refresh Timer register - byte_offset: 340 - fieldset: SDRTR - - name: SDSR - description: SDRAM Status register - byte_offset: 344 - access: Read - fieldset: SDSR + - name: BCR1 + description: SRAM/NOR-Flash chip-select control register 1 + byte_offset: 0 + fieldset: BCR1 + - name: BTR + description: SRAM/NOR-Flash chip-select timing register 1-4 + array: + len: 4 + stride: 8 + byte_offset: 4 + fieldset: BTR + - name: BCR + description: SRAM/NOR-Flash chip-select control register 2-4 + array: + len: 3 + stride: 8 + byte_offset: 8 + fieldset: BCR + - name: PCR + description: PC Card/NAND Flash control register + byte_offset: 128 + fieldset: PCR + - name: SR + description: FIFO status and interrupt register + byte_offset: 132 + fieldset: SR + - name: PMEM + description: Common memory space timing register + byte_offset: 136 + fieldset: PMEM + - name: PATT + description: Attribute memory space timing register + byte_offset: 140 + fieldset: PATT + - name: ECCR + description: ECC result register + byte_offset: 148 + access: Read + fieldset: ECCR + - name: BWTR + description: SRAM/NOR-Flash write timing registers 1-4 + array: + len: 4 + stride: 8 + byte_offset: 260 + fieldset: BWTR + - name: SDCR + description: SDRAM Control Register 1-2 + array: + len: 2 + stride: 4 + byte_offset: 320 + fieldset: SDCR + - name: SDTR + description: SDRAM Timing register 1-2 + array: + len: 2 + stride: 4 + byte_offset: 328 + fieldset: SDTR + - name: SDCMR + description: SDRAM Command Mode register + byte_offset: 336 + fieldset: SDCMR + - name: SDRTR + description: SDRAM Refresh Timer register + byte_offset: 340 + fieldset: SDRTR + - name: SDSR + description: SDRAM Status register + byte_offset: 344 + access: Read + fieldset: SDSR fieldset/BCR: description: SRAM/NOR-Flash chip-select control register 2-4 fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 fieldset/BCR1: description: SRAM/NOR-Flash chip-select control register 1 fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 - - name: CCLKEN - description: Continuous clock enable - bit_offset: 20 - bit_size: 1 - - name: WFDIS - description: Write FIFO disable - bit_offset: 21 - bit_size: 1 - - name: BMAP - description: "FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register." - bit_offset: 24 - bit_size: 2 - - name: FMCEN - description: FMC controller enable - bit_offset: 31 - bit_size: 1 + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 + - name: CCLKEN + description: Continuous clock enable + bit_offset: 20 + bit_size: 1 + - name: WFDIS + description: Write FIFO disable + bit_offset: 21 + bit_size: 1 + - name: BMAP + description: 'FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register.' + bit_offset: 24 + bit_size: 2 + - name: FMCEN + description: FMC controller enable + bit_offset: 31 + bit_size: 1 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - - name: CLKDIV - description: Clock divide ratio (for FMC_CLK signal) - bit_offset: 20 - bit_size: 4 - - name: DATLAT - description: Data latency for synchronous memory - bit_offset: 24 - bit_size: 4 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 + - name: CLKDIV + description: Clock divide ratio (for FMC_CLK signal) + bit_offset: 20 + bit_size: 4 + - name: DATLAT + description: Data latency for synchronous memory + bit_offset: 24 + bit_size: 4 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD fieldset/BWTR: description: SRAM/NOR-Flash write timing registers fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD fieldset/ECCR: description: ECC result register fields: - - name: ECC - description: ECC computation result value - bit_offset: 0 - bit_size: 32 + - name: ECC + description: ECC computation result value + bit_offset: 0 + bit_size: 32 fieldset/PATT: description: Attribute memory space timing register fields: - - name: ATTSET - description: Attribute memory setup time - bit_offset: 0 - bit_size: 8 - - name: ATTWAIT - description: Attribute memory wait time - bit_offset: 8 - bit_size: 8 - - name: ATTHOLD - description: Attribute memory hold time - bit_offset: 16 - bit_size: 8 - - name: ATTHIZ - description: Attribute memory data bus Hi-Z time - bit_offset: 24 - bit_size: 8 + - name: ATTSET + description: Attribute memory setup time + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: Attribute memory wait time + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: Attribute memory hold time + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: Attribute memory data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/PCR: description: PC Card/NAND Flash control register fields: - - name: PWAITEN - description: Wait feature enable bit - bit_offset: 1 - bit_size: 1 - - name: PBKEN - description: NAND Flash memory bank enable bit - bit_offset: 2 - bit_size: 1 - - name: PWID - description: Data bus width - bit_offset: 4 - bit_size: 2 - enum: PWID - - name: ECCEN - description: ECC computation logic enable bit - bit_offset: 6 - bit_size: 1 - - name: TCLR - description: CLE to RE delay - bit_offset: 9 - bit_size: 4 - - name: TAR - description: ALE to RE delay - bit_offset: 13 - bit_size: 4 - - name: ECCPS - description: ECC page size - bit_offset: 17 - bit_size: 3 - enum: ECCPS + - name: PWAITEN + description: Wait feature enable bit + bit_offset: 1 + bit_size: 1 + - name: PBKEN + description: NAND Flash memory bank enable bit + bit_offset: 2 + bit_size: 1 + - name: PWID + description: Data bus width + bit_offset: 4 + bit_size: 2 + enum: PWID + - name: ECCEN + description: ECC computation logic enable bit + bit_offset: 6 + bit_size: 1 + - name: TCLR + description: CLE to RE delay + bit_offset: 9 + bit_size: 4 + - name: TAR + description: ALE to RE delay + bit_offset: 13 + bit_size: 4 + - name: ECCPS + description: ECC page size + bit_offset: 17 + bit_size: 3 + enum: ECCPS fieldset/PMEM: description: Common memory space timing register fields: - - name: MEMSET - description: Common memory x setup time - bit_offset: 0 - bit_size: 8 - - name: MEMWAIT - description: Common memory wait time - bit_offset: 8 - bit_size: 8 - - name: MEMHOLD - description: Common memory hold time - bit_offset: 16 - bit_size: 8 - - name: MEMHIZ - description: Common memory x data bus Hi-Z time - bit_offset: 24 - bit_size: 8 + - name: MEMSET + description: Common memory x setup time + bit_offset: 0 + bit_size: 8 + - name: MEMWAIT + description: Common memory wait time + bit_offset: 8 + bit_size: 8 + - name: MEMHOLD + description: Common memory hold time + bit_offset: 16 + bit_size: 8 + - name: MEMHIZ + description: Common memory x data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/SDCMR: description: SDRAM Command Mode register fields: - - name: MODE - description: Command mode - bit_offset: 0 - bit_size: 3 - enum: MODE - - name: CTB2 - description: Command target bank 2 - bit_offset: 3 - bit_size: 1 - - name: CTB1 - description: Command target bank 1 - bit_offset: 4 - bit_size: 1 - - name: NRFS - description: Number of Auto-refresh - bit_offset: 5 - bit_size: 4 - - name: MRD - description: Mode Register definition - bit_offset: 9 - bit_size: 13 + - name: MODE + description: Command mode + bit_offset: 0 + bit_size: 3 + enum: MODE + - name: CTB2 + description: Command target bank 2 + bit_offset: 3 + bit_size: 1 + - name: CTB1 + description: Command target bank 1 + bit_offset: 4 + bit_size: 1 + - name: NRFS + description: Number of Auto-refresh + bit_offset: 5 + bit_size: 4 + - name: MRD + description: Mode Register definition + bit_offset: 9 + bit_size: 13 fieldset/SDCR: description: SDRAM Control Register fields: - - name: NC - description: Number of column address bits - bit_offset: 0 - bit_size: 2 - enum: NC - - name: NR - description: Number of row address bits - bit_offset: 2 - bit_size: 2 - enum: NR - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: NB - description: Number of internal banks - bit_offset: 6 - bit_size: 1 - enum: NB - - name: CAS - description: CAS latency - bit_offset: 7 - bit_size: 2 - enum: CAS - - name: WP - description: Write protection - bit_offset: 9 - bit_size: 1 - - name: SDCLK - description: SDRAM clock configuration - bit_offset: 10 - bit_size: 2 - enum: SDCLK - - name: RBURST - description: Burst read - bit_offset: 12 - bit_size: 1 - - name: RPIPE - description: Read pipe - bit_offset: 13 - bit_size: 2 - enum: RPIPE + - name: NC + description: Number of column address bits + bit_offset: 0 + bit_size: 2 + enum: NC + - name: NR + description: Number of row address bits + bit_offset: 2 + bit_size: 2 + enum: NR + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: NB + description: Number of internal banks + bit_offset: 6 + bit_size: 1 + enum: NB + - name: CAS + description: CAS latency + bit_offset: 7 + bit_size: 2 + enum: CAS + - name: WP + description: Write protection + bit_offset: 9 + bit_size: 1 + - name: SDCLK + description: SDRAM clock configuration + bit_offset: 10 + bit_size: 2 + enum: SDCLK + - name: RBURST + description: Burst read + bit_offset: 12 + bit_size: 1 + - name: RPIPE + description: Read pipe + bit_offset: 13 + bit_size: 2 + enum: RPIPE fieldset/SDRTR: description: SDRAM Refresh Timer register fields: - - name: CRE - description: Clear Refresh error flag - bit_offset: 0 - bit_size: 1 - - name: COUNT - description: Refresh Timer Count - bit_offset: 1 - bit_size: 13 - - name: REIE - description: RES Interrupt Enable - bit_offset: 14 - bit_size: 1 + - name: CRE + description: Clear Refresh error flag + bit_offset: 0 + bit_size: 1 + - name: COUNT + description: Refresh Timer Count + bit_offset: 1 + bit_size: 13 + - name: REIE + description: RES Interrupt Enable + bit_offset: 14 + bit_size: 1 fieldset/SDSR: description: SDRAM Status register fields: - - name: RE - description: Refresh error flag - bit_offset: 0 - bit_size: 1 - - name: MODES1 - description: Status Mode for Bank 1 - bit_offset: 1 - bit_size: 2 - enum: MODES - - name: MODES2 - description: Status Mode for Bank 2 - bit_offset: 3 - bit_size: 2 - enum: MODES + - name: RE + description: Refresh error flag + bit_offset: 0 + bit_size: 1 + - name: MODES1 + description: Status Mode for Bank 1 + bit_offset: 1 + bit_size: 2 + enum: MODES + - name: MODES2 + description: Status Mode for Bank 2 + bit_offset: 3 + bit_size: 2 + enum: MODES fieldset/SDTR: description: SDRAM Timing register fields: - - name: TMRD - description: Load Mode Register to Active - bit_offset: 0 - bit_size: 4 - - name: TXSR - description: Exit self-refresh delay - bit_offset: 4 - bit_size: 4 - - name: TRAS - description: Self refresh time - bit_offset: 8 - bit_size: 4 - - name: TRC - description: Row cycle delay - bit_offset: 12 - bit_size: 4 - - name: TWR - description: Recovery delay - bit_offset: 16 - bit_size: 4 - - name: TRP - description: Row precharge delay - bit_offset: 20 - bit_size: 4 - - name: TRCD - description: Row to column delay - bit_offset: 24 - bit_size: 4 + - name: TMRD + description: Load Mode Register to Active + bit_offset: 0 + bit_size: 4 + - name: TXSR + description: Exit self-refresh delay + bit_offset: 4 + bit_size: 4 + - name: TRAS + description: Self refresh time + bit_offset: 8 + bit_size: 4 + - name: TRC + description: Row cycle delay + bit_offset: 12 + bit_size: 4 + - name: TWR + description: Recovery delay + bit_offset: 16 + bit_size: 4 + - name: TRP + description: Row precharge delay + bit_offset: 20 + bit_size: 4 + - name: TRCD + description: Row to column delay + bit_offset: 24 + bit_size: 4 fieldset/SR: description: FIFO status and interrupt register fields: - - name: IRS - description: Interrupt rising edge status - bit_offset: 0 - bit_size: 1 - - name: ILS - description: Interrupt high-level status - bit_offset: 1 - bit_size: 1 - - name: IFS - description: Interrupt falling edge status - bit_offset: 2 - bit_size: 1 - - name: IREN - description: Interrupt rising edge detection enable bit - bit_offset: 3 - bit_size: 1 - - name: ILEN - description: Interrupt high-level detection enable bit - bit_offset: 4 - bit_size: 1 - - name: IFEN - description: Interrupt falling edge detection enable bit - bit_offset: 5 - bit_size: 1 - - name: FEMPT - description: FIFO empty status - bit_offset: 6 - bit_size: 1 + - name: IRS + description: Interrupt rising edge status + bit_offset: 0 + bit_size: 1 + - name: ILS + description: Interrupt high-level status + bit_offset: 1 + bit_size: 1 + - name: IFS + description: Interrupt falling edge status + bit_offset: 2 + bit_size: 1 + - name: IREN + description: Interrupt rising edge detection enable bit + bit_offset: 3 + bit_size: 1 + - name: ILEN + description: Interrupt high-level detection enable bit + bit_offset: 4 + bit_size: 1 + - name: IFEN + description: Interrupt falling edge detection enable bit + bit_offset: 5 + bit_size: 1 + - name: FEMPT + description: FIFO empty status + bit_offset: 6 + bit_size: 1 enum/ACCMOD: bit_size: 2 variants: - - name: A - description: Access mode A - value: 0 - - name: B - description: Access mode B - value: 1 - - name: C - description: Access mode C - value: 2 - - name: D - description: Access mode D - value: 3 + - name: A + description: Access mode A + value: 0 + - name: B + description: Access mode B + value: 1 + - name: C + description: Access mode C + value: 2 + - name: D + description: Access mode D + value: 3 enum/CAS: bit_size: 2 variants: - - name: Clocks1 - description: 1 cycle - value: 1 - - name: Clocks2 - description: 2 cycles - value: 2 - - name: Clocks3 - description: 3 cycles - value: 3 + - name: Clocks1 + description: 1 cycle + value: 1 + - name: Clocks2 + description: 2 cycles + value: 2 + - name: Clocks3 + description: 3 cycles + value: 3 enum/CPSIZE: bit_size: 3 variants: - - name: NoBurstSplit - description: No burst split when crossing page boundary - value: 0 - - name: Bytes128 - description: 128 bytes CRAM page size - value: 1 - - name: Bytes256 - description: 256 bytes CRAM page size - value: 2 - - name: Bytes512 - description: 512 bytes CRAM page size - value: 3 - - name: Bytes1024 - description: 1024 bytes CRAM page size - value: 4 + - name: NoBurstSplit + description: No burst split when crossing page boundary + value: 0 + - name: Bytes128 + description: 128 bytes CRAM page size + value: 1 + - name: Bytes256 + description: 256 bytes CRAM page size + value: 2 + - name: Bytes512 + description: 512 bytes CRAM page size + value: 3 + - name: Bytes1024 + description: 1024 bytes CRAM page size + value: 4 enum/ECCPS: bit_size: 3 variants: - - name: Bytes256 - description: ECC page size 256 bytes - value: 0 - - name: Bytes512 - description: ECC page size 512 bytes - value: 1 - - name: Bytes1024 - description: ECC page size 1024 bytes - value: 2 - - name: Bytes2048 - description: ECC page size 2048 bytes - value: 3 - - name: Bytes4096 - description: ECC page size 4096 bytes - value: 4 - - name: Bytes8192 - description: ECC page size 8192 bytes - value: 5 + - name: Bytes256 + description: ECC page size 256 bytes + value: 0 + - name: Bytes512 + description: ECC page size 512 bytes + value: 1 + - name: Bytes1024 + description: ECC page size 1024 bytes + value: 2 + - name: Bytes2048 + description: ECC page size 2048 bytes + value: 3 + - name: Bytes4096 + description: ECC page size 4096 bytes + value: 4 + - name: Bytes8192 + description: ECC page size 8192 bytes + value: 5 enum/MODE: bit_size: 3 variants: - - name: Normal - description: Normal Mode - value: 0 - - name: ClockConfigurationEnable - description: Clock Configuration Enable - value: 1 - - name: PALL - description: PALL (All Bank Precharge) command - value: 2 - - name: AutoRefreshCommand - description: Auto-refresh command - value: 3 - - name: LoadModeRegister - description: Load Mode Resgier - value: 4 - - name: SelfRefreshCommand - description: Self-refresh command - value: 5 - - name: PowerDownCommand - description: Power-down command - value: 6 + - name: Normal + description: Normal Mode + value: 0 + - name: ClockConfigurationEnable + description: Clock Configuration Enable + value: 1 + - name: PALL + description: PALL (All Bank Precharge) command + value: 2 + - name: AutoRefreshCommand + description: Auto-refresh command + value: 3 + - name: LoadModeRegister + description: Load Mode Resgier + value: 4 + - name: SelfRefreshCommand + description: Self-refresh command + value: 5 + - name: PowerDownCommand + description: Power-down command + value: 6 enum/MODES: bit_size: 2 variants: - - name: Normal - description: Normal Mode - value: 0 - - name: SelfRefresh - description: Self-refresh mode - value: 1 - - name: PowerDown - description: Power-down mode - value: 2 + - name: Normal + description: Normal Mode + value: 0 + - name: SelfRefresh + description: Self-refresh mode + value: 1 + - name: PowerDown + description: Power-down mode + value: 2 enum/MTYP: bit_size: 2 variants: - - name: SRAM - description: SRAM memory type - value: 0 - - name: PSRAM - description: PSRAM (CRAM) memory type - value: 1 - - name: Flash - description: NOR Flash/OneNAND Flash - value: 2 + - name: SRAM + description: SRAM memory type + value: 0 + - name: PSRAM + description: PSRAM (CRAM) memory type + value: 1 + - name: Flash + description: NOR Flash/OneNAND Flash + value: 2 enum/MWID: bit_size: 2 variants: - - name: Bits8 - description: Memory data bus width 8 bits - value: 0 - - name: Bits16 - description: Memory data bus width 16 bits - value: 1 - - name: Bits32 - description: Memory data bus width 32 bits - value: 2 + - name: Bits8 + description: Memory data bus width 8 bits + value: 0 + - name: Bits16 + description: Memory data bus width 16 bits + value: 1 + - name: Bits32 + description: Memory data bus width 32 bits + value: 2 enum/NB: bit_size: 1 variants: - - name: NB2 - description: Two internal Banks - value: 0 - - name: NB4 - description: Four internal Banks - value: 1 + - name: NB2 + description: Two internal Banks + value: 0 + - name: NB4 + description: Four internal Banks + value: 1 enum/NC: bit_size: 2 variants: - - name: Bits8 - description: 8 bits - value: 0 - - name: Bits9 - description: 9 bits - value: 1 - - name: Bits10 - description: 10 bits - value: 2 - - name: Bits11 - description: 11 bits - value: 3 + - name: Bits8 + description: 8 bits + value: 0 + - name: Bits9 + description: 9 bits + value: 1 + - name: Bits10 + description: 10 bits + value: 2 + - name: Bits11 + description: 11 bits + value: 3 enum/NR: bit_size: 2 variants: - - name: Bits11 - description: 11 bits - value: 0 - - name: Bits12 - description: 12 bits - value: 1 - - name: Bits13 - description: 13 bits - value: 2 + - name: Bits11 + description: 11 bits + value: 0 + - name: Bits12 + description: 12 bits + value: 1 + - name: Bits13 + description: 13 bits + value: 2 enum/PWID: bit_size: 2 variants: - - name: Bits8 - description: External memory device width 8 bits - value: 0 - - name: Bits16 - description: External memory device width 16 bits - value: 1 + - name: Bits8 + description: External memory device width 8 bits + value: 0 + - name: Bits16 + description: External memory device width 16 bits + value: 1 enum/RPIPE: bit_size: 2 variants: - - name: NoDelay - description: No clock cycle delay - value: 0 - - name: Clocks1 - description: One clock cycle delay - value: 1 - - name: Clocks2 - description: Two clock cycles delay - value: 2 + - name: NoDelay + description: No clock cycle delay + value: 0 + - name: Clocks1 + description: One clock cycle delay + value: 1 + - name: Clocks2 + description: Two clock cycles delay + value: 2 enum/SDCLK: bit_size: 2 variants: - - name: Disabled - description: SDCLK clock disabled - value: 0 - - name: Div2 - description: SDCLK period = 2 x HCLK period - value: 2 - - name: Div3 - description: SDCLK period = 3 x HCLK period - value: 3 + - name: Disabled + description: SDCLK clock disabled + value: 0 + - name: Div2 + description: SDCLK period = 2 x HCLK period + value: 2 + - name: Div3 + description: SDCLK period = 3 x HCLK period + value: 3 enum/WAITCFG: bit_size: 1 variants: - - name: BeforeWaitState - description: NWAIT signal is active one data cycle before wait state - value: 0 - - name: DuringWaitState - description: NWAIT signal is active during wait state - value: 1 + - name: BeforeWaitState + description: NWAIT signal is active one data cycle before wait state + value: 0 + - name: DuringWaitState + description: NWAIT signal is active during wait state + value: 1 enum/WAITPOL: bit_size: 1 variants: - - name: ActiveLow - description: NWAIT active low - value: 0 - - name: ActiveHigh - description: NWAIT active high - value: 1 + - name: ActiveLow + description: NWAIT active low + value: 0 + - name: ActiveHigh + description: NWAIT active high + value: 1 diff --git a/data/registers/fsmc_v1x0.yaml b/data/registers/fsmc_v1x0.yaml index d04b507..7a53db7 100644 --- a/data/registers/fsmc_v1x0.yaml +++ b/data/registers/fsmc_v1x0.yaml @@ -1,224 +1,223 @@ ---- block/FSMC: description: Flexible static memory controller items: - - name: BCR - description: SRAM/NOR-Flash chip-select control register 1-4 - array: - len: 4 - stride: 8 - byte_offset: 0 - fieldset: BCR - - name: BTR - description: SRAM/NOR-Flash chip-select timing register 1-4 - array: - len: 4 - stride: 8 - byte_offset: 4 - fieldset: BTR - - name: BWTR - description: SRAM/NOR-Flash write timing registers 1-4 - array: - len: 4 - stride: 8 - byte_offset: 260 - fieldset: BWTR + - name: BCR + description: SRAM/NOR-Flash chip-select control register 1-4 + array: + len: 4 + stride: 8 + byte_offset: 0 + fieldset: BCR + - name: BTR + description: SRAM/NOR-Flash chip-select timing register 1-4 + array: + len: 4 + stride: 8 + byte_offset: 4 + fieldset: BTR + - name: BWTR + description: SRAM/NOR-Flash write timing registers 1-4 + array: + len: 4 + stride: 8 + byte_offset: 260 + fieldset: BWTR fieldset/BCR: description: SRAM/NOR-Flash chip-select control register fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WRAPMOD - description: WRAPMOD - bit_offset: 10 - bit_size: 1 - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WRAPMOD + description: WRAPMOD + bit_offset: 10 + bit_size: 1 + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - - name: CLKDIV - description: Clock divide ratio (for FMC_CLK signal) - bit_offset: 20 - bit_size: 4 - - name: DATLAT - description: Data latency for synchronous memory - bit_offset: 24 - bit_size: 4 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 + - name: CLKDIV + description: Clock divide ratio (for FMC_CLK signal) + bit_offset: 20 + bit_size: 4 + - name: DATLAT + description: Data latency for synchronous memory + bit_offset: 24 + bit_size: 4 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD fieldset/BWTR: description: SRAM/NOR-Flash write timing registers fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD enum/ACCMOD: bit_size: 2 variants: - - name: A - description: Access mode A - value: 0 - - name: B - description: Access mode B - value: 1 - - name: C - description: Access mode C - value: 2 - - name: D - description: Access mode D - value: 3 + - name: A + description: Access mode A + value: 0 + - name: B + description: Access mode B + value: 1 + - name: C + description: Access mode C + value: 2 + - name: D + description: Access mode D + value: 3 enum/CPSIZE: bit_size: 3 variants: - - name: NoBurstSplit - description: No burst split when crossing page boundary - value: 0 - - name: Bytes128 - description: 128 bytes CRAM page size - value: 1 - - name: Bytes256 - description: 256 bytes CRAM page size - value: 2 - - name: Bytes512 - description: 512 bytes CRAM page size - value: 3 - - name: Bytes1024 - description: 1024 bytes CRAM page size - value: 4 + - name: NoBurstSplit + description: No burst split when crossing page boundary + value: 0 + - name: Bytes128 + description: 128 bytes CRAM page size + value: 1 + - name: Bytes256 + description: 256 bytes CRAM page size + value: 2 + - name: Bytes512 + description: 512 bytes CRAM page size + value: 3 + - name: Bytes1024 + description: 1024 bytes CRAM page size + value: 4 enum/MTYP: bit_size: 2 variants: - - name: SRAM - description: SRAM memory type - value: 0 - - name: PSRAM - description: PSRAM (CRAM) memory type - value: 1 - - name: Flash - description: NOR Flash/OneNAND Flash - value: 2 + - name: SRAM + description: SRAM memory type + value: 0 + - name: PSRAM + description: PSRAM (CRAM) memory type + value: 1 + - name: Flash + description: NOR Flash/OneNAND Flash + value: 2 enum/MWID: bit_size: 2 variants: - - name: Bits8 - description: Memory data bus width 8 bits - value: 0 - - name: Bits16 - description: Memory data bus width 16 bits - value: 1 - - name: Bits32 - description: Memory data bus width 32 bits - value: 2 + - name: Bits8 + description: Memory data bus width 8 bits + value: 0 + - name: Bits16 + description: Memory data bus width 16 bits + value: 1 + - name: Bits32 + description: Memory data bus width 32 bits + value: 2 enum/WAITCFG: bit_size: 1 variants: - - name: BeforeWaitState - description: NWAIT signal is active one data cycle before wait state - value: 0 - - name: DuringWaitState - description: NWAIT signal is active during wait state - value: 1 + - name: BeforeWaitState + description: NWAIT signal is active one data cycle before wait state + value: 0 + - name: DuringWaitState + description: NWAIT signal is active during wait state + value: 1 enum/WAITPOL: bit_size: 1 variants: - - name: ActiveLow - description: NWAIT active low - value: 0 - - name: ActiveHigh - description: NWAIT active high - value: 1 + - name: ActiveLow + description: NWAIT active low + value: 0 + - name: ActiveHigh + description: NWAIT active high + value: 1 diff --git a/data/registers/fsmc_v1x3.yaml b/data/registers/fsmc_v1x3.yaml index 286604c..06687a0 100644 --- a/data/registers/fsmc_v1x3.yaml +++ b/data/registers/fsmc_v1x3.yaml @@ -1,433 +1,432 @@ ---- block/FSMC: description: Flexible static memory controller items: - - name: BCR - description: SRAM/NOR-Flash chip-select control register 1-4 - array: - len: 4 - stride: 8 - byte_offset: 0 - fieldset: BCR - - name: BTR - description: SRAM/NOR-Flash chip-select timing register 1-4 - array: - len: 4 - stride: 8 - byte_offset: 4 - fieldset: BTR - - name: PCR - description: PC Card/NAND Flash control register 2-4 - array: - len: 3 - stride: 32 - byte_offset: 96 - fieldset: PCR - - name: SR - description: FIFO status and interrupt register 2-4 - array: - len: 3 - stride: 32 - byte_offset: 100 - fieldset: SR - - name: PMEM - description: Common memory space timing register 2-4 - array: - len: 3 - stride: 32 - byte_offset: 104 - fieldset: PMEM - - name: PATT - description: Attribute memory space timing register 2-4 - array: - len: 3 - stride: 32 - byte_offset: 108 - fieldset: PATT - - name: ECCR - description: ECC result register 2-3 - array: - len: 2 - stride: 32 - byte_offset: 116 - access: Read - fieldset: ECCR - - name: PIO4 - description: I/O space timing register 4 - byte_offset: 176 - fieldset: PIO4 - - name: BWTR - description: SRAM/NOR-Flash write timing registers 1-4 - array: - len: 4 - stride: 8 - byte_offset: 260 - fieldset: BWTR + - name: BCR + description: SRAM/NOR-Flash chip-select control register 1-4 + array: + len: 4 + stride: 8 + byte_offset: 0 + fieldset: BCR + - name: BTR + description: SRAM/NOR-Flash chip-select timing register 1-4 + array: + len: 4 + stride: 8 + byte_offset: 4 + fieldset: BTR + - name: PCR + description: PC Card/NAND Flash control register 2-4 + array: + len: 3 + stride: 32 + byte_offset: 96 + fieldset: PCR + - name: SR + description: FIFO status and interrupt register 2-4 + array: + len: 3 + stride: 32 + byte_offset: 100 + fieldset: SR + - name: PMEM + description: Common memory space timing register 2-4 + array: + len: 3 + stride: 32 + byte_offset: 104 + fieldset: PMEM + - name: PATT + description: Attribute memory space timing register 2-4 + array: + len: 3 + stride: 32 + byte_offset: 108 + fieldset: PATT + - name: ECCR + description: ECC result register 2-3 + array: + len: 2 + stride: 32 + byte_offset: 116 + access: Read + fieldset: ECCR + - name: PIO4 + description: I/O space timing register 4 + byte_offset: 176 + fieldset: PIO4 + - name: BWTR + description: SRAM/NOR-Flash write timing registers 1-4 + array: + len: 4 + stride: 8 + byte_offset: 260 + fieldset: BWTR fieldset/BCR: description: SRAM/NOR-Flash chip-select control register fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WRAPMOD - description: WRAPMOD - bit_offset: 10 - bit_size: 1 - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WRAPMOD + description: WRAPMOD + bit_offset: 10 + bit_size: 1 + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - - name: CLKDIV - description: Clock divide ratio (for FMC_CLK signal) - bit_offset: 20 - bit_size: 4 - - name: DATLAT - description: Data latency for synchronous memory - bit_offset: 24 - bit_size: 4 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 + - name: CLKDIV + description: Clock divide ratio (for FMC_CLK signal) + bit_offset: 20 + bit_size: 4 + - name: DATLAT + description: Data latency for synchronous memory + bit_offset: 24 + bit_size: 4 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD fieldset/BWTR: description: SRAM/NOR-Flash write timing registers fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD fieldset/ECCR: description: ECC result register fields: - - name: ECC - description: ECC computation result value - bit_offset: 0 - bit_size: 32 + - name: ECC + description: ECC computation result value + bit_offset: 0 + bit_size: 32 fieldset/PATT: description: Attribute memory space timing register fields: - - name: ATTSET - description: Attribute memory setup time - bit_offset: 0 - bit_size: 8 - - name: ATTWAIT - description: Attribute memory wait time - bit_offset: 8 - bit_size: 8 - - name: ATTHOLD - description: Attribute memory hold time - bit_offset: 16 - bit_size: 8 - - name: ATTHIZ - description: Attribute memory data bus Hi-Z time - bit_offset: 24 - bit_size: 8 + - name: ATTSET + description: Attribute memory setup time + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: Attribute memory wait time + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: Attribute memory hold time + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: Attribute memory data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/PCR: description: PC Card/NAND Flash control register fields: - - name: PWAITEN - description: Wait feature enable bit - bit_offset: 1 - bit_size: 1 - - name: PBKEN - description: NAND Flash memory bank enable bit - bit_offset: 2 - bit_size: 1 - - name: PTYP - description: Memory type - bit_offset: 3 - bit_size: 1 - enum: PTYP - - name: PWID - description: Data bus width - bit_offset: 4 - bit_size: 2 - enum: PWID - - name: ECCEN - description: ECC computation logic enable bit - bit_offset: 6 - bit_size: 1 - - name: TCLR - description: CLE to RE delay - bit_offset: 9 - bit_size: 4 - - name: TAR - description: ALE to RE delay - bit_offset: 13 - bit_size: 4 - - name: ECCPS - description: ECC page size - bit_offset: 17 - bit_size: 3 - enum: ECCPS + - name: PWAITEN + description: Wait feature enable bit + bit_offset: 1 + bit_size: 1 + - name: PBKEN + description: NAND Flash memory bank enable bit + bit_offset: 2 + bit_size: 1 + - name: PTYP + description: Memory type + bit_offset: 3 + bit_size: 1 + enum: PTYP + - name: PWID + description: Data bus width + bit_offset: 4 + bit_size: 2 + enum: PWID + - name: ECCEN + description: ECC computation logic enable bit + bit_offset: 6 + bit_size: 1 + - name: TCLR + description: CLE to RE delay + bit_offset: 9 + bit_size: 4 + - name: TAR + description: ALE to RE delay + bit_offset: 13 + bit_size: 4 + - name: ECCPS + description: ECC page size + bit_offset: 17 + bit_size: 3 + enum: ECCPS fieldset/PIO4: description: I/O space timing register 4 fields: - - name: IOSETx - description: IOSETx - bit_offset: 0 - bit_size: 8 - - name: IOWAITx - description: IOWAITx - bit_offset: 8 - bit_size: 8 - - name: IOHOLDx - description: IOHOLDx - bit_offset: 16 - bit_size: 8 - - name: IOHIZx - description: IOHIZx - bit_offset: 24 - bit_size: 8 + - name: IOSETx + description: IOSETx + bit_offset: 0 + bit_size: 8 + - name: IOWAITx + description: IOWAITx + bit_offset: 8 + bit_size: 8 + - name: IOHOLDx + description: IOHOLDx + bit_offset: 16 + bit_size: 8 + - name: IOHIZx + description: IOHIZx + bit_offset: 24 + bit_size: 8 fieldset/PMEM: description: Common memory space timing register fields: - - name: MEMSET - description: Common memory x setup time - bit_offset: 0 - bit_size: 8 - - name: MEMWAIT - description: Common memory wait time - bit_offset: 8 - bit_size: 8 - - name: MEMHOLD - description: Common memory hold time - bit_offset: 16 - bit_size: 8 - - name: MEMHIZ - description: Common memory x data bus Hi-Z time - bit_offset: 24 - bit_size: 8 + - name: MEMSET + description: Common memory x setup time + bit_offset: 0 + bit_size: 8 + - name: MEMWAIT + description: Common memory wait time + bit_offset: 8 + bit_size: 8 + - name: MEMHOLD + description: Common memory hold time + bit_offset: 16 + bit_size: 8 + - name: MEMHIZ + description: Common memory x data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/SR: description: FIFO status and interrupt register fields: - - name: IRS - description: Interrupt rising edge status - bit_offset: 0 - bit_size: 1 - - name: ILS - description: Interrupt high-level status - bit_offset: 1 - bit_size: 1 - - name: IFS - description: Interrupt falling edge status - bit_offset: 2 - bit_size: 1 - - name: IREN - description: Interrupt rising edge detection enable bit - bit_offset: 3 - bit_size: 1 - - name: ILEN - description: Interrupt high-level detection enable bit - bit_offset: 4 - bit_size: 1 - - name: IFEN - description: Interrupt falling edge detection enable bit - bit_offset: 5 - bit_size: 1 - - name: FEMPT - description: FIFO empty status - bit_offset: 6 - bit_size: 1 + - name: IRS + description: Interrupt rising edge status + bit_offset: 0 + bit_size: 1 + - name: ILS + description: Interrupt high-level status + bit_offset: 1 + bit_size: 1 + - name: IFS + description: Interrupt falling edge status + bit_offset: 2 + bit_size: 1 + - name: IREN + description: Interrupt rising edge detection enable bit + bit_offset: 3 + bit_size: 1 + - name: ILEN + description: Interrupt high-level detection enable bit + bit_offset: 4 + bit_size: 1 + - name: IFEN + description: Interrupt falling edge detection enable bit + bit_offset: 5 + bit_size: 1 + - name: FEMPT + description: FIFO empty status + bit_offset: 6 + bit_size: 1 enum/ACCMOD: bit_size: 2 variants: - - name: A - description: Access mode A - value: 0 - - name: B - description: Access mode B - value: 1 - - name: C - description: Access mode C - value: 2 - - name: D - description: Access mode D - value: 3 + - name: A + description: Access mode A + value: 0 + - name: B + description: Access mode B + value: 1 + - name: C + description: Access mode C + value: 2 + - name: D + description: Access mode D + value: 3 enum/CPSIZE: bit_size: 3 variants: - - name: NoBurstSplit - description: No burst split when crossing page boundary - value: 0 - - name: Bytes128 - description: 128 bytes CRAM page size - value: 1 - - name: Bytes256 - description: 256 bytes CRAM page size - value: 2 - - name: Bytes512 - description: 512 bytes CRAM page size - value: 3 - - name: Bytes1024 - description: 1024 bytes CRAM page size - value: 4 + - name: NoBurstSplit + description: No burst split when crossing page boundary + value: 0 + - name: Bytes128 + description: 128 bytes CRAM page size + value: 1 + - name: Bytes256 + description: 256 bytes CRAM page size + value: 2 + - name: Bytes512 + description: 512 bytes CRAM page size + value: 3 + - name: Bytes1024 + description: 1024 bytes CRAM page size + value: 4 enum/ECCPS: bit_size: 3 variants: - - name: Bytes256 - description: ECC page size 256 bytes - value: 0 - - name: Bytes512 - description: ECC page size 512 bytes - value: 1 - - name: Bytes1024 - description: ECC page size 1024 bytes - value: 2 - - name: Bytes2048 - description: ECC page size 2048 bytes - value: 3 - - name: Bytes4096 - description: ECC page size 4096 bytes - value: 4 - - name: Bytes8192 - description: ECC page size 8192 bytes - value: 5 + - name: Bytes256 + description: ECC page size 256 bytes + value: 0 + - name: Bytes512 + description: ECC page size 512 bytes + value: 1 + - name: Bytes1024 + description: ECC page size 1024 bytes + value: 2 + - name: Bytes2048 + description: ECC page size 2048 bytes + value: 3 + - name: Bytes4096 + description: ECC page size 4096 bytes + value: 4 + - name: Bytes8192 + description: ECC page size 8192 bytes + value: 5 enum/MTYP: bit_size: 2 variants: - - name: SRAM - description: SRAM memory type - value: 0 - - name: PSRAM - description: PSRAM (CRAM) memory type - value: 1 - - name: Flash - description: NOR Flash/OneNAND Flash - value: 2 + - name: SRAM + description: SRAM memory type + value: 0 + - name: PSRAM + description: PSRAM (CRAM) memory type + value: 1 + - name: Flash + description: NOR Flash/OneNAND Flash + value: 2 enum/MWID: bit_size: 2 variants: - - name: Bits8 - description: Memory data bus width 8 bits - value: 0 - - name: Bits16 - description: Memory data bus width 16 bits - value: 1 - - name: Bits32 - description: Memory data bus width 32 bits - value: 2 + - name: Bits8 + description: Memory data bus width 8 bits + value: 0 + - name: Bits16 + description: Memory data bus width 16 bits + value: 1 + - name: Bits32 + description: Memory data bus width 32 bits + value: 2 enum/PTYP: bit_size: 1 variants: - - name: NANDFlash - description: NAND Flash - value: 1 + - name: NANDFlash + description: NAND Flash + value: 1 enum/PWID: bit_size: 2 variants: - - name: Bits8 - description: External memory device width 8 bits - value: 0 - - name: Bits16 - description: External memory device width 16 bits - value: 1 + - name: Bits8 + description: External memory device width 8 bits + value: 0 + - name: Bits16 + description: External memory device width 16 bits + value: 1 enum/WAITCFG: bit_size: 1 variants: - - name: BeforeWaitState - description: NWAIT signal is active one data cycle before wait state - value: 0 - - name: DuringWaitState - description: NWAIT signal is active during wait state - value: 1 + - name: BeforeWaitState + description: NWAIT signal is active one data cycle before wait state + value: 0 + - name: DuringWaitState + description: NWAIT signal is active during wait state + value: 1 enum/WAITPOL: bit_size: 1 variants: - - name: ActiveLow - description: NWAIT active low - value: 0 - - name: ActiveHigh - description: NWAIT active high - value: 1 + - name: ActiveLow + description: NWAIT active low + value: 0 + - name: ActiveHigh + description: NWAIT active high + value: 1 diff --git a/data/registers/fsmc_v2x3.yaml b/data/registers/fsmc_v2x3.yaml index d9a658a..565f0ce 100644 --- a/data/registers/fsmc_v2x3.yaml +++ b/data/registers/fsmc_v2x3.yaml @@ -1,477 +1,476 @@ ---- block/FSMC: description: Flexible static memory controller items: - - name: BCR1 - description: SRAM/NOR-Flash chip-select control register 1 - byte_offset: 0 - fieldset: BCR1 - - name: BTR - description: SRAM/NOR-Flash chip-select timing register 1-4 - array: - len: 4 - stride: 8 - byte_offset: 4 - fieldset: BTR - - name: BCR - description: SRAM/NOR-Flash chip-select control register 2-4 - array: - len: 3 - stride: 8 - byte_offset: 8 - fieldset: BCR - - name: PCR - description: PC Card/NAND Flash control register 2-4 - array: - len: 3 - stride: 32 - byte_offset: 96 - fieldset: PCR - - name: SR - description: FIFO status and interrupt register 2-4 - array: - len: 3 - stride: 32 - byte_offset: 100 - fieldset: SR - - name: PMEM - description: Common memory space timing register 2-4 - array: - len: 3 - stride: 32 - byte_offset: 104 - fieldset: PMEM - - name: PATT - description: Attribute memory space timing register 2-4 - array: - len: 3 - stride: 32 - byte_offset: 108 - fieldset: PATT - - name: ECCR - description: ECC result register 2-3 - array: - len: 2 - stride: 32 - byte_offset: 116 - access: Read - fieldset: ECCR - - name: PIO4 - description: I/O space timing register 4 - byte_offset: 176 - fieldset: PIO4 - - name: BWTR - description: SRAM/NOR-Flash write timing registers 1-4 - array: - len: 4 - stride: 8 - byte_offset: 260 - fieldset: BWTR + - name: BCR1 + description: SRAM/NOR-Flash chip-select control register 1 + byte_offset: 0 + fieldset: BCR1 + - name: BTR + description: SRAM/NOR-Flash chip-select timing register 1-4 + array: + len: 4 + stride: 8 + byte_offset: 4 + fieldset: BTR + - name: BCR + description: SRAM/NOR-Flash chip-select control register 2-4 + array: + len: 3 + stride: 8 + byte_offset: 8 + fieldset: BCR + - name: PCR + description: PC Card/NAND Flash control register 2-4 + array: + len: 3 + stride: 32 + byte_offset: 96 + fieldset: PCR + - name: SR + description: FIFO status and interrupt register 2-4 + array: + len: 3 + stride: 32 + byte_offset: 100 + fieldset: SR + - name: PMEM + description: Common memory space timing register 2-4 + array: + len: 3 + stride: 32 + byte_offset: 104 + fieldset: PMEM + - name: PATT + description: Attribute memory space timing register 2-4 + array: + len: 3 + stride: 32 + byte_offset: 108 + fieldset: PATT + - name: ECCR + description: ECC result register 2-3 + array: + len: 2 + stride: 32 + byte_offset: 116 + access: Read + fieldset: ECCR + - name: PIO4 + description: I/O space timing register 4 + byte_offset: 176 + fieldset: PIO4 + - name: BWTR + description: SRAM/NOR-Flash write timing registers 1-4 + array: + len: 4 + stride: 8 + byte_offset: 260 + fieldset: BWTR fieldset/BCR: description: SRAM/NOR-Flash chip-select control register 2-4 fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WRAPMOD - description: WRAPMOD - bit_offset: 10 - bit_size: 1 - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WRAPMOD + description: WRAPMOD + bit_offset: 10 + bit_size: 1 + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 fieldset/BCR1: description: SRAM/NOR-Flash chip-select control register 1 fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WRAPMOD - description: WRAPMOD - bit_offset: 10 - bit_size: 1 - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 - - name: CCLKEN - description: Continuous clock enable - bit_offset: 20 - bit_size: 1 + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WRAPMOD + description: WRAPMOD + bit_offset: 10 + bit_size: 1 + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 + - name: CCLKEN + description: Continuous clock enable + bit_offset: 20 + bit_size: 1 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - - name: CLKDIV - description: Clock divide ratio (for FMC_CLK signal) - bit_offset: 20 - bit_size: 4 - - name: DATLAT - description: Data latency for synchronous memory - bit_offset: 24 - bit_size: 4 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 + - name: CLKDIV + description: Clock divide ratio (for FMC_CLK signal) + bit_offset: 20 + bit_size: 4 + - name: DATLAT + description: Data latency for synchronous memory + bit_offset: 24 + bit_size: 4 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD fieldset/BWTR: description: SRAM/NOR-Flash write timing registers fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD fieldset/ECCR: description: ECC result register fields: - - name: ECC - description: ECC computation result value - bit_offset: 0 - bit_size: 32 + - name: ECC + description: ECC computation result value + bit_offset: 0 + bit_size: 32 fieldset/PATT: description: Attribute memory space timing register fields: - - name: ATTSET - description: Attribute memory setup time - bit_offset: 0 - bit_size: 8 - - name: ATTWAIT - description: Attribute memory wait time - bit_offset: 8 - bit_size: 8 - - name: ATTHOLD - description: Attribute memory hold time - bit_offset: 16 - bit_size: 8 - - name: ATTHIZ - description: Attribute memory data bus Hi-Z time - bit_offset: 24 - bit_size: 8 + - name: ATTSET + description: Attribute memory setup time + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: Attribute memory wait time + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: Attribute memory hold time + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: Attribute memory data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/PCR: description: PC Card/NAND Flash control register fields: - - name: PWAITEN - description: Wait feature enable bit - bit_offset: 1 - bit_size: 1 - - name: PBKEN - description: NAND Flash memory bank enable bit - bit_offset: 2 - bit_size: 1 - - name: PTYP - description: Memory type - bit_offset: 3 - bit_size: 1 - enum: PTYP - - name: PWID - description: Data bus width - bit_offset: 4 - bit_size: 2 - enum: PWID - - name: ECCEN - description: ECC computation logic enable bit - bit_offset: 6 - bit_size: 1 - - name: TCLR - description: CLE to RE delay - bit_offset: 9 - bit_size: 4 - - name: TAR - description: ALE to RE delay - bit_offset: 13 - bit_size: 4 - - name: ECCPS - description: ECC page size - bit_offset: 17 - bit_size: 3 - enum: ECCPS + - name: PWAITEN + description: Wait feature enable bit + bit_offset: 1 + bit_size: 1 + - name: PBKEN + description: NAND Flash memory bank enable bit + bit_offset: 2 + bit_size: 1 + - name: PTYP + description: Memory type + bit_offset: 3 + bit_size: 1 + enum: PTYP + - name: PWID + description: Data bus width + bit_offset: 4 + bit_size: 2 + enum: PWID + - name: ECCEN + description: ECC computation logic enable bit + bit_offset: 6 + bit_size: 1 + - name: TCLR + description: CLE to RE delay + bit_offset: 9 + bit_size: 4 + - name: TAR + description: ALE to RE delay + bit_offset: 13 + bit_size: 4 + - name: ECCPS + description: ECC page size + bit_offset: 17 + bit_size: 3 + enum: ECCPS fieldset/PIO4: description: I/O space timing register 4 fields: - - name: IOSETx - description: IOSETx - bit_offset: 0 - bit_size: 8 - - name: IOWAITx - description: IOWAITx - bit_offset: 8 - bit_size: 8 - - name: IOHOLDx - description: IOHOLDx - bit_offset: 16 - bit_size: 8 - - name: IOHIZx - description: IOHIZx - bit_offset: 24 - bit_size: 8 + - name: IOSETx + description: IOSETx + bit_offset: 0 + bit_size: 8 + - name: IOWAITx + description: IOWAITx + bit_offset: 8 + bit_size: 8 + - name: IOHOLDx + description: IOHOLDx + bit_offset: 16 + bit_size: 8 + - name: IOHIZx + description: IOHIZx + bit_offset: 24 + bit_size: 8 fieldset/PMEM: description: Common memory space timing register fields: - - name: MEMSET - description: Common memory x setup time - bit_offset: 0 - bit_size: 8 - - name: MEMWAIT - description: Common memory wait time - bit_offset: 8 - bit_size: 8 - - name: MEMHOLD - description: Common memory hold time - bit_offset: 16 - bit_size: 8 - - name: MEMHIZ - description: Common memory x data bus Hi-Z time - bit_offset: 24 - bit_size: 8 + - name: MEMSET + description: Common memory x setup time + bit_offset: 0 + bit_size: 8 + - name: MEMWAIT + description: Common memory wait time + bit_offset: 8 + bit_size: 8 + - name: MEMHOLD + description: Common memory hold time + bit_offset: 16 + bit_size: 8 + - name: MEMHIZ + description: Common memory x data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/SR: description: FIFO status and interrupt register fields: - - name: IRS - description: Interrupt rising edge status - bit_offset: 0 - bit_size: 1 - - name: ILS - description: Interrupt high-level status - bit_offset: 1 - bit_size: 1 - - name: IFS - description: Interrupt falling edge status - bit_offset: 2 - bit_size: 1 - - name: IREN - description: Interrupt rising edge detection enable bit - bit_offset: 3 - bit_size: 1 - - name: ILEN - description: Interrupt high-level detection enable bit - bit_offset: 4 - bit_size: 1 - - name: IFEN - description: Interrupt falling edge detection enable bit - bit_offset: 5 - bit_size: 1 - - name: FEMPT - description: FIFO empty status - bit_offset: 6 - bit_size: 1 + - name: IRS + description: Interrupt rising edge status + bit_offset: 0 + bit_size: 1 + - name: ILS + description: Interrupt high-level status + bit_offset: 1 + bit_size: 1 + - name: IFS + description: Interrupt falling edge status + bit_offset: 2 + bit_size: 1 + - name: IREN + description: Interrupt rising edge detection enable bit + bit_offset: 3 + bit_size: 1 + - name: ILEN + description: Interrupt high-level detection enable bit + bit_offset: 4 + bit_size: 1 + - name: IFEN + description: Interrupt falling edge detection enable bit + bit_offset: 5 + bit_size: 1 + - name: FEMPT + description: FIFO empty status + bit_offset: 6 + bit_size: 1 enum/ACCMOD: bit_size: 2 variants: - - name: A - description: Access mode A - value: 0 - - name: B - description: Access mode B - value: 1 - - name: C - description: Access mode C - value: 2 - - name: D - description: Access mode D - value: 3 + - name: A + description: Access mode A + value: 0 + - name: B + description: Access mode B + value: 1 + - name: C + description: Access mode C + value: 2 + - name: D + description: Access mode D + value: 3 enum/ECCPS: bit_size: 3 variants: - - name: Bytes256 - description: ECC page size 256 bytes - value: 0 - - name: Bytes512 - description: ECC page size 512 bytes - value: 1 - - name: Bytes1024 - description: ECC page size 1024 bytes - value: 2 - - name: Bytes2048 - description: ECC page size 2048 bytes - value: 3 - - name: Bytes4096 - description: ECC page size 4096 bytes - value: 4 - - name: Bytes8192 - description: ECC page size 8192 bytes - value: 5 + - name: Bytes256 + description: ECC page size 256 bytes + value: 0 + - name: Bytes512 + description: ECC page size 512 bytes + value: 1 + - name: Bytes1024 + description: ECC page size 1024 bytes + value: 2 + - name: Bytes2048 + description: ECC page size 2048 bytes + value: 3 + - name: Bytes4096 + description: ECC page size 4096 bytes + value: 4 + - name: Bytes8192 + description: ECC page size 8192 bytes + value: 5 enum/MTYP: bit_size: 2 variants: - - name: SRAM - description: SRAM memory type - value: 0 - - name: PSRAM - description: PSRAM (CRAM) memory type - value: 1 - - name: Flash - description: NOR Flash/OneNAND Flash - value: 2 + - name: SRAM + description: SRAM memory type + value: 0 + - name: PSRAM + description: PSRAM (CRAM) memory type + value: 1 + - name: Flash + description: NOR Flash/OneNAND Flash + value: 2 enum/MWID: bit_size: 2 variants: - - name: Bits8 - description: Memory data bus width 8 bits - value: 0 - - name: Bits16 - description: Memory data bus width 16 bits - value: 1 - - name: Bits32 - description: Memory data bus width 32 bits - value: 2 + - name: Bits8 + description: Memory data bus width 8 bits + value: 0 + - name: Bits16 + description: Memory data bus width 16 bits + value: 1 + - name: Bits32 + description: Memory data bus width 32 bits + value: 2 enum/PTYP: bit_size: 1 variants: - - name: NANDFlash - description: NAND Flash - value: 1 + - name: NANDFlash + description: NAND Flash + value: 1 enum/PWID: bit_size: 2 variants: - - name: Bits8 - description: External memory device width 8 bits - value: 0 - - name: Bits16 - description: External memory device width 16 bits - value: 1 + - name: Bits8 + description: External memory device width 8 bits + value: 0 + - name: Bits16 + description: External memory device width 16 bits + value: 1 enum/WAITCFG: bit_size: 1 variants: - - name: BeforeWaitState - description: NWAIT signal is active one data cycle before wait state - value: 0 - - name: DuringWaitState - description: NWAIT signal is active during wait state - value: 1 + - name: BeforeWaitState + description: NWAIT signal is active one data cycle before wait state + value: 0 + - name: DuringWaitState + description: NWAIT signal is active during wait state + value: 1 enum/WAITPOL: bit_size: 1 variants: - - name: ActiveLow - description: NWAIT active low - value: 0 - - name: ActiveHigh - description: NWAIT active high - value: 1 + - name: ActiveLow + description: NWAIT active low + value: 0 + - name: ActiveHigh + description: NWAIT active high + value: 1 diff --git a/data/registers/fsmc_v3x1.yaml b/data/registers/fsmc_v3x1.yaml index 964e49c..c0a37e9 100644 --- a/data/registers/fsmc_v3x1.yaml +++ b/data/registers/fsmc_v3x1.yaml @@ -1,467 +1,466 @@ ---- block/FSMC: description: Flexible static memory controller items: - - name: BCR1 - description: SRAM/NOR-Flash chip-select control register 1 - byte_offset: 0 - fieldset: BCR1 - - name: BTR - description: SRAM/NOR-Flash chip-select timing register 1-4 - array: - len: 4 - stride: 8 - byte_offset: 4 - fieldset: BTR - - name: BCR - description: SRAM/NOR-Flash chip-select control register 2-4 - array: - len: 3 - stride: 8 - byte_offset: 8 - fieldset: BCR - - name: PCR - description: PC Card/NAND Flash control register - byte_offset: 128 - fieldset: PCR - - name: SR - description: FIFO status and interrupt register - byte_offset: 132 - fieldset: SR - - name: PMEM - description: Common memory space timing register - byte_offset: 136 - fieldset: PMEM - - name: PATT - description: Attribute memory space timing register - byte_offset: 140 - fieldset: PATT - - name: ECCR - description: ECC result register - byte_offset: 148 - access: Read - fieldset: ECCR - - name: BWTR - description: SRAM/NOR-Flash write timing registers 1-4 - array: - len: 4 - stride: 8 - byte_offset: 260 - fieldset: BWTR + - name: BCR1 + description: SRAM/NOR-Flash chip-select control register 1 + byte_offset: 0 + fieldset: BCR1 + - name: BTR + description: SRAM/NOR-Flash chip-select timing register 1-4 + array: + len: 4 + stride: 8 + byte_offset: 4 + fieldset: BTR + - name: BCR + description: SRAM/NOR-Flash chip-select control register 2-4 + array: + len: 3 + stride: 8 + byte_offset: 8 + fieldset: BCR + - name: PCR + description: PC Card/NAND Flash control register + byte_offset: 128 + fieldset: PCR + - name: SR + description: FIFO status and interrupt register + byte_offset: 132 + fieldset: SR + - name: PMEM + description: Common memory space timing register + byte_offset: 136 + fieldset: PMEM + - name: PATT + description: Attribute memory space timing register + byte_offset: 140 + fieldset: PATT + - name: ECCR + description: ECC result register + byte_offset: 148 + access: Read + fieldset: ECCR + - name: BWTR + description: SRAM/NOR-Flash write timing registers 1-4 + array: + len: 4 + stride: 8 + byte_offset: 260 + fieldset: BWTR fieldset/BCR: description: SRAM/NOR-Flash chip-select control register 2-4 fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 fieldset/BCR1: description: SRAM/NOR-Flash chip-select control register 1 fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 - - name: CCLKEN - description: Continuous clock enable - bit_offset: 20 - bit_size: 1 - - name: WFDIS - description: Write FIFO disable - bit_offset: 21 - bit_size: 1 + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 + - name: CCLKEN + description: Continuous clock enable + bit_offset: 20 + bit_size: 1 + - name: WFDIS + description: Write FIFO disable + bit_offset: 21 + bit_size: 1 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - - name: CLKDIV - description: Clock divide ratio (for FMC_CLK signal) - bit_offset: 20 - bit_size: 4 - - name: DATLAT - description: Data latency for synchronous memory - bit_offset: 24 - bit_size: 4 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 + - name: CLKDIV + description: Clock divide ratio (for FMC_CLK signal) + bit_offset: 20 + bit_size: 4 + - name: DATLAT + description: Data latency for synchronous memory + bit_offset: 24 + bit_size: 4 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD fieldset/BWTR: description: SRAM/NOR-Flash write timing registers fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD fieldset/ECCR: description: ECC result register fields: - - name: ECC - description: ECC computation result value - bit_offset: 0 - bit_size: 32 + - name: ECC + description: ECC computation result value + bit_offset: 0 + bit_size: 32 fieldset/PATT: description: Attribute memory space timing register fields: - - name: ATTSET - description: Attribute memory setup time - bit_offset: 0 - bit_size: 8 - - name: ATTWAIT - description: Attribute memory wait time - bit_offset: 8 - bit_size: 8 - - name: ATTHOLD - description: Attribute memory hold time - bit_offset: 16 - bit_size: 8 - - name: ATTHIZ - description: Attribute memory data bus Hi-Z time - bit_offset: 24 - bit_size: 8 + - name: ATTSET + description: Attribute memory setup time + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: Attribute memory wait time + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: Attribute memory hold time + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: Attribute memory data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/PCR: description: PC Card/NAND Flash control register fields: - - name: PWAITEN - description: Wait feature enable bit - bit_offset: 1 - bit_size: 1 - - name: PBKEN - description: NAND Flash memory bank enable bit - bit_offset: 2 - bit_size: 1 - - name: PTYP - description: Memory type - bit_offset: 3 - bit_size: 1 - enum: PTYP - - name: PWID - description: Data bus width - bit_offset: 4 - bit_size: 2 - enum: PWID - - name: ECCEN - description: ECC computation logic enable bit - bit_offset: 6 - bit_size: 1 - - name: TCLR - description: CLE to RE delay - bit_offset: 9 - bit_size: 4 - - name: TAR - description: ALE to RE delay - bit_offset: 13 - bit_size: 4 - - name: ECCPS - description: ECC page size - bit_offset: 17 - bit_size: 3 - enum: ECCPS + - name: PWAITEN + description: Wait feature enable bit + bit_offset: 1 + bit_size: 1 + - name: PBKEN + description: NAND Flash memory bank enable bit + bit_offset: 2 + bit_size: 1 + - name: PTYP + description: Memory type + bit_offset: 3 + bit_size: 1 + enum: PTYP + - name: PWID + description: Data bus width + bit_offset: 4 + bit_size: 2 + enum: PWID + - name: ECCEN + description: ECC computation logic enable bit + bit_offset: 6 + bit_size: 1 + - name: TCLR + description: CLE to RE delay + bit_offset: 9 + bit_size: 4 + - name: TAR + description: ALE to RE delay + bit_offset: 13 + bit_size: 4 + - name: ECCPS + description: ECC page size + bit_offset: 17 + bit_size: 3 + enum: ECCPS fieldset/PMEM: description: Common memory space timing register fields: - - name: MEMSET - description: Common memory x setup time - bit_offset: 0 - bit_size: 8 - - name: MEMWAIT - description: Common memory wait time - bit_offset: 8 - bit_size: 8 - - name: MEMHOLD - description: Common memory hold time - bit_offset: 16 - bit_size: 8 - - name: MEMHIZ - description: Common memory x data bus Hi-Z time - bit_offset: 24 - bit_size: 8 + - name: MEMSET + description: Common memory x setup time + bit_offset: 0 + bit_size: 8 + - name: MEMWAIT + description: Common memory wait time + bit_offset: 8 + bit_size: 8 + - name: MEMHOLD + description: Common memory hold time + bit_offset: 16 + bit_size: 8 + - name: MEMHIZ + description: Common memory x data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/SR: description: FIFO status and interrupt register fields: - - name: IRS - description: Interrupt rising edge status - bit_offset: 0 - bit_size: 1 - - name: ILS - description: Interrupt high-level status - bit_offset: 1 - bit_size: 1 - - name: IFS - description: Interrupt falling edge status - bit_offset: 2 - bit_size: 1 - - name: IREN - description: Interrupt rising edge detection enable bit - bit_offset: 3 - bit_size: 1 - - name: ILEN - description: Interrupt high-level detection enable bit - bit_offset: 4 - bit_size: 1 - - name: IFEN - description: Interrupt falling edge detection enable bit - bit_offset: 5 - bit_size: 1 - - name: FEMPT - description: FIFO empty status - bit_offset: 6 - bit_size: 1 + - name: IRS + description: Interrupt rising edge status + bit_offset: 0 + bit_size: 1 + - name: ILS + description: Interrupt high-level status + bit_offset: 1 + bit_size: 1 + - name: IFS + description: Interrupt falling edge status + bit_offset: 2 + bit_size: 1 + - name: IREN + description: Interrupt rising edge detection enable bit + bit_offset: 3 + bit_size: 1 + - name: ILEN + description: Interrupt high-level detection enable bit + bit_offset: 4 + bit_size: 1 + - name: IFEN + description: Interrupt falling edge detection enable bit + bit_offset: 5 + bit_size: 1 + - name: FEMPT + description: FIFO empty status + bit_offset: 6 + bit_size: 1 enum/ACCMOD: bit_size: 2 variants: - - name: A - description: Access mode A - value: 0 - - name: B - description: Access mode B - value: 1 - - name: C - description: Access mode C - value: 2 - - name: D - description: Access mode D - value: 3 + - name: A + description: Access mode A + value: 0 + - name: B + description: Access mode B + value: 1 + - name: C + description: Access mode C + value: 2 + - name: D + description: Access mode D + value: 3 enum/CPSIZE: bit_size: 3 variants: - - name: NoBurstSplit - description: No burst split when crossing page boundary - value: 0 - - name: Bytes128 - description: 128 bytes CRAM page size - value: 1 - - name: Bytes256 - description: 256 bytes CRAM page size - value: 2 - - name: Bytes512 - description: 512 bytes CRAM page size - value: 3 - - name: Bytes1024 - description: 1024 bytes CRAM page size - value: 4 + - name: NoBurstSplit + description: No burst split when crossing page boundary + value: 0 + - name: Bytes128 + description: 128 bytes CRAM page size + value: 1 + - name: Bytes256 + description: 256 bytes CRAM page size + value: 2 + - name: Bytes512 + description: 512 bytes CRAM page size + value: 3 + - name: Bytes1024 + description: 1024 bytes CRAM page size + value: 4 enum/ECCPS: bit_size: 3 variants: - - name: Bytes256 - description: ECC page size 256 bytes - value: 0 - - name: Bytes512 - description: ECC page size 512 bytes - value: 1 - - name: Bytes1024 - description: ECC page size 1024 bytes - value: 2 - - name: Bytes2048 - description: ECC page size 2048 bytes - value: 3 - - name: Bytes4096 - description: ECC page size 4096 bytes - value: 4 - - name: Bytes8192 - description: ECC page size 8192 bytes - value: 5 + - name: Bytes256 + description: ECC page size 256 bytes + value: 0 + - name: Bytes512 + description: ECC page size 512 bytes + value: 1 + - name: Bytes1024 + description: ECC page size 1024 bytes + value: 2 + - name: Bytes2048 + description: ECC page size 2048 bytes + value: 3 + - name: Bytes4096 + description: ECC page size 4096 bytes + value: 4 + - name: Bytes8192 + description: ECC page size 8192 bytes + value: 5 enum/MTYP: bit_size: 2 variants: - - name: SRAM - description: SRAM memory type - value: 0 - - name: PSRAM - description: PSRAM (CRAM) memory type - value: 1 - - name: Flash - description: NOR Flash/OneNAND Flash - value: 2 + - name: SRAM + description: SRAM memory type + value: 0 + - name: PSRAM + description: PSRAM (CRAM) memory type + value: 1 + - name: Flash + description: NOR Flash/OneNAND Flash + value: 2 enum/MWID: bit_size: 2 variants: - - name: Bits8 - description: Memory data bus width 8 bits - value: 0 - - name: Bits16 - description: Memory data bus width 16 bits - value: 1 - - name: Bits32 - description: Memory data bus width 32 bits - value: 2 + - name: Bits8 + description: Memory data bus width 8 bits + value: 0 + - name: Bits16 + description: Memory data bus width 16 bits + value: 1 + - name: Bits32 + description: Memory data bus width 32 bits + value: 2 enum/PTYP: bit_size: 1 variants: - - name: NANDFlash - description: NAND Flash - value: 1 + - name: NANDFlash + description: NAND Flash + value: 1 enum/PWID: bit_size: 2 variants: - - name: Bits8 - description: External memory device width 8 bits - value: 0 - - name: Bits16 - description: External memory device width 16 bits - value: 1 + - name: Bits8 + description: External memory device width 8 bits + value: 0 + - name: Bits16 + description: External memory device width 16 bits + value: 1 enum/WAITCFG: bit_size: 1 variants: - - name: BeforeWaitState - description: NWAIT signal is active one data cycle before wait state - value: 0 - - name: DuringWaitState - description: NWAIT signal is active during wait state - value: 1 + - name: BeforeWaitState + description: NWAIT signal is active one data cycle before wait state + value: 0 + - name: DuringWaitState + description: NWAIT signal is active during wait state + value: 1 enum/WAITPOL: bit_size: 1 variants: - - name: ActiveLow - description: NWAIT active low - value: 0 - - name: ActiveHigh - description: NWAIT active high - value: 1 + - name: ActiveLow + description: NWAIT active low + value: 0 + - name: ActiveHigh + description: NWAIT active high + value: 1 diff --git a/data/registers/fsmc_v4x1.yaml b/data/registers/fsmc_v4x1.yaml index 7935fdc..f0b7023 100644 --- a/data/registers/fsmc_v4x1.yaml +++ b/data/registers/fsmc_v4x1.yaml @@ -1,514 +1,513 @@ ---- block/FSMC: description: Flexible static memory controller items: - - name: BCR1 - description: SRAM/NOR-Flash chip-select control register 1 - byte_offset: 0 - fieldset: BCR1 - - name: BTR - description: SRAM/NOR-Flash chip-select timing register 1-4 - array: - len: 4 - stride: 8 - byte_offset: 4 - fieldset: BTR - - name: BCR - description: SRAM/NOR-Flash chip-select control register 2-4 - array: - len: 3 - stride: 8 - byte_offset: 8 - fieldset: BCR - - name: PCSCNTR - description: PSRAM chip select counter register - byte_offset: 32 - fieldset: PCSCNTR - - name: PCR - description: PC Card/NAND Flash control register - byte_offset: 128 - fieldset: PCR - - name: SR - description: FIFO status and interrupt register - byte_offset: 132 - fieldset: SR - - name: PMEM - description: Common memory space timing register - byte_offset: 136 - fieldset: PMEM - - name: PATT - description: Attribute memory space timing register - byte_offset: 140 - fieldset: PATT - - name: ECCR - description: ECC result register - byte_offset: 148 - access: Read - fieldset: ECCR - - name: BWTR - description: SRAM/NOR-Flash write timing registers 1-4 - array: - len: 4 - stride: 8 - byte_offset: 260 - fieldset: BWTR + - name: BCR1 + description: SRAM/NOR-Flash chip-select control register 1 + byte_offset: 0 + fieldset: BCR1 + - name: BTR + description: SRAM/NOR-Flash chip-select timing register 1-4 + array: + len: 4 + stride: 8 + byte_offset: 4 + fieldset: BTR + - name: BCR + description: SRAM/NOR-Flash chip-select control register 2-4 + array: + len: 3 + stride: 8 + byte_offset: 8 + fieldset: BCR + - name: PCSCNTR + description: PSRAM chip select counter register + byte_offset: 32 + fieldset: PCSCNTR + - name: PCR + description: PC Card/NAND Flash control register + byte_offset: 128 + fieldset: PCR + - name: SR + description: FIFO status and interrupt register + byte_offset: 132 + fieldset: SR + - name: PMEM + description: Common memory space timing register + byte_offset: 136 + fieldset: PMEM + - name: PATT + description: Attribute memory space timing register + byte_offset: 140 + fieldset: PATT + - name: ECCR + description: ECC result register + byte_offset: 148 + access: Read + fieldset: ECCR + - name: BWTR + description: SRAM/NOR-Flash write timing registers 1-4 + array: + len: 4 + stride: 8 + byte_offset: 260 + fieldset: BWTR fieldset/BCR: description: SRAM/NOR-Flash chip-select control register 2-4 fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 - - name: NBLSET - description: Byte lane (NBL) setup - bit_offset: 22 - bit_size: 2 + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 + - name: NBLSET + description: Byte lane (NBL) setup + bit_offset: 22 + bit_size: 2 fieldset/BCR1: description: SRAM/NOR-Flash chip-select control register 1 fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 - - name: CCLKEN - description: Continuous clock enable - bit_offset: 20 - bit_size: 1 - - name: WFDIS - description: Write FIFO disable - bit_offset: 21 - bit_size: 1 - - name: NBLSET - description: Byte lane (NBL) setup - bit_offset: 22 - bit_size: 2 - - name: FMCEN - description: FMC controller enable - bit_offset: 31 - bit_size: 1 + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 + - name: CCLKEN + description: Continuous clock enable + bit_offset: 20 + bit_size: 1 + - name: WFDIS + description: Write FIFO disable + bit_offset: 21 + bit_size: 1 + - name: NBLSET + description: Byte lane (NBL) setup + bit_offset: 22 + bit_size: 2 + - name: FMCEN + description: FMC controller enable + bit_offset: 31 + bit_size: 1 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - - name: CLKDIV - description: Clock divide ratio (for FMC_CLK signal) - bit_offset: 20 - bit_size: 4 - - name: DATLAT - description: Data latency for synchronous memory - bit_offset: 24 - bit_size: 4 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD - - name: DATAHLD - description: Data hold phase duration - bit_offset: 30 - bit_size: 2 + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 + - name: CLKDIV + description: Clock divide ratio (for FMC_CLK signal) + bit_offset: 20 + bit_size: 4 + - name: DATLAT + description: Data latency for synchronous memory + bit_offset: 24 + bit_size: 4 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD + - name: DATAHLD + description: Data hold phase duration + bit_offset: 30 + bit_size: 2 fieldset/BWTR: description: SRAM/NOR-Flash write timing registers fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD - - name: DATAHLD - description: Data hold phase duration - bit_offset: 30 - bit_size: 2 + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD + - name: DATAHLD + description: Data hold phase duration + bit_offset: 30 + bit_size: 2 fieldset/ECCR: description: ECC result register fields: - - name: ECC - description: ECC computation result value - bit_offset: 0 - bit_size: 32 + - name: ECC + description: ECC computation result value + bit_offset: 0 + bit_size: 32 fieldset/PATT: description: Attribute memory space timing register fields: - - name: ATTSET - description: Attribute memory setup time - bit_offset: 0 - bit_size: 8 - - name: ATTWAIT - description: Attribute memory wait time - bit_offset: 8 - bit_size: 8 - - name: ATTHOLD - description: Attribute memory hold time - bit_offset: 16 - bit_size: 8 - - name: ATTHIZ - description: Attribute memory data bus Hi-Z time - bit_offset: 24 - bit_size: 8 + - name: ATTSET + description: Attribute memory setup time + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: Attribute memory wait time + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: Attribute memory hold time + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: Attribute memory data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/PCR: description: PC Card/NAND Flash control register fields: - - name: PWAITEN - description: Wait feature enable bit - bit_offset: 1 - bit_size: 1 - - name: PBKEN - description: NAND Flash memory bank enable bit - bit_offset: 2 - bit_size: 1 - - name: PTYP - description: Memory type - bit_offset: 3 - bit_size: 1 - enum: PTYP - - name: PWID - description: Data bus width - bit_offset: 4 - bit_size: 2 - enum: PWID - - name: ECCEN - description: ECC computation logic enable bit - bit_offset: 6 - bit_size: 1 - - name: TCLR - description: CLE to RE delay - bit_offset: 9 - bit_size: 4 - - name: TAR - description: ALE to RE delay - bit_offset: 13 - bit_size: 4 - - name: ECCPS - description: ECC page size - bit_offset: 17 - bit_size: 3 - enum: ECCPS + - name: PWAITEN + description: Wait feature enable bit + bit_offset: 1 + bit_size: 1 + - name: PBKEN + description: NAND Flash memory bank enable bit + bit_offset: 2 + bit_size: 1 + - name: PTYP + description: Memory type + bit_offset: 3 + bit_size: 1 + enum: PTYP + - name: PWID + description: Data bus width + bit_offset: 4 + bit_size: 2 + enum: PWID + - name: ECCEN + description: ECC computation logic enable bit + bit_offset: 6 + bit_size: 1 + - name: TCLR + description: CLE to RE delay + bit_offset: 9 + bit_size: 4 + - name: TAR + description: ALE to RE delay + bit_offset: 13 + bit_size: 4 + - name: ECCPS + description: ECC page size + bit_offset: 17 + bit_size: 3 + enum: ECCPS fieldset/PCSCNTR: description: PSRAM chip select counter register fields: - - name: CSCOUNT - description: Chip select counter - bit_offset: 0 - bit_size: 16 - - name: CNTB1EN - description: Counter Bank 1 enable - bit_offset: 16 - bit_size: 1 - - name: CNTB2EN - description: Counter Bank 2 enable - bit_offset: 17 - bit_size: 1 - - name: CNTB3EN - description: Counter Bank 3 enable - bit_offset: 18 - bit_size: 1 - - name: CNTB4EN - description: Counter Bank 4 enable - bit_offset: 19 - bit_size: 1 + - name: CSCOUNT + description: Chip select counter + bit_offset: 0 + bit_size: 16 + - name: CNTB1EN + description: Counter Bank 1 enable + bit_offset: 16 + bit_size: 1 + - name: CNTB2EN + description: Counter Bank 2 enable + bit_offset: 17 + bit_size: 1 + - name: CNTB3EN + description: Counter Bank 3 enable + bit_offset: 18 + bit_size: 1 + - name: CNTB4EN + description: Counter Bank 4 enable + bit_offset: 19 + bit_size: 1 fieldset/PMEM: description: Common memory space timing register fields: - - name: MEMSET - description: Common memory x setup time - bit_offset: 0 - bit_size: 8 - - name: MEMWAIT - description: Common memory wait time - bit_offset: 8 - bit_size: 8 - - name: MEMHOLD - description: Common memory hold time - bit_offset: 16 - bit_size: 8 - - name: MEMHIZ - description: Common memory x data bus Hi-Z time - bit_offset: 24 - bit_size: 8 + - name: MEMSET + description: Common memory x setup time + bit_offset: 0 + bit_size: 8 + - name: MEMWAIT + description: Common memory wait time + bit_offset: 8 + bit_size: 8 + - name: MEMHOLD + description: Common memory hold time + bit_offset: 16 + bit_size: 8 + - name: MEMHIZ + description: Common memory x data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/SR: description: FIFO status and interrupt register fields: - - name: IRS - description: Interrupt rising edge status - bit_offset: 0 - bit_size: 1 - - name: ILS - description: Interrupt high-level status - bit_offset: 1 - bit_size: 1 - - name: IFS - description: Interrupt falling edge status - bit_offset: 2 - bit_size: 1 - - name: IREN - description: Interrupt rising edge detection enable bit - bit_offset: 3 - bit_size: 1 - - name: ILEN - description: Interrupt high-level detection enable bit - bit_offset: 4 - bit_size: 1 - - name: IFEN - description: Interrupt falling edge detection enable bit - bit_offset: 5 - bit_size: 1 - - name: FEMPT - description: FIFO empty status - bit_offset: 6 - bit_size: 1 + - name: IRS + description: Interrupt rising edge status + bit_offset: 0 + bit_size: 1 + - name: ILS + description: Interrupt high-level status + bit_offset: 1 + bit_size: 1 + - name: IFS + description: Interrupt falling edge status + bit_offset: 2 + bit_size: 1 + - name: IREN + description: Interrupt rising edge detection enable bit + bit_offset: 3 + bit_size: 1 + - name: ILEN + description: Interrupt high-level detection enable bit + bit_offset: 4 + bit_size: 1 + - name: IFEN + description: Interrupt falling edge detection enable bit + bit_offset: 5 + bit_size: 1 + - name: FEMPT + description: FIFO empty status + bit_offset: 6 + bit_size: 1 enum/ACCMOD: bit_size: 2 variants: - - name: A - description: Access mode A - value: 0 - - name: B - description: Access mode B - value: 1 - - name: C - description: Access mode C - value: 2 - - name: D - description: Access mode D - value: 3 + - name: A + description: Access mode A + value: 0 + - name: B + description: Access mode B + value: 1 + - name: C + description: Access mode C + value: 2 + - name: D + description: Access mode D + value: 3 enum/CPSIZE: bit_size: 3 variants: - - name: NoBurstSplit - description: No burst split when crossing page boundary - value: 0 - - name: Bytes128 - description: 128 bytes CRAM page size - value: 1 - - name: Bytes256 - description: 256 bytes CRAM page size - value: 2 - - name: Bytes512 - description: 512 bytes CRAM page size - value: 3 - - name: Bytes1024 - description: 1024 bytes CRAM page size - value: 4 + - name: NoBurstSplit + description: No burst split when crossing page boundary + value: 0 + - name: Bytes128 + description: 128 bytes CRAM page size + value: 1 + - name: Bytes256 + description: 256 bytes CRAM page size + value: 2 + - name: Bytes512 + description: 512 bytes CRAM page size + value: 3 + - name: Bytes1024 + description: 1024 bytes CRAM page size + value: 4 enum/ECCPS: bit_size: 3 variants: - - name: Bytes256 - description: ECC page size 256 bytes - value: 0 - - name: Bytes512 - description: ECC page size 512 bytes - value: 1 - - name: Bytes1024 - description: ECC page size 1024 bytes - value: 2 - - name: Bytes2048 - description: ECC page size 2048 bytes - value: 3 - - name: Bytes4096 - description: ECC page size 4096 bytes - value: 4 - - name: Bytes8192 - description: ECC page size 8192 bytes - value: 5 + - name: Bytes256 + description: ECC page size 256 bytes + value: 0 + - name: Bytes512 + description: ECC page size 512 bytes + value: 1 + - name: Bytes1024 + description: ECC page size 1024 bytes + value: 2 + - name: Bytes2048 + description: ECC page size 2048 bytes + value: 3 + - name: Bytes4096 + description: ECC page size 4096 bytes + value: 4 + - name: Bytes8192 + description: ECC page size 8192 bytes + value: 5 enum/MTYP: bit_size: 2 variants: - - name: SRAM - description: SRAM memory type - value: 0 - - name: PSRAM - description: PSRAM (CRAM) memory type - value: 1 - - name: Flash - description: NOR Flash/OneNAND Flash - value: 2 + - name: SRAM + description: SRAM memory type + value: 0 + - name: PSRAM + description: PSRAM (CRAM) memory type + value: 1 + - name: Flash + description: NOR Flash/OneNAND Flash + value: 2 enum/MWID: bit_size: 2 variants: - - name: Bits8 - description: Memory data bus width 8 bits - value: 0 - - name: Bits16 - description: Memory data bus width 16 bits - value: 1 - - name: Bits32 - description: Memory data bus width 32 bits - value: 2 + - name: Bits8 + description: Memory data bus width 8 bits + value: 0 + - name: Bits16 + description: Memory data bus width 16 bits + value: 1 + - name: Bits32 + description: Memory data bus width 32 bits + value: 2 enum/PTYP: bit_size: 1 variants: - - name: NANDFlash - description: NAND Flash - value: 1 + - name: NANDFlash + description: NAND Flash + value: 1 enum/PWID: bit_size: 2 variants: - - name: Bits8 - description: External memory device width 8 bits - value: 0 - - name: Bits16 - description: External memory device width 16 bits - value: 1 + - name: Bits8 + description: External memory device width 8 bits + value: 0 + - name: Bits16 + description: External memory device width 16 bits + value: 1 enum/WAITCFG: bit_size: 1 variants: - - name: BeforeWaitState - description: NWAIT signal is active one data cycle before wait state - value: 0 - - name: DuringWaitState - description: NWAIT signal is active during wait state - value: 1 + - name: BeforeWaitState + description: NWAIT signal is active one data cycle before wait state + value: 0 + - name: DuringWaitState + description: NWAIT signal is active during wait state + value: 1 enum/WAITPOL: bit_size: 1 variants: - - name: ActiveLow - description: NWAIT active low - value: 0 - - name: ActiveHigh - description: NWAIT active high - value: 1 + - name: ActiveLow + description: NWAIT active low + value: 0 + - name: ActiveHigh + description: NWAIT active high + value: 1 diff --git a/data/registers/fsmc_v5x1.yaml b/data/registers/fsmc_v5x1.yaml index 7935fdc..f0b7023 100644 --- a/data/registers/fsmc_v5x1.yaml +++ b/data/registers/fsmc_v5x1.yaml @@ -1,514 +1,513 @@ ---- block/FSMC: description: Flexible static memory controller items: - - name: BCR1 - description: SRAM/NOR-Flash chip-select control register 1 - byte_offset: 0 - fieldset: BCR1 - - name: BTR - description: SRAM/NOR-Flash chip-select timing register 1-4 - array: - len: 4 - stride: 8 - byte_offset: 4 - fieldset: BTR - - name: BCR - description: SRAM/NOR-Flash chip-select control register 2-4 - array: - len: 3 - stride: 8 - byte_offset: 8 - fieldset: BCR - - name: PCSCNTR - description: PSRAM chip select counter register - byte_offset: 32 - fieldset: PCSCNTR - - name: PCR - description: PC Card/NAND Flash control register - byte_offset: 128 - fieldset: PCR - - name: SR - description: FIFO status and interrupt register - byte_offset: 132 - fieldset: SR - - name: PMEM - description: Common memory space timing register - byte_offset: 136 - fieldset: PMEM - - name: PATT - description: Attribute memory space timing register - byte_offset: 140 - fieldset: PATT - - name: ECCR - description: ECC result register - byte_offset: 148 - access: Read - fieldset: ECCR - - name: BWTR - description: SRAM/NOR-Flash write timing registers 1-4 - array: - len: 4 - stride: 8 - byte_offset: 260 - fieldset: BWTR + - name: BCR1 + description: SRAM/NOR-Flash chip-select control register 1 + byte_offset: 0 + fieldset: BCR1 + - name: BTR + description: SRAM/NOR-Flash chip-select timing register 1-4 + array: + len: 4 + stride: 8 + byte_offset: 4 + fieldset: BTR + - name: BCR + description: SRAM/NOR-Flash chip-select control register 2-4 + array: + len: 3 + stride: 8 + byte_offset: 8 + fieldset: BCR + - name: PCSCNTR + description: PSRAM chip select counter register + byte_offset: 32 + fieldset: PCSCNTR + - name: PCR + description: PC Card/NAND Flash control register + byte_offset: 128 + fieldset: PCR + - name: SR + description: FIFO status and interrupt register + byte_offset: 132 + fieldset: SR + - name: PMEM + description: Common memory space timing register + byte_offset: 136 + fieldset: PMEM + - name: PATT + description: Attribute memory space timing register + byte_offset: 140 + fieldset: PATT + - name: ECCR + description: ECC result register + byte_offset: 148 + access: Read + fieldset: ECCR + - name: BWTR + description: SRAM/NOR-Flash write timing registers 1-4 + array: + len: 4 + stride: 8 + byte_offset: 260 + fieldset: BWTR fieldset/BCR: description: SRAM/NOR-Flash chip-select control register 2-4 fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 - - name: NBLSET - description: Byte lane (NBL) setup - bit_offset: 22 - bit_size: 2 + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 + - name: NBLSET + description: Byte lane (NBL) setup + bit_offset: 22 + bit_size: 2 fieldset/BCR1: description: SRAM/NOR-Flash chip-select control register 1 fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 - - name: CCLKEN - description: Continuous clock enable - bit_offset: 20 - bit_size: 1 - - name: WFDIS - description: Write FIFO disable - bit_offset: 21 - bit_size: 1 - - name: NBLSET - description: Byte lane (NBL) setup - bit_offset: 22 - bit_size: 2 - - name: FMCEN - description: FMC controller enable - bit_offset: 31 - bit_size: 1 + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 + - name: CCLKEN + description: Continuous clock enable + bit_offset: 20 + bit_size: 1 + - name: WFDIS + description: Write FIFO disable + bit_offset: 21 + bit_size: 1 + - name: NBLSET + description: Byte lane (NBL) setup + bit_offset: 22 + bit_size: 2 + - name: FMCEN + description: FMC controller enable + bit_offset: 31 + bit_size: 1 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - - name: CLKDIV - description: Clock divide ratio (for FMC_CLK signal) - bit_offset: 20 - bit_size: 4 - - name: DATLAT - description: Data latency for synchronous memory - bit_offset: 24 - bit_size: 4 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD - - name: DATAHLD - description: Data hold phase duration - bit_offset: 30 - bit_size: 2 + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 + - name: CLKDIV + description: Clock divide ratio (for FMC_CLK signal) + bit_offset: 20 + bit_size: 4 + - name: DATLAT + description: Data latency for synchronous memory + bit_offset: 24 + bit_size: 4 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD + - name: DATAHLD + description: Data hold phase duration + bit_offset: 30 + bit_size: 2 fieldset/BWTR: description: SRAM/NOR-Flash write timing registers fields: - - name: ADDSET - description: Address setup phase duration - bit_offset: 0 - bit_size: 4 - - name: ADDHLD - description: Address-hold phase duration - bit_offset: 4 - bit_size: 4 - - name: DATAST - description: Data-phase duration - bit_offset: 8 - bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - - name: ACCMOD - description: Access mode - bit_offset: 28 - bit_size: 2 - enum: ACCMOD - - name: DATAHLD - description: Data hold phase duration - bit_offset: 30 - bit_size: 2 + - name: ADDSET + description: Address setup phase duration + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: Address-hold phase duration + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: Data-phase duration + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 + - name: ACCMOD + description: Access mode + bit_offset: 28 + bit_size: 2 + enum: ACCMOD + - name: DATAHLD + description: Data hold phase duration + bit_offset: 30 + bit_size: 2 fieldset/ECCR: description: ECC result register fields: - - name: ECC - description: ECC computation result value - bit_offset: 0 - bit_size: 32 + - name: ECC + description: ECC computation result value + bit_offset: 0 + bit_size: 32 fieldset/PATT: description: Attribute memory space timing register fields: - - name: ATTSET - description: Attribute memory setup time - bit_offset: 0 - bit_size: 8 - - name: ATTWAIT - description: Attribute memory wait time - bit_offset: 8 - bit_size: 8 - - name: ATTHOLD - description: Attribute memory hold time - bit_offset: 16 - bit_size: 8 - - name: ATTHIZ - description: Attribute memory data bus Hi-Z time - bit_offset: 24 - bit_size: 8 + - name: ATTSET + description: Attribute memory setup time + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: Attribute memory wait time + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: Attribute memory hold time + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: Attribute memory data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/PCR: description: PC Card/NAND Flash control register fields: - - name: PWAITEN - description: Wait feature enable bit - bit_offset: 1 - bit_size: 1 - - name: PBKEN - description: NAND Flash memory bank enable bit - bit_offset: 2 - bit_size: 1 - - name: PTYP - description: Memory type - bit_offset: 3 - bit_size: 1 - enum: PTYP - - name: PWID - description: Data bus width - bit_offset: 4 - bit_size: 2 - enum: PWID - - name: ECCEN - description: ECC computation logic enable bit - bit_offset: 6 - bit_size: 1 - - name: TCLR - description: CLE to RE delay - bit_offset: 9 - bit_size: 4 - - name: TAR - description: ALE to RE delay - bit_offset: 13 - bit_size: 4 - - name: ECCPS - description: ECC page size - bit_offset: 17 - bit_size: 3 - enum: ECCPS + - name: PWAITEN + description: Wait feature enable bit + bit_offset: 1 + bit_size: 1 + - name: PBKEN + description: NAND Flash memory bank enable bit + bit_offset: 2 + bit_size: 1 + - name: PTYP + description: Memory type + bit_offset: 3 + bit_size: 1 + enum: PTYP + - name: PWID + description: Data bus width + bit_offset: 4 + bit_size: 2 + enum: PWID + - name: ECCEN + description: ECC computation logic enable bit + bit_offset: 6 + bit_size: 1 + - name: TCLR + description: CLE to RE delay + bit_offset: 9 + bit_size: 4 + - name: TAR + description: ALE to RE delay + bit_offset: 13 + bit_size: 4 + - name: ECCPS + description: ECC page size + bit_offset: 17 + bit_size: 3 + enum: ECCPS fieldset/PCSCNTR: description: PSRAM chip select counter register fields: - - name: CSCOUNT - description: Chip select counter - bit_offset: 0 - bit_size: 16 - - name: CNTB1EN - description: Counter Bank 1 enable - bit_offset: 16 - bit_size: 1 - - name: CNTB2EN - description: Counter Bank 2 enable - bit_offset: 17 - bit_size: 1 - - name: CNTB3EN - description: Counter Bank 3 enable - bit_offset: 18 - bit_size: 1 - - name: CNTB4EN - description: Counter Bank 4 enable - bit_offset: 19 - bit_size: 1 + - name: CSCOUNT + description: Chip select counter + bit_offset: 0 + bit_size: 16 + - name: CNTB1EN + description: Counter Bank 1 enable + bit_offset: 16 + bit_size: 1 + - name: CNTB2EN + description: Counter Bank 2 enable + bit_offset: 17 + bit_size: 1 + - name: CNTB3EN + description: Counter Bank 3 enable + bit_offset: 18 + bit_size: 1 + - name: CNTB4EN + description: Counter Bank 4 enable + bit_offset: 19 + bit_size: 1 fieldset/PMEM: description: Common memory space timing register fields: - - name: MEMSET - description: Common memory x setup time - bit_offset: 0 - bit_size: 8 - - name: MEMWAIT - description: Common memory wait time - bit_offset: 8 - bit_size: 8 - - name: MEMHOLD - description: Common memory hold time - bit_offset: 16 - bit_size: 8 - - name: MEMHIZ - description: Common memory x data bus Hi-Z time - bit_offset: 24 - bit_size: 8 + - name: MEMSET + description: Common memory x setup time + bit_offset: 0 + bit_size: 8 + - name: MEMWAIT + description: Common memory wait time + bit_offset: 8 + bit_size: 8 + - name: MEMHOLD + description: Common memory hold time + bit_offset: 16 + bit_size: 8 + - name: MEMHIZ + description: Common memory x data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/SR: description: FIFO status and interrupt register fields: - - name: IRS - description: Interrupt rising edge status - bit_offset: 0 - bit_size: 1 - - name: ILS - description: Interrupt high-level status - bit_offset: 1 - bit_size: 1 - - name: IFS - description: Interrupt falling edge status - bit_offset: 2 - bit_size: 1 - - name: IREN - description: Interrupt rising edge detection enable bit - bit_offset: 3 - bit_size: 1 - - name: ILEN - description: Interrupt high-level detection enable bit - bit_offset: 4 - bit_size: 1 - - name: IFEN - description: Interrupt falling edge detection enable bit - bit_offset: 5 - bit_size: 1 - - name: FEMPT - description: FIFO empty status - bit_offset: 6 - bit_size: 1 + - name: IRS + description: Interrupt rising edge status + bit_offset: 0 + bit_size: 1 + - name: ILS + description: Interrupt high-level status + bit_offset: 1 + bit_size: 1 + - name: IFS + description: Interrupt falling edge status + bit_offset: 2 + bit_size: 1 + - name: IREN + description: Interrupt rising edge detection enable bit + bit_offset: 3 + bit_size: 1 + - name: ILEN + description: Interrupt high-level detection enable bit + bit_offset: 4 + bit_size: 1 + - name: IFEN + description: Interrupt falling edge detection enable bit + bit_offset: 5 + bit_size: 1 + - name: FEMPT + description: FIFO empty status + bit_offset: 6 + bit_size: 1 enum/ACCMOD: bit_size: 2 variants: - - name: A - description: Access mode A - value: 0 - - name: B - description: Access mode B - value: 1 - - name: C - description: Access mode C - value: 2 - - name: D - description: Access mode D - value: 3 + - name: A + description: Access mode A + value: 0 + - name: B + description: Access mode B + value: 1 + - name: C + description: Access mode C + value: 2 + - name: D + description: Access mode D + value: 3 enum/CPSIZE: bit_size: 3 variants: - - name: NoBurstSplit - description: No burst split when crossing page boundary - value: 0 - - name: Bytes128 - description: 128 bytes CRAM page size - value: 1 - - name: Bytes256 - description: 256 bytes CRAM page size - value: 2 - - name: Bytes512 - description: 512 bytes CRAM page size - value: 3 - - name: Bytes1024 - description: 1024 bytes CRAM page size - value: 4 + - name: NoBurstSplit + description: No burst split when crossing page boundary + value: 0 + - name: Bytes128 + description: 128 bytes CRAM page size + value: 1 + - name: Bytes256 + description: 256 bytes CRAM page size + value: 2 + - name: Bytes512 + description: 512 bytes CRAM page size + value: 3 + - name: Bytes1024 + description: 1024 bytes CRAM page size + value: 4 enum/ECCPS: bit_size: 3 variants: - - name: Bytes256 - description: ECC page size 256 bytes - value: 0 - - name: Bytes512 - description: ECC page size 512 bytes - value: 1 - - name: Bytes1024 - description: ECC page size 1024 bytes - value: 2 - - name: Bytes2048 - description: ECC page size 2048 bytes - value: 3 - - name: Bytes4096 - description: ECC page size 4096 bytes - value: 4 - - name: Bytes8192 - description: ECC page size 8192 bytes - value: 5 + - name: Bytes256 + description: ECC page size 256 bytes + value: 0 + - name: Bytes512 + description: ECC page size 512 bytes + value: 1 + - name: Bytes1024 + description: ECC page size 1024 bytes + value: 2 + - name: Bytes2048 + description: ECC page size 2048 bytes + value: 3 + - name: Bytes4096 + description: ECC page size 4096 bytes + value: 4 + - name: Bytes8192 + description: ECC page size 8192 bytes + value: 5 enum/MTYP: bit_size: 2 variants: - - name: SRAM - description: SRAM memory type - value: 0 - - name: PSRAM - description: PSRAM (CRAM) memory type - value: 1 - - name: Flash - description: NOR Flash/OneNAND Flash - value: 2 + - name: SRAM + description: SRAM memory type + value: 0 + - name: PSRAM + description: PSRAM (CRAM) memory type + value: 1 + - name: Flash + description: NOR Flash/OneNAND Flash + value: 2 enum/MWID: bit_size: 2 variants: - - name: Bits8 - description: Memory data bus width 8 bits - value: 0 - - name: Bits16 - description: Memory data bus width 16 bits - value: 1 - - name: Bits32 - description: Memory data bus width 32 bits - value: 2 + - name: Bits8 + description: Memory data bus width 8 bits + value: 0 + - name: Bits16 + description: Memory data bus width 16 bits + value: 1 + - name: Bits32 + description: Memory data bus width 32 bits + value: 2 enum/PTYP: bit_size: 1 variants: - - name: NANDFlash - description: NAND Flash - value: 1 + - name: NANDFlash + description: NAND Flash + value: 1 enum/PWID: bit_size: 2 variants: - - name: Bits8 - description: External memory device width 8 bits - value: 0 - - name: Bits16 - description: External memory device width 16 bits - value: 1 + - name: Bits8 + description: External memory device width 8 bits + value: 0 + - name: Bits16 + description: External memory device width 16 bits + value: 1 enum/WAITCFG: bit_size: 1 variants: - - name: BeforeWaitState - description: NWAIT signal is active one data cycle before wait state - value: 0 - - name: DuringWaitState - description: NWAIT signal is active during wait state - value: 1 + - name: BeforeWaitState + description: NWAIT signal is active one data cycle before wait state + value: 0 + - name: DuringWaitState + description: NWAIT signal is active during wait state + value: 1 enum/WAITPOL: bit_size: 1 variants: - - name: ActiveLow - description: NWAIT active low - value: 0 - - name: ActiveHigh - description: NWAIT active high - value: 1 + - name: ActiveLow + description: NWAIT active low + value: 0 + - name: ActiveHigh + description: NWAIT active high + value: 1 diff --git a/data/registers/gpdma_v1.yaml b/data/registers/gpdma_v1.yaml index f285c3d..6e06b48 100644 --- a/data/registers/gpdma_v1.yaml +++ b/data/registers/gpdma_v1.yaml @@ -1,597 +1,600 @@ ---- block/Channel: items: - - name: LBAR - description: GPDMA channel 15 linked-list base address register - byte_offset: 0 - fieldset: CH_LBAR - - name: FCR - description: GPDMA channel 15 flag clear register - byte_offset: 12 - fieldset: CH_FCR - - name: SR - description: GPDMA channel 15 status register - byte_offset: 16 - fieldset: CH_SR - - name: CR - description: GPDMA channel 15 control register - byte_offset: 20 - fieldset: CH_CR - - name: TR1 - description: GPDMA channel 15 transfer register 1 - byte_offset: 64 - fieldset: CH_TR1 - - name: TR2 - description: GPDMA channel 15 transfer register 2 - byte_offset: 68 - fieldset: CH_TR2 - - name: BR1 - description: GPDMA channel 15 alternate block register 1 - byte_offset: 72 - fieldset: CH_BR1 - - name: SAR - description: GPDMA channel 15 source address register - byte_offset: 76 - - name: DAR - description: GPDMA channel 15 destination address register - byte_offset: 80 - - name: TR3 - description: GPDMA channel 15 transfer register 3 - byte_offset: 84 - fieldset: CH_TR3 - - name: BR2 - description: GPDMA channel 15 block register 2 - byte_offset: 88 - fieldset: CH_BR2 - - name: LLR - description: GPDMA channel 15 alternate linked-list address register - byte_offset: 124 - fieldset: CH_LLR + - name: LBAR + description: GPDMA channel 15 linked-list base address register + byte_offset: 0 + fieldset: CH_LBAR + - name: FCR + description: GPDMA channel 15 flag clear register + byte_offset: 12 + fieldset: CH_FCR + - name: SR + description: GPDMA channel 15 status register + byte_offset: 16 + fieldset: CH_SR + - name: CR + description: GPDMA channel 15 control register + byte_offset: 20 + fieldset: CH_CR + - name: TR1 + description: GPDMA channel 15 transfer register 1 + byte_offset: 64 + fieldset: CH_TR1 + - name: TR2 + description: GPDMA channel 15 transfer register 2 + byte_offset: 68 + fieldset: CH_TR2 + - name: BR1 + description: GPDMA channel 15 alternate block register 1 + byte_offset: 72 + fieldset: CH_BR1 + - name: SAR + description: GPDMA channel 15 source address register + byte_offset: 76 + - name: DAR + description: GPDMA channel 15 destination address register + byte_offset: 80 + - name: TR3 + description: GPDMA channel 15 transfer register 3 + byte_offset: 84 + fieldset: CH_TR3 + - name: BR2 + description: GPDMA channel 15 block register 2 + byte_offset: 88 + fieldset: CH_BR2 + - name: LLR + description: GPDMA channel 15 alternate linked-list address register + byte_offset: 124 + fieldset: CH_LLR block/GPDMA: description: GPDMA items: - - name: SECCFGR - description: GPDMA secure configuration register - byte_offset: 0 - fieldset: SECCFGR - - name: PRIVCFGR - description: GPDMA privileged configuration register - byte_offset: 4 - fieldset: PRIVCFGR - - name: RCFGLOCKR - description: GPDMA configuration lock register - byte_offset: 8 - fieldset: RCFGLOCKR - - name: MISR - description: GPDMA non-secure masked interrupt status register - byte_offset: 12 - fieldset: MISR - - name: SMISR - description: GPDMA secure masked interrupt status register - byte_offset: 16 - fieldset: MISR - - name: CH - array: - len: 16 - stride: 128 - byte_offset: 80 - block: Channel + - name: SECCFGR + description: GPDMA secure configuration register + byte_offset: 0 + fieldset: SECCFGR + - name: PRIVCFGR + description: GPDMA privileged configuration register + byte_offset: 4 + fieldset: PRIVCFGR + - name: RCFGLOCKR + description: GPDMA configuration lock register + byte_offset: 8 + fieldset: RCFGLOCKR + - name: MISR + description: GPDMA non-secure masked interrupt status register + byte_offset: 12 + fieldset: MISR + - name: SMISR + description: GPDMA secure masked interrupt status register + byte_offset: 16 + fieldset: MISR + - name: CH + array: + len: 16 + stride: 128 + byte_offset: 80 + block: Channel fieldset/CH_BR1: description: GPDMA channel 15 alternate block register 1 fields: - - name: BNDT - description: "block number of data bytes to transfer from the source. Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if CH[x].LLR.UB1 = 1, this field is updated by the LLI in the memory. - if CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if CH[x].LLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (CH[x].TR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued." - bit_offset: 0 - bit_size: 16 - - name: BRC - description: "Block repeat counter. This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If CH[x].LLR.UB1 = 1, all CH[x].BR1 fields are updated by the next LLI in the memory. If CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if CH[x].LLR = 0, this field is kept as zero following the last LLI and data transfer." - bit_offset: 16 - bit_size: 11 - - name: SDEC - description: source address decrement - bit_offset: 28 - bit_size: 1 - enum: CH_BR1_DEC - - name: DDEC - description: destination address decrement - bit_offset: 29 - bit_size: 1 - enum: CH_BR1_DEC - - name: BRSDEC - description: "Block repeat source address decrement. Note: On top of this increment/decrement (depending on BRSDEC), CH[x].SAR is in the same time also updated by the increment/decrement (depending on SDEC) of the CH[x].TR3.SAO value, as it is done after any programmed burst transfer." - bit_offset: 30 - bit_size: 1 - enum: CH_BR1_DEC - - name: BRDDEC - description: "Block repeat destination address decrement. Note: On top of this increment/decrement (depending on BRDDEC), CH[x].DAR is in the same time also updated by the increment/decrement (depending on DDEC) of the CH[x].TR3.DAO value, as it is usually done at the end of each programmed burst transfer." - bit_offset: 31 - bit_size: 1 - enum: CH_BR1_DEC + - name: BNDT + description: 'block number of data bytes to transfer from the source. Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if CH[x].LLR.UB1 = 1, this field is updated by the LLI in the memory. - if CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if CH[x].LLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (CH[x].TR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued.' + bit_offset: 0 + bit_size: 16 + - name: BRC + description: 'Block repeat counter. This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If CH[x].LLR.UB1 = 1, all CH[x].BR1 fields are updated by the next LLI in the memory. If CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if CH[x].LLR = 0, this field is kept as zero following the last LLI and data transfer.' + bit_offset: 16 + bit_size: 11 + - name: SDEC + description: source address decrement + bit_offset: 28 + bit_size: 1 + enum: CH_BR1_DEC + - name: DDEC + description: destination address decrement + bit_offset: 29 + bit_size: 1 + enum: CH_BR1_DEC + - name: BRSDEC + description: 'Block repeat source address decrement. Note: On top of this increment/decrement (depending on BRSDEC), CH[x].SAR is in the same time also updated by the increment/decrement (depending on SDEC) of the CH[x].TR3.SAO value, as it is done after any programmed burst transfer.' + bit_offset: 30 + bit_size: 1 + enum: CH_BR1_DEC + - name: BRDDEC + description: 'Block repeat destination address decrement. Note: On top of this increment/decrement (depending on BRDDEC), CH[x].DAR is in the same time also updated by the increment/decrement (depending on DDEC) of the CH[x].TR3.DAO value, as it is usually done at the end of each programmed burst transfer.' + bit_offset: 31 + bit_size: 1 + enum: CH_BR1_DEC fieldset/CH_BR2: description: GPDMA channel 12 block register 2 fields: - - name: BRSAO - description: "Block repeated source address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRSDEC) the current source address (CH[x].SAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued." - bit_offset: 0 - bit_size: 16 - - name: BRDAO - description: "Block repeated destination address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRDDEC) the current destination address (CH[x].DAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued." - bit_offset: 16 - bit_size: 16 + - name: BRSAO + description: 'Block repeated source address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRSDEC) the current source address (CH[x].SAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued.' + bit_offset: 0 + bit_size: 16 + - name: BRDAO + description: 'Block repeated destination address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRDDEC) the current destination address (CH[x].DAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued.' + bit_offset: 16 + bit_size: 16 fieldset/CH_CR: description: GPDMA channel 11 control register fields: - - name: EN - description: "enable. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored." - bit_offset: 0 - bit_size: 1 - - name: RESET - description: "reset. This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (CH[x].SR.SUSPF = 1 and CH[x].SR.IDLEF = CH[x].CR.EN = 1). - channel in disabled state (CH[x].SR.IDLEF = 1 and CH[x].CR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (CH[x].BR1, CH[x].SAR and CH[x].DAR) before enabling again the channel (see the programming sequence in )." - bit_offset: 1 - bit_size: 1 - - name: SUSP - description: "suspend. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going GPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in ." - bit_offset: 2 - bit_size: 1 - - name: TCIE - description: transfer complete interrupt enable - bit_offset: 8 - bit_size: 1 - - name: HTIE - description: half transfer complete interrupt enable - bit_offset: 9 - bit_size: 1 - - name: DTEIE - description: data transfer error interrupt enable - bit_offset: 10 - bit_size: 1 - - name: ULEIE - description: update link transfer error interrupt enable - bit_offset: 11 - bit_size: 1 - - name: USEIE - description: user setting error interrupt enable - bit_offset: 12 - bit_size: 1 - - name: SUSPIE - description: completed suspension interrupt enable - bit_offset: 13 - bit_size: 1 - - name: TOIE - description: trigger overrun interrupt enable - bit_offset: 14 - bit_size: 1 - - name: LSM - description: "Link step mode. First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by CH[x].LLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1." - bit_offset: 16 - bit_size: 1 - enum: CH_CR_LSM - - name: LAP - description: "linked-list allocated port. This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1." - bit_offset: 17 - bit_size: 1 - enum: CH_CR_LAP - - name: PRIO - description: "priority level of the channel x GPDMA transfer versus others. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1." - bit_offset: 22 - bit_size: 2 - enum: CH_CR_PRIO + - name: EN + description: 'enable. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored.' + bit_offset: 0 + bit_size: 1 + - name: RESET + description: 'reset. This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (CH[x].SR.SUSPF = 1 and CH[x].SR.IDLEF = CH[x].CR.EN = 1). - channel in disabled state (CH[x].SR.IDLEF = 1 and CH[x].CR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (CH[x].BR1, CH[x].SAR and CH[x].DAR) before enabling again the channel (see the programming sequence in ).' + bit_offset: 1 + bit_size: 1 + - name: SUSP + description: 'suspend. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going GPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in .' + bit_offset: 2 + bit_size: 1 + - name: TCIE + description: transfer complete interrupt enable + bit_offset: 8 + bit_size: 1 + - name: HTIE + description: half transfer complete interrupt enable + bit_offset: 9 + bit_size: 1 + - name: DTEIE + description: data transfer error interrupt enable + bit_offset: 10 + bit_size: 1 + - name: ULEIE + description: update link transfer error interrupt enable + bit_offset: 11 + bit_size: 1 + - name: USEIE + description: user setting error interrupt enable + bit_offset: 12 + bit_size: 1 + - name: SUSPIE + description: completed suspension interrupt enable + bit_offset: 13 + bit_size: 1 + - name: TOIE + description: trigger overrun interrupt enable + bit_offset: 14 + bit_size: 1 + - name: LSM + description: 'Link step mode. First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by CH[x].LLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1.' + bit_offset: 16 + bit_size: 1 + enum: CH_CR_LSM + - name: LAP + description: 'linked-list allocated port. This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1.' + bit_offset: 17 + bit_size: 1 + enum: CH_CR_LAP + - name: PRIO + description: 'priority level of the channel x GPDMA transfer versus others. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.' + bit_offset: 22 + bit_size: 2 + enum: CH_CR_PRIO fieldset/CH_FCR: description: GPDMA channel 7 flag clear register fields: - - name: TCF - description: transfer complete flag clear - bit_offset: 8 - bit_size: 1 - - name: HTF - description: half transfer flag clear - bit_offset: 9 - bit_size: 1 - - name: DTEF - description: data transfer error flag clear - bit_offset: 10 - bit_size: 1 - - name: ULEF - description: update link transfer error flag clear - bit_offset: 11 - bit_size: 1 - - name: USEF - description: user setting error flag clear - bit_offset: 12 - bit_size: 1 - - name: SUSPF - description: completed suspension flag clear - bit_offset: 13 - bit_size: 1 - - name: TOF - description: trigger overrun flag clear - bit_offset: 14 - bit_size: 1 + - name: TCF + description: transfer complete flag clear + bit_offset: 8 + bit_size: 1 + - name: HTF + description: half transfer flag clear + bit_offset: 9 + bit_size: 1 + - name: DTEF + description: data transfer error flag clear + bit_offset: 10 + bit_size: 1 + - name: ULEF + description: update link transfer error flag clear + bit_offset: 11 + bit_size: 1 + - name: USEF + description: user setting error flag clear + bit_offset: 12 + bit_size: 1 + - name: SUSPF + description: completed suspension flag clear + bit_offset: 13 + bit_size: 1 + - name: TOF + description: trigger overrun flag clear + bit_offset: 14 + bit_size: 1 fieldset/CH_LBAR: description: GPDMA channel 14 linked-list base address register fields: - - name: LBA - description: linked-list base address of GPDMA channel x - bit_offset: 16 - bit_size: 16 + - name: LBA + description: linked-list base address of GPDMA channel x + bit_offset: 16 + bit_size: 16 fieldset/CH_LLR: description: GPDMA channel 15 alternate linked-list address register fields: - - name: LA - description: "pointer (16-bit low-significant address) to the next linked-list data structure. If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (CH[x].CTR1, CH[x].TR2, CH[x].BR1, CH[x].SAR, CH[x].DAR and CH[x].LLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored." - bit_offset: 2 - bit_size: 14 - - name: ULL - description: "Update CH[x].LLR register from memory. This bit is used to control the update of CH[x].LLR from the memory during the link transfer." - bit_offset: 16 - bit_size: 1 - - name: UB2 - description: "Update CH[x].BR2 from memory. This bit controls the update of CH[x].BR2 from the memory during the link transfer." - bit_offset: 25 - bit_size: 1 - - name: UT3 - description: "Update CH[x].TR3 from memory. This bit controls the update of CH[x].TR3 from the memory during the link transfer." - bit_offset: 26 - bit_size: 1 - - name: UDA - description: "Update CH[x].DAR register from memory. This bit is used to control the update of CH[x].DAR from the memory during the link transfer." - bit_offset: 27 - bit_size: 1 - - name: USA - description: "update CH[x].SAR from memory. This bit controls the update of CH[x].SAR from the memory during the link transfer." - bit_offset: 28 - bit_size: 1 - - name: UB1 - description: "Update CH[x].BR1 from memory. This bit controls the update of CH[x].BR1 from the memory during the link transfer. If UB1 = 0 and if CH[x].LLR ≠ 0, the linked-list is not completed. CH[x].BR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer." - bit_offset: 29 - bit_size: 1 - - name: UT2 - description: "Update CH[x].TR2 from memory. This bit controls the update of CH[x].TR2 from the memory during the link transfer." - bit_offset: 30 - bit_size: 1 - - name: UT1 - description: "Update CH[x].TR1 from memory. This bit controls the update of CH[x].TR1 from the memory during the link transfer." - bit_offset: 31 - bit_size: 1 + - name: LA + description: 'pointer (16-bit low-significant address) to the next linked-list data structure. If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (CH[x].CTR1, CH[x].TR2, CH[x].BR1, CH[x].SAR, CH[x].DAR and CH[x].LLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.' + bit_offset: 2 + bit_size: 14 + - name: ULL + description: Update CH[x].LLR register from memory. This bit is used to control the update of CH[x].LLR from the memory during the link transfer. + bit_offset: 16 + bit_size: 1 + - name: UB2 + description: Update CH[x].BR2 from memory. This bit controls the update of CH[x].BR2 from the memory during the link transfer. + bit_offset: 25 + bit_size: 1 + - name: UT3 + description: Update CH[x].TR3 from memory. This bit controls the update of CH[x].TR3 from the memory during the link transfer. + bit_offset: 26 + bit_size: 1 + - name: UDA + description: Update CH[x].DAR register from memory. This bit is used to control the update of CH[x].DAR from the memory during the link transfer. + bit_offset: 27 + bit_size: 1 + - name: USA + description: update CH[x].SAR from memory. This bit controls the update of CH[x].SAR from the memory during the link transfer. + bit_offset: 28 + bit_size: 1 + - name: UB1 + description: Update CH[x].BR1 from memory. This bit controls the update of CH[x].BR1 from the memory during the link transfer. If UB1 = 0 and if CH[x].LLR ≠ 0, the linked-list is not completed. CH[x].BR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer. + bit_offset: 29 + bit_size: 1 + - name: UT2 + description: Update CH[x].TR2 from memory. This bit controls the update of CH[x].TR2 from the memory during the link transfer. + bit_offset: 30 + bit_size: 1 + - name: UT1 + description: Update CH[x].TR1 from memory. This bit controls the update of CH[x].TR1 from the memory during the link transfer. + bit_offset: 31 + bit_size: 1 fieldset/CH_SR: description: GPDMA channel 15 status register fields: - - name: IDLEF - description: "idle flag. This idle flag is de-asserted by hardware when the channel is enabled (CH[x].CR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state)." - bit_offset: 0 - bit_size: 1 - - name: TCF - description: "transfer complete flag. A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0])." - bit_offset: 8 - bit_size: 1 - - name: HTF - description: "half transfer flag. An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of CH[x].BR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (CH[x].BR1.BRC[10:0]+1)/2)) has been transferred to the destination." - bit_offset: 9 - bit_size: 1 - - name: DTEF - description: data transfer error flag - bit_offset: 10 - bit_size: 1 - - name: ULEF - description: update link transfer error flag - bit_offset: 11 - bit_size: 1 - - name: USEF - description: user setting error flag - bit_offset: 12 - bit_size: 1 - - name: SUSPF - description: completed suspension flag - bit_offset: 13 - bit_size: 1 - - name: TOF - description: trigger overrun flag - bit_offset: 14 - bit_size: 1 - - name: FIFOL - description: "monitored FIFO level. Number of available write beats in the FIFO, in units of the programmed destination data width (see CH[x].TR1.DDW[1:0], in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to CH[x].BR1.BDNT[15:0] and CH[x].BR1.BRC[10:0], to know how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be suspended (CH[x].SR.SUSPF = 1)." - bit_offset: 16 - bit_size: 8 + - name: IDLEF + description: idle flag. This idle flag is de-asserted by hardware when the channel is enabled (CH[x].CR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state). + bit_offset: 0 + bit_size: 1 + - name: TCF + description: transfer complete flag. A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). + bit_offset: 8 + bit_size: 1 + - name: HTF + description: half transfer flag. An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of CH[x].BR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (CH[x].BR1.BRC[10:0]+1)/2)) has been transferred to the destination. + bit_offset: 9 + bit_size: 1 + - name: DTEF + description: data transfer error flag + bit_offset: 10 + bit_size: 1 + - name: ULEF + description: update link transfer error flag + bit_offset: 11 + bit_size: 1 + - name: USEF + description: user setting error flag + bit_offset: 12 + bit_size: 1 + - name: SUSPF + description: completed suspension flag + bit_offset: 13 + bit_size: 1 + - name: TOF + description: trigger overrun flag + bit_offset: 14 + bit_size: 1 + - name: FIFOL + description: 'monitored FIFO level. Number of available write beats in the FIFO, in units of the programmed destination data width (see CH[x].TR1.DDW[1:0], in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to CH[x].BR1.BDNT[15:0] and CH[x].BR1.BRC[10:0], to know how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be suspended (CH[x].SR.SUSPF = 1).' + bit_offset: 16 + bit_size: 8 fieldset/CH_TR1: description: GPDMA channel 8 transfer register 1 fields: - - name: SDW - description: "binary logarithm of the source data width of a burst in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (CH[x].BR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address CH[x].SAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued." - bit_offset: 0 - bit_size: 2 - enum: CH_TR1_DW - - name: SINC - description: "source incrementing burst. The source address, pointed by CH[x].SAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer." - bit_offset: 3 - bit_size: 1 - - name: SBL_1 - description: "source burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If SBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed." - bit_offset: 4 - bit_size: 6 - - name: PAM - description: "padding/alignment mode. If DDW[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer. - Case 2: If destination data width < source data width. 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination. Note:" - bit_offset: 11 - bit_size: 2 - enum: CH_TR1_PAM - - name: SBX - description: "source byte exchange within the unaligned half-word of each source word. If set, the two consecutive bytes within the unaligned half-word of each source word are exchanged. If the source data width is shorter than a word, this bit is ignored." - bit_offset: 13 - bit_size: 1 - - name: SAP - description: "source allocated port. This bit is used to allocate the master port for the source transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1." - bit_offset: 14 - bit_size: 1 - enum: CH_TR1_AP - - name: SSEC - description: "security attribute of the GPDMA transfer from the source. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx =1 . A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer from the source is non-secure." - bit_offset: 15 - bit_size: 1 - - name: DDW - description: "binary logarithm of the destination data width of a burst, in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address CH[x].DAR[2:0] and address offset CH[x].TR3.DAO[2:0], versus DDW[1:0]). Otherwise a user setting error is reported and no transfer is issued." - bit_offset: 16 - bit_size: 2 - enum: CH_TR1_DW - - name: DINC - description: "destination incrementing burst. The destination address, pointed by CH[x].DAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer." - bit_offset: 19 - bit_size: 1 - - name: DBL_1 - description: "destination burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If DBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed." - bit_offset: 20 - bit_size: 6 - - name: DBX - description: "destination byte exchange. IF set, the two consecutive (post PAM) bytes are exchanged in each destination half-word. If the destination data size is a byte, this bit is ignored." - bit_offset: 26 - bit_size: 1 - - name: DHX - description: "destination half-word exchange. If set, e two consecutive (post PAM) half-words are exchanged in each destination word. If the destination data size is shorter than a word, this bit is ignored." - bit_offset: 27 - bit_size: 1 - - name: DAP - description: "destination allocated port. This bit is used to allocate the master port for the destination transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1." - bit_offset: 30 - bit_size: 1 - enum: CH_TR1_AP - - name: DSEC - description: "security attribute of the GPDMA transfer to the destination. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx = 1. A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer to the destination is non-secure." - bit_offset: 31 - bit_size: 1 + - name: SDW + description: 'binary logarithm of the source data width of a burst in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (CH[x].BR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address CH[x].SAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued.' + bit_offset: 0 + bit_size: 2 + enum: CH_TR1_DW + - name: SINC + description: source incrementing burst. The source address, pointed by CH[x].SAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + bit_offset: 3 + bit_size: 1 + - name: SBL_1 + description: 'source burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If SBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed.' + bit_offset: 4 + bit_size: 6 + - name: PAM + description: 'padding/alignment mode. If DDW[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer. - Case 2: If destination data width < source data width. 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination. Note:' + bit_offset: 11 + bit_size: 2 + enum: CH_TR1_PAM + - name: SBX + description: source byte exchange within the unaligned half-word of each source word. If set, the two consecutive bytes within the unaligned half-word of each source word are exchanged. If the source data width is shorter than a word, this bit is ignored. + bit_offset: 13 + bit_size: 1 + - name: SAP + description: 'source allocated port. This bit is used to allocate the master port for the source transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.' + bit_offset: 14 + bit_size: 1 + enum: CH_TR1_AP + - name: SSEC + description: 'security attribute of the GPDMA transfer from the source. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx =1 . A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer from the source is non-secure.' + bit_offset: 15 + bit_size: 1 + - name: DDW + description: 'binary logarithm of the destination data width of a burst, in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address CH[x].DAR[2:0] and address offset CH[x].TR3.DAO[2:0], versus DDW[1:0]). Otherwise a user setting error is reported and no transfer is issued.' + bit_offset: 16 + bit_size: 2 + enum: CH_TR1_DW + - name: DINC + description: destination incrementing burst. The destination address, pointed by CH[x].DAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + bit_offset: 19 + bit_size: 1 + - name: DBL_1 + description: 'destination burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If DBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed.' + bit_offset: 20 + bit_size: 6 + - name: DBX + description: destination byte exchange. IF set, the two consecutive (post PAM) bytes are exchanged in each destination half-word. If the destination data size is a byte, this bit is ignored. + bit_offset: 26 + bit_size: 1 + - name: DHX + description: destination half-word exchange. If set, e two consecutive (post PAM) half-words are exchanged in each destination word. If the destination data size is shorter than a word, this bit is ignored. + bit_offset: 27 + bit_size: 1 + - name: DAP + description: 'destination allocated port. This bit is used to allocate the master port for the destination transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.' + bit_offset: 30 + bit_size: 1 + enum: CH_TR1_AP + - name: DSEC + description: 'security attribute of the GPDMA transfer to the destination. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx = 1. A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer to the destination is non-secure.' + bit_offset: 31 + bit_size: 1 fieldset/CH_TR2: description: GPDMA channel 10 transfer register 2 fields: - - name: REQSEL - description: "GPDMA hardware request selection. These bits are ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per . The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active GPDMA channels (CH[x].CR.EN = 1 and CH[x].TR2.SWREQ = 0 for these channels). GPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting." - bit_offset: 0 - bit_size: 7 - - name: SWREQ - description: "software request. This bit is internally taken into account when CH[x].CR.EN is asserted." - bit_offset: 9 - bit_size: 1 - enum: CH_TR2_SWREQ - - name: DREQ - description: "destination hardware request. This bit is ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note:" - bit_offset: 10 - bit_size: 1 - enum: CH_TR2_DREQ - - name: BREQ - description: "Block hardware request. If the channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:" - bit_offset: 11 - bit_size: 1 - enum: CH_TR2_BREQ - - name: TRIGM - description: "trigger mode. These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (CH[x].CR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a GPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. – If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. – If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The GPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the CH[x].TR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (CH[x].SR.TOF =1 ), and an interrupt is generated if enabled (CH[x].CR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger." - bit_offset: 14 - bit_size: 2 - enum: CH_TR2_TRIGM - - name: TRIGSEL - description: "trigger event input selection. These bits select the trigger event input of the GPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0] ≠ 00." - bit_offset: 16 - bit_size: 6 - - name: TRIGPOL - description: "trigger event polarity. These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0]." - bit_offset: 24 - bit_size: 2 - enum: CH_TR2_TRIGPOL - - name: TCEM - description: "transfer complete event mode. These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1." - bit_offset: 30 - bit_size: 2 - enum: CH_TR2_TCEM + - name: REQSEL + description: GPDMA hardware request selection. These bits are ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per . The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active GPDMA channels (CH[x].CR.EN = 1 and CH[x].TR2.SWREQ = 0 for these channels). GPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting. + bit_offset: 0 + bit_size: 7 + - name: SWREQ + description: software request. This bit is internally taken into account when CH[x].CR.EN is asserted. + bit_offset: 9 + bit_size: 1 + enum: CH_TR2_SWREQ + - name: DREQ + description: 'destination hardware request. This bit is ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note:' + bit_offset: 10 + bit_size: 1 + enum: CH_TR2_DREQ + - name: BREQ + description: 'Block hardware request. If the channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:' + bit_offset: 11 + bit_size: 1 + enum: CH_TR2_BREQ + - name: TRIGM + description: 'trigger mode. These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (CH[x].CR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a GPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. – If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. – If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The GPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the CH[x].TR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (CH[x].SR.TOF =1 ), and an interrupt is generated if enabled (CH[x].CR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger.' + bit_offset: 14 + bit_size: 2 + enum: CH_TR2_TRIGM + - name: TRIGSEL + description: trigger event input selection. These bits select the trigger event input of the GPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0] ≠ 00. + bit_offset: 16 + bit_size: 6 + - name: TRIGPOL + description: trigger event polarity. These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0]. + bit_offset: 24 + bit_size: 2 + enum: CH_TR2_TRIGPOL + - name: TCEM + description: 'transfer complete event mode. These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1.' + bit_offset: 30 + bit_size: 2 + enum: CH_TR2_TCEM fieldset/CH_TR3: description: GPDMA channel 14 transfer register 3 fields: - - name: SAO - description: "source address offset increment. The source address, pointed by CH[x].SAR, is incremented or decremented (depending on CH[x].BR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional CH[x].TR3.SAO[12:0] is not applied." - bit_offset: 0 - bit_size: 13 - - name: DAO - description: "destination address offset increment. The destination address, pointed by CH[x].DAR, is incremented or decremented (depending on CH[x].BR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus CH[x].TR1.DDW[1:0]). Else, a user setting error is reported and no transfer is issued." - bit_offset: 16 - bit_size: 13 + - name: SAO + description: 'source address offset increment. The source address, pointed by CH[x].SAR, is incremented or decremented (depending on CH[x].BR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional CH[x].TR3.SAO[12:0] is not applied.' + bit_offset: 0 + bit_size: 13 + - name: DAO + description: 'destination address offset increment. The destination address, pointed by CH[x].DAR, is incremented or decremented (depending on CH[x].BR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus CH[x].TR1.DDW[1:0]). Else, a user setting error is reported and no transfer is issued.' + bit_offset: 16 + bit_size: 13 fieldset/MISR: description: GPDMA secure masked interrupt status register fields: - - name: MIS - description: MIS0 - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 + - name: MIS + description: MIS0 + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 fieldset/PRIVCFGR: description: GPDMA privileged configuration register fields: - - name: PRIV - description: PRIV0 - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 + - name: PRIV + description: PRIV0 + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 fieldset/RCFGLOCKR: description: GPDMA configuration lock register fields: - - name: LOCK - description: LOCK0 - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 + - name: LOCK + description: LOCK0 + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 fieldset/SECCFGR: description: GPDMA secure configuration register fields: - - name: SEC - description: SEC0 - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 + - name: SEC + description: SEC0 + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 enum/CH_BR1_DEC: bit_size: 1 variants: - - name: Add - description: The address is incremented by the programmed offset. - value: 0 - - name: Subtract - description: The address is decremented by the programmed offset. - value: 1 + - name: Add + description: The address is incremented by the programmed offset. + value: 0 + - name: Subtract + description: The address is decremented by the programmed offset. + value: 1 enum/CH_CR_LAP: bit_size: 1 variants: - - name: Port0 - description: port 0 (AHB) allocated - value: 0 - - name: Port1 - description: port 1 (AHB) allocated - value: 1 + - name: Port0 + description: port 0 (AHB) allocated + value: 0 + - name: Port1 + description: port 1 (AHB) allocated + value: 1 enum/CH_CR_LSM: bit_size: 1 variants: - - name: RunToCompletion - description: "channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present." - value: 0 - - name: LinkStep - description: channel executed once for the current LLI - value: 1 + - name: RunToCompletion + description: channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. + value: 0 + - name: LinkStep + description: channel executed once for the current LLI + value: 1 enum/CH_CR_PRIO: bit_size: 2 variants: - - name: LowWithLowhWeight - description: "low priority, low weight" - value: 0 - - name: LowWithMidWeight - description: "low priority, mid weight" - value: 1 - - name: LowWithHighWeight - description: "low priority, high weight" - value: 2 - - name: High - description: high priority - value: 3 + - name: LowWithLowhWeight + description: low priority, low weight + value: 0 + - name: LowWithMidWeight + description: low priority, mid weight + value: 1 + - name: LowWithHighWeight + description: low priority, high weight + value: 2 + - name: High + description: high priority + value: 3 enum/CH_TR1_AP: bit_size: 1 variants: - - name: Port0 - description: port 0 (AHB) allocated - value: 0 - - name: Port1 - description: port 1 (AHB) allocated - value: 1 + - name: Port0 + description: port 0 (AHB) allocated + value: 0 + - name: Port1 + description: port 1 (AHB) allocated + value: 1 enum/CH_TR1_DW: bit_size: 2 variants: - - name: Byte - description: byte - value: 0 - - name: HalfWord - description: half-word (2 bytes) - value: 1 - - name: Word - description: word (4 bytes) - value: 2 + - name: Byte + description: byte + value: 0 + - name: HalfWord + description: half-word (2 bytes) + value: 1 + - name: Word + description: word (4 bytes) + value: 2 enum/CH_TR1_PAM: bit_size: 2 variants: - - name: ZeroExtendOrLeftTruncate - description: "If destination is wider: source data is transferred as right aligned, padded with 0s up to the destination data width\nIf source is wider: source data is transferred as right aligned, left-truncated down to the destination data width" - value: 0 - - name: SignExtendOrRightTruncate - description: "If destination is wider: source data is transferred as right aligned, sign extended up to the destination data width\nIf source is wider: source data is transferred as left-aligned, right-truncated down to the destination data width" - value: 1 - - name: Pack - description: "source data is FIFO queued and packed/unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination" - value: 2 + - name: ZeroExtendOrLeftTruncate + description: |- + If destination is wider: source data is transferred as right aligned, padded with 0s up to the destination data width + If source is wider: source data is transferred as right aligned, left-truncated down to the destination data width + value: 0 + - name: SignExtendOrRightTruncate + description: |- + If destination is wider: source data is transferred as right aligned, sign extended up to the destination data width + If source is wider: source data is transferred as left-aligned, right-truncated down to the destination data width + value: 1 + - name: Pack + description: source data is FIFO queued and packed/unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination + value: 2 enum/CH_TR2_BREQ: bit_size: 1 variants: - - name: Burst - description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. - value: 0 - - name: Block - description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ). - value: 1 + - name: Burst + description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + value: 0 + - name: Block + description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ). + value: 1 enum/CH_TR2_DREQ: bit_size: 1 variants: - - name: SourcePeripheral - description: selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) - value: 0 - - name: DestinationPeripheral - description: selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) - value: 1 + - name: SourcePeripheral + description: selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + value: 0 + - name: DestinationPeripheral + description: selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + value: 1 enum/CH_TR2_SWREQ: bit_size: 1 variants: - - name: Hardware - description: "no software request. The selected hardware request REQSEL[6:0] is taken into account." - value: 0 - - name: Software - description: "software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored." - value: 1 + - name: Hardware + description: no software request. The selected hardware request REQSEL[6:0] is taken into account. + value: 0 + - name: Software + description: software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored. + value: 1 enum/CH_TR2_TCEM: bit_size: 2 variants: - - name: EachBlock - description: "at block level (when CH[x].BR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." - value: 0 - - name: Each2DBlock - description: "channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when CH[x].BR1.BRC[10:0] = 0 and CH[x].BR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." - value: 1 - - name: EachLinkedListItem - description: "at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." - value: 2 - - name: LastLinkedListItem - description: "at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address CH[x].LLR.LA[15:2] to zero and clears all the CH[x].LLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." - value: 3 + - name: EachBlock + description: 'at block level (when CH[x].BR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.' + value: 0 + - name: Each2DBlock + description: channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when CH[x].BR1.BRC[10:0] = 0 and CH[x].BR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block. + value: 1 + - name: EachLinkedListItem + description: 'at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer.' + value: 2 + - name: LastLinkedListItem + description: 'at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address CH[x].LLR.LA[15:2] to zero and clears all the CH[x].LLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated.' + value: 3 enum/CH_TR2_TRIGM: bit_size: 2 variants: - - name: Block - description: "at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with CH[x].BR1.BRC[10:0] ≠ 0)." - value: 0 - - name: 2DBlock - description: "channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" - value: 1 - - name: LinkedListItem - description: "at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." - value: 2 - - name: Burst - description: "at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." - value: 3 + - name: Block + description: 'at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with CH[x].BR1.BRC[10:0] ≠ 0).' + value: 0 + - name: 2DBlock + description: channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the + value: 1 + - name: LinkedListItem + description: 'at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.' + value: 2 + - name: Burst + description: 'at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger.' + value: 3 enum/CH_TR2_TRIGPOL: bit_size: 2 variants: - - name: None - description: no trigger (masked trigger event) - value: 0 - - name: RisingEdge - description: trigger on the rising edge - value: 1 - - name: FallingEdge - description: trigger on the falling edge - value: 2 - - name: NoneAlt - description: same as 00 - value: 3 + - name: None + description: no trigger (masked trigger event) + value: 0 + - name: RisingEdge + description: trigger on the rising edge + value: 1 + - name: FallingEdge + description: trigger on the falling edge + value: 2 + - name: NoneAlt + description: same as 00 + value: 3 diff --git a/data/registers/gpio_v1.yaml b/data/registers/gpio_v1.yaml index 37eabef..d0d2cb7 100644 --- a/data/registers/gpio_v1.yaml +++ b/data/registers/gpio_v1.yaml @@ -1,204 +1,203 @@ ---- block/GPIO: description: General purpose I/O items: - - name: CR - description: Port configuration register low (GPIOn_CRL) - array: - len: 2 - stride: 4 - byte_offset: 0 - fieldset: CR - - name: IDR - description: Port input data register (GPIOn_IDR) - byte_offset: 8 - access: Read - fieldset: IDR - - name: ODR - description: Port output data register (GPIOn_ODR) - byte_offset: 12 - fieldset: ODR - - name: BSRR - description: Port bit set/reset register (GPIOn_BSRR) - byte_offset: 16 - access: Write - fieldset: BSRR - - name: BRR - description: Port bit reset register (GPIOn_BRR) - byte_offset: 20 - access: Write - fieldset: BRR - - name: LCKR - description: Port configuration lock register - byte_offset: 24 - fieldset: LCKR + - name: CR + description: Port configuration register low (GPIOn_CRL) + array: + len: 2 + stride: 4 + byte_offset: 0 + fieldset: CR + - name: IDR + description: Port input data register (GPIOn_IDR) + byte_offset: 8 + access: Read + fieldset: IDR + - name: ODR + description: Port output data register (GPIOn_ODR) + byte_offset: 12 + fieldset: ODR + - name: BSRR + description: Port bit set/reset register (GPIOn_BSRR) + byte_offset: 16 + access: Write + fieldset: BSRR + - name: BRR + description: Port bit reset register (GPIOn_BRR) + byte_offset: 20 + access: Write + fieldset: BRR + - name: LCKR + description: Port configuration lock register + byte_offset: 24 + fieldset: LCKR fieldset/BRR: description: Port bit reset register (GPIOn_BRR) fields: - - name: BR - description: Reset bit - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 + - name: BR + description: Reset bit + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 fieldset/BSRR: description: Port bit set/reset register (GPIOn_BSRR) fields: - - name: BS - description: Set bit - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 - - name: BR - description: Reset bit - bit_offset: 16 - bit_size: 1 - array: - len: 16 - stride: 1 + - name: BS + description: Set bit + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 + - name: BR + description: Reset bit + bit_offset: 16 + bit_size: 1 + array: + len: 16 + stride: 1 fieldset/CR: description: Port configuration register (GPIOn_CRx) fields: - - name: MODE - description: Port n mode bits - bit_offset: 0 - bit_size: 2 - array: - len: 8 - stride: 4 - enum: MODE - - name: CNF_IN - description: "Port n configuration bits, for input mode" - bit_offset: 2 - bit_size: 2 - array: - len: 8 - stride: 4 - enum: CNF_IN - - name: CNF_OUT - description: "Port n configuration bits, for output mode" - bit_offset: 2 - bit_size: 2 - array: - len: 8 - stride: 4 - enum: CNF_OUT + - name: MODE + description: Port n mode bits + bit_offset: 0 + bit_size: 2 + array: + len: 8 + stride: 4 + enum: MODE + - name: CNF_IN + description: Port n configuration bits, for input mode + bit_offset: 2 + bit_size: 2 + array: + len: 8 + stride: 4 + enum: CNF_IN + - name: CNF_OUT + description: Port n configuration bits, for output mode + bit_offset: 2 + bit_size: 2 + array: + len: 8 + stride: 4 + enum: CNF_OUT fieldset/IDR: description: Port input data register (GPIOn_IDR) fields: - - name: IDR - description: Port input data - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 - enum: IDR + - name: IDR + description: Port input data + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 + enum: IDR fieldset/LCKR: description: Port configuration lock register fields: - - name: LCK - description: Port A Lock bit - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 - enum: LCK - - name: LCKK - description: Lock key - bit_offset: 16 - bit_size: 1 - enum: LCKK + - name: LCK + description: Port A Lock bit + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 + enum: LCK + - name: LCKK + description: Lock key + bit_offset: 16 + bit_size: 1 + enum: LCKK fieldset/ODR: description: Port output data register (GPIOn_ODR) fields: - - name: ODR - description: Port output data - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 - enum: ODR + - name: ODR + description: Port output data + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 + enum: ODR enum/CNF_IN: bit_size: 2 variants: - - name: Analog - description: Analog mode - value: 0 - - name: Floating - description: Floating input (reset state) - value: 1 - - name: Pull - description: Input with pull-up/pull-down - value: 2 + - name: Analog + description: Analog mode + value: 0 + - name: Floating + description: Floating input (reset state) + value: 1 + - name: Pull + description: Input with pull-up/pull-down + value: 2 enum/CNF_OUT: bit_size: 2 variants: - - name: PushPull - description: Push-Pull mode - value: 0 - - name: OpenDrain - description: Open Drain-Mode - value: 1 - - name: AltPushPull - description: Alternate Function Push-Pull Mode - value: 2 - - name: AltOpenDrain - description: Alternate Function Open-Drain Mode - value: 3 + - name: PushPull + description: Push-Pull mode + value: 0 + - name: OpenDrain + description: Open Drain-Mode + value: 1 + - name: AltPushPull + description: Alternate Function Push-Pull Mode + value: 2 + - name: AltOpenDrain + description: Alternate Function Open-Drain Mode + value: 3 enum/IDR: bit_size: 1 variants: - - name: Low - description: Input is logic low - value: 0 - - name: High - description: Input is logic high - value: 1 + - name: Low + description: Input is logic low + value: 0 + - name: High + description: Input is logic high + value: 1 enum/LCK: bit_size: 1 variants: - - name: Unlocked - description: Port configuration not locked - value: 0 - - name: Locked - description: Port configuration locked - value: 1 + - name: Unlocked + description: Port configuration not locked + value: 0 + - name: Locked + description: Port configuration locked + value: 1 enum/LCKK: bit_size: 1 variants: - - name: NotActive - description: Port configuration lock key not active - value: 0 - - name: Active - description: Port configuration lock key active - value: 1 + - name: NotActive + description: Port configuration lock key not active + value: 0 + - name: Active + description: Port configuration lock key active + value: 1 enum/MODE: bit_size: 2 variants: - - name: Input - description: Input mode (reset state) - value: 0 - - name: Output10Mhz - description: Output mode 10 MHz - value: 1 - - name: Output2Mhz - description: Output mode 2 MHz - value: 2 - - name: Output50Mhz - description: Output mode 50 MHz - value: 3 + - name: Input + description: Input mode (reset state) + value: 0 + - name: Output10Mhz + description: Output mode 10 MHz + value: 1 + - name: Output2Mhz + description: Output mode 2 MHz + value: 2 + - name: Output50Mhz + description: Output mode 50 MHz + value: 3 enum/ODR: bit_size: 1 variants: - - name: Low - description: Set output to logic low - value: 0 - - name: High - description: Set output to logic high - value: 1 + - name: Low + description: Set output to logic low + value: 0 + - name: High + description: Set output to logic high + value: 1 diff --git a/data/registers/gpio_v2.yaml b/data/registers/gpio_v2.yaml index d8ef09c..fe773ee 100644 --- a/data/registers/gpio_v2.yaml +++ b/data/registers/gpio_v2.yaml @@ -1,241 +1,240 @@ ---- block/GPIO: description: General-purpose I/Os items: - - name: MODER - description: GPIO port mode register - byte_offset: 0 - fieldset: MODER - - name: OTYPER - description: GPIO port output type register - byte_offset: 4 - fieldset: OTYPER - - name: OSPEEDR - description: GPIO port output speed register - byte_offset: 8 - fieldset: OSPEEDR - - name: PUPDR - description: GPIO port pull-up/pull-down register - byte_offset: 12 - fieldset: PUPDR - - name: IDR - description: GPIO port input data register - byte_offset: 16 - access: Read - fieldset: IDR - - name: ODR - description: GPIO port output data register - byte_offset: 20 - fieldset: ODR - - name: BSRR - description: GPIO port bit set/reset register - byte_offset: 24 - access: Write - fieldset: BSRR - - name: LCKR - description: GPIO port configuration lock register - byte_offset: 28 - fieldset: LCKR - - name: AFR - description: "GPIO alternate function registers. The register described in the datasheet as AFRL is index 0 in this array, and AFRH is index 1. Note that when operating on AFRH, you need to subtract 8 from any operations on the field array it contains -- the alternate function for pin 9 is at index 1, for instance." - array: - len: 2 - stride: 4 - byte_offset: 32 - fieldset: AFR + - name: MODER + description: GPIO port mode register + byte_offset: 0 + fieldset: MODER + - name: OTYPER + description: GPIO port output type register + byte_offset: 4 + fieldset: OTYPER + - name: OSPEEDR + description: GPIO port output speed register + byte_offset: 8 + fieldset: OSPEEDR + - name: PUPDR + description: GPIO port pull-up/pull-down register + byte_offset: 12 + fieldset: PUPDR + - name: IDR + description: GPIO port input data register + byte_offset: 16 + access: Read + fieldset: IDR + - name: ODR + description: GPIO port output data register + byte_offset: 20 + fieldset: ODR + - name: BSRR + description: GPIO port bit set/reset register + byte_offset: 24 + access: Write + fieldset: BSRR + - name: LCKR + description: GPIO port configuration lock register + byte_offset: 28 + fieldset: LCKR + - name: AFR + description: GPIO alternate function registers. The register described in the datasheet as AFRL is index 0 in this array, and AFRH is index 1. Note that when operating on AFRH, you need to subtract 8 from any operations on the field array it contains -- the alternate function for pin 9 is at index 1, for instance. + array: + len: 2 + stride: 4 + byte_offset: 32 + fieldset: AFR fieldset/AFR: - description: "GPIO alternate function register. This contains an array of 8 fields, which correspond to pins 0-7 of the port (for AFRL) or pins 8-15 of the port (for AFRH)." + description: GPIO alternate function register. This contains an array of 8 fields, which correspond to pins 0-7 of the port (for AFRL) or pins 8-15 of the port (for AFRH). fields: - - name: AFR - description: Alternate function selection for one of the pins controlled by this register (0-7). - bit_offset: 0 - bit_size: 4 - array: - len: 8 - stride: 4 + - name: AFR + description: Alternate function selection for one of the pins controlled by this register (0-7). + bit_offset: 0 + bit_size: 4 + array: + len: 8 + stride: 4 fieldset/BSRR: description: GPIO port bit set/reset register fields: - - name: BS - description: Port x set bit y (y= 0..15) - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 - - name: BR - description: Port x set bit y (y= 0..15) - bit_offset: 16 - bit_size: 1 - array: - len: 16 - stride: 1 + - name: BS + description: Port x set bit y (y= 0..15) + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 + - name: BR + description: Port x set bit y (y= 0..15) + bit_offset: 16 + bit_size: 1 + array: + len: 16 + stride: 1 fieldset/IDR: description: GPIO port input data register fields: - - name: IDR - description: Port input data (y = 0..15) - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 - enum: IDR + - name: IDR + description: Port input data (y = 0..15) + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 + enum: IDR fieldset/LCKR: description: GPIO port configuration lock register fields: - - name: LCK - description: Port x lock bit y (y= 0..15) - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 - enum: LCK - - name: LCKK - description: Port x lock bit y (y= 0..15) - bit_offset: 16 - bit_size: 1 - enum: LCKK + - name: LCK + description: Port x lock bit y (y= 0..15) + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 + enum: LCK + - name: LCKK + description: Port x lock bit y (y= 0..15) + bit_offset: 16 + bit_size: 1 + enum: LCKK fieldset/MODER: description: GPIO port mode register fields: - - name: MODER - description: Port x configuration bits (y = 0..15) - bit_offset: 0 - bit_size: 2 - array: - len: 16 - stride: 2 - enum: MODER + - name: MODER + description: Port x configuration bits (y = 0..15) + bit_offset: 0 + bit_size: 2 + array: + len: 16 + stride: 2 + enum: MODER fieldset/ODR: description: GPIO port output data register fields: - - name: ODR - description: Port output data (y = 0..15) - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 - enum: ODR + - name: ODR + description: Port output data (y = 0..15) + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 + enum: ODR fieldset/OSPEEDR: description: GPIO port output speed register fields: - - name: OSPEEDR - description: Port x configuration bits (y = 0..15) - bit_offset: 0 - bit_size: 2 - array: - len: 16 - stride: 2 - enum: OSPEEDR + - name: OSPEEDR + description: Port x configuration bits (y = 0..15) + bit_offset: 0 + bit_size: 2 + array: + len: 16 + stride: 2 + enum: OSPEEDR fieldset/OTYPER: description: GPIO port output type register fields: - - name: OT - description: Port x configuration bits (y = 0..15) - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 - enum: OT + - name: OT + description: Port x configuration bits (y = 0..15) + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 + enum: OT fieldset/PUPDR: description: GPIO port pull-up/pull-down register fields: - - name: PUPDR - description: Port x configuration bits (y = 0..15) - bit_offset: 0 - bit_size: 2 - array: - len: 16 - stride: 2 - enum: PUPDR + - name: PUPDR + description: Port x configuration bits (y = 0..15) + bit_offset: 0 + bit_size: 2 + array: + len: 16 + stride: 2 + enum: PUPDR enum/IDR: bit_size: 1 variants: - - name: Low - description: Input is logic low - value: 0 - - name: High - description: Input is logic high - value: 1 + - name: Low + description: Input is logic low + value: 0 + - name: High + description: Input is logic high + value: 1 enum/LCK: bit_size: 1 variants: - - name: Unlocked - description: Port configuration not locked - value: 0 - - name: Locked - description: Port configuration locked - value: 1 + - name: Unlocked + description: Port configuration not locked + value: 0 + - name: Locked + description: Port configuration locked + value: 1 enum/LCKK: bit_size: 1 variants: - - name: NotActive - description: Port configuration lock key not active - value: 0 - - name: Active - description: Port configuration lock key active - value: 1 + - name: NotActive + description: Port configuration lock key not active + value: 0 + - name: Active + description: Port configuration lock key active + value: 1 enum/MODER: bit_size: 2 variants: - - name: Input - description: Input mode (reset state) - value: 0 - - name: Output - description: General purpose output mode - value: 1 - - name: Alternate - description: Alternate function mode - value: 2 - - name: Analog - description: Analog mode - value: 3 + - name: Input + description: Input mode (reset state) + value: 0 + - name: Output + description: General purpose output mode + value: 1 + - name: Alternate + description: Alternate function mode + value: 2 + - name: Analog + description: Analog mode + value: 3 enum/ODR: bit_size: 1 variants: - - name: Low - description: Set output to logic low - value: 0 - - name: High - description: Set output to logic high - value: 1 + - name: Low + description: Set output to logic low + value: 0 + - name: High + description: Set output to logic high + value: 1 enum/OSPEEDR: bit_size: 2 variants: - - name: LowSpeed - description: Low speed - value: 0 - - name: MediumSpeed - description: Medium speed - value: 1 - - name: HighSpeed - description: High speed - value: 2 - - name: VeryHighSpeed - description: Very high speed - value: 3 + - name: LowSpeed + description: Low speed + value: 0 + - name: MediumSpeed + description: Medium speed + value: 1 + - name: HighSpeed + description: High speed + value: 2 + - name: VeryHighSpeed + description: Very high speed + value: 3 enum/OT: bit_size: 1 variants: - - name: PushPull - description: Output push-pull (reset state) - value: 0 - - name: OpenDrain - description: Output open-drain - value: 1 + - name: PushPull + description: Output push-pull (reset state) + value: 0 + - name: OpenDrain + description: Output open-drain + value: 1 enum/PUPDR: bit_size: 2 variants: - - name: Floating - description: "No pull-up, pull-down" - value: 0 - - name: PullUp - description: Pull-up - value: 1 - - name: PullDown - description: Pull-down - value: 2 + - name: Floating + description: No pull-up, pull-down + value: 0 + - name: PullUp + description: Pull-up + value: 1 + - name: PullDown + description: Pull-down + value: 2 diff --git a/data/registers/hrtim_v1.yaml b/data/registers/hrtim_v1.yaml index 0bc8270..e521c50 100644 --- a/data/registers/hrtim_v1.yaml +++ b/data/registers/hrtim_v1.yaml @@ -1,2345 +1,2343 @@ ---- block/HRTIM: - description: "High Resolution Timer" + description: High Resolution Timer items: - - name: MCR - description: Master Timer Control Register - byte_offset: 0 - fieldset: MCR - - name: MISR - description: Master Timer Interrupt Status Register - byte_offset: 4 - access: Read - fieldset: MISR - - name: MICR - description: Master Timer Interrupt Clear Register - byte_offset: 8 - access: Write - fieldset: MICR - - name: MDIER - description: Master Timer DMA / Interrupt Enable Register - byte_offset: 12 - fieldset: MDIER - - name: MCNTR - description: Master Timer Counter Register - byte_offset: 16 - fieldset: MCNTR - - name: MPER - description: Master Timer Period Register - byte_offset: 20 - fieldset: MPER - - name: MREP - description: Master Timer Repetition Register - byte_offset: 24 - fieldset: MREP - - name: MCMP - description: Master Timer Compare X Register - array: - offsets: - - 0 - - 8 - - 12 - - 16 - byte_offset: 28 - fieldset: MCMPX - - name: TIM - description: "High Resolution Timer: Timing Unit" - array: - len: 5 - stride: 128 - byte_offset: 128 - block: HRTIM_TIMX - - name: CR1 - description: "High Resolution Timer: Control Register 1" - byte_offset: 0x380 - fieldset: HRTIM_CR1 - - name: CR2 - description: "High Resolution Timer: Control Register 2" - byte_offset: 0x384 - fieldset: HRTIM_CR2 - - name: ISR - description: "High Resolution Timer: Interrupt Status Register" - byte_offset: 0x388 - access: Read - fieldset: HRTIM_ISR - - name: ICR - description: "High Resolution Timer: Interrupt Clear Register" - byte_offset: 0x38c - access: Write - fieldset: HRTIM_ICR - - name: IER - description: "High Resolution Timer: Interrupt Enable Register" - byte_offset: 0x390 - fieldset: HRTIM_IER - - name: OENR - description: "High Resolution Timer: Output Enable Register" - byte_offset: 0x394 - fieldset: HRTIM_OENR - - name: ODISR - description: "High Resolution Timer: Output Disable Register" - byte_offset: 0x398 - fieldset: HRTIM_ODISR - - name: ODSR - description: "High Resolution Timer: Output Disable Status Register" - byte_offset: 0x39c - fieldset: HRTIM_ODSR - - name: BMCR - description: "High Resolution Timer: Burst Mode Control Register" - byte_offset: 0x3a0 - fieldset: HRTIM_BMCR - - name: BMTRGR - description: "High Resolution Timer: Burst Mode Trigger Register" - byte_offset: 0x3a4 - fieldset: HRTIM_BMTRGR - - name: BMCMPR - description: "High Resolution Timer: Burst Mode Compare Register" - byte_offset: 0x3a8 - fieldset: HRTIM_BMCMPR - - name: BMPER - description: "High Resolution Timer: Burst Mode Period Register" - byte_offset: 0x3ac - fieldset: HRTIM_BMPER - - name: EECR1 - description: "High Resolution Timer: External Event Control Register 1" - byte_offset: 0x3b0 - fieldset: HRTIM_EECR1 - - name: EECR2 - description: "High Resolution Timer: External Event Control Register 2" - byte_offset: 0x3b4 - fieldset: HRTIM_EECR2 - - name: EECR3 - description: "High Resolution Timer: External Event Control Register 3" - byte_offset: 0x3b8 - fieldset: HRTIM_EECR3 - - name: ADC1R - description: "High Resolution Timer: ADC Trigger [1, 3] Register" - byte_offset: 0x3bc - fieldset: HRTIM_ADC1R - array: - offsets: - - 0 - - 8 - - name: ADC2R - description: "High Resolution Timer: ADC Trigger [2, 4] Register" - byte_offset: 0x3c0 - fieldset: HRTIM_ADC2R - array: - offsets: - - 0 - - 8 - - name: DLLCR - description: "High Resolution Timer: DLL Control Register" - byte_offset: 0x3cc - fieldset: HRTIM_DLLCR - - name: FLTINR1 - description: "High Resolution Timer: Fault Input Register 1" - byte_offset: 0x3d0 - fieldset: HRTIM_FLTINR1 - - name: FLTINR2 - description: "High Resolution Timer: Fault Input Register 2" - byte_offset: 0x3d0 - fieldset: HRTIM_FLTINR2 - - name: BDMUPR - description: "High Resolution Timer: Burst DMA Master timer update Register" - byte_offset: 0x3d8 - fieldset: HRTIM_BDMUPR - - name: BDTUPR - description: "High Resolution Timer: Burst DMA Timer X update Register" - byte_offset: 0x3dc - fieldset: HRTIM_BDTUPR - array: - len: 5 - stride: 4 - - name: BDMADR - description: "High Resolution Timer: Burst DMA Data Register" - byte_offset: 0x3f0 - access: Write - fieldset: HRTIM_BDMADR + - name: MCR + description: Master Timer Control Register + byte_offset: 0 + fieldset: MCR + - name: MISR + description: Master Timer Interrupt Status Register + byte_offset: 4 + access: Read + fieldset: MISR + - name: MICR + description: Master Timer Interrupt Clear Register + byte_offset: 8 + access: Write + fieldset: MICR + - name: MDIER + description: Master Timer DMA / Interrupt Enable Register + byte_offset: 12 + fieldset: MDIER + - name: MCNTR + description: Master Timer Counter Register + byte_offset: 16 + fieldset: MCNTR + - name: MPER + description: Master Timer Period Register + byte_offset: 20 + fieldset: MPER + - name: MREP + description: Master Timer Repetition Register + byte_offset: 24 + fieldset: MREP + - name: MCMP + description: Master Timer Compare X Register + array: + offsets: + - 0 + - 8 + - 12 + - 16 + byte_offset: 28 + fieldset: MCMPX + - name: TIM + description: 'High Resolution Timer: Timing Unit' + array: + len: 5 + stride: 128 + byte_offset: 128 + block: HRTIM_TIMX + - name: CR1 + description: 'High Resolution Timer: Control Register 1' + byte_offset: 896 + fieldset: HRTIM_CR1 + - name: CR2 + description: 'High Resolution Timer: Control Register 2' + byte_offset: 900 + fieldset: HRTIM_CR2 + - name: ISR + description: 'High Resolution Timer: Interrupt Status Register' + byte_offset: 904 + access: Read + fieldset: HRTIM_ISR + - name: ICR + description: 'High Resolution Timer: Interrupt Clear Register' + byte_offset: 908 + access: Write + fieldset: HRTIM_ICR + - name: IER + description: 'High Resolution Timer: Interrupt Enable Register' + byte_offset: 912 + fieldset: HRTIM_IER + - name: OENR + description: 'High Resolution Timer: Output Enable Register' + byte_offset: 916 + fieldset: HRTIM_OENR + - name: ODISR + description: 'High Resolution Timer: Output Disable Register' + byte_offset: 920 + fieldset: HRTIM_ODISR + - name: ODSR + description: 'High Resolution Timer: Output Disable Status Register' + byte_offset: 924 + fieldset: HRTIM_ODSR + - name: BMCR + description: 'High Resolution Timer: Burst Mode Control Register' + byte_offset: 928 + fieldset: HRTIM_BMCR + - name: BMTRGR + description: 'High Resolution Timer: Burst Mode Trigger Register' + byte_offset: 932 + fieldset: HRTIM_BMTRGR + - name: BMCMPR + description: 'High Resolution Timer: Burst Mode Compare Register' + byte_offset: 936 + fieldset: HRTIM_BMCMPR + - name: BMPER + description: 'High Resolution Timer: Burst Mode Period Register' + byte_offset: 940 + fieldset: HRTIM_BMPER + - name: EECR1 + description: 'High Resolution Timer: External Event Control Register 1' + byte_offset: 944 + fieldset: HRTIM_EECR1 + - name: EECR2 + description: 'High Resolution Timer: External Event Control Register 2' + byte_offset: 948 + fieldset: HRTIM_EECR2 + - name: EECR3 + description: 'High Resolution Timer: External Event Control Register 3' + byte_offset: 952 + fieldset: HRTIM_EECR3 + - name: ADC1R + description: 'High Resolution Timer: ADC Trigger [1, 3] Register' + array: + offsets: + - 0 + - 8 + byte_offset: 956 + fieldset: HRTIM_ADC1R + - name: ADC2R + description: 'High Resolution Timer: ADC Trigger [2, 4] Register' + array: + offsets: + - 0 + - 8 + byte_offset: 960 + fieldset: HRTIM_ADC2R + - name: DLLCR + description: 'High Resolution Timer: DLL Control Register' + byte_offset: 972 + fieldset: HRTIM_DLLCR + - name: FLTINR1 + description: 'High Resolution Timer: Fault Input Register 1' + byte_offset: 976 + fieldset: HRTIM_FLTINR1 + - name: FLTINR2 + description: 'High Resolution Timer: Fault Input Register 2' + byte_offset: 976 + fieldset: HRTIM_FLTINR2 + - name: BDMUPR + description: 'High Resolution Timer: Burst DMA Master timer update Register' + byte_offset: 984 + fieldset: HRTIM_BDMUPR + - name: BDTUPR + description: 'High Resolution Timer: Burst DMA Timer X update Register' + array: + len: 5 + stride: 4 + byte_offset: 988 + fieldset: HRTIM_BDTUPR + - name: BDMADR + description: 'High Resolution Timer: Burst DMA Data Register' + byte_offset: 1008 + access: Write + fieldset: HRTIM_BDMADR block/HRTIM_TIMX: - description: "High Resolution Timer: Timing Unit" + description: 'High Resolution Timer: Timing Unit' items: - - name: CR - description: Timer X Control Register - byte_offset: 0 - fieldset: TIMXCR - - name: ISR - description: Timer X Interrupt Status Register - byte_offset: 4 - access: Read - fieldset: TIMXISR - - name: ICR - description: Timer X Interrupt Clear Register - byte_offset: 8 - access: Write - fieldset: TIMXICR - - name: DIER - description: Timer X DMA / Interrupt Enable Register - byte_offset: 12 - fieldset: TIMXDIER - - name: CNT - description: Timer X Counter Register - byte_offset: 16 - fieldset: TIMXCNT - - name: PER - description: Timer X Period Register - byte_offset: 20 - fieldset: TIMXPER - - name: REP - description: Timer X Repetition Register - byte_offset: 24 - fieldset: TIMXREP - - name: CMP - description: Timer X Compare X Register - array: - offsets: - - 0 - - 8 - - 12 - - 16 - byte_offset: 28 - fieldset: TIMXCMP - - name: CMPC - description: Timer X Compare X Compound Register - array: - offsets: - - 0 - byte_offset: 32 - fieldset: TIMXCMPC - - name: CPT - description: Timer X Capture X Register - array: - len: 2 - stride: 4 - byte_offset: 48 - access: Read - fieldset: TIMXCPT - - name: DT - description: Timer X Deadtime Register - byte_offset: 56 - fieldset: TIMXDT - - name: SETR - description: Timer X Output X Set Register - array: - offsets: - - 0 - - 8 - byte_offset: 60 - fieldset: TIMXSETR - - name: RSTR - description: Timer X Output X Reset Register - array: - offsets: - - 0 - - 8 - byte_offset: 64 - fieldset: TIMXRSTR - - name: EEF - description: Timer X External Event Filtering Register 1 - array: - offsets: - - 0 - - 4 - byte_offset: 76 - fieldset: TIMXEEF - - name: RST - description: Timer X Reset Register - byte_offset: 84 - fieldset: TIMXRST - - name: CHP - description: Timer X Chopper Register - byte_offset: 88 - fieldset: TIMXCHP - - name: CCR - description: Timer X Capture X Control Register - array: - offsets: - - 0 - - 4 - byte_offset: 92 - fieldset: TIMXCCR - - name: OUTR - description: Timer X Output Register - byte_offset: 100 - fieldset: TIMXOUTR - - name: FLT - description: Timer X Fault Register - byte_offset: 104 - fieldset: TIMXFLT -fieldset/HRTIM_CR1: - description: "High Resolution Timer: Control Register 1" - fields: - - name: MUDIS - description: Master Update Disable - bit_offset: 0 - bit_size: 1 - - name: TUDIS - description: Timer X Update Disable - bit_offset: 1 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: ADUSRC - description: ADC Trigger X Update Source - bit_offset: 16 - bit_size: 3 - array: - len: 4 - stride: 2 -fieldset/HRTIM_CR2: - description: "High Resolution Timer: Control Register 2" - fields: - - name: MSWU - description: Master Timer Software Update - bit_offset: 0 - bit_size: 1 - - name: TSWU - description: Timer X Software Update - bit_offset: 1 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: MRST - description: Master Counter Software Reset - bit_offset: 8 - bit_size: 1 - - name: TRST - description: Timer X Counter Software Reset - bit_offset: 9 - bit_size: 1 - array: - len: 5 - stride: 1 -fieldset/HRTIM_ISR: - description: "High Resolution Timer: Interrupt Status Register" - fields: - - name: FLT - description: Fault X Interrupt Flag - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: SYSFLT - description: System Fault Interrupt Flag - bit_offset: 5 - bit_size: 1 - - name: DLLRDY - description: DLL Ready Interrupt Flag - bit_offset: 16 - bit_size: 1 - - name: BMPER - description: Burst Mode Period Interrupt Flag - bit_offset: 17 - bit_size: 1 -fieldset/HRTIM_ICR: - description: "High Resolution Timer: Interrupt Clear Register" - fields: - - name: FLT - description: Fault X Interrupt Flag Clear - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: SYSFLT - description: System Fault Interrupt Flag Clear - bit_offset: 5 - bit_size: 1 - - name: DLLRDY - description: DLL Ready Interrupt Flag Clear - bit_offset: 16 - bit_size: 1 - - name: BMPER - description: Burst Mode Period Interrupt Flag Clear - bit_offset: 17 - bit_size: 1 -fieldset/HRTIM_IER: - description: "High Resolution Timer: Interrupt Enable Register" - fields: - - name: FLT - description: Fault X Interrupt Flag Enable - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: SYSFLT - description: System Fault Interrupt Flag Enable - bit_offset: 5 - bit_size: 1 - - name: DLLRDY - description: DLL Ready Interrupt Flag Enable - bit_offset: 16 - bit_size: 1 - - name: BMPER - description: Burst Mode Period Interrupt Flag Enable - bit_offset: 17 - bit_size: 1 -fieldset/HRTIM_OENR: - description: "High Resolution Timer: Output Enable Register" - fields: - - name: T1OEN - description: "Timer X Output Enable" - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - 4 - - 6 - - 8 - - name: T2OEN - description: "Timer X Complementary Output Enable" - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - 4 - - 6 - - 8 -fieldset/HRTIM_ODISR: - description: "High Resolution Timer: Output Disable Register" - fields: - - name: T1ODIS - description: "Timer X Output Disable" - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - 4 - - 6 - - 8 - - name: T2ODIS - description: "Timer X Complementary Output Disable" - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - 4 - - 6 - - 8 -fieldset/HRTIM_ODSR: - description: "High Resolution Timer: Output Disable Status Register" - fields: - - name: T1ODIS - description: "Timer X Output Disable Status" - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - 4 - - 6 - - 8 - - name: T2ODIS - description: "Timer X Complementary Output Disable Status" - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - 4 - - 6 - - 8 -fieldset/HRTIM_BMCR: - description: "High Resolution Timer: Burst Mode Control Register" - fields: - - name: BME - description: Burst Mode Enable - bit_offset: 0 - bit_size: 1 - - name: BMOM - description: Burst Mode Operating Mode - bit_offset: 1 - bit_size: 1 - - name: BMCLK - description: Burst Mode Clock source - bit_offset: 2 - bit_size: 3 - - name: BMPRSC - description: Burst Mode Prescaler - bit_offset: 6 - bit_size: 3 - - name: BMPREN - description: Burst Mode Preload Enable - bit_offset: 10 - bit_size: 1 - - name: MTBM - description: Master Timer Burst Mode - bit_offset: 16 - bit_size: 1 - - name: TBM - description: Timer X Burst Mode - bit_offset: 17 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: BMSTAT - decription: Burst Mode Status - bit_offset: 31 - bit_size: 1 -fieldset/HRTIM_BMTRGR: - description: "High Resolution Timer: Burst Mode Trigger Register" - fields: - - name: SW - description: Software start - bit_offset: 0 - bit_size: 1 - - name: MSTRST - description: Master reset or roll-over - bit_offset: 1 - bit_size: 1 - - name: MSTREP - description: Master repetition - bit_offset: 2 - bit_size: 1 - - name: MSTCMP - description: Master Compare X - bit_offset: 3 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: TRST - description: Timer X reset or roll-over - bit_offset: 7 - bit_size: 1 - array: - offsets: - - 0 - - 4 - - 8 - - 12 - - 16 - - name: TREP - description: Timer X repetition - bit_offset: 8 - bit_size: 1 - array: - offsets: - - 0 - - 4 - - 8 - - 12 - - 16 - - name: TCMP1 - description: Timer X compare 1 event - bit_offset: 9 - bit_size: 1 - array: - offsets: - - 0 - - 4 - - 8 - - 12 - - 16 - - name: TCMP2 - description: Timer X compare 2 event - bit_offset: 10 - bit_size: 1 - array: - offsets: - - 0 - - 4 - - 8 - - 12 - - 16 -fieldset/HRTIM_BMCMPR: - description: "High Resolution Timer: Burst Mode Compare Register" - fields: - - name: BMCMP - description: Burst mode compare value - bit_offset: 0 - bit_size: 16 -fieldset/HRTIM_BMPER: - description: "High Resolution Timer: Burst Mode Period Register" - fields: - - name: BMPER - description: Burst mode period value - bit_offset: 0 - bit_size: 16 -fieldset/HRTIM_EECR1: - description: "High Resolution Timer: External Events Control Register 1" - fields: - - name: EESRC - description: External Event X Source - bit_offset: 0 - bit_size: 2 - array: - offsets: - - 0 - - 6 - - 12 - - 18 - - 24 - - name: EEPOL - description: External Event X Polarity - bit_offset: 2 - bit_size: 1 - array: - offsets: - - 0 - - 6 - - 12 - - 18 - - 24 - - name: EESNS - description: External Event X Sensitivity - bit_offset: 3 - bit_size: 2 - array: - offsets: - - 0 - - 6 - - 12 - - 18 - - 24 - - name: EEFAST - description: External Event X Fast Mode - bit_offset: 5 - bit_size: 2 - array: - offsets: - - 0 - - 6 - - 12 - - 18 - - 24 -fieldset/HRTIM_EECR2: - description: "High Resolution Timer: External Events Control Register 2" - fields: - - name: EESRC - description: External Event X Source - bit_offset: 0 - bit_size: 2 - array: - offsets: - - 0 - - 6 - - 12 - - 18 - - 24 - - name: EEPOL - description: External Event X Polarity - bit_offset: 2 - bit_size: 1 - array: - offsets: - - 0 - - 6 - - 12 - - 18 - - 24 - - name: EESNS - description: External Event X Sensitivity - bit_offset: 3 - bit_size: 2 - array: - offsets: - - 0 - - 6 - - 12 - - 18 - - 24 -fieldset/HRTIM_EECR3: - description: "High Resolution Timer: External Events Control Register 2" - fields: - - name: EEF - description: External Event X filter - bit_offset: 0 - bit_size: 3 - array: - offsets: - - 0 - - 6 - - 12 - - 18 - - 24 - - name: EEVSD - description: External Event Sampling Clock Division - bit_offset: 30 - bit_size: 2 + - name: CR + description: Timer X Control Register + byte_offset: 0 + fieldset: TIMXCR + - name: ISR + description: Timer X Interrupt Status Register + byte_offset: 4 + access: Read + fieldset: TIMXISR + - name: ICR + description: Timer X Interrupt Clear Register + byte_offset: 8 + access: Write + fieldset: TIMXICR + - name: DIER + description: Timer X DMA / Interrupt Enable Register + byte_offset: 12 + fieldset: TIMXDIER + - name: CNT + description: Timer X Counter Register + byte_offset: 16 + fieldset: TIMXCNT + - name: PER + description: Timer X Period Register + byte_offset: 20 + fieldset: TIMXPER + - name: REP + description: Timer X Repetition Register + byte_offset: 24 + fieldset: TIMXREP + - name: CMP + description: Timer X Compare X Register + array: + offsets: + - 0 + - 8 + - 12 + - 16 + byte_offset: 28 + fieldset: TIMXCMP + - name: CMPC + description: Timer X Compare X Compound Register + array: + offsets: + - 0 + byte_offset: 32 + fieldset: TIMXCMPC + - name: CPT + description: Timer X Capture X Register + array: + len: 2 + stride: 4 + byte_offset: 48 + access: Read + fieldset: TIMXCPT + - name: DT + description: Timer X Deadtime Register + byte_offset: 56 + fieldset: TIMXDT + - name: SETR + description: Timer X Output X Set Register + array: + offsets: + - 0 + - 8 + byte_offset: 60 + fieldset: TIMXSETR + - name: RSTR + description: Timer X Output X Reset Register + array: + offsets: + - 0 + - 8 + byte_offset: 64 + fieldset: TIMXRSTR + - name: EEF + description: Timer X External Event Filtering Register 1 + array: + offsets: + - 0 + - 4 + byte_offset: 76 + fieldset: TIMXEEF + - name: RST + description: Timer X Reset Register + byte_offset: 84 + fieldset: TIMXRST + - name: CHP + description: Timer X Chopper Register + byte_offset: 88 + fieldset: TIMXCHP + - name: CCR + description: Timer X Capture X Control Register + array: + offsets: + - 0 + - 4 + byte_offset: 92 + fieldset: TIMXCCR + - name: OUTR + description: Timer X Output Register + byte_offset: 100 + fieldset: TIMXOUTR + - name: FLT + description: Timer X Fault Register + byte_offset: 104 + fieldset: TIMXFLT fieldset/HRTIM_ADC1R: - description: "High Resolution Timer: ADC Trigger 1 Register" + description: 'High Resolution Timer: ADC Trigger 1 Register' fields: - - name: ADCMC - description: ADC trigger X on Master Compare Y - bit_offset: 0 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: ADCMPER - description: ADC trigger X on Master Period - bit_offset: 4 - bit_size: 1 - - name: ADCEEV - description: ADC trigger X on External Event Y - bit_offset: 5 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: ADCTC2 - description: ADC trigger X on Timer Y Compare 2 - bit_offset: 10 - bit_size: 1 - array: - offsets: - - 0 - - 5 - - 10 - - 14 - - 18 - - name: ADCTC3 - description: ADC trigger X on Timer Y Compare 3 - bit_offset: 11 - bit_size: 1 - array: - offsets: - - 0 - - 5 - - 10 - - 14 - - 18 - - name: ADCTC4 - description: ADC trigger X on Timer Y Compare 3 - bit_offset: 12 - bit_size: 1 - array: - offsets: - - 0 - - 5 - - 10 - - 14 - - 18 - - name: ADCTPER - description: ADC trigger X on Timer Y Period - bit_offset: 13 - bit_size: 1 - array: - offsets: - - 0 - - 5 - - 10 - - 14 - - 18 - - name: ADCTRST - description: ADC trigger X on Timer Y Reset - bit_offset: 14 - bit_size: 1 - array: - offsets: - - 0 - - 5 + - name: ADCMC + description: ADC trigger X on Master Compare Y + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: ADCMPER + description: ADC trigger X on Master Period + bit_offset: 4 + bit_size: 1 + - name: ADCEEV + description: ADC trigger X on External Event Y + bit_offset: 5 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: ADCTC2 + description: ADC trigger X on Timer Y Compare 2 + bit_offset: 10 + bit_size: 1 + array: + offsets: + - 0 + - 5 + - 10 + - 14 + - 18 + - name: ADCTC3 + description: ADC trigger X on Timer Y Compare 3 + bit_offset: 11 + bit_size: 1 + array: + offsets: + - 0 + - 5 + - 10 + - 14 + - 18 + - name: ADCTC4 + description: ADC trigger X on Timer Y Compare 3 + bit_offset: 12 + bit_size: 1 + array: + offsets: + - 0 + - 5 + - 10 + - 14 + - 18 + - name: ADCTPER + description: ADC trigger X on Timer Y Period + bit_offset: 13 + bit_size: 1 + array: + offsets: + - 0 + - 5 + - 10 + - 14 + - 18 + - name: ADCTRST + description: ADC trigger X on Timer Y Reset + bit_offset: 14 + bit_size: 1 + array: + offsets: + - 0 + - 5 fieldset/HRTIM_ADC2R: - description: "High Resolution Timer: ADC Trigger 2 Register" + description: 'High Resolution Timer: ADC Trigger 2 Register' fields: - - name: ADCMC - description: ADC trigger X on Master Compare Y - bit_offset: 0 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: ADCMPER - description: ADC trigger X on Master Period - bit_offset: 4 - bit_size: 1 - - name: ADCEEV - description: ADC trigger X on External Event Y - bit_offset: 5 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: ADCTC2 - description: ADC trigger X on Timer Y Compare 2 - bit_offset: 10 - bit_size: 1 - array: - offsets: - - 0 - - 4 - - 8 - - 13 - - 18 - - name: ADCTC3 - description: ADC trigger X on Timer Y Compare 3 - bit_offset: 11 - bit_size: 1 - array: - offsets: - - 0 - - 4 - - 8 - - 13 - - 18 - - name: ADCTC4 - description: ADC trigger X on Timer Y Compare 3 - bit_offset: 12 - bit_size: 1 - array: - offsets: - - 0 - - 4 - - 8 - - 13 - - 18 - - name: ADCTPER - description: ADC trigger X on Timer Y Period - bit_offset: 13 - bit_size: 1 - array: - offsets: - - 0 - - 4 - - 8 - - 13 - - name: ADCTRST - description: ADC trigger X on Timer Y Reset - bit_offset: 22 - bit_size: 1 - array: - offsets: - - 0 - - 5 - - 9 -fieldset/HRTIM_DLLCR: - description: "High Resolution Timer: DLL Control Register" - fields: - - name: CAL - description: DLL Calibration Start - bit_offset: 0 - bit_size: 1 - - name: CALEN - description: DLL Calibration Enable - bit_offset: 1 - bit_size: 1 - - name: CALRTE - description: DLL Calibration Rate - bit_offset: 2 - bit_size: 2 -fieldset/HRTIM_FLTINR1: - description: "High Resolution Timer: Fault Input Register 1" - fields: - - name: FLTE - description: Fault X enable - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - 8 - - 16 - - 24 - - name: FLTP - description: Fault X polarity - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 8 - - 16 - - 24 - - name: FLTSRC - description: Fault X source - bit_offset: 2 - bit_size: 1 - array: - offsets: - - 0 - - 8 - - 16 - - 24 - - name: FLTF - description: Fault X filter - bit_offset: 3 - bit_size: 4 - array: - offsets: - - 0 - - 8 - - 16 - - 24 - - name: FLTLCK - description: Fault X Lock - bit_offset: 7 - bit_size: 1 - array: - offsets: - - 0 - - 8 - - 16 - - 24 -fieldset/HRTIM_FLTINR2: - description: "High Resolution Timer: Fault Input Register 2" - fields: - - name: FLTE - description: Fault X enable - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - name: FLTP - description: Fault X polarity - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - name: FLTSRC - description: Fault X source - bit_offset: 2 - bit_size: 1 - array: - offsets: - - 0 - - name: FLTF - description: Fault X filter - bit_offset: 3 - bit_size: 4 - array: - offsets: - - 0 - - name: FLTLCK - description: Fault X Lock - bit_offset: 7 - bit_size: 1 - array: - offsets: - - 0 - - name: FLTSD - description: Fault Sampling clock division - bit_offset: 24 - bit_size: 2 -fieldset/HRTIM_BDMUPR: - description: "High Resolution Timer: Burst DMA Master timer update Register" - fields: - - name: MCR - description: MCR register update enable - bit_offset: 0 - bit_size: 1 - - name: MICR - description: MICR register update enable - bit_offset: 1 - bit_size: 1 - - name: MDIER - description: MDIER register update enable - bit_offset: 2 - bit_size: 1 - - name: MCNT - description: MCNT register update enable - bit_offset: 3 - bit_size: 1 - - name: MPER - description: MPER register update enable - bit_offset: 4 - bit_size: 1 - - name: MREP - description: MREP register update enable - bit_offset: 5 - bit_size: 1 - - name: MCMP - description: MCMP register X update enable - bit_offset: 6 - bit_size: 1 - array: - len: 4 - stride: 1 -fieldset/HRTIM_BDTUPR: - description: "High Resolution Timer: Burst DMA Master timer update Register" - fields: - - name: CR - description: CR register update enable - bit_offset: 0 - bit_size: 1 - - name: ICR - description: ICR register update enable - bit_offset: 1 - bit_size: 1 - - name: DIER - description: DIER register update enable - bit_offset: 2 - bit_size: 1 - - name: CNT - description: CNT register update enable - bit_offset: 3 - bit_size: 1 - - name: PER - description: PER register update enable - bit_offset: 4 - bit_size: 1 - - name: REP - description: REP register update enable - bit_offset: 5 - bit_size: 1 - - name: CMP - description: CMP register X update enable - bit_offset: 6 - bit_size: 1 - array: - len: 4 - stride: 1 + - name: ADCMC + description: ADC trigger X on Master Compare Y + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: ADCMPER + description: ADC trigger X on Master Period + bit_offset: 4 + bit_size: 1 + - name: ADCEEV + description: ADC trigger X on External Event Y + bit_offset: 5 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: ADCTC2 + description: ADC trigger X on Timer Y Compare 2 + bit_offset: 10 + bit_size: 1 + array: + offsets: + - 0 + - 4 + - 8 + - 13 + - 18 + - name: ADCTC3 + description: ADC trigger X on Timer Y Compare 3 + bit_offset: 11 + bit_size: 1 + array: + offsets: + - 0 + - 4 + - 8 + - 13 + - 18 + - name: ADCTC4 + description: ADC trigger X on Timer Y Compare 3 + bit_offset: 12 + bit_size: 1 + array: + offsets: + - 0 + - 4 + - 8 + - 13 + - 18 + - name: ADCTPER + description: ADC trigger X on Timer Y Period + bit_offset: 13 + bit_size: 1 + array: + offsets: + - 0 + - 4 + - 8 + - 13 + - name: ADCTRST + description: ADC trigger X on Timer Y Reset + bit_offset: 22 + bit_size: 1 + array: + offsets: + - 0 + - 5 + - 9 fieldset/HRTIM_BDMADR: - description: "High Resolution Timer: Burst DMA Data Register" + description: 'High Resolution Timer: Burst DMA Data Register' fields: - - name: BDMADR - description: Burst DMA Data register - bit_offset: 0 - bit_size: 31 + - name: BDMADR + description: Burst DMA Data register + bit_offset: 0 + bit_size: 31 +fieldset/HRTIM_BDMUPR: + description: 'High Resolution Timer: Burst DMA Master timer update Register' + fields: + - name: MCR + description: MCR register update enable + bit_offset: 0 + bit_size: 1 + - name: MICR + description: MICR register update enable + bit_offset: 1 + bit_size: 1 + - name: MDIER + description: MDIER register update enable + bit_offset: 2 + bit_size: 1 + - name: MCNT + description: MCNT register update enable + bit_offset: 3 + bit_size: 1 + - name: MPER + description: MPER register update enable + bit_offset: 4 + bit_size: 1 + - name: MREP + description: MREP register update enable + bit_offset: 5 + bit_size: 1 + - name: MCMP + description: MCMP register X update enable + bit_offset: 6 + bit_size: 1 + array: + len: 4 + stride: 1 +fieldset/HRTIM_BDTUPR: + description: 'High Resolution Timer: Burst DMA Master timer update Register' + fields: + - name: CR + description: CR register update enable + bit_offset: 0 + bit_size: 1 + - name: ICR + description: ICR register update enable + bit_offset: 1 + bit_size: 1 + - name: DIER + description: DIER register update enable + bit_offset: 2 + bit_size: 1 + - name: CNT + description: CNT register update enable + bit_offset: 3 + bit_size: 1 + - name: PER + description: PER register update enable + bit_offset: 4 + bit_size: 1 + - name: REP + description: REP register update enable + bit_offset: 5 + bit_size: 1 + - name: CMP + description: CMP register X update enable + bit_offset: 6 + bit_size: 1 + array: + len: 4 + stride: 1 +fieldset/HRTIM_BMCMPR: + description: 'High Resolution Timer: Burst Mode Compare Register' + fields: + - name: BMCMP + description: Burst mode compare value + bit_offset: 0 + bit_size: 16 +fieldset/HRTIM_BMCR: + description: 'High Resolution Timer: Burst Mode Control Register' + fields: + - name: BME + description: Burst Mode Enable + bit_offset: 0 + bit_size: 1 + - name: BMOM + description: Burst Mode Operating Mode + bit_offset: 1 + bit_size: 1 + - name: BMCLK + description: Burst Mode Clock source + bit_offset: 2 + bit_size: 3 + - name: BMPRSC + description: Burst Mode Prescaler + bit_offset: 6 + bit_size: 3 + - name: BMPREN + description: Burst Mode Preload Enable + bit_offset: 10 + bit_size: 1 + - name: MTBM + description: Master Timer Burst Mode + bit_offset: 16 + bit_size: 1 + - name: TBM + description: Timer X Burst Mode + bit_offset: 17 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: BMSTAT + bit_offset: 31 + bit_size: 1 +fieldset/HRTIM_BMPER: + description: 'High Resolution Timer: Burst Mode Period Register' + fields: + - name: BMPER + description: Burst mode period value + bit_offset: 0 + bit_size: 16 +fieldset/HRTIM_BMTRGR: + description: 'High Resolution Timer: Burst Mode Trigger Register' + fields: + - name: SW + description: Software start + bit_offset: 0 + bit_size: 1 + - name: MSTRST + description: Master reset or roll-over + bit_offset: 1 + bit_size: 1 + - name: MSTREP + description: Master repetition + bit_offset: 2 + bit_size: 1 + - name: MSTCMP + description: Master Compare X + bit_offset: 3 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: TRST + description: Timer X reset or roll-over + bit_offset: 7 + bit_size: 1 + array: + offsets: + - 0 + - 4 + - 8 + - 12 + - 16 + - name: TREP + description: Timer X repetition + bit_offset: 8 + bit_size: 1 + array: + offsets: + - 0 + - 4 + - 8 + - 12 + - 16 + - name: TCMP1 + description: Timer X compare 1 event + bit_offset: 9 + bit_size: 1 + array: + offsets: + - 0 + - 4 + - 8 + - 12 + - 16 + - name: TCMP2 + description: Timer X compare 2 event + bit_offset: 10 + bit_size: 1 + array: + offsets: + - 0 + - 4 + - 8 + - 12 + - 16 +fieldset/HRTIM_CR1: + description: 'High Resolution Timer: Control Register 1' + fields: + - name: MUDIS + description: Master Update Disable + bit_offset: 0 + bit_size: 1 + - name: TUDIS + description: Timer X Update Disable + bit_offset: 1 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: ADUSRC + description: ADC Trigger X Update Source + bit_offset: 16 + bit_size: 3 + array: + len: 4 + stride: 2 +fieldset/HRTIM_CR2: + description: 'High Resolution Timer: Control Register 2' + fields: + - name: MSWU + description: Master Timer Software Update + bit_offset: 0 + bit_size: 1 + - name: TSWU + description: Timer X Software Update + bit_offset: 1 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: MRST + description: Master Counter Software Reset + bit_offset: 8 + bit_size: 1 + - name: TRST + description: Timer X Counter Software Reset + bit_offset: 9 + bit_size: 1 + array: + len: 5 + stride: 1 +fieldset/HRTIM_DLLCR: + description: 'High Resolution Timer: DLL Control Register' + fields: + - name: CAL + description: DLL Calibration Start + bit_offset: 0 + bit_size: 1 + - name: CALEN + description: DLL Calibration Enable + bit_offset: 1 + bit_size: 1 + - name: CALRTE + description: DLL Calibration Rate + bit_offset: 2 + bit_size: 2 +fieldset/HRTIM_EECR1: + description: 'High Resolution Timer: External Events Control Register 1' + fields: + - name: EESRC + description: External Event X Source + bit_offset: 0 + bit_size: 2 + array: + offsets: + - 0 + - 6 + - 12 + - 18 + - 24 + - name: EEPOL + description: External Event X Polarity + bit_offset: 2 + bit_size: 1 + array: + offsets: + - 0 + - 6 + - 12 + - 18 + - 24 + - name: EESNS + description: External Event X Sensitivity + bit_offset: 3 + bit_size: 2 + array: + offsets: + - 0 + - 6 + - 12 + - 18 + - 24 + - name: EEFAST + description: External Event X Fast Mode + bit_offset: 5 + bit_size: 2 + array: + offsets: + - 0 + - 6 + - 12 + - 18 + - 24 +fieldset/HRTIM_EECR2: + description: 'High Resolution Timer: External Events Control Register 2' + fields: + - name: EESRC + description: External Event X Source + bit_offset: 0 + bit_size: 2 + array: + offsets: + - 0 + - 6 + - 12 + - 18 + - 24 + - name: EEPOL + description: External Event X Polarity + bit_offset: 2 + bit_size: 1 + array: + offsets: + - 0 + - 6 + - 12 + - 18 + - 24 + - name: EESNS + description: External Event X Sensitivity + bit_offset: 3 + bit_size: 2 + array: + offsets: + - 0 + - 6 + - 12 + - 18 + - 24 +fieldset/HRTIM_EECR3: + description: 'High Resolution Timer: External Events Control Register 2' + fields: + - name: EEF + description: External Event X filter + bit_offset: 0 + bit_size: 3 + array: + offsets: + - 0 + - 6 + - 12 + - 18 + - 24 + - name: EEVSD + description: External Event Sampling Clock Division + bit_offset: 30 + bit_size: 2 +fieldset/HRTIM_FLTINR1: + description: 'High Resolution Timer: Fault Input Register 1' + fields: + - name: FLTE + description: Fault X enable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 8 + - 16 + - 24 + - name: FLTP + description: Fault X polarity + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 8 + - 16 + - 24 + - name: FLTSRC + description: Fault X source + bit_offset: 2 + bit_size: 1 + array: + offsets: + - 0 + - 8 + - 16 + - 24 + - name: FLTF + description: Fault X filter + bit_offset: 3 + bit_size: 4 + array: + offsets: + - 0 + - 8 + - 16 + - 24 + - name: FLTLCK + description: Fault X Lock + bit_offset: 7 + bit_size: 1 + array: + offsets: + - 0 + - 8 + - 16 + - 24 +fieldset/HRTIM_FLTINR2: + description: 'High Resolution Timer: Fault Input Register 2' + fields: + - name: FLTE + description: Fault X enable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - name: FLTP + description: Fault X polarity + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - name: FLTSRC + description: Fault X source + bit_offset: 2 + bit_size: 1 + array: + offsets: + - 0 + - name: FLTF + description: Fault X filter + bit_offset: 3 + bit_size: 4 + array: + offsets: + - 0 + - name: FLTLCK + description: Fault X Lock + bit_offset: 7 + bit_size: 1 + array: + offsets: + - 0 + - name: FLTSD + description: Fault Sampling clock division + bit_offset: 24 + bit_size: 2 +fieldset/HRTIM_ICR: + description: 'High Resolution Timer: Interrupt Clear Register' + fields: + - name: FLT + description: Fault X Interrupt Flag Clear + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: SYSFLT + description: System Fault Interrupt Flag Clear + bit_offset: 5 + bit_size: 1 + - name: DLLRDY + description: DLL Ready Interrupt Flag Clear + bit_offset: 16 + bit_size: 1 + - name: BMPER + description: Burst Mode Period Interrupt Flag Clear + bit_offset: 17 + bit_size: 1 +fieldset/HRTIM_IER: + description: 'High Resolution Timer: Interrupt Enable Register' + fields: + - name: FLT + description: Fault X Interrupt Flag Enable + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: SYSFLT + description: System Fault Interrupt Flag Enable + bit_offset: 5 + bit_size: 1 + - name: DLLRDY + description: DLL Ready Interrupt Flag Enable + bit_offset: 16 + bit_size: 1 + - name: BMPER + description: Burst Mode Period Interrupt Flag Enable + bit_offset: 17 + bit_size: 1 +fieldset/HRTIM_ISR: + description: 'High Resolution Timer: Interrupt Status Register' + fields: + - name: FLT + description: Fault X Interrupt Flag + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: SYSFLT + description: System Fault Interrupt Flag + bit_offset: 5 + bit_size: 1 + - name: DLLRDY + description: DLL Ready Interrupt Flag + bit_offset: 16 + bit_size: 1 + - name: BMPER + description: Burst Mode Period Interrupt Flag + bit_offset: 17 + bit_size: 1 +fieldset/HRTIM_ODISR: + description: 'High Resolution Timer: Output Disable Register' + fields: + - name: T1ODIS + description: Timer X Output Disable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - 4 + - 6 + - 8 + - name: T2ODIS + description: Timer X Complementary Output Disable + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - 4 + - 6 + - 8 +fieldset/HRTIM_ODSR: + description: 'High Resolution Timer: Output Disable Status Register' + fields: + - name: T1ODIS + description: Timer X Output Disable Status + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - 4 + - 6 + - 8 + - name: T2ODIS + description: Timer X Complementary Output Disable Status + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - 4 + - 6 + - 8 +fieldset/HRTIM_OENR: + description: 'High Resolution Timer: Output Enable Register' + fields: + - name: T1OEN + description: Timer X Output Enable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - 4 + - 6 + - 8 + - name: T2OEN + description: Timer X Complementary Output Enable + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - 4 + - 6 + - 8 fieldset/MCMPX: description: Master Timer Compare X Register fields: - - name: MCMP - description: Master Timer Compare X value - bit_offset: 0 - bit_size: 16 + - name: MCMP + description: Master Timer Compare X value + bit_offset: 0 + bit_size: 16 fieldset/MCNTR: description: Master Timer Counter Register fields: - - name: MCNT - description: Counter value - bit_offset: 0 - bit_size: 16 + - name: MCNT + description: Counter value + bit_offset: 0 + bit_size: 16 fieldset/MCR: description: Master Timer Control Register fields: - - name: CKPSC - description: HRTIM Master Clock prescaler - bit_offset: 0 - bit_size: 3 - - name: CONT - description: Master Continuous mode - bit_offset: 3 - bit_size: 1 - - name: RETRIG - description: Master Re-triggerable mode - bit_offset: 4 - bit_size: 1 - - name: HALF - description: Half mode enable - bit_offset: 5 - bit_size: 1 - - name: SYNCIN - description: Synchronization input - bit_offset: 8 - bit_size: 2 - enum: SYNCIN - - name: SYNCRSTM - description: Synchronization Resets Master - bit_offset: 10 - bit_size: 1 - - name: SYNCSTRTM - description: Synchronization Starts Master - bit_offset: 11 - bit_size: 1 - - name: SYNCOUT - description: Synchronization output - bit_offset: 12 - bit_size: 2 - enum: SYNCOUT - - name: SYNCSRC - description: Synchronization source - bit_offset: 14 - bit_size: 2 - enum: SYNCSRC - - name: MCEN - description: Master Counter enable - bit_offset: 16 - bit_size: 1 - - name: TCEN - description: Timer X counter enable - bit_offset: 17 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: DACSYNC - description: AC Synchronization - bit_offset: 25 - bit_size: 2 - enum: DACSYNC - - name: PREEN - description: Preload enable - bit_offset: 27 - bit_size: 1 - - name: MREPU - description: Master Timer Repetition update - bit_offset: 29 - bit_size: 1 - - name: BRSTDMA - description: Burst DMA Update - bit_offset: 30 - bit_size: 2 - enum: BRSTDMA + - name: CKPSC + description: HRTIM Master Clock prescaler + bit_offset: 0 + bit_size: 3 + - name: CONT + description: Master Continuous mode + bit_offset: 3 + bit_size: 1 + - name: RETRIG + description: Master Re-triggerable mode + bit_offset: 4 + bit_size: 1 + - name: HALF + description: Half mode enable + bit_offset: 5 + bit_size: 1 + - name: SYNCIN + description: Synchronization input + bit_offset: 8 + bit_size: 2 + enum: SYNCIN + - name: SYNCRSTM + description: Synchronization Resets Master + bit_offset: 10 + bit_size: 1 + - name: SYNCSTRTM + description: Synchronization Starts Master + bit_offset: 11 + bit_size: 1 + - name: SYNCOUT + description: Synchronization output + bit_offset: 12 + bit_size: 2 + enum: SYNCOUT + - name: SYNCSRC + description: Synchronization source + bit_offset: 14 + bit_size: 2 + enum: SYNCSRC + - name: MCEN + description: Master Counter enable + bit_offset: 16 + bit_size: 1 + - name: TCEN + description: Timer X counter enable + bit_offset: 17 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: DACSYNC + description: AC Synchronization + bit_offset: 25 + bit_size: 2 + enum: DACSYNC + - name: PREEN + description: Preload enable + bit_offset: 27 + bit_size: 1 + - name: MREPU + description: Master Timer Repetition update + bit_offset: 29 + bit_size: 1 + - name: BRSTDMA + description: Burst DMA Update + bit_offset: 30 + bit_size: 2 + enum: BRSTDMA fieldset/MDIER: description: Master Timer DMA / Interrupt Enable Register fields: - - name: MCMPIE - description: Master Compare X Interrupt Enable - bit_offset: 0 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: MREPIE - description: Master Repetition Interrupt Enable - bit_offset: 4 - bit_size: 1 - - name: SYNCIE - description: Sync Input Interrupt Enable - bit_offset: 5 - bit_size: 1 - - name: MUPDIE - description: Master Update Interrupt Enable - bit_offset: 6 - bit_size: 1 - - name: MCMPDE - description: Master Compare X DMA request Enable - bit_offset: 16 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: MREPDE - description: Master Repetition DMA request Enable - bit_offset: 20 - bit_size: 1 - - name: SYNCDE - description: Sync Input DMA request Enable - bit_offset: 21 - bit_size: 1 - - name: MUPDDE - description: Master Update DMA request Enable - bit_offset: 22 - bit_size: 1 + - name: MCMPIE + description: Master Compare X Interrupt Enable + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: MREPIE + description: Master Repetition Interrupt Enable + bit_offset: 4 + bit_size: 1 + - name: SYNCIE + description: Sync Input Interrupt Enable + bit_offset: 5 + bit_size: 1 + - name: MUPDIE + description: Master Update Interrupt Enable + bit_offset: 6 + bit_size: 1 + - name: MCMPDE + description: Master Compare X DMA request Enable + bit_offset: 16 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: MREPDE + description: Master Repetition DMA request Enable + bit_offset: 20 + bit_size: 1 + - name: SYNCDE + description: Sync Input DMA request Enable + bit_offset: 21 + bit_size: 1 + - name: MUPDDE + description: Master Update DMA request Enable + bit_offset: 22 + bit_size: 1 fieldset/MICR: description: Master Timer Interrupt Clear Register fields: - - name: MCMPC - description: Master Compare X Interrupt flag clear - bit_offset: 0 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: MREPC - description: Repetition Interrupt flag clear - bit_offset: 4 - bit_size: 1 - - name: SYNCC - description: Sync Input Interrupt flag clear - bit_offset: 5 - bit_size: 1 - - name: MUPDC - description: Master update Interrupt flag clear - bit_offset: 6 - bit_size: 1 + - name: MCMPC + description: Master Compare X Interrupt flag clear + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: MREPC + description: Repetition Interrupt flag clear + bit_offset: 4 + bit_size: 1 + - name: SYNCC + description: Sync Input Interrupt flag clear + bit_offset: 5 + bit_size: 1 + - name: MUPDC + description: Master update Interrupt flag clear + bit_offset: 6 + bit_size: 1 fieldset/MISR: description: Master Timer Interrupt Status Register fields: - - name: MCMP - description: Master Compare X Interrupt Flag - bit_offset: 0 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: EVENT - - name: MREP - description: Master Repetition Interrupt Flag - bit_offset: 4 - bit_size: 1 - enum: EVENT - - name: SYNC - description: Sync Input Interrupt Flag - bit_offset: 5 - bit_size: 1 - enum: EVENT - - name: MUPD - description: Master Update Interrupt Flag - bit_offset: 6 - bit_size: 1 - enum: EVENT + - name: MCMP + description: Master Compare X Interrupt Flag + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: EVENT + - name: MREP + description: Master Repetition Interrupt Flag + bit_offset: 4 + bit_size: 1 + enum: EVENT + - name: SYNC + description: Sync Input Interrupt Flag + bit_offset: 5 + bit_size: 1 + enum: EVENT + - name: MUPD + description: Master Update Interrupt Flag + bit_offset: 6 + bit_size: 1 + enum: EVENT fieldset/MPER: description: Master Timer Period Register fields: - - name: MPER - description: Master Timer Period value - bit_offset: 0 - bit_size: 16 + - name: MPER + description: Master Timer Period value + bit_offset: 0 + bit_size: 16 fieldset/MREP: description: Master Timer Repetition Register fields: - - name: MREP - description: Master Timer Repetition counter value - bit_offset: 0 - bit_size: 8 + - name: MREP + description: Master Timer Repetition counter value + bit_offset: 0 + bit_size: 8 fieldset/TIMXCCR: description: Timerx Capture 2 Control Register fields: - - name: SWCPT - description: Software Capture - bit_offset: 0 - bit_size: 1 - enum: CAPTUREEFFECT - - name: UPDCPT - description: Update Capture - bit_offset: 1 - bit_size: 1 - enum: CAPTUREEFFECT - - name: EXEVCPT - description: External Event X Capture - bit_offset: 2 - bit_size: 1 - array: - len: 10 - stride: 1 - enum: CAPTUREEFFECT - - name: TXSET - description: Timer X output Set - bit_offset: 16 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TXRST - description: Timer X output Reset - bit_offset: 17 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TXCMP - description: Timer X Compare X - bit_offset: 18 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: CAPTUREEFFECT - - name: TYSET - description: Timer Y output Set - bit_offset: 20 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TYRST - description: Timer Y output Reset - bit_offset: 21 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TYCMP - description: Timer Y Compare X - bit_offset: 22 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: CAPTUREEFFECT - - name: TZSET - description: Timer Z output Set - bit_offset: 24 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TZRST - description: Timer Z output Reset - bit_offset: 25 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TZCMP - description: Timer Z Compare X - bit_offset: 26 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: CAPTUREEFFECT - - name: TTSET - description: Timer T output Set - bit_offset: 28 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TTRST - description: Timer T output Reset - bit_offset: 29 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TTCMP - description: Timer T Compare X - bit_offset: 30 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: CAPTUREEFFECT + - name: SWCPT + description: Software Capture + bit_offset: 0 + bit_size: 1 + enum: CAPTUREEFFECT + - name: UPDCPT + description: Update Capture + bit_offset: 1 + bit_size: 1 + enum: CAPTUREEFFECT + - name: EXEVCPT + description: External Event X Capture + bit_offset: 2 + bit_size: 1 + array: + len: 10 + stride: 1 + enum: CAPTUREEFFECT + - name: TXSET + description: Timer X output Set + bit_offset: 16 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TXRST + description: Timer X output Reset + bit_offset: 17 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TXCMP + description: Timer X Compare X + bit_offset: 18 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: CAPTUREEFFECT + - name: TYSET + description: Timer Y output Set + bit_offset: 20 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TYRST + description: Timer Y output Reset + bit_offset: 21 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TYCMP + description: Timer Y Compare X + bit_offset: 22 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: CAPTUREEFFECT + - name: TZSET + description: Timer Z output Set + bit_offset: 24 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TZRST + description: Timer Z output Reset + bit_offset: 25 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TZCMP + description: Timer Z Compare X + bit_offset: 26 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: CAPTUREEFFECT + - name: TTSET + description: Timer T output Set + bit_offset: 28 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TTRST + description: Timer T output Reset + bit_offset: 29 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TTCMP + description: Timer T Compare X + bit_offset: 30 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: CAPTUREEFFECT fieldset/TIMXCHP: description: Timerx Chopper Register fields: - - name: CARFRQ - description: Timerx carrier frequency value - bit_offset: 0 - bit_size: 4 - - name: CARDTY - description: Timerx chopper duty cycle value - bit_offset: 4 - bit_size: 3 - - name: STRTPW - description: Timerx start pulsewidth - bit_offset: 7 - bit_size: 4 + - name: CARFRQ + description: Timerx carrier frequency value + bit_offset: 0 + bit_size: 4 + - name: CARDTY + description: Timerx chopper duty cycle value + bit_offset: 4 + bit_size: 3 + - name: STRTPW + description: Timerx start pulsewidth + bit_offset: 7 + bit_size: 4 fieldset/TIMXCMP: description: Timerx Compare X Register fields: - - name: CMP - description: Timerx Compare X value - bit_offset: 0 - bit_size: 16 + - name: CMP + description: Timerx Compare X value + bit_offset: 0 + bit_size: 16 fieldset/TIMXCMPC: description: Timerx Compare X Compound Register fields: - - name: CMP - description: Timerx Compare X value - bit_offset: 0 - bit_size: 16 - - name: REP - description: Timerx Repetition value (aliased from HRTIM_REPx register) - bit_offset: 16 - bit_size: 8 + - name: CMP + description: Timerx Compare X value + bit_offset: 0 + bit_size: 16 + - name: REP + description: Timerx Repetition value (aliased from HRTIM_REPx register) + bit_offset: 16 + bit_size: 8 fieldset/TIMXCNT: description: Timerx Counter Register fields: - - name: CNT - description: Timerx Counter value - bit_offset: 0 - bit_size: 16 + - name: CNT + description: Timerx Counter value + bit_offset: 0 + bit_size: 16 fieldset/TIMXCPT: description: Timerx Capture X Register fields: - - name: CPT - description: Timerx Capture X value - bit_offset: 0 - bit_size: 16 + - name: CPT + description: Timerx Capture X value + bit_offset: 0 + bit_size: 16 fieldset/TIMXCR: description: Timerx Control Register fields: - - name: CKPSC - description: HRTIM Timer x Clock prescaler - bit_offset: 0 - bit_size: 3 - - name: CONT - description: Continuous mode - bit_offset: 3 - bit_size: 1 - - name: RETRIG - description: Re-triggerable mode - bit_offset: 4 - bit_size: 1 - - name: HALF - description: Half mode enable - bit_offset: 5 - bit_size: 1 - - name: PSHPLL - description: Push-Pull mode enable - bit_offset: 6 - bit_size: 1 - - name: SYNCRST - description: Synchronization Resets Timer X - bit_offset: 10 - bit_size: 1 - enum: SYNCRST - - name: SYNCSTRT - description: Synchronization Starts Timer X - bit_offset: 11 - bit_size: 1 - enum: SYNCSTRT - - name: DELCMP2 - description: Delayed CMP2 mode - bit_offset: 12 - bit_size: 2 - enum: DELCMP - - name: DELCMP4 - description: Delayed CMP4 mode - bit_offset: 14 - bit_size: 2 - enum: DELCMP - - name: REPU - description: Timer X Repetition update - bit_offset: 17 - bit_size: 1 - - name: RSTU - description: Timer X reset update - bit_offset: 18 - bit_size: 1 - - name: TAU - description: Timer A update - bit_offset: 19 - bit_size: 1 - - name: TBU - description: Timer B update - bit_offset: 20 - bit_size: 1 - - name: TCU - description: Timer C update - bit_offset: 21 - bit_size: 1 - - name: TDU - description: Timer D update - bit_offset: 22 - bit_size: 1 - - name: TEU - description: Timer E update - bit_offset: 23 - bit_size: 1 - - name: MSTU - description: Master Timer update - bit_offset: 24 - bit_size: 1 - - name: DACSYNC - description: AC Synchronization - bit_offset: 25 - bit_size: 2 - enum: DACSYNC - - name: PREEN - description: Preload enable - bit_offset: 27 - bit_size: 1 - - name: UPDGAT - description: Update Gating - bit_offset: 28 - bit_size: 4 - enum: UPDGAT + - name: CKPSC + description: HRTIM Timer x Clock prescaler + bit_offset: 0 + bit_size: 3 + - name: CONT + description: Continuous mode + bit_offset: 3 + bit_size: 1 + - name: RETRIG + description: Re-triggerable mode + bit_offset: 4 + bit_size: 1 + - name: HALF + description: Half mode enable + bit_offset: 5 + bit_size: 1 + - name: PSHPLL + description: Push-Pull mode enable + bit_offset: 6 + bit_size: 1 + - name: SYNCRST + description: Synchronization Resets Timer X + bit_offset: 10 + bit_size: 1 + enum: SYNCRST + - name: SYNCSTRT + description: Synchronization Starts Timer X + bit_offset: 11 + bit_size: 1 + enum: SYNCSTRT + - name: DELCMP2 + description: Delayed CMP2 mode + bit_offset: 12 + bit_size: 2 + enum: DELCMP + - name: DELCMP4 + description: Delayed CMP4 mode + bit_offset: 14 + bit_size: 2 + enum: DELCMP + - name: REPU + description: Timer X Repetition update + bit_offset: 17 + bit_size: 1 + - name: RSTU + description: Timer X reset update + bit_offset: 18 + bit_size: 1 + - name: TAU + description: Timer A update + bit_offset: 19 + bit_size: 1 + - name: TBU + description: Timer B update + bit_offset: 20 + bit_size: 1 + - name: TCU + description: Timer C update + bit_offset: 21 + bit_size: 1 + - name: TDU + description: Timer D update + bit_offset: 22 + bit_size: 1 + - name: TEU + description: Timer E update + bit_offset: 23 + bit_size: 1 + - name: MSTU + description: Master Timer update + bit_offset: 24 + bit_size: 1 + - name: DACSYNC + description: AC Synchronization + bit_offset: 25 + bit_size: 2 + enum: DACSYNC + - name: PREEN + description: Preload enable + bit_offset: 27 + bit_size: 1 + - name: UPDGAT + description: Update Gating + bit_offset: 28 + bit_size: 4 + enum: UPDGAT fieldset/TIMXDIER: description: Timerx DMA / Interrupt Enable Register fields: - - name: CMPIE - description: Compare X Interrupt Enable - bit_offset: 0 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: REPIE - description: Repetition Interrupt Enable - bit_offset: 4 - bit_size: 1 - - name: UPDIE - description: Update Interrupt Enable - bit_offset: 6 - bit_size: 1 - - name: CPTIE - description: Capture Interrupt Enable - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: SETRIE - description: Output X Set Interrupt Enable - bit_offset: 9 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - name: RSTRIE - description: Output X Reset Interrupt Enable - bit_offset: 10 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - name: RSTIE - description: Reset/roll-over Interrupt Enable - bit_offset: 13 - bit_size: 1 - - name: DLYPRTIE - description: Delayed Protection Interrupt Enable - bit_offset: 14 - bit_size: 1 - - name: CMPDE - description: Compare X DMA request Enable - bit_offset: 16 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: REPDE - description: Repetition DMA request Enable - bit_offset: 20 - bit_size: 1 - - name: UPDDE - description: Update DMA request Enable - bit_offset: 22 - bit_size: 1 - - name: CPTDE - description: Capture X DMA request Enable - bit_offset: 23 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: SETRDE - description: Output X Set DMA request Enable - bit_offset: 25 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - name: RSTRDE - description: Output X Reset DMA request Enable - bit_offset: 26 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - name: RSTDE - description: Reset/roll-over DMA request Enable - bit_offset: 29 - bit_size: 1 - - name: DLYPRTDE - description: Delayed Protection DMA request Enable - bit_offset: 30 - bit_size: 1 + - name: CMPIE + description: Compare X Interrupt Enable + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: REPIE + description: Repetition Interrupt Enable + bit_offset: 4 + bit_size: 1 + - name: UPDIE + description: Update Interrupt Enable + bit_offset: 6 + bit_size: 1 + - name: CPTIE + description: Capture Interrupt Enable + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: SETRIE + description: Output X Set Interrupt Enable + bit_offset: 9 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - name: RSTRIE + description: Output X Reset Interrupt Enable + bit_offset: 10 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - name: RSTIE + description: Reset/roll-over Interrupt Enable + bit_offset: 13 + bit_size: 1 + - name: DLYPRTIE + description: Delayed Protection Interrupt Enable + bit_offset: 14 + bit_size: 1 + - name: CMPDE + description: Compare X DMA request Enable + bit_offset: 16 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: REPDE + description: Repetition DMA request Enable + bit_offset: 20 + bit_size: 1 + - name: UPDDE + description: Update DMA request Enable + bit_offset: 22 + bit_size: 1 + - name: CPTDE + description: Capture X DMA request Enable + bit_offset: 23 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: SETRDE + description: Output X Set DMA request Enable + bit_offset: 25 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - name: RSTRDE + description: Output X Reset DMA request Enable + bit_offset: 26 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - name: RSTDE + description: Reset/roll-over DMA request Enable + bit_offset: 29 + bit_size: 1 + - name: DLYPRTDE + description: Delayed Protection DMA request Enable + bit_offset: 30 + bit_size: 1 fieldset/TIMXDT: description: Timerx Deadtime Register fields: - - name: DTR - description: Deadtime Rising value - bit_offset: 0 - bit_size: 9 - - name: SDTR - description: Sign Deadtime Rising value - bit_offset: 9 - bit_size: 1 - enum: SDTR - - name: DTPRSC - description: Deadtime Prescaler - bit_offset: 10 - bit_size: 3 - - name: DTRSLK - description: Deadtime Rising Sign Lock - bit_offset: 14 - bit_size: 1 - enum: LOCKED - - name: DTRLK - description: Deadtime Rising Lock - bit_offset: 15 - bit_size: 1 - enum: LOCKED - - name: DTF - description: Deadtime Falling value - bit_offset: 16 - bit_size: 9 - - name: SDTF - description: Sign Deadtime Falling value - bit_offset: 25 - bit_size: 1 - enum: SDTF - - name: DTFSLK - description: Deadtime Falling Sign Lock - bit_offset: 30 - bit_size: 1 - enum: LOCKED - - name: DTFLK - description: Deadtime Falling Lock - bit_offset: 31 - bit_size: 1 - enum: LOCKED + - name: DTR + description: Deadtime Rising value + bit_offset: 0 + bit_size: 9 + - name: SDTR + description: Sign Deadtime Rising value + bit_offset: 9 + bit_size: 1 + enum: SDTR + - name: DTPRSC + description: Deadtime Prescaler + bit_offset: 10 + bit_size: 3 + - name: DTRSLK + description: Deadtime Rising Sign Lock + bit_offset: 14 + bit_size: 1 + enum: LOCKED + - name: DTRLK + description: Deadtime Rising Lock + bit_offset: 15 + bit_size: 1 + enum: LOCKED + - name: DTF + description: Deadtime Falling value + bit_offset: 16 + bit_size: 9 + - name: SDTF + description: Sign Deadtime Falling value + bit_offset: 25 + bit_size: 1 + enum: SDTF + - name: DTFSLK + description: Deadtime Falling Sign Lock + bit_offset: 30 + bit_size: 1 + enum: LOCKED + - name: DTFLK + description: Deadtime Falling Lock + bit_offset: 31 + bit_size: 1 + enum: LOCKED fieldset/TIMXEEF: description: Timer X External Event Filtering Register fields: - - name: LTCH - description: External Event X latch - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 6 - - name: FLTR - description: External Event X filter - bit_offset: 1 - bit_size: 4 - array: - len: 5 - stride: 6 - enum: EEFLTR + - name: LTCH + description: External Event X latch + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 6 + - name: FLTR + description: External Event X filter + bit_offset: 1 + bit_size: 4 + array: + len: 5 + stride: 6 + enum: EEFLTR fieldset/TIMXFLT: description: Timerx Fault Register fields: - - name: FLTEN - description: Fault X enable - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 1 - enum: FLTEN - - name: FLTLCK - description: Fault sources Lock - bit_offset: 31 - bit_size: 1 - enum: LOCKED + - name: FLTEN + description: Fault X enable + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + enum: FLTEN + - name: FLTLCK + description: Fault sources Lock + bit_offset: 31 + bit_size: 1 + enum: LOCKED fieldset/TIMXICR: description: Timerx Interrupt Clear Register fields: - - name: CMPC - description: Compare X Interrupt flag Clear - bit_offset: 0 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: REPC - description: Repetition Interrupt flag Clear - bit_offset: 4 - bit_size: 1 - - name: UPDC - description: Update Interrupt flag Clear - bit_offset: 6 - bit_size: 1 - - name: CPTC - description: Capture X Interrupt flag Clear - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: SETRC - description: Output X Set flag Clear - bit_offset: 9 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - name: RSTRC - description: Output X Reset flag Clear - bit_offset: 10 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - name: RSTC - description: Reset Interrupt flag Clear - bit_offset: 13 - bit_size: 1 - - name: DLYPRTC - description: Delayed Protection Flag Clear - bit_offset: 14 - bit_size: 1 + - name: CMPC + description: Compare X Interrupt flag Clear + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: REPC + description: Repetition Interrupt flag Clear + bit_offset: 4 + bit_size: 1 + - name: UPDC + description: Update Interrupt flag Clear + bit_offset: 6 + bit_size: 1 + - name: CPTC + description: Capture X Interrupt flag Clear + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: SETRC + description: Output X Set flag Clear + bit_offset: 9 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - name: RSTRC + description: Output X Reset flag Clear + bit_offset: 10 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - name: RSTC + description: Reset Interrupt flag Clear + bit_offset: 13 + bit_size: 1 + - name: DLYPRTC + description: Delayed Protection Flag Clear + bit_offset: 14 + bit_size: 1 fieldset/TIMXISR: description: Timerx Interrupt Status Register fields: - - name: CMP - description: Compare X Interrupt Flag - bit_offset: 0 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: EVENT - - name: REP - description: Repetition Interrupt Flag - bit_offset: 4 - bit_size: 1 - enum: EVENT - - name: UPD - description: Update Interrupt Flag - bit_offset: 6 - bit_size: 1 - enum: EVENT - - name: CPT - description: Capture X Interrupt Flag - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: EVENT - - name: SETR - description: Output X Set Interrupt Flag - bit_offset: 9 - bit_size: 1 - array: - offsets: - - 0 - - 2 - enum: EVENT - - name: RSTR - description: Output X Reset Interrupt Flag - bit_offset: 10 - bit_size: 1 - array: - offsets: - - 0 - - 2 - enum: EVENT - - name: RST - description: Reset Interrupt Flag - bit_offset: 13 - bit_size: 1 - enum: EVENT - - name: DLYPRT - description: Delayed Protection Flag - bit_offset: 14 - bit_size: 1 - enum: TIMAISR_DLYPRT - - name: CPPSTAT - description: Current Push Pull Status - bit_offset: 16 - bit_size: 1 - enum: CPPSTAT - - name: IPPSTAT - description: Idle Push Pull Status - bit_offset: 17 - bit_size: 1 - enum: IPPSTAT - - name: OSTAT - description: Output X State - bit_offset: 18 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: OUTPUTSTATE - - name: OCPY - description: Output X Copy - bit_offset: 20 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: OUTPUTSTATE + - name: CMP + description: Compare X Interrupt Flag + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: EVENT + - name: REP + description: Repetition Interrupt Flag + bit_offset: 4 + bit_size: 1 + enum: EVENT + - name: UPD + description: Update Interrupt Flag + bit_offset: 6 + bit_size: 1 + enum: EVENT + - name: CPT + description: Capture X Interrupt Flag + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: EVENT + - name: SETR + description: Output X Set Interrupt Flag + bit_offset: 9 + bit_size: 1 + array: + offsets: + - 0 + - 2 + enum: EVENT + - name: RSTR + description: Output X Reset Interrupt Flag + bit_offset: 10 + bit_size: 1 + array: + offsets: + - 0 + - 2 + enum: EVENT + - name: RST + description: Reset Interrupt Flag + bit_offset: 13 + bit_size: 1 + enum: EVENT + - name: DLYPRT + description: Delayed Protection Flag + bit_offset: 14 + bit_size: 1 + enum: TIMAISR_DLYPRT + - name: CPPSTAT + description: Current Push Pull Status + bit_offset: 16 + bit_size: 1 + enum: CPPSTAT + - name: IPPSTAT + description: Idle Push Pull Status + bit_offset: 17 + bit_size: 1 + enum: IPPSTAT + - name: OSTAT + description: Output X State + bit_offset: 18 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: OUTPUTSTATE + - name: OCPY + description: Output X Copy + bit_offset: 20 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: OUTPUTSTATE fieldset/TIMXOUTR: description: Timerx Output Register fields: - - name: POL - description: Output 1 polarity - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 16 - enum: POL - - name: IDLEM - description: Output X Idle mode - bit_offset: 2 - bit_size: 1 - array: - offsets: - - 0 - - 16 - - name: IDLES - description: Output X Idle State - bit_offset: 3 - bit_size: 1 - array: - offsets: - - 0 - - 16 - - name: FAULTX - description: Output X Fault state - bit_offset: 4 - bit_size: 2 - array: - offsets: - - 0 - - 16 - enum: FAULT - - name: CHP - description: Output X Chopper enable - bit_offset: 6 - bit_size: 1 - array: - offsets: - - 0 - - 16 - - name: DIDL - description: Output X Deadtime upon burst mode Idle entry - bit_offset: 7 - bit_size: 1 - array: - offsets: - - 0 - - 16 - - name: DTEN - description: Deadtime enable - bit_offset: 8 - bit_size: 1 - - name: DLYPRTEN - description: Delayed Protection Enable - bit_offset: 9 - bit_size: 1 - - name: DLYPRT - description: Delayed Protection - bit_offset: 10 - bit_size: 3 - enum: DLYPRT + - name: POL + description: Output 1 polarity + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 16 + enum: POL + - name: IDLEM + description: Output X Idle mode + bit_offset: 2 + bit_size: 1 + array: + offsets: + - 0 + - 16 + - name: IDLES + description: Output X Idle State + bit_offset: 3 + bit_size: 1 + array: + offsets: + - 0 + - 16 + - name: FAULTX + description: Output X Fault state + bit_offset: 4 + bit_size: 2 + array: + offsets: + - 0 + - 16 + enum: FAULT + - name: CHP + description: Output X Chopper enable + bit_offset: 6 + bit_size: 1 + array: + offsets: + - 0 + - 16 + - name: DIDL + description: Output X Deadtime upon burst mode Idle entry + bit_offset: 7 + bit_size: 1 + array: + offsets: + - 0 + - 16 + - name: DTEN + description: Deadtime enable + bit_offset: 8 + bit_size: 1 + - name: DLYPRTEN + description: Delayed Protection Enable + bit_offset: 9 + bit_size: 1 + - name: DLYPRT + description: Delayed Protection + bit_offset: 10 + bit_size: 3 + enum: DLYPRT fieldset/TIMXPER: description: Timerx Period Register fields: - - name: PER - description: Timerx Period value - bit_offset: 0 - bit_size: 16 + - name: PER + description: Timerx Period value + bit_offset: 0 + bit_size: 16 fieldset/TIMXREP: description: Timerx Repetition Register fields: - - name: REP - description: Timerx Repetition counter value - bit_offset: 0 - bit_size: 8 + - name: REP + description: Timerx Repetition counter value + bit_offset: 0 + bit_size: 8 fieldset/TIMXRST: description: Timerx Reset Register fields: - - name: UPDT - description: Timer X Update reset - bit_offset: 1 - bit_size: 1 - enum: RESETEFFECT - - name: CMP - description: Timer X compare X reset - bit_offset: 2 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: RESETEFFECT - - name: MSTPER - description: Master timer Period - bit_offset: 4 - bit_size: 1 - enum: RESETEFFECT - - name: MSTCMP - description: Master compare X - bit_offset: 5 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: RESETEFFECT - - name: EXTEVNT - description: External Event X - bit_offset: 9 - bit_size: 1 - array: - len: 10 - stride: 1 - enum: RESETEFFECT - - name: TCMP1 - description: Timer X compare 1 event - bit_offset: 19 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 6 - - 9 - enum: RESETEFFECT - - name: TCMP2 - description: Timer X compare 2 event - bit_offset: 20 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 6 - - 9 - enum: RESETEFFECT - - name: TCMP4 - description: Timer X compare 4 event - bit_offset: 21 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 6 - - 9 - enum: RESETEFFECT + - name: UPDT + description: Timer X Update reset + bit_offset: 1 + bit_size: 1 + enum: RESETEFFECT + - name: CMP + description: Timer X compare X reset + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: RESETEFFECT + - name: MSTPER + description: Master timer Period + bit_offset: 4 + bit_size: 1 + enum: RESETEFFECT + - name: MSTCMP + description: Master compare X + bit_offset: 5 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: RESETEFFECT + - name: EXTEVNT + description: External Event X + bit_offset: 9 + bit_size: 1 + array: + len: 10 + stride: 1 + enum: RESETEFFECT + - name: TCMP1 + description: Timer X compare 1 event + bit_offset: 19 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 6 + - 9 + enum: RESETEFFECT + - name: TCMP2 + description: Timer X compare 2 event + bit_offset: 20 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 6 + - 9 + enum: RESETEFFECT + - name: TCMP4 + description: Timer X compare 4 event + bit_offset: 21 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 6 + - 9 + enum: RESETEFFECT fieldset/TIMXRSTR: description: Timerx OutputX Reset Register fields: - - name: SRT - description: Software Reset trigger - bit_offset: 0 - bit_size: 1 - enum: INACTIVEEFFECT - - name: RESYNC - description: Timer X resynchronizaton - bit_offset: 1 - bit_size: 1 - enum: INACTIVEEFFECT - - name: PER - description: Timer X Period - bit_offset: 2 - bit_size: 1 - enum: INACTIVEEFFECT - - name: CMP - description: Timer X compare X - bit_offset: 3 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: INACTIVEEFFECT - - name: MSTPER - description: Master Period - bit_offset: 7 - bit_size: 1 - enum: INACTIVEEFFECT - - name: MSTCMP - description: Master Compare X - bit_offset: 8 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: INACTIVEEFFECT - - name: TIMEVNT - description: Timer Event X - bit_offset: 12 - bit_size: 1 - array: - len: 9 - stride: 1 - enum: INACTIVEEFFECT - - name: EXTEVNT - description: External Event X - bit_offset: 21 - bit_size: 1 - array: - len: 10 - stride: 1 - enum: INACTIVEEFFECT - - name: UPDATE - description: Registers update (transfer preload to active) - bit_offset: 31 - bit_size: 1 - enum: INACTIVEEFFECT + - name: SRT + description: Software Reset trigger + bit_offset: 0 + bit_size: 1 + enum: INACTIVEEFFECT + - name: RESYNC + description: Timer X resynchronizaton + bit_offset: 1 + bit_size: 1 + enum: INACTIVEEFFECT + - name: PER + description: Timer X Period + bit_offset: 2 + bit_size: 1 + enum: INACTIVEEFFECT + - name: CMP + description: Timer X compare X + bit_offset: 3 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: INACTIVEEFFECT + - name: MSTPER + description: Master Period + bit_offset: 7 + bit_size: 1 + enum: INACTIVEEFFECT + - name: MSTCMP + description: Master Compare X + bit_offset: 8 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: INACTIVEEFFECT + - name: TIMEVNT + description: Timer Event X + bit_offset: 12 + bit_size: 1 + array: + len: 9 + stride: 1 + enum: INACTIVEEFFECT + - name: EXTEVNT + description: External Event X + bit_offset: 21 + bit_size: 1 + array: + len: 10 + stride: 1 + enum: INACTIVEEFFECT + - name: UPDATE + description: Registers update (transfer preload to active) + bit_offset: 31 + bit_size: 1 + enum: INACTIVEEFFECT fieldset/TIMXSETR: description: Timerx OutputX Set Register fields: - - name: SST - description: Software Set trigger - bit_offset: 0 - bit_size: 1 - enum: ACTIVEEFFECT - - name: RESYNC - description: Timer X resynchronizaton - bit_offset: 1 - bit_size: 1 - enum: ACTIVEEFFECT - - name: PER - description: Timer X Period - bit_offset: 2 - bit_size: 1 - enum: ACTIVEEFFECT - - name: CMP - description: Timer X compare X - bit_offset: 3 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: ACTIVEEFFECT - - name: MSTPER - description: Master Period - bit_offset: 7 - bit_size: 1 - enum: ACTIVEEFFECT - - name: MSTCMPX - description: Master Compare X - bit_offset: 8 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: ACTIVEEFFECT - - name: TIMEVNT - description: Timer Event X - bit_offset: 12 - bit_size: 1 - array: - len: 9 - stride: 1 - enum: ACTIVEEFFECT - - name: EXTEVNT - description: External Event X - bit_offset: 21 - bit_size: 1 - array: - len: 10 - stride: 1 - enum: ACTIVEEFFECT - - name: UPDATE - description: Registers update (transfer preload to active) - bit_offset: 31 - bit_size: 1 - enum: ACTIVEEFFECT + - name: SST + description: Software Set trigger + bit_offset: 0 + bit_size: 1 + enum: ACTIVEEFFECT + - name: RESYNC + description: Timer X resynchronizaton + bit_offset: 1 + bit_size: 1 + enum: ACTIVEEFFECT + - name: PER + description: Timer X Period + bit_offset: 2 + bit_size: 1 + enum: ACTIVEEFFECT + - name: CMP + description: Timer X compare X + bit_offset: 3 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: ACTIVEEFFECT + - name: MSTPER + description: Master Period + bit_offset: 7 + bit_size: 1 + enum: ACTIVEEFFECT + - name: MSTCMPX + description: Master Compare X + bit_offset: 8 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: ACTIVEEFFECT + - name: TIMEVNT + description: Timer Event X + bit_offset: 12 + bit_size: 1 + array: + len: 9 + stride: 1 + enum: ACTIVEEFFECT + - name: EXTEVNT + description: External Event X + bit_offset: 21 + bit_size: 1 + array: + len: 10 + stride: 1 + enum: ACTIVEEFFECT + - name: UPDATE + description: Registers update (transfer preload to active) + bit_offset: 31 + bit_size: 1 + enum: ACTIVEEFFECT enum/ACTIVEEFFECT: bit_size: 1 variants: - - name: NoEffect - description: Timer event has no effect - value: 0 - - name: SetActive - description: Timer event forces the output to its active state - value: 1 + - name: NoEffect + description: Timer event has no effect + value: 0 + - name: SetActive + description: Timer event forces the output to its active state + value: 1 enum/BRSTDMA: bit_size: 2 variants: - - name: Independent - description: Update done independently from the DMA burst transfer completion - value: 0 - - name: Completion - description: Update done when the DMA burst transfer is completed - value: 1 - - name: Rollover - description: Update done on master timer roll-over following a DMA burst transfer completion - value: 2 + - name: Independent + description: Update done independently from the DMA burst transfer completion + value: 0 + - name: Completion + description: Update done when the DMA burst transfer is completed + value: 1 + - name: Rollover + description: Update done on master timer roll-over following a DMA burst transfer completion + value: 2 enum/CAPTUREEFFECT: bit_size: 1 variants: - - name: NoEffect - description: Timer event has no effect - value: 0 - - name: TriggerCapture - description: Timer event triggers capture - value: 1 + - name: NoEffect + description: Timer event has no effect + value: 0 + - name: TriggerCapture + description: Timer event triggers capture + value: 1 enum/CPPSTAT: bit_size: 1 variants: - - name: Output1Active - description: Signal applied on output 1 and output 2 forced inactive - value: 0 - - name: Output2Active - description: Signal applied on output 2 and output 1 forced inactive - value: 1 + - name: Output1Active + description: Signal applied on output 1 and output 2 forced inactive + value: 0 + - name: Output2Active + description: Signal applied on output 2 and output 1 forced inactive + value: 1 enum/DACSYNC: bit_size: 2 variants: - - name: Disabled - description: No DAC trigger generated - value: 0 - - name: DACSync1 - description: Trigger generated on DACSync1 - value: 1 - - name: DACSync2 - description: Trigger generated on DACSync2 - value: 2 - - name: DACSync3 - description: Trigger generated on DACSync3 - value: 3 + - name: Disabled + description: No DAC trigger generated + value: 0 + - name: DACSync1 + description: Trigger generated on DACSync1 + value: 1 + - name: DACSync2 + description: Trigger generated on DACSync2 + value: 2 + - name: DACSync3 + description: Trigger generated on DACSync3 + value: 3 enum/DELCMP: bit_size: 2 variants: - - name: Standard - description: CMP register is always active (standard compare mode) - value: 0 - - name: Capture1 - description: CMP is recomputed and is active following a capture 1 event - value: 1 - - name: CaptureX_Compare1 - description: CMP is recomputed and is active following a capture 1 event or a Compare 1 match - value: 2 - - name: CaptureX_Compare3 - description: CMP is recomputed and is active following a capture 1 event or a Compare 3 match - value: 3 + - name: Standard + description: CMP register is always active (standard compare mode) + value: 0 + - name: Capture1 + description: CMP is recomputed and is active following a capture 1 event + value: 1 + - name: CaptureX_Compare1 + description: CMP is recomputed and is active following a capture 1 event or a Compare 1 match + value: 2 + - name: CaptureX_Compare3 + description: CMP is recomputed and is active following a capture 1 event or a Compare 3 match + value: 3 enum/DLYPRT: bit_size: 3 variants: - - name: Output1_EE6 - description: Output 1 delayed idle on external event 6 - value: 0 - - name: Output2_EE6 - description: Output 2 delayed idle on external event 6 - value: 1 - - name: Output1_2_EE6 - description: Output 1 and 2 delayed idle on external event 6 - value: 2 - - name: Balanced_EE6 - description: Balanced idle on external event 6 - value: 3 - - name: Output1_EE7 - description: Output 1 delayed idle on external event 7 - value: 4 - - name: Output2_EE7 - description: Output 2 delayed idle on external event 7 - value: 5 - - name: Output1_2_EE7 - description: Output 1 and 2 delayed idle on external event 7 - value: 6 - - name: Balanced_EE7 - description: Balanced idle on external event 7 - value: 7 + - name: Output1_EE6 + description: Output 1 delayed idle on external event 6 + value: 0 + - name: Output2_EE6 + description: Output 2 delayed idle on external event 6 + value: 1 + - name: Output1_2_EE6 + description: Output 1 and 2 delayed idle on external event 6 + value: 2 + - name: Balanced_EE6 + description: Balanced idle on external event 6 + value: 3 + - name: Output1_EE7 + description: Output 1 delayed idle on external event 7 + value: 4 + - name: Output2_EE7 + description: Output 2 delayed idle on external event 7 + value: 5 + - name: Output1_2_EE7 + description: Output 1 and 2 delayed idle on external event 7 + value: 6 + - name: Balanced_EE7 + description: Balanced idle on external event 7 + value: 7 enum/EEFLTR: bit_size: 4 variants: - - name: Disabled - description: No filtering - value: 0 - - name: BlankResetToCompare1 - description: Blanking from counter reset/roll-over to Compare 1 - value: 1 - - name: BlankResetToCompare2 - description: Blanking from counter reset/roll-over to Compare 2 - value: 2 - - name: BlankResetToCompare3 - description: Blanking from counter reset/roll-over to Compare 3 - value: 3 - - name: BlankResetToCompare4 - description: Blanking from counter reset/roll-over to Compare 4 - value: 4 - - name: BlankTIMFLTR1 - description: "Blanking from another timing unit: TIMFLTR1 source" - value: 5 - - name: BlankTIMFLTR2 - description: "Blanking from another timing unit: TIMFLTR2 source" - value: 6 - - name: BlankTIMFLTR3 - description: "Blanking from another timing unit: TIMFLTR3 source" - value: 7 - - name: BlankTIMFLTR4 - description: "Blanking from another timing unit: TIMFLTR4 source" - value: 8 - - name: BlankTIMFLTR5 - description: "Blanking from another timing unit: TIMFLTR5 source" - value: 9 - - name: BlankTIMFLTR6 - description: "Blanking from another timing unit: TIMFLTR6 source" - value: 10 - - name: BlankTIMFLTR7 - description: "Blanking from another timing unit: TIMFLTR7 source" - value: 11 - - name: BlankTIMFLTR8 - description: "Blanking from another timing unit: TIMFLTR8 source" - value: 12 - - name: WindowResetToCompare2 - description: Windowing from counter reset/roll-over to compare 2 - value: 13 - - name: WindowResetToCompare3 - description: Windowing from counter reset/roll-over to compare 3 - value: 14 - - name: WindowTIMWIN - description: "Windowing from another timing unit: TIMWIN source" - value: 15 + - name: Disabled + description: No filtering + value: 0 + - name: BlankResetToCompare1 + description: Blanking from counter reset/roll-over to Compare 1 + value: 1 + - name: BlankResetToCompare2 + description: Blanking from counter reset/roll-over to Compare 2 + value: 2 + - name: BlankResetToCompare3 + description: Blanking from counter reset/roll-over to Compare 3 + value: 3 + - name: BlankResetToCompare4 + description: Blanking from counter reset/roll-over to Compare 4 + value: 4 + - name: BlankTIMFLTR1 + description: 'Blanking from another timing unit: TIMFLTR1 source' + value: 5 + - name: BlankTIMFLTR2 + description: 'Blanking from another timing unit: TIMFLTR2 source' + value: 6 + - name: BlankTIMFLTR3 + description: 'Blanking from another timing unit: TIMFLTR3 source' + value: 7 + - name: BlankTIMFLTR4 + description: 'Blanking from another timing unit: TIMFLTR4 source' + value: 8 + - name: BlankTIMFLTR5 + description: 'Blanking from another timing unit: TIMFLTR5 source' + value: 9 + - name: BlankTIMFLTR6 + description: 'Blanking from another timing unit: TIMFLTR6 source' + value: 10 + - name: BlankTIMFLTR7 + description: 'Blanking from another timing unit: TIMFLTR7 source' + value: 11 + - name: BlankTIMFLTR8 + description: 'Blanking from another timing unit: TIMFLTR8 source' + value: 12 + - name: WindowResetToCompare2 + description: Windowing from counter reset/roll-over to compare 2 + value: 13 + - name: WindowResetToCompare3 + description: Windowing from counter reset/roll-over to compare 3 + value: 14 + - name: WindowTIMWIN + description: 'Windowing from another timing unit: TIMWIN source' + value: 15 enum/EVENT: bit_size: 1 variants: - - name: NoEvent - description: No compare interrupt occurred - value: 0 - - name: Event - description: Compare interrupt occurred - value: 1 + - name: NoEvent + description: No compare interrupt occurred + value: 0 + - name: Event + description: Compare interrupt occurred + value: 1 enum/FAULT: bit_size: 2 variants: - - name: Disabled - description: "No action: the output is not affected by the fault input and stays in run mode" - value: 0 - - name: SetActive - description: Output goes to active state after a fault event - value: 1 - - name: SetInactive - description: Output goes to inactive state after a fault event - value: 2 - - name: SetHighZ - description: Output goes to high-z state after a fault event - value: 3 + - name: Disabled + description: 'No action: the output is not affected by the fault input and stays in run mode' + value: 0 + - name: SetActive + description: Output goes to active state after a fault event + value: 1 + - name: SetInactive + description: Output goes to inactive state after a fault event + value: 2 + - name: SetHighZ + description: Output goes to high-z state after a fault event + value: 3 enum/FLTEN: bit_size: 1 variants: - - name: Ignored - description: Fault input ignored - value: 0 - - name: Active - description: Fault input is active and can disable HRTIM outputs - value: 1 + - name: Ignored + description: Fault input ignored + value: 0 + - name: Active + description: Fault input is active and can disable HRTIM outputs + value: 1 enum/INACTIVEEFFECT: bit_size: 1 variants: - - name: NoEffect - description: Timer event has no effect - value: 0 - - name: SetInactive - description: Timer event forces the output to its inactive state - value: 1 + - name: NoEffect + description: Timer event has no effect + value: 0 + - name: SetInactive + description: Timer event forces the output to its inactive state + value: 1 enum/IPPSTAT: bit_size: 1 variants: - - name: Output1Active - description: Protection occurred when the output 1 was active and output 2 forced inactive - value: 0 - - name: Output2Active - description: Protection occurred when the output 2 was active and output 1 forced inactive - value: 1 + - name: Output1Active + description: Protection occurred when the output 1 was active and output 2 forced inactive + value: 0 + - name: Output2Active + description: Protection occurred when the output 2 was active and output 1 forced inactive + value: 1 enum/LOCKED: bit_size: 1 variants: - - name: Unlocked - description: Bits are writeable - value: 0 - - name: Locked - description: Bits are read-only - value: 1 + - name: Unlocked + description: Bits are writeable + value: 0 + - name: Locked + description: Bits are read-only + value: 1 enum/OUTPUTSTATE: bit_size: 1 variants: - - name: Inactive - description: Output is or was inactive - value: 0 - - name: Active - description: Output is or was active - value: 1 + - name: Inactive + description: Output is or was inactive + value: 0 + - name: Active + description: Output is or was active + value: 1 enum/POL: bit_size: 1 variants: - - name: ActiveHigh - description: Positive polarity (output active high) - value: 0 - - name: ActiveLow - description: Negative polarity (output active low) - value: 1 + - name: ActiveHigh + description: Positive polarity (output active high) + value: 0 + - name: ActiveLow + description: Negative polarity (output active low) + value: 1 enum/RESETEFFECT: bit_size: 1 variants: - - name: NoEffect - description: Timer Y compare Z event has no effect - value: 0 - - name: ResetCounter - description: Timer X counter is reset upon timer Y compare Z event - value: 1 + - name: NoEffect + description: Timer Y compare Z event has no effect + value: 0 + - name: ResetCounter + description: Timer X counter is reset upon timer Y compare Z event + value: 1 enum/SDTF: bit_size: 1 variants: - - name: Positive - description: Positive deadtime on falling edge - value: 0 - - name: Negative - description: Negative deadtime on falling edge - value: 1 + - name: Positive + description: Positive deadtime on falling edge + value: 0 + - name: Negative + description: Negative deadtime on falling edge + value: 1 enum/SDTR: bit_size: 1 variants: - - name: Positive - description: Positive deadtime on rising edge - value: 0 - - name: Negative - description: Negative deadtime on rising edge - value: 1 + - name: Positive + description: Positive deadtime on rising edge + value: 0 + - name: Negative + description: Negative deadtime on rising edge + value: 1 enum/SYNCIN: bit_size: 2 variants: - - name: Disabled - description: Disabled. HRTIM is not synchronized and runs in standalone mode - value: 0 - - name: Internal - description: "Internal event: the HRTIM is synchronized with the on-chip timer" - value: 2 - - name: External - description: "External event: a positive pulse on HRTIM_SCIN input triggers the HRTIM" - value: 3 + - name: Disabled + description: Disabled. HRTIM is not synchronized and runs in standalone mode + value: 0 + - name: Internal + description: 'Internal event: the HRTIM is synchronized with the on-chip timer' + value: 2 + - name: External + description: 'External event: a positive pulse on HRTIM_SCIN input triggers the HRTIM' + value: 3 enum/SYNCOUT: bit_size: 2 variants: - - name: Disabled - description: Disabled - value: 0 - - name: PositivePulse - description: Positive pulse on SCOUT output (16x f_HRTIM clock cycles) - value: 2 - - name: NegativePulse - description: Negative pulse on SCOUT output (16x f_HRTIM clock cycles) - value: 3 + - name: Disabled + description: Disabled + value: 0 + - name: PositivePulse + description: Positive pulse on SCOUT output (16x f_HRTIM clock cycles) + value: 2 + - name: NegativePulse + description: Negative pulse on SCOUT output (16x f_HRTIM clock cycles) + value: 3 enum/SYNCRST: bit_size: 1 variants: - - name: Disabled - description: Synchronization event has no effect on Timer x - value: 0 - - name: Reset - description: Synchronization event resets Timer x - value: 1 + - name: Disabled + description: Synchronization event has no effect on Timer x + value: 0 + - name: Reset + description: Synchronization event resets Timer x + value: 1 enum/SYNCSRC: bit_size: 2 variants: - - name: MasterStart - description: Master timer Start - value: 0 - - name: MasterCompare1 - description: Master timer Compare 1 event - value: 1 - - name: TimerAStart - description: Timer A start/reset - value: 2 - - name: TimerACompare1 - description: Timer A Compare 1 event - value: 3 + - name: MasterStart + description: Master timer Start + value: 0 + - name: MasterCompare1 + description: Master timer Compare 1 event + value: 1 + - name: TimerAStart + description: Timer A start/reset + value: 2 + - name: TimerACompare1 + description: Timer A Compare 1 event + value: 3 enum/SYNCSTRT: bit_size: 1 variants: - - name: Disabled - description: Synchronization event has no effect on Timer x - value: 0 - - name: Start - description: Synchronization event starts Timer x - value: 1 + - name: Disabled + description: Synchronization event has no effect on Timer x + value: 0 + - name: Start + description: Synchronization event starts Timer x + value: 1 enum/TIMAISR_DLYPRT: bit_size: 1 variants: - - name: Inactive - description: Not in delayed idle or balanced idle mode - value: 0 - - name: Active - description: Delayed idle or balanced idle mode entry - value: 1 + - name: Inactive + description: Not in delayed idle or balanced idle mode + value: 0 + - name: Active + description: Delayed idle or balanced idle mode entry + value: 1 enum/UPDGAT: bit_size: 4 variants: - - name: Independent - description: Update occurs independently from the DMA burst transfer - value: 0 - - name: DMABurst - description: Update occurs when the DMA burst transfer is completed - value: 1 - - name: DMABurst_Update - description: Update occurs on the update event following DMA burst transfer completion - value: 2 - - name: Input1 - description: Update occurs on a rising edge of HRTIM update enable input 1 - value: 3 - - name: Input2 - description: Update occurs on a rising edge of HRTIM update enable input 2 - value: 4 - - name: Input3 - description: Update occurs on a rising edge of HRTIM update enable input 3 - value: 5 - - name: Input1_Update - description: Update occurs on the update event following a rising edge of HRTIM update enable input 1 - value: 6 - - name: Input2_Update - description: Update occurs on the update event following a rising edge of HRTIM update enable input 2 - value: 7 - - name: Input3_Update - description: Update occurs on the update event following a rising edge of HRTIM update enable input 3 - value: 8 + - name: Independent + description: Update occurs independently from the DMA burst transfer + value: 0 + - name: DMABurst + description: Update occurs when the DMA burst transfer is completed + value: 1 + - name: DMABurst_Update + description: Update occurs on the update event following DMA burst transfer completion + value: 2 + - name: Input1 + description: Update occurs on a rising edge of HRTIM update enable input 1 + value: 3 + - name: Input2 + description: Update occurs on a rising edge of HRTIM update enable input 2 + value: 4 + - name: Input3 + description: Update occurs on a rising edge of HRTIM update enable input 3 + value: 5 + - name: Input1_Update + description: Update occurs on the update event following a rising edge of HRTIM update enable input 1 + value: 6 + - name: Input2_Update + description: Update occurs on the update event following a rising edge of HRTIM update enable input 2 + value: 7 + - name: Input3_Update + description: Update occurs on the update event following a rising edge of HRTIM update enable input 3 + value: 8 diff --git a/data/registers/hrtim_v2.yaml b/data/registers/hrtim_v2.yaml index f7c2d93..c265c11 100644 --- a/data/registers/hrtim_v2.yaml +++ b/data/registers/hrtim_v2.yaml @@ -1,2344 +1,2342 @@ ---- block/HRTIM: - description: "High Resolution Timer" + description: High Resolution Timer items: - - name: MCR - description: Master Timer Control Register - byte_offset: 0 - fieldset: MCR - - name: MISR - description: Master Timer Interrupt Status Register - byte_offset: 4 - access: Read - fieldset: MISR - - name: MICR - description: Master Timer Interrupt Clear Register - byte_offset: 8 - access: Write - fieldset: MICR - - name: MDIER - description: Master Timer DMA / Interrupt Enable Register - byte_offset: 12 - fieldset: MDIER - - name: MCNTR - description: Master Timer Counter Register - byte_offset: 16 - fieldset: MCNTR - - name: MPER - description: Master Timer Period Register - byte_offset: 20 - fieldset: MPER - - name: MREP - description: Master Timer Repetition Register - byte_offset: 24 - fieldset: MREP - - name: MCMP - description: Master Timer Compare X Register - array: - offsets: - - 0 - - 8 - - 12 - - 16 - byte_offset: 28 - fieldset: MCMPX - - name: TIM - description: "High Resolution Timer: Timing Unit" - array: - len: 6 - stride: 128 - byte_offset: 128 - block: HRTIM_TIMX - - name: CR1 - description: "High Resolution Timer: Control Register 1" - byte_offset: 0x380 - fieldset: HRTIM_CR1 - - name: CR2 - description: "High Resolution Timer: Control Register 2" - byte_offset: 0x384 - fieldset: HRTIM_CR2 - - name: ISR - description: "High Resolution Timer: Interrupt Status Register" - byte_offset: 0x388 - access: Read - fieldset: HRTIM_ISR - - name: ICR - description: "High Resolution Timer: Interrupt Clear Register" - byte_offset: 0x38c - access: Write - fieldset: HRTIM_ICR - - name: IER - description: "High Resolution Timer: Interrupt Enable Register" - byte_offset: 0x390 - fieldset: HRTIM_IER - - name: OENR - description: "High Resolution Timer: Output Enable Register" - byte_offset: 0x394 - fieldset: HRTIM_OENR - - name: ODISR - description: "High Resolution Timer: Output Disable Register" - byte_offset: 0x398 - fieldset: HRTIM_ODISR - - name: ODSR - description: "High Resolution Timer: Output Disable Status Register" - byte_offset: 0x39c - fieldset: HRTIM_ODSR - - name: BMCR - description: "High Resolution Timer: Burst Mode Control Register" - byte_offset: 0x3a0 - fieldset: HRTIM_BMCR - - name: BMTRGR - description: "High Resolution Timer: Burst Mode Trigger Register" - byte_offset: 0x3a4 - fieldset: HRTIM_BMTRGR - - name: BMCMPR - description: "High Resolution Timer: Burst Mode Compare Register" - byte_offset: 0x3a8 - fieldset: HRTIM_BMCMPR - - name: BMPER - description: "High Resolution Timer: Burst Mode Period Register" - byte_offset: 0x3ac - fieldset: HRTIM_BMPER - - name: EECR1 - description: "High Resolution Timer: External Event Control Register 1" - byte_offset: 0x3b0 - fieldset: HRTIM_EECR1 - - name: EECR2 - description: "High Resolution Timer: External Event Control Register 2" - byte_offset: 0x3b4 - fieldset: HRTIM_EECR2 - - name: EECR3 - description: "High Resolution Timer: External Event Control Register 3" - byte_offset: 0x3b8 - fieldset: HRTIM_EECR3 - - name: ADC1R - description: "High Resolution Timer: ADC Trigger [1, 3] Register" - byte_offset: 0x3bc - fieldset: HRTIM_ADC1R - array: - offsets: - - 0 - - 8 - - name: ADC2R - description: "High Resolution Timer: ADC Trigger [2, 4] Register" - byte_offset: 0x3c0 - fieldset: HRTIM_ADC2R - array: - offsets: - - 0 - - 8 - - name: DLLCR - description: "High Resolution Timer: DLL Control Register" - byte_offset: 0x3cc - fieldset: HRTIM_DLLCR - - name: FLTINR1 - description: "High Resolution Timer: Fault Input Register 1" - byte_offset: 0x3d0 - fieldset: HRTIM_FLTINR1 - - name: FLTINR2 - description: "High Resolution Timer: Fault Input Register 2" - byte_offset: 0x3d0 - fieldset: HRTIM_FLTINR2 - - name: BDMUPR - description: "High Resolution Timer: Burst DMA Master timer update Register" - byte_offset: 0x3d8 - fieldset: HRTIM_BDMUPR - - name: BDTUPR - description: "High Resolution Timer: Burst DMA Timer X update Register" - byte_offset: 0x3dc - fieldset: HRTIM_BDTUPR - array: - len: 5 - stride: 4 - - name: BDMADR - description: "High Resolution Timer: Burst DMA Data Register" - byte_offset: 0x3f0 - access: Write - fieldset: HRTIM_BDMADR + - name: MCR + description: Master Timer Control Register + byte_offset: 0 + fieldset: MCR + - name: MISR + description: Master Timer Interrupt Status Register + byte_offset: 4 + access: Read + fieldset: MISR + - name: MICR + description: Master Timer Interrupt Clear Register + byte_offset: 8 + access: Write + fieldset: MICR + - name: MDIER + description: Master Timer DMA / Interrupt Enable Register + byte_offset: 12 + fieldset: MDIER + - name: MCNTR + description: Master Timer Counter Register + byte_offset: 16 + fieldset: MCNTR + - name: MPER + description: Master Timer Period Register + byte_offset: 20 + fieldset: MPER + - name: MREP + description: Master Timer Repetition Register + byte_offset: 24 + fieldset: MREP + - name: MCMP + description: Master Timer Compare X Register + array: + offsets: + - 0 + - 8 + - 12 + - 16 + byte_offset: 28 + fieldset: MCMPX + - name: TIM + description: 'High Resolution Timer: Timing Unit' + array: + len: 6 + stride: 128 + byte_offset: 128 + block: HRTIM_TIMX + - name: CR1 + description: 'High Resolution Timer: Control Register 1' + byte_offset: 896 + fieldset: HRTIM_CR1 + - name: CR2 + description: 'High Resolution Timer: Control Register 2' + byte_offset: 900 + fieldset: HRTIM_CR2 + - name: ISR + description: 'High Resolution Timer: Interrupt Status Register' + byte_offset: 904 + access: Read + fieldset: HRTIM_ISR + - name: ICR + description: 'High Resolution Timer: Interrupt Clear Register' + byte_offset: 908 + access: Write + fieldset: HRTIM_ICR + - name: IER + description: 'High Resolution Timer: Interrupt Enable Register' + byte_offset: 912 + fieldset: HRTIM_IER + - name: OENR + description: 'High Resolution Timer: Output Enable Register' + byte_offset: 916 + fieldset: HRTIM_OENR + - name: ODISR + description: 'High Resolution Timer: Output Disable Register' + byte_offset: 920 + fieldset: HRTIM_ODISR + - name: ODSR + description: 'High Resolution Timer: Output Disable Status Register' + byte_offset: 924 + fieldset: HRTIM_ODSR + - name: BMCR + description: 'High Resolution Timer: Burst Mode Control Register' + byte_offset: 928 + fieldset: HRTIM_BMCR + - name: BMTRGR + description: 'High Resolution Timer: Burst Mode Trigger Register' + byte_offset: 932 + fieldset: HRTIM_BMTRGR + - name: BMCMPR + description: 'High Resolution Timer: Burst Mode Compare Register' + byte_offset: 936 + fieldset: HRTIM_BMCMPR + - name: BMPER + description: 'High Resolution Timer: Burst Mode Period Register' + byte_offset: 940 + fieldset: HRTIM_BMPER + - name: EECR1 + description: 'High Resolution Timer: External Event Control Register 1' + byte_offset: 944 + fieldset: HRTIM_EECR1 + - name: EECR2 + description: 'High Resolution Timer: External Event Control Register 2' + byte_offset: 948 + fieldset: HRTIM_EECR2 + - name: EECR3 + description: 'High Resolution Timer: External Event Control Register 3' + byte_offset: 952 + fieldset: HRTIM_EECR3 + - name: ADC1R + description: 'High Resolution Timer: ADC Trigger [1, 3] Register' + array: + offsets: + - 0 + - 8 + byte_offset: 956 + fieldset: HRTIM_ADC1R + - name: ADC2R + description: 'High Resolution Timer: ADC Trigger [2, 4] Register' + array: + offsets: + - 0 + - 8 + byte_offset: 960 + fieldset: HRTIM_ADC2R + - name: DLLCR + description: 'High Resolution Timer: DLL Control Register' + byte_offset: 972 + fieldset: HRTIM_DLLCR + - name: FLTINR1 + description: 'High Resolution Timer: Fault Input Register 1' + byte_offset: 976 + fieldset: HRTIM_FLTINR1 + - name: FLTINR2 + description: 'High Resolution Timer: Fault Input Register 2' + byte_offset: 976 + fieldset: HRTIM_FLTINR2 + - name: BDMUPR + description: 'High Resolution Timer: Burst DMA Master timer update Register' + byte_offset: 984 + fieldset: HRTIM_BDMUPR + - name: BDTUPR + description: 'High Resolution Timer: Burst DMA Timer X update Register' + array: + len: 5 + stride: 4 + byte_offset: 988 + fieldset: HRTIM_BDTUPR + - name: BDMADR + description: 'High Resolution Timer: Burst DMA Data Register' + byte_offset: 1008 + access: Write + fieldset: HRTIM_BDMADR block/HRTIM_TIMX: - description: "High Resolution Timer: Timing Unit" + description: 'High Resolution Timer: Timing Unit' items: - - name: CR - description: Timer X Control Register - byte_offset: 0 - fieldset: TIMXCR - - name: ISR - description: Timer X Interrupt Status Register - byte_offset: 4 - access: Read - fieldset: TIMXISR - - name: ICR - description: Timer X Interrupt Clear Register - byte_offset: 8 - access: Write - fieldset: TIMXICR - - name: DIER - description: Timer X DMA / Interrupt Enable Register - byte_offset: 12 - fieldset: TIMXDIER - - name: CNT - description: Timer X Counter Register - byte_offset: 16 - fieldset: TIMXCNT - - name: PER - description: Timer X Period Register - byte_offset: 20 - fieldset: TIMXPER - - name: REP - description: Timer X Repetition Register - byte_offset: 24 - fieldset: TIMXREP - - name: CMP - description: Timer X Compare X Register - array: - offsets: - - 0 - - 8 - - 12 - - 16 - byte_offset: 28 - fieldset: TIMXCMP - - name: CMPC - description: Timer X Compare X Compound Register - array: - offsets: - - 0 - byte_offset: 32 - fieldset: TIMXCMPC - - name: CPT - description: Timer X Capture X Register - array: - len: 2 - stride: 4 - byte_offset: 48 - access: Read - fieldset: TIMXCPT - - name: DT - description: Timer X Deadtime Register - byte_offset: 56 - fieldset: TIMXDT - - name: SETR - description: Timer X Output X Set Register - array: - offsets: - - 0 - - 8 - byte_offset: 60 - fieldset: TIMXSETR - - name: RSTR - description: Timer X Output X Reset Register - array: - offsets: - - 0 - - 8 - byte_offset: 64 - fieldset: TIMXRSTR - - name: EEF - description: Timer X External Event Filtering Register 1 - array: - offsets: - - 0 - - 4 - byte_offset: 76 - fieldset: TIMXEEF - - name: RST - description: Timer X Reset Register - byte_offset: 84 - fieldset: TIMXRST - - name: CHP - description: Timer X Chopper Register - byte_offset: 88 - fieldset: TIMXCHP - - name: CCR - description: Timer X Capture X Control Register - array: - offsets: - - 0 - - 4 - byte_offset: 92 - fieldset: TIMXCCR - - name: OUTR - description: Timer X Output Register - byte_offset: 100 - fieldset: TIMXOUTR - - name: FLT - description: Timer X Fault Register - byte_offset: 104 - fieldset: TIMXFLT -fieldset/HRTIM_CR1: - description: "High Resolution Timer: Control Register 1" - fields: - - name: MUDIS - description: Master Update Disable - bit_offset: 0 - bit_size: 1 - - name: TUDIS - description: Timer X Update Disable - bit_offset: 1 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: ADUSRC - description: ADC Trigger X Update Source - bit_offset: 16 - bit_size: 3 - array: - len: 4 - stride: 2 -fieldset/HRTIM_CR2: - description: "High Resolution Timer: Control Register 2" - fields: - - name: MSWU - description: Master Timer Software Update - bit_offset: 0 - bit_size: 1 - - name: TSWU - description: Timer X Software Update - bit_offset: 1 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: MRST - description: Master Counter Software Reset - bit_offset: 8 - bit_size: 1 - - name: TRST - description: Timer X Counter Software Reset - bit_offset: 9 - bit_size: 1 - array: - len: 5 - stride: 1 -fieldset/HRTIM_ISR: - description: "High Resolution Timer: Interrupt Status Register" - fields: - - name: FLT - description: Fault X Interrupt Flag - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: SYSFLT - description: System Fault Interrupt Flag - bit_offset: 5 - bit_size: 1 - - name: DLLRDY - description: DLL Ready Interrupt Flag - bit_offset: 16 - bit_size: 1 - - name: BMPER - description: Burst Mode Period Interrupt Flag - bit_offset: 17 - bit_size: 1 -fieldset/HRTIM_ICR: - description: "High Resolution Timer: Interrupt Clear Register" - fields: - - name: FLT - description: Fault X Interrupt Flag Clear - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: SYSFLT - description: System Fault Interrupt Flag Clear - bit_offset: 5 - bit_size: 1 - - name: DLLRDY - description: DLL Ready Interrupt Flag Clear - bit_offset: 16 - bit_size: 1 - - name: BMPER - description: Burst Mode Period Interrupt Flag Clear - bit_offset: 17 - bit_size: 1 -fieldset/HRTIM_IER: - description: "High Resolution Timer: Interrupt Enable Register" - fields: - - name: FLT - description: Fault X Interrupt Flag Enable - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: SYSFLT - description: System Fault Interrupt Flag Enable - bit_offset: 5 - bit_size: 1 - - name: DLLRDY - description: DLL Ready Interrupt Flag Enable - bit_offset: 16 - bit_size: 1 - - name: BMPER - description: Burst Mode Period Interrupt Flag Enable - bit_offset: 17 - bit_size: 1 -fieldset/HRTIM_OENR: - description: "High Resolution Timer: Output Enable Register" - fields: - - name: T1OEN - description: "Timer X Output Enable" - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - 4 - - 6 - - 8 - - name: T2OEN - description: "Timer X Complementary Output Enable" - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - 4 - - 6 - - 8 -fieldset/HRTIM_ODISR: - description: "High Resolution Timer: Output Disable Register" - fields: - - name: T1ODIS - description: "Timer X Output Disable" - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - 4 - - 6 - - 8 - - name: T2ODIS - description: "Timer X Complementary Output Disable" - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - 4 - - 6 - - 8 -fieldset/HRTIM_ODSR: - description: "High Resolution Timer: Output Disable Status Register" - fields: - - name: T1ODIS - description: "Timer X Output Disable Status" - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - 4 - - 6 - - 8 - - name: T2ODIS - description: "Timer X Complementary Output Disable Status" - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - 4 - - 6 - - 8 -fieldset/HRTIM_BMCR: - description: "High Resolution Timer: Burst Mode Control Register" - fields: - - name: BME - description: Burst Mode Enable - bit_offset: 0 - bit_size: 1 - - name: BMOM - description: Burst Mode Operating Mode - bit_offset: 1 - bit_size: 1 - - name: BMCLK - description: Burst Mode Clock source - bit_offset: 2 - bit_size: 3 - - name: BMPRSC - description: Burst Mode Prescaler - bit_offset: 6 - bit_size: 3 - - name: BMPREN - description: Burst Mode Preload Enable - bit_offset: 10 - bit_size: 1 - - name: MTBM - description: Master Timer Burst Mode - bit_offset: 16 - bit_size: 1 - - name: TBM - description: Timer X Burst Mode - bit_offset: 17 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: BMSTAT - decription: Burst Mode Status - bit_offset: 31 - bit_size: 1 -fieldset/HRTIM_BMTRGR: - description: "High Resolution Timer: Burst Mode Trigger Register" - fields: - - name: SW - description: Software start - bit_offset: 0 - bit_size: 1 - - name: MSTRST - description: Master reset or roll-over - bit_offset: 1 - bit_size: 1 - - name: MSTREP - description: Master repetition - bit_offset: 2 - bit_size: 1 - - name: MSTCMP - description: Master Compare X - bit_offset: 3 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: TRST - description: Timer X reset or roll-over - bit_offset: 7 - bit_size: 1 - array: - offsets: - - 0 - - 4 - - 8 - - 12 - - 16 - - name: TREP - description: Timer X repetition - bit_offset: 8 - bit_size: 1 - array: - offsets: - - 0 - - 4 - - 8 - - 12 - - 16 - - name: TCMP1 - description: Timer X compare 1 event - bit_offset: 9 - bit_size: 1 - array: - offsets: - - 0 - - 4 - - 8 - - 12 - - 16 - - name: TCMP2 - description: Timer X compare 2 event - bit_offset: 10 - bit_size: 1 - array: - offsets: - - 0 - - 4 - - 8 - - 12 - - 16 -fieldset/HRTIM_BMCMPR: - description: "High Resolution Timer: Burst Mode Compare Register" - fields: - - name: BMCMP - description: Burst mode compare value - bit_offset: 0 - bit_size: 16 -fieldset/HRTIM_BMPER: - description: "High Resolution Timer: Burst Mode Period Register" - fields: - - name: BMPER - description: Burst mode period value - bit_offset: 0 - bit_size: 16 -fieldset/HRTIM_EECR1: - description: "High Resolution Timer: External Events Control Register 1" - fields: - - name: EESRC - description: External Event X Source - bit_offset: 0 - bit_size: 2 - array: - offsets: - - 0 - - 6 - - 12 - - 18 - - 24 - - name: EEPOL - description: External Event X Polarity - bit_offset: 2 - bit_size: 1 - array: - offsets: - - 0 - - 6 - - 12 - - 18 - - 24 - - name: EESNS - description: External Event X Sensitivity - bit_offset: 3 - bit_size: 2 - array: - offsets: - - 0 - - 6 - - 12 - - 18 - - 24 - - name: EEFAST - description: External Event X Fast Mode - bit_offset: 5 - bit_size: 2 - array: - offsets: - - 0 - - 6 - - 12 - - 18 - - 24 -fieldset/HRTIM_EECR2: - description: "High Resolution Timer: External Events Control Register 2" - fields: - - name: EESRC - description: External Event X Source - bit_offset: 0 - bit_size: 2 - array: - offsets: - - 0 - - 6 - - 12 - - 18 - - 24 - - name: EEPOL - description: External Event X Polarity - bit_offset: 2 - bit_size: 1 - array: - offsets: - - 0 - - 6 - - 12 - - 18 - - 24 - - name: EESNS - description: External Event X Sensitivity - bit_offset: 3 - bit_size: 2 - array: - offsets: - - 0 - - 6 - - 12 - - 18 - - 24 -fieldset/HRTIM_EECR3: - description: "High Resolution Timer: External Events Control Register 2" - fields: - - name: EEF - description: External Event X filter - bit_offset: 0 - bit_size: 3 - array: - offsets: - - 0 - - 6 - - 12 - - 18 - - 24 - - name: EEVSD - description: External Event Sampling Clock Division - bit_offset: 30 - bit_size: 2 + - name: CR + description: Timer X Control Register + byte_offset: 0 + fieldset: TIMXCR + - name: ISR + description: Timer X Interrupt Status Register + byte_offset: 4 + access: Read + fieldset: TIMXISR + - name: ICR + description: Timer X Interrupt Clear Register + byte_offset: 8 + access: Write + fieldset: TIMXICR + - name: DIER + description: Timer X DMA / Interrupt Enable Register + byte_offset: 12 + fieldset: TIMXDIER + - name: CNT + description: Timer X Counter Register + byte_offset: 16 + fieldset: TIMXCNT + - name: PER + description: Timer X Period Register + byte_offset: 20 + fieldset: TIMXPER + - name: REP + description: Timer X Repetition Register + byte_offset: 24 + fieldset: TIMXREP + - name: CMP + description: Timer X Compare X Register + array: + offsets: + - 0 + - 8 + - 12 + - 16 + byte_offset: 28 + fieldset: TIMXCMP + - name: CMPC + description: Timer X Compare X Compound Register + array: + offsets: + - 0 + byte_offset: 32 + fieldset: TIMXCMPC + - name: CPT + description: Timer X Capture X Register + array: + len: 2 + stride: 4 + byte_offset: 48 + access: Read + fieldset: TIMXCPT + - name: DT + description: Timer X Deadtime Register + byte_offset: 56 + fieldset: TIMXDT + - name: SETR + description: Timer X Output X Set Register + array: + offsets: + - 0 + - 8 + byte_offset: 60 + fieldset: TIMXSETR + - name: RSTR + description: Timer X Output X Reset Register + array: + offsets: + - 0 + - 8 + byte_offset: 64 + fieldset: TIMXRSTR + - name: EEF + description: Timer X External Event Filtering Register 1 + array: + offsets: + - 0 + - 4 + byte_offset: 76 + fieldset: TIMXEEF + - name: RST + description: Timer X Reset Register + byte_offset: 84 + fieldset: TIMXRST + - name: CHP + description: Timer X Chopper Register + byte_offset: 88 + fieldset: TIMXCHP + - name: CCR + description: Timer X Capture X Control Register + array: + offsets: + - 0 + - 4 + byte_offset: 92 + fieldset: TIMXCCR + - name: OUTR + description: Timer X Output Register + byte_offset: 100 + fieldset: TIMXOUTR + - name: FLT + description: Timer X Fault Register + byte_offset: 104 + fieldset: TIMXFLT fieldset/HRTIM_ADC1R: - description: "High Resolution Timer: ADC Trigger 1 Register" + description: 'High Resolution Timer: ADC Trigger 1 Register' fields: - - name: ADCMC - description: ADC trigger X on Master Compare Y - bit_offset: 0 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: ADCMPER - description: ADC trigger X on Master Period - bit_offset: 4 - bit_size: 1 - - name: ADCEEV - description: ADC trigger X on External Event Y - bit_offset: 5 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: ADCTC2 - description: ADC trigger X on Timer Y Compare 2 - bit_offset: 10 - bit_size: 1 - array: - offsets: - - 0 - - name: ADCTC3 - description: ADC trigger X on Timer Y Compare 3 - bit_offset: 11 - bit_size: 1 - array: - offsets: - - 0 - - 5 - - 10 - - 14 - - 18 - - name: ADCTC4 - description: ADC trigger X on Timer Y Compare 3 - bit_offset: 12 - bit_size: 1 - array: - offsets: - - 0 - - 5 - - 10 - - 14 - - 18 - - 8 - - name: ADCTPER - description: ADC trigger X on Timer Y Period - bit_offset: 13 - bit_size: 1 - array: - offsets: - - 0 - - 5 - - 10 - - 14 - - 18 - - name: ADCTRST - description: ADC trigger X on Timer Y Reset - bit_offset: 14 - bit_size: 1 - array: - offsets: - - 0 - - 5 - - 14 + - name: ADCMC + description: ADC trigger X on Master Compare Y + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: ADCMPER + description: ADC trigger X on Master Period + bit_offset: 4 + bit_size: 1 + - name: ADCEEV + description: ADC trigger X on External Event Y + bit_offset: 5 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: ADCTC2 + description: ADC trigger X on Timer Y Compare 2 + bit_offset: 10 + bit_size: 1 + array: + offsets: + - 0 + - name: ADCTC3 + description: ADC trigger X on Timer Y Compare 3 + bit_offset: 11 + bit_size: 1 + array: + offsets: + - 0 + - 5 + - 10 + - 14 + - 18 + - name: ADCTC4 + description: ADC trigger X on Timer Y Compare 3 + bit_offset: 12 + bit_size: 1 + array: + offsets: + - 0 + - 5 + - 10 + - 14 + - 18 + - 8 + - name: ADCTPER + description: ADC trigger X on Timer Y Period + bit_offset: 13 + bit_size: 1 + array: + offsets: + - 0 + - 5 + - 10 + - 14 + - 18 + - name: ADCTRST + description: ADC trigger X on Timer Y Reset + bit_offset: 14 + bit_size: 1 + array: + offsets: + - 0 + - 5 + - 14 fieldset/HRTIM_ADC2R: - description: "High Resolution Timer: ADC Trigger 2 Register" + description: 'High Resolution Timer: ADC Trigger 2 Register' fields: - - name: ADCMC - description: ADC trigger X on Master Compare Y - bit_offset: 0 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: ADCMPER - description: ADC trigger X on Master Period - bit_offset: 4 - bit_size: 1 - - name: ADCEEV - description: ADC trigger X on External Event Y - bit_offset: 5 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: ADCTC2 - description: ADC trigger X on Timer Y Compare 2 - bit_offset: 10 - bit_size: 1 - array: - offsets: - - 0 - - 4 - - 8 - - 13 - - 18 - - 1 - - name: ADCTC3 - description: ADC trigger X on Timer Y Compare 3 - bit_offset: 15 - bit_size: 1 - array: - offsets: - - 14 - - 0 - - name: ADCTC4 - description: ADC trigger X on Timer Y Compare 3 - bit_offset: 12 - bit_size: 1 - array: - offsets: - - 0 - - 4 - - 8 - - 13 - - 18 - - name: ADCTPER - description: ADC trigger X on Timer Y Period - bit_offset: 13 - bit_size: 1 - array: - offsets: - - 0 - - 4 - - 8 - - 13 - - 11 - - name: ADCTRST - description: ADC trigger X on Timer Y Reset - bit_offset: 22 - bit_size: 1 - array: - offsets: - - 0 - - 5 - - 9 -fieldset/HRTIM_DLLCR: - description: "High Resolution Timer: DLL Control Register" - fields: - - name: CAL - description: DLL Calibration Start - bit_offset: 0 - bit_size: 1 - - name: CALEN - description: DLL Calibration Enable - bit_offset: 1 - bit_size: 1 - - name: CALRTE - description: DLL Calibration Rate - bit_offset: 2 - bit_size: 2 -fieldset/HRTIM_FLTINR1: - description: "High Resolution Timer: Fault Input Register 1" - fields: - - name: FLTE - description: Fault X enable - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - 8 - - 16 - - 24 - - name: FLTP - description: Fault X polarity - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 8 - - 16 - - 24 - - name: FLTSRC - description: Fault X source - bit_offset: 2 - bit_size: 1 - array: - offsets: - - 0 - - 8 - - 16 - - 24 - - name: FLTF - description: Fault X filter - bit_offset: 3 - bit_size: 4 - array: - offsets: - - 0 - - 8 - - 16 - - 24 - - name: FLTLCK - description: Fault X Lock - bit_offset: 7 - bit_size: 1 - array: - offsets: - - 0 - - 8 - - 16 - - 24 -fieldset/HRTIM_FLTINR2: - description: "High Resolution Timer: Fault Input Register 2" - fields: - - name: FLTE - description: Fault X enable - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - name: FLTP - description: Fault X polarity - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - name: FLTSRC - description: Fault X source - bit_offset: 2 - bit_size: 1 - array: - offsets: - - 0 - - name: FLTF - description: Fault X filter - bit_offset: 3 - bit_size: 4 - array: - offsets: - - 0 - - name: FLTLCK - description: Fault X Lock - bit_offset: 7 - bit_size: 1 - array: - offsets: - - 0 - - name: FLTSD - description: Fault Sampling clock division - bit_offset: 24 - bit_size: 2 -fieldset/HRTIM_BDMUPR: - description: "High Resolution Timer: Burst DMA Master timer update Register" - fields: - - name: MCR - description: MCR register update enable - bit_offset: 0 - bit_size: 1 - - name: MICR - description: MICR register update enable - bit_offset: 1 - bit_size: 1 - - name: MDIER - description: MDIER register update enable - bit_offset: 2 - bit_size: 1 - - name: MCNT - description: MCNT register update enable - bit_offset: 3 - bit_size: 1 - - name: MPER - description: MPER register update enable - bit_offset: 4 - bit_size: 1 - - name: MREP - description: MREP register update enable - bit_offset: 5 - bit_size: 1 - - name: MCMP - description: MCMP register X update enable - bit_offset: 6 - bit_size: 1 - array: - len: 4 - stride: 1 -fieldset/HRTIM_BDTUPR: - description: "High Resolution Timer: Burst DMA Master timer update Register" - fields: - - name: CR - description: CR register update enable - bit_offset: 0 - bit_size: 1 - - name: ICR - description: ICR register update enable - bit_offset: 1 - bit_size: 1 - - name: DIER - description: DIER register update enable - bit_offset: 2 - bit_size: 1 - - name: CNT - description: CNT register update enable - bit_offset: 3 - bit_size: 1 - - name: PER - description: PER register update enable - bit_offset: 4 - bit_size: 1 - - name: REP - description: REP register update enable - bit_offset: 5 - bit_size: 1 - - name: CMP - description: CMP register X update enable - bit_offset: 6 - bit_size: 1 - array: - len: 4 - stride: 1 + - name: ADCMC + description: ADC trigger X on Master Compare Y + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: ADCMPER + description: ADC trigger X on Master Period + bit_offset: 4 + bit_size: 1 + - name: ADCEEV + description: ADC trigger X on External Event Y + bit_offset: 5 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: ADCTC2 + description: ADC trigger X on Timer Y Compare 2 + bit_offset: 10 + bit_size: 1 + array: + offsets: + - 0 + - 4 + - 8 + - 13 + - 18 + - 1 + - name: ADCTC4 + description: ADC trigger X on Timer Y Compare 3 + bit_offset: 12 + bit_size: 1 + array: + offsets: + - 0 + - 4 + - 8 + - 13 + - 18 + - name: ADCTPER + description: ADC trigger X on Timer Y Period + bit_offset: 13 + bit_size: 1 + array: + offsets: + - 0 + - 4 + - 8 + - 13 + - 11 + - name: ADCTC3 + description: ADC trigger X on Timer Y Compare 3 + bit_offset: 15 + bit_size: 1 + array: + offsets: + - 14 + - 0 + - name: ADCTRST + description: ADC trigger X on Timer Y Reset + bit_offset: 22 + bit_size: 1 + array: + offsets: + - 0 + - 5 + - 9 fieldset/HRTIM_BDMADR: - description: "High Resolution Timer: Burst DMA Data Register" + description: 'High Resolution Timer: Burst DMA Data Register' fields: - - name: BDMADR - description: Burst DMA Data register - bit_offset: 0 - bit_size: 31 + - name: BDMADR + description: Burst DMA Data register + bit_offset: 0 + bit_size: 31 +fieldset/HRTIM_BDMUPR: + description: 'High Resolution Timer: Burst DMA Master timer update Register' + fields: + - name: MCR + description: MCR register update enable + bit_offset: 0 + bit_size: 1 + - name: MICR + description: MICR register update enable + bit_offset: 1 + bit_size: 1 + - name: MDIER + description: MDIER register update enable + bit_offset: 2 + bit_size: 1 + - name: MCNT + description: MCNT register update enable + bit_offset: 3 + bit_size: 1 + - name: MPER + description: MPER register update enable + bit_offset: 4 + bit_size: 1 + - name: MREP + description: MREP register update enable + bit_offset: 5 + bit_size: 1 + - name: MCMP + description: MCMP register X update enable + bit_offset: 6 + bit_size: 1 + array: + len: 4 + stride: 1 +fieldset/HRTIM_BDTUPR: + description: 'High Resolution Timer: Burst DMA Master timer update Register' + fields: + - name: CR + description: CR register update enable + bit_offset: 0 + bit_size: 1 + - name: ICR + description: ICR register update enable + bit_offset: 1 + bit_size: 1 + - name: DIER + description: DIER register update enable + bit_offset: 2 + bit_size: 1 + - name: CNT + description: CNT register update enable + bit_offset: 3 + bit_size: 1 + - name: PER + description: PER register update enable + bit_offset: 4 + bit_size: 1 + - name: REP + description: REP register update enable + bit_offset: 5 + bit_size: 1 + - name: CMP + description: CMP register X update enable + bit_offset: 6 + bit_size: 1 + array: + len: 4 + stride: 1 +fieldset/HRTIM_BMCMPR: + description: 'High Resolution Timer: Burst Mode Compare Register' + fields: + - name: BMCMP + description: Burst mode compare value + bit_offset: 0 + bit_size: 16 +fieldset/HRTIM_BMCR: + description: 'High Resolution Timer: Burst Mode Control Register' + fields: + - name: BME + description: Burst Mode Enable + bit_offset: 0 + bit_size: 1 + - name: BMOM + description: Burst Mode Operating Mode + bit_offset: 1 + bit_size: 1 + - name: BMCLK + description: Burst Mode Clock source + bit_offset: 2 + bit_size: 3 + - name: BMPRSC + description: Burst Mode Prescaler + bit_offset: 6 + bit_size: 3 + - name: BMPREN + description: Burst Mode Preload Enable + bit_offset: 10 + bit_size: 1 + - name: MTBM + description: Master Timer Burst Mode + bit_offset: 16 + bit_size: 1 + - name: TBM + description: Timer X Burst Mode + bit_offset: 17 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: BMSTAT + bit_offset: 31 + bit_size: 1 +fieldset/HRTIM_BMPER: + description: 'High Resolution Timer: Burst Mode Period Register' + fields: + - name: BMPER + description: Burst mode period value + bit_offset: 0 + bit_size: 16 +fieldset/HRTIM_BMTRGR: + description: 'High Resolution Timer: Burst Mode Trigger Register' + fields: + - name: SW + description: Software start + bit_offset: 0 + bit_size: 1 + - name: MSTRST + description: Master reset or roll-over + bit_offset: 1 + bit_size: 1 + - name: MSTREP + description: Master repetition + bit_offset: 2 + bit_size: 1 + - name: MSTCMP + description: Master Compare X + bit_offset: 3 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: TRST + description: Timer X reset or roll-over + bit_offset: 7 + bit_size: 1 + array: + offsets: + - 0 + - 4 + - 8 + - 12 + - 16 + - name: TREP + description: Timer X repetition + bit_offset: 8 + bit_size: 1 + array: + offsets: + - 0 + - 4 + - 8 + - 12 + - 16 + - name: TCMP1 + description: Timer X compare 1 event + bit_offset: 9 + bit_size: 1 + array: + offsets: + - 0 + - 4 + - 8 + - 12 + - 16 + - name: TCMP2 + description: Timer X compare 2 event + bit_offset: 10 + bit_size: 1 + array: + offsets: + - 0 + - 4 + - 8 + - 12 + - 16 +fieldset/HRTIM_CR1: + description: 'High Resolution Timer: Control Register 1' + fields: + - name: MUDIS + description: Master Update Disable + bit_offset: 0 + bit_size: 1 + - name: TUDIS + description: Timer X Update Disable + bit_offset: 1 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: ADUSRC + description: ADC Trigger X Update Source + bit_offset: 16 + bit_size: 3 + array: + len: 4 + stride: 2 +fieldset/HRTIM_CR2: + description: 'High Resolution Timer: Control Register 2' + fields: + - name: MSWU + description: Master Timer Software Update + bit_offset: 0 + bit_size: 1 + - name: TSWU + description: Timer X Software Update + bit_offset: 1 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: MRST + description: Master Counter Software Reset + bit_offset: 8 + bit_size: 1 + - name: TRST + description: Timer X Counter Software Reset + bit_offset: 9 + bit_size: 1 + array: + len: 5 + stride: 1 +fieldset/HRTIM_DLLCR: + description: 'High Resolution Timer: DLL Control Register' + fields: + - name: CAL + description: DLL Calibration Start + bit_offset: 0 + bit_size: 1 + - name: CALEN + description: DLL Calibration Enable + bit_offset: 1 + bit_size: 1 + - name: CALRTE + description: DLL Calibration Rate + bit_offset: 2 + bit_size: 2 +fieldset/HRTIM_EECR1: + description: 'High Resolution Timer: External Events Control Register 1' + fields: + - name: EESRC + description: External Event X Source + bit_offset: 0 + bit_size: 2 + array: + offsets: + - 0 + - 6 + - 12 + - 18 + - 24 + - name: EEPOL + description: External Event X Polarity + bit_offset: 2 + bit_size: 1 + array: + offsets: + - 0 + - 6 + - 12 + - 18 + - 24 + - name: EESNS + description: External Event X Sensitivity + bit_offset: 3 + bit_size: 2 + array: + offsets: + - 0 + - 6 + - 12 + - 18 + - 24 + - name: EEFAST + description: External Event X Fast Mode + bit_offset: 5 + bit_size: 2 + array: + offsets: + - 0 + - 6 + - 12 + - 18 + - 24 +fieldset/HRTIM_EECR2: + description: 'High Resolution Timer: External Events Control Register 2' + fields: + - name: EESRC + description: External Event X Source + bit_offset: 0 + bit_size: 2 + array: + offsets: + - 0 + - 6 + - 12 + - 18 + - 24 + - name: EEPOL + description: External Event X Polarity + bit_offset: 2 + bit_size: 1 + array: + offsets: + - 0 + - 6 + - 12 + - 18 + - 24 + - name: EESNS + description: External Event X Sensitivity + bit_offset: 3 + bit_size: 2 + array: + offsets: + - 0 + - 6 + - 12 + - 18 + - 24 +fieldset/HRTIM_EECR3: + description: 'High Resolution Timer: External Events Control Register 2' + fields: + - name: EEF + description: External Event X filter + bit_offset: 0 + bit_size: 3 + array: + offsets: + - 0 + - 6 + - 12 + - 18 + - 24 + - name: EEVSD + description: External Event Sampling Clock Division + bit_offset: 30 + bit_size: 2 +fieldset/HRTIM_FLTINR1: + description: 'High Resolution Timer: Fault Input Register 1' + fields: + - name: FLTE + description: Fault X enable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 8 + - 16 + - 24 + - name: FLTP + description: Fault X polarity + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 8 + - 16 + - 24 + - name: FLTSRC + description: Fault X source + bit_offset: 2 + bit_size: 1 + array: + offsets: + - 0 + - 8 + - 16 + - 24 + - name: FLTF + description: Fault X filter + bit_offset: 3 + bit_size: 4 + array: + offsets: + - 0 + - 8 + - 16 + - 24 + - name: FLTLCK + description: Fault X Lock + bit_offset: 7 + bit_size: 1 + array: + offsets: + - 0 + - 8 + - 16 + - 24 +fieldset/HRTIM_FLTINR2: + description: 'High Resolution Timer: Fault Input Register 2' + fields: + - name: FLTE + description: Fault X enable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - name: FLTP + description: Fault X polarity + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - name: FLTSRC + description: Fault X source + bit_offset: 2 + bit_size: 1 + array: + offsets: + - 0 + - name: FLTF + description: Fault X filter + bit_offset: 3 + bit_size: 4 + array: + offsets: + - 0 + - name: FLTLCK + description: Fault X Lock + bit_offset: 7 + bit_size: 1 + array: + offsets: + - 0 + - name: FLTSD + description: Fault Sampling clock division + bit_offset: 24 + bit_size: 2 +fieldset/HRTIM_ICR: + description: 'High Resolution Timer: Interrupt Clear Register' + fields: + - name: FLT + description: Fault X Interrupt Flag Clear + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: SYSFLT + description: System Fault Interrupt Flag Clear + bit_offset: 5 + bit_size: 1 + - name: DLLRDY + description: DLL Ready Interrupt Flag Clear + bit_offset: 16 + bit_size: 1 + - name: BMPER + description: Burst Mode Period Interrupt Flag Clear + bit_offset: 17 + bit_size: 1 +fieldset/HRTIM_IER: + description: 'High Resolution Timer: Interrupt Enable Register' + fields: + - name: FLT + description: Fault X Interrupt Flag Enable + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: SYSFLT + description: System Fault Interrupt Flag Enable + bit_offset: 5 + bit_size: 1 + - name: DLLRDY + description: DLL Ready Interrupt Flag Enable + bit_offset: 16 + bit_size: 1 + - name: BMPER + description: Burst Mode Period Interrupt Flag Enable + bit_offset: 17 + bit_size: 1 +fieldset/HRTIM_ISR: + description: 'High Resolution Timer: Interrupt Status Register' + fields: + - name: FLT + description: Fault X Interrupt Flag + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: SYSFLT + description: System Fault Interrupt Flag + bit_offset: 5 + bit_size: 1 + - name: DLLRDY + description: DLL Ready Interrupt Flag + bit_offset: 16 + bit_size: 1 + - name: BMPER + description: Burst Mode Period Interrupt Flag + bit_offset: 17 + bit_size: 1 +fieldset/HRTIM_ODISR: + description: 'High Resolution Timer: Output Disable Register' + fields: + - name: T1ODIS + description: Timer X Output Disable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - 4 + - 6 + - 8 + - name: T2ODIS + description: Timer X Complementary Output Disable + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - 4 + - 6 + - 8 +fieldset/HRTIM_ODSR: + description: 'High Resolution Timer: Output Disable Status Register' + fields: + - name: T1ODIS + description: Timer X Output Disable Status + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - 4 + - 6 + - 8 + - name: T2ODIS + description: Timer X Complementary Output Disable Status + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - 4 + - 6 + - 8 +fieldset/HRTIM_OENR: + description: 'High Resolution Timer: Output Enable Register' + fields: + - name: T1OEN + description: Timer X Output Enable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - 4 + - 6 + - 8 + - name: T2OEN + description: Timer X Complementary Output Enable + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - 4 + - 6 + - 8 fieldset/MCMPX: description: Master Timer Compare X Register fields: - - name: MCMP - description: Master Timer Compare X value - bit_offset: 0 - bit_size: 16 + - name: MCMP + description: Master Timer Compare X value + bit_offset: 0 + bit_size: 16 fieldset/MCNTR: description: Master Timer Counter Register fields: - - name: MCNT - description: Counter value - bit_offset: 0 - bit_size: 16 + - name: MCNT + description: Counter value + bit_offset: 0 + bit_size: 16 fieldset/MCR: description: Master Timer Control Register fields: - - name: CKPSC - description: HRTIM Master Clock prescaler - bit_offset: 0 - bit_size: 3 - - name: CONT - description: Master Continuous mode - bit_offset: 3 - bit_size: 1 - - name: RETRIG - description: Master Re-triggerable mode - bit_offset: 4 - bit_size: 1 - - name: HALF - description: Half mode enable - bit_offset: 5 - bit_size: 1 - - name: SYNCIN - description: Synchronization input - bit_offset: 8 - bit_size: 2 - enum: SYNCIN - - name: SYNCRSTM - description: Synchronization Resets Master - bit_offset: 10 - bit_size: 1 - - name: SYNCSTRTM - description: Synchronization Starts Master - bit_offset: 11 - bit_size: 1 - - name: SYNCOUT - description: Synchronization output - bit_offset: 12 - bit_size: 2 - enum: SYNCOUT - - name: SYNCSRC - description: Synchronization source - bit_offset: 14 - bit_size: 2 - enum: SYNCSRC - - name: MCEN - description: Master Counter enable - bit_offset: 16 - bit_size: 1 - - name: TCEN - description: Timer X counter enable - bit_offset: 17 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: DACSYNC - description: AC Synchronization - bit_offset: 25 - bit_size: 2 - enum: DACSYNC - - name: PREEN - description: Preload enable - bit_offset: 27 - bit_size: 1 - - name: MREPU - description: Master Timer Repetition update - bit_offset: 29 - bit_size: 1 - - name: BRSTDMA - description: Burst DMA Update - bit_offset: 30 - bit_size: 2 - enum: BRSTDMA + - name: CKPSC + description: HRTIM Master Clock prescaler + bit_offset: 0 + bit_size: 3 + - name: CONT + description: Master Continuous mode + bit_offset: 3 + bit_size: 1 + - name: RETRIG + description: Master Re-triggerable mode + bit_offset: 4 + bit_size: 1 + - name: HALF + description: Half mode enable + bit_offset: 5 + bit_size: 1 + - name: SYNCIN + description: Synchronization input + bit_offset: 8 + bit_size: 2 + enum: SYNCIN + - name: SYNCRSTM + description: Synchronization Resets Master + bit_offset: 10 + bit_size: 1 + - name: SYNCSTRTM + description: Synchronization Starts Master + bit_offset: 11 + bit_size: 1 + - name: SYNCOUT + description: Synchronization output + bit_offset: 12 + bit_size: 2 + enum: SYNCOUT + - name: SYNCSRC + description: Synchronization source + bit_offset: 14 + bit_size: 2 + enum: SYNCSRC + - name: MCEN + description: Master Counter enable + bit_offset: 16 + bit_size: 1 + - name: TCEN + description: Timer X counter enable + bit_offset: 17 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: DACSYNC + description: AC Synchronization + bit_offset: 25 + bit_size: 2 + enum: DACSYNC + - name: PREEN + description: Preload enable + bit_offset: 27 + bit_size: 1 + - name: MREPU + description: Master Timer Repetition update + bit_offset: 29 + bit_size: 1 + - name: BRSTDMA + description: Burst DMA Update + bit_offset: 30 + bit_size: 2 + enum: BRSTDMA fieldset/MDIER: description: Master Timer DMA / Interrupt Enable Register fields: - - name: MCMPIE - description: Master Compare X Interrupt Enable - bit_offset: 0 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: MREPIE - description: Master Repetition Interrupt Enable - bit_offset: 4 - bit_size: 1 - - name: SYNCIE - description: Sync Input Interrupt Enable - bit_offset: 5 - bit_size: 1 - - name: MUPDIE - description: Master Update Interrupt Enable - bit_offset: 6 - bit_size: 1 - - name: MCMPDE - description: Master Compare X DMA request Enable - bit_offset: 16 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: MREPDE - description: Master Repetition DMA request Enable - bit_offset: 20 - bit_size: 1 - - name: SYNCDE - description: Sync Input DMA request Enable - bit_offset: 21 - bit_size: 1 - - name: MUPDDE - description: Master Update DMA request Enable - bit_offset: 22 - bit_size: 1 + - name: MCMPIE + description: Master Compare X Interrupt Enable + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: MREPIE + description: Master Repetition Interrupt Enable + bit_offset: 4 + bit_size: 1 + - name: SYNCIE + description: Sync Input Interrupt Enable + bit_offset: 5 + bit_size: 1 + - name: MUPDIE + description: Master Update Interrupt Enable + bit_offset: 6 + bit_size: 1 + - name: MCMPDE + description: Master Compare X DMA request Enable + bit_offset: 16 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: MREPDE + description: Master Repetition DMA request Enable + bit_offset: 20 + bit_size: 1 + - name: SYNCDE + description: Sync Input DMA request Enable + bit_offset: 21 + bit_size: 1 + - name: MUPDDE + description: Master Update DMA request Enable + bit_offset: 22 + bit_size: 1 fieldset/MICR: description: Master Timer Interrupt Clear Register fields: - - name: MCMPC - description: Master Compare X Interrupt flag clear - bit_offset: 0 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: MREPC - description: Repetition Interrupt flag clear - bit_offset: 4 - bit_size: 1 - - name: SYNCC - description: Sync Input Interrupt flag clear - bit_offset: 5 - bit_size: 1 - - name: MUPDC - description: Master update Interrupt flag clear - bit_offset: 6 - bit_size: 1 + - name: MCMPC + description: Master Compare X Interrupt flag clear + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: MREPC + description: Repetition Interrupt flag clear + bit_offset: 4 + bit_size: 1 + - name: SYNCC + description: Sync Input Interrupt flag clear + bit_offset: 5 + bit_size: 1 + - name: MUPDC + description: Master update Interrupt flag clear + bit_offset: 6 + bit_size: 1 fieldset/MISR: description: Master Timer Interrupt Status Register fields: - - name: MCMP - description: Master Compare X Interrupt Flag - bit_offset: 0 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: EVENT - - name: MREP - description: Master Repetition Interrupt Flag - bit_offset: 4 - bit_size: 1 - enum: EVENT - - name: SYNC - description: Sync Input Interrupt Flag - bit_offset: 5 - bit_size: 1 - enum: EVENT - - name: MUPD - description: Master Update Interrupt Flag - bit_offset: 6 - bit_size: 1 - enum: EVENT + - name: MCMP + description: Master Compare X Interrupt Flag + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: EVENT + - name: MREP + description: Master Repetition Interrupt Flag + bit_offset: 4 + bit_size: 1 + enum: EVENT + - name: SYNC + description: Sync Input Interrupt Flag + bit_offset: 5 + bit_size: 1 + enum: EVENT + - name: MUPD + description: Master Update Interrupt Flag + bit_offset: 6 + bit_size: 1 + enum: EVENT fieldset/MPER: description: Master Timer Period Register fields: - - name: MPER - description: Master Timer Period value - bit_offset: 0 - bit_size: 16 + - name: MPER + description: Master Timer Period value + bit_offset: 0 + bit_size: 16 fieldset/MREP: description: Master Timer Repetition Register fields: - - name: MREP - description: Master Timer Repetition counter value - bit_offset: 0 - bit_size: 8 + - name: MREP + description: Master Timer Repetition counter value + bit_offset: 0 + bit_size: 8 fieldset/TIMXCCR: description: Timerx Capture 2 Control Register fields: - - name: SWCPT - description: Software Capture - bit_offset: 0 - bit_size: 1 - enum: CAPTUREEFFECT - - name: UPDCPT - description: Update Capture - bit_offset: 1 - bit_size: 1 - enum: CAPTUREEFFECT - - name: EXEVCPT - description: External Event X Capture - bit_offset: 2 - bit_size: 1 - array: - len: 10 - stride: 1 - enum: CAPTUREEFFECT - - name: TXSET - description: Timer X output Set - bit_offset: 16 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TXRST - description: Timer X output Reset - bit_offset: 17 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TXCMP - description: Timer X Compare X - bit_offset: 18 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: CAPTUREEFFECT - - name: TYSET - description: Timer Y output Set - bit_offset: 20 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TYRST - description: Timer Y output Reset - bit_offset: 21 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TYCMP - description: Timer Y Compare X - bit_offset: 22 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: CAPTUREEFFECT - - name: TZSET - description: Timer Z output Set - bit_offset: 24 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TZRST - description: Timer Z output Reset - bit_offset: 25 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TZCMP - description: Timer Z Compare X - bit_offset: 26 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: CAPTUREEFFECT - - name: TTSET - description: Timer T output Set - bit_offset: 28 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TTRST - description: Timer T output Reset - bit_offset: 29 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TTCMP - description: Timer T Compare X - bit_offset: 30 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: CAPTUREEFFECT + - name: SWCPT + description: Software Capture + bit_offset: 0 + bit_size: 1 + enum: CAPTUREEFFECT + - name: UPDCPT + description: Update Capture + bit_offset: 1 + bit_size: 1 + enum: CAPTUREEFFECT + - name: EXEVCPT + description: External Event X Capture + bit_offset: 2 + bit_size: 1 + array: + len: 10 + stride: 1 + enum: CAPTUREEFFECT + - name: TXSET + description: Timer X output Set + bit_offset: 16 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TXRST + description: Timer X output Reset + bit_offset: 17 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TXCMP + description: Timer X Compare X + bit_offset: 18 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: CAPTUREEFFECT + - name: TYSET + description: Timer Y output Set + bit_offset: 20 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TYRST + description: Timer Y output Reset + bit_offset: 21 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TYCMP + description: Timer Y Compare X + bit_offset: 22 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: CAPTUREEFFECT + - name: TZSET + description: Timer Z output Set + bit_offset: 24 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TZRST + description: Timer Z output Reset + bit_offset: 25 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TZCMP + description: Timer Z Compare X + bit_offset: 26 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: CAPTUREEFFECT + - name: TTSET + description: Timer T output Set + bit_offset: 28 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TTRST + description: Timer T output Reset + bit_offset: 29 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TTCMP + description: Timer T Compare X + bit_offset: 30 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: CAPTUREEFFECT fieldset/TIMXCHP: description: Timerx Chopper Register fields: - - name: CARFRQ - description: Timerx carrier frequency value - bit_offset: 0 - bit_size: 4 - - name: CARDTY - description: Timerx chopper duty cycle value - bit_offset: 4 - bit_size: 3 - - name: STRTPW - description: Timerx start pulsewidth - bit_offset: 7 - bit_size: 4 + - name: CARFRQ + description: Timerx carrier frequency value + bit_offset: 0 + bit_size: 4 + - name: CARDTY + description: Timerx chopper duty cycle value + bit_offset: 4 + bit_size: 3 + - name: STRTPW + description: Timerx start pulsewidth + bit_offset: 7 + bit_size: 4 fieldset/TIMXCMP: description: Timerx Compare X Register fields: - - name: CMP - description: Timerx Compare X value - bit_offset: 0 - bit_size: 16 + - name: CMP + description: Timerx Compare X value + bit_offset: 0 + bit_size: 16 fieldset/TIMXCMPC: description: Timerx Compare X Compound Register fields: - - name: CMP - description: Timerx Compare X value - bit_offset: 0 - bit_size: 16 - - name: REP - description: Timerx Repetition value (aliased from HRTIM_REPx register) - bit_offset: 16 - bit_size: 8 + - name: CMP + description: Timerx Compare X value + bit_offset: 0 + bit_size: 16 + - name: REP + description: Timerx Repetition value (aliased from HRTIM_REPx register) + bit_offset: 16 + bit_size: 8 fieldset/TIMXCNT: description: Timerx Counter Register fields: - - name: CNT - description: Timerx Counter value - bit_offset: 0 - bit_size: 16 + - name: CNT + description: Timerx Counter value + bit_offset: 0 + bit_size: 16 fieldset/TIMXCPT: description: Timerx Capture X Register fields: - - name: CPT - description: Timerx Capture X value - bit_offset: 0 - bit_size: 16 + - name: CPT + description: Timerx Capture X value + bit_offset: 0 + bit_size: 16 fieldset/TIMXCR: description: Timerx Control Register fields: - - name: CKPSC - description: HRTIM Timer x Clock prescaler - bit_offset: 0 - bit_size: 3 - - name: CONT - description: Continuous mode - bit_offset: 3 - bit_size: 1 - - name: RETRIG - description: Re-triggerable mode - bit_offset: 4 - bit_size: 1 - - name: HALF - description: Half mode enable - bit_offset: 5 - bit_size: 1 - - name: PSHPLL - description: Push-Pull mode enable - bit_offset: 6 - bit_size: 1 - - name: SYNCRST - description: Synchronization Resets Timer X - bit_offset: 10 - bit_size: 1 - enum: SYNCRST - - name: SYNCSTRT - description: Synchronization Starts Timer X - bit_offset: 11 - bit_size: 1 - enum: SYNCSTRT - - name: DELCMP2 - description: Delayed CMP2 mode - bit_offset: 12 - bit_size: 2 - enum: DELCMP - - name: DELCMP4 - description: Delayed CMP4 mode - bit_offset: 14 - bit_size: 2 - enum: DELCMP - - name: REPU - description: Timer X Repetition update - bit_offset: 17 - bit_size: 1 - - name: RSTU - description: Timer X reset update - bit_offset: 18 - bit_size: 1 - - name: TAU - description: Timer A update - bit_offset: 19 - bit_size: 1 - - name: TBU - description: Timer B update - bit_offset: 20 - bit_size: 1 - - name: TCU - description: Timer C update - bit_offset: 21 - bit_size: 1 - - name: TDU - description: Timer D update - bit_offset: 22 - bit_size: 1 - - name: TEU - description: Timer E update - bit_offset: 23 - bit_size: 1 - - name: MSTU - description: Master Timer update - bit_offset: 24 - bit_size: 1 - - name: DACSYNC - description: AC Synchronization - bit_offset: 25 - bit_size: 2 - enum: DACSYNC - - name: PREEN - description: Preload enable - bit_offset: 27 - bit_size: 1 - - name: UPDGAT - description: Update Gating - bit_offset: 28 - bit_size: 4 - enum: UPDGAT + - name: CKPSC + description: HRTIM Timer x Clock prescaler + bit_offset: 0 + bit_size: 3 + - name: CONT + description: Continuous mode + bit_offset: 3 + bit_size: 1 + - name: RETRIG + description: Re-triggerable mode + bit_offset: 4 + bit_size: 1 + - name: HALF + description: Half mode enable + bit_offset: 5 + bit_size: 1 + - name: PSHPLL + description: Push-Pull mode enable + bit_offset: 6 + bit_size: 1 + - name: SYNCRST + description: Synchronization Resets Timer X + bit_offset: 10 + bit_size: 1 + enum: SYNCRST + - name: SYNCSTRT + description: Synchronization Starts Timer X + bit_offset: 11 + bit_size: 1 + enum: SYNCSTRT + - name: DELCMP2 + description: Delayed CMP2 mode + bit_offset: 12 + bit_size: 2 + enum: DELCMP + - name: DELCMP4 + description: Delayed CMP4 mode + bit_offset: 14 + bit_size: 2 + enum: DELCMP + - name: REPU + description: Timer X Repetition update + bit_offset: 17 + bit_size: 1 + - name: RSTU + description: Timer X reset update + bit_offset: 18 + bit_size: 1 + - name: TAU + description: Timer A update + bit_offset: 19 + bit_size: 1 + - name: TBU + description: Timer B update + bit_offset: 20 + bit_size: 1 + - name: TCU + description: Timer C update + bit_offset: 21 + bit_size: 1 + - name: TDU + description: Timer D update + bit_offset: 22 + bit_size: 1 + - name: TEU + description: Timer E update + bit_offset: 23 + bit_size: 1 + - name: MSTU + description: Master Timer update + bit_offset: 24 + bit_size: 1 + - name: DACSYNC + description: AC Synchronization + bit_offset: 25 + bit_size: 2 + enum: DACSYNC + - name: PREEN + description: Preload enable + bit_offset: 27 + bit_size: 1 + - name: UPDGAT + description: Update Gating + bit_offset: 28 + bit_size: 4 + enum: UPDGAT fieldset/TIMXDIER: description: Timerx DMA / Interrupt Enable Register fields: - - name: CMPIE - description: Compare X Interrupt Enable - bit_offset: 0 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: REPIE - description: Repetition Interrupt Enable - bit_offset: 4 - bit_size: 1 - - name: UPDIE - description: Update Interrupt Enable - bit_offset: 6 - bit_size: 1 - - name: CPTIE - description: Capture Interrupt Enable - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: SETRIE - description: Output X Set Interrupt Enable - bit_offset: 9 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - name: RSTRIE - description: Output X Reset Interrupt Enable - bit_offset: 10 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - name: RSTIE - description: Reset/roll-over Interrupt Enable - bit_offset: 13 - bit_size: 1 - - name: DLYPRTIE - description: Delayed Protection Interrupt Enable - bit_offset: 14 - bit_size: 1 - - name: CMPDE - description: Compare X DMA request Enable - bit_offset: 16 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: REPDE - description: Repetition DMA request Enable - bit_offset: 20 - bit_size: 1 - - name: UPDDE - description: Update DMA request Enable - bit_offset: 22 - bit_size: 1 - - name: CPTDE - description: Capture X DMA request Enable - bit_offset: 23 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: SETRDE - description: Output X Set DMA request Enable - bit_offset: 25 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - name: RSTRDE - description: Output X Reset DMA request Enable - bit_offset: 26 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - name: RSTDE - description: Reset/roll-over DMA request Enable - bit_offset: 29 - bit_size: 1 - - name: DLYPRTDE - description: Delayed Protection DMA request Enable - bit_offset: 30 - bit_size: 1 + - name: CMPIE + description: Compare X Interrupt Enable + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: REPIE + description: Repetition Interrupt Enable + bit_offset: 4 + bit_size: 1 + - name: UPDIE + description: Update Interrupt Enable + bit_offset: 6 + bit_size: 1 + - name: CPTIE + description: Capture Interrupt Enable + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: SETRIE + description: Output X Set Interrupt Enable + bit_offset: 9 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - name: RSTRIE + description: Output X Reset Interrupt Enable + bit_offset: 10 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - name: RSTIE + description: Reset/roll-over Interrupt Enable + bit_offset: 13 + bit_size: 1 + - name: DLYPRTIE + description: Delayed Protection Interrupt Enable + bit_offset: 14 + bit_size: 1 + - name: CMPDE + description: Compare X DMA request Enable + bit_offset: 16 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: REPDE + description: Repetition DMA request Enable + bit_offset: 20 + bit_size: 1 + - name: UPDDE + description: Update DMA request Enable + bit_offset: 22 + bit_size: 1 + - name: CPTDE + description: Capture X DMA request Enable + bit_offset: 23 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: SETRDE + description: Output X Set DMA request Enable + bit_offset: 25 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - name: RSTRDE + description: Output X Reset DMA request Enable + bit_offset: 26 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - name: RSTDE + description: Reset/roll-over DMA request Enable + bit_offset: 29 + bit_size: 1 + - name: DLYPRTDE + description: Delayed Protection DMA request Enable + bit_offset: 30 + bit_size: 1 fieldset/TIMXDT: description: Timerx Deadtime Register fields: - - name: DTR - description: Deadtime Rising value - bit_offset: 0 - bit_size: 9 - - name: SDTR - description: Sign Deadtime Rising value - bit_offset: 9 - bit_size: 1 - enum: SDTR - - name: DTPRSC - description: Deadtime Prescaler - bit_offset: 10 - bit_size: 3 - - name: DTRSLK - description: Deadtime Rising Sign Lock - bit_offset: 14 - bit_size: 1 - enum: LOCKED - - name: DTRLK - description: Deadtime Rising Lock - bit_offset: 15 - bit_size: 1 - enum: LOCKED - - name: DTF - description: Deadtime Falling value - bit_offset: 16 - bit_size: 9 - - name: SDTF - description: Sign Deadtime Falling value - bit_offset: 25 - bit_size: 1 - enum: SDTF - - name: DTFSLK - description: Deadtime Falling Sign Lock - bit_offset: 30 - bit_size: 1 - enum: LOCKED - - name: DTFLK - description: Deadtime Falling Lock - bit_offset: 31 - bit_size: 1 - enum: LOCKED + - name: DTR + description: Deadtime Rising value + bit_offset: 0 + bit_size: 9 + - name: SDTR + description: Sign Deadtime Rising value + bit_offset: 9 + bit_size: 1 + enum: SDTR + - name: DTPRSC + description: Deadtime Prescaler + bit_offset: 10 + bit_size: 3 + - name: DTRSLK + description: Deadtime Rising Sign Lock + bit_offset: 14 + bit_size: 1 + enum: LOCKED + - name: DTRLK + description: Deadtime Rising Lock + bit_offset: 15 + bit_size: 1 + enum: LOCKED + - name: DTF + description: Deadtime Falling value + bit_offset: 16 + bit_size: 9 + - name: SDTF + description: Sign Deadtime Falling value + bit_offset: 25 + bit_size: 1 + enum: SDTF + - name: DTFSLK + description: Deadtime Falling Sign Lock + bit_offset: 30 + bit_size: 1 + enum: LOCKED + - name: DTFLK + description: Deadtime Falling Lock + bit_offset: 31 + bit_size: 1 + enum: LOCKED fieldset/TIMXEEF: description: Timer X External Event Filtering Register fields: - - name: LTCH - description: External Event X latch - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 6 - - name: FLTR - description: External Event X filter - bit_offset: 1 - bit_size: 4 - array: - len: 5 - stride: 6 - enum: EEFLTR + - name: LTCH + description: External Event X latch + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 6 + - name: FLTR + description: External Event X filter + bit_offset: 1 + bit_size: 4 + array: + len: 5 + stride: 6 + enum: EEFLTR fieldset/TIMXFLT: description: Timerx Fault Register fields: - - name: FLTEN - description: Fault X enable - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 1 - enum: FLTEN - - name: FLTLCK - description: Fault sources Lock - bit_offset: 31 - bit_size: 1 - enum: LOCKED + - name: FLTEN + description: Fault X enable + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + enum: FLTEN + - name: FLTLCK + description: Fault sources Lock + bit_offset: 31 + bit_size: 1 + enum: LOCKED fieldset/TIMXICR: description: Timerx Interrupt Clear Register fields: - - name: CMPC - description: Compare X Interrupt flag Clear - bit_offset: 0 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: REPC - description: Repetition Interrupt flag Clear - bit_offset: 4 - bit_size: 1 - - name: UPDC - description: Update Interrupt flag Clear - bit_offset: 6 - bit_size: 1 - - name: CPTC - description: Capture X Interrupt flag Clear - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: SETRC - description: Output X Set flag Clear - bit_offset: 9 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - name: RSTRC - description: Output X Reset flag Clear - bit_offset: 10 - bit_size: 1 - array: - offsets: - - 0 - - 2 - - name: RSTC - description: Reset Interrupt flag Clear - bit_offset: 13 - bit_size: 1 - - name: DLYPRTC - description: Delayed Protection Flag Clear - bit_offset: 14 - bit_size: 1 + - name: CMPC + description: Compare X Interrupt flag Clear + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: REPC + description: Repetition Interrupt flag Clear + bit_offset: 4 + bit_size: 1 + - name: UPDC + description: Update Interrupt flag Clear + bit_offset: 6 + bit_size: 1 + - name: CPTC + description: Capture X Interrupt flag Clear + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: SETRC + description: Output X Set flag Clear + bit_offset: 9 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - name: RSTRC + description: Output X Reset flag Clear + bit_offset: 10 + bit_size: 1 + array: + offsets: + - 0 + - 2 + - name: RSTC + description: Reset Interrupt flag Clear + bit_offset: 13 + bit_size: 1 + - name: DLYPRTC + description: Delayed Protection Flag Clear + bit_offset: 14 + bit_size: 1 fieldset/TIMXISR: description: Timerx Interrupt Status Register fields: - - name: CMP - description: Compare X Interrupt Flag - bit_offset: 0 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: EVENT - - name: REP - description: Repetition Interrupt Flag - bit_offset: 4 - bit_size: 1 - enum: EVENT - - name: UPD - description: Update Interrupt Flag - bit_offset: 6 - bit_size: 1 - enum: EVENT - - name: CPT - description: Capture X Interrupt Flag - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: EVENT - - name: SETR - description: Output X Set Interrupt Flag - bit_offset: 9 - bit_size: 1 - array: - offsets: - - 0 - - 2 - enum: EVENT - - name: RSTR - description: Output X Reset Interrupt Flag - bit_offset: 10 - bit_size: 1 - array: - offsets: - - 0 - - 2 - enum: EVENT - - name: RST - description: Reset Interrupt Flag - bit_offset: 13 - bit_size: 1 - enum: EVENT - - name: DLYPRT - description: Delayed Protection Flag - bit_offset: 14 - bit_size: 1 - enum: TIMAISR_DLYPRT - - name: CPPSTAT - description: Current Push Pull Status - bit_offset: 16 - bit_size: 1 - enum: CPPSTAT - - name: IPPSTAT - description: Idle Push Pull Status - bit_offset: 17 - bit_size: 1 - enum: IPPSTAT - - name: OSTAT - description: Output X State - bit_offset: 18 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: OUTPUTSTATE - - name: OCPY - description: Output X Copy - bit_offset: 20 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: OUTPUTSTATE + - name: CMP + description: Compare X Interrupt Flag + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: EVENT + - name: REP + description: Repetition Interrupt Flag + bit_offset: 4 + bit_size: 1 + enum: EVENT + - name: UPD + description: Update Interrupt Flag + bit_offset: 6 + bit_size: 1 + enum: EVENT + - name: CPT + description: Capture X Interrupt Flag + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: EVENT + - name: SETR + description: Output X Set Interrupt Flag + bit_offset: 9 + bit_size: 1 + array: + offsets: + - 0 + - 2 + enum: EVENT + - name: RSTR + description: Output X Reset Interrupt Flag + bit_offset: 10 + bit_size: 1 + array: + offsets: + - 0 + - 2 + enum: EVENT + - name: RST + description: Reset Interrupt Flag + bit_offset: 13 + bit_size: 1 + enum: EVENT + - name: DLYPRT + description: Delayed Protection Flag + bit_offset: 14 + bit_size: 1 + enum: TIMAISR_DLYPRT + - name: CPPSTAT + description: Current Push Pull Status + bit_offset: 16 + bit_size: 1 + enum: CPPSTAT + - name: IPPSTAT + description: Idle Push Pull Status + bit_offset: 17 + bit_size: 1 + enum: IPPSTAT + - name: OSTAT + description: Output X State + bit_offset: 18 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: OUTPUTSTATE + - name: OCPY + description: Output X Copy + bit_offset: 20 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: OUTPUTSTATE fieldset/TIMXOUTR: description: Timerx Output Register fields: - - name: POL - description: Output 1 polarity - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 16 - enum: POL - - name: IDLEM - description: Output X Idle mode - bit_offset: 2 - bit_size: 1 - array: - offsets: - - 0 - - 16 - - name: IDLES - description: Output X Idle State - bit_offset: 3 - bit_size: 1 - array: - offsets: - - 0 - - 16 - - name: FAULTX - description: Output X Fault state - bit_offset: 4 - bit_size: 2 - array: - offsets: - - 0 - - 16 - enum: FAULT - - name: CHP - description: Output X Chopper enable - bit_offset: 6 - bit_size: 1 - array: - offsets: - - 0 - - 16 - - name: DIDL - description: Output X Deadtime upon burst mode Idle entry - bit_offset: 7 - bit_size: 1 - array: - offsets: - - 0 - - 16 - - name: DTEN - description: Deadtime enable - bit_offset: 8 - bit_size: 1 - - name: DLYPRTEN - description: Delayed Protection Enable - bit_offset: 9 - bit_size: 1 - - name: DLYPRT - description: Delayed Protection - bit_offset: 10 - bit_size: 3 - enum: DLYPRT + - name: POL + description: Output 1 polarity + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 16 + enum: POL + - name: IDLEM + description: Output X Idle mode + bit_offset: 2 + bit_size: 1 + array: + offsets: + - 0 + - 16 + - name: IDLES + description: Output X Idle State + bit_offset: 3 + bit_size: 1 + array: + offsets: + - 0 + - 16 + - name: FAULTX + description: Output X Fault state + bit_offset: 4 + bit_size: 2 + array: + offsets: + - 0 + - 16 + enum: FAULT + - name: CHP + description: Output X Chopper enable + bit_offset: 6 + bit_size: 1 + array: + offsets: + - 0 + - 16 + - name: DIDL + description: Output X Deadtime upon burst mode Idle entry + bit_offset: 7 + bit_size: 1 + array: + offsets: + - 0 + - 16 + - name: DTEN + description: Deadtime enable + bit_offset: 8 + bit_size: 1 + - name: DLYPRTEN + description: Delayed Protection Enable + bit_offset: 9 + bit_size: 1 + - name: DLYPRT + description: Delayed Protection + bit_offset: 10 + bit_size: 3 + enum: DLYPRT fieldset/TIMXPER: description: Timerx Period Register fields: - - name: PER - description: Timerx Period value - bit_offset: 0 - bit_size: 16 + - name: PER + description: Timerx Period value + bit_offset: 0 + bit_size: 16 fieldset/TIMXREP: description: Timerx Repetition Register fields: - - name: REP - description: Timerx Repetition counter value - bit_offset: 0 - bit_size: 8 + - name: REP + description: Timerx Repetition counter value + bit_offset: 0 + bit_size: 8 fieldset/TIMXRST: description: Timerx Reset Register fields: - - name: UPDT - description: Timer X Update reset - bit_offset: 1 - bit_size: 1 - enum: RESETEFFECT - - name: CMP - description: Timer X compare X reset - bit_offset: 2 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: RESETEFFECT - - name: MSTPER - description: Master timer Period - bit_offset: 4 - bit_size: 1 - enum: RESETEFFECT - - name: MSTCMP - description: Master compare X - bit_offset: 5 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: RESETEFFECT - - name: EXTEVNT - description: External Event X - bit_offset: 9 - bit_size: 1 - array: - len: 10 - stride: 1 - enum: RESETEFFECT - - name: TCMP1 - description: Timer X compare 1 event - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 19 - - 22 - - 25 - - 28 - - 0 - enum: RESETEFFECT - - name: TCMP2 - description: Timer X compare 2 event - bit_offset: 20 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 6 - - 9 - - 11 - enum: RESETEFFECT - - name: TCMP4 - description: Timer X compare 4 event - bit_offset: 21 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 6 - - 9 - enum: RESETEFFECT + - name: TCMP1 + description: Timer X compare 1 event + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 19 + - 22 + - 25 + - 28 + - 0 + enum: RESETEFFECT + - name: UPDT + description: Timer X Update reset + bit_offset: 1 + bit_size: 1 + enum: RESETEFFECT + - name: CMP + description: Timer X compare X reset + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: RESETEFFECT + - name: MSTPER + description: Master timer Period + bit_offset: 4 + bit_size: 1 + enum: RESETEFFECT + - name: MSTCMP + description: Master compare X + bit_offset: 5 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: RESETEFFECT + - name: EXTEVNT + description: External Event X + bit_offset: 9 + bit_size: 1 + array: + len: 10 + stride: 1 + enum: RESETEFFECT + - name: TCMP2 + description: Timer X compare 2 event + bit_offset: 20 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 6 + - 9 + - 11 + enum: RESETEFFECT + - name: TCMP4 + description: Timer X compare 4 event + bit_offset: 21 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 6 + - 9 + enum: RESETEFFECT fieldset/TIMXRSTR: description: Timerx OutputX Reset Register fields: - - name: SRT - description: Software Reset trigger - bit_offset: 0 - bit_size: 1 - enum: INACTIVEEFFECT - - name: RESYNC - description: Timer X resynchronizaton - bit_offset: 1 - bit_size: 1 - enum: INACTIVEEFFECT - - name: PER - description: Timer X Period - bit_offset: 2 - bit_size: 1 - enum: INACTIVEEFFECT - - name: CMP - description: Timer X compare X - bit_offset: 3 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: INACTIVEEFFECT - - name: MSTPER - description: Master Period - bit_offset: 7 - bit_size: 1 - enum: INACTIVEEFFECT - - name: MSTCMP - description: Master Compare X - bit_offset: 8 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: INACTIVEEFFECT - - name: TIMEVNT - description: Timer Event X - bit_offset: 12 - bit_size: 1 - array: - len: 9 - stride: 1 - enum: INACTIVEEFFECT - - name: EXTEVNT - description: External Event X - bit_offset: 21 - bit_size: 1 - array: - len: 10 - stride: 1 - enum: INACTIVEEFFECT - - name: UPDATE - description: Registers update (transfer preload to active) - bit_offset: 31 - bit_size: 1 - enum: INACTIVEEFFECT + - name: SRT + description: Software Reset trigger + bit_offset: 0 + bit_size: 1 + enum: INACTIVEEFFECT + - name: RESYNC + description: Timer X resynchronizaton + bit_offset: 1 + bit_size: 1 + enum: INACTIVEEFFECT + - name: PER + description: Timer X Period + bit_offset: 2 + bit_size: 1 + enum: INACTIVEEFFECT + - name: CMP + description: Timer X compare X + bit_offset: 3 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: INACTIVEEFFECT + - name: MSTPER + description: Master Period + bit_offset: 7 + bit_size: 1 + enum: INACTIVEEFFECT + - name: MSTCMP + description: Master Compare X + bit_offset: 8 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: INACTIVEEFFECT + - name: TIMEVNT + description: Timer Event X + bit_offset: 12 + bit_size: 1 + array: + len: 9 + stride: 1 + enum: INACTIVEEFFECT + - name: EXTEVNT + description: External Event X + bit_offset: 21 + bit_size: 1 + array: + len: 10 + stride: 1 + enum: INACTIVEEFFECT + - name: UPDATE + description: Registers update (transfer preload to active) + bit_offset: 31 + bit_size: 1 + enum: INACTIVEEFFECT fieldset/TIMXSETR: description: Timerx OutputX Set Register fields: - - name: SST - description: Software Set trigger - bit_offset: 0 - bit_size: 1 - enum: ACTIVEEFFECT - - name: RESYNC - description: Timer X resynchronizaton - bit_offset: 1 - bit_size: 1 - enum: ACTIVEEFFECT - - name: PER - description: Timer X Period - bit_offset: 2 - bit_size: 1 - enum: ACTIVEEFFECT - - name: CMP - description: Timer X compare X - bit_offset: 3 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: ACTIVEEFFECT - - name: MSTPER - description: Master Period - bit_offset: 7 - bit_size: 1 - enum: ACTIVEEFFECT - - name: MSTCMPX - description: Master Compare X - bit_offset: 8 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: ACTIVEEFFECT - - name: TIMEVNT - description: Timer Event X - bit_offset: 12 - bit_size: 1 - array: - len: 9 - stride: 1 - enum: ACTIVEEFFECT - - name: EXTEVNT - description: External Event X - bit_offset: 21 - bit_size: 1 - array: - len: 10 - stride: 1 - enum: ACTIVEEFFECT - - name: UPDATE - description: Registers update (transfer preload to active) - bit_offset: 31 - bit_size: 1 - enum: ACTIVEEFFECT + - name: SST + description: Software Set trigger + bit_offset: 0 + bit_size: 1 + enum: ACTIVEEFFECT + - name: RESYNC + description: Timer X resynchronizaton + bit_offset: 1 + bit_size: 1 + enum: ACTIVEEFFECT + - name: PER + description: Timer X Period + bit_offset: 2 + bit_size: 1 + enum: ACTIVEEFFECT + - name: CMP + description: Timer X compare X + bit_offset: 3 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: ACTIVEEFFECT + - name: MSTPER + description: Master Period + bit_offset: 7 + bit_size: 1 + enum: ACTIVEEFFECT + - name: MSTCMPX + description: Master Compare X + bit_offset: 8 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: ACTIVEEFFECT + - name: TIMEVNT + description: Timer Event X + bit_offset: 12 + bit_size: 1 + array: + len: 9 + stride: 1 + enum: ACTIVEEFFECT + - name: EXTEVNT + description: External Event X + bit_offset: 21 + bit_size: 1 + array: + len: 10 + stride: 1 + enum: ACTIVEEFFECT + - name: UPDATE + description: Registers update (transfer preload to active) + bit_offset: 31 + bit_size: 1 + enum: ACTIVEEFFECT enum/ACTIVEEFFECT: bit_size: 1 variants: - - name: NoEffect - description: Timer event has no effect - value: 0 - - name: SetActive - description: Timer event forces the output to its active state - value: 1 + - name: NoEffect + description: Timer event has no effect + value: 0 + - name: SetActive + description: Timer event forces the output to its active state + value: 1 enum/BRSTDMA: bit_size: 2 variants: - - name: Independent - description: Update done independently from the DMA burst transfer completion - value: 0 - - name: Completion - description: Update done when the DMA burst transfer is completed - value: 1 - - name: Rollover - description: Update done on master timer roll-over following a DMA burst transfer completion - value: 2 + - name: Independent + description: Update done independently from the DMA burst transfer completion + value: 0 + - name: Completion + description: Update done when the DMA burst transfer is completed + value: 1 + - name: Rollover + description: Update done on master timer roll-over following a DMA burst transfer completion + value: 2 enum/CAPTUREEFFECT: bit_size: 1 variants: - - name: NoEffect - description: Timer event has no effect - value: 0 - - name: TriggerCapture - description: Timer event triggers capture - value: 1 + - name: NoEffect + description: Timer event has no effect + value: 0 + - name: TriggerCapture + description: Timer event triggers capture + value: 1 enum/CPPSTAT: bit_size: 1 variants: - - name: Output1Active - description: Signal applied on output 1 and output 2 forced inactive - value: 0 - - name: Output2Active - description: Signal applied on output 2 and output 1 forced inactive - value: 1 + - name: Output1Active + description: Signal applied on output 1 and output 2 forced inactive + value: 0 + - name: Output2Active + description: Signal applied on output 2 and output 1 forced inactive + value: 1 enum/DACSYNC: bit_size: 2 variants: - - name: Disabled - description: No DAC trigger generated - value: 0 - - name: DACSync1 - description: Trigger generated on DACSync1 - value: 1 - - name: DACSync2 - description: Trigger generated on DACSync2 - value: 2 - - name: DACSync3 - description: Trigger generated on DACSync3 - value: 3 + - name: Disabled + description: No DAC trigger generated + value: 0 + - name: DACSync1 + description: Trigger generated on DACSync1 + value: 1 + - name: DACSync2 + description: Trigger generated on DACSync2 + value: 2 + - name: DACSync3 + description: Trigger generated on DACSync3 + value: 3 enum/DELCMP: bit_size: 2 variants: - - name: Standard - description: CMP register is always active (standard compare mode) - value: 0 - - name: Capture1 - description: CMP is recomputed and is active following a capture 1 event - value: 1 - - name: CaptureX_Compare1 - description: CMP is recomputed and is active following a capture 1 event or a Compare 1 match - value: 2 - - name: CaptureX_Compare3 - description: CMP is recomputed and is active following a capture 1 event or a Compare 3 match - value: 3 + - name: Standard + description: CMP register is always active (standard compare mode) + value: 0 + - name: Capture1 + description: CMP is recomputed and is active following a capture 1 event + value: 1 + - name: CaptureX_Compare1 + description: CMP is recomputed and is active following a capture 1 event or a Compare 1 match + value: 2 + - name: CaptureX_Compare3 + description: CMP is recomputed and is active following a capture 1 event or a Compare 3 match + value: 3 enum/DLYPRT: bit_size: 3 variants: - - name: Output1_EE6 - description: Output 1 delayed idle on external event 6 - value: 0 - - name: Output2_EE6 - description: Output 2 delayed idle on external event 6 - value: 1 - - name: Output1_2_EE6 - description: Output 1 and 2 delayed idle on external event 6 - value: 2 - - name: Balanced_EE6 - description: Balanced idle on external event 6 - value: 3 - - name: Output1_EE7 - description: Output 1 delayed idle on external event 7 - value: 4 - - name: Output2_EE7 - description: Output 2 delayed idle on external event 7 - value: 5 - - name: Output1_2_EE7 - description: Output 1 and 2 delayed idle on external event 7 - value: 6 - - name: Balanced_EE7 - description: Balanced idle on external event 7 - value: 7 + - name: Output1_EE6 + description: Output 1 delayed idle on external event 6 + value: 0 + - name: Output2_EE6 + description: Output 2 delayed idle on external event 6 + value: 1 + - name: Output1_2_EE6 + description: Output 1 and 2 delayed idle on external event 6 + value: 2 + - name: Balanced_EE6 + description: Balanced idle on external event 6 + value: 3 + - name: Output1_EE7 + description: Output 1 delayed idle on external event 7 + value: 4 + - name: Output2_EE7 + description: Output 2 delayed idle on external event 7 + value: 5 + - name: Output1_2_EE7 + description: Output 1 and 2 delayed idle on external event 7 + value: 6 + - name: Balanced_EE7 + description: Balanced idle on external event 7 + value: 7 enum/EEFLTR: bit_size: 4 variants: - - name: Disabled - description: No filtering - value: 0 - - name: BlankResetToCompare1 - description: Blanking from counter reset/roll-over to Compare 1 - value: 1 - - name: BlankResetToCompare2 - description: Blanking from counter reset/roll-over to Compare 2 - value: 2 - - name: BlankResetToCompare3 - description: Blanking from counter reset/roll-over to Compare 3 - value: 3 - - name: BlankResetToCompare4 - description: Blanking from counter reset/roll-over to Compare 4 - value: 4 - - name: BlankTIMFLTR1 - description: "Blanking from another timing unit: TIMFLTR1 source" - value: 5 - - name: BlankTIMFLTR2 - description: "Blanking from another timing unit: TIMFLTR2 source" - value: 6 - - name: BlankTIMFLTR3 - description: "Blanking from another timing unit: TIMFLTR3 source" - value: 7 - - name: BlankTIMFLTR4 - description: "Blanking from another timing unit: TIMFLTR4 source" - value: 8 - - name: BlankTIMFLTR5 - description: "Blanking from another timing unit: TIMFLTR5 source" - value: 9 - - name: BlankTIMFLTR6 - description: "Blanking from another timing unit: TIMFLTR6 source" - value: 10 - - name: BlankTIMFLTR7 - description: "Blanking from another timing unit: TIMFLTR7 source" - value: 11 - - name: BlankTIMFLTR8 - description: "Blanking from another timing unit: TIMFLTR8 source" - value: 12 - - name: WindowResetToCompare2 - description: Windowing from counter reset/roll-over to compare 2 - value: 13 - - name: WindowResetToCompare3 - description: Windowing from counter reset/roll-over to compare 3 - value: 14 - - name: WindowTIMWIN - description: "Windowing from another timing unit: TIMWIN source" - value: 15 + - name: Disabled + description: No filtering + value: 0 + - name: BlankResetToCompare1 + description: Blanking from counter reset/roll-over to Compare 1 + value: 1 + - name: BlankResetToCompare2 + description: Blanking from counter reset/roll-over to Compare 2 + value: 2 + - name: BlankResetToCompare3 + description: Blanking from counter reset/roll-over to Compare 3 + value: 3 + - name: BlankResetToCompare4 + description: Blanking from counter reset/roll-over to Compare 4 + value: 4 + - name: BlankTIMFLTR1 + description: 'Blanking from another timing unit: TIMFLTR1 source' + value: 5 + - name: BlankTIMFLTR2 + description: 'Blanking from another timing unit: TIMFLTR2 source' + value: 6 + - name: BlankTIMFLTR3 + description: 'Blanking from another timing unit: TIMFLTR3 source' + value: 7 + - name: BlankTIMFLTR4 + description: 'Blanking from another timing unit: TIMFLTR4 source' + value: 8 + - name: BlankTIMFLTR5 + description: 'Blanking from another timing unit: TIMFLTR5 source' + value: 9 + - name: BlankTIMFLTR6 + description: 'Blanking from another timing unit: TIMFLTR6 source' + value: 10 + - name: BlankTIMFLTR7 + description: 'Blanking from another timing unit: TIMFLTR7 source' + value: 11 + - name: BlankTIMFLTR8 + description: 'Blanking from another timing unit: TIMFLTR8 source' + value: 12 + - name: WindowResetToCompare2 + description: Windowing from counter reset/roll-over to compare 2 + value: 13 + - name: WindowResetToCompare3 + description: Windowing from counter reset/roll-over to compare 3 + value: 14 + - name: WindowTIMWIN + description: 'Windowing from another timing unit: TIMWIN source' + value: 15 enum/EVENT: bit_size: 1 variants: - - name: NoEvent - description: No compare interrupt occurred - value: 0 - - name: Event - description: Compare interrupt occurred - value: 1 + - name: NoEvent + description: No compare interrupt occurred + value: 0 + - name: Event + description: Compare interrupt occurred + value: 1 enum/FAULT: bit_size: 2 variants: - - name: Disabled - description: "No action: the output is not affected by the fault input and stays in run mode" - value: 0 - - name: SetActive - description: Output goes to active state after a fault event - value: 1 - - name: SetInactive - description: Output goes to inactive state after a fault event - value: 2 - - name: SetHighZ - description: Output goes to high-z state after a fault event - value: 3 + - name: Disabled + description: 'No action: the output is not affected by the fault input and stays in run mode' + value: 0 + - name: SetActive + description: Output goes to active state after a fault event + value: 1 + - name: SetInactive + description: Output goes to inactive state after a fault event + value: 2 + - name: SetHighZ + description: Output goes to high-z state after a fault event + value: 3 enum/FLTEN: bit_size: 1 variants: - - name: Ignored - description: Fault input ignored - value: 0 - - name: Active - description: Fault input is active and can disable HRTIM outputs - value: 1 + - name: Ignored + description: Fault input ignored + value: 0 + - name: Active + description: Fault input is active and can disable HRTIM outputs + value: 1 enum/INACTIVEEFFECT: bit_size: 1 variants: - - name: NoEffect - description: Timer event has no effect - value: 0 - - name: SetInactive - description: Timer event forces the output to its inactive state - value: 1 + - name: NoEffect + description: Timer event has no effect + value: 0 + - name: SetInactive + description: Timer event forces the output to its inactive state + value: 1 enum/IPPSTAT: bit_size: 1 variants: - - name: Output1Active - description: Protection occurred when the output 1 was active and output 2 forced inactive - value: 0 - - name: Output2Active - description: Protection occurred when the output 2 was active and output 1 forced inactive - value: 1 + - name: Output1Active + description: Protection occurred when the output 1 was active and output 2 forced inactive + value: 0 + - name: Output2Active + description: Protection occurred when the output 2 was active and output 1 forced inactive + value: 1 enum/LOCKED: bit_size: 1 variants: - - name: Unlocked - description: Bits are writeable - value: 0 - - name: Locked - description: Bits are read-only - value: 1 + - name: Unlocked + description: Bits are writeable + value: 0 + - name: Locked + description: Bits are read-only + value: 1 enum/OUTPUTSTATE: bit_size: 1 variants: - - name: Inactive - description: Output is or was inactive - value: 0 - - name: Active - description: Output is or was active - value: 1 + - name: Inactive + description: Output is or was inactive + value: 0 + - name: Active + description: Output is or was active + value: 1 enum/POL: bit_size: 1 variants: - - name: ActiveHigh - description: Positive polarity (output active high) - value: 0 - - name: ActiveLow - description: Negative polarity (output active low) - value: 1 + - name: ActiveHigh + description: Positive polarity (output active high) + value: 0 + - name: ActiveLow + description: Negative polarity (output active low) + value: 1 enum/RESETEFFECT: bit_size: 1 variants: - - name: NoEffect - description: Timer Y compare Z event has no effect - value: 0 - - name: ResetCounter - description: Timer X counter is reset upon timer Y compare Z event - value: 1 + - name: NoEffect + description: Timer Y compare Z event has no effect + value: 0 + - name: ResetCounter + description: Timer X counter is reset upon timer Y compare Z event + value: 1 enum/SDTF: bit_size: 1 variants: - - name: Positive - description: Positive deadtime on falling edge - value: 0 - - name: Negative - description: Negative deadtime on falling edge - value: 1 + - name: Positive + description: Positive deadtime on falling edge + value: 0 + - name: Negative + description: Negative deadtime on falling edge + value: 1 enum/SDTR: bit_size: 1 variants: - - name: Positive - description: Positive deadtime on rising edge - value: 0 - - name: Negative - description: Negative deadtime on rising edge - value: 1 + - name: Positive + description: Positive deadtime on rising edge + value: 0 + - name: Negative + description: Negative deadtime on rising edge + value: 1 enum/SYNCIN: bit_size: 2 variants: - - name: Disabled - description: Disabled. HRTIM is not synchronized and runs in standalone mode - value: 0 - - name: Internal - description: "Internal event: the HRTIM is synchronized with the on-chip timer" - value: 2 - - name: External - description: "External event: a positive pulse on HRTIM_SCIN input triggers the HRTIM" - value: 3 + - name: Disabled + description: Disabled. HRTIM is not synchronized and runs in standalone mode + value: 0 + - name: Internal + description: 'Internal event: the HRTIM is synchronized with the on-chip timer' + value: 2 + - name: External + description: 'External event: a positive pulse on HRTIM_SCIN input triggers the HRTIM' + value: 3 enum/SYNCOUT: bit_size: 2 variants: - - name: Disabled - description: Disabled - value: 0 - - name: PositivePulse - description: Positive pulse on SCOUT output (16x f_HRTIM clock cycles) - value: 2 - - name: NegativePulse - description: Negative pulse on SCOUT output (16x f_HRTIM clock cycles) - value: 3 + - name: Disabled + description: Disabled + value: 0 + - name: PositivePulse + description: Positive pulse on SCOUT output (16x f_HRTIM clock cycles) + value: 2 + - name: NegativePulse + description: Negative pulse on SCOUT output (16x f_HRTIM clock cycles) + value: 3 enum/SYNCRST: bit_size: 1 variants: - - name: Disabled - description: Synchronization event has no effect on Timer x - value: 0 - - name: Reset - description: Synchronization event resets Timer x - value: 1 + - name: Disabled + description: Synchronization event has no effect on Timer x + value: 0 + - name: Reset + description: Synchronization event resets Timer x + value: 1 enum/SYNCSRC: bit_size: 2 variants: - - name: MasterStart - description: Master timer Start - value: 0 - - name: MasterCompare1 - description: Master timer Compare 1 event - value: 1 - - name: TimerAStart - description: Timer A start/reset - value: 2 - - name: TimerACompare1 - description: Timer A Compare 1 event - value: 3 + - name: MasterStart + description: Master timer Start + value: 0 + - name: MasterCompare1 + description: Master timer Compare 1 event + value: 1 + - name: TimerAStart + description: Timer A start/reset + value: 2 + - name: TimerACompare1 + description: Timer A Compare 1 event + value: 3 enum/SYNCSTRT: bit_size: 1 variants: - - name: Disabled - description: Synchronization event has no effect on Timer x - value: 0 - - name: Start - description: Synchronization event starts Timer x - value: 1 + - name: Disabled + description: Synchronization event has no effect on Timer x + value: 0 + - name: Start + description: Synchronization event starts Timer x + value: 1 enum/TIMAISR_DLYPRT: bit_size: 1 variants: - - name: Inactive - description: Not in delayed idle or balanced idle mode - value: 0 - - name: Active - description: Delayed idle or balanced idle mode entry - value: 1 + - name: Inactive + description: Not in delayed idle or balanced idle mode + value: 0 + - name: Active + description: Delayed idle or balanced idle mode entry + value: 1 enum/UPDGAT: bit_size: 4 variants: - - name: Independent - description: Update occurs independently from the DMA burst transfer - value: 0 - - name: DMABurst - description: Update occurs when the DMA burst transfer is completed - value: 1 - - name: DMABurst_Update - description: Update occurs on the update event following DMA burst transfer completion - value: 2 - - name: Input1 - description: Update occurs on a rising edge of HRTIM update enable input 1 - value: 3 - - name: Input2 - description: Update occurs on a rising edge of HRTIM update enable input 2 - value: 4 - - name: Input3 - description: Update occurs on a rising edge of HRTIM update enable input 3 - value: 5 - - name: Input1_Update - description: Update occurs on the update event following a rising edge of HRTIM update enable input 1 - value: 6 - - name: Input2_Update - description: Update occurs on the update event following a rising edge of HRTIM update enable input 2 - value: 7 - - name: Input3_Update - description: Update occurs on the update event following a rising edge of HRTIM update enable input 3 - value: 8 + - name: Independent + description: Update occurs independently from the DMA burst transfer + value: 0 + - name: DMABurst + description: Update occurs when the DMA burst transfer is completed + value: 1 + - name: DMABurst_Update + description: Update occurs on the update event following DMA burst transfer completion + value: 2 + - name: Input1 + description: Update occurs on a rising edge of HRTIM update enable input 1 + value: 3 + - name: Input2 + description: Update occurs on a rising edge of HRTIM update enable input 2 + value: 4 + - name: Input3 + description: Update occurs on a rising edge of HRTIM update enable input 3 + value: 5 + - name: Input1_Update + description: Update occurs on the update event following a rising edge of HRTIM update enable input 1 + value: 6 + - name: Input2_Update + description: Update occurs on the update event following a rising edge of HRTIM update enable input 2 + value: 7 + - name: Input3_Update + description: Update occurs on the update event following a rising edge of HRTIM update enable input 3 + value: 8 diff --git a/data/registers/i2c_v1.yaml b/data/registers/i2c_v1.yaml index 9c3fcdc..1a5439e 100644 --- a/data/registers/i2c_v1.yaml +++ b/data/registers/i2c_v1.yaml @@ -1,408 +1,407 @@ ---- block/I2C: description: Inter-integrated circuit items: - - name: CR1 - description: Control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Control register 2 - byte_offset: 4 - fieldset: CR2 - - name: OAR1 - description: Own address register 1 - byte_offset: 8 - fieldset: OAR1 - - name: OAR2 - description: Own address register 2 - byte_offset: 12 - fieldset: OAR2 - - name: DR - description: Data register - byte_offset: 16 - fieldset: DR - - name: SR1 - description: Status register 1 - byte_offset: 20 - fieldset: SR1 - - name: SR2 - description: Status register 2 - byte_offset: 24 - fieldset: SR2 - - name: CCR - description: Clock control register - byte_offset: 28 - fieldset: CCR - - name: TRISE - description: TRISE register - byte_offset: 32 - fieldset: TRISE - - name: FLTR - description: FLTR register - byte_offset: 36 - fieldset: FLTR + - name: CR1 + description: Control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Control register 2 + byte_offset: 4 + fieldset: CR2 + - name: OAR1 + description: Own address register 1 + byte_offset: 8 + fieldset: OAR1 + - name: OAR2 + description: Own address register 2 + byte_offset: 12 + fieldset: OAR2 + - name: DR + description: Data register + byte_offset: 16 + fieldset: DR + - name: SR1 + description: Status register 1 + byte_offset: 20 + fieldset: SR1 + - name: SR2 + description: Status register 2 + byte_offset: 24 + fieldset: SR2 + - name: CCR + description: Clock control register + byte_offset: 28 + fieldset: CCR + - name: TRISE + description: TRISE register + byte_offset: 32 + fieldset: TRISE + - name: FLTR + description: FLTR register + byte_offset: 36 + fieldset: FLTR fieldset/CCR: description: Clock control register fields: - - name: CCR - description: Clock control register in Fast/Standard mode (Master mode) - bit_offset: 0 - bit_size: 12 - - name: DUTY - description: Fast mode duty cycle - bit_offset: 14 - bit_size: 1 - enum: DUTY - - name: F_S - description: I2C master mode selection - bit_offset: 15 - bit_size: 1 - enum: F_S + - name: CCR + description: Clock control register in Fast/Standard mode (Master mode) + bit_offset: 0 + bit_size: 12 + - name: DUTY + description: Fast mode duty cycle + bit_offset: 14 + bit_size: 1 + enum: DUTY + - name: F_S + description: I2C master mode selection + bit_offset: 15 + bit_size: 1 + enum: F_S fieldset/CR1: description: Control register 1 fields: - - name: PE - description: Peripheral enable - bit_offset: 0 - bit_size: 1 - - name: SMBUS - description: SMBus mode - bit_offset: 1 - bit_size: 1 - enum: SMBUS - - name: SMBTYPE - description: SMBus type - bit_offset: 3 - bit_size: 1 - enum: SMBTYPE - - name: ENARP - description: ARP enable - bit_offset: 4 - bit_size: 1 - - name: ENPEC - description: PEC enable - bit_offset: 5 - bit_size: 1 - - name: ENGC - description: General call enable - bit_offset: 6 - bit_size: 1 - - name: NOSTRETCH - description: Clock stretching disable (Slave mode) - bit_offset: 7 - bit_size: 1 - - name: START - description: Start generation - bit_offset: 8 - bit_size: 1 - - name: STOP - description: Stop generation - bit_offset: 9 - bit_size: 1 - - name: ACK - description: Acknowledge enable - bit_offset: 10 - bit_size: 1 - - name: POS - description: Acknowledge/PEC Position (for data reception) - bit_offset: 11 - bit_size: 1 - enum: POS - - name: PEC - description: Packet error checking - bit_offset: 12 - bit_size: 1 - - name: ALERT - description: SMBus alert - bit_offset: 13 - bit_size: 1 - - name: SWRST - description: Software reset - bit_offset: 15 - bit_size: 1 + - name: PE + description: Peripheral enable + bit_offset: 0 + bit_size: 1 + - name: SMBUS + description: SMBus mode + bit_offset: 1 + bit_size: 1 + enum: SMBUS + - name: SMBTYPE + description: SMBus type + bit_offset: 3 + bit_size: 1 + enum: SMBTYPE + - name: ENARP + description: ARP enable + bit_offset: 4 + bit_size: 1 + - name: ENPEC + description: PEC enable + bit_offset: 5 + bit_size: 1 + - name: ENGC + description: General call enable + bit_offset: 6 + bit_size: 1 + - name: NOSTRETCH + description: Clock stretching disable (Slave mode) + bit_offset: 7 + bit_size: 1 + - name: START + description: Start generation + bit_offset: 8 + bit_size: 1 + - name: STOP + description: Stop generation + bit_offset: 9 + bit_size: 1 + - name: ACK + description: Acknowledge enable + bit_offset: 10 + bit_size: 1 + - name: POS + description: Acknowledge/PEC Position (for data reception) + bit_offset: 11 + bit_size: 1 + enum: POS + - name: PEC + description: Packet error checking + bit_offset: 12 + bit_size: 1 + - name: ALERT + description: SMBus alert + bit_offset: 13 + bit_size: 1 + - name: SWRST + description: Software reset + bit_offset: 15 + bit_size: 1 fieldset/CR2: description: Control register 2 fields: - - name: FREQ - description: Peripheral clock frequency - bit_offset: 0 - bit_size: 6 - - name: ITERREN - description: Error interrupt enable - bit_offset: 8 - bit_size: 1 - - name: ITEVTEN - description: Event interrupt enable - bit_offset: 9 - bit_size: 1 - - name: ITBUFEN - description: Buffer interrupt enable - bit_offset: 10 - bit_size: 1 - - name: DMAEN - description: DMA requests enable - bit_offset: 11 - bit_size: 1 - - name: LAST - description: DMA last transfer - bit_offset: 12 - bit_size: 1 + - name: FREQ + description: Peripheral clock frequency + bit_offset: 0 + bit_size: 6 + - name: ITERREN + description: Error interrupt enable + bit_offset: 8 + bit_size: 1 + - name: ITEVTEN + description: Event interrupt enable + bit_offset: 9 + bit_size: 1 + - name: ITBUFEN + description: Buffer interrupt enable + bit_offset: 10 + bit_size: 1 + - name: DMAEN + description: DMA requests enable + bit_offset: 11 + bit_size: 1 + - name: LAST + description: DMA last transfer + bit_offset: 12 + bit_size: 1 fieldset/DR: description: Data register fields: - - name: DR - description: 8-bit data register - bit_offset: 0 - bit_size: 8 + - name: DR + description: 8-bit data register + bit_offset: 0 + bit_size: 8 fieldset/FLTR: description: FLTR register fields: - - name: DNF - description: Digital noise filter - bit_offset: 0 - bit_size: 4 - enum: DNF - - name: ANOFF - description: Analog noise filter - bit_offset: 4 - bit_size: 1 + - name: DNF + description: Digital noise filter + bit_offset: 0 + bit_size: 4 + enum: DNF + - name: ANOFF + description: Analog noise filter + bit_offset: 4 + bit_size: 1 fieldset/OAR1: description: Own address register 1 fields: - - name: ADD - description: Interface address - bit_offset: 0 - bit_size: 10 - - name: ADDMODE - description: Addressing mode (slave mode) - bit_offset: 15 - bit_size: 1 - enum: ADDMODE + - name: ADD + description: Interface address + bit_offset: 0 + bit_size: 10 + - name: ADDMODE + description: Addressing mode (slave mode) + bit_offset: 15 + bit_size: 1 + enum: ADDMODE fieldset/OAR2: description: Own address register 2 fields: - - name: ENDUAL - description: Dual addressing mode enable - bit_offset: 0 - bit_size: 1 - enum: ENDUAL - - name: ADD2 - description: Interface address - bit_offset: 1 - bit_size: 7 + - name: ENDUAL + description: Dual addressing mode enable + bit_offset: 0 + bit_size: 1 + enum: ENDUAL + - name: ADD2 + description: Interface address + bit_offset: 1 + bit_size: 7 fieldset/SR1: description: Status register 1 fields: - - name: START - description: Start bit (Master mode) - bit_offset: 0 - bit_size: 1 - - name: ADDR - description: Address sent (master mode)/matched (slave mode) - bit_offset: 1 - bit_size: 1 - - name: BTF - description: Byte transfer finished - bit_offset: 2 - bit_size: 1 - - name: ADD10 - description: 10-bit header sent (Master mode) - bit_offset: 3 - bit_size: 1 - - name: STOPF - description: Stop detection (slave mode) - bit_offset: 4 - bit_size: 1 - - name: RXNE - description: Data register not empty (receivers) - bit_offset: 6 - bit_size: 1 - - name: TXE - description: Data register empty (transmitters) - bit_offset: 7 - bit_size: 1 - - name: BERR - description: Bus error - bit_offset: 8 - bit_size: 1 - - name: ARLO - description: Arbitration lost (master mode) - bit_offset: 9 - bit_size: 1 - - name: AF - description: Acknowledge failure - bit_offset: 10 - bit_size: 1 - - name: OVR - description: Overrun/Underrun - bit_offset: 11 - bit_size: 1 - - name: PECERR - description: PEC Error in reception - bit_offset: 12 - bit_size: 1 - - name: TIMEOUT - description: Timeout or t_low detection flag - bit_offset: 14 - bit_size: 1 - - name: ALERT - description: SMBus alert - bit_offset: 15 - bit_size: 1 + - name: START + description: Start bit (Master mode) + bit_offset: 0 + bit_size: 1 + - name: ADDR + description: Address sent (master mode)/matched (slave mode) + bit_offset: 1 + bit_size: 1 + - name: BTF + description: Byte transfer finished + bit_offset: 2 + bit_size: 1 + - name: ADD10 + description: 10-bit header sent (Master mode) + bit_offset: 3 + bit_size: 1 + - name: STOPF + description: Stop detection (slave mode) + bit_offset: 4 + bit_size: 1 + - name: RXNE + description: Data register not empty (receivers) + bit_offset: 6 + bit_size: 1 + - name: TXE + description: Data register empty (transmitters) + bit_offset: 7 + bit_size: 1 + - name: BERR + description: Bus error + bit_offset: 8 + bit_size: 1 + - name: ARLO + description: Arbitration lost (master mode) + bit_offset: 9 + bit_size: 1 + - name: AF + description: Acknowledge failure + bit_offset: 10 + bit_size: 1 + - name: OVR + description: Overrun/Underrun + bit_offset: 11 + bit_size: 1 + - name: PECERR + description: PEC Error in reception + bit_offset: 12 + bit_size: 1 + - name: TIMEOUT + description: Timeout or t_low detection flag + bit_offset: 14 + bit_size: 1 + - name: ALERT + description: SMBus alert + bit_offset: 15 + bit_size: 1 fieldset/SR2: description: Status register 2 fields: - - name: MSL - description: Master/slave - bit_offset: 0 - bit_size: 1 - - name: BUSY - description: Bus busy - bit_offset: 1 - bit_size: 1 - - name: TRA - description: Transmitter/receiver - bit_offset: 2 - bit_size: 1 - - name: GENCALL - description: General call address (Slave mode) - bit_offset: 4 - bit_size: 1 - - name: SMBDEFAULT - description: SMBus device default address (Slave mode) - bit_offset: 5 - bit_size: 1 - - name: SMBHOST - description: SMBus host header (Slave mode) - bit_offset: 6 - bit_size: 1 - - name: DUALF - description: Dual flag (Slave mode) - bit_offset: 7 - bit_size: 1 - - name: PEC - description: Packet error checking register - bit_offset: 8 - bit_size: 8 + - name: MSL + description: Master/slave + bit_offset: 0 + bit_size: 1 + - name: BUSY + description: Bus busy + bit_offset: 1 + bit_size: 1 + - name: TRA + description: Transmitter/receiver + bit_offset: 2 + bit_size: 1 + - name: GENCALL + description: General call address (Slave mode) + bit_offset: 4 + bit_size: 1 + - name: SMBDEFAULT + description: SMBus device default address (Slave mode) + bit_offset: 5 + bit_size: 1 + - name: SMBHOST + description: SMBus host header (Slave mode) + bit_offset: 6 + bit_size: 1 + - name: DUALF + description: Dual flag (Slave mode) + bit_offset: 7 + bit_size: 1 + - name: PEC + description: Packet error checking register + bit_offset: 8 + bit_size: 8 fieldset/TRISE: description: TRISE register fields: - - name: TRISE - description: Maximum rise time in Fast/Standard mode (Master mode) - bit_offset: 0 - bit_size: 6 + - name: TRISE + description: Maximum rise time in Fast/Standard mode (Master mode) + bit_offset: 0 + bit_size: 6 enum/ADDMODE: bit_size: 1 variants: - - name: Bit7 - description: 7-bit addressing mode - value: 0 - - name: Bit10 - description: 10-bit addressing mode - value: 1 + - name: Bit7 + description: 7-bit addressing mode + value: 0 + - name: Bit10 + description: 10-bit addressing mode + value: 1 enum/DNF: bit_size: 4 variants: - - name: NoFilter - description: Digital filter disabled - value: 0 - - name: Filter1 - description: Digital filter enabled and filtering capability up to 1 tI2CCLK - value: 1 - - name: Filter2 - description: Digital filter enabled and filtering capability up to 2 tI2CCLK - value: 2 - - name: Filter3 - description: Digital filter enabled and filtering capability up to 3 tI2CCLK - value: 3 - - name: Filter4 - description: Digital filter enabled and filtering capability up to 4 tI2CCLK - value: 4 - - name: Filter5 - description: Digital filter enabled and filtering capability up to 5 tI2CCLK - value: 5 - - name: Filter6 - description: Digital filter enabled and filtering capability up to 6 tI2CCLK - value: 6 - - name: Filter7 - description: Digital filter enabled and filtering capability up to 7 tI2CCLK - value: 7 - - name: Filter8 - description: Digital filter enabled and filtering capability up to 8 tI2CCLK - value: 8 - - name: Filter9 - description: Digital filter enabled and filtering capability up to 9 tI2CCLK - value: 9 - - name: Filter10 - description: Digital filter enabled and filtering capability up to 10 tI2CCLK - value: 10 - - name: Filter11 - description: Digital filter enabled and filtering capability up to 11 tI2CCLK - value: 11 - - name: Filter12 - description: Digital filter enabled and filtering capability up to 12 tI2CCLK - value: 12 - - name: Filter13 - description: Digital filter enabled and filtering capability up to 13 tI2CCLK - value: 13 - - name: Filter14 - description: Digital filter enabled and filtering capability up to 14 tI2CCLK - value: 14 - - name: Filter15 - description: Digital filter enabled and filtering capability up to 15 tI2CCLK - value: 15 + - name: NoFilter + description: Digital filter disabled + value: 0 + - name: Filter1 + description: Digital filter enabled and filtering capability up to 1 tI2CCLK + value: 1 + - name: Filter2 + description: Digital filter enabled and filtering capability up to 2 tI2CCLK + value: 2 + - name: Filter3 + description: Digital filter enabled and filtering capability up to 3 tI2CCLK + value: 3 + - name: Filter4 + description: Digital filter enabled and filtering capability up to 4 tI2CCLK + value: 4 + - name: Filter5 + description: Digital filter enabled and filtering capability up to 5 tI2CCLK + value: 5 + - name: Filter6 + description: Digital filter enabled and filtering capability up to 6 tI2CCLK + value: 6 + - name: Filter7 + description: Digital filter enabled and filtering capability up to 7 tI2CCLK + value: 7 + - name: Filter8 + description: Digital filter enabled and filtering capability up to 8 tI2CCLK + value: 8 + - name: Filter9 + description: Digital filter enabled and filtering capability up to 9 tI2CCLK + value: 9 + - name: Filter10 + description: Digital filter enabled and filtering capability up to 10 tI2CCLK + value: 10 + - name: Filter11 + description: Digital filter enabled and filtering capability up to 11 tI2CCLK + value: 11 + - name: Filter12 + description: Digital filter enabled and filtering capability up to 12 tI2CCLK + value: 12 + - name: Filter13 + description: Digital filter enabled and filtering capability up to 13 tI2CCLK + value: 13 + - name: Filter14 + description: Digital filter enabled and filtering capability up to 14 tI2CCLK + value: 14 + - name: Filter15 + description: Digital filter enabled and filtering capability up to 15 tI2CCLK + value: 15 enum/DUTY: bit_size: 1 variants: - - name: Duty2_1 - description: Duty cycle t_low/t_high = 2/1 - value: 0 - - name: Duty16_9 - description: Duty cycle t_low/t_high = 16/9 - value: 1 + - name: Duty2_1 + description: Duty cycle t_low/t_high = 2/1 + value: 0 + - name: Duty16_9 + description: Duty cycle t_low/t_high = 16/9 + value: 1 enum/ENDUAL: bit_size: 1 variants: - - name: Single - description: Single addressing mode - value: 0 - - name: Dual - description: Dual addressing mode - value: 1 + - name: Single + description: Single addressing mode + value: 0 + - name: Dual + description: Dual addressing mode + value: 1 enum/F_S: bit_size: 1 variants: - - name: Standard - description: Standard mode I2C - value: 0 - - name: Fast - description: Fast mode I2C - value: 1 + - name: Standard + description: Standard mode I2C + value: 0 + - name: Fast + description: Fast mode I2C + value: 1 enum/POS: bit_size: 1 variants: - - name: Current - description: ACK bit controls the (N)ACK of the current byte being received - value: 0 - - name: Next - description: ACK bit controls the (N)ACK of the next byte to be received - value: 1 + - name: Current + description: ACK bit controls the (N)ACK of the current byte being received + value: 0 + - name: Next + description: ACK bit controls the (N)ACK of the next byte to be received + value: 1 enum/SMBTYPE: bit_size: 1 variants: - - name: Device - description: SMBus Device - value: 0 - - name: Host - description: SMBus Host - value: 1 + - name: Device + description: SMBus Device + value: 0 + - name: Host + description: SMBus Host + value: 1 enum/SMBUS: bit_size: 1 variants: - - name: I2C - description: I2C Mode - value: 0 - - name: SMBus - description: SMBus - value: 1 + - name: I2C + description: I2C Mode + value: 0 + - name: SMBus + description: SMBus + value: 1 diff --git a/data/registers/i2c_v2.yaml b/data/registers/i2c_v2.yaml index 5844cc4..9486c3d 100644 --- a/data/registers/i2c_v2.yaml +++ b/data/registers/i2c_v2.yaml @@ -1,513 +1,512 @@ ---- block/I2C: description: Inter-integrated circuit items: - - name: CR1 - description: Control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Control register 2 - byte_offset: 4 - fieldset: CR2 - - name: OAR1 - description: Own address register 1 - byte_offset: 8 - fieldset: OAR1 - - name: OAR2 - description: Own address register 2 - byte_offset: 12 - fieldset: OAR2 - - name: TIMINGR - description: Timing register - byte_offset: 16 - fieldset: TIMINGR - - name: TIMEOUTR - description: Timeout register - byte_offset: 20 - fieldset: TIMEOUTR - - name: ISR - description: Interrupt and Status register - byte_offset: 24 - fieldset: ISR - - name: ICR - description: Interrupt clear register - byte_offset: 28 - fieldset: ICR - - name: PECR - description: PEC register - byte_offset: 32 - fieldset: PECR - - name: RXDR - description: Receive data register - byte_offset: 36 - fieldset: RXDR - - name: TXDR - description: Transmit data register - byte_offset: 40 - fieldset: TXDR + - name: CR1 + description: Control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Control register 2 + byte_offset: 4 + fieldset: CR2 + - name: OAR1 + description: Own address register 1 + byte_offset: 8 + fieldset: OAR1 + - name: OAR2 + description: Own address register 2 + byte_offset: 12 + fieldset: OAR2 + - name: TIMINGR + description: Timing register + byte_offset: 16 + fieldset: TIMINGR + - name: TIMEOUTR + description: Timeout register + byte_offset: 20 + fieldset: TIMEOUTR + - name: ISR + description: Interrupt and Status register + byte_offset: 24 + fieldset: ISR + - name: ICR + description: Interrupt clear register + byte_offset: 28 + fieldset: ICR + - name: PECR + description: PEC register + byte_offset: 32 + fieldset: PECR + - name: RXDR + description: Receive data register + byte_offset: 36 + fieldset: RXDR + - name: TXDR + description: Transmit data register + byte_offset: 40 + fieldset: TXDR fieldset/CR1: description: Control register 1 fields: - - name: PE - description: Peripheral enable - bit_offset: 0 - bit_size: 1 - - name: TXIE - description: TX Interrupt enable - bit_offset: 1 - bit_size: 1 - - name: RXIE - description: RX Interrupt enable - bit_offset: 2 - bit_size: 1 - - name: ADDRIE - description: Address match interrupt enable (slave only) - bit_offset: 3 - bit_size: 1 - - name: NACKIE - description: Not acknowledge received interrupt enable - bit_offset: 4 - bit_size: 1 - - name: STOPIE - description: STOP detection Interrupt enable - bit_offset: 5 - bit_size: 1 - - name: TCIE - description: Transfer Complete interrupt enable - bit_offset: 6 - bit_size: 1 - - name: ERRIE - description: Error interrupts enable - bit_offset: 7 - bit_size: 1 - - name: DNF - description: Digital noise filter - bit_offset: 8 - bit_size: 4 - enum: DNF - - name: ANFOFF - description: Analog noise filter OFF - bit_offset: 12 - bit_size: 1 - - name: TXDMAEN - description: DMA transmission requests enable - bit_offset: 14 - bit_size: 1 - - name: RXDMAEN - description: DMA reception requests enable - bit_offset: 15 - bit_size: 1 - - name: SBC - description: Slave byte control - bit_offset: 16 - bit_size: 1 - - name: NOSTRETCH - description: Clock stretching disable - bit_offset: 17 - bit_size: 1 - - name: GCEN - description: General call enable - bit_offset: 19 - bit_size: 1 - - name: SMBHEN - description: SMBus Host address enable - bit_offset: 20 - bit_size: 1 - - name: SMBDEN - description: SMBus Device Default address enable - bit_offset: 21 - bit_size: 1 - - name: ALERTEN - description: SMBUS alert enable - bit_offset: 22 - bit_size: 1 - - name: PECEN - description: PEC enable - bit_offset: 23 - bit_size: 1 + - name: PE + description: Peripheral enable + bit_offset: 0 + bit_size: 1 + - name: TXIE + description: TX Interrupt enable + bit_offset: 1 + bit_size: 1 + - name: RXIE + description: RX Interrupt enable + bit_offset: 2 + bit_size: 1 + - name: ADDRIE + description: Address match interrupt enable (slave only) + bit_offset: 3 + bit_size: 1 + - name: NACKIE + description: Not acknowledge received interrupt enable + bit_offset: 4 + bit_size: 1 + - name: STOPIE + description: STOP detection Interrupt enable + bit_offset: 5 + bit_size: 1 + - name: TCIE + description: Transfer Complete interrupt enable + bit_offset: 6 + bit_size: 1 + - name: ERRIE + description: Error interrupts enable + bit_offset: 7 + bit_size: 1 + - name: DNF + description: Digital noise filter + bit_offset: 8 + bit_size: 4 + enum: DNF + - name: ANFOFF + description: Analog noise filter OFF + bit_offset: 12 + bit_size: 1 + - name: TXDMAEN + description: DMA transmission requests enable + bit_offset: 14 + bit_size: 1 + - name: RXDMAEN + description: DMA reception requests enable + bit_offset: 15 + bit_size: 1 + - name: SBC + description: Slave byte control + bit_offset: 16 + bit_size: 1 + - name: NOSTRETCH + description: Clock stretching disable + bit_offset: 17 + bit_size: 1 + - name: GCEN + description: General call enable + bit_offset: 19 + bit_size: 1 + - name: SMBHEN + description: SMBus Host address enable + bit_offset: 20 + bit_size: 1 + - name: SMBDEN + description: SMBus Device Default address enable + bit_offset: 21 + bit_size: 1 + - name: ALERTEN + description: SMBUS alert enable + bit_offset: 22 + bit_size: 1 + - name: PECEN + description: PEC enable + bit_offset: 23 + bit_size: 1 fieldset/CR2: description: Control register 2 fields: - - name: SADD - description: Slave address bit (master mode) - bit_offset: 0 - bit_size: 10 - - name: DIR - description: Transfer direction (master mode) - bit_offset: 10 - bit_size: 1 - enum: DIR - - name: ADD10 - description: 10-bit addressing mode (master mode) - bit_offset: 11 - bit_size: 1 - enum: ADDMODE - - name: HEAD10R - description: 10-bit address header only read direction (master receiver mode) - bit_offset: 12 - bit_size: 1 - enum: HEADR - - name: START - description: Start generation - bit_offset: 13 - bit_size: 1 - - name: STOP - description: Stop generation (master mode) - bit_offset: 14 - bit_size: 1 - - name: NACK - description: NACK generation (slave mode) - bit_offset: 15 - bit_size: 1 - - name: NBYTES - description: Number of bytes - bit_offset: 16 - bit_size: 8 - - name: RELOAD - description: NBYTES reload mode - bit_offset: 24 - bit_size: 1 - enum: RELOAD - - name: AUTOEND - description: Automatic end mode (master mode) - bit_offset: 25 - bit_size: 1 - enum: AUTOEND - - name: PECBYTE - description: Packet error checking byte - bit_offset: 26 - bit_size: 1 + - name: SADD + description: Slave address bit (master mode) + bit_offset: 0 + bit_size: 10 + - name: DIR + description: Transfer direction (master mode) + bit_offset: 10 + bit_size: 1 + enum: DIR + - name: ADD10 + description: 10-bit addressing mode (master mode) + bit_offset: 11 + bit_size: 1 + enum: ADDMODE + - name: HEAD10R + description: 10-bit address header only read direction (master receiver mode) + bit_offset: 12 + bit_size: 1 + enum: HEADR + - name: START + description: Start generation + bit_offset: 13 + bit_size: 1 + - name: STOP + description: Stop generation (master mode) + bit_offset: 14 + bit_size: 1 + - name: NACK + description: NACK generation (slave mode) + bit_offset: 15 + bit_size: 1 + - name: NBYTES + description: Number of bytes + bit_offset: 16 + bit_size: 8 + - name: RELOAD + description: NBYTES reload mode + bit_offset: 24 + bit_size: 1 + enum: RELOAD + - name: AUTOEND + description: Automatic end mode (master mode) + bit_offset: 25 + bit_size: 1 + enum: AUTOEND + - name: PECBYTE + description: Packet error checking byte + bit_offset: 26 + bit_size: 1 fieldset/ICR: description: Interrupt clear register fields: - - name: ADDRCF - description: Address Matched flag clear - bit_offset: 3 - bit_size: 1 - - name: NACKCF - description: Not Acknowledge flag clear - bit_offset: 4 - bit_size: 1 - - name: STOPCF - description: Stop detection flag clear - bit_offset: 5 - bit_size: 1 - - name: BERRCF - description: Bus error flag clear - bit_offset: 8 - bit_size: 1 - - name: ARLOCF - description: Arbitration lost flag clear - bit_offset: 9 - bit_size: 1 - - name: OVRCF - description: Overrun/Underrun flag clear - bit_offset: 10 - bit_size: 1 - - name: PECCF - description: PEC Error flag clear - bit_offset: 11 - bit_size: 1 - - name: TIMOUTCF - description: Timeout detection flag clear - bit_offset: 12 - bit_size: 1 - - name: ALERTCF - description: Alert flag clear - bit_offset: 13 - bit_size: 1 + - name: ADDRCF + description: Address Matched flag clear + bit_offset: 3 + bit_size: 1 + - name: NACKCF + description: Not Acknowledge flag clear + bit_offset: 4 + bit_size: 1 + - name: STOPCF + description: Stop detection flag clear + bit_offset: 5 + bit_size: 1 + - name: BERRCF + description: Bus error flag clear + bit_offset: 8 + bit_size: 1 + - name: ARLOCF + description: Arbitration lost flag clear + bit_offset: 9 + bit_size: 1 + - name: OVRCF + description: Overrun/Underrun flag clear + bit_offset: 10 + bit_size: 1 + - name: PECCF + description: PEC Error flag clear + bit_offset: 11 + bit_size: 1 + - name: TIMOUTCF + description: Timeout detection flag clear + bit_offset: 12 + bit_size: 1 + - name: ALERTCF + description: Alert flag clear + bit_offset: 13 + bit_size: 1 fieldset/ISR: description: Interrupt and Status register fields: - - name: TXE - description: Transmit data register empty (transmitters) - bit_offset: 0 - bit_size: 1 - - name: TXIS - description: Transmit interrupt status (transmitters) - bit_offset: 1 - bit_size: 1 - - name: RXNE - description: Receive data register not empty (receivers) - bit_offset: 2 - bit_size: 1 - - name: ADDR - description: Address matched (slave mode) - bit_offset: 3 - bit_size: 1 - - name: NACKF - description: Not acknowledge received flag - bit_offset: 4 - bit_size: 1 - - name: STOPF - description: Stop detection flag - bit_offset: 5 - bit_size: 1 - - name: TC - description: Transfer Complete (master mode) - bit_offset: 6 - bit_size: 1 - - name: TCR - description: Transfer Complete Reload - bit_offset: 7 - bit_size: 1 - - name: BERR - description: Bus error - bit_offset: 8 - bit_size: 1 - - name: ARLO - description: Arbitration lost - bit_offset: 9 - bit_size: 1 - - name: OVR - description: Overrun/Underrun (slave mode) - bit_offset: 10 - bit_size: 1 - - name: PECERR - description: PEC Error in reception - bit_offset: 11 - bit_size: 1 - - name: TIMEOUT - description: Timeout or t_low detection flag - bit_offset: 12 - bit_size: 1 - - name: ALERT - description: SMBus alert - bit_offset: 13 - bit_size: 1 - - name: BUSY - description: Bus busy - bit_offset: 15 - bit_size: 1 - - name: DIR - description: Transfer direction (Slave mode) - bit_offset: 16 - bit_size: 1 - enum: DIR - - name: ADDCODE - description: Address match code (Slave mode) - bit_offset: 17 - bit_size: 7 + - name: TXE + description: Transmit data register empty (transmitters) + bit_offset: 0 + bit_size: 1 + - name: TXIS + description: Transmit interrupt status (transmitters) + bit_offset: 1 + bit_size: 1 + - name: RXNE + description: Receive data register not empty (receivers) + bit_offset: 2 + bit_size: 1 + - name: ADDR + description: Address matched (slave mode) + bit_offset: 3 + bit_size: 1 + - name: NACKF + description: Not acknowledge received flag + bit_offset: 4 + bit_size: 1 + - name: STOPF + description: Stop detection flag + bit_offset: 5 + bit_size: 1 + - name: TC + description: Transfer Complete (master mode) + bit_offset: 6 + bit_size: 1 + - name: TCR + description: Transfer Complete Reload + bit_offset: 7 + bit_size: 1 + - name: BERR + description: Bus error + bit_offset: 8 + bit_size: 1 + - name: ARLO + description: Arbitration lost + bit_offset: 9 + bit_size: 1 + - name: OVR + description: Overrun/Underrun (slave mode) + bit_offset: 10 + bit_size: 1 + - name: PECERR + description: PEC Error in reception + bit_offset: 11 + bit_size: 1 + - name: TIMEOUT + description: Timeout or t_low detection flag + bit_offset: 12 + bit_size: 1 + - name: ALERT + description: SMBus alert + bit_offset: 13 + bit_size: 1 + - name: BUSY + description: Bus busy + bit_offset: 15 + bit_size: 1 + - name: DIR + description: Transfer direction (Slave mode) + bit_offset: 16 + bit_size: 1 + enum: DIR + - name: ADDCODE + description: Address match code (Slave mode) + bit_offset: 17 + bit_size: 7 fieldset/OAR1: description: Own address register 1 fields: - - name: OA1 - description: Interface address - bit_offset: 0 - bit_size: 10 - - name: OA1MODE - description: Own Address 1 10-bit mode - bit_offset: 10 - bit_size: 1 - enum: ADDMODE - - name: OA1EN - description: Own Address 1 enable - bit_offset: 15 - bit_size: 1 + - name: OA1 + description: Interface address + bit_offset: 0 + bit_size: 10 + - name: OA1MODE + description: Own Address 1 10-bit mode + bit_offset: 10 + bit_size: 1 + enum: ADDMODE + - name: OA1EN + description: Own Address 1 enable + bit_offset: 15 + bit_size: 1 fieldset/OAR2: description: Own address register 2 fields: - - name: OA2 - description: Interface address - bit_offset: 1 - bit_size: 7 - - name: OA2MSK - description: Own Address 2 masks - bit_offset: 8 - bit_size: 3 - enum: OAMSK - - name: OA2EN - description: Own Address 2 enable - bit_offset: 15 - bit_size: 1 + - name: OA2 + description: Interface address + bit_offset: 1 + bit_size: 7 + - name: OA2MSK + description: Own Address 2 masks + bit_offset: 8 + bit_size: 3 + enum: OAMSK + - name: OA2EN + description: Own Address 2 enable + bit_offset: 15 + bit_size: 1 fieldset/PECR: description: PEC register fields: - - name: PEC - description: Packet error checking register - bit_offset: 0 - bit_size: 8 + - name: PEC + description: Packet error checking register + bit_offset: 0 + bit_size: 8 fieldset/RXDR: description: Receive data register fields: - - name: RXDATA - description: 8-bit receive data - bit_offset: 0 - bit_size: 8 + - name: RXDATA + description: 8-bit receive data + bit_offset: 0 + bit_size: 8 fieldset/TIMEOUTR: description: Timeout register fields: - - name: TIMEOUTA - description: Bus timeout A - bit_offset: 0 - bit_size: 12 - - name: TIDLE - description: Idle clock timeout detection - bit_offset: 12 - bit_size: 1 - - name: TIMOUTEN - description: Clock timeout enable - bit_offset: 15 - bit_size: 1 - - name: TIMEOUTB - description: Bus timeout B - bit_offset: 16 - bit_size: 12 - - name: TEXTEN - description: Extended clock timeout enable - bit_offset: 31 - bit_size: 1 + - name: TIMEOUTA + description: Bus timeout A + bit_offset: 0 + bit_size: 12 + - name: TIDLE + description: Idle clock timeout detection + bit_offset: 12 + bit_size: 1 + - name: TIMOUTEN + description: Clock timeout enable + bit_offset: 15 + bit_size: 1 + - name: TIMEOUTB + description: Bus timeout B + bit_offset: 16 + bit_size: 12 + - name: TEXTEN + description: Extended clock timeout enable + bit_offset: 31 + bit_size: 1 fieldset/TIMINGR: description: Timing register fields: - - name: SCLL - description: SCL low period (master mode) - bit_offset: 0 - bit_size: 8 - - name: SCLH - description: SCL high period (master mode) - bit_offset: 8 - bit_size: 8 - - name: SDADEL - description: Data hold time - bit_offset: 16 - bit_size: 4 - - name: SCLDEL - description: Data setup time - bit_offset: 20 - bit_size: 4 - - name: PRESC - description: Timing prescaler - bit_offset: 28 - bit_size: 4 + - name: SCLL + description: SCL low period (master mode) + bit_offset: 0 + bit_size: 8 + - name: SCLH + description: SCL high period (master mode) + bit_offset: 8 + bit_size: 8 + - name: SDADEL + description: Data hold time + bit_offset: 16 + bit_size: 4 + - name: SCLDEL + description: Data setup time + bit_offset: 20 + bit_size: 4 + - name: PRESC + description: Timing prescaler + bit_offset: 28 + bit_size: 4 fieldset/TXDR: description: Transmit data register fields: - - name: TXDATA - description: 8-bit transmit data - bit_offset: 0 - bit_size: 8 + - name: TXDATA + description: 8-bit transmit data + bit_offset: 0 + bit_size: 8 enum/ADDMODE: bit_size: 1 variants: - - name: Bit7 - description: 7-bit addressing mode - value: 0 - - name: Bit10 - description: 10-bit addressing mode - value: 1 + - name: Bit7 + description: 7-bit addressing mode + value: 0 + - name: Bit10 + description: 10-bit addressing mode + value: 1 enum/AUTOEND: bit_size: 1 variants: - - name: Software - description: "Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low" - value: 0 - - name: Automatic - description: "Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred" - value: 1 + - name: Software + description: 'Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low' + value: 0 + - name: Automatic + description: 'Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred' + value: 1 enum/DIR: bit_size: 1 variants: - - name: Write - description: "Write transfer, slave enters receiver mode" - value: 0 - - name: Read - description: "Read transfer, slave enters transmitter mode" - value: 1 + - name: Write + description: Write transfer, slave enters receiver mode + value: 0 + - name: Read + description: Read transfer, slave enters transmitter mode + value: 1 enum/DNF: bit_size: 4 variants: - - name: NoFilter - description: Digital filter disabled - value: 0 - - name: Filter1 - description: Digital filter enabled and filtering capability up to 1 tI2CCLK - value: 1 - - name: Filter2 - description: Digital filter enabled and filtering capability up to 2 tI2CCLK - value: 2 - - name: Filter3 - description: Digital filter enabled and filtering capability up to 3 tI2CCLK - value: 3 - - name: Filter4 - description: Digital filter enabled and filtering capability up to 4 tI2CCLK - value: 4 - - name: Filter5 - description: Digital filter enabled and filtering capability up to 5 tI2CCLK - value: 5 - - name: Filter6 - description: Digital filter enabled and filtering capability up to 6 tI2CCLK - value: 6 - - name: Filter7 - description: Digital filter enabled and filtering capability up to 7 tI2CCLK - value: 7 - - name: Filter8 - description: Digital filter enabled and filtering capability up to 8 tI2CCLK - value: 8 - - name: Filter9 - description: Digital filter enabled and filtering capability up to 9 tI2CCLK - value: 9 - - name: Filter10 - description: Digital filter enabled and filtering capability up to 10 tI2CCLK - value: 10 - - name: Filter11 - description: Digital filter enabled and filtering capability up to 11 tI2CCLK - value: 11 - - name: Filter12 - description: Digital filter enabled and filtering capability up to 12 tI2CCLK - value: 12 - - name: Filter13 - description: Digital filter enabled and filtering capability up to 13 tI2CCLK - value: 13 - - name: Filter14 - description: Digital filter enabled and filtering capability up to 14 tI2CCLK - value: 14 - - name: Filter15 - description: Digital filter enabled and filtering capability up to 15 tI2CCLK - value: 15 + - name: NoFilter + description: Digital filter disabled + value: 0 + - name: Filter1 + description: Digital filter enabled and filtering capability up to 1 tI2CCLK + value: 1 + - name: Filter2 + description: Digital filter enabled and filtering capability up to 2 tI2CCLK + value: 2 + - name: Filter3 + description: Digital filter enabled and filtering capability up to 3 tI2CCLK + value: 3 + - name: Filter4 + description: Digital filter enabled and filtering capability up to 4 tI2CCLK + value: 4 + - name: Filter5 + description: Digital filter enabled and filtering capability up to 5 tI2CCLK + value: 5 + - name: Filter6 + description: Digital filter enabled and filtering capability up to 6 tI2CCLK + value: 6 + - name: Filter7 + description: Digital filter enabled and filtering capability up to 7 tI2CCLK + value: 7 + - name: Filter8 + description: Digital filter enabled and filtering capability up to 8 tI2CCLK + value: 8 + - name: Filter9 + description: Digital filter enabled and filtering capability up to 9 tI2CCLK + value: 9 + - name: Filter10 + description: Digital filter enabled and filtering capability up to 10 tI2CCLK + value: 10 + - name: Filter11 + description: Digital filter enabled and filtering capability up to 11 tI2CCLK + value: 11 + - name: Filter12 + description: Digital filter enabled and filtering capability up to 12 tI2CCLK + value: 12 + - name: Filter13 + description: Digital filter enabled and filtering capability up to 13 tI2CCLK + value: 13 + - name: Filter14 + description: Digital filter enabled and filtering capability up to 14 tI2CCLK + value: 14 + - name: Filter15 + description: Digital filter enabled and filtering capability up to 15 tI2CCLK + value: 15 enum/HEADR: bit_size: 1 variants: - - name: Complete - description: The master sends the complete 10 bit slave address read sequence - value: 0 - - name: Partial - description: "The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction" - value: 1 + - name: Complete + description: The master sends the complete 10 bit slave address read sequence + value: 0 + - name: Partial + description: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction + value: 1 enum/OAMSK: bit_size: 3 variants: - - name: NoMask - description: No mask - value: 0 - - name: Mask1 - description: "OA2[1] is masked and don’t care. Only OA2[7:2] are compared" - value: 1 - - name: Mask2 - description: "OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared" - value: 2 - - name: Mask3 - description: "OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared" - value: 3 - - name: Mask4 - description: "OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared" - value: 4 - - name: Mask5 - description: "OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared" - value: 5 - - name: Mask6 - description: "OA2[6:1] are masked and don’t care. Only OA2[7] is compared." - value: 6 - - name: Mask7 - description: "OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged" - value: 7 + - name: NoMask + description: No mask + value: 0 + - name: Mask1 + description: OA2[1] is masked and don’t care. Only OA2[7:2] are compared + value: 1 + - name: Mask2 + description: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared + value: 2 + - name: Mask3 + description: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared + value: 3 + - name: Mask4 + description: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared + value: 4 + - name: Mask5 + description: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared + value: 5 + - name: Mask6 + description: OA2[6:1] are masked and don’t care. Only OA2[7] is compared. + value: 6 + - name: Mask7 + description: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged + value: 7 enum/RELOAD: bit_size: 1 variants: - - name: Completed - description: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) - value: 0 - - name: NotCompleted - description: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) - value: 1 + - name: Completed + description: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) + value: 0 + - name: NotCompleted + description: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) + value: 1 diff --git a/data/registers/ipcc_v1.yaml b/data/registers/ipcc_v1.yaml index 4987b60..8212dff 100644 --- a/data/registers/ipcc_v1.yaml +++ b/data/registers/ipcc_v1.yaml @@ -1,142 +1,141 @@ ---- block/IPCC: description: IPCC items: - - name: CPU - description: CPU specific registers - array: - len: 2 - stride: 16 - byte_offset: 0 - block: IPCC_CPU + - name: CPU + description: CPU specific registers + array: + len: 2 + stride: 16 + byte_offset: 0 + block: IPCC_CPU block/IPCC_CPU: description: IPCC items: - - name: CR - description: Control register CPUx - byte_offset: 0 - fieldset: C1CR - - name: MR - description: Mask register CPUx - byte_offset: 4 - fieldset: C1MR - - name: SCR - description: Status Set or Clear register CPU1 - byte_offset: 8 - access: Write - fieldset: C1SCR - - name: SR - description: CPU1 to CPU2 status register - byte_offset: 12 - access: Read - fieldset: C1TO2SR + - name: CR + description: Control register CPUx + byte_offset: 0 + fieldset: C1CR + - name: MR + description: Mask register CPUx + byte_offset: 4 + fieldset: C1MR + - name: SCR + description: Status Set or Clear register CPU1 + byte_offset: 8 + access: Write + fieldset: C1SCR + - name: SR + description: CPU1 to CPU2 status register + byte_offset: 12 + access: Read + fieldset: C1TO2SR fieldset/C1CR: description: Control register CPU1 fields: - - name: RXOIE - description: processor 1 Receive channel occupied interrupt enable - bit_offset: 0 - bit_size: 1 - - name: TXFIE - description: processor 1 Transmit channel free interrupt enable - bit_offset: 16 - bit_size: 1 + - name: RXOIE + description: processor 1 Receive channel occupied interrupt enable + bit_offset: 0 + bit_size: 1 + - name: TXFIE + description: processor 1 Transmit channel free interrupt enable + bit_offset: 16 + bit_size: 1 fieldset/C1MR: description: Mask register CPU1 fields: - - name: CHOM - description: processor 1 Receive channel x occupied interrupt enable - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: CHFM - description: processor 1 Transmit channel x free interrupt mask - bit_offset: 16 - bit_size: 1 - array: - len: 6 - stride: 1 + - name: CHOM + description: processor 1 Receive channel x occupied interrupt enable + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: CHFM + description: processor 1 Transmit channel x free interrupt mask + bit_offset: 16 + bit_size: 1 + array: + len: 6 + stride: 1 fieldset/C1SCR: description: Status Set or Clear register CPU1 fields: - - name: CHC - description: processor 1 Receive channel x status clear - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: CHS - description: processor 1 Transmit channel x status set - bit_offset: 16 - bit_size: 1 - array: - len: 6 - stride: 1 + - name: CHC + description: processor 1 Receive channel x status clear + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: CHS + description: processor 1 Transmit channel x status set + bit_offset: 16 + bit_size: 1 + array: + len: 6 + stride: 1 fieldset/C1TO2SR: description: CPU1 to CPU2 status register fields: - - name: CHF - description: processor 1 transmit to process 2 Receive channel x status flag - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 + - name: CHF + description: processor 1 transmit to process 2 Receive channel x status flag + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 fieldset/C2CR: description: Control register CPU2 fields: - - name: RXOIE - description: processor 2 Receive channel occupied interrupt enable - bit_offset: 0 - bit_size: 1 - - name: TXFIE - description: processor 2 Transmit channel free interrupt enable - bit_offset: 16 - bit_size: 1 + - name: RXOIE + description: processor 2 Receive channel occupied interrupt enable + bit_offset: 0 + bit_size: 1 + - name: TXFIE + description: processor 2 Transmit channel free interrupt enable + bit_offset: 16 + bit_size: 1 fieldset/C2MR: description: Mask register CPU2 fields: - - name: CHOM - description: processor 2 Receive channel x occupied interrupt enable - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: CHFM - description: processor 2 Transmit channel 1 free interrupt mask - bit_offset: 16 - bit_size: 1 - array: - len: 6 - stride: 1 + - name: CHOM + description: processor 2 Receive channel x occupied interrupt enable + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: CHFM + description: processor 2 Transmit channel 1 free interrupt mask + bit_offset: 16 + bit_size: 1 + array: + len: 6 + stride: 1 fieldset/C2SCR: description: Status Set or Clear register CPU2 fields: - - name: CHC - description: processor 2 Receive channel x status clear - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: CHS - description: processor 2 Transmit channel 1 status set - bit_offset: 16 - bit_size: 1 - array: - len: 6 - stride: 1 + - name: CHC + description: processor 2 Receive channel x status clear + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: CHS + description: processor 2 Transmit channel 1 status set + bit_offset: 16 + bit_size: 1 + array: + len: 6 + stride: 1 fieldset/C2TOC1SR: description: CPU2 to CPU1 status register fields: - - name: CHF - description: processor 2 transmit to process 1 Receive channel x status flag - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 + - name: CHF + description: processor 2 transmit to process 1 Receive channel x status flag + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 diff --git a/data/registers/iwdg_v1.yaml b/data/registers/iwdg_v1.yaml index ff32087..d8b8362 100644 --- a/data/registers/iwdg_v1.yaml +++ b/data/registers/iwdg_v1.yaml @@ -1,95 +1,94 @@ ---- block/IWDG: description: Independent watchdog items: - - name: KR - description: Key register - byte_offset: 0 - access: Write - fieldset: KR - - name: PR - description: Prescaler register - byte_offset: 4 - fieldset: PR - - name: RLR - description: Reload register - byte_offset: 8 - fieldset: RLR - - name: SR - description: Status register - byte_offset: 12 - access: Read - fieldset: SR + - name: KR + description: Key register + byte_offset: 0 + access: Write + fieldset: KR + - name: PR + description: Prescaler register + byte_offset: 4 + fieldset: PR + - name: RLR + description: Reload register + byte_offset: 8 + fieldset: RLR + - name: SR + description: Status register + byte_offset: 12 + access: Read + fieldset: SR fieldset/KR: description: Key register fields: - - name: KEY - description: "Key value (write only, read 0000h)" - bit_offset: 0 - bit_size: 16 - enum: KEY + - name: KEY + description: Key value (write only, read 0000h) + bit_offset: 0 + bit_size: 16 + enum: KEY fieldset/PR: description: Prescaler register fields: - - name: PR - description: Prescaler divider - bit_offset: 0 - bit_size: 3 - enum: PR + - name: PR + description: Prescaler divider + bit_offset: 0 + bit_size: 3 + enum: PR fieldset/RLR: description: Reload register fields: - - name: RL - description: Watchdog counter reload value - bit_offset: 0 - bit_size: 12 + - name: RL + description: Watchdog counter reload value + bit_offset: 0 + bit_size: 12 fieldset/SR: description: Status register fields: - - name: PVU - description: Watchdog prescaler value update - bit_offset: 0 - bit_size: 1 - - name: RVU - description: Watchdog counter reload value update - bit_offset: 1 - bit_size: 1 + - name: PVU + description: Watchdog prescaler value update + bit_offset: 0 + bit_size: 1 + - name: RVU + description: Watchdog counter reload value update + bit_offset: 1 + bit_size: 1 enum/KEY: bit_size: 16 variants: - - name: Enable - description: "Enable access to PR, RLR and WINR registers (0x5555)" - value: 21845 - - name: Reset - description: Reset the watchdog value (0xAAAA) - value: 43690 - - name: Start - description: Start the watchdog (0xCCCC) - value: 52428 + - name: Enable + description: Enable access to PR, RLR and WINR registers (0x5555) + value: 21845 + - name: Reset + description: Reset the watchdog value (0xAAAA) + value: 43690 + - name: Start + description: Start the watchdog (0xCCCC) + value: 52428 enum/PR: bit_size: 3 variants: - - name: DivideBy4 - description: Divider /4 - value: 0 - - name: DivideBy8 - description: Divider /8 - value: 1 - - name: DivideBy16 - description: Divider /16 - value: 2 - - name: DivideBy32 - description: Divider /32 - value: 3 - - name: DivideBy64 - description: Divider /64 - value: 4 - - name: DivideBy128 - description: Divider /128 - value: 5 - - name: DivideBy256 - description: Divider /256 - value: 6 - - name: DivideBy256bis - description: Divider /256 - value: 7 + - name: DivideBy4 + description: Divider /4 + value: 0 + - name: DivideBy8 + description: Divider /8 + value: 1 + - name: DivideBy16 + description: Divider /16 + value: 2 + - name: DivideBy32 + description: Divider /32 + value: 3 + - name: DivideBy64 + description: Divider /64 + value: 4 + - name: DivideBy128 + description: Divider /128 + value: 5 + - name: DivideBy256 + description: Divider /256 + value: 6 + - name: DivideBy256bis + description: Divider /256 + value: 7 diff --git a/data/registers/iwdg_v2.yaml b/data/registers/iwdg_v2.yaml index a74774c..5cfaf45 100644 --- a/data/registers/iwdg_v2.yaml +++ b/data/registers/iwdg_v2.yaml @@ -1,110 +1,109 @@ ---- block/IWDG: description: Independent watchdog items: - - name: KR - description: Key register - byte_offset: 0 - access: Write - fieldset: KR - - name: PR - description: Prescaler register - byte_offset: 4 - fieldset: PR - - name: RLR - description: Reload register - byte_offset: 8 - fieldset: RLR - - name: SR - description: Status register - byte_offset: 12 - access: Read - fieldset: SR - - name: WINR - description: Window register - byte_offset: 16 - fieldset: WINR + - name: KR + description: Key register + byte_offset: 0 + access: Write + fieldset: KR + - name: PR + description: Prescaler register + byte_offset: 4 + fieldset: PR + - name: RLR + description: Reload register + byte_offset: 8 + fieldset: RLR + - name: SR + description: Status register + byte_offset: 12 + access: Read + fieldset: SR + - name: WINR + description: Window register + byte_offset: 16 + fieldset: WINR fieldset/KR: description: Key register fields: - - name: KEY - description: "Key value (write only, read 0000h)" - bit_offset: 0 - bit_size: 16 - enum: KEY + - name: KEY + description: Key value (write only, read 0000h) + bit_offset: 0 + bit_size: 16 + enum: KEY fieldset/PR: description: Prescaler register fields: - - name: PR - description: Prescaler divider - bit_offset: 0 - bit_size: 3 - enum: PR + - name: PR + description: Prescaler divider + bit_offset: 0 + bit_size: 3 + enum: PR fieldset/RLR: description: Reload register fields: - - name: RL - description: Watchdog counter reload value - bit_offset: 0 - bit_size: 12 + - name: RL + description: Watchdog counter reload value + bit_offset: 0 + bit_size: 12 fieldset/SR: description: Status register fields: - - name: PVU - description: Watchdog prescaler value update - bit_offset: 0 - bit_size: 1 - - name: RVU - description: Watchdog counter reload value update - bit_offset: 1 - bit_size: 1 - - name: WVU - description: Watchdog counter window value update - bit_offset: 2 - bit_size: 1 + - name: PVU + description: Watchdog prescaler value update + bit_offset: 0 + bit_size: 1 + - name: RVU + description: Watchdog counter reload value update + bit_offset: 1 + bit_size: 1 + - name: WVU + description: Watchdog counter window value update + bit_offset: 2 + bit_size: 1 fieldset/WINR: description: Window register fields: - - name: WIN - description: Watchdog counter window value - bit_offset: 0 - bit_size: 12 + - name: WIN + description: Watchdog counter window value + bit_offset: 0 + bit_size: 12 enum/KEY: bit_size: 16 variants: - - name: Enable - description: "Enable access to PR, RLR and WINR registers (0x5555)" - value: 21845 - - name: Reset - description: Reset the watchdog value (0xAAAA) - value: 43690 - - name: Start - description: Start the watchdog (0xCCCC) - value: 52428 + - name: Enable + description: Enable access to PR, RLR and WINR registers (0x5555) + value: 21845 + - name: Reset + description: Reset the watchdog value (0xAAAA) + value: 43690 + - name: Start + description: Start the watchdog (0xCCCC) + value: 52428 enum/PR: bit_size: 3 variants: - - name: DivideBy4 - description: Divider /4 - value: 0 - - name: DivideBy8 - description: Divider /8 - value: 1 - - name: DivideBy16 - description: Divider /16 - value: 2 - - name: DivideBy32 - description: Divider /32 - value: 3 - - name: DivideBy64 - description: Divider /64 - value: 4 - - name: DivideBy128 - description: Divider /128 - value: 5 - - name: DivideBy256 - description: Divider /256 - value: 6 - - name: DivideBy256bis - description: Divider /256 - value: 7 + - name: DivideBy4 + description: Divider /4 + value: 0 + - name: DivideBy8 + description: Divider /8 + value: 1 + - name: DivideBy16 + description: Divider /16 + value: 2 + - name: DivideBy32 + description: Divider /32 + value: 3 + - name: DivideBy64 + description: Divider /64 + value: 4 + - name: DivideBy128 + description: Divider /128 + value: 5 + - name: DivideBy256 + description: Divider /256 + value: 6 + - name: DivideBy256bis + description: Divider /256 + value: 7 diff --git a/data/registers/jpeg_v1.yaml b/data/registers/jpeg_v1.yaml index 5783765..882c8a2 100644 --- a/data/registers/jpeg_v1.yaml +++ b/data/registers/jpeg_v1.yaml @@ -1,5849 +1,5848 @@ ---- block/JPEG: description: JPEG codec items: - - name: JPEG_CONFR0 - description: JPEG codec configuration register 0 - byte_offset: 0 - access: Write - fieldset: JPEG_CONFR0 - - name: JPEG_CONFR1 - description: JPEG codec configuration register 1 - byte_offset: 4 - fieldset: JPEG_CONFR1 - - name: JPEG_CONFR2 - description: JPEG codec configuration register 2 - byte_offset: 8 - fieldset: JPEG_CONFR2 - - name: JPEG_CONFR3 - description: JPEG codec configuration register 3 - byte_offset: 12 - fieldset: JPEG_CONFR3 - - name: JPEG_CONFR4 - description: JPEG codec configuration register 4 - byte_offset: 16 - fieldset: JPEG_CONFR4 - - name: JPEG_CONFR5 - description: JPEG codec configuration register 5 - byte_offset: 20 - fieldset: JPEG_CONFR5 - - name: JPEG_CONFR6 - description: JPEG codec configuration register 6 - byte_offset: 24 - fieldset: JPEG_CONFR6 - - name: JPEG_CONFR7 - description: JPEG codec configuration register 7 - byte_offset: 28 - fieldset: JPEG_CONFR7 - - name: JPEG_CR - description: JPEG control register - byte_offset: 48 - fieldset: JPEG_CR - - name: JPEG_SR - description: JPEG status register - byte_offset: 52 - access: Read - fieldset: JPEG_SR - - name: JPEG_CFR - description: JPEG clear flag register - byte_offset: 56 - access: Write - fieldset: JPEG_CFR - - name: JPEG_DIR - description: JPEG data input register - byte_offset: 64 - access: Write - fieldset: JPEG_DIR - - name: JPEG_DOR - description: JPEG data output register - byte_offset: 68 - access: Read - fieldset: JPEG_DOR - - name: QMEM0_0 - description: JPEG quantization tables - byte_offset: 80 - fieldset: QMEM0_0 - - name: QMEM0_1 - description: JPEG quantization tables - byte_offset: 84 - fieldset: QMEM0_1 - - name: QMEM0_2 - description: JPEG quantization tables - byte_offset: 88 - fieldset: QMEM0_2 - - name: QMEM0_3 - description: JPEG quantization tables - byte_offset: 92 - fieldset: QMEM0_3 - - name: QMEM0_4 - description: JPEG quantization tables - byte_offset: 96 - fieldset: QMEM0_4 - - name: QMEM0_5 - description: JPEG quantization tables - byte_offset: 100 - fieldset: QMEM0_5 - - name: QMEM0_6 - description: JPEG quantization tables - byte_offset: 104 - fieldset: QMEM0_6 - - name: QMEM0_7 - description: JPEG quantization tables - byte_offset: 108 - fieldset: QMEM0_7 - - name: QMEM0_8 - description: JPEG quantization tables - byte_offset: 112 - fieldset: QMEM0_8 - - name: QMEM0_9 - description: JPEG quantization tables - byte_offset: 116 - fieldset: QMEM0_9 - - name: QMEM0_10 - description: JPEG quantization tables - byte_offset: 120 - fieldset: QMEM0_10 - - name: QMEM0_11 - description: JPEG quantization tables - byte_offset: 124 - fieldset: QMEM0_11 - - name: QMEM0_12 - description: JPEG quantization tables - byte_offset: 128 - fieldset: QMEM0_12 - - name: QMEM0_13 - description: JPEG quantization tables - byte_offset: 132 - fieldset: QMEM0_13 - - name: QMEM0_14 - description: JPEG quantization tables - byte_offset: 136 - fieldset: QMEM0_14 - - name: QMEM0_15 - description: JPEG quantization tables - byte_offset: 140 - fieldset: QMEM0_15 - - name: QMEM1_0 - description: JPEG quantization tables - byte_offset: 144 - fieldset: QMEM1_0 - - name: QMEM1_1 - description: JPEG quantization tables - byte_offset: 148 - fieldset: QMEM1_1 - - name: QMEM1_2 - description: JPEG quantization tables - byte_offset: 152 - fieldset: QMEM1_2 - - name: QMEM1_3 - description: JPEG quantization tables - byte_offset: 156 - fieldset: QMEM1_3 - - name: QMEM1_4 - description: JPEG quantization tables - byte_offset: 160 - fieldset: QMEM1_4 - - name: QMEM1_5 - description: JPEG quantization tables - byte_offset: 164 - fieldset: QMEM1_5 - - name: QMEM1_6 - description: JPEG quantization tables - byte_offset: 168 - fieldset: QMEM1_6 - - name: QMEM1_7 - description: JPEG quantization tables - byte_offset: 172 - fieldset: QMEM1_7 - - name: QMEM1_8 - description: JPEG quantization tables - byte_offset: 176 - fieldset: QMEM1_8 - - name: QMEM1_9 - description: JPEG quantization tables - byte_offset: 180 - fieldset: QMEM1_9 - - name: QMEM1_10 - description: JPEG quantization tables - byte_offset: 184 - fieldset: QMEM1_10 - - name: QMEM1_11 - description: JPEG quantization tables - byte_offset: 188 - fieldset: QMEM1_11 - - name: QMEM1_12 - description: JPEG quantization tables - byte_offset: 192 - fieldset: QMEM1_12 - - name: QMEM1_13 - description: JPEG quantization tables - byte_offset: 196 - fieldset: QMEM1_13 - - name: QMEM1_14 - description: JPEG quantization tables - byte_offset: 200 - fieldset: QMEM1_14 - - name: QMEM1_15 - description: JPEG quantization tables - byte_offset: 204 - fieldset: QMEM1_15 - - name: QMEM2_0 - description: JPEG quantization tables - byte_offset: 208 - fieldset: QMEM2_0 - - name: QMEM2_1 - description: JPEG quantization tables - byte_offset: 212 - fieldset: QMEM2_1 - - name: QMEM2_2 - description: JPEG quantization tables - byte_offset: 216 - fieldset: QMEM2_2 - - name: QMEM2_3 - description: JPEG quantization tables - byte_offset: 220 - fieldset: QMEM2_3 - - name: QMEM2_4 - description: JPEG quantization tables - byte_offset: 224 - fieldset: QMEM2_4 - - name: QMEM2_5 - description: JPEG quantization tables - byte_offset: 228 - fieldset: QMEM2_5 - - name: QMEM2_6 - description: JPEG quantization tables - byte_offset: 232 - fieldset: QMEM2_6 - - name: QMEM2_7 - description: JPEG quantization tables - byte_offset: 236 - fieldset: QMEM2_7 - - name: QMEM2_8 - description: JPEG quantization tables - byte_offset: 240 - fieldset: QMEM2_8 - - name: QMEM2_9 - description: JPEG quantization tables - byte_offset: 244 - fieldset: QMEM2_9 - - name: QMEM2_10 - description: JPEG quantization tables - byte_offset: 248 - fieldset: QMEM2_10 - - name: QMEM2_11 - description: JPEG quantization tables - byte_offset: 252 - fieldset: QMEM2_11 - - name: QMEM2_12 - description: JPEG quantization tables - byte_offset: 256 - fieldset: QMEM2_12 - - name: QMEM2_13 - description: JPEG quantization tables - byte_offset: 260 - fieldset: QMEM2_13 - - name: QMEM2_14 - description: JPEG quantization tables - byte_offset: 264 - fieldset: QMEM2_14 - - name: QMEM2_15 - description: JPEG quantization tables - byte_offset: 268 - fieldset: QMEM2_15 - - name: QMEM3_0 - description: JPEG quantization tables - byte_offset: 272 - fieldset: QMEM3_0 - - name: QMEM3_1 - description: JPEG quantization tables - byte_offset: 276 - fieldset: QMEM3_1 - - name: QMEM3_2 - description: JPEG quantization tables - byte_offset: 280 - fieldset: QMEM3_2 - - name: QMEM3_3 - description: JPEG quantization tables - byte_offset: 284 - fieldset: QMEM3_3 - - name: QMEM3_4 - description: JPEG quantization tables - byte_offset: 288 - fieldset: QMEM3_4 - - name: QMEM3_5 - description: JPEG quantization tables - byte_offset: 292 - fieldset: QMEM3_5 - - name: QMEM3_6 - description: JPEG quantization tables - byte_offset: 296 - fieldset: QMEM3_6 - - name: QMEM3_7 - description: JPEG quantization tables - byte_offset: 300 - fieldset: QMEM3_7 - - name: QMEM3_8 - description: JPEG quantization tables - byte_offset: 304 - fieldset: QMEM3_8 - - name: QMEM3_9 - description: JPEG quantization tables - byte_offset: 308 - fieldset: QMEM3_9 - - name: QMEM3_10 - description: JPEG quantization tables - byte_offset: 312 - fieldset: QMEM3_10 - - name: QMEM3_11 - description: JPEG quantization tables - byte_offset: 316 - fieldset: QMEM3_11 - - name: QMEM3_12 - description: JPEG quantization tables - byte_offset: 320 - fieldset: QMEM3_12 - - name: QMEM3_13 - description: JPEG quantization tables - byte_offset: 324 - fieldset: QMEM3_13 - - name: QMEM3_14 - description: JPEG quantization tables - byte_offset: 328 - fieldset: QMEM3_14 - - name: QMEM3_15 - description: JPEG quantization tables - byte_offset: 332 - fieldset: QMEM3_15 - - name: HUFFMIN_0 - description: JPEG HuffMin tables - byte_offset: 336 - fieldset: HUFFMIN_0 - - name: HUFFMIN_1 - description: JPEG HuffMin tables - byte_offset: 340 - fieldset: HUFFMIN_1 - - name: HUFFMIN_2 - description: JPEG HuffMin tables - byte_offset: 344 - fieldset: HUFFMIN_2 - - name: HUFFMIN_3 - description: JPEG HuffMin tables - byte_offset: 348 - fieldset: HUFFMIN_3 - - name: HUFFMIN_4 - description: JPEG HuffMin tables - byte_offset: 352 - fieldset: HUFFMIN_4 - - name: HUFFMIN_5 - description: JPEG HuffMin tables - byte_offset: 356 - fieldset: HUFFMIN_5 - - name: HUFFMIN_6 - description: JPEG HuffMin tables - byte_offset: 360 - fieldset: HUFFMIN_6 - - name: HUFFMIN_7 - description: JPEG HuffMin tables - byte_offset: 364 - fieldset: HUFFMIN_7 - - name: HUFFMIN_8 - description: JPEG HuffMin tables - byte_offset: 368 - fieldset: HUFFMIN_8 - - name: HUFFMIN_9 - description: JPEG HuffMin tables - byte_offset: 372 - fieldset: HUFFMIN_9 - - name: HUFFMIN_10 - description: JPEG HuffMin tables - byte_offset: 376 - fieldset: HUFFMIN_10 - - name: HUFFMIN_11 - description: JPEG HuffMin tables - byte_offset: 380 - fieldset: HUFFMIN_11 - - name: HUFFMIN_12 - description: JPEG HuffMin tables - byte_offset: 384 - fieldset: HUFFMIN_12 - - name: HUFFMIN_13 - description: JPEG HuffMin tables - byte_offset: 388 - fieldset: HUFFMIN_13 - - name: HUFFMIN_14 - description: JPEG HuffMin tables - byte_offset: 392 - fieldset: HUFFMIN_14 - - name: HUFFMIN_15 - description: JPEG HuffMin tables - byte_offset: 396 - fieldset: HUFFMIN_15 - - name: HUFFBASE0 - description: JPEG HuffSymb tables - byte_offset: 400 - fieldset: HUFFBASE0 - - name: HUFFBASE1 - description: JPEG HuffSymb tables - byte_offset: 404 - fieldset: HUFFBASE1 - - name: HUFFBASE2 - description: JPEG HuffSymb tables - byte_offset: 408 - fieldset: HUFFBASE2 - - name: HUFFBASE3 - description: JPEG HuffSymb tables - byte_offset: 412 - fieldset: HUFFBASE3 - - name: HUFFBASE4 - description: JPEG HuffSymb tables - byte_offset: 416 - fieldset: HUFFBASE4 - - name: HUFFBASE5 - description: JPEG HuffSymb tables - byte_offset: 420 - fieldset: HUFFBASE5 - - name: HUFFBASE6 - description: JPEG HuffSymb tables - byte_offset: 424 - fieldset: HUFFBASE6 - - name: HUFFBASE7 - description: JPEG HuffSymb tables - byte_offset: 428 - fieldset: HUFFBASE7 - - name: HUFFBASE8 - description: JPEG HuffSymb tables - byte_offset: 432 - fieldset: HUFFBASE8 - - name: HUFFBASE9 - description: JPEG HuffSymb tables - byte_offset: 436 - fieldset: HUFFBASE9 - - name: HUFFBASE10 - description: JPEG HuffSymb tables - byte_offset: 440 - fieldset: HUFFBASE10 - - name: HUFFBASE11 - description: JPEG HuffSymb tables - byte_offset: 444 - fieldset: HUFFBASE11 - - name: HUFFBASE12 - description: JPEG HuffSymb tables - byte_offset: 448 - fieldset: HUFFBASE12 - - name: HUFFBASE13 - description: JPEG HuffSymb tables - byte_offset: 452 - fieldset: HUFFBASE13 - - name: HUFFBASE14 - description: JPEG HuffSymb tables - byte_offset: 456 - fieldset: HUFFBASE14 - - name: HUFFBASE15 - description: JPEG HuffSymb tables - byte_offset: 460 - fieldset: HUFFBASE15 - - name: HUFFBASE16 - description: JPEG HuffSymb tables - byte_offset: 464 - fieldset: HUFFBASE16 - - name: HUFFBASE17 - description: JPEG HuffSymb tables - byte_offset: 468 - fieldset: HUFFBASE17 - - name: HUFFBASE18 - description: JPEG HuffSymb tables - byte_offset: 472 - fieldset: HUFFBASE18 - - name: HUFFBASE19 - description: JPEG HuffSymb tables - byte_offset: 476 - fieldset: HUFFBASE19 - - name: HUFFBASE20 - description: JPEG HuffSymb tables - byte_offset: 480 - fieldset: HUFFBASE20 - - name: HUFFBASE21 - description: JPEG HuffSymb tables - byte_offset: 484 - fieldset: HUFFBASE21 - - name: HUFFBASE22 - description: JPEG HuffSymb tables - byte_offset: 488 - fieldset: HUFFBASE22 - - name: HUFFBASE23 - description: JPEG HuffSymb tables - byte_offset: 492 - fieldset: HUFFBASE23 - - name: HUFFBASE24 - description: JPEG HuffSymb tables - byte_offset: 496 - fieldset: HUFFBASE24 - - name: HUFFBASE25 - description: JPEG HuffSymb tables - byte_offset: 500 - fieldset: HUFFBASE25 - - name: HUFFBASE26 - description: JPEG HuffSymb tables - byte_offset: 504 - fieldset: HUFFBASE26 - - name: HUFFBASE27 - description: JPEG HuffSymb tables - byte_offset: 508 - fieldset: HUFFBASE27 - - name: HUFFBASE28 - description: JPEG HuffSymb tables - byte_offset: 512 - fieldset: HUFFBASE28 - - name: HUFFBASE29 - description: JPEG HuffSymb tables - byte_offset: 516 - fieldset: HUFFBASE29 - - name: HUFFBASE30 - description: JPEG HuffSymb tables - byte_offset: 520 - fieldset: HUFFBASE30 - - name: HUFFBASE31 - description: JPEG HuffSymb tables - byte_offset: 524 - fieldset: HUFFBASE31 - - name: HUFFSYMB0 - description: JPEG HUFFSYMB tables - byte_offset: 528 - fieldset: HUFFSYMB0 - - name: HUFFSYMB1 - description: JPEG HUFFSYMB tables - byte_offset: 532 - fieldset: HUFFSYMB1 - - name: HUFFSYMB2 - description: JPEG HUFFSYMB tables - byte_offset: 536 - fieldset: HUFFSYMB2 - - name: HUFFSYMB3 - description: JPEG HUFFSYMB tables - byte_offset: 540 - fieldset: HUFFSYMB3 - - name: HUFFSYMB4 - description: JPEG HUFFSYMB tables - byte_offset: 544 - fieldset: HUFFSYMB4 - - name: HUFFSYMB5 - description: JPEG HUFFSYMB tables - byte_offset: 548 - fieldset: HUFFSYMB5 - - name: HUFFSYMB6 - description: JPEG HUFFSYMB tables - byte_offset: 552 - fieldset: HUFFSYMB6 - - name: HUFFSYMB7 - description: JPEG HUFFSYMB tables - byte_offset: 556 - fieldset: HUFFSYMB7 - - name: HUFFSYMB8 - description: JPEG HUFFSYMB tables - byte_offset: 560 - fieldset: HUFFSYMB8 - - name: HUFFSYMB9 - description: JPEG HUFFSYMB tables - byte_offset: 564 - fieldset: HUFFSYMB9 - - name: HUFFSYMB10 - description: JPEG HUFFSYMB tables - byte_offset: 568 - fieldset: HUFFSYMB10 - - name: HUFFSYMB11 - description: JPEG HUFFSYMB tables - byte_offset: 572 - fieldset: HUFFSYMB11 - - name: HUFFSYMB12 - description: JPEG HUFFSYMB tables - byte_offset: 576 - fieldset: HUFFSYMB12 - - name: HUFFSYMB13 - description: JPEG HUFFSYMB tables - byte_offset: 580 - fieldset: HUFFSYMB13 - - name: HUFFSYMB14 - description: JPEG HUFFSYMB tables - byte_offset: 584 - fieldset: HUFFSYMB14 - - name: HUFFSYMB15 - description: JPEG HUFFSYMB tables - byte_offset: 588 - fieldset: HUFFSYMB15 - - name: HUFFSYMB16 - description: JPEG HUFFSYMB tables - byte_offset: 592 - fieldset: HUFFSYMB16 - - name: HUFFSYMB17 - description: JPEG HUFFSYMB tables - byte_offset: 596 - fieldset: HUFFSYMB17 - - name: HUFFSYMB18 - description: JPEG HUFFSYMB tables - byte_offset: 600 - fieldset: HUFFSYMB18 - - name: HUFFSYMB19 - description: JPEG HUFFSYMB tables - byte_offset: 604 - fieldset: HUFFSYMB19 - - name: HUFFSYMB20 - description: JPEG HUFFSYMB tables - byte_offset: 608 - fieldset: HUFFSYMB20 - - name: HUFFSYMB21 - description: JPEG HUFFSYMB tables - byte_offset: 612 - fieldset: HUFFSYMB21 - - name: HUFFSYMB22 - description: JPEG HUFFSYMB tables - byte_offset: 616 - fieldset: HUFFSYMB22 - - name: HUFFSYMB23 - description: JPEG HUFFSYMB tables - byte_offset: 620 - fieldset: HUFFSYMB23 - - name: HUFFSYMB24 - description: JPEG HUFFSYMB tables - byte_offset: 624 - fieldset: HUFFSYMB24 - - name: HUFFSYMB25 - description: JPEG HUFFSYMB tables - byte_offset: 628 - fieldset: HUFFSYMB25 - - name: HUFFSYMB26 - description: JPEG HUFFSYMB tables - byte_offset: 632 - fieldset: HUFFSYMB26 - - name: HUFFSYMB27 - description: JPEG HUFFSYMB tables - byte_offset: 636 - fieldset: HUFFSYMB27 - - name: HUFFSYMB28 - description: JPEG HUFFSYMB tables - byte_offset: 640 - fieldset: HUFFSYMB28 - - name: HUFFSYMB29 - description: JPEG HUFFSYMB tables - byte_offset: 644 - fieldset: HUFFSYMB29 - - name: HUFFSYMB30 - description: JPEG HUFFSYMB tables - byte_offset: 648 - fieldset: HUFFSYMB30 - - name: HUFFSYMB31 - description: JPEG HUFFSYMB tables - byte_offset: 652 - fieldset: HUFFSYMB31 - - name: HUFFSYMB32 - description: JPEG HUFFSYMB tables - byte_offset: 656 - fieldset: HUFFSYMB32 - - name: HUFFSYMB33 - description: JPEG HUFFSYMB tables - byte_offset: 660 - fieldset: HUFFSYMB33 - - name: HUFFSYMB34 - description: JPEG HUFFSYMB tables - byte_offset: 664 - fieldset: HUFFSYMB34 - - name: HUFFSYMB35 - description: JPEG HUFFSYMB tables - byte_offset: 668 - fieldset: HUFFSYMB35 - - name: HUFFSYMB36 - description: JPEG HUFFSYMB tables - byte_offset: 672 - fieldset: HUFFSYMB36 - - name: HUFFSYMB37 - description: JPEG HUFFSYMB tables - byte_offset: 676 - fieldset: HUFFSYMB37 - - name: HUFFSYMB38 - description: JPEG HUFFSYMB tables - byte_offset: 680 - fieldset: HUFFSYMB38 - - name: HUFFSYMB39 - description: JPEG HUFFSYMB tables - byte_offset: 684 - fieldset: HUFFSYMB39 - - name: HUFFSYMB40 - description: JPEG HUFFSYMB tables - byte_offset: 688 - fieldset: HUFFSYMB40 - - name: HUFFSYMB41 - description: JPEG HUFFSYMB tables - byte_offset: 692 - fieldset: HUFFSYMB41 - - name: HUFFSYMB42 - description: JPEG HUFFSYMB tables - byte_offset: 696 - fieldset: HUFFSYMB42 - - name: HUFFSYMB43 - description: JPEG HUFFSYMB tables - byte_offset: 700 - fieldset: HUFFSYMB43 - - name: HUFFSYMB44 - description: JPEG HUFFSYMB tables - byte_offset: 704 - fieldset: HUFFSYMB44 - - name: HUFFSYMB45 - description: JPEG HUFFSYMB tables - byte_offset: 708 - fieldset: HUFFSYMB45 - - name: HUFFSYMB46 - description: JPEG HUFFSYMB tables - byte_offset: 712 - fieldset: HUFFSYMB46 - - name: HUFFSYMB47 - description: JPEG HUFFSYMB tables - byte_offset: 716 - fieldset: HUFFSYMB47 - - name: HUFFSYMB48 - description: JPEG HUFFSYMB tables - byte_offset: 720 - fieldset: HUFFSYMB48 - - name: HUFFSYMB49 - description: JPEG HUFFSYMB tables - byte_offset: 724 - fieldset: HUFFSYMB49 - - name: HUFFSYMB50 - description: JPEG HUFFSYMB tables - byte_offset: 728 - fieldset: HUFFSYMB50 - - name: HUFFSYMB51 - description: JPEG HUFFSYMB tables - byte_offset: 732 - fieldset: HUFFSYMB51 - - name: HUFFSYMB52 - description: JPEG HUFFSYMB tables - byte_offset: 736 - fieldset: HUFFSYMB52 - - name: HUFFSYMB53 - description: JPEG HUFFSYMB tables - byte_offset: 740 - fieldset: HUFFSYMB53 - - name: HUFFSYMB54 - description: JPEG HUFFSYMB tables - byte_offset: 744 - fieldset: HUFFSYMB54 - - name: HUFFSYMB55 - description: JPEG HUFFSYMB tables - byte_offset: 748 - fieldset: HUFFSYMB55 - - name: HUFFSYMB56 - description: JPEG HUFFSYMB tables - byte_offset: 752 - fieldset: HUFFSYMB56 - - name: HUFFSYMB57 - description: JPEG HUFFSYMB tables - byte_offset: 756 - fieldset: HUFFSYMB57 - - name: HUFFSYMB58 - description: JPEG HUFFSYMB tables - byte_offset: 760 - fieldset: HUFFSYMB58 - - name: HUFFSYMB59 - description: JPEG HUFFSYMB tables - byte_offset: 764 - fieldset: HUFFSYMB59 - - name: HUFFSYMB60 - description: JPEG HUFFSYMB tables - byte_offset: 768 - fieldset: HUFFSYMB60 - - name: HUFFSYMB61 - description: JPEG HUFFSYMB tables - byte_offset: 772 - fieldset: HUFFSYMB61 - - name: HUFFSYMB62 - description: JPEG HUFFSYMB tables - byte_offset: 776 - fieldset: HUFFSYMB62 - - name: HUFFSYMB63 - description: JPEG HUFFSYMB tables - byte_offset: 780 - fieldset: HUFFSYMB63 - - name: HUFFSYMB64 - description: JPEG HUFFSYMB tables - byte_offset: 784 - fieldset: HUFFSYMB64 - - name: HUFFSYMB65 - description: JPEG HUFFSYMB tables - byte_offset: 788 - fieldset: HUFFSYMB65 - - name: HUFFSYMB66 - description: JPEG HUFFSYMB tables - byte_offset: 792 - fieldset: HUFFSYMB66 - - name: HUFFSYMB67 - description: JPEG HUFFSYMB tables - byte_offset: 796 - fieldset: HUFFSYMB67 - - name: HUFFSYMB68 - description: JPEG HUFFSYMB tables - byte_offset: 800 - fieldset: HUFFSYMB68 - - name: HUFFSYMB69 - description: JPEG HUFFSYMB tables - byte_offset: 804 - fieldset: HUFFSYMB69 - - name: HUFFSYMB70 - description: JPEG HUFFSYMB tables - byte_offset: 808 - fieldset: HUFFSYMB70 - - name: HUFFSYMB71 - description: JPEG HUFFSYMB tables - byte_offset: 812 - fieldset: HUFFSYMB71 - - name: HUFFSYMB72 - description: JPEG HUFFSYMB tables - byte_offset: 816 - fieldset: HUFFSYMB72 - - name: HUFFSYMB73 - description: JPEG HUFFSYMB tables - byte_offset: 820 - fieldset: HUFFSYMB73 - - name: HUFFSYMB74 - description: JPEG HUFFSYMB tables - byte_offset: 824 - fieldset: HUFFSYMB74 - - name: HUFFSYMB75 - description: JPEG HUFFSYMB tables - byte_offset: 828 - fieldset: HUFFSYMB75 - - name: HUFFSYMB76 - description: JPEG HUFFSYMB tables - byte_offset: 832 - fieldset: HUFFSYMB76 - - name: HUFFSYMB77 - description: JPEG HUFFSYMB tables - byte_offset: 836 - fieldset: HUFFSYMB77 - - name: HUFFSYMB78 - description: JPEG HUFFSYMB tables - byte_offset: 840 - fieldset: HUFFSYMB78 - - name: HUFFSYMB79 - description: JPEG HUFFSYMB tables - byte_offset: 844 - fieldset: HUFFSYMB79 - - name: HUFFSYMB80 - description: JPEG HUFFSYMB tables - byte_offset: 848 - fieldset: HUFFSYMB80 - - name: HUFFSYMB81 - description: JPEG HUFFSYMB tables - byte_offset: 852 - fieldset: HUFFSYMB81 - - name: HUFFSYMB82 - description: JPEG HUFFSYMB tables - byte_offset: 856 - fieldset: HUFFSYMB82 - - name: HUFFSYMB83 - description: JPEG HUFFSYMB tables - byte_offset: 860 - fieldset: HUFFSYMB83 - - name: DHTMEM0 - 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byte_offset: 1560 - fieldset: HUFFENC_AC0_70 - - name: HUFFENC_AC0_71 - description: "JPEG encoder, AC Huffman table 0" - byte_offset: 1564 - fieldset: HUFFENC_AC0_71 - - name: HUFFENC_AC0_72 - description: "JPEG encoder, AC Huffman table 0" - byte_offset: 1568 - fieldset: HUFFENC_AC0_72 - - name: HUFFENC_AC0_73 - description: "JPEG encoder, AC Huffman table 0" - byte_offset: 1572 - fieldset: HUFFENC_AC0_73 - - name: HUFFENC_AC0_74 - description: "JPEG encoder, AC Huffman table 0" - byte_offset: 1576 - fieldset: HUFFENC_AC0_74 - - name: HUFFENC_AC0_75 - description: "JPEG encoder, AC Huffman table 0" - byte_offset: 1580 - fieldset: HUFFENC_AC0_75 - - name: HUFFENC_AC0_76 - description: "JPEG encoder, AC Huffman table 0" - byte_offset: 1584 - fieldset: HUFFENC_AC0_76 - - name: HUFFENC_AC0_77 - description: "JPEG encoder, AC Huffman table 0" - byte_offset: 1588 - fieldset: HUFFENC_AC0_77 - - name: HUFFENC_AC0_78 - description: "JPEG encoder, AC Huffman table 0" - byte_offset: 1592 - fieldset: HUFFENC_AC0_78 - - name: HUFFENC_AC0_79 - description: "JPEG encoder, AC Huffman table 0" - byte_offset: 1596 - fieldset: HUFFENC_AC0_79 - - name: HUFFENC_AC0_80 - description: "JPEG encoder, AC Huffman table 0" - byte_offset: 1600 - fieldset: HUFFENC_AC0_80 - - name: HUFFENC_AC0_81 - description: "JPEG encoder, AC Huffman table 0" - byte_offset: 1604 - fieldset: HUFFENC_AC0_81 - - name: HUFFENC_AC0_82 - description: "JPEG encoder, AC Huffman table 0" - byte_offset: 1608 - fieldset: HUFFENC_AC0_82 - - name: HUFFENC_AC0_83 - description: "JPEG encoder, AC Huffman table 0" - byte_offset: 1612 - fieldset: HUFFENC_AC0_83 - - name: HUFFENC_AC0_84 - description: "JPEG encoder, AC Huffman table 0" - byte_offset: 1616 - fieldset: HUFFENC_AC0_84 - - name: HUFFENC_AC0_85 - description: "JPEG encoder, AC Huffman table 0" - byte_offset: 1620 - fieldset: HUFFENC_AC0_85 - - name: HUFFENC_AC0_86 - description: "JPEG encoder, AC Huffman table 0" - byte_offset: 1624 - fieldset: HUFFENC_AC0_86 - - name: HUFFENC_AC0_87 - description: "JPEG encoder, AC Huffman table 0" - byte_offset: 1628 - fieldset: HUFFENC_AC0_87 - - name: HUFFENC_AC1_0 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1632 - fieldset: HUFFENC_AC1_0 - - name: HUFFENC_AC1_1 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1636 - fieldset: HUFFENC_AC1_1 - - name: HUFFENC_AC1_2 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1640 - fieldset: HUFFENC_AC1_2 - - name: HUFFENC_AC1_3 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1644 - fieldset: HUFFENC_AC1_3 - - name: HUFFENC_AC1_4 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1648 - fieldset: HUFFENC_AC1_4 - - name: HUFFENC_AC1_5 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1652 - fieldset: HUFFENC_AC1_5 - - name: HUFFENC_AC1_6 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1656 - fieldset: HUFFENC_AC1_6 - - name: HUFFENC_AC1_7 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1660 - fieldset: HUFFENC_AC1_7 - - name: HUFFENC_AC1_8 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1664 - fieldset: HUFFENC_AC1_8 - - name: HUFFENC_AC1_9 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1668 - fieldset: HUFFENC_AC1_9 - - name: HUFFENC_AC1_10 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1672 - fieldset: HUFFENC_AC1_10 - - name: HUFFENC_AC1_11 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1676 - fieldset: HUFFENC_AC1_11 - - name: HUFFENC_AC1_12 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1680 - fieldset: HUFFENC_AC1_12 - - name: HUFFENC_AC1_13 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1684 - fieldset: HUFFENC_AC1_13 - - name: HUFFENC_AC1_14 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1688 - fieldset: HUFFENC_AC1_14 - - name: HUFFENC_AC1_15 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1692 - fieldset: HUFFENC_AC1_15 - - name: HUFFENC_AC1_16 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1696 - fieldset: HUFFENC_AC1_16 - - name: HUFFENC_AC1_17 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1700 - fieldset: HUFFENC_AC1_17 - - name: HUFFENC_AC1_18 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1704 - fieldset: HUFFENC_AC1_18 - - name: HUFFENC_AC1_19 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1708 - fieldset: HUFFENC_AC1_19 - - name: HUFFENC_AC1_20 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1712 - fieldset: HUFFENC_AC1_20 - - name: HUFFENC_AC1_21 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1716 - fieldset: HUFFENC_AC1_21 - - name: HUFFENC_AC1_22 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1720 - fieldset: HUFFENC_AC1_22 - - name: HUFFENC_AC1_23 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1724 - fieldset: HUFFENC_AC1_23 - - name: HUFFENC_AC1_24 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1728 - fieldset: HUFFENC_AC1_24 - - name: HUFFENC_AC1_25 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1732 - fieldset: HUFFENC_AC1_25 - - name: HUFFENC_AC1_26 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1736 - fieldset: HUFFENC_AC1_26 - - name: HUFFENC_AC1_27 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1740 - fieldset: HUFFENC_AC1_27 - - name: HUFFENC_AC1_28 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1744 - fieldset: HUFFENC_AC1_28 - - name: HUFFENC_AC1_29 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1748 - fieldset: HUFFENC_AC1_29 - - name: HUFFENC_AC1_30 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1752 - fieldset: HUFFENC_AC1_30 - - name: HUFFENC_AC1_31 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1756 - fieldset: HUFFENC_AC1_31 - - name: HUFFENC_AC1_32 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1760 - fieldset: HUFFENC_AC1_32 - - name: HUFFENC_AC1_33 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1764 - fieldset: HUFFENC_AC1_33 - - name: HUFFENC_AC1_34 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1768 - fieldset: HUFFENC_AC1_34 - - name: HUFFENC_AC1_35 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1772 - fieldset: HUFFENC_AC1_35 - - name: HUFFENC_AC1_36 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1776 - fieldset: HUFFENC_AC1_36 - - name: HUFFENC_AC1_37 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1780 - fieldset: HUFFENC_AC1_37 - - name: HUFFENC_AC1_38 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1784 - fieldset: HUFFENC_AC1_38 - - name: HUFFENC_AC1_39 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1788 - fieldset: HUFFENC_AC1_39 - - name: HUFFENC_AC1_40 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1792 - fieldset: HUFFENC_AC1_40 - - name: HUFFENC_AC1_41 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1796 - fieldset: HUFFENC_AC1_41 - - name: HUFFENC_AC1_42 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1800 - fieldset: HUFFENC_AC1_42 - - name: HUFFENC_AC1_43 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1804 - fieldset: HUFFENC_AC1_43 - - name: HUFFENC_AC1_44 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1808 - fieldset: HUFFENC_AC1_44 - - name: HUFFENC_AC1_45 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1812 - fieldset: HUFFENC_AC1_45 - - name: HUFFENC_AC1_46 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1816 - fieldset: HUFFENC_AC1_46 - - name: HUFFENC_AC1_47 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1820 - fieldset: HUFFENC_AC1_47 - - name: HUFFENC_AC1_48 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1824 - fieldset: HUFFENC_AC1_48 - - name: HUFFENC_AC1_49 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1828 - fieldset: HUFFENC_AC1_49 - - name: HUFFENC_AC1_50 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1832 - fieldset: HUFFENC_AC1_50 - - name: HUFFENC_AC1_51 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1836 - fieldset: HUFFENC_AC1_51 - - name: HUFFENC_AC1_52 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1840 - fieldset: HUFFENC_AC1_52 - - name: HUFFENC_AC1_53 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1844 - fieldset: HUFFENC_AC1_53 - - name: HUFFENC_AC1_54 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1848 - fieldset: HUFFENC_AC1_54 - - name: HUFFENC_AC1_55 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1852 - fieldset: HUFFENC_AC1_55 - - name: HUFFENC_AC1_56 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1856 - fieldset: HUFFENC_AC1_56 - - name: HUFFENC_AC1_57 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1860 - fieldset: HUFFENC_AC1_57 - - name: HUFFENC_AC1_58 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1864 - fieldset: HUFFENC_AC1_58 - - name: HUFFENC_AC1_59 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1868 - fieldset: HUFFENC_AC1_59 - - name: HUFFENC_AC1_60 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1872 - fieldset: HUFFENC_AC1_60 - - name: HUFFENC_AC1_61 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1876 - fieldset: HUFFENC_AC1_61 - - name: HUFFENC_AC1_62 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1880 - fieldset: HUFFENC_AC1_62 - - name: HUFFENC_AC1_63 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1884 - fieldset: HUFFENC_AC1_63 - - name: HUFFENC_AC1_64 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1888 - fieldset: HUFFENC_AC1_64 - - name: HUFFENC_AC1_65 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1892 - fieldset: HUFFENC_AC1_65 - - name: HUFFENC_AC1_66 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1896 - fieldset: HUFFENC_AC1_66 - - name: HUFFENC_AC1_67 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1900 - fieldset: HUFFENC_AC1_67 - - name: HUFFENC_AC1_68 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1904 - fieldset: HUFFENC_AC1_68 - - name: HUFFENC_AC1_69 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1908 - fieldset: HUFFENC_AC1_69 - - name: HUFFENC_AC1_70 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1912 - fieldset: HUFFENC_AC1_70 - - name: HUFFENC_AC1_71 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1916 - fieldset: HUFFENC_AC1_71 - - name: HUFFENC_AC1_72 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1920 - fieldset: HUFFENC_AC1_72 - - name: HUFFENC_AC1_73 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1924 - fieldset: HUFFENC_AC1_73 - - name: HUFFENC_AC1_74 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1928 - fieldset: HUFFENC_AC1_74 - - name: HUFFENC_AC1_75 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1932 - fieldset: HUFFENC_AC1_75 - - name: HUFFENC_AC1_76 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1936 - fieldset: HUFFENC_AC1_76 - - name: HUFFENC_AC1_77 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1940 - fieldset: HUFFENC_AC1_77 - - name: HUFFENC_AC1_78 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1944 - fieldset: HUFFENC_AC1_78 - - name: HUFFENC_AC1_79 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1948 - fieldset: HUFFENC_AC1_79 - - name: HUFFENC_AC1_80 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1952 - fieldset: HUFFENC_AC1_80 - - name: HUFFENC_AC1_81 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1956 - fieldset: HUFFENC_AC1_81 - - name: HUFFENC_AC1_82 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1960 - fieldset: HUFFENC_AC1_82 - - name: HUFFENC_AC1_83 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1964 - fieldset: HUFFENC_AC1_83 - - name: HUFFENC_AC1_84 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1968 - fieldset: HUFFENC_AC1_84 - - name: HUFFENC_AC1_85 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1972 - fieldset: HUFFENC_AC1_85 - - name: HUFFENC_AC1_86 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1976 - fieldset: HUFFENC_AC1_86 - - name: HUFFENC_AC1_87 - description: "JPEG encoder, AC Huffman table 1" - byte_offset: 1980 - fieldset: HUFFENC_AC1_87 - - name: HUFFENC_DC0_0 - description: "JPEG encoder, DC Huffman table 0" - byte_offset: 1984 - fieldset: HUFFENC_DC0_0 - - name: HUFFENC_DC0_1 - description: "JPEG encoder, DC Huffman table 0" - byte_offset: 1988 - fieldset: HUFFENC_DC0_1 - - name: HUFFENC_DC0_2 - description: "JPEG encoder, DC Huffman table 0" - byte_offset: 1992 - fieldset: HUFFENC_DC0_2 - - name: HUFFENC_DC0_3 - description: "JPEG encoder, DC Huffman table 0" - byte_offset: 1996 - fieldset: HUFFENC_DC0_3 - - name: HUFFENC_DC0_4 - description: "JPEG encoder, DC Huffman table 0" - byte_offset: 2000 - fieldset: HUFFENC_DC0_4 - - name: HUFFENC_DC0_5 - description: "JPEG encoder, DC Huffman table 0" - byte_offset: 2004 - fieldset: HUFFENC_DC0_5 - - name: HUFFENC_DC0_6 - description: "JPEG encoder, DC Huffman table 0" - byte_offset: 2008 - fieldset: HUFFENC_DC0_6 - - name: HUFFENC_DC0_7 - description: "JPEG encoder, DC Huffman table 0" - byte_offset: 2012 - fieldset: HUFFENC_DC0_7 - - name: HUFFENC_DC1_0 - description: "JPEG encoder, DC Huffman table 1" - byte_offset: 2016 - fieldset: HUFFENC_DC1_0 - - name: HUFFENC_DC1_1 - description: "JPEG encoder, DC Huffman table 1" - byte_offset: 2020 - fieldset: HUFFENC_DC1_1 - - name: HUFFENC_DC1_2 - description: "JPEG encoder, DC Huffman table 1" - byte_offset: 2024 - fieldset: HUFFENC_DC1_2 - - name: HUFFENC_DC1_3 - description: "JPEG encoder, DC Huffman table 1" - byte_offset: 2028 - fieldset: HUFFENC_DC1_3 - - name: HUFFENC_DC1_4 - description: "JPEG encoder, DC Huffman table 1" - byte_offset: 2032 - fieldset: HUFFENC_DC1_4 - - name: HUFFENC_DC1_5 - description: "JPEG encoder, DC Huffman table 1" - byte_offset: 2036 - fieldset: HUFFENC_DC1_5 - - name: HUFFENC_DC1_6 - description: "JPEG encoder, DC Huffman table 1" - byte_offset: 2040 - fieldset: HUFFENC_DC1_6 - - name: HUFFENC_DC1_7 - description: "JPEG encoder, DC Huffman table 1" - byte_offset: 2044 - fieldset: HUFFENC_DC1_7 + - name: JPEG_CONFR0 + description: JPEG codec configuration register 0 + byte_offset: 0 + access: Write + fieldset: JPEG_CONFR0 + - name: JPEG_CONFR1 + description: JPEG codec configuration register 1 + byte_offset: 4 + fieldset: JPEG_CONFR1 + - name: JPEG_CONFR2 + description: JPEG codec configuration register 2 + byte_offset: 8 + fieldset: JPEG_CONFR2 + - name: JPEG_CONFR3 + description: JPEG codec configuration register 3 + byte_offset: 12 + fieldset: JPEG_CONFR3 + - name: JPEG_CONFR4 + description: JPEG codec configuration register 4 + byte_offset: 16 + fieldset: JPEG_CONFR4 + - name: JPEG_CONFR5 + description: JPEG codec configuration register 5 + byte_offset: 20 + fieldset: JPEG_CONFR5 + - name: JPEG_CONFR6 + description: JPEG codec configuration register 6 + byte_offset: 24 + fieldset: JPEG_CONFR6 + - name: JPEG_CONFR7 + description: JPEG codec configuration register 7 + byte_offset: 28 + fieldset: JPEG_CONFR7 + - name: JPEG_CR + description: JPEG control register + byte_offset: 48 + fieldset: JPEG_CR + - name: JPEG_SR + description: JPEG status register + byte_offset: 52 + access: Read + fieldset: JPEG_SR + - name: JPEG_CFR + description: JPEG clear flag register + byte_offset: 56 + access: Write + fieldset: JPEG_CFR + - name: JPEG_DIR + description: JPEG data input register + byte_offset: 64 + access: Write + fieldset: JPEG_DIR + - name: JPEG_DOR + description: JPEG data output register + byte_offset: 68 + access: Read + fieldset: JPEG_DOR + - name: QMEM0_0 + description: JPEG quantization tables + byte_offset: 80 + fieldset: QMEM0_0 + - name: QMEM0_1 + description: JPEG quantization tables + byte_offset: 84 + fieldset: QMEM0_1 + - name: QMEM0_2 + description: JPEG quantization tables + byte_offset: 88 + fieldset: QMEM0_2 + - name: QMEM0_3 + description: JPEG quantization tables + byte_offset: 92 + fieldset: QMEM0_3 + - name: QMEM0_4 + description: JPEG quantization tables + byte_offset: 96 + fieldset: QMEM0_4 + - name: QMEM0_5 + description: JPEG quantization tables + byte_offset: 100 + fieldset: QMEM0_5 + - name: QMEM0_6 + description: JPEG quantization tables + byte_offset: 104 + fieldset: QMEM0_6 + - name: QMEM0_7 + description: JPEG quantization tables + byte_offset: 108 + fieldset: QMEM0_7 + - name: QMEM0_8 + description: JPEG quantization tables + byte_offset: 112 + fieldset: QMEM0_8 + - name: QMEM0_9 + description: JPEG quantization tables + byte_offset: 116 + fieldset: QMEM0_9 + - name: QMEM0_10 + description: JPEG quantization tables + byte_offset: 120 + fieldset: QMEM0_10 + - name: QMEM0_11 + description: JPEG quantization tables + byte_offset: 124 + fieldset: QMEM0_11 + - name: QMEM0_12 + description: JPEG quantization tables + byte_offset: 128 + fieldset: QMEM0_12 + - name: QMEM0_13 + description: JPEG quantization tables + byte_offset: 132 + fieldset: QMEM0_13 + - name: QMEM0_14 + description: JPEG quantization tables + byte_offset: 136 + fieldset: QMEM0_14 + - name: QMEM0_15 + description: JPEG quantization tables + byte_offset: 140 + fieldset: QMEM0_15 + - name: QMEM1_0 + description: JPEG quantization tables + byte_offset: 144 + fieldset: QMEM1_0 + - name: QMEM1_1 + description: JPEG quantization tables + byte_offset: 148 + fieldset: QMEM1_1 + - name: QMEM1_2 + description: JPEG quantization tables + byte_offset: 152 + fieldset: QMEM1_2 + - name: QMEM1_3 + description: JPEG quantization tables + byte_offset: 156 + fieldset: QMEM1_3 + - name: QMEM1_4 + description: JPEG quantization tables + byte_offset: 160 + fieldset: QMEM1_4 + - name: QMEM1_5 + description: JPEG quantization tables + byte_offset: 164 + fieldset: QMEM1_5 + - name: QMEM1_6 + description: JPEG quantization tables + byte_offset: 168 + fieldset: QMEM1_6 + - name: QMEM1_7 + description: JPEG quantization tables + byte_offset: 172 + fieldset: QMEM1_7 + - name: QMEM1_8 + description: JPEG quantization tables + byte_offset: 176 + fieldset: QMEM1_8 + - name: QMEM1_9 + description: JPEG quantization tables + byte_offset: 180 + fieldset: QMEM1_9 + - name: QMEM1_10 + description: JPEG quantization tables + byte_offset: 184 + fieldset: QMEM1_10 + - name: QMEM1_11 + description: JPEG quantization tables + byte_offset: 188 + fieldset: QMEM1_11 + - name: QMEM1_12 + description: JPEG quantization tables + byte_offset: 192 + fieldset: QMEM1_12 + - name: QMEM1_13 + description: JPEG quantization tables + byte_offset: 196 + fieldset: QMEM1_13 + - name: QMEM1_14 + description: JPEG quantization tables + byte_offset: 200 + fieldset: QMEM1_14 + - name: QMEM1_15 + description: JPEG quantization tables + byte_offset: 204 + fieldset: QMEM1_15 + - name: QMEM2_0 + description: JPEG quantization tables + byte_offset: 208 + fieldset: QMEM2_0 + - name: QMEM2_1 + description: JPEG quantization tables + byte_offset: 212 + fieldset: QMEM2_1 + - name: QMEM2_2 + description: JPEG quantization tables + byte_offset: 216 + fieldset: QMEM2_2 + - name: QMEM2_3 + description: JPEG quantization tables + byte_offset: 220 + fieldset: QMEM2_3 + - name: QMEM2_4 + description: JPEG quantization tables + byte_offset: 224 + fieldset: QMEM2_4 + - name: QMEM2_5 + description: JPEG quantization tables + byte_offset: 228 + fieldset: QMEM2_5 + - name: QMEM2_6 + description: JPEG quantization tables + byte_offset: 232 + fieldset: QMEM2_6 + - name: QMEM2_7 + description: JPEG quantization tables + byte_offset: 236 + fieldset: QMEM2_7 + - name: QMEM2_8 + description: JPEG quantization tables + byte_offset: 240 + fieldset: QMEM2_8 + - name: QMEM2_9 + description: JPEG quantization tables + byte_offset: 244 + fieldset: QMEM2_9 + - name: QMEM2_10 + description: JPEG quantization tables + byte_offset: 248 + fieldset: QMEM2_10 + - name: QMEM2_11 + description: JPEG quantization tables + byte_offset: 252 + fieldset: QMEM2_11 + - name: QMEM2_12 + description: JPEG quantization tables + byte_offset: 256 + fieldset: QMEM2_12 + - name: QMEM2_13 + description: JPEG quantization tables + byte_offset: 260 + fieldset: QMEM2_13 + - name: QMEM2_14 + description: JPEG quantization tables + byte_offset: 264 + fieldset: QMEM2_14 + - name: QMEM2_15 + description: JPEG quantization tables + byte_offset: 268 + fieldset: QMEM2_15 + - name: QMEM3_0 + description: JPEG quantization tables + byte_offset: 272 + fieldset: QMEM3_0 + - name: QMEM3_1 + description: JPEG quantization tables + byte_offset: 276 + fieldset: QMEM3_1 + - name: QMEM3_2 + description: JPEG quantization tables + byte_offset: 280 + fieldset: QMEM3_2 + - name: QMEM3_3 + description: JPEG quantization tables + byte_offset: 284 + fieldset: QMEM3_3 + - name: QMEM3_4 + description: JPEG quantization tables + byte_offset: 288 + fieldset: QMEM3_4 + - name: QMEM3_5 + description: JPEG quantization tables + byte_offset: 292 + fieldset: QMEM3_5 + - name: QMEM3_6 + description: JPEG quantization tables + byte_offset: 296 + fieldset: QMEM3_6 + - name: QMEM3_7 + description: JPEG quantization tables + byte_offset: 300 + fieldset: QMEM3_7 + - name: QMEM3_8 + description: JPEG quantization tables + byte_offset: 304 + fieldset: QMEM3_8 + - name: QMEM3_9 + description: JPEG quantization tables + byte_offset: 308 + fieldset: QMEM3_9 + - name: QMEM3_10 + description: JPEG quantization tables + byte_offset: 312 + fieldset: QMEM3_10 + - name: QMEM3_11 + description: JPEG quantization tables + byte_offset: 316 + fieldset: QMEM3_11 + - name: QMEM3_12 + description: JPEG quantization tables + byte_offset: 320 + fieldset: QMEM3_12 + - name: QMEM3_13 + description: JPEG quantization tables + byte_offset: 324 + fieldset: QMEM3_13 + - name: QMEM3_14 + description: JPEG quantization tables + byte_offset: 328 + fieldset: QMEM3_14 + - name: QMEM3_15 + description: JPEG quantization tables + byte_offset: 332 + fieldset: QMEM3_15 + - name: HUFFMIN_0 + description: JPEG HuffMin tables + byte_offset: 336 + fieldset: HUFFMIN_0 + - name: HUFFMIN_1 + description: JPEG HuffMin tables + byte_offset: 340 + fieldset: HUFFMIN_1 + - name: HUFFMIN_2 + description: JPEG HuffMin tables + byte_offset: 344 + fieldset: HUFFMIN_2 + - name: HUFFMIN_3 + description: JPEG HuffMin tables + byte_offset: 348 + fieldset: HUFFMIN_3 + - name: HUFFMIN_4 + description: JPEG HuffMin tables + byte_offset: 352 + fieldset: HUFFMIN_4 + - name: HUFFMIN_5 + description: JPEG HuffMin tables + byte_offset: 356 + fieldset: HUFFMIN_5 + - name: HUFFMIN_6 + description: JPEG HuffMin tables + byte_offset: 360 + fieldset: HUFFMIN_6 + - name: HUFFMIN_7 + description: JPEG HuffMin tables + byte_offset: 364 + fieldset: HUFFMIN_7 + - name: HUFFMIN_8 + description: JPEG HuffMin tables + byte_offset: 368 + fieldset: HUFFMIN_8 + - name: HUFFMIN_9 + description: JPEG HuffMin tables + byte_offset: 372 + fieldset: HUFFMIN_9 + - name: HUFFMIN_10 + description: JPEG HuffMin tables + byte_offset: 376 + fieldset: HUFFMIN_10 + - name: HUFFMIN_11 + description: JPEG HuffMin tables + byte_offset: 380 + fieldset: HUFFMIN_11 + - name: HUFFMIN_12 + description: JPEG HuffMin tables + byte_offset: 384 + fieldset: HUFFMIN_12 + - name: HUFFMIN_13 + description: JPEG HuffMin tables + byte_offset: 388 + fieldset: HUFFMIN_13 + - name: HUFFMIN_14 + description: JPEG HuffMin tables + byte_offset: 392 + fieldset: HUFFMIN_14 + - name: HUFFMIN_15 + description: JPEG HuffMin tables + byte_offset: 396 + fieldset: HUFFMIN_15 + - name: HUFFBASE0 + description: JPEG HuffSymb tables + byte_offset: 400 + fieldset: HUFFBASE0 + - name: HUFFBASE1 + description: JPEG HuffSymb tables + byte_offset: 404 + fieldset: HUFFBASE1 + - name: HUFFBASE2 + description: JPEG HuffSymb tables + byte_offset: 408 + fieldset: HUFFBASE2 + - name: HUFFBASE3 + description: JPEG HuffSymb tables + byte_offset: 412 + fieldset: HUFFBASE3 + - name: HUFFBASE4 + description: JPEG HuffSymb tables + byte_offset: 416 + fieldset: HUFFBASE4 + - name: HUFFBASE5 + description: JPEG HuffSymb tables + byte_offset: 420 + fieldset: HUFFBASE5 + - name: HUFFBASE6 + description: JPEG HuffSymb tables + byte_offset: 424 + fieldset: HUFFBASE6 + - name: HUFFBASE7 + description: JPEG HuffSymb tables + byte_offset: 428 + fieldset: HUFFBASE7 + - name: HUFFBASE8 + description: JPEG HuffSymb tables + byte_offset: 432 + fieldset: HUFFBASE8 + - name: HUFFBASE9 + description: JPEG HuffSymb tables + byte_offset: 436 + fieldset: HUFFBASE9 + - name: HUFFBASE10 + description: JPEG HuffSymb tables + byte_offset: 440 + fieldset: HUFFBASE10 + - name: HUFFBASE11 + description: JPEG HuffSymb tables + byte_offset: 444 + fieldset: HUFFBASE11 + - name: HUFFBASE12 + description: JPEG HuffSymb tables + byte_offset: 448 + fieldset: HUFFBASE12 + - name: HUFFBASE13 + description: JPEG HuffSymb tables + byte_offset: 452 + fieldset: HUFFBASE13 + - name: HUFFBASE14 + description: JPEG HuffSymb tables + byte_offset: 456 + fieldset: HUFFBASE14 + - name: HUFFBASE15 + description: JPEG HuffSymb tables + byte_offset: 460 + fieldset: HUFFBASE15 + - name: HUFFBASE16 + description: JPEG HuffSymb tables + byte_offset: 464 + fieldset: HUFFBASE16 + - name: HUFFBASE17 + description: JPEG HuffSymb tables + byte_offset: 468 + fieldset: HUFFBASE17 + - name: HUFFBASE18 + description: JPEG HuffSymb tables + byte_offset: 472 + fieldset: HUFFBASE18 + - name: HUFFBASE19 + description: JPEG HuffSymb tables + byte_offset: 476 + fieldset: HUFFBASE19 + - name: HUFFBASE20 + description: JPEG HuffSymb tables + byte_offset: 480 + fieldset: HUFFBASE20 + - name: HUFFBASE21 + description: JPEG HuffSymb tables + byte_offset: 484 + fieldset: HUFFBASE21 + - name: HUFFBASE22 + description: JPEG HuffSymb tables + byte_offset: 488 + fieldset: HUFFBASE22 + - name: HUFFBASE23 + description: JPEG HuffSymb tables + byte_offset: 492 + fieldset: HUFFBASE23 + - name: HUFFBASE24 + description: JPEG HuffSymb tables + byte_offset: 496 + fieldset: HUFFBASE24 + - name: HUFFBASE25 + description: JPEG HuffSymb tables + byte_offset: 500 + fieldset: HUFFBASE25 + - name: HUFFBASE26 + description: JPEG HuffSymb tables + byte_offset: 504 + fieldset: HUFFBASE26 + - name: HUFFBASE27 + description: JPEG HuffSymb tables + byte_offset: 508 + fieldset: HUFFBASE27 + - name: HUFFBASE28 + description: JPEG HuffSymb tables + byte_offset: 512 + fieldset: HUFFBASE28 + - name: HUFFBASE29 + description: JPEG HuffSymb tables + byte_offset: 516 + fieldset: HUFFBASE29 + - name: HUFFBASE30 + description: JPEG HuffSymb tables + byte_offset: 520 + fieldset: HUFFBASE30 + - name: HUFFBASE31 + description: JPEG HuffSymb tables + byte_offset: 524 + fieldset: HUFFBASE31 + - name: HUFFSYMB0 + description: JPEG HUFFSYMB tables + byte_offset: 528 + fieldset: HUFFSYMB0 + - name: HUFFSYMB1 + description: JPEG HUFFSYMB tables + byte_offset: 532 + fieldset: HUFFSYMB1 + - name: HUFFSYMB2 + description: JPEG HUFFSYMB tables + byte_offset: 536 + fieldset: HUFFSYMB2 + - name: HUFFSYMB3 + description: JPEG HUFFSYMB tables + byte_offset: 540 + fieldset: HUFFSYMB3 + - name: HUFFSYMB4 + description: JPEG HUFFSYMB tables + byte_offset: 544 + fieldset: HUFFSYMB4 + - name: HUFFSYMB5 + description: JPEG HUFFSYMB tables + byte_offset: 548 + fieldset: HUFFSYMB5 + - name: HUFFSYMB6 + description: JPEG HUFFSYMB tables + byte_offset: 552 + fieldset: HUFFSYMB6 + - name: HUFFSYMB7 + description: JPEG HUFFSYMB tables + byte_offset: 556 + fieldset: HUFFSYMB7 + - name: HUFFSYMB8 + description: JPEG HUFFSYMB tables + byte_offset: 560 + fieldset: HUFFSYMB8 + - name: HUFFSYMB9 + description: JPEG HUFFSYMB tables + byte_offset: 564 + fieldset: HUFFSYMB9 + - name: HUFFSYMB10 + description: JPEG HUFFSYMB tables + byte_offset: 568 + fieldset: HUFFSYMB10 + - name: HUFFSYMB11 + description: JPEG HUFFSYMB tables + byte_offset: 572 + fieldset: HUFFSYMB11 + - name: HUFFSYMB12 + description: JPEG HUFFSYMB tables + byte_offset: 576 + fieldset: HUFFSYMB12 + - name: HUFFSYMB13 + description: JPEG HUFFSYMB tables + byte_offset: 580 + fieldset: HUFFSYMB13 + - name: HUFFSYMB14 + description: JPEG HUFFSYMB tables + byte_offset: 584 + fieldset: HUFFSYMB14 + - name: HUFFSYMB15 + description: JPEG HUFFSYMB tables + byte_offset: 588 + fieldset: HUFFSYMB15 + - name: HUFFSYMB16 + description: JPEG HUFFSYMB tables + byte_offset: 592 + fieldset: HUFFSYMB16 + - name: HUFFSYMB17 + description: JPEG HUFFSYMB tables + byte_offset: 596 + fieldset: HUFFSYMB17 + - name: HUFFSYMB18 + description: JPEG HUFFSYMB tables + byte_offset: 600 + fieldset: HUFFSYMB18 + - name: HUFFSYMB19 + description: JPEG HUFFSYMB tables + byte_offset: 604 + fieldset: HUFFSYMB19 + - name: HUFFSYMB20 + description: JPEG HUFFSYMB tables + byte_offset: 608 + fieldset: HUFFSYMB20 + - name: HUFFSYMB21 + description: JPEG HUFFSYMB tables + byte_offset: 612 + fieldset: HUFFSYMB21 + - name: HUFFSYMB22 + description: JPEG HUFFSYMB tables + byte_offset: 616 + fieldset: HUFFSYMB22 + - name: HUFFSYMB23 + description: JPEG HUFFSYMB tables + byte_offset: 620 + fieldset: HUFFSYMB23 + - name: HUFFSYMB24 + description: JPEG HUFFSYMB tables + byte_offset: 624 + fieldset: HUFFSYMB24 + - name: HUFFSYMB25 + description: JPEG HUFFSYMB tables + byte_offset: 628 + fieldset: HUFFSYMB25 + - name: HUFFSYMB26 + description: JPEG HUFFSYMB tables + byte_offset: 632 + fieldset: HUFFSYMB26 + - name: HUFFSYMB27 + description: JPEG HUFFSYMB tables + byte_offset: 636 + fieldset: HUFFSYMB27 + - name: HUFFSYMB28 + description: JPEG HUFFSYMB tables + byte_offset: 640 + fieldset: HUFFSYMB28 + - name: HUFFSYMB29 + description: JPEG HUFFSYMB tables + byte_offset: 644 + fieldset: HUFFSYMB29 + - name: HUFFSYMB30 + description: JPEG HUFFSYMB tables + byte_offset: 648 + fieldset: HUFFSYMB30 + - name: HUFFSYMB31 + description: JPEG HUFFSYMB tables + byte_offset: 652 + fieldset: HUFFSYMB31 + - name: HUFFSYMB32 + description: JPEG HUFFSYMB tables + byte_offset: 656 + fieldset: HUFFSYMB32 + - name: HUFFSYMB33 + description: JPEG HUFFSYMB tables + byte_offset: 660 + fieldset: HUFFSYMB33 + - name: HUFFSYMB34 + description: JPEG HUFFSYMB tables + byte_offset: 664 + fieldset: HUFFSYMB34 + - name: HUFFSYMB35 + description: JPEG HUFFSYMB tables + byte_offset: 668 + fieldset: HUFFSYMB35 + - name: HUFFSYMB36 + description: JPEG HUFFSYMB tables + byte_offset: 672 + fieldset: HUFFSYMB36 + - name: HUFFSYMB37 + description: JPEG HUFFSYMB tables + byte_offset: 676 + fieldset: HUFFSYMB37 + - name: HUFFSYMB38 + description: JPEG HUFFSYMB tables + byte_offset: 680 + fieldset: HUFFSYMB38 + - name: HUFFSYMB39 + description: JPEG HUFFSYMB tables + byte_offset: 684 + fieldset: HUFFSYMB39 + - name: HUFFSYMB40 + description: JPEG HUFFSYMB tables + byte_offset: 688 + fieldset: HUFFSYMB40 + - name: HUFFSYMB41 + description: JPEG HUFFSYMB tables + byte_offset: 692 + fieldset: HUFFSYMB41 + - name: HUFFSYMB42 + description: JPEG HUFFSYMB tables + byte_offset: 696 + fieldset: HUFFSYMB42 + - name: HUFFSYMB43 + description: JPEG HUFFSYMB tables + byte_offset: 700 + fieldset: HUFFSYMB43 + - name: HUFFSYMB44 + description: JPEG HUFFSYMB tables + byte_offset: 704 + fieldset: HUFFSYMB44 + - name: HUFFSYMB45 + description: JPEG HUFFSYMB tables + byte_offset: 708 + fieldset: HUFFSYMB45 + - name: HUFFSYMB46 + description: JPEG HUFFSYMB tables + byte_offset: 712 + fieldset: HUFFSYMB46 + - name: HUFFSYMB47 + description: JPEG HUFFSYMB tables + byte_offset: 716 + fieldset: HUFFSYMB47 + - name: HUFFSYMB48 + description: JPEG HUFFSYMB tables + byte_offset: 720 + fieldset: HUFFSYMB48 + - name: HUFFSYMB49 + description: JPEG HUFFSYMB tables + byte_offset: 724 + fieldset: HUFFSYMB49 + - name: HUFFSYMB50 + description: JPEG HUFFSYMB tables + byte_offset: 728 + fieldset: HUFFSYMB50 + - name: HUFFSYMB51 + description: JPEG HUFFSYMB tables + byte_offset: 732 + fieldset: HUFFSYMB51 + - name: HUFFSYMB52 + description: JPEG HUFFSYMB tables + byte_offset: 736 + fieldset: HUFFSYMB52 + - name: HUFFSYMB53 + description: JPEG HUFFSYMB tables + byte_offset: 740 + fieldset: HUFFSYMB53 + - name: HUFFSYMB54 + description: JPEG HUFFSYMB tables + byte_offset: 744 + fieldset: HUFFSYMB54 + - name: HUFFSYMB55 + description: JPEG HUFFSYMB tables + byte_offset: 748 + fieldset: HUFFSYMB55 + - name: HUFFSYMB56 + description: JPEG HUFFSYMB tables + byte_offset: 752 + fieldset: HUFFSYMB56 + - name: HUFFSYMB57 + description: JPEG HUFFSYMB tables + byte_offset: 756 + fieldset: HUFFSYMB57 + - name: HUFFSYMB58 + description: JPEG HUFFSYMB tables + byte_offset: 760 + fieldset: HUFFSYMB58 + - name: HUFFSYMB59 + description: JPEG HUFFSYMB tables + byte_offset: 764 + fieldset: HUFFSYMB59 + - name: HUFFSYMB60 + description: JPEG HUFFSYMB tables + byte_offset: 768 + fieldset: HUFFSYMB60 + - name: HUFFSYMB61 + description: JPEG HUFFSYMB tables + byte_offset: 772 + fieldset: HUFFSYMB61 + - name: HUFFSYMB62 + description: JPEG HUFFSYMB tables + byte_offset: 776 + fieldset: HUFFSYMB62 + - name: HUFFSYMB63 + description: JPEG HUFFSYMB tables + byte_offset: 780 + fieldset: HUFFSYMB63 + - name: HUFFSYMB64 + description: JPEG HUFFSYMB tables + byte_offset: 784 + fieldset: HUFFSYMB64 + - name: HUFFSYMB65 + description: JPEG HUFFSYMB tables + byte_offset: 788 + fieldset: HUFFSYMB65 + - name: HUFFSYMB66 + description: JPEG HUFFSYMB tables + byte_offset: 792 + fieldset: HUFFSYMB66 + - name: HUFFSYMB67 + description: JPEG HUFFSYMB tables + byte_offset: 796 + fieldset: HUFFSYMB67 + - name: HUFFSYMB68 + description: JPEG HUFFSYMB tables + byte_offset: 800 + fieldset: HUFFSYMB68 + - name: HUFFSYMB69 + description: JPEG HUFFSYMB tables + byte_offset: 804 + fieldset: HUFFSYMB69 + - name: HUFFSYMB70 + description: JPEG HUFFSYMB tables + byte_offset: 808 + fieldset: HUFFSYMB70 + - name: HUFFSYMB71 + description: JPEG HUFFSYMB tables + byte_offset: 812 + fieldset: HUFFSYMB71 + - name: HUFFSYMB72 + description: JPEG HUFFSYMB tables + byte_offset: 816 + fieldset: HUFFSYMB72 + - name: HUFFSYMB73 + description: JPEG HUFFSYMB tables + byte_offset: 820 + fieldset: HUFFSYMB73 + - name: HUFFSYMB74 + description: JPEG HUFFSYMB tables + byte_offset: 824 + fieldset: HUFFSYMB74 + - name: HUFFSYMB75 + description: JPEG HUFFSYMB tables + byte_offset: 828 + fieldset: HUFFSYMB75 + - name: HUFFSYMB76 + description: JPEG HUFFSYMB tables + byte_offset: 832 + fieldset: HUFFSYMB76 + - name: HUFFSYMB77 + description: JPEG HUFFSYMB tables + byte_offset: 836 + fieldset: HUFFSYMB77 + - name: HUFFSYMB78 + description: JPEG HUFFSYMB tables + byte_offset: 840 + fieldset: HUFFSYMB78 + - name: HUFFSYMB79 + description: JPEG HUFFSYMB tables + byte_offset: 844 + fieldset: HUFFSYMB79 + - name: HUFFSYMB80 + description: JPEG HUFFSYMB tables + byte_offset: 848 + fieldset: HUFFSYMB80 + - name: HUFFSYMB81 + description: JPEG HUFFSYMB tables + byte_offset: 852 + fieldset: HUFFSYMB81 + - name: HUFFSYMB82 + description: JPEG HUFFSYMB tables + byte_offset: 856 + fieldset: HUFFSYMB82 + - name: HUFFSYMB83 + description: JPEG HUFFSYMB tables + byte_offset: 860 + fieldset: HUFFSYMB83 + - name: DHTMEM0 + description: JPEG DHTMem tables + byte_offset: 864 + fieldset: DHTMEM0 + - name: DHTMEM2 + description: JPEG DHTMem tables + byte_offset: 868 + fieldset: DHTMEM2 + - name: DHTMEM3 + description: JPEG DHTMem tables + byte_offset: 872 + fieldset: DHTMEM3 + - name: DHTMEM4 + description: JPEG DHTMem tables + byte_offset: 876 + fieldset: DHTMEM4 + - name: DHTMEM5 + description: JPEG DHTMem tables + byte_offset: 880 + fieldset: DHTMEM5 + - name: DHTMEM6 + description: JPEG DHTMem tables + byte_offset: 884 + fieldset: DHTMEM6 + - name: DHTMEM7 + description: JPEG DHTMem tables + byte_offset: 888 + fieldset: DHTMEM7 + - name: DHTMEM8 + description: JPEG DHTMem tables + byte_offset: 892 + fieldset: DHTMEM8 + - name: DHTMEM9 + description: JPEG DHTMem tables + byte_offset: 896 + fieldset: DHTMEM9 + - name: DHTMEM10 + description: JPEG DHTMem tables + byte_offset: 900 + fieldset: DHTMEM10 + - name: DHTMEM11 + description: JPEG DHTMem tables + byte_offset: 904 + fieldset: DHTMEM11 + - name: DHTMEM12 + description: JPEG DHTMem tables + byte_offset: 908 + fieldset: DHTMEM12 + - name: DHTMEM13 + description: JPEG DHTMem tables + byte_offset: 912 + fieldset: DHTMEM13 + - name: DHTMEM14 + description: JPEG DHTMem tables + byte_offset: 916 + fieldset: DHTMEM14 + - name: DHTMEM15 + description: JPEG DHTMem tables + byte_offset: 920 + fieldset: DHTMEM15 + - name: DHTMEM16 + description: JPEG DHTMem tables + byte_offset: 924 + fieldset: DHTMEM16 + - name: DHTMEM17 + description: JPEG DHTMem tables + byte_offset: 928 + fieldset: DHTMEM17 + - name: DHTMEM18 + description: JPEG DHTMem tables + byte_offset: 932 + fieldset: DHTMEM18 + - name: DHTMEM19 + description: JPEG DHTMem tables + byte_offset: 936 + fieldset: DHTMEM19 + - name: DHTMEM20 + description: JPEG DHTMem tables + byte_offset: 940 + fieldset: DHTMEM20 + - name: DHTMEM21 + description: JPEG DHTMem tables + byte_offset: 944 + fieldset: DHTMEM21 + - name: DHTMEM22 + description: JPEG DHTMem tables + byte_offset: 948 + fieldset: DHTMEM22 + - name: DHTMEM23 + description: JPEG DHTMem tables + byte_offset: 952 + fieldset: DHTMEM23 + - name: DHTMEM24 + description: JPEG DHTMem tables + byte_offset: 956 + fieldset: DHTMEM24 + - name: DHTMEM25 + description: JPEG DHTMem tables + byte_offset: 960 + fieldset: DHTMEM25 + - name: DHTMEM26 + description: JPEG DHTMem tables + byte_offset: 964 + fieldset: DHTMEM26 + - name: DHTMEM27 + description: JPEG DHTMem tables + byte_offset: 968 + fieldset: DHTMEM27 + - name: DHTMEM28 + description: JPEG DHTMem tables + byte_offset: 972 + fieldset: DHTMEM28 + - name: DHTMEM29 + description: JPEG DHTMem tables + byte_offset: 976 + fieldset: DHTMEM29 + - name: DHTMEM30 + description: JPEG DHTMem tables + byte_offset: 980 + fieldset: DHTMEM30 + - name: DHTMEM31 + description: JPEG DHTMem tables + byte_offset: 984 + fieldset: DHTMEM31 + - name: DHTMEM32 + description: JPEG DHTMem tables + byte_offset: 988 + fieldset: DHTMEM32 + - name: DHTMEM33 + description: JPEG DHTMem tables + byte_offset: 992 + fieldset: DHTMEM33 + - name: DHTMEM34 + description: JPEG DHTMem tables + byte_offset: 996 + fieldset: DHTMEM34 + - name: DHTMEM35 + description: JPEG DHTMem tables + byte_offset: 1000 + fieldset: DHTMEM35 + - name: DHTMEM36 + description: JPEG DHTMem tables + byte_offset: 1004 + fieldset: DHTMEM36 + - name: DHTMEM37 + description: JPEG DHTMem tables + byte_offset: 1008 + fieldset: DHTMEM37 + - name: DHTMEM38 + description: JPEG DHTMem tables + byte_offset: 1012 + fieldset: DHTMEM38 + - name: DHTMEM39 + description: JPEG DHTMem tables + byte_offset: 1016 + fieldset: DHTMEM39 + - name: DHTMEM40 + description: JPEG DHTMem tables + byte_offset: 1020 + fieldset: DHTMEM40 + - name: DHTMEM41 + description: JPEG DHTMem tables + byte_offset: 1024 + fieldset: DHTMEM41 + - name: DHTMEM42 + description: JPEG DHTMem tables + byte_offset: 1028 + fieldset: DHTMEM42 + - name: DHTMEM43 + description: JPEG DHTMem tables + byte_offset: 1032 + fieldset: DHTMEM43 + - name: DHTMEM44 + description: JPEG DHTMem tables + byte_offset: 1036 + fieldset: DHTMEM44 + - name: DHTMEM45 + description: JPEG DHTMem tables + byte_offset: 1040 + fieldset: DHTMEM45 + - name: DHTMEM46 + description: JPEG DHTMem tables + byte_offset: 1044 + fieldset: DHTMEM46 + - name: DHTMEM47 + description: JPEG DHTMem tables + byte_offset: 1048 + fieldset: DHTMEM47 + - name: DHTMEM48 + description: JPEG DHTMem tables + byte_offset: 1052 + fieldset: DHTMEM48 + - name: DHTMEM49 + description: JPEG DHTMem tables + byte_offset: 1056 + fieldset: DHTMEM49 + - name: DHTMEM50 + description: JPEG DHTMem tables + byte_offset: 1060 + fieldset: DHTMEM50 + - name: DHTMEM51 + description: JPEG DHTMem tables + byte_offset: 1064 + fieldset: DHTMEM51 + - name: DHTMEM52 + description: JPEG DHTMem tables + byte_offset: 1068 + fieldset: DHTMEM52 + - name: DHTMEM53 + description: JPEG DHTMem tables + byte_offset: 1072 + fieldset: DHTMEM53 + - name: DHTMEM54 + description: JPEG DHTMem tables + byte_offset: 1076 + fieldset: DHTMEM54 + - name: DHTMEM55 + description: JPEG DHTMem tables + byte_offset: 1080 + fieldset: DHTMEM55 + - name: DHTMEM56 + description: JPEG DHTMem tables + byte_offset: 1084 + fieldset: DHTMEM56 + - name: DHTMEM57 + description: JPEG DHTMem tables + byte_offset: 1088 + fieldset: DHTMEM57 + - name: DHTMEM58 + description: JPEG DHTMem tables + byte_offset: 1092 + fieldset: DHTMEM58 + - name: DHTMEM59 + description: JPEG DHTMem tables + byte_offset: 1096 + fieldset: DHTMEM59 + - name: DHTMEM60 + description: JPEG DHTMem tables + byte_offset: 1100 + fieldset: DHTMEM60 + - name: DHTMEM61 + description: JPEG DHTMem tables + byte_offset: 1104 + fieldset: DHTMEM61 + - name: DHTMEM62 + description: JPEG DHTMem tables + byte_offset: 1108 + fieldset: DHTMEM62 + - name: DHTMEM63 + description: JPEG DHTMem tables + byte_offset: 1112 + fieldset: DHTMEM63 + - name: DHTMEM64 + description: JPEG DHTMem tables + byte_offset: 1116 + fieldset: DHTMEM64 + - name: DHTMEM65 + description: JPEG DHTMem tables + byte_offset: 1120 + fieldset: DHTMEM65 + - name: DHTMEM66 + description: JPEG DHTMem tables + byte_offset: 1124 + fieldset: DHTMEM66 + - name: DHTMEM67 + description: JPEG DHTMem tables + byte_offset: 1128 + fieldset: DHTMEM67 + - name: DHTMEM68 + description: JPEG DHTMem tables + byte_offset: 1132 + fieldset: DHTMEM68 + - name: DHTMEM69 + description: JPEG DHTMem tables + byte_offset: 1136 + fieldset: DHTMEM69 + - name: DHTMEM70 + description: JPEG DHTMem tables + byte_offset: 1140 + fieldset: DHTMEM70 + - name: DHTMEM71 + description: JPEG DHTMem tables + byte_offset: 1144 + fieldset: DHTMEM71 + - name: DHTMEM72 + description: JPEG DHTMem tables + byte_offset: 1148 + fieldset: DHTMEM72 + - name: DHTMEM73 + description: JPEG DHTMem tables + byte_offset: 1152 + fieldset: DHTMEM73 + - name: DHTMEM74 + description: JPEG DHTMem tables + byte_offset: 1156 + fieldset: DHTMEM74 + - name: DHTMEM75 + description: JPEG DHTMem tables + byte_offset: 1160 + fieldset: DHTMEM75 + - name: DHTMEM76 + description: JPEG DHTMem tables + byte_offset: 1164 + fieldset: DHTMEM76 + - name: DHTMEM77 + description: JPEG DHTMem tables + byte_offset: 1168 + fieldset: DHTMEM77 + - name: DHTMEM78 + description: JPEG DHTMem tables + byte_offset: 1172 + fieldset: DHTMEM78 + - name: DHTMEM79 + description: JPEG DHTMem tables + byte_offset: 1176 + fieldset: DHTMEM79 + - name: DHTMEM80 + description: JPEG DHTMem tables + byte_offset: 1180 + fieldset: DHTMEM80 + - name: DHTMEM81 + description: JPEG DHTMem tables + byte_offset: 1184 + fieldset: DHTMEM81 + - name: DHTMEM82 + description: JPEG DHTMem tables + byte_offset: 1188 + fieldset: DHTMEM82 + - name: DHTMEM83 + description: JPEG DHTMem tables + byte_offset: 1192 + fieldset: DHTMEM83 + - name: DHTMEM84 + description: JPEG DHTMem tables + byte_offset: 1196 + fieldset: DHTMEM84 + - name: DHTMEM85 + description: JPEG DHTMem tables + byte_offset: 1200 + fieldset: DHTMEM85 + - name: DHTMEM86 + description: JPEG DHTMem tables + byte_offset: 1204 + fieldset: DHTMEM86 + - name: DHTMEM87 + description: JPEG DHTMem tables + byte_offset: 1208 + fieldset: DHTMEM87 + - name: DHTMEM88 + description: JPEG DHTMem tables + byte_offset: 1212 + fieldset: DHTMEM88 + - name: DHTMEM89 + description: JPEG DHTMem tables + byte_offset: 1216 + fieldset: DHTMEM89 + - name: DHTMEM90 + description: JPEG DHTMem tables + byte_offset: 1220 + fieldset: DHTMEM90 + - name: DHTMEM91 + description: JPEG DHTMem tables + byte_offset: 1224 + fieldset: DHTMEM91 + - name: DHTMEM92 + description: JPEG DHTMem tables + byte_offset: 1228 + fieldset: DHTMEM92 + - name: DHTMEM93 + description: JPEG DHTMem tables + byte_offset: 1232 + fieldset: DHTMEM93 + - name: DHTMEM94 + description: JPEG DHTMem tables + byte_offset: 1236 + fieldset: DHTMEM94 + - name: DHTMEM95 + description: JPEG DHTMem tables + byte_offset: 1240 + fieldset: DHTMEM95 + - name: DHTMEM96 + description: JPEG DHTMem tables + byte_offset: 1244 + fieldset: DHTMEM96 + - name: DHTMEM97 + description: JPEG DHTMem tables + byte_offset: 1248 + fieldset: DHTMEM97 + - name: DHTMEM98 + description: JPEG DHTMem tables + byte_offset: 1252 + fieldset: DHTMEM98 + - name: DHTMEM99 + description: JPEG DHTMem tables + byte_offset: 1256 + fieldset: DHTMEM99 + - name: DHTMEM100 + description: JPEG DHTMem tables + byte_offset: 1260 + fieldset: DHTMEM100 + - name: DHTMEM101 + description: JPEG DHTMem tables + byte_offset: 1264 + fieldset: DHTMEM101 + - name: DHTMEM102 + description: JPEG DHTMem tables + byte_offset: 1268 + fieldset: DHTMEM102 + - name: DHTMEM103 + description: JPEG DHTMem tables + byte_offset: 1272 + fieldset: DHTMEM103 + - name: HUFFENC_AC0_0 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1280 + fieldset: HUFFENC_AC0_0 + - name: HUFFENC_AC0_1 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1284 + fieldset: HUFFENC_AC0_1 + - name: HUFFENC_AC0_2 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1288 + fieldset: HUFFENC_AC0_2 + - name: HUFFENC_AC0_3 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1292 + fieldset: HUFFENC_AC0_3 + - name: HUFFENC_AC0_4 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1296 + fieldset: HUFFENC_AC0_4 + - name: HUFFENC_AC0_5 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1300 + fieldset: HUFFENC_AC0_5 + - name: HUFFENC_AC0_6 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1304 + fieldset: HUFFENC_AC0_6 + - name: HUFFENC_AC0_7 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1308 + fieldset: HUFFENC_AC0_7 + - name: HUFFENC_AC0_8 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1312 + fieldset: HUFFENC_AC0_8 + - name: HUFFENC_AC0_9 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1316 + fieldset: HUFFENC_AC0_9 + - name: HUFFENC_AC0_10 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1320 + fieldset: HUFFENC_AC0_10 + - name: HUFFENC_AC0_11 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1324 + fieldset: HUFFENC_AC0_11 + - name: HUFFENC_AC0_12 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1328 + fieldset: HUFFENC_AC0_12 + - name: HUFFENC_AC0_13 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1332 + fieldset: HUFFENC_AC0_13 + - name: HUFFENC_AC0_14 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1336 + fieldset: HUFFENC_AC0_14 + - name: HUFFENC_AC0_15 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1340 + fieldset: HUFFENC_AC0_15 + - name: HUFFENC_AC0_16 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1344 + fieldset: HUFFENC_AC0_16 + - name: HUFFENC_AC0_17 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1348 + fieldset: HUFFENC_AC0_17 + - name: HUFFENC_AC0_18 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1352 + fieldset: HUFFENC_AC0_18 + - name: HUFFENC_AC0_19 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1356 + fieldset: HUFFENC_AC0_19 + - name: HUFFENC_AC0_20 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1360 + fieldset: HUFFENC_AC0_20 + - name: HUFFENC_AC0_21 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1364 + fieldset: HUFFENC_AC0_21 + - name: HUFFENC_AC0_22 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1368 + fieldset: HUFFENC_AC0_22 + - name: HUFFENC_AC0_23 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1372 + fieldset: HUFFENC_AC0_23 + - name: HUFFENC_AC0_24 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1376 + fieldset: HUFFENC_AC0_24 + - name: HUFFENC_AC0_25 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1380 + fieldset: HUFFENC_AC0_25 + - name: HUFFENC_AC0_26 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1384 + fieldset: HUFFENC_AC0_26 + - name: HUFFENC_AC0_27 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1388 + fieldset: HUFFENC_AC0_27 + - name: HUFFENC_AC0_28 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1392 + fieldset: HUFFENC_AC0_28 + - name: HUFFENC_AC0_29 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1396 + fieldset: HUFFENC_AC0_29 + - name: HUFFENC_AC0_30 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1400 + fieldset: HUFFENC_AC0_30 + - name: HUFFENC_AC0_31 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1404 + fieldset: HUFFENC_AC0_31 + - name: HUFFENC_AC0_32 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1408 + fieldset: HUFFENC_AC0_32 + - name: HUFFENC_AC0_33 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1412 + fieldset: HUFFENC_AC0_33 + - name: HUFFENC_AC0_34 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1416 + fieldset: HUFFENC_AC0_34 + - name: HUFFENC_AC0_35 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1420 + fieldset: HUFFENC_AC0_35 + - name: HUFFENC_AC0_36 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1424 + fieldset: HUFFENC_AC0_36 + - name: HUFFENC_AC0_37 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1428 + fieldset: HUFFENC_AC0_37 + - name: HUFFENC_AC0_38 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1432 + fieldset: HUFFENC_AC0_38 + - name: HUFFENC_AC0_39 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1436 + fieldset: HUFFENC_AC0_39 + - name: HUFFENC_AC0_40 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1440 + fieldset: HUFFENC_AC0_40 + - name: HUFFENC_AC0_41 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1444 + fieldset: HUFFENC_AC0_41 + - name: HUFFENC_AC0_42 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1448 + fieldset: HUFFENC_AC0_42 + - name: HUFFENC_AC0_43 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1452 + fieldset: HUFFENC_AC0_43 + - name: HUFFENC_AC0_44 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1456 + fieldset: HUFFENC_AC0_44 + - name: HUFFENC_AC0_45 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1460 + fieldset: HUFFENC_AC0_45 + - name: HUFFENC_AC0_46 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1464 + fieldset: HUFFENC_AC0_46 + - name: HUFFENC_AC0_47 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1468 + fieldset: HUFFENC_AC0_47 + - name: HUFFENC_AC0_48 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1472 + fieldset: HUFFENC_AC0_48 + - name: HUFFENC_AC0_49 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1476 + fieldset: HUFFENC_AC0_49 + - name: HUFFENC_AC0_50 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1480 + fieldset: HUFFENC_AC0_50 + - name: HUFFENC_AC0_51 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1484 + fieldset: HUFFENC_AC0_51 + - name: HUFFENC_AC0_52 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1488 + fieldset: HUFFENC_AC0_52 + - name: HUFFENC_AC0_53 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1492 + fieldset: HUFFENC_AC0_53 + - name: HUFFENC_AC0_54 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1496 + fieldset: HUFFENC_AC0_54 + - name: HUFFENC_AC0_55 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1500 + fieldset: HUFFENC_AC0_55 + - name: HUFFENC_AC0_56 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1504 + fieldset: HUFFENC_AC0_56 + - name: HUFFENC_AC0_57 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1508 + fieldset: HUFFENC_AC0_57 + - name: HUFFENC_AC0_58 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1512 + fieldset: HUFFENC_AC0_58 + - name: HUFFENC_AC0_59 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1516 + fieldset: HUFFENC_AC0_59 + - name: HUFFENC_AC0_60 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1520 + fieldset: HUFFENC_AC0_60 + - name: HUFFENC_AC0_61 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1524 + fieldset: HUFFENC_AC0_61 + - name: HUFFENC_AC0_62 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1528 + fieldset: HUFFENC_AC0_62 + - name: HUFFENC_AC0_63 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1532 + fieldset: HUFFENC_AC0_63 + - name: HUFFENC_AC0_64 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1536 + fieldset: HUFFENC_AC0_64 + - name: HUFFENC_AC0_65 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1540 + fieldset: HUFFENC_AC0_65 + - name: HUFFENC_AC0_66 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1544 + fieldset: HUFFENC_AC0_66 + - name: HUFFENC_AC0_67 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1548 + fieldset: HUFFENC_AC0_67 + - name: HUFFENC_AC0_68 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1552 + fieldset: HUFFENC_AC0_68 + - name: HUFFENC_AC0_69 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1556 + fieldset: HUFFENC_AC0_69 + - name: HUFFENC_AC0_70 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1560 + fieldset: HUFFENC_AC0_70 + - name: HUFFENC_AC0_71 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1564 + fieldset: HUFFENC_AC0_71 + - name: HUFFENC_AC0_72 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1568 + fieldset: HUFFENC_AC0_72 + - name: HUFFENC_AC0_73 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1572 + fieldset: HUFFENC_AC0_73 + - name: HUFFENC_AC0_74 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1576 + fieldset: HUFFENC_AC0_74 + - name: HUFFENC_AC0_75 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1580 + fieldset: HUFFENC_AC0_75 + - name: HUFFENC_AC0_76 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1584 + fieldset: HUFFENC_AC0_76 + - name: HUFFENC_AC0_77 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1588 + fieldset: HUFFENC_AC0_77 + - name: HUFFENC_AC0_78 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1592 + fieldset: HUFFENC_AC0_78 + - name: HUFFENC_AC0_79 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1596 + fieldset: HUFFENC_AC0_79 + - name: HUFFENC_AC0_80 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1600 + fieldset: HUFFENC_AC0_80 + - name: HUFFENC_AC0_81 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1604 + fieldset: HUFFENC_AC0_81 + - name: HUFFENC_AC0_82 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1608 + fieldset: HUFFENC_AC0_82 + - name: HUFFENC_AC0_83 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1612 + fieldset: HUFFENC_AC0_83 + - name: HUFFENC_AC0_84 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1616 + fieldset: HUFFENC_AC0_84 + - name: HUFFENC_AC0_85 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1620 + fieldset: HUFFENC_AC0_85 + - name: HUFFENC_AC0_86 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1624 + fieldset: HUFFENC_AC0_86 + - name: HUFFENC_AC0_87 + description: JPEG encoder, AC Huffman table 0 + byte_offset: 1628 + fieldset: HUFFENC_AC0_87 + - name: HUFFENC_AC1_0 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1632 + fieldset: HUFFENC_AC1_0 + - name: HUFFENC_AC1_1 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1636 + fieldset: HUFFENC_AC1_1 + - name: HUFFENC_AC1_2 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1640 + fieldset: HUFFENC_AC1_2 + - name: HUFFENC_AC1_3 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1644 + fieldset: HUFFENC_AC1_3 + - name: HUFFENC_AC1_4 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1648 + fieldset: HUFFENC_AC1_4 + - name: HUFFENC_AC1_5 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1652 + fieldset: HUFFENC_AC1_5 + - name: HUFFENC_AC1_6 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1656 + fieldset: HUFFENC_AC1_6 + - name: HUFFENC_AC1_7 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1660 + fieldset: HUFFENC_AC1_7 + - name: HUFFENC_AC1_8 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1664 + fieldset: HUFFENC_AC1_8 + - name: HUFFENC_AC1_9 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1668 + fieldset: HUFFENC_AC1_9 + - name: HUFFENC_AC1_10 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1672 + fieldset: HUFFENC_AC1_10 + - name: HUFFENC_AC1_11 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1676 + fieldset: HUFFENC_AC1_11 + - name: HUFFENC_AC1_12 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1680 + fieldset: HUFFENC_AC1_12 + - name: HUFFENC_AC1_13 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1684 + fieldset: HUFFENC_AC1_13 + - name: HUFFENC_AC1_14 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1688 + fieldset: HUFFENC_AC1_14 + - name: HUFFENC_AC1_15 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1692 + fieldset: HUFFENC_AC1_15 + - name: HUFFENC_AC1_16 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1696 + fieldset: HUFFENC_AC1_16 + - name: HUFFENC_AC1_17 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1700 + fieldset: HUFFENC_AC1_17 + - name: HUFFENC_AC1_18 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1704 + fieldset: HUFFENC_AC1_18 + - name: HUFFENC_AC1_19 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1708 + fieldset: HUFFENC_AC1_19 + - name: HUFFENC_AC1_20 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1712 + fieldset: HUFFENC_AC1_20 + - name: HUFFENC_AC1_21 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1716 + fieldset: HUFFENC_AC1_21 + - name: HUFFENC_AC1_22 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1720 + fieldset: HUFFENC_AC1_22 + - name: HUFFENC_AC1_23 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1724 + fieldset: HUFFENC_AC1_23 + - name: HUFFENC_AC1_24 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1728 + fieldset: HUFFENC_AC1_24 + - name: HUFFENC_AC1_25 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1732 + fieldset: HUFFENC_AC1_25 + - name: HUFFENC_AC1_26 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1736 + fieldset: HUFFENC_AC1_26 + - name: HUFFENC_AC1_27 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1740 + fieldset: HUFFENC_AC1_27 + - name: HUFFENC_AC1_28 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1744 + fieldset: HUFFENC_AC1_28 + - name: HUFFENC_AC1_29 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1748 + fieldset: HUFFENC_AC1_29 + - name: HUFFENC_AC1_30 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1752 + fieldset: HUFFENC_AC1_30 + - name: HUFFENC_AC1_31 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1756 + fieldset: HUFFENC_AC1_31 + - name: HUFFENC_AC1_32 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1760 + fieldset: HUFFENC_AC1_32 + - name: HUFFENC_AC1_33 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1764 + fieldset: HUFFENC_AC1_33 + - name: HUFFENC_AC1_34 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1768 + fieldset: HUFFENC_AC1_34 + - name: HUFFENC_AC1_35 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1772 + fieldset: HUFFENC_AC1_35 + - name: HUFFENC_AC1_36 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1776 + fieldset: HUFFENC_AC1_36 + - name: HUFFENC_AC1_37 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1780 + fieldset: HUFFENC_AC1_37 + - name: HUFFENC_AC1_38 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1784 + fieldset: HUFFENC_AC1_38 + - name: HUFFENC_AC1_39 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1788 + fieldset: HUFFENC_AC1_39 + - name: HUFFENC_AC1_40 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1792 + fieldset: HUFFENC_AC1_40 + - name: HUFFENC_AC1_41 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1796 + fieldset: HUFFENC_AC1_41 + - name: HUFFENC_AC1_42 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1800 + fieldset: HUFFENC_AC1_42 + - name: HUFFENC_AC1_43 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1804 + fieldset: HUFFENC_AC1_43 + - name: HUFFENC_AC1_44 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1808 + fieldset: HUFFENC_AC1_44 + - name: HUFFENC_AC1_45 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1812 + fieldset: HUFFENC_AC1_45 + - name: HUFFENC_AC1_46 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1816 + fieldset: HUFFENC_AC1_46 + - name: HUFFENC_AC1_47 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1820 + fieldset: HUFFENC_AC1_47 + - name: HUFFENC_AC1_48 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1824 + fieldset: HUFFENC_AC1_48 + - name: HUFFENC_AC1_49 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1828 + fieldset: HUFFENC_AC1_49 + - name: HUFFENC_AC1_50 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1832 + fieldset: HUFFENC_AC1_50 + - name: HUFFENC_AC1_51 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1836 + fieldset: HUFFENC_AC1_51 + - name: HUFFENC_AC1_52 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1840 + fieldset: HUFFENC_AC1_52 + - name: HUFFENC_AC1_53 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1844 + fieldset: HUFFENC_AC1_53 + - name: HUFFENC_AC1_54 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1848 + fieldset: HUFFENC_AC1_54 + - name: HUFFENC_AC1_55 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1852 + fieldset: HUFFENC_AC1_55 + - name: HUFFENC_AC1_56 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1856 + fieldset: HUFFENC_AC1_56 + - name: HUFFENC_AC1_57 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1860 + fieldset: HUFFENC_AC1_57 + - name: HUFFENC_AC1_58 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1864 + fieldset: HUFFENC_AC1_58 + - name: HUFFENC_AC1_59 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1868 + fieldset: HUFFENC_AC1_59 + - name: HUFFENC_AC1_60 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1872 + fieldset: HUFFENC_AC1_60 + - name: HUFFENC_AC1_61 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1876 + fieldset: HUFFENC_AC1_61 + - name: HUFFENC_AC1_62 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1880 + fieldset: HUFFENC_AC1_62 + - name: HUFFENC_AC1_63 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1884 + fieldset: HUFFENC_AC1_63 + - name: HUFFENC_AC1_64 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1888 + fieldset: HUFFENC_AC1_64 + - name: HUFFENC_AC1_65 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1892 + fieldset: HUFFENC_AC1_65 + - name: HUFFENC_AC1_66 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1896 + fieldset: HUFFENC_AC1_66 + - name: HUFFENC_AC1_67 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1900 + fieldset: HUFFENC_AC1_67 + - name: HUFFENC_AC1_68 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1904 + fieldset: HUFFENC_AC1_68 + - name: HUFFENC_AC1_69 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1908 + fieldset: HUFFENC_AC1_69 + - name: HUFFENC_AC1_70 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1912 + fieldset: HUFFENC_AC1_70 + - name: HUFFENC_AC1_71 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1916 + fieldset: HUFFENC_AC1_71 + - name: HUFFENC_AC1_72 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1920 + fieldset: HUFFENC_AC1_72 + - name: HUFFENC_AC1_73 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1924 + fieldset: HUFFENC_AC1_73 + - name: HUFFENC_AC1_74 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1928 + fieldset: HUFFENC_AC1_74 + - name: HUFFENC_AC1_75 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1932 + fieldset: HUFFENC_AC1_75 + - name: HUFFENC_AC1_76 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1936 + fieldset: HUFFENC_AC1_76 + - name: HUFFENC_AC1_77 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1940 + fieldset: HUFFENC_AC1_77 + - name: HUFFENC_AC1_78 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1944 + fieldset: HUFFENC_AC1_78 + - name: HUFFENC_AC1_79 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1948 + fieldset: HUFFENC_AC1_79 + - name: HUFFENC_AC1_80 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1952 + fieldset: HUFFENC_AC1_80 + - name: HUFFENC_AC1_81 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1956 + fieldset: HUFFENC_AC1_81 + - name: HUFFENC_AC1_82 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1960 + fieldset: HUFFENC_AC1_82 + - name: HUFFENC_AC1_83 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1964 + fieldset: HUFFENC_AC1_83 + - name: HUFFENC_AC1_84 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1968 + fieldset: HUFFENC_AC1_84 + - name: HUFFENC_AC1_85 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1972 + fieldset: HUFFENC_AC1_85 + - name: HUFFENC_AC1_86 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1976 + fieldset: HUFFENC_AC1_86 + - name: HUFFENC_AC1_87 + description: JPEG encoder, AC Huffman table 1 + byte_offset: 1980 + fieldset: HUFFENC_AC1_87 + - name: HUFFENC_DC0_0 + description: JPEG encoder, DC Huffman table 0 + byte_offset: 1984 + fieldset: HUFFENC_DC0_0 + - name: HUFFENC_DC0_1 + description: JPEG encoder, DC Huffman table 0 + byte_offset: 1988 + fieldset: HUFFENC_DC0_1 + - name: HUFFENC_DC0_2 + description: JPEG encoder, DC Huffman table 0 + byte_offset: 1992 + fieldset: HUFFENC_DC0_2 + - name: HUFFENC_DC0_3 + description: JPEG encoder, DC Huffman table 0 + byte_offset: 1996 + fieldset: HUFFENC_DC0_3 + - name: HUFFENC_DC0_4 + description: JPEG encoder, DC Huffman table 0 + byte_offset: 2000 + fieldset: HUFFENC_DC0_4 + - name: HUFFENC_DC0_5 + description: JPEG encoder, DC Huffman table 0 + byte_offset: 2004 + fieldset: HUFFENC_DC0_5 + - name: HUFFENC_DC0_6 + description: JPEG encoder, DC Huffman table 0 + byte_offset: 2008 + fieldset: HUFFENC_DC0_6 + - name: HUFFENC_DC0_7 + description: JPEG encoder, DC Huffman table 0 + byte_offset: 2012 + fieldset: HUFFENC_DC0_7 + - name: HUFFENC_DC1_0 + description: JPEG encoder, DC Huffman table 1 + byte_offset: 2016 + fieldset: HUFFENC_DC1_0 + - name: HUFFENC_DC1_1 + description: JPEG encoder, DC Huffman table 1 + byte_offset: 2020 + fieldset: HUFFENC_DC1_1 + - name: HUFFENC_DC1_2 + description: JPEG encoder, DC Huffman table 1 + byte_offset: 2024 + fieldset: HUFFENC_DC1_2 + - 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bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_11: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_12: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_13: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_14: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_15: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_16: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_17: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_18: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_19: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_2: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_20: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_21: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_22: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_23: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_24: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_25: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_26: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_27: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_28: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_29: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_3: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_30: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_31: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_32: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_33: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_34: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_35: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_36: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_37: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_38: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_39: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_4: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_40: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_41: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_42: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_43: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_44: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_45: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_46: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_47: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_48: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_49: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_5: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_50: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_51: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_52: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_53: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_54: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_55: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_56: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_57: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_58: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_59: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_6: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_60: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_61: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_62: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_63: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_64: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_65: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_66: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_67: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_68: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_69: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_7: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_70: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_71: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_72: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_73: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_74: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_75: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_76: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_77: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_78: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_79: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_8: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_80: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_81: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_82: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_83: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_84: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_85: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_86: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_87: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_9: - description: "JPEG encoder, AC Huffman table 1" + description: JPEG encoder, AC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC0_0: - description: "JPEG encoder, DC Huffman table 0" + description: JPEG encoder, DC Huffman table 0 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC0_1: - description: "JPEG encoder, DC Huffman table 0" + description: JPEG encoder, DC Huffman table 0 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC0_2: - description: "JPEG encoder, DC Huffman table 0" + description: JPEG encoder, DC Huffman table 0 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC0_3: - description: "JPEG encoder, DC Huffman table 0" + description: JPEG encoder, DC Huffman table 0 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC0_4: - description: "JPEG encoder, DC Huffman table 0" + description: JPEG encoder, DC Huffman table 0 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC0_5: - description: "JPEG encoder, DC Huffman table 0" + description: JPEG encoder, DC Huffman table 0 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC0_6: - description: "JPEG encoder, DC Huffman table 0" + description: JPEG encoder, DC Huffman table 0 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC0_7: - description: "JPEG encoder, DC Huffman table 0" + description: JPEG encoder, DC Huffman table 0 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC1_0: - description: "JPEG encoder, DC Huffman table 1" + description: JPEG encoder, DC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC1_1: - description: "JPEG encoder, DC Huffman table 1" + description: JPEG encoder, DC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC1_2: - description: "JPEG encoder, DC Huffman table 1" + description: JPEG encoder, DC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC1_3: - description: "JPEG encoder, DC Huffman table 1" + description: JPEG encoder, DC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC1_4: - description: "JPEG encoder, DC Huffman table 1" + description: JPEG encoder, DC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC1_5: - description: "JPEG encoder, DC Huffman table 1" + description: JPEG encoder, DC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC1_6: - description: "JPEG encoder, DC Huffman table 1" + description: JPEG encoder, DC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC1_7: - description: "JPEG encoder, DC Huffman table 1" + description: JPEG encoder, DC Huffman table 1 fields: - - name: DHTMem_RAM - description: DHTMem RAM - bit_offset: 0 - bit_size: 32 + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_0: description: JPEG HuffMin tables fields: - - name: HuffMin_RAM - description: HuffMin RAM - bit_offset: 0 - bit_size: 32 + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_1: description: JPEG HuffMin tables fields: - - name: HuffMin_RAM - description: HuffMin RAM - bit_offset: 0 - bit_size: 32 + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_10: description: JPEG HuffMin tables fields: - - name: HuffMin_RAM - description: HuffMin RAM - bit_offset: 0 - bit_size: 32 + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_11: description: JPEG HuffMin tables fields: - - name: HuffMin_RAM - description: HuffMin RAM - bit_offset: 0 - bit_size: 32 + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_12: description: JPEG HuffMin tables fields: - - name: HuffMin_RAM - description: HuffMin RAM - bit_offset: 0 - bit_size: 32 + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_13: description: JPEG HuffMin tables fields: - - name: HuffMin_RAM - description: HuffMin RAM - bit_offset: 0 - bit_size: 32 + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_14: description: JPEG HuffMin tables fields: - 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- name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB46: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB47: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB48: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB49: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB5: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB50: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB51: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB52: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB53: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB54: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB55: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB56: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB57: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB58: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB59: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB6: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB60: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB61: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB62: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB63: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB64: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB65: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB66: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB67: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB68: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB69: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB7: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB70: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB71: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB72: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB73: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB74: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB75: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB76: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB77: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB78: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB79: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB8: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB80: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB81: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB82: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB83: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB9: description: JPEG HUFFSYMB tables fields: - - name: HuffSymb_RAM - description: DHTSymb RAM - bit_offset: 0 - bit_size: 32 + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/JPEG_CFR: description: JPEG clear flag register fields: - - name: CEOCF - description: Clear End of Conversion Flag - bit_offset: 5 - bit_size: 1 - - name: CHPDF - description: Clear Header Parsing Done Flag - bit_offset: 6 - bit_size: 1 + - name: CEOCF + description: Clear End of Conversion Flag + bit_offset: 5 + bit_size: 1 + - name: CHPDF + description: Clear Header Parsing Done Flag + bit_offset: 6 + bit_size: 1 fieldset/JPEG_CONFR0: description: JPEG codec configuration register 0 fields: - - name: START - description: Start - bit_offset: 0 - bit_size: 1 + - name: START + description: Start + bit_offset: 0 + bit_size: 1 fieldset/JPEG_CONFR1: description: JPEG codec configuration register 1 fields: - - name: NF - description: Number of color components - bit_offset: 0 - bit_size: 2 - - name: DE - description: Decoding Enable - bit_offset: 3 - bit_size: 1 - - name: COLORSPACE - description: Color Space - bit_offset: 4 - bit_size: 2 - - name: NS - description: Number of components for Scan - bit_offset: 6 - bit_size: 2 - - name: HDR - description: Header Processing - bit_offset: 8 - bit_size: 1 - - name: YSIZE - description: Y Size - bit_offset: 16 - bit_size: 16 + - name: NF + description: Number of color components + bit_offset: 0 + bit_size: 2 + - name: DE + description: Decoding Enable + bit_offset: 3 + bit_size: 1 + - name: COLORSPACE + description: Color Space + bit_offset: 4 + bit_size: 2 + - name: NS + description: Number of components for Scan + bit_offset: 6 + bit_size: 2 + - name: HDR + description: Header Processing + bit_offset: 8 + bit_size: 1 + - name: YSIZE + description: Y Size + bit_offset: 16 + bit_size: 16 fieldset/JPEG_CONFR2: description: JPEG codec configuration register 2 fields: - - name: NMCU - description: Number of MCU - bit_offset: 0 - bit_size: 26 + - name: NMCU + description: Number of MCU + bit_offset: 0 + bit_size: 26 fieldset/JPEG_CONFR3: description: JPEG codec configuration register 3 fields: - - name: XSIZE - description: X size - bit_offset: 16 - bit_size: 16 + - name: XSIZE + description: X size + bit_offset: 16 + bit_size: 16 fieldset/JPEG_CONFR4: description: JPEG codec configuration register 4 fields: - - name: HD - description: Huffman DC - bit_offset: 0 - bit_size: 1 - - name: HA - description: Huffman AC - bit_offset: 1 - bit_size: 1 - - name: QT - description: Quantization Table - bit_offset: 2 - bit_size: 2 - - name: NB - description: Number of Block - bit_offset: 4 - bit_size: 4 - - name: VSF - description: Vertical Sampling Factor - bit_offset: 8 - bit_size: 4 - - name: HSF - description: Horizontal Sampling Factor - bit_offset: 12 - bit_size: 4 + - name: HD + description: Huffman DC + bit_offset: 0 + bit_size: 1 + - name: HA + description: Huffman AC + bit_offset: 1 + bit_size: 1 + - name: QT + description: Quantization Table + bit_offset: 2 + bit_size: 2 + - name: NB + description: Number of Block + bit_offset: 4 + bit_size: 4 + - name: VSF + description: Vertical Sampling Factor + bit_offset: 8 + bit_size: 4 + - name: HSF + description: Horizontal Sampling Factor + bit_offset: 12 + bit_size: 4 fieldset/JPEG_CONFR5: description: JPEG codec configuration register 5 fields: - - name: HD - description: Huffman DC - bit_offset: 0 - bit_size: 1 - - name: HA - description: Huffman AC - bit_offset: 1 - bit_size: 1 - - name: QT - description: Quantization Table - bit_offset: 2 - bit_size: 2 - - name: NB - description: Number of Block - bit_offset: 4 - bit_size: 4 - - name: VSF - description: Vertical Sampling Factor - bit_offset: 8 - bit_size: 4 - - name: HSF - description: Horizontal Sampling Factor - bit_offset: 12 - bit_size: 4 + - name: HD + description: Huffman DC + bit_offset: 0 + bit_size: 1 + - name: HA + description: Huffman AC + bit_offset: 1 + bit_size: 1 + - name: QT + description: Quantization Table + bit_offset: 2 + bit_size: 2 + - name: NB + description: Number of Block + bit_offset: 4 + bit_size: 4 + - name: VSF + description: Vertical Sampling Factor + bit_offset: 8 + bit_size: 4 + - name: HSF + description: Horizontal Sampling Factor + bit_offset: 12 + bit_size: 4 fieldset/JPEG_CONFR6: description: JPEG codec configuration register 6 fields: - - name: HD - description: Huffman DC - bit_offset: 0 - bit_size: 1 - - name: HA - description: Huffman AC - bit_offset: 1 - bit_size: 1 - - name: QT - description: Quantization Table - bit_offset: 2 - bit_size: 2 - - name: NB - description: Number of Block - bit_offset: 4 - bit_size: 4 - - name: VSF - description: Vertical Sampling Factor - bit_offset: 8 - bit_size: 4 - - name: HSF - description: Horizontal Sampling Factor - bit_offset: 12 - bit_size: 4 + - name: HD + description: Huffman DC + bit_offset: 0 + bit_size: 1 + - name: HA + description: Huffman AC + bit_offset: 1 + bit_size: 1 + - name: QT + description: Quantization Table + bit_offset: 2 + bit_size: 2 + - name: NB + description: Number of Block + bit_offset: 4 + bit_size: 4 + - name: VSF + description: Vertical Sampling Factor + bit_offset: 8 + bit_size: 4 + - name: HSF + description: Horizontal Sampling Factor + bit_offset: 12 + bit_size: 4 fieldset/JPEG_CONFR7: description: JPEG codec configuration register 7 fields: - - name: HD - description: Huffman DC - bit_offset: 0 - bit_size: 1 - - name: HA - description: Huffman AC - bit_offset: 1 - bit_size: 1 - - name: QT - description: Quantization Table - bit_offset: 2 - bit_size: 2 - - name: NB - description: Number of Block - bit_offset: 4 - bit_size: 4 - - name: VSF - description: Vertical Sampling Factor - bit_offset: 8 - bit_size: 4 - - name: HSF - description: Horizontal Sampling Factor - bit_offset: 12 - bit_size: 4 + - name: HD + description: Huffman DC + bit_offset: 0 + bit_size: 1 + - name: HA + description: Huffman AC + bit_offset: 1 + bit_size: 1 + - name: QT + description: Quantization Table + bit_offset: 2 + bit_size: 2 + - name: NB + description: Number of Block + bit_offset: 4 + bit_size: 4 + - name: VSF + description: Vertical Sampling Factor + bit_offset: 8 + bit_size: 4 + - name: HSF + description: Horizontal Sampling Factor + bit_offset: 12 + bit_size: 4 fieldset/JPEG_CR: description: JPEG control register fields: - - name: JCEN - description: JPEG Core Enable - bit_offset: 0 - bit_size: 1 - - name: IFTIE - description: Input FIFO Threshold Interrupt Enable - bit_offset: 1 - bit_size: 1 - - name: IFNFIE - description: Input FIFO Not Full Interrupt Enable - bit_offset: 2 - bit_size: 1 - - name: OFTIE - description: Output FIFO Threshold Interrupt Enable - bit_offset: 3 - bit_size: 1 - - name: OFNEIE - description: Output FIFO Not Empty Interrupt Enable - bit_offset: 4 - bit_size: 1 - - name: EOCIE - description: End of Conversion Interrupt Enable - bit_offset: 5 - bit_size: 1 - - name: HPDIE - description: Header Parsing Done Interrupt Enable - bit_offset: 6 - bit_size: 1 - - name: IDMAEN - description: Input DMA Enable - bit_offset: 11 - bit_size: 1 - - name: ODMAEN - description: Output DMA Enable - bit_offset: 12 - bit_size: 1 - - name: IFF - description: Input FIFO Flush - bit_offset: 13 - bit_size: 1 - - name: "OFF" - description: Output FIFO Flush - bit_offset: 14 - bit_size: 1 + - name: JCEN + description: JPEG Core Enable + bit_offset: 0 + bit_size: 1 + - name: IFTIE + description: Input FIFO Threshold Interrupt Enable + bit_offset: 1 + bit_size: 1 + - name: IFNFIE + description: Input FIFO Not Full Interrupt Enable + bit_offset: 2 + bit_size: 1 + - name: OFTIE + description: Output FIFO Threshold Interrupt Enable + bit_offset: 3 + bit_size: 1 + - name: OFNEIE + description: Output FIFO Not Empty Interrupt Enable + bit_offset: 4 + bit_size: 1 + - name: EOCIE + description: End of Conversion Interrupt Enable + bit_offset: 5 + bit_size: 1 + - name: HPDIE + description: Header Parsing Done Interrupt Enable + bit_offset: 6 + bit_size: 1 + - name: IDMAEN + description: Input DMA Enable + bit_offset: 11 + bit_size: 1 + - name: ODMAEN + description: Output DMA Enable + bit_offset: 12 + bit_size: 1 + - name: IFF + description: Input FIFO Flush + bit_offset: 13 + bit_size: 1 + - name: OFF + description: Output FIFO Flush + bit_offset: 14 + bit_size: 1 fieldset/JPEG_DIR: description: JPEG data input register fields: - - name: DATAIN - description: Data Input FIFO - bit_offset: 0 - bit_size: 32 + - name: DATAIN + description: Data Input FIFO + bit_offset: 0 + bit_size: 32 fieldset/JPEG_DOR: description: JPEG data output register fields: - - name: DATAOUT - description: Data Output FIFO - bit_offset: 0 - bit_size: 32 + - name: DATAOUT + description: Data Output FIFO + bit_offset: 0 + bit_size: 32 fieldset/JPEG_SR: description: JPEG status register fields: - - name: IFTF - description: Input FIFO Threshold Flag - bit_offset: 1 - bit_size: 1 - - name: IFNFF - description: Input FIFO Not Full Flag - bit_offset: 2 - bit_size: 1 - - name: OFTF - description: Output FIFO Threshold Flag - bit_offset: 3 - bit_size: 1 - - name: OFNEF - description: Output FIFO Not Empty Flag - bit_offset: 4 - bit_size: 1 - - name: EOCF - description: End of Conversion Flag - bit_offset: 5 - bit_size: 1 - - name: HPDF - description: Header Parsing Done Flag - bit_offset: 6 - bit_size: 1 - - name: COF - description: Codec Operation Flag - bit_offset: 7 - bit_size: 1 + - name: IFTF + description: Input FIFO Threshold Flag + bit_offset: 1 + bit_size: 1 + - name: IFNFF + description: Input FIFO Not Full Flag + bit_offset: 2 + bit_size: 1 + - name: OFTF + description: Output FIFO Threshold Flag + bit_offset: 3 + bit_size: 1 + - name: OFNEF + description: Output FIFO Not Empty Flag + bit_offset: 4 + bit_size: 1 + - name: EOCF + description: End of Conversion Flag + bit_offset: 5 + bit_size: 1 + - name: HPDF + description: Header Parsing Done Flag + bit_offset: 6 + bit_size: 1 + - name: COF + description: Codec Operation Flag + bit_offset: 7 + bit_size: 1 fieldset/QMEM0_0: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_1: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_10: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_11: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_12: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_13: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_14: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_15: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_2: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_3: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_4: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_5: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_6: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_7: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_8: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_9: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_0: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_1: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_10: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_11: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_12: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_13: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_14: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_15: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_2: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_3: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_4: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_5: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_6: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_7: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_8: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_9: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_0: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_1: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_10: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_11: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_12: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_13: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_14: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_15: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_2: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_3: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_4: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_5: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_6: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_7: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_8: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_9: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_0: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_1: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_10: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_11: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_12: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_13: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_14: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_15: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_2: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_3: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_4: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_5: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_6: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_7: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_8: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_9: description: JPEG quantization tables fields: - - name: QMem_RAM - description: QMem RAM - bit_offset: 0 - bit_size: 32 + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 diff --git a/data/registers/lcd_v1.yaml b/data/registers/lcd_v1.yaml index 9b76cf5..ddc34e8 100644 --- a/data/registers/lcd_v1.yaml +++ b/data/registers/lcd_v1.yaml @@ -1,141 +1,140 @@ ---- block/LCD: description: Liquid crystal display controller items: - - name: CR - description: control register - byte_offset: 0 - fieldset: CR - - name: FCR - description: frame control register - byte_offset: 4 - fieldset: FCR - - name: SR - description: status register - byte_offset: 8 - fieldset: SR - - name: CLR - description: clear register - byte_offset: 12 - access: Write - fieldset: CLR - - name: RAM_COM - description: display memory - array: - len: 8 - stride: 8 - byte_offset: 20 - block: RAM_COM + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: FCR + description: frame control register + byte_offset: 4 + fieldset: FCR + - name: SR + description: status register + byte_offset: 8 + fieldset: SR + - name: CLR + description: clear register + byte_offset: 12 + access: Write + fieldset: CLR + - name: RAM_COM + description: display memory + array: + len: 8 + stride: 8 + byte_offset: 20 + block: RAM_COM block/RAM_COM: description: display memory items: - - name: LOW - description: display memory low word - byte_offset: 0 - - name: HIGH - description: display memory high word - byte_offset: 4 + - name: LOW + description: display memory low word + byte_offset: 0 + - name: HIGH + description: display memory high word + byte_offset: 4 fieldset/CLR: description: clear register fields: - - name: SOFC - description: Start of frame flag clear - bit_offset: 1 - bit_size: 1 - - name: UDDC - description: Update display done clear - bit_offset: 3 - bit_size: 1 + - name: SOFC + description: Start of frame flag clear + bit_offset: 1 + bit_size: 1 + - name: UDDC + description: Update display done clear + bit_offset: 3 + bit_size: 1 fieldset/CR: description: control register fields: - - name: LCDEN - description: LCD controller enable - bit_offset: 0 - bit_size: 1 - - name: VSEL - description: Voltage source selection - bit_offset: 1 - bit_size: 1 - - name: DUTY - description: Duty selection - bit_offset: 2 - bit_size: 3 - - name: BIAS - description: Bias selector - bit_offset: 5 - bit_size: 2 - - name: MUX_SEG - description: Mux segment enable - bit_offset: 7 - bit_size: 1 + - name: LCDEN + description: LCD controller enable + bit_offset: 0 + bit_size: 1 + - name: VSEL + description: Voltage source selection + bit_offset: 1 + bit_size: 1 + - name: DUTY + description: Duty selection + bit_offset: 2 + bit_size: 3 + - name: BIAS + description: Bias selector + bit_offset: 5 + bit_size: 2 + - name: MUX_SEG + description: Mux segment enable + bit_offset: 7 + bit_size: 1 fieldset/FCR: description: frame control register fields: - - name: HD - description: High drive enable - bit_offset: 0 - bit_size: 1 - - name: SOFIE - description: Start of frame interrupt enable - bit_offset: 1 - bit_size: 1 - - name: UDDIE - description: Update display done interrupt enable - bit_offset: 3 - bit_size: 1 - - name: PON - description: Pulse ON duration - bit_offset: 4 - bit_size: 3 - - name: DEAD - description: Dead time duration - bit_offset: 7 - bit_size: 3 - - name: CC - description: Contrast control - bit_offset: 10 - bit_size: 3 - - name: BLINKF - description: Blink frequency selection - bit_offset: 13 - bit_size: 3 - - name: BLINK - description: Blink mode selection - bit_offset: 16 - bit_size: 2 - - name: DIV - description: DIV clock divider - bit_offset: 18 - bit_size: 4 - - name: PS - description: PS 16-bit prescaler - bit_offset: 22 - bit_size: 4 + - name: HD + description: High drive enable + bit_offset: 0 + bit_size: 1 + - name: SOFIE + description: Start of frame interrupt enable + bit_offset: 1 + bit_size: 1 + - name: UDDIE + description: Update display done interrupt enable + bit_offset: 3 + bit_size: 1 + - name: PON + description: Pulse ON duration + bit_offset: 4 + bit_size: 3 + - name: DEAD + description: Dead time duration + bit_offset: 7 + bit_size: 3 + - name: CC + description: Contrast control + bit_offset: 10 + bit_size: 3 + - name: BLINKF + description: Blink frequency selection + bit_offset: 13 + bit_size: 3 + - name: BLINK + description: Blink mode selection + bit_offset: 16 + bit_size: 2 + - name: DIV + description: DIV clock divider + bit_offset: 18 + bit_size: 4 + - name: PS + description: PS 16-bit prescaler + bit_offset: 22 + bit_size: 4 fieldset/SR: description: status register fields: - - name: ENS - description: LCD enabled status - bit_offset: 0 - bit_size: 1 - - name: SOF - description: Start of frame flag - bit_offset: 1 - bit_size: 1 - - name: UDR - description: Update display request - bit_offset: 2 - bit_size: 1 - - name: UDD - description: Update Display Done - bit_offset: 3 - bit_size: 1 - - name: RDY - description: Ready flag - bit_offset: 4 - bit_size: 1 - - name: FCRSF - description: LCD Frame Control Register Synchronization flag - bit_offset: 5 - bit_size: 1 + - name: ENS + description: LCD enabled status + bit_offset: 0 + bit_size: 1 + - name: SOF + description: Start of frame flag + bit_offset: 1 + bit_size: 1 + - name: UDR + description: Update display request + bit_offset: 2 + bit_size: 1 + - name: UDD + description: Update Display Done + bit_offset: 3 + bit_size: 1 + - name: RDY + description: Ready flag + bit_offset: 4 + bit_size: 1 + - name: FCRSF + description: LCD Frame Control Register Synchronization flag + bit_offset: 5 + bit_size: 1 diff --git a/data/registers/lcd_v2.yaml b/data/registers/lcd_v2.yaml index c76e775..1b88405 100644 --- a/data/registers/lcd_v2.yaml +++ b/data/registers/lcd_v2.yaml @@ -1,145 +1,144 @@ ---- block/LCD: description: Liquid crystal display controller items: - - name: CR - description: control register - byte_offset: 0 - fieldset: CR - - name: FCR - description: frame control register - byte_offset: 4 - fieldset: FCR - - name: SR - description: status register - byte_offset: 8 - fieldset: SR - - name: CLR - description: clear register - byte_offset: 12 - access: Write - fieldset: CLR - - name: RAM_COM - description: display memory - array: - len: 8 - stride: 8 - byte_offset: 20 - block: RAM_COM + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: FCR + description: frame control register + byte_offset: 4 + fieldset: FCR + - name: SR + description: status register + byte_offset: 8 + fieldset: SR + - name: CLR + description: clear register + byte_offset: 12 + access: Write + fieldset: CLR + - name: RAM_COM + description: display memory + array: + len: 8 + stride: 8 + byte_offset: 20 + block: RAM_COM block/RAM_COM: description: display memory items: - - name: LOW - description: display memory low word - byte_offset: 0 - - name: HIGH - description: display memory high word - byte_offset: 4 + - name: LOW + description: display memory low word + byte_offset: 0 + - name: HIGH + description: display memory high word + byte_offset: 4 fieldset/CLR: description: clear register fields: - - name: SOFC - description: Start of frame flag clear - bit_offset: 1 - bit_size: 1 - - name: UDDC - description: Update display done clear - bit_offset: 3 - bit_size: 1 + - name: SOFC + description: Start of frame flag clear + bit_offset: 1 + bit_size: 1 + - name: UDDC + description: Update display done clear + bit_offset: 3 + bit_size: 1 fieldset/CR: description: control register fields: - - name: LCDEN - description: LCD controller enable - bit_offset: 0 - bit_size: 1 - - name: VSEL - description: Voltage source selection - bit_offset: 1 - bit_size: 1 - - name: DUTY - description: Duty selection - bit_offset: 2 - bit_size: 3 - - name: BIAS - description: Bias selector - bit_offset: 5 - bit_size: 2 - - name: MUX_SEG - description: Mux segment enable - bit_offset: 7 - bit_size: 1 - - name: BUFEN - description: Voltage output buffer enable - bit_offset: 8 - bit_size: 1 + - name: LCDEN + description: LCD controller enable + bit_offset: 0 + bit_size: 1 + - name: VSEL + description: Voltage source selection + bit_offset: 1 + bit_size: 1 + - name: DUTY + description: Duty selection + bit_offset: 2 + bit_size: 3 + - name: BIAS + description: Bias selector + bit_offset: 5 + bit_size: 2 + - name: MUX_SEG + description: Mux segment enable + bit_offset: 7 + bit_size: 1 + - name: BUFEN + description: Voltage output buffer enable + bit_offset: 8 + bit_size: 1 fieldset/FCR: description: frame control register fields: - - name: HD - description: High drive enable - bit_offset: 0 - bit_size: 1 - - name: SOFIE - description: Start of frame interrupt enable - bit_offset: 1 - bit_size: 1 - - name: UDDIE - description: Update display done interrupt enable - bit_offset: 3 - bit_size: 1 - - name: PON - description: Pulse ON duration - bit_offset: 4 - bit_size: 3 - - name: DEAD - description: Dead time duration - bit_offset: 7 - bit_size: 3 - - name: CC - description: Contrast control - bit_offset: 10 - bit_size: 3 - - name: BLINKF - description: Blink frequency selection - bit_offset: 13 - bit_size: 3 - - name: BLINK - description: Blink mode selection - bit_offset: 16 - bit_size: 2 - - name: DIV - description: DIV clock divider - bit_offset: 18 - bit_size: 4 - - name: PS - description: PS 16-bit prescaler - bit_offset: 22 - bit_size: 4 + - name: HD + description: High drive enable + bit_offset: 0 + bit_size: 1 + - name: SOFIE + description: Start of frame interrupt enable + bit_offset: 1 + bit_size: 1 + - name: UDDIE + description: Update display done interrupt enable + bit_offset: 3 + bit_size: 1 + - name: PON + description: Pulse ON duration + bit_offset: 4 + bit_size: 3 + - name: DEAD + description: Dead time duration + bit_offset: 7 + bit_size: 3 + - name: CC + description: Contrast control + bit_offset: 10 + bit_size: 3 + - name: BLINKF + description: Blink frequency selection + bit_offset: 13 + bit_size: 3 + - name: BLINK + description: Blink mode selection + bit_offset: 16 + bit_size: 2 + - name: DIV + description: DIV clock divider + bit_offset: 18 + bit_size: 4 + - name: PS + description: PS 16-bit prescaler + bit_offset: 22 + bit_size: 4 fieldset/SR: description: status register fields: - - name: ENS - description: LCD enabled status - bit_offset: 0 - bit_size: 1 - - name: SOF - description: Start of frame flag - bit_offset: 1 - bit_size: 1 - - name: UDR - description: Update display request - bit_offset: 2 - bit_size: 1 - - name: UDD - description: Update Display Done - bit_offset: 3 - bit_size: 1 - - name: RDY - description: Ready flag - bit_offset: 4 - bit_size: 1 - - name: FCRSF - description: LCD Frame Control Register Synchronization flag - bit_offset: 5 - bit_size: 1 + - name: ENS + description: LCD enabled status + bit_offset: 0 + bit_size: 1 + - name: SOF + description: Start of frame flag + bit_offset: 1 + bit_size: 1 + - name: UDR + description: Update display request + bit_offset: 2 + bit_size: 1 + - name: UDD + description: Update Display Done + bit_offset: 3 + bit_size: 1 + - name: RDY + description: Ready flag + bit_offset: 4 + bit_size: 1 + - name: FCRSF + description: LCD Frame Control Register Synchronization flag + bit_offset: 5 + bit_size: 1 diff --git a/data/registers/lptim_v1.yaml b/data/registers/lptim_v1.yaml index 839d7c3..7a85c84 100644 --- a/data/registers/lptim_v1.yaml +++ b/data/registers/lptim_v1.yaml @@ -1,223 +1,222 @@ ---- block/LPTIM: description: Low power timer items: - - name: ISR - description: Interrupt and Status Register - byte_offset: 0 - access: Read - fieldset: ISR - - name: ICR - description: Interrupt Clear Register - byte_offset: 4 - access: Write - fieldset: ICR - - name: IER - description: Interrupt Enable Register - byte_offset: 8 - fieldset: IER - - name: CFGR - description: Configuration Register - byte_offset: 12 - fieldset: CFGR - - name: CR - description: Control Register - byte_offset: 16 - fieldset: CR - - name: CMP - description: Compare Register - byte_offset: 20 - fieldset: CMP - - name: ARR - description: Autoreload Register - byte_offset: 24 - fieldset: ARR - - name: CNT - description: Counter Register - byte_offset: 28 - access: Read - fieldset: CNT + - name: ISR + description: Interrupt and Status Register + byte_offset: 0 + access: Read + fieldset: ISR + - name: ICR + description: Interrupt Clear Register + byte_offset: 4 + access: Write + fieldset: ICR + - name: IER + description: Interrupt Enable Register + byte_offset: 8 + fieldset: IER + - name: CFGR + description: Configuration Register + byte_offset: 12 + fieldset: CFGR + - name: CR + description: Control Register + byte_offset: 16 + fieldset: CR + - name: CMP + description: Compare Register + byte_offset: 20 + fieldset: CMP + - name: ARR + description: Autoreload Register + byte_offset: 24 + fieldset: ARR + - name: CNT + description: Counter Register + byte_offset: 28 + access: Read + fieldset: CNT fieldset/ARR: description: Autoreload Register fields: - - name: ARR - description: Auto reload value - bit_offset: 0 - bit_size: 16 + - name: ARR + description: Auto reload value + bit_offset: 0 + bit_size: 16 fieldset/CFGR: description: Configuration Register fields: - - name: CKSEL - description: Clock selector - bit_offset: 0 - bit_size: 1 - - name: CKPOL - description: Clock Polarity - bit_offset: 1 - bit_size: 2 - - name: CKFLT - description: Configurable digital filter for external clock - bit_offset: 3 - bit_size: 2 - - name: TRGFLT - description: Configurable digital filter for trigger - bit_offset: 6 - bit_size: 2 - - name: PRESC - description: Clock prescaler - bit_offset: 9 - bit_size: 3 - - name: TRIGSEL - description: Trigger selector - bit_offset: 13 - bit_size: 3 - - name: TRIGEN - description: Trigger enable and polarity - bit_offset: 17 - bit_size: 2 - - name: TIMOUT - description: Timeout enable - bit_offset: 19 - bit_size: 1 - - name: WAVE - description: Waveform shape - bit_offset: 20 - bit_size: 1 - - name: WAVPOL - description: Waveform shape polarity - bit_offset: 21 - bit_size: 1 - - name: PRELOAD - description: Registers update mode - bit_offset: 22 - bit_size: 1 - - name: COUNTMODE - description: counter mode enabled - bit_offset: 23 - bit_size: 1 - - name: ENC - description: Encoder mode enable - bit_offset: 24 - bit_size: 1 + - name: CKSEL + description: Clock selector + bit_offset: 0 + bit_size: 1 + - name: CKPOL + description: Clock Polarity + bit_offset: 1 + bit_size: 2 + - name: CKFLT + description: Configurable digital filter for external clock + bit_offset: 3 + bit_size: 2 + - name: TRGFLT + description: Configurable digital filter for trigger + bit_offset: 6 + bit_size: 2 + - name: PRESC + description: Clock prescaler + bit_offset: 9 + bit_size: 3 + - name: TRIGSEL + description: Trigger selector + bit_offset: 13 + bit_size: 3 + - name: TRIGEN + description: Trigger enable and polarity + bit_offset: 17 + bit_size: 2 + - name: TIMOUT + description: Timeout enable + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: Waveform shape polarity + bit_offset: 21 + bit_size: 1 + - name: PRELOAD + description: Registers update mode + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled + bit_offset: 23 + bit_size: 1 + - name: ENC + description: Encoder mode enable + bit_offset: 24 + bit_size: 1 fieldset/CMP: description: Compare Register fields: - - name: CMP - description: Compare value - bit_offset: 0 - bit_size: 16 + - name: CMP + description: Compare value + bit_offset: 0 + bit_size: 16 fieldset/CNT: description: Counter Register fields: - - name: CNT - description: Counter value - bit_offset: 0 - bit_size: 16 + - name: CNT + description: Counter value + bit_offset: 0 + bit_size: 16 fieldset/CR: description: Control Register fields: - - name: ENABLE - description: LPTIM Enable - bit_offset: 0 - bit_size: 1 - - name: SNGSTRT - description: LPTIM start in single mode - bit_offset: 1 - bit_size: 1 - - name: CNTSTRT - description: Timer start in continuous mode - bit_offset: 2 - bit_size: 1 + - name: ENABLE + description: LPTIM Enable + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in single mode + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in continuous mode + bit_offset: 2 + bit_size: 1 fieldset/ICR: description: Interrupt Clear Register fields: - - name: CMPMCF - description: compare match Clear Flag - bit_offset: 0 - bit_size: 1 - - name: ARRMCF - description: Autoreload match Clear Flag - bit_offset: 1 - bit_size: 1 - - name: EXTTRIGCF - description: External trigger valid edge Clear Flag - bit_offset: 2 - bit_size: 1 - - name: CMPOKCF - description: Compare register update OK Clear Flag - bit_offset: 3 - bit_size: 1 - - name: ARROKCF - description: Autoreload register update OK Clear Flag - bit_offset: 4 - bit_size: 1 - - name: UPCF - description: Direction change to UP Clear Flag - bit_offset: 5 - bit_size: 1 - - name: DOWNCF - description: Direction change to down Clear Flag - bit_offset: 6 - bit_size: 1 + - name: CMPMCF + description: compare match Clear Flag + bit_offset: 0 + bit_size: 1 + - name: ARRMCF + description: Autoreload match Clear Flag + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge Clear Flag + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register update OK Clear Flag + bit_offset: 3 + bit_size: 1 + - name: ARROKCF + description: Autoreload register update OK Clear Flag + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: Direction change to UP Clear Flag + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: Direction change to down Clear Flag + bit_offset: 6 + bit_size: 1 fieldset/IER: description: Interrupt Enable Register fields: - - name: CMPMIE - description: Compare match Interrupt Enable - bit_offset: 0 - bit_size: 1 - - name: ARRMIE - description: Autoreload match Interrupt Enable - bit_offset: 1 - bit_size: 1 - - name: EXTTRIGIE - description: External trigger valid edge Interrupt Enable - bit_offset: 2 - bit_size: 1 - - name: CMPOKIE - description: Compare register update OK Interrupt Enable - bit_offset: 3 - bit_size: 1 - - name: ARROKIE - description: Autoreload register update OK Interrupt Enable - bit_offset: 4 - bit_size: 1 - - name: UPIE - description: Direction change to UP Interrupt Enable - bit_offset: 5 - bit_size: 1 - - name: DOWNIE - description: Direction change to down Interrupt Enable - bit_offset: 6 - bit_size: 1 + - name: CMPMIE + description: Compare match Interrupt Enable + bit_offset: 0 + bit_size: 1 + - name: ARRMIE + description: Autoreload match Interrupt Enable + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register update OK Interrupt Enable + bit_offset: 3 + bit_size: 1 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: Direction change to UP Interrupt Enable + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: Direction change to down Interrupt Enable + bit_offset: 6 + bit_size: 1 fieldset/ISR: description: Interrupt and Status Register fields: - - name: CMPM - description: Compare match - bit_offset: 0 - bit_size: 1 - - name: ARRM - description: Autoreload match - bit_offset: 1 - bit_size: 1 - - name: EXTTRIG - description: External trigger edge event - bit_offset: 2 - bit_size: 1 - - name: CMPOK - description: Compare register update OK - bit_offset: 3 - bit_size: 1 - - name: ARROK - description: Autoreload register update OK - bit_offset: 4 - bit_size: 1 - - name: UP - description: Counter direction change down to up - bit_offset: 5 - bit_size: 1 - - name: DOWN - description: Counter direction change up to down - bit_offset: 6 - bit_size: 1 + - name: CMPM + description: Compare match + bit_offset: 0 + bit_size: 1 + - name: ARRM + description: Autoreload match + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: Compare register update OK + bit_offset: 3 + bit_size: 1 + - name: ARROK + description: Autoreload register update OK + bit_offset: 4 + bit_size: 1 + - name: UP + description: Counter direction change down to up + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: Counter direction change up to down + bit_offset: 6 + bit_size: 1 diff --git a/data/registers/ltdc_v1.yaml b/data/registers/ltdc_v1.yaml index c8c5026..ea6b881 100644 --- a/data/registers/ltdc_v1.yaml +++ b/data/registers/ltdc_v1.yaml @@ -1,757 +1,756 @@ ---- block/LAYER: - description: "Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR" + description: Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR items: - - name: CR - description: Layerx Control Register - byte_offset: 0 - fieldset: CR - - name: WHPCR - description: Layerx Window Horizontal Position Configuration Register - byte_offset: 4 - fieldset: WHPCR - - name: WVPCR - description: Layerx Window Vertical Position Configuration Register - byte_offset: 8 - fieldset: WVPCR - - name: CKCR - description: Layerx Color Keying Configuration Register - byte_offset: 12 - fieldset: CKCR - - name: PFCR - description: Layerx Pixel Format Configuration Register - byte_offset: 16 - fieldset: PFCR - - name: CACR - description: Layerx Constant Alpha Configuration Register - byte_offset: 20 - fieldset: CACR - - name: DCCR - description: Layerx Default Color Configuration Register - byte_offset: 24 - fieldset: DCCR - - name: BFCR - description: Layerx Blending Factors Configuration Register - byte_offset: 28 - fieldset: BFCR - - name: CFBAR - description: Layerx Color Frame Buffer Address Register - byte_offset: 40 - fieldset: CFBAR - - name: CFBLR - description: Layerx Color Frame Buffer Length Register - byte_offset: 44 - fieldset: CFBLR - - name: CFBLNR - description: Layerx ColorFrame Buffer Line Number Register - byte_offset: 48 - fieldset: CFBLNR - - name: CLUTWR - description: Layerx CLUT Write Register - byte_offset: 64 - access: Write - fieldset: CLUTWR + - name: CR + description: Layerx Control Register + byte_offset: 0 + fieldset: CR + - name: WHPCR + description: Layerx Window Horizontal Position Configuration Register + byte_offset: 4 + fieldset: WHPCR + - name: WVPCR + description: Layerx Window Vertical Position Configuration Register + byte_offset: 8 + fieldset: WVPCR + - name: CKCR + description: Layerx Color Keying Configuration Register + byte_offset: 12 + fieldset: CKCR + - name: PFCR + description: Layerx Pixel Format Configuration Register + byte_offset: 16 + fieldset: PFCR + - name: CACR + description: Layerx Constant Alpha Configuration Register + byte_offset: 20 + fieldset: CACR + - name: DCCR + description: Layerx Default Color Configuration Register + byte_offset: 24 + fieldset: DCCR + - name: BFCR + description: Layerx Blending Factors Configuration Register + byte_offset: 28 + fieldset: BFCR + - name: CFBAR + description: Layerx Color Frame Buffer Address Register + byte_offset: 40 + fieldset: CFBAR + - name: CFBLR + description: Layerx Color Frame Buffer Length Register + byte_offset: 44 + fieldset: CFBLR + - name: CFBLNR + description: Layerx ColorFrame Buffer Line Number Register + byte_offset: 48 + fieldset: CFBLNR + - name: CLUTWR + description: Layerx CLUT Write Register + byte_offset: 64 + access: Write + fieldset: CLUTWR block/LTDC: description: LCD-TFT Controller items: - - name: SSCR - description: Synchronization Size Configuration Register - byte_offset: 8 - fieldset: SSCR - - name: BPCR - description: Back Porch Configuration Register - byte_offset: 12 - fieldset: BPCR - - name: AWCR - description: Active Width Configuration Register - byte_offset: 16 - fieldset: AWCR - - name: TWCR - description: Total Width Configuration Register - byte_offset: 20 - fieldset: TWCR - - name: GCR - description: Global Control Register - byte_offset: 24 - fieldset: GCR - - name: SRCR - description: Shadow Reload Configuration Register - byte_offset: 36 - fieldset: SRCR - - name: BCCR - description: Background Color Configuration Register - byte_offset: 44 - fieldset: BCCR - - name: IER - description: Interrupt Enable Register - byte_offset: 52 - fieldset: IER - - name: ISR - description: Interrupt Status Register - byte_offset: 56 - access: Read - fieldset: ISR - - name: ICR - description: Interrupt Clear Register - byte_offset: 60 - access: Write - fieldset: ICR - - name: LIPCR - description: Line Interrupt Position Configuration Register - byte_offset: 64 - fieldset: LIPCR - - name: CPSR - description: Current Position Status Register - byte_offset: 68 - access: Read - fieldset: CPSR - - name: CDSR - description: Current Display Status Register - byte_offset: 72 - access: Read - fieldset: CDSR - - name: LAYER - description: "Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR" - array: - len: 2 - stride: 128 - byte_offset: 132 - block: LAYER + - name: SSCR + description: Synchronization Size Configuration Register + byte_offset: 8 + fieldset: SSCR + - name: BPCR + description: Back Porch Configuration Register + byte_offset: 12 + fieldset: BPCR + - name: AWCR + description: Active Width Configuration Register + byte_offset: 16 + fieldset: AWCR + - name: TWCR + description: Total Width Configuration Register + byte_offset: 20 + fieldset: TWCR + - name: GCR + description: Global Control Register + byte_offset: 24 + fieldset: GCR + - name: SRCR + description: Shadow Reload Configuration Register + byte_offset: 36 + fieldset: SRCR + - name: BCCR + description: Background Color Configuration Register + byte_offset: 44 + fieldset: BCCR + - name: IER + description: Interrupt Enable Register + byte_offset: 52 + fieldset: IER + - name: ISR + description: Interrupt Status Register + byte_offset: 56 + access: Read + fieldset: ISR + - name: ICR + description: Interrupt Clear Register + byte_offset: 60 + access: Write + fieldset: ICR + - name: LIPCR + description: Line Interrupt Position Configuration Register + byte_offset: 64 + fieldset: LIPCR + - name: CPSR + description: Current Position Status Register + byte_offset: 68 + access: Read + fieldset: CPSR + - name: CDSR + description: Current Display Status Register + byte_offset: 72 + access: Read + fieldset: CDSR + - name: LAYER + description: Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR + array: + len: 2 + stride: 128 + byte_offset: 132 + block: LAYER fieldset/AWCR: description: Active Width Configuration Register fields: - - name: AAH - description: Accumulated Active Height (in units of horizontal scan line) - bit_offset: 0 - bit_size: 11 - - name: AAW - description: Accumulated Active Width (in units of pixel clock period) - bit_offset: 16 - bit_size: 12 + - name: AAH + description: Accumulated Active Height (in units of horizontal scan line) + bit_offset: 0 + bit_size: 11 + - name: AAW + description: Accumulated Active Width (in units of pixel clock period) + bit_offset: 16 + bit_size: 12 fieldset/BCCR: description: Background Color Configuration Register fields: - - name: BCBLUE - description: Background color blue value - bit_offset: 0 - bit_size: 8 - - name: BCGREEN - description: Background color green value - bit_offset: 8 - bit_size: 8 - - name: BCRED - description: Background color red value - bit_offset: 16 - bit_size: 8 + - name: BCBLUE + description: Background color blue value + bit_offset: 0 + bit_size: 8 + - name: BCGREEN + description: Background color green value + bit_offset: 8 + bit_size: 8 + - name: BCRED + description: Background color red value + bit_offset: 16 + bit_size: 8 fieldset/BFCR: description: Layerx Blending Factors Configuration Register fields: - - name: BF - description: Blending Factor 2 - bit_offset: 0 - bit_size: 3 - array: - len: 2 - stride: 8 - enum: BF2 + - name: BF + description: Blending Factor 2 + bit_offset: 0 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: BF2 fieldset/BPCR: description: Back Porch Configuration Register fields: - - name: AVBP - description: Accumulated Vertical back porch (in units of horizontal scan line) - bit_offset: 0 - bit_size: 11 - - name: AHBP - description: Accumulated Horizontal back porch (in units of pixel clock period) - bit_offset: 16 - bit_size: 12 + - name: AVBP + description: Accumulated Vertical back porch (in units of horizontal scan line) + bit_offset: 0 + bit_size: 11 + - name: AHBP + description: Accumulated Horizontal back porch (in units of pixel clock period) + bit_offset: 16 + bit_size: 12 fieldset/CACR: description: Layerx Constant Alpha Configuration Register fields: - - name: CONSTA - description: Constant Alpha - bit_offset: 0 - bit_size: 8 + - name: CONSTA + description: Constant Alpha + bit_offset: 0 + bit_size: 8 fieldset/CDSR: description: Current Display Status Register fields: - - name: VDES - description: Vertical Data Enable display Status - bit_offset: 0 - bit_size: 1 - enum: VDES - - name: HDES - description: Horizontal Data Enable display Status - bit_offset: 1 - bit_size: 1 - enum: HDES - - name: VSYNCS - description: Vertical Synchronization display Status - bit_offset: 2 - bit_size: 1 - enum: VSYNCS - - name: HSYNCS - description: Horizontal Synchronization display Status - bit_offset: 3 - bit_size: 1 - enum: HSYNCS + - name: VDES + description: Vertical Data Enable display Status + bit_offset: 0 + bit_size: 1 + enum: VDES + - name: HDES + description: Horizontal Data Enable display Status + bit_offset: 1 + bit_size: 1 + enum: HDES + - name: VSYNCS + description: Vertical Synchronization display Status + bit_offset: 2 + bit_size: 1 + enum: VSYNCS + - name: HSYNCS + description: Horizontal Synchronization display Status + bit_offset: 3 + bit_size: 1 + enum: HSYNCS fieldset/CFBAR: description: Layerx Color Frame Buffer Address Register fields: - - name: CFBADD - description: Color Frame Buffer Start Address - bit_offset: 0 - bit_size: 32 + - name: CFBADD + description: Color Frame Buffer Start Address + bit_offset: 0 + bit_size: 32 fieldset/CFBLNR: description: Layerx ColorFrame Buffer Line Number Register fields: - - name: CFBLNBR - description: Frame Buffer Line Number - bit_offset: 0 - bit_size: 11 + - name: CFBLNBR + description: Frame Buffer Line Number + bit_offset: 0 + bit_size: 11 fieldset/CFBLR: description: Layerx Color Frame Buffer Length Register fields: - - name: CFBLL - description: Color Frame Buffer Line Length - bit_offset: 0 - bit_size: 13 - - name: CFBP - description: Color Frame Buffer Pitch in bytes - bit_offset: 16 - bit_size: 13 + - name: CFBLL + description: Color Frame Buffer Line Length + bit_offset: 0 + bit_size: 13 + - name: CFBP + description: Color Frame Buffer Pitch in bytes + bit_offset: 16 + bit_size: 13 fieldset/CKCR: description: Layerx Color Keying Configuration Register fields: - - name: CKBLUE - description: Color Key Blue value - bit_offset: 0 - bit_size: 8 - - name: CKGREEN - description: Color Key Green value - bit_offset: 8 - bit_size: 8 - - name: CKRED - description: Color Key Red value - bit_offset: 16 - bit_size: 8 + - name: CKBLUE + description: Color Key Blue value + bit_offset: 0 + bit_size: 8 + - name: CKGREEN + description: Color Key Green value + bit_offset: 8 + bit_size: 8 + - name: CKRED + description: Color Key Red value + bit_offset: 16 + bit_size: 8 fieldset/CLUTWR: description: Layerx CLUT Write Register fields: - - name: BLUE - description: Blue value - bit_offset: 0 - bit_size: 8 - - name: GREEN - description: Green value - bit_offset: 8 - bit_size: 8 - - name: RED - description: Red value - bit_offset: 16 - bit_size: 8 - - name: CLUTADD - description: CLUT Address - bit_offset: 24 - bit_size: 8 + - name: BLUE + description: Blue value + bit_offset: 0 + bit_size: 8 + - name: GREEN + description: Green value + bit_offset: 8 + bit_size: 8 + - name: RED + description: Red value + bit_offset: 16 + bit_size: 8 + - name: CLUTADD + description: CLUT Address + bit_offset: 24 + bit_size: 8 fieldset/CPSR: description: Current Position Status Register fields: - - name: CYPOS - description: Current Y Position - bit_offset: 0 - bit_size: 16 - - name: CXPOS - description: Current X Position - bit_offset: 16 - bit_size: 16 + - name: CYPOS + description: Current Y Position + bit_offset: 0 + bit_size: 16 + - name: CXPOS + description: Current X Position + bit_offset: 16 + bit_size: 16 fieldset/CR: description: Layerx Control Register fields: - - name: LEN - description: Layer Enable - bit_offset: 0 - bit_size: 1 - enum: LEN - - name: COLKEN - description: Color Keying Enable - bit_offset: 1 - bit_size: 1 - enum: COLKEN - - name: CLUTEN - description: Color Look-Up Table Enable - bit_offset: 4 - bit_size: 1 - enum: CLUTEN + - name: LEN + description: Layer Enable + bit_offset: 0 + bit_size: 1 + enum: LEN + - name: COLKEN + description: Color Keying Enable + bit_offset: 1 + bit_size: 1 + enum: COLKEN + - name: CLUTEN + description: Color Look-Up Table Enable + bit_offset: 4 + bit_size: 1 + enum: CLUTEN fieldset/DCCR: description: Layerx Default Color Configuration Register fields: - - name: DCBLUE - description: Default Color Blue - bit_offset: 0 - bit_size: 8 - - name: DCGREEN - description: Default Color Green - bit_offset: 8 - bit_size: 8 - - name: DCRED - description: Default Color Red - bit_offset: 16 - bit_size: 8 - - name: DCALPHA - description: Default Color Alpha - bit_offset: 24 - bit_size: 8 + - name: DCBLUE + description: Default Color Blue + bit_offset: 0 + bit_size: 8 + - name: DCGREEN + description: Default Color Green + bit_offset: 8 + bit_size: 8 + - name: DCRED + description: Default Color Red + bit_offset: 16 + bit_size: 8 + - name: DCALPHA + description: Default Color Alpha + bit_offset: 24 + bit_size: 8 fieldset/GCR: description: Global Control Register fields: - - name: LTDCEN - description: LCD-TFT controller enable bit - bit_offset: 0 - bit_size: 1 - enum: LTDCEN - - name: DBW - description: Dither Blue Width - bit_offset: 4 - bit_size: 3 - - name: DGW - description: Dither Green Width - bit_offset: 8 - bit_size: 3 - - name: DRW - description: Dither Red Width - bit_offset: 12 - bit_size: 3 - - name: DEN - description: Dither Enable - bit_offset: 16 - bit_size: 1 - enum: DEN - - name: PCPOL - description: Pixel Clock Polarity - bit_offset: 28 - bit_size: 1 - enum: PCPOL - - name: DEPOL - description: Data Enable Polarity - bit_offset: 29 - bit_size: 1 - enum: DEPOL - - name: VSPOL - description: Vertical Synchronization Polarity - bit_offset: 30 - bit_size: 1 - enum: VSPOL - - name: HSPOL - description: Horizontal Synchronization Polarity - bit_offset: 31 - bit_size: 1 - enum: HSPOL + - name: LTDCEN + description: LCD-TFT controller enable bit + bit_offset: 0 + bit_size: 1 + enum: LTDCEN + - name: DBW + description: Dither Blue Width + bit_offset: 4 + bit_size: 3 + - name: DGW + description: Dither Green Width + bit_offset: 8 + bit_size: 3 + - name: DRW + description: Dither Red Width + bit_offset: 12 + bit_size: 3 + - name: DEN + description: Dither Enable + bit_offset: 16 + bit_size: 1 + enum: DEN + - name: PCPOL + description: Pixel Clock Polarity + bit_offset: 28 + bit_size: 1 + enum: PCPOL + - name: DEPOL + description: Data Enable Polarity + bit_offset: 29 + bit_size: 1 + enum: DEPOL + - name: VSPOL + description: Vertical Synchronization Polarity + bit_offset: 30 + bit_size: 1 + enum: VSPOL + - name: HSPOL + description: Horizontal Synchronization Polarity + bit_offset: 31 + bit_size: 1 + enum: HSPOL fieldset/ICR: description: Interrupt Clear Register fields: - - name: CLIF - description: Clears the Line Interrupt Flag - bit_offset: 0 - bit_size: 1 - enum: CLIF - - name: CFUIF - description: Clears the FIFO Underrun Interrupt flag - bit_offset: 1 - bit_size: 1 - enum: CFUIF - - name: CTERRIF - description: Clears the Transfer Error Interrupt Flag - bit_offset: 2 - bit_size: 1 - enum: CTERRIF - - name: CRRIF - description: Clears Register Reload Interrupt Flag - bit_offset: 3 - bit_size: 1 - enum: CRRIF + - name: CLIF + description: Clears the Line Interrupt Flag + bit_offset: 0 + bit_size: 1 + enum: CLIF + - name: CFUIF + description: Clears the FIFO Underrun Interrupt flag + bit_offset: 1 + bit_size: 1 + enum: CFUIF + - name: CTERRIF + description: Clears the Transfer Error Interrupt Flag + bit_offset: 2 + bit_size: 1 + enum: CTERRIF + - name: CRRIF + description: Clears Register Reload Interrupt Flag + bit_offset: 3 + bit_size: 1 + enum: CRRIF fieldset/IER: description: Interrupt Enable Register fields: - - name: LIE - description: Line Interrupt Enable - bit_offset: 0 - bit_size: 1 - enum: LIE - - name: FUIE - description: FIFO Underrun Interrupt Enable - bit_offset: 1 - bit_size: 1 - enum: FUIE - - name: TERRIE - description: Transfer Error Interrupt Enable - bit_offset: 2 - bit_size: 1 - enum: TERRIE - - name: RRIE - description: Register Reload interrupt enable - bit_offset: 3 - bit_size: 1 - enum: RRIE + - name: LIE + description: Line Interrupt Enable + bit_offset: 0 + bit_size: 1 + enum: LIE + - name: FUIE + description: FIFO Underrun Interrupt Enable + bit_offset: 1 + bit_size: 1 + enum: FUIE + - name: TERRIE + description: Transfer Error Interrupt Enable + bit_offset: 2 + bit_size: 1 + enum: TERRIE + - name: RRIE + description: Register Reload interrupt enable + bit_offset: 3 + bit_size: 1 + enum: RRIE fieldset/ISR: description: Interrupt Status Register fields: - - name: LIF - description: Line Interrupt flag - bit_offset: 0 - bit_size: 1 - enum: LIF - - name: FUIF - description: FIFO Underrun Interrupt flag - bit_offset: 1 - bit_size: 1 - enum: FUIF - - name: TERRIF - description: Transfer Error interrupt flag - bit_offset: 2 - bit_size: 1 - enum: TERRIF - - name: RRIF - description: Register Reload Interrupt Flag - bit_offset: 3 - bit_size: 1 - enum: RRIF + - name: LIF + description: Line Interrupt flag + bit_offset: 0 + bit_size: 1 + enum: LIF + - name: FUIF + description: FIFO Underrun Interrupt flag + bit_offset: 1 + bit_size: 1 + enum: FUIF + - name: TERRIF + description: Transfer Error interrupt flag + bit_offset: 2 + bit_size: 1 + enum: TERRIF + - name: RRIF + description: Register Reload Interrupt Flag + bit_offset: 3 + bit_size: 1 + enum: RRIF fieldset/LIPCR: description: Line Interrupt Position Configuration Register fields: - - name: LIPOS - description: Line Interrupt Position - bit_offset: 0 - bit_size: 11 + - name: LIPOS + description: Line Interrupt Position + bit_offset: 0 + bit_size: 11 fieldset/PFCR: description: Layerx Pixel Format Configuration Register fields: - - name: PF - description: Pixel Format - bit_offset: 0 - bit_size: 3 - enum: PF + - name: PF + description: Pixel Format + bit_offset: 0 + bit_size: 3 + enum: PF fieldset/SRCR: description: Shadow Reload Configuration Register fields: - - name: IMR - description: Immediate Reload - bit_offset: 0 - bit_size: 1 - enum: IMR - - name: VBR - description: Vertical Blanking Reload - bit_offset: 1 - bit_size: 1 - enum: VBR + - name: IMR + description: Immediate Reload + bit_offset: 0 + bit_size: 1 + enum: IMR + - name: VBR + description: Vertical Blanking Reload + bit_offset: 1 + bit_size: 1 + enum: VBR fieldset/SSCR: description: Synchronization Size Configuration Register fields: - - name: VSH - description: Vertical Synchronization Height (in units of horizontal scan line) - bit_offset: 0 - bit_size: 11 - - name: HSW - description: Horizontal Synchronization Width (in units of pixel clock period) - bit_offset: 16 - bit_size: 12 + - name: VSH + description: Vertical Synchronization Height (in units of horizontal scan line) + bit_offset: 0 + bit_size: 11 + - name: HSW + description: Horizontal Synchronization Width (in units of pixel clock period) + bit_offset: 16 + bit_size: 12 fieldset/TWCR: description: Total Width Configuration Register fields: - - name: TOTALH - description: Total Height (in units of horizontal scan line) - bit_offset: 0 - bit_size: 11 - - name: TOTALW - description: Total Width (in units of pixel clock period) - bit_offset: 16 - bit_size: 12 + - name: TOTALH + description: Total Height (in units of horizontal scan line) + bit_offset: 0 + bit_size: 11 + - name: TOTALW + description: Total Width (in units of pixel clock period) + bit_offset: 16 + bit_size: 12 fieldset/WHPCR: description: Layerx Window Horizontal Position Configuration Register fields: - - name: WHSTPOS - description: Window Horizontal Start Position - bit_offset: 0 - bit_size: 12 - - name: WHSPPOS - description: Window Horizontal Stop Position - bit_offset: 16 - bit_size: 12 + - name: WHSTPOS + description: Window Horizontal Start Position + bit_offset: 0 + bit_size: 12 + - name: WHSPPOS + description: Window Horizontal Stop Position + bit_offset: 16 + bit_size: 12 fieldset/WVPCR: description: Layerx Window Vertical Position Configuration Register fields: - - name: WVSTPOS - description: Window Vertical Start Position - bit_offset: 0 - bit_size: 11 - - name: WVSPPOS - description: Window Vertical Stop Position - bit_offset: 16 - bit_size: 11 + - name: WVSTPOS + description: Window Vertical Start Position + bit_offset: 0 + bit_size: 11 + - name: WVSPPOS + description: Window Vertical Stop Position + bit_offset: 16 + bit_size: 11 enum/BF2: bit_size: 3 variants: - - name: Constant - description: BF2 = 1 - constant alpha - value: 5 - - name: Pixel - description: BF2 = 1 - pixel alpha * constant alpha - value: 7 + - name: Constant + description: BF2 = 1 - constant alpha + value: 5 + - name: Pixel + description: BF2 = 1 - pixel alpha * constant alpha + value: 7 enum/CFUIF: bit_size: 1 variants: - - name: Clear - description: Clears the FUIF flag in the ISR register - value: 1 + - name: Clear + description: Clears the FUIF flag in the ISR register + value: 1 enum/CLIF: bit_size: 1 variants: - - name: Clear - description: Clears the LIF flag in the ISR register - value: 1 + - name: Clear + description: Clears the LIF flag in the ISR register + value: 1 enum/CLUTEN: bit_size: 1 variants: - - name: Disabled - description: Color look-up table disabled - value: 0 - - name: Enabled - description: Color look-up table enabled - value: 1 + - name: Disabled + description: Color look-up table disabled + value: 0 + - name: Enabled + description: Color look-up table enabled + value: 1 enum/COLKEN: bit_size: 1 variants: - - name: Disabled - description: Color keying disabled - value: 0 - - name: Enabled - description: Color keying enabled - value: 1 + - name: Disabled + description: Color keying disabled + value: 0 + - name: Enabled + description: Color keying enabled + value: 1 enum/CRRIF: bit_size: 1 variants: - - name: Clear - description: Clears the RRIF flag in the ISR register - value: 1 + - name: Clear + description: Clears the RRIF flag in the ISR register + value: 1 enum/CTERRIF: bit_size: 1 variants: - - name: Clear - description: Clears the TERRIF flag in the ISR register - value: 1 + - name: Clear + description: Clears the TERRIF flag in the ISR register + value: 1 enum/DEN: bit_size: 1 variants: - - name: Disabled - description: Dither disabled - value: 0 - - name: Enabled - description: Dither enabled - value: 1 + - name: Disabled + description: Dither disabled + value: 0 + - name: Enabled + description: Dither enabled + value: 1 enum/DEPOL: bit_size: 1 variants: - - name: ActiveLow - description: Data enable polarity is active low - value: 0 - - name: ActiveHigh - description: Data enable polarity is active high - value: 1 + - name: ActiveLow + description: Data enable polarity is active low + value: 0 + - name: ActiveHigh + description: Data enable polarity is active high + value: 1 enum/FUIE: bit_size: 1 variants: - - name: Disabled - description: FIFO underrun interrupt disabled - value: 0 - - name: Enabled - description: FIFO underrun interrupt enabled - value: 1 + - name: Disabled + description: FIFO underrun interrupt disabled + value: 0 + - name: Enabled + description: FIFO underrun interrupt enabled + value: 1 enum/FUIF: bit_size: 1 variants: - - name: NoUnderrun - description: No FIFO underrun - value: 0 - - name: Underrun - description: "FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO" - value: 1 + - name: NoUnderrun + description: No FIFO underrun + value: 0 + - name: Underrun + description: FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO + value: 1 enum/HDES: bit_size: 1 variants: - - name: NotActive - description: Currently not in horizontal Data Enable phase - value: 0 - - name: Active - description: Currently in horizontal Data Enable phase - value: 1 + - name: NotActive + description: Currently not in horizontal Data Enable phase + value: 0 + - name: Active + description: Currently in horizontal Data Enable phase + value: 1 enum/HSPOL: bit_size: 1 variants: - - name: ActiveLow - description: Horizontal synchronization polarity is active low - value: 0 - - name: ActiveHigh - description: Horizontal synchronization polarity is active high - value: 1 + - name: ActiveLow + description: Horizontal synchronization polarity is active low + value: 0 + - name: ActiveHigh + description: Horizontal synchronization polarity is active high + value: 1 enum/HSYNCS: bit_size: 1 variants: - - name: NotActive - description: Currently not in HSYNC phase - value: 0 - - name: Active - description: Currently in HSYNC phase - value: 1 + - name: NotActive + description: Currently not in HSYNC phase + value: 0 + - name: Active + description: Currently in HSYNC phase + value: 1 enum/IMR: bit_size: 1 variants: - - name: NoEffect - description: This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) - value: 0 - - name: Reload - description: The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload - value: 1 + - name: NoEffect + description: This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) + value: 0 + - name: Reload + description: The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload + value: 1 enum/LEN: bit_size: 1 variants: - - name: Disabled - description: Layer disabled - value: 0 - - name: Enabled - description: Layer enabled - value: 1 + - name: Disabled + description: Layer disabled + value: 0 + - name: Enabled + description: Layer enabled + value: 1 enum/LIE: bit_size: 1 variants: - - name: Disabled - description: Line interrupt disabled - value: 0 - - name: Enabled - description: Line interrupt enabled - value: 1 + - name: Disabled + description: Line interrupt disabled + value: 0 + - name: Enabled + description: Line interrupt enabled + value: 1 enum/LIF: bit_size: 1 variants: - - name: NotReached - description: Programmed line not reached - value: 0 - - name: Reached - description: Line interrupt generated when a programmed line is reached - value: 1 + - name: NotReached + description: Programmed line not reached + value: 0 + - name: Reached + description: Line interrupt generated when a programmed line is reached + value: 1 enum/LTDCEN: bit_size: 1 variants: - - name: Disabled - description: LCD-TFT controller disabled - value: 0 - - name: Enabled - description: LCD-TFT controller enabled - value: 1 + - name: Disabled + description: LCD-TFT controller disabled + value: 0 + - name: Enabled + description: LCD-TFT controller enabled + value: 1 enum/PCPOL: bit_size: 1 variants: - - name: RisingEdge - description: Pixel clock on rising edge - value: 0 - - name: FallingEdge - description: Pixel clock on falling edge - value: 1 + - name: RisingEdge + description: Pixel clock on rising edge + value: 0 + - name: FallingEdge + description: Pixel clock on falling edge + value: 1 enum/PF: bit_size: 3 variants: - - name: ARGB8888 - description: ARGB8888 - value: 0 - - name: RGB888 - description: RGB888 - value: 1 - - name: RGB565 - description: RGB565 - value: 2 - - name: ARGB1555 - description: ARGB1555 - value: 3 - - name: ARGB4444 - description: ARGB4444 - value: 4 - - name: L8 - description: L8 (8-bit luminance) - value: 5 - - name: AL44 - description: "AL44 (4-bit alpha, 4-bit luminance)" - value: 6 - - name: AL88 - description: "AL88 (8-bit alpha, 8-bit luminance)" - value: 7 + - name: ARGB8888 + description: ARGB8888 + value: 0 + - name: RGB888 + description: RGB888 + value: 1 + - name: RGB565 + description: RGB565 + value: 2 + - name: ARGB1555 + description: ARGB1555 + value: 3 + - name: ARGB4444 + description: ARGB4444 + value: 4 + - name: L8 + description: L8 (8-bit luminance) + value: 5 + - name: AL44 + description: AL44 (4-bit alpha, 4-bit luminance) + value: 6 + - name: AL88 + description: AL88 (8-bit alpha, 8-bit luminance) + value: 7 enum/RRIE: bit_size: 1 variants: - - name: Disabled - description: Register reload interrupt disabled - value: 0 - - name: Enabled - description: Register reload interrupt enabled - value: 1 + - name: Disabled + description: Register reload interrupt disabled + value: 0 + - name: Enabled + description: Register reload interrupt enabled + value: 1 enum/RRIF: bit_size: 1 variants: - - name: NoReload - description: No register reload - value: 0 - - name: Reload - description: Register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) - value: 1 + - name: NoReload + description: No register reload + value: 0 + - name: Reload + description: Register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) + value: 1 enum/TERRIE: bit_size: 1 variants: - - name: Disabled - description: Transfer error interrupt disabled - value: 0 - - name: Enabled - description: Transfer error interrupt enabled - value: 1 + - name: Disabled + description: Transfer error interrupt disabled + value: 0 + - name: Enabled + description: Transfer error interrupt enabled + value: 1 enum/TERRIF: bit_size: 1 variants: - - name: NoError - description: No transfer error - value: 0 - - name: Error - description: Transfer error interrupt generated when a bus error occurs - value: 1 + - name: NoError + description: No transfer error + value: 0 + - name: Error + description: Transfer error interrupt generated when a bus error occurs + value: 1 enum/VBR: bit_size: 1 variants: - - name: NoEffect - description: This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) - value: 0 - - name: Reload - description: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). - value: 1 + - name: NoEffect + description: This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) + value: 0 + - name: Reload + description: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). + value: 1 enum/VDES: bit_size: 1 variants: - - name: NotActive - description: Currently not in vertical Data Enable phase - value: 0 - - name: Active - description: Currently in vertical Data Enable phase - value: 1 + - name: NotActive + description: Currently not in vertical Data Enable phase + value: 0 + - name: Active + description: Currently in vertical Data Enable phase + value: 1 enum/VSPOL: bit_size: 1 variants: - - name: ActiveLow - description: Vertical synchronization polarity is active low - value: 0 - - name: ActiveHigh - description: Vertical synchronization polarity is active high - value: 1 + - name: ActiveLow + description: Vertical synchronization polarity is active low + value: 0 + - name: ActiveHigh + description: Vertical synchronization polarity is active high + value: 1 enum/VSYNCS: bit_size: 1 variants: - - name: NotActive - description: Currently not in VSYNC phase - value: 0 - - name: Active - description: Currently in VSYNC phase - value: 1 + - name: NotActive + description: Currently not in VSYNC phase + value: 0 + - name: Active + description: Currently in VSYNC phase + value: 1 diff --git a/data/registers/mdios_v1.yaml b/data/registers/mdios_v1.yaml index 2359595..c6f5ed1 100644 --- a/data/registers/mdios_v1.yaml +++ b/data/registers/mdios_v1.yaml @@ -1,149 +1,148 @@ ---- block/MDIOS: description: Management data input/output slave items: - - name: CR - description: MDIOS configuration register - byte_offset: 0 - fieldset: CR - - name: WRFR - description: MDIOS write flag register - byte_offset: 4 - access: Read - fieldset: WRFR - - name: CWRFR - description: MDIOS clear write flag register - byte_offset: 8 - fieldset: CWRFR - - name: RDFR - description: MDIOS read flag register - byte_offset: 12 - access: Read - fieldset: RDFR - - name: CRDFR - description: MDIOS clear read flag register - byte_offset: 16 - fieldset: CRDFR - - name: SR - description: MDIOS status register - byte_offset: 20 - access: Read - fieldset: SR - - name: CLRFR - description: MDIOS clear flag register - byte_offset: 24 - fieldset: CLRFR - - name: DINR - description: MDIOS input data register %s - array: - len: 32 - stride: 4 - byte_offset: 28 - access: Read - fieldset: DINR - - name: DOUTR - description: MDIOS output data register %s - array: - len: 32 - stride: 4 - byte_offset: 156 - fieldset: DOUTR + - name: CR + description: MDIOS configuration register + byte_offset: 0 + fieldset: CR + - name: WRFR + description: MDIOS write flag register + byte_offset: 4 + access: Read + fieldset: WRFR + - name: CWRFR + description: MDIOS clear write flag register + byte_offset: 8 + fieldset: CWRFR + - name: RDFR + description: MDIOS read flag register + byte_offset: 12 + access: Read + fieldset: RDFR + - name: CRDFR + description: MDIOS clear read flag register + byte_offset: 16 + fieldset: CRDFR + - name: SR + description: MDIOS status register + byte_offset: 20 + access: Read + fieldset: SR + - name: CLRFR + description: MDIOS clear flag register + byte_offset: 24 + fieldset: CLRFR + - name: DINR + description: MDIOS input data register %s + array: + len: 32 + stride: 4 + byte_offset: 28 + access: Read + fieldset: DINR + - name: DOUTR + description: MDIOS output data register %s + array: + len: 32 + stride: 4 + byte_offset: 156 + fieldset: DOUTR fieldset/CLRFR: description: MDIOS clear flag register fields: - - name: CPERF - description: Clear the preamble error flag - bit_offset: 0 - bit_size: 1 - - name: CSERF - description: Clear the start error flag - bit_offset: 1 - bit_size: 1 - - name: CTERF - description: Clear the turnaround error flag - bit_offset: 2 - bit_size: 1 + - name: CPERF + description: Clear the preamble error flag + bit_offset: 0 + bit_size: 1 + - name: CSERF + description: Clear the start error flag + bit_offset: 1 + bit_size: 1 + - name: CTERF + description: Clear the turnaround error flag + bit_offset: 2 + bit_size: 1 fieldset/CR: description: MDIOS configuration register fields: - - name: EN - description: Peripheral enable - bit_offset: 0 - bit_size: 1 - - name: WRIE - description: Register write interrupt enable - bit_offset: 1 - bit_size: 1 - - name: RDIE - description: Register Read Interrupt Enable - bit_offset: 2 - bit_size: 1 - - name: EIE - description: Error interrupt enable - bit_offset: 3 - bit_size: 1 - - name: DPC - description: Disable Preamble Check - bit_offset: 7 - bit_size: 1 - - name: PORT_ADDRESS - description: "Slaves's address" - bit_offset: 8 - bit_size: 5 + - name: EN + description: Peripheral enable + bit_offset: 0 + bit_size: 1 + - name: WRIE + description: Register write interrupt enable + bit_offset: 1 + bit_size: 1 + - name: RDIE + description: Register Read Interrupt Enable + bit_offset: 2 + bit_size: 1 + - name: EIE + description: Error interrupt enable + bit_offset: 3 + bit_size: 1 + - name: DPC + description: Disable Preamble Check + bit_offset: 7 + bit_size: 1 + - name: PORT_ADDRESS + description: Slaves's address + bit_offset: 8 + bit_size: 5 fieldset/CRDFR: description: MDIOS clear read flag register fields: - - name: CRDF - description: Clear the read flag - bit_offset: 0 - bit_size: 32 + - name: CRDF + description: Clear the read flag + bit_offset: 0 + bit_size: 32 fieldset/CWRFR: description: MDIOS clear write flag register fields: - - name: CWRF - description: Clear the write flag - bit_offset: 0 - bit_size: 32 + - name: CWRF + description: Clear the write flag + bit_offset: 0 + bit_size: 32 fieldset/DINR: description: MDIOS input data register %s fields: - - name: DIN - description: Input data received from MDIO Master during write frames - bit_offset: 0 - bit_size: 16 + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 fieldset/DOUTR: description: MDIOS output data register %s fields: - - name: DOUT - description: Output data sent to MDIO Master during read frames - bit_offset: 0 - bit_size: 16 + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 fieldset/RDFR: description: MDIOS read flag register fields: - - name: RDF - description: Read flags for MDIO registers 0 to 31 - bit_offset: 0 - bit_size: 32 + - name: RDF + description: Read flags for MDIO registers 0 to 31 + bit_offset: 0 + bit_size: 32 fieldset/SR: description: MDIOS status register fields: - - name: PERF - description: Preamble error flag - bit_offset: 0 - bit_size: 1 - - name: SERF - description: Start error flag - bit_offset: 1 - bit_size: 1 - - name: TERF - description: Turnaround error flag - bit_offset: 2 - bit_size: 1 + - name: PERF + description: Preamble error flag + bit_offset: 0 + bit_size: 1 + - name: SERF + description: Start error flag + bit_offset: 1 + bit_size: 1 + - name: TERF + description: Turnaround error flag + bit_offset: 2 + bit_size: 1 fieldset/WRFR: description: MDIOS write flag register fields: - - name: WRF - description: Write flags for MDIO registers 0 to 31 - bit_offset: 0 - bit_size: 32 + - name: WRF + description: Write flags for MDIO registers 0 to 31 + bit_offset: 0 + bit_size: 32 diff --git a/data/registers/otg_v1.yaml b/data/registers/otg_v1.yaml index 1edc2bd..29dcf16 100644 --- a/data/registers/otg_v1.yaml +++ b/data/registers/otg_v1.yaml @@ -1,1709 +1,1708 @@ ---- block/OTG: description: USB on the go items: - - name: GOTGCTL - description: Control and status register - byte_offset: 0 - fieldset: GOTGCTL - - name: GOTGINT - description: Interrupt register - byte_offset: 4 - fieldset: GOTGINT - - name: GAHBCFG - description: AHB configuration register - byte_offset: 8 - fieldset: GAHBCFG - - name: GUSBCFG - description: USB configuration register - byte_offset: 12 - fieldset: GUSBCFG - - name: GRSTCTL - description: Reset register - byte_offset: 16 - fieldset: GRSTCTL - - name: GINTSTS - description: Core interrupt register - byte_offset: 20 - fieldset: GINTSTS - - name: GINTMSK - description: Interrupt mask register - byte_offset: 24 - fieldset: GINTMSK - - name: GRXSTSR - description: Receive status debug read register - byte_offset: 28 - access: Read - fieldset: GRXSTS - - name: GRXSTSP - description: Status read and pop register - byte_offset: 32 - access: Read - fieldset: GRXSTS - - name: GRXFSIZ - description: Receive FIFO size register - byte_offset: 36 - fieldset: GRXFSIZ - - name: DIEPTXF0 - description: Endpoint 0 transmit FIFO size register (device mode) - byte_offset: 40 - fieldset: FSIZ - - name: HNPTXFSIZ - description: Non-periodic transmit FIFO size register (host mode) - byte_offset: 40 - fieldset: FSIZ - - name: HNPTXSTS - description: Non-periodic transmit FIFO/queue status register (host mode) - byte_offset: 44 - access: Read - fieldset: HNPTXSTS - - name: GI2CCTL - description: OTG I2C access register - byte_offset: 48 - fieldset: GI2CCTL - - name: GCCFG_V1 - description: "General core configuration register, for core_id 0x0000_1xxx" - byte_offset: 56 - fieldset: GCCFG_V1 - - name: GCCFG_V2 - description: "General core configuration register, for core_id 0x0000_[23]xxx" - byte_offset: 56 - fieldset: GCCFG_V2 - - name: CID - description: Core ID register - byte_offset: 60 - fieldset: CID - - name: GLPMCFG - description: OTG core LPM configuration register - byte_offset: 84 - fieldset: GLPMCFG - - name: HPTXFSIZ - description: Host periodic transmit FIFO size register - byte_offset: 256 - fieldset: FSIZ - - name: DIEPTXF - description: Device IN endpoint transmit FIFO size register - array: - len: 7 - stride: 4 - byte_offset: 260 - fieldset: FSIZ - - name: HCFG - description: Host configuration register - byte_offset: 1024 - fieldset: HCFG - - name: HFIR - description: Host frame interval register - byte_offset: 1028 - fieldset: HFIR - - name: HFNUM - description: Host frame number/frame time remaining register - byte_offset: 1032 - access: Read - fieldset: HFNUM - - name: HPTXSTS - description: Periodic transmit FIFO/queue status register - byte_offset: 1040 - fieldset: HPTXSTS - - name: HAINT - description: Host all channels interrupt register - byte_offset: 1044 - access: Read - fieldset: HAINT - - name: HAINTMSK - description: Host all channels interrupt mask register - byte_offset: 1048 - fieldset: HAINTMSK - - name: HPRT - description: Host port control and status register - byte_offset: 1088 - fieldset: HPRT - - name: HCCHAR - description: Host channel characteristics register - array: - len: 12 - stride: 32 - byte_offset: 1280 - fieldset: HCCHAR - - name: HCSPLT - description: Host channel split control register - array: - len: 12 - stride: 32 - byte_offset: 1284 - - name: HCINT - description: Host channel interrupt register - array: - len: 12 - stride: 32 - byte_offset: 1288 - fieldset: HCINT - - name: HCINTMSK - description: Host channel mask register - array: - len: 12 - stride: 32 - byte_offset: 1292 - fieldset: HCINTMSK - - name: HCTSIZ - description: Host channel transfer size register - array: - len: 12 - stride: 32 - byte_offset: 1296 - fieldset: HCTSIZ - - name: DCFG - description: Device configuration register - byte_offset: 2048 - fieldset: DCFG - - name: DCTL - description: Device control register - byte_offset: 2052 - fieldset: DCTL - - name: DSTS - description: Device status register - byte_offset: 2056 - access: Read - fieldset: DSTS - - name: DIEPMSK - description: Device IN endpoint common interrupt mask register - byte_offset: 2064 - fieldset: DIEPMSK - - name: DOEPMSK - description: Device OUT endpoint common interrupt mask register - byte_offset: 2068 - fieldset: DOEPMSK - - name: DAINT - description: Device all endpoints interrupt register - byte_offset: 2072 - access: Read - fieldset: DAINT - - name: DAINTMSK - description: All endpoints interrupt mask register - byte_offset: 2076 - fieldset: DAINTMSK - - name: DVBUSDIS - description: Device VBUS discharge time register - byte_offset: 2088 - fieldset: DVBUSDIS - - name: DVBUSPULSE - description: Device VBUS pulsing time register - byte_offset: 2092 - fieldset: DVBUSPULSE - - name: DIEPEMPMSK - description: Device IN endpoint FIFO empty interrupt mask register - byte_offset: 2100 - fieldset: DIEPEMPMSK - - name: DIEPCTL - description: Device IN endpoint control register - array: - len: 16 - stride: 32 - byte_offset: 2304 - fieldset: DIEPCTL - - name: DIEPINT - description: Device IN endpoint interrupt register - array: - len: 16 - stride: 32 - byte_offset: 2312 - fieldset: DIEPINT - - name: DIEPTSIZ - description: Device IN endpoint transfer size register - array: - len: 16 - stride: 32 - byte_offset: 2320 - fieldset: DIEPTSIZ - - name: DTXFSTS - description: Device IN endpoint transmit FIFO status register - array: - len: 16 - stride: 32 - byte_offset: 2328 - access: Read - fieldset: DTXFSTS - - name: DOEPCTL - description: Device OUT endpoint control register - array: - len: 16 - stride: 32 - byte_offset: 2816 - fieldset: DOEPCTL - - name: DOEPINT - description: Device OUT endpoint interrupt register - array: - len: 16 - stride: 32 - byte_offset: 2824 - fieldset: DOEPINT - - name: DOEPTSIZ - description: Device OUT endpoint transfer size register - array: - len: 16 - stride: 32 - byte_offset: 2832 - fieldset: DOEPTSIZ - - name: PCGCCTL - description: Power and clock gating control register - byte_offset: 3584 - fieldset: PCGCCTL - - name: FIFO - description: Device endpoint / host channel FIFO register - array: - len: 16 - stride: 4096 - byte_offset: 4096 - fieldset: FIFO + - name: GOTGCTL + description: Control and status register + byte_offset: 0 + fieldset: GOTGCTL + - name: GOTGINT + description: Interrupt register + byte_offset: 4 + fieldset: GOTGINT + - name: GAHBCFG + description: AHB configuration register + byte_offset: 8 + fieldset: GAHBCFG + - name: GUSBCFG + description: USB configuration register + byte_offset: 12 + fieldset: GUSBCFG + - name: GRSTCTL + description: Reset register + byte_offset: 16 + fieldset: GRSTCTL + - name: GINTSTS + description: Core interrupt register + byte_offset: 20 + fieldset: GINTSTS + - name: GINTMSK + description: Interrupt mask register + byte_offset: 24 + fieldset: GINTMSK + - name: GRXSTSR + description: Receive status debug read register + byte_offset: 28 + access: Read + fieldset: GRXSTS + - name: GRXSTSP + description: Status read and pop register + byte_offset: 32 + access: Read + fieldset: GRXSTS + - name: GRXFSIZ + description: Receive FIFO size register + byte_offset: 36 + fieldset: GRXFSIZ + - name: DIEPTXF0 + description: Endpoint 0 transmit FIFO size register (device mode) + byte_offset: 40 + fieldset: FSIZ + - name: HNPTXFSIZ + description: Non-periodic transmit FIFO size register (host mode) + byte_offset: 40 + fieldset: FSIZ + - name: HNPTXSTS + description: Non-periodic transmit FIFO/queue status register (host mode) + byte_offset: 44 + access: Read + fieldset: HNPTXSTS + - name: GI2CCTL + description: OTG I2C access register + byte_offset: 48 + fieldset: GI2CCTL + - name: GCCFG_V1 + description: General core configuration register, for core_id 0x0000_1xxx + byte_offset: 56 + fieldset: GCCFG_V1 + - name: GCCFG_V2 + description: General core configuration register, for core_id 0x0000_[23]xxx + byte_offset: 56 + fieldset: GCCFG_V2 + - name: CID + description: Core ID register + byte_offset: 60 + fieldset: CID + - name: GLPMCFG + description: OTG core LPM configuration register + byte_offset: 84 + fieldset: GLPMCFG + - name: HPTXFSIZ + description: Host periodic transmit FIFO size register + byte_offset: 256 + fieldset: FSIZ + - name: DIEPTXF + description: Device IN endpoint transmit FIFO size register + array: + len: 7 + stride: 4 + byte_offset: 260 + fieldset: FSIZ + - name: HCFG + description: Host configuration register + byte_offset: 1024 + fieldset: HCFG + - name: HFIR + description: Host frame interval register + byte_offset: 1028 + fieldset: HFIR + - name: HFNUM + description: Host frame number/frame time remaining register + byte_offset: 1032 + access: Read + fieldset: HFNUM + - name: HPTXSTS + description: Periodic transmit FIFO/queue status register + byte_offset: 1040 + fieldset: HPTXSTS + - name: HAINT + description: Host all channels interrupt register + byte_offset: 1044 + access: Read + fieldset: HAINT + - name: HAINTMSK + description: Host all channels interrupt mask register + byte_offset: 1048 + fieldset: HAINTMSK + - name: HPRT + description: Host port control and status register + byte_offset: 1088 + fieldset: HPRT + - name: HCCHAR + description: Host channel characteristics register + array: + len: 12 + stride: 32 + byte_offset: 1280 + fieldset: HCCHAR + - name: HCSPLT + description: Host channel split control register + array: + len: 12 + stride: 32 + byte_offset: 1284 + - name: HCINT + description: Host channel interrupt register + array: + len: 12 + stride: 32 + byte_offset: 1288 + fieldset: HCINT + - name: HCINTMSK + description: Host channel mask register + array: + len: 12 + stride: 32 + byte_offset: 1292 + fieldset: HCINTMSK + - name: HCTSIZ + description: Host channel transfer size register + array: + len: 12 + stride: 32 + byte_offset: 1296 + fieldset: HCTSIZ + - name: DCFG + description: Device configuration register + byte_offset: 2048 + fieldset: DCFG + - name: DCTL + description: Device control register + byte_offset: 2052 + fieldset: DCTL + - name: DSTS + description: Device status register + byte_offset: 2056 + access: Read + fieldset: DSTS + - name: DIEPMSK + description: Device IN endpoint common interrupt mask register + byte_offset: 2064 + fieldset: DIEPMSK + - name: DOEPMSK + description: Device OUT endpoint common interrupt mask register + byte_offset: 2068 + fieldset: DOEPMSK + - name: DAINT + description: Device all endpoints interrupt register + byte_offset: 2072 + access: Read + fieldset: DAINT + - name: DAINTMSK + description: All endpoints interrupt mask register + byte_offset: 2076 + fieldset: DAINTMSK + - name: DVBUSDIS + description: Device VBUS discharge time register + byte_offset: 2088 + fieldset: DVBUSDIS + - name: DVBUSPULSE + description: Device VBUS pulsing time register + byte_offset: 2092 + fieldset: DVBUSPULSE + - name: DIEPEMPMSK + description: Device IN endpoint FIFO empty interrupt mask register + byte_offset: 2100 + fieldset: DIEPEMPMSK + - name: DIEPCTL + description: Device IN endpoint control register + array: + len: 16 + stride: 32 + byte_offset: 2304 + fieldset: DIEPCTL + - name: DIEPINT + description: Device IN endpoint interrupt register + array: + len: 16 + stride: 32 + byte_offset: 2312 + fieldset: DIEPINT + - name: DIEPTSIZ + description: Device IN endpoint transfer size register + array: + len: 16 + stride: 32 + byte_offset: 2320 + fieldset: DIEPTSIZ + - name: DTXFSTS + description: Device IN endpoint transmit FIFO status register + array: + len: 16 + stride: 32 + byte_offset: 2328 + access: Read + fieldset: DTXFSTS + - name: DOEPCTL + description: Device OUT endpoint control register + array: + len: 16 + stride: 32 + byte_offset: 2816 + fieldset: DOEPCTL + - name: DOEPINT + description: Device OUT endpoint interrupt register + array: + len: 16 + stride: 32 + byte_offset: 2824 + fieldset: DOEPINT + - name: DOEPTSIZ + description: Device OUT endpoint transfer size register + array: + len: 16 + stride: 32 + byte_offset: 2832 + fieldset: DOEPTSIZ + - name: PCGCCTL + description: Power and clock gating control register + byte_offset: 3584 + fieldset: PCGCCTL + - name: FIFO + description: Device endpoint / host channel FIFO register + array: + len: 16 + stride: 4096 + byte_offset: 4096 + fieldset: FIFO fieldset/CID: description: Core ID register fields: - - name: PRODUCT_ID - description: Product ID field - bit_offset: 0 - bit_size: 32 + - name: PRODUCT_ID + description: Product ID field + bit_offset: 0 + bit_size: 32 fieldset/DAINT: description: Device all endpoints interrupt register fields: - - name: IEPINT - description: IN endpoint interrupt bits - bit_offset: 0 - bit_size: 16 - - name: OEPINT - description: OUT endpoint interrupt bits - bit_offset: 16 - bit_size: 16 + - name: IEPINT + description: IN endpoint interrupt bits + bit_offset: 0 + bit_size: 16 + - name: OEPINT + description: OUT endpoint interrupt bits + bit_offset: 16 + bit_size: 16 fieldset/DAINTMSK: description: All endpoints interrupt mask register fields: - - name: IEPM - description: IN EP interrupt mask bits - bit_offset: 0 - bit_size: 16 - - name: OEPM - description: OUT EP interrupt mask bits - bit_offset: 16 - bit_size: 16 + - name: IEPM + description: IN EP interrupt mask bits + bit_offset: 0 + bit_size: 16 + - name: OEPM + description: OUT EP interrupt mask bits + bit_offset: 16 + bit_size: 16 fieldset/DCFG: description: Device configuration register fields: - - name: DSPD - description: Device speed - bit_offset: 0 - bit_size: 2 - enum: DSPD - - name: NZLSOHSK - description: Non-zero-length status OUT handshake - bit_offset: 2 - bit_size: 1 - - name: DAD - description: Device address - bit_offset: 4 - bit_size: 7 - - name: PFIVL - description: Periodic frame interval - bit_offset: 11 - bit_size: 2 - enum: PFIVL - - name: XCVRDLY - description: Transceiver delay - bit_offset: 14 - bit_size: 1 + - name: DSPD + description: Device speed + bit_offset: 0 + bit_size: 2 + enum: DSPD + - name: NZLSOHSK + description: Non-zero-length status OUT handshake + bit_offset: 2 + bit_size: 1 + - name: DAD + description: Device address + bit_offset: 4 + bit_size: 7 + - name: PFIVL + description: Periodic frame interval + bit_offset: 11 + bit_size: 2 + enum: PFIVL + - name: XCVRDLY + description: Transceiver delay + bit_offset: 14 + bit_size: 1 fieldset/DCTL: description: Device control register fields: - - name: RWUSIG - description: Remote wakeup signaling - bit_offset: 0 - bit_size: 1 - - name: SDIS - description: Soft disconnect - bit_offset: 1 - bit_size: 1 - - name: GINSTS - description: Global IN NAK status - bit_offset: 2 - bit_size: 1 - - name: GONSTS - description: Global OUT NAK status - bit_offset: 3 - bit_size: 1 - - name: TCTL - description: Test control - bit_offset: 4 - bit_size: 3 - - name: SGINAK - description: Set global IN NAK - bit_offset: 7 - bit_size: 1 - - name: CGINAK - description: Clear global IN NAK - bit_offset: 8 - bit_size: 1 - - name: SGONAK - description: Set global OUT NAK - bit_offset: 9 - bit_size: 1 - - name: CGONAK - description: Clear global OUT NAK - bit_offset: 10 - bit_size: 1 - - name: POPRGDNE - description: Power-on programming done - bit_offset: 11 - bit_size: 1 + - name: RWUSIG + description: Remote wakeup signaling + bit_offset: 0 + bit_size: 1 + - name: SDIS + description: Soft disconnect + bit_offset: 1 + bit_size: 1 + - name: GINSTS + description: Global IN NAK status + bit_offset: 2 + bit_size: 1 + - name: GONSTS + description: Global OUT NAK status + bit_offset: 3 + bit_size: 1 + - name: TCTL + description: Test control + bit_offset: 4 + bit_size: 3 + - name: SGINAK + description: Set global IN NAK + bit_offset: 7 + bit_size: 1 + - name: CGINAK + description: Clear global IN NAK + bit_offset: 8 + bit_size: 1 + - name: SGONAK + description: Set global OUT NAK + bit_offset: 9 + bit_size: 1 + - name: CGONAK + description: Clear global OUT NAK + bit_offset: 10 + bit_size: 1 + - name: POPRGDNE + description: Power-on programming done + bit_offset: 11 + bit_size: 1 fieldset/DIEPCTL: description: Device endpoint control register fields: - - name: MPSIZ - description: MPSIZ - bit_offset: 0 - bit_size: 11 - - name: USBAEP - description: USBAEP - bit_offset: 15 - bit_size: 1 - - name: EONUM_DPID - description: EONUM/DPID - bit_offset: 16 - bit_size: 1 - - name: NAKSTS - description: NAKSTS - bit_offset: 17 - bit_size: 1 - - name: EPTYP - description: EPTYP - bit_offset: 18 - bit_size: 2 - enum: EPTYP - - name: SNPM - description: SNPM - bit_offset: 20 - bit_size: 1 - - name: STALL - description: STALL - bit_offset: 21 - bit_size: 1 - - name: TXFNUM - description: TXFNUM - bit_offset: 22 - bit_size: 4 - - name: CNAK - description: CNAK - bit_offset: 26 - bit_size: 1 - - name: SNAK - description: SNAK - bit_offset: 27 - bit_size: 1 - - name: SD0PID_SEVNFRM - description: SD0PID/SEVNFRM - bit_offset: 28 - bit_size: 1 - - name: SODDFRM_SD1PID - description: SODDFRM/SD1PID - bit_offset: 29 - bit_size: 1 - - name: EPDIS - description: EPDIS - bit_offset: 30 - bit_size: 1 - - name: EPENA - description: EPENA - bit_offset: 31 - bit_size: 1 + - name: MPSIZ + description: MPSIZ + bit_offset: 0 + bit_size: 11 + - name: USBAEP + description: USBAEP + bit_offset: 15 + bit_size: 1 + - name: EONUM_DPID + description: EONUM/DPID + bit_offset: 16 + bit_size: 1 + - name: NAKSTS + description: NAKSTS + bit_offset: 17 + bit_size: 1 + - name: EPTYP + description: EPTYP + bit_offset: 18 + bit_size: 2 + enum: EPTYP + - name: SNPM + description: SNPM + bit_offset: 20 + bit_size: 1 + - name: STALL + description: STALL + bit_offset: 21 + bit_size: 1 + - name: TXFNUM + description: TXFNUM + bit_offset: 22 + bit_size: 4 + - name: CNAK + description: CNAK + bit_offset: 26 + bit_size: 1 + - name: SNAK + description: SNAK + bit_offset: 27 + bit_size: 1 + - name: SD0PID_SEVNFRM + description: SD0PID/SEVNFRM + bit_offset: 28 + bit_size: 1 + - name: SODDFRM_SD1PID + description: SODDFRM/SD1PID + bit_offset: 29 + bit_size: 1 + - name: EPDIS + description: EPDIS + bit_offset: 30 + bit_size: 1 + - name: EPENA + description: EPENA + bit_offset: 31 + bit_size: 1 fieldset/DIEPEMPMSK: description: Device IN endpoint FIFO empty interrupt mask register fields: - - name: INEPTXFEM - description: IN EP Tx FIFO empty interrupt mask bits - bit_offset: 0 - bit_size: 16 + - name: INEPTXFEM + description: IN EP Tx FIFO empty interrupt mask bits + bit_offset: 0 + bit_size: 16 fieldset/DIEPINT: description: Device endpoint interrupt register fields: - - name: XFRC - description: XFRC - bit_offset: 0 - bit_size: 1 - - name: EPDISD - description: EPDISD - bit_offset: 1 - bit_size: 1 - - name: TOC - description: TOC - bit_offset: 3 - bit_size: 1 - - name: ITTXFE - description: ITTXFE - bit_offset: 4 - bit_size: 1 - - name: INEPNE - description: INEPNE - bit_offset: 6 - bit_size: 1 - - name: TXFE - description: TXFE - bit_offset: 7 - bit_size: 1 + - name: XFRC + description: XFRC + bit_offset: 0 + bit_size: 1 + - name: EPDISD + description: EPDISD + bit_offset: 1 + bit_size: 1 + - name: TOC + description: TOC + bit_offset: 3 + bit_size: 1 + - name: ITTXFE + description: ITTXFE + bit_offset: 4 + bit_size: 1 + - name: INEPNE + description: INEPNE + bit_offset: 6 + bit_size: 1 + - name: TXFE + description: TXFE + bit_offset: 7 + bit_size: 1 fieldset/DIEPMSK: description: Device IN endpoint common interrupt mask register fields: - - name: XFRCM - description: Transfer completed interrupt mask - bit_offset: 0 - bit_size: 1 - - name: EPDM - description: Endpoint disabled interrupt mask - bit_offset: 1 - bit_size: 1 - - name: TOM - description: Timeout condition mask (Non-isochronous endpoints) - bit_offset: 3 - bit_size: 1 - - name: ITTXFEMSK - description: IN token received when TxFIFO empty mask - bit_offset: 4 - bit_size: 1 - - name: INEPNMM - description: IN token received with EP mismatch mask - bit_offset: 5 - bit_size: 1 - - name: INEPNEM - description: IN endpoint NAK effective mask - bit_offset: 6 - bit_size: 1 + - name: XFRCM + description: Transfer completed interrupt mask + bit_offset: 0 + bit_size: 1 + - name: EPDM + description: Endpoint disabled interrupt mask + bit_offset: 1 + bit_size: 1 + - name: TOM + description: Timeout condition mask (Non-isochronous endpoints) + bit_offset: 3 + bit_size: 1 + - name: ITTXFEMSK + description: IN token received when TxFIFO empty mask + bit_offset: 4 + bit_size: 1 + - name: INEPNMM + description: IN token received with EP mismatch mask + bit_offset: 5 + bit_size: 1 + - name: INEPNEM + description: IN endpoint NAK effective mask + bit_offset: 6 + bit_size: 1 fieldset/DIEPTSIZ: description: Device endpoint transfer size register fields: - - name: XFRSIZ - description: Transfer size - bit_offset: 0 - bit_size: 19 - - name: PKTCNT - description: Packet count - bit_offset: 19 - bit_size: 10 - - name: MCNT - description: Multi count - bit_offset: 29 - bit_size: 2 + - name: XFRSIZ + description: Transfer size + bit_offset: 0 + bit_size: 19 + - name: PKTCNT + description: Packet count + bit_offset: 19 + bit_size: 10 + - name: MCNT + description: Multi count + bit_offset: 29 + bit_size: 2 fieldset/DOEPCTL: description: Device endpoint control register fields: - - name: MPSIZ - description: MPSIZ - bit_offset: 0 - bit_size: 11 - - name: USBAEP - description: USBAEP - bit_offset: 15 - bit_size: 1 - - name: EONUM_DPID - description: EONUM/DPID - bit_offset: 16 - bit_size: 1 - - name: NAKSTS - description: NAKSTS - bit_offset: 17 - bit_size: 1 - - name: EPTYP - description: EPTYP - bit_offset: 18 - bit_size: 2 - enum: EPTYP - - name: SNPM - description: SNPM - bit_offset: 20 - bit_size: 1 - - name: STALL - description: STALL - bit_offset: 21 - bit_size: 1 - - name: CNAK - description: CNAK - bit_offset: 26 - bit_size: 1 - - name: SNAK - description: SNAK - bit_offset: 27 - bit_size: 1 - - name: SD0PID_SEVNFRM - description: SD0PID/SEVNFRM - bit_offset: 28 - bit_size: 1 - - name: SODDFRM - description: SODDFRM - bit_offset: 29 - bit_size: 1 - - name: EPDIS - description: EPDIS - bit_offset: 30 - bit_size: 1 - - name: EPENA - description: EPENA - bit_offset: 31 - bit_size: 1 + - name: MPSIZ + description: MPSIZ + bit_offset: 0 + bit_size: 11 + - name: USBAEP + description: USBAEP + bit_offset: 15 + bit_size: 1 + - name: EONUM_DPID + description: EONUM/DPID + bit_offset: 16 + bit_size: 1 + - name: NAKSTS + description: NAKSTS + bit_offset: 17 + bit_size: 1 + - name: EPTYP + description: EPTYP + bit_offset: 18 + bit_size: 2 + enum: EPTYP + - name: SNPM + description: SNPM + bit_offset: 20 + bit_size: 1 + - name: STALL + description: STALL + bit_offset: 21 + bit_size: 1 + - name: CNAK + description: CNAK + bit_offset: 26 + bit_size: 1 + - name: SNAK + description: SNAK + bit_offset: 27 + bit_size: 1 + - name: SD0PID_SEVNFRM + description: SD0PID/SEVNFRM + bit_offset: 28 + bit_size: 1 + - name: SODDFRM + description: SODDFRM + bit_offset: 29 + bit_size: 1 + - name: EPDIS + description: EPDIS + bit_offset: 30 + bit_size: 1 + - name: EPENA + description: EPENA + bit_offset: 31 + bit_size: 1 fieldset/DOEPINT: description: Device endpoint interrupt register fields: - - name: XFRC - description: XFRC - bit_offset: 0 - bit_size: 1 - - name: EPDISD - description: EPDISD - bit_offset: 1 - bit_size: 1 - - name: STUP - description: STUP - bit_offset: 3 - bit_size: 1 - - name: OTEPDIS - description: OTEPDIS - bit_offset: 4 - bit_size: 1 - - name: B2BSTUP - description: B2BSTUP - bit_offset: 6 - bit_size: 1 + - name: XFRC + description: XFRC + bit_offset: 0 + bit_size: 1 + - name: EPDISD + description: EPDISD + bit_offset: 1 + bit_size: 1 + - name: STUP + description: STUP + bit_offset: 3 + bit_size: 1 + - name: OTEPDIS + description: OTEPDIS + bit_offset: 4 + bit_size: 1 + - name: B2BSTUP + description: B2BSTUP + bit_offset: 6 + bit_size: 1 fieldset/DOEPMSK: description: Device OUT endpoint common interrupt mask register fields: - - name: XFRCM - description: Transfer completed interrupt mask - bit_offset: 0 - bit_size: 1 - - name: EPDM - description: Endpoint disabled interrupt mask - bit_offset: 1 - bit_size: 1 - - name: STUPM - description: SETUP phase done mask - bit_offset: 3 - bit_size: 1 - - name: OTEPDM - description: OUT token received when endpoint disabled mask - bit_offset: 4 - bit_size: 1 + - name: XFRCM + description: Transfer completed interrupt mask + bit_offset: 0 + bit_size: 1 + - name: EPDM + description: Endpoint disabled interrupt mask + bit_offset: 1 + bit_size: 1 + - name: STUPM + description: SETUP phase done mask + bit_offset: 3 + bit_size: 1 + - name: OTEPDM + description: OUT token received when endpoint disabled mask + bit_offset: 4 + bit_size: 1 fieldset/DOEPTSIZ: description: Device OUT endpoint transfer size register fields: - - name: XFRSIZ - description: Transfer size - bit_offset: 0 - bit_size: 19 - - name: PKTCNT - description: Packet count - bit_offset: 19 - bit_size: 10 - - name: RXDPID_STUPCNT - description: Received data PID/SETUP packet count - bit_offset: 29 - bit_size: 2 + - name: XFRSIZ + description: Transfer size + bit_offset: 0 + bit_size: 19 + - name: PKTCNT + description: Packet count + bit_offset: 19 + bit_size: 10 + - name: RXDPID_STUPCNT + description: Received data PID/SETUP packet count + bit_offset: 29 + bit_size: 2 fieldset/DSTS: description: Device status register fields: - - name: SUSPSTS - description: Suspend status - bit_offset: 0 - bit_size: 1 - - name: ENUMSPD - description: Enumerated speed - bit_offset: 1 - bit_size: 2 - enum: DSPD - - name: EERR - description: Erratic error - bit_offset: 3 - bit_size: 1 - - name: FNSOF - description: Frame number of the received SOF - bit_offset: 8 - bit_size: 14 + - name: SUSPSTS + description: Suspend status + bit_offset: 0 + bit_size: 1 + - name: ENUMSPD + description: Enumerated speed + bit_offset: 1 + bit_size: 2 + enum: DSPD + - name: EERR + description: Erratic error + bit_offset: 3 + bit_size: 1 + - name: FNSOF + description: Frame number of the received SOF + bit_offset: 8 + bit_size: 14 fieldset/DTXFSTS: description: Device IN endpoint transmit FIFO status register fields: - - name: INEPTFSAV - description: IN endpoint TxFIFO space available - bit_offset: 0 - bit_size: 16 + - name: INEPTFSAV + description: IN endpoint TxFIFO space available + bit_offset: 0 + bit_size: 16 fieldset/DVBUSDIS: description: Device VBUS discharge time register fields: - - name: VBUSDT - description: Device VBUS discharge time - bit_offset: 0 - bit_size: 16 + - name: VBUSDT + description: Device VBUS discharge time + bit_offset: 0 + bit_size: 16 fieldset/DVBUSPULSE: description: Device VBUS pulsing time register fields: - - name: DVBUSP - description: Device VBUS pulsing time - bit_offset: 0 - bit_size: 12 + - name: DVBUSP + description: Device VBUS pulsing time + bit_offset: 0 + bit_size: 12 fieldset/FIFO: description: FIFO register fields: - - name: DATA - description: Data - bit_offset: 0 - bit_size: 32 + - name: DATA + description: Data + bit_offset: 0 + bit_size: 32 fieldset/FSIZ: description: FIFO size register fields: - - name: SA - description: RAM start address - bit_offset: 0 - bit_size: 16 - - name: FD - description: FIFO depth - bit_offset: 16 - bit_size: 16 + - name: SA + description: RAM start address + bit_offset: 0 + bit_size: 16 + - name: FD + description: FIFO depth + bit_offset: 16 + bit_size: 16 fieldset/GAHBCFG: description: AHB configuration register fields: - - name: GINT - description: Global interrupt mask - bit_offset: 0 - bit_size: 1 - - name: HBSTLEN - description: Burst length/type - bit_offset: 1 - bit_size: 4 - - name: DMAEN - description: DMA enable - bit_offset: 5 - bit_size: 1 - - name: TXFELVL - description: TxFIFO empty level - bit_offset: 7 - bit_size: 1 - - name: PTXFELVL - description: Periodic TxFIFO empty level - bit_offset: 8 - bit_size: 1 + - name: GINT + description: Global interrupt mask + bit_offset: 0 + bit_size: 1 + - name: HBSTLEN + description: Burst length/type + bit_offset: 1 + bit_size: 4 + - name: DMAEN + description: DMA enable + bit_offset: 5 + bit_size: 1 + - name: TXFELVL + description: TxFIFO empty level + bit_offset: 7 + bit_size: 1 + - name: PTXFELVL + description: Periodic TxFIFO empty level + bit_offset: 8 + bit_size: 1 fieldset/GCCFG_V1: description: General core configuration register fields: - - name: PWRDWN - description: Power down - bit_offset: 16 - bit_size: 1 - - name: VBUSASEN - description: "Enable the VBUS \"A\" sensing device" - bit_offset: 18 - bit_size: 1 - - name: VBUSBSEN - description: "Enable the VBUS \"B\" sensing device" - bit_offset: 19 - bit_size: 1 - - name: SOFOUTEN - description: SOF output enable - bit_offset: 20 - bit_size: 1 - - name: NOVBUSSENS - description: VBUS sensing disable - bit_offset: 21 - bit_size: 1 + - name: PWRDWN + description: Power down + bit_offset: 16 + bit_size: 1 + - name: VBUSASEN + description: Enable the VBUS "A" sensing device + bit_offset: 18 + bit_size: 1 + - name: VBUSBSEN + description: Enable the VBUS "B" sensing device + bit_offset: 19 + bit_size: 1 + - name: SOFOUTEN + description: SOF output enable + bit_offset: 20 + bit_size: 1 + - name: NOVBUSSENS + description: VBUS sensing disable + bit_offset: 21 + bit_size: 1 fieldset/GCCFG_V2: description: General core configuration register fields: - - name: DCDET - description: Data contact detection (DCD) status - bit_offset: 0 - bit_size: 1 - - name: PDET - description: Primary detection (PD) status - bit_offset: 1 - bit_size: 1 - - name: SDET - description: Secondary detection (SD) status - bit_offset: 2 - bit_size: 1 - - name: PS2DET - description: DM pull-up detection status - bit_offset: 3 - bit_size: 1 - - name: PWRDWN - description: Power down - bit_offset: 16 - bit_size: 1 - - name: BCDEN - description: Battery charging detector (BCD) enable - bit_offset: 17 - bit_size: 1 - - name: DCDEN - description: Data contact detection (DCD) mode enable - bit_offset: 18 - bit_size: 1 - - name: PDEN - description: Primary detection (PD) mode enable - bit_offset: 19 - bit_size: 1 - - name: SDEN - description: Secondary detection (SD) mode enable - bit_offset: 20 - bit_size: 1 - - name: VBDEN - description: USB VBUS detection enable - bit_offset: 21 - bit_size: 1 - - name: PHYHSEN - description: Internal high-speed PHY enable. - bit_offset: 23 - bit_size: 1 + - name: DCDET + description: Data contact detection (DCD) status + bit_offset: 0 + bit_size: 1 + - name: PDET + description: Primary detection (PD) status + bit_offset: 1 + bit_size: 1 + - name: SDET + description: Secondary detection (SD) status + bit_offset: 2 + bit_size: 1 + - name: PS2DET + description: DM pull-up detection status + bit_offset: 3 + bit_size: 1 + - name: PWRDWN + description: Power down + bit_offset: 16 + bit_size: 1 + - name: BCDEN + description: Battery charging detector (BCD) enable + bit_offset: 17 + bit_size: 1 + - name: DCDEN + description: Data contact detection (DCD) mode enable + bit_offset: 18 + bit_size: 1 + - name: PDEN + description: Primary detection (PD) mode enable + bit_offset: 19 + bit_size: 1 + - name: SDEN + description: Secondary detection (SD) mode enable + bit_offset: 20 + bit_size: 1 + - name: VBDEN + description: USB VBUS detection enable + bit_offset: 21 + bit_size: 1 + - name: PHYHSEN + description: Internal high-speed PHY enable. + bit_offset: 23 + bit_size: 1 fieldset/GI2CCTL: description: I2C access register fields: - - name: RWDATA - description: I2C Read/Write Data - bit_offset: 0 - bit_size: 8 - - name: REGADDR - description: I2C Register Address - bit_offset: 8 - bit_size: 8 - - name: ADDR - description: I2C Address - bit_offset: 16 - bit_size: 7 - - name: I2CEN - description: I2C Enable - bit_offset: 23 - bit_size: 1 - - name: ACK - description: I2C ACK - bit_offset: 24 - bit_size: 1 - - name: I2CDEVADR - description: I2C Device Address - bit_offset: 26 - bit_size: 2 - - name: I2CDATSE0 - description: I2C DatSe0 USB mode - bit_offset: 28 - bit_size: 1 - - name: RW - description: Read/Write Indicator - bit_offset: 30 - bit_size: 1 - - name: BSYDNE - description: I2C Busy/Done - bit_offset: 31 - bit_size: 1 + - name: RWDATA + description: I2C Read/Write Data + bit_offset: 0 + bit_size: 8 + - name: REGADDR + description: I2C Register Address + bit_offset: 8 + bit_size: 8 + - name: ADDR + description: I2C Address + bit_offset: 16 + bit_size: 7 + - name: I2CEN + description: I2C Enable + bit_offset: 23 + bit_size: 1 + - name: ACK + description: I2C ACK + bit_offset: 24 + bit_size: 1 + - name: I2CDEVADR + description: I2C Device Address + bit_offset: 26 + bit_size: 2 + - name: I2CDATSE0 + description: I2C DatSe0 USB mode + bit_offset: 28 + bit_size: 1 + - name: RW + description: Read/Write Indicator + bit_offset: 30 + bit_size: 1 + - name: BSYDNE + description: I2C Busy/Done + bit_offset: 31 + bit_size: 1 fieldset/GINTMSK: description: Interrupt mask register fields: - - name: MMISM - description: Mode mismatch interrupt mask - bit_offset: 1 - bit_size: 1 - - name: OTGINT - description: OTG interrupt mask - bit_offset: 2 - bit_size: 1 - - name: SOFM - description: Start of frame mask - bit_offset: 3 - bit_size: 1 - - name: RXFLVLM - description: Receive FIFO non-empty mask - bit_offset: 4 - bit_size: 1 - - name: NPTXFEM - description: Non-periodic TxFIFO empty mask - bit_offset: 5 - bit_size: 1 - - name: GINAKEFFM - description: Global non-periodic IN NAK effective mask - bit_offset: 6 - bit_size: 1 - - name: GONAKEFFM - description: Global OUT NAK effective mask - bit_offset: 7 - bit_size: 1 - - name: ESUSPM - description: Early suspend mask - bit_offset: 10 - bit_size: 1 - - name: USBSUSPM - description: USB suspend mask - bit_offset: 11 - bit_size: 1 - - name: USBRST - description: USB reset mask - bit_offset: 12 - bit_size: 1 - - name: ENUMDNEM - description: Enumeration done mask - bit_offset: 13 - bit_size: 1 - - name: ISOODRPM - description: Isochronous OUT packet dropped interrupt mask - bit_offset: 14 - bit_size: 1 - - name: EOPFM - description: End of periodic frame interrupt mask - bit_offset: 15 - bit_size: 1 - - name: EPMISM - description: Endpoint mismatch interrupt mask - bit_offset: 17 - bit_size: 1 - - name: IEPINT - description: IN endpoints interrupt mask - bit_offset: 18 - bit_size: 1 - - name: OEPINT - description: OUT endpoints interrupt mask - bit_offset: 19 - bit_size: 1 - - name: IISOIXFRM - description: Incomplete isochronous IN transfer mask - bit_offset: 20 - bit_size: 1 - - name: IPXFRM_IISOOXFRM - description: Incomplete periodic transfer mask (host mode) / Incomplete isochronous OUT transfer mask (device mode) - bit_offset: 21 - bit_size: 1 - - name: FSUSPM - description: Data fetch suspended mask - bit_offset: 22 - bit_size: 1 - - name: RSTDE - description: Reset detected interrupt mask - bit_offset: 23 - bit_size: 1 - - name: PRTIM - description: Host port interrupt mask - bit_offset: 24 - bit_size: 1 - - name: HCIM - description: Host channels interrupt mask - bit_offset: 25 - bit_size: 1 - - name: PTXFEM - description: Periodic TxFIFO empty mask - bit_offset: 26 - bit_size: 1 - - name: LPMINTM - description: LPM interrupt mask - bit_offset: 27 - bit_size: 1 - - name: CIDSCHGM - description: Connector ID status change mask - bit_offset: 28 - bit_size: 1 - - name: DISCINT - description: Disconnect detected interrupt mask - bit_offset: 29 - bit_size: 1 - - name: SRQIM - description: Session request/new session detected interrupt mask - bit_offset: 30 - bit_size: 1 - - name: WUIM - description: Resume/remote wakeup detected interrupt mask - bit_offset: 31 - bit_size: 1 + - name: MMISM + description: Mode mismatch interrupt mask + bit_offset: 1 + bit_size: 1 + - name: OTGINT + description: OTG interrupt mask + bit_offset: 2 + bit_size: 1 + - name: SOFM + description: Start of frame mask + bit_offset: 3 + bit_size: 1 + - name: RXFLVLM + description: Receive FIFO non-empty mask + bit_offset: 4 + bit_size: 1 + - name: NPTXFEM + description: Non-periodic TxFIFO empty mask + bit_offset: 5 + bit_size: 1 + - name: GINAKEFFM + description: Global non-periodic IN NAK effective mask + bit_offset: 6 + bit_size: 1 + - name: GONAKEFFM + description: Global OUT NAK effective mask + bit_offset: 7 + bit_size: 1 + - name: ESUSPM + description: Early suspend mask + bit_offset: 10 + bit_size: 1 + - name: USBSUSPM + description: USB suspend mask + bit_offset: 11 + bit_size: 1 + - name: USBRST + description: USB reset mask + bit_offset: 12 + bit_size: 1 + - name: ENUMDNEM + description: Enumeration done mask + bit_offset: 13 + bit_size: 1 + - name: ISOODRPM + description: Isochronous OUT packet dropped interrupt mask + bit_offset: 14 + bit_size: 1 + - name: EOPFM + description: End of periodic frame interrupt mask + bit_offset: 15 + bit_size: 1 + - name: EPMISM + description: Endpoint mismatch interrupt mask + bit_offset: 17 + bit_size: 1 + - name: IEPINT + description: IN endpoints interrupt mask + bit_offset: 18 + bit_size: 1 + - name: OEPINT + description: OUT endpoints interrupt mask + bit_offset: 19 + bit_size: 1 + - name: IISOIXFRM + description: Incomplete isochronous IN transfer mask + bit_offset: 20 + bit_size: 1 + - name: IPXFRM_IISOOXFRM + description: Incomplete periodic transfer mask (host mode) / Incomplete isochronous OUT transfer mask (device mode) + bit_offset: 21 + bit_size: 1 + - name: FSUSPM + description: Data fetch suspended mask + bit_offset: 22 + bit_size: 1 + - name: RSTDE + description: Reset detected interrupt mask + bit_offset: 23 + bit_size: 1 + - name: PRTIM + description: Host port interrupt mask + bit_offset: 24 + bit_size: 1 + - name: HCIM + description: Host channels interrupt mask + bit_offset: 25 + bit_size: 1 + - name: PTXFEM + description: Periodic TxFIFO empty mask + bit_offset: 26 + bit_size: 1 + - name: LPMINTM + description: LPM interrupt mask + bit_offset: 27 + bit_size: 1 + - name: CIDSCHGM + description: Connector ID status change mask + bit_offset: 28 + bit_size: 1 + - name: DISCINT + description: Disconnect detected interrupt mask + bit_offset: 29 + bit_size: 1 + - name: SRQIM + description: Session request/new session detected interrupt mask + bit_offset: 30 + bit_size: 1 + - name: WUIM + description: Resume/remote wakeup detected interrupt mask + bit_offset: 31 + bit_size: 1 fieldset/GINTSTS: description: Core interrupt register fields: - - name: CMOD - description: Current mode of operation - bit_offset: 0 - bit_size: 1 - - name: MMIS - description: Mode mismatch interrupt - bit_offset: 1 - bit_size: 1 - - name: OTGINT - description: OTG interrupt - bit_offset: 2 - bit_size: 1 - - name: SOF - description: Start of frame - bit_offset: 3 - bit_size: 1 - - name: RXFLVL - description: RxFIFO non-empty - bit_offset: 4 - bit_size: 1 - - name: NPTXFE - description: Non-periodic TxFIFO empty - bit_offset: 5 - bit_size: 1 - - name: GINAKEFF - description: Global IN non-periodic NAK effective - bit_offset: 6 - bit_size: 1 - - name: GOUTNAKEFF - description: Global OUT NAK effective - bit_offset: 7 - bit_size: 1 - - name: ESUSP - description: Early suspend - bit_offset: 10 - bit_size: 1 - - name: USBSUSP - description: USB suspend - bit_offset: 11 - bit_size: 1 - - name: USBRST - description: USB reset - bit_offset: 12 - bit_size: 1 - - name: ENUMDNE - description: Enumeration done - bit_offset: 13 - bit_size: 1 - - name: ISOODRP - description: Isochronous OUT packet dropped interrupt - bit_offset: 14 - bit_size: 1 - - name: EOPF - description: End of periodic frame interrupt - bit_offset: 15 - bit_size: 1 - - name: IEPINT - description: IN endpoint interrupt - bit_offset: 18 - bit_size: 1 - - name: OEPINT - description: OUT endpoint interrupt - bit_offset: 19 - bit_size: 1 - - name: IISOIXFR - description: Incomplete isochronous IN transfer - bit_offset: 20 - bit_size: 1 - - name: IPXFR_INCOMPISOOUT - description: Incomplete periodic transfer (host mode) / Incomplete isochronous OUT transfer (device mode) - bit_offset: 21 - bit_size: 1 - - name: DATAFSUSP - description: Data fetch suspended - bit_offset: 22 - bit_size: 1 - - name: HPRTINT - description: Host port interrupt - bit_offset: 24 - bit_size: 1 - - name: HCINT - description: Host channels interrupt - bit_offset: 25 - bit_size: 1 - - name: PTXFE - description: Periodic TxFIFO empty - bit_offset: 26 - bit_size: 1 - - name: CIDSCHG - description: Connector ID status change - bit_offset: 28 - bit_size: 1 - - name: DISCINT - description: Disconnect detected interrupt - bit_offset: 29 - bit_size: 1 - - name: SRQINT - description: Session request/new session detected interrupt - bit_offset: 30 - bit_size: 1 - - name: WKUPINT - description: Resume/remote wakeup detected interrupt - bit_offset: 31 - bit_size: 1 + - name: CMOD + description: Current mode of operation + bit_offset: 0 + bit_size: 1 + - name: MMIS + description: Mode mismatch interrupt + bit_offset: 1 + bit_size: 1 + - name: OTGINT + description: OTG interrupt + bit_offset: 2 + bit_size: 1 + - name: SOF + description: Start of frame + bit_offset: 3 + bit_size: 1 + - name: RXFLVL + description: RxFIFO non-empty + bit_offset: 4 + bit_size: 1 + - name: NPTXFE + description: Non-periodic TxFIFO empty + bit_offset: 5 + bit_size: 1 + - name: GINAKEFF + description: Global IN non-periodic NAK effective + bit_offset: 6 + bit_size: 1 + - name: GOUTNAKEFF + description: Global OUT NAK effective + bit_offset: 7 + bit_size: 1 + - name: ESUSP + description: Early suspend + bit_offset: 10 + bit_size: 1 + - name: USBSUSP + description: USB suspend + bit_offset: 11 + bit_size: 1 + - name: USBRST + description: USB reset + bit_offset: 12 + bit_size: 1 + - name: ENUMDNE + description: Enumeration done + bit_offset: 13 + bit_size: 1 + - name: ISOODRP + description: Isochronous OUT packet dropped interrupt + bit_offset: 14 + bit_size: 1 + - name: EOPF + description: End of periodic frame interrupt + bit_offset: 15 + bit_size: 1 + - name: IEPINT + description: IN endpoint interrupt + bit_offset: 18 + bit_size: 1 + - name: OEPINT + description: OUT endpoint interrupt + bit_offset: 19 + bit_size: 1 + - name: IISOIXFR + description: Incomplete isochronous IN transfer + bit_offset: 20 + bit_size: 1 + - name: IPXFR_INCOMPISOOUT + description: Incomplete periodic transfer (host mode) / Incomplete isochronous OUT transfer (device mode) + bit_offset: 21 + bit_size: 1 + - name: DATAFSUSP + description: Data fetch suspended + bit_offset: 22 + bit_size: 1 + - name: HPRTINT + description: Host port interrupt + bit_offset: 24 + bit_size: 1 + - name: HCINT + description: Host channels interrupt + bit_offset: 25 + bit_size: 1 + - name: PTXFE + description: Periodic TxFIFO empty + bit_offset: 26 + bit_size: 1 + - name: CIDSCHG + description: Connector ID status change + bit_offset: 28 + bit_size: 1 + - name: DISCINT + description: Disconnect detected interrupt + bit_offset: 29 + bit_size: 1 + - name: SRQINT + description: Session request/new session detected interrupt + bit_offset: 30 + bit_size: 1 + - name: WKUPINT + description: Resume/remote wakeup detected interrupt + bit_offset: 31 + bit_size: 1 fieldset/GLPMCFG: description: Core LPM configuration register fields: - - name: LPMEN - description: LPM support enable - bit_offset: 0 - bit_size: 1 - - name: LPMACK - description: LPM token acknowledge enable - bit_offset: 1 - bit_size: 1 - - name: BESL - description: Best effort service latency - bit_offset: 2 - bit_size: 4 - - name: REMWAKE - description: bRemoteWake value - bit_offset: 6 - bit_size: 1 - - name: L1SSEN - description: L1 Shallow Sleep enable - bit_offset: 7 - bit_size: 1 - - name: BESLTHRS - description: BESL threshold - bit_offset: 8 - bit_size: 4 - - name: L1DSEN - description: L1 deep sleep enable - bit_offset: 12 - bit_size: 1 - - name: LPMRST - description: LPM response - bit_offset: 13 - bit_size: 2 - - name: SLPSTS - description: Port sleep status - bit_offset: 15 - bit_size: 1 - - name: L1RSMOK - description: Sleep State Resume OK - bit_offset: 16 - bit_size: 1 - - name: LPMCHIDX - description: LPM Channel Index - bit_offset: 17 - bit_size: 4 - - name: LPMRCNT - description: LPM retry count - bit_offset: 21 - bit_size: 3 - - name: SNDLPM - description: Send LPM transaction - bit_offset: 24 - bit_size: 1 - - name: LPMRCNTSTS - description: LPM retry count status - bit_offset: 25 - bit_size: 3 - - name: ENBESL - description: Enable best effort service latency - bit_offset: 28 - bit_size: 1 + - name: LPMEN + description: LPM support enable + bit_offset: 0 + bit_size: 1 + - name: LPMACK + description: LPM token acknowledge enable + bit_offset: 1 + bit_size: 1 + - name: BESL + description: Best effort service latency + bit_offset: 2 + bit_size: 4 + - name: REMWAKE + description: bRemoteWake value + bit_offset: 6 + bit_size: 1 + - name: L1SSEN + description: L1 Shallow Sleep enable + bit_offset: 7 + bit_size: 1 + - name: BESLTHRS + description: BESL threshold + bit_offset: 8 + bit_size: 4 + - name: L1DSEN + description: L1 deep sleep enable + bit_offset: 12 + bit_size: 1 + - name: LPMRST + description: LPM response + bit_offset: 13 + bit_size: 2 + - name: SLPSTS + description: Port sleep status + bit_offset: 15 + bit_size: 1 + - name: L1RSMOK + description: Sleep State Resume OK + bit_offset: 16 + bit_size: 1 + - name: LPMCHIDX + description: LPM Channel Index + bit_offset: 17 + bit_size: 4 + - name: LPMRCNT + description: LPM retry count + bit_offset: 21 + bit_size: 3 + - name: SNDLPM + description: Send LPM transaction + bit_offset: 24 + bit_size: 1 + - name: LPMRCNTSTS + description: LPM retry count status + bit_offset: 25 + bit_size: 3 + - name: ENBESL + description: Enable best effort service latency + bit_offset: 28 + bit_size: 1 fieldset/GNPTXSTS: description: Non-periodic transmit FIFO/queue status register fields: - - name: NPTXFSAV - description: Non-periodic TxFIFO space available - bit_offset: 0 - bit_size: 16 - - name: NPTQXSAV - description: Non-periodic transmit request queue space available - bit_offset: 16 - bit_size: 8 - - name: NPTXQTOP - description: Top of the non-periodic transmit request queue - bit_offset: 24 - bit_size: 7 + - name: NPTXFSAV + description: Non-periodic TxFIFO space available + bit_offset: 0 + bit_size: 16 + - name: NPTQXSAV + description: Non-periodic transmit request queue space available + bit_offset: 16 + bit_size: 8 + - name: NPTXQTOP + description: Top of the non-periodic transmit request queue + bit_offset: 24 + bit_size: 7 fieldset/GOTGCTL: description: Control and status register fields: - - name: SRQSCS - description: Session request success - bit_offset: 0 - bit_size: 1 - - name: SRQ - description: Session request - bit_offset: 1 - bit_size: 1 - - name: VBVALOEN - description: VBUS valid override enable - bit_offset: 2 - bit_size: 1 - - name: VBVALOVAL - description: VBUS valid override value - bit_offset: 3 - bit_size: 1 - - name: AVALOEN - description: A-peripheral session valid override enable - bit_offset: 4 - bit_size: 1 - - name: AVALOVAL - description: A-peripheral session valid override value - bit_offset: 5 - bit_size: 1 - - name: BVALOEN - description: B-peripheral session valid override enable - bit_offset: 6 - bit_size: 1 - - name: BVALOVAL - description: B-peripheral session valid override value - bit_offset: 7 - bit_size: 1 - - name: HNGSCS - description: Host negotiation success - bit_offset: 8 - bit_size: 1 - - name: HNPRQ - description: HNP request - bit_offset: 9 - bit_size: 1 - - name: HSHNPEN - description: Host set HNP enable - bit_offset: 10 - bit_size: 1 - - name: DHNPEN - description: Device HNP enabled - bit_offset: 11 - bit_size: 1 - - name: EHEN - description: Embedded host enable - bit_offset: 12 - bit_size: 1 - - name: CIDSTS - description: Connector ID status - bit_offset: 16 - bit_size: 1 - - name: DBCT - description: Long/short debounce time - bit_offset: 17 - bit_size: 1 - - name: ASVLD - description: A-session valid - bit_offset: 18 - bit_size: 1 - - name: BSVLD - description: B-session valid - bit_offset: 19 - bit_size: 1 + - name: SRQSCS + description: Session request success + bit_offset: 0 + bit_size: 1 + - name: SRQ + description: Session request + bit_offset: 1 + bit_size: 1 + - name: VBVALOEN + description: VBUS valid override enable + bit_offset: 2 + bit_size: 1 + - name: VBVALOVAL + description: VBUS valid override value + bit_offset: 3 + bit_size: 1 + - name: AVALOEN + description: A-peripheral session valid override enable + bit_offset: 4 + bit_size: 1 + - name: AVALOVAL + description: A-peripheral session valid override value + bit_offset: 5 + bit_size: 1 + - name: BVALOEN + description: B-peripheral session valid override enable + bit_offset: 6 + bit_size: 1 + - name: BVALOVAL + description: B-peripheral session valid override value + bit_offset: 7 + bit_size: 1 + - name: HNGSCS + description: Host negotiation success + bit_offset: 8 + bit_size: 1 + - name: HNPRQ + description: HNP request + bit_offset: 9 + bit_size: 1 + - name: HSHNPEN + description: Host set HNP enable + bit_offset: 10 + bit_size: 1 + - name: DHNPEN + description: Device HNP enabled + bit_offset: 11 + bit_size: 1 + - name: EHEN + description: Embedded host enable + bit_offset: 12 + bit_size: 1 + - name: CIDSTS + description: Connector ID status + bit_offset: 16 + bit_size: 1 + - name: DBCT + description: Long/short debounce time + bit_offset: 17 + bit_size: 1 + - name: ASVLD + description: A-session valid + bit_offset: 18 + bit_size: 1 + - name: BSVLD + description: B-session valid + bit_offset: 19 + bit_size: 1 fieldset/GOTGINT: description: Interrupt register fields: - - name: SEDET - description: Session end detected - bit_offset: 2 - bit_size: 1 - - name: SRSSCHG - description: Session request success status change - bit_offset: 8 - bit_size: 1 - - name: HNSSCHG - description: Host negotiation success status change - bit_offset: 9 - bit_size: 1 - - name: HNGDET - description: Host negotiation detected - bit_offset: 17 - bit_size: 1 - - name: ADTOCHG - description: A-device timeout change - bit_offset: 18 - bit_size: 1 - - name: DBCDNE - description: Debounce done - bit_offset: 19 - bit_size: 1 - - name: IDCHNG - description: ID input pin changed - bit_offset: 20 - bit_size: 1 + - name: SEDET + description: Session end detected + bit_offset: 2 + bit_size: 1 + - name: SRSSCHG + description: Session request success status change + bit_offset: 8 + bit_size: 1 + - name: HNSSCHG + description: Host negotiation success status change + bit_offset: 9 + bit_size: 1 + - name: HNGDET + description: Host negotiation detected + bit_offset: 17 + bit_size: 1 + - name: ADTOCHG + description: A-device timeout change + bit_offset: 18 + bit_size: 1 + - name: DBCDNE + description: Debounce done + bit_offset: 19 + bit_size: 1 + - name: IDCHNG + description: ID input pin changed + bit_offset: 20 + bit_size: 1 fieldset/GRSTCTL: description: Reset register fields: - - name: CSRST - description: Core soft reset - bit_offset: 0 - bit_size: 1 - - name: HSRST - description: HCLK soft reset - bit_offset: 1 - bit_size: 1 - - name: FCRST - description: Host frame counter reset - bit_offset: 2 - bit_size: 1 - - name: RXFFLSH - description: RxFIFO flush - bit_offset: 4 - bit_size: 1 - - name: TXFFLSH - description: TxFIFO flush - bit_offset: 5 - bit_size: 1 - - name: TXFNUM - description: TxFIFO number - bit_offset: 6 - bit_size: 5 - - name: DMAREQ - description: DMA request signal enabled for USB OTG HS - bit_offset: 30 - bit_size: 1 - - name: AHBIDL - description: AHB master idle - bit_offset: 31 - bit_size: 1 + - name: CSRST + description: Core soft reset + bit_offset: 0 + bit_size: 1 + - name: HSRST + description: HCLK soft reset + bit_offset: 1 + bit_size: 1 + - name: FCRST + description: Host frame counter reset + bit_offset: 2 + bit_size: 1 + - name: RXFFLSH + description: RxFIFO flush + bit_offset: 4 + bit_size: 1 + - name: TXFFLSH + description: TxFIFO flush + bit_offset: 5 + bit_size: 1 + - name: TXFNUM + description: TxFIFO number + bit_offset: 6 + bit_size: 5 + - name: DMAREQ + description: DMA request signal enabled for USB OTG HS + bit_offset: 30 + bit_size: 1 + - name: AHBIDL + description: AHB master idle + bit_offset: 31 + bit_size: 1 fieldset/GRXFSIZ: description: Receive FIFO size register fields: - - name: RXFD - description: RxFIFO depth - bit_offset: 0 - bit_size: 16 + - name: RXFD + description: RxFIFO depth + bit_offset: 0 + bit_size: 16 fieldset/GRXSTS: description: Status read and pop register fields: - - name: EPNUM - description: Endpoint number (device mode) / Channel number (host mode) - bit_offset: 0 - bit_size: 4 - - name: BCNT - description: Byte count - bit_offset: 4 - bit_size: 11 - - name: DPID - description: Data PID - bit_offset: 15 - bit_size: 2 - enum: DPID - - name: PKTSTSD - description: Packet status (device mode) - bit_offset: 17 - bit_size: 4 - enum: PKTSTSD - - name: PKTSTSH - description: Packet status (host mode) - bit_offset: 17 - bit_size: 4 - enum: PKTSTSH - - name: FRMNUM - description: Frame number (device mode) - bit_offset: 21 - bit_size: 4 + - name: EPNUM + description: Endpoint number (device mode) / Channel number (host mode) + bit_offset: 0 + bit_size: 4 + - name: BCNT + description: Byte count + bit_offset: 4 + bit_size: 11 + - name: DPID + description: Data PID + bit_offset: 15 + bit_size: 2 + enum: DPID + - name: PKTSTSD + description: Packet status (device mode) + bit_offset: 17 + bit_size: 4 + enum: PKTSTSD + - name: PKTSTSH + description: Packet status (host mode) + bit_offset: 17 + bit_size: 4 + enum: PKTSTSH + - name: FRMNUM + description: Frame number (device mode) + bit_offset: 21 + bit_size: 4 fieldset/GUSBCFG: description: USB configuration register fields: - - name: TOCAL - description: FS timeout calibration - bit_offset: 0 - bit_size: 3 - - name: PHYSEL - description: Full-speed internal serial transceiver enable - bit_offset: 6 - bit_size: 1 - - name: SRPCAP - description: SRP-capable - bit_offset: 8 - bit_size: 1 - - name: HNPCAP - description: HNP-capable - bit_offset: 9 - bit_size: 1 - - name: TRDT - description: USB turnaround time - bit_offset: 10 - bit_size: 4 - - name: PHYLPCS - description: PHY Low-power clock select - bit_offset: 15 - bit_size: 1 - - name: ULPIFSLS - description: ULPI FS/LS select - bit_offset: 17 - bit_size: 1 - - name: ULPIAR - description: ULPI Auto-resume - bit_offset: 18 - bit_size: 1 - - name: ULPICSM - description: ULPI Clock SuspendM - bit_offset: 19 - bit_size: 1 - - name: ULPIEVBUSD - description: ULPI External VBUS Drive - bit_offset: 20 - bit_size: 1 - - name: ULPIEVBUSI - description: ULPI external VBUS indicator - bit_offset: 21 - bit_size: 1 - - name: TSDPS - description: TermSel DLine pulsing selection - bit_offset: 22 - bit_size: 1 - - name: PCCI - description: Indicator complement - bit_offset: 23 - bit_size: 1 - - name: PTCI - description: Indicator pass through - bit_offset: 24 - bit_size: 1 - - name: ULPIIPD - description: ULPI interface protect disable - bit_offset: 25 - bit_size: 1 - - name: FHMOD - description: Force host mode - bit_offset: 29 - bit_size: 1 - - name: FDMOD - description: Force device mode - bit_offset: 30 - bit_size: 1 - - name: CTXPKT - description: Corrupt Tx packet - bit_offset: 31 - bit_size: 1 + - name: TOCAL + description: FS timeout calibration + bit_offset: 0 + bit_size: 3 + - name: PHYSEL + description: Full-speed internal serial transceiver enable + bit_offset: 6 + bit_size: 1 + - name: SRPCAP + description: SRP-capable + bit_offset: 8 + bit_size: 1 + - name: HNPCAP + description: HNP-capable + bit_offset: 9 + bit_size: 1 + - name: TRDT + description: USB turnaround time + bit_offset: 10 + bit_size: 4 + - name: PHYLPCS + description: PHY Low-power clock select + bit_offset: 15 + bit_size: 1 + - name: ULPIFSLS + description: ULPI FS/LS select + bit_offset: 17 + bit_size: 1 + - name: ULPIAR + description: ULPI Auto-resume + bit_offset: 18 + bit_size: 1 + - name: ULPICSM + description: ULPI Clock SuspendM + bit_offset: 19 + bit_size: 1 + - name: ULPIEVBUSD + description: ULPI External VBUS Drive + bit_offset: 20 + bit_size: 1 + - name: ULPIEVBUSI + description: ULPI external VBUS indicator + bit_offset: 21 + bit_size: 1 + - name: TSDPS + description: TermSel DLine pulsing selection + bit_offset: 22 + bit_size: 1 + - name: PCCI + description: Indicator complement + bit_offset: 23 + bit_size: 1 + - name: PTCI + description: Indicator pass through + bit_offset: 24 + bit_size: 1 + - name: ULPIIPD + description: ULPI interface protect disable + bit_offset: 25 + bit_size: 1 + - name: FHMOD + description: Force host mode + bit_offset: 29 + bit_size: 1 + - name: FDMOD + description: Force device mode + bit_offset: 30 + bit_size: 1 + - name: CTXPKT + description: Corrupt Tx packet + bit_offset: 31 + bit_size: 1 fieldset/HAINT: description: Host all channels interrupt register fields: - - name: HAINT - description: Channel interrupts - bit_offset: 0 - bit_size: 16 + - name: HAINT + description: Channel interrupts + bit_offset: 0 + bit_size: 16 fieldset/HAINTMSK: description: Host all channels interrupt mask register fields: - - name: HAINTM - description: Channel interrupt mask - bit_offset: 0 - bit_size: 16 + - name: HAINTM + description: Channel interrupt mask + bit_offset: 0 + bit_size: 16 fieldset/HCCHAR: description: Host channel characteristics register fields: - - name: MPSIZ - description: Maximum packet size - bit_offset: 0 - bit_size: 11 - - name: EPNUM - description: Endpoint number - bit_offset: 11 - bit_size: 4 - - name: EPDIR - description: Endpoint direction - bit_offset: 15 - bit_size: 1 - - name: LSDEV - description: Low-speed device - bit_offset: 17 - bit_size: 1 - - name: EPTYP - description: Endpoint type - bit_offset: 18 - bit_size: 2 - enum: EPTYP - - name: MCNT - description: Multicount - bit_offset: 20 - bit_size: 2 - - name: DAD - description: Device address - bit_offset: 22 - bit_size: 7 - - name: ODDFRM - description: Odd frame - bit_offset: 29 - bit_size: 1 - - name: CHDIS - description: Channel disable - bit_offset: 30 - bit_size: 1 - - name: CHENA - description: Channel enable - bit_offset: 31 - bit_size: 1 + - name: MPSIZ + description: Maximum packet size + bit_offset: 0 + bit_size: 11 + - name: EPNUM + description: Endpoint number + bit_offset: 11 + bit_size: 4 + - name: EPDIR + description: Endpoint direction + bit_offset: 15 + bit_size: 1 + - name: LSDEV + description: Low-speed device + bit_offset: 17 + bit_size: 1 + - name: EPTYP + description: Endpoint type + bit_offset: 18 + bit_size: 2 + enum: EPTYP + - name: MCNT + description: Multicount + bit_offset: 20 + bit_size: 2 + - name: DAD + description: Device address + bit_offset: 22 + bit_size: 7 + - name: ODDFRM + description: Odd frame + bit_offset: 29 + bit_size: 1 + - name: CHDIS + description: Channel disable + bit_offset: 30 + bit_size: 1 + - name: CHENA + description: Channel enable + bit_offset: 31 + bit_size: 1 fieldset/HCFG: description: Host configuration register fields: - - name: FSLSPCS - description: FS/LS PHY clock select - bit_offset: 0 - bit_size: 2 - - name: FSLSS - description: FS- and LS-only support - bit_offset: 2 - bit_size: 1 + - name: FSLSPCS + description: FS/LS PHY clock select + bit_offset: 0 + bit_size: 2 + - name: FSLSS + description: FS- and LS-only support + bit_offset: 2 + bit_size: 1 fieldset/HCINT: description: Host channel interrupt register fields: - - name: XFRC - description: Transfer completed - bit_offset: 0 - bit_size: 1 - - name: CHH - description: Channel halted - bit_offset: 1 - bit_size: 1 - - name: STALL - description: STALL response received interrupt - bit_offset: 3 - bit_size: 1 - - name: NAK - description: NAK response received interrupt - bit_offset: 4 - bit_size: 1 - - name: ACK - description: ACK response received/transmitted interrupt - bit_offset: 5 - bit_size: 1 - - name: TXERR - description: Transaction error - bit_offset: 7 - bit_size: 1 - - name: BBERR - description: Babble error - bit_offset: 8 - bit_size: 1 - - name: FRMOR - description: Frame overrun - bit_offset: 9 - bit_size: 1 - - name: DTERR - description: Data toggle error - bit_offset: 10 - bit_size: 1 + - name: XFRC + description: Transfer completed + bit_offset: 0 + bit_size: 1 + - name: CHH + description: Channel halted + bit_offset: 1 + bit_size: 1 + - name: STALL + description: STALL response received interrupt + bit_offset: 3 + bit_size: 1 + - name: NAK + description: NAK response received interrupt + bit_offset: 4 + bit_size: 1 + - name: ACK + description: ACK response received/transmitted interrupt + bit_offset: 5 + bit_size: 1 + - name: TXERR + description: Transaction error + bit_offset: 7 + bit_size: 1 + - name: BBERR + description: Babble error + bit_offset: 8 + bit_size: 1 + - name: FRMOR + description: Frame overrun + bit_offset: 9 + bit_size: 1 + - name: DTERR + description: Data toggle error + bit_offset: 10 + bit_size: 1 fieldset/HCINTMSK: description: Host channel mask register fields: - - name: XFRCM - description: Transfer completed mask - bit_offset: 0 - bit_size: 1 - - name: CHHM - description: Channel halted mask - bit_offset: 1 - bit_size: 1 - - name: STALLM - description: STALL response received interrupt mask - bit_offset: 3 - bit_size: 1 - - name: NAKM - description: NAK response received interrupt mask - bit_offset: 4 - bit_size: 1 - - name: ACKM - description: ACK response received/transmitted interrupt mask - bit_offset: 5 - bit_size: 1 - - name: NYET - description: Response received interrupt mask - bit_offset: 6 - bit_size: 1 - - name: TXERRM - description: Transaction error mask - bit_offset: 7 - bit_size: 1 - - name: BBERRM - description: Babble error mask - bit_offset: 8 - bit_size: 1 - - name: FRMORM - description: Frame overrun mask - bit_offset: 9 - bit_size: 1 - - name: DTERRM - description: Data toggle error mask - bit_offset: 10 - bit_size: 1 + - name: XFRCM + description: Transfer completed mask + bit_offset: 0 + bit_size: 1 + - name: CHHM + description: Channel halted mask + bit_offset: 1 + bit_size: 1 + - name: STALLM + description: STALL response received interrupt mask + bit_offset: 3 + bit_size: 1 + - name: NAKM + description: NAK response received interrupt mask + bit_offset: 4 + bit_size: 1 + - name: ACKM + description: ACK response received/transmitted interrupt mask + bit_offset: 5 + bit_size: 1 + - name: NYET + description: Response received interrupt mask + bit_offset: 6 + bit_size: 1 + - name: TXERRM + description: Transaction error mask + bit_offset: 7 + bit_size: 1 + - name: BBERRM + description: Babble error mask + bit_offset: 8 + bit_size: 1 + - name: FRMORM + description: Frame overrun mask + bit_offset: 9 + bit_size: 1 + - name: DTERRM + description: Data toggle error mask + bit_offset: 10 + bit_size: 1 fieldset/HCTSIZ: description: Host channel transfer size register fields: - - name: XFRSIZ - description: Transfer size - bit_offset: 0 - bit_size: 19 - - name: PKTCNT - description: Packet count - bit_offset: 19 - bit_size: 10 - - name: DPID - description: Data PID - bit_offset: 29 - bit_size: 2 + - name: XFRSIZ + description: Transfer size + bit_offset: 0 + bit_size: 19 + - name: PKTCNT + description: Packet count + bit_offset: 19 + bit_size: 10 + - name: DPID + description: Data PID + bit_offset: 29 + bit_size: 2 fieldset/HFIR: description: Host frame interval register fields: - - name: FRIVL - description: Frame interval - bit_offset: 0 - bit_size: 16 + - name: FRIVL + description: Frame interval + bit_offset: 0 + bit_size: 16 fieldset/HFNUM: description: Host frame number/frame time remaining register fields: - - name: FRNUM - description: Frame number - bit_offset: 0 - bit_size: 16 - - name: FTREM - description: Frame time remaining - bit_offset: 16 - bit_size: 16 + - name: FRNUM + description: Frame number + bit_offset: 0 + bit_size: 16 + - name: FTREM + description: Frame time remaining + bit_offset: 16 + bit_size: 16 fieldset/HNPTXSTS: description: Non-periodic transmit FIFO/queue status register fields: - - name: NPTXFSAV - description: Non-periodic TxFIFO space available - bit_offset: 0 - bit_size: 16 - - name: NPTQXSAV - description: Non-periodic transmit request queue space available - bit_offset: 16 - bit_size: 8 - - name: NPTXQTOP - description: Top of the non-periodic transmit request queue - bit_offset: 24 - bit_size: 7 + - name: NPTXFSAV + description: Non-periodic TxFIFO space available + bit_offset: 0 + bit_size: 16 + - name: NPTQXSAV + description: Non-periodic transmit request queue space available + bit_offset: 16 + bit_size: 8 + - name: NPTXQTOP + description: Top of the non-periodic transmit request queue + bit_offset: 24 + bit_size: 7 fieldset/HPRT: description: Host port control and status register fields: - - name: PCSTS - description: Port connect status - bit_offset: 0 - bit_size: 1 - - name: PCDET - description: Port connect detected - bit_offset: 1 - bit_size: 1 - - name: PENA - description: Port enable - bit_offset: 2 - bit_size: 1 - - name: PENCHNG - description: Port enable/disable change - bit_offset: 3 - bit_size: 1 - - name: POCA - description: Port overcurrent active - bit_offset: 4 - bit_size: 1 - - name: POCCHNG - description: Port overcurrent change - bit_offset: 5 - bit_size: 1 - - name: PRES - description: Port resume - bit_offset: 6 - bit_size: 1 - - name: PSUSP - description: Port suspend - bit_offset: 7 - bit_size: 1 - - name: PRST - description: Port reset - bit_offset: 8 - bit_size: 1 - - name: PLSTS - description: Port line status - bit_offset: 10 - bit_size: 2 - - name: PPWR - description: Port power - bit_offset: 12 - bit_size: 1 - - name: PTCTL - description: Port test control - bit_offset: 13 - bit_size: 4 - - name: PSPD - description: Port speed - bit_offset: 17 - bit_size: 2 + - name: PCSTS + description: Port connect status + bit_offset: 0 + bit_size: 1 + - name: PCDET + description: Port connect detected + bit_offset: 1 + bit_size: 1 + - name: PENA + description: Port enable + bit_offset: 2 + bit_size: 1 + - name: PENCHNG + description: Port enable/disable change + bit_offset: 3 + bit_size: 1 + - name: POCA + description: Port overcurrent active + bit_offset: 4 + bit_size: 1 + - name: POCCHNG + description: Port overcurrent change + bit_offset: 5 + bit_size: 1 + - name: PRES + description: Port resume + bit_offset: 6 + bit_size: 1 + - name: PSUSP + description: Port suspend + bit_offset: 7 + bit_size: 1 + - name: PRST + description: Port reset + bit_offset: 8 + bit_size: 1 + - name: PLSTS + description: Port line status + bit_offset: 10 + bit_size: 2 + - name: PPWR + description: Port power + bit_offset: 12 + bit_size: 1 + - name: PTCTL + description: Port test control + bit_offset: 13 + bit_size: 4 + - name: PSPD + description: Port speed + bit_offset: 17 + bit_size: 2 fieldset/HPTXSTS: description: Periodic transmit FIFO/queue status register fields: - - name: PTXFSAVL - description: Periodic transmit data FIFO space available - bit_offset: 0 - bit_size: 16 - - name: PTXQSAV - description: Periodic transmit request queue space available - bit_offset: 16 - bit_size: 8 - - name: PTXQTOP - description: Top of the periodic transmit request queue - bit_offset: 24 - bit_size: 8 + - name: PTXFSAVL + description: Periodic transmit data FIFO space available + bit_offset: 0 + bit_size: 16 + - name: PTXQSAV + description: Periodic transmit request queue space available + bit_offset: 16 + bit_size: 8 + - name: PTXQTOP + description: Top of the periodic transmit request queue + bit_offset: 24 + bit_size: 8 fieldset/PCGCCTL: description: Power and clock gating control register fields: - - name: STPPCLK - description: Stop PHY clock - bit_offset: 0 - bit_size: 1 - - name: GATEHCLK - description: Gate HCLK - bit_offset: 1 - bit_size: 1 - - name: PHYSUSP - description: PHY Suspended - bit_offset: 4 - bit_size: 1 + - name: STPPCLK + description: Stop PHY clock + bit_offset: 0 + bit_size: 1 + - name: GATEHCLK + description: Gate HCLK + bit_offset: 1 + bit_size: 1 + - name: PHYSUSP + description: PHY Suspended + bit_offset: 4 + bit_size: 1 enum/DPID: bit_size: 2 variants: - - name: DATA0 - value: 0 - - name: DATA2 - value: 1 - - name: DATA1 - value: 2 - - name: MDATA - value: 3 + - name: DATA0 + value: 0 + - name: DATA2 + value: 1 + - name: DATA1 + value: 2 + - name: MDATA + value: 3 enum/DSPD: bit_size: 2 variants: - - name: HIGH_SPEED - description: High speed - value: 0 - - name: FULL_SPEED_EXTERNAL - description: Full speed using external ULPI PHY - value: 1 - - name: FULL_SPEED_INTERNAL - description: Full speed using internal embedded PHY - value: 3 + - name: HIGH_SPEED + description: High speed + value: 0 + - name: FULL_SPEED_EXTERNAL + description: Full speed using external ULPI PHY + value: 1 + - name: FULL_SPEED_INTERNAL + description: Full speed using internal embedded PHY + value: 3 enum/EPTYP: bit_size: 2 variants: - - name: CONTROL - value: 0 - - name: ISOCHRONOUS - value: 1 - - name: BULK - value: 2 - - name: INTERRUPT - value: 3 + - name: CONTROL + value: 0 + - name: ISOCHRONOUS + value: 1 + - name: BULK + value: 2 + - name: INTERRUPT + value: 3 enum/PFIVL: bit_size: 2 variants: - - name: FRAME_INTERVAL_80 - description: 80% of the frame interval - value: 0 - - name: FRAME_INTERVAL_85 - description: 85% of the frame interval - value: 1 - - name: FRAME_INTERVAL_90 - description: 90% of the frame interval - value: 2 - - name: FRAME_INTERVAL_95 - description: 95% of the frame interval - value: 3 + - name: FRAME_INTERVAL_80 + description: 80% of the frame interval + value: 0 + - name: FRAME_INTERVAL_85 + description: 85% of the frame interval + value: 1 + - name: FRAME_INTERVAL_90 + description: 90% of the frame interval + value: 2 + - name: FRAME_INTERVAL_95 + description: 95% of the frame interval + value: 3 enum/PKTSTSD: bit_size: 4 variants: - - name: OUT_NAK - description: Global OUT NAK (triggers an interrupt) - value: 1 - - name: OUT_DATA_RX - description: OUT data packet received - value: 2 - - name: OUT_DATA_DONE - description: OUT transfer completed (triggers an interrupt) - value: 3 - - name: SETUP_DATA_DONE - description: SETUP transaction completed (triggers an interrupt) - value: 4 - - name: SETUP_DATA_RX - description: SETUP data packet received - value: 6 + - name: OUT_NAK + description: Global OUT NAK (triggers an interrupt) + value: 1 + - name: OUT_DATA_RX + description: OUT data packet received + value: 2 + - name: OUT_DATA_DONE + description: OUT transfer completed (triggers an interrupt) + value: 3 + - name: SETUP_DATA_DONE + description: SETUP transaction completed (triggers an interrupt) + value: 4 + - name: SETUP_DATA_RX + description: SETUP data packet received + value: 6 enum/PKTSTSH: bit_size: 4 variants: - - name: IN_DATA_RX - description: IN data packet received - value: 2 - - name: IN_DATA_DONE - description: IN transfer completed (triggers an interrupt) - value: 3 - - name: DATA_TOGGLE_ERR - description: Data toggle error (triggers an interrupt) - value: 5 - - name: CHANNEL_HALTED - description: Channel halted (triggers an interrupt) - value: 7 + - name: IN_DATA_RX + description: IN data packet received + value: 2 + - name: IN_DATA_DONE + description: IN transfer completed (triggers an interrupt) + value: 3 + - name: DATA_TOGGLE_ERR + description: Data toggle error (triggers an interrupt) + value: 5 + - name: CHANNEL_HALTED + description: Channel halted (triggers an interrupt) + value: 7 diff --git a/data/registers/pwr_c0.yaml b/data/registers/pwr_c0.yaml index eb0628c..0c7c7e1 100644 --- a/data/registers/pwr_c0.yaml +++ b/data/registers/pwr_c0.yaml @@ -1,134 +1,133 @@ ---- block/PWR: description: PWR address block description items: - - name: CR1 - description: PWR control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR3 - description: PWR control register 3 - byte_offset: 8 - fieldset: CR3 - - name: CR4 - description: PWR control register 4 - byte_offset: 12 - fieldset: CR4 - - name: SR1 - description: PWR status register 1 - byte_offset: 16 - fieldset: SR1 - - name: SR2 - description: PWR status register 2 - byte_offset: 20 - fieldset: SR2 - - name: SCR - description: PWR status clear register - byte_offset: 24 - fieldset: SCR - - name: PUCR - description: PWR Port pull-up control register - array: - len: 6 - stride: 8 - byte_offset: 32 - fieldset: PCR - - name: PDCR - description: PWR Port pull-down control register - array: - len: 6 - stride: 8 - byte_offset: 36 - fieldset: PCR + - name: CR1 + description: PWR control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR3 + description: PWR control register 3 + byte_offset: 8 + fieldset: CR3 + - name: CR4 + description: PWR control register 4 + byte_offset: 12 + fieldset: CR4 + - name: SR1 + description: PWR status register 1 + byte_offset: 16 + fieldset: SR1 + - name: SR2 + description: PWR status register 2 + byte_offset: 20 + fieldset: SR2 + - name: SCR + description: PWR status clear register + byte_offset: 24 + fieldset: SCR + - name: PUCR + description: PWR Port pull-up control register + array: + len: 6 + stride: 8 + byte_offset: 32 + fieldset: PCR + - name: PDCR + description: PWR Port pull-down control register + array: + len: 6 + stride: 8 + byte_offset: 36 + fieldset: PCR fieldset/CR1: description: PWR control register 1 fields: - - name: LPMS - description: "Low-power mode selection\r These bits select the low-power mode entered when CPU enters deepsleep mode.\r 1XX: Shutdown mode" - bit_offset: 0 - bit_size: 3 - - name: FPD_STOP - description: "Flash memory powered down during Stop mode\r This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode." - bit_offset: 3 - bit_size: 1 - - name: FPD_SLP - description: "Flash memory powered down during Sleep mode\r This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Sleep mode." - bit_offset: 5 - bit_size: 1 + - name: LPMS + description: "Low-power mode selection\r These bits select the low-power mode entered when CPU enters deepsleep mode.\r 1XX: Shutdown mode" + bit_offset: 0 + bit_size: 3 + - name: FPD_STOP + description: "Flash memory powered down during Stop mode\r This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode." + bit_offset: 3 + bit_size: 1 + - name: FPD_SLP + description: "Flash memory powered down during Sleep mode\r This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Sleep mode." + bit_offset: 5 + bit_size: 1 fieldset/CR3: description: PWR control register 3 fields: - - name: EWUP - description: Enable Wakeup pin - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: APC - description: "Apply pull-up and pull-down configuration\r This bit determines whether the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied." - bit_offset: 10 - bit_size: 1 - - name: EIWUL - description: "Enable internal wakeup line\r When set, a rising edge on the internal wakeup line triggers a wakeup event." - bit_offset: 15 - bit_size: 1 + - name: EWUP + description: Enable Wakeup pin + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: APC + description: "Apply pull-up and pull-down configuration\r This bit determines whether the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied." + bit_offset: 10 + bit_size: 1 + - name: EIWUL + description: "Enable internal wakeup line\r When set, a rising edge on the internal wakeup line triggers a wakeup event." + bit_offset: 15 + bit_size: 1 fieldset/CR4: description: PWR control register 4 fields: - - name: WP - description: Wakeup pin WKUP1 polarity - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 + - name: WP + description: Wakeup pin WKUP1 polarity + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 fieldset/PCR: description: Power Port pull control register fields: - - name: P - description: Port pull bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 + - name: P + description: Port pull bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 fieldset/SCR: description: PWR status clear register fields: - - name: CWUF - description: Clear Wakeup flag - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: CSBF - description: "Clear standby flag\r Setting this bit clears the SBF flag in the PWR_SR1 register." - bit_offset: 8 - bit_size: 1 + - name: CWUF + description: Clear Wakeup flag + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: CSBF + description: "Clear standby flag\r Setting this bit clears the SBF flag in the PWR_SR1 register." + bit_offset: 8 + bit_size: 1 fieldset/SR1: description: PWR status register 1 fields: - - name: WUF - description: Wakeup flag - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: SBF - description: "Standby/Shutdown flag\r This bit is set by hardware when the device enters Standby or Shutdown mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset." - bit_offset: 8 - bit_size: 1 - - name: WUFI - description: "Wakeup flag internal\r This bit is set when a wakeup condition is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared." - bit_offset: 15 - bit_size: 1 + - name: WUF + description: Wakeup flag + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: SBF + description: "Standby/Shutdown flag\r This bit is set by hardware when the device enters Standby or Shutdown mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset." + bit_offset: 8 + bit_size: 1 + - name: WUFI + description: "Wakeup flag internal\r This bit is set when a wakeup condition is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared." + bit_offset: 15 + bit_size: 1 fieldset/SR2: description: PWR status register 2 fields: - - name: FLASH_RDY - description: "Flash ready flag\r This bit is set by hardware to indicate when the Flash memory is ready to be accessed after wakeup from power-down. To place the Flash memory in power-down, set either FPD_SLP or FPD_STP bit.\r Note: If the system boots from SRAM, the user application must wait till FLASH_RDY bit is set, prior to jumping to Flash memory." - bit_offset: 7 - bit_size: 1 + - name: FLASH_RDY + description: "Flash ready flag\r This bit is set by hardware to indicate when the Flash memory is ready to be accessed after wakeup from power-down. To place the Flash memory in power-down, set either FPD_SLP or FPD_STP bit.\r Note: If the system boots from SRAM, the user application must wait till FLASH_RDY bit is set, prior to jumping to Flash memory." + bit_offset: 7 + bit_size: 1 diff --git a/data/registers/pwr_f0.yaml b/data/registers/pwr_f0.yaml new file mode 100644 index 0000000..7b438d5 --- /dev/null +++ b/data/registers/pwr_f0.yaml @@ -0,0 +1,78 @@ +block/PWR: + description: Power control + items: + - name: CR + description: power control register + byte_offset: 0 + fieldset: CR + - name: CSR + description: power control/status register + byte_offset: 4 + fieldset: CSR +fieldset/CR: + description: power control register + fields: + - name: LPDS + description: Low-power deep sleep + bit_offset: 0 + bit_size: 1 + - name: PDDS + description: Power down deepsleep + bit_offset: 1 + bit_size: 1 + enum: PDDS + - name: CWUF + description: Clear wakeup flag + bit_offset: 2 + bit_size: 1 + - name: CSBF + description: Clear standby flag + bit_offset: 3 + bit_size: 1 + - name: PVDE + description: Power voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PLS + description: PVD level selection + bit_offset: 5 + bit_size: 3 + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 +fieldset/CSR: + description: power control/status register + fields: + - name: WUF + description: Wakeup flag + bit_offset: 0 + bit_size: 1 + - name: SBF + description: Standby flag + bit_offset: 1 + bit_size: 1 + - name: PVDO + description: PVD output + bit_offset: 2 + bit_size: 1 + - name: VREFINTRDY + description: VREFINT reference voltage ready + bit_offset: 3 + bit_size: 1 + - name: EWUP + description: Enable WKUP pin 1 + bit_offset: 8 + bit_size: 1 + array: + len: 8 + stride: 1 +enum/PDDS: + bit_size: 1 + variants: + - name: STOP_MODE + description: Enter Stop mode when the CPU enters deepsleep + value: 0 + - name: STANDBY_MODE + description: Enter Standby mode when the CPU enters deepsleep + value: 1 diff --git a/data/registers/pwr_f0x0.yaml b/data/registers/pwr_f0x0.yaml new file mode 100644 index 0000000..795bc33 --- /dev/null +++ b/data/registers/pwr_f0x0.yaml @@ -0,0 +1,62 @@ +block/PWR: + description: Power control + items: + - name: CR + description: power control register + byte_offset: 0 + fieldset: CR + - name: CSR + description: power control/status register + byte_offset: 4 + fieldset: CSR +fieldset/CR: + description: power control register + fields: + - name: LPDS + description: Low-power deep sleep + bit_offset: 0 + bit_size: 1 + - name: PDDS + description: Power down deepsleep + bit_offset: 1 + bit_size: 1 + enum: PDDS + - name: CWUF + description: Clear wakeup flag + bit_offset: 2 + bit_size: 1 + - name: CSBF + description: Clear standby flag + bit_offset: 3 + bit_size: 1 + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 +fieldset/CSR: + description: power control/status register + fields: + - name: WUF + description: Wakeup flag + bit_offset: 0 + bit_size: 1 + - name: SBF + description: Standby flag + bit_offset: 1 + bit_size: 1 + - name: EWUP + description: Enable WKUP pin 1 + bit_offset: 8 + bit_size: 1 + array: + len: 8 + stride: 1 +enum/PDDS: + bit_size: 1 + variants: + - name: STOP_MODE + description: Enter Stop mode when the CPU enters deepsleep + value: 0 + - name: STANDBY_MODE + description: Enter Standby mode when the CPU enters deepsleep + value: 1 diff --git a/data/registers/pwr_f1.yaml b/data/registers/pwr_f1.yaml new file mode 100644 index 0000000..96e2858 --- /dev/null +++ b/data/registers/pwr_f1.yaml @@ -0,0 +1,71 @@ +block/PWR: + description: Power control + items: + - name: CR + description: Power control register (PWR_CR) + byte_offset: 0 + fieldset: CR + - name: CSR + description: Power control register (PWR_CR) + byte_offset: 4 + fieldset: CSR +fieldset/CR: + description: Power control register (PWR_CR) + fields: + - name: LPDS + description: Low Power Deep Sleep + bit_offset: 0 + bit_size: 1 + - name: PDDS + description: Power Down Deep Sleep + bit_offset: 1 + bit_size: 1 + enum: PDDS + - name: CWUF + description: Clear Wake-up Flag + bit_offset: 2 + bit_size: 1 + - name: CSBF + description: Clear STANDBY Flag + bit_offset: 3 + bit_size: 1 + - name: PVDE + description: Power Voltage Detector Enable + bit_offset: 4 + bit_size: 1 + - name: PLS + description: PVD Level Selection + bit_offset: 5 + bit_size: 3 + - name: DBP + description: Disable Backup Domain write protection + bit_offset: 8 + bit_size: 1 +fieldset/CSR: + description: Power control register (PWR_CR) + fields: + - name: WUF + description: Wake-Up Flag + bit_offset: 0 + bit_size: 1 + - name: SBF + description: STANDBY Flag + bit_offset: 1 + bit_size: 1 + - name: PVDO + description: PVD Output + bit_offset: 2 + bit_size: 1 + - name: EWUP + description: Enable WKUP pin + bit_offset: 8 + bit_size: 1 +enum/PDDS: + bit_size: 1 + variants: + - name: STOP_MODE + description: Enter Stop mode when the CPU enters deepsleep + value: 0 + - name: STANDBY_MODE + description: Enter Standby mode when the CPU enters deepsleep + value: 1 diff --git a/data/registers/pwr_f2.yaml b/data/registers/pwr_f2.yaml index c9ff8bd..6b3c36d 100644 --- a/data/registers/pwr_f2.yaml +++ b/data/registers/pwr_f2.yaml @@ -1,84 +1,83 @@ ---- block/PWR: description: Power control items: - - name: CR - description: power control register - byte_offset: 0 - fieldset: CR - - name: CSR - description: power control/status register - byte_offset: 4 - fieldset: CSR + - name: CR + description: power control register + byte_offset: 0 + fieldset: CR + - name: CSR + description: power control/status register + byte_offset: 4 + fieldset: CSR fieldset/CR: description: power control register fields: - - name: LPDS - description: Low-power deep sleep - bit_offset: 0 - bit_size: 1 - - name: PDDS - description: Power down deepsleep - bit_offset: 1 - bit_size: 1 - enum: PDDS - - name: CWUF - description: Clear wakeup flag - bit_offset: 2 - bit_size: 1 - - name: CSBF - description: Clear standby flag - bit_offset: 3 - bit_size: 1 - - name: PVDE - description: Power voltage detector enable - bit_offset: 4 - bit_size: 1 - - name: PLS - description: PVD level selection - bit_offset: 5 - bit_size: 3 - - name: DBP - description: Disable backup domain write protection - bit_offset: 8 - bit_size: 1 - - name: FPDS - description: Flash power down in Stop mode - bit_offset: 9 - bit_size: 1 + - name: LPDS + description: Low-power deep sleep + bit_offset: 0 + bit_size: 1 + - name: PDDS + description: Power down deepsleep + bit_offset: 1 + bit_size: 1 + enum: PDDS + - name: CWUF + description: Clear wakeup flag + bit_offset: 2 + bit_size: 1 + - name: CSBF + description: Clear standby flag + bit_offset: 3 + bit_size: 1 + - name: PVDE + description: Power voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PLS + description: PVD level selection + bit_offset: 5 + bit_size: 3 + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: FPDS + description: Flash power down in Stop mode + bit_offset: 9 + bit_size: 1 fieldset/CSR: description: power control/status register fields: - - name: WUF - description: Wakeup flag - bit_offset: 0 - bit_size: 1 - - name: SBF - description: Standby flag - bit_offset: 1 - bit_size: 1 - - name: PVDO - description: PVD output - bit_offset: 2 - bit_size: 1 - - name: BRR - description: Backup regulator ready - bit_offset: 3 - bit_size: 1 - - name: EWUP - description: Enable WKUP pin - bit_offset: 8 - bit_size: 1 - - name: BRE - description: Backup regulator enable - bit_offset: 9 - bit_size: 1 + - name: WUF + description: Wakeup flag + bit_offset: 0 + bit_size: 1 + - name: SBF + description: Standby flag + bit_offset: 1 + bit_size: 1 + - name: PVDO + description: PVD output + bit_offset: 2 + bit_size: 1 + - name: BRR + description: Backup regulator ready + bit_offset: 3 + bit_size: 1 + - name: EWUP + description: Enable WKUP pin + bit_offset: 8 + bit_size: 1 + - name: BRE + description: Backup regulator enable + bit_offset: 9 + bit_size: 1 enum/PDDS: bit_size: 1 variants: - - name: STOP_MODE - description: Enter Stop mode when the CPU enters deepsleep - value: 0 - - name: STANDBY_MODE - description: Enter Standby mode when the CPU enters deepsleep - value: 1 + - name: STOP_MODE + description: Enter Stop mode when the CPU enters deepsleep + value: 0 + - name: STANDBY_MODE + description: Enter Standby mode when the CPU enters deepsleep + value: 1 diff --git a/data/registers/pwr_f3.yaml b/data/registers/pwr_f3.yaml index d83cca3..383d25a 100644 --- a/data/registers/pwr_f3.yaml +++ b/data/registers/pwr_f3.yaml @@ -1,86 +1,85 @@ ---- block/PWR: description: Power control items: - - name: CR - description: power control register - byte_offset: 0 - fieldset: CR - - name: CSR - description: power control/status register - byte_offset: 4 - fieldset: CSR + - name: CR + description: power control register + byte_offset: 0 + fieldset: CR + - name: CSR + description: power control/status register + byte_offset: 4 + fieldset: CSR fieldset/CR: description: power control register fields: - - name: LPDS - description: Low-power deep sleep - bit_offset: 0 - bit_size: 1 - - name: PDDS - description: Power down deepsleep - bit_offset: 1 - bit_size: 1 - enum: PDDS - - name: CWUF - description: Clear wakeup flag - bit_offset: 2 - bit_size: 1 - - name: CSBF - description: Clear standby flag - bit_offset: 3 - bit_size: 1 - - name: PVDE - description: Power voltage detector enable - bit_offset: 4 - bit_size: 1 - - name: PLS - description: PVD level selection - bit_offset: 5 - bit_size: 3 - - name: DBP - description: Disable backup domain write protection - bit_offset: 8 - bit_size: 1 - - name: ENSD - description: ENable SD1 ADC - bit_offset: 9 - bit_size: 1 - array: - len: 3 - stride: 1 + - name: LPDS + description: Low-power deep sleep + bit_offset: 0 + bit_size: 1 + - name: PDDS + description: Power down deepsleep + bit_offset: 1 + bit_size: 1 + enum: PDDS + - name: CWUF + description: Clear wakeup flag + bit_offset: 2 + bit_size: 1 + - name: CSBF + description: Clear standby flag + bit_offset: 3 + bit_size: 1 + - name: PVDE + description: Power voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PLS + description: PVD level selection + bit_offset: 5 + bit_size: 3 + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: ENSD + description: ENable SD1 ADC + bit_offset: 9 + bit_size: 1 + array: + len: 3 + stride: 1 fieldset/CSR: description: power control/status register fields: - - name: WUF - description: Wakeup flag - bit_offset: 0 - bit_size: 1 - - name: SBF - description: Standby flag - bit_offset: 1 - bit_size: 1 - - name: PVDO - description: PVD output - bit_offset: 2 - bit_size: 1 - - name: VREFINTRDYF - description: Internal voltage reference ready flag - bit_offset: 3 - bit_size: 1 - - name: EWUP - description: Enable WKUP1 pin - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 + - name: WUF + description: Wakeup flag + bit_offset: 0 + bit_size: 1 + - name: SBF + description: Standby flag + bit_offset: 1 + bit_size: 1 + - name: PVDO + description: PVD output + bit_offset: 2 + bit_size: 1 + - name: VREFINTRDYF + description: Internal voltage reference ready flag + bit_offset: 3 + bit_size: 1 + - name: EWUP + description: Enable WKUP1 pin + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 enum/PDDS: bit_size: 1 variants: - - name: STOP_MODE - description: Enter Stop mode when the CPU enters deepsleep - value: 0 - - name: STANDBY_MODE - description: Enter Standby mode when the CPU enters deepsleep - value: 1 + - name: STOP_MODE + description: Enter Stop mode when the CPU enters deepsleep + value: 0 + - name: STANDBY_MODE + description: Enter Standby mode when the CPU enters deepsleep + value: 1 diff --git a/data/registers/pwr_f4.yaml b/data/registers/pwr_f4.yaml index 9a9d68e..5e2252a 100644 --- a/data/registers/pwr_f4.yaml +++ b/data/registers/pwr_f4.yaml @@ -1,153 +1,152 @@ ---- block/PWR: description: Power control items: - - name: CR1 - description: power control register - byte_offset: 0 - fieldset: CR1 - - name: CSR1 - description: power control/status register - byte_offset: 4 - fieldset: CSR1 + - name: CR1 + description: power control register + byte_offset: 0 + fieldset: CR1 + - name: CSR1 + description: power control/status register + byte_offset: 4 + fieldset: CSR1 fieldset/CR1: description: power control register fields: - - name: LPDS - description: Low-power deep sleep - bit_offset: 0 - bit_size: 1 - - name: PDDS - description: Power down deepsleep - bit_offset: 1 - bit_size: 1 - enum: PDDS - - name: CWUF - description: Clear wakeup flag - bit_offset: 2 - bit_size: 1 - - name: CSBF - description: Clear standby flag - bit_offset: 3 - bit_size: 1 - - name: PVDE - description: Power voltage detector enable - bit_offset: 4 - bit_size: 1 - - name: PLS - description: PVD level selection - bit_offset: 5 - bit_size: 3 - - name: DBP - description: Disable backup domain write protection - bit_offset: 8 - bit_size: 1 - - name: FPDS - description: Flash power down in Stop mode - bit_offset: 9 - bit_size: 1 - - name: LPLVDS - description: Low-Power Regulator Low Voltage in deepsleep - bit_offset: 10 - bit_size: 1 - - name: MRLVDS - description: Main regulator low voltage in deepsleep mode - bit_offset: 11 - bit_size: 1 - - name: ADCDC1 - description: ADCDC1 - bit_offset: 13 - bit_size: 1 - - name: VOS - description: Regulator voltage scaling output selection - bit_offset: 14 - bit_size: 2 - enum: VOS - - name: ODEN - description: "Over-drive enable (STM32F4[23] ONLY)" - bit_offset: 16 - bit_size: 1 - - name: ODSWEN - description: "Over-drive switching enabled (STM32F4[23] ONLY)" - bit_offset: 17 - bit_size: 1 - - name: UDEN - description: "Under-drive enable in stop mode (STM32F4[23] ONLY)" - bit_offset: 18 - bit_size: 2 - - name: FMSSR - description: Flash Memory Stop while System Run - bit_offset: 20 - bit_size: 1 - - name: FISSR - description: Flash Interface Stop while System Run - bit_offset: 21 - bit_size: 1 + - name: LPDS + description: Low-power deep sleep + bit_offset: 0 + bit_size: 1 + - name: PDDS + description: Power down deepsleep + bit_offset: 1 + bit_size: 1 + enum: PDDS + - name: CWUF + description: Clear wakeup flag + bit_offset: 2 + bit_size: 1 + - name: CSBF + description: Clear standby flag + bit_offset: 3 + bit_size: 1 + - name: PVDE + description: Power voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PLS + description: PVD level selection + bit_offset: 5 + bit_size: 3 + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: FPDS + description: Flash power down in Stop mode + bit_offset: 9 + bit_size: 1 + - name: LPLVDS + description: Low-Power Regulator Low Voltage in deepsleep + bit_offset: 10 + bit_size: 1 + - name: MRLVDS + description: Main regulator low voltage in deepsleep mode + bit_offset: 11 + bit_size: 1 + - name: ADCDC1 + description: ADCDC1 + bit_offset: 13 + bit_size: 1 + - name: VOS + description: Regulator voltage scaling output selection + bit_offset: 14 + bit_size: 2 + enum: VOS + - name: ODEN + description: Over-drive enable (STM32F4[23] ONLY) + bit_offset: 16 + bit_size: 1 + - name: ODSWEN + description: Over-drive switching enabled (STM32F4[23] ONLY) + bit_offset: 17 + bit_size: 1 + - name: UDEN + description: Under-drive enable in stop mode (STM32F4[23] ONLY) + bit_offset: 18 + bit_size: 2 + - name: FMSSR + description: Flash Memory Stop while System Run + bit_offset: 20 + bit_size: 1 + - name: FISSR + description: Flash Interface Stop while System Run + bit_offset: 21 + bit_size: 1 fieldset/CSR1: description: power control/status register fields: - - name: WUF - description: Wakeup flag - bit_offset: 0 - bit_size: 1 - - name: SBF - description: Standby flag - bit_offset: 1 - bit_size: 1 - - name: PVDO - description: PVD output - bit_offset: 2 - bit_size: 1 - - name: BRR - description: Backup regulator ready - bit_offset: 3 - bit_size: 1 - - name: EWUP2 - description: Enable WKUP2 pin - bit_offset: 7 - bit_size: 1 - - name: EWUP - description: Enable WKUP pin - bit_offset: 8 - bit_size: 1 - - name: BRE - description: Backup regulator enable - bit_offset: 9 - bit_size: 1 - - name: VOSRDY - description: "Regulator voltage scaling output selection ready bit (STM32F4[23] ONLY)" - bit_offset: 14 - bit_size: 1 - - name: ODRDY - description: "Over-drive mode ready (STM32F4[23] ONLY)" - bit_offset: 16 - bit_size: 1 - - name: ODSWRDY - description: "Over-drive mode switching ready (STM32F4[23] ONLY)" - bit_offset: 17 - bit_size: 1 - - name: UDRDY - description: Under-drive ready flag - bit_offset: 18 - bit_size: 2 + - name: WUF + description: Wakeup flag + bit_offset: 0 + bit_size: 1 + - name: SBF + description: Standby flag + bit_offset: 1 + bit_size: 1 + - name: PVDO + description: PVD output + bit_offset: 2 + bit_size: 1 + - name: BRR + description: Backup regulator ready + bit_offset: 3 + bit_size: 1 + - name: EWUP2 + description: Enable WKUP2 pin + bit_offset: 7 + bit_size: 1 + - name: EWUP + description: Enable WKUP pin + bit_offset: 8 + bit_size: 1 + - name: BRE + description: Backup regulator enable + bit_offset: 9 + bit_size: 1 + - name: VOSRDY + description: Regulator voltage scaling output selection ready bit (STM32F4[23] ONLY) + bit_offset: 14 + bit_size: 1 + - name: ODRDY + description: Over-drive mode ready (STM32F4[23] ONLY) + bit_offset: 16 + bit_size: 1 + - name: ODSWRDY + description: Over-drive mode switching ready (STM32F4[23] ONLY) + bit_offset: 17 + bit_size: 1 + - name: UDRDY + description: Under-drive ready flag + bit_offset: 18 + bit_size: 2 enum/PDDS: bit_size: 1 variants: - - name: STOP_MODE - description: Enter Stop mode when the CPU enters deepsleep - value: 0 - - name: STANDBY_MODE - description: Enter Standby mode when the CPU enters deepsleep - value: 1 + - name: STOP_MODE + description: Enter Stop mode when the CPU enters deepsleep + value: 0 + - name: STANDBY_MODE + description: Enter Standby mode when the CPU enters deepsleep + value: 1 enum/VOS: bit_size: 2 variants: - - name: SCALE3 - description: "Scale 3 mode (STM32F4[23] ONLY)" - value: 1 - - name: SCALE2 - description: Scale 2 mode - value: 2 - - name: SCALE1 - description: Scale 1 mode (reset value) - value: 3 + - name: SCALE3 + description: Scale 3 mode (STM32F4[23] ONLY) + value: 1 + - name: SCALE2 + description: Scale 2 mode + value: 2 + - name: SCALE1 + description: Scale 1 mode (reset value) + value: 3 diff --git a/data/registers/pwr_f7.yaml b/data/registers/pwr_f7.yaml index 3eafd3c..876d2f2 100644 --- a/data/registers/pwr_f7.yaml +++ b/data/registers/pwr_f7.yaml @@ -1,179 +1,178 @@ ---- block/PWR: description: Power control items: - - name: CR1 - description: power control register - byte_offset: 0 - fieldset: CR1 - - name: CSR1 - description: power control/status register - byte_offset: 4 - fieldset: CSR1 - - name: CR2 - description: power control register - byte_offset: 8 - fieldset: CR2 - - name: CSR2 - description: power control/status register - byte_offset: 12 - fieldset: CSR2 + - name: CR1 + description: power control register + byte_offset: 0 + fieldset: CR1 + - name: CSR1 + description: power control/status register + byte_offset: 4 + fieldset: CSR1 + - name: CR2 + description: power control register + byte_offset: 8 + fieldset: CR2 + - name: CSR2 + description: power control/status register + byte_offset: 12 + fieldset: CSR2 fieldset/CR1: description: power control register fields: - - name: LPDS - description: Low-power deep sleep - bit_offset: 0 - bit_size: 1 - - name: PDDS - description: Power down deepsleep - bit_offset: 1 - bit_size: 1 - enum: PDDS - - name: CSBF - description: Clear standby flag - bit_offset: 3 - bit_size: 1 - - name: PVDE - description: Power voltage detector enable - bit_offset: 4 - bit_size: 1 - - name: PLS - description: PVD level selection - bit_offset: 5 - bit_size: 3 - - name: DBP - description: Disable backup domain write protection - bit_offset: 8 - bit_size: 1 - - name: FPDS - description: Flash power down in Stop mode - bit_offset: 9 - bit_size: 1 - - name: LPUDS - description: Low-power regulator in deepsleep under-drive mode - bit_offset: 10 - bit_size: 1 - - name: MRUDS - description: Main regulator in deepsleep under-drive mode - bit_offset: 11 - bit_size: 1 - - name: ADCDC1 - description: ADCDC1 - bit_offset: 13 - bit_size: 1 - - name: VOS - description: Regulator voltage scaling output selection - bit_offset: 14 - bit_size: 2 - enum: VOS - - name: ODEN - description: Over-drive enable - bit_offset: 16 - bit_size: 1 - - name: ODSWEN - description: Over-drive switching enabled - bit_offset: 17 - bit_size: 1 - - name: UDEN - description: Under-drive enable in stop mode - bit_offset: 18 - bit_size: 2 + - name: LPDS + description: Low-power deep sleep + bit_offset: 0 + bit_size: 1 + - name: PDDS + description: Power down deepsleep + bit_offset: 1 + bit_size: 1 + enum: PDDS + - name: CSBF + description: Clear standby flag + bit_offset: 3 + bit_size: 1 + - name: PVDE + description: Power voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PLS + description: PVD level selection + bit_offset: 5 + bit_size: 3 + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: FPDS + description: Flash power down in Stop mode + bit_offset: 9 + bit_size: 1 + - name: LPUDS + description: Low-power regulator in deepsleep under-drive mode + bit_offset: 10 + bit_size: 1 + - name: MRUDS + description: Main regulator in deepsleep under-drive mode + bit_offset: 11 + bit_size: 1 + - name: ADCDC1 + description: ADCDC1 + bit_offset: 13 + bit_size: 1 + - name: VOS + description: Regulator voltage scaling output selection + bit_offset: 14 + bit_size: 2 + enum: VOS + - name: ODEN + description: Over-drive enable + bit_offset: 16 + bit_size: 1 + - name: ODSWEN + description: Over-drive switching enabled + bit_offset: 17 + bit_size: 1 + - name: UDEN + description: Under-drive enable in stop mode + bit_offset: 18 + bit_size: 2 fieldset/CR2: description: power control register fields: - - name: CWUPF - description: Clear Wakeup Pin flag for PA0 - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: WUPP - description: Wakeup pin polarity bit for PA0 - bit_offset: 8 - bit_size: 1 - array: - len: 6 - stride: 1 + - name: CWUPF + description: Clear Wakeup Pin flag for PA0 + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: WUPP + description: Wakeup pin polarity bit for PA0 + bit_offset: 8 + bit_size: 1 + array: + len: 6 + stride: 1 fieldset/CSR1: description: power control/status register fields: - - name: WUIF - description: Wakeup internal flag - bit_offset: 0 - bit_size: 1 - - name: SBF - description: Standby flag - bit_offset: 1 - bit_size: 1 - - name: PVDO - description: PVD output - bit_offset: 2 - bit_size: 1 - - name: BRR - description: Backup regulator ready - bit_offset: 3 - bit_size: 1 - - name: EIWUP - description: Enable internal wakeup - bit_offset: 8 - bit_size: 1 - - name: BRE - description: Backup regulator enable - bit_offset: 9 - bit_size: 1 - - name: VOSRDY - description: Regulator voltage scaling output selection ready bit - bit_offset: 14 - bit_size: 1 - - name: ODRDY - description: Over-drive mode ready - bit_offset: 16 - bit_size: 1 - - name: ODSWRDY - description: Over-drive mode switching ready - bit_offset: 17 - bit_size: 1 - - name: UDRDY - description: Under-drive ready flag - bit_offset: 18 - bit_size: 2 + - name: WUIF + description: Wakeup internal flag + bit_offset: 0 + bit_size: 1 + - name: SBF + description: Standby flag + bit_offset: 1 + bit_size: 1 + - name: PVDO + description: PVD output + bit_offset: 2 + bit_size: 1 + - name: BRR + description: Backup regulator ready + bit_offset: 3 + bit_size: 1 + - name: EIWUP + description: Enable internal wakeup + bit_offset: 8 + bit_size: 1 + - name: BRE + description: Backup regulator enable + bit_offset: 9 + bit_size: 1 + - name: VOSRDY + description: Regulator voltage scaling output selection ready bit + bit_offset: 14 + bit_size: 1 + - name: ODRDY + description: Over-drive mode ready + bit_offset: 16 + bit_size: 1 + - name: ODSWRDY + description: Over-drive mode switching ready + bit_offset: 17 + bit_size: 1 + - name: UDRDY + description: Under-drive ready flag + bit_offset: 18 + bit_size: 2 fieldset/CSR2: description: power control/status register fields: - - name: WUPF - description: Wakeup Pin flag for PA0 - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: EWUP - description: Enable Wakeup pin for PA0 - bit_offset: 8 - bit_size: 1 - array: - len: 6 - stride: 1 + - name: WUPF + description: Wakeup Pin flag for PA0 + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: EWUP + description: Enable Wakeup pin for PA0 + bit_offset: 8 + bit_size: 1 + array: + len: 6 + stride: 1 enum/PDDS: bit_size: 1 variants: - - name: STOP_MODE - description: Enter Stop mode when the CPU enters deepsleep - value: 0 - - name: STANDBY_MODE - description: Enter Standby mode when the CPU enters deepsleep - value: 1 + - name: STOP_MODE + description: Enter Stop mode when the CPU enters deepsleep + value: 0 + - name: STANDBY_MODE + description: Enter Standby mode when the CPU enters deepsleep + value: 1 enum/VOS: bit_size: 2 variants: - - name: SCALE3 - description: Scale 3 mode - value: 1 - - name: SCALE2 - description: Scale 2 mode - value: 2 - - name: SCALE1 - description: Scale 1 mode (reset value) - value: 3 + - name: SCALE3 + description: Scale 3 mode + value: 1 + - name: SCALE2 + description: Scale 2 mode + value: 2 + - name: SCALE1 + description: Scale 1 mode (reset value) + value: 3 diff --git a/data/registers/pwr_g0.yaml b/data/registers/pwr_g0.yaml index ad52698..886bc07 100644 --- a/data/registers/pwr_g0.yaml +++ b/data/registers/pwr_g0.yaml @@ -1,204 +1,211 @@ ---- block/PWR: description: Power control items: - - name: CR1 - description: Power control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Power control register 2 - byte_offset: 4 - fieldset: CR2 - - name: CR3 - description: Power control register 3 - byte_offset: 8 - fieldset: CR3 - - name: CR4 - description: Power control register 4 - byte_offset: 12 - fieldset: CR4 - - name: SR1 - description: Power status register 1 - byte_offset: 16 - access: Read - fieldset: SR1 - - name: SR2 - description: Power status register 2 - byte_offset: 20 - access: Read - fieldset: SR2 - - name: SCR - description: Power status clear register - byte_offset: 24 - access: Write - fieldset: SCR - - name: PUCR - description: Power Port pull-up control register - array: - len: 6 - stride: 8 - byte_offset: 32 - fieldset: PCR - - name: PDCR - description: Power Port pull-down control register - array: - len: 6 - stride: 8 - byte_offset: 36 - fieldset: PCR + - name: CR1 + description: Power control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Power control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: Power control register 3 + byte_offset: 8 + fieldset: CR3 + - name: CR4 + description: Power control register 4 + byte_offset: 12 + fieldset: CR4 + - name: SR1 + description: Power status register 1 + byte_offset: 16 + access: Read + fieldset: SR1 + - name: SR2 + description: Power status register 2 + byte_offset: 20 + access: Read + fieldset: SR2 + - name: SCR + description: Power status clear register + byte_offset: 24 + access: Write + fieldset: SCR + - name: PUCR + description: Power Port pull-up control register + array: + len: 6 + stride: 8 + byte_offset: 32 + fieldset: PCR + - name: PDCR + description: Power Port pull-down control register + array: + len: 6 + stride: 8 + byte_offset: 36 + fieldset: PCR fieldset/CR1: description: Power control register 1 fields: - - name: LPMS - description: Low-power mode selection - bit_offset: 0 - bit_size: 3 - - name: FPD_STOP - description: Flash memory powered down during Stop mode - bit_offset: 3 - bit_size: 1 - - name: FPD_LPRUN - description: Flash memory powered down during Low-power run mode - bit_offset: 4 - bit_size: 1 - - name: FPD_LPSLP - description: Flash memory powered down during Low-power sleep mode - bit_offset: 5 - bit_size: 1 - - name: DBP - description: Disable backup domain write protection - bit_offset: 8 - bit_size: 1 - - name: VOS - description: Voltage scaling range selection - bit_offset: 9 - bit_size: 2 - - name: LPR - description: Low-power run - bit_offset: 14 - bit_size: 1 + - name: LPMS + description: Low-power mode selection + bit_offset: 0 + bit_size: 3 + - name: FPD_STOP + description: Flash memory powered down during Stop mode + bit_offset: 3 + bit_size: 1 + - name: FPD_LPRUN + description: Flash memory powered down during Low-power run mode + bit_offset: 4 + bit_size: 1 + - name: FPD_LPSLP + description: Flash memory powered down during Low-power sleep mode + bit_offset: 5 + bit_size: 1 + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: VOS + description: Voltage scaling range selection + bit_offset: 9 + bit_size: 2 + enum: VOS + - name: LPR + description: Low-power run + bit_offset: 14 + bit_size: 1 fieldset/CR2: description: Power control register 2 fields: - - name: PVDE - description: Power voltage detector enable - bit_offset: 0 - bit_size: 1 - - name: PVDFT - description: Power voltage detector falling threshold selection - bit_offset: 1 - bit_size: 3 - - name: PVDRT - description: Power voltage detector rising threshold selection - bit_offset: 4 - bit_size: 3 + - name: PVDE + description: Power voltage detector enable + bit_offset: 0 + bit_size: 1 + - name: PVDFT + description: Power voltage detector falling threshold selection + bit_offset: 1 + bit_size: 3 + - name: PVDRT + description: Power voltage detector rising threshold selection + bit_offset: 4 + bit_size: 3 fieldset/CR3: description: Power control register 3 fields: - - name: EWUP - description: Enable Wakeup pin - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: RRS - description: SRAM retention in Standby mode - bit_offset: 8 - bit_size: 1 - - name: ULPEN - description: Enable the periodical sampling mode for PDR detection - bit_offset: 9 - bit_size: 1 - - name: APC - description: Apply pull-up and pull-down configuration - bit_offset: 10 - bit_size: 1 - - name: EIWUL - description: Enable internal wakeup line - bit_offset: 15 - bit_size: 1 + - name: EWUP + description: Enable Wakeup pin + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: RRS + description: SRAM retention in Standby mode + bit_offset: 8 + bit_size: 1 + - name: ULPEN + description: Enable the periodical sampling mode for PDR detection + bit_offset: 9 + bit_size: 1 + - name: APC + description: Apply pull-up and pull-down configuration + bit_offset: 10 + bit_size: 1 + - name: EIWUL + description: Enable internal wakeup line + bit_offset: 15 + bit_size: 1 fieldset/CR4: description: Power control register 4 fields: - - name: WP - description: Wakeup pin WKUP1 polarity - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: VBE - description: VBAT battery charging enable - bit_offset: 8 - bit_size: 1 - - name: VBRS - description: VBAT battery charging resistor selection - bit_offset: 9 - bit_size: 1 + - name: WP + description: Wakeup pin WKUP1 polarity + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: VBE + description: VBAT battery charging enable + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT battery charging resistor selection + bit_offset: 9 + bit_size: 1 fieldset/PCR: description: Power Port pull control register fields: - - name: P - description: Port pull bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 + - name: P + description: Port pull bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 fieldset/SCR: description: Power status clear register fields: - - name: CWUF - description: Clear Wakeup flag - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: CSBF - description: Clear standby flag - bit_offset: 8 - bit_size: 1 + - name: CWUF + description: Clear Wakeup flag + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: CSBF + description: Clear standby flag + bit_offset: 8 + bit_size: 1 fieldset/SR1: description: Power status register 1 fields: - - name: WUF - description: Wakeup flag - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: SBF - description: Standby flag - bit_offset: 8 - bit_size: 1 - - name: WUFI - description: Wakeup flag internal - bit_offset: 15 - bit_size: 1 + - name: WUF + description: Wakeup flag + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: SBF + description: Standby flag + bit_offset: 8 + bit_size: 1 + - name: WUFI + description: Wakeup flag internal + bit_offset: 15 + bit_size: 1 fieldset/SR2: description: Power status register 2 fields: - - name: FLASH_RDY - description: Flash ready flag - bit_offset: 7 - bit_size: 1 - - name: REGLPS - description: Low-power regulator started - bit_offset: 8 - bit_size: 1 - - name: REGLPF - description: Low-power regulator flag - bit_offset: 9 - bit_size: 1 - - name: VOSF - description: Voltage scaling flag - bit_offset: 10 - bit_size: 1 - - name: PVDO - description: Power voltage detector output - bit_offset: 11 - bit_size: 1 + - name: FLASH_RDY + description: Flash ready flag + bit_offset: 7 + bit_size: 1 + - name: REGLPS + description: Low-power regulator started + bit_offset: 8 + bit_size: 1 + - name: REGLPF + description: Low-power regulator flag + bit_offset: 9 + bit_size: 1 + - name: VOSF + description: Voltage scaling flag + bit_offset: 10 + bit_size: 1 + - name: PVDO + description: Power voltage detector output + bit_offset: 11 + bit_size: 1 +enum/VOS: + bit_size: 2 + variants: + - name: Range1 + value: 1 + - name: Range2 + value: 2 diff --git a/data/registers/pwr_g4.yaml b/data/registers/pwr_g4.yaml index f942f95..fbf8e5a 100644 --- a/data/registers/pwr_g4.yaml +++ b/data/registers/pwr_g4.yaml @@ -1,283 +1,290 @@ ---- block/PWR: description: Power control items: - - name: CR1 - description: Power control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Power control register 2 - byte_offset: 4 - fieldset: CR2 - - name: CR3 - description: Power control register 3 - byte_offset: 8 - fieldset: CR3 - - name: CR4 - description: Power control register 4 - byte_offset: 12 - fieldset: CR4 - - name: SR1 - description: Power status register 1 - byte_offset: 16 - access: Read - fieldset: SR1 - - name: SR2 - description: Power status register 2 - byte_offset: 20 - access: Read - fieldset: SR2 - - name: SCR - description: Power status clear register - byte_offset: 24 - access: Write - fieldset: SCR - - name: PUCR - description: Power Port pull-up control register - array: - len: 7 - stride: 8 - byte_offset: 32 - fieldset: PCR - - name: PDCR - description: Power Port pull-down control register - array: - len: 7 - stride: 8 - byte_offset: 36 - fieldset: PCR - - name: CR5 - description: Power control register 5 - byte_offset: 128 - fieldset: CR5 + - name: CR1 + description: Power control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Power control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: Power control register 3 + byte_offset: 8 + fieldset: CR3 + - name: CR4 + description: Power control register 4 + byte_offset: 12 + fieldset: CR4 + - name: SR1 + description: Power status register 1 + byte_offset: 16 + access: Read + fieldset: SR1 + - name: SR2 + description: Power status register 2 + byte_offset: 20 + access: Read + fieldset: SR2 + - name: SCR + description: Power status clear register + byte_offset: 24 + access: Write + fieldset: SCR + - name: PUCR + description: Power Port pull-up control register + array: + len: 7 + stride: 8 + byte_offset: 32 + fieldset: PCR + - name: PDCR + description: Power Port pull-down control register + array: + len: 7 + stride: 8 + byte_offset: 36 + fieldset: PCR + - name: CR5 + description: Power control register 5 + byte_offset: 128 + fieldset: CR5 fieldset/CR1: description: Power control register 1 fields: - - name: LPMS - description: Low-power mode selection - bit_offset: 0 - bit_size: 3 - - name: DBP - description: Disable backup domain write protection - bit_offset: 8 - bit_size: 1 - - name: VOS - description: Voltage scaling range selection - bit_offset: 9 - bit_size: 2 - - name: LPR - description: Low-power run - bit_offset: 14 - bit_size: 1 + - name: LPMS + description: Low-power mode selection + bit_offset: 0 + bit_size: 3 + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: VOS + description: Voltage scaling range selection + bit_offset: 9 + bit_size: 2 + enum: VOS + - name: LPR + description: Low-power run + bit_offset: 14 + bit_size: 1 fieldset/CR2: description: Power control register 2 fields: - - name: PVDE - description: Power voltage detector enable - bit_offset: 0 - bit_size: 1 - - name: PLS - description: Power voltage detector level selection - bit_offset: 1 - bit_size: 3 - - name: PVMEN1 - description: "Peripheral voltage monitoring 1 enable: VDDA vs. COMP min voltage" - bit_offset: 4 - bit_size: 1 - - name: PVMEN2 - description: "Peripheral voltage monitoring 2 enable: VDDA vs. Fast DAC min voltage" - bit_offset: 5 - bit_size: 1 - - name: PVMEN3 - description: "Peripheral voltage monitoring 3 enable: VDDA vs. ADC min voltage 1.62V" - bit_offset: 6 - bit_size: 1 - - name: PVMEN4 - description: "Peripheral voltage monitoring 4 enable: VDDA vs. OPAMP/DAC min voltage" - bit_offset: 7 - bit_size: 1 + - name: PVDE + description: Power voltage detector enable + bit_offset: 0 + bit_size: 1 + - name: PLS + description: Power voltage detector level selection + bit_offset: 1 + bit_size: 3 + - name: PVMEN1 + description: 'Peripheral voltage monitoring 1 enable: VDDA vs. COMP min voltage' + bit_offset: 4 + bit_size: 1 + - name: PVMEN2 + description: 'Peripheral voltage monitoring 2 enable: VDDA vs. Fast DAC min voltage' + bit_offset: 5 + bit_size: 1 + - name: PVMEN3 + description: 'Peripheral voltage monitoring 3 enable: VDDA vs. ADC min voltage 1.62V' + bit_offset: 6 + bit_size: 1 + - name: PVMEN4 + description: 'Peripheral voltage monitoring 4 enable: VDDA vs. OPAMP/DAC min voltage' + bit_offset: 7 + bit_size: 1 fieldset/CR3: description: Power control register 3 fields: - - name: EWUP1 - description: Enable Wakeup pin WKUP1 - bit_offset: 0 - bit_size: 1 - - name: EWUP2 - description: Enable Wakeup pin WKUP2 - bit_offset: 1 - bit_size: 1 - - name: EWUP3 - description: Enable Wakeup pin WKUP3 - bit_offset: 2 - bit_size: 1 - - name: EWUP4 - description: Enable Wakeup pin WKUP4 - bit_offset: 3 - bit_size: 1 - - name: EWUP5 - description: Enable Wakeup pin WKUP5 - bit_offset: 4 - bit_size: 1 - - name: RRS - description: SRAM2 retention in Standby mode - bit_offset: 8 - bit_size: 1 - - name: APC - description: Apply pull-up and pull-down configuration - bit_offset: 10 - bit_size: 1 - - name: UCPD1_STDBY - description: STDBY - bit_offset: 13 - bit_size: 1 - - name: UCPD1_DBDIS - description: DBDIS - bit_offset: 14 - bit_size: 1 - - name: EIWUL - description: Enable external WakeUp line - bit_offset: 15 - bit_size: 1 + - name: EWUP1 + description: Enable Wakeup pin WKUP1 + bit_offset: 0 + bit_size: 1 + - name: EWUP2 + description: Enable Wakeup pin WKUP2 + bit_offset: 1 + bit_size: 1 + - name: EWUP3 + description: Enable Wakeup pin WKUP3 + bit_offset: 2 + bit_size: 1 + - name: EWUP4 + description: Enable Wakeup pin WKUP4 + bit_offset: 3 + bit_size: 1 + - name: EWUP5 + description: Enable Wakeup pin WKUP5 + bit_offset: 4 + bit_size: 1 + - name: RRS + description: SRAM2 retention in Standby mode + bit_offset: 8 + bit_size: 1 + - name: APC + description: Apply pull-up and pull-down configuration + bit_offset: 10 + bit_size: 1 + - name: UCPD1_STDBY + description: STDBY + bit_offset: 13 + bit_size: 1 + - name: UCPD1_DBDIS + description: DBDIS + bit_offset: 14 + bit_size: 1 + - name: EIWUL + description: Enable external WakeUp line + bit_offset: 15 + bit_size: 1 fieldset/CR4: description: Power control register 4 fields: - - name: WP1 - description: Wakeup pin WKUP1 polarity - bit_offset: 0 - bit_size: 1 - - name: WP2 - description: Wakeup pin WKUP2 polarity - bit_offset: 1 - bit_size: 1 - - name: WP3 - description: Wakeup pin WKUP3 polarity - bit_offset: 2 - bit_size: 1 - - name: WP4 - description: Wakeup pin WKUP4 polarity - bit_offset: 3 - bit_size: 1 - - name: WP5 - description: Wakeup pin WKUP5 polarity - bit_offset: 4 - bit_size: 1 - - name: VBE - description: VBAT battery charging enable - bit_offset: 8 - bit_size: 1 - - name: VBRS - description: VBAT battery charging resistor selection - bit_offset: 9 - bit_size: 1 + - name: WP1 + description: Wakeup pin WKUP1 polarity + bit_offset: 0 + bit_size: 1 + - name: WP2 + description: Wakeup pin WKUP2 polarity + bit_offset: 1 + bit_size: 1 + - name: WP3 + description: Wakeup pin WKUP3 polarity + bit_offset: 2 + bit_size: 1 + - name: WP4 + description: Wakeup pin WKUP4 polarity + bit_offset: 3 + bit_size: 1 + - name: WP5 + description: Wakeup pin WKUP5 polarity + bit_offset: 4 + bit_size: 1 + - name: VBE + description: VBAT battery charging enable + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT battery charging resistor selection + bit_offset: 9 + bit_size: 1 fieldset/CR5: description: Power control register 5 fields: - - name: R1MODE - description: Main regular range 1 mode - bit_offset: 0 - bit_size: 1 + - name: R1MODE + description: Main regular range 1 mode + bit_offset: 0 + bit_size: 1 fieldset/PCR: description: Power Port pull control register fields: - - name: P - description: Port pull bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 + - name: P + description: Port pull bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 fieldset/SCR: description: Power status clear register fields: - - name: CWUF1 - description: Clear wakeup flag 1 - bit_offset: 0 - bit_size: 1 - - name: CWUF2 - description: Clear wakeup flag 2 - bit_offset: 1 - bit_size: 1 - - name: CWUF3 - description: Clear wakeup flag 3 - bit_offset: 2 - bit_size: 1 - - name: CWUF4 - description: Clear wakeup flag 4 - bit_offset: 3 - bit_size: 1 - - name: CWUF5 - description: Clear wakeup flag 5 - bit_offset: 4 - bit_size: 1 - - name: CSBF - description: Clear standby flag - bit_offset: 8 - bit_size: 1 + - name: CWUF1 + description: Clear wakeup flag 1 + bit_offset: 0 + bit_size: 1 + - name: CWUF2 + description: Clear wakeup flag 2 + bit_offset: 1 + bit_size: 1 + - name: CWUF3 + description: Clear wakeup flag 3 + bit_offset: 2 + bit_size: 1 + - name: CWUF4 + description: Clear wakeup flag 4 + bit_offset: 3 + bit_size: 1 + - name: CWUF5 + description: Clear wakeup flag 5 + bit_offset: 4 + bit_size: 1 + - name: CSBF + description: Clear standby flag + bit_offset: 8 + bit_size: 1 fieldset/SR1: description: Power status register 1 fields: - - name: WUF1 - description: Wakeup flag 1 - bit_offset: 0 - bit_size: 1 - - name: WUF2 - description: Wakeup flag 2 - bit_offset: 1 - bit_size: 1 - - name: WUF3 - description: Wakeup flag 3 - bit_offset: 2 - bit_size: 1 - - name: WUF4 - description: Wakeup flag 4 - bit_offset: 3 - bit_size: 1 - - name: WUF5 - description: Wakeup flag 5 - bit_offset: 4 - bit_size: 1 - - name: SBF - description: Standby flag - bit_offset: 8 - bit_size: 1 - - name: WUFI - description: Wakeup flag internal - bit_offset: 15 - bit_size: 1 + - name: WUF1 + description: Wakeup flag 1 + bit_offset: 0 + bit_size: 1 + - name: WUF2 + description: Wakeup flag 2 + bit_offset: 1 + bit_size: 1 + - name: WUF3 + description: Wakeup flag 3 + bit_offset: 2 + bit_size: 1 + - name: WUF4 + description: Wakeup flag 4 + bit_offset: 3 + bit_size: 1 + - name: WUF5 + description: Wakeup flag 5 + bit_offset: 4 + bit_size: 1 + - name: SBF + description: Standby flag + bit_offset: 8 + bit_size: 1 + - name: WUFI + description: Wakeup flag internal + bit_offset: 15 + bit_size: 1 fieldset/SR2: description: Power status register 2 fields: - - name: REGLPS - description: Low-power regulator started - bit_offset: 8 - bit_size: 1 - - name: REGLPF - description: Low-power regulator flag - bit_offset: 9 - bit_size: 1 - - name: VOSF - description: Voltage scaling flag - bit_offset: 10 - bit_size: 1 - - name: PVDO - description: Power voltage detector output - bit_offset: 11 - bit_size: 1 - - name: PVMO1 - description: "Peripheral voltage monitoring output: VDDUSB vs. 1.2 V" - bit_offset: 12 - bit_size: 1 - - name: PVMO2 - description: "Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V" - bit_offset: 13 - bit_size: 1 - - name: PVMO3 - description: "Peripheral voltage monitoring output: VDDA vs. 1.62 V" - bit_offset: 14 - bit_size: 1 - - name: PVMO4 - description: "Peripheral voltage monitoring output: VDDA vs. 2.2 V" - bit_offset: 15 - bit_size: 1 + - name: REGLPS + description: Low-power regulator started + bit_offset: 8 + bit_size: 1 + - name: REGLPF + description: Low-power regulator flag + bit_offset: 9 + bit_size: 1 + - name: VOSF + description: Voltage scaling flag + bit_offset: 10 + bit_size: 1 + - name: PVDO + description: Power voltage detector output + bit_offset: 11 + bit_size: 1 + - name: PVMO1 + description: 'Peripheral voltage monitoring output: VDDUSB vs. 1.2 V' + bit_offset: 12 + bit_size: 1 + - name: PVMO2 + description: 'Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V' + bit_offset: 13 + bit_size: 1 + - name: PVMO3 + description: 'Peripheral voltage monitoring output: VDDA vs. 1.62 V' + bit_offset: 14 + bit_size: 1 + - name: PVMO4 + description: 'Peripheral voltage monitoring output: VDDA vs. 2.2 V' + bit_offset: 15 + bit_size: 1 +enum/VOS: + bit_size: 2 + variants: + - name: Range1 + value: 1 + - name: Range2 + value: 2 diff --git a/data/registers/pwr_h5.yaml b/data/registers/pwr_h5.yaml index 66c1dec..5620f22 100644 --- a/data/registers/pwr_h5.yaml +++ b/data/registers/pwr_h5.yaml @@ -1,582 +1,581 @@ ---- block/PWR: description: Power control items: - - name: PMCR - description: PWR power mode control register - byte_offset: 0 - fieldset: PMCR - - name: PMSR - description: PWR status register - byte_offset: 4 - fieldset: PMSR - - name: VOSCR - description: PWR voltage scaling control register - byte_offset: 16 - fieldset: VOSCR - - name: VOSSR - description: PWR voltage scaling status register - byte_offset: 20 - fieldset: VOSSR - - name: BDCR - description: PWR Backup domain control register - byte_offset: 32 - fieldset: BDCR - - name: DBPCR - description: PWR Backup domain control register - byte_offset: 36 - fieldset: DBPCR - - name: BDSR - description: PWR Backup domain status register - byte_offset: 40 - fieldset: BDSR - - name: UCPDR - description: PWR USB Type-C power delivery register - byte_offset: 44 - fieldset: UCPDR - - name: SCCR - description: PWR supply configuration control register - byte_offset: 48 - fieldset: SCCR - - name: VMCR - description: PWR voltage monitor control register - byte_offset: 52 - fieldset: VMCR - - name: USBSCR - description: PWR USB supply control register - byte_offset: 56 - fieldset: USBSCR - - name: VMSR - description: PWR voltage monitor status register - byte_offset: 60 - fieldset: VMSR - - name: WUSCR - description: PWR wakeup status clear register - byte_offset: 64 - fieldset: WUSCR - - name: WUSR - description: PWR wakeup status register - byte_offset: 68 - fieldset: WUSR - - name: WUCR - description: PWR wakeup configuration register - byte_offset: 72 - fieldset: WUCR - - name: IORETR - description: PWR I/O retention register - byte_offset: 80 - fieldset: IORETR - - name: SECCFGR - description: PWR security configuration register - byte_offset: 256 - fieldset: SECCFGR - - name: PRIVCFGR - description: PWR privilege configuration register - byte_offset: 260 - fieldset: PRIVCFGR + - name: PMCR + description: PWR power mode control register + byte_offset: 0 + fieldset: PMCR + - name: PMSR + description: PWR status register + byte_offset: 4 + fieldset: PMSR + - name: VOSCR + description: PWR voltage scaling control register + byte_offset: 16 + fieldset: VOSCR + - name: VOSSR + description: PWR voltage scaling status register + byte_offset: 20 + fieldset: VOSSR + - name: BDCR + description: PWR Backup domain control register + byte_offset: 32 + fieldset: BDCR + - name: DBPCR + description: PWR Backup domain control register + byte_offset: 36 + fieldset: DBPCR + - name: BDSR + description: PWR Backup domain status register + byte_offset: 40 + fieldset: BDSR + - name: UCPDR + description: PWR USB Type-C power delivery register + byte_offset: 44 + fieldset: UCPDR + - name: SCCR + description: PWR supply configuration control register + byte_offset: 48 + fieldset: SCCR + - name: VMCR + description: PWR voltage monitor control register + byte_offset: 52 + fieldset: VMCR + - name: USBSCR + description: PWR USB supply control register + byte_offset: 56 + fieldset: USBSCR + - name: VMSR + description: PWR voltage monitor status register + byte_offset: 60 + fieldset: VMSR + - name: WUSCR + description: PWR wakeup status clear register + byte_offset: 64 + fieldset: WUSCR + - name: WUSR + description: PWR wakeup status register + byte_offset: 68 + fieldset: WUSR + - name: WUCR + description: PWR wakeup configuration register + byte_offset: 72 + fieldset: WUCR + - name: IORETR + description: PWR I/O retention register + byte_offset: 80 + fieldset: IORETR + - name: SECCFGR + description: PWR security configuration register + byte_offset: 256 + fieldset: SECCFGR + - name: PRIVCFGR + description: PWR privilege configuration register + byte_offset: 260 + fieldset: PRIVCFGR fieldset/BDCR: description: PWR Backup domain control register fields: - - name: BREN - description: "Backup RAM retention in Standby and VBAT modes\r When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled.\r If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in \tRun and Stop modes. However its content is lost in Standby and VBAT modes.\r If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and VBAT modes." - bit_offset: 0 - bit_size: 1 - - name: MONEN - description: Backup domain voltage and temperature monitoring enable - bit_offset: 1 - bit_size: 1 - - name: VBE - description: "VBAT charging enable\r Note: Reset only by POR,." - bit_offset: 8 - bit_size: 1 - - name: VBRS - description: VBAT charging resistor selection - bit_offset: 9 - bit_size: 1 - enum: VBRS + - name: BREN + description: "Backup RAM retention in Standby and VBAT modes\r When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled.\r If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in \tRun and Stop modes. However its content is lost in Standby and VBAT modes.\r If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and VBAT modes." + bit_offset: 0 + bit_size: 1 + - name: MONEN + description: Backup domain voltage and temperature monitoring enable + bit_offset: 1 + bit_size: 1 + - name: VBE + description: "VBAT charging enable\r Note: Reset only by POR,." + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT charging resistor selection + bit_offset: 9 + bit_size: 1 + enum: VBRS fieldset/BDSR: description: PWR Backup domain status register fields: - - name: BRRDY - description: "backup regulator ready\r This bit is set by hardware to indicate that the backup regulator is ready." - bit_offset: 16 - bit_size: 1 - - name: VBATL - description: VBAT level monitoring versus low threshold - bit_offset: 20 - bit_size: 1 - - name: VBATH - description: VBAT level monitoring versus high threshold - bit_offset: 21 - bit_size: 1 - - name: TEMPL - description: temperature level monitoring versus low threshold - bit_offset: 22 - bit_size: 1 - - name: TEMPH - description: temperature level monitoring versus high threshold - bit_offset: 23 - bit_size: 1 + - name: BRRDY + description: "backup regulator ready\r This bit is set by hardware to indicate that the backup regulator is ready." + bit_offset: 16 + bit_size: 1 + - name: VBATL + description: VBAT level monitoring versus low threshold + bit_offset: 20 + bit_size: 1 + - name: VBATH + description: VBAT level monitoring versus high threshold + bit_offset: 21 + bit_size: 1 + - name: TEMPL + description: temperature level monitoring versus low threshold + bit_offset: 22 + bit_size: 1 + - name: TEMPH + description: temperature level monitoring versus high threshold + bit_offset: 23 + bit_size: 1 fieldset/DBPCR: description: PWR Backup domain control register fields: - - name: DBP - description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write \taccess. This bit must be set to enable write access to these registers." - bit_offset: 0 - bit_size: 1 + - name: DBP + description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write \taccess. This bit must be set to enable write access to these registers." + bit_offset: 0 + bit_size: 1 fieldset/IORETR: description: PWR I/O retention register fields: - - name: IORETEN - description: "IO retention enable:\r When entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. \r Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register." - bit_offset: 0 - bit_size: 1 - - name: JTAGIORETEN - description: "IO retention enable for JTAG IOs\r when entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode" - bit_offset: 16 - bit_size: 1 + - name: IORETEN + description: "IO retention enable:\r When entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. \r Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register." + bit_offset: 0 + bit_size: 1 + - name: JTAGIORETEN + description: "IO retention enable for JTAG IOs\r when entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode" + bit_offset: 16 + bit_size: 1 fieldset/PMCR: description: PWR power mode control register fields: - - name: LPMS - description: "low-power mode selection\r This bit defines the Deepsleep mode." - bit_offset: 0 - bit_size: 1 - - name: SVOS - description: "system Stop mode voltage scaling selection\r These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance." - bit_offset: 2 - bit_size: 2 - enum: SVOS - - name: CSSF - description: "clear Standby and Stop flags (always read as 0)\r This bit is cleared to 0 by hardware." - bit_offset: 7 - bit_size: 1 - - name: FLPS - description: "Flash memory low-power mode in Stop mode\r This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode.\r When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode.\r Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode." - bit_offset: 9 - bit_size: 1 - - name: BOOSTE - description: "analog switch VBOOST control\r This bit enables the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The VDD supply voltage can be monitored through the PVD and the PLS bits." - bit_offset: 12 - bit_size: 1 - - name: AVD_READY - description: "analog voltage ready\r This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit).\r It must be set by software when the expected VDDA analog supply level is available.\r The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored \t(ALS bits)." - bit_offset: 13 - bit_size: 1 - - name: ETHERNETSO - description: ETHERNET RAM shut-off in Stop mode. - bit_offset: 16 - bit_size: 1 - - name: SRAM3SO - description: AHB SRAM3 shut-off in Stop mode. - bit_offset: 23 - bit_size: 1 - - name: SRAM2_16SO - description: AHB SRAM2 16-Kbyte shut-off in Stop mode. - bit_offset: 24 - bit_size: 1 - - name: SRAM2_48SO - description: AHB SRAM2 48-Kbyte shut-off in Stop mode. - bit_offset: 25 - bit_size: 1 - - name: SRAM1SO - description: AHB SRAM1 shut-off in Stop mode - bit_offset: 26 - bit_size: 1 + - name: LPMS + description: "low-power mode selection\r This bit defines the Deepsleep mode." + bit_offset: 0 + bit_size: 1 + - name: SVOS + description: "system Stop mode voltage scaling selection\r These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance." + bit_offset: 2 + bit_size: 2 + enum: SVOS + - name: CSSF + description: "clear Standby and Stop flags (always read as 0)\r This bit is cleared to 0 by hardware." + bit_offset: 7 + bit_size: 1 + - name: FLPS + description: "Flash memory low-power mode in Stop mode\r This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode.\r When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode.\r Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode." + bit_offset: 9 + bit_size: 1 + - name: BOOSTE + description: "analog switch VBOOST control\r This bit enables the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The VDD supply voltage can be monitored through the PVD and the PLS bits." + bit_offset: 12 + bit_size: 1 + - name: AVD_READY + description: "analog voltage ready\r This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit).\r It must be set by software when the expected VDDA analog supply level is available.\r The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored \t(ALS bits)." + bit_offset: 13 + bit_size: 1 + - name: ETHERNETSO + description: ETHERNET RAM shut-off in Stop mode. + bit_offset: 16 + bit_size: 1 + - name: SRAM3SO + description: AHB SRAM3 shut-off in Stop mode. + bit_offset: 23 + bit_size: 1 + - name: SRAM2_16SO + description: AHB SRAM2 16-Kbyte shut-off in Stop mode. + bit_offset: 24 + bit_size: 1 + - name: SRAM2_48SO + description: AHB SRAM2 48-Kbyte shut-off in Stop mode. + bit_offset: 25 + bit_size: 1 + - name: SRAM1SO + description: AHB SRAM1 shut-off in Stop mode + bit_offset: 26 + bit_size: 1 fieldset/PMSR: description: PWR status register fields: - - name: STOPF - description: "Stop flag\r This bit is set by hardware and cleared only by any reset or by setting the CSSF bit." - bit_offset: 5 - bit_size: 1 - - name: SBF - description: "System standby flag\r This bit is set by hardware and cleared only by a POR or by setting the CSSF bit." - bit_offset: 6 - bit_size: 1 + - name: STOPF + description: "Stop flag\r This bit is set by hardware and cleared only by any reset or by setting the CSSF bit." + bit_offset: 5 + bit_size: 1 + - name: SBF + description: "System standby flag\r This bit is set by hardware and cleared only by a POR or by setting the CSSF bit." + bit_offset: 6 + bit_size: 1 fieldset/PRIVCFGR: description: PWR privilege configuration register fields: - - name: SPRIV - description: "PWR secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access." - bit_offset: 0 - bit_size: 1 - enum: PRIV - - name: NSPRIV - description: "PWR non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure." - bit_offset: 1 - bit_size: 1 - enum: PRIV + - name: SPRIV + description: "PWR secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access." + bit_offset: 0 + bit_size: 1 + enum: PRIV + - name: NSPRIV + description: "PWR non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure." + bit_offset: 1 + bit_size: 1 + enum: PRIV fieldset/SCCR: description: PWR supply configuration control register fields: - - name: BYPASS - description: power management unit bypass - bit_offset: 0 - bit_size: 1 - - name: LDOEN - description: "LDO enable \r The value is set by hardware when the package uses the LDO regulator." - bit_offset: 8 - bit_size: 1 - - name: SMPSEN - description: "SMPS enable \r The value is set by hardware when the package uses the SMPS regulator." - bit_offset: 9 - bit_size: 1 + - name: BYPASS + description: power management unit bypass + bit_offset: 0 + bit_size: 1 + - name: LDOEN + description: "LDO enable \r The value is set by hardware when the package uses the LDO regulator." + bit_offset: 8 + bit_size: 1 + - name: SMPSEN + description: "SMPS enable \r The value is set by hardware when the package uses the SMPS regulator." + bit_offset: 9 + bit_size: 1 fieldset/SECCFGR: description: PWR security configuration register fields: - - name: WUP1SEC - description: WUPx secure protection - bit_offset: 0 - bit_size: 1 - enum: SEC - - name: WUP2SEC - description: WUPx secure protection - bit_offset: 1 - bit_size: 1 - enum: SEC - - name: WUP3SEC - description: WUPx secure protection - bit_offset: 2 - bit_size: 1 - enum: SEC - - name: WUP4SEC - description: WUPx secure protection - bit_offset: 3 - bit_size: 1 - enum: SEC - - name: WUP5SEC - description: WUPx secure protection - bit_offset: 4 - bit_size: 1 - enum: SEC - - name: WUP6SEC - description: WUPx secure protection - bit_offset: 5 - bit_size: 1 - enum: SEC - - name: WUP7SEC - description: WUPx secure protection - bit_offset: 6 - bit_size: 1 - enum: SEC - - name: WUP8SEC - description: WUPx secure protection - bit_offset: 7 - bit_size: 1 - enum: SEC - - name: RETSEC - description: retention secure protection - bit_offset: 11 - bit_size: 1 - enum: SEC - - name: LPMSEC - description: low-power modes secure protection - bit_offset: 12 - bit_size: 1 - enum: SEC - - name: SCMSEC - description: supply configuration and monitoring secure protection. - bit_offset: 13 - bit_size: 1 - enum: SEC - - name: VBSEC - description: backup domain secure protection - bit_offset: 14 - bit_size: 1 - enum: SEC - - name: VUSBSEC - description: voltage USB secure protection - bit_offset: 15 - bit_size: 1 - enum: SEC + - name: WUP1SEC + description: WUPx secure protection + bit_offset: 0 + bit_size: 1 + enum: SEC + - name: WUP2SEC + description: WUPx secure protection + bit_offset: 1 + bit_size: 1 + enum: SEC + - name: WUP3SEC + description: WUPx secure protection + bit_offset: 2 + bit_size: 1 + enum: SEC + - name: WUP4SEC + description: WUPx secure protection + bit_offset: 3 + bit_size: 1 + enum: SEC + - name: WUP5SEC + description: WUPx secure protection + bit_offset: 4 + bit_size: 1 + enum: SEC + - name: WUP6SEC + description: WUPx secure protection + bit_offset: 5 + bit_size: 1 + enum: SEC + - name: WUP7SEC + description: WUPx secure protection + bit_offset: 6 + bit_size: 1 + enum: SEC + - name: WUP8SEC + description: WUPx secure protection + bit_offset: 7 + bit_size: 1 + enum: SEC + - name: RETSEC + description: retention secure protection + bit_offset: 11 + bit_size: 1 + enum: SEC + - name: LPMSEC + description: low-power modes secure protection + bit_offset: 12 + bit_size: 1 + enum: SEC + - name: SCMSEC + description: supply configuration and monitoring secure protection. + bit_offset: 13 + bit_size: 1 + enum: SEC + - name: VBSEC + description: backup domain secure protection + bit_offset: 14 + bit_size: 1 + enum: SEC + - name: VUSBSEC + description: voltage USB secure protection + bit_offset: 15 + bit_size: 1 + enum: SEC fieldset/UCPDR: description: PWR USB Type-C power delivery register fields: - - name: UCPD_DBDIS - description: "USB Type-C and power delivery dead battery disable\r After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all case, either to stop this pull-down or to hand over control to the UCPD (which should therefore be initialized before doing the disable)." - bit_offset: 0 - bit_size: 1 - - name: UCPD_STBY - description: "USB Type-c and Power delivery Standby mode\r When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD, and it must be written to 0 after exiting the standby mode and before writing any UCPD register." - bit_offset: 1 - bit_size: 1 + - name: UCPD_DBDIS + description: "USB Type-C and power delivery dead battery disable\r After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all case, either to stop this pull-down or to hand over control to the UCPD (which should therefore be initialized before doing the disable)." + bit_offset: 0 + bit_size: 1 + - name: UCPD_STBY + description: "USB Type-c and Power delivery Standby mode\r When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD, and it must be written to 0 after exiting the standby mode and before writing any UCPD register." + bit_offset: 1 + bit_size: 1 fieldset/USBSCR: description: PWR USB supply control register fields: - - name: USB33DEN - description: VDDUSB voltage level detector enable - bit_offset: 24 - bit_size: 1 - - name: USB33SV - description: "independent USB supply valid\r This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USBFS peripheral. If VDDUSB is not always present in the application, the VDDUSB voltage monitor can be used to determine whether this supply is ready or not." - bit_offset: 25 - bit_size: 1 + - name: USB33DEN + description: VDDUSB voltage level detector enable + bit_offset: 24 + bit_size: 1 + - name: USB33SV + description: "independent USB supply valid\r This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USBFS peripheral. If VDDUSB is not always present in the application, the VDDUSB voltage monitor can be used to determine whether this supply is ready or not." + bit_offset: 25 + bit_size: 1 fieldset/VMCR: description: PWR voltage monitor control register fields: - - name: PVDE - description: PVD enable - bit_offset: 0 - bit_size: 1 - - name: PLS - description: "programmable voltage detector (PVD) level selection\r These bits select the voltage threshold detected by the PVD." - bit_offset: 1 - bit_size: 3 - enum: PLS - - name: AVDEN - description: peripheral voltage monitor on VDDA enable - bit_offset: 8 - bit_size: 1 - - name: ALS - description: "analog voltage detector (AVD) level selection\r These bits select the voltage threshold detected by the AVD." - bit_offset: 9 - bit_size: 2 - enum: ALS + - name: PVDE + description: PVD enable + bit_offset: 0 + bit_size: 1 + - name: PLS + description: "programmable voltage detector (PVD) level selection\r These bits select the voltage threshold detected by the PVD." + bit_offset: 1 + bit_size: 3 + enum: PLS + - name: AVDEN + description: peripheral voltage monitor on VDDA enable + bit_offset: 8 + bit_size: 1 + - name: ALS + description: "analog voltage detector (AVD) level selection\r These bits select the voltage threshold detected by the AVD." + bit_offset: 9 + bit_size: 2 + enum: ALS fieldset/VMSR: description: PWR voltage monitor status register fields: - - name: AVDO - description: "analog voltage detector output on VDDA\r This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit.\r Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set." - bit_offset: 19 - bit_size: 1 - enum: AVDO - - name: VDDIO2RDY - description: "voltage detector output on VDDIO2\r This bit is set and cleared by hardware." - bit_offset: 20 - bit_size: 1 - - name: PVDO - description: "programmable voltage detect output\r This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit.\r Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set." - bit_offset: 22 - bit_size: 1 - enum: PVDO - - name: USB33RDY - description: VDDUSB ready - bit_offset: 24 - bit_size: 1 + - name: AVDO + description: "analog voltage detector output on VDDA\r This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit.\r Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set." + bit_offset: 19 + bit_size: 1 + enum: AVDO + - name: VDDIO2RDY + description: "voltage detector output on VDDIO2\r This bit is set and cleared by hardware." + bit_offset: 20 + bit_size: 1 + - name: PVDO + description: "programmable voltage detect output\r This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit.\r Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set." + bit_offset: 22 + bit_size: 1 + enum: PVDO + - name: USB33RDY + description: VDDUSB ready + bit_offset: 24 + bit_size: 1 fieldset/VOSCR: description: PWR voltage scaling control register fields: - - name: VOS - description: "voltage scaling selection according to performance\r These bits control the VCORE voltage level and allow to obtain the best trade-off between power consumption and performance:\r - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance.\r - When increasing the performance, the voltage scaling must be changed before increasing the system frequency.\r - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling." - bit_offset: 4 - bit_size: 2 - enum: VOS + - name: VOS + description: "voltage scaling selection according to performance\r These bits control the VCORE voltage level and allow to obtain the best trade-off between power consumption and performance:\r - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance.\r - When increasing the performance, the voltage scaling must be changed before increasing the system frequency.\r - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling." + bit_offset: 4 + bit_size: 2 + enum: VOS fieldset/VOSSR: description: PWR voltage scaling status register fields: - - name: VOSRDY - description: Ready bit for VCORE voltage scaling output selection. - bit_offset: 3 - bit_size: 1 - - name: ACTVOSRDY - description: Voltage level ready for currently used VOS - bit_offset: 13 - bit_size: 1 - - name: ACTVOS - description: "voltage output scaling currently applied to VCORE\r This field provides the last VOS value." - bit_offset: 14 - bit_size: 2 - enum: ACTVOS + - name: VOSRDY + description: Ready bit for VCORE voltage scaling output selection. + bit_offset: 3 + bit_size: 1 + - name: ACTVOSRDY + description: Voltage level ready for currently used VOS + bit_offset: 13 + bit_size: 1 + - name: ACTVOS + description: "voltage output scaling currently applied to VCORE\r This field provides the last VOS value." + bit_offset: 14 + bit_size: 2 + enum: ACTVOS fieldset/WUCR: description: PWR wakeup configuration register fields: - - name: WUPEN - description: "enable wakeup pin WUPx\r These bits are set and cleared by software.\r Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge." - bit_offset: 0 - bit_size: 1 - array: - len: 8 - stride: 1 - - name: WUPP - description: "wakeup pin polarity bit for WUPx\r These bits define the polarity used for event detection on WUPx external wakeup pin." - bit_offset: 8 - bit_size: 1 - array: - len: 8 - stride: 1 - enum: WUPP - - name: WUPPUPD - description: "wakeup pin pull configuration for WKUPx\r These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode." - bit_offset: 16 - bit_size: 2 - array: - len: 8 - stride: 2 - enum: WUPPUPD + - name: WUPEN + description: "enable wakeup pin WUPx\r These bits are set and cleared by software.\r Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge." + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 + - name: WUPP + description: "wakeup pin polarity bit for WUPx\r These bits define the polarity used for event detection on WUPx external wakeup pin." + bit_offset: 8 + bit_size: 1 + array: + len: 8 + stride: 1 + enum: WUPP + - name: WUPPUPD + description: "wakeup pin pull configuration for WKUPx\r These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode." + bit_offset: 16 + bit_size: 2 + array: + len: 8 + stride: 2 + enum: WUPPUPD fieldset/WUSCR: description: PWR wakeup status clear register fields: - - name: CWUF - description: "clear wakeup pin flag for WUFx\r These bits are always read as 0." - bit_offset: 0 - bit_size: 1 - array: - len: 8 - stride: 1 + - name: CWUF + description: "clear wakeup pin flag for WUFx\r These bits are always read as 0." + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 fieldset/WUSR: description: PWR wakeup status register fields: - - name: WUF - description: "wakeup pin WUFx flag\r This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register." - bit_offset: 0 - bit_size: 1 - array: - len: 8 - stride: 1 + - name: WUF + description: "wakeup pin WUFx flag\r This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register." + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 enum/ACTVOS: bit_size: 2 variants: - - name: B_0x0 - description: VOS3 (lowest power) - value: 0 - - name: B_0x1 - description: VOS2 - value: 1 - - name: B_0x2 - description: VOS1 - value: 2 - - name: B_0x3 - description: VOS0 (highest frequency) - value: 3 + - name: B_0x0 + description: VOS3 (lowest power) + value: 0 + - name: B_0x1 + description: VOS2 + value: 1 + - name: B_0x2 + description: VOS1 + value: 2 + - name: B_0x3 + description: VOS0 (highest frequency) + value: 3 enum/ALS: bit_size: 2 variants: - - name: B_0x0 - description: 1.7 V - value: 0 - - name: B_0x1 - description: 2.1 V - value: 1 - - name: B_0x2 - description: 2.5 V - value: 2 - - name: B_0x3 - description: 2.8 V - value: 3 + - name: B_0x0 + description: 1.7 V + value: 0 + - name: B_0x1 + description: 2.1 V + value: 1 + - name: B_0x2 + description: 2.5 V + value: 2 + - name: B_0x3 + description: 2.8 V + value: 3 enum/AVDO: bit_size: 1 variants: - - name: B_0x0 - description: "VDDA is equal or higher than the AVD threshold selected with the ALS[2:0] bits." - value: 0 - - name: B_0x1 - description: "VDDA is lower than the AVD threshold selected with the ALS[2:0] bits." - value: 1 + - name: B_0x0 + description: VDDA is equal or higher than the AVD threshold selected with the ALS[2:0] bits. + value: 0 + - name: B_0x1 + description: VDDA is lower than the AVD threshold selected with the ALS[2:0] bits. + value: 1 enum/PLS: bit_size: 3 variants: - - name: B_0x0 - description: 1.95 V - value: 0 - - name: B_0x1 - description: 2.1 V - value: 1 - - name: B_0x2 - description: 2.25 V - value: 2 - - name: B_0x3 - description: 2.4 V - value: 3 - - name: B_0x4 - description: 2.55 V - value: 4 - - name: B_0x5 - description: 2.7 V - value: 5 - - name: B_0x6 - description: 2.85 V - value: 6 - - name: B_0x7 - description: PVD_IN pin - value: 7 + - name: B_0x0 + description: 1.95 V + value: 0 + - name: B_0x1 + description: 2.1 V + value: 1 + - name: B_0x2 + description: 2.25 V + value: 2 + - name: B_0x3 + description: 2.4 V + value: 3 + - name: B_0x4 + description: 2.55 V + value: 4 + - name: B_0x5 + description: 2.7 V + value: 5 + - name: B_0x6 + description: 2.85 V + value: 6 + - name: B_0x7 + description: PVD_IN pin + value: 7 enum/PRIV: bit_size: 1 variants: - - name: B_0x0 - description: Read and write to PWR secure functions can be done by privileged or unprivileged access. - value: 0 - - name: B_0x1 - description: Read and write to PWR secure functions can be done by privileged access only. - value: 1 + - name: B_0x0 + description: Read and write to PWR secure functions can be done by privileged or unprivileged access. + value: 0 + - name: B_0x1 + description: Read and write to PWR secure functions can be done by privileged access only. + value: 1 enum/PVDO: bit_size: 1 variants: - - name: B_0x0 - description: "VDD is equal or higher than the PVD threshold selected through the PLS[2:0] bits." - value: 0 - - name: B_0x1 - description: "VDD is lower than the PVD threshold selected through the PLS[2:0] bits." - value: 1 + - name: B_0x0 + description: VDD is equal or higher than the PVD threshold selected through the PLS[2:0] bits. + value: 0 + - name: B_0x1 + description: VDD is lower than the PVD threshold selected through the PLS[2:0] bits. + value: 1 enum/SEC: bit_size: 1 variants: - - name: B_0x0 - description: PWR_SCCR and PWR_VMCR can be read and written with secure or non-secure access. - value: 0 - - name: B_0x1 - description: PWR_SCCR and PWR_VMCR can be read and written only with secure access. - value: 1 + - name: B_0x0 + description: PWR_SCCR and PWR_VMCR can be read and written with secure or non-secure access. + value: 0 + - name: B_0x1 + description: PWR_SCCR and PWR_VMCR can be read and written only with secure access. + value: 1 enum/SVOS: bit_size: 2 variants: - - name: B_0x0 - description: reserved - value: 0 - - name: B_0x1 - description: SVOS5 scale 5 - value: 1 - - name: B_0x2 - description: SVOS4 scale 4 - value: 2 - - name: B_0x3 - description: SVOS3 scale 3 (default). - value: 3 + - name: B_0x0 + description: reserved + value: 0 + - name: B_0x1 + description: SVOS5 scale 5 + value: 1 + - name: B_0x2 + description: SVOS4 scale 4 + value: 2 + - name: B_0x3 + description: SVOS3 scale 3 (default). + value: 3 enum/VBRS: bit_size: 1 variants: - - name: B_0x0 - description: Charge VBAT through a 5 kΩ resistor. - value: 0 - - name: B_0x1 - description: Charge VBAT through a 1.5 kΩ resistor. - value: 1 + - name: B_0x0 + description: Charge VBAT through a 5 kΩ resistor. + value: 0 + - name: B_0x1 + description: Charge VBAT through a 1.5 kΩ resistor. + value: 1 enum/VOS: bit_size: 2 variants: - - name: Scale3 - description: scale 3 (default) - value: 0 - - name: Scale2 - description: scale 2 - value: 1 - - name: Scale1 - description: scale 1 - value: 2 - - name: Scale0 - description: scale 0 - value: 3 + - name: Scale3 + description: scale 3 (default) + value: 0 + - name: Scale2 + description: scale 2 + value: 1 + - name: Scale1 + description: scale 1 + value: 2 + - name: Scale0 + description: scale 0 + value: 3 enum/WUPP: bit_size: 1 variants: - - name: B_0x0 - description: detection on high level (rising edge) - value: 0 - - name: B_0x1 - description: detection on low level (falling edge) - value: 1 + - name: B_0x0 + description: detection on high level (rising edge) + value: 0 + - name: B_0x1 + description: detection on low level (falling edge) + value: 1 enum/WUPPUPD: bit_size: 2 variants: - - name: B_0x0 - description: no pull-up - value: 0 - - name: B_0x1 - description: pull-up - value: 1 - - name: B_0x2 - description: pull-down - value: 2 - - name: B_0x3 - description: reserved - value: 3 + - name: B_0x0 + description: no pull-up + value: 0 + - name: B_0x1 + description: pull-up + value: 1 + - name: B_0x2 + description: pull-down + value: 2 + - name: B_0x3 + description: reserved + value: 3 diff --git a/data/registers/pwr_h50.yaml b/data/registers/pwr_h50.yaml index 932e941..9b3949c 100644 --- a/data/registers/pwr_h50.yaml +++ b/data/registers/pwr_h50.yaml @@ -1,446 +1,445 @@ ---- block/PWR: description: Power control items: - - name: PMCR - description: PWR power mode control register - byte_offset: 0 - fieldset: PMCR - - name: PMSR - description: PWR status register - byte_offset: 4 - fieldset: PMSR - - name: VOSCR - description: PWR voltage scaling control register - byte_offset: 16 - fieldset: VOSCR - - name: VOSSR - description: PWR voltage scaling status register - byte_offset: 20 - fieldset: VOSSR - - name: BDCR - description: PWR Backup domain control register - byte_offset: 32 - fieldset: BDCR - - name: DBPCR - description: PWR disable backup protection control register - byte_offset: 36 - fieldset: DBPCR - - name: BDSR - description: PWR Backup domain status register - byte_offset: 40 - fieldset: BDSR - - name: SCCR - description: PWR supply configuration control register - byte_offset: 48 - fieldset: SCCR - - name: VMCR - description: PWR voltage monitor control register - byte_offset: 52 - fieldset: VMCR - - name: VMSR - description: PWR voltage monitor status register - byte_offset: 60 - fieldset: VMSR - - name: WUSCR - description: PWR wakeup status clear register - byte_offset: 64 - fieldset: WUSCR - - name: WUSR - description: PWR wakeup status register - byte_offset: 68 - fieldset: WUSR - - name: WUCR - description: PWR wakeup configuration register - byte_offset: 72 - fieldset: WUCR - - name: IORETR - description: PWR I/O retention register - byte_offset: 80 - fieldset: IORETR - - name: PRIVCFGR - description: PWR privilege configuration register - byte_offset: 260 - fieldset: PRIVCFGR + - name: PMCR + description: PWR power mode control register + byte_offset: 0 + fieldset: PMCR + - name: PMSR + description: PWR status register + byte_offset: 4 + fieldset: PMSR + - name: VOSCR + description: PWR voltage scaling control register + byte_offset: 16 + fieldset: VOSCR + - name: VOSSR + description: PWR voltage scaling status register + byte_offset: 20 + fieldset: VOSSR + - name: BDCR + description: PWR Backup domain control register + byte_offset: 32 + fieldset: BDCR + - name: DBPCR + description: PWR disable backup protection control register + byte_offset: 36 + fieldset: DBPCR + - name: BDSR + description: PWR Backup domain status register + byte_offset: 40 + fieldset: BDSR + - name: SCCR + description: PWR supply configuration control register + byte_offset: 48 + fieldset: SCCR + - name: VMCR + description: PWR voltage monitor control register + byte_offset: 52 + fieldset: VMCR + - name: VMSR + description: PWR voltage monitor status register + byte_offset: 60 + fieldset: VMSR + - name: WUSCR + description: PWR wakeup status clear register + byte_offset: 64 + fieldset: WUSCR + - name: WUSR + description: PWR wakeup status register + byte_offset: 68 + fieldset: WUSR + - name: WUCR + description: PWR wakeup configuration register + byte_offset: 72 + fieldset: WUCR + - name: IORETR + description: PWR I/O retention register + byte_offset: 80 + fieldset: IORETR + - name: PRIVCFGR + description: PWR privilege configuration register + byte_offset: 260 + fieldset: PRIVCFGR fieldset/BDCR: description: PWR Backup domain control register fields: - - name: BREN - description: "Backup RAM retention in Standby and VBAT modes\r When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled.\r If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in \tRun and Stop modes. However its content is lost in Standby and VBAT modes.\r If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and VBAT modes." - bit_offset: 0 - bit_size: 1 - - name: MONEN - description: Backup domain voltage and temperature monitoring enable - bit_offset: 1 - bit_size: 1 - - name: VBE - description: "VBAT charging enable\r Note: Reset only by POR,." - bit_offset: 8 - bit_size: 1 - - name: VBRS - description: VBAT charging resistor selection - bit_offset: 9 - bit_size: 1 - enum: VBRS + - name: BREN + description: "Backup RAM retention in Standby and VBAT modes\r When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled.\r If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in \tRun and Stop modes. However its content is lost in Standby and VBAT modes.\r If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and VBAT modes." + bit_offset: 0 + bit_size: 1 + - name: MONEN + description: Backup domain voltage and temperature monitoring enable + bit_offset: 1 + bit_size: 1 + - name: VBE + description: "VBAT charging enable\r Note: Reset only by POR,." + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT charging resistor selection + bit_offset: 9 + bit_size: 1 + enum: VBRS fieldset/BDSR: description: PWR Backup domain status register fields: - - name: BRRDY - description: "backup regulator ready\r This bit is set by hardware to indicate that the backup regulator is ready." - bit_offset: 16 - bit_size: 1 - - name: VBATL - description: VBAT level monitoring versus low threshold - bit_offset: 20 - bit_size: 1 - - name: VBATH - description: VBAT level monitoring versus high threshold - bit_offset: 21 - bit_size: 1 - - name: TEMPL - description: temperature level monitoring versus low threshold - bit_offset: 22 - bit_size: 1 - - name: TEMPH - description: temperature level monitoring versus high threshold - bit_offset: 23 - bit_size: 1 + - name: BRRDY + description: "backup regulator ready\r This bit is set by hardware to indicate that the backup regulator is ready." + bit_offset: 16 + bit_size: 1 + - name: VBATL + description: VBAT level monitoring versus low threshold + bit_offset: 20 + bit_size: 1 + - name: VBATH + description: VBAT level monitoring versus high threshold + bit_offset: 21 + bit_size: 1 + - name: TEMPL + description: temperature level monitoring versus low threshold + bit_offset: 22 + bit_size: 1 + - name: TEMPH + description: temperature level monitoring versus high threshold + bit_offset: 23 + bit_size: 1 fieldset/DBPCR: description: PWR disable backup protection control register fields: - - name: DBP - description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write \taccess. This bit must be set to enable write access to these registers." - bit_offset: 0 - bit_size: 1 + - name: DBP + description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write \taccess. This bit must be set to enable write access to these registers." + bit_offset: 0 + bit_size: 1 fieldset/IORETR: description: PWR I/O retention register fields: - - name: IORETEN - description: "IO retention enable:\r When entering into standby mode, the output is sampled, and applied to the output IO during the standby power mode. \r Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register." - bit_offset: 0 - bit_size: 1 - - name: JTAGIORETEN - description: "IO retention enable for JTAG IOs\r when entering into standby mode, the output is sampled, and applied to the output IO during the standby power mode" - bit_offset: 16 - bit_size: 1 + - name: IORETEN + description: "IO retention enable:\r When entering into standby mode, the output is sampled, and applied to the output IO during the standby power mode. \r Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register." + bit_offset: 0 + bit_size: 1 + - name: JTAGIORETEN + description: "IO retention enable for JTAG IOs\r when entering into standby mode, the output is sampled, and applied to the output IO during the standby power mode" + bit_offset: 16 + bit_size: 1 fieldset/PMCR: description: PWR power mode control register fields: - - name: LPMS - description: "low-power mode selection\r This bit defines the Deepsleep mode." - bit_offset: 0 - bit_size: 1 - - name: SVOS - description: "system Stop mode voltage scaling selection\r These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance." - bit_offset: 2 - bit_size: 2 - enum: SVOS - - name: CSSF - description: "clear Standby and Stop flags (always read as 0)\r This bit is cleared to 0 by hardware." - bit_offset: 7 - bit_size: 1 - - name: FLPS - description: "Flash memory low-power mode in Stop mode\r This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode.\r When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode.\r Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode." - bit_offset: 9 - bit_size: 1 - - name: BOOSTE - description: "analog switch VBOOST control\r This bit enables the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The VDD supply voltage can be monitored through the PVD and the PLS bits." - bit_offset: 12 - bit_size: 1 - - name: AVD_READY - description: "analog voltage ready\r This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit).\r It must be set by software when the expected VDDA analog supply level is available.\r The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored \t(ALS bits)." - bit_offset: 13 - bit_size: 1 - - name: SRAM2SO - description: AHB SRAM2 shut-off in Stop mode. - bit_offset: 25 - bit_size: 1 - - name: SRAM1SO - description: AHB SRAM1 shut-off in Stop mode - bit_offset: 26 - bit_size: 1 + - name: LPMS + description: "low-power mode selection\r This bit defines the Deepsleep mode." + bit_offset: 0 + bit_size: 1 + - name: SVOS + description: "system Stop mode voltage scaling selection\r These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance." + bit_offset: 2 + bit_size: 2 + enum: SVOS + - name: CSSF + description: "clear Standby and Stop flags (always read as 0)\r This bit is cleared to 0 by hardware." + bit_offset: 7 + bit_size: 1 + - name: FLPS + description: "Flash memory low-power mode in Stop mode\r This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode.\r When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode.\r Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode." + bit_offset: 9 + bit_size: 1 + - name: BOOSTE + description: "analog switch VBOOST control\r This bit enables the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The VDD supply voltage can be monitored through the PVD and the PLS bits." + bit_offset: 12 + bit_size: 1 + - name: AVD_READY + description: "analog voltage ready\r This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit).\r It must be set by software when the expected VDDA analog supply level is available.\r The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored \t(ALS bits)." + bit_offset: 13 + bit_size: 1 + - name: SRAM2SO + description: AHB SRAM2 shut-off in Stop mode. + bit_offset: 25 + bit_size: 1 + - name: SRAM1SO + description: AHB SRAM1 shut-off in Stop mode + bit_offset: 26 + bit_size: 1 fieldset/PMSR: description: PWR status register fields: - - name: STOPF - description: "Stop flag\r This bit is set by hardware and cleared only by any reset or by setting the CSSF bit." - bit_offset: 5 - bit_size: 1 - - name: SBF - description: "System standby flag\r This bit is set by hardware and cleared only by a POR or by setting the CSSF bit." - bit_offset: 6 - bit_size: 1 + - name: STOPF + description: "Stop flag\r This bit is set by hardware and cleared only by any reset or by setting the CSSF bit." + bit_offset: 5 + bit_size: 1 + - name: SBF + description: "System standby flag\r This bit is set by hardware and cleared only by a POR or by setting the CSSF bit." + bit_offset: 6 + bit_size: 1 fieldset/PRIVCFGR: description: PWR privilege configuration register fields: - - name: NSPRIV - description: "PWR functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access." - bit_offset: 1 - bit_size: 1 - enum: PRIV + - name: NSPRIV + description: "PWR functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access." + bit_offset: 1 + bit_size: 1 + enum: PRIV fieldset/SCCR: description: PWR supply configuration control register fields: - - name: BYPASS - description: power management unit bypass - bit_offset: 0 - bit_size: 1 - - name: LDOEN - description: "LDO enable \r The value is set by hardware when the package uses the LDO regulator." - bit_offset: 8 - bit_size: 1 + - name: BYPASS + description: power management unit bypass + bit_offset: 0 + bit_size: 1 + - name: LDOEN + description: "LDO enable \r The value is set by hardware when the package uses the LDO regulator." + bit_offset: 8 + bit_size: 1 fieldset/VMCR: description: PWR voltage monitor control register fields: - - name: PVDE - description: PVD enable - bit_offset: 0 - bit_size: 1 - - name: PLS - description: "programmable voltage detector (PVD) level selection\r These bits select the voltage threshold detected by the PVD." - bit_offset: 1 - bit_size: 3 - enum: PLS - - name: AVDEN - description: peripheral voltage monitor on VDDA enable - bit_offset: 8 - bit_size: 1 - - name: ALS - description: "analog voltage detector (AVD) level selection\r These bits select the voltage threshold detected by the AVD." - bit_offset: 9 - bit_size: 2 - enum: ALS + - name: PVDE + description: PVD enable + bit_offset: 0 + bit_size: 1 + - name: PLS + description: "programmable voltage detector (PVD) level selection\r These bits select the voltage threshold detected by the PVD." + bit_offset: 1 + bit_size: 3 + enum: PLS + - name: AVDEN + description: peripheral voltage monitor on VDDA enable + bit_offset: 8 + bit_size: 1 + - name: ALS + description: "analog voltage detector (AVD) level selection\r These bits select the voltage threshold detected by the AVD." + bit_offset: 9 + bit_size: 2 + enum: ALS fieldset/VMSR: description: PWR voltage monitor status register fields: - - name: AVDO - description: "analog voltage detector output on VDDA\r This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit.\r Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set." - bit_offset: 19 - bit_size: 1 - enum: AVDO - - name: VDDIO2RDY - description: "voltage detector output on VDDIO2\r This bit is set and cleared by hardware." - bit_offset: 20 - bit_size: 1 - - name: PVDO - description: "programmable voltage detect output\r This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit.\r Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set." - bit_offset: 22 - bit_size: 1 - enum: PVDO + - name: AVDO + description: "analog voltage detector output on VDDA\r This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit.\r Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set." + bit_offset: 19 + bit_size: 1 + enum: AVDO + - name: VDDIO2RDY + description: "voltage detector output on VDDIO2\r This bit is set and cleared by hardware." + bit_offset: 20 + bit_size: 1 + - name: PVDO + description: "programmable voltage detect output\r This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit.\r Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set." + bit_offset: 22 + bit_size: 1 + enum: PVDO fieldset/VOSCR: description: PWR voltage scaling control register fields: - - name: VOS - description: "voltage scaling selection according to performance\r These bits control the VCORE voltage level and allow to obtain the best trade-off between power consumption and performance:\r - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance.\r - When increasing the performance, the voltage scaling must be changed before increasing the system frequency.\r - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling." - bit_offset: 4 - bit_size: 2 - enum: VOS + - name: VOS + description: "voltage scaling selection according to performance\r These bits control the VCORE voltage level and allow to obtain the best trade-off between power consumption and performance:\r - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance.\r - When increasing the performance, the voltage scaling must be changed before increasing the system frequency.\r - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling." + bit_offset: 4 + bit_size: 2 + enum: VOS fieldset/VOSSR: description: PWR voltage scaling status register fields: - - name: VOSRDY - description: Ready bit for VCORE voltage scaling output selection. - bit_offset: 3 - bit_size: 1 - - name: ACTVOSRDY - description: Voltage level ready for currently used VOS - bit_offset: 13 - bit_size: 1 - - name: ACTVOS - description: "voltage output scaling currently applied to VCORE\r This field provides the last VOS value." - bit_offset: 14 - bit_size: 2 - enum: ACTVOS + - name: VOSRDY + description: Ready bit for VCORE voltage scaling output selection. + bit_offset: 3 + bit_size: 1 + - name: ACTVOSRDY + description: Voltage level ready for currently used VOS + bit_offset: 13 + bit_size: 1 + - name: ACTVOS + description: "voltage output scaling currently applied to VCORE\r This field provides the last VOS value." + bit_offset: 14 + bit_size: 2 + enum: ACTVOS fieldset/WUCR: description: PWR wakeup configuration register fields: - - name: WUPEN - description: "enable wakeup pin WUPx\r These bits are set and cleared by software.\r Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge." - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: WUPP - description: "wakeup pin polarity bit for WUPx\r These bits define the polarity used for event detection on WUPx external wakeup pin." - bit_offset: 8 - bit_size: 1 - array: - len: 5 - stride: 1 - enum: WUPP - - name: WUPPUPD - description: "wakeup pin pull configuration for WKUPx\r These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode." - bit_offset: 16 - bit_size: 2 - array: - len: 5 - stride: 2 - enum: WUPPUPD + - name: WUPEN + description: "enable wakeup pin WUPx\r These bits are set and cleared by software.\r Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge." + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: WUPP + description: "wakeup pin polarity bit for WUPx\r These bits define the polarity used for event detection on WUPx external wakeup pin." + bit_offset: 8 + bit_size: 1 + array: + len: 5 + stride: 1 + enum: WUPP + - name: WUPPUPD + description: "wakeup pin pull configuration for WKUPx\r These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode." + bit_offset: 16 + bit_size: 2 + array: + len: 5 + stride: 2 + enum: WUPPUPD fieldset/WUSCR: description: PWR wakeup status clear register fields: - - name: CWUF - description: "clear wakeup pin flag for WUFx\r These bits are always read as 0." - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 1 + - name: CWUF + description: "clear wakeup pin flag for WUFx\r These bits are always read as 0." + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 fieldset/WUSR: description: PWR wakeup status register fields: - - name: WUF - description: "wakeup pin WUFx flag\r This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register." - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 1 + - name: WUF + description: "wakeup pin WUFx flag\r This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register." + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 enum/ACTVOS: bit_size: 2 variants: - - name: B_0x0 - description: VOS3 (lowest power) - value: 0 - - name: B_0x1 - description: VOS2 - value: 1 - - name: B_0x2 - description: VOS1 - value: 2 - - name: B_0x3 - description: VOS0 (highest frequency) - value: 3 + - name: B_0x0 + description: VOS3 (lowest power) + value: 0 + - name: B_0x1 + description: VOS2 + value: 1 + - name: B_0x2 + description: VOS1 + value: 2 + - name: B_0x3 + description: VOS0 (highest frequency) + value: 3 enum/ALS: bit_size: 2 variants: - - name: B_0x0 - description: 1.7 V - value: 0 - - name: B_0x1 - description: 2.1 V - value: 1 - - name: B_0x2 - description: 2.5 V - value: 2 - - name: B_0x3 - description: 2.8 V - value: 3 + - name: B_0x0 + description: 1.7 V + value: 0 + - name: B_0x1 + description: 2.1 V + value: 1 + - name: B_0x2 + description: 2.5 V + value: 2 + - name: B_0x3 + description: 2.8 V + value: 3 enum/AVDO: bit_size: 1 variants: - - name: B_0x0 - description: "VDDA is equal or higher than the AVD threshold selected with the ALS[2:0] bits." - value: 0 - - name: B_0x1 - description: "VDDA is lower than the AVD threshold selected with the ALS[2:0] bits." - value: 1 + - name: B_0x0 + description: VDDA is equal or higher than the AVD threshold selected with the ALS[2:0] bits. + value: 0 + - name: B_0x1 + description: VDDA is lower than the AVD threshold selected with the ALS[2:0] bits. + value: 1 enum/PLS: bit_size: 3 variants: - - name: B_0x0 - description: 1.95 V - value: 0 - - name: B_0x1 - description: 2.1 V - value: 1 - - name: B_0x2 - description: 2.25 V - value: 2 - - name: B_0x3 - description: 2.4 V - value: 3 - - name: B_0x4 - description: 2.55 V - value: 4 - - name: B_0x5 - description: 2.7 V - value: 5 - - name: B_0x6 - description: 2.85 V - value: 6 - - name: B_0x7 - description: PVD_IN pin - value: 7 + - name: B_0x0 + description: 1.95 V + value: 0 + - name: B_0x1 + description: 2.1 V + value: 1 + - name: B_0x2 + description: 2.25 V + value: 2 + - name: B_0x3 + description: 2.4 V + value: 3 + - name: B_0x4 + description: 2.55 V + value: 4 + - name: B_0x5 + description: 2.7 V + value: 5 + - name: B_0x6 + description: 2.85 V + value: 6 + - name: B_0x7 + description: PVD_IN pin + value: 7 enum/PRIV: bit_size: 1 variants: - - name: B_0x0 - description: Read and write to PWR functions can be done by privileged or unprivileged access. - value: 0 - - name: B_0x1 - description: Read and write to PWR functions can be done by privileged access only. - value: 1 + - name: B_0x0 + description: Read and write to PWR functions can be done by privileged or unprivileged access. + value: 0 + - name: B_0x1 + description: Read and write to PWR functions can be done by privileged access only. + value: 1 enum/PVDO: bit_size: 1 variants: - - name: B_0x0 - description: "VDD is equal or higher than the PVD threshold selected through the PLS[2:0] bits." - value: 0 - - name: B_0x1 - description: "VDD is lower than the PVD threshold selected through the PLS[2:0] bits." - value: 1 + - name: B_0x0 + description: VDD is equal or higher than the PVD threshold selected through the PLS[2:0] bits. + value: 0 + - name: B_0x1 + description: VDD is lower than the PVD threshold selected through the PLS[2:0] bits. + value: 1 enum/SVOS: bit_size: 2 variants: - - name: B_0x0 - description: reserved - value: 0 - - name: B_0x1 - description: SVOS5 scale 5 - value: 1 - - name: B_0x2 - description: SVOS4 scale 4 - value: 2 - - name: B_0x3 - description: SVOS3 scale 3 (default). - value: 3 + - name: B_0x0 + description: reserved + value: 0 + - name: B_0x1 + description: SVOS5 scale 5 + value: 1 + - name: B_0x2 + description: SVOS4 scale 4 + value: 2 + - name: B_0x3 + description: SVOS3 scale 3 (default). + value: 3 enum/VBRS: bit_size: 1 variants: - - name: B_0x0 - description: Charge VBAT through a 5 kΩ resistor. - value: 0 - - name: B_0x1 - description: Charge VBAT through a 1.5 kΩ resistor. - value: 1 + - name: B_0x0 + description: Charge VBAT through a 5 kΩ resistor. + value: 0 + - name: B_0x1 + description: Charge VBAT through a 1.5 kΩ resistor. + value: 1 enum/VOS: bit_size: 2 variants: - - name: Scale3 - description: scale 3 (default) - value: 0 - - name: Scale2 - description: scale 2 - value: 1 - - name: Scale1 - description: scale 1 - value: 2 - - name: Scale0 - description: scale 0 - value: 3 + - name: Scale3 + description: scale 3 (default) + value: 0 + - name: Scale2 + description: scale 2 + value: 1 + - name: Scale1 + description: scale 1 + value: 2 + - name: Scale0 + description: scale 0 + value: 3 enum/WUPP: bit_size: 1 variants: - - name: B_0x0 - description: detection on high level (rising edge) - value: 0 - - name: B_0x1 - description: detection on low level (falling edge) - value: 1 + - name: B_0x0 + description: detection on high level (rising edge) + value: 0 + - name: B_0x1 + description: detection on low level (falling edge) + value: 1 enum/WUPPUPD: bit_size: 2 variants: - - name: B_0x0 - description: no pull-up - value: 0 - - name: B_0x1 - description: pull-up - value: 1 - - name: B_0x2 - description: pull-down - value: 2 - - name: B_0x3 - description: reserved - value: 3 + - name: B_0x0 + description: no pull-up + value: 0 + - name: B_0x1 + description: pull-up + value: 1 + - name: B_0x2 + description: pull-down + value: 2 + - name: B_0x3 + description: reserved + value: 3 diff --git a/data/registers/pwr_h7.yaml b/data/registers/pwr_h7.yaml deleted file mode 100644 index 9649635..0000000 --- a/data/registers/pwr_h7.yaml +++ /dev/null @@ -1,252 +0,0 @@ ---- -block/PWR: - description: PWR - items: - - name: CR1 - description: PWR control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CSR1 - description: PWR control status register 1 - byte_offset: 4 - access: Read - fieldset: CSR1 - - name: CR2 - description: "This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection." - byte_offset: 8 - fieldset: CR2 - - name: CR3 - description: "Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value." - byte_offset: 12 - fieldset: CR3 - - name: CPUCR - description: This register allows controlling CPU1 power. - byte_offset: 16 - fieldset: CPUCR - - name: D3CR - description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software - byte_offset: 24 - fieldset: D3CR - - name: WKUPCR - description: "reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared)." - byte_offset: 32 - fieldset: WKUPCR - - name: WKUPFR - description: "reset only by system reset, not reset by wakeup from Standby mode" - byte_offset: 36 - fieldset: WKUPFR - - name: WKUPEPR - description: "Reset only by system reset, not reset by wakeup from Standby mode" - byte_offset: 40 - fieldset: WKUPEPR -fieldset/CPUCR: - description: This register allows controlling CPU1 power. - fields: - - name: PDDS_D1 - description: D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain. - bit_offset: 0 - bit_size: 1 - - name: PDDS_D2 - description: D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain. - bit_offset: 1 - bit_size: 1 - - name: PDDS_D3 - description: System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain. - bit_offset: 2 - bit_size: 1 - - name: STOPF - description: STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. - bit_offset: 5 - bit_size: 1 - - name: SBF - description: System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit - bit_offset: 6 - bit_size: 1 - - name: SBF_D1 - description: "D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode." - bit_offset: 7 - bit_size: 1 - - name: SBF_D2 - description: "D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode." - bit_offset: 8 - bit_size: 1 - - name: CSSF - description: "Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware." - bit_offset: 9 - bit_size: 1 - - name: RUN_D3 - description: Keep system D3 domain in Run mode regardless of the CPU sub-systems modes - bit_offset: 11 - bit_size: 1 -fieldset/CR1: - description: PWR control register 1 - fields: - - name: LPDS - description: "Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit)" - bit_offset: 0 - bit_size: 1 - - name: PVDE - description: Programmable voltage detector enable - bit_offset: 4 - bit_size: 1 - - name: PLS - description: "Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details." - bit_offset: 5 - bit_size: 3 - - name: DBP - description: "Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers." - bit_offset: 8 - bit_size: 1 - - name: FLPS - description: "Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode." - bit_offset: 9 - bit_size: 1 - - name: SVOS - description: "System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance." - bit_offset: 14 - bit_size: 2 - - name: AVDEN - description: Peripheral voltage monitor on VDDA enable - bit_offset: 16 - bit_size: 1 - - name: ALS - description: Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. - bit_offset: 17 - bit_size: 2 -fieldset/CR2: - description: "This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection." - fields: - - name: BREN - description: "Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes." - bit_offset: 0 - bit_size: 1 - - name: MONEN - description: "VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled." - bit_offset: 4 - bit_size: 1 - - name: BRRDY - description: Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. - bit_offset: 16 - bit_size: 1 - - name: VBATL - description: VBAT level monitoring versus low threshold - bit_offset: 20 - bit_size: 1 - - name: VBATH - description: VBAT level monitoring versus high threshold - bit_offset: 21 - bit_size: 1 - - name: TEMPL - description: Temperature level monitoring versus low threshold - bit_offset: 22 - bit_size: 1 - - name: TEMPH - description: Temperature level monitoring versus high threshold - bit_offset: 23 - bit_size: 1 -fieldset/CR3: - description: "Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value." - fields: - - name: BYPASS - description: Power management unit bypass - bit_offset: 0 - bit_size: 1 - - name: LDOEN - description: Low drop-out regulator enable - bit_offset: 1 - bit_size: 1 - - name: SCUEN - description: SD converter Enable - bit_offset: 2 - bit_size: 1 - - name: VBE - description: VBAT charging enable - bit_offset: 8 - bit_size: 1 - - name: VBRS - description: VBAT charging resistor selection - bit_offset: 9 - bit_size: 1 - - name: USB33DEN - description: VDD33USB voltage level detector enable. - bit_offset: 24 - bit_size: 1 - - name: USBREGEN - description: USB regulator enable. - bit_offset: 25 - bit_size: 1 - - name: USB33RDY - description: USB supply ready. - bit_offset: 26 - bit_size: 1 -fieldset/CSR1: - description: PWR control status register 1 - fields: - - name: PVDO - description: "Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set." - bit_offset: 4 - bit_size: 1 - - name: ACTVOSRDY - description: Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3). - bit_offset: 13 - bit_size: 1 - - name: ACTVOS - description: VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU. - bit_offset: 14 - bit_size: 2 - - name: AVDO - description: "Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set." - bit_offset: 16 - bit_size: 1 -fieldset/D3CR: - description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software - fields: - - name: VOSRDY - description: VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3). - bit_offset: 13 - bit_size: 1 - - name: VOS - description: "Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling." - bit_offset: 14 - bit_size: 2 -fieldset/WKUPCR: - description: "reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared)." - fields: - - name: WKUPC - description: Clear Wakeup pin flag for WKUP. These bits are always read as 0. - bit_offset: 0 - bit_size: 6 -fieldset/WKUPEPR: - description: "Reset only by system reset, not reset by wakeup from Standby mode" - fields: - - name: WKUPEN - description: "Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge." - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: WKUPP - description: Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. - bit_offset: 8 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: WKUPPUPD - description: Wakeup pin pull configuration - bit_offset: 16 - bit_size: 2 - array: - len: 6 - stride: 2 -fieldset/WKUPFR: - description: "reset only by system reset, not reset by wakeup from Standby mode" - fields: - - name: WKUPF - description: Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 diff --git a/data/registers/pwr_h7rm0399.yaml b/data/registers/pwr_h7rm0399.yaml new file mode 100644 index 0000000..40bda89 --- /dev/null +++ b/data/registers/pwr_h7rm0399.yaml @@ -0,0 +1,273 @@ +block/PWR: + description: PWR + items: + - name: CR1 + description: PWR control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CSR1 + description: PWR control status register 1 + byte_offset: 4 + access: Read + fieldset: CSR1 + - name: CR2 + description: This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. + byte_offset: 8 + fieldset: CR2 + - name: CR3 + description: 'Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.' + byte_offset: 12 + fieldset: CR3 + - name: CPUCR + description: This register allows controlling CPU1 power. + byte_offset: 16 + fieldset: CPUCR + - name: D3CR + description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software + byte_offset: 24 + fieldset: D3CR + - name: WKUPCR + description: reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). + byte_offset: 32 + fieldset: WKUPCR + - name: WKUPFR + description: reset only by system reset, not reset by wakeup from Standby mode + byte_offset: 36 + fieldset: WKUPFR + - name: WKUPEPR + description: Reset only by system reset, not reset by wakeup from Standby mode + byte_offset: 40 + fieldset: WKUPEPR +fieldset/CPUCR: + description: This register allows controlling CPU1 power. + fields: + - name: PDDS_D1 + description: D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain. + bit_offset: 0 + bit_size: 1 + - name: PDDS_D2 + description: D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain. + bit_offset: 1 + bit_size: 1 + - name: PDDS_D3 + description: System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain. + bit_offset: 2 + bit_size: 1 + - name: STOPF + description: STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. + bit_offset: 5 + bit_size: 1 + - name: SBF + description: System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit + bit_offset: 6 + bit_size: 1 + - name: SBF_D1 + description: D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode. + bit_offset: 7 + bit_size: 1 + - name: SBF_D2 + description: D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode. + bit_offset: 8 + bit_size: 1 + - name: CSSF + description: Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware. + bit_offset: 9 + bit_size: 1 + - name: RUN_D3 + description: Keep system D3 domain in Run mode regardless of the CPU sub-systems modes + bit_offset: 11 + bit_size: 1 +fieldset/CR1: + description: PWR control register 1 + fields: + - name: LPDS + description: Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit) + bit_offset: 0 + bit_size: 1 + - name: PVDE + description: Programmable voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PLS + description: 'Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details.' + bit_offset: 5 + bit_size: 3 + - name: DBP + description: Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. + bit_offset: 8 + bit_size: 1 + - name: FLPS + description: Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode. + bit_offset: 9 + bit_size: 1 + - name: SVOS + description: System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. + bit_offset: 14 + bit_size: 2 + - name: AVDEN + description: Peripheral voltage monitor on VDDA enable + bit_offset: 16 + bit_size: 1 + - name: ALS + description: Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. + bit_offset: 17 + bit_size: 2 +fieldset/CR2: + description: This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. + fields: + - name: BREN + description: Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. + bit_offset: 0 + bit_size: 1 + - name: MONEN + description: VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. + bit_offset: 4 + bit_size: 1 + - name: BRRDY + description: Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. + bit_offset: 16 + bit_size: 1 + - name: VBATL + description: VBAT level monitoring versus low threshold + bit_offset: 20 + bit_size: 1 + - name: VBATH + description: VBAT level monitoring versus high threshold + bit_offset: 21 + bit_size: 1 + - name: TEMPL + description: Temperature level monitoring versus low threshold + bit_offset: 22 + bit_size: 1 + - name: TEMPH + description: Temperature level monitoring versus high threshold + bit_offset: 23 + bit_size: 1 +fieldset/CR3: + description: 'Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.' + fields: + - name: BYPASS + description: Power management unit bypass + bit_offset: 0 + bit_size: 1 + - name: LDOEN + description: Low drop-out regulator enable + bit_offset: 1 + bit_size: 1 + - name: SDEN + description: SD converter Enable + bit_offset: 2 + bit_size: 1 + - name: SDEXTHP + description: Step-down converter forced ON and in High Power MR mode + bit_offset: 3 + bit_size: 1 + - name: SDLEVEL + description: Step-down converter voltage output level selection + bit_offset: 4 + bit_size: 2 + - name: VBE + description: VBAT charging enable + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT charging resistor selection + bit_offset: 9 + bit_size: 1 + - name: SDEXTRDY + description: SMPS step-down converter external supply ready + bit_offset: 16 + bit_size: 1 + - name: USB33DEN + description: VDD33USB voltage level detector enable. + bit_offset: 24 + bit_size: 1 + - name: USBREGEN + description: USB regulator enable. + bit_offset: 25 + bit_size: 1 + - name: USB33RDY + description: USB supply ready. + bit_offset: 26 + bit_size: 1 +fieldset/CSR1: + description: PWR control status register 1 + fields: + - name: PVDO + description: 'Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.' + bit_offset: 4 + bit_size: 1 + - name: ACTVOSRDY + description: Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3). + bit_offset: 13 + bit_size: 1 + - name: ACTVOS + description: VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU. + bit_offset: 14 + bit_size: 2 + - name: AVDO + description: 'Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set.' + bit_offset: 16 + bit_size: 1 +fieldset/D3CR: + description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software + fields: + - name: VOSRDY + description: VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3). + bit_offset: 13 + bit_size: 1 + - name: VOS + description: 'Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling.' + bit_offset: 14 + bit_size: 2 + enum: VOS +fieldset/WKUPCR: + description: reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). + fields: + - name: WKUPC + description: Clear Wakeup pin flag for WKUP. These bits are always read as 0. + bit_offset: 0 + bit_size: 6 +fieldset/WKUPEPR: + description: Reset only by system reset, not reset by wakeup from Standby mode + fields: + - name: WKUPEN + description: 'Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge.' + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: WKUPP + description: Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + bit_offset: 8 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: WKUPPUPD + description: Wakeup pin pull configuration + bit_offset: 16 + bit_size: 2 + array: + len: 6 + stride: 2 +fieldset/WKUPFR: + description: reset only by system reset, not reset by wakeup from Standby mode + fields: + - name: WKUPF + description: Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 +enum/VOS: + bit_size: 2 + variants: + - name: Scale3 + value: 1 + - name: Scale2 + value: 2 + - name: Scale1 + value: 3 diff --git a/data/registers/pwr_h7rm0433.yaml b/data/registers/pwr_h7rm0433.yaml new file mode 100644 index 0000000..e7eb3e0 --- /dev/null +++ b/data/registers/pwr_h7rm0433.yaml @@ -0,0 +1,261 @@ +block/PWR: + description: PWR + items: + - name: CR1 + description: PWR control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CSR1 + description: PWR control status register 1 + byte_offset: 4 + access: Read + fieldset: CSR1 + - name: CR2 + description: This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. + byte_offset: 8 + fieldset: CR2 + - name: CR3 + description: 'Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.' + byte_offset: 12 + fieldset: CR3 + - name: CPUCR + description: This register allows controlling CPU1 power. + byte_offset: 16 + fieldset: CPUCR + - name: D3CR + description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software + byte_offset: 24 + fieldset: D3CR + - name: WKUPCR + description: reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). + byte_offset: 32 + fieldset: WKUPCR + - name: WKUPFR + description: reset only by system reset, not reset by wakeup from Standby mode + byte_offset: 36 + fieldset: WKUPFR + - name: WKUPEPR + description: Reset only by system reset, not reset by wakeup from Standby mode + byte_offset: 40 + fieldset: WKUPEPR +fieldset/CPUCR: + description: This register allows controlling CPU1 power. + fields: + - name: PDDS_D1 + description: D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain. + bit_offset: 0 + bit_size: 1 + - name: PDDS_D2 + description: D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain. + bit_offset: 1 + bit_size: 1 + - name: PDDS_D3 + description: System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain. + bit_offset: 2 + bit_size: 1 + - name: STOPF + description: STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. + bit_offset: 5 + bit_size: 1 + - name: SBF + description: System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit + bit_offset: 6 + bit_size: 1 + - name: SBF_D1 + description: D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode. + bit_offset: 7 + bit_size: 1 + - name: SBF_D2 + description: D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode. + bit_offset: 8 + bit_size: 1 + - name: CSSF + description: Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware. + bit_offset: 9 + bit_size: 1 + - name: RUN_D3 + description: Keep system D3 domain in Run mode regardless of the CPU sub-systems modes + bit_offset: 11 + bit_size: 1 +fieldset/CR1: + description: PWR control register 1 + fields: + - name: LPDS + description: Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit) + bit_offset: 0 + bit_size: 1 + - name: PVDE + description: Programmable voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PLS + description: 'Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details.' + bit_offset: 5 + bit_size: 3 + - name: DBP + description: Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. + bit_offset: 8 + bit_size: 1 + - name: FLPS + description: Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode. + bit_offset: 9 + bit_size: 1 + - name: SVOS + description: System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. + bit_offset: 14 + bit_size: 2 + - name: AVDEN + description: Peripheral voltage monitor on VDDA enable + bit_offset: 16 + bit_size: 1 + - name: ALS + description: Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. + bit_offset: 17 + bit_size: 2 +fieldset/CR2: + description: This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. + fields: + - name: BREN + description: Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. + bit_offset: 0 + bit_size: 1 + - name: MONEN + description: VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. + bit_offset: 4 + bit_size: 1 + - name: BRRDY + description: Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. + bit_offset: 16 + bit_size: 1 + - name: VBATL + description: VBAT level monitoring versus low threshold + bit_offset: 20 + bit_size: 1 + - name: VBATH + description: VBAT level monitoring versus high threshold + bit_offset: 21 + bit_size: 1 + - name: TEMPL + description: Temperature level monitoring versus low threshold + bit_offset: 22 + bit_size: 1 + - name: TEMPH + description: Temperature level monitoring versus high threshold + bit_offset: 23 + bit_size: 1 +fieldset/CR3: + description: 'Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.' + fields: + - name: BYPASS + description: Power management unit bypass + bit_offset: 0 + bit_size: 1 + - name: LDOEN + description: Low drop-out regulator enable + bit_offset: 1 + bit_size: 1 + - name: SCUEN + description: Supply configuration update enable + bit_offset: 2 + bit_size: 1 + - name: VBE + description: VBAT charging enable + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT charging resistor selection + bit_offset: 9 + bit_size: 1 + - name: USB33DEN + description: VDD33USB voltage level detector enable. + bit_offset: 24 + bit_size: 1 + - name: USBREGEN + description: USB regulator enable. + bit_offset: 25 + bit_size: 1 + - name: USB33RDY + description: USB supply ready. + bit_offset: 26 + bit_size: 1 +fieldset/CSR1: + description: PWR control status register 1 + fields: + - name: PVDO + description: 'Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.' + bit_offset: 4 + bit_size: 1 + - name: ACTVOSRDY + description: Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3). + bit_offset: 13 + bit_size: 1 + - name: ACTVOS + description: VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU. + bit_offset: 14 + bit_size: 2 + - name: AVDO + description: 'Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set.' + bit_offset: 16 + bit_size: 1 +fieldset/D3CR: + description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software + fields: + - name: VOSRDY + description: VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3). + bit_offset: 13 + bit_size: 1 + - name: VOS + description: 'Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling.' + bit_offset: 14 + bit_size: 2 + enum: VOS +fieldset/WKUPCR: + description: reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). + fields: + - name: WKUPC + description: Clear Wakeup pin flag for WKUP. These bits are always read as 0. + bit_offset: 0 + bit_size: 6 +fieldset/WKUPEPR: + description: Reset only by system reset, not reset by wakeup from Standby mode + fields: + - name: WKUPEN + description: 'Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge.' + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: WKUPP + description: Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + bit_offset: 8 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: WKUPPUPD + description: Wakeup pin pull configuration + bit_offset: 16 + bit_size: 2 + array: + len: 6 + stride: 2 +fieldset/WKUPFR: + description: reset only by system reset, not reset by wakeup from Standby mode + fields: + - name: WKUPF + description: Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 +enum/VOS: + bit_size: 2 + variants: + - name: Scale3 + value: 1 + - name: Scale2 + value: 2 + - name: Scale1 + value: 3 diff --git a/data/registers/pwr_h7rm0455.yaml b/data/registers/pwr_h7rm0455.yaml new file mode 100644 index 0000000..2d3943d --- /dev/null +++ b/data/registers/pwr_h7rm0455.yaml @@ -0,0 +1,275 @@ +block/PWR: + description: PWR + items: + - name: CR1 + description: PWR control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CSR1 + description: PWR control status register 1 + byte_offset: 4 + access: Read + fieldset: CSR1 + - name: CR2 + description: This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. + byte_offset: 8 + fieldset: CR2 + - name: CR3 + description: 'Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.' + byte_offset: 12 + fieldset: CR3 + - name: CPUCR + description: This register allows controlling CPU1 power. + byte_offset: 16 + fieldset: CPUCR + - name: D3CR + description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software + byte_offset: 24 + fieldset: D3CR + - name: WKUPCR + description: reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). + byte_offset: 32 + fieldset: WKUPCR + - name: WKUPFR + description: reset only by system reset, not reset by wakeup from Standby mode + byte_offset: 36 + fieldset: WKUPFR + - name: WKUPEPR + description: Reset only by system reset, not reset by wakeup from Standby mode + byte_offset: 40 + fieldset: WKUPEPR +fieldset/CPUCR: + description: This register allows controlling CPU1 power. + fields: + - name: PDDS_D1 + description: D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain. + bit_offset: 0 + bit_size: 1 + - name: PDDS_D2 + description: D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain. + bit_offset: 1 + bit_size: 1 + - name: PDDS_D3 + description: System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain. + bit_offset: 2 + bit_size: 1 + - name: STOPF + description: STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. + bit_offset: 5 + bit_size: 1 + - name: SBF + description: System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit + bit_offset: 6 + bit_size: 1 + - name: SBF_D1 + description: D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode. + bit_offset: 7 + bit_size: 1 + - name: SBF_D2 + description: D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode. + bit_offset: 8 + bit_size: 1 + - name: CSSF + description: Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware. + bit_offset: 9 + bit_size: 1 + - name: RUN_D3 + description: Keep system D3 domain in Run mode regardless of the CPU sub-systems modes + bit_offset: 11 + bit_size: 1 +fieldset/CR1: + description: PWR control register 1 + fields: + - name: LPDS + description: Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit) + bit_offset: 0 + bit_size: 1 + - name: PVDE + description: Programmable voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PLS + description: 'Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details.' + bit_offset: 5 + bit_size: 3 + - name: DBP + description: Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. + bit_offset: 8 + bit_size: 1 + - name: FLPS + description: Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode. + bit_offset: 9 + bit_size: 1 + - name: SVOS + description: System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. + bit_offset: 14 + bit_size: 2 + - name: AVDEN + description: Peripheral voltage monitor on VDDA enable + bit_offset: 16 + bit_size: 1 + - name: ALS + description: Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. + bit_offset: 17 + bit_size: 2 +fieldset/CR2: + description: This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. + fields: + - name: BREN + description: Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. + bit_offset: 0 + bit_size: 1 + - name: MONEN + description: VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. + bit_offset: 4 + bit_size: 1 + - name: BRRDY + description: Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. + bit_offset: 16 + bit_size: 1 + - name: VBATL + description: VBAT level monitoring versus low threshold + bit_offset: 20 + bit_size: 1 + - name: VBATH + description: VBAT level monitoring versus high threshold + bit_offset: 21 + bit_size: 1 + - name: TEMPL + description: Temperature level monitoring versus low threshold + bit_offset: 22 + bit_size: 1 + - name: TEMPH + description: Temperature level monitoring versus high threshold + bit_offset: 23 + bit_size: 1 +fieldset/CR3: + description: 'Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.' + fields: + - name: BYPASS + description: Power management unit bypass + bit_offset: 0 + bit_size: 1 + - name: LDOEN + description: Low drop-out regulator enable + bit_offset: 1 + bit_size: 1 + - name: SDEN + description: SD converter Enable + bit_offset: 2 + bit_size: 1 + - name: SDEXTHP + description: Step-down converter forced ON and in High Power MR mode + bit_offset: 3 + bit_size: 1 + - name: SDLEVEL + description: Step-down converter voltage output level selection + bit_offset: 4 + bit_size: 2 + - name: VBE + description: VBAT charging enable + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT charging resistor selection + bit_offset: 9 + bit_size: 1 + - name: SDEXTRDY + description: SMPS step-down converter external supply ready + bit_offset: 16 + bit_size: 1 + - name: USB33DEN + description: VDD33USB voltage level detector enable. + bit_offset: 24 + bit_size: 1 + - name: USBREGEN + description: USB regulator enable. + bit_offset: 25 + bit_size: 1 + - name: USB33RDY + description: USB supply ready. + bit_offset: 26 + bit_size: 1 +fieldset/CSR1: + description: PWR control status register 1 + fields: + - name: PVDO + description: 'Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.' + bit_offset: 4 + bit_size: 1 + - name: ACTVOSRDY + description: Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3). + bit_offset: 13 + bit_size: 1 + - name: ACTVOS + description: VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU. + bit_offset: 14 + bit_size: 2 + - name: AVDO + description: 'Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set.' + bit_offset: 16 + bit_size: 1 +fieldset/D3CR: + description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software + fields: + - name: VOSRDY + description: VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3). + bit_offset: 13 + bit_size: 1 + - name: VOS + description: 'Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling.' + bit_offset: 14 + bit_size: 2 + enum: VOS +fieldset/WKUPCR: + description: reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). + fields: + - name: WKUPC + description: Clear Wakeup pin flag for WKUP. These bits are always read as 0. + bit_offset: 0 + bit_size: 6 +fieldset/WKUPEPR: + description: Reset only by system reset, not reset by wakeup from Standby mode + fields: + - name: WKUPEN + description: 'Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge.' + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: WKUPP + description: Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + bit_offset: 8 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: WKUPPUPD + description: Wakeup pin pull configuration + bit_offset: 16 + bit_size: 2 + array: + len: 6 + stride: 2 +fieldset/WKUPFR: + description: reset only by system reset, not reset by wakeup from Standby mode + fields: + - name: WKUPF + description: Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 +enum/VOS: + bit_size: 2 + variants: + - name: Scale3 + value: 0 + - name: Scale2 + value: 1 + - name: Scale1 + value: 2 + - name: Scale0 + value: 3 diff --git a/data/registers/pwr_h7rm0468.yaml b/data/registers/pwr_h7rm0468.yaml new file mode 100644 index 0000000..7bb5267 --- /dev/null +++ b/data/registers/pwr_h7rm0468.yaml @@ -0,0 +1,275 @@ +block/PWR: + description: PWR + items: + - name: CR1 + description: PWR control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CSR1 + description: PWR control status register 1 + byte_offset: 4 + access: Read + fieldset: CSR1 + - name: CR2 + description: This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. + byte_offset: 8 + fieldset: CR2 + - name: CR3 + description: 'Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.' + byte_offset: 12 + fieldset: CR3 + - name: CPUCR + description: This register allows controlling CPU1 power. + byte_offset: 16 + fieldset: CPUCR + - name: D3CR + description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software + byte_offset: 24 + fieldset: D3CR + - name: WKUPCR + description: reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). + byte_offset: 32 + fieldset: WKUPCR + - name: WKUPFR + description: reset only by system reset, not reset by wakeup from Standby mode + byte_offset: 36 + fieldset: WKUPFR + - name: WKUPEPR + description: Reset only by system reset, not reset by wakeup from Standby mode + byte_offset: 40 + fieldset: WKUPEPR +fieldset/CPUCR: + description: This register allows controlling CPU1 power. + fields: + - name: PDDS_D1 + description: D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain. + bit_offset: 0 + bit_size: 1 + - name: PDDS_D2 + description: D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain. + bit_offset: 1 + bit_size: 1 + - name: PDDS_D3 + description: System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain. + bit_offset: 2 + bit_size: 1 + - name: STOPF + description: STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. + bit_offset: 5 + bit_size: 1 + - name: SBF + description: System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit + bit_offset: 6 + bit_size: 1 + - name: SBF_D1 + description: D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode. + bit_offset: 7 + bit_size: 1 + - name: SBF_D2 + description: D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode. + bit_offset: 8 + bit_size: 1 + - name: CSSF + description: Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware. + bit_offset: 9 + bit_size: 1 + - name: RUN_D3 + description: Keep system D3 domain in Run mode regardless of the CPU sub-systems modes + bit_offset: 11 + bit_size: 1 +fieldset/CR1: + description: PWR control register 1 + fields: + - name: LPDS + description: Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit) + bit_offset: 0 + bit_size: 1 + - name: PVDE + description: Programmable voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PLS + description: 'Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details.' + bit_offset: 5 + bit_size: 3 + - name: DBP + description: Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. + bit_offset: 8 + bit_size: 1 + - name: FLPS + description: Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode. + bit_offset: 9 + bit_size: 1 + - name: SVOS + description: System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. + bit_offset: 14 + bit_size: 2 + - name: AVDEN + description: Peripheral voltage monitor on VDDA enable + bit_offset: 16 + bit_size: 1 + - name: ALS + description: Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. + bit_offset: 17 + bit_size: 2 +fieldset/CR2: + description: This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. + fields: + - name: BREN + description: Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. + bit_offset: 0 + bit_size: 1 + - name: MONEN + description: VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. + bit_offset: 4 + bit_size: 1 + - name: BRRDY + description: Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. + bit_offset: 16 + bit_size: 1 + - name: VBATL + description: VBAT level monitoring versus low threshold + bit_offset: 20 + bit_size: 1 + - name: VBATH + description: VBAT level monitoring versus high threshold + bit_offset: 21 + bit_size: 1 + - name: TEMPL + description: Temperature level monitoring versus low threshold + bit_offset: 22 + bit_size: 1 + - name: TEMPH + description: Temperature level monitoring versus high threshold + bit_offset: 23 + bit_size: 1 +fieldset/CR3: + description: 'Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.' + fields: + - name: BYPASS + description: Power management unit bypass + bit_offset: 0 + bit_size: 1 + - name: LDOEN + description: Low drop-out regulator enable + bit_offset: 1 + bit_size: 1 + - name: SDEN + description: SD converter Enable + bit_offset: 2 + bit_size: 1 + - name: SDEXTHP + description: Step-down converter forced ON and in High Power MR mode + bit_offset: 3 + bit_size: 1 + - name: SDLEVEL + description: Step-down converter voltage output level selection + bit_offset: 4 + bit_size: 2 + - name: VBE + description: VBAT charging enable + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT charging resistor selection + bit_offset: 9 + bit_size: 1 + - name: SDEXTRDY + description: SMPS step-down converter external supply ready + bit_offset: 16 + bit_size: 1 + - name: USB33DEN + description: VDD33USB voltage level detector enable. + bit_offset: 24 + bit_size: 1 + - name: USBREGEN + description: USB regulator enable. + bit_offset: 25 + bit_size: 1 + - name: USB33RDY + description: USB supply ready. + bit_offset: 26 + bit_size: 1 +fieldset/CSR1: + description: PWR control status register 1 + fields: + - name: PVDO + description: 'Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.' + bit_offset: 4 + bit_size: 1 + - name: ACTVOSRDY + description: Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3). + bit_offset: 13 + bit_size: 1 + - name: ACTVOS + description: VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU. + bit_offset: 14 + bit_size: 2 + - name: AVDO + description: 'Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set.' + bit_offset: 16 + bit_size: 1 +fieldset/D3CR: + description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software + fields: + - name: VOSRDY + description: VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3). + bit_offset: 13 + bit_size: 1 + - name: VOS + description: 'Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling.' + bit_offset: 14 + bit_size: 2 + enum: VOS +fieldset/WKUPCR: + description: reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). + fields: + - name: WKUPC + description: Clear Wakeup pin flag for WKUP. These bits are always read as 0. + bit_offset: 0 + bit_size: 6 +fieldset/WKUPEPR: + description: Reset only by system reset, not reset by wakeup from Standby mode + fields: + - name: WKUPEN + description: 'Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge.' + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: WKUPP + description: Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + bit_offset: 8 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: WKUPPUPD + description: Wakeup pin pull configuration + bit_offset: 16 + bit_size: 2 + array: + len: 6 + stride: 2 +fieldset/WKUPFR: + description: reset only by system reset, not reset by wakeup from Standby mode + fields: + - name: WKUPF + description: Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 +enum/VOS: + bit_size: 2 + variants: + - name: Scale0 + value: 0 + - name: Scale3 + value: 1 + - name: Scale2 + value: 2 + - name: Scale1 + value: 3 diff --git a/data/registers/pwr_h7smps.yaml b/data/registers/pwr_h7smps.yaml deleted file mode 100644 index 49cc3b8..0000000 --- a/data/registers/pwr_h7smps.yaml +++ /dev/null @@ -1,264 +0,0 @@ ---- -block/PWR: - description: PWR - items: - - name: CR1 - description: PWR control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CSR1 - description: PWR control status register 1 - byte_offset: 4 - access: Read - fieldset: CSR1 - - name: CR2 - description: "This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection." - byte_offset: 8 - fieldset: CR2 - - name: CR3 - description: "Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value." - byte_offset: 12 - fieldset: CR3 - - name: CPUCR - description: This register allows controlling CPU1 power. - byte_offset: 16 - fieldset: CPUCR - - name: D3CR - description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software - byte_offset: 24 - fieldset: D3CR - - name: WKUPCR - description: "reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared)." - byte_offset: 32 - fieldset: WKUPCR - - name: WKUPFR - description: "reset only by system reset, not reset by wakeup from Standby mode" - byte_offset: 36 - fieldset: WKUPFR - - name: WKUPEPR - description: "Reset only by system reset, not reset by wakeup from Standby mode" - byte_offset: 40 - fieldset: WKUPEPR -fieldset/CPUCR: - description: This register allows controlling CPU1 power. - fields: - - name: PDDS_D1 - description: D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain. - bit_offset: 0 - bit_size: 1 - - name: PDDS_D2 - description: D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain. - bit_offset: 1 - bit_size: 1 - - name: PDDS_D3 - description: System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain. - bit_offset: 2 - bit_size: 1 - - name: STOPF - description: STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. - bit_offset: 5 - bit_size: 1 - - name: SBF - description: System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit - bit_offset: 6 - bit_size: 1 - - name: SBF_D1 - description: "D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode." - bit_offset: 7 - bit_size: 1 - - name: SBF_D2 - description: "D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode." - bit_offset: 8 - bit_size: 1 - - name: CSSF - description: "Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware." - bit_offset: 9 - bit_size: 1 - - name: RUN_D3 - description: Keep system D3 domain in Run mode regardless of the CPU sub-systems modes - bit_offset: 11 - bit_size: 1 -fieldset/CR1: - description: PWR control register 1 - fields: - - name: LPDS - description: "Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit)" - bit_offset: 0 - bit_size: 1 - - name: PVDE - description: Programmable voltage detector enable - bit_offset: 4 - bit_size: 1 - - name: PLS - description: "Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details." - bit_offset: 5 - bit_size: 3 - - name: DBP - description: "Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers." - bit_offset: 8 - bit_size: 1 - - name: FLPS - description: "Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode." - bit_offset: 9 - bit_size: 1 - - name: SVOS - description: "System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance." - bit_offset: 14 - bit_size: 2 - - name: AVDEN - description: Peripheral voltage monitor on VDDA enable - bit_offset: 16 - bit_size: 1 - - name: ALS - description: Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. - bit_offset: 17 - bit_size: 2 -fieldset/CR2: - description: "This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection." - fields: - - name: BREN - description: "Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes." - bit_offset: 0 - bit_size: 1 - - name: MONEN - description: "VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled." - bit_offset: 4 - bit_size: 1 - - name: BRRDY - description: Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. - bit_offset: 16 - bit_size: 1 - - name: VBATL - description: VBAT level monitoring versus low threshold - bit_offset: 20 - bit_size: 1 - - name: VBATH - description: VBAT level monitoring versus high threshold - bit_offset: 21 - bit_size: 1 - - name: TEMPL - description: Temperature level monitoring versus low threshold - bit_offset: 22 - bit_size: 1 - - name: TEMPH - description: Temperature level monitoring versus high threshold - bit_offset: 23 - bit_size: 1 -fieldset/CR3: - description: "Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value." - fields: - - name: BYPASS - description: Power management unit bypass - bit_offset: 0 - bit_size: 1 - - name: LDOEN - description: Low drop-out regulator enable - bit_offset: 1 - bit_size: 1 - - name: SDEN - description: SD converter Enable - bit_offset: 2 - bit_size: 1 - - name: SDEXTHP - description: Step-down converter forced ON and in High Power MR mode - bit_offset: 3 - bit_size: 1 - - name: SDLEVEL - description: Step-down converter voltage output level selection - bit_offset: 4 - bit_size: 2 - - name: VBE - description: VBAT charging enable - bit_offset: 8 - bit_size: 1 - - name: VBRS - description: VBAT charging resistor selection - bit_offset: 9 - bit_size: 1 - - name: SDEXTRDY - description: SMPS step-down converter external supply ready - bit_offset: 16 - bit_size: 1 - - name: USB33DEN - description: VDD33USB voltage level detector enable. - bit_offset: 24 - bit_size: 1 - - name: USBREGEN - description: USB regulator enable. - bit_offset: 25 - bit_size: 1 - - name: USB33RDY - description: USB supply ready. - bit_offset: 26 - bit_size: 1 -fieldset/CSR1: - description: PWR control status register 1 - fields: - - name: PVDO - description: "Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set." - bit_offset: 4 - bit_size: 1 - - name: ACTVOSRDY - description: Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3). - bit_offset: 13 - bit_size: 1 - - name: ACTVOS - description: VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU. - bit_offset: 14 - bit_size: 2 - - name: AVDO - description: "Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set." - bit_offset: 16 - bit_size: 1 -fieldset/D3CR: - description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software - fields: - - name: VOSRDY - description: VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3). - bit_offset: 13 - bit_size: 1 - - name: VOS - description: "Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling." - bit_offset: 14 - bit_size: 2 -fieldset/WKUPCR: - description: "reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared)." - fields: - - name: WKUPC - description: Clear Wakeup pin flag for WKUP. These bits are always read as 0. - bit_offset: 0 - bit_size: 6 -fieldset/WKUPEPR: - description: "Reset only by system reset, not reset by wakeup from Standby mode" - fields: - - name: WKUPEN - description: "Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge." - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: WKUPP - description: Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. - bit_offset: 8 - bit_size: 1 - array: - len: 6 - stride: 1 - - name: WKUPPUPD - description: Wakeup pin pull configuration - bit_offset: 16 - bit_size: 2 - array: - len: 6 - stride: 2 -fieldset/WKUPFR: - description: "reset only by system reset, not reset by wakeup from Standby mode" - fields: - - name: WKUPF - description: Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 1 diff --git a/data/registers/pwr_l0.yaml b/data/registers/pwr_l0.yaml new file mode 100644 index 0000000..caf0fa2 --- /dev/null +++ b/data/registers/pwr_l0.yaml @@ -0,0 +1,178 @@ +block/PWR: + description: Power control + items: + - name: CR + description: power control register + byte_offset: 0 + fieldset: CR + - name: CSR + description: power control/status register + byte_offset: 4 + fieldset: CSR +fieldset/CR: + description: power control register + fields: + - name: LPSDSR + description: Low-power deepsleep/Sleep/Low-power run + bit_offset: 0 + bit_size: 1 + enum: MODE + - name: PDDS + description: Power down deepsleep + bit_offset: 1 + bit_size: 1 + enum: PDDS + - name: CWUF + description: Clear wakeup flag + bit_offset: 2 + bit_size: 1 + - name: CSBF + description: Clear standby flag + bit_offset: 3 + bit_size: 1 + - name: PVDE + description: Power voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PLS + description: PVD level selection + bit_offset: 5 + bit_size: 3 + enum: PLS + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: ULP + description: Ultra-low-power mode + bit_offset: 9 + bit_size: 1 + - name: FWU + description: Fast wakeup + bit_offset: 10 + bit_size: 1 + - name: VOS + description: Voltage scaling range selection + bit_offset: 11 + bit_size: 2 + enum: VOS + - name: DS_EE_KOFF + description: Deep sleep mode with Flash memory kept off + bit_offset: 13 + bit_size: 1 + enum: DS_EE_KOFF + - name: LPRUN + description: Low power run mode + bit_offset: 14 + bit_size: 1 + enum: MODE + - name: LPDS + description: Regulator in Low-power deepsleep mode + bit_offset: 16 + bit_size: 1 + enum: MODE +fieldset/CSR: + description: power control/status register + fields: + - name: WUF + description: Wakeup flag + bit_offset: 0 + bit_size: 1 + - name: SBF + description: Standby flag + bit_offset: 1 + bit_size: 1 + - name: PVDO + description: PVD output + bit_offset: 2 + bit_size: 1 + - name: VREFINTRDYF + description: Internal voltage reference ready flag + bit_offset: 3 + bit_size: 1 + - name: VOSF + description: Voltage Scaling select flag + bit_offset: 4 + bit_size: 1 + - name: REGLPF + description: Regulator LP flag + bit_offset: 5 + bit_size: 1 + - name: EWUP1 + description: Enable WKUP pin 1 + bit_offset: 8 + bit_size: 1 + - name: EWUP2 + description: Enable WKUP pin 2 + bit_offset: 9 + bit_size: 1 + - name: EWUP3 + description: Enable WKUP pin 3 + bit_offset: 10 + bit_size: 1 +enum/DS_EE_KOFF: + bit_size: 1 + variants: + - name: NVMWakeUp + description: NVM woken up when exiting from Deepsleep mode even if the bit RUN_PD is set + value: 0 + - name: NVMSleep + description: NVM not woken up when exiting from low-power mode (if the bit RUN_PD is set) + value: 1 +enum/MODE: + bit_size: 1 + variants: + - name: MAIN_MODE + description: Voltage regulator in Main mode + value: 0 + - name: LOW_POWER_MODE + description: Voltage regulator switches to low-power mode + value: 1 +enum/PDDS: + bit_size: 1 + variants: + - name: STOP_MODE + description: Enter Stop mode when the CPU enters deepsleep + value: 0 + - name: STANDBY_MODE + description: Enter Standby mode when the CPU enters deepsleep + value: 1 +enum/PLS: + bit_size: 3 + variants: + - name: V1_9 + description: 1.9 V + value: 0 + - name: V2_1 + description: 2.1 V + value: 1 + - name: V2_3 + description: 2.3 V + value: 2 + - name: V2_5 + description: 2.5 V + value: 3 + - name: V2_7 + description: 2.7 V + value: 4 + - name: V2_9 + description: 2.9 V + value: 5 + - name: V3_1 + description: 3.1 V + value: 6 + - name: External + description: External input analog voltage (Compare internally to VREFINT) + value: 7 +enum/VOS: + bit_size: 2 + variants: + - name: Range1 + description: 1.8 V (range 1) + value: 1 + - name: Range2 + description: 1.5 V (range 2) + value: 2 + - name: Range3 + description: 1.2 V (range 3) + value: 3 diff --git a/data/registers/pwr_l1.yaml b/data/registers/pwr_l1.yaml index 3b48ba0..4fd0e2a 100644 --- a/data/registers/pwr_l1.yaml +++ b/data/registers/pwr_l1.yaml @@ -1,103 +1,115 @@ ---- block/PWR: description: Power control items: - - name: CR - description: power control register - byte_offset: 0 - fieldset: CR - - name: CSR - description: power control/status register - byte_offset: 4 - fieldset: CSR + - name: CR + description: power control register + byte_offset: 0 + fieldset: CR + - name: CSR + description: power control/status register + byte_offset: 4 + fieldset: CSR fieldset/CR: description: power control register fields: - - name: LPSDSR - description: Low-power deep sleep - bit_offset: 0 - bit_size: 1 - - name: PDDS - description: Power down deepsleep - bit_offset: 1 - bit_size: 1 - enum: PDDS - - name: CWUF - description: Clear wakeup flag - bit_offset: 2 - bit_size: 1 - - name: CSBF - description: Clear standby flag - bit_offset: 3 - bit_size: 1 - - name: PVDE - description: Power voltage detector enable - bit_offset: 4 - bit_size: 1 - - name: PLS - description: PVD level selection - bit_offset: 5 - bit_size: 3 - - name: DBP - description: Disable backup domain write protection - bit_offset: 8 - bit_size: 1 - - name: ULP - description: Ultralow power mode - bit_offset: 9 - bit_size: 1 - - name: FWU - description: Fast wakeup - bit_offset: 10 - bit_size: 1 - - name: VOS - description: Voltage scaling range selection - bit_offset: 11 - bit_size: 2 - - name: LPRUN - description: Low power run mode - bit_offset: 14 - bit_size: 1 + - name: LPSDSR + description: Low-power deep sleep + bit_offset: 0 + bit_size: 1 + - name: PDDS + description: Power down deepsleep + bit_offset: 1 + bit_size: 1 + enum: PDDS + - name: CWUF + description: Clear wakeup flag + bit_offset: 2 + bit_size: 1 + - name: CSBF + description: Clear standby flag + bit_offset: 3 + bit_size: 1 + - name: PVDE + description: Power voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PLS + description: PVD level selection + bit_offset: 5 + bit_size: 3 + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: ULP + description: Ultralow power mode + bit_offset: 9 + bit_size: 1 + - name: FWU + description: Fast wakeup + bit_offset: 10 + bit_size: 1 + - name: VOS + description: Voltage scaling range selection + bit_offset: 11 + bit_size: 2 + enum: VOS + - name: LPRUN + description: Low power run mode + bit_offset: 14 + bit_size: 1 fieldset/CSR: description: power control/status register fields: - - name: WUF - description: Wakeup flag - bit_offset: 0 - bit_size: 1 - - name: SBF - description: Standby flag - bit_offset: 1 - bit_size: 1 - - name: PVDO - description: PVD output - bit_offset: 2 - bit_size: 1 - - name: VREFINTRDYF - description: Internal voltage reference (VREFINT) ready flag - bit_offset: 3 - bit_size: 1 - - name: VOSF - description: Voltage Scaling select flag - bit_offset: 4 - bit_size: 1 - - name: REGLPF - description: Regulator LP flag - bit_offset: 5 - bit_size: 1 - - name: EWUP - description: Enable WKUP pin 1 - bit_offset: 8 - bit_size: 1 - array: - len: 3 - stride: 1 + - name: WUF + description: Wakeup flag + bit_offset: 0 + bit_size: 1 + - name: SBF + description: Standby flag + bit_offset: 1 + bit_size: 1 + - name: PVDO + description: PVD output + bit_offset: 2 + bit_size: 1 + - name: VREFINTRDYF + description: Internal voltage reference (VREFINT) ready flag + bit_offset: 3 + bit_size: 1 + - name: VOSF + description: Voltage Scaling select flag + bit_offset: 4 + bit_size: 1 + - name: REGLPF + description: Regulator LP flag + bit_offset: 5 + bit_size: 1 + - name: EWUP + description: Enable WKUP pin 1 + bit_offset: 8 + bit_size: 1 + array: + len: 3 + stride: 1 enum/PDDS: bit_size: 1 variants: - - name: STOP_MODE - description: Enter Stop mode when the CPU enters deepsleep - value: 0 - - name: STANDBY_MODE - description: Enter Standby mode when the CPU enters deepsleep - value: 1 + - name: STOP_MODE + description: Enter Stop mode when the CPU enters deepsleep + value: 0 + - name: STANDBY_MODE + description: Enter Standby mode when the CPU enters deepsleep + value: 1 +enum/VOS: + bit_size: 2 + variants: + - name: Range1 + description: Range 1 + value: 1 + - name: Range2 + description: Range 2 + value: 2 + - name: Range3 + description: Range 3 + value: 3 diff --git a/data/registers/pwr_l4.yaml b/data/registers/pwr_l4.yaml index 96e69b7..dd0025d 100644 --- a/data/registers/pwr_l4.yaml +++ b/data/registers/pwr_l4.yaml @@ -1,323 +1,322 @@ ---- block/PWR: description: Power control items: - - name: CR1 - description: Power control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Power control register 2 - byte_offset: 4 - fieldset: CR2 - - name: CR3 - description: Power control register 3 - byte_offset: 8 - fieldset: CR3 - - name: CR4 - description: Power control register 4 - byte_offset: 12 - fieldset: CR4 - - name: SR1 - description: Power status register 1 - byte_offset: 16 - access: Read - fieldset: SR1 - - name: SR2 - description: Power status register 2 - byte_offset: 20 - access: Read - fieldset: SR2 - - name: SCR - description: Power status clear register - byte_offset: 24 - access: Write - fieldset: SCR - - name: PUCR - description: Power Port A pull-up control register - array: - len: 8 - stride: 8 - byte_offset: 32 - fieldset: PCR - - name: PDCR - description: Power Port A pull-down control register - array: - len: 8 - stride: 8 - byte_offset: 36 - fieldset: PCR + - name: CR1 + description: Power control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Power control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: Power control register 3 + byte_offset: 8 + fieldset: CR3 + - name: CR4 + description: Power control register 4 + byte_offset: 12 + fieldset: CR4 + - name: SR1 + description: Power status register 1 + byte_offset: 16 + access: Read + fieldset: SR1 + - name: SR2 + description: Power status register 2 + byte_offset: 20 + access: Read + fieldset: SR2 + - name: SCR + description: Power status clear register + byte_offset: 24 + access: Write + fieldset: SCR + - name: PUCR + description: Power Port A pull-up control register + array: + len: 8 + stride: 8 + byte_offset: 32 + fieldset: PCR + - name: PDCR + description: Power Port A pull-down control register + array: + len: 8 + stride: 8 + byte_offset: 36 + fieldset: PCR fieldset/CR1: description: Power control register 1 fields: - - name: LPMS - description: Low-power mode selection - bit_offset: 0 - bit_size: 3 - enum: LPMS - - name: DBP - description: Disable backup domain write protection - bit_offset: 8 - bit_size: 1 - - name: VOS - description: Voltage scaling range selection - bit_offset: 9 - bit_size: 2 - enum: VOS - - name: LPR - description: Low-power run - bit_offset: 14 - bit_size: 1 - enum: LPR + - name: LPMS + description: Low-power mode selection + bit_offset: 0 + bit_size: 3 + enum: LPMS + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: VOS + description: Voltage scaling range selection + bit_offset: 9 + bit_size: 2 + enum: VOS + - name: LPR + description: Low-power run + bit_offset: 14 + bit_size: 1 + enum: LPR fieldset/CR2: description: Power control register 2 fields: - - name: PVDE - description: Power voltage detector enable - bit_offset: 0 - bit_size: 1 - - name: PLS - description: Power voltage detector level selection - bit_offset: 1 - bit_size: 3 - enum: PLS - - name: PVME1 - description: "Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V" - bit_offset: 4 - bit_size: 1 - - name: PVME2 - description: "Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V" - bit_offset: 5 - bit_size: 1 - - name: PVME3 - description: "Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" - bit_offset: 6 - bit_size: 1 - - name: PVME4 - description: "Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V" - bit_offset: 7 - bit_size: 1 - - name: IOSV - description: VDDIO2 Independent I/Os supply valid - bit_offset: 9 - bit_size: 1 - - name: USV - description: VDDUSB USB supply valid - bit_offset: 10 - bit_size: 1 + - name: PVDE + description: Power voltage detector enable + bit_offset: 0 + bit_size: 1 + - name: PLS + description: Power voltage detector level selection + bit_offset: 1 + bit_size: 3 + enum: PLS + - name: PVME1 + description: 'Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V' + bit_offset: 4 + bit_size: 1 + - name: PVME2 + description: 'Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V' + bit_offset: 5 + bit_size: 1 + - name: PVME3 + description: 'Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V' + bit_offset: 6 + bit_size: 1 + - name: PVME4 + description: 'Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V' + bit_offset: 7 + bit_size: 1 + - name: IOSV + description: VDDIO2 Independent I/Os supply valid + bit_offset: 9 + bit_size: 1 + - name: USV + description: VDDUSB USB supply valid + bit_offset: 10 + bit_size: 1 fieldset/CR3: description: Power control register 3 fields: - - name: EWUP - description: Enable Wakeup pin WKUP - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: RRS - description: SRAM2 retention in Standby mode - bit_offset: 8 - bit_size: 1 - enum: RRS - - name: APC - description: Apply pull-up and pull-down configuration - bit_offset: 10 - bit_size: 1 - - name: EWF - description: Enable internal wakeup line - bit_offset: 15 - bit_size: 1 + - name: EWUP + description: Enable Wakeup pin WKUP + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: RRS + description: SRAM2 retention in Standby mode + bit_offset: 8 + bit_size: 1 + enum: RRS + - name: APC + description: Apply pull-up and pull-down configuration + bit_offset: 10 + bit_size: 1 + - name: EWF + description: Enable internal wakeup line + bit_offset: 15 + bit_size: 1 fieldset/CR4: description: Power control register 4 fields: - - name: WP1 - description: Wakeup pin WKUP1 polarity - bit_offset: 0 - bit_size: 1 - - name: WP2 - description: Wakeup pin WKUP2 polarity - bit_offset: 1 - bit_size: 1 - - name: WP3 - description: Wakeup pin WKUP3 polarity - bit_offset: 2 - bit_size: 1 - - name: WP4 - description: Wakeup pin WKUP4 polarity - bit_offset: 3 - bit_size: 1 - - name: WP5 - description: Wakeup pin WKUP5 polarity - bit_offset: 4 - bit_size: 1 - - name: VBE - description: VBAT battery charging enable - bit_offset: 8 - bit_size: 1 - - name: VBRS - description: VBAT battery charging resistor selection - bit_offset: 9 - bit_size: 1 + - name: WP1 + description: Wakeup pin WKUP1 polarity + bit_offset: 0 + bit_size: 1 + - name: WP2 + description: Wakeup pin WKUP2 polarity + bit_offset: 1 + bit_size: 1 + - name: WP3 + description: Wakeup pin WKUP3 polarity + bit_offset: 2 + bit_size: 1 + - name: WP4 + description: Wakeup pin WKUP4 polarity + bit_offset: 3 + bit_size: 1 + - name: WP5 + description: Wakeup pin WKUP5 polarity + bit_offset: 4 + bit_size: 1 + - name: VBE + description: VBAT battery charging enable + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT battery charging resistor selection + bit_offset: 9 + bit_size: 1 fieldset/PCR: description: Power Port pull control register fields: - - name: P - description: Port pull bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 + - name: P + description: Port pull bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 fieldset/SCR: description: Power status clear register fields: - - name: CWUF - description: Clear wakeup flag - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: SBF - description: Clear standby flag - bit_offset: 8 - bit_size: 1 + - name: CWUF + description: Clear wakeup flag + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: SBF + description: Clear standby flag + bit_offset: 8 + bit_size: 1 fieldset/SR1: description: Power status register 1 fields: - - name: CWUF1 - description: Wakeup flag 1 - bit_offset: 0 - bit_size: 1 - - name: CWUF2 - description: Wakeup flag 2 - bit_offset: 1 - bit_size: 1 - - name: CWUF3 - description: Wakeup flag 3 - bit_offset: 2 - bit_size: 1 - - name: CWUF4 - description: Wakeup flag 4 - bit_offset: 3 - bit_size: 1 - - name: CWUF5 - description: Wakeup flag 5 - bit_offset: 4 - bit_size: 1 - - name: CSBF - description: Standby flag - bit_offset: 8 - bit_size: 1 - - name: WUFI - description: Wakeup flag internal - bit_offset: 15 - bit_size: 1 + - name: CWUF1 + description: Wakeup flag 1 + bit_offset: 0 + bit_size: 1 + - name: CWUF2 + description: Wakeup flag 2 + bit_offset: 1 + bit_size: 1 + - name: CWUF3 + description: Wakeup flag 3 + bit_offset: 2 + bit_size: 1 + - name: CWUF4 + description: Wakeup flag 4 + bit_offset: 3 + bit_size: 1 + - name: CWUF5 + description: Wakeup flag 5 + bit_offset: 4 + bit_size: 1 + - name: CSBF + description: Standby flag + bit_offset: 8 + bit_size: 1 + - name: WUFI + description: Wakeup flag internal + bit_offset: 15 + bit_size: 1 fieldset/SR2: description: Power status register 2 fields: - - name: REGLPS - description: Low-power regulator started - bit_offset: 8 - bit_size: 1 - - name: REGLPF - description: Low-power regulator flag - bit_offset: 9 - bit_size: 1 - - name: VOSF - description: Voltage scaling flag - bit_offset: 10 - bit_size: 1 - - name: PVDO - description: Power voltage detector output - bit_offset: 11 - bit_size: 1 - - name: PVMO1 - description: "Peripheral voltage monitoring output: VDDUSB vs. 1.2 V" - bit_offset: 12 - bit_size: 1 - - name: PVMO2 - description: "Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V" - bit_offset: 13 - bit_size: 1 - - name: PVMO3 - description: "Peripheral voltage monitoring output: VDDA vs. 1.62 V" - bit_offset: 14 - bit_size: 1 - - name: PVMO4 - description: "Peripheral voltage monitoring output: VDDA vs. 2.2 V" - bit_offset: 15 - bit_size: 1 + - name: REGLPS + description: Low-power regulator started + bit_offset: 8 + bit_size: 1 + - name: REGLPF + description: Low-power regulator flag + bit_offset: 9 + bit_size: 1 + - name: VOSF + description: Voltage scaling flag + bit_offset: 10 + bit_size: 1 + - name: PVDO + description: Power voltage detector output + bit_offset: 11 + bit_size: 1 + - name: PVMO1 + description: 'Peripheral voltage monitoring output: VDDUSB vs. 1.2 V' + bit_offset: 12 + bit_size: 1 + - name: PVMO2 + description: 'Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V' + bit_offset: 13 + bit_size: 1 + - name: PVMO3 + description: 'Peripheral voltage monitoring output: VDDA vs. 1.62 V' + bit_offset: 14 + bit_size: 1 + - name: PVMO4 + description: 'Peripheral voltage monitoring output: VDDA vs. 2.2 V' + bit_offset: 15 + bit_size: 1 enum/LPMS: bit_size: 3 variants: - - name: Stop0 - description: Stop 0 mode - value: 0 - - name: Stop1 - description: Stop 1 mode - value: 1 - - name: Stop2 - description: Stop 2 mode - value: 2 - - name: Standby - description: Standby mode - value: 3 - - name: Shutdown - description: Shutdown mode - value: 4 + - name: Stop0 + description: Stop 0 mode + value: 0 + - name: Stop1 + description: Stop 1 mode + value: 1 + - name: Stop2 + description: Stop 2 mode + value: 2 + - name: Standby + description: Standby mode + value: 3 + - name: Shutdown + description: Shutdown mode + value: 4 enum/LPR: bit_size: 1 variants: - - name: MainMode - description: Voltage regulator in Main mode - value: 0 - - name: LowPowerMode - description: Voltage regulator in low-power mode - value: 1 + - name: MainMode + description: Voltage regulator in Main mode + value: 0 + - name: LowPowerMode + description: Voltage regulator in low-power mode + value: 1 enum/PLS: bit_size: 3 variants: - - name: V2_0 - description: 2.0V - value: 0 - - name: V2_2 - description: 2.2V - value: 1 - - name: V2_4 - description: 2.4V - value: 2 - - name: V2_5 - description: 2.5V - value: 3 - - name: V2_6 - description: 2.6V - value: 4 - - name: V2_8 - description: 2.8V - value: 5 - - name: V2_9 - description: 2.9V - value: 6 - - name: External - description: External input analog voltage PVD_IN (compared internally to VREFINT) - value: 7 + - name: V2_0 + description: 2.0V + value: 0 + - name: V2_2 + description: 2.2V + value: 1 + - name: V2_4 + description: 2.4V + value: 2 + - name: V2_5 + description: 2.5V + value: 3 + - name: V2_6 + description: 2.6V + value: 4 + - name: V2_8 + description: 2.8V + value: 5 + - name: V2_9 + description: 2.9V + value: 6 + - name: External + description: External input analog voltage PVD_IN (compared internally to VREFINT) + value: 7 enum/RRS: bit_size: 1 variants: - - name: PowerOff - description: SRAM2 powered off in Standby mode (SRAM2 content lost) - value: 0 - - name: OnLPR - description: SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept) - value: 1 + - name: PowerOff + description: SRAM2 powered off in Standby mode (SRAM2 content lost) + value: 0 + - name: OnLPR + description: SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept) + value: 1 enum/VOS: bit_size: 2 variants: - - name: Range1 - description: Range 1 - value: 1 - - name: Range2 - description: Range 2 - value: 2 + - name: Range1 + description: Range 1 + value: 1 + - name: Range2 + description: Range 2 + value: 2 diff --git a/data/registers/pwr_l5.yaml b/data/registers/pwr_l5.yaml index 040b20f..5c2a32a 100644 --- a/data/registers/pwr_l5.yaml +++ b/data/registers/pwr_l5.yaml @@ -1,407 +1,406 @@ ---- block/PWR: description: Power control items: - - name: CR1 - description: Power control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Power control register 2 - byte_offset: 4 - fieldset: CR2 - - name: CR3 - description: Power control register 3 - byte_offset: 8 - fieldset: CR3 - - name: CR4 - description: Power control register 4 - byte_offset: 12 - fieldset: CR4 - - name: SR1 - description: Power status register 1 - byte_offset: 16 - access: Read - fieldset: SR1 - - name: SR2 - description: Power status register 2 - byte_offset: 20 - access: Read - fieldset: SR2 - - name: SCR - description: Power status clear register - byte_offset: 24 - access: Write - fieldset: SCR - - name: PUCR - description: Power Port A pull-up control register - array: - len: 8 - stride: 8 - byte_offset: 32 - fieldset: PCR - - name: PDCR - description: Power Port A pull-down control register - array: - len: 8 - stride: 8 - byte_offset: 36 - fieldset: PCR - - name: SECCFGR - description: Power secure configuration register - byte_offset: 120 - fieldset: SECCFGR - - name: PRIVCFGR - description: Power privilege configuration register - byte_offset: 128 - fieldset: PRIVCFGR + - name: CR1 + description: Power control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Power control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: Power control register 3 + byte_offset: 8 + fieldset: CR3 + - name: CR4 + description: Power control register 4 + byte_offset: 12 + fieldset: CR4 + - name: SR1 + description: Power status register 1 + byte_offset: 16 + access: Read + fieldset: SR1 + - name: SR2 + description: Power status register 2 + byte_offset: 20 + access: Read + fieldset: SR2 + - name: SCR + description: Power status clear register + byte_offset: 24 + access: Write + fieldset: SCR + - name: PUCR + description: Power Port A pull-up control register + array: + len: 8 + stride: 8 + byte_offset: 32 + fieldset: PCR + - name: PDCR + description: Power Port A pull-down control register + array: + len: 8 + stride: 8 + byte_offset: 36 + fieldset: PCR + - name: SECCFGR + description: Power secure configuration register + byte_offset: 120 + fieldset: SECCFGR + - name: PRIVCFGR + description: Power privilege configuration register + byte_offset: 128 + fieldset: PRIVCFGR fieldset/CR1: description: Power control register 1 fields: - - name: LPMS - description: Low-power mode selection - bit_offset: 0 - bit_size: 3 - enum: LPMS - - name: DBP - description: Disable backup domain write protection - bit_offset: 8 - bit_size: 1 - - name: VOS - description: Voltage scaling range selection - bit_offset: 9 - bit_size: 2 - enum: VOS - - name: LPR - description: Low-power run - bit_offset: 14 - bit_size: 1 - enum: LPR + - name: LPMS + description: Low-power mode selection + bit_offset: 0 + bit_size: 3 + enum: LPMS + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: VOS + description: Voltage scaling range selection + bit_offset: 9 + bit_size: 2 + enum: VOS + - name: LPR + description: Low-power run + bit_offset: 14 + bit_size: 1 + enum: LPR fieldset/CR2: description: Power control register 2 fields: - - name: PVDE - description: Power voltage detector enable - bit_offset: 0 - bit_size: 1 - - name: PLS - description: Power voltage detector level selection - bit_offset: 1 - bit_size: 3 - enum: PLS - - name: PVME1 - description: "Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V" - bit_offset: 4 - bit_size: 1 - - name: PVME2 - description: "Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V" - bit_offset: 5 - bit_size: 1 - - name: PVME3 - description: "Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" - bit_offset: 6 - bit_size: 1 - - name: PVME4 - description: "Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V" - bit_offset: 7 - bit_size: 1 - - name: IOSV - description: VDDIO2 Independent I/Os supply valid - bit_offset: 9 - bit_size: 1 - - name: USV - description: VDDUSB USB supply valid - bit_offset: 10 - bit_size: 1 + - name: PVDE + description: Power voltage detector enable + bit_offset: 0 + bit_size: 1 + - name: PLS + description: Power voltage detector level selection + bit_offset: 1 + bit_size: 3 + enum: PLS + - name: PVME1 + description: 'Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V' + bit_offset: 4 + bit_size: 1 + - name: PVME2 + description: 'Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V' + bit_offset: 5 + bit_size: 1 + - name: PVME3 + description: 'Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V' + bit_offset: 6 + bit_size: 1 + - name: PVME4 + description: 'Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V' + bit_offset: 7 + bit_size: 1 + - name: IOSV + description: VDDIO2 Independent I/Os supply valid + bit_offset: 9 + bit_size: 1 + - name: USV + description: VDDUSB USB supply valid + bit_offset: 10 + bit_size: 1 fieldset/CR3: description: Power control register 3 fields: - - name: EWUP - description: Enable Wakeup pin WKUP - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: RRS - description: SRAM2 retention in Standby mode - bit_offset: 8 - bit_size: 2 - enum: RRS - - name: APC - description: Apply pull-up and pull-down configuration - bit_offset: 10 - bit_size: 1 - - name: ULPMEN - description: ULPMEN - bit_offset: 11 - bit_size: 1 - - name: UCPD_STDBY - description: UCPD_STDBY - bit_offset: 13 - bit_size: 1 - - name: UCPD_DBDIS - description: UCPD_DBDIS - bit_offset: 14 - bit_size: 1 + - name: EWUP + description: Enable Wakeup pin WKUP + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: RRS + description: SRAM2 retention in Standby mode + bit_offset: 8 + bit_size: 2 + enum: RRS + - name: APC + description: Apply pull-up and pull-down configuration + bit_offset: 10 + bit_size: 1 + - name: ULPMEN + description: ULPMEN + bit_offset: 11 + bit_size: 1 + - name: UCPD_STDBY + description: UCPD_STDBY + bit_offset: 13 + bit_size: 1 + - name: UCPD_DBDIS + description: UCPD_DBDIS + bit_offset: 14 + bit_size: 1 fieldset/CR4: description: Power control register 4 fields: - - name: WP1 - description: Wakeup pin WKUP1 polarity - bit_offset: 0 - bit_size: 1 - - name: WP2 - description: Wakeup pin WKUP2 polarity - bit_offset: 1 - bit_size: 1 - - name: WP3 - description: Wakeup pin WKUP3 polarity - bit_offset: 2 - bit_size: 1 - - name: WP4 - description: Wakeup pin WKUP4 polarity - bit_offset: 3 - bit_size: 1 - - name: WP5 - description: Wakeup pin WKUP5 polarity - bit_offset: 4 - bit_size: 1 - - name: VBE - description: VBAT battery charging enable - bit_offset: 8 - bit_size: 1 - - name: VBRS - description: VBAT battery charging resistor selection - bit_offset: 9 - bit_size: 1 - - name: SMPSBYP - description: SMPSBYP - bit_offset: 12 - bit_size: 1 - - name: EXTSMPSEN - description: EXTSMPSEN - bit_offset: 13 - bit_size: 1 - - name: SMPSFSTEN - description: SMPSFSTEN - bit_offset: 14 - bit_size: 1 - - name: SMPSLPEN - description: SMPSLPEN - bit_offset: 15 - bit_size: 1 + - name: WP1 + description: Wakeup pin WKUP1 polarity + bit_offset: 0 + bit_size: 1 + - name: WP2 + description: Wakeup pin WKUP2 polarity + bit_offset: 1 + bit_size: 1 + - name: WP3 + description: Wakeup pin WKUP3 polarity + bit_offset: 2 + bit_size: 1 + - name: WP4 + description: Wakeup pin WKUP4 polarity + bit_offset: 3 + bit_size: 1 + - name: WP5 + description: Wakeup pin WKUP5 polarity + bit_offset: 4 + bit_size: 1 + - name: VBE + description: VBAT battery charging enable + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT battery charging resistor selection + bit_offset: 9 + bit_size: 1 + - name: SMPSBYP + description: SMPSBYP + bit_offset: 12 + bit_size: 1 + - name: EXTSMPSEN + description: EXTSMPSEN + bit_offset: 13 + bit_size: 1 + - name: SMPSFSTEN + description: SMPSFSTEN + bit_offset: 14 + bit_size: 1 + - name: SMPSLPEN + description: SMPSLPEN + bit_offset: 15 + bit_size: 1 fieldset/PCR: description: Power Port pull control register fields: - - name: P - description: Port pull bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 + - name: P + description: Port pull bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 fieldset/PRIVCFGR: description: Power privilege configuration register fields: - - name: PRIV - description: PRIV - bit_offset: 0 - bit_size: 1 + - name: PRIV + description: PRIV + bit_offset: 0 + bit_size: 1 fieldset/SCR: description: Power status clear register fields: - - name: CWUF - description: Clear wakeup flag - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 1 - - name: SBF - description: Clear standby flag - bit_offset: 8 - bit_size: 1 + - name: CWUF + description: Clear wakeup flag + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: SBF + description: Clear standby flag + bit_offset: 8 + bit_size: 1 fieldset/SECCFGR: description: Power secure configuration register fields: - - name: WUP1SEC - description: WKUP1 pin security - bit_offset: 0 - bit_size: 1 - - name: WUP2SEC - description: WKUP2 pin security - bit_offset: 1 - bit_size: 1 - - name: WUP3SEC - description: WKUP3 pin security - bit_offset: 2 - bit_size: 1 - - name: WUP4SEC - description: WKUP4 pin security - bit_offset: 3 - bit_size: 1 - - name: WUP5SEC - description: WKUP5 pin security - bit_offset: 4 - bit_size: 1 - - name: LPMSEC - description: LPMSEC - bit_offset: 8 - bit_size: 1 - - name: VDMSEC - description: VDMSEC - bit_offset: 9 - bit_size: 1 - - name: VBSEC - description: VBSEC - bit_offset: 10 - bit_size: 1 - - name: APCSEC - description: APCSEC - bit_offset: 11 - bit_size: 1 + - name: WUP1SEC + description: WKUP1 pin security + bit_offset: 0 + bit_size: 1 + - name: WUP2SEC + description: WKUP2 pin security + bit_offset: 1 + bit_size: 1 + - name: WUP3SEC + description: WKUP3 pin security + bit_offset: 2 + bit_size: 1 + - name: WUP4SEC + description: WKUP4 pin security + bit_offset: 3 + bit_size: 1 + - name: WUP5SEC + description: WKUP5 pin security + bit_offset: 4 + bit_size: 1 + - name: LPMSEC + description: LPMSEC + bit_offset: 8 + bit_size: 1 + - name: VDMSEC + description: VDMSEC + bit_offset: 9 + bit_size: 1 + - name: VBSEC + description: VBSEC + bit_offset: 10 + bit_size: 1 + - name: APCSEC + description: APCSEC + bit_offset: 11 + bit_size: 1 fieldset/SR1: description: Power status register 1 fields: - - name: CWUF1 - description: Wakeup flag 1 - bit_offset: 0 - bit_size: 1 - - name: CWUF2 - description: Wakeup flag 2 - bit_offset: 1 - bit_size: 1 - - name: CWUF3 - description: Wakeup flag 3 - bit_offset: 2 - bit_size: 1 - - name: CWUF4 - description: Wakeup flag 4 - bit_offset: 3 - bit_size: 1 - - name: CWUF5 - description: Wakeup flag 5 - bit_offset: 4 - bit_size: 1 - - name: CSBF - description: Standby flag - bit_offset: 8 - bit_size: 1 - - name: WUFI - description: Wakeup flag internal - bit_offset: 15 - bit_size: 1 + - name: CWUF1 + description: Wakeup flag 1 + bit_offset: 0 + bit_size: 1 + - name: CWUF2 + description: Wakeup flag 2 + bit_offset: 1 + bit_size: 1 + - name: CWUF3 + description: Wakeup flag 3 + bit_offset: 2 + bit_size: 1 + - name: CWUF4 + description: Wakeup flag 4 + bit_offset: 3 + bit_size: 1 + - name: CWUF5 + description: Wakeup flag 5 + bit_offset: 4 + bit_size: 1 + - name: CSBF + description: Standby flag + bit_offset: 8 + bit_size: 1 + - name: WUFI + description: Wakeup flag internal + bit_offset: 15 + bit_size: 1 fieldset/SR2: description: Power status register 2 fields: - - name: REGLPS - description: Low-power regulator started - bit_offset: 8 - bit_size: 1 - - name: REGLPF - description: Low-power regulator flag - bit_offset: 9 - bit_size: 1 - - name: VOSF - description: Voltage scaling flag - bit_offset: 10 - bit_size: 1 - - name: PVDO - description: Power voltage detector output - bit_offset: 11 - bit_size: 1 - - name: PVMO1 - description: "Peripheral voltage monitoring output: VDDUSB vs. 1.2 V" - bit_offset: 12 - bit_size: 1 - - name: PVMO2 - description: "Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V" - bit_offset: 13 - bit_size: 1 - - name: PVMO3 - description: "Peripheral voltage monitoring output: VDDA vs. 1.62 V" - bit_offset: 14 - bit_size: 1 - - name: PVMO4 - description: "Peripheral voltage monitoring output: VDDA vs. 2.2 V" - bit_offset: 15 - bit_size: 1 + - name: REGLPS + description: Low-power regulator started + bit_offset: 8 + bit_size: 1 + - name: REGLPF + description: Low-power regulator flag + bit_offset: 9 + bit_size: 1 + - name: VOSF + description: Voltage scaling flag + bit_offset: 10 + bit_size: 1 + - name: PVDO + description: Power voltage detector output + bit_offset: 11 + bit_size: 1 + - name: PVMO1 + description: 'Peripheral voltage monitoring output: VDDUSB vs. 1.2 V' + bit_offset: 12 + bit_size: 1 + - name: PVMO2 + description: 'Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V' + bit_offset: 13 + bit_size: 1 + - name: PVMO3 + description: 'Peripheral voltage monitoring output: VDDA vs. 1.62 V' + bit_offset: 14 + bit_size: 1 + - name: PVMO4 + description: 'Peripheral voltage monitoring output: VDDA vs. 2.2 V' + bit_offset: 15 + bit_size: 1 enum/LPMS: bit_size: 3 variants: - - name: Stop0 - description: Stop 0 mode - value: 0 - - name: Stop1 - description: Stop 1 mode - value: 1 - - name: Stop2 - description: Stop 2 mode - value: 2 - - name: Standby - description: Standby mode - value: 3 - - name: Shutdown - description: Shutdown mode - value: 4 + - name: Stop0 + description: Stop 0 mode + value: 0 + - name: Stop1 + description: Stop 1 mode + value: 1 + - name: Stop2 + description: Stop 2 mode + value: 2 + - name: Standby + description: Standby mode + value: 3 + - name: Shutdown + description: Shutdown mode + value: 4 enum/LPR: bit_size: 1 variants: - - name: MainMode - description: Voltage regulator in Main mode - value: 0 - - name: LowPowerMode - description: Voltage regulator in low-power mode - value: 1 + - name: MainMode + description: Voltage regulator in Main mode + value: 0 + - name: LowPowerMode + description: Voltage regulator in low-power mode + value: 1 enum/PLS: bit_size: 3 variants: - - name: V2_0 - description: 2.0V - value: 0 - - name: V2_2 - description: 2.2V - value: 1 - - name: V2_4 - description: 2.4V - value: 2 - - name: V2_5 - description: 2.5V - value: 3 - - name: V2_6 - description: 2.6V - value: 4 - - name: V2_8 - description: 2.8V - value: 5 - - name: V2_9 - description: 2.9V - value: 6 - - name: External - description: External input analog voltage PVD_IN (compared internally to VREFINT) - value: 7 + - name: V2_0 + description: 2.0V + value: 0 + - name: V2_2 + description: 2.2V + value: 1 + - name: V2_4 + description: 2.4V + value: 2 + - name: V2_5 + description: 2.5V + value: 3 + - name: V2_6 + description: 2.6V + value: 4 + - name: V2_8 + description: 2.8V + value: 5 + - name: V2_9 + description: 2.9V + value: 6 + - name: External + description: External input analog voltage PVD_IN (compared internally to VREFINT) + value: 7 enum/RRS: bit_size: 2 variants: - - name: PowerOff - description: SRAM2 powered off in Standby mode (SRAM2 content lost) - value: 0 - - name: OnLPR - description: SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept) - value: 1 - - name: OnLPRTop4kb - description: Only the upper 4 Kbytes of SRAM2 are powered by the low-power regulator in Standby mode (upper 4 Kbytes of SRAM2 content 0x2003 F000 - 0x2003 FFFF is kept). - value: 2 + - name: PowerOff + description: SRAM2 powered off in Standby mode (SRAM2 content lost) + value: 0 + - name: OnLPR + description: SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept) + value: 1 + - name: OnLPRTop4kb + description: Only the upper 4 Kbytes of SRAM2 are powered by the low-power regulator in Standby mode (upper 4 Kbytes of SRAM2 content 0x2003 F000 - 0x2003 FFFF is kept). + value: 2 enum/VOS: bit_size: 2 variants: - - name: Range0 - description: Range 0 - value: 0 - - name: Range1 - description: Range 1 - value: 1 - - name: Range2 - description: Range 2 - value: 2 + - name: Range0 + description: Range 0 + value: 0 + - name: Range1 + description: Range 1 + value: 1 + - name: Range2 + description: Range 2 + value: 2 diff --git a/data/registers/pwr_u5.yaml b/data/registers/pwr_u5.yaml index c118bb1..334724f 100644 --- a/data/registers/pwr_u5.yaml +++ b/data/registers/pwr_u5.yaml @@ -1,951 +1,861 @@ ---- block/PWR: description: Power control items: - - name: CR1 - description: PWR control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: PWR control register 2 - byte_offset: 4 - fieldset: CR2 - - name: CR3 - description: PWR control register 3 - byte_offset: 8 - fieldset: CR3 - - name: VOSR - description: PWR voltage scaling register - byte_offset: 12 - fieldset: VOSR - - name: SVMCR - description: PWR supply voltage monitoring control register - byte_offset: 16 - fieldset: SVMCR - - name: WUCR1 - description: PWR wakeup control register 1 - byte_offset: 20 - fieldset: WUCR1 - - name: WUCR2 - description: PWR wakeup control register 2 - byte_offset: 24 - fieldset: WUCR2 - - name: WUCR3 - description: PWR wakeup control register 3 - byte_offset: 28 - fieldset: WUCR3 - - name: BDCR1 - description: PWR Backup domain control register 1 - byte_offset: 32 - fieldset: BDCR1 - - name: BDCR2 - description: PWR Backup domain control register 2 - byte_offset: 36 - fieldset: BDCR2 - - name: DBPR - description: PWR disable Backup domain register - byte_offset: 40 - fieldset: DBPR - - name: UCPDR - description: PWR USB Type-C™ and Power Delivery register - byte_offset: 44 - fieldset: UCPDR - - name: SECCFGR - description: PWR security configuration register - byte_offset: 48 - fieldset: SECCFGR - - name: PRIVCFGR - description: PWR privilege control register - byte_offset: 52 - fieldset: PRIVCFGR - - name: SR - description: PWR status register - byte_offset: 56 - fieldset: SR - - name: SVMSR - byte_offset: 60 - fieldset: SVMSR - - name: BDSR - description: PWR Backup domain status register - byte_offset: 64 - fieldset: BDSR - - name: WUSR - description: PWR wakeup status register - byte_offset: 68 - fieldset: WUSR - - name: WUSCR - description: PWR wakeup status clear register - byte_offset: 72 - fieldset: WUSCR - - name: APCR - description: PWR apply pull configuration register - byte_offset: 76 - fieldset: APCR - - name: PUCR - description: Power Port pull-up control register - array: - len: 9 - stride: 8 - byte_offset: 80 - fieldset: PCR - - name: PDCR - description: Power Port pull-down control register - array: - len: 9 - stride: 8 - byte_offset: 84 - fieldset: PCR + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: control register 3 + byte_offset: 8 + fieldset: CR3 + - name: VOSR + description: voltage scaling register + byte_offset: 12 + fieldset: VOSR + - name: SVMCR + description: supply voltage monitoring control register + byte_offset: 16 + fieldset: SVMCR + - name: WUCR1 + description: wakeup control register 1 + byte_offset: 20 + fieldset: WUCR1 + - name: WUCR2 + description: wakeup control register 2 + byte_offset: 24 + fieldset: WUCR2 + - name: WUCR3 + description: wakeup control register 3 + byte_offset: 28 + fieldset: WUCR3 + - name: BDCR1 + description: Backup domain control register 1 + byte_offset: 32 + fieldset: BDCR1 + - name: BDCR2 + description: Backup domain control register 2 + byte_offset: 36 + fieldset: BDCR2 + - name: DBPR + description: disable Backup domain register + byte_offset: 40 + fieldset: DBPR + - name: UCPDR + description: USB Type-C™ and Power Delivery register + byte_offset: 44 + fieldset: UCPDR + - name: SECCFGR + description: security configuration register + byte_offset: 48 + fieldset: SECCFGR + - name: PRIVCFGR + description: privilege control register + byte_offset: 52 + fieldset: PRIVCFGR + - name: SR + description: status register + byte_offset: 56 + fieldset: SR + - name: SVMSR + byte_offset: 60 + fieldset: SVMSR + - name: BDSR + description: Backup domain status register + byte_offset: 64 + fieldset: BDSR + - name: WUSR + description: wakeup status register + byte_offset: 68 + fieldset: WUSR + - name: WUSCR + description: wakeup status clear register + byte_offset: 72 + fieldset: WUSCR + - name: APCR + description: apply pull configuration register + byte_offset: 76 + fieldset: APCR + - name: PUCR + description: Power Port pull-up control register + array: + len: 9 + stride: 8 + byte_offset: 80 + fieldset: PCR + - name: PDCR + description: Power Port pull-down control register + array: + len: 9 + stride: 8 + byte_offset: 84 + fieldset: PCR fieldset/APCR: - description: PWR apply pull configuration register + description: apply pull configuration register fields: - - name: APC - description: "Apply pull-up and pull-down configuration\r When this bit is set, the I/O pull-up and pull-down configurations defined in PUCRx and PDCRx are applied. When this bit is cleared, PUCRx and PDCRx are not applied to the I/Os." - bit_offset: 0 - bit_size: 1 + - name: APC + description: "Apply pull-up and pull-down configuration\r When this bit is set, the I/O pull-up and pull-down configurations defined in PUCRx and PDCRx are applied. When this bit is cleared, PUCRx and PDCRx are not applied to the I/Os." + bit_offset: 0 + bit_size: 1 fieldset/BDCR1: - description: PWR Backup domain control register 1 + description: Backup domain control register 1 fields: - - name: BREN - description: "Backup RAM retention in Standby and VBAT modes\r When this bit is set, the backup RAM content is kept in Standby and VBAT modes.\r If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS.\r Note: Backup RAM cannot be preserved in Shutdown mode." - bit_offset: 0 - bit_size: 1 - - name: MONEN - description: Backup domain voltage and temperature monitoring enable - bit_offset: 4 - bit_size: 1 + - name: BREN + description: "Backup RAM retention in Standby and VBAT modes\r When this bit is set, the backup RAM content is kept in Standby and VBAT modes.\r If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS.\r Note: Backup RAM cannot be preserved in Shutdown mode." + bit_offset: 0 + bit_size: 1 + - name: MONEN + description: Backup domain voltage and temperature monitoring enable + bit_offset: 4 + bit_size: 1 fieldset/BDCR2: - description: PWR Backup domain control register 2 + description: Backup domain control register 2 fields: - - name: VBE - description: VBAT charging enable - bit_offset: 0 - bit_size: 1 - enum: VBE - - name: VBRS - description: VBAT charging resistor selection - bit_offset: 1 - bit_size: 1 - enum: VBRS + - name: VBE + description: VBAT charging enable + bit_offset: 0 + bit_size: 1 + enum: VBE + - name: VBRS + description: VBAT charging resistor selection + bit_offset: 1 + bit_size: 1 + enum: VBRS fieldset/BDSR: - description: PWR Backup domain status register + description: Backup domain status register fields: - - name: VBATH - description: Backup domain voltage level monitoring versus high threshold - bit_offset: 1 - bit_size: 1 - enum: VBATH - - name: TEMPL - description: Temperature level monitoring versus low threshold - bit_offset: 2 - bit_size: 1 - enum: TEMPL - - name: TEMPH - description: Temperature level monitoring versus high threshold - bit_offset: 3 - bit_size: 1 - enum: TEMPH + - name: VBATH + description: Backup domain voltage level monitoring versus high threshold + bit_offset: 1 + bit_size: 1 + enum: VBATH + - name: TEMPL + description: Temperature level monitoring versus low threshold + bit_offset: 2 + bit_size: 1 + enum: TEMPL + - name: TEMPH + description: Temperature level monitoring versus high threshold + bit_offset: 3 + bit_size: 1 + enum: TEMPH fieldset/CR1: - description: PWR control register 1 + description: control register 1 fields: - - name: LPMS - description: "Low-power mode selection\r These bits select the low-power mode entered when the CPU enters the Deepsleep mode.\r 10x: Standby mode (Standby mode also entered if LPMS=11X in CR1\r with BREN=1 in BDCR1)\r 11x: Shutdown mode if BREN = 0 in BDCR1" - bit_offset: 0 - bit_size: 3 - enum: LPMS - - name: RRSB1 - description: "SRAM2 page 1 retention in Stop 3 and Standby modes\r This bit is used to keep the SRAM2 page 1 content in Stop 3 and Standby modes. The SRAM2 page 1 corresponds to the first 8 Kbytes of the SRAM2\r (from SRAM2 base address to SRAM2 base address + 0x1FFF).\r Note: This bit has no effect in Shutdown mode." - bit_offset: 5 - bit_size: 1 - enum: RRSB - - name: RRSB2 - description: "SRAM2 page 2 retention in Stop 3 and Standby modes\r This bit is used to keep the SRAM2 page 2 content in Stop 3 and Standby modes. The SRAM2 page 2 corresponds to the last 56 Kbytes of the SRAM2\r (from SRAM2 base address + 0x2000 to SRAM2 base address + 0xFFFF).\r Note: This bit has no effect in Shutdown mode." - bit_offset: 6 - bit_size: 1 - enum: RRSB - - name: ULPMEN - description: "BOR ultra-low power mode\r This bit is used to reduce the consumption by configuring the BOR in discontinuous mode.\r This bit must be set to reach the lowest power consumption in the low-power modes." - bit_offset: 7 - bit_size: 1 - - name: SRAM1PD - description: "SRAM1 power down\r This bit is used to reduce the consumption by powering off the SRAM1." - bit_offset: 8 - bit_size: 1 - enum: SRAMPD - - name: SRAM2PD - description: "SRAM2 power down\r This bit is used to reduce the consumption by powering off the SRAM2." - bit_offset: 9 - bit_size: 1 - enum: SRAMPD - - name: SRAM3PD - description: "SRAM3 power down\r This bit is used to reduce the consumption by powering off the SRAM3." - bit_offset: 10 - bit_size: 1 - enum: SRAMPD - - name: SRAM4PD - description: "SRAM4 power down\r This bit is used to reduce the consumption by powering off the SRAM4." - bit_offset: 11 - bit_size: 1 - enum: SRAMPD + - name: LPMS + description: "Low-power mode selection\r These bits select the low-power mode entered when the CPU enters the Deepsleep mode.\r 10x: Standby mode (Standby mode also entered if LPMS=11X in CR1\r with BREN=1 in BDCR1)\r 11x: Shutdown mode if BREN = 0 in BDCR1" + bit_offset: 0 + bit_size: 3 + enum: LPMS + - name: RRSB1 + description: "SRAM2 page 1 retention in Stop 3 and Standby modes\r This bit is used to keep the SRAM2 page 1 content in Stop 3 and Standby modes. The SRAM2 page 1 corresponds to the first 8 Kbytes of the SRAM2\r (from SRAM2 base address to SRAM2 base address + 0x1FFF).\r Note: This bit has no effect in Shutdown mode." + bit_offset: 5 + bit_size: 1 + enum: RRSB + - name: RRSB2 + description: "SRAM2 page 2 retention in Stop 3 and Standby modes\r This bit is used to keep the SRAM2 page 2 content in Stop 3 and Standby modes. The SRAM2 page 2 corresponds to the last 56 Kbytes of the SRAM2\r (from SRAM2 base address + 0x2000 to SRAM2 base address + 0xFFFF).\r Note: This bit has no effect in Shutdown mode." + bit_offset: 6 + bit_size: 1 + enum: RRSB + - name: ULPMEN + description: "BOR ultra-low power mode\r This bit is used to reduce the consumption by configuring the BOR in discontinuous mode.\r This bit must be set to reach the lowest power consumption in the low-power modes." + bit_offset: 7 + bit_size: 1 + - name: SRAM1PD + description: "SRAM1 power down\r This bit is used to reduce the consumption by powering off the SRAM1." + bit_offset: 8 + bit_size: 1 + enum: SRAMPD + - name: SRAM2PD + description: "SRAM2 power down\r This bit is used to reduce the consumption by powering off the SRAM2." + bit_offset: 9 + bit_size: 1 + enum: SRAMPD + - name: SRAM3PD + description: "SRAM3 power down\r This bit is used to reduce the consumption by powering off the SRAM3." + bit_offset: 10 + bit_size: 1 + enum: SRAMPD + - name: SRAM4PD + description: "SRAM4 power down\r This bit is used to reduce the consumption by powering off the SRAM4." + bit_offset: 11 + bit_size: 1 + enum: SRAMPD fieldset/CR2: - description: PWR control register 2 + description: control register 2 fields: - - name: SRAM1PDS1 - description: "SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)" - bit_offset: 0 - bit_size: 1 - enum: PDS - - name: SRAM1PDS2 - description: "SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)" - bit_offset: 1 - bit_size: 1 - enum: PDS - - name: SRAM1PDS3 - description: "SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)" - bit_offset: 2 - bit_size: 1 - enum: PDS - - name: SRAM2PDS1 - description: "SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2)\r Note: The SRAM2 page 1 retention in Stop 3 is controlled by RRSB1 bit in CR1." - bit_offset: 4 - bit_size: 1 - enum: PDS - - name: SRAM2PDS2 - description: "SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2)\r Note: The SRAM2 page 2 retention in Stop 3 is controlled by RRSB2 bit in CR1." - bit_offset: 5 - bit_size: 1 - enum: PDS - - name: SRAM4PDS - description: "SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3)" - bit_offset: 6 - bit_size: 1 - enum: PDS - - name: ICRAMPDS - description: "ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3)" - bit_offset: 8 - bit_size: 1 - enum: PDS - - name: DC1RAMPDS - description: "DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3)" - bit_offset: 9 - bit_size: 1 - enum: PDS - - name: DMA2DRAMPDS - description: "DMA2D SRAM power-down in Stop modes (Stop 0, 1, 2, 3)" - bit_offset: 10 - bit_size: 1 - enum: PDS - - name: PRAMPDS - description: "FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (Stop0,1,2,3)" - bit_offset: 11 - bit_size: 1 - enum: PDS - - name: PKARAMPDS - description: PKA SRAM power-down - bit_offset: 12 - bit_size: 1 - enum: PDS - - name: SRAM4FWU - description: "SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes\r This bit is used to obtain the best trade-off between low-power consumption and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting Stop 0, 1 and 2 modes, and also increases the LPDMA access time to SRAM4 during Stop modes." - bit_offset: 13 - bit_size: 1 - enum: SRAMFWU - - name: FLASHFWU - description: "Flash memory fast wakeup from Stop 0 and Stop 1 modes\r This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.\r When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption." - bit_offset: 14 - bit_size: 1 - enum: FLASHFWU - - name: SRAM3PDS1 - description: "SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)" - bit_offset: 16 - bit_size: 1 - enum: PDS - - name: SRAM3PDS2 - description: "SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)" - bit_offset: 17 - bit_size: 1 - enum: PDS - - name: SRAM3PDS3 - description: "SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)" - bit_offset: 18 - bit_size: 1 - enum: PDS - - name: SRAM3PDS4 - description: "SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)" - bit_offset: 19 - bit_size: 1 - enum: PDS - - name: SRAM3PDS5 - description: "SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)" - bit_offset: 20 - bit_size: 1 - enum: PDS - - name: SRAM3PDS6 - description: "SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)" - bit_offset: 21 - bit_size: 1 - enum: PDS - - name: SRAM3PDS7 - description: "SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)" - bit_offset: 22 - bit_size: 1 - enum: PDS - - name: SRAM3PDS8 - description: "SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)" - bit_offset: 23 - bit_size: 1 - enum: PDS - - name: SRDRUN - description: SmartRun domain in Run mode - bit_offset: 31 - bit_size: 1 + - name: SRAM1PDS1 + description: SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + bit_offset: 0 + bit_size: 1 + enum: PDS + - name: SRAM1PDS2 + description: SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + bit_offset: 1 + bit_size: 1 + enum: PDS + - name: SRAM1PDS3 + description: SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + bit_offset: 2 + bit_size: 1 + enum: PDS + - name: SRAM2PDS1 + description: "SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2)\r Note: The SRAM2 page 1 retention in Stop 3 is controlled by RRSB1 bit in CR1." + bit_offset: 4 + bit_size: 1 + enum: PDS + - name: SRAM2PDS2 + description: "SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2)\r Note: The SRAM2 page 2 retention in Stop 3 is controlled by RRSB2 bit in CR1." + bit_offset: 5 + bit_size: 1 + enum: PDS + - name: SRAM4PDS + description: SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3) + bit_offset: 6 + bit_size: 1 + enum: PDS + - name: ICRAMPDS + description: ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3) + bit_offset: 8 + bit_size: 1 + enum: PDS + - name: DC1RAMPDS + description: DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3) + bit_offset: 9 + bit_size: 1 + enum: PDS + - name: DMA2DRAMPDS + description: DMA2D SRAM power-down in Stop modes (Stop 0, 1, 2, 3) + bit_offset: 10 + bit_size: 1 + enum: PDS + - name: PRAMPDS + description: FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (Stop0,1,2,3) + bit_offset: 11 + bit_size: 1 + enum: PDS + - name: PKARAMPDS + description: PKA SRAM power-down + bit_offset: 12 + bit_size: 1 + enum: PDS + - name: SRAM4FWU + description: "SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes\r This bit is used to obtain the best trade-off between low-power consumption and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting Stop 0, 1 and 2 modes, and also increases the LPDMA access time to SRAM4 during Stop modes." + bit_offset: 13 + bit_size: 1 + enum: SRAMFWU + - name: FLASHFWU + description: "Flash memory fast wakeup from Stop 0 and Stop 1 modes\r This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.\r When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption." + bit_offset: 14 + bit_size: 1 + enum: FLASHFWU + - name: SRAM3PDS1 + description: SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + bit_offset: 16 + bit_size: 1 + enum: PDS + - name: SRAM3PDS2 + description: SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + bit_offset: 17 + bit_size: 1 + enum: PDS + - name: SRAM3PDS3 + description: SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + bit_offset: 18 + bit_size: 1 + enum: PDS + - name: SRAM3PDS4 + description: SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + bit_offset: 19 + bit_size: 1 + enum: PDS + - name: SRAM3PDS5 + description: SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + bit_offset: 20 + bit_size: 1 + enum: PDS + - name: SRAM3PDS6 + description: SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + bit_offset: 21 + bit_size: 1 + enum: PDS + - name: SRAM3PDS7 + description: SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + bit_offset: 22 + bit_size: 1 + enum: PDS + - name: SRAM3PDS8 + description: SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + bit_offset: 23 + bit_size: 1 + enum: PDS + - name: SRDRUN + description: SmartRun domain in Run mode + bit_offset: 31 + bit_size: 1 fieldset/CR3: - description: PWR control register 3 + description: control register 3 fields: - - name: REGSEL - description: "Regulator selection\r Note: REGSEL is reserved and must be kept at reset value in packages without SMPS." - bit_offset: 1 - bit_size: 1 - enum: REGSEL - - name: FSTEN - description: Fast soft start - bit_offset: 2 - bit_size: 1 + - name: REGSEL + description: "Regulator selection\r Note: REGSEL is reserved and must be kept at reset value in packages without SMPS." + bit_offset: 1 + bit_size: 1 + enum: REGSEL + - name: FSTEN + description: Fast soft start + bit_offset: 2 + bit_size: 1 fieldset/DBPR: - description: PWR disable Backup domain register + description: disable Backup domain register fields: - - name: DBP - description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers." - bit_offset: 0 - bit_size: 1 - enum: DBP + - name: DBP + description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers." + bit_offset: 0 + bit_size: 1 + enum: DBP fieldset/PCR: description: Power Port pull control register fields: - - name: P - description: Port pull bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 + - name: P + description: Port pull bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 fieldset/PRIVCFGR: - description: PWR privilege control register + description: privilege control register fields: - - name: SPRIV - description: "PWR secure functions privilege configuration\r This bit is set and reset by software. It can be written only by a secure privileged access." - bit_offset: 0 - bit_size: 1 - enum: PRIV - - name: NSPRIV - description: "PWR non-secure functions privilege configuration\r This bit is set and reset by software. It can be written only by privileged access, secure or non-secure." - bit_offset: 1 - bit_size: 1 - enum: PRIV + - name: SPRIV + description: "secure functions privilege configuration\r This bit is set and reset by software. It can be written only by a secure privileged access." + bit_offset: 0 + bit_size: 1 + enum: PRIV + - name: NSPRIV + description: "non-secure functions privilege configuration\r This bit is set and reset by software. It can be written only by privileged access, secure or non-secure." + bit_offset: 1 + bit_size: 1 + enum: PRIV fieldset/SECCFGR: - description: PWR security configuration register + description: security configuration register fields: - - name: WUP1SEC - description: WUP1 secure protection - bit_offset: 0 - bit_size: 1 - enum: SEC - - name: WUP2SEC - description: WUP2 secure protection - bit_offset: 1 - bit_size: 1 - enum: SEC - - name: WUP3SEC - description: WUP3 secure protection - bit_offset: 2 - bit_size: 1 - enum: SEC - - name: WUP4SEC - description: WUP4 secure protection - bit_offset: 3 - bit_size: 1 - enum: SEC - - name: WUP5SEC - description: WUP5 secure protection - bit_offset: 4 - bit_size: 1 - enum: SEC - - name: WUP6SEC - description: WUP6 secure protection - bit_offset: 5 - bit_size: 1 - enum: SEC - - name: WUP7SEC - description: WUP7 secure protection - bit_offset: 6 - bit_size: 1 - enum: SEC - - name: WUP8SEC - description: WUP8 secure protection - bit_offset: 7 - bit_size: 1 - enum: SEC - - name: LPMSEC - description: Low-power modes secure protection - bit_offset: 12 - bit_size: 1 - enum: SEC - - name: VDMSEC - description: Voltage detection and monitoring secure protection - bit_offset: 13 - bit_size: 1 - enum: SEC - - name: VBSEC - description: Backup domain secure protection - bit_offset: 14 - bit_size: 1 - enum: SEC - - name: APCSEC - description: Pull-up/pull-down secure protection - bit_offset: 15 - bit_size: 1 - enum: SEC + - name: WUP1SEC + description: WUP1 secure protection + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 + enum: SEC + - name: LPMSEC + description: Low-power modes secure protection + bit_offset: 12 + bit_size: 1 + enum: SEC + - name: VDMSEC + description: Voltage detection and monitoring secure protection + bit_offset: 13 + bit_size: 1 + enum: SEC + - name: VBSEC + description: Backup domain secure protection + bit_offset: 14 + bit_size: 1 + enum: SEC + - name: APCSEC + description: Pull-up/pull-down secure protection + bit_offset: 15 + bit_size: 1 + enum: SEC fieldset/SR: - description: PWR status register + description: status register fields: - - name: CSSF - description: "Clear Stop and Standby flags\r This bit is protected against non-secure access when LPMSEC=1 in SECCFGR.\r This bit is protected against unprivileged access when LPMSEC=1 and SPRIV=1 in PRIVCFGR, or when LPMSEC=0 and NSPRIV=1.\r Writing 1 to this bit clears the STOPF and SBF flags." - bit_offset: 0 - bit_size: 1 - - name: STOPF - description: "Stop flag\r This bit is set by hardware when the device enters a Stop mode, and is cleared by software by writing 1 to the CSSF bit." - bit_offset: 1 - bit_size: 1 - - name: SBF - description: "Standby flag\r This bit is set by hardware when the device enters the Standby mode, and is cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset." - bit_offset: 2 - bit_size: 1 + - name: CSSF + description: "Clear Stop and Standby flags\r This bit is protected against non-secure access when LPMSEC=1 in SECCFGR.\r This bit is protected against unprivileged access when LPMSEC=1 and SPRIV=1 in PRIVCFGR, or when LPMSEC=0 and NSPRIV=1.\r Writing 1 to this bit clears the STOPF and SBF flags." + bit_offset: 0 + bit_size: 1 + - name: STOPF + description: "Stop flag\r This bit is set by hardware when the device enters a Stop mode, and is cleared by software by writing 1 to the CSSF bit." + bit_offset: 1 + bit_size: 1 + - name: SBF + description: "Standby flag\r This bit is set by hardware when the device enters the Standby mode, and is cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset." + bit_offset: 2 + bit_size: 1 fieldset/SVMCR: - description: PWR supply voltage monitoring control register + description: supply voltage monitoring control register fields: - - name: PVDE - description: Power voltage detector enable - bit_offset: 4 - bit_size: 1 - - name: PVDLS - description: "Power voltage detector level selection\r These bits select the voltage threshold detected by the power voltage detector:" - bit_offset: 5 - bit_size: 3 - enum: PVDLS - - name: UVMEN - description: VDDUSB independent USB voltage monitor enable - bit_offset: 24 - bit_size: 1 - - name: IO2VMEN - description: VDDIO2 independent I/Os voltage monitor enable - bit_offset: 25 - bit_size: 1 - - name: AVM1EN - description: VDDA independent analog supply voltage monitor 1 enable (1.6V threshold) - bit_offset: 26 - bit_size: 1 - - name: AVM2EN - description: VDDA independent analog supply voltage monitor 2 enable (1.8V threshold) - bit_offset: 27 - bit_size: 1 - - name: USV - description: VDDUSB independent USB supply valid - bit_offset: 28 - bit_size: 1 - - name: IO2SV - description: "VDDIO2 independent I/Os supply valid\r This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose.\r Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the VDDIO2 voltage monitor can be used to determine whether this supply is ready or not." - bit_offset: 29 - bit_size: 1 - - name: ASV - description: VDDA independent analog supply valid - bit_offset: 30 - bit_size: 1 + - name: PVDE + description: Power voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PVDLS + description: "Power voltage detector level selection\r These bits select the voltage threshold detected by the power voltage detector:" + bit_offset: 5 + bit_size: 3 + enum: PVDLS + - name: UVMEN + description: VDDUSB independent USB voltage monitor enable + bit_offset: 24 + bit_size: 1 + - name: IO2VMEN + description: VDDIO2 independent I/Os voltage monitor enable + bit_offset: 25 + bit_size: 1 + - name: AVM1EN + description: VDDA independent analog supply voltage monitor 1 enable (1.6V threshold) + bit_offset: 26 + bit_size: 1 + - name: AVM2EN + description: VDDA independent analog supply voltage monitor 2 enable (1.8V threshold) + bit_offset: 27 + bit_size: 1 + - name: USV + description: VDDUSB independent USB supply valid + bit_offset: 28 + bit_size: 1 + - name: IO2SV + description: "VDDIO2 independent I/Os supply valid\r This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose.\r Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the VDDIO2 voltage monitor can be used to determine whether this supply is ready or not." + bit_offset: 29 + bit_size: 1 + - name: ASV + description: VDDA independent analog supply valid + bit_offset: 30 + bit_size: 1 fieldset/SVMSR: fields: - - name: REGS - description: Regulator selection - bit_offset: 1 - bit_size: 1 - enum: REGSEL - - name: PVDO - description: VDD voltage detector output - bit_offset: 4 - bit_size: 1 - enum: PVDO - - name: ACTVOSRDY - description: Voltage level ready for currently used VOS - bit_offset: 15 - bit_size: 1 - - name: ACTVOS - description: "VOS currently applied to VCORE\r This field provides the last VOS value." - bit_offset: 16 - bit_size: 2 - enum: ACTVOS - - name: VDDUSBRDY - description: VDDUSB ready - bit_offset: 24 - bit_size: 1 - - name: VDDIO2RDY - description: VDDIO2 ready - bit_offset: 25 - bit_size: 1 - - name: VDDA1RDY - description: VDDA ready versus 1.6V voltage monitor - bit_offset: 26 - bit_size: 1 - - name: VDDA2RDY - description: VDDA ready versus 1.8V voltage monitor - bit_offset: 27 - bit_size: 1 + - name: REGS + description: Regulator selection + bit_offset: 1 + bit_size: 1 + enum: REGSEL + - name: PVDO + description: VDD voltage detector output + bit_offset: 4 + bit_size: 1 + enum: PVDO + - name: ACTVOSRDY + description: Voltage level ready for currently used VOS + bit_offset: 15 + bit_size: 1 + - name: ACTVOS + description: "VOS currently applied to VCORE\r This field provides the last VOS value." + bit_offset: 16 + bit_size: 2 + enum: ACTVOS + - name: VDDUSBRDY + description: VDDUSB ready + bit_offset: 24 + bit_size: 1 + - name: VDDIO2RDY + description: VDDIO2 ready + bit_offset: 25 + bit_size: 1 + - name: VDDA1RDY + description: VDDA ready versus 1.6V voltage monitor + bit_offset: 26 + bit_size: 1 + - name: VDDA2RDY + description: VDDA ready versus 1.8V voltage monitor + bit_offset: 27 + bit_size: 1 fieldset/UCPDR: - description: PWR USB Type-C™ and Power Delivery register + description: USB Type-C™ and Power Delivery register fields: - - name: UCPD_DBDIS - description: "UCPD dead battery disable\r After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable)." - bit_offset: 0 - bit_size: 1 - - name: UCPD_STBY - description: "UCPD Standby mode\r When set, this bit is used to memorize the UCPD configuration in Standby mode.\r This bit must be written to 1 just before entering Standby mode when using UCPD.\r It must be written to 0 after exiting the Standby mode and before writing any UCPD registers." - bit_offset: 1 - bit_size: 1 + - name: UCPD_DBDIS + description: "UCPD dead battery disable\r After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable)." + bit_offset: 0 + bit_size: 1 + - name: UCPD_STBY + description: "UCPD Standby mode\r When set, this bit is used to memorize the UCPD configuration in Standby mode.\r This bit must be written to 1 just before entering Standby mode when using UCPD.\r It must be written to 0 after exiting the Standby mode and before writing any UCPD registers." + bit_offset: 1 + bit_size: 1 fieldset/VOSR: - description: PWR voltage scaling register + description: voltage scaling register fields: - - name: BOOSTRDY - description: "EPOD booster ready\r This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set." - bit_offset: 14 - bit_size: 1 - - name: VOSRDY - description: Ready bit for VCORE voltage scaling output selection - bit_offset: 15 - bit_size: 1 - - name: VOS - description: "Voltage scaling range selection\r This field is protected against non-secure access when SYSCLKSEC=1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC=1 in RCC_SECCFGR and SPRIV=1 in PRIVCFGR, or when SYSCLKSEC=0 and NSPRIV=1." - bit_offset: 16 - bit_size: 2 - enum: VOS - - name: BOOSTEN - description: EPOD booster enable - bit_offset: 18 - bit_size: 1 + - name: BOOSTRDY + description: "EPOD booster ready\r This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set." + bit_offset: 14 + bit_size: 1 + - name: VOSRDY + description: Ready bit for VCORE voltage scaling output selection + bit_offset: 15 + bit_size: 1 + - name: VOS + description: "Voltage scaling range selection\r This field is protected against non-secure access when SYSCLKSEC=1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC=1 in RCC_SECCFGR and SPRIV=1 in PRIVCFGR, or when SYSCLKSEC=0 and NSPRIV=1." + bit_offset: 16 + bit_size: 2 + enum: VOS + - name: BOOSTEN + description: EPOD booster enable + bit_offset: 18 + bit_size: 1 fieldset/WUCR1: - description: PWR wakeup control register 1 + description: wakeup control register 1 fields: - - name: WUPEN1 - description: Wakeup pin WKUP1 enable - bit_offset: 0 - bit_size: 1 - - name: WUPEN2 - description: Wakeup pin WKUP2 enable - bit_offset: 1 - bit_size: 1 - - name: WUPEN3 - description: Wakeup pin WKUP3 enable - bit_offset: 2 - bit_size: 1 - - name: WUPEN4 - description: Wakeup pin WKUP4 enable - bit_offset: 3 - bit_size: 1 - - name: WUPEN5 - description: Wakeup pin WKUP5 enable - bit_offset: 4 - bit_size: 1 - - name: WUPEN6 - description: Wakeup pin WKUP6 enable - bit_offset: 5 - bit_size: 1 - - name: WUPEN7 - description: Wakeup pin WKUP7 enable - bit_offset: 6 - bit_size: 1 - - name: WUPEN8 - description: Wakeup pin WKUP8 enable - bit_offset: 7 - bit_size: 1 + - name: WUPEN + description: Wakeup pin WKUP1 enable + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 fieldset/WUCR2: - description: PWR wakeup control register 2 + description: wakeup control register 2 fields: - - name: WUPP1 - description: "Wakeup pin WKUP1 polarity.\r This bit must be configured when WUPEN1 = 0." - bit_offset: 0 - bit_size: 1 - enum: WUPP - - name: WUPP2 - description: "Wakeup pin WKUP2 polarity\r This bit must be configured when WUPEN2 = 0." - bit_offset: 1 - bit_size: 1 - enum: WUPP - - name: WUPP3 - description: "Wakeup pin WKUP3 polarity\r This bit must be configured when WUPEN3 = 0." - bit_offset: 2 - bit_size: 1 - enum: WUPP - - name: WUPP4 - description: "Wakeup pin WKUP4 polarity\r This bit must be configured when WUPEN4 = 0." - bit_offset: 3 - bit_size: 1 - enum: WUPP - - name: WUPP5 - description: "Wakeup pin WKUP5 polarity\r This bit must be configured when WUPEN5 = 0." - bit_offset: 4 - bit_size: 1 - enum: WUPP - - name: WUPP6 - description: "Wakeup pin WKUP6 polarity\r This bit must be configured when WUPEN6 = 0." - bit_offset: 5 - bit_size: 1 - enum: WUPP - - name: WUPP7 - description: "Wakeup pin WKUP7 polarity\r This bit must be configured when WUPEN7 = 0." - bit_offset: 6 - bit_size: 1 - enum: WUPP - - name: WUPP8 - description: "Wakeup pin WKUP8 polarity\r This bit must be configured when WUPEN8=0." - bit_offset: 7 - bit_size: 1 - enum: WUPP + - name: WUPP + description: "Wakeup pin WKUP1 polarity.\r This bit must be configured when WUPEN1 = 0." + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 + enum: WUPP fieldset/WUCR3: - description: PWR wakeup control register 3 + description: wakeup control register 3 fields: - - name: WUSEL1 - description: "Wakeup pin WKUP1 selection\r This field must be configured when WUPEN1 = 0." - bit_offset: 0 - bit_size: 2 - enum: WUSEL - - name: WUSEL2 - description: "Wakeup pin WKUP2 selection\r This field must be configured when WUPEN2 = 0." - bit_offset: 2 - bit_size: 2 - enum: WUSEL - - name: WUSEL3 - description: "Wakeup pin WKUP3 selection\r This field must be configured when WUPEN3 = 0." - bit_offset: 4 - bit_size: 2 - enum: WUSEL - - name: WUSEL4 - description: "Wakeup pin WKUP4 selection\r This field must be configured when WUPEN4 = 0." - bit_offset: 6 - bit_size: 2 - enum: WUSEL - - name: WUSEL5 - description: "Wakeup pin WKUP5 selection\r This field must be configured when WUPEN5 = 0." - bit_offset: 8 - bit_size: 2 - enum: WUSEL - - name: WUSEL6 - description: "Wakeup pin WKUP6 selection\r This field must be configured when WUPEN6 = 0." - bit_offset: 10 - bit_size: 2 - enum: WUSEL - - name: WUSEL7 - description: "Wakeup pin WKUP7 selection\r This field must be configured when WUPEN7 = 0." - bit_offset: 12 - bit_size: 2 - enum: WUSEL - - name: WUSEL8 - description: "Wakeup pin WKUP8 selection\r This field must be configured when WUPEN8 = 0." - bit_offset: 14 - bit_size: 2 - enum: WUSEL + - name: WUSEL1 + description: "Wakeup pin WKUP1 selection\r This field must be configured when WUPEN1 = 0." + bit_offset: 0 + bit_size: 2 + enum: WUSEL + - name: WUSEL2 + description: "Wakeup pin WKUP2 selection\r This field must be configured when WUPEN2 = 0." + bit_offset: 2 + bit_size: 2 + enum: WUSEL + - name: WUSEL3 + description: "Wakeup pin WKUP3 selection\r This field must be configured when WUPEN3 = 0." + bit_offset: 4 + bit_size: 2 + enum: WUSEL + - name: WUSEL4 + description: "Wakeup pin WKUP4 selection\r This field must be configured when WUPEN4 = 0." + bit_offset: 6 + bit_size: 2 + enum: WUSEL + - name: WUSEL5 + description: "Wakeup pin WKUP5 selection\r This field must be configured when WUPEN5 = 0." + bit_offset: 8 + bit_size: 2 + enum: WUSEL + - name: WUSEL6 + description: "Wakeup pin WKUP6 selection\r This field must be configured when WUPEN6 = 0." + bit_offset: 10 + bit_size: 2 + enum: WUSEL + - name: WUSEL7 + description: "Wakeup pin WKUP7 selection\r This field must be configured when WUPEN7 = 0." + bit_offset: 12 + bit_size: 2 + enum: WUSEL + - name: WUSEL8 + description: "Wakeup pin WKUP8 selection\r This field must be configured when WUPEN8 = 0." + bit_offset: 14 + bit_size: 2 + enum: WUSEL fieldset/WUSCR: - description: PWR wakeup status clear register + description: wakeup status clear register fields: - - name: CWUF1 - description: "Wakeup flag 1\r Writing 1 to this bit clears the WUF1 flag in WUSR." - bit_offset: 0 - bit_size: 1 - - name: CWUF2 - description: "Wakeup flag 2\r Writing 1 to this bit clears the WUF2 flag in WUSR." - bit_offset: 1 - bit_size: 1 - - name: CWUF3 - description: "Wakeup flag 3\r Writing 1 to this bit clears the WUF3 flag in WUSR." - bit_offset: 2 - bit_size: 1 - - name: CWUF4 - description: "Wakeup flag 4\r Writing 1 to this bit clears the WUF4 flag in WUSR." - bit_offset: 3 - bit_size: 1 - - name: CWUF5 - description: "Wakeup flag 5\r Writing 1 to this bit clears the WUF5 flag in WUSR." - bit_offset: 4 - bit_size: 1 - - name: CWUF6 - description: "Wakeup flag 6\r Writing 1 to this bit clears the WUF6 flag in WUSR." - bit_offset: 5 - bit_size: 1 - - name: CWUF7 - description: "Wakeup flag 7\r Writing 1 to this bit clears the WUF7 flag in WUSR." - bit_offset: 6 - bit_size: 1 - - name: CWUF8 - description: "Wakeup flag 8\r Writing 1 to this bit clears the WUF8 flag in WUSR." - bit_offset: 7 - bit_size: 1 + - name: CWUF1 + description: "Wakeup flag 1\r Writing 1 to this bit clears the WUF1 flag in WUSR." + bit_offset: 0 + bit_size: 1 + - name: CWUF2 + description: "Wakeup flag 2\r Writing 1 to this bit clears the WUF2 flag in WUSR." + bit_offset: 1 + bit_size: 1 + - name: CWUF3 + description: "Wakeup flag 3\r Writing 1 to this bit clears the WUF3 flag in WUSR." + bit_offset: 2 + bit_size: 1 + - name: CWUF4 + description: "Wakeup flag 4\r Writing 1 to this bit clears the WUF4 flag in WUSR." + bit_offset: 3 + bit_size: 1 + - name: CWUF5 + description: "Wakeup flag 5\r Writing 1 to this bit clears the WUF5 flag in WUSR." + bit_offset: 4 + bit_size: 1 + - name: CWUF6 + description: "Wakeup flag 6\r Writing 1 to this bit clears the WUF6 flag in WUSR." + bit_offset: 5 + bit_size: 1 + - name: CWUF7 + description: "Wakeup flag 7\r Writing 1 to this bit clears the WUF7 flag in WUSR." + bit_offset: 6 + bit_size: 1 + - name: CWUF8 + description: "Wakeup flag 8\r Writing 1 to this bit clears the WUF8 flag in WUSR." + bit_offset: 7 + bit_size: 1 fieldset/WUSR: - description: PWR wakeup status register + description: wakeup status register fields: - - name: WUF1 - description: "Wakeup flag 1\r This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1=0." - bit_offset: 0 - bit_size: 1 - - name: WUF2 - description: "Wakeup flag 2\r This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by writing 1 in the CWUF2 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN2=0." - bit_offset: 1 - bit_size: 1 - - name: WUF3 - description: "Wakeup flag 3\r This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by writing 1 in the CWUF3 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN3=0." - bit_offset: 2 - bit_size: 1 - - name: WUF4 - description: "Wakeup flag 4\r This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by writing 1 in the CWUF4 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN4=0." - bit_offset: 3 - bit_size: 1 - - name: WUF5 - description: "Wakeup flag 5\r This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by writing 1 in the CWUF5 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN5=0." - bit_offset: 4 - bit_size: 1 - - name: WUF6 - description: "Wakeup flag 6\r This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by writing 1 in the CWUF6 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN6=0.\r If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared." - bit_offset: 5 - bit_size: 1 - - name: WUF7 - description: "Wakeup flag 7\r This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by writing 1 in the CWUF7 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN7=0.\r If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared." - bit_offset: 6 - bit_size: 1 - - name: WUF8 - description: "Wakeup flag 8\r This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by writing 1 in the CWUF8 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN8=0.\r If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared." - bit_offset: 7 - bit_size: 1 + - name: WUF1 + description: "Wakeup flag 1\r This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1=0." + bit_offset: 0 + bit_size: 1 + - name: WUF2 + description: "Wakeup flag 2\r This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by writing 1 in the CWUF2 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN2=0." + bit_offset: 1 + bit_size: 1 + - name: WUF3 + description: "Wakeup flag 3\r This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by writing 1 in the CWUF3 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN3=0." + bit_offset: 2 + bit_size: 1 + - name: WUF4 + description: "Wakeup flag 4\r This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by writing 1 in the CWUF4 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN4=0." + bit_offset: 3 + bit_size: 1 + - name: WUF5 + description: "Wakeup flag 5\r This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by writing 1 in the CWUF5 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN5=0." + bit_offset: 4 + bit_size: 1 + - name: WUF6 + description: "Wakeup flag 6\r This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by writing 1 in the CWUF6 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN6=0.\r If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared." + bit_offset: 5 + bit_size: 1 + - name: WUF7 + description: "Wakeup flag 7\r This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by writing 1 in the CWUF7 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN7=0.\r If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared." + bit_offset: 6 + bit_size: 1 + - name: WUF8 + description: "Wakeup flag 8\r This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by writing 1 in the CWUF8 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN8=0.\r If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared." + bit_offset: 7 + bit_size: 1 enum/ACTVOS: bit_size: 2 variants: - - name: Range4 - description: Range 4 (lowest power) - value: 0 - - name: Range3 - description: Range 3 - value: 1 - - name: Range2 - description: Range 2 - value: 2 - - name: Range1 - description: Range 1 (highest frequency) - value: 3 + - name: Range4 + description: Range 4 (lowest power) + value: 0 + - name: Range3 + description: Range 3 + value: 1 + - name: Range2 + description: Range 2 + value: 2 + - name: Range1 + description: Range 1 (highest frequency) + value: 3 enum/DBP: bit_size: 1 variants: - - name: Disabled - description: Write access to Backup domain disabled - value: 0 - - name: Enabled - description: Write access to Backup domain enabled - value: 1 + - name: Disabled + description: Write access to Backup domain disabled + value: 0 + - name: Enabled + description: Write access to Backup domain enabled + value: 1 enum/FLASHFWU: bit_size: 1 variants: - - name: LowPower - description: Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption). - value: 0 - - name: Normal - description: Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time). - value: 1 + - name: LowPower + description: Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption). + value: 0 + - name: Normal + description: Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time). + value: 1 enum/LPMS: bit_size: 3 variants: - - name: Stop0 - description: Stop 0 mode - value: 0 - - name: Stop1 - description: Stop 1 mode - value: 1 - - name: Stop2 - description: Stop 2 mode - value: 2 - - name: Stop3 - description: Stop 3 mode - value: 3 + - name: Stop0 + description: Stop 0 mode + value: 0 + - name: Stop1 + description: Stop 1 mode + value: 1 + - name: Stop2 + description: Stop 2 mode + value: 2 + - name: Stop3 + description: Stop 3 mode + value: 3 enum/PDS: bit_size: 1 variants: - - name: Retained - description: Content retained in Stop modes - value: 0 - - name: Lost - description: Content lost in Stop modes - value: 1 + - name: Retained + description: Content retained in Stop modes + value: 0 + - name: Lost + description: Content lost in Stop modes + value: 1 enum/PRIV: bit_size: 1 variants: - - name: Unprivileged - description: Read and write to PWR non-secure functions can be done by privileged or unprivileged access. - value: 0 - - name: Privileged - description: Read and write to PWR non-secure functions can be done by privileged access only. - value: 1 + - name: Unprivileged + description: Read and write to non-secure functions can be done by privileged or unprivileged access. + value: 0 + - name: Privileged + description: Read and write to non-secure functions can be done by privileged access only. + value: 1 enum/PVDLS: bit_size: 3 variants: - - name: B_0x0 - description: VPVD0 around 2.0 V - value: 0 - - name: B_0x1 - description: VPVD1 around 2.2 V - value: 1 - - name: B_0x2 - description: VPVD2 around 2.4 V - value: 2 - - name: B_0x3 - description: VPVD3 around 2.5 V - value: 3 - - name: B_0x4 - description: VPVD4 around 2.6 V - value: 4 - - name: B_0x5 - description: VPVD5 around 2.8 V - value: 5 - - name: B_0x6 - description: VPVD6 around 2.9 V - value: 6 - - name: B_0x7 - description: External input analog voltage PVD_IN (compared internally to VREFINT) - value: 7 + - name: v20 + description: VPVD0 around 2.0 V + value: 0 + - name: v22 + description: VPVD1 around 2.2 V + value: 1 + - name: v24 + description: VPVD2 around 2.4 V + value: 2 + - name: v25 + description: VPVD3 around 2.5 V + value: 3 + - name: v26 + description: VPVD4 around 2.6 V + value: 4 + - name: v28 + description: VPVD5 around 2.8 V + value: 5 + - name: v29 + description: VPVD6 around 2.9 V + value: 6 + - name: pvd_in + description: External input analog voltage PVD_IN (compared internally to VREFINT) + value: 7 enum/PVDO: bit_size: 1 variants: - - name: AboveOrEqual - description: "VDD is equal or above the PVD threshold selected by PVDLS[2:0]." - value: 0 - - name: Below - description: "VDD is below the PVD threshold selected by PVDLS[2:0]." - value: 1 + - name: AboveOrEqual + description: VDD is equal or above the PVD threshold selected by PVDLS[2:0]. + value: 0 + - name: Below + description: VDD is below the PVD threshold selected by PVDLS[2:0]. + value: 1 enum/REGSEL: bit_size: 1 variants: - - name: LDO - description: LDO selected - value: 0 - - name: SMPS - description: SMPS selected - value: 1 + - name: LDO + description: LDO selected + value: 0 + - name: SMPS + description: SMPS selected + value: 1 enum/RRSB: bit_size: 1 variants: - - name: NotRetained - description: SRAM2 page1 content not retained in Stop 3 and Standby modes - value: 0 - - name: Retained - description: SRAM2 page1 content retained in Stop 3 and Standby modes - value: 1 + - name: NotRetained + description: SRAM2 page1 content not retained in Stop 3 and Standby modes + value: 0 + - name: Retained + description: SRAM2 page1 content retained in Stop 3 and Standby modes + value: 1 enum/SEC: bit_size: 1 variants: - - name: NonSecure - description: "CR1, CR2 and CSSF in the SR can be read and written with secure or non-secure access." - value: 0 - - name: Secure - description: "CR1, CR2, and CSSF in the SR can be read and written only with secure access." - value: 1 + - name: NonSecure + description: CR1, CR2 and CSSF in the SR can be read and written with secure or non-secure access. + value: 0 + - name: Secure + description: CR1, CR2, and CSSF in the SR can be read and written only with secure access. + value: 1 enum/SRAMFWU: bit_size: 1 variants: - - name: B_0x0 - description: "SRAM4 enters low-power mode in Stop 0, 1 and 2 modes (source biasing for lower-power consumption)." - value: 0 - - name: B_0x1 - description: "SRAM4 remains in normal mode in Stop 0, 1 and 2 modes (higher consumption but no SRAM4 wakeup time)." - value: 1 + - name: B_0x0 + description: SRAM4 enters low-power mode in Stop 0, 1 and 2 modes (source biasing for lower-power consumption). + value: 0 + - name: B_0x1 + description: SRAM4 remains in normal mode in Stop 0, 1 and 2 modes (higher consumption but no SRAM4 wakeup time). + value: 1 enum/SRAMPD: bit_size: 1 variants: - - name: PoweredOn - description: SRAM1 powered on - value: 0 - - name: PoweredOff - description: SRAM1 powered off - value: 1 + - name: PoweredOn + description: SRAM1 powered on + value: 0 + - name: PoweredOff + description: SRAM1 powered off + value: 1 enum/TEMPH: bit_size: 1 variants: - - name: B_0x0 - description: Temperature < high threshold - value: 0 - - name: B_0x1 - description: Temperature ≥ high threshold - value: 1 + - name: B_0x0 + description: Temperature < high threshold + value: 0 + - name: B_0x1 + description: Temperature ≥ high threshold + value: 1 enum/TEMPL: bit_size: 1 variants: - - name: B_0x0 - description: Temperature > low threshold - value: 0 - - name: B_0x1 - description: Temperature ≤ low threshold - value: 1 + - name: B_0x0 + description: Temperature > low threshold + value: 0 + - name: B_0x1 + description: Temperature ≤ low threshold + value: 1 enum/VBATH: bit_size: 1 variants: - - name: B_0x0 - description: Backup domain voltage level < high threshold - value: 0 - - name: B_0x1 - description: Backup domain voltage level ≥ high threshold - value: 1 + - name: B_0x0 + description: Backup domain voltage level < high threshold + value: 0 + - name: B_0x1 + description: Backup domain voltage level ≥ high threshold + value: 1 enum/VBE: bit_size: 1 variants: - - name: B_0x0 - description: VBAT battery charging disabled - value: 0 - - name: B_0x1 - description: VBAT battery charging enabled - value: 1 + - name: B_0x0 + description: VBAT battery charging disabled + value: 0 + - name: B_0x1 + description: VBAT battery charging enabled + value: 1 enum/VBRS: bit_size: 1 variants: - - name: B_0x0 - description: Charge VBAT through a 5 kΩ resistor - value: 0 - - name: B_0x1 - description: Charge VBAT through a 1.5 kΩ resistor - value: 1 + - name: B_0x0 + description: Charge VBAT through a 5 kΩ resistor + value: 0 + - name: B_0x1 + description: Charge VBAT through a 1.5 kΩ resistor + value: 1 enum/VOS: bit_size: 2 variants: - - name: B_0x0 - description: Range 4 (lowest power) - value: 0 - - name: B_0x1 - description: Range 3 - value: 1 - - name: B_0x2 - description: Range 2 - value: 2 - - name: B_0x3 - description: Range 1 (highest frequency). This value cannot be written when VCOREMEN = 1 in TAMP_OR register. - value: 3 + - name: Range4 + description: Range 4 (lowest power) + value: 0 + - name: Range3 + description: Range 3 + value: 1 + - name: Range2 + description: Range 2 + value: 2 + - name: Range1 + description: Range 1 (highest frequency). This value cannot be written when VCOREMEN = 1 in TAMP_OR register. + value: 3 enum/WUPP: bit_size: 1 variants: - - name: B_0x0 - description: Detection on high level (rising edge) - value: 0 - - name: B_0x1 - description: Detection on low level (falling edge) - value: 1 + - name: High + description: Detection on high level (rising edge) + value: 0 + - name: Low + description: Detection on low level (falling edge) + value: 1 enum/WUSEL: bit_size: 2 variants: - - name: B_0x0 - description: WKUP7_0 - value: 0 - - name: B_0x1 - description: WKUP7_1 - value: 1 - - name: B_0x2 - description: WKUP7_2 - value: 2 - - name: B_0x3 - description: WKUP7_3 - value: 3 + - name: B_0x0 + description: WKUP7_0 + value: 0 + - name: B_0x1 + description: WKUP7_1 + value: 1 + - name: B_0x2 + description: WKUP7_2 + value: 2 + - name: B_0x3 + description: WKUP7_3 + value: 3 diff --git a/data/registers/pwr_wb.yaml b/data/registers/pwr_wb.yaml new file mode 100644 index 0000000..cd8a526 --- /dev/null +++ b/data/registers/pwr_wb.yaml @@ -0,0 +1,448 @@ +block/PWR: + description: Power control + items: + - name: CR1 + description: Power control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Power control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: Power control register 3 + byte_offset: 8 + fieldset: CR3 + - name: CR4 + description: Power control register 4 + byte_offset: 12 + fieldset: CR4 + - name: SR1 + description: Power status register 1 + byte_offset: 16 + access: Read + fieldset: SR1 + - name: SR2 + description: Power status register 2 + byte_offset: 20 + access: Read + fieldset: SR2 + - name: SCR + description: Power status clear register + byte_offset: 24 + access: Write + fieldset: SCR + - name: CR5 + description: Power control register 5 + byte_offset: 28 + fieldset: CR5 + - name: PUCRA + description: Power Port A pull-up control register + byte_offset: 32 + fieldset: PXCR + - name: PDCRA + description: Power Port A pull-down control register + byte_offset: 36 + fieldset: PXCR + - name: PUCRB + description: Power Port B pull-up control register + byte_offset: 40 + fieldset: PXCR + - name: PDCRB + description: Power Port B pull-down control register + byte_offset: 44 + fieldset: PXCR + - name: PUCRC + description: Power Port C pull-up control register + byte_offset: 48 + fieldset: PXCR + - name: PDCRC + description: Power Port C pull-down control register + byte_offset: 52 + fieldset: PXCR + - name: PUCRD + description: Power Port D pull-up control register + byte_offset: 56 + fieldset: PXCR + - name: PDCRD + description: Power Port D pull-down control register + byte_offset: 60 + fieldset: PXCR + - name: PUCRE + description: Power Port E pull-up control register + byte_offset: 64 + fieldset: PXCR + - name: PDCRE + description: Power Port E pull-down control register + byte_offset: 68 + fieldset: PXCR + - name: PUCRH + description: Power Port H pull-up control register + byte_offset: 88 + fieldset: PXCR + - name: PDCRH + description: Power Port H pull-down control register + byte_offset: 92 + fieldset: PXCR + - name: C2CR1 + description: CPU2 Power control register 1 + byte_offset: 128 + fieldset: C2CR1 + - name: C2CR3 + description: CPU2 Power control register 3 + byte_offset: 132 + fieldset: C2CR3 + - name: EXTSCR + description: Power status clear register + byte_offset: 136 + fieldset: EXTSCR +fieldset/C2CR1: + description: CPU2 Power control register 1 + fields: + - name: LPMS + description: Low-power mode selection for CPU2 + bit_offset: 0 + bit_size: 3 + - name: FPDR + description: Flash power down mode during LPRun for CPU2 + bit_offset: 4 + bit_size: 1 + - name: FPDS + description: Flash power down mode during LPSleep for CPU2 + bit_offset: 5 + bit_size: 1 + - name: BLEEWKUP + description: BLE external wakeup signal + bit_offset: 14 + bit_size: 1 + - name: _802EWKUP + description: 802.15.4 external wakeup signal + bit_offset: 15 + bit_size: 1 +fieldset/C2CR3: + description: CPU2 Power control register 3 + fields: + - name: EWUP + description: Enable Wakeup pin + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: EBLEWUP + description: Enable BLE host wakeup interrupt for CPU2 + bit_offset: 9 + bit_size: 1 + - name: E802WUP + description: Enable 802.15.4 host wakeup interrupt for CPU2 + bit_offset: 10 + bit_size: 1 + - name: APC + description: Apply pull-up and pull-down configuration for CPU2 + bit_offset: 12 + bit_size: 1 + - name: EIWUL + description: Enable internal wakeup line for CPU2 + bit_offset: 15 + bit_size: 1 +fieldset/CR1: + description: Power control register 1 + fields: + - name: LPMS + description: Low-power mode selection for CPU1 + bit_offset: 0 + bit_size: 3 + - name: FPDR + description: Flash power down mode during LPRun for CPU1 + bit_offset: 4 + bit_size: 1 + - name: FPDS + description: Flash power down mode during LPsSleep for CPU1 + bit_offset: 5 + bit_size: 1 + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: LPR + description: Low-power run + bit_offset: 14 + bit_size: 1 +fieldset/CR2: + description: Power control register 2 + fields: + - name: PVDE + description: Power voltage detector enable + bit_offset: 0 + bit_size: 1 + - name: PLS + description: Power voltage detector level selection + bit_offset: 1 + bit_size: 3 +fieldset/CR3: + description: Power control register 3 + fields: + - name: EWUP + description: Enable Wakeup pin + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: EBORHSDFB + description: Enable BORH and Step Down counverter forced in Bypass interrups for CPU1 + bit_offset: 8 + bit_size: 1 + - name: RRS + description: SRAM2a retention in Standby mode + bit_offset: 9 + bit_size: 1 + - name: APC + description: Apply pull-up and pull-down configuration + bit_offset: 10 + bit_size: 1 + - name: EBLEA + description: Enable BLE end of activity interrupt for CPU1 + bit_offset: 11 + bit_size: 1 + - name: ECRPE + description: Enable critical radio phase end of activity interrupt for CPU1 + bit_offset: 12 + bit_size: 1 + - name: E802A + description: Enable end of activity interrupt for CPU1 + bit_offset: 13 + bit_size: 1 + - name: EC2H + description: Enable CPU2 Hold interrupt for CPU1 + bit_offset: 14 + bit_size: 1 + - name: EIWUL + description: Enable internal wakeup line for CPU1 + bit_offset: 15 + bit_size: 1 +fieldset/CR4: + description: Power control register 4 + fields: + - name: WP1 + description: Wakeup pin WKUP1 polarity + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: VBE + description: VBAT battery charging enable + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT battery charging resistor selection + bit_offset: 9 + bit_size: 1 + - name: C2BOOT + description: BOOT CPU2 after reset or wakeup from Stop or Standby modes + bit_offset: 15 + bit_size: 1 +fieldset/CR5: + description: Power control register 5 + fields: + - name: SDVOS + description: Step Down converter voltage output scaling + bit_offset: 0 + bit_size: 4 + - name: SDSC + description: Step Down converter supplt startup current selection + bit_offset: 4 + bit_size: 3 + - name: BORHC + description: BORH configuration selection + bit_offset: 8 + bit_size: 1 + - name: SMPSCFG + description: VOS configuration selection (non user) + bit_offset: 9 + bit_size: 1 + - name: SDBEN + description: Enable Step Down converter Bypass mode enabled + bit_offset: 14 + bit_size: 1 + - name: SDEB + description: Enable Step Down converter SMPS mode enabled + bit_offset: 15 + bit_size: 1 +fieldset/EXTSCR: + description: Power status clear register + fields: + - name: C1CSSF + description: Clear CPU1 Stop Standby flags + bit_offset: 0 + bit_size: 1 + - name: C2CSSF + description: Clear CPU2 Stop Standby flags + bit_offset: 1 + bit_size: 1 + - name: CCRPF + description: Clear Critical Radio system phase + bit_offset: 2 + bit_size: 1 + - name: C1SBF + description: System Standby flag for CPU1 + bit_offset: 8 + bit_size: 1 + - name: C1STOPF + description: System Stop flag for CPU1 + bit_offset: 9 + bit_size: 1 + - name: C2SBF + description: System Standby flag for CPU2 + bit_offset: 10 + bit_size: 1 + - name: C2STOPF + description: System Stop flag for CPU2 + bit_offset: 11 + bit_size: 1 + - name: CRPF + description: Critical Radio system phase + bit_offset: 13 + bit_size: 1 + - name: C1DS + description: CPU1 deepsleep mode + bit_offset: 14 + bit_size: 1 + - name: C2DS + description: CPU2 deepsleep mode + bit_offset: 15 + bit_size: 1 +fieldset/PXCR: + description: Power Port pull-up/down control register + fields: + - name: PD + description: Port A pull-up/down bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 +fieldset/SCR: + description: Power status clear register + fields: + - name: CWUF + description: Clear wakeup flag 1 + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: CSMPSFBF + description: Clear SMPS Step Down converter forced in Bypass interrupt flag + bit_offset: 7 + bit_size: 1 + - name: CBORHF + description: Clear BORH interrupt flag + bit_offset: 8 + bit_size: 1 + - name: CBLEWUF + description: Clear BLE wakeup interrupt flag + bit_offset: 9 + bit_size: 1 + - name: C802WUF + description: Clear 802.15.4 wakeup interrupt flag + bit_offset: 10 + bit_size: 1 + - name: CCRPEF + description: Clear critical radio phase end of activity interrupt flag + bit_offset: 11 + bit_size: 1 + - name: CBLEAF + description: Clear BLE end of activity interrupt flag + bit_offset: 12 + bit_size: 1 + - name: C802AF + description: Clear 802.15.4 end of activity interrupt flag + bit_offset: 13 + bit_size: 1 + - name: CC2HF + description: Clear CPU2 Hold interrupt flag + bit_offset: 14 + bit_size: 1 +fieldset/SR1: + description: Power status register 1 + fields: + - name: CWUF + description: Wakeup flag 1 + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: SDFBF + description: Step Down converter forced in Bypass interrupt flag + bit_offset: 7 + bit_size: 1 + - name: BORHF + description: BORH interrupt flag + bit_offset: 8 + bit_size: 1 + - name: BLEWUF + description: BLE wakeup interrupt flag + bit_offset: 9 + bit_size: 1 + - name: _802WUF + description: 802.15.4 wakeup interrupt flag + bit_offset: 10 + bit_size: 1 + - name: CRPEF + description: Enable critical radio phase end of activity interrupt flag + bit_offset: 11 + bit_size: 1 + - name: BLEAF + description: BLE end of activity interrupt flag + bit_offset: 12 + bit_size: 1 + - name: AF802 + description: 802.15.4 end of activity interrupt flag + bit_offset: 13 + bit_size: 1 + - name: C2HF + description: CPU2 Hold interrupt flag + bit_offset: 14 + bit_size: 1 + - name: WUFI + description: Internal Wakeup interrupt flag + bit_offset: 15 + bit_size: 1 +fieldset/SR2: + description: Power status register 2 + fields: + - name: SDBF + description: Step Down converter Bypass mode flag + bit_offset: 0 + bit_size: 1 + - name: SDSMPSF + description: Step Down converter SMPS mode flag + bit_offset: 1 + bit_size: 1 + - name: REGLPS + description: Low-power regulator started + bit_offset: 8 + bit_size: 1 + - name: REGLPF + description: Low-power regulator flag + bit_offset: 9 + bit_size: 1 + - name: VOSF + description: Voltage scaling flag + bit_offset: 10 + bit_size: 1 + - name: PVDO + description: Power voltage detector output + bit_offset: 11 + bit_size: 1 + - name: PVMO1 + description: 'Peripheral voltage monitoring output: VDDUSB vs. 1.2 V' + bit_offset: 12 + bit_size: 1 + - name: PVMO3 + description: 'Peripheral voltage monitoring output: VDDA vs. 1.62 V' + bit_offset: 14 + bit_size: 1 diff --git a/data/registers/pwr_wb55.yaml b/data/registers/pwr_wb55.yaml index 2d237ab..c652f2f 100644 --- a/data/registers/pwr_wb55.yaml +++ b/data/registers/pwr_wb55.yaml @@ -1,1116 +1,474 @@ ---- block/PWR: description: Power control items: - - name: CR1 - description: Power control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Power control register 2 - byte_offset: 4 - fieldset: CR2 - - name: CR3 - description: Power control register 3 - byte_offset: 8 - fieldset: CR3 - - name: CR4 - description: Power control register 4 - byte_offset: 12 - fieldset: CR4 - - name: SR1 - description: Power status register 1 - byte_offset: 16 - access: Read - fieldset: SR1 - - name: SR2 - description: Power status register 2 - byte_offset: 20 - access: Read - fieldset: SR2 - - name: SCR - description: Power status clear register - byte_offset: 24 - access: Write - fieldset: SCR - - name: CR5 - description: Power control register 5 - byte_offset: 28 - fieldset: CR5 - - name: PUCRA - description: Power Port A pull-up control register - byte_offset: 32 - fieldset: PUCRA - - name: PDCRA - description: Power Port A pull-down control register - byte_offset: 36 - fieldset: PDCRA - - name: PUCRB - description: Power Port B pull-up control register - byte_offset: 40 - fieldset: PUCRB - - name: PDCRB - description: Power Port B pull-down control register - byte_offset: 44 - fieldset: PDCRB - - name: PUCRC - description: Power Port C pull-up control register - byte_offset: 48 - fieldset: PUCRC - - name: PDCRC - description: Power Port C pull-down control register - byte_offset: 52 - fieldset: PDCRC - - name: PUCRD - description: Power Port D pull-up control register - byte_offset: 56 - fieldset: PUCRD - - name: PDCRD - description: Power Port D pull-down control register - byte_offset: 60 - fieldset: PDCRD - - name: PUCRE - description: Power Port E pull-up control register - byte_offset: 64 - fieldset: PUCRE - - name: PDCRE - description: Power Port E pull-down control register - byte_offset: 68 - fieldset: PDCRE - - name: PUCRH - description: Power Port H pull-up control register - byte_offset: 88 - fieldset: PUCRH - - name: PDCRH - description: Power Port H pull-down control register - byte_offset: 92 - fieldset: PDCRH - - name: C2CR1 - description: CPU2 Power control register 1 - byte_offset: 128 - fieldset: C2CR1 - - name: C2CR3 - description: CPU2 Power control register 3 - byte_offset: 132 - fieldset: C2CR3 - - name: EXTSCR - description: Power status clear register - byte_offset: 136 - fieldset: EXTSCR + - name: CR1 + description: Power control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Power control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: Power control register 3 + byte_offset: 8 + fieldset: CR3 + - name: CR4 + description: Power control register 4 + byte_offset: 12 + fieldset: CR4 + - name: SR1 + description: Power status register 1 + byte_offset: 16 + access: Read + fieldset: SR1 + - name: SR2 + description: Power status register 2 + byte_offset: 20 + access: Read + fieldset: SR2 + - name: SCR + description: Power status clear register + byte_offset: 24 + access: Write + fieldset: SCR + - name: CR5 + description: Power control register 5 + byte_offset: 28 + fieldset: CR5 + - name: PUCRA + description: Power Port A pull-up control register + byte_offset: 32 + fieldset: PXCR + - name: PDCRA + description: Power Port A pull-down control register + byte_offset: 36 + fieldset: PXCR + - name: PUCRB + description: Power Port B pull-up control register + byte_offset: 40 + fieldset: PXCR + - name: PDCRB + description: Power Port B pull-down control register + byte_offset: 44 + fieldset: PXCR + - name: PUCRC + description: Power Port C pull-up control register + byte_offset: 48 + fieldset: PXCR + - name: PDCRC + description: Power Port C pull-down control register + byte_offset: 52 + fieldset: PXCR + - name: PUCRD + description: Power Port D pull-up control register + byte_offset: 56 + fieldset: PXCR + - name: PDCRD + description: Power Port D pull-down control register + byte_offset: 60 + fieldset: PXCR + - name: PUCRE + description: Power Port E pull-up control register + byte_offset: 64 + fieldset: PXCR + - name: PDCRE + description: Power Port E pull-down control register + byte_offset: 68 + fieldset: PXCR + - name: PUCRH + description: Power Port H pull-up control register + byte_offset: 88 + fieldset: PXCR + - name: PDCRH + description: Power Port H pull-down control register + byte_offset: 92 + fieldset: PXCR + - name: C2CR1 + description: CPU2 Power control register 1 + byte_offset: 128 + fieldset: C2CR1 + - name: C2CR3 + description: CPU2 Power control register 3 + byte_offset: 132 + fieldset: C2CR3 + - name: EXTSCR + description: Power status clear register + byte_offset: 136 + fieldset: EXTSCR fieldset/C2CR1: description: CPU2 Power control register 1 fields: - - name: LPMS - description: Low-power mode selection for CPU2 - bit_offset: 0 - bit_size: 3 - - name: FPDR - description: Flash power down mode during LPRun for CPU2 - bit_offset: 4 - bit_size: 1 - - name: FPDS - description: Flash power down mode during LPSleep for CPU2 - bit_offset: 5 - bit_size: 1 - - name: BLEEWKUP - description: BLE external wakeup signal - bit_offset: 14 - bit_size: 1 - - name: _802EWKUP - description: 802.15.4 external wakeup signal - bit_offset: 15 - bit_size: 1 + - name: LPMS + description: Low-power mode selection for CPU2 + bit_offset: 0 + bit_size: 3 + - name: FPDR + description: Flash power down mode during LPRun for CPU2 + bit_offset: 4 + bit_size: 1 + - name: FPDS + description: Flash power down mode during LPSleep for CPU2 + bit_offset: 5 + bit_size: 1 + - name: BLEEWKUP + description: BLE external wakeup signal + bit_offset: 14 + bit_size: 1 + - name: _802EWKUP + description: 802.15.4 external wakeup signal + bit_offset: 15 + bit_size: 1 fieldset/C2CR3: description: CPU2 Power control register 3 fields: - - name: EWUP1 - description: Enable Wakeup pin WKUP1 for CPU2 - bit_offset: 0 - bit_size: 1 - - name: EWUP2 - description: Enable Wakeup pin WKUP2 for CPU2 - bit_offset: 1 - bit_size: 1 - - name: EWUP3 - description: Enable Wakeup pin WKUP3 for CPU2 - bit_offset: 2 - bit_size: 1 - - name: EWUP4 - description: Enable Wakeup pin WKUP4 for CPU2 - bit_offset: 3 - bit_size: 1 - - name: EWUP5 - description: Enable Wakeup pin WKUP5 for CPU2 - bit_offset: 4 - bit_size: 1 - - name: EBLEWUP - description: Enable BLE host wakeup interrupt for CPU2 - bit_offset: 9 - bit_size: 1 - - name: E802WUP - description: Enable 802.15.4 host wakeup interrupt for CPU2 - bit_offset: 10 - bit_size: 1 - - name: APC - description: Apply pull-up and pull-down configuration for CPU2 - bit_offset: 12 - bit_size: 1 - - name: EIWUL - description: Enable internal wakeup line for CPU2 - bit_offset: 15 - bit_size: 1 + - name: EWUP + description: Enable Wakeup pin + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: EBLEWUP + description: Enable BLE host wakeup interrupt for CPU2 + bit_offset: 9 + bit_size: 1 + - name: E802WUP + description: Enable 802.15.4 host wakeup interrupt for CPU2 + bit_offset: 10 + bit_size: 1 + - name: APC + description: Apply pull-up and pull-down configuration for CPU2 + bit_offset: 12 + bit_size: 1 + - name: EIWUL + description: Enable internal wakeup line for CPU2 + bit_offset: 15 + bit_size: 1 fieldset/CR1: description: Power control register 1 fields: - - name: LPMS - description: Low-power mode selection for CPU1 - bit_offset: 0 - bit_size: 3 - - name: FPDR - description: Flash power down mode during LPRun for CPU1 - bit_offset: 4 - bit_size: 1 - - name: FPDS - description: Flash power down mode during LPsSleep for CPU1 - bit_offset: 5 - bit_size: 1 - - name: DBP - description: Disable backup domain write protection - bit_offset: 8 - bit_size: 1 - - name: VOS - description: Voltage scaling range selection - bit_offset: 9 - bit_size: 2 - - name: LPR - description: Low-power run - bit_offset: 14 - bit_size: 1 + - name: LPMS + description: Low-power mode selection for CPU1 + bit_offset: 0 + bit_size: 3 + - name: FPDR + description: Flash power down mode during LPRun for CPU1 + bit_offset: 4 + bit_size: 1 + - name: FPDS + description: Flash power down mode during LPsSleep for CPU1 + bit_offset: 5 + bit_size: 1 + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: VOS + description: Voltage scaling range selection + bit_offset: 9 + bit_size: 2 + enum: VOS + - name: LPR + description: Low-power run + bit_offset: 14 + bit_size: 1 fieldset/CR2: description: Power control register 2 fields: - - name: PVDE - description: Power voltage detector enable - bit_offset: 0 - bit_size: 1 - - name: PLS - description: Power voltage detector level selection - bit_offset: 1 - bit_size: 3 - - name: PVME1 - description: "Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V" - bit_offset: 4 - bit_size: 1 - - name: PVME3 - description: "Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" - bit_offset: 6 - bit_size: 1 - - name: USV - description: VDDUSB USB supply valid - bit_offset: 10 - bit_size: 1 + - name: PVDE + description: Power voltage detector enable + bit_offset: 0 + bit_size: 1 + - name: PLS + description: Power voltage detector level selection + bit_offset: 1 + bit_size: 3 + - name: PVME1 + description: 'Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V' + bit_offset: 4 + bit_size: 1 + - name: PVME3 + description: 'Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V' + bit_offset: 6 + bit_size: 1 + - name: USV + description: VDDUSB USB supply valid + bit_offset: 10 + bit_size: 1 fieldset/CR3: description: Power control register 3 fields: - - name: EWUP1 - description: Enable Wakeup pin WKUP1 - bit_offset: 0 - bit_size: 1 - - name: EWUP2 - description: Enable Wakeup pin WKUP2 - bit_offset: 1 - bit_size: 1 - - name: EWUP3 - description: Enable Wakeup pin WKUP3 - bit_offset: 2 - bit_size: 1 - - name: EWUP4 - description: Enable Wakeup pin WKUP4 - bit_offset: 3 - bit_size: 1 - - name: EWUP5 - description: Enable Wakeup pin WKUP5 - bit_offset: 4 - bit_size: 1 - - name: EBORHSDFB - description: Enable BORH and Step Down counverter forced in Bypass interrups for CPU1 - bit_offset: 8 - bit_size: 1 - - name: RRS - description: SRAM2a retention in Standby mode - bit_offset: 9 - bit_size: 1 - - name: APC - description: Apply pull-up and pull-down configuration - bit_offset: 10 - bit_size: 1 - - name: EBLEA - description: Enable BLE end of activity interrupt for CPU1 - bit_offset: 11 - bit_size: 1 - - name: ECRPE - description: Enable critical radio phase end of activity interrupt for CPU1 - bit_offset: 12 - bit_size: 1 - - name: E802A - description: Enable end of activity interrupt for CPU1 - bit_offset: 13 - bit_size: 1 - - name: EC2H - description: Enable CPU2 Hold interrupt for CPU1 - bit_offset: 14 - bit_size: 1 - - name: EIWUL - description: Enable internal wakeup line for CPU1 - bit_offset: 15 - bit_size: 1 + - name: EWUP + description: Enable Wakeup pin + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: EBORHSDFB + description: Enable BORH and Step Down counverter forced in Bypass interrups for CPU1 + bit_offset: 8 + bit_size: 1 + - name: RRS + description: SRAM2a retention in Standby mode + bit_offset: 9 + bit_size: 1 + - name: APC + description: Apply pull-up and pull-down configuration + bit_offset: 10 + bit_size: 1 + - name: EBLEA + description: Enable BLE end of activity interrupt for CPU1 + bit_offset: 11 + bit_size: 1 + - name: ECRPE + description: Enable critical radio phase end of activity interrupt for CPU1 + bit_offset: 12 + bit_size: 1 + - name: E802A + description: Enable end of activity interrupt for CPU1 + bit_offset: 13 + bit_size: 1 + - name: EC2H + description: Enable CPU2 Hold interrupt for CPU1 + bit_offset: 14 + bit_size: 1 + - name: EIWUL + description: Enable internal wakeup line for CPU1 + bit_offset: 15 + bit_size: 1 fieldset/CR4: description: Power control register 4 fields: - - name: WP1 - description: Wakeup pin WKUP1 polarity - bit_offset: 0 - bit_size: 1 - - name: WP2 - description: Wakeup pin WKUP2 polarity - bit_offset: 1 - bit_size: 1 - - name: WP3 - description: Wakeup pin WKUP3 polarity - bit_offset: 2 - bit_size: 1 - - name: WP4 - description: Wakeup pin WKUP4 polarity - bit_offset: 3 - bit_size: 1 - - name: WP5 - description: Wakeup pin WKUP5 polarity - bit_offset: 4 - bit_size: 1 - - name: VBE - description: VBAT battery charging enable - bit_offset: 8 - bit_size: 1 - - name: VBRS - description: VBAT battery charging resistor selection - bit_offset: 9 - bit_size: 1 - - name: C2BOOT - description: BOOT CPU2 after reset or wakeup from Stop or Standby modes - bit_offset: 15 - bit_size: 1 + - name: WP1 + description: Wakeup pin WKUP1 polarity + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: VBE + description: VBAT battery charging enable + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT battery charging resistor selection + bit_offset: 9 + bit_size: 1 + - name: C2BOOT + description: BOOT CPU2 after reset or wakeup from Stop or Standby modes + bit_offset: 15 + bit_size: 1 fieldset/CR5: description: Power control register 5 fields: - - name: SDVOS - description: Step Down converter voltage output scaling - bit_offset: 0 - bit_size: 4 - - name: SDSC - description: Step Down converter supplt startup current selection - bit_offset: 4 - bit_size: 3 - - name: BORHC - description: BORH configuration selection - bit_offset: 8 - bit_size: 1 - - name: SMPSCFG - description: VOS configuration selection (non user) - bit_offset: 9 - bit_size: 1 - - name: SDBEN - description: Enable Step Down converter Bypass mode enabled - bit_offset: 14 - bit_size: 1 - - name: SDEB - description: Enable Step Down converter SMPS mode enabled - bit_offset: 15 - bit_size: 1 + - name: SDVOS + description: Step Down converter voltage output scaling + bit_offset: 0 + bit_size: 4 + - name: SDSC + description: Step Down converter supplt startup current selection + bit_offset: 4 + bit_size: 3 + - name: BORHC + description: BORH configuration selection + bit_offset: 8 + bit_size: 1 + - name: SMPSCFG + description: VOS configuration selection (non user) + bit_offset: 9 + bit_size: 1 + - name: SDBEN + description: Enable Step Down converter Bypass mode enabled + bit_offset: 14 + bit_size: 1 + - name: SDEB + description: Enable Step Down converter SMPS mode enabled + bit_offset: 15 + bit_size: 1 fieldset/EXTSCR: description: Power status clear register fields: - - name: C1CSSF - description: Clear CPU1 Stop Standby flags - bit_offset: 0 - bit_size: 1 - - name: C2CSSF - description: Clear CPU2 Stop Standby flags - bit_offset: 1 - bit_size: 1 - - name: CCRPF - description: Clear Critical Radio system phase - bit_offset: 2 - bit_size: 1 - - name: C1SBF - description: System Standby flag for CPU1 - bit_offset: 8 - bit_size: 1 - - name: C1STOPF - description: System Stop flag for CPU1 - bit_offset: 9 - bit_size: 1 - - name: C2SBF - description: System Standby flag for CPU2 - bit_offset: 10 - bit_size: 1 - - name: C2STOPF - description: System Stop flag for CPU2 - bit_offset: 11 - bit_size: 1 - - name: CRPF - description: Critical Radio system phase - bit_offset: 13 - bit_size: 1 - - name: C1DS - description: CPU1 deepsleep mode - bit_offset: 14 - bit_size: 1 - - name: C2DS - description: CPU2 deepsleep mode - bit_offset: 15 - bit_size: 1 -fieldset/PDCRA: - description: Power Port A pull-down control register + - name: C1CSSF + description: Clear CPU1 Stop Standby flags + bit_offset: 0 + bit_size: 1 + - name: C2CSSF + description: Clear CPU2 Stop Standby flags + bit_offset: 1 + bit_size: 1 + - name: CCRPF + description: Clear Critical Radio system phase + bit_offset: 2 + bit_size: 1 + - name: C1SBF + description: System Standby flag for CPU1 + bit_offset: 8 + bit_size: 1 + - name: C1STOPF + description: System Stop flag for CPU1 + bit_offset: 9 + bit_size: 1 + - name: C2SBF + description: System Standby flag for CPU2 + bit_offset: 10 + bit_size: 1 + - name: C2STOPF + description: System Stop flag for CPU2 + bit_offset: 11 + bit_size: 1 + - name: CRPF + description: Critical Radio system phase + bit_offset: 13 + bit_size: 1 + - name: C1DS + description: CPU1 deepsleep mode + bit_offset: 14 + bit_size: 1 + - name: C2DS + description: CPU2 deepsleep mode + bit_offset: 15 + bit_size: 1 +fieldset/PXCR: + description: Power Port pull-up/down control register fields: - - name: PD0 - description: Port A pull-down bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PD1 - description: Port A pull-down bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PD2 - description: Port A pull-down bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PD3 - description: Port A pull-down bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PD4 - description: Port A pull-down bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PD5 - description: Port A pull-down bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PD6 - description: Port A pull-down bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PD7 - description: Port A pull-down bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PD8 - description: Port A pull-down bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PD9 - description: Port A pull-down bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PD10 - description: Port A pull-down bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PD11 - description: Port A pull-down bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PD12 - description: Port A pull-down bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PD14 - description: Port A pull-down bit y (y=0..15) - bit_offset: 14 - bit_size: 1 -fieldset/PDCRB: - description: Power Port B pull-down control register - fields: - - name: PD0 - description: Port B pull-down bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PD1 - description: Port B pull-down bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PD2 - description: Port B pull-down bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PD3 - description: Port B pull-down bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PD5 - description: Port B pull-down bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PD6 - description: Port B pull-down bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PD7 - description: Port B pull-down bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PD8 - description: Port B pull-down bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PD9 - description: Port B pull-down bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PD10 - description: Port B pull-down bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PD11 - description: Port B pull-down bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PD12 - description: Port B pull-down bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PD13 - description: Port B pull-down bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PD14 - description: Port B pull-down bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PD15 - description: Port B pull-down bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PDCRC: - description: Power Port C pull-down control register - fields: - - name: PD0 - description: Port C pull-down bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PD1 - description: Port C pull-down bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PD2 - description: Port C pull-down bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PD3 - description: Port C pull-down bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PD4 - description: Port C pull-down bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PD5 - description: Port C pull-down bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PD6 - description: Port C pull-down bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PD7 - description: Port C pull-down bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PD8 - description: Port C pull-down bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PD9 - description: Port C pull-down bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PD10 - description: Port C pull-down bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PD11 - description: Port C pull-down bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PD12 - description: Port C pull-down bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PD13 - description: Port C pull-down bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PD14 - description: Port C pull-down bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PD15 - description: Port C pull-down bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PDCRD: - description: Power Port D pull-down control register - fields: - - name: PD0 - description: Port D pull-down bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PD1 - description: Port D pull-down bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PD2 - description: Port D pull-down bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PD3 - description: Port D pull-down bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PD4 - description: Port D pull-down bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PD5 - description: Port D pull-down bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PD6 - description: Port D pull-down bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PD7 - description: Port D pull-down bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PD8 - description: Port D pull-down bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PD9 - description: Port D pull-down bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PD10 - description: Port D pull-down bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PD11 - description: Port D pull-down bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PD12 - description: Port D pull-down bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PD13 - description: Port D pull-down bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PD14 - description: Port D pull-down bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PD15 - description: Port D pull-down bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PDCRE: - description: Power Port E pull-down control register - fields: - - name: PD0 - description: Port E pull-down bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PD1 - description: Port E pull-down bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PD2 - description: Port E pull-down bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PD3 - description: Port E pull-down bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PD4 - description: Port E pull-down bit y (y=0..15) - bit_offset: 4 - bit_size: 1 -fieldset/PDCRH: - description: Power Port H pull-down control register - fields: - - name: PD0 - description: Port H pull-down bit y (y=0..1) - bit_offset: 0 - bit_size: 1 - - name: PD1 - description: Port H pull-down bit y (y=0..1) - bit_offset: 1 - bit_size: 1 - - name: PD3 - description: Port H pull-down bit y (y=0..1) - bit_offset: 3 - bit_size: 1 -fieldset/PUCRA: - description: Power Port A pull-up control register - fields: - - name: PU0 - description: Port A pull-up bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PU1 - description: Port A pull-up bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PU2 - description: Port A pull-up bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PU3 - description: Port A pull-up bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PU4 - description: Port A pull-up bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PU5 - description: Port A pull-up bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PU6 - description: Port A pull-up bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PU7 - description: Port A pull-up bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PU8 - description: Port A pull-up bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PU9 - description: Port A pull-up bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PU10 - description: Port A pull-up bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PU11 - description: Port A pull-up bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PU12 - description: Port A pull-up bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PU13 - description: Port A pull-up bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PU15 - description: Port A pull-up bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PUCRB: - description: Power Port B pull-up control register - fields: - - name: PU0 - description: Port B pull-up bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PU1 - description: Port B pull-up bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PU2 - description: Port B pull-up bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PU3 - description: Port B pull-up bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PU4 - description: Port B pull-up bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PU5 - description: Port B pull-up bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PU6 - description: Port B pull-up bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PU7 - description: Port B pull-up bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PU8 - description: Port B pull-up bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PU9 - description: Port B pull-up bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PU10 - description: Port B pull-up bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PU11 - description: Port B pull-up bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PU12 - description: Port B pull-up bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PU13 - description: Port B pull-up bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PU14 - description: Port B pull-up bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PU15 - description: Port B pull-up bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PUCRC: - description: Power Port C pull-up control register - fields: - - name: PU0 - description: Port C pull-up bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PU1 - description: Port C pull-up bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PU2 - description: Port C pull-up bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PU3 - description: Port C pull-up bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PU4 - description: Port C pull-up bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PU5 - description: Port C pull-up bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PU6 - description: Port C pull-up bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PU7 - description: Port C pull-up bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PU8 - description: Port C pull-up bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PU9 - description: Port C pull-up bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PU10 - description: Port C pull-up bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PU11 - description: Port C pull-up bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PU12 - description: Port C pull-up bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PU13 - description: Port C pull-up bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PU14 - description: Port C pull-up bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PU15 - description: Port C pull-up bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PUCRD: - description: Power Port D pull-up control register - fields: - - name: PU0 - description: Port D pull-up bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PU1 - description: Port D pull-up bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PU2 - description: Port D pull-up bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PU3 - description: Port D pull-up bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PU4 - description: Port D pull-up bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PU5 - description: Port D pull-up bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PU6 - description: Port D pull-up bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PU7 - description: Port D pull-up bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PU8 - description: Port D pull-up bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PU9 - description: Port D pull-up bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PU10 - description: Port D pull-up bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PU11 - description: Port D pull-up bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PU12 - description: Port D pull-up bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PU13 - description: Port D pull-up bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PU14 - description: Port D pull-up bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PU15 - description: Port D pull-up bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PUCRE: - description: Power Port E pull-up control register - fields: - - name: PU0 - description: Port E pull-up bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PU1 - description: Port E pull-up bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PU2 - description: Port E pull-up bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PU3 - description: Port E pull-up bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PU4 - description: Port E pull-up bit y (y=0..15) - bit_offset: 4 - bit_size: 1 -fieldset/PUCRH: - description: Power Port H pull-up control register - fields: - - name: PU0 - description: Port H pull-up bit y (y=0..1) - bit_offset: 0 - bit_size: 1 - - name: PU1 - description: Port H pull-up bit y (y=0..1) - bit_offset: 1 - bit_size: 1 - - name: PU3 - description: Port H pull-up bit y (y=0..1) - bit_offset: 3 - bit_size: 1 + - name: PD + description: Port A pull-up/down bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 fieldset/SCR: description: Power status clear register fields: - - name: CWUF1 - description: Clear wakeup flag 1 - bit_offset: 0 - bit_size: 1 - - name: CWUF2 - description: Clear wakeup flag 2 - bit_offset: 1 - bit_size: 1 - - name: CWUF3 - description: Clear wakeup flag 3 - bit_offset: 2 - bit_size: 1 - - name: CWUF4 - description: Clear wakeup flag 4 - bit_offset: 3 - bit_size: 1 - - name: CWUF5 - description: Clear wakeup flag 5 - bit_offset: 4 - bit_size: 1 - - name: CSMPSFBF - description: Clear SMPS Step Down converter forced in Bypass interrupt flag - bit_offset: 7 - bit_size: 1 - - name: CBORHF - description: Clear BORH interrupt flag - bit_offset: 8 - bit_size: 1 - - name: CBLEWUF - description: Clear BLE wakeup interrupt flag - bit_offset: 9 - bit_size: 1 - - name: C802WUF - description: Clear 802.15.4 wakeup interrupt flag - bit_offset: 10 - bit_size: 1 - - name: CCRPEF - description: Clear critical radio phase end of activity interrupt flag - bit_offset: 11 - bit_size: 1 - - name: CBLEAF - description: Clear BLE end of activity interrupt flag - bit_offset: 12 - bit_size: 1 - - name: C802AF - description: Clear 802.15.4 end of activity interrupt flag - bit_offset: 13 - bit_size: 1 - - name: CC2HF - description: Clear CPU2 Hold interrupt flag - bit_offset: 14 - bit_size: 1 + - name: CWUF + description: Clear wakeup flag 1 + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: CSMPSFBF + description: Clear SMPS Step Down converter forced in Bypass interrupt flag + bit_offset: 7 + bit_size: 1 + - name: CBORHF + description: Clear BORH interrupt flag + bit_offset: 8 + bit_size: 1 + - name: CBLEWUF + description: Clear BLE wakeup interrupt flag + bit_offset: 9 + bit_size: 1 + - name: C802WUF + description: Clear 802.15.4 wakeup interrupt flag + bit_offset: 10 + bit_size: 1 + - name: CCRPEF + description: Clear critical radio phase end of activity interrupt flag + bit_offset: 11 + bit_size: 1 + - name: CBLEAF + description: Clear BLE end of activity interrupt flag + bit_offset: 12 + bit_size: 1 + - name: C802AF + description: Clear 802.15.4 end of activity interrupt flag + bit_offset: 13 + bit_size: 1 + - name: CC2HF + description: Clear CPU2 Hold interrupt flag + bit_offset: 14 + bit_size: 1 fieldset/SR1: description: Power status register 1 fields: - - name: CWUF1 - description: Wakeup flag 1 - bit_offset: 0 - bit_size: 1 - - name: CWUF2 - description: Wakeup flag 2 - bit_offset: 1 - bit_size: 1 - - name: CWUF3 - description: Wakeup flag 3 - bit_offset: 2 - bit_size: 1 - - name: CWUF4 - description: Wakeup flag 4 - bit_offset: 3 - bit_size: 1 - - name: CWUF5 - description: Wakeup flag 5 - bit_offset: 4 - bit_size: 1 - - name: SDFBF - description: Step Down converter forced in Bypass interrupt flag - bit_offset: 7 - bit_size: 1 - - name: BORHF - description: BORH interrupt flag - bit_offset: 8 - bit_size: 1 - - name: BLEWUF - description: BLE wakeup interrupt flag - bit_offset: 9 - bit_size: 1 - - name: _802WUF - description: 802.15.4 wakeup interrupt flag - bit_offset: 10 - bit_size: 1 - - name: CRPEF - description: Enable critical radio phase end of activity interrupt flag - bit_offset: 11 - bit_size: 1 - - name: BLEAF - description: BLE end of activity interrupt flag - bit_offset: 12 - bit_size: 1 - - name: AF802 - description: 802.15.4 end of activity interrupt flag - bit_offset: 13 - bit_size: 1 - - name: C2HF - description: CPU2 Hold interrupt flag - bit_offset: 14 - bit_size: 1 - - name: WUFI - description: Internal Wakeup interrupt flag - bit_offset: 15 - bit_size: 1 + - name: CWUF + description: Wakeup flag 1 + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + - name: SDFBF + description: Step Down converter forced in Bypass interrupt flag + bit_offset: 7 + bit_size: 1 + - name: BORHF + description: BORH interrupt flag + bit_offset: 8 + bit_size: 1 + - name: BLEWUF + description: BLE wakeup interrupt flag + bit_offset: 9 + bit_size: 1 + - name: _802WUF + description: 802.15.4 wakeup interrupt flag + bit_offset: 10 + bit_size: 1 + - name: CRPEF + description: Enable critical radio phase end of activity interrupt flag + bit_offset: 11 + bit_size: 1 + - name: BLEAF + description: BLE end of activity interrupt flag + bit_offset: 12 + bit_size: 1 + - name: AF802 + description: 802.15.4 end of activity interrupt flag + bit_offset: 13 + bit_size: 1 + - name: C2HF + description: CPU2 Hold interrupt flag + bit_offset: 14 + bit_size: 1 + - name: WUFI + description: Internal Wakeup interrupt flag + bit_offset: 15 + bit_size: 1 fieldset/SR2: description: Power status register 2 fields: - - name: SDBF - description: Step Down converter Bypass mode flag - bit_offset: 0 - bit_size: 1 - - name: SDSMPSF - description: Step Down converter SMPS mode flag - bit_offset: 1 - bit_size: 1 - - name: REGLPS - description: Low-power regulator started - bit_offset: 8 - bit_size: 1 - - name: REGLPF - description: Low-power regulator flag - bit_offset: 9 - bit_size: 1 - - name: VOSF - description: Voltage scaling flag - bit_offset: 10 - bit_size: 1 - - name: PVDO - description: Power voltage detector output - bit_offset: 11 - bit_size: 1 - - name: PVMO1 - description: "Peripheral voltage monitoring output: VDDUSB vs. 1.2 V" - bit_offset: 12 - bit_size: 1 - - name: PVMO3 - description: "Peripheral voltage monitoring output: VDDA vs. 1.62 V" - bit_offset: 14 - bit_size: 1 + - name: SDBF + description: Step Down converter Bypass mode flag + bit_offset: 0 + bit_size: 1 + - name: SDSMPSF + description: Step Down converter SMPS mode flag + bit_offset: 1 + bit_size: 1 + - name: REGLPS + description: Low-power regulator started + bit_offset: 8 + bit_size: 1 + - name: REGLPF + description: Low-power regulator flag + bit_offset: 9 + bit_size: 1 + - name: VOSF + description: Voltage scaling flag + bit_offset: 10 + bit_size: 1 + - name: PVDO + description: Power voltage detector output + bit_offset: 11 + bit_size: 1 + - name: PVMO1 + description: 'Peripheral voltage monitoring output: VDDUSB vs. 1.2 V' + bit_offset: 12 + bit_size: 1 + - name: PVMO3 + description: 'Peripheral voltage monitoring output: VDDA vs. 1.62 V' + bit_offset: 14 + bit_size: 1 +enum/VOS: + bit_size: 2 + variants: + - name: Range1 + description: Range 1 + value: 1 + - name: Range2 + description: Range 2 + value: 2 diff --git a/data/registers/pwr_wba.yaml b/data/registers/pwr_wba.yaml new file mode 100644 index 0000000..b1d12af --- /dev/null +++ b/data/registers/pwr_wba.yaml @@ -0,0 +1,537 @@ +block/PWR: + description: Power control + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: control register 3 + byte_offset: 8 + fieldset: CR3 + - name: VOSR + description: voltage scaling register + byte_offset: 12 + fieldset: VOSR + - name: SVMCR + description: supply voltage monitoring control register + byte_offset: 16 + fieldset: SVMCR + - name: WUCR1 + description: wakeup control register 1 + byte_offset: 20 + fieldset: WUCR1 + - name: WUCR2 + description: wakeup control register 2 + byte_offset: 24 + fieldset: WUCR2 + - name: WUCR3 + description: wakeup control register 3 + byte_offset: 28 + fieldset: WUCR3 + - name: DBPR + description: disable Backup domain register + byte_offset: 40 + fieldset: DBPR + - name: SECCFGR + description: security configuration register + byte_offset: 48 + fieldset: SECCFGR + - name: PRIVCFGR + description: privilege control register + byte_offset: 52 + fieldset: PRIVCFGR + - name: SR + description: status register + byte_offset: 56 + fieldset: SR + - name: SVMSR + description: supply voltage monitoring status register + byte_offset: 60 + fieldset: SVMSR + - name: WUSR + description: wakeup status register + byte_offset: 68 + fieldset: WUSR + - name: WUSCR + description: wakeup status clear register + byte_offset: 72 + fieldset: WUSCR + - name: IORETENR + description: port Standby IO retention enable register + array: + len: 8 + stride: 8 + byte_offset: 80 + fieldset: IORETENR + - name: IORETRA + description: port Standby IO retention status register + array: + len: 8 + stride: 8 + byte_offset: 84 + fieldset: IORETR + - name: RADIOSCR + description: 2.4 GHz RADIO status and control register + byte_offset: 256 + fieldset: RADIOSCR +fieldset/CR1: + description: control register 1 + fields: + - name: LPMS + description: "Low-power mode selection\r These bits select the low-power mode entered when the CPU enters the SleepDeep mode.\r 10x: Standby mode\r others reserved" + bit_offset: 0 + bit_size: 3 + enum: LPMS + - name: R2RSB1 + description: "SRAM2 retention in Standby mode\r This bit is used to keep the SRAM2 content in Standby retention mode." + bit_offset: 5 + bit_size: 1 + enum: RRSB + - name: ULPMEN + description: "BOR0 ultra-low-power mode. \r This bit is used to reduce the consumption by configuring the BOR0 in discontinuous mode for Stop 1 and Standby modes. Discontinuous mode is only available when BOR levels 1 to 4 and PVD are disabled.\r Note: This bit must be set to reach the lowest power consumption in the low-power modes.\r Note: This bit must not be set together with autonomous peripherals using HSI16 as kernel clock.\r Note: When BOR level 1 to 4 or PVD is enabled continuous mode applies independent from ULPMEN." + bit_offset: 7 + bit_size: 1 + - name: RADIORSB + description: "2.4 GHz RADIO SRAMs (RXTXRAM and Sequence RAM) and Sleep clock retention in Standby mode.\r This bit is used to keep the 2.4 GHz RADIO SRAMs content in Standby retention mode and the 2.4 GHz RADIO sleep timer counter operational." + bit_offset: 9 + bit_size: 1 + enum: RADIORSB + - name: R1RSB1 + description: "SRAM1 retention in Standby mode\r This bit is used to keep the SRAM1 content in Standby retention mode." + bit_offset: 12 + bit_size: 1 + enum: RRSB +fieldset/CR2: + description: control register 2 + fields: + - name: SRAM1PDS1 + description: "SRAM1 power-down in Stop modes (Stop 0, 1)\r Note: The SRAM1 retention in Standby mode is controlled by R1RSB1 bit in CR1." + bit_offset: 0 + bit_size: 1 + enum: SRAMPDS + - name: SRAM2PDS1 + description: "SRAM2 power-down in Stop modes (Stop 0, 1)\r Note: The SRAM2 retention in Standby mode is controlled by R2RSB1 bit in CR1." + bit_offset: 4 + bit_size: 1 + enum: SRAMPDS + - name: ICRAMPDS + description: ICACHE SRAM power-down in Stop modes (Stop 0, 1) + bit_offset: 8 + bit_size: 1 + enum: ICRAMPDS + - name: FLASHFWU + description: "Flash memory fast wakeup from Stop modes (Stop 0, 1)\r This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.\r When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption." + bit_offset: 14 + bit_size: 1 + enum: FLASHFWU +fieldset/CR3: + description: control register 3 + fields: + - name: FSTEN + description: Fast soft start + bit_offset: 2 + bit_size: 1 +fieldset/DBPR: + description: disable Backup domain register + fields: + - name: DBP + description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers." + bit_offset: 0 + bit_size: 1 +fieldset/IORETENR: + description: port A Standby IO retention enable register + fields: + - name: EN + description: "Port A Standby GPIO retention enable\r Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV.\r When set, each bit enables the Standby GPIO retention feature for PAy" + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 +fieldset/IORETR: + description: port A Standby IO retention status register + fields: + - name: RET + description: "Port A Standby GPIO retention active\r Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV." + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 +fieldset/PRIVCFGR: + description: privilege control register + fields: + - name: SPRIV + description: "secure functions privilege configuration\r This bit is set and reset by software.\r It can be written only by a secure privileged access." + bit_offset: 0 + bit_size: 1 + enum: PRIV + - name: NSPRIV + description: "non-secure functions privilege configuration\r This bit is set and reset by software.\r It can be written only by privileged access, secure or non-secure." + bit_offset: 1 + bit_size: 1 + enum: PRIV +fieldset/RADIOSCR: + description: 2.4 GHz RADIO status and control register + fields: + - name: MODE + description: "2.4 GHz RADIO operating mode.\r 1x: 2.4 GHz RADIO active mode" + bit_offset: 0 + bit_size: 2 + enum: MODE + - name: PHYMODE + description: 2.4 GHz RADIO PHY operating mode + bit_offset: 2 + bit_size: 1 + - name: ENCMODE + description: 2.4 GHz RADIO encryption function operating mode + bit_offset: 3 + bit_size: 1 + - name: RFVDDHPA + description: "2.4 GHz RADIO VDDHPA control word.\r Bits [3:0] see Table 81: PA output power table format for definition.\r Bit [4] rf_event." + bit_offset: 8 + bit_size: 5 + - name: REGPARDYVDDRFPA + description: "Ready bit for VDDHPA voltage level when selecting VDDRFPA input.\r Note: REGPARDYVDDRFPA does not allow to detect correct VDDHPA voltage level when request to lower the level." + bit_offset: 15 + bit_size: 1 + enum: REGPARDYVDDRFPA +fieldset/SECCFGR: + description: security configuration register + fields: + - name: WUP1SEC + description: WUP1 secure protection + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 + enum: SEC + - name: LPMSEC + description: Low-power modes secure protection + bit_offset: 12 + bit_size: 1 + enum: SEC + - name: VDMSEC + description: Voltage detection secure protection + bit_offset: 13 + bit_size: 1 + enum: SEC + - name: VBSEC + description: Backup domain secure protection + bit_offset: 14 + bit_size: 1 + enum: SEC +fieldset/SR: + description: status register + fields: + - name: CSSF + description: "Clear Stop and Standby flags\r Access can be secured by LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r Writing 1 to this bit clears the STOPF and SBF flags." + bit_offset: 0 + bit_size: 1 + - name: STOPF + description: "Stop flag\r This bit is set by hardware when the device enters a Stop or Standby mode at the same time as the sysclk has been set by hardware to select HSI16. It’s cleared by software by writing 1 to the CSSF bit and by hardware when SBF is set." + bit_offset: 1 + bit_size: 1 + - name: SBF + description: "Standby flag\r This bit is set by hardware when the device enters the Standby mode and the CPU restart from its reset vector. It’s cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset." + bit_offset: 2 + bit_size: 1 +fieldset/SVMCR: + description: supply voltage monitoring control register + fields: + - name: PVDE + description: Programmable voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PVDLS + description: "Programmable voltage detector level selection\r These bits select the voltage threshold detected by the programmable voltage detector:" + bit_offset: 5 + bit_size: 3 + enum: PVDLS +fieldset/SVMSR: + description: supply voltage monitoring status register + fields: + - name: PVDO + description: Programmable voltage detector output + bit_offset: 4 + bit_size: 1 + enum: PVDO + - name: ACTVOSRDY + description: Voltage level ready for currently used VOS + bit_offset: 15 + bit_size: 1 + - name: ACTVOS + description: "VOS currently applied to VCORE\r This field provides the last VOS value." + bit_offset: 16 + bit_size: 1 + enum: ACTVOS +fieldset/VOSR: + description: voltage scaling register + fields: + - name: VOSRDY + description: "Ready bit for VCORE voltage scaling output selection\r Set and cleared by hardware. When decreasing the voltage scaling range, VOSRDY must be one before increasing the SYSCLK frequency." + bit_offset: 15 + bit_size: 1 + - name: VOS + description: "Voltage scaling range selection\r Set a and cleared by software.\r Cleared by hardware when entering Stop 1 mode.\r Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 16 + bit_size: 1 + enum: VOS +fieldset/WUCR1: + description: wakeup control register 1 + fields: + - name: WUPEN + description: "Wakeup and interrupt pin WKUP1 enable\r Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 +fieldset/WUCR2: + description: wakeup control register 2 + fields: + - name: WUPP + description: "Wakeup pin WKUP1 polarity.\r This bit must be configured when WUPEN1 = 0.\r Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 + enum: WUPP +fieldset/WUCR3: + description: wakeup control register 3 + fields: + - name: WUSEL1 + description: "Wakeup and interrupt pin WKUP1 selection\r This field must be configured when WUPEN1 = 0.\r Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 0 + bit_size: 2 + enum: WUSEL + - name: WUSEL2 + description: "Wakeup and interrupt pin WKUP2 selection\r This field must be configured when WUPEN2 = 0.\r Access can be secured by WUP2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 2 + bit_size: 2 + enum: WUSEL + - name: WUSEL3 + description: "Wakeup and interrupt pin WKUP3 selection\r This field must be configured when WUPEN3 = 0.\r Access can be secured by WUP3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 4 + bit_size: 2 + enum: WUSEL + - name: WUSEL4 + description: "Wakeup and interrupt pin WKUP4 selection\r This field must be configured when WUPEN4 = 0.\r Access can be secured by WUP4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 6 + bit_size: 2 + enum: WUSEL + - name: WUSEL5 + description: "Wakeup and interrupt pin WKUP5 selection\r This field must be configured when WUPEN5 = 0.\r Access can be secured by WUP5SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 8 + bit_size: 2 + enum: WUSEL + - name: WUSEL6 + description: "Wakeup and interrupt pin WKUP6 selection\r This field must be configured when WUPEN6 = 0.\r Access can be secured by WUP6SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 10 + bit_size: 2 + enum: WUSEL + - name: WUSEL7 + description: "Wakeup and interrupt pin WKUP7 selection\r This field must be configured when WUPEN7 = 0.\r Access can be secured by WUP7SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 12 + bit_size: 2 + enum: WUSEL + - name: WUSEL8 + description: "Wakeup and interrupt pin WKUP8 selection\r This field must be configured when WUPEN8 = 0.\r Access can be secured by WUP8SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 14 + bit_size: 2 + enum: WUSEL +fieldset/WUSCR: + description: wakeup status clear register + fields: + - name: CWUF + description: "Clear wakeup flag 1\r Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r Writing 1 to this bit clears the WUF1 flag in WUSR." + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 +fieldset/WUSR: + description: wakeup status register + fields: + - name: WUF + description: "Wakeup and interrupt pending flag 1\r This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR or by hardware when WUPEN1 = 0." + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 +enum/ACTVOS: + bit_size: 1 + variants: + - name: Range2 + description: Range 2 (lowest power) + value: 0 + - name: Range1 + description: Range 1 (highest frequency) + value: 1 +enum/FLASHFWU: + bit_size: 1 + variants: + - name: LowPower + description: Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption). + value: 0 + - name: Normal + description: Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time). + value: 1 +enum/ICRAMPDS: + bit_size: 1 + variants: + - name: Retained + description: ICACHE SRAM content retained in Stop modes + value: 0 + - name: NotRetained + description: ICACHE SRAM content lost in Stop modes + value: 1 +enum/LPMS: + bit_size: 3 + variants: + - name: Stop0 + description: Stop 0 mode + value: 0 + - name: Stop1 + description: Stop 1 mode + value: 1 +enum/MODE: + bit_size: 2 + variants: + - name: DeepSleep + description: 2.4 GHz RADIO deep sleep mode + value: 0 + - name: Sleep + description: 2.4 GHz RADIO sleep mode + value: 1 +enum/PRIV: + bit_size: 1 + variants: + - name: Unprivileged + description: Read and write to non-secure functions can be done by privileged or unprivileged access. + value: 0 + - name: Privileged + description: Read and write to non-secure functions can be done by privileged access only. + value: 1 +enum/PVDLS: + bit_size: 3 + variants: + - name: v20 + description: VPVD0 around 2.0 V + value: 0 + - name: v22 + description: VPVD1 around 2.2 V + value: 1 + - name: v24 + description: VPVD2 around 2.4 V + value: 2 + - name: v25 + description: VPVD3 around 2.5 V + value: 3 + - name: v26 + description: VPVD4 around 2.6 V + value: 4 + - name: v28 + description: VPVD5 around 2.8 V + value: 5 + - name: v29 + description: VPVD6 around 2.9 V + value: 6 + - name: pvd_in + description: External input analog voltage PVD_IN (compared internally to VREFINT) + value: 7 +enum/PVDO: + bit_size: 1 + variants: + - name: AboveOrEqual + description: VDD is equal or above the PVD threshold selected by PVDLS[2:0]. + value: 0 + - name: Below + description: VDD is below the PVD threshold selected by PVDLS[2:0]. + value: 1 +enum/RADIORSB: + bit_size: 1 + variants: + - name: NotRetained + description: 2.4 GHz RADIO SRAMs and sleep timer content not retained in Standby mode + value: 0 + - name: Retained + description: 2.4 GHz RADIO SRAMs and sleep timer content retained in Standby mode + value: 1 +enum/REGPARDYVDDRFPA: + bit_size: 1 + variants: + - name: NotReady + description: Not ready, VDDHPA voltage level < REGPAVOS selected supply level + value: 0 + - name: Ready + description: Ready, VDDHPA voltage level ≥ REGPAVOS selected supply level + value: 1 +enum/RRSB: + bit_size: 1 + variants: + - name: B_0x0 + description: SRAM2 content not retained in Standby mode + value: 0 + - name: B_0x1 + description: SRAM2 content retained in Standby mode + value: 1 +enum/SEC: + bit_size: 1 + variants: + - name: NotSecure + description: SVMCR and CR3 can be read and written with secure or non-secure access. + value: 0 + - name: Secure + description: SVMCR and CR3 can be read and written only with secure access. + value: 1 +enum/SRAMPDS: + bit_size: 1 + variants: + - name: PoweredOn + description: SRAM1 content retained in Stop modes + value: 0 + - name: PoweredOff + description: SRAM1 content lost in Stop modes + value: 1 +enum/VOS: + bit_size: 1 + variants: + - name: Range2 + description: Range 2 (lowest power) + value: 0 + - name: Range1 + description: Range 1 (highest frequency). + value: 1 +enum/WUPP: + bit_size: 1 + variants: + - name: High + description: Detection on high level (rising edge) + value: 0 + - name: Low + description: Detection on low level (falling edge) + value: 1 +enum/WUSEL: + bit_size: 2 + variants: + - name: B_0x0 + description: reserved + value: 0 + - name: B_0x1 + description: WKUP3_1 + value: 1 + - name: B_0x2 + description: WKUP3_2 + value: 2 + - name: B_0x3 + description: reserved + value: 3 diff --git a/data/registers/pwr_wl5.yaml b/data/registers/pwr_wl5.yaml index 858653a..fc1cd2f 100644 --- a/data/registers/pwr_wl5.yaml +++ b/data/registers/pwr_wl5.yaml @@ -1,892 +1,550 @@ ---- block/PWR: description: Power control items: - - name: CR1 - description: Power control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Power control register 2 - byte_offset: 4 - fieldset: CR2 - - name: CR3 - description: Power control register 3 - byte_offset: 8 - fieldset: CR3 - - name: CR4 - description: Power control register 4 - byte_offset: 12 - fieldset: CR4 - - name: SR1 - description: Power status register 1 - byte_offset: 16 - access: Read - fieldset: SR1 - - name: SR2 - description: Power status register 2 - byte_offset: 20 - access: Read - fieldset: SR2 - - name: SCR - description: Power status clear register - byte_offset: 24 - access: Write - fieldset: SCR - - name: CR5 - description: Power control register 5 - byte_offset: 28 - fieldset: CR5 - - name: PUCR - description: Power Port pull-up control register - array: - len: 8 - stride: 8 - byte_offset: 32 - fieldset: PCR - - name: PDCR - description: Power Port pull-down control register - array: - len: 8 - stride: 8 - byte_offset: 36 - fieldset: PCR - - name: C2CR1 - description: "Power CPU2 control register 1 [dual core device only]" - byte_offset: 128 - fieldset: C2CR1 - - name: C2CR3 - description: "Power CPU2 control register 3 [dual core device only]" - byte_offset: 132 - fieldset: C2CR3 - - name: EXTSCR - description: Power extended status and status clear register - byte_offset: 136 - fieldset: EXTSCR - - name: SECCFGR - description: "Power security configuration register [dual core device only]" - byte_offset: 140 - fieldset: SECCFGR - - name: SUBGHZSPICR - description: Power SPI3 control register - byte_offset: 144 - fieldset: SUBGHZSPICR - - name: RSSCMDR - description: "RSS Command register [dual core device only]" - byte_offset: 152 - fieldset: RSSCMDR + - name: CR1 + description: Power control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Power control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: Power control register 3 + byte_offset: 8 + fieldset: CR3 + - name: CR4 + description: Power control register 4 + byte_offset: 12 + fieldset: CR4 + - name: SR1 + description: Power status register 1 + byte_offset: 16 + access: Read + fieldset: SR1 + - name: SR2 + description: Power status register 2 + byte_offset: 20 + access: Read + fieldset: SR2 + - name: SCR + description: Power status clear register + byte_offset: 24 + access: Write + fieldset: SCR + - name: CR5 + description: Power control register 5 + byte_offset: 28 + fieldset: CR5 + - name: PUCR + description: Power Port pull-up control register + array: + len: 8 + stride: 8 + byte_offset: 32 + fieldset: PCR + - name: PDCR + description: Power Port pull-down control register + array: + len: 8 + stride: 8 + byte_offset: 36 + fieldset: PCR + - name: C2CR1 + description: Power CPU2 control register 1 [dual core device only] + byte_offset: 128 + fieldset: C2CR1 + - name: C2CR3 + description: Power CPU2 control register 3 [dual core device only] + byte_offset: 132 + fieldset: C2CR3 + - name: EXTSCR + description: Power extended status and status clear register + byte_offset: 136 + fieldset: EXTSCR + - name: SECCFGR + description: Power security configuration register [dual core device only] + byte_offset: 140 + fieldset: SECCFGR + - name: SUBGHZSPICR + description: Power SPI3 control register + byte_offset: 144 + fieldset: SUBGHZSPICR + - name: RSSCMDR + description: RSS Command register [dual core device only] + byte_offset: 152 + fieldset: RSSCMDR fieldset/C2CR1: - description: "Power CPU2 control register 1 [dual core device only]" + description: Power CPU2 control register 1 [dual core device only] fields: - - name: LPMS - description: Low-power mode selection for CPU2 - bit_offset: 0 - bit_size: 3 - - name: FPDR - description: Flash memory power down mode during LPRun for CPU2 - bit_offset: 4 - bit_size: 1 - - name: FPDS - description: Flash memory power down mode during LPSleep for CPU2 - bit_offset: 5 - bit_size: 1 + - name: LPMS + description: Low-power mode selection for CPU2 + bit_offset: 0 + bit_size: 3 + - name: FPDR + description: Flash memory power down mode during LPRun for CPU2 + bit_offset: 4 + bit_size: 1 + - name: FPDS + description: Flash memory power down mode during LPSleep for CPU2 + bit_offset: 5 + bit_size: 1 fieldset/C2CR3: - description: "Power CPU2 control register 3 [dual core device only]" + description: Power CPU2 control register 3 [dual core device only] fields: - - name: EWUP - description: Enable Wakeup pin WKUP1 for CPU2 - bit_offset: 0 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: EWPVD - description: Enable wakeup PVD for CPU2 - bit_offset: 8 - bit_size: 1 - - name: APC - description: Apply pull-up and pull-down configuration for CPU2 - bit_offset: 10 - bit_size: 1 - - name: EWRFBUSY - description: EWRFBUSY - bit_offset: 11 - bit_size: 1 - - name: EWRFIRQ - description: akeup for CPU2 - bit_offset: 13 - bit_size: 1 - - name: EIWUL - description: Enable internal wakeup line for CPU2 - bit_offset: 15 - bit_size: 1 + - name: EWUP + description: Enable Wakeup pin WKUP1 for CPU2 + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: EWPVD + description: Enable wakeup PVD for CPU2 + bit_offset: 8 + bit_size: 1 + - name: APC + description: Apply pull-up and pull-down configuration for CPU2 + bit_offset: 10 + bit_size: 1 + - name: EWRFBUSY + description: EWRFBUSY + bit_offset: 11 + bit_size: 1 + - name: EWRFIRQ + description: akeup for CPU2 + bit_offset: 13 + bit_size: 1 + - name: EIWUL + description: Enable internal wakeup line for CPU2 + bit_offset: 15 + bit_size: 1 fieldset/CR1: description: Power control register 1 fields: - - name: LPMS - description: Low-power mode selection for CPU1 - bit_offset: 0 - bit_size: 3 - enum: LPMS - - name: SUBGHZSPINSSSEL - description: sub-GHz SPI NSS source select - bit_offset: 3 - bit_size: 1 - enum: SUBGHZSPINSSSEL - - name: FPDR - description: Flash memory power down mode during LPRun for CPU1 - bit_offset: 4 - bit_size: 1 - enum: FPDR - - name: FPDS - description: Flash memory power down mode during LPSleep for CPU1 - bit_offset: 5 - bit_size: 1 - enum: FPDS - - name: DBP - description: Disable backup domain write protection - bit_offset: 8 - bit_size: 1 - enum: DBP - - name: VOS - description: Voltage scaling range selection - bit_offset: 9 - bit_size: 2 - enum: VOS - - name: LPR - description: Low-power run - bit_offset: 14 - bit_size: 1 - enum: LPR + - name: LPMS + description: Low-power mode selection for CPU1 + bit_offset: 0 + bit_size: 3 + enum: LPMS + - name: SUBGHZSPINSSSEL + description: sub-GHz SPI NSS source select + bit_offset: 3 + bit_size: 1 + enum: SUBGHZSPINSSSEL + - name: FPDR + description: Flash memory power down mode during LPRun for CPU1 + bit_offset: 4 + bit_size: 1 + enum: FPDR + - name: FPDS + description: Flash memory power down mode during LPSleep for CPU1 + bit_offset: 5 + bit_size: 1 + enum: FPDS + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: VOS + description: Voltage scaling range selection + bit_offset: 9 + bit_size: 2 + enum: VOS + - name: LPR + description: Low-power run + bit_offset: 14 + bit_size: 1 + enum: LPR fieldset/CR2: description: Power control register 2 fields: - - name: PVDE - description: Power voltage detector enable - bit_offset: 0 - bit_size: 1 - enum: PVDE - - name: PLS - description: Power voltage detector level selection. - bit_offset: 1 - bit_size: 3 - enum: PLS - - name: PVME - description: "Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" - bit_offset: 6 - bit_size: 1 - enum: PVME + - name: PVDE + description: Power voltage detector enable + bit_offset: 0 + bit_size: 1 + - name: PLS + description: Power voltage detector level selection. + bit_offset: 1 + bit_size: 3 + enum: PLS + - name: PVME + description: 'Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V' + bit_offset: 6 + bit_size: 1 fieldset/CR3: description: Power control register 3 fields: - - name: EWUP - description: Enable Wakeup pin WKUP1 for CPU1 - bit_offset: 0 - bit_size: 1 - array: - len: 3 - stride: 1 - enum: EWUP - - name: EULPEN - description: Ultra-low-power enable - bit_offset: 7 - bit_size: 1 - enum: EULPEN - - name: EWPVD - description: Enable wakeup PVD for CPU1 - bit_offset: 8 - bit_size: 1 - enum: EWPVD - - name: RRS - description: SRAM2 retention in Standby mode - bit_offset: 9 - bit_size: 1 - enum: RRS - - name: APC - description: Apply pull-up and pull-down configuration from CPU1 - bit_offset: 10 - bit_size: 1 - enum: APC - - name: EWRFBUSY - description: Enable Radio BUSY Wakeup from Standby for CPU1 - bit_offset: 11 - bit_size: 1 - enum: EWRFBUSY - - name: EWRFIRQ - description: akeup for CPU1 - bit_offset: 13 - bit_size: 1 - enum: EWRFIRQ - - name: EC2H - description: nable CPU2 Hold interrupt for CPU1 - bit_offset: 14 - bit_size: 1 - - name: EIWUL - description: Enable internal wakeup line for CPU1 - bit_offset: 15 - bit_size: 1 - enum: EIWUL + - name: EWUP + description: Enable Wakeup pin WKUP1 for CPU1 + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: EULPEN + description: Ultra-low-power enable + bit_offset: 7 + bit_size: 1 + - name: EWPVD + description: Enable wakeup PVD for CPU1 + bit_offset: 8 + bit_size: 1 + - name: RRS + description: SRAM2 retention in Standby mode + bit_offset: 9 + bit_size: 1 + - name: APC + description: Apply pull-up and pull-down configuration from CPU1 + bit_offset: 10 + bit_size: 1 + - name: EWRFBUSY + description: Enable Radio BUSY Wakeup from Standby for CPU1 + bit_offset: 11 + bit_size: 1 + - name: EWRFIRQ + description: Wakeup for CPU1 + bit_offset: 13 + bit_size: 1 + - name: EC2H + description: nable CPU2 Hold interrupt for CPU1 + bit_offset: 14 + bit_size: 1 + - name: EIWUL + description: Enable internal wakeup line for CPU1 + bit_offset: 15 + bit_size: 1 fieldset/CR4: description: Power control register 4 fields: - - name: WP - description: Wakeup pin WKUP1 polarity - bit_offset: 0 - bit_size: 1 - array: - len: 3 - stride: 1 - enum: WP - - name: VBE - description: VBAT battery charging enable - bit_offset: 8 - bit_size: 1 - enum: VBE - - name: VBRS - description: VBAT battery charging resistor selection - bit_offset: 9 - bit_size: 1 - enum: VBRS - - name: WRFBUSYP - description: Wakeup Radio BUSY polarity - bit_offset: 11 - bit_size: 1 - enum: WRFBUSYP - - name: C2BOOT - description: oot CPU2 after reset or wakeup from Stop or Standby modes. - bit_offset: 15 - bit_size: 1 + - name: WP + description: Wakeup pin WKUP1 polarity + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: WP + - name: VBE + description: VBAT battery charging enable + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT battery charging resistor selection + bit_offset: 9 + bit_size: 1 + enum: VBRS + - name: WRFBUSYP + description: Wakeup Radio BUSY polarity + bit_offset: 11 + bit_size: 1 + - name: C2BOOT + description: oot CPU2 after reset or wakeup from Stop or Standby modes. + bit_offset: 15 + bit_size: 1 fieldset/CR5: description: Power control register 5 fields: - - name: RFEOLEN - description: Enable Radio End Of Life detector enabled - bit_offset: 14 - bit_size: 1 - enum: RFEOLEN - - name: SMPSEN - description: Enable SMPS Step Down converter SMPS mode enabled. - bit_offset: 15 - bit_size: 1 - enum: SMPSEN + - name: RFEOLEN + description: Enable Radio End Of Life detector enabled + bit_offset: 14 + bit_size: 1 + - name: SMPSEN + description: Enable SMPS Step Down converter SMPS mode enabled. + bit_offset: 15 + bit_size: 1 fieldset/EXTSCR: description: Power extended status and status clear register fields: - - name: C1CSSF - description: Clear CPU1 Stop Standby flags - bit_offset: 0 - bit_size: 1 - - name: C2CSSF - description: lear CPU2 Stop Standby flags - bit_offset: 1 - bit_size: 1 - - name: C1SBF - description: System Standby flag for CPU1. (no core states retained) - bit_offset: 8 - bit_size: 1 - enum: CSBF - - name: C1STOP2F - description: System Stop2 flag for CPU1. (partial core states retained) - bit_offset: 9 - bit_size: 1 - enum: CSTOPF - - name: C1STOPF - description: "System Stop0, 1 flag for CPU1. (All core states retained)" - bit_offset: 10 - bit_size: 1 - enum: CSTOPF - - name: C2SBF - description: ystem Standby flag for CPU2. (no core states retained) - bit_offset: 11 - bit_size: 1 - - name: C2STOP2F - description: ystem Stop2 flag for CPU2. (partial core states retained) - bit_offset: 12 - bit_size: 1 - - name: C2STOPF - description: "ystem Stop0, 1 flag for CPU2. (All core states retained)" - bit_offset: 13 - bit_size: 1 - - name: C1DS - description: CPU1 deepsleep mode - bit_offset: 14 - bit_size: 1 - enum: CDS - - name: C2DS - description: PU2 deepsleep mode - bit_offset: 15 - bit_size: 1 + - name: C1CSSF + description: Clear CPU1 Stop Standby flags + bit_offset: 0 + bit_size: 1 + - name: C2CSSF + description: lear CPU2 Stop Standby flags + bit_offset: 1 + bit_size: 1 + - name: C1SBF + description: System Standby flag for CPU1. (no core states retained) + bit_offset: 8 + bit_size: 1 + - name: C1STOP2F + description: System Stop2 flag for CPU1. (partial core states retained) + bit_offset: 9 + bit_size: 1 + - name: C1STOPF + description: System Stop0, 1 flag for CPU1. (All core states retained) + bit_offset: 10 + bit_size: 1 + - name: C2SBF + description: ystem Standby flag for CPU2. (no core states retained) + bit_offset: 11 + bit_size: 1 + - name: C2STOP2F + description: ystem Stop2 flag for CPU2. (partial core states retained) + bit_offset: 12 + bit_size: 1 + - name: C2STOPF + description: ystem Stop0, 1 flag for CPU2. (All core states retained) + bit_offset: 13 + bit_size: 1 + - name: C1DS + description: CPU1 deepsleep mode + bit_offset: 14 + bit_size: 1 + enum: CDS + - name: C2DS + description: PU2 deepsleep mode + bit_offset: 15 + bit_size: 1 fieldset/PCR: description: Power Port pull control register fields: - - name: P - description: Port pull bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 + - name: P + description: Port pull bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 fieldset/RSSCMDR: - description: "RSS Command register [dual core device only]" + description: RSS Command register [dual core device only] fields: - - name: RSSCMD - description: RSS command - bit_offset: 0 - bit_size: 8 + - name: RSSCMD + description: RSS command + bit_offset: 0 + bit_size: 8 fieldset/SCR: description: Power status clear register fields: - - name: CWUF - description: Clear wakeup flag 1 - bit_offset: 0 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: CWPVDF - description: Clear wakeup PVD interrupt flag - bit_offset: 8 - bit_size: 1 - - name: CWRFBUSYF - description: Clear wakeup Radio BUSY flag - bit_offset: 11 - bit_size: 1 - - name: CC2HF - description: lear CPU2 Hold interrupt flag - bit_offset: 14 - bit_size: 1 + - name: CWUF + description: Clear wakeup flag 1 + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: CWPVDF + description: Clear wakeup PVD interrupt flag + bit_offset: 8 + bit_size: 1 + - name: CWRFBUSYF + description: Clear wakeup Radio BUSY flag + bit_offset: 11 + bit_size: 1 + - name: CC2HF + description: lear CPU2 Hold interrupt flag + bit_offset: 14 + bit_size: 1 fieldset/SECCFGR: - description: "Power security configuration register [dual core device only]" + description: Power security configuration register [dual core device only] fields: - - name: C2EWILA - description: wakeup on CPU2 illegal access interrupt enable - bit_offset: 15 - bit_size: 1 + - name: C2EWILA + description: wakeup on CPU2 illegal access interrupt enable + bit_offset: 15 + bit_size: 1 fieldset/SR1: description: Power status register 1 fields: - - name: WUF - description: Wakeup flag 1 - bit_offset: 0 - bit_size: 1 - array: - len: 3 - stride: 1 - enum: WUF - - name: WPVDF - description: Wakeup PVD flag - bit_offset: 8 - bit_size: 1 - enum: WPVDF - - name: WRFBUSYF - description: Radio BUSY wakeup flag - bit_offset: 11 - bit_size: 1 - enum: WRFBUSYF - - name: C2HF - description: PU2 Hold interrupt flag - bit_offset: 14 - bit_size: 1 - - name: WUFI - description: Internal wakeup interrupt flag - bit_offset: 15 - bit_size: 1 - enum: WUFI + - name: WUF + description: Wakeup flag 1 + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: WPVDF + description: Wakeup PVD flag + bit_offset: 8 + bit_size: 1 + - name: WRFBUSYF + description: Radio BUSY wakeup flag + bit_offset: 11 + bit_size: 1 + - name: C2HF + description: PU2 Hold interrupt flag + bit_offset: 14 + bit_size: 1 + - name: WUFI + description: Internal wakeup interrupt flag + bit_offset: 15 + bit_size: 1 fieldset/SR2: description: Power status register 2 fields: - - name: C2BOOTS - description: PU2 boot/wakeup request source information - bit_offset: 0 - bit_size: 1 - - name: RFBUSYS - description: Radio BUSY signal status - bit_offset: 1 - bit_size: 1 - enum: RFBUSYS - - name: RFBUSYMS - description: Radio BUSY masked signal status - bit_offset: 2 - bit_size: 1 - enum: RFBUSYMS - - name: SMPSRDY - description: SMPS ready flag - bit_offset: 3 - bit_size: 1 - enum: SMPSRDY - - name: LDORDY - description: LDO ready flag - bit_offset: 4 - bit_size: 1 - enum: LDORDY - - name: RFEOLF - description: Radio end of life flag - bit_offset: 5 - bit_size: 1 - enum: RFEOLF - - name: REGMRS - description: regulator2 low power flag - bit_offset: 6 - bit_size: 1 - enum: REGMRS - - name: FLASHRDY - description: Flash ready - bit_offset: 7 - bit_size: 1 - enum: FLASHRDY - - name: REGLPS - description: regulator1 started - bit_offset: 8 - bit_size: 1 - enum: REGLPS - - name: REGLPF - description: regulator1 low power flag - bit_offset: 9 - bit_size: 1 - enum: REGLPF - - name: VOSF - description: Voltage scaling flag - bit_offset: 10 - bit_size: 1 - enum: VOSF - - name: PVDO - description: Power voltage detector output - bit_offset: 11 - bit_size: 1 - enum: PVDO - - name: PVMO - description: "Peripheral voltage monitoring output: VDDA vs. 1.62 V" - bit_offset: 14 - bit_size: 1 - enum: PVMO + - name: C2BOOTS + description: PU2 boot/wakeup request source information + bit_offset: 0 + bit_size: 1 + - name: RFBUSYS + description: Radio BUSY signal status + bit_offset: 1 + bit_size: 1 + - name: RFBUSYMS + description: Radio BUSY masked signal status + bit_offset: 2 + bit_size: 1 + - name: SMPSRDY + description: SMPS ready flag + bit_offset: 3 + bit_size: 1 + - name: LDORDY + description: LDO ready flag + bit_offset: 4 + bit_size: 1 + - name: RFEOLF + description: Radio end of life flag + bit_offset: 5 + bit_size: 1 + - name: REGMRS + description: regulator2 low power flag + bit_offset: 6 + bit_size: 1 + - name: FLASHRDY + description: Flash ready + bit_offset: 7 + bit_size: 1 + - name: REGLPS + description: regulator1 started + bit_offset: 8 + bit_size: 1 + - name: REGLPF + description: regulator1 low power flag + bit_offset: 9 + bit_size: 1 + - name: VOSF + description: Voltage scaling flag + bit_offset: 10 + bit_size: 1 + - name: PVDO + description: Power voltage detector output + bit_offset: 11 + bit_size: 1 + - name: PVMO + description: 'Peripheral voltage monitoring output: VDDA vs. 1.62 V' + bit_offset: 14 + bit_size: 1 fieldset/SUBGHZSPICR: description: Power SPI3 control register fields: - - name: NSS - description: sub-GHz SPI NSS control - bit_offset: 15 - bit_size: 1 - enum: NSS -enum/APC: - bit_size: 1 - variants: - - name: Disabled - description: I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied - value: 0 - - name: Enabled - description: PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os - value: 1 + - name: NSS + description: sub-GHz SPI NSS control + bit_offset: 15 + bit_size: 1 enum/CDS: bit_size: 1 variants: - - name: RunningOrSleep - description: CPU is running or in sleep - value: 0 - - name: DeepSleep - description: CPU is in Deep-Sleep - value: 1 -enum/CSBF: - bit_size: 1 - variants: - - name: NoStandby - description: System has not been in Standby mode - value: 0 - - name: Standby - description: System has been in Standby mode - value: 1 -enum/CSTOPF: - bit_size: 1 - variants: - - name: NoStop - description: System has not been in Stop 2 mode - value: 0 - - name: Stop - description: System has been in Stop 2 mode - value: 1 -enum/DBP: - bit_size: 1 - variants: - - name: Disabled - description: Access to RTC and backup registers disabled - value: 0 - - name: Enabled - description: Access to RTC and backup registers enabled - value: 1 -enum/EIWUL: - bit_size: 1 - variants: - - name: Disabled - description: Internal wakeup line interrupt to CPU disabled - value: 0 - - name: Enabled - description: Internal wakeup line interrupt to CPU enabled - value: 1 -enum/EULPEN: - bit_size: 1 - variants: - - name: Disabled - description: Disable (the supply voltage is monitored continuously) - value: 0 - - name: Enabled - description: "Enable, when set, the supply voltage is sampled for PDR/BOR reset condition only periodically" - value: 1 -enum/EWPVD: - bit_size: 1 - variants: - - name: Disabled - description: PVD not enabled by the sub-GHz radio active state - value: 0 - - name: Enabled - description: PVD enabled while the sub-GHz radio is active - value: 1 -enum/EWRFBUSY: - bit_size: 1 - variants: - - name: Disabled - description: Radio Busy is disabled and does not trigger a wakeup from Standby event to CPUwhen a rising or a falling edge occurs - value: 0 - - name: Enabled - description: Radio Busy is enabled and triggers a wakeup from Standby event to CPUwhen a rising or a falling edge occurs. The active edge is configured via the WRFBUSYP bit in PWR_CR4 - value: 1 -enum/EWRFIRQ: - bit_size: 1 - variants: - - name: Disabled - description: "Radio IRQ[2:0] is disabled and does not trigger a wakeup from Standby event to CPU." - value: 0 - - name: Enabled - description: "Radio IRQ[2:0] is enabled and triggers a wakeup from Standby event to CPU." - value: 1 -enum/EWUP: - bit_size: 1 - variants: - - name: Disabled - description: WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode - value: 0 - - name: Enabled - description: WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode) - value: 1 -enum/FLASHRDY: - bit_size: 1 - variants: - - name: NotReady - description: Flash memory not ready to be accessed - value: 0 - - name: Ready - description: Flash memory ready to be accessed - value: 1 + - name: RunningOrSleep + description: CPU is running or in sleep + value: 0 + - name: DeepSleep + description: CPU is in Deep-Sleep + value: 1 enum/FPDR: bit_size: 1 variants: - - name: Idle - description: Flash memory in Idle mode when system is in LPRun mode - value: 0 - - name: PowerDown - description: Flash memory in Power-down mode when system is in LPRun mode - value: 1 + - name: Idle + description: Flash memory in Idle mode when system is in LPRun mode + value: 0 + - name: PowerDown + description: Flash memory in Power-down mode when system is in LPRun mode + value: 1 enum/FPDS: bit_size: 1 variants: - - name: Idle - description: Flash memory in Idle mode when system is in LPSleep mode - value: 0 - - name: PowerDown - description: Flash memory in Power-down mode when system is in LPSleep mode - value: 1 -enum/LDORDY: - bit_size: 1 - variants: - - name: NotReady - description: LDO not ready or off - value: 0 - - name: Ready - description: LDO ready - value: 1 + - name: Idle + description: Flash memory in Idle mode when system is in LPSleep mode + value: 0 + - name: PowerDown + description: Flash memory in Power-down mode when system is in LPSleep mode + value: 1 enum/LPMS: bit_size: 3 variants: - - name: Stop0 - description: Stop 0 mode - value: 0 - - name: Stop1 - description: Stop 1 mode - value: 1 - - name: Stop2 - description: Stop 2 mode - value: 2 - - name: Standby - description: Standby mode - value: 3 - - name: Shutdown - description: Shutdown mode - value: 4 + - name: Stop0 + description: Stop 0 mode + value: 0 + - name: Stop1 + description: Stop 1 mode + value: 1 + - name: Stop2 + description: Stop 2 mode + value: 2 + - name: Standby + description: Standby mode + value: 3 + - name: Shutdown + description: Shutdown mode + value: 4 enum/LPR: bit_size: 1 variants: - - name: MainMode - description: Voltage regulator in Main mode in Low-power run mode - value: 0 - - name: LowPowerMode - description: Voltage regulator in low-power mode in Low-power run mode - value: 1 -enum/NSS: - bit_size: 1 - variants: - - name: Low - description: Sub-GHz SPI NSS signal at level low - value: 0 - - name: High - description: Sub-GHz SPI NSS signal is at level high - value: 1 + - name: MainMode + description: Voltage regulator in Main mode in Low-power run mode + value: 0 + - name: LowPowerMode + description: Voltage regulator in low-power mode in Low-power run mode + value: 1 enum/PLS: bit_size: 3 variants: - - name: V2_0 - description: 2.0V - value: 0 - - name: V2_2 - description: 2.2V - value: 1 - - name: V2_4 - description: 2.4V - value: 2 - - name: V2_5 - description: 2.5V - value: 3 - - name: V2_6 - description: 2.6V - value: 4 - - name: V2_8 - description: 2.8V - value: 5 - - name: V2_9 - description: 2.9V - value: 6 - - name: External - description: External input analog voltage PVD_IN (compared internally to VREFINT) - value: 7 -enum/PVDE: - bit_size: 1 - variants: - - name: Disabled - description: PVD Disabled - value: 0 - - name: Enabled - description: PVD Enabled - value: 1 -enum/PVDO: - bit_size: 1 - variants: - - name: Above - description: VDD or voltage level on PVD_IN above the selected PVD threshold - value: 0 - - name: Below - description: VDD or voltage level on PVD_IN below the selected PVD threshold - value: 1 -enum/PVME: - bit_size: 1 - variants: - - name: Disabled - description: PVM3 (VDDA monitoring versus 1.62 V threshold) disable - value: 0 - - name: Enabled - description: PVM3 (VDDA monitoring versus 1.62 V threshold) enable - value: 1 -enum/PVMO: - bit_size: 1 - variants: - - name: Above - description: VDDA voltage above PVM3 threshold (around 1.62 V) - value: 0 - - name: Below - description: VDDA voltage below PVM3 threshold (around 1.62 V) - value: 1 -enum/REGLPF: - bit_size: 1 - variants: - - name: Main - description: Main regulator (MR) ready and used - value: 0 - - name: LowPower - description: Low-power regulator (LPR) used - value: 1 -enum/REGLPS: - bit_size: 1 - variants: - - name: NotReady - description: LPR not ready - value: 0 - - name: Ready - description: LPR ready - value: 1 -enum/REGMRS: - bit_size: 1 - variants: - - name: V_DD - description: Main regulator supplied directly from VDD - value: 0 - - name: LDO_SMPS - description: Main regulator supplied through LDO or SMPS - value: 1 -enum/RFBUSYMS: - bit_size: 1 - variants: - - name: NotBusy - description: radio busy masked signal low (not busy) - value: 0 - - name: Busy - description: radio busy masked signal high (busy) - value: 1 -enum/RFBUSYS: - bit_size: 1 - variants: - - name: NotBusy - description: radio busy signal low (not busy) - value: 0 - - name: Busy - description: radio busy signal high (busy) - value: 1 -enum/RFEOLEN: - bit_size: 1 - variants: - - name: Disabled - description: Radio end-of-life detector disabled - value: 0 - - name: Enabled - description: Radio end-of-life detector enabled - value: 1 -enum/RFEOLF: - bit_size: 1 - variants: - - name: Above - description: Supply voltage above radio end-of-life operating low level - value: 0 - - name: Below - description: Supply voltage below radio end-of-life operating low level - value: 1 -enum/RRS: - bit_size: 1 - variants: - - name: PowerOff - description: SRAM2 powered off in Standby mode (SRAM2 content lost) - value: 0 - - name: OnLPR - description: SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept) - value: 1 -enum/SMPSEN: - bit_size: 1 - variants: - - name: Disabled - description: SMPS step-down converter SMPS mode disabled (LDO mode enabled) - value: 0 - - name: Enabled - description: SMPS step-down converter SMPS mode enabled - value: 1 -enum/SMPSRDY: - bit_size: 1 - variants: - - name: NotReady - description: SMPS step-down converter not ready or off - value: 0 - - name: Ready - description: SMPS step-down converter ready - value: 1 + - name: V2_0 + description: 2.0V + value: 0 + - name: V2_2 + description: 2.2V + value: 1 + - name: V2_4 + description: 2.4V + value: 2 + - name: V2_5 + description: 2.5V + value: 3 + - name: V2_6 + description: 2.6V + value: 4 + - name: V2_8 + description: 2.8V + value: 5 + - name: V2_9 + description: 2.9V + value: 6 + - name: External + description: External input analog voltage PVD_IN (compared internally to VREFINT) + value: 7 enum/SUBGHZSPINSSSEL: bit_size: 1 variants: - - name: SUBGHZSPICR - description: sub-GHz SPI NSS signal driven from PWR_SUBGHZSPICR.NSS (RFBUSYMS functionality enabled) - value: 0 - - name: LPTIM3 - description: sub-GHz SPI NSS signal driven from LPTIM3_OUT (RFBUSYMS functionality disabled) - value: 1 -enum/VBE: - bit_size: 1 - variants: - - name: Disabled - description: VBAT battery charging disabled - value: 0 - - name: Enabled - description: VBAT battery charging enabled - value: 1 + - name: SUBGHZSPICR + description: sub-GHz SPI NSS signal driven from PWR_SUBGHZSPICR.NSS (RFBUSYMS functionality enabled) + value: 0 + - name: LPTIM3 + description: sub-GHz SPI NSS signal driven from LPTIM3_OUT (RFBUSYMS functionality disabled) + value: 1 enum/VBRS: bit_size: 1 variants: - - name: R5k - description: VBAT charging through a 5 kΩ resistor - value: 0 - - name: R1_5k - description: VBAT charging through a 1.5 kΩ resistor - value: 1 + - name: R5k + description: VBAT charging through a 5 kΩ resistor + value: 0 + - name: R1_5k + description: VBAT charging through a 1.5 kΩ resistor + value: 1 enum/VOS: bit_size: 2 variants: - - name: V1_2 - description: 1.2 V (range 1) - value: 1 - - name: V1_0 - description: 1.0 V (range 2) - value: 2 -enum/VOSF: - bit_size: 1 - variants: - - name: Ready - description: Regulator ready in the selected voltage range - value: 0 - - name: Change - description: Regulator output voltage changed to the required voltage level - value: 1 + - name: Range1 + description: 1.2 V (range 1) + value: 1 + - name: Range2 + description: 1.0 V (range 2) + value: 2 enum/WP: bit_size: 1 variants: - - name: RisingEdge - description: Detection on high level (rising edge) - value: 0 - - name: FallingEdge - description: Detection on low level (falling edge) - value: 1 -enum/WPVDF: - bit_size: 1 - variants: - - name: Clear - description: No wakeup event detected on PVD - value: 0 - - name: Wakeup - description: Wakeup event detected on PVD - value: 1 -enum/WRFBUSYF: - bit_size: 1 - variants: - - name: Clear - description: No wakeup event detected on radio busy - value: 0 - - name: Wakeup - description: Wakeup event detected on radio busy - value: 1 -enum/WRFBUSYP: - bit_size: 1 - variants: - - name: RisingEdge - description: Detection on high level (rising edge) - value: 0 - - name: FallingEdge - description: Detection on low level (falling edge) - value: 1 -enum/WUF: - bit_size: 1 - variants: - - name: Clear - description: No wakeup event detected on WKUP3 - value: 0 - - name: Wakeup - description: Wakeup event detected on WKUP3 - value: 1 -enum/WUFI: - bit_size: 1 - variants: - - name: Clear - description: All internal wakeup sources are cleared - value: 0 - - name: Wakeup - description: wakeup is detected on the internal wakeup line - value: 1 + - name: RisingEdge + description: Detection on high level (rising edge) + value: 0 + - name: FallingEdge + description: Detection on low level (falling edge) + value: 1 diff --git a/data/registers/quadspi_v1.yaml b/data/registers/quadspi_v1.yaml index 23c9011..ecf3e50 100644 --- a/data/registers/quadspi_v1.yaml +++ b/data/registers/quadspi_v1.yaml @@ -1,296 +1,299 @@ ---- block/QUADSPI: description: QuadSPI interface items: - - name: CR - description: control register - byte_offset: 0 - fieldset: CR - - name: DCR - description: device configuration register - byte_offset: 4 - fieldset: DCR - - name: SR - description: status register - byte_offset: 8 - access: Read - fieldset: SR - - name: FCR - description: flag clear register - byte_offset: 12 - fieldset: FCR - - name: DLR - description: data length register - byte_offset: 16 - fieldset: DLR - - name: CCR - description: communication configuration register - byte_offset: 20 - fieldset: CCR - - name: AR - description: address register - byte_offset: 24 - fieldset: AR - - name: ABR - description: ABR - byte_offset: 28 - fieldset: ABR - - name: DR - description: data register - byte_offset: 32 - fieldset: DR - - name: PSMKR - description: polling status mask register - byte_offset: 36 - fieldset: PSMKR - - name: PSMAR - description: polling status match register - byte_offset: 40 - fieldset: PSMAR - - name: PIR - description: polling interval register - byte_offset: 44 - fieldset: PIR - - name: LPTR - description: low-power timeout register - byte_offset: 48 - fieldset: LPTR + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: DCR + description: device configuration register + byte_offset: 4 + fieldset: DCR + - name: SR + description: status register + byte_offset: 8 + access: Read + fieldset: SR + - name: FCR + description: flag clear register + byte_offset: 12 + fieldset: FCR + - name: DLR + description: data length register + byte_offset: 16 + fieldset: DLR + - name: CCR + description: communication configuration register + byte_offset: 20 + fieldset: CCR + - name: AR + description: address register + byte_offset: 24 + fieldset: AR + - name: ABR + description: ABR + byte_offset: 28 + fieldset: ABR + - name: DR + description: data register + byte_offset: 32 + fieldset: DR + - name: PSMKR + description: polling status mask register + byte_offset: 36 + fieldset: PSMKR + - name: PSMAR + description: polling status match register + byte_offset: 40 + fieldset: PSMAR + - name: PIR + description: polling interval register + byte_offset: 44 + fieldset: PIR + - name: LPTR + description: low-power timeout register + byte_offset: 48 + fieldset: LPTR fieldset/ABR: description: ABR fields: - - name: ALTERNATE - description: ALTERNATE - bit_offset: 0 - bit_size: 32 + - name: ALTERNATE + description: ALTERNATE + bit_offset: 0 + bit_size: 32 fieldset/AR: description: address register fields: - - name: ADDRESS - description: Address - bit_offset: 0 - bit_size: 32 + - name: ADDRESS + description: Address + bit_offset: 0 + bit_size: 32 fieldset/CCR: description: communication configuration register fields: - - name: INSTRUCTION - description: Instruction - bit_offset: 0 - bit_size: 8 - - name: IMODE - description: Instruction mode - bit_offset: 8 - bit_size: 2 - - name: ADMODE - description: Address mode - bit_offset: 10 - bit_size: 2 - - name: ADSIZE - description: Address size - bit_offset: 12 - bit_size: 2 - - name: ABMODE - description: Alternate bytes mode - bit_offset: 14 - bit_size: 2 - - name: ABSIZE - description: Alternate bytes size - bit_offset: 16 - bit_size: 2 - - name: DCYC - description: Number of dummy cycles - bit_offset: 18 - bit_size: 5 - - name: DMODE - description: Data mode - bit_offset: 24 - bit_size: 2 - - name: FMODE - description: Functional mode - bit_offset: 26 - bit_size: 2 - - name: SIOO - description: Send instruction only once mode - bit_offset: 28 - bit_size: 1 - - name: DHHC - description: DDR hold half cycle - bit_offset: 30 - bit_size: 1 - - name: DDRM - description: Double data rate mode - bit_offset: 31 - bit_size: 1 + - name: INSTRUCTION + description: Instruction + bit_offset: 0 + bit_size: 8 + - name: IMODE + description: Instruction mode + bit_offset: 8 + bit_size: 2 + - name: ADMODE + description: Address mode + bit_offset: 10 + bit_size: 2 + - name: ADSIZE + description: Address size + bit_offset: 12 + bit_size: 2 + - name: ABMODE + description: Alternate bytes mode + bit_offset: 14 + bit_size: 2 + - name: ABSIZE + description: Alternate bytes size + bit_offset: 16 + bit_size: 2 + - name: DCYC + description: Number of dummy cycles + bit_offset: 18 + bit_size: 5 + - name: DMODE + description: Data mode + bit_offset: 24 + bit_size: 2 + - name: FMODE + description: Functional mode + bit_offset: 26 + bit_size: 2 + - name: SIOO + description: Send instruction only once mode + bit_offset: 28 + bit_size: 1 + - name: FRCM + description: Free-running clock mode (not available on all chips!) + bit_offset: 29 + bit_size: 1 + - name: DHHC + description: DDR hold half cycle + bit_offset: 30 + bit_size: 1 + - name: DDRM + description: Double data rate mode + bit_offset: 31 + bit_size: 1 fieldset/CR: description: control register fields: - - name: EN - description: Enable - bit_offset: 0 - bit_size: 1 - - name: ABORT - description: Abort request - bit_offset: 1 - bit_size: 1 - - name: DMAEN - description: DMA enable - bit_offset: 2 - bit_size: 1 - - name: TCEN - description: Timeout counter enable - bit_offset: 3 - bit_size: 1 - - name: SSHIFT - description: Sample shift - bit_offset: 4 - bit_size: 1 - - name: DFM - description: Dual-flash mode - bit_offset: 6 - bit_size: 1 - - name: FSEL - description: FLASH memory selection - bit_offset: 7 - bit_size: 1 - - name: FTHRES - description: IFO threshold level - bit_offset: 8 - bit_size: 5 - - name: TEIE - description: Transfer error interrupt enable - bit_offset: 16 - bit_size: 1 - - name: TCIE - description: Transfer complete interrupt enable - bit_offset: 17 - bit_size: 1 - - name: FTIE - description: FIFO threshold interrupt enable - bit_offset: 18 - bit_size: 1 - - name: SMIE - description: Status match interrupt enable - bit_offset: 19 - bit_size: 1 - - name: TOIE - description: TimeOut interrupt enable - bit_offset: 20 - bit_size: 1 - - name: APMS - description: Automatic poll mode stop - bit_offset: 22 - bit_size: 1 - - name: PMM - description: Polling match mode - bit_offset: 23 - bit_size: 1 - - name: PRESCALER - description: Clock prescaler - bit_offset: 24 - bit_size: 8 + - name: EN + description: Enable + bit_offset: 0 + bit_size: 1 + - name: ABORT + description: Abort request + bit_offset: 1 + bit_size: 1 + - name: DMAEN + description: DMA enable (not available on all chips!) + bit_offset: 2 + bit_size: 1 + - name: TCEN + description: Timeout counter enable + bit_offset: 3 + bit_size: 1 + - name: SSHIFT + description: Sample shift + bit_offset: 4 + bit_size: 1 + - name: DFM + description: Dual-flash mode + bit_offset: 6 + bit_size: 1 + - name: FSEL + description: FLASH memory selection + bit_offset: 7 + bit_size: 1 + - name: FTHRES + description: IFO threshold level + bit_offset: 8 + bit_size: 5 + - name: TEIE + description: Transfer error interrupt enable + bit_offset: 16 + bit_size: 1 + - name: TCIE + description: Transfer complete interrupt enable + bit_offset: 17 + bit_size: 1 + - name: FTIE + description: FIFO threshold interrupt enable + bit_offset: 18 + bit_size: 1 + - name: SMIE + description: Status match interrupt enable + bit_offset: 19 + bit_size: 1 + - name: TOIE + description: TimeOut interrupt enable + bit_offset: 20 + bit_size: 1 + - name: APMS + description: Automatic poll mode stop + bit_offset: 22 + bit_size: 1 + - name: PMM + description: Polling match mode + bit_offset: 23 + bit_size: 1 + - name: PRESCALER + description: Clock prescaler + bit_offset: 24 + bit_size: 8 fieldset/DCR: description: device configuration register fields: - - name: CKMODE - description: Mode 0 / mode 3 - bit_offset: 0 - bit_size: 1 - - name: CSHT - description: Chip select high time - bit_offset: 8 - bit_size: 3 - - name: FSIZE - description: FLASH memory size - bit_offset: 16 - bit_size: 5 + - name: CKMODE + description: Mode 0 / mode 3 + bit_offset: 0 + bit_size: 1 + - name: CSHT + description: Chip select high time + bit_offset: 8 + bit_size: 3 + - name: FSIZE + description: FLASH memory size + bit_offset: 16 + bit_size: 5 fieldset/DLR: description: data length register fields: - - name: DL - description: Data length - bit_offset: 0 - bit_size: 32 + - name: DL + description: Data length + bit_offset: 0 + bit_size: 32 fieldset/DR: description: data register fields: - - name: DATA - description: Data - bit_offset: 0 - bit_size: 32 + - name: DATA + description: Data + bit_offset: 0 + bit_size: 32 fieldset/FCR: description: flag clear register fields: - - name: CTEF - description: Clear transfer error flag - bit_offset: 0 - bit_size: 1 - - name: CTCF - description: Clear transfer complete flag - bit_offset: 1 - bit_size: 1 - - name: CSMF - description: Clear status match flag - bit_offset: 3 - bit_size: 1 - - name: CTOF - description: Clear timeout flag - bit_offset: 4 - bit_size: 1 + - name: CTEF + description: Clear transfer error flag + bit_offset: 0 + bit_size: 1 + - name: CTCF + description: Clear transfer complete flag + bit_offset: 1 + bit_size: 1 + - name: CSMF + description: Clear status match flag + bit_offset: 3 + bit_size: 1 + - name: CTOF + description: Clear timeout flag + bit_offset: 4 + bit_size: 1 fieldset/LPTR: description: low-power timeout register fields: - - name: TIMEOUT - description: Timeout period - bit_offset: 0 - bit_size: 16 + - name: TIMEOUT + description: Timeout period + bit_offset: 0 + bit_size: 16 fieldset/PIR: description: polling interval register fields: - - name: INTERVAL - description: Polling interval - bit_offset: 0 - bit_size: 16 + - name: INTERVAL + description: Polling interval + bit_offset: 0 + bit_size: 16 fieldset/PSMAR: description: polling status match register fields: - - name: MATCH - description: Status match - bit_offset: 0 - bit_size: 32 + - name: MATCH + description: Status match + bit_offset: 0 + bit_size: 32 fieldset/PSMKR: description: polling status mask register fields: - - name: MASK - description: Status mask - bit_offset: 0 - bit_size: 32 + - name: MASK + description: Status mask + bit_offset: 0 + bit_size: 32 fieldset/SR: description: status register fields: - - name: TEF - description: Transfer error flag - bit_offset: 0 - bit_size: 1 - - name: TCF - description: Transfer complete flag - bit_offset: 1 - bit_size: 1 - - name: FTF - description: FIFO threshold flag - bit_offset: 2 - bit_size: 1 - - name: SMF - description: Status match flag - bit_offset: 3 - bit_size: 1 - - name: TOF - description: Timeout flag - bit_offset: 4 - bit_size: 1 - - name: BUSY - description: Busy - bit_offset: 5 - bit_size: 1 - - name: FLEVEL - description: FIFO level - bit_offset: 8 - bit_size: 7 + - name: TEF + description: Transfer error flag + bit_offset: 0 + bit_size: 1 + - name: TCF + description: Transfer complete flag + bit_offset: 1 + bit_size: 1 + - name: FTF + description: FIFO threshold flag + bit_offset: 2 + bit_size: 1 + - name: SMF + description: Status match flag + bit_offset: 3 + bit_size: 1 + - name: TOF + description: Timeout flag + bit_offset: 4 + bit_size: 1 + - name: BUSY + description: Busy + bit_offset: 5 + bit_size: 1 + - name: FLEVEL + description: FIFO level + bit_offset: 8 + bit_size: 7 diff --git a/data/registers/rcc_c0.yaml b/data/registers/rcc_c0.yaml index 90df91f..e5072d4 100644 --- a/data/registers/rcc_c0.yaml +++ b/data/registers/rcc_c0.yaml @@ -1,964 +1,963 @@ ---- block/RCC: description: RCC address block description items: - - name: CR - description: RCC clock control register - byte_offset: 0 - fieldset: CR - - name: ICSCR - description: RCC internal clock source calibration register - byte_offset: 4 - fieldset: ICSCR - - name: CFGR - description: RCC clock configuration register - byte_offset: 8 - fieldset: CFGR - - name: CIER - description: RCC clock interrupt enable register - byte_offset: 24 - fieldset: CIER - - name: CIFR - description: RCC clock interrupt flag register - byte_offset: 28 - fieldset: CIFR - - name: CICR - description: RCC clock interrupt clear register - byte_offset: 32 - fieldset: CICR - - name: GPIORSTR - description: RCC I/O port reset register - byte_offset: 36 - fieldset: GPIORSTR - - name: AHBRSTR - description: RCC AHB peripheral reset register - byte_offset: 40 - fieldset: AHBRSTR - - name: APBRSTR1 - description: RCC APB peripheral reset register 1 - byte_offset: 44 - fieldset: APBRSTR1 - - name: APBRSTR2 - description: RCC APB peripheral reset register 2 - byte_offset: 48 - fieldset: APBRSTR2 - - name: GPIOENR - description: RCC I/O port clock enable register - byte_offset: 52 - fieldset: GPIOENR - - name: AHBENR - description: RCC AHB peripheral clock enable register - byte_offset: 56 - fieldset: AHBENR - - name: APBENR1 - description: RCC APB peripheral clock enable register 1 - byte_offset: 60 - fieldset: APBENR1 - - name: APBENR2 - description: RCC APB peripheral clock enable register 2 - byte_offset: 64 - fieldset: APBENR2 - - name: GPIOSMENR - description: RCC I/O port in Sleep mode clock enable register - byte_offset: 68 - fieldset: GPIOSMENR - - name: AHBSMENR - description: RCC AHB peripheral clock enable in Sleep/Stop mode register - byte_offset: 72 - fieldset: AHBSMENR - - name: APBSMENR1 - description: RCC APB peripheral clock enable in Sleep/Stop mode register 1 - byte_offset: 76 - fieldset: APBSMENR1 - - name: APBSMENR2 - description: RCC APB peripheral clock enable in Sleep/Stop mode register 2 - byte_offset: 80 - fieldset: APBSMENR2 - - name: CCIPR - description: RCC peripherals independent clock configuration register - byte_offset: 84 - fieldset: CCIPR - - name: CSR1 - description: RCC control/status register 1 - byte_offset: 92 - fieldset: CSR1 - - name: CSR2 - description: RCC control/status register 2 - byte_offset: 96 - fieldset: CSR2 + - name: CR + description: RCC clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: RCC internal clock source calibration register + byte_offset: 4 + fieldset: ICSCR + - name: CFGR + description: RCC clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: CIER + description: RCC clock interrupt enable register + byte_offset: 24 + fieldset: CIER + - name: CIFR + description: RCC clock interrupt flag register + byte_offset: 28 + fieldset: CIFR + - name: CICR + description: RCC clock interrupt clear register + byte_offset: 32 + fieldset: CICR + - name: GPIORSTR + description: RCC I/O port reset register + byte_offset: 36 + fieldset: GPIORSTR + - name: AHBRSTR + description: RCC AHB peripheral reset register + byte_offset: 40 + fieldset: AHBRSTR + - name: APBRSTR1 + description: RCC APB peripheral reset register 1 + byte_offset: 44 + fieldset: APBRSTR1 + - name: APBRSTR2 + description: RCC APB peripheral reset register 2 + byte_offset: 48 + fieldset: APBRSTR2 + - name: GPIOENR + description: RCC I/O port clock enable register + byte_offset: 52 + fieldset: GPIOENR + - name: AHBENR + description: RCC AHB peripheral clock enable register + byte_offset: 56 + fieldset: AHBENR + - name: APBENR1 + description: RCC APB peripheral clock enable register 1 + byte_offset: 60 + fieldset: APBENR1 + - name: APBENR2 + description: RCC APB peripheral clock enable register 2 + byte_offset: 64 + fieldset: APBENR2 + - name: GPIOSMENR + description: RCC I/O port in Sleep mode clock enable register + byte_offset: 68 + fieldset: GPIOSMENR + - name: AHBSMENR + description: RCC AHB peripheral clock enable in Sleep/Stop mode register + byte_offset: 72 + fieldset: AHBSMENR + - name: APBSMENR1 + description: RCC APB peripheral clock enable in Sleep/Stop mode register 1 + byte_offset: 76 + fieldset: APBSMENR1 + - name: APBSMENR2 + description: RCC APB peripheral clock enable in Sleep/Stop mode register 2 + byte_offset: 80 + fieldset: APBSMENR2 + - name: CCIPR + description: RCC peripherals independent clock configuration register + byte_offset: 84 + fieldset: CCIPR + - name: CSR1 + description: RCC control/status register 1 + byte_offset: 92 + fieldset: CSR1 + - name: CSR2 + description: RCC control/status register 2 + byte_offset: 96 + fieldset: CSR2 fieldset/AHBENR: description: RCC AHB peripheral clock enable register fields: - - name: DMA1EN - description: "DMA1 and DMAMUX clock enable\r Set and cleared by software.\r DMAMUX is enabled as long as at least one DMA peripheral is enabled." - bit_offset: 0 - bit_size: 1 - - name: FLASHEN - description: "Flash memory interface clock enable\r Set and cleared by software.\r This bit can only be cleared when the Flash memory is in power down mode." - bit_offset: 8 - bit_size: 1 - - name: CRCEN - description: "CRC clock enable\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 + - name: DMA1EN + description: "DMA1 and DMAMUX clock enable\r Set and cleared by software.\r DMAMUX is enabled as long as at least one DMA peripheral is enabled." + bit_offset: 0 + bit_size: 1 + - name: FLASHEN + description: "Flash memory interface clock enable\r Set and cleared by software.\r This bit can only be cleared when the Flash memory is in power down mode." + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: "CRC clock enable\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 fieldset/AHBRSTR: description: RCC AHB peripheral reset register fields: - - name: DMA1RST - description: "DMA1 and DMAMUX reset\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: FLASHRST - description: "Flash memory interface reset\r Set and cleared by software.\r This bit can only be set when the Flash memory is in power down mode." - bit_offset: 8 - bit_size: 1 - - name: CRCRST - description: "CRC reset\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 + - name: DMA1RST + description: "DMA1 and DMAMUX reset\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: FLASHRST + description: "Flash memory interface reset\r Set and cleared by software.\r This bit can only be set when the Flash memory is in power down mode." + bit_offset: 8 + bit_size: 1 + - name: CRCRST + description: "CRC reset\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 fieldset/AHBSMENR: description: RCC AHB peripheral clock enable in Sleep/Stop mode register fields: - - name: DMA1SMEN - description: "DMA1 and DMAMUX clock enable during Sleep mode\r Set and cleared by software.\r Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral." - bit_offset: 0 - bit_size: 1 - - name: FLASHSMEN - description: "Flash memory interface clock enable during Sleep mode\r Set and cleared by software.\r This bit can be activated only when the Flash memory is in power down mode." - bit_offset: 8 - bit_size: 1 - - name: SRAMSMEN - description: "SRAM clock enable during Sleep mode\r Set and cleared by software." - bit_offset: 9 - bit_size: 1 - - name: CRCSMEN - description: "CRC clock enable during Sleep mode\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 + - name: DMA1SMEN + description: "DMA1 and DMAMUX clock enable during Sleep mode\r Set and cleared by software.\r Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral." + bit_offset: 0 + bit_size: 1 + - name: FLASHSMEN + description: "Flash memory interface clock enable during Sleep mode\r Set and cleared by software.\r This bit can be activated only when the Flash memory is in power down mode." + bit_offset: 8 + bit_size: 1 + - name: SRAMSMEN + description: "SRAM clock enable during Sleep mode\r Set and cleared by software." + bit_offset: 9 + bit_size: 1 + - name: CRCSMEN + description: "CRC clock enable during Sleep mode\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 fieldset/APBENR1: description: RCC APB peripheral clock enable register 1 fields: - - name: TIM3EN - description: "TIM3 timer clock enable\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: RTCAPBEN - description: "RTC APB clock enable\r Set and cleared by software." - bit_offset: 10 - bit_size: 1 - - name: WWDGEN - description: "WWDG clock enable\r Set by software to enable the window watchdog clock. Cleared by hardware system reset\r This bit can also be set by hardware if the WWDG_SW option bit is 0." - bit_offset: 11 - bit_size: 1 - - name: USART2EN - description: "USART2 clock enable\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: I2C1EN - description: "I2C1 clock enable\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: DBGEN - description: "Debug support clock enable\r Set and cleared by software." - bit_offset: 27 - bit_size: 1 - - name: PWREN - description: "Power interface clock enable\r Set and cleared by software." - bit_offset: 28 - bit_size: 1 + - name: TIM3EN + description: "TIM3 timer clock enable\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: RTCAPBEN + description: "RTC APB clock enable\r Set and cleared by software." + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: "WWDG clock enable\r Set by software to enable the window watchdog clock. Cleared by hardware system reset\r This bit can also be set by hardware if the WWDG_SW option bit is 0." + bit_offset: 11 + bit_size: 1 + - name: USART2EN + description: "USART2 clock enable\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: I2C1EN + description: "I2C1 clock enable\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: DBGEN + description: "Debug support clock enable\r Set and cleared by software." + bit_offset: 27 + bit_size: 1 + - name: PWREN + description: "Power interface clock enable\r Set and cleared by software." + bit_offset: 28 + bit_size: 1 fieldset/APBENR2: description: RCC APB peripheral clock enable register 2 fields: - - name: SYSCFGEN - description: "SYSCFG clock enable\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: TIM1EN - description: "TIM1 timer clock enable\r Set and cleared by software." - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: "SPI1 clock enable\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: USART1EN - description: "USART1 clock enable\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: TIM14EN - description: "TIM14 timer clock enable\r Set and cleared by software." - bit_offset: 15 - bit_size: 1 - - name: TIM16EN - description: "TIM16 timer clock enable\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: "TIM16 timer clock enable\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: ADCEN - description: "ADC clock enable\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 + - name: SYSCFGEN + description: "SYSCFG clock enable\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: TIM1EN + description: "TIM1 timer clock enable\r Set and cleared by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: "SPI1 clock enable\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: "USART1 clock enable\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: TIM14EN + description: "TIM14 timer clock enable\r Set and cleared by software." + bit_offset: 15 + bit_size: 1 + - name: TIM16EN + description: "TIM16 timer clock enable\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: "TIM16 timer clock enable\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: ADCEN + description: "ADC clock enable\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 fieldset/APBRSTR1: description: RCC APB peripheral reset register 1 fields: - - name: TIM3RST - description: "TIM3 timer reset\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: USART2RST - description: "USART2 reset\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: I2C1RST - description: "I2C1 reset\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: DBGRST - description: "Debug support reset\r Set and cleared by software." - bit_offset: 27 - bit_size: 1 - - name: PWRRST - description: "Power interface reset\r Set and cleared by software." - bit_offset: 28 - bit_size: 1 + - name: TIM3RST + description: "TIM3 timer reset\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: USART2RST + description: "USART2 reset\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: I2C1RST + description: "I2C1 reset\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: DBGRST + description: "Debug support reset\r Set and cleared by software." + bit_offset: 27 + bit_size: 1 + - name: PWRRST + description: "Power interface reset\r Set and cleared by software." + bit_offset: 28 + bit_size: 1 fieldset/APBRSTR2: description: RCC APB peripheral reset register 2 fields: - - name: SYSCFGRST - description: "SYSCFG reset\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: TIM1RST - description: "TIM1 timer reset\r Set and cleared by software." - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: "SPI1 reset\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: USART1RST - description: "USART1 reset\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: TIM14RST - description: "TIM14 timer reset\r Set and cleared by software." - bit_offset: 15 - bit_size: 1 - - name: TIM16RST - description: "TIM16 timer reset\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: "TIM16 timer reset\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: ADCRST - description: "ADC reset\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 + - name: SYSCFGRST + description: "SYSCFG reset\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: TIM1RST + description: "TIM1 timer reset\r Set and cleared by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: "SPI1 reset\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: "USART1 reset\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: TIM14RST + description: "TIM14 timer reset\r Set and cleared by software." + bit_offset: 15 + bit_size: 1 + - name: TIM16RST + description: "TIM16 timer reset\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: "TIM16 timer reset\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: ADCRST + description: "ADC reset\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 fieldset/APBSMENR1: description: RCC APB peripheral clock enable in Sleep/Stop mode register 1 fields: - - name: TIM3SMEN - description: "TIM3 timer clock enable during Sleep mode\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: RTCAPBSMEN - description: "RTC APB clock enable during Sleep mode\r Set and cleared by software." - bit_offset: 10 - bit_size: 1 - - name: WWDGSMEN - description: "WWDG clock enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 11 - bit_size: 1 - - name: USART2SMEN - description: "USART2 clock enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: I2C1SMEN - description: "I2C1 clock enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: DBGSMEN - description: "Debug support clock enable during Sleep mode\r Set and cleared by software." - bit_offset: 27 - bit_size: 1 - - name: PWRSMEN - description: "Power interface clock enable during Sleep mode\r Set and cleared by software." - bit_offset: 28 - bit_size: 1 + - name: TIM3SMEN + description: "TIM3 timer clock enable during Sleep mode\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: RTCAPBSMEN + description: "RTC APB clock enable during Sleep mode\r Set and cleared by software." + bit_offset: 10 + bit_size: 1 + - name: WWDGSMEN + description: "WWDG clock enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 11 + bit_size: 1 + - name: USART2SMEN + description: "USART2 clock enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: I2C1SMEN + description: "I2C1 clock enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: DBGSMEN + description: "Debug support clock enable during Sleep mode\r Set and cleared by software." + bit_offset: 27 + bit_size: 1 + - name: PWRSMEN + description: "Power interface clock enable during Sleep mode\r Set and cleared by software." + bit_offset: 28 + bit_size: 1 fieldset/APBSMENR2: description: RCC APB peripheral clock enable in Sleep/Stop mode register 2 fields: - - name: SYSCFGSMEN - description: "SYSCFG clock enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: TIM1SMEN - description: "TIM1 timer clock enable during Sleep mode\r Set and cleared by software." - bit_offset: 11 - bit_size: 1 - - name: SPI1SMEN - description: "SPI1 clock enable during Sleep mode\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: USART1SMEN - description: "USART1 clock enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: TIM14SMEN - description: "TIM14 timer clock enable during Sleep mode\r Set and cleared by software." - bit_offset: 15 - bit_size: 1 - - name: TIM16SMEN - description: "TIM16 timer clock enable during Sleep mode\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: TIM17SMEN - description: "TIM16 timer clock enable during Sleep mode\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: ADCSMEN - description: "ADC clock enable during Sleep mode\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 + - name: SYSCFGSMEN + description: "SYSCFG clock enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: TIM1SMEN + description: "TIM1 timer clock enable during Sleep mode\r Set and cleared by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: "SPI1 clock enable during Sleep mode\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: USART1SMEN + description: "USART1 clock enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: TIM14SMEN + description: "TIM14 timer clock enable during Sleep mode\r Set and cleared by software." + bit_offset: 15 + bit_size: 1 + - name: TIM16SMEN + description: "TIM16 timer clock enable during Sleep mode\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: "TIM16 timer clock enable during Sleep mode\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: ADCSMEN + description: "ADC clock enable during Sleep mode\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 fieldset/CCIPR: description: RCC peripherals independent clock configuration register fields: - - name: USART1SEL - description: "USART1 clock source selection\r This bitfield is controlled by software to select USART1 clock source as follows:" - bit_offset: 0 - bit_size: 2 - enum: USART1SEL - - name: I2C1SEL - description: "I2C1 clock source selection\r This bitfield is controlled by software to select I2C1 clock source as follows:" - bit_offset: 12 - bit_size: 2 - enum: I2C1SEL - - name: I2S1SEL - description: "I2S1 clock source selection\r This bitfield is controlled by software to select I2S1 clock source as follows:" - bit_offset: 14 - bit_size: 2 - enum: I2S1SEL - - name: ADCSEL - description: "ADCs clock source selection\r This bitfield is controlled by software to select the clock source for ADC:" - bit_offset: 30 - bit_size: 2 - enum: ADCSEL + - name: USART1SEL + description: "USART1 clock source selection\r This bitfield is controlled by software to select USART1 clock source as follows:" + bit_offset: 0 + bit_size: 2 + enum: USART1SEL + - name: I2C1SEL + description: "I2C1 clock source selection\r This bitfield is controlled by software to select I2C1 clock source as follows:" + bit_offset: 12 + bit_size: 2 + enum: I2C1SEL + - name: I2S1SEL + description: "I2S1 clock source selection\r This bitfield is controlled by software to select I2S1 clock source as follows:" + bit_offset: 14 + bit_size: 2 + enum: I2S1SEL + - name: ADCSEL + description: "ADCs clock source selection\r This bitfield is controlled by software to select the clock source for ADC:" + bit_offset: 30 + bit_size: 2 + enum: ADCSEL fieldset/CFGR: description: RCC clock configuration register fields: - - name: SW - description: "System clock switch\r This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows:\r Others: Reserved\r The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, or Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected." - bit_offset: 0 - bit_size: 3 - enum: SW - - name: SWS - description: "System clock switch status\r This bitfield is controlled by hardware to indicate the clock source used as system clock:\r Others: Reserved" - bit_offset: 3 - bit_size: 3 - enum: SW - - name: HPRE - description: "AHB prescaler\r This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows:\r 0xxx: 1" - bit_offset: 8 - bit_size: 4 - enum: HPRE - - name: PPRE - description: "APB prescaler\r This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows:\r 0xx: 1" - bit_offset: 12 - bit_size: 3 - enum: PPRE - - name: MCO2SEL - description: "Microcontroller clock output 2 clock selector\r This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows:\r This bitfield is controlled by software. It sets the clock selector for MCO output as follows:\r Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching." - bit_offset: 16 - bit_size: 4 - enum: MCOSEL - - name: MCO2PRE - description: "Microcontroller clock output 2 prescaler\r This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows:\r ...\r It is highly recommended to set this field before the MCO2 output is enabled." - bit_offset: 20 - bit_size: 4 - enum: MCOPRE - - name: MCOSEL - description: "Microcontroller clock output clock selector\r This bitfield is controlled by software. It sets the clock selector for MCO output as follows:\r Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Any other value means no clock on MCO." - bit_offset: 24 - bit_size: 4 - enum: MCOSEL - - name: MCOPRE - description: "Microcontroller clock output prescaler\r This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows:\r ...\r It is highly recommended to set this field before the MCO output is enabled." - bit_offset: 28 - bit_size: 4 - enum: MCOPRE + - name: SW + description: "System clock switch\r This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows:\r Others: Reserved\r The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, or Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected." + bit_offset: 0 + bit_size: 3 + enum: SW + - name: SWS + description: "System clock switch status\r This bitfield is controlled by hardware to indicate the clock source used as system clock:\r Others: Reserved" + bit_offset: 3 + bit_size: 3 + enum: SW + - name: HPRE + description: "AHB prescaler\r This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows:\r 0xxx: 1" + bit_offset: 8 + bit_size: 4 + enum: HPRE + - name: PPRE + description: "APB prescaler\r This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows:\r 0xx: 1" + bit_offset: 12 + bit_size: 3 + enum: PPRE + - name: MCO2SEL + description: "Microcontroller clock output 2 clock selector\r This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows:\r This bitfield is controlled by software. It sets the clock selector for MCO output as follows:\r Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching." + bit_offset: 16 + bit_size: 4 + enum: MCOSEL + - name: MCO2PRE + description: "Microcontroller clock output 2 prescaler\r This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows:\r ...\r It is highly recommended to set this field before the MCO2 output is enabled." + bit_offset: 20 + bit_size: 4 + enum: MCOPRE + - name: MCOSEL + description: "Microcontroller clock output clock selector\r This bitfield is controlled by software. It sets the clock selector for MCO output as follows:\r Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Any other value means no clock on MCO." + bit_offset: 24 + bit_size: 4 + enum: MCOSEL + - name: MCOPRE + description: "Microcontroller clock output prescaler\r This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows:\r ...\r It is highly recommended to set this field before the MCO output is enabled." + bit_offset: 28 + bit_size: 4 + enum: MCOPRE fieldset/CICR: description: RCC clock interrupt clear register fields: - - name: LSIRDYC - description: "LSI ready interrupt clear\r This bit is set by software to clear the LSIRDYF flag." - bit_offset: 0 - bit_size: 1 - - name: LSERDYC - description: "LSE ready interrupt clear\r This bit is set by software to clear the LSERDYF flag." - bit_offset: 1 - bit_size: 1 - - name: HSIRDYC - description: "HSI16 ready interrupt clear\r This bit is set software to clear the HSIRDYF flag." - bit_offset: 3 - bit_size: 1 - - name: HSERDYC - description: "HSE ready interrupt clear\r This bit is set by software to clear the HSERDYF flag." - bit_offset: 4 - bit_size: 1 - - name: CSSC - description: "Clock security system interrupt clear\r This bit is set by software to clear the HSECSSF flag." - bit_offset: 8 - bit_size: 1 - - name: LSECSSC - description: "LSE Clock security system interrupt clear\r This bit is set by software to clear the LSECSSF flag." - bit_offset: 9 - bit_size: 1 + - name: LSIRDYC + description: "LSI ready interrupt clear\r This bit is set by software to clear the LSIRDYF flag." + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: "LSE ready interrupt clear\r This bit is set by software to clear the LSERDYF flag." + bit_offset: 1 + bit_size: 1 + - name: HSIRDYC + description: "HSI16 ready interrupt clear\r This bit is set software to clear the HSIRDYF flag." + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: "HSE ready interrupt clear\r This bit is set by software to clear the HSERDYF flag." + bit_offset: 4 + bit_size: 1 + - name: CSSC + description: "Clock security system interrupt clear\r This bit is set by software to clear the HSECSSF flag." + bit_offset: 8 + bit_size: 1 + - name: LSECSSC + description: "LSE Clock security system interrupt clear\r This bit is set by software to clear the LSECSSF flag." + bit_offset: 9 + bit_size: 1 fieldset/CIER: description: RCC clock interrupt enable register fields: - - name: LSIRDYIE - description: "LSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization:" - bit_offset: 0 - bit_size: 1 - - name: LSERDYIE - description: "LSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization:" - bit_offset: 1 - bit_size: 1 - - name: HSIRDYIE - description: "HSI16 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization:" - bit_offset: 3 - bit_size: 1 - - name: HSERDYIE - description: "HSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization:" - bit_offset: 4 - bit_size: 1 + - name: LSIRDYIE + description: "LSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization:" + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: "LSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization:" + bit_offset: 1 + bit_size: 1 + - name: HSIRDYIE + description: "HSI16 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization:" + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: "HSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization:" + bit_offset: 4 + bit_size: 1 fieldset/CIFR: description: RCC clock interrupt flag register fields: - - name: LSIRDYF - description: "LSI ready interrupt flag\r This flag indicates a pending interrupt upon LSE clock getting ready.\r Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.\r Cleared by software setting the LSIRDYC bit." - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: "LSE ready interrupt flag\r This flag indicates a pending interrupt upon LSE clock getting ready.\r Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.\r Cleared by software setting the LSERDYC bit." - bit_offset: 1 - bit_size: 1 - - name: HSIRDYF - description: "HSI16 ready interrupt flag\r This flag indicates a pending interrupt upon HSI16 clock getting ready.\r Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in response to setting the HSION (refer to ). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Cleared by software setting the HSIRDYC bit." - bit_offset: 3 - bit_size: 1 - - name: HSERDYF - description: "HSE ready interrupt flag\r This flag indicates a pending interrupt upon HSE clock getting ready.\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set.\r Cleared by software setting the HSERDYC bit." - bit_offset: 4 - bit_size: 1 - - name: CSSF - description: "HSE clock security system interrupt flag\r This flag indicates a pending interrupt upon HSE clock failure.\r Set by hardware when a failure is detected in the HSE oscillator.\r Cleared by software setting the CSSC bit." - bit_offset: 8 - bit_size: 1 - - name: LSECSSF - description: "LSE clock security system interrupt flag\r This flag indicates a pending interrupt upon LSE clock failure.\r Set by hardware when a failure is detected in the LSE oscillator.\r Cleared by software by setting the LSECSSC bit." - bit_offset: 9 - bit_size: 1 + - name: LSIRDYF + description: "LSI ready interrupt flag\r This flag indicates a pending interrupt upon LSE clock getting ready.\r Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.\r Cleared by software setting the LSIRDYC bit." + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: "LSE ready interrupt flag\r This flag indicates a pending interrupt upon LSE clock getting ready.\r Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.\r Cleared by software setting the LSERDYC bit." + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: "HSI16 ready interrupt flag\r This flag indicates a pending interrupt upon HSI16 clock getting ready.\r Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in response to setting the HSION (refer to ). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Cleared by software setting the HSIRDYC bit." + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: "HSE ready interrupt flag\r This flag indicates a pending interrupt upon HSE clock getting ready.\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set.\r Cleared by software setting the HSERDYC bit." + bit_offset: 4 + bit_size: 1 + - name: CSSF + description: "HSE clock security system interrupt flag\r This flag indicates a pending interrupt upon HSE clock failure.\r Set by hardware when a failure is detected in the HSE oscillator.\r Cleared by software setting the CSSC bit." + bit_offset: 8 + bit_size: 1 + - name: LSECSSF + description: "LSE clock security system interrupt flag\r This flag indicates a pending interrupt upon LSE clock failure.\r Set by hardware when a failure is detected in the LSE oscillator.\r Cleared by software by setting the LSECSSC bit." + bit_offset: 9 + bit_size: 1 fieldset/CR: description: RCC clock control register fields: - - name: SYSDIV - description: "System clock division factor\r This bitfield controlled by software sets the division factor of the system clock divider to produce SYSCLK clock:" - bit_offset: 2 - bit_size: 3 - enum: SYSDIV - - name: HSIKERDIV - description: "HSI48 kernel clock division factor\r This bitfield controlled by software sets the division factor of the kernel clock divider to produce HSIKER clock:" - bit_offset: 5 - bit_size: 3 - enum: HSIKERDIV - - name: HSION - description: "HSI48 clock enable\r Set and cleared by software and hardware, with hardware taking priority.\r Kept low by hardware as long as the device is in a low-power mode.\r Kept high by hardware as long as the system is clocked with a clock derived from HSI48. This includes the exit from low-power modes and the system clock fall-back to HSI48 upon failing HSE oscillator clock selected as system clock source." - bit_offset: 8 - bit_size: 1 - - name: HSIKERON - description: "HSI48 always-enable for peripheral kernels.\r Set and cleared by software.\r Setting the bit activates the HSI48 oscillator in Run and Stop modes, regardless of the HSION bit state. The HSI48 clock can only feed USART1, USART2, and I2C1 peripherals configured with HSI48 as kernel clock.\r Note: Keeping the HSI48 active in Stop mode allows speeding up the serial interface communication as the HSI48 clock is ready immediately upon exiting Stop mode." - bit_offset: 9 - bit_size: 1 - - name: HSIRDY - description: "HSI48 clock ready flag\r Set by hardware when the HSI48 oscillator is enabled through HSION and ready to use (stable).\r Note: Upon clearing HSION, HSIRDY goes low after six HSI48 clock cycles." - bit_offset: 10 - bit_size: 1 - - name: HSIDIV - description: "HSI48 clock division factor\r This bitfield controlled by software sets the division factor of the HSI48 clock divider to produce HSISYS clock:" - bit_offset: 11 - bit_size: 3 - enum: HSIDIV - - name: HSEON - description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE oscillator when entering Stop, or Standby, or Shutdown mode. This bit cannot be cleared if the HSE oscillator is used directly or indirectly as the system clock." - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable and ready for use.\r Note: Upon clearing HSEON, HSERDY goes low after six HSE clock cycles." - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: "HSE crystal oscillator bypass\r Set and cleared by software.\r When the bit is set, the internal HSE oscillator is bypassed for use of an external clock. The external clock must then be enabled with the HSEON bit set. Write access to the bit is only effective when the HSE oscillator is disabled." - bit_offset: 18 - bit_size: 1 - - name: CSSON - description: "Clock security system enable\r Set by software to enable the clock security system. When the bit is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. The bit is cleared by hardware upon reset." - bit_offset: 19 - bit_size: 1 + - name: SYSDIV + description: "System clock division factor\r This bitfield controlled by software sets the division factor of the system clock divider to produce SYSCLK clock:" + bit_offset: 2 + bit_size: 3 + enum: SYSDIV + - name: HSIKERDIV + description: "HSI48 kernel clock division factor\r This bitfield controlled by software sets the division factor of the kernel clock divider to produce HSIKER clock:" + bit_offset: 5 + bit_size: 3 + enum: HSIKERDIV + - name: HSION + description: "HSI48 clock enable\r Set and cleared by software and hardware, with hardware taking priority.\r Kept low by hardware as long as the device is in a low-power mode.\r Kept high by hardware as long as the system is clocked with a clock derived from HSI48. This includes the exit from low-power modes and the system clock fall-back to HSI48 upon failing HSE oscillator clock selected as system clock source." + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: "HSI48 always-enable for peripheral kernels.\r Set and cleared by software.\r Setting the bit activates the HSI48 oscillator in Run and Stop modes, regardless of the HSION bit state. The HSI48 clock can only feed USART1, USART2, and I2C1 peripherals configured with HSI48 as kernel clock.\r Note: Keeping the HSI48 active in Stop mode allows speeding up the serial interface communication as the HSI48 clock is ready immediately upon exiting Stop mode." + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: "HSI48 clock ready flag\r Set by hardware when the HSI48 oscillator is enabled through HSION and ready to use (stable).\r Note: Upon clearing HSION, HSIRDY goes low after six HSI48 clock cycles." + bit_offset: 10 + bit_size: 1 + - name: HSIDIV + description: "HSI48 clock division factor\r This bitfield controlled by software sets the division factor of the HSI48 clock divider to produce HSISYS clock:" + bit_offset: 11 + bit_size: 3 + enum: HSIDIV + - name: HSEON + description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE oscillator when entering Stop, or Standby, or Shutdown mode. This bit cannot be cleared if the HSE oscillator is used directly or indirectly as the system clock." + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable and ready for use.\r Note: Upon clearing HSEON, HSERDY goes low after six HSE clock cycles." + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: "HSE crystal oscillator bypass\r Set and cleared by software.\r When the bit is set, the internal HSE oscillator is bypassed for use of an external clock. The external clock must then be enabled with the HSEON bit set. Write access to the bit is only effective when the HSE oscillator is disabled." + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: "Clock security system enable\r Set by software to enable the clock security system. When the bit is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. The bit is cleared by hardware upon reset." + bit_offset: 19 + bit_size: 1 fieldset/CSR1: description: RCC control/status register 1 fields: - - name: LSEON - description: "LSE oscillator enable\r Set and cleared by software to enable LSE oscillator:" - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: "LSE oscillator ready\r Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable):\r After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles." - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: "LSE oscillator bypass\r Set and cleared by software to bypass the LSE oscillator (in debug mode).\r This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0)." - bit_offset: 2 - bit_size: 1 - - name: LSEDRV - description: "LSE oscillator drive capability\r Set by software to select the LSE oscillator drive capability as follows:\r Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode." - bit_offset: 3 - bit_size: 2 - enum: LSEDRV - - name: LSECSSON - description: "CSS on LSE enable\r Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows:\r LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD\r =1). In that case the software must disable the LSECSSON bit." - bit_offset: 5 - bit_size: 1 - - name: LSECSSD - description: "CSS on LSE failure Detection\r Set by hardware to indicate when a failure is detected by the clock security system\r on the external 32 kHz oscillator (LSE):" - bit_offset: 6 - bit_size: 1 - - name: RTCSEL - description: "RTC clock source selection\r Set by software to select the clock source for the RTC as follows:\r Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The RTCRST bit can be used to reset this bitfield to 00." - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: "RTC clock enable\r Set and cleared by software. The bit enables clock to RTC and TAMP." - bit_offset: 15 - bit_size: 1 - - name: RTCRST - description: "RTC domain software reset\r Set and cleared by software to reset the RTC domain:" - bit_offset: 16 - bit_size: 1 - - name: LSCOEN - description: "Low-speed clock output (LSCO) enable\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: LSCOSEL - description: "Low-speed clock output selection\r Set and cleared by software to select the low-speed output clock:" - bit_offset: 25 - bit_size: 1 - enum: LSCOSEL + - name: LSEON + description: "LSE oscillator enable\r Set and cleared by software to enable LSE oscillator:" + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: "LSE oscillator ready\r Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable):\r After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles." + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: "LSE oscillator bypass\r Set and cleared by software to bypass the LSE oscillator (in debug mode).\r This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0)." + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: "LSE oscillator drive capability\r Set by software to select the LSE oscillator drive capability as follows:\r Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode." + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: "CSS on LSE enable\r Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows:\r LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD\r =1). In that case the software must disable the LSECSSON bit." + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: "CSS on LSE failure Detection\r Set by hardware to indicate when a failure is detected by the clock security system\r on the external 32 kHz oscillator (LSE):" + bit_offset: 6 + bit_size: 1 + - name: RTCSEL + description: "RTC clock source selection\r Set by software to select the clock source for the RTC as follows:\r Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The RTCRST bit can be used to reset this bitfield to 00." + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: "RTC clock enable\r Set and cleared by software. The bit enables clock to RTC and TAMP." + bit_offset: 15 + bit_size: 1 + - name: RTCRST + description: "RTC domain software reset\r Set and cleared by software to reset the RTC domain:" + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: "Low-speed clock output (LSCO) enable\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: "Low-speed clock output selection\r Set and cleared by software to select the low-speed output clock:" + bit_offset: 25 + bit_size: 1 + enum: LSCOSEL fieldset/CSR2: description: RCC control/status register 2 fields: - - name: LSION - description: "LSI oscillator enable\r Set and cleared by software to enable/disable the LSI oscillator:" - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is ready (stable):\r After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC." - bit_offset: 1 - bit_size: 1 - - name: RMVF - description: "Remove reset flags\r Set by software to clear the reset flags." - bit_offset: 23 - bit_size: 1 - - name: OBLRSTF - description: "Option byte loader reset flag\r Set by hardware when a reset from the Option byte loading occurs.\r Cleared by setting the RMVF bit." - bit_offset: 25 - bit_size: 1 - - name: PINRSTF - description: "Pin reset flag\r Set by hardware when a reset from the NRST pin occurs.\r Cleared by setting the RMVF bit." - bit_offset: 26 - bit_size: 1 - - name: PWRRSTF - description: "BOR or POR/PDR flag\r Set by hardware when a BOR or POR/PDR occurs.\r Cleared by setting the RMVF bit." - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: "Software reset flag\r Set by hardware when a software reset occurs.\r Cleared by setting the RMVF bit." - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: "Independent window watchdog reset flag\r Set by hardware when an independent watchdog reset domain occurs.\r Cleared by setting the RMVF bit." - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: "Window watchdog reset flag\r Set by hardware when a window watchdog reset occurs.\r Cleared by setting the RMVF bit." - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: "Low-power reset flag\r Set by hardware when a reset occurs due to illegal Stop, or Standby, or Shutdown mode entry.\r Cleared by setting the RMVF bit.\r This operates only if nRST_STOP, or nRST_STDBY or nRST_SHDW option bits are cleared." - bit_offset: 31 - bit_size: 1 + - name: LSION + description: "LSI oscillator enable\r Set and cleared by software to enable/disable the LSI oscillator:" + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is ready (stable):\r After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC." + bit_offset: 1 + bit_size: 1 + - name: RMVF + description: "Remove reset flags\r Set by software to clear the reset flags." + bit_offset: 23 + bit_size: 1 + - name: OBLRSTF + description: "Option byte loader reset flag\r Set by hardware when a reset from the Option byte loading occurs.\r Cleared by setting the RMVF bit." + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: "Pin reset flag\r Set by hardware when a reset from the NRST pin occurs.\r Cleared by setting the RMVF bit." + bit_offset: 26 + bit_size: 1 + - name: PWRRSTF + description: "BOR or POR/PDR flag\r Set by hardware when a BOR or POR/PDR occurs.\r Cleared by setting the RMVF bit." + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: "Software reset flag\r Set by hardware when a software reset occurs.\r Cleared by setting the RMVF bit." + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: "Independent window watchdog reset flag\r Set by hardware when an independent watchdog reset domain occurs.\r Cleared by setting the RMVF bit." + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: "Window watchdog reset flag\r Set by hardware when a window watchdog reset occurs.\r Cleared by setting the RMVF bit." + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: "Low-power reset flag\r Set by hardware when a reset occurs due to illegal Stop, or Standby, or Shutdown mode entry.\r Cleared by setting the RMVF bit.\r This operates only if nRST_STOP, or nRST_STDBY or nRST_SHDW option bits are cleared." + bit_offset: 31 + bit_size: 1 fieldset/GPIOENR: description: RCC I/O port clock enable register fields: - - name: GPIOAEN - description: "I/O port A clock enable\r This bit is set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: "I/O port B clock enable\r This bit is set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: "I/O port C clock enable\r This bit is set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: "I/O port D clock enable\r This bit is set and cleared by software." - bit_offset: 3 - bit_size: 1 - - name: GPIOFEN - description: "I/O port F clock enable\r This bit is set and cleared by software." - bit_offset: 5 - bit_size: 1 + - name: GPIOAEN + description: "I/O port A clock enable\r This bit is set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: "I/O port B clock enable\r This bit is set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: "I/O port C clock enable\r This bit is set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: "I/O port D clock enable\r This bit is set and cleared by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOFEN + description: "I/O port F clock enable\r This bit is set and cleared by software." + bit_offset: 5 + bit_size: 1 fieldset/GPIORSTR: description: RCC I/O port reset register fields: - - name: GPIOARST - description: "I/O port A reset\r This bit is set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: "I/O port B reset\r This bit is set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: "I/O port C reset\r This bit is set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: "I/O port D reset\r This bit is set and cleared by software." - bit_offset: 3 - bit_size: 1 - - name: GPIOFRST - description: "I/O port F reset\r This bit is set and cleared by software." - bit_offset: 5 - bit_size: 1 + - name: GPIOARST + description: "I/O port A reset\r This bit is set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: "I/O port B reset\r This bit is set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: "I/O port C reset\r This bit is set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: "I/O port D reset\r This bit is set and cleared by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOFRST + description: "I/O port F reset\r This bit is set and cleared by software." + bit_offset: 5 + bit_size: 1 fieldset/GPIOSMENR: description: RCC I/O port in Sleep mode clock enable register fields: - - name: GPIOASMEN - description: "I/O port A clock enable during Sleep mode\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: GPIOBSMEN - description: "I/O port B clock enable during Sleep mode\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: GPIOCSMEN - description: "I/O port C clock enable during Sleep mode\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: GPIODSMEN - description: "I/O port D clock enable during Sleep mode\r Set and cleared by software." - bit_offset: 3 - bit_size: 1 - - name: GPIOFSMEN - description: "I/O port F clock enable during Sleep mode\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 + - name: GPIOASMEN + description: "I/O port A clock enable during Sleep mode\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: "I/O port B clock enable during Sleep mode\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: "I/O port C clock enable during Sleep mode\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODSMEN + description: "I/O port D clock enable during Sleep mode\r Set and cleared by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOFSMEN + description: "I/O port F clock enable during Sleep mode\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 fieldset/ICSCR: description: RCC internal clock source calibration register fields: - - name: HSICAL - description: "HSI48 clock calibration\r This bitfield directly acts on the HSI48 clock frequency. Its value is a sum of an internal factory-programmed number and the value of the HSITRIM[6:0] bitfield. In the factory, the internal number is set to calibrate the HSI48 clock frequency to 48 MHz (with HSITRIM[6:0] left at its reset value). Refer to the device datasheet for HSI48 calibration accuracy and for the frequency trimming granularity.\r Note: The trimming effect presents discontinuities at HSICAL[7:0] multiples of 64." - bit_offset: 0 - bit_size: 8 - - name: HSITRIM - description: "HSI48 clock trimming\r The value of this bitfield contributes to the HSICAL[7:0] bitfield value.\r It allows HSI48 clock frequency user trimming.\r The HSI48 frequency accuracy as stated in the device datasheet applies when this bitfield is left at its reset value." - bit_offset: 8 - bit_size: 7 + - name: HSICAL + description: "HSI48 clock calibration\r This bitfield directly acts on the HSI48 clock frequency. Its value is a sum of an internal factory-programmed number and the value of the HSITRIM[6:0] bitfield. In the factory, the internal number is set to calibrate the HSI48 clock frequency to 48 MHz (with HSITRIM[6:0] left at its reset value). Refer to the device datasheet for HSI48 calibration accuracy and for the frequency trimming granularity.\r Note: The trimming effect presents discontinuities at HSICAL[7:0] multiples of 64." + bit_offset: 0 + bit_size: 8 + - name: HSITRIM + description: "HSI48 clock trimming\r The value of this bitfield contributes to the HSICAL[7:0] bitfield value.\r It allows HSI48 clock frequency user trimming.\r The HSI48 frequency accuracy as stated in the device datasheet applies when this bitfield is left at its reset value." + bit_offset: 8 + bit_size: 7 enum/ADCSEL: bit_size: 2 variants: - - name: SYSCLK - description: System clock - value: 0 - - name: HSIKER - description: HSIKER - value: 2 + - name: SYSCLK + description: System clock + value: 0 + - name: HSIKER + description: HSIKER + value: 2 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: SYSCLK not divided - value: 0 - - name: Div2 - description: SYSCLK is divided by 2 - value: 8 - - name: Div4 - description: SYSCLK is divided by 4 - value: 9 - - name: Div8 - description: SYSCLK is divided by 8 - value: 10 - - name: Div16 - description: SYSCLK is divided by 16 - value: 11 - - name: Div64 - description: SYSCLK is divided by 64 - value: 12 - - name: Div128 - description: SYSCLK is divided by 128 - value: 13 - - name: Div256 - description: SYSCLK is divided by 256 - value: 14 - - name: Div512 - description: SYSCLK is divided by 512 - value: 15 + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK is divided by 2 + value: 8 + - name: Div4 + description: SYSCLK is divided by 4 + value: 9 + - name: Div8 + description: SYSCLK is divided by 8 + value: 10 + - name: Div16 + description: SYSCLK is divided by 16 + value: 11 + - name: Div64 + description: SYSCLK is divided by 64 + value: 12 + - name: Div128 + description: SYSCLK is divided by 128 + value: 13 + - name: Div256 + description: SYSCLK is divided by 256 + value: 14 + - name: Div512 + description: SYSCLK is divided by 512 + value: 15 enum/HSIDIV: bit_size: 3 variants: - - name: Div1 - description: HSI clock is not divided - value: 0 - - name: Div2 - description: HSI clock is divided by 2 - value: 1 - - name: Div4 - description: HSI clock is divided by 4 - value: 2 - - name: Div8 - description: HSI clock is divided by 8 - value: 3 - - name: Div16 - description: HSI clock is divided by 16 - value: 4 - - name: Div32 - description: HSI clock is divided by 32 - value: 5 - - name: Div64 - description: HSI clock is divided by 64 - value: 6 - - name: Div128 - description: HSI clock is divided by 128 - value: 7 + - name: Div1 + description: HSI clock is not divided + value: 0 + - name: Div2 + description: HSI clock is divided by 2 + value: 1 + - name: Div4 + description: HSI clock is divided by 4 + value: 2 + - name: Div8 + description: HSI clock is divided by 8 + value: 3 + - name: Div16 + description: HSI clock is divided by 16 + value: 4 + - name: Div32 + description: HSI clock is divided by 32 + value: 5 + - name: Div64 + description: HSI clock is divided by 64 + value: 6 + - name: Div128 + description: HSI clock is divided by 128 + value: 7 enum/HSIKERDIV: bit_size: 3 variants: - - name: Div1 - description: "1" - value: 0 - - name: Div2 - description: "2" - value: 1 - - name: Div3 - description: 3 (reset value) - value: 2 - - name: Div4 - description: "4" - value: 3 - - name: Div5 - description: "5" - value: 4 - - name: Div6 - description: "6" - value: 5 - - name: Div7 - description: "7" - value: 6 - - name: Div8 - description: "8" - value: 7 + - name: Div1 + description: '1' + value: 0 + - name: Div2 + description: '2' + value: 1 + - name: Div3 + description: 3 (reset value) + value: 2 + - name: Div4 + description: '4' + value: 3 + - name: Div5 + description: '5' + value: 4 + - name: Div6 + description: '6' + value: 5 + - name: Div7 + description: '7' + value: 6 + - name: Div8 + description: '8' + value: 7 enum/I2C1SEL: bit_size: 2 variants: - - name: PCLK - description: PCLK - value: 0 - - name: SYSCLK - description: SYSCLK - value: 1 - - name: HSIKER - description: HSIKER - value: 2 + - name: PCLK + description: PCLK + value: 0 + - name: SYSCLK + description: SYSCLK + value: 1 + - name: HSIKER + description: HSIKER + value: 2 enum/I2S1SEL: bit_size: 2 variants: - - name: SYSCLK - description: SYSCLK - value: 0 - - name: HSIKER - description: HSIKER - value: 2 - - name: I2S_CKIN - description: I2S_CKIN - value: 3 + - name: SYSCLK + description: SYSCLK + value: 0 + - name: HSIKER + description: HSIKER + value: 2 + - name: I2S_CKIN + description: I2S_CKIN + value: 3 enum/LSCOSEL: bit_size: 1 variants: - - name: LSI - description: LSI - value: 0 - - name: LSE - description: LSE - value: 1 + - name: LSI + description: LSI + value: 0 + - name: LSE + description: LSE + value: 1 enum/LSEDRV: bit_size: 2 variants: - - name: Low - description: Low driving capability - value: 0 - - name: MediumLow - description: Medium low driving capability - value: 1 - - name: MediumHigh - description: Medium high driving capability - value: 2 - - name: High - description: High driving capability - value: 3 + - name: Low + description: Low driving capability + value: 0 + - name: MediumLow + description: Medium low driving capability + value: 1 + - name: MediumHigh + description: Medium high driving capability + value: 2 + - name: High + description: High driving capability + value: 3 enum/MCOPRE: bit_size: 4 variants: - - name: Div1 - description: MCO2 not divided - value: 0 - - name: Div2 - description: MCO clock is divided by 2 - value: 1 - - name: Div4 - description: MCO clock is divided by 4 - value: 2 - - name: Div8 - description: MCO clock is divided by 8 - value: 3 - - name: Div16 - description: MCO clock is divided divided by 16 - value: 4 - - name: Div32 - description: MCO clock is divided divided by 32 - value: 5 - - name: Div64 - description: MCO clock is divided divided by 64 - value: 6 - - name: Div128 - description: MCO clock is divided divided by 128 - value: 7 + - name: Div1 + description: MCO2 not divided + value: 0 + - name: Div2 + description: MCO clock is divided by 2 + value: 1 + - name: Div4 + description: MCO clock is divided by 4 + value: 2 + - name: Div8 + description: MCO clock is divided by 8 + value: 3 + - name: Div16 + description: MCO clock is divided divided by 16 + value: 4 + - name: Div32 + description: MCO clock is divided divided by 32 + value: 5 + - name: Div64 + description: MCO clock is divided divided by 64 + value: 6 + - name: Div128 + description: MCO clock is divided divided by 128 + value: 7 enum/MCOSEL: bit_size: 4 variants: - - name: NoClock - description: "No clock, MCO output disabled" - value: 0 - - name: SYSCLK - description: SYSCLK selected as MCO source - value: 1 - - name: HSI48 - description: HSI48 selected as MCO source - value: 3 - - name: HSE - description: HSE selected as MCO source - value: 4 - - name: LSI - description: LSI selected as MCO source - value: 6 - - name: LSE - description: LSE selected as MCO source - value: 7 + - name: NoClock + description: No clock, MCO output disabled + value: 0 + - name: SYSCLK + description: SYSCLK selected as MCO source + value: 1 + - name: HSI48 + description: HSI48 selected as MCO source + value: 3 + - name: HSE + description: HSE selected as MCO source + value: 4 + - name: LSI + description: LSI selected as MCO source + value: 6 + - name: LSE + description: LSE selected as MCO source + value: 7 enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK is divided by 2 - value: 4 - - name: Div4 - description: HCLK is divided by 4 - value: 5 - - name: Div8 - description: HCLK is divided by 8 - value: 6 - - name: Div16 - description: HCLK is divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK is divided by 2 + value: 4 + - name: Div4 + description: HCLK is divided by 4 + value: 5 + - name: Div8 + description: HCLK is divided by 8 + value: 6 + - name: Div16 + description: HCLK is divided by 16 + value: 7 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock used as RTC clock - value: 0 - - name: LSE - description: LSE used as RTC clock - value: 1 - - name: LSI - description: LSI used as RTC clock - value: 2 - - name: HSE_Div32 - description: HSE divided by 32 used as RTC clock - value: 3 + - name: NoClock + description: No clock used as RTC clock + value: 0 + - name: LSE + description: LSE used as RTC clock + value: 1 + - name: LSI + description: LSI used as RTC clock + value: 2 + - name: HSE_Div32 + description: HSE divided by 32 used as RTC clock + value: 3 enum/SW: bit_size: 3 variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: HSE - description: HSE selected as system clock - value: 1 - - name: LSI - description: LSI selected as system clock - value: 3 - - name: LSE - description: LSE selected as system clock - value: 4 + - name: HSI + description: HSI selected as system clock + value: 0 + - name: HSE + description: HSE selected as system clock + value: 1 + - name: LSI + description: LSI selected as system clock + value: 3 + - name: LSE + description: LSE selected as system clock + value: 4 enum/SYSDIV: bit_size: 3 variants: - - name: Div1 - description: "1" - value: 0 - - name: Div2 - description: "2" - value: 1 - - name: Div3 - description: 3 (reset value) - value: 2 - - name: Div4 - description: "4" - value: 3 - - name: Div5 - description: "5" - value: 4 - - name: Div6 - description: "6" - value: 5 - - name: Div7 - description: "7" - value: 6 - - name: Div8 - description: "8" - value: 7 + - name: Div1 + description: '1' + value: 0 + - name: Div2 + description: '2' + value: 1 + - name: Div3 + description: 3 (reset value) + value: 2 + - name: Div4 + description: '4' + value: 3 + - name: Div5 + description: '5' + value: 4 + - name: Div6 + description: '6' + value: 5 + - name: Div7 + description: '7' + value: 6 + - name: Div8 + description: '8' + value: 7 enum/USART1SEL: bit_size: 2 variants: - - name: PCLK - description: PCLK - value: 0 - - name: SYSCLK - description: SYSCLK - value: 1 - - name: HSIKER - description: HSIKER - value: 2 - - name: LSE - description: LSE - value: 3 + - name: PCLK + description: PCLK + value: 0 + - name: SYSCLK + description: SYSCLK + value: 1 + - name: HSIKER + description: HSIKER + value: 2 + - name: LSE + description: LSE + value: 3 diff --git a/data/registers/rcc_f0.yaml b/data/registers/rcc_f0.yaml index d2b860f..d15a076 100644 --- a/data/registers/rcc_f0.yaml +++ b/data/registers/rcc_f0.yaml @@ -1,1099 +1,1083 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: Clock control register - byte_offset: 0 - fieldset: CR - - name: CFGR - description: Clock configuration register (RCC_CFGR) - byte_offset: 4 - fieldset: CFGR - - name: CIR - description: Clock interrupt register (RCC_CIR) - byte_offset: 8 - fieldset: CIR - - name: APB2RSTR - description: APB2 peripheral reset register (RCC_APB2RSTR) - byte_offset: 12 - fieldset: APB2RSTR - - name: APB1RSTR - description: APB1 peripheral reset register (RCC_APB1RSTR) - byte_offset: 16 - fieldset: APB1RSTR - - name: AHBENR - description: AHB Peripheral Clock enable register (RCC_AHBENR) - byte_offset: 20 - fieldset: AHBENR - - name: APB2ENR - description: APB2 peripheral clock enable register (RCC_APB2ENR) - byte_offset: 24 - fieldset: APB2ENR - - name: APB1ENR - description: APB1 peripheral clock enable register (RCC_APB1ENR) - byte_offset: 28 - fieldset: APB1ENR - - name: BDCR - description: Backup domain control register (RCC_BDCR) - byte_offset: 32 - fieldset: BDCR - - name: CSR - description: Control/status register (RCC_CSR) - byte_offset: 36 - fieldset: CSR - - name: AHBRSTR - description: AHB peripheral reset register - byte_offset: 40 - fieldset: AHBRSTR - - name: CFGR2 - description: Clock configuration register 2 - byte_offset: 44 - fieldset: CFGR2 - - name: CFGR3 - description: Clock configuration register 3 - byte_offset: 48 - fieldset: CFGR3 - - name: CR2 - description: Clock control register 2 - byte_offset: 52 - fieldset: CR2 + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: CFGR + description: Clock configuration register (RCC_CFGR) + byte_offset: 4 + fieldset: CFGR + - name: CIR + description: Clock interrupt register (RCC_CIR) + byte_offset: 8 + fieldset: CIR + - name: APB2RSTR + description: APB2 peripheral reset register (RCC_APB2RSTR) + byte_offset: 12 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register (RCC_APB1RSTR) + byte_offset: 16 + fieldset: APB1RSTR + - name: AHBENR + description: AHB Peripheral Clock enable register (RCC_AHBENR) + byte_offset: 20 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register (RCC_APB2ENR) + byte_offset: 24 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register (RCC_APB1ENR) + byte_offset: 28 + fieldset: APB1ENR + - name: BDCR + description: Backup domain control register (RCC_BDCR) + byte_offset: 32 + fieldset: BDCR + - name: CSR + description: Control/status register (RCC_CSR) + byte_offset: 36 + fieldset: CSR + - name: AHBRSTR + description: AHB peripheral reset register + byte_offset: 40 + fieldset: AHBRSTR + - name: CFGR2 + description: Clock configuration register 2 + byte_offset: 44 + fieldset: CFGR2 + - name: CFGR3 + description: Clock configuration register 3 + byte_offset: 48 + fieldset: CFGR3 + - name: CR2 + description: Clock control register 2 + byte_offset: 52 + fieldset: CR2 fieldset/AHBENR: description: AHB Peripheral Clock enable register (RCC_AHBENR) fields: - - name: DMAEN - description: DMA clock enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: DMA2 clock enable - bit_offset: 1 - bit_size: 1 - - name: SRAMEN - description: SRAM interface clock enable - bit_offset: 2 - bit_size: 1 - - name: FLASHEN - description: FLASH clock enable - bit_offset: 4 - bit_size: 1 - - name: CRCEN - description: CRC clock enable - bit_offset: 6 - bit_size: 1 - - name: GPIOAEN - description: I/O port A clock enable - bit_offset: 17 - bit_size: 1 - - name: GPIOBEN - description: I/O port B clock enable - bit_offset: 18 - bit_size: 1 - - name: GPIOCEN - description: I/O port C clock enable - bit_offset: 19 - bit_size: 1 - - name: GPIODEN - description: I/O port D clock enable - bit_offset: 20 - bit_size: 1 - - name: GPIOEEN - description: I/O port E clock enable - bit_offset: 21 - bit_size: 1 - - name: GPIOFEN - description: I/O port F clock enable - bit_offset: 22 - bit_size: 1 - - name: TSCEN - description: Touch sensing controller clock enable - bit_offset: 24 - bit_size: 1 + - name: DMAEN + description: DMA clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: SRAMEN + description: SRAM interface clock enable + bit_offset: 2 + bit_size: 1 + - name: FLASHEN + description: FLASH clock enable + bit_offset: 4 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOAEN + description: I/O port A clock enable + bit_offset: 17 + bit_size: 1 + - name: GPIOBEN + description: I/O port B clock enable + bit_offset: 18 + bit_size: 1 + - name: GPIOCEN + description: I/O port C clock enable + bit_offset: 19 + bit_size: 1 + - name: GPIODEN + description: I/O port D clock enable + bit_offset: 20 + bit_size: 1 + - name: GPIOEEN + description: I/O port E clock enable + bit_offset: 21 + bit_size: 1 + - name: GPIOFEN + description: I/O port F clock enable + bit_offset: 22 + bit_size: 1 + - name: TSCEN + description: Touch sensing controller clock enable + bit_offset: 24 + bit_size: 1 fieldset/AHBRSTR: description: AHB peripheral reset register fields: - - name: GPIOARST - description: I/O port A reset - bit_offset: 17 - bit_size: 1 - - name: GPIOBRST - description: I/O port B reset - bit_offset: 18 - bit_size: 1 - - name: GPIOCRST - description: I/O port C reset - bit_offset: 19 - bit_size: 1 - - name: GPIODRST - description: I/O port D reset - bit_offset: 20 - bit_size: 1 - - name: GPIOERST - description: I/O port E reset - bit_offset: 21 - bit_size: 1 - - name: GPIOFRST - description: I/O port F reset - bit_offset: 22 - bit_size: 1 - - name: TSCRST - description: Touch sensing controller reset - bit_offset: 24 - bit_size: 1 + - name: GPIOARST + description: I/O port A reset + bit_offset: 17 + bit_size: 1 + - name: GPIOBRST + description: I/O port B reset + bit_offset: 18 + bit_size: 1 + - name: GPIOCRST + description: I/O port C reset + bit_offset: 19 + bit_size: 1 + - name: GPIODRST + description: I/O port D reset + bit_offset: 20 + bit_size: 1 + - name: GPIOERST + description: I/O port E reset + bit_offset: 21 + bit_size: 1 + - name: GPIOFRST + description: I/O port F reset + bit_offset: 22 + bit_size: 1 + - name: TSCRST + description: Touch sensing controller reset + bit_offset: 24 + bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register (RCC_APB1ENR) fields: - - name: TIM2EN - description: Timer 2 clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: Timer 3 clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM6EN - description: Timer 6 clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: TIM7 timer clock enable - bit_offset: 5 - bit_size: 1 - - name: TIM14EN - description: Timer 14 clock enable - bit_offset: 8 - bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI 2 clock enable - bit_offset: 14 - bit_size: 1 - - name: USART2EN - description: USART 2 clock enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART3 clock enable - bit_offset: 18 - bit_size: 1 - - name: USART4EN - description: USART4 clock enable - bit_offset: 19 - bit_size: 1 - - name: USART5EN - description: USART5 clock enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C 1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C 2 clock enable - bit_offset: 22 - bit_size: 1 - - name: USBEN - description: USB interface clock enable - bit_offset: 23 - bit_size: 1 - - name: CANEN - description: CAN interface clock enable - bit_offset: 25 - bit_size: 1 - - name: CRSEN - description: Clock Recovery System interface clock enable - bit_offset: 27 - bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - - name: DACEN - description: DAC interface clock enable - bit_offset: 29 - bit_size: 1 - - name: CECEN - description: HDMI CEC interface clock enable - bit_offset: 30 - bit_size: 1 + - name: TIM2EN + description: Timer 2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM7 timer clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM14EN + description: Timer 14 clock enable + bit_offset: 8 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI 2 clock enable + bit_offset: 14 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 clock enable + bit_offset: 18 + bit_size: 1 + - name: USART4EN + description: USART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: USART5EN + description: USART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C 2 clock enable + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: USB interface clock enable + bit_offset: 23 + bit_size: 1 + - name: CANEN + description: CAN interface clock enable + bit_offset: 25 + bit_size: 1 + - name: CRSEN + description: Clock Recovery System interface clock enable + bit_offset: 27 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: CECEN + description: HDMI CEC interface clock enable + bit_offset: 30 + bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register (RCC_APB1RSTR) fields: - - name: TIM2RST - description: Timer 2 reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: Timer 3 reset - bit_offset: 1 - bit_size: 1 - - name: TIM6RST - description: Timer 6 reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: TIM7 timer reset - bit_offset: 5 - bit_size: 1 - - name: TIM14RST - description: Timer 14 reset - bit_offset: 8 - bit_size: 1 - - name: WWDGRST - description: Window watchdog reset - bit_offset: 11 - bit_size: 1 - - name: SPI2RST - description: SPI2 reset - bit_offset: 14 - bit_size: 1 - - name: USART2RST - description: USART 2 reset - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: USART3 reset - bit_offset: 18 - bit_size: 1 - - name: USART4RST - description: USART4 reset - bit_offset: 19 - bit_size: 1 - - name: USART5RST - description: USART5 reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C2 reset - bit_offset: 22 - bit_size: 1 - - name: USBRST - description: USB interface reset - bit_offset: 23 - bit_size: 1 - - name: CANRST - description: CAN interface reset - bit_offset: 25 - bit_size: 1 - - name: CRSRST - description: Clock Recovery System interface reset - bit_offset: 27 - bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - - name: DACRST - description: DAC interface reset - bit_offset: 29 - bit_size: 1 - - name: CECRST - description: HDMI CEC reset - bit_offset: 30 - bit_size: 1 + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM6RST + description: Timer 6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM7 timer reset + bit_offset: 5 + bit_size: 1 + - name: TIM14RST + description: Timer 14 reset + bit_offset: 8 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 reset + bit_offset: 18 + bit_size: 1 + - name: USART4RST + description: USART4 reset + bit_offset: 19 + bit_size: 1 + - name: USART5RST + description: USART5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: USB interface reset + bit_offset: 23 + bit_size: 1 + - name: CANRST + description: CAN interface reset + bit_offset: 25 + bit_size: 1 + - name: CRSRST + description: Clock Recovery System interface reset + bit_offset: 27 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 + - name: CECRST + description: HDMI CEC reset + bit_offset: 30 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register (RCC_APB2ENR) fields: - - name: SYSCFGEN - description: SYSCFG clock enable - bit_offset: 0 - bit_size: 1 - - name: USART6EN - description: USART6 clock enable - bit_offset: 5 - bit_size: 1 - - name: USART7EN - description: USART7 clock enable - bit_offset: 6 - bit_size: 1 - - name: USART8EN - description: USART8 clock enable - bit_offset: 7 - bit_size: 1 - - name: ADCEN - description: ADC 1 interface clock enable - bit_offset: 9 - bit_size: 1 - - name: TIM1EN - description: TIM1 Timer clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: SPI 1 clock enable - bit_offset: 12 - bit_size: 1 - - name: USART1EN - description: USART1 clock enable - bit_offset: 14 - bit_size: 1 - - name: TIM15EN - description: TIM15 timer clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: TIM16 timer clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: TIM17 timer clock enable - bit_offset: 18 - bit_size: 1 - - name: DBGMCUEN - description: MCU debug module clock enable - bit_offset: 22 - bit_size: 1 + - name: SYSCFGEN + description: SYSCFG clock enable + bit_offset: 0 + bit_size: 1 + - name: USART6EN + description: USART6 clock enable + bit_offset: 5 + bit_size: 1 + - name: USART7EN + description: USART7 clock enable + bit_offset: 6 + bit_size: 1 + - name: USART8EN + description: USART8 clock enable + bit_offset: 7 + bit_size: 1 + - name: ADCEN + description: ADC 1 interface clock enable + bit_offset: 9 + bit_size: 1 + - name: TIM1EN + description: TIM1 Timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM15EN + description: TIM15 timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: DBGMCUEN + description: MCU debug module clock enable + bit_offset: 22 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register (RCC_APB2RSTR) fields: - - name: SYSCFGRST - description: SYSCFG and COMP reset - bit_offset: 0 - bit_size: 1 - - name: USART6RST - description: USART6 reset - bit_offset: 5 - bit_size: 1 - - name: USART7RST - description: USART7 reset - bit_offset: 6 - bit_size: 1 - - name: USART8RST - description: USART8 reset - bit_offset: 7 - bit_size: 1 - - name: ADCRST - description: ADC interface reset - bit_offset: 9 - bit_size: 1 - - name: TIM1RST - description: TIM1 timer reset - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: SPI 1 reset - bit_offset: 12 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 14 - bit_size: 1 - - name: TIM15RST - description: TIM15 timer reset - bit_offset: 16 - bit_size: 1 - - name: TIM16RST - description: TIM16 timer reset - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: TIM17 timer reset - bit_offset: 18 - bit_size: 1 - - name: DBGMCURST - description: Debug MCU reset - bit_offset: 22 - bit_size: 1 + - name: SYSCFGRST + description: SYSCFG and COMP reset + bit_offset: 0 + bit_size: 1 + - name: USART6RST + description: USART6 reset + bit_offset: 5 + bit_size: 1 + - name: USART7RST + description: USART7 reset + bit_offset: 6 + bit_size: 1 + - name: USART8RST + description: USART8 reset + bit_offset: 7 + bit_size: 1 + - name: ADCRST + description: ADC interface reset + bit_offset: 9 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: DBGMCURST + description: Debug MCU reset + bit_offset: 22 + bit_size: 1 fieldset/BDCR: description: Backup domain control register (RCC_BDCR) fields: - - name: LSEON - description: External Low Speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: External Low Speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: External Low Speed oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: LSEDRV - description: LSE oscillator drive capability - bit_offset: 3 - bit_size: 2 - enum: LSEDRV - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: Backup domain software reset - bit_offset: 16 - bit_size: 1 + - name: LSEON + description: External Low Speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External Low Speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: External Low Speed oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: LSE oscillator drive capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 fieldset/CFGR: description: Clock configuration register (RCC_CFGR) fields: - - name: SW - description: System clock Switch - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: System Clock Switch Status - bit_offset: 2 - bit_size: 2 - enum: SWS - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - enum: HPRE - - name: PPRE - description: APB Low speed prescaler (APB1) - bit_offset: 8 - bit_size: 3 - enum: PPRE - - name: ADCPRE - description: APCPRE is deprecated. See ADC field in CFGR2 register. - bit_offset: 14 - bit_size: 1 - - name: PLLSRC - description: PLL input clock source - bit_offset: 15 - bit_size: 2 - enum: PLLSRC - - name: PLLXTPRE - description: "HSE divider for PLL entry. Same bit as PREDIC[0] from CFGR2 register. Refer to it for its meaning" - bit_offset: 17 - bit_size: 1 - enum: PLLXTPRE - - name: PLLMUL - description: PLL Multiplication Factor - bit_offset: 18 - bit_size: 4 - enum: PLLMUL - - name: MCO - description: Microcontroller clock output - bit_offset: 24 - bit_size: 3 - enum: MCO - - name: MCOPRE - description: Microcontroller Clock Output Prescaler - bit_offset: 28 - bit_size: 3 - enum: MCOPRE - - name: PLLNODIV - description: PLL clock not divided for MCO - bit_offset: 31 - bit_size: 1 - enum: PLLNODIV + - name: SW + description: System clock Switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System Clock Switch Status + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE + description: APB Low speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: ADCPRE + description: APCPRE is deprecated. See ADC field in CFGR2 register. + bit_offset: 14 + bit_size: 1 + - name: PLLSRC + description: PLL input clock source + bit_offset: 15 + bit_size: 2 + enum: PLLSRC + - name: PLLXTPRE + description: HSE divider for PLL entry. Same bit as PREDIC[0] from CFGR2 register. Refer to it for its meaning + bit_offset: 17 + bit_size: 1 + enum: PLLXTPRE + - name: PLLMUL + description: PLL Multiplication Factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: MCO + description: Microcontroller clock output + bit_offset: 24 + bit_size: 3 + enum: MCO + - name: MCOPRE + description: Microcontroller Clock Output Prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE + - name: PLLNODIV + description: PLL clock not divided for MCO + bit_offset: 31 + bit_size: 1 + enum: PLLNODIV fieldset/CFGR2: description: Clock configuration register 2 fields: - - name: PREDIV - description: PREDIV division factor - bit_offset: 0 - bit_size: 4 - enum: PREDIV + - name: PREDIV + description: PREDIV division factor + bit_offset: 0 + bit_size: 4 + enum: PREDIV fieldset/CFGR3: description: Clock configuration register 3 fields: - - name: USART1SW - description: USART1 clock source selection - bit_offset: 0 - bit_size: 2 - enum: USARTSW - - name: I2C1SW - description: I2C1 clock source selection - bit_offset: 4 - bit_size: 1 - enum: ICSW - - name: CECSW - description: HDMI CEC clock source selection - bit_offset: 6 - bit_size: 1 - enum: CECSW - - name: USBSW - description: USB clock source selection - bit_offset: 7 - bit_size: 1 - enum: USBSW - - name: ADCSW - description: ADCSW is deprecated. See ADC field in CFGR2 register. - bit_offset: 8 - bit_size: 1 - - name: USART2SW - description: USART2 clock source selection - bit_offset: 16 - bit_size: 2 - enum: USARTSW - - name: USART3SW - description: USART3 clock source - bit_offset: 18 - bit_size: 2 - enum: USARTSW + - name: USART1SW + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + enum: USARTSW + - name: I2C1SW + description: I2C1 clock source selection + bit_offset: 4 + bit_size: 1 + enum: ICSW + - name: CECSW + description: HDMI CEC clock source selection + bit_offset: 6 + bit_size: 1 + enum: CECSW + - name: USBSW + description: USB clock source selection + bit_offset: 7 + bit_size: 1 + enum: USBSW + - name: ADCSW + description: ADCSW is deprecated. See ADC field in CFGR2 register. + bit_offset: 8 + bit_size: 1 + - name: USART2SW + description: USART2 clock source selection + bit_offset: 16 + bit_size: 2 + enum: USARTSW + - name: USART3SW + description: USART3 clock source + bit_offset: 18 + bit_size: 2 + enum: USARTSW fieldset/CIR: description: Clock interrupt register (RCC_CIR) fields: - - name: LSIRDYF - description: LSI Ready Interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE Ready Interrupt flag - bit_offset: 1 - bit_size: 1 - - name: HSIRDYF - description: HSI Ready Interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSERDYF - description: HSE Ready Interrupt flag - bit_offset: 3 - bit_size: 1 - - name: PLLRDYF - description: PLL Ready Interrupt flag - bit_offset: 4 - bit_size: 1 - - name: HSI14RDYF - description: HSI14 ready interrupt flag - bit_offset: 5 - bit_size: 1 - - name: HSI48RDYF - description: HSI48 ready interrupt flag - bit_offset: 6 - bit_size: 1 - - name: CSSF - description: Clock Security System Interrupt flag - bit_offset: 7 - bit_size: 1 - - name: LSIRDYIE - description: LSI Ready Interrupt Enable - bit_offset: 8 - bit_size: 1 - - name: LSERDYIE - description: LSE Ready Interrupt Enable - bit_offset: 9 - bit_size: 1 - - name: HSIRDYIE - description: HSI Ready Interrupt Enable - bit_offset: 10 - bit_size: 1 - - name: HSERDYIE - description: HSE Ready Interrupt Enable - bit_offset: 11 - bit_size: 1 - - name: PLLRDYIE - description: PLL Ready Interrupt Enable - bit_offset: 12 - bit_size: 1 - - name: HSI14RDYIE - description: HSI14 ready interrupt enable - bit_offset: 13 - bit_size: 1 - - name: HSI48RDYIE - description: HSI48 ready interrupt enable - bit_offset: 14 - bit_size: 1 - - name: LSIRDYC - description: LSI Ready Interrupt Clear - bit_offset: 16 - bit_size: 1 - - name: LSERDYC - description: LSE Ready Interrupt Clear - bit_offset: 17 - bit_size: 1 - - name: HSIRDYC - description: HSI Ready Interrupt Clear - bit_offset: 18 - bit_size: 1 - - name: HSERDYC - description: HSE Ready Interrupt Clear - bit_offset: 19 - bit_size: 1 - - name: PLLRDYC - description: PLL Ready Interrupt Clear - bit_offset: 20 - bit_size: 1 - - name: HSI14RDYC - description: HSI 14 MHz Ready Interrupt Clear - bit_offset: 21 - bit_size: 1 - - name: HSI48RDYC - description: HSI48 Ready Interrupt Clear - bit_offset: 22 - bit_size: 1 - - name: CSSC - description: Clock security system interrupt clear - bit_offset: 23 - bit_size: 1 + - name: LSIRDYF + description: LSI Ready Interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE Ready Interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI Ready Interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE Ready Interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: PLL Ready Interrupt flag + bit_offset: 4 + bit_size: 1 + - name: HSI14RDYF + description: HSI14 ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: HSI48RDYF + description: HSI48 ready interrupt flag + bit_offset: 6 + bit_size: 1 + - name: CSSF + description: Clock Security System Interrupt flag + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI Ready Interrupt Enable + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE Ready Interrupt Enable + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI Ready Interrupt Enable + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE Ready Interrupt Enable + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: PLL Ready Interrupt Enable + bit_offset: 12 + bit_size: 1 + - name: HSI14RDYIE + description: HSI14 ready interrupt enable + bit_offset: 13 + bit_size: 1 + - name: HSI48RDYIE + description: HSI48 ready interrupt enable + bit_offset: 14 + bit_size: 1 + - name: LSIRDYC + description: LSI Ready Interrupt Clear + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE Ready Interrupt Clear + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI Ready Interrupt Clear + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE Ready Interrupt Clear + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: PLL Ready Interrupt Clear + bit_offset: 20 + bit_size: 1 + - name: HSI14RDYC + description: HSI 14 MHz Ready Interrupt Clear + bit_offset: 21 + bit_size: 1 + - name: HSI48RDYC + description: HSI48 Ready Interrupt Clear + bit_offset: 22 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 fieldset/CR: description: Clock control register fields: - - name: HSION - description: Internal High Speed clock enable - bit_offset: 0 - bit_size: 1 - - name: HSIRDY - description: Internal High Speed clock ready flag - bit_offset: 1 - bit_size: 1 - - name: HSITRIM - description: Internal High Speed clock trimming - bit_offset: 3 - bit_size: 5 - - name: HSICAL - description: Internal High Speed clock Calibration - bit_offset: 8 - bit_size: 8 - - name: HSEON - description: External High Speed clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: External High Speed clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: External High Speed clock Bypass - bit_offset: 18 - bit_size: 1 - - name: CSSON - description: Clock Security System enable - bit_offset: 19 - bit_size: 1 - - name: PLLON - description: PLL enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: PLL clock ready flag - bit_offset: 25 - bit_size: 1 + - name: HSION + description: Internal High Speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal High Speed clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSITRIM + description: Internal High Speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal High Speed clock Calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: External High Speed clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: External High Speed clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: External High Speed clock Bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 fieldset/CR2: description: Clock control register 2 fields: - - name: HSI14ON - description: HSI14 clock enable - bit_offset: 0 - bit_size: 1 - - name: HSI14RDY - description: HR14 clock ready flag - bit_offset: 1 - bit_size: 1 - - name: HSI14DIS - description: HSI14 clock request from ADC disable - bit_offset: 2 - bit_size: 1 - - name: HSI14TRIM - description: HSI14 clock trimming - bit_offset: 3 - bit_size: 5 - - name: HSI14CAL - description: HSI14 clock calibration - bit_offset: 8 - bit_size: 8 - - name: HSI48ON - description: HSI48 clock enable - bit_offset: 16 - bit_size: 1 - - name: HSI48RDY - description: HSI48 clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSI48CAL - description: HSI48 factory clock calibration - bit_offset: 24 - bit_size: 8 + - name: HSI14ON + description: HSI14 clock enable + bit_offset: 0 + bit_size: 1 + - name: HSI14RDY + description: HR14 clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSI14DIS + description: HSI14 clock request from ADC disable + bit_offset: 2 + bit_size: 1 + - name: HSI14TRIM + description: HSI14 clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSI14CAL + description: HSI14 clock calibration + bit_offset: 8 + bit_size: 8 + - name: HSI48ON + description: HSI48 clock enable + bit_offset: 16 + bit_size: 1 + - name: HSI48RDY + description: HSI48 clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSI48CAL + description: HSI48 factory clock calibration + bit_offset: 24 + bit_size: 8 fieldset/CSR: description: Control/status register (RCC_CSR) fields: - - name: LSION - description: Internal low speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: Internal low speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: V18PWRRSTF - description: 1.8 V domain reset flag - bit_offset: 23 - bit_size: 1 - - name: RMVF - description: Remove reset flag - bit_offset: 24 - bit_size: 1 - - name: OBLRSTF - description: Option byte loader reset flag - bit_offset: 25 - bit_size: 1 - - name: PINRSTF - description: PIN reset flag - bit_offset: 26 - bit_size: 1 - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: Independent watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSION + description: Internal low speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: V18PWRRSTF + description: 1.8 V domain reset flag + bit_offset: 23 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 enum/CECSW: bit_size: 1 variants: - - name: HSI_Div244 - description: HSI clock divided by 244 selected as CEC clock source - value: 0 - - name: LSE - description: LSE clock selected as CEC clock source - value: 1 + - name: HSI_Div244 + description: HSI clock divided by 244 selected as CEC clock source + value: 0 + - name: LSE + description: LSE clock selected as CEC clock source + value: 1 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: SYSCLK not divided - value: 0 - - name: Div2 - description: SYSCLK divided by 2 - value: 8 - - name: Div4 - description: SYSCLK divided by 4 - value: 9 - - name: Div8 - description: SYSCLK divided by 8 - value: 10 - - name: Div16 - description: SYSCLK divided by 16 - value: 11 - - name: Div64 - description: SYSCLK divided by 64 - value: 12 - - name: Div128 - description: SYSCLK divided by 128 - value: 13 - - name: Div256 - description: SYSCLK divided by 256 - value: 14 - - name: Div512 - description: SYSCLK divided by 512 - value: 15 + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 enum/ICSW: bit_size: 1 variants: - - name: HSI - description: HSI clock selected as I2C clock source - value: 0 - - name: SYSCLK - description: SYSCLK clock selected as I2C clock source - value: 1 + - name: HSI + description: HSI clock selected as I2C clock source + value: 0 + - name: SYSCLK + description: SYSCLK clock selected as I2C clock source + value: 1 enum/LSEDRV: bit_size: 2 variants: - - name: Low - description: Low drive capacity - value: 0 - - name: MediumHigh - description: Medium-high drive capacity - value: 1 - - name: MediumLow - description: Medium-low drive capacity - value: 2 - - name: High - description: High drive capacity - value: 3 + - name: Low + description: Low drive capacity + value: 0 + - name: MediumHigh + description: Medium-high drive capacity + value: 1 + - name: MediumLow + description: Medium-low drive capacity + value: 2 + - name: High + description: High drive capacity + value: 3 enum/MCO: bit_size: 3 variants: - - name: NoMCO - description: "MCO output disabled, no clock on MCO" - value: 0 - - name: HSI14 - description: Internal RC 14 MHz (HSI14) oscillator clock selected - value: 1 - - name: LSI - description: Internal low speed (LSI) oscillator clock selected - value: 2 - - name: LSE - description: External low speed (LSE) oscillator clock selected - value: 3 - - name: SYSCLK - description: System clock selected - value: 4 - - name: HSI - description: Internal RC 8 MHz (HSI) oscillator clock selected - value: 5 - - name: HSE - description: External 4-32 MHz (HSE) oscillator clock selected - value: 6 - - name: PLL - description: "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)" - value: 7 - - name: HSI48 - description: Internal RC 48 MHz (HSI48) oscillator clock selected - value: 8 + - name: NoMCO + description: MCO output disabled, no clock on MCO + value: 0 + - name: HSI14 + description: Internal RC 14 MHz (HSI14) oscillator clock selected + value: 1 + - name: LSI + description: Internal low speed (LSI) oscillator clock selected + value: 2 + - name: LSE + description: External low speed (LSE) oscillator clock selected + value: 3 + - name: SYSCLK + description: System clock selected + value: 4 + - name: HSI + description: Internal RC 8 MHz (HSI) oscillator clock selected + value: 5 + - name: HSE + description: External 4-32 MHz (HSE) oscillator clock selected + value: 6 + - name: PLL + description: PLL clock selected (divided by 1 or 2, depending en PLLNODIV) + value: 7 + - name: HSI48 + description: Internal RC 48 MHz (HSI48) oscillator clock selected + value: 8 enum/MCOPRE: bit_size: 3 variants: - - name: Div1 - description: MCO is divided by 1 - value: 0 - - name: Div2 - description: MCO is divided by 2 - value: 1 - - name: Div4 - description: MCO is divided by 4 - value: 2 - - name: Div8 - description: MCO is divided by 8 - value: 3 - - name: Div16 - description: MCO is divided by 16 - value: 4 - - name: Div32 - description: MCO is divided by 32 - value: 5 - - name: Div64 - description: MCO is divided by 64 - value: 6 - - name: Div128 - description: MCO is divided by 128 - value: 7 + - name: Div1 + description: MCO is divided by 1 + value: 0 + - name: Div2 + description: MCO is divided by 2 + value: 1 + - name: Div4 + description: MCO is divided by 4 + value: 2 + - name: Div8 + description: MCO is divided by 8 + value: 3 + - name: Div16 + description: MCO is divided by 16 + value: 4 + - name: Div32 + description: MCO is divided by 32 + value: 5 + - name: Div64 + description: MCO is divided by 64 + value: 6 + - name: Div128 + description: MCO is divided by 128 + value: 7 enum/PLLMUL: bit_size: 4 variants: - - name: Mul2 - description: PLL input clock x2 - value: 0 - - name: Mul3 - description: PLL input clock x3 - value: 1 - - name: Mul4 - description: PLL input clock x4 - value: 2 - - name: Mul5 - description: PLL input clock x5 - value: 3 - - name: Mul6 - description: PLL input clock x6 - value: 4 - - name: Mul7 - description: PLL input clock x7 - value: 5 - - name: Mul8 - description: PLL input clock x8 - value: 6 - - name: Mul9 - description: PLL input clock x9 - value: 7 - - name: Mul10 - description: PLL input clock x10 - value: 8 - - name: Mul11 - description: PLL input clock x11 - value: 9 - - name: Mul12 - description: PLL input clock x12 - value: 10 - - name: Mul13 - description: PLL input clock x13 - value: 11 - - name: Mul14 - description: PLL input clock x14 - value: 12 - - name: Mul15 - description: PLL input clock x15 - value: 13 - - name: Mul16 - description: PLL input clock x16 - value: 14 - - name: Mul16x - description: PLL input clock x16 - value: 15 + - name: Mul2 + description: PLL input clock x2 + value: 0 + - name: Mul3 + description: PLL input clock x3 + value: 1 + - name: Mul4 + description: PLL input clock x4 + value: 2 + - name: Mul5 + description: PLL input clock x5 + value: 3 + - name: Mul6 + description: PLL input clock x6 + value: 4 + - name: Mul7 + description: PLL input clock x7 + value: 5 + - name: Mul8 + description: PLL input clock x8 + value: 6 + - name: Mul9 + description: PLL input clock x9 + value: 7 + - name: Mul10 + description: PLL input clock x10 + value: 8 + - name: Mul11 + description: PLL input clock x11 + value: 9 + - name: Mul12 + description: PLL input clock x12 + value: 10 + - name: Mul13 + description: PLL input clock x13 + value: 11 + - name: Mul14 + description: PLL input clock x14 + value: 12 + - name: Mul15 + description: PLL input clock x15 + value: 13 + - name: Mul16 + description: PLL input clock x16 + value: 14 + - name: Mul16x + description: PLL input clock x16 + value: 15 enum/PLLNODIV: bit_size: 1 variants: - - name: Div2 - description: PLL is divided by 2 for MCO - value: 0 - - name: Div1 - description: PLL is not divided for MCO - value: 1 + - name: Div2 + description: PLL is divided by 2 for MCO + value: 0 + - name: Div1 + description: PLL is not divided for MCO + value: 1 enum/PLLSRC: bit_size: 2 variants: - - name: HSI_Div2 - description: HSI divided by 2 selected as PLL input clock - value: 0 - - name: HSI_Div_PREDIV - description: NOT ALLOWED IN F0x0 - HSI divided by PREDIV selected as PLL input clock - value: 1 - - name: HSE_Div_PREDIV - description: HSE divided by PREDIV selected as PLL input clock - value: 2 - - name: HSI48_Div_PREDIV - description: NOT ALLOWED IN F0x0 - HSI48 divided by PREDIV selected as PLL input clock - value: 3 + - name: HSI_Div2 + description: HSI divided by 2 selected as PLL input clock + value: 0 + - name: HSI_Div_PREDIV + description: NOT ALLOWED IN F0x0 - HSI divided by PREDIV selected as PLL input clock + value: 1 + - name: HSE_Div_PREDIV + description: HSE divided by PREDIV selected as PLL input clock + value: 2 + - name: HSI48_Div_PREDIV + description: NOT ALLOWED IN F0x0 - HSI48 divided by PREDIV selected as PLL input clock + value: 3 enum/PLLXTPRE: bit_size: 1 variants: - - name: Div1 - description: HSE clock not divided - value: 0 - - name: Div2 - description: HSE clock divided by 2 - value: 1 + - name: Div1 + description: HSE clock not divided + value: 0 + - name: Div2 + description: HSE clock divided by 2 + value: 1 enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK divided by 2 - value: 4 - - name: Div4 - description: HCLK divided by 4 - value: 5 - - name: Div8 - description: HCLK divided by 8 - value: 6 - - name: Div16 - description: HCLK divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 enum/PREDIV: bit_size: 4 variants: - - name: Div1 - description: PREDIV input clock not divided - value: 0 - - name: Div2 - description: PREDIV input clock divided by 2 - value: 1 - - name: Div3 - description: PREDIV input clock divided by 3 - value: 2 - - name: Div4 - description: PREDIV input clock divided by 4 - value: 3 - - name: Div5 - description: PREDIV input clock divided by 5 - value: 4 - - name: Div6 - description: PREDIV input clock divided by 6 - value: 5 - - name: Div7 - description: PREDIV input clock divided by 7 - value: 6 - - name: Div8 - description: PREDIV input clock divided by 8 - value: 7 - - name: Div9 - description: PREDIV input clock divided by 9 - value: 8 - - name: Div10 - description: PREDIV input clock divided by 10 - value: 9 - - name: Div11 - description: PREDIV input clock divided by 11 - value: 10 - - name: Div12 - description: PREDIV input clock divided by 12 - value: 11 - - name: Div13 - description: PREDIV input clock divided by 13 - value: 12 - - name: Div14 - description: PREDIV input clock divided by 14 - value: 13 - - name: Div15 - description: PREDIV input clock divided by 15 - value: 14 - - name: Div16 - description: PREDIV input clock divided by 16 - value: 15 + - name: Div1 + description: PREDIV input clock not divided + value: 0 + - name: Div2 + description: PREDIV input clock divided by 2 + value: 1 + - name: Div3 + description: PREDIV input clock divided by 3 + value: 2 + - name: Div4 + description: PREDIV input clock divided by 4 + value: 3 + - name: Div5 + description: PREDIV input clock divided by 5 + value: 4 + - name: Div6 + description: PREDIV input clock divided by 6 + value: 5 + - name: Div7 + description: PREDIV input clock divided by 7 + value: 6 + - name: Div8 + description: PREDIV input clock divided by 8 + value: 7 + - name: Div9 + description: PREDIV input clock divided by 9 + value: 8 + - name: Div10 + description: PREDIV input clock divided by 10 + value: 9 + - name: Div11 + description: PREDIV input clock divided by 11 + value: 10 + - name: Div12 + description: PREDIV input clock divided by 12 + value: 11 + - name: Div13 + description: PREDIV input clock divided by 13 + value: 12 + - name: Div14 + description: PREDIV input clock divided by 14 + value: 13 + - name: Div15 + description: PREDIV input clock divided by 15 + value: 14 + - name: Div16 + description: PREDIV input clock divided by 16 + value: 15 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: HSE oscillator clock divided by a prescaler used as RTC clock - value: 3 + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 enum/SW: bit_size: 2 variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: HSE - description: HSE selected as system clock - value: 1 - - name: PLL - description: PLL selected as system clock - value: 2 - - name: HSI48 - description: HSI48 selected as system clock (when available) - value: 3 -enum/SWS: - bit_size: 2 - variants: - - name: HSI - description: HSI oscillator used as system clock - value: 0 - - name: HSE - description: HSE oscillator used as system clock - value: 1 - - name: PLL - description: PLL used as system clock - value: 2 - - name: HSI48 - description: HSI48 used as system clock (when avaiable) - value: 3 + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL + description: PLL used as system clock + value: 2 + - name: HSI48 + description: HSI48 used as system clock (when avaiable) + value: 3 enum/USARTSW: bit_size: 2 variants: - - name: PCLK - description: PCLK selected as USART clock source - value: 0 - - name: SYSCLK - description: SYSCLK selected as USART clock source - value: 1 - - name: LSE - description: LSE selected as USART clock source - value: 2 - - name: HSI - description: HSI selected as USART clock source - value: 3 + - name: PCLK + description: PCLK selected as USART clock source + value: 0 + - name: SYSCLK + description: SYSCLK selected as USART clock source + value: 1 + - name: LSE + description: LSE selected as USART clock source + value: 2 + - name: HSI + description: HSI selected as USART clock source + value: 3 enum/USBSW: bit_size: 1 variants: - - name: HSI48 - description: NOT ALLOWED IN F0x0 - HSI48 selected as USB clock source - value: 0 - - name: PLLCLK - description: PLL clock selected as USB clock source - value: 1 + - name: HSI48 + description: NOT ALLOWED IN F0x0 - HSI48 selected as USB clock source + value: 0 + - name: PLLCLK + description: PLL clock selected as USB clock source + value: 1 diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml index a96555a..901c896 100644 --- a/data/registers/rcc_f1.yaml +++ b/data/registers/rcc_f1.yaml @@ -1,852 +1,839 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: Clock control register - byte_offset: 0 - fieldset: CR - - name: CFGR - description: Clock configuration register (RCC_CFGR) - byte_offset: 4 - fieldset: CFGR - - name: CIR - description: Clock interrupt register (RCC_CIR) - byte_offset: 8 - fieldset: CIR - - name: APB2RSTR - description: APB2 peripheral reset register (RCC_APB2RSTR) - byte_offset: 12 - fieldset: APB2RSTR - - name: APB1RSTR - description: APB1 peripheral reset register (RCC_APB1RSTR) - byte_offset: 16 - fieldset: APB1RSTR - - name: AHBENR - description: AHB Peripheral Clock enable register (RCC_AHBENR) - byte_offset: 20 - fieldset: AHBENR - - name: APB2ENR - description: APB2 peripheral clock enable register (RCC_APB2ENR) - byte_offset: 24 - fieldset: APB2ENR - - name: APB1ENR - description: APB1 peripheral clock enable register (RCC_APB1ENR) - byte_offset: 28 - fieldset: APB1ENR - - name: BDCR - description: Backup domain control register (RCC_BDCR) - byte_offset: 32 - fieldset: BDCR - - name: CSR - description: Control/status register (RCC_CSR) - byte_offset: 36 - fieldset: CSR + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: CFGR + description: Clock configuration register (RCC_CFGR) + byte_offset: 4 + fieldset: CFGR + - name: CIR + description: Clock interrupt register (RCC_CIR) + byte_offset: 8 + fieldset: CIR + - name: APB2RSTR + description: APB2 peripheral reset register (RCC_APB2RSTR) + byte_offset: 12 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register (RCC_APB1RSTR) + byte_offset: 16 + fieldset: APB1RSTR + - name: AHBENR + description: AHB Peripheral Clock enable register (RCC_AHBENR) + byte_offset: 20 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register (RCC_APB2ENR) + byte_offset: 24 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register (RCC_APB1ENR) + byte_offset: 28 + fieldset: APB1ENR + - name: BDCR + description: Backup domain control register (RCC_BDCR) + byte_offset: 32 + fieldset: BDCR + - name: CSR + description: Control/status register (RCC_CSR) + byte_offset: 36 + fieldset: CSR fieldset/AHBENR: description: AHB Peripheral Clock enable register (RCC_AHBENR) fields: - - name: DMA1EN - description: DMA1 clock enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: DMA2 clock enable - bit_offset: 1 - bit_size: 1 - - name: SRAMEN - description: SRAM interface clock enable - bit_offset: 2 - bit_size: 1 - - name: FLASHEN - description: FLASH clock enable - bit_offset: 4 - bit_size: 1 - - name: CRCEN - description: CRC clock enable - bit_offset: 6 - bit_size: 1 - - name: FSMCEN - description: FSMC clock enable - bit_offset: 8 - bit_size: 1 - - name: SDIOEN - description: SDIO clock enable - bit_offset: 10 - bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: SRAMEN + description: SRAM interface clock enable + bit_offset: 2 + bit_size: 1 + - name: FLASHEN + description: FLASH clock enable + bit_offset: 4 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 6 + bit_size: 1 + - name: FSMCEN + description: FSMC clock enable + bit_offset: 8 + bit_size: 1 + - name: SDIOEN + description: SDIO clock enable + bit_offset: 10 + bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register (RCC_APB1ENR) fields: - - name: TIM2EN - description: Timer 2 clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: Timer 3 clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: Timer 4 clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: Timer 5 clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: Timer 6 clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: Timer 7 clock enable - bit_offset: 5 - bit_size: 1 - - name: TIM12EN - description: Timer 12 clock enable - bit_offset: 6 - bit_size: 1 - - name: TIM13EN - description: Timer 13 clock enable - bit_offset: 7 - bit_size: 1 - - name: TIM14EN - description: Timer 14 clock enable - bit_offset: 8 - bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI 2 clock enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI 3 clock enable - bit_offset: 15 - bit_size: 1 - - name: USART2EN - description: USART 2 clock enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART 3 clock enable - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: UART 4 clock enable - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: UART 5 clock enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C 1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C 2 clock enable - bit_offset: 22 - bit_size: 1 - - name: USBEN - description: USB clock enable - bit_offset: 23 - bit_size: 1 - - name: CANEN - description: CAN clock enable - bit_offset: 25 - bit_size: 1 - - name: BKPEN - description: Backup interface clock enable - bit_offset: 27 - bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - - name: DACEN - description: DAC interface clock enable - bit_offset: 29 - bit_size: 1 + - name: TIM2EN + description: Timer 2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: Timer 4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: Timer 5 clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: Timer 7 clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: Timer 12 clock enable + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: Timer 13 clock enable + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: Timer 14 clock enable + bit_offset: 8 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI 2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI 3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART 3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART 4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART 5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C 2 clock enable + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: USB clock enable + bit_offset: 23 + bit_size: 1 + - name: CANEN + description: CAN clock enable + bit_offset: 25 + bit_size: 1 + - name: BKPEN + description: Backup interface clock enable + bit_offset: 27 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register (RCC_APB1RSTR) fields: - - name: TIM2RST - description: Timer 2 reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: Timer 3 reset - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: Timer 4 reset - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: Timer 5 reset - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: Timer 6 reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: Timer 7 reset - bit_offset: 5 - bit_size: 1 - - name: TIM12RST - description: Timer 12 reset - bit_offset: 6 - bit_size: 1 - - name: TIM13RST - description: Timer 13 reset - bit_offset: 7 - bit_size: 1 - - name: TIM14RST - description: Timer 14 reset - bit_offset: 8 - bit_size: 1 - - name: WWDGRST - description: Window watchdog reset - bit_offset: 11 - bit_size: 1 - - name: SPI2RST - description: SPI2 reset - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: SPI3 reset - bit_offset: 15 - bit_size: 1 - - name: USART2RST - description: USART 2 reset - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: USART 3 reset - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: USART 4 reset - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: USART 5 reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C2 reset - bit_offset: 22 - bit_size: 1 - - name: USBRST - description: USB reset - bit_offset: 23 - bit_size: 1 - - name: CANRST - description: CAN reset - bit_offset: 25 - bit_size: 1 - - name: BKPRST - description: Backup interface reset - bit_offset: 27 - bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - - name: DACRST - description: DAC interface reset - bit_offset: 29 - bit_size: 1 + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: Timer 4 reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: Timer 5 reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: Timer 6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: Timer 7 reset + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: Timer 12 reset + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: Timer 13 reset + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: Timer 14 reset + bit_offset: 8 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART 3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: USART 4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: USART 5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: USB reset + bit_offset: 23 + bit_size: 1 + - name: CANRST + description: CAN reset + bit_offset: 25 + bit_size: 1 + - name: BKPRST + description: Backup interface reset + bit_offset: 27 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register (RCC_APB2ENR) fields: - - name: AFIOEN - description: Alternate function I/O clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOAEN - description: I/O port A clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIOBEN - description: I/O port B clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOCEN - description: I/O port C clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIODEN - description: I/O port D clock enable - bit_offset: 5 - bit_size: 1 - - name: GPIOEEN - description: I/O port E clock enable - bit_offset: 6 - bit_size: 1 - - name: GPIOFEN - description: I/O port F clock enable - bit_offset: 7 - bit_size: 1 - - name: GPIOGEN - description: I/O port G clock enable - bit_offset: 8 - bit_size: 1 - - name: ADC1EN - description: ADC 1 interface clock enable - bit_offset: 9 - bit_size: 1 - - name: ADC2EN - description: ADC 2 interface clock enable - bit_offset: 10 - bit_size: 1 - - name: TIM1EN - description: TIM1 Timer clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: SPI 1 clock enable - bit_offset: 12 - bit_size: 1 - - name: TIM8EN - description: TIM8 Timer clock enable - bit_offset: 13 - bit_size: 1 - - name: USART1EN - description: USART1 clock enable - bit_offset: 14 - bit_size: 1 - - name: ADC3EN - description: ADC3 interface clock enable - bit_offset: 15 - bit_size: 1 - - name: TIM9EN - description: TIM9 Timer clock enable - bit_offset: 19 - bit_size: 1 - - name: TIM10EN - description: TIM10 Timer clock enable - bit_offset: 20 - bit_size: 1 - - name: TIM11EN - description: TIM11 Timer clock enable - bit_offset: 21 - bit_size: 1 + - name: AFIOEN + description: Alternate function I/O clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOAEN + description: I/O port A clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIOBEN + description: I/O port B clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOCEN + description: I/O port C clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIODEN + description: I/O port D clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOEEN + description: I/O port E clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOFEN + description: I/O port F clock enable + bit_offset: 7 + bit_size: 1 + - name: GPIOGEN + description: I/O port G clock enable + bit_offset: 8 + bit_size: 1 + - name: ADC1EN + description: ADC 1 interface clock enable + bit_offset: 9 + bit_size: 1 + - name: ADC2EN + description: ADC 2 interface clock enable + bit_offset: 10 + bit_size: 1 + - name: TIM1EN + description: TIM1 Timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable + bit_offset: 12 + bit_size: 1 + - name: TIM8EN + description: TIM8 Timer clock enable + bit_offset: 13 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 + - name: ADC3EN + description: ADC3 interface clock enable + bit_offset: 15 + bit_size: 1 + - name: TIM9EN + description: TIM9 Timer clock enable + bit_offset: 19 + bit_size: 1 + - name: TIM10EN + description: TIM10 Timer clock enable + bit_offset: 20 + bit_size: 1 + - name: TIM11EN + description: TIM11 Timer clock enable + bit_offset: 21 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register (RCC_APB2RSTR) fields: - - name: AFIORST - description: Alternate function I/O reset - bit_offset: 0 - bit_size: 1 - - name: GPIOARST - description: IO port A reset - bit_offset: 2 - bit_size: 1 - - name: GPIOBRST - description: IO port B reset - bit_offset: 3 - bit_size: 1 - - name: GPIOCRST - description: IO port C reset - bit_offset: 4 - bit_size: 1 - - name: GPIODRST - description: IO port D reset - bit_offset: 5 - bit_size: 1 - - name: GPIOERST - description: IO port E reset - bit_offset: 6 - bit_size: 1 - - name: GPIOFRST - description: IO port F reset - bit_offset: 7 - bit_size: 1 - - name: GPIOGRST - description: IO port G reset - bit_offset: 8 - bit_size: 1 - - name: ADC1RST - description: ADC 1 interface reset - bit_offset: 9 - bit_size: 1 - - name: ADC2RST - description: ADC 2 interface reset - bit_offset: 10 - bit_size: 1 - - name: TIM1RST - description: TIM1 timer reset - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: SPI 1 reset - bit_offset: 12 - bit_size: 1 - - name: TIM8RST - description: TIM8 timer reset - bit_offset: 13 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 14 - bit_size: 1 - - name: ADC3RST - description: ADC 3 interface reset - bit_offset: 15 - bit_size: 1 - - name: TIM9RST - description: TIM9 timer reset - bit_offset: 19 - bit_size: 1 - - name: TIM10RST - description: TIM10 timer reset - bit_offset: 20 - bit_size: 1 - - name: TIM11RST - description: TIM11 timer reset - bit_offset: 21 - bit_size: 1 + - name: AFIORST + description: Alternate function I/O reset + bit_offset: 0 + bit_size: 1 + - name: GPIOARST + description: IO port A reset + bit_offset: 2 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 3 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 4 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 5 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 6 + bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 7 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 8 + bit_size: 1 + - name: ADC1RST + description: ADC 1 interface reset + bit_offset: 9 + bit_size: 1 + - name: ADC2RST + description: ADC 2 interface reset + bit_offset: 10 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: TIM8RST + description: TIM8 timer reset + bit_offset: 13 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: ADC3RST + description: ADC 3 interface reset + bit_offset: 15 + bit_size: 1 + - name: TIM9RST + description: TIM9 timer reset + bit_offset: 19 + bit_size: 1 + - name: TIM10RST + description: TIM10 timer reset + bit_offset: 20 + bit_size: 1 + - name: TIM11RST + description: TIM11 timer reset + bit_offset: 21 + bit_size: 1 fieldset/BDCR: description: Backup domain control register (RCC_BDCR) fields: - - name: LSEON - description: External Low Speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: External Low Speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: External Low Speed oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: Backup domain software reset - bit_offset: 16 - bit_size: 1 + - name: LSEON + description: External Low Speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External Low Speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: External Low Speed oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 fieldset/CFGR: description: Clock configuration register (RCC_CFGR) fields: - - name: SW - description: System clock Switch - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: System Clock Switch Status - bit_offset: 2 - bit_size: 2 - enum: SWS - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - enum: HPRE - - name: PPRE1 - description: APB Low speed prescaler (APB1) - bit_offset: 8 - bit_size: 3 - enum: PPRE1 - - name: PPRE2 - description: APB High speed prescaler (APB2) - bit_offset: 11 - bit_size: 3 - enum: PPRE1 - - name: ADCPRE - description: ADC prescaler - bit_offset: 14 - bit_size: 2 - enum: ADCPRE - - name: PLLSRC - description: PLL entry clock source - bit_offset: 16 - bit_size: 1 - enum: PLLSRC - - name: PLLXTPRE - description: HSE divider for PLL entry - bit_offset: 17 - bit_size: 1 - enum: PLLXTPRE - - name: PLLMUL - description: PLL Multiplication Factor - bit_offset: 18 - bit_size: 4 - enum: PLLMUL - - name: USBPRE - description: USB prescaler - bit_offset: 22 - bit_size: 1 - enum: USBPRE - - name: MCO - description: Microcontroller clock output - bit_offset: 24 - bit_size: 3 - enum: MCO + - name: SW + description: System clock Switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System Clock Switch Status + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB High speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: ADCPRE + description: ADC prescaler + bit_offset: 14 + bit_size: 2 + enum: ADCPRE + - name: PLLSRC + description: PLL entry clock source + bit_offset: 16 + bit_size: 1 + enum: PLLSRC + - name: PLLXTPRE + description: HSE divider for PLL entry + bit_offset: 17 + bit_size: 1 + enum: PLLXTPRE + - name: PLLMUL + description: PLL Multiplication Factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: USBPRE + description: USB prescaler + bit_offset: 22 + bit_size: 1 + enum: USBPRE + - name: MCO + description: Microcontroller clock output + bit_offset: 24 + bit_size: 3 + enum: MCO fieldset/CIR: description: Clock interrupt register (RCC_CIR) fields: - - name: LSIRDYF - description: LSI Ready Interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE Ready Interrupt flag - bit_offset: 1 - bit_size: 1 - - name: HSIRDYF - description: HSI Ready Interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSERDYF - description: HSE Ready Interrupt flag - bit_offset: 3 - bit_size: 1 - - name: PLLRDYF - description: PLL Ready Interrupt flag - bit_offset: 4 - bit_size: 1 - - name: CSSF - description: Clock Security System Interrupt flag - bit_offset: 7 - bit_size: 1 - - name: LSIRDYIE - description: LSI Ready Interrupt Enable - bit_offset: 8 - bit_size: 1 - - name: LSERDYIE - description: LSE Ready Interrupt Enable - bit_offset: 9 - bit_size: 1 - - name: HSIRDYIE - description: HSI Ready Interrupt Enable - bit_offset: 10 - bit_size: 1 - - name: HSERDYIE - description: HSE Ready Interrupt Enable - bit_offset: 11 - bit_size: 1 - - name: PLLRDYIE - description: PLL Ready Interrupt Enable - bit_offset: 12 - bit_size: 1 - - name: LSIRDYC - description: LSI Ready Interrupt Clear - bit_offset: 16 - bit_size: 1 - - name: LSERDYC - description: LSE Ready Interrupt Clear - bit_offset: 17 - bit_size: 1 - - name: HSIRDYC - description: HSI Ready Interrupt Clear - bit_offset: 18 - bit_size: 1 - - name: HSERDYC - description: HSE Ready Interrupt Clear - bit_offset: 19 - bit_size: 1 - - name: PLLRDYC - description: PLL Ready Interrupt Clear - bit_offset: 20 - bit_size: 1 - - name: CSSC - description: Clock security system interrupt clear - bit_offset: 23 - bit_size: 1 + - name: LSIRDYF + description: LSI Ready Interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE Ready Interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI Ready Interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE Ready Interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: PLL Ready Interrupt flag + bit_offset: 4 + bit_size: 1 + - name: CSSF + description: Clock Security System Interrupt flag + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI Ready Interrupt Enable + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE Ready Interrupt Enable + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI Ready Interrupt Enable + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE Ready Interrupt Enable + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: PLL Ready Interrupt Enable + bit_offset: 12 + bit_size: 1 + - name: LSIRDYC + description: LSI Ready Interrupt Clear + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE Ready Interrupt Clear + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI Ready Interrupt Clear + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE Ready Interrupt Clear + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: PLL Ready Interrupt Clear + bit_offset: 20 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 fieldset/CR: description: Clock control register fields: - - name: HSION - description: Internal High Speed clock enable - bit_offset: 0 - bit_size: 1 - - name: HSIRDY - description: Internal High Speed clock ready flag - bit_offset: 1 - bit_size: 1 - - name: HSITRIM - description: Internal High Speed clock trimming - bit_offset: 3 - bit_size: 5 - - name: HSICAL - description: Internal High Speed clock Calibration - bit_offset: 8 - bit_size: 8 - - name: HSEON - description: External High Speed clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: External High Speed clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: External High Speed clock Bypass - bit_offset: 18 - bit_size: 1 - - name: CSSON - description: Clock Security System enable - bit_offset: 19 - bit_size: 1 - - name: PLLON - description: PLL enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: PLL clock ready flag - bit_offset: 25 - bit_size: 1 + - name: HSION + description: Internal High Speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal High Speed clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSITRIM + description: Internal High Speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal High Speed clock Calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: External High Speed clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: External High Speed clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: External High Speed clock Bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 fieldset/CSR: description: Control/status register (RCC_CSR) fields: - - name: LSION - description: Internal low speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: Internal low speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: RMVF - description: Remove reset flag - bit_offset: 24 - bit_size: 1 - - name: PINRSTF - description: PIN reset flag - bit_offset: 26 - bit_size: 1 - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: Independent watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSION + description: Internal low speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 enum/ADCPRE: bit_size: 2 variants: - - name: Div2 - description: PCLK2 divided by 2 - value: 0 - - name: Div4 - description: PCLK2 divided by 4 - value: 1 - - name: Div6 - description: PCLK2 divided by 6 - value: 2 - - name: Div8 - description: PCLK2 divided by 8 - value: 3 + - name: Div2 + description: PCLK2 divided by 2 + value: 0 + - name: Div4 + description: PCLK2 divided by 4 + value: 1 + - name: Div6 + description: PCLK2 divided by 6 + value: 2 + - name: Div8 + description: PCLK2 divided by 8 + value: 3 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: SYSCLK not divided - value: 0 - - name: Div2 - description: SYSCLK divided by 2 - value: 8 - - name: Div4 - description: SYSCLK divided by 4 - value: 9 - - name: Div8 - description: SYSCLK divided by 8 - value: 10 - - name: Div16 - description: SYSCLK divided by 16 - value: 11 - - name: Div64 - description: SYSCLK divided by 64 - value: 12 - - name: Div128 - description: SYSCLK divided by 128 - value: 13 - - name: Div256 - description: SYSCLK divided by 256 - value: 14 - - name: Div512 - description: SYSCLK divided by 512 - value: 15 + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 enum/MCO: bit_size: 3 variants: - - name: NoMCO - description: "MCO output disabled, no clock on MCO" - value: 0 - - name: SYSCLK - description: System clock selected - value: 4 - - name: HSI - description: HSI oscillator clock selected - value: 5 - - name: HSE - description: HSE oscillator clock selected - value: 6 - - name: PLL - description: PLL clock divided by 2 selected - value: 7 + - name: NoMCO + description: MCO output disabled, no clock on MCO + value: 0 + - name: SYSCLK + description: System clock selected + value: 4 + - name: HSI + description: HSI oscillator clock selected + value: 5 + - name: HSE + description: HSE oscillator clock selected + value: 6 + - name: PLL + description: PLL clock divided by 2 selected + value: 7 enum/PLLMUL: bit_size: 4 variants: - - name: Mul2 - description: PLL input clock x2 - value: 0 - - name: Mul3 - description: PLL input clock x3 - value: 1 - - name: Mul4 - description: PLL input clock x4 - value: 2 - - name: Mul5 - description: PLL input clock x5 - value: 3 - - name: Mul6 - description: PLL input clock x6 - value: 4 - - name: Mul7 - description: PLL input clock x7 - value: 5 - - name: Mul8 - description: PLL input clock x8 - value: 6 - - name: Mul9 - description: PLL input clock x9 - value: 7 - - name: Mul10 - description: PLL input clock x10 - value: 8 - - name: Mul11 - description: PLL input clock x11 - value: 9 - - name: Mul12 - description: PLL input clock x12 - value: 10 - - name: Mul13 - description: PLL input clock x13 - value: 11 - - name: Mul14 - description: PLL input clock x14 - value: 12 - - name: Mul15 - description: PLL input clock x15 - value: 13 - - name: Mul16 - description: PLL input clock x16 - value: 14 - - name: Mul16x - description: PLL input clock x16 - value: 15 + - name: Mul2 + description: PLL input clock x2 + value: 0 + - name: Mul3 + description: PLL input clock x3 + value: 1 + - name: Mul4 + description: PLL input clock x4 + value: 2 + - name: Mul5 + description: PLL input clock x5 + value: 3 + - name: Mul6 + description: PLL input clock x6 + value: 4 + - name: Mul7 + description: PLL input clock x7 + value: 5 + - name: Mul8 + description: PLL input clock x8 + value: 6 + - name: Mul9 + description: PLL input clock x9 + value: 7 + - name: Mul10 + description: PLL input clock x10 + value: 8 + - name: Mul11 + description: PLL input clock x11 + value: 9 + - name: Mul12 + description: PLL input clock x12 + value: 10 + - name: Mul13 + description: PLL input clock x13 + value: 11 + - name: Mul14 + description: PLL input clock x14 + value: 12 + - name: Mul15 + description: PLL input clock x15 + value: 13 + - name: Mul16 + description: PLL input clock x16 + value: 14 + - name: Mul16x + description: PLL input clock x16 + value: 15 enum/PLLSRC: bit_size: 1 variants: - - name: HSI_Div2 - description: HSI divided by 2 selected as PLL input clock - value: 0 - - name: HSE_Div_PREDIV - description: HSE divided by PREDIV selected as PLL input clock - value: 1 + - name: HSI_Div2 + description: HSI divided by 2 selected as PLL input clock + value: 0 + - name: HSE_Div_PREDIV + description: HSE divided by PREDIV selected as PLL input clock + value: 1 enum/PLLXTPRE: bit_size: 1 variants: - - name: Div1 - description: HSE clock not divided - value: 0 - - name: Div2 - description: HSE clock divided by 2 - value: 1 -enum/PPRE1: + - name: Div1 + description: HSE clock not divided + value: 0 + - name: Div2 + description: HSE clock divided by 2 + value: 1 +enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK divided by 2 - value: 4 - - name: Div4 - description: HCLK divided by 4 - value: 5 - - name: Div8 - description: HCLK divided by 8 - value: 6 - - name: Div16 - description: HCLK divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: HSE oscillator clock divided by a prescaler used as RTC clock - value: 3 + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 enum/SW: bit_size: 2 variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: HSE - description: HSE selected as system clock - value: 1 - - name: PLL - description: PLL selected as system clock - value: 2 -enum/SWS: - bit_size: 2 - variants: - - name: HSI - description: HSI oscillator used as system clock - value: 0 - - name: HSE - description: HSE oscillator used as system clock - value: 1 - - name: PLL - description: PLL used as system clock - value: 2 + - name: HSI + description: HSI selected as system clock + value: 0 + - name: HSE + description: HSE selected as system clock + value: 1 + - name: PLL + description: PLL selected as system clock + value: 2 enum/USBPRE: bit_size: 1 variants: - - name: DIV1_5 - description: PLL clock is divided by 1.5 - value: 0 - - name: DIV1 - description: PLL clock is not divided - value: 1 + - name: Div1_5 + description: PLL clock is divided by 1.5 + value: 0 + - name: Div1 + description: PLL clock is not divided + value: 1 diff --git a/data/registers/rcc_f100.yaml b/data/registers/rcc_f100.yaml index a094e0b..3162335 100644 --- a/data/registers/rcc_f100.yaml +++ b/data/registers/rcc_f100.yaml @@ -1,865 +1,852 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: Clock control register - byte_offset: 0 - fieldset: CR - - name: CFGR - description: Clock configuration register (RCC_CFGR) - byte_offset: 4 - fieldset: CFGR - - name: CIR - description: Clock interrupt register (RCC_CIR) - byte_offset: 8 - fieldset: CIR - - name: APB2RSTR - description: APB2 peripheral reset register (RCC_APB2RSTR) - byte_offset: 12 - fieldset: APB2RSTR - - name: APB1RSTR - description: APB1 peripheral reset register (RCC_APB1RSTR) - byte_offset: 16 - fieldset: APB1RSTR - - name: AHBENR - description: AHB Peripheral Clock enable register (RCC_AHBENR) - byte_offset: 20 - fieldset: AHBENR - - name: APB2ENR - description: APB2 peripheral clock enable register (RCC_APB2ENR) - byte_offset: 24 - fieldset: APB2ENR - - name: APB1ENR - description: APB1 peripheral clock enable register (RCC_APB1ENR) - byte_offset: 28 - fieldset: APB1ENR - - name: BDCR - description: Backup domain control register (RCC_BDCR) - byte_offset: 32 - fieldset: BDCR - - name: CSR - description: Control/status register (RCC_CSR) - byte_offset: 36 - fieldset: CSR - - name: CFGR2 - description: Clock configuration register 2 - byte_offset: 44 - fieldset: CFGR2 + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: CFGR + description: Clock configuration register (RCC_CFGR) + byte_offset: 4 + fieldset: CFGR + - name: CIR + description: Clock interrupt register (RCC_CIR) + byte_offset: 8 + fieldset: CIR + - name: APB2RSTR + description: APB2 peripheral reset register (RCC_APB2RSTR) + byte_offset: 12 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register (RCC_APB1RSTR) + byte_offset: 16 + fieldset: APB1RSTR + - name: AHBENR + description: AHB Peripheral Clock enable register (RCC_AHBENR) + byte_offset: 20 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register (RCC_APB2ENR) + byte_offset: 24 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register (RCC_APB1ENR) + byte_offset: 28 + fieldset: APB1ENR + - name: BDCR + description: Backup domain control register (RCC_BDCR) + byte_offset: 32 + fieldset: BDCR + - name: CSR + description: Control/status register (RCC_CSR) + byte_offset: 36 + fieldset: CSR + - name: CFGR2 + description: Clock configuration register 2 + byte_offset: 44 + fieldset: CFGR2 fieldset/AHBENR: description: AHB Peripheral Clock enable register (RCC_AHBENR) fields: - - name: DMA1EN - description: DMA1 clock enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: DMA2 clock enable - bit_offset: 1 - bit_size: 1 - - name: SRAMEN - description: SRAM interface clock enable - bit_offset: 2 - bit_size: 1 - - name: FLASHEN - description: FLASH clock enable - bit_offset: 4 - bit_size: 1 - - name: CRCEN - description: CRC clock enable - bit_offset: 6 - bit_size: 1 - - name: FSMCEN - description: FSMC clock enable - bit_offset: 8 - bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: SRAMEN + description: SRAM interface clock enable + bit_offset: 2 + bit_size: 1 + - name: FLASHEN + description: FLASH clock enable + bit_offset: 4 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 6 + bit_size: 1 + - name: FSMCEN + description: FSMC clock enable + bit_offset: 8 + bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register (RCC_APB1ENR) fields: - - name: TIM2EN - description: Timer 2 clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: Timer 3 clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: Timer 4 clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: Timer 5 clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: Timer 6 clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: Timer 7 clock enable - bit_offset: 5 - bit_size: 1 - - name: TIM12EN - description: Timer 12 clock enable - bit_offset: 6 - bit_size: 1 - - name: TIM13EN - description: Timer 13 clock enable - bit_offset: 7 - bit_size: 1 - - name: TIM14EN - description: Timer 14 clock enable - bit_offset: 8 - bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI 2 clock enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI 3 clock enable - bit_offset: 15 - bit_size: 1 - - name: USART2EN - description: USART 2 clock enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART 3 clock enable - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: UART 4 clock enable - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: UART 5 clock enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C 1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C 2 clock enable - bit_offset: 22 - bit_size: 1 - - name: BKPEN - description: Backup interface clock enable - bit_offset: 27 - bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - - name: DACEN - description: DAC interface clock enable - bit_offset: 29 - bit_size: 1 - - name: CECEN - description: CEC clock enable - bit_offset: 30 - bit_size: 1 + - name: TIM2EN + description: Timer 2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: Timer 4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: Timer 5 clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: Timer 7 clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: Timer 12 clock enable + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: Timer 13 clock enable + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: Timer 14 clock enable + bit_offset: 8 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI 2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI 3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART 3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART 4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART 5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C 2 clock enable + bit_offset: 22 + bit_size: 1 + - name: BKPEN + description: Backup interface clock enable + bit_offset: 27 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: CECEN + description: CEC clock enable + bit_offset: 30 + bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register (RCC_APB1RSTR) fields: - - name: TIM2RST - description: Timer 2 reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: Timer 3 reset - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: Timer 4 reset - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: Timer 5 reset - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: Timer 6 reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: Timer 7 reset - bit_offset: 5 - bit_size: 1 - - name: TIM12RST - description: Timer 12 reset - bit_offset: 6 - bit_size: 1 - - name: TIM13RST - description: Timer 13 reset - bit_offset: 7 - bit_size: 1 - - name: TIM14RST - description: Timer 14 reset - bit_offset: 8 - bit_size: 1 - - name: WWDGRST - description: Window watchdog reset - bit_offset: 11 - bit_size: 1 - - name: SPI2RST - description: SPI2 reset - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: SPI3 reset - bit_offset: 15 - bit_size: 1 - - name: USART2RST - description: USART 2 reset - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: USART 3 reset - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: USART 4 reset - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: USART 5 reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C2 reset - bit_offset: 22 - bit_size: 1 - - name: BKPRST - description: Backup interface reset - bit_offset: 27 - bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - - name: DACRST - description: DAC interface reset - bit_offset: 29 - bit_size: 1 - - name: CECRST - description: CEC reset - bit_offset: 30 - bit_size: 1 + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: Timer 4 reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: Timer 5 reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: Timer 6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: Timer 7 reset + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: Timer 12 reset + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: Timer 13 reset + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: Timer 14 reset + bit_offset: 8 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART 3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: USART 4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: USART 5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: BKPRST + description: Backup interface reset + bit_offset: 27 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 + - name: CECRST + description: CEC reset + bit_offset: 30 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register (RCC_APB2ENR) fields: - - name: AFIOEN - description: Alternate function I/O clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOAEN - description: I/O port A clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIOBEN - description: I/O port B clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOCEN - description: I/O port C clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIODEN - description: I/O port D clock enable - bit_offset: 5 - bit_size: 1 - - name: GPIOEEN - description: I/O port E clock enable - bit_offset: 6 - bit_size: 1 - - name: GPIOFEN - description: I/O port F clock enable - bit_offset: 7 - bit_size: 1 - - name: GPIOGEN - description: I/O port G clock enable - bit_offset: 8 - bit_size: 1 - - name: ADC1EN - description: ADC 1 interface clock enable - bit_offset: 9 - bit_size: 1 - - name: TIM1EN - description: TIM1 Timer clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: SPI 1 clock enable - bit_offset: 12 - bit_size: 1 - - name: USART1EN - description: USART1 clock enable - bit_offset: 14 - bit_size: 1 - - name: TIM15EN - description: TIM15 Timer clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: TIM16 Timer clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: TIM17 Timer clock enable - bit_offset: 18 - bit_size: 1 + - name: AFIOEN + description: Alternate function I/O clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOAEN + description: I/O port A clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIOBEN + description: I/O port B clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOCEN + description: I/O port C clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIODEN + description: I/O port D clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOEEN + description: I/O port E clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOFEN + description: I/O port F clock enable + bit_offset: 7 + bit_size: 1 + - name: GPIOGEN + description: I/O port G clock enable + bit_offset: 8 + bit_size: 1 + - name: ADC1EN + description: ADC 1 interface clock enable + bit_offset: 9 + bit_size: 1 + - name: TIM1EN + description: TIM1 Timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM15EN + description: TIM15 Timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 Timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 Timer clock enable + bit_offset: 18 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register (RCC_APB2RSTR) fields: - - name: AFIORST - description: Alternate function I/O reset - bit_offset: 0 - bit_size: 1 - - name: GPIOARST - description: IO port A reset - bit_offset: 2 - bit_size: 1 - - name: GPIOBRST - description: IO port B reset - bit_offset: 3 - bit_size: 1 - - name: GPIOCRST - description: IO port C reset - bit_offset: 4 - bit_size: 1 - - name: GPIODRST - description: IO port D reset - bit_offset: 5 - bit_size: 1 - - name: GPIOERST - description: IO port E reset - bit_offset: 6 - bit_size: 1 - - name: GPIOFRST - description: IO port F reset - bit_offset: 7 - bit_size: 1 - - name: GPIOGRST - description: IO port G reset - bit_offset: 8 - bit_size: 1 - - name: ADC1RST - description: ADC 1 interface reset - bit_offset: 9 - bit_size: 1 - - name: TIM1RST - description: TIM1 timer reset - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: SPI 1 reset - bit_offset: 12 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 14 - bit_size: 1 - - name: TIM15RST - description: TIM15 timer reset - bit_offset: 16 - bit_size: 1 - - name: TIM16RST - description: TIM16 timer reset - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: TIM17 timer reset - bit_offset: 18 - bit_size: 1 + - name: AFIORST + description: Alternate function I/O reset + bit_offset: 0 + bit_size: 1 + - name: GPIOARST + description: IO port A reset + bit_offset: 2 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 3 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 4 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 5 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 6 + bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 7 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 8 + bit_size: 1 + - name: ADC1RST + description: ADC 1 interface reset + bit_offset: 9 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 fieldset/BDCR: description: Backup domain control register (RCC_BDCR) fields: - - name: LSEON - description: External Low Speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: External Low Speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: External Low Speed oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: Backup domain software reset - bit_offset: 16 - bit_size: 1 + - name: LSEON + description: External Low Speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External Low Speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: External Low Speed oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 fieldset/CFGR: description: Clock configuration register (RCC_CFGR) fields: - - name: SW - description: System clock Switch - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: System Clock Switch Status - bit_offset: 2 - bit_size: 2 - enum: SWS - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - enum: HPRE - - name: PPRE1 - description: APB Low speed prescaler (APB1) - bit_offset: 8 - bit_size: 3 - enum: PPRE1 - - name: PPRE2 - description: APB High speed prescaler (APB2) - bit_offset: 11 - bit_size: 3 - enum: PPRE1 - - name: ADCPRE - description: ADC prescaler - bit_offset: 14 - bit_size: 2 - enum: ADCPRE - - name: PLLSRC - description: PLL entry clock source - bit_offset: 16 - bit_size: 1 - enum: PLLSRC - - name: PLLXTPRE - description: HSE divider for PLL entry - bit_offset: 17 - bit_size: 1 - enum: PLLXTPRE - - name: PLLMUL - description: PLL Multiplication Factor - bit_offset: 18 - bit_size: 4 - enum: PLLMUL - - name: MCO - description: Microcontroller clock output - bit_offset: 24 - bit_size: 3 - enum: MCO + - name: SW + description: System clock Switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System Clock Switch Status + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB High speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: ADCPRE + description: ADC prescaler + bit_offset: 14 + bit_size: 2 + enum: ADCPRE + - name: PLLSRC + description: PLL entry clock source + bit_offset: 16 + bit_size: 1 + enum: PLLSRC + - name: PLLXTPRE + description: HSE divider for PLL entry + bit_offset: 17 + bit_size: 1 + enum: PLLXTPRE + - name: PLLMUL + description: PLL Multiplication Factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: MCO + description: Microcontroller clock output + bit_offset: 24 + bit_size: 3 + enum: MCO fieldset/CFGR2: description: Clock configuration register 2 fields: - - name: PREDIV1 - description: PREDIV1 division factor - bit_offset: 0 - bit_size: 4 - enum: PREDIV1 + - name: PREDIV1 + description: PREDIV1 division factor + bit_offset: 0 + bit_size: 4 + enum: PREDIV1 fieldset/CIR: description: Clock interrupt register (RCC_CIR) fields: - - name: LSIRDYF - description: LSI Ready Interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE Ready Interrupt flag - bit_offset: 1 - bit_size: 1 - - name: HSIRDYF - description: HSI Ready Interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSERDYF - description: HSE Ready Interrupt flag - bit_offset: 3 - bit_size: 1 - - name: PLLRDYF - description: PLL Ready Interrupt flag - bit_offset: 4 - bit_size: 1 - - name: CSSF - description: Clock Security System Interrupt flag - bit_offset: 7 - bit_size: 1 - - name: LSIRDYIE - description: LSI Ready Interrupt Enable - bit_offset: 8 - bit_size: 1 - - name: LSERDYIE - description: LSE Ready Interrupt Enable - bit_offset: 9 - bit_size: 1 - - name: HSIRDYIE - description: HSI Ready Interrupt Enable - bit_offset: 10 - bit_size: 1 - - name: HSERDYIE - description: HSE Ready Interrupt Enable - bit_offset: 11 - bit_size: 1 - - name: PLLRDYIE - description: PLL Ready Interrupt Enable - bit_offset: 12 - bit_size: 1 - - name: LSIRDYC - description: LSI Ready Interrupt Clear - bit_offset: 16 - bit_size: 1 - - name: LSERDYC - description: LSE Ready Interrupt Clear - bit_offset: 17 - bit_size: 1 - - name: HSIRDYC - description: HSI Ready Interrupt Clear - bit_offset: 18 - bit_size: 1 - - name: HSERDYC - description: HSE Ready Interrupt Clear - bit_offset: 19 - bit_size: 1 - - name: PLLRDYC - description: PLL Ready Interrupt Clear - bit_offset: 20 - bit_size: 1 - - name: CSSC - description: Clock security system interrupt clear - bit_offset: 23 - bit_size: 1 + - name: LSIRDYF + description: LSI Ready Interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE Ready Interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI Ready Interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE Ready Interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: PLL Ready Interrupt flag + bit_offset: 4 + bit_size: 1 + - name: CSSF + description: Clock Security System Interrupt flag + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI Ready Interrupt Enable + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE Ready Interrupt Enable + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI Ready Interrupt Enable + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE Ready Interrupt Enable + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: PLL Ready Interrupt Enable + bit_offset: 12 + bit_size: 1 + - name: LSIRDYC + description: LSI Ready Interrupt Clear + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE Ready Interrupt Clear + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI Ready Interrupt Clear + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE Ready Interrupt Clear + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: PLL Ready Interrupt Clear + bit_offset: 20 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 fieldset/CR: description: Clock control register fields: - - name: HSION - description: Internal High Speed clock enable - bit_offset: 0 - bit_size: 1 - - name: HSIRDY - description: Internal High Speed clock ready flag - bit_offset: 1 - bit_size: 1 - - name: HSITRIM - description: Internal High Speed clock trimming - bit_offset: 3 - bit_size: 5 - - name: HSICAL - description: Internal High Speed clock Calibration - bit_offset: 8 - bit_size: 8 - - name: HSEON - description: External High Speed clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: External High Speed clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: External High Speed clock Bypass - bit_offset: 18 - bit_size: 1 - - name: CSSON - description: Clock Security System enable - bit_offset: 19 - bit_size: 1 - - name: PLLON - description: PLL enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: PLL clock ready flag - bit_offset: 25 - bit_size: 1 + - name: HSION + description: Internal High Speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal High Speed clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSITRIM + description: Internal High Speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal High Speed clock Calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: External High Speed clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: External High Speed clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: External High Speed clock Bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 fieldset/CSR: description: Control/status register (RCC_CSR) fields: - - name: LSION - description: Internal low speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: Internal low speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: RMVF - description: Remove reset flag - bit_offset: 24 - bit_size: 1 - - name: PINRSTF - description: PIN reset flag - bit_offset: 26 - bit_size: 1 - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: Independent watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSION + description: Internal low speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 enum/ADCPRE: bit_size: 2 variants: - - name: Div2 - description: PCLK2 divided by 2 - value: 0 - - name: Div4 - description: PCLK2 divided by 4 - value: 1 - - name: Div6 - description: PCLK2 divided by 6 - value: 2 - - name: Div8 - description: PCLK2 divided by 8 - value: 3 + - name: Div2 + description: PCLK2 divided by 2 + value: 0 + - name: Div4 + description: PCLK2 divided by 4 + value: 1 + - name: Div6 + description: PCLK2 divided by 6 + value: 2 + - name: Div8 + description: PCLK2 divided by 8 + value: 3 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: SYSCLK not divided - value: 0 - - name: Div2 - description: SYSCLK divided by 2 - value: 8 - - name: Div4 - description: SYSCLK divided by 4 - value: 9 - - name: Div8 - description: SYSCLK divided by 8 - value: 10 - - name: Div16 - description: SYSCLK divided by 16 - value: 11 - - name: Div64 - description: SYSCLK divided by 64 - value: 12 - - name: Div128 - description: SYSCLK divided by 128 - value: 13 - - name: Div256 - description: SYSCLK divided by 256 - value: 14 - - name: Div512 - description: SYSCLK divided by 512 - value: 15 + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 enum/MCO: bit_size: 3 variants: - - name: NoMCO - description: "MCO output disabled, no clock on MCO" - value: 0 - - name: SYSCLK - description: System clock selected - value: 4 - - name: HSI - description: HSI oscillator clock selected - value: 5 - - name: HSE - description: HSE oscillator clock selected - value: 6 - - name: PLL - description: PLL clock divided by 2 selected - value: 7 + - name: NoMCO + description: MCO output disabled, no clock on MCO + value: 0 + - name: SYSCLK + description: System clock selected + value: 4 + - name: HSI + description: HSI oscillator clock selected + value: 5 + - name: HSE + description: HSE oscillator clock selected + value: 6 + - name: PLL + description: PLL clock divided by 2 selected + value: 7 enum/PLLMUL: bit_size: 4 variants: - - name: Mul2 - description: PLL input clock x2 - value: 0 - - name: Mul3 - description: PLL input clock x3 - value: 1 - - name: Mul4 - description: PLL input clock x4 - value: 2 - - name: Mul5 - description: PLL input clock x5 - value: 3 - - name: Mul6 - description: PLL input clock x6 - value: 4 - - name: Mul7 - description: PLL input clock x7 - value: 5 - - name: Mul8 - description: PLL input clock x8 - value: 6 - - name: Mul9 - description: PLL input clock x9 - value: 7 - - name: Mul10 - description: PLL input clock x10 - value: 8 - - name: Mul11 - description: PLL input clock x11 - value: 9 - - name: Mul12 - description: PLL input clock x12 - value: 10 - - name: Mul13 - description: PLL input clock x13 - value: 11 - - name: Mul14 - description: PLL input clock x14 - value: 12 - - name: Mul15 - description: PLL input clock x15 - value: 13 - - name: Mul16 - description: PLL input clock x16 - value: 14 - - name: Mul16x - description: PLL input clock x16 - value: 15 + - name: Mul2 + description: PLL input clock x2 + value: 0 + - name: Mul3 + description: PLL input clock x3 + value: 1 + - name: Mul4 + description: PLL input clock x4 + value: 2 + - name: Mul5 + description: PLL input clock x5 + value: 3 + - name: Mul6 + description: PLL input clock x6 + value: 4 + - name: Mul7 + description: PLL input clock x7 + value: 5 + - name: Mul8 + description: PLL input clock x8 + value: 6 + - name: Mul9 + description: PLL input clock x9 + value: 7 + - name: Mul10 + description: PLL input clock x10 + value: 8 + - name: Mul11 + description: PLL input clock x11 + value: 9 + - name: Mul12 + description: PLL input clock x12 + value: 10 + - name: Mul13 + description: PLL input clock x13 + value: 11 + - name: Mul14 + description: PLL input clock x14 + value: 12 + - name: Mul15 + description: PLL input clock x15 + value: 13 + - name: Mul16 + description: PLL input clock x16 + value: 14 + - name: Mul16x + description: PLL input clock x16 + value: 15 enum/PLLSRC: bit_size: 1 variants: - - name: HSI_Div2 - description: HSI divided by 2 selected as PLL input clock - value: 0 - - name: HSE_Div_PREDIV - description: HSE divided by PREDIV selected as PLL input clock - value: 1 + - name: HSI_Div2 + description: HSI divided by 2 selected as PLL input clock + value: 0 + - name: HSE_Div_PREDIV + description: HSE divided by PREDIV selected as PLL input clock + value: 1 enum/PLLXTPRE: bit_size: 1 variants: - - name: Div1 - description: HSE clock not divided - value: 0 - - name: Div2 - description: HSE clock divided by 2 - value: 1 -enum/PPRE1: + - name: Div1 + description: HSE clock not divided + value: 0 + - name: Div2 + description: HSE clock divided by 2 + value: 1 +enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK divided by 2 - value: 4 - - name: Div4 - description: HCLK divided by 4 - value: 5 - - name: Div8 - description: HCLK divided by 8 - value: 6 - - name: Div16 - description: HCLK divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 enum/PREDIV1: bit_size: 4 variants: - - name: Div1 - description: PREDIV input clock not divided - value: 0 - - name: Div2 - description: PREDIV input clock divided by 2 - value: 1 - - name: Div3 - description: PREDIV input clock divided by 3 - value: 2 - - name: Div4 - description: PREDIV input clock divided by 4 - value: 3 - - name: Div5 - description: PREDIV input clock divided by 5 - value: 4 - - name: Div6 - description: PREDIV input clock divided by 6 - value: 5 - - name: Div7 - description: PREDIV input clock divided by 7 - value: 6 - - name: Div8 - description: PREDIV input clock divided by 8 - value: 7 - - name: Div9 - description: PREDIV input clock divided by 9 - value: 8 - - name: Div10 - description: PREDIV input clock divided by 10 - value: 9 - - name: Div11 - description: PREDIV input clock divided by 11 - value: 10 - - name: Div12 - description: PREDIV input clock divided by 12 - value: 11 - - name: Div13 - description: PREDIV input clock divided by 13 - value: 12 - - name: Div14 - description: PREDIV input clock divided by 14 - value: 13 - - name: Div15 - description: PREDIV input clock divided by 15 - value: 14 - - name: Div16 - description: PREDIV input clock divided by 16 - value: 15 + - name: Div1 + description: PREDIV input clock not divided + value: 0 + - name: Div2 + description: PREDIV input clock divided by 2 + value: 1 + - name: Div3 + description: PREDIV input clock divided by 3 + value: 2 + - name: Div4 + description: PREDIV input clock divided by 4 + value: 3 + - name: Div5 + description: PREDIV input clock divided by 5 + value: 4 + - name: Div6 + description: PREDIV input clock divided by 6 + value: 5 + - name: Div7 + description: PREDIV input clock divided by 7 + value: 6 + - name: Div8 + description: PREDIV input clock divided by 8 + value: 7 + - name: Div9 + description: PREDIV input clock divided by 9 + value: 8 + - name: Div10 + description: PREDIV input clock divided by 10 + value: 9 + - name: Div11 + description: PREDIV input clock divided by 11 + value: 10 + - name: Div12 + description: PREDIV input clock divided by 12 + value: 11 + - name: Div13 + description: PREDIV input clock divided by 13 + value: 12 + - name: Div14 + description: PREDIV input clock divided by 14 + value: 13 + - name: Div15 + description: PREDIV input clock divided by 15 + value: 14 + - name: Div16 + description: PREDIV input clock divided by 16 + value: 15 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: HSE oscillator clock divided by a prescaler used as RTC clock - value: 3 + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 enum/SW: bit_size: 2 variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: HSE - description: HSE selected as system clock - value: 1 - - name: PLL - description: PLL selected as system clock - value: 2 -enum/SWS: - bit_size: 2 - variants: - - name: HSI - description: HSI oscillator used as system clock - value: 0 - - name: HSE - description: HSE oscillator used as system clock - value: 1 - - name: PLL - description: PLL used as system clock - value: 2 + - name: HSI + description: HSI selected as system clock + value: 0 + - name: HSE + description: HSE selected as system clock + value: 1 + - name: PLL + description: PLL selected as system clock + value: 2 diff --git a/data/registers/rcc_f1cl.yaml b/data/registers/rcc_f1cl.yaml index e48898f..6dd0090 100644 --- a/data/registers/rcc_f1cl.yaml +++ b/data/registers/rcc_f1cl.yaml @@ -1,961 +1,948 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: Clock control register - byte_offset: 0 - fieldset: CR - - name: CFGR - description: Clock configuration register (RCC_CFGR) - byte_offset: 4 - fieldset: CFGR - - name: CIR - description: Clock interrupt register (RCC_CIR) - byte_offset: 8 - fieldset: CIR - - name: APB2RSTR - description: APB2 peripheral reset register (RCC_APB2RSTR) - byte_offset: 12 - fieldset: APB2RSTR - - name: APB1RSTR - description: APB1 peripheral reset register (RCC_APB1RSTR) - byte_offset: 16 - fieldset: APB1RSTR - - name: AHBENR - description: AHB Peripheral Clock enable register (RCC_AHBENR) - byte_offset: 20 - fieldset: AHBENR - - name: APB2ENR - description: APB2 peripheral clock enable register (RCC_APB2ENR) - byte_offset: 24 - fieldset: APB2ENR - - name: APB1ENR - description: APB1 peripheral clock enable register (RCC_APB1ENR) - byte_offset: 28 - fieldset: APB1ENR - - name: BDCR - description: Backup domain control register (RCC_BDCR) - byte_offset: 32 - fieldset: BDCR - - name: CSR - description: Control/status register (RCC_CSR) - byte_offset: 36 - fieldset: CSR - - name: AHBRSTR - description: AHB peripheral clock reset register (RCC_AHBRSTR) - byte_offset: 40 - fieldset: AHBRSTR - - name: CFGR2 - description: Clock configuration register 2 - byte_offset: 44 - fieldset: CFGR2 + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: CFGR + description: Clock configuration register (RCC_CFGR) + byte_offset: 4 + fieldset: CFGR + - name: CIR + description: Clock interrupt register (RCC_CIR) + byte_offset: 8 + fieldset: CIR + - name: APB2RSTR + description: APB2 peripheral reset register (RCC_APB2RSTR) + byte_offset: 12 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register (RCC_APB1RSTR) + byte_offset: 16 + fieldset: APB1RSTR + - name: AHBENR + description: AHB Peripheral Clock enable register (RCC_AHBENR) + byte_offset: 20 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register (RCC_APB2ENR) + byte_offset: 24 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register (RCC_APB1ENR) + byte_offset: 28 + fieldset: APB1ENR + - name: BDCR + description: Backup domain control register (RCC_BDCR) + byte_offset: 32 + fieldset: BDCR + - name: CSR + description: Control/status register (RCC_CSR) + byte_offset: 36 + fieldset: CSR + - name: AHBRSTR + description: AHB peripheral clock reset register (RCC_AHBRSTR) + byte_offset: 40 + fieldset: AHBRSTR + - name: CFGR2 + description: Clock configuration register 2 + byte_offset: 44 + fieldset: CFGR2 fieldset/AHBENR: description: AHB Peripheral Clock enable register (RCC_AHBENR) fields: - - name: DMA1EN - description: DMA1 clock enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: DMA2 clock enable - bit_offset: 1 - bit_size: 1 - - name: SRAMEN - description: SRAM interface clock enable - bit_offset: 2 - bit_size: 1 - - name: FLASHEN - description: FLASH clock enable - bit_offset: 4 - bit_size: 1 - - name: CRCEN - description: CRC clock enable - bit_offset: 6 - bit_size: 1 - - name: USB_OTG_FSEN - description: USB OTG FS clock enable - bit_offset: 12 - bit_size: 1 - - name: ETHEN - description: Ethernet MAC clock enable - bit_offset: 14 - bit_size: 1 - - name: ETHTXEN - description: Ethernet MAC TX clock enable - bit_offset: 15 - bit_size: 1 - - name: ETHRXEN - description: Ethernet MAC RX clock enable - bit_offset: 16 - bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: SRAMEN + description: SRAM interface clock enable + bit_offset: 2 + bit_size: 1 + - name: FLASHEN + description: FLASH clock enable + bit_offset: 4 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 6 + bit_size: 1 + - name: USB_OTG_FSEN + description: USB OTG FS clock enable + bit_offset: 12 + bit_size: 1 + - name: ETHEN + description: Ethernet MAC clock enable + bit_offset: 14 + bit_size: 1 + - name: ETHTXEN + description: Ethernet MAC TX clock enable + bit_offset: 15 + bit_size: 1 + - name: ETHRXEN + description: Ethernet MAC RX clock enable + bit_offset: 16 + bit_size: 1 fieldset/AHBRSTR: description: AHB peripheral clock reset register (RCC_AHBRSTR) fields: - - name: USB_OTG_FSRST - description: USB OTG FS reset - bit_offset: 12 - bit_size: 1 - - name: ETHRST - description: Ethernet MAC reset - bit_offset: 14 - bit_size: 1 + - name: USB_OTG_FSRST + description: USB OTG FS reset + bit_offset: 12 + bit_size: 1 + - name: ETHRST + description: Ethernet MAC reset + bit_offset: 14 + bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register (RCC_APB1ENR) fields: - - name: TIM2EN - description: Timer 2 clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: Timer 3 clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: Timer 4 clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: Timer 5 clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: Timer 6 clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: Timer 7 clock enable - bit_offset: 5 - bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI 2 clock enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI 3 clock enable - bit_offset: 15 - bit_size: 1 - - name: USART2EN - description: USART 2 clock enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART 3 clock enable - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: UART 4 clock enable - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: UART 5 clock enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C 1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C 2 clock enable - bit_offset: 22 - bit_size: 1 - - name: CAN1EN - description: CAN1 clock enable - bit_offset: 25 - bit_size: 1 - - name: CAN2EN - description: CAN2 clock enable - bit_offset: 26 - bit_size: 1 - - name: BKPEN - description: Backup interface clock enable - bit_offset: 27 - bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - - name: DACEN - description: DAC interface clock enable - bit_offset: 29 - bit_size: 1 + - name: TIM2EN + description: Timer 2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: Timer 4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: Timer 5 clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: Timer 7 clock enable + bit_offset: 5 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI 2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI 3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART 3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART 4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART 5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C 2 clock enable + bit_offset: 22 + bit_size: 1 + - name: CAN1EN + description: CAN1 clock enable + bit_offset: 25 + bit_size: 1 + - name: CAN2EN + description: CAN2 clock enable + bit_offset: 26 + bit_size: 1 + - name: BKPEN + description: Backup interface clock enable + bit_offset: 27 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register (RCC_APB1RSTR) fields: - - name: TIM2RST - description: Timer 2 reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: Timer 3 reset - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: Timer 4 reset - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: Timer 5 reset - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: Timer 6 reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: Timer 7 reset - bit_offset: 5 - bit_size: 1 - - name: WWDGRST - description: Window watchdog reset - bit_offset: 11 - bit_size: 1 - - name: SPI2RST - description: SPI2 reset - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: SPI3 reset - bit_offset: 15 - bit_size: 1 - - name: USART2RST - description: USART 2 reset - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: USART 3 reset - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: USART 4 reset - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: USART 5 reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C2 reset - bit_offset: 22 - bit_size: 1 - - name: CAN1RST - description: CAN1 reset - bit_offset: 25 - bit_size: 1 - - name: CAN2RST - description: CAN2 reset - bit_offset: 26 - bit_size: 1 - - name: BKPRST - description: Backup interface reset - bit_offset: 27 - bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - - name: DACRST - description: DAC interface reset - bit_offset: 29 - bit_size: 1 + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: Timer 4 reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: Timer 5 reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: Timer 6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: Timer 7 reset + bit_offset: 5 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART 3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: USART 4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: USART 5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: CAN1RST + description: CAN1 reset + bit_offset: 25 + bit_size: 1 + - name: CAN2RST + description: CAN2 reset + bit_offset: 26 + bit_size: 1 + - name: BKPRST + description: Backup interface reset + bit_offset: 27 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register (RCC_APB2ENR) fields: - - name: AFIOEN - description: Alternate function I/O clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOAEN - description: I/O port A clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIOBEN - description: I/O port B clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOCEN - description: I/O port C clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIODEN - description: I/O port D clock enable - bit_offset: 5 - bit_size: 1 - - name: GPIOEEN - description: I/O port E clock enable - bit_offset: 6 - bit_size: 1 - - name: ADC1EN - description: ADC 1 interface clock enable - bit_offset: 9 - bit_size: 1 - - name: ADC2EN - description: ADC 2 interface clock enable - bit_offset: 10 - bit_size: 1 - - name: TIM1EN - description: TIM1 Timer clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: SPI 1 clock enable - bit_offset: 12 - bit_size: 1 - - name: USART1EN - description: USART1 clock enable - bit_offset: 14 - bit_size: 1 + - name: AFIOEN + description: Alternate function I/O clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOAEN + description: I/O port A clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIOBEN + description: I/O port B clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOCEN + description: I/O port C clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIODEN + description: I/O port D clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOEEN + description: I/O port E clock enable + bit_offset: 6 + bit_size: 1 + - name: ADC1EN + description: ADC 1 interface clock enable + bit_offset: 9 + bit_size: 1 + - name: ADC2EN + description: ADC 2 interface clock enable + bit_offset: 10 + bit_size: 1 + - name: TIM1EN + description: TIM1 Timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register (RCC_APB2RSTR) fields: - - name: AFIORST - description: Alternate function I/O reset - bit_offset: 0 - bit_size: 1 - - name: GPIOARST - description: IO port A reset - bit_offset: 2 - bit_size: 1 - - name: GPIOBRST - description: IO port B reset - bit_offset: 3 - bit_size: 1 - - name: GPIOCRST - description: IO port C reset - bit_offset: 4 - bit_size: 1 - - name: GPIODRST - description: IO port D reset - bit_offset: 5 - bit_size: 1 - - name: GPIOERST - description: IO port E reset - bit_offset: 6 - bit_size: 1 - - name: ADC1RST - description: ADC 1 interface reset - bit_offset: 9 - bit_size: 1 - - name: ADC2RST - description: ADC 2 interface reset - bit_offset: 10 - bit_size: 1 - - name: TIM1RST - description: TIM1 timer reset - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: SPI 1 reset - bit_offset: 12 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 14 - bit_size: 1 + - name: AFIORST + description: Alternate function I/O reset + bit_offset: 0 + bit_size: 1 + - name: GPIOARST + description: IO port A reset + bit_offset: 2 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 3 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 4 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 5 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 6 + bit_size: 1 + - name: ADC1RST + description: ADC 1 interface reset + bit_offset: 9 + bit_size: 1 + - name: ADC2RST + description: ADC 2 interface reset + bit_offset: 10 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 fieldset/BDCR: description: Backup domain control register (RCC_BDCR) fields: - - name: LSEON - description: External Low Speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: External Low Speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: External Low Speed oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: Backup domain software reset - bit_offset: 16 - bit_size: 1 + - name: LSEON + description: External Low Speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External Low Speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: External Low Speed oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 fieldset/CFGR: description: Clock configuration register (RCC_CFGR) fields: - - name: SW - description: System clock Switch - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: System Clock Switch Status - bit_offset: 2 - bit_size: 2 - enum: SWS - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - enum: HPRE - - name: PPRE1 - description: APB Low speed prescaler (APB1) - bit_offset: 8 - bit_size: 3 - enum: PPRE1 - - name: PPRE2 - description: APB High speed prescaler (APB2) - bit_offset: 11 - bit_size: 3 - enum: PPRE1 - - name: ADCPRE - description: ADC prescaler - bit_offset: 14 - bit_size: 2 - enum: ADCPRE - - name: PLLSRC - description: PLL entry clock source - bit_offset: 16 - bit_size: 1 - enum: PLLSRC - - name: PLLXTPRE - description: HSE divider for PLL entry - bit_offset: 17 - bit_size: 1 - enum: PLLXTPRE - - name: PLLMUL - description: PLL Multiplication Factor - bit_offset: 18 - bit_size: 4 - enum: PLLMUL - - name: USBPRE - description: USB prescaler - bit_offset: 22 - bit_size: 1 - enum: USBPRE - - name: MCO - description: Microcontroller clock output - bit_offset: 24 - bit_size: 4 - enum: MCO + - name: SW + description: System clock Switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System Clock Switch Status + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB High speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: ADCPRE + description: ADC prescaler + bit_offset: 14 + bit_size: 2 + enum: ADCPRE + - name: PLLSRC + description: PLL entry clock source + bit_offset: 16 + bit_size: 1 + enum: PLLSRC + - name: PLLXTPRE + description: HSE divider for PLL entry + bit_offset: 17 + bit_size: 1 + enum: PLLXTPRE + - name: PLLMUL + description: PLL Multiplication Factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: USBPRE + description: USB prescaler + bit_offset: 22 + bit_size: 1 + enum: USBPRE + - name: MCO + description: Microcontroller clock output + bit_offset: 24 + bit_size: 4 + enum: MCO fieldset/CFGR2: description: Clock configuration register2 (RCC_CFGR2) fields: - - name: PREDIV1 - description: PREDIV1 division factor - bit_offset: 0 - bit_size: 4 - enum: PREDIV1 - - name: PREDIV2 - description: PREDIV2 division factor - bit_offset: 4 - bit_size: 4 - enum: PREDIV1 - - name: PLL2MUL - description: PLL2 Multiplication Factor - bit_offset: 8 - bit_size: 4 - enum: PLL2MUL - - name: PLL3MUL - description: PLL3 Multiplication Factor - bit_offset: 12 - bit_size: 4 - enum: PLL2MUL - - name: PREDIV1SRC - description: PREDIV1 entry clock source - bit_offset: 16 - bit_size: 1 - enum: PREDIV1SRC - - name: I2S2SRC - description: I2S2 clock source - bit_offset: 17 - bit_size: 1 - enum: I2S2SRC - - name: I2S3SRC - description: I2S3 clock source - bit_offset: 18 - bit_size: 1 - enum: I2S2SRC + - name: PREDIV1 + description: PREDIV1 division factor + bit_offset: 0 + bit_size: 4 + enum: PREDIV1 + - name: PREDIV2 + description: PREDIV2 division factor + bit_offset: 4 + bit_size: 4 + enum: PREDIV1 + - name: PLL2MUL + description: PLL2 Multiplication Factor + bit_offset: 8 + bit_size: 4 + enum: PLL2MUL + - name: PLL3MUL + description: PLL3 Multiplication Factor + bit_offset: 12 + bit_size: 4 + enum: PLL2MUL + - name: PREDIV1SRC + description: PREDIV1 entry clock source + bit_offset: 16 + bit_size: 1 + enum: PREDIV1SRC + - name: I2S2SRC + description: I2S2 clock source + bit_offset: 17 + bit_size: 1 + enum: I2S2SRC + - name: I2S3SRC + description: I2S3 clock source + bit_offset: 18 + bit_size: 1 + enum: I2S2SRC fieldset/CIR: description: Clock interrupt register (RCC_CIR) fields: - - name: LSIRDYF - description: LSI Ready Interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE Ready Interrupt flag - bit_offset: 1 - bit_size: 1 - - name: HSIRDYF - description: HSI Ready Interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSERDYF - description: HSE Ready Interrupt flag - bit_offset: 3 - bit_size: 1 - - name: PLLRDYF - description: PLL Ready Interrupt flag - bit_offset: 4 - bit_size: 1 - - name: PLL2RDYF - description: PLL2 Ready Interrupt flag - bit_offset: 5 - bit_size: 1 - - name: PLL3RDYF - description: PLL3 Ready Interrupt flag - bit_offset: 6 - bit_size: 1 - - name: CSSF - description: Clock Security System Interrupt flag - bit_offset: 7 - bit_size: 1 - - name: LSIRDYIE - description: LSI Ready Interrupt Enable - bit_offset: 8 - bit_size: 1 - - name: LSERDYIE - description: LSE Ready Interrupt Enable - bit_offset: 9 - bit_size: 1 - - name: HSIRDYIE - description: HSI Ready Interrupt Enable - bit_offset: 10 - bit_size: 1 - - name: HSERDYIE - description: HSE Ready Interrupt Enable - bit_offset: 11 - bit_size: 1 - - name: PLLRDYIE - description: PLL Ready Interrupt Enable - bit_offset: 12 - bit_size: 1 - - name: PLL2RDYIE - description: PLL2 Ready Interrupt Enable - bit_offset: 13 - bit_size: 1 - - name: PLL3RDYIE - description: PLL3 Ready Interrupt Enable - bit_offset: 14 - bit_size: 1 - - name: LSIRDYC - description: LSI Ready Interrupt Clear - bit_offset: 16 - bit_size: 1 - - name: LSERDYC - description: LSE Ready Interrupt Clear - bit_offset: 17 - bit_size: 1 - - name: HSIRDYC - description: HSI Ready Interrupt Clear - bit_offset: 18 - bit_size: 1 - - name: HSERDYC - description: HSE Ready Interrupt Clear - bit_offset: 19 - bit_size: 1 - - name: PLLRDYC - description: PLL Ready Interrupt Clear - bit_offset: 20 - bit_size: 1 - - name: PLL2RDYC - description: PLL2 Ready Interrupt Clear - bit_offset: 21 - bit_size: 1 - - name: PLL3RDYC - description: PLL3 Ready Interrupt Clear - bit_offset: 22 - bit_size: 1 - - name: CSSC - description: Clock security system interrupt clear - bit_offset: 23 - bit_size: 1 + - name: LSIRDYF + description: LSI Ready Interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE Ready Interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI Ready Interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE Ready Interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: PLL Ready Interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLL2RDYF + description: PLL2 Ready Interrupt flag + bit_offset: 5 + bit_size: 1 + - name: PLL3RDYF + description: PLL3 Ready Interrupt flag + bit_offset: 6 + bit_size: 1 + - name: CSSF + description: Clock Security System Interrupt flag + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI Ready Interrupt Enable + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE Ready Interrupt Enable + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI Ready Interrupt Enable + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE Ready Interrupt Enable + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: PLL Ready Interrupt Enable + bit_offset: 12 + bit_size: 1 + - name: PLL2RDYIE + description: PLL2 Ready Interrupt Enable + bit_offset: 13 + bit_size: 1 + - name: PLL3RDYIE + description: PLL3 Ready Interrupt Enable + bit_offset: 14 + bit_size: 1 + - name: LSIRDYC + description: LSI Ready Interrupt Clear + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE Ready Interrupt Clear + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI Ready Interrupt Clear + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE Ready Interrupt Clear + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: PLL Ready Interrupt Clear + bit_offset: 20 + bit_size: 1 + - name: PLL2RDYC + description: PLL2 Ready Interrupt Clear + bit_offset: 21 + bit_size: 1 + - name: PLL3RDYC + description: PLL3 Ready Interrupt Clear + bit_offset: 22 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 fieldset/CR: description: Clock control register fields: - - name: HSION - description: Internal High Speed clock enable - bit_offset: 0 - bit_size: 1 - - name: HSIRDY - description: Internal High Speed clock ready flag - bit_offset: 1 - bit_size: 1 - - name: HSITRIM - description: Internal High Speed clock trimming - bit_offset: 3 - bit_size: 5 - - name: HSICAL - description: Internal High Speed clock Calibration - bit_offset: 8 - bit_size: 8 - - name: HSEON - description: External High Speed clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: External High Speed clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: External High Speed clock Bypass - bit_offset: 18 - bit_size: 1 - - name: CSSON - description: Clock Security System enable - bit_offset: 19 - bit_size: 1 - - name: PLLON - description: PLL enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: PLL clock ready flag - bit_offset: 25 - bit_size: 1 - - name: PLL2ON - description: PLL2 enable - bit_offset: 26 - bit_size: 1 - - name: PLL2RDY - description: PLL2 clock ready flag - bit_offset: 27 - bit_size: 1 - - name: PLL3ON - description: PLL3 enable - bit_offset: 28 - bit_size: 1 - - name: PLL3RDY - description: PLL3 clock ready flag - bit_offset: 29 - bit_size: 1 + - name: HSION + description: Internal High Speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal High Speed clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSITRIM + description: Internal High Speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal High Speed clock Calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: External High Speed clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: External High Speed clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: External High Speed clock Bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 + - name: PLL2ON + description: PLL2 enable + bit_offset: 26 + bit_size: 1 + - name: PLL2RDY + description: PLL2 clock ready flag + bit_offset: 27 + bit_size: 1 + - name: PLL3ON + description: PLL3 enable + bit_offset: 28 + bit_size: 1 + - name: PLL3RDY + description: PLL3 clock ready flag + bit_offset: 29 + bit_size: 1 fieldset/CSR: description: Control/status register (RCC_CSR) fields: - - name: LSION - description: Internal low speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: Internal low speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: RMVF - description: Remove reset flag - bit_offset: 24 - bit_size: 1 - - name: PINRSTF - description: PIN reset flag - bit_offset: 26 - bit_size: 1 - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: Independent watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSION + description: Internal low speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 enum/ADCPRE: bit_size: 2 variants: - - name: Div2 - description: PCLK2 divided by 2 - value: 0 - - name: Div4 - description: PCLK2 divided by 4 - value: 1 - - name: Div6 - description: PCLK2 divided by 6 - value: 2 - - name: Div8 - description: PCLK2 divided by 8 - value: 3 + - name: Div2 + description: PCLK2 divided by 2 + value: 0 + - name: Div4 + description: PCLK2 divided by 4 + value: 1 + - name: Div6 + description: PCLK2 divided by 6 + value: 2 + - name: Div8 + description: PCLK2 divided by 8 + value: 3 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: SYSCLK not divided - value: 0 - - name: Div2 - description: SYSCLK divided by 2 - value: 8 - - name: Div4 - description: SYSCLK divided by 4 - value: 9 - - name: Div8 - description: SYSCLK divided by 8 - value: 10 - - name: Div16 - description: SYSCLK divided by 16 - value: 11 - - name: Div64 - description: SYSCLK divided by 64 - value: 12 - - name: Div128 - description: SYSCLK divided by 128 - value: 13 - - name: Div256 - description: SYSCLK divided by 256 - value: 14 - - name: Div512 - description: SYSCLK divided by 512 - value: 15 + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 enum/I2S2SRC: bit_size: 1 variants: - - name: SYSCLK - description: System clock (SYSCLK) selected as I2S clock entry - value: 0 - - name: PLL3 - description: PLL3 VCO clock selected as I2S clock entry - value: 1 + - name: SYSCLK + description: System clock (SYSCLK) selected as I2S clock entry + value: 0 + - name: PLL3 + description: PLL3 VCO clock selected as I2S clock entry + value: 1 enum/MCO: bit_size: 4 variants: - - name: NoMCO - description: "MCO output disabled, no clock on MCO" - value: 0 - - name: SYSCLK - description: System clock selected - value: 4 - - name: HSI - description: HSI oscillator clock selected - value: 5 - - name: HSE - description: HSE oscillator clock selected - value: 6 - - name: PLL - description: PLL clock divided by 2 selected - value: 7 - - name: PLL2 - description: PLL2 clock selected - value: 8 - - name: PLL3DIV2 - description: PLL3 clock divided by 2 selected - value: 9 - - name: XT1 - description: XT1 external oscillator selected - value: 10 - - name: PLL3 - description: PLL3 clock selected - value: 11 + - name: NoMCO + description: MCO output disabled, no clock on MCO + value: 0 + - name: SYSCLK + description: System clock selected + value: 4 + - name: HSI + description: HSI oscillator clock selected + value: 5 + - name: HSE + description: HSE oscillator clock selected + value: 6 + - name: PLL + description: PLL clock divided by 2 selected + value: 7 + - name: PLL2 + description: PLL2 clock selected + value: 8 + - name: PLL3DIV2 + description: PLL3 clock divided by 2 selected + value: 9 + - name: XT1 + description: XT1 external oscillator selected + value: 10 + - name: PLL3 + description: PLL3 clock selected + value: 11 enum/PLL2MUL: bit_size: 4 variants: - - name: Mul8 - description: PLL clock entry x8 - value: 6 - - name: Mul9 - description: PLL clock entry x9 - value: 7 - - name: Mul10 - description: PLL clock entry x10 - value: 8 - - name: Mul11 - description: PLL clock entry x11 - value: 9 - - name: Mul12 - description: PLL clock entry x12 - value: 10 - - name: Mul13 - description: PLL clock entry x13 - value: 11 - - name: Mul14 - description: PLL clock entry x14 - value: 12 - - name: Mul16 - description: PLL clock entry x16 - value: 14 - - name: Mul20 - description: PLL clock entry x20 - value: 15 + - name: Mul8 + description: PLL clock entry x8 + value: 6 + - name: Mul9 + description: PLL clock entry x9 + value: 7 + - name: Mul10 + description: PLL clock entry x10 + value: 8 + - name: Mul11 + description: PLL clock entry x11 + value: 9 + - name: Mul12 + description: PLL clock entry x12 + value: 10 + - name: Mul13 + description: PLL clock entry x13 + value: 11 + - name: Mul14 + description: PLL clock entry x14 + value: 12 + - name: Mul16 + description: PLL clock entry x16 + value: 14 + - name: Mul20 + description: PLL clock entry x20 + value: 15 enum/PLLMUL: bit_size: 4 variants: - - name: Mul4 - description: PLL input clock x4 - value: 2 - - name: Mul5 - description: PLL input clock x5 - value: 3 - - name: Mul6 - description: PLL input clock x6 - value: 4 - - name: Mul7 - description: PLL input clock x7 - value: 5 - - name: Mul8 - description: PLL input clock x8 - value: 6 - - name: Mul9 - description: PLL input clock x9 - value: 7 - - name: Mul6_5 - description: PLL input clock x6.5 - value: 13 + - name: Mul4 + description: PLL input clock x4 + value: 2 + - name: Mul5 + description: PLL input clock x5 + value: 3 + - name: Mul6 + description: PLL input clock x6 + value: 4 + - name: Mul7 + description: PLL input clock x7 + value: 5 + - name: Mul8 + description: PLL input clock x8 + value: 6 + - name: Mul9 + description: PLL input clock x9 + value: 7 + - name: Mul6_5 + description: PLL input clock x6.5 + value: 13 enum/PLLSRC: bit_size: 1 variants: - - name: HSI_Div2 - description: HSI divided by 2 selected as PLL input clock - value: 0 - - name: HSE_Div_PREDIV - description: HSE divided by PREDIV selected as PLL input clock - value: 1 + - name: HSI_Div2 + description: HSI divided by 2 selected as PLL input clock + value: 0 + - name: HSE_Div_PREDIV + description: HSE divided by PREDIV selected as PLL input clock + value: 1 enum/PLLXTPRE: bit_size: 1 variants: - - name: Div1 - description: HSE clock not divided - value: 0 - - name: Div2 - description: HSE clock divided by 2 - value: 1 -enum/PPRE1: + - name: Div1 + description: HSE clock not divided + value: 0 + - name: Div2 + description: HSE clock divided by 2 + value: 1 +enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK divided by 2 - value: 4 - - name: Div4 - description: HCLK divided by 4 - value: 5 - - name: Div8 - description: HCLK divided by 8 - value: 6 - - name: Div16 - description: HCLK divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 enum/PREDIV1: bit_size: 4 variants: - - name: Div1 - description: PREDIV input clock not divided - value: 0 - - name: Div2 - description: PREDIV input clock divided by 2 - value: 1 - - name: Div3 - description: PREDIV input clock divided by 3 - value: 2 - - name: Div4 - description: PREDIV input clock divided by 4 - value: 3 - - name: Div5 - description: PREDIV input clock divided by 5 - value: 4 - - name: Div6 - description: PREDIV input clock divided by 6 - value: 5 - - name: Div7 - description: PREDIV input clock divided by 7 - value: 6 - - name: Div8 - description: PREDIV input clock divided by 8 - value: 7 - - name: Div9 - description: PREDIV input clock divided by 9 - value: 8 - - name: Div10 - description: PREDIV input clock divided by 10 - value: 9 - - name: Div11 - description: PREDIV input clock divided by 11 - value: 10 - - name: Div12 - description: PREDIV input clock divided by 12 - value: 11 - - name: Div13 - description: PREDIV input clock divided by 13 - value: 12 - - name: Div14 - description: PREDIV input clock divided by 14 - value: 13 - - name: Div15 - description: PREDIV input clock divided by 15 - value: 14 - - name: Div16 - description: PREDIV input clock divided by 16 - value: 15 + - name: Div1 + description: PREDIV input clock not divided + value: 0 + - name: Div2 + description: PREDIV input clock divided by 2 + value: 1 + - name: Div3 + description: PREDIV input clock divided by 3 + value: 2 + - name: Div4 + description: PREDIV input clock divided by 4 + value: 3 + - name: Div5 + description: PREDIV input clock divided by 5 + value: 4 + - name: Div6 + description: PREDIV input clock divided by 6 + value: 5 + - name: Div7 + description: PREDIV input clock divided by 7 + value: 6 + - name: Div8 + description: PREDIV input clock divided by 8 + value: 7 + - name: Div9 + description: PREDIV input clock divided by 9 + value: 8 + - name: Div10 + description: PREDIV input clock divided by 10 + value: 9 + - name: Div11 + description: PREDIV input clock divided by 11 + value: 10 + - name: Div12 + description: PREDIV input clock divided by 12 + value: 11 + - name: Div13 + description: PREDIV input clock divided by 13 + value: 12 + - name: Div14 + description: PREDIV input clock divided by 14 + value: 13 + - name: Div15 + description: PREDIV input clock divided by 15 + value: 14 + - name: Div16 + description: PREDIV input clock divided by 16 + value: 15 enum/PREDIV1SRC: bit_size: 1 variants: - - name: HSE - description: HSE oscillator clock selected as PREDIV1 clock entry - value: 0 - - name: PLL2 - description: PLL2 selected as PREDIV1 clock entry - value: 1 + - name: HSE + description: HSE oscillator clock selected as PREDIV1 clock entry + value: 0 + - name: PLL2 + description: PLL2 selected as PREDIV1 clock entry + value: 1 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: HSE oscillator clock divided by a prescaler used as RTC clock - value: 3 + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 enum/SW: bit_size: 2 variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: HSE - description: HSE selected as system clock - value: 1 - - name: PLL - description: PLL selected as system clock - value: 2 -enum/SWS: - bit_size: 2 - variants: - - name: HSI - description: HSI oscillator used as system clock - value: 0 - - name: HSE - description: HSE oscillator used as system clock - value: 1 - - name: PLL - description: PLL used as system clock - value: 2 + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL + description: PLL used as system clock + value: 2 enum/USBPRE: bit_size: 1 variants: - - name: DIV1_5 - description: PLL clock is divided by 1.5 - value: 0 - - name: DIV1 - description: PLL clock is not divided - value: 1 + - name: Div1_5 + description: PLL clock is divided by 1.5 + value: 0 + - name: Div1 + description: PLL clock is not divided + value: 1 diff --git a/data/registers/rcc_f2.yaml b/data/registers/rcc_f2.yaml index 2f35de9..955d03a 100644 --- a/data/registers/rcc_f2.yaml +++ b/data/registers/rcc_f2.yaml @@ -1,1352 +1,1339 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: clock control register - byte_offset: 0 - fieldset: CR - - name: PLLCFGR - description: PLL configuration register - byte_offset: 4 - fieldset: PLLCFGR - - name: CFGR - description: clock configuration register - byte_offset: 8 - fieldset: CFGR - - name: CIR - description: clock interrupt register - byte_offset: 12 - fieldset: CIR - - name: AHB1RSTR - description: AHB1 peripheral reset register - byte_offset: 16 - fieldset: AHB1RSTR - - name: AHB2RSTR - description: AHB2 peripheral reset register - byte_offset: 20 - fieldset: AHB2RSTR - - name: AHB3RSTR - description: AHB3 peripheral reset register - byte_offset: 24 - fieldset: AHB3RSTR - - name: APB1RSTR - description: APB1 peripheral reset register - byte_offset: 32 - fieldset: APB1RSTR - - name: APB2RSTR - description: APB2 peripheral reset register - byte_offset: 36 - fieldset: APB2RSTR - - name: AHB1ENR - description: AHB1 peripheral clock register - byte_offset: 48 - fieldset: AHB1ENR - - name: AHB2ENR - description: AHB2 peripheral clock enable register - byte_offset: 52 - fieldset: AHB2ENR - - name: AHB3ENR - description: AHB3 peripheral clock enable register - byte_offset: 56 - fieldset: AHB3ENR - - name: APB1ENR - description: APB1 peripheral clock enable register - byte_offset: 64 - fieldset: APB1ENR - - name: APB2ENR - description: APB2 peripheral clock enable register - byte_offset: 68 - fieldset: APB2ENR - - name: AHB1LPENR - description: AHB1 peripheral clock enable in low power mode register - byte_offset: 80 - fieldset: AHB1LPENR - - name: AHB2LPENR - description: AHB2 peripheral clock enable in low power mode register - byte_offset: 84 - fieldset: AHB2LPENR - - name: AHB3LPENR - description: AHB3 peripheral clock enable in low power mode register - byte_offset: 88 - fieldset: AHB3LPENR - - name: APB1LPENR - description: APB1 peripheral clock enable in low power mode register - byte_offset: 96 - fieldset: APB1LPENR - - name: APB2LPENR - description: APB2 peripheral clock enabled in low power mode register - byte_offset: 100 - fieldset: APB2LPENR - - name: BDCR - description: Backup domain control register - byte_offset: 112 - fieldset: BDCR - - name: CSR - description: clock control & status register - byte_offset: 116 - fieldset: CSR - - name: SSCGR - description: spread spectrum clock generation register - byte_offset: 128 - fieldset: SSCGR - - name: PLLI2SCFGR - description: PLLI2S configuration register - byte_offset: 132 - fieldset: PLLI2SCFGR + - name: CR + description: clock control register + byte_offset: 0 + fieldset: CR + - name: PLLCFGR + description: PLL configuration register + byte_offset: 4 + fieldset: PLLCFGR + - name: CFGR + description: clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: CIR + description: clock interrupt register + byte_offset: 12 + fieldset: CIR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 16 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: AHB2 peripheral reset register + byte_offset: 20 + fieldset: AHB2RSTR + - name: AHB3RSTR + description: AHB3 peripheral reset register + byte_offset: 24 + fieldset: AHB3RSTR + - name: APB1RSTR + description: APB1 peripheral reset register + byte_offset: 32 + fieldset: APB1RSTR + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 36 + fieldset: APB2RSTR + - name: AHB1ENR + description: AHB1 peripheral clock register + byte_offset: 48 + fieldset: AHB1ENR + - name: AHB2ENR + description: AHB2 peripheral clock enable register + byte_offset: 52 + fieldset: AHB2ENR + - name: AHB3ENR + description: AHB3 peripheral clock enable register + byte_offset: 56 + fieldset: AHB3ENR + - name: APB1ENR + description: APB1 peripheral clock enable register + byte_offset: 64 + fieldset: APB1ENR + - name: APB2ENR + description: APB2 peripheral clock enable register + byte_offset: 68 + fieldset: APB2ENR + - name: AHB1LPENR + description: AHB1 peripheral clock enable in low power mode register + byte_offset: 80 + fieldset: AHB1LPENR + - name: AHB2LPENR + description: AHB2 peripheral clock enable in low power mode register + byte_offset: 84 + fieldset: AHB2LPENR + - name: AHB3LPENR + description: AHB3 peripheral clock enable in low power mode register + byte_offset: 88 + fieldset: AHB3LPENR + - name: APB1LPENR + description: APB1 peripheral clock enable in low power mode register + byte_offset: 96 + fieldset: APB1LPENR + - name: APB2LPENR + description: APB2 peripheral clock enabled in low power mode register + byte_offset: 100 + fieldset: APB2LPENR + - name: BDCR + description: Backup domain control register + byte_offset: 112 + fieldset: BDCR + - name: CSR + description: clock control & status register + byte_offset: 116 + fieldset: CSR + - name: SSCGR + description: spread spectrum clock generation register + byte_offset: 128 + fieldset: SSCGR + - name: PLLI2SCFGR + description: PLLI2S configuration register + byte_offset: 132 + fieldset: PLLI2SCFGR fieldset/AHB1ENR: description: AHB1 peripheral clock register fields: - - name: GPIOAEN - description: IO port A clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: IO port B clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: IO port C clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: IO port D clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: IO port E clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIOFEN - description: IO port F clock enable - bit_offset: 5 - bit_size: 1 - - name: GPIOGEN - description: IO port G clock enable - bit_offset: 6 - bit_size: 1 - - name: GPIOHEN - description: IO port H clock enable - bit_offset: 7 - bit_size: 1 - - name: GPIOIEN - description: IO port I clock enable - bit_offset: 8 - bit_size: 1 - - name: CRCEN - description: CRC clock enable - bit_offset: 12 - bit_size: 1 - - name: BKPSRAMEN - description: Backup SRAM interface clock enable - bit_offset: 18 - bit_size: 1 - - name: DMA1EN - description: DMA1 clock enable - bit_offset: 21 - bit_size: 1 - - name: DMA2EN - description: DMA2 clock enable - bit_offset: 22 - bit_size: 1 - - name: ETHEN - description: Ethernet MAC clock enable - bit_offset: 25 - bit_size: 1 - - name: ETHTXEN - description: Ethernet Transmission clock enable - bit_offset: 26 - bit_size: 1 - - name: ETHRXEN - description: Ethernet Reception clock enable - bit_offset: 27 - bit_size: 1 - - name: ETHPTPEN - description: Ethernet PTP clock enable - bit_offset: 28 - bit_size: 1 - - name: USB_OTG_HSEN - description: USB OTG HS clock enable - bit_offset: 29 - bit_size: 1 - - name: USB_OTG_HSULPIEN - description: USB OTG HSULPI clock enable - bit_offset: 30 - bit_size: 1 + - name: GPIOAEN + description: IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: IO port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: IO port E clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: IO port F clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: IO port G clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: IO port H clock enable + bit_offset: 7 + bit_size: 1 + - name: GPIOIEN + description: IO port I clock enable + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: BKPSRAMEN + description: Backup SRAM interface clock enable + bit_offset: 18 + bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 21 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 22 + bit_size: 1 + - name: ETHEN + description: Ethernet MAC clock enable + bit_offset: 25 + bit_size: 1 + - name: ETHTXEN + description: Ethernet Transmission clock enable + bit_offset: 26 + bit_size: 1 + - name: ETHRXEN + description: Ethernet Reception clock enable + bit_offset: 27 + bit_size: 1 + - name: ETHPTPEN + description: Ethernet PTP clock enable + bit_offset: 28 + bit_size: 1 + - name: USB_OTG_HSEN + description: USB OTG HS clock enable + bit_offset: 29 + bit_size: 1 + - name: USB_OTG_HSULPIEN + description: USB OTG HSULPI clock enable + bit_offset: 30 + bit_size: 1 fieldset/AHB1LPENR: description: AHB1 peripheral clock enable in low power mode register fields: - - name: GPIOALPEN - description: IO port A clock enable during sleep mode - bit_offset: 0 - bit_size: 1 - - name: GPIOBLPEN - description: IO port B clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: GPIOCLPEN - description: IO port C clock enable during Sleep mode - bit_offset: 2 - bit_size: 1 - - name: GPIODLPEN - description: IO port D clock enable during Sleep mode - bit_offset: 3 - bit_size: 1 - - name: GPIOELPEN - description: IO port E clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: GPIOFLPEN - description: IO port F clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: GPIOGLPEN - description: IO port G clock enable during Sleep mode - bit_offset: 6 - bit_size: 1 - - name: GPIOHLPEN - description: IO port H clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 - - name: GPIOILPEN - description: IO port I clock enable during Sleep mode - bit_offset: 8 - bit_size: 1 - - name: CRCLPEN - description: CRC clock enable during Sleep mode - bit_offset: 12 - bit_size: 1 - - name: FLASHLPEN - description: Flash interface clock enable during Sleep mode - bit_offset: 15 - bit_size: 1 - - name: SRAM1LPEN - description: SRAM 1interface clock enable during Sleep mode - bit_offset: 16 - bit_size: 1 - - name: SRAM2LPEN - description: SRAM 2 interface clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: BKPSRAMLPEN - description: Backup SRAM interface clock enable during Sleep mode - bit_offset: 18 - bit_size: 1 - - name: DMA1LPEN - description: DMA1 clock enable during Sleep mode - bit_offset: 21 - bit_size: 1 - - name: DMA2LPEN - description: DMA2 clock enable during Sleep mode - bit_offset: 22 - bit_size: 1 - - name: ETHLPEN - description: Ethernet MAC clock enable during Sleep mode - bit_offset: 25 - bit_size: 1 - - name: ETHTXLPEN - description: Ethernet transmission clock enable during Sleep mode - bit_offset: 26 - bit_size: 1 - - name: ETHRXLPEN - description: Ethernet reception clock enable during Sleep mode - bit_offset: 27 - bit_size: 1 - - name: ETHPTPLPEN - description: Ethernet PTP clock enable during Sleep mode - bit_offset: 28 - bit_size: 1 - - name: USB_OTG_HSLPEN - description: USB OTG HS clock enable during Sleep mode - bit_offset: 29 - bit_size: 1 - - name: USB_OTG_HSULPILPEN - description: USB OTG HS ULPI clock enable during Sleep mode - bit_offset: 30 - bit_size: 1 + - name: GPIOALPEN + description: IO port A clock enable during sleep mode + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: IO port B clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: IO port C clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: GPIODLPEN + description: IO port D clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: GPIOELPEN + description: IO port E clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: GPIOFLPEN + description: IO port F clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: GPIOGLPEN + description: IO port G clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: GPIOHLPEN + description: IO port H clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: GPIOILPEN + description: IO port I clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: CRCLPEN + description: CRC clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: FLASHLPEN + description: Flash interface clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: SRAM1LPEN + description: SRAM 1interface clock enable during Sleep mode + bit_offset: 16 + bit_size: 1 + - name: SRAM2LPEN + description: SRAM 2 interface clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: BKPSRAMLPEN + description: Backup SRAM interface clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: DMA1LPEN + description: DMA1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: DMA2LPEN + description: DMA2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: ETHLPEN + description: Ethernet MAC clock enable during Sleep mode + bit_offset: 25 + bit_size: 1 + - name: ETHTXLPEN + description: Ethernet transmission clock enable during Sleep mode + bit_offset: 26 + bit_size: 1 + - name: ETHRXLPEN + description: Ethernet reception clock enable during Sleep mode + bit_offset: 27 + bit_size: 1 + - name: ETHPTPLPEN + description: Ethernet PTP clock enable during Sleep mode + bit_offset: 28 + bit_size: 1 + - name: USB_OTG_HSLPEN + description: USB OTG HS clock enable during Sleep mode + bit_offset: 29 + bit_size: 1 + - name: USB_OTG_HSULPILPEN + description: USB OTG HS ULPI clock enable during Sleep mode + bit_offset: 30 + bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - - name: GPIOARST - description: IO port A reset - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: IO port B reset - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: IO port C reset - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: IO port D reset - bit_offset: 3 - bit_size: 1 - - name: GPIOERST - description: IO port E reset - bit_offset: 4 - bit_size: 1 - - name: GPIOFRST - description: IO port F reset - bit_offset: 5 - bit_size: 1 - - name: GPIOGRST - description: IO port G reset - bit_offset: 6 - bit_size: 1 - - name: GPIOHRST - description: IO port H reset - bit_offset: 7 - bit_size: 1 - - name: GPIOIRST - description: IO port I reset - bit_offset: 8 - bit_size: 1 - - name: CRCRST - description: CRC reset - bit_offset: 12 - bit_size: 1 - - name: DMA1RST - description: DMA2 reset - bit_offset: 21 - bit_size: 1 - - name: DMA2RST - description: DMA2 reset - bit_offset: 22 - bit_size: 1 - - name: ETHRST - description: Ethernet MAC reset - bit_offset: 25 - bit_size: 1 - - name: USB_OTG_HSRST - description: USB OTG HS module reset - bit_offset: 29 - bit_size: 1 + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 6 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 7 + bit_size: 1 + - name: GPIOIRST + description: IO port I reset + bit_offset: 8 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 + - name: DMA1RST + description: DMA2 reset + bit_offset: 21 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 22 + bit_size: 1 + - name: ETHRST + description: Ethernet MAC reset + bit_offset: 25 + bit_size: 1 + - name: USB_OTG_HSRST + description: USB OTG HS module reset + bit_offset: 29 + bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - - name: DCMIEN - description: Camera interface enable - bit_offset: 0 - bit_size: 1 - - name: CRYPEN - description: Cryptographic modules clock enable - bit_offset: 4 - bit_size: 1 - - name: HASHEN - description: Hash modules clock enable - bit_offset: 5 - bit_size: 1 - - name: RNGEN - description: Random number generator clock enable - bit_offset: 6 - bit_size: 1 - - name: USB_OTG_FSEN - description: USB OTG FS clock enable - bit_offset: 7 - bit_size: 1 + - name: DCMIEN + description: Camera interface enable + bit_offset: 0 + bit_size: 1 + - name: CRYPEN + description: Cryptographic modules clock enable + bit_offset: 4 + bit_size: 1 + - name: HASHEN + description: Hash modules clock enable + bit_offset: 5 + bit_size: 1 + - name: RNGEN + description: Random number generator clock enable + bit_offset: 6 + bit_size: 1 + - name: USB_OTG_FSEN + description: USB OTG FS clock enable + bit_offset: 7 + bit_size: 1 fieldset/AHB2LPENR: description: AHB2 peripheral clock enable in low power mode register fields: - - name: DCMILPEN - description: Camera interface enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: CRYPLPEN - description: Cryptography modules clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: HASHLPEN - description: Hash modules clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: RNGLPEN - description: Random number generator clock enable during Sleep mode - bit_offset: 6 - bit_size: 1 - - name: USB_OTG_FSLPEN - description: USB OTG FS clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 + - name: DCMILPEN + description: Camera interface enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: CRYPLPEN + description: Cryptography modules clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: HASHLPEN + description: Hash modules clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: RNGLPEN + description: Random number generator clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: USB_OTG_FSLPEN + description: USB OTG FS clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - - name: DCMIRST - description: Camera interface reset - bit_offset: 0 - bit_size: 1 - - name: CRYPRST - description: Cryptographic module reset - bit_offset: 4 - bit_size: 1 - - name: HSAHRST - description: Hash module reset - bit_offset: 5 - bit_size: 1 - - name: RNGRST - description: Random number generator module reset - bit_offset: 6 - bit_size: 1 - - name: USB_OTG_FSRST - description: USB OTG FS module reset - bit_offset: 7 - bit_size: 1 + - name: DCMIRST + description: Camera interface reset + bit_offset: 0 + bit_size: 1 + - name: CRYPRST + description: Cryptographic module reset + bit_offset: 4 + bit_size: 1 + - name: HSAHRST + description: Hash module reset + bit_offset: 5 + bit_size: 1 + - name: RNGRST + description: Random number generator module reset + bit_offset: 6 + bit_size: 1 + - name: USB_OTG_FSRST + description: USB OTG FS module reset + bit_offset: 7 + bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: - - name: FSMCEN - description: Flexible static memory controller module clock enable - bit_offset: 0 - bit_size: 1 + - name: FSMCEN + description: Flexible static memory controller module clock enable + bit_offset: 0 + bit_size: 1 fieldset/AHB3LPENR: description: AHB3 peripheral clock enable in low power mode register fields: - - name: FSMCLPEN - description: Flexible static memory controller module clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 + - name: FSMCLPEN + description: Flexible static memory controller module clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - - name: FSMCRST - description: Flexible static memory controller module reset - bit_offset: 0 - bit_size: 1 + - name: FSMCRST + description: Flexible static memory controller module reset + bit_offset: 0 + bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register fields: - - name: TIM2EN - description: TIM2 clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: TIM3 clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: TIM4 clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: TIM5 clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: TIM6 clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: TIM7 clock enable - bit_offset: 5 - bit_size: 1 - - name: TIM12EN - description: TIM12 clock enable - bit_offset: 6 - bit_size: 1 - - name: TIM13EN - description: TIM13 clock enable - bit_offset: 7 - bit_size: 1 - - name: TIM14EN - description: TIM14 clock enable - bit_offset: 8 - bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI2 clock enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI3 clock enable - bit_offset: 15 - bit_size: 1 - - name: USART2EN - description: USART 2 clock enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART3 clock enable - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: UART4 clock enable - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: UART5 clock enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C2 clock enable - bit_offset: 22 - bit_size: 1 - - name: I2C3EN - description: I2C3 clock enable - bit_offset: 23 - bit_size: 1 - - name: CAN1EN - description: CAN 1 clock enable - bit_offset: 25 - bit_size: 1 - - name: CAN2EN - description: CAN 2 clock enable - bit_offset: 26 - bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - - name: DACEN - description: DAC interface clock enable - bit_offset: 29 - bit_size: 1 + - name: TIM2EN + description: TIM2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: TIM5 clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM7 clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: TIM12 clock enable + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: TIM13 clock enable + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: TIM14 clock enable + bit_offset: 8 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 23 + bit_size: 1 + - name: CAN1EN + description: CAN 1 clock enable + bit_offset: 25 + bit_size: 1 + - name: CAN2EN + description: CAN 2 clock enable + bit_offset: 26 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 fieldset/APB1LPENR: description: APB1 peripheral clock enable in low power mode register fields: - - name: TIM2LPEN - description: TIM2 clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM3LPEN - description: TIM3 clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: TIM4LPEN - description: TIM4 clock enable during Sleep mode - bit_offset: 2 - bit_size: 1 - - name: TIM5LPEN - description: TIM5 clock enable during Sleep mode - bit_offset: 3 - bit_size: 1 - - name: TIM6LPEN - description: TIM6 clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: TIM7LPEN - description: TIM7 clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: TIM12LPEN - description: TIM12 clock enable during Sleep mode - bit_offset: 6 - bit_size: 1 - - name: TIM13LPEN - description: TIM13 clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 - - name: TIM14LPEN - description: TIM14 clock enable during Sleep mode - bit_offset: 8 - bit_size: 1 - - name: WWDGLPEN - description: Window watchdog clock enable during Sleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI2LPEN - description: SPI2 clock enable during Sleep mode - bit_offset: 14 - bit_size: 1 - - name: SPI3LPEN - description: SPI3 clock enable during Sleep mode - bit_offset: 15 - bit_size: 1 - - name: USART2LPEN - description: USART2 clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: USART3LPEN - description: USART3 clock enable during Sleep mode - bit_offset: 18 - bit_size: 1 - - name: UART4LPEN - description: UART4 clock enable during Sleep mode - bit_offset: 19 - bit_size: 1 - - name: UART5LPEN - description: UART5 clock enable during Sleep mode - bit_offset: 20 - bit_size: 1 - - name: I2C1LPEN - description: I2C1 clock enable during Sleep mode - bit_offset: 21 - bit_size: 1 - - name: I2C2LPEN - description: I2C2 clock enable during Sleep mode - bit_offset: 22 - bit_size: 1 - - name: I2C3LPEN - description: I2C3 clock enable during Sleep mode - bit_offset: 23 - bit_size: 1 - - name: CAN1LPEN - description: CAN 1 clock enable during Sleep mode - bit_offset: 25 - bit_size: 1 - - name: CAN2LPEN - description: CAN 2 clock enable during Sleep mode - bit_offset: 26 - bit_size: 1 - - name: PWRLPEN - description: Power interface clock enable during Sleep mode - bit_offset: 28 - bit_size: 1 - - name: DACLPEN - description: DAC interface clock enable during Sleep mode - bit_offset: 29 - bit_size: 1 + - name: TIM2LPEN + description: TIM2 clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM3LPEN + description: TIM3 clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: TIM4LPEN + description: TIM4 clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: TIM5LPEN + description: TIM5 clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: TIM6LPEN + description: TIM6 clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: TIM7LPEN + description: TIM7 clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: TIM12LPEN + description: TIM12 clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: TIM13LPEN + description: TIM13 clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: TIM14LPEN + description: TIM14 clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: WWDGLPEN + description: Window watchdog clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI2LPEN + description: SPI2 clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: SPI3LPEN + description: SPI3 clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: USART2LPEN + description: USART2 clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: USART3LPEN + description: USART3 clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: UART4LPEN + description: UART4 clock enable during Sleep mode + bit_offset: 19 + bit_size: 1 + - name: UART5LPEN + description: UART5 clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 + - name: I2C1LPEN + description: I2C1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: I2C2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: I2C3LPEN + description: I2C3 clock enable during Sleep mode + bit_offset: 23 + bit_size: 1 + - name: CAN1LPEN + description: CAN 1 clock enable during Sleep mode + bit_offset: 25 + bit_size: 1 + - name: CAN2LPEN + description: CAN 2 clock enable during Sleep mode + bit_offset: 26 + bit_size: 1 + - name: PWRLPEN + description: Power interface clock enable during Sleep mode + bit_offset: 28 + bit_size: 1 + - name: DACLPEN + description: DAC interface clock enable during Sleep mode + bit_offset: 29 + bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register fields: - - name: TIM2RST - description: TIM2 reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: TIM3 reset - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: TIM4 reset - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: TIM5 reset - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: TIM6 reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: TIM7 reset - bit_offset: 5 - bit_size: 1 - - name: TIM12RST - description: TIM12 reset - bit_offset: 6 - bit_size: 1 - - name: TIM13RST - description: TIM13 reset - bit_offset: 7 - bit_size: 1 - - name: TIM14RST - description: TIM14 reset - bit_offset: 8 - bit_size: 1 - - name: WWDGRST - description: Window watchdog reset - bit_offset: 11 - bit_size: 1 - - name: SPI2RST - description: SPI 2 reset - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: SPI 3 reset - bit_offset: 15 - bit_size: 1 - - name: UART2RST - description: USART 2 reset - bit_offset: 17 - bit_size: 1 - - name: UART3RST - description: USART 3 reset - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: USART 4 reset - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: USART 5 reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C 1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C 2 reset - bit_offset: 22 - bit_size: 1 - - name: I2C3RST - description: I2C3 reset - bit_offset: 23 - bit_size: 1 - - name: CAN1RST - description: CAN1 reset - bit_offset: 25 - bit_size: 1 - - name: CAN2RST - description: CAN2 reset - bit_offset: 26 - bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - - name: DACRST - description: DAC reset - bit_offset: 29 - bit_size: 1 + - name: TIM2RST + description: TIM2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: TIM3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: TIM4 reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: TIM5 reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: TIM6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM7 reset + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: TIM12 reset + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: TIM13 reset + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: TIM14 reset + bit_offset: 8 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI 2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI 3 reset + bit_offset: 15 + bit_size: 1 + - name: UART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: UART3RST + description: USART 3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: USART 4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: USART 5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C 1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C 2 reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 23 + bit_size: 1 + - name: CAN1RST + description: CAN1 reset + bit_offset: 25 + bit_size: 1 + - name: CAN2RST + description: CAN2 reset + bit_offset: 26 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC reset + bit_offset: 29 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - - name: TIM1EN - description: TIM1 clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM8EN - description: TIM8 clock enable - bit_offset: 1 - bit_size: 1 - - name: USART1EN - description: USART1 clock enable - bit_offset: 4 - bit_size: 1 - - name: USART6EN - description: USART6 clock enable - bit_offset: 5 - bit_size: 1 - - name: ADC1EN - description: ADC1 clock enable - bit_offset: 8 - bit_size: 1 - - name: ADC2EN - description: ADC2 clock enable - bit_offset: 9 - bit_size: 1 - - name: ADC3EN - description: ADC3 clock enable - bit_offset: 10 - bit_size: 1 - - name: SDIOEN - description: SDIO clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: SPI1 clock enable - bit_offset: 12 - bit_size: 1 - - name: SYSCFGEN - description: System configuration controller clock enable - bit_offset: 14 - bit_size: 1 - - name: TIM9EN - description: TIM9 clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM10EN - description: TIM10 clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM11EN - description: TIM11 clock enable - bit_offset: 18 - bit_size: 1 + - name: TIM1EN + description: TIM1 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM8EN + description: TIM8 clock enable + bit_offset: 1 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 4 + bit_size: 1 + - name: USART6EN + description: USART6 clock enable + bit_offset: 5 + bit_size: 1 + - name: ADC1EN + description: ADC1 clock enable + bit_offset: 8 + bit_size: 1 + - name: ADC2EN + description: ADC2 clock enable + bit_offset: 9 + bit_size: 1 + - name: ADC3EN + description: ADC3 clock enable + bit_offset: 10 + bit_size: 1 + - name: SDIOEN + description: SDIO clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: SYSCFGEN + description: System configuration controller clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM9EN + description: TIM9 clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM10EN + description: TIM10 clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM11EN + description: TIM11 clock enable + bit_offset: 18 + bit_size: 1 fieldset/APB2LPENR: description: APB2 peripheral clock enabled in low power mode register fields: - - name: TIM1LPEN - description: TIM1 clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM8LPEN - description: TIM8 clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: USART1LPEN - description: USART1 clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: USART6LPEN - description: USART6 clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: ADC1LPEN - description: ADC1 clock enable during Sleep mode - bit_offset: 8 - bit_size: 1 - - name: ADC2LPEN - description: ADC2 clock enable during Sleep mode - bit_offset: 9 - bit_size: 1 - - name: ADC3LPEN - description: ADC 3 clock enable during Sleep mode - bit_offset: 10 - bit_size: 1 - - name: SDIOLPEN - description: SDIO clock enable during Sleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI1LPEN - description: SPI 1 clock enable during Sleep mode - bit_offset: 12 - bit_size: 1 - - name: SYSCFGLPEN - description: System configuration controller clock enable during Sleep mode - bit_offset: 14 - bit_size: 1 - - name: TIM9LPEN - description: TIM9 clock enable during sleep mode - bit_offset: 16 - bit_size: 1 - - name: TIM10LPEN - description: TIM10 clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: TIM11LPEN - description: TIM11 clock enable during Sleep mode - bit_offset: 18 - bit_size: 1 + - name: TIM1LPEN + description: TIM1 clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM8LPEN + description: TIM8 clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: USART1LPEN + description: USART1 clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: USART6LPEN + description: USART6 clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: ADC1LPEN + description: ADC1 clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: ADC2LPEN + description: ADC2 clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: ADC3LPEN + description: ADC 3 clock enable during Sleep mode + bit_offset: 10 + bit_size: 1 + - name: SDIOLPEN + description: SDIO clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI1LPEN + description: SPI 1 clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: SYSCFGLPEN + description: System configuration controller clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: TIM9LPEN + description: TIM9 clock enable during sleep mode + bit_offset: 16 + bit_size: 1 + - name: TIM10LPEN + description: TIM10 clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: TIM11LPEN + description: TIM11 clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - - name: TIM1RST - description: TIM1 reset - bit_offset: 0 - bit_size: 1 - - name: TIM8RST - description: TIM8 reset - bit_offset: 1 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 4 - bit_size: 1 - - name: USART6RST - description: USART6 reset - bit_offset: 5 - bit_size: 1 - - name: ADCRST - description: ADC interface reset (common to all ADCs) - bit_offset: 8 - bit_size: 1 - - name: SDIORST - description: SDIO reset - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: SPI 1 reset - bit_offset: 12 - bit_size: 1 - - name: SYSCFGRST - description: System configuration controller reset - bit_offset: 14 - bit_size: 1 - - name: TIM9RST - description: TIM9 reset - bit_offset: 16 - bit_size: 1 - - name: TIM10RST - description: TIM10 reset - bit_offset: 17 - bit_size: 1 - - name: TIM11RST - description: TIM11 reset - bit_offset: 18 - bit_size: 1 + - name: TIM1RST + description: TIM1 reset + bit_offset: 0 + bit_size: 1 + - name: TIM8RST + description: TIM8 reset + bit_offset: 1 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 4 + bit_size: 1 + - name: USART6RST + description: USART6 reset + bit_offset: 5 + bit_size: 1 + - name: ADCRST + description: ADC interface reset (common to all ADCs) + bit_offset: 8 + bit_size: 1 + - name: SDIORST + description: SDIO reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: SYSCFGRST + description: System configuration controller reset + bit_offset: 14 + bit_size: 1 + - name: TIM9RST + description: TIM9 reset + bit_offset: 16 + bit_size: 1 + - name: TIM10RST + description: TIM10 reset + bit_offset: 17 + bit_size: 1 + - name: TIM11RST + description: TIM11 reset + bit_offset: 18 + bit_size: 1 fieldset/BDCR: description: Backup domain control register fields: - - name: LSEON - description: External low-speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: External low-speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: External low-speed oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: Backup domain software reset - bit_offset: 16 - bit_size: 1 + - name: LSEON + description: External low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External low-speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: External low-speed oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 fieldset/CFGR: description: clock configuration register fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: System clock switch status - bit_offset: 2 - bit_size: 2 - enum: SWS - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - enum: HPRE - - name: PPRE1 - description: APB Low speed prescaler (APB1) - bit_offset: 10 - bit_size: 3 - enum: PPRE - - name: PPRE2 - description: APB high-speed prescaler (APB2) - bit_offset: 13 - bit_size: 3 - enum: PPRE - - name: RTCPRE - description: HSE division factor for RTC clock - bit_offset: 16 - bit_size: 5 - - name: MCO1 - description: Microcontroller clock output 1 - bit_offset: 21 - bit_size: 2 - enum: MCO1 - - name: I2SSRC - description: I2S clock selection - bit_offset: 23 - bit_size: 1 - enum: ISSRC - - name: MCO1PRE - description: MCO1 prescaler - bit_offset: 24 - bit_size: 3 - enum: MCOPRE - - name: MCO2PRE - description: MCO2 prescaler - bit_offset: 27 - bit_size: 3 - enum: MCOPRE - - name: MCO2 - description: Microcontroller clock output 2 - bit_offset: 30 - bit_size: 2 - enum: MCO2 + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 10 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high-speed prescaler (APB2) + bit_offset: 13 + bit_size: 3 + enum: PPRE + - name: RTCPRE + description: HSE division factor for RTC clock + bit_offset: 16 + bit_size: 5 + - name: MCO1 + description: Microcontroller clock output 1 + bit_offset: 21 + bit_size: 2 + enum: MCO1 + - name: I2SSRC + description: I2S clock selection + bit_offset: 23 + bit_size: 1 + enum: ISSRC + - name: MCO1PRE + description: MCO1 prescaler + bit_offset: 24 + bit_size: 3 + enum: MCOPRE + - name: MCO2PRE + description: MCO2 prescaler + bit_offset: 27 + bit_size: 3 + enum: MCOPRE + - name: MCO2 + description: Microcontroller clock output 2 + bit_offset: 30 + bit_size: 2 + enum: MCO2 fieldset/CIR: description: clock interrupt register fields: - - name: LSIRDYF - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - - name: HSIRDYF - description: HSI ready interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSERDYF - description: HSE ready interrupt flag - bit_offset: 3 - bit_size: 1 - - name: PLLRDYF - description: Main PLL (PLL) ready interrupt flag - bit_offset: 4 - bit_size: 1 - - name: PLLI2SRDYF - description: PLLI2S ready interrupt flag - bit_offset: 5 - bit_size: 1 - - name: CSSF - description: Clock security system interrupt flag - bit_offset: 7 - bit_size: 1 - - name: LSIRDYIE - description: LSI ready interrupt enable - bit_offset: 8 - bit_size: 1 - - name: LSERDYIE - description: LSE ready interrupt enable - bit_offset: 9 - bit_size: 1 - - name: HSIRDYIE - description: HSI ready interrupt enable - bit_offset: 10 - bit_size: 1 - - name: HSERDYIE - description: HSE ready interrupt enable - bit_offset: 11 - bit_size: 1 - - name: PLLRDYIE - description: Main PLL (PLL) ready interrupt enable - bit_offset: 12 - bit_size: 1 - - name: PLLI2SRDYIE - description: PLLI2S ready interrupt enable - bit_offset: 13 - bit_size: 1 - - name: LSIRDYC - description: LSI ready interrupt clear - bit_offset: 16 - bit_size: 1 - - name: LSERDYC - description: LSE ready interrupt clear - bit_offset: 17 - bit_size: 1 - - name: HSIRDYC - description: HSI ready interrupt clear - bit_offset: 18 - bit_size: 1 - - name: HSERDYC - description: HSE ready interrupt clear - bit_offset: 19 - bit_size: 1 - - name: PLLRDYC - description: Main PLL(PLL) ready interrupt clear - bit_offset: 20 - bit_size: 1 - - name: PLLI2SRDYC - description: PLLI2S ready interrupt clear - bit_offset: 21 - bit_size: 1 - - name: CSSC - description: Clock security system interrupt clear - bit_offset: 23 - bit_size: 1 + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: Main PLL (PLL) ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLLI2SRDYF + description: PLLI2S ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: CSSF + description: Clock security system interrupt flag + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: Main PLL (PLL) ready interrupt enable + bit_offset: 12 + bit_size: 1 + - name: PLLI2SRDYIE + description: PLLI2S ready interrupt enable + bit_offset: 13 + bit_size: 1 + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: Main PLL(PLL) ready interrupt clear + bit_offset: 20 + bit_size: 1 + - name: PLLI2SRDYC + description: PLLI2S ready interrupt clear + bit_offset: 21 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 fieldset/CR: description: clock control register fields: - - name: HSION - description: Internal high-speed clock enable - bit_offset: 0 - bit_size: 1 - - name: HSIRDY - description: Internal high-speed clock ready flag - bit_offset: 1 - bit_size: 1 - - name: HSITRIM - description: Internal high-speed clock trimming - bit_offset: 3 - bit_size: 5 - - name: HSICAL - description: Internal high-speed clock calibration - bit_offset: 8 - bit_size: 8 - - name: HSEON - description: HSE clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: HSE clock bypass - bit_offset: 18 - bit_size: 1 - - name: CSSON - description: Clock security system enable - bit_offset: 19 - bit_size: 1 - - name: PLLON - description: Main PLL (PLL) enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: Main PLL (PLL) clock ready flag - bit_offset: 25 - bit_size: 1 - - name: PLLI2SON - description: PLLI2S enable - bit_offset: 26 - bit_size: 1 - - name: PLLI2SRDY - description: PLLI2S clock ready flag - bit_offset: 27 - bit_size: 1 + - name: HSION + description: Internal high-speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal high-speed clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSITRIM + description: Internal high-speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal high-speed clock calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: HSE clock bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: Main PLL (PLL) enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL (PLL) clock ready flag + bit_offset: 25 + bit_size: 1 + - name: PLLI2SON + description: PLLI2S enable + bit_offset: 26 + bit_size: 1 + - name: PLLI2SRDY + description: PLLI2S clock ready flag + bit_offset: 27 + bit_size: 1 fieldset/CSR: description: clock control & status register fields: - - name: LSION - description: Internal low-speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: Internal low-speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: RMVF - description: Remove reset flag - bit_offset: 24 - bit_size: 1 - - name: BORRSTF - description: BOR reset flag - bit_offset: 25 - bit_size: 1 - - name: PADRSTF - description: PIN reset flag - bit_offset: 26 - bit_size: 1 - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: WDGRSTF - description: Independent watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSION + description: Internal low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low-speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + - name: BORRSTF + description: BOR reset flag + bit_offset: 25 + bit_size: 1 + - name: PADRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: WDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 fieldset/PLLCFGR: description: PLL configuration register fields: - - name: PLLM - description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - bit_offset: 0 - bit_size: 6 - - name: PLLN - description: Main PLL (PLL) multiplication factor for VCO - bit_offset: 6 - bit_size: 9 - - name: PLLP - description: Main PLL (PLL) division factor for main system clock - bit_offset: 16 - bit_size: 2 - enum: PLLP - - name: PLLSRC - description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - bit_offset: 22 - bit_size: 1 - enum: PLLSRC - - name: PLLQ - description: "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks" - bit_offset: 24 - bit_size: 4 + - name: PLLM + description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + bit_offset: 0 + bit_size: 6 + - name: PLLN + description: Main PLL (PLL) multiplication factor for VCO + bit_offset: 6 + bit_size: 9 + - name: PLLP + description: Main PLL (PLL) division factor for main system clock + bit_offset: 16 + bit_size: 2 + enum: PLLP + - name: PLLSRC + description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + bit_offset: 22 + bit_size: 1 + enum: PLLSRC + - name: PLLQ + description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + bit_offset: 24 + bit_size: 4 fieldset/PLLI2SCFGR: description: PLLI2S configuration register fields: - - name: PLLI2SN - description: PLLI2S multiplication factor for VCO - bit_offset: 6 - bit_size: 9 - - name: PLLI2SR - description: PLLI2S division factor for I2S clocks - bit_offset: 28 - bit_size: 3 + - name: PLLI2SN + description: PLLI2S multiplication factor for VCO + bit_offset: 6 + bit_size: 9 + - name: PLLI2SR + description: PLLI2S division factor for I2S clocks + bit_offset: 28 + bit_size: 3 fieldset/SSCGR: description: spread spectrum clock generation register fields: - - name: MODPER - description: Modulation period - bit_offset: 0 - bit_size: 13 - - name: INCSTEP - description: Incrementation step - bit_offset: 13 - bit_size: 15 - - name: SPREADSEL - description: Spread Select - bit_offset: 30 - bit_size: 1 - enum: SPREADSEL - - name: SSCGEN - description: Spread spectrum modulation enable - bit_offset: 31 - bit_size: 1 + - name: MODPER + description: Modulation period + bit_offset: 0 + bit_size: 13 + - name: INCSTEP + description: Incrementation step + bit_offset: 13 + bit_size: 15 + - name: SPREADSEL + description: Spread Select + bit_offset: 30 + bit_size: 1 + enum: SPREADSEL + - name: SSCGEN + description: Spread spectrum modulation enable + bit_offset: 31 + bit_size: 1 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: SYSCLK not divided - value: 0 - - name: Div2 - description: SYSCLK divided by 2 - value: 8 - - name: Div4 - description: SYSCLK divided by 4 - value: 9 - - name: Div8 - description: SYSCLK divided by 8 - value: 10 - - name: Div16 - description: SYSCLK divided by 16 - value: 11 - - name: Div64 - description: SYSCLK divided by 64 - value: 12 - - name: Div128 - description: SYSCLK divided by 128 - value: 13 - - name: Div256 - description: SYSCLK divided by 256 - value: 14 - - name: Div512 - description: SYSCLK divided by 512 - value: 15 + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 enum/ISSRC: bit_size: 1 variants: - - name: PLLI2S - description: PLLI2S clock used as I2S clock source - value: 0 - - name: CKIN - description: External clock mapped on the I2S_CKIN pin used as I2S clock source - value: 1 + - name: PLLI2S + description: PLLI2S clock used as I2S clock source + value: 0 + - name: CKIN + description: External clock mapped on the I2S_CKIN pin used as I2S clock source + value: 1 enum/MCO1: bit_size: 2 variants: - - name: HSI - description: HSI clock selected - value: 0 - - name: LSE - description: LSE oscillator selected - value: 1 - - name: HSE - description: HSE oscillator clock selected - value: 2 - - name: PLL - description: PLL clock selected - value: 3 + - name: HSI + description: HSI clock selected + value: 0 + - name: LSE + description: LSE oscillator selected + value: 1 + - name: HSE + description: HSE oscillator clock selected + value: 2 + - name: PLL + description: PLL clock selected + value: 3 enum/MCO2: bit_size: 2 variants: - - name: SYSCLK - description: System clock (SYSCLK) selected - value: 0 - - name: PLLI2S - description: PLLI2S clock selected - value: 1 - - name: HSE - description: HSE oscillator clock selected - value: 2 - - name: PLL - description: PLL clock selected - value: 3 + - name: SYSCLK + description: System clock (SYSCLK) selected + value: 0 + - name: PLLI2S + description: PLLI2S clock selected + value: 1 + - name: HSE + description: HSE oscillator clock selected + value: 2 + - name: PLL + description: PLL clock selected + value: 3 enum/MCOPRE: bit_size: 3 variants: - - name: Div1 - description: No division - value: 0 - - name: Div2 - description: Division by 2 - value: 4 - - name: Div3 - description: Division by 3 - value: 5 - - name: Div4 - description: Division by 4 - value: 6 - - name: Div5 - description: Division by 5 - value: 7 + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 4 + - name: Div3 + description: Division by 3 + value: 5 + - name: Div4 + description: Division by 4 + value: 6 + - name: Div5 + description: Division by 5 + value: 7 enum/PLLP: bit_size: 2 variants: - - name: Div2 - description: PLLP=2 - value: 0 - - name: Div4 - description: PLLP=4 - value: 1 - - name: Div6 - description: PLLP=6 - value: 2 - - name: Div8 - description: PLLP=8 - value: 3 + - name: Div2 + description: PLLP=2 + value: 0 + - name: Div4 + description: PLLP=4 + value: 1 + - name: Div6 + description: PLLP=6 + value: 2 + - name: Div8 + description: PLLP=8 + value: 3 enum/PLLSRC: bit_size: 1 variants: - - name: HSI - description: HSI clock selected as PLL and PLLI2S clock entry - value: 0 - - name: HSE - description: HSE oscillator clock selected as PLL and PLLI2S clock entry - value: 1 + - name: HSI + description: HSI clock selected as PLL and PLLI2S clock entry + value: 0 + - name: HSE + description: HSE oscillator clock selected as PLL and PLLI2S clock entry + value: 1 enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK divided by 2 - value: 4 - - name: Div4 - description: HCLK divided by 4 - value: 5 - - name: Div8 - description: HCLK divided by 8 - value: 6 - - name: Div16 - description: HCLK divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: HSE oscillator clock divided by a prescaler used as RTC clock - value: 3 + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 enum/SPREADSEL: bit_size: 1 variants: - - name: Center - description: Center spread - value: 0 - - name: Down - description: Down spread - value: 1 + - name: Center + description: Center spread + value: 0 + - name: Down + description: Down spread + value: 1 enum/SW: bit_size: 2 variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: HSE - description: HSE selected as system clock - value: 1 - - name: PLL - description: PLL selected as system clock - value: 2 -enum/SWS: - bit_size: 2 - variants: - - name: HSI - description: HSI oscillator used as system clock - value: 0 - - name: HSE - description: HSE oscillator used as system clock - value: 1 - - name: PLL - description: PLL used as system clock - value: 2 + - name: HSI + description: HSI selected as system clock + value: 0 + - name: HSE + description: HSE selected as system clock + value: 1 + - name: PLL + description: PLL selected as system clock + value: 2 diff --git a/data/registers/rcc_f3.yaml b/data/registers/rcc_f3.yaml index abeff29..e6ce340 100644 --- a/data/registers/rcc_f3.yaml +++ b/data/registers/rcc_f3.yaml @@ -1,1379 +1,1282 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: Clock control register - byte_offset: 0 - fieldset: CR - - name: CFGR - description: Clock configuration register (RCC_CFGR) - byte_offset: 4 - fieldset: CFGR - - name: CIR - description: Clock interrupt register (RCC_CIR) - byte_offset: 8 - fieldset: CIR - - name: APB2RSTR - description: APB2 peripheral reset register (RCC_APB2RSTR) - byte_offset: 12 - fieldset: APB2RSTR - - name: APB1RSTR - description: APB1 peripheral reset register (RCC_APB1RSTR) - byte_offset: 16 - fieldset: APB1RSTR - - name: AHBENR - description: AHB Peripheral Clock enable register (RCC_AHBENR) - byte_offset: 20 - fieldset: AHBENR - - name: APB2ENR - description: APB2 peripheral clock enable register (RCC_APB2ENR) - byte_offset: 24 - fieldset: APB2ENR - - name: APB1ENR - description: APB1 peripheral clock enable register (RCC_APB1ENR) - byte_offset: 28 - fieldset: APB1ENR - - name: BDCR - description: Backup domain control register (RCC_BDCR) - byte_offset: 32 - fieldset: BDCR - - name: CSR - description: Control/status register (RCC_CSR) - byte_offset: 36 - fieldset: CSR - - name: AHBRSTR - description: AHB peripheral reset register - byte_offset: 40 - fieldset: AHBRSTR - - name: CFGR2 - description: Clock configuration register 2 - byte_offset: 44 - fieldset: CFGR2 - - name: CFGR3 - description: Clock configuration register 3 - byte_offset: 48 - fieldset: CFGR3 + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: CFGR + description: Clock configuration register (RCC_CFGR) + byte_offset: 4 + fieldset: CFGR + - name: CIR + description: Clock interrupt register (RCC_CIR) + byte_offset: 8 + fieldset: CIR + - name: APB2RSTR + description: APB2 peripheral reset register (RCC_APB2RSTR) + byte_offset: 12 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register (RCC_APB1RSTR) + byte_offset: 16 + fieldset: APB1RSTR + - name: AHBENR + description: AHB Peripheral Clock enable register (RCC_AHBENR) + byte_offset: 20 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register (RCC_APB2ENR) + byte_offset: 24 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register (RCC_APB1ENR) + byte_offset: 28 + fieldset: APB1ENR + - name: BDCR + description: Backup domain control register (RCC_BDCR) + byte_offset: 32 + fieldset: BDCR + - name: CSR + description: Control/status register (RCC_CSR) + byte_offset: 36 + fieldset: CSR + - name: AHBRSTR + description: AHB peripheral reset register + byte_offset: 40 + fieldset: AHBRSTR + - name: CFGR2 + description: Clock configuration register 2 + byte_offset: 44 + fieldset: CFGR2 + - name: CFGR3 + description: Clock configuration register 3 + byte_offset: 48 + fieldset: CFGR3 fieldset/AHBENR: description: AHB Peripheral Clock enable register (RCC_AHBENR) fields: - - name: DMA1EN - description: DMA1 clock enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: DMA2 clock enable - bit_offset: 1 - bit_size: 1 - - name: SRAMEN - description: SRAM interface clock enable - bit_offset: 2 - bit_size: 1 - - name: FLASHEN - description: FLASH clock enable - bit_offset: 4 - bit_size: 1 - - name: FMCEN - description: FMC clock enable - bit_offset: 5 - bit_size: 1 - - name: CRCEN - description: CRC clock enable - bit_offset: 6 - bit_size: 1 - - name: GPIOHEN - description: IO port H clock enable - bit_offset: 16 - bit_size: 1 - - name: GPIOAEN - description: I/O port A clock enable - bit_offset: 17 - bit_size: 1 - - name: GPIOBEN - description: I/O port B clock enable - bit_offset: 18 - bit_size: 1 - - name: GPIOCEN - description: I/O port C clock enable - bit_offset: 19 - bit_size: 1 - - name: GPIODEN - description: I/O port D clock enable - bit_offset: 20 - bit_size: 1 - - name: GPIOEEN - description: I/O port E clock enable - bit_offset: 21 - bit_size: 1 - - name: GPIOFEN - description: I/O port F clock enable - bit_offset: 22 - bit_size: 1 - - name: GPIOGEN - description: IO port G clock enable - bit_offset: 23 - bit_size: 1 - - name: TSCEN - description: Touch sensing controller clock enable - bit_offset: 24 - bit_size: 1 - - name: ADC12EN - description: ADC1 and ADC2 clock enable - bit_offset: 28 - bit_size: 1 - - name: ADC1EN - description: ADC 1 - bit_offset: 28 - bit_size: 1 - - name: ADC34EN - description: ADC3 and ADC4 clock enable - bit_offset: 29 - bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: SRAMEN + description: SRAM interface clock enable + bit_offset: 2 + bit_size: 1 + - name: FLASHEN + description: FLASH clock enable + bit_offset: 4 + bit_size: 1 + - name: FMCEN + description: FMC clock enable + bit_offset: 5 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: IO port H clock enable + bit_offset: 16 + bit_size: 1 + - name: GPIOAEN + description: I/O port A clock enable + bit_offset: 17 + bit_size: 1 + - name: GPIOBEN + description: I/O port B clock enable + bit_offset: 18 + bit_size: 1 + - name: GPIOCEN + description: I/O port C clock enable + bit_offset: 19 + bit_size: 1 + - name: GPIODEN + description: I/O port D clock enable + bit_offset: 20 + bit_size: 1 + - name: GPIOEEN + description: I/O port E clock enable + bit_offset: 21 + bit_size: 1 + - name: GPIOFEN + description: I/O port F clock enable + bit_offset: 22 + bit_size: 1 + - name: GPIOGEN + description: IO port G clock enable + bit_offset: 23 + bit_size: 1 + - name: TSCEN + description: Touch sensing controller clock enable + bit_offset: 24 + bit_size: 1 + - name: ADC12EN + description: ADC1 and ADC2 clock enable + bit_offset: 28 + bit_size: 1 + - name: ADC34EN + description: ADC3 and ADC4 clock enable + bit_offset: 29 + bit_size: 1 fieldset/AHBRSTR: description: AHB peripheral reset register fields: - - name: FMCRST - description: FMC reset - bit_offset: 5 - bit_size: 1 - - name: GPIOHRST - description: IO port H reset - bit_offset: 16 - bit_size: 1 - - name: GPIOARST - description: I/O port A reset - bit_offset: 17 - bit_size: 1 - - name: GPIOBRST - description: I/O port B reset - bit_offset: 18 - bit_size: 1 - - name: GPIOCRST - description: I/O port C reset - bit_offset: 19 - bit_size: 1 - - name: GPIODRST - description: I/O port D reset - bit_offset: 20 - bit_size: 1 - - name: GPIOERST - description: I/O port E reset - bit_offset: 21 - bit_size: 1 - - name: GPIOFRST - description: I/O port F reset - bit_offset: 22 - bit_size: 1 - - name: GPIOGRST - description: IO port G reset - bit_offset: 23 - bit_size: 1 - - name: TSCRST - description: Touch sensing controller reset - bit_offset: 24 - bit_size: 1 - - name: ADC12RST - description: ADC1 and ADC2 reset - bit_offset: 28 - bit_size: 1 - - name: ADC1RST - description: ADC1 reset - bit_offset: 28 - bit_size: 1 - - name: ADC34RST - description: ADC3 and ADC4 reset - bit_offset: 29 - bit_size: 1 + - name: FMCRST + description: FMC reset + bit_offset: 5 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 16 + bit_size: 1 + - name: GPIOARST + description: I/O port A reset + bit_offset: 17 + bit_size: 1 + - name: GPIOBRST + description: I/O port B reset + bit_offset: 18 + bit_size: 1 + - name: GPIOCRST + description: I/O port C reset + bit_offset: 19 + bit_size: 1 + - name: GPIODRST + description: I/O port D reset + bit_offset: 20 + bit_size: 1 + - name: GPIOERST + description: I/O port E reset + bit_offset: 21 + bit_size: 1 + - name: GPIOFRST + description: I/O port F reset + bit_offset: 22 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 23 + bit_size: 1 + - name: TSCRST + description: Touch sensing controller reset + bit_offset: 24 + bit_size: 1 + - name: ADC12RST + description: ADC1 and ADC2 reset + bit_offset: 28 + bit_size: 1 + - name: ADC34RST + description: ADC3 and ADC4 reset + bit_offset: 29 + bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register (RCC_APB1ENR) fields: - - name: TIM2EN - description: Timer 2 clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: Timer 3 clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: Timer 4 clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: Timer 5 clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: Timer 6 clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: Timer 7 clock enable - bit_offset: 5 - bit_size: 1 - - name: TIM12EN - description: Timer 12 clock enable - bit_offset: 6 - bit_size: 1 - - name: TIM13EN - description: Timer 13 clock enable - bit_offset: 7 - bit_size: 1 - - name: TIM14EN - description: Timer 14 clock enable - bit_offset: 8 - bit_size: 1 - - name: TIM18EN - description: Timer 18 clock enable - bit_offset: 9 - bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI 2 clock enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI 3 clock enable - bit_offset: 15 - bit_size: 1 - - name: USART2EN - description: USART 2 clock enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART 3 clock enable - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: UART4 clock enable - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: UART5 clock enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C 1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C 2 clock enable - bit_offset: 22 - bit_size: 1 - - name: USBEN - description: USB clock enable - bit_offset: 23 - bit_size: 1 - - name: CANEN - description: CAN clock enable - bit_offset: 25 - bit_size: 1 - - name: DAC2EN - description: DAC2 interface clock enable - bit_offset: 26 - bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - - name: DACEN - description: DAC interface clock enable - bit_offset: 29 - bit_size: 1 - - name: CECEN - description: HDMI CEC interface clock enable - bit_offset: 30 - bit_size: 1 - - name: I2C3EN - description: I2C3 clock enable - bit_offset: 30 - bit_size: 1 + - name: TIM2EN + description: Timer 2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: Timer 4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: Timer 7 clock enable + bit_offset: 5 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI 2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI 3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART 3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C 2 clock enable + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: USB clock enable + bit_offset: 23 + bit_size: 1 + - name: CANEN + description: CAN clock enable + bit_offset: 25 + bit_size: 1 + - name: DAC2EN + description: DAC2 interface clock enable + bit_offset: 26 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 30 + bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register (RCC_APB1RSTR) fields: - - name: TIM2RST - description: Timer 2 reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: Timer 3 reset - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: Timer 14 reset - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: Timer 5 reset - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: Timer 6 reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: Timer 7 reset - bit_offset: 5 - bit_size: 1 - - name: TIM12RST - description: Timer 12 reset - bit_offset: 6 - bit_size: 1 - - name: TIM13RST - description: Timer 13 reset - bit_offset: 7 - bit_size: 1 - - name: TIM14RST - description: Timer 14 reset - bit_offset: 8 - bit_size: 1 - - name: TIM18RST - description: Timer 18 reset - bit_offset: 9 - bit_size: 1 - - name: WWDGRST - description: Window watchdog reset - bit_offset: 11 - bit_size: 1 - - name: SPI2RST - description: SPI2 reset - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: SPI3 reset - bit_offset: 15 - bit_size: 1 - - name: USART2RST - description: USART 2 reset - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: USART3 reset - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: UART 4 reset - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: UART 5 reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C2 reset - bit_offset: 22 - bit_size: 1 - - name: USBRST - description: USB reset - bit_offset: 23 - bit_size: 1 - - name: CANRST - description: CAN reset - bit_offset: 25 - bit_size: 1 - - name: DAC2RST - description: DAC2 interface reset - bit_offset: 26 - bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - - name: DACRST - description: DAC interface reset - bit_offset: 29 - bit_size: 1 - - name: CECRST - description: HDMI CEC reset - bit_offset: 30 - bit_size: 1 - - name: I2C3RST - description: I2C3 reset - bit_offset: 30 - bit_size: 1 + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: Timer 14 reset + bit_offset: 2 + bit_size: 1 + - name: TIM6RST + description: Timer 6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: Timer 7 reset + bit_offset: 5 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: UART 4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: UART 5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: USB reset + bit_offset: 23 + bit_size: 1 + - name: CANRST + description: CAN reset + bit_offset: 25 + bit_size: 1 + - name: DAC2RST + description: DAC2 interface reset + bit_offset: 26 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 30 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register (RCC_APB2ENR) fields: - - name: SYSCFGEN - description: SYSCFG clock enable - bit_offset: 0 - bit_size: 1 - - name: ADCEN - description: ADC 1 interface clock enable - bit_offset: 9 - bit_size: 1 - - name: TIM1EN - description: TIM1 Timer clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: SPI 1 clock enable - bit_offset: 12 - bit_size: 1 - - name: TIM8EN - description: TIM8 Timer clock enable - bit_offset: 13 - bit_size: 1 - - name: USART1EN - description: USART1 clock enable - bit_offset: 14 - bit_size: 1 - - name: SPI4EN - description: SPI4 clock enable - bit_offset: 15 - bit_size: 1 - - name: TIM15EN - description: TIM15 timer clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: TIM16 timer clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: TIM17 timer clock enable - bit_offset: 18 - bit_size: 1 - - name: TIM19EN - description: TIM19 timer clock enable - bit_offset: 19 - bit_size: 1 - - name: TIM20EN - description: TIM20 timer clock enable - bit_offset: 20 - bit_size: 1 - - name: DBGMCUEN - description: MCU debug module clock enable - bit_offset: 22 - bit_size: 1 - - name: SDADC1EN - description: SDADC1 (Sigma Delta ADC 1) clock enable - bit_offset: 24 - bit_size: 1 - - name: SDADC2EN - description: SDADC2 (Sigma Delta ADC 2) clock enable - bit_offset: 25 - bit_size: 1 - - name: SDADC3EN - description: SDADC3 (Sigma Delta ADC 3) clock enable - bit_offset: 26 - bit_size: 1 - - name: HRTIM1EN - description: High Resolution Timer 1 clock enable - bit_offset: 29 - bit_size: 1 + - name: SYSCFGEN + description: SYSCFG clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM1EN + description: TIM1 Timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable + bit_offset: 12 + bit_size: 1 + - name: TIM8EN + description: TIM8 Timer clock enable + bit_offset: 13 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI4EN + description: SPI4 clock enable + bit_offset: 15 + bit_size: 1 + - name: TIM15EN + description: TIM15 timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: TIM19EN + description: TIM19 timer clock enable + bit_offset: 19 + bit_size: 1 + - name: TIM20EN + description: TIM20 timer clock enable + bit_offset: 20 + bit_size: 1 + - name: DBGMCUEN + description: MCU debug module clock enable + bit_offset: 22 + bit_size: 1 + - name: HRTIM1EN + description: High Resolution Timer 1 clock enable + bit_offset: 29 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register (RCC_APB2RSTR) fields: - - name: SYSCFGRST - description: SYSCFG and COMP reset - bit_offset: 0 - bit_size: 1 - - name: ADCRST - description: ADC interface reset - bit_offset: 9 - bit_size: 1 - - name: TIM1RST - description: TIM1 timer reset - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: SPI 1 reset - bit_offset: 12 - bit_size: 1 - - name: TIM8RST - description: TIM8 timer reset - bit_offset: 13 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 14 - bit_size: 1 - - name: SPI4RST - description: SPI4 reset - bit_offset: 15 - bit_size: 1 - - name: TIM15RST - description: TIM15 timer reset - bit_offset: 16 - bit_size: 1 - - name: TIM16RST - description: TIM16 timer reset - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: TIM17 timer reset - bit_offset: 18 - bit_size: 1 - - name: TIM19RST - description: TIM19 timer reset - bit_offset: 19 - bit_size: 1 - - name: TIM20RST - description: TIM20 timer reset - bit_offset: 20 - bit_size: 1 - - name: SDADC1RST - description: SDADC1 (Sigma delta ADC 1) reset - bit_offset: 24 - bit_size: 1 - - name: SDADC2RST - description: SDADC2 (Sigma delta ADC 2) reset - bit_offset: 25 - bit_size: 1 - - name: SDADC3RST - description: SDADC3 (Sigma delta ADC 3) reset - bit_offset: 26 - bit_size: 1 - - name: HRTIM1RST - description: High Resolution Timer1 reset - bit_offset: 29 - bit_size: 1 + - name: SYSCFGRST + description: SYSCFG and COMP reset + bit_offset: 0 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: TIM8RST + description: TIM8 timer reset + bit_offset: 13 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: SPI4RST + description: SPI4 reset + bit_offset: 15 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: TIM19RST + description: TIM19 timer reset + bit_offset: 19 + bit_size: 1 + - name: TIM20RST + description: TIM20 timer reset + bit_offset: 20 + bit_size: 1 + - name: DBGMCURST + description: Debug MCU reset + bit_offset: 22 + bit_size: 1 + - name: HRTIM1RST + description: High Resolution Timer1 reset + bit_offset: 29 + bit_size: 1 fieldset/BDCR: description: Backup domain control register (RCC_BDCR) fields: - - name: LSEON - description: External Low Speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: External Low Speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: External Low Speed oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: LSEDRV - description: LSE oscillator drive capability - bit_offset: 3 - bit_size: 2 - enum: LSEDRV - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: Backup domain software reset - bit_offset: 16 - bit_size: 1 + - name: LSEON + description: External Low Speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External Low Speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: External Low Speed oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: LSE oscillator drive capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 fieldset/CFGR: description: Clock configuration register (RCC_CFGR) fields: - - name: SW - description: System clock Switch - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: System Clock Switch Status - bit_offset: 2 - bit_size: 2 - enum: SWS - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - enum: HPRE - - name: PPRE1 - description: APB Low speed prescaler (APB1) - bit_offset: 8 - bit_size: 3 - enum: PPRE - - name: PPRE2 - description: APB high speed prescaler (APB2) - bit_offset: 11 - bit_size: 3 - enum: PPRE - - name: ADCPRE - description: ADC prescaler - bit_offset: 14 - bit_size: 2 - enum: ADCPRE - - name: PLLSRC - description: PLL entry clock source - bit_offset: 15 - bit_size: 2 - enum: PLLSRC - - name: PLLXTPRE - description: HSE divider for PLL entry - bit_offset: 17 - bit_size: 1 - enum: PLLXTPRE - - name: PLLMUL - description: PLL Multiplication Factor - bit_offset: 18 - bit_size: 4 - enum: PLLMUL - - name: USBPRE - description: USB prescaler - bit_offset: 22 - bit_size: 1 - enum: USBPRE - - name: I2SSRC - description: I2S external clock source selection - bit_offset: 23 - bit_size: 1 - enum: ISSRC - - name: MCO - description: Microcontroller clock output - bit_offset: 24 - bit_size: 3 - enum: MCO - - name: SDPRE - description: SDADC prescaler - bit_offset: 27 - bit_size: 5 - enum: SDPRE - - name: MCOPRE - description: Microcontroller Clock Output Prescaler - bit_offset: 28 - bit_size: 3 - enum: MCOPRE - - name: PLLNODIV - description: Do not divide PLL to MCO - bit_offset: 31 - bit_size: 1 - enum: PLLNODIV + - name: SW + description: System clock Switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System Clock Switch Status + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: ADCPRE + description: ADC prescaler + bit_offset: 14 + bit_size: 2 + enum: ADCPRE + - name: PLLSRC + description: PLL entry clock source + bit_offset: 15 + bit_size: 2 + enum: PLLSRC + - name: PLLXTPRE + description: HSE divider for PLL entry + bit_offset: 17 + bit_size: 1 + enum: PLLXTPRE + - name: PLLMUL + description: PLL Multiplication Factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: USBPRE + description: USB prescaler + bit_offset: 22 + bit_size: 1 + enum: USBPRE + - name: I2SSRC + description: I2S external clock source selection + bit_offset: 23 + bit_size: 1 + enum: ISSRC + - name: MCO + description: Microcontroller clock output + bit_offset: 24 + bit_size: 3 + enum: MCO + - name: SDPRE + description: SDADC prescaler + bit_offset: 27 + bit_size: 5 + enum: SDPRE + - name: MCOPRE + description: Microcontroller Clock Output Prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE + - name: PLLNODIV + description: Do not divide PLL to MCO + bit_offset: 31 + bit_size: 1 + enum: PLLNODIV fieldset/CFGR2: description: Clock configuration register 2 fields: - - name: PREDIV - description: PREDIV division factor - bit_offset: 0 - bit_size: 4 - enum: PREDIV - - name: ADC12PRES - description: ADC1 and ADC2 prescaler - bit_offset: 4 - bit_size: 5 - enum: ADCPRES - - name: ADC1PRES - description: ADC1 prescaler - bit_offset: 4 - bit_size: 5 - enum: ADCPRES - - name: ADC34PRES - description: ADC3 and ADC4 prescaler - bit_offset: 9 - bit_size: 5 - enum: ADCPRES + - name: PREDIV + description: PREDIV division factor + bit_offset: 0 + bit_size: 4 + enum: PREDIV + - name: ADC12PRES + description: ADC1 and ADC2 prescaler + bit_offset: 4 + bit_size: 5 + enum: ADCPRES + - name: ADC1PRES + description: ADC1 prescaler + bit_offset: 4 + bit_size: 5 + enum: ADCPRES + - name: ADC34PRES + description: ADC3 and ADC4 prescaler + bit_offset: 9 + bit_size: 5 + enum: ADCPRES fieldset/CFGR3: description: Clock configuration register 3 fields: - - name: USART1SW - description: USART1 clock source selection - bit_offset: 0 - bit_size: 2 - enum: USARTSW - - name: I2C1SW - description: I2C1 clock source selection - bit_offset: 4 - bit_size: 1 - enum: ICSW - - name: I2C2SW - description: I2C2 clock source selection - bit_offset: 5 - bit_size: 1 - enum: ICSW - - name: CECSW - description: HDMI CEC clock source selection - bit_offset: 6 - bit_size: 1 - enum: CECSW - - name: I2C3SW - description: I2C3 clock source selection - bit_offset: 6 - bit_size: 1 - enum: ICSW - - name: TIM1SW - description: Timer1 clock source selection - bit_offset: 8 - bit_size: 1 - enum: TIMSW - - name: TIM8SW - description: Timer8 clock source selection - bit_offset: 9 - bit_size: 1 - enum: TIMSW - - name: TIM15SW - description: Timer15 clock source selection - bit_offset: 10 - bit_size: 1 - enum: TIMSW - - name: TIM16SW - description: Timer16 clock source selection - bit_offset: 11 - bit_size: 1 - enum: TIMSW - - name: HRTIM1SW - description: Hrtim1 clock source selection - bit_offset: 12 - bit_size: 1 - enum: TIMSW - - name: TIM17SW - description: Timer17 clock source selection - bit_offset: 13 - bit_size: 1 - enum: TIMSW - - name: TIM20SW - description: Timer20 clock source selection - bit_offset: 15 - bit_size: 1 - enum: TIMSW - - name: USART2SW - description: USART2 clock source selection - bit_offset: 16 - bit_size: 2 - enum: USARTSW - - name: USART3SW - description: USART3 clock source selection - bit_offset: 18 - bit_size: 2 - enum: USARTSW - - name: UART4SW - description: UART4 clock source selection - bit_offset: 20 - bit_size: 2 - enum: USARTSW - - name: UART5SW - description: UART5 clock source selection - bit_offset: 22 - bit_size: 2 - enum: USARTSW - - name: TIM2SW - description: Timer2 clock source selection - bit_offset: 24 - bit_size: 1 - enum: TIMSW - - name: TIM34SW - description: Timer34 clock source selection - bit_offset: 25 - bit_size: 1 - enum: TIMSW + - name: USART1SW + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + enum: USARTSW + - name: I2C1SW + description: I2C1 clock source selection + bit_offset: 4 + bit_size: 1 + enum: ICSW + - name: I2C2SW + description: I2C2 clock source selection + bit_offset: 5 + bit_size: 1 + enum: ICSW + - name: CECSW + description: HDMI CEC clock source selection + bit_offset: 6 + bit_size: 1 + enum: CECSW + - name: I2C3SW + description: I2C3 clock source selection + bit_offset: 6 + bit_size: 1 + enum: ICSW + - name: TIM1SW + description: Timer1 clock source selection + bit_offset: 8 + bit_size: 1 + enum: TIMSW + - name: TIM8SW + description: Timer8 clock source selection + bit_offset: 9 + bit_size: 1 + enum: TIMSW + - name: TIM15SW + description: Timer15 clock source selection + bit_offset: 10 + bit_size: 1 + enum: TIMSW + - name: TIM16SW + description: Timer16 clock source selection + bit_offset: 11 + bit_size: 1 + enum: TIMSW + - name: HRTIM1SW + description: Hrtim1 clock source selection + bit_offset: 12 + bit_size: 1 + enum: TIMSW + - name: TIM17SW + description: Timer17 clock source selection + bit_offset: 13 + bit_size: 1 + enum: TIMSW + - name: TIM20SW + description: Timer20 clock source selection + bit_offset: 15 + bit_size: 1 + enum: TIMSW + - name: USART2SW + description: USART2 clock source selection + bit_offset: 16 + bit_size: 2 + enum: USARTSW + - name: USART3SW + description: USART3 clock source selection + bit_offset: 18 + bit_size: 2 + enum: USARTSW + - name: UART4SW + description: UART4 clock source selection + bit_offset: 20 + bit_size: 2 + enum: USARTSW + - name: UART5SW + description: UART5 clock source selection + bit_offset: 22 + bit_size: 2 + enum: USARTSW + - name: TIM2SW + description: Timer2 clock source selection + bit_offset: 24 + bit_size: 1 + enum: TIMSW + - name: TIM34SW + description: Timer34 clock source selection + bit_offset: 25 + bit_size: 1 + enum: TIMSW fieldset/CIR: description: Clock interrupt register (RCC_CIR) fields: - - name: LSIRDYF - description: LSI Ready Interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE Ready Interrupt flag - bit_offset: 1 - bit_size: 1 - - name: HSIRDYF - description: HSI Ready Interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSERDYF - description: HSE Ready Interrupt flag - bit_offset: 3 - bit_size: 1 - - name: PLLRDYF - description: PLL Ready Interrupt flag - bit_offset: 4 - bit_size: 1 - - name: CSSF - description: Clock Security System Interrupt flag - bit_offset: 7 - bit_size: 1 - - name: LSIRDYIE - description: LSI Ready Interrupt Enable - bit_offset: 8 - bit_size: 1 - - name: LSERDYIE - description: LSE Ready Interrupt Enable - bit_offset: 9 - bit_size: 1 - - name: HSIRDYIE - description: HSI Ready Interrupt Enable - bit_offset: 10 - bit_size: 1 - - name: HSERDYIE - description: HSE Ready Interrupt Enable - bit_offset: 11 - bit_size: 1 - - name: PLLRDYIE - description: PLL Ready Interrupt Enable - bit_offset: 12 - bit_size: 1 - - name: LSIRDYC - description: LSI Ready Interrupt Clear - bit_offset: 16 - bit_size: 1 - - name: LSERDYC - description: LSE Ready Interrupt Clear - bit_offset: 17 - bit_size: 1 - - name: HSIRDYC - description: HSI Ready Interrupt Clear - bit_offset: 18 - bit_size: 1 - - name: HSERDYC - description: HSE Ready Interrupt Clear - bit_offset: 19 - bit_size: 1 - - name: PLLRDYC - description: PLL Ready Interrupt Clear - bit_offset: 20 - bit_size: 1 - - name: CSSC - description: Clock security system interrupt clear - bit_offset: 23 - bit_size: 1 + - name: LSIRDYF + description: LSI Ready Interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE Ready Interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI Ready Interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE Ready Interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: PLL Ready Interrupt flag + bit_offset: 4 + bit_size: 1 + - name: CSSF + description: Clock Security System Interrupt flag + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI Ready Interrupt Enable + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE Ready Interrupt Enable + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI Ready Interrupt Enable + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE Ready Interrupt Enable + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: PLL Ready Interrupt Enable + bit_offset: 12 + bit_size: 1 + - name: LSIRDYC + description: LSI Ready Interrupt Clear + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE Ready Interrupt Clear + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI Ready Interrupt Clear + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE Ready Interrupt Clear + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: PLL Ready Interrupt Clear + bit_offset: 20 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 fieldset/CR: description: Clock control register fields: - - name: HSION - description: Internal High Speed clock enable - bit_offset: 0 - bit_size: 1 - - name: HSIRDY - description: Internal High Speed clock ready flag - bit_offset: 1 - bit_size: 1 - - name: HSITRIM - description: Internal High Speed clock trimming - bit_offset: 3 - bit_size: 5 - - name: HSICAL - description: Internal High Speed clock Calibration - bit_offset: 8 - bit_size: 8 - - name: HSEON - description: External High Speed clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: External High Speed clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: External High Speed clock Bypass - bit_offset: 18 - bit_size: 1 - - name: CSSON - description: Clock Security System enable - bit_offset: 19 - bit_size: 1 - - name: PLLON - description: PLL enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: PLL clock ready flag - bit_offset: 25 - bit_size: 1 + - name: HSION + description: Internal High Speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal High Speed clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSITRIM + description: Internal High Speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal High Speed clock Calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: External High Speed clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: External High Speed clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: External High Speed clock Bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 fieldset/CSR: description: Control/status register (RCC_CSR) fields: - - name: LSION - description: Internal low speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: Internal low speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: V18PWRRSTF - description: Reset flag of the 1.8 V domain - bit_offset: 23 - bit_size: 1 - - name: RMVF - description: Remove reset flag - bit_offset: 24 - bit_size: 1 - - name: OBLRSTF - description: Option byte loader reset flag - bit_offset: 25 - bit_size: 1 - - name: PINRSTF - description: PIN reset flag - bit_offset: 26 - bit_size: 1 - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: Independent watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSION + description: Internal low speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: V18PWRRSTF + description: Reset flag of the 1.8 V domain + bit_offset: 23 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 enum/ADCPRE: bit_size: 2 variants: - - name: Div2 - description: PCLK divided by 2 - value: 0 - - name: Div4 - description: PCLK divided by 4 - value: 1 - - name: Div6 - description: PCLK divided by 6 - value: 2 - - name: Div8 - description: PCLK divided by 8 - value: 3 + - name: Div2 + description: PCLK divided by 2 + value: 0 + - name: Div4 + description: PCLK divided by 4 + value: 1 + - name: Div6 + description: PCLK divided by 6 + value: 2 + - name: Div8 + description: PCLK divided by 8 + value: 3 enum/ADCPRES: bit_size: 5 variants: - - name: NoClock - description: No clock - value: 0 - - name: Div1 - description: PLL clock not divided - value: 16 - - name: Div2 - description: PLL clock divided by 2 - value: 17 - - name: Div4 - description: PLL clock divided by 4 - value: 18 - - name: Div6 - description: PLL clock divided by 6 - value: 19 - - name: Div8 - description: PLL clock divided by 8 - value: 20 - - name: Div10 - description: PLL clock divided by 10 - value: 21 - - name: Div12 - description: PLL clock divided by 12 - value: 22 - - name: Div16 - description: PLL clock divided by 16 - value: 23 - - name: Div32 - description: PLL clock divided by 32 - value: 24 - - name: Div64 - description: PLL clock divided by 64 - value: 25 - - name: Div128 - description: PLL clock divided by 128 - value: 26 - - name: Div256 - description: PLL clock divided by 256 - value: 27 + - name: NoClock + description: No clock + value: 0 + - name: Div1 + description: PLL clock not divided + value: 16 + - name: Div2 + description: PLL clock divided by 2 + value: 17 + - name: Div4 + description: PLL clock divided by 4 + value: 18 + - name: Div6 + description: PLL clock divided by 6 + value: 19 + - name: Div8 + description: PLL clock divided by 8 + value: 20 + - name: Div10 + description: PLL clock divided by 10 + value: 21 + - name: Div12 + description: PLL clock divided by 12 + value: 22 + - name: Div16 + description: PLL clock divided by 16 + value: 23 + - name: Div32 + description: PLL clock divided by 32 + value: 24 + - name: Div64 + description: PLL clock divided by 64 + value: 25 + - name: Div128 + description: PLL clock divided by 128 + value: 26 + - name: Div256 + description: PLL clock divided by 256 + value: 27 enum/CECSW: bit_size: 1 variants: - - name: HSI_Div244 - description: HSI clock divided by 244 selected as CEC clock source - value: 0 - - name: LSE - description: LSE clock selected as CEC clock source - value: 1 + - name: HSI_Div244 + description: HSI clock divided by 244 selected as CEC clock source + value: 0 + - name: LSE + description: LSE clock selected as CEC clock source + value: 1 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: SYSCLK not divided - value: 0 - - name: Div2 - description: SYSCLK divided by 2 - value: 8 - - name: Div4 - description: SYSCLK divided by 4 - value: 9 - - name: Div8 - description: SYSCLK divided by 8 - value: 10 - - name: Div16 - description: SYSCLK divided by 16 - value: 11 - - name: Div64 - description: SYSCLK divided by 64 - value: 12 - - name: Div128 - description: SYSCLK divided by 128 - value: 13 - - name: Div256 - description: SYSCLK divided by 256 - value: 14 - - name: Div512 - description: SYSCLK divided by 512 - value: 15 + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 enum/ICSW: bit_size: 1 variants: - - name: HSI - description: HSI clock selected as I2C clock source - value: 0 - - name: SYSCLK - description: SYSCLK clock selected as I2C clock source - value: 1 + - name: HSI + description: HSI clock selected as I2C clock source + value: 0 + - name: SYSCLK + description: SYSCLK clock selected as I2C clock source + value: 1 enum/ISSRC: bit_size: 1 variants: - - name: SYSCLK - description: System clock used as I2S clock source - value: 0 - - name: CKIN - description: External clock mapped on the I2S_CKIN pin used as I2S clock source - value: 1 + - name: SYSCLK + description: System clock used as I2S clock source + value: 0 + - name: CKIN + description: External clock mapped on the I2S_CKIN pin used as I2S clock source + value: 1 enum/LSEDRV: bit_size: 2 variants: - - name: Low - description: Low drive capacity - value: 0 - - name: MediumHigh - description: Medium-high drive capacity - value: 1 - - name: MediumLow - description: Medium-low drive capacity - value: 2 - - name: High - description: High drive capacity - value: 3 + - name: Low + description: Low drive capacity + value: 0 + - name: MediumHigh + description: Medium-high drive capacity + value: 1 + - name: MediumLow + description: Medium-low drive capacity + value: 2 + - name: High + description: High drive capacity + value: 3 enum/MCO: bit_size: 3 variants: - - name: NoMCO - description: "MCO output disabled, no clock on MCO" - value: 0 - - name: LSI - description: Internal low speed (LSI) oscillator clock selected - value: 2 - - name: LSE - description: External low speed (LSE) oscillator clock selected - value: 3 - - name: SYSCLK - description: System clock selected - value: 4 - - name: HSI - description: Internal RC 8 MHz (HSI) oscillator clock selected - value: 5 - - name: HSE - description: External 4-32 MHz (HSE) oscillator clock selected - value: 6 - - name: PLL - description: "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)" - value: 7 + - name: NoMCO + description: MCO output disabled, no clock on MCO + value: 0 + - name: LSI + description: Internal low speed (LSI) oscillator clock selected + value: 2 + - name: LSE + description: External low speed (LSE) oscillator clock selected + value: 3 + - name: SYSCLK + description: System clock selected + value: 4 + - name: HSI + description: Internal RC 8 MHz (HSI) oscillator clock selected + value: 5 + - name: HSE + description: External 4-32 MHz (HSE) oscillator clock selected + value: 6 + - name: PLL + description: PLL clock selected (divided by 1 or 2, depending en PLLNODIV) + value: 7 enum/MCOPRE: bit_size: 3 variants: - - name: Div1 - description: MCO is divided by 1 - value: 0 - - name: Div2 - description: MCO is divided by 2 - value: 1 - - name: Div4 - description: MCO is divided by 4 - value: 2 - - name: Div8 - description: MCO is divided by 8 - value: 3 - - name: Div16 - description: MCO is divided by 16 - value: 4 - - name: Div32 - description: MCO is divided by 32 - value: 5 - - name: Div64 - description: MCO is divided by 64 - value: 6 - - name: Div128 - description: MCO is divided by 128 - value: 7 + - name: Div1 + description: MCO is divided by 1 + value: 0 + - name: Div2 + description: MCO is divided by 2 + value: 1 + - name: Div4 + description: MCO is divided by 4 + value: 2 + - name: Div8 + description: MCO is divided by 8 + value: 3 + - name: Div16 + description: MCO is divided by 16 + value: 4 + - name: Div32 + description: MCO is divided by 32 + value: 5 + - name: Div64 + description: MCO is divided by 64 + value: 6 + - name: Div128 + description: MCO is divided by 128 + value: 7 enum/PLLMUL: bit_size: 4 variants: - - name: Mul2 - description: PLL input clock x2 - value: 0 - - name: Mul3 - description: PLL input clock x3 - value: 1 - - name: Mul4 - description: PLL input clock x4 - value: 2 - - name: Mul5 - description: PLL input clock x5 - value: 3 - - name: Mul6 - description: PLL input clock x6 - value: 4 - - name: Mul7 - description: PLL input clock x7 - value: 5 - - name: Mul8 - description: PLL input clock x8 - value: 6 - - name: Mul9 - description: PLL input clock x9 - value: 7 - - name: Mul10 - description: PLL input clock x10 - value: 8 - - name: Mul11 - description: PLL input clock x11 - value: 9 - - name: Mul12 - description: PLL input clock x12 - value: 10 - - name: Mul13 - description: PLL input clock x13 - value: 11 - - name: Mul14 - description: PLL input clock x14 - value: 12 - - name: Mul15 - description: PLL input clock x15 - value: 13 - - name: Mul16 - description: PLL input clock x16 - value: 14 - - name: Mul16x - description: PLL input clock x16 - value: 15 + - name: Mul2 + description: PLL input clock x2 + value: 0 + - name: Mul3 + description: PLL input clock x3 + value: 1 + - name: Mul4 + description: PLL input clock x4 + value: 2 + - name: Mul5 + description: PLL input clock x5 + value: 3 + - name: Mul6 + description: PLL input clock x6 + value: 4 + - name: Mul7 + description: PLL input clock x7 + value: 5 + - name: Mul8 + description: PLL input clock x8 + value: 6 + - name: Mul9 + description: PLL input clock x9 + value: 7 + - name: Mul10 + description: PLL input clock x10 + value: 8 + - name: Mul11 + description: PLL input clock x11 + value: 9 + - name: Mul12 + description: PLL input clock x12 + value: 10 + - name: Mul13 + description: PLL input clock x13 + value: 11 + - name: Mul14 + description: PLL input clock x14 + value: 12 + - name: Mul15 + description: PLL input clock x15 + value: 13 + - name: Mul16 + description: PLL input clock x16 + value: 14 + - name: Mul16x + description: PLL input clock x16 + value: 15 enum/PLLNODIV: bit_size: 1 variants: - - name: Div2 - description: PLL is divided by 2 for MCO - value: 0 - - name: Div1 - description: PLL is not divided for MCO - value: 1 + - name: Div2 + description: PLL is divided by 2 for MCO + value: 0 + - name: Div1 + description: PLL is not divided for MCO + value: 1 enum/PLLSRC: bit_size: 2 variants: - - name: HSI_Div2 - description: HSI divided by 2 selected as PLL input clock - value: 0 - - name: HSI_Div_PREDIV - description: HSI divided by PREDIV selected as PLL input clock - value: 1 - - name: HSE_Div_PREDIV - description: HSE divided by PREDIV selected as PLL input clock - value: 2 + - name: HSI_Div2 + description: HSI divided by 2 selected as PLL input clock + value: 0 + - name: HSI_Div_PREDIV + description: HSI divided by PREDIV selected as PLL input clock + value: 1 + - name: HSE_Div_PREDIV + description: HSE divided by PREDIV selected as PLL input clock + value: 2 enum/PLLXTPRE: bit_size: 1 variants: - - name: Div1 - description: HSE clock not divided - value: 0 - - name: Div2 - description: HSE clock divided by 2 - value: 1 + - name: Div1 + description: HSE clock not divided + value: 0 + - name: Div2 + description: HSE clock divided by 2 + value: 1 enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK divided by 2 - value: 4 - - name: Div4 - description: HCLK divided by 4 - value: 5 - - name: Div8 - description: HCLK divided by 8 - value: 6 - - name: Div16 - description: HCLK divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 enum/PREDIV: bit_size: 4 variants: - - name: Div1 - description: PREDIV input clock not divided - value: 0 - - name: Div2 - description: PREDIV input clock divided by 2 - value: 1 - - name: Div3 - description: PREDIV input clock divided by 3 - value: 2 - - name: Div4 - description: PREDIV input clock divided by 4 - value: 3 - - name: Div5 - description: PREDIV input clock divided by 5 - value: 4 - - name: Div6 - description: PREDIV input clock divided by 6 - value: 5 - - name: Div7 - description: PREDIV input clock divided by 7 - value: 6 - - name: Div8 - description: PREDIV input clock divided by 8 - value: 7 - - name: Div9 - description: PREDIV input clock divided by 9 - value: 8 - - name: Div10 - description: PREDIV input clock divided by 10 - value: 9 - - name: Div11 - description: PREDIV input clock divided by 11 - value: 10 - - name: Div12 - description: PREDIV input clock divided by 12 - value: 11 - - name: Div13 - description: PREDIV input clock divided by 13 - value: 12 - - name: Div14 - description: PREDIV input clock divided by 14 - value: 13 - - name: Div15 - description: PREDIV input clock divided by 15 - value: 14 - - name: Div16 - description: PREDIV input clock divided by 16 - value: 15 + - name: Div1 + description: PREDIV input clock not divided + value: 0 + - name: Div2 + description: PREDIV input clock divided by 2 + value: 1 + - name: Div3 + description: PREDIV input clock divided by 3 + value: 2 + - name: Div4 + description: PREDIV input clock divided by 4 + value: 3 + - name: Div5 + description: PREDIV input clock divided by 5 + value: 4 + - name: Div6 + description: PREDIV input clock divided by 6 + value: 5 + - name: Div7 + description: PREDIV input clock divided by 7 + value: 6 + - name: Div8 + description: PREDIV input clock divided by 8 + value: 7 + - name: Div9 + description: PREDIV input clock divided by 9 + value: 8 + - name: Div10 + description: PREDIV input clock divided by 10 + value: 9 + - name: Div11 + description: PREDIV input clock divided by 11 + value: 10 + - name: Div12 + description: PREDIV input clock divided by 12 + value: 11 + - name: Div13 + description: PREDIV input clock divided by 13 + value: 12 + - name: Div14 + description: PREDIV input clock divided by 14 + value: 13 + - name: Div15 + description: PREDIV input clock divided by 15 + value: 14 + - name: Div16 + description: PREDIV input clock divided by 16 + value: 15 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: HSE oscillator clock divided by a prescaler used as RTC clock - value: 3 + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 enum/SDPRE: bit_size: 5 variants: - - name: Div2 - description: SYSCLK divided by 2 - value: 0 - - name: Div4 - description: SYSCLK divided by 4 - value: 17 - - name: Div6 - description: SYSCLK divided by 6 - value: 18 - - name: Div8 - description: SYSCLK divided by 8 - value: 19 - - name: Div10 - description: SYSCLK divided by 10 - value: 20 - - name: Div12 - description: SYSCLK divided by 12 - value: 21 - - name: Div14 - description: SYSCLK divided by 14 - value: 22 - - name: Div16 - description: SYSCLK divided by 16 - value: 23 - - name: Div20 - description: SYSCLK divided by 20 - value: 24 - - name: Div24 - description: SYSCLK divided by 24 - value: 25 - - name: Div28 - description: SYSCLK divided by 28 - value: 26 - - name: Div32 - description: SYSCLK divided by 32 - value: 27 - - name: Div36 - description: SYSCLK divided by 36 - value: 28 - - name: Div40 - description: SYSCLK divided by 40 - value: 29 - - name: Div44 - description: SYSCLK divided by 44 - value: 30 - - name: Div48 - description: SYSCLK divided by 48 - value: 31 + - name: Div2 + description: SYSCLK divided by 2 + value: 0 + - name: Div4 + description: SYSCLK divided by 4 + value: 17 + - name: Div6 + description: SYSCLK divided by 6 + value: 18 + - name: Div8 + description: SYSCLK divided by 8 + value: 19 + - name: Div10 + description: SYSCLK divided by 10 + value: 20 + - name: Div12 + description: SYSCLK divided by 12 + value: 21 + - name: Div14 + description: SYSCLK divided by 14 + value: 22 + - name: Div16 + description: SYSCLK divided by 16 + value: 23 + - name: Div20 + description: SYSCLK divided by 20 + value: 24 + - name: Div24 + description: SYSCLK divided by 24 + value: 25 + - name: Div28 + description: SYSCLK divided by 28 + value: 26 + - name: Div32 + description: SYSCLK divided by 32 + value: 27 + - name: Div36 + description: SYSCLK divided by 36 + value: 28 + - name: Div40 + description: SYSCLK divided by 40 + value: 29 + - name: Div44 + description: SYSCLK divided by 44 + value: 30 + - name: Div48 + description: SYSCLK divided by 48 + value: 31 enum/SW: bit_size: 2 variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: HSE - description: HSE selected as system clock - value: 1 - - name: PLL - description: PLL selected as system clock - value: 2 -enum/SWS: - bit_size: 2 - variants: - - name: HSI - description: HSI oscillator used as system clock - value: 0 - - name: HSE - description: HSE oscillator used as system clock - value: 1 - - name: PLL - description: PLL used as system clock - value: 2 + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL + description: PLL used as system clock + value: 2 enum/TIMSW: bit_size: 1 variants: - - name: PCLK2 - description: PCLK2 clock (doubled frequency when prescaled) - value: 0 - - name: PLL - description: PLL vco output (running up to 144 MHz) - value: 1 + - name: PCLK2 + description: PCLK2 clock (doubled frequency when prescaled) + value: 0 + - name: PLL + description: PLL vco output (running up to 144 MHz) + value: 1 enum/USARTSW: bit_size: 2 variants: - - name: PCLK - description: PCLK selected as USART clock source - value: 0 - - name: SYSCLK - description: SYSCLK selected as USART clock source - value: 1 - - name: LSE - description: LSE selected as USART clock source - value: 2 - - name: HSI - description: HSI selected as USART clock source - value: 3 + - name: PCLK + description: PCLK selected as USART clock source + value: 0 + - name: SYSCLK + description: SYSCLK selected as USART clock source + value: 1 + - name: LSE + description: LSE selected as USART clock source + value: 2 + - name: HSI + description: HSI selected as USART clock source + value: 3 enum/USBPRE: bit_size: 1 variants: - - name: DIV1_5 - description: PLL clock is divided by 1.5 - value: 0 - - name: DIV1 - description: PLL clock is not divided - value: 1 + - name: Div1_5 + description: PLL clock is divided by 1.5 + value: 0 + - name: Div1 + description: PLL clock is not divided + value: 1 diff --git a/data/registers/rcc_f3_v2.yaml b/data/registers/rcc_f3_v2.yaml new file mode 100644 index 0000000..398a7ef --- /dev/null +++ b/data/registers/rcc_f3_v2.yaml @@ -0,0 +1,1258 @@ +block/RCC: + description: Reset and clock control + items: + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: CFGR + description: Clock configuration register (RCC_CFGR) + byte_offset: 4 + fieldset: CFGR + - name: CIR + description: Clock interrupt register (RCC_CIR) + byte_offset: 8 + fieldset: CIR + - name: APB2RSTR + description: APB2 peripheral reset register (RCC_APB2RSTR) + byte_offset: 12 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register (RCC_APB1RSTR) + byte_offset: 16 + fieldset: APB1RSTR + - name: AHBENR + description: AHB Peripheral Clock enable register (RCC_AHBENR) + byte_offset: 20 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register (RCC_APB2ENR) + byte_offset: 24 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register (RCC_APB1ENR) + byte_offset: 28 + fieldset: APB1ENR + - name: BDCR + description: Backup domain control register (RCC_BDCR) + byte_offset: 32 + fieldset: BDCR + - name: CSR + description: Control/status register (RCC_CSR) + byte_offset: 36 + fieldset: CSR + - name: AHBRSTR + description: AHB peripheral reset register + byte_offset: 40 + fieldset: AHBRSTR + - name: CFGR2 + description: Clock configuration register 2 + byte_offset: 44 + fieldset: CFGR2 + - name: CFGR3 + description: Clock configuration register 3 + byte_offset: 48 + fieldset: CFGR3 +fieldset/AHBENR: + description: AHB Peripheral Clock enable register (RCC_AHBENR) + fields: + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: SRAMEN + description: SRAM interface clock enable + bit_offset: 2 + bit_size: 1 + - name: FLASHEN + description: FLASH clock enable + bit_offset: 4 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOAEN + description: I/O port A clock enable + bit_offset: 17 + bit_size: 1 + - name: GPIOBEN + description: I/O port B clock enable + bit_offset: 18 + bit_size: 1 + - name: GPIOCEN + description: I/O port C clock enable + bit_offset: 19 + bit_size: 1 + - name: GPIODEN + description: I/O port D clock enable + bit_offset: 20 + bit_size: 1 + - name: GPIOEEN + description: I/O port E clock enable + bit_offset: 21 + bit_size: 1 + - name: GPIOFEN + description: I/O port F clock enable + bit_offset: 22 + bit_size: 1 + - name: TSCEN + description: Touch sensing controller clock enable + bit_offset: 24 + bit_size: 1 +fieldset/AHBRSTR: + description: AHB peripheral reset register + fields: + - name: GPIOARST + description: I/O port A reset + bit_offset: 17 + bit_size: 1 + - name: GPIOBRST + description: I/O port B reset + bit_offset: 18 + bit_size: 1 + - name: GPIOCRST + description: I/O port C reset + bit_offset: 19 + bit_size: 1 + - name: GPIODRST + description: I/O port D reset + bit_offset: 20 + bit_size: 1 + - name: GPIOERST + description: I/O port E reset + bit_offset: 21 + bit_size: 1 + - name: GPIOFRST + description: I/O port F reset + bit_offset: 22 + bit_size: 1 + - name: TSCRST + description: Touch sensing controller reset + bit_offset: 24 + bit_size: 1 +fieldset/APB1ENR: + description: APB1 peripheral clock enable register (RCC_APB1ENR) + fields: + - name: TIM2EN + description: Timer 2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: Timer 4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: Timer 5 clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: Timer 7 clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: Timer 12 clock enable + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: Timer 13 clock enable + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: Timer 14 clock enable + bit_offset: 8 + bit_size: 1 + - name: TIM18EN + description: Timer 18 clock enable + bit_offset: 9 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI 2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI 3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART 3 clock enable + bit_offset: 18 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C 2 clock enable + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: USB clock enable + bit_offset: 23 + bit_size: 1 + - name: CANEN + description: CAN clock enable + bit_offset: 25 + bit_size: 1 + - name: DAC2EN + description: DAC2 interface clock enable + bit_offset: 26 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: CECEN + description: HDMI CEC interface clock enable + bit_offset: 30 + bit_size: 1 +fieldset/APB1RSTR: + description: APB1 peripheral reset register (RCC_APB1RSTR) + fields: + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: Timer 14 reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: Timer 5 reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: Timer 6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: Timer 7 reset + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: Timer 12 reset + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: Timer 13 reset + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: Timer 14 reset + bit_offset: 8 + bit_size: 1 + - name: TIM18RST + description: Timer 18 reset + bit_offset: 9 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 reset + bit_offset: 18 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: USB reset + bit_offset: 23 + bit_size: 1 + - name: CANRST + description: CAN reset + bit_offset: 25 + bit_size: 1 + - name: DAC2RST + description: DAC2 interface reset + bit_offset: 26 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 + - name: CECRST + description: HDMI CEC reset + bit_offset: 30 + bit_size: 1 +fieldset/APB2ENR: + description: APB2 peripheral clock enable register (RCC_APB2ENR) + fields: + - name: SYSCFGEN + description: SYSCFG clock enable + bit_offset: 0 + bit_size: 1 + - name: ADCEN + description: ADC 1 interface clock enable + bit_offset: 9 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM15EN + description: TIM15 timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: TIM19EN + description: TIM19 timer clock enable + bit_offset: 19 + bit_size: 1 + - name: DBGMCUEN + description: MCU debug module clock enable + bit_offset: 22 + bit_size: 1 + - name: SDADC1EN + description: SDADC1 (Sigma Delta ADC 1) clock enable + bit_offset: 24 + bit_size: 1 + - name: SDADC2EN + description: SDADC2 (Sigma Delta ADC 2) clock enable + bit_offset: 25 + bit_size: 1 + - name: SDADC3EN + description: SDADC3 (Sigma Delta ADC 3) clock enable + bit_offset: 26 + bit_size: 1 +fieldset/APB2RSTR: + description: APB2 peripheral reset register (RCC_APB2RSTR) + fields: + - name: SYSCFGRST + description: SYSCFG and COMP reset + bit_offset: 0 + bit_size: 1 + - name: ADCRST + description: ADC interface reset + bit_offset: 9 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: TIM19RST + description: TIM19 timer reset + bit_offset: 19 + bit_size: 1 + - name: DBGMCURST + description: MCU debug module clock enable + bit_offset: 22 + bit_size: 1 + - name: SDADC1RST + description: SDADC1 (Sigma delta ADC 1) reset + bit_offset: 24 + bit_size: 1 + - name: SDADC2RST + description: SDADC2 (Sigma delta ADC 2) reset + bit_offset: 25 + bit_size: 1 + - name: SDADC3RST + description: SDADC3 (Sigma delta ADC 3) reset + bit_offset: 26 + bit_size: 1 +fieldset/BDCR: + description: Backup domain control register (RCC_BDCR) + fields: + - name: LSEON + description: External Low Speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External Low Speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: External Low Speed oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: LSE oscillator drive capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 +fieldset/CFGR: + description: Clock configuration register (RCC_CFGR) + fields: + - name: SW + description: System clock Switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System Clock Switch Status + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: ADCPRE + description: ADC prescaler + bit_offset: 14 + bit_size: 2 + enum: ADCPRE + - name: PLLSRC + description: PLL entry clock source + bit_offset: 15 + bit_size: 2 + enum: PLLSRC + - name: PLLXTPRE + description: HSE divider for PLL entry + bit_offset: 17 + bit_size: 1 + enum: PLLXTPRE + - name: PLLMUL + description: PLL Multiplication Factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: USBPRE + description: USB prescaler + bit_offset: 22 + bit_size: 1 + enum: USBPRE + - name: I2SSRC + description: I2S external clock source selection + bit_offset: 23 + bit_size: 1 + enum: ISSRC + - name: MCO + description: Microcontroller clock output + bit_offset: 24 + bit_size: 3 + enum: MCO + - name: SDPRE + description: SDADC prescaler + bit_offset: 27 + bit_size: 5 + enum: SDPRE + - name: MCOPRE + description: Microcontroller Clock Output Prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE + - name: PLLNODIV + description: Do not divide PLL to MCO + bit_offset: 31 + bit_size: 1 + enum: PLLNODIV +fieldset/CFGR2: + description: Clock configuration register 2 + fields: + - name: PREDIV + description: PREDIV division factor + bit_offset: 0 + bit_size: 4 + enum: PREDIV + - name: ADC12PRES + description: ADC1 and ADC2 prescaler + bit_offset: 4 + bit_size: 5 + enum: ADCPRES + - name: ADC1PRES + description: ADC1 prescaler + bit_offset: 4 + bit_size: 5 + enum: ADCPRES + - name: ADC34PRES + description: ADC3 and ADC4 prescaler + bit_offset: 9 + bit_size: 5 + enum: ADCPRES +fieldset/CFGR3: + description: Clock configuration register 3 + fields: + - name: USART1SW + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + enum: USARTSW + - name: I2C1SW + description: I2C1 clock source selection + bit_offset: 4 + bit_size: 1 + enum: ICSW + - name: I2C2SW + description: I2C2 clock source selection + bit_offset: 5 + bit_size: 1 + enum: ICSW + - name: CECSW + description: HDMI CEC clock source selection + bit_offset: 6 + bit_size: 1 + enum: CECSW + - name: I2C3SW + description: I2C3 clock source selection + bit_offset: 6 + bit_size: 1 + enum: ICSW + - name: TIM1SW + description: Timer1 clock source selection + bit_offset: 8 + bit_size: 1 + enum: TIMSW + - name: TIM8SW + description: Timer8 clock source selection + bit_offset: 9 + bit_size: 1 + enum: TIMSW + - name: TIM15SW + description: Timer15 clock source selection + bit_offset: 10 + bit_size: 1 + enum: TIMSW + - name: TIM16SW + description: Timer16 clock source selection + bit_offset: 11 + bit_size: 1 + enum: TIMSW + - name: HRTIM1SW + description: Hrtim1 clock source selection + bit_offset: 12 + bit_size: 1 + enum: TIMSW + - name: TIM17SW + description: Timer17 clock source selection + bit_offset: 13 + bit_size: 1 + enum: TIMSW + - name: TIM20SW + description: Timer20 clock source selection + bit_offset: 15 + bit_size: 1 + enum: TIMSW + - name: USART2SW + description: USART2 clock source selection + bit_offset: 16 + bit_size: 2 + enum: USARTSW + - name: USART3SW + description: USART3 clock source selection + bit_offset: 18 + bit_size: 2 + enum: USARTSW + - name: UART4SW + description: UART4 clock source selection + bit_offset: 20 + bit_size: 2 + enum: USARTSW + - name: UART5SW + description: UART5 clock source selection + bit_offset: 22 + bit_size: 2 + enum: USARTSW + - name: TIM2SW + description: Timer2 clock source selection + bit_offset: 24 + bit_size: 1 + enum: TIMSW + - name: TIM34SW + description: Timer34 clock source selection + bit_offset: 25 + bit_size: 1 + enum: TIMSW +fieldset/CIR: + description: Clock interrupt register (RCC_CIR) + fields: + - name: LSIRDYF + description: LSI Ready Interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE Ready Interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI Ready Interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE Ready Interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: PLL Ready Interrupt flag + bit_offset: 4 + bit_size: 1 + - name: CSSF + description: Clock Security System Interrupt flag + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI Ready Interrupt Enable + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE Ready Interrupt Enable + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI Ready Interrupt Enable + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE Ready Interrupt Enable + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: PLL Ready Interrupt Enable + bit_offset: 12 + bit_size: 1 + - name: LSIRDYC + description: LSI Ready Interrupt Clear + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE Ready Interrupt Clear + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI Ready Interrupt Clear + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE Ready Interrupt Clear + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: PLL Ready Interrupt Clear + bit_offset: 20 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 +fieldset/CR: + description: Clock control register + fields: + - name: HSION + description: Internal High Speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal High Speed clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSITRIM + description: Internal High Speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal High Speed clock Calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: External High Speed clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: External High Speed clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: External High Speed clock Bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 +fieldset/CSR: + description: Control/status register (RCC_CSR) + fields: + - name: LSION + description: Internal low speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: V18PWRRSTF + description: Reset flag of the 1.8 V domain + bit_offset: 23 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 +enum/ADCPRE: + bit_size: 2 + variants: + - name: Div2 + description: PCLK divided by 2 + value: 0 + - name: Div4 + description: PCLK divided by 4 + value: 1 + - name: Div6 + description: PCLK divided by 6 + value: 2 + - name: Div8 + description: PCLK divided by 8 + value: 3 +enum/ADCPRES: + bit_size: 5 + variants: + - name: NoClock + description: No clock + value: 0 + - name: Div1 + description: PLL clock not divided + value: 16 + - name: Div2 + description: PLL clock divided by 2 + value: 17 + - name: Div4 + description: PLL clock divided by 4 + value: 18 + - name: Div6 + description: PLL clock divided by 6 + value: 19 + - name: Div8 + description: PLL clock divided by 8 + value: 20 + - name: Div10 + description: PLL clock divided by 10 + value: 21 + - name: Div12 + description: PLL clock divided by 12 + value: 22 + - name: Div16 + description: PLL clock divided by 16 + value: 23 + - name: Div32 + description: PLL clock divided by 32 + value: 24 + - name: Div64 + description: PLL clock divided by 64 + value: 25 + - name: Div128 + description: PLL clock divided by 128 + value: 26 + - name: Div256 + description: PLL clock divided by 256 + value: 27 +enum/CECSW: + bit_size: 1 + variants: + - name: HSI_Div244 + description: HSI clock divided by 244 selected as CEC clock source + value: 0 + - name: LSE + description: LSE clock selected as CEC clock source + value: 1 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 +enum/ICSW: + bit_size: 1 + variants: + - name: HSI + description: HSI clock selected as I2C clock source + value: 0 + - name: SYSCLK + description: SYSCLK clock selected as I2C clock source + value: 1 +enum/ISSRC: + bit_size: 1 + variants: + - name: SYSCLK + description: System clock used as I2S clock source + value: 0 + - name: CKIN + description: External clock mapped on the I2S_CKIN pin used as I2S clock source + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Low + description: Low drive capacity + value: 0 + - name: MediumHigh + description: Medium-high drive capacity + value: 1 + - name: MediumLow + description: Medium-low drive capacity + value: 2 + - name: High + description: High drive capacity + value: 3 +enum/MCO: + bit_size: 3 + variants: + - name: NoMCO + description: MCO output disabled, no clock on MCO + value: 0 + - name: LSI + description: Internal low speed (LSI) oscillator clock selected + value: 2 + - name: LSE + description: External low speed (LSE) oscillator clock selected + value: 3 + - name: SYSCLK + description: System clock selected + value: 4 + - name: HSI + description: Internal RC 8 MHz (HSI) oscillator clock selected + value: 5 + - name: HSE + description: External 4-32 MHz (HSE) oscillator clock selected + value: 6 + - name: PLL + description: PLL clock selected (divided by 1 or 2, depending en PLLNODIV) + value: 7 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: MCO is divided by 1 + value: 0 + - name: Div2 + description: MCO is divided by 2 + value: 1 + - name: Div4 + description: MCO is divided by 4 + value: 2 + - name: Div8 + description: MCO is divided by 8 + value: 3 + - name: Div16 + description: MCO is divided by 16 + value: 4 + - name: Div32 + description: MCO is divided by 32 + value: 5 + - name: Div64 + description: MCO is divided by 64 + value: 6 + - name: Div128 + description: MCO is divided by 128 + value: 7 +enum/PLLMUL: + bit_size: 4 + variants: + - name: Mul2 + description: PLL input clock x2 + value: 0 + - name: Mul3 + description: PLL input clock x3 + value: 1 + - name: Mul4 + description: PLL input clock x4 + value: 2 + - name: Mul5 + description: PLL input clock x5 + value: 3 + - name: Mul6 + description: PLL input clock x6 + value: 4 + - name: Mul7 + description: PLL input clock x7 + value: 5 + - name: Mul8 + description: PLL input clock x8 + value: 6 + - name: Mul9 + description: PLL input clock x9 + value: 7 + - name: Mul10 + description: PLL input clock x10 + value: 8 + - name: Mul11 + description: PLL input clock x11 + value: 9 + - name: Mul12 + description: PLL input clock x12 + value: 10 + - name: Mul13 + description: PLL input clock x13 + value: 11 + - name: Mul14 + description: PLL input clock x14 + value: 12 + - name: Mul15 + description: PLL input clock x15 + value: 13 + - name: Mul16 + description: PLL input clock x16 + value: 14 + - name: Mul16x + description: PLL input clock x16 + value: 15 +enum/PLLNODIV: + bit_size: 1 + variants: + - name: Div2 + description: PLL is divided by 2 for MCO + value: 0 + - name: Div1 + description: PLL is not divided for MCO + value: 1 +enum/PLLSRC: + bit_size: 2 + variants: + - name: HSI_Div2 + description: HSI divided by 2 selected as PLL input clock + value: 0 + - name: HSI_Div_PREDIV + description: HSI divided by PREDIV selected as PLL input clock + value: 1 + - name: HSE_Div_PREDIV + description: HSE divided by PREDIV selected as PLL input clock + value: 2 +enum/PLLXTPRE: + bit_size: 1 + variants: + - name: Div1 + description: HSE clock not divided + value: 0 + - name: Div2 + description: HSE clock divided by 2 + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/PREDIV: + bit_size: 4 + variants: + - name: Div1 + description: PREDIV input clock not divided + value: 0 + - name: Div2 + description: PREDIV input clock divided by 2 + value: 1 + - name: Div3 + description: PREDIV input clock divided by 3 + value: 2 + - name: Div4 + description: PREDIV input clock divided by 4 + value: 3 + - name: Div5 + description: PREDIV input clock divided by 5 + value: 4 + - name: Div6 + description: PREDIV input clock divided by 6 + value: 5 + - name: Div7 + description: PREDIV input clock divided by 7 + value: 6 + - name: Div8 + description: PREDIV input clock divided by 8 + value: 7 + - name: Div9 + description: PREDIV input clock divided by 9 + value: 8 + - name: Div10 + description: PREDIV input clock divided by 10 + value: 9 + - name: Div11 + description: PREDIV input clock divided by 11 + value: 10 + - name: Div12 + description: PREDIV input clock divided by 12 + value: 11 + - name: Div13 + description: PREDIV input clock divided by 13 + value: 12 + - name: Div14 + description: PREDIV input clock divided by 14 + value: 13 + - name: Div15 + description: PREDIV input clock divided by 15 + value: 14 + - name: Div16 + description: PREDIV input clock divided by 16 + value: 15 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 +enum/SDPRE: + bit_size: 5 + variants: + - name: Div2 + description: SYSCLK divided by 2 + value: 0 + - name: Div4 + description: SYSCLK divided by 4 + value: 17 + - name: Div6 + description: SYSCLK divided by 6 + value: 18 + - name: Div8 + description: SYSCLK divided by 8 + value: 19 + - name: Div10 + description: SYSCLK divided by 10 + value: 20 + - name: Div12 + description: SYSCLK divided by 12 + value: 21 + - name: Div14 + description: SYSCLK divided by 14 + value: 22 + - name: Div16 + description: SYSCLK divided by 16 + value: 23 + - name: Div20 + description: SYSCLK divided by 20 + value: 24 + - name: Div24 + description: SYSCLK divided by 24 + value: 25 + - name: Div28 + description: SYSCLK divided by 28 + value: 26 + - name: Div32 + description: SYSCLK divided by 32 + value: 27 + - name: Div36 + description: SYSCLK divided by 36 + value: 28 + - name: Div40 + description: SYSCLK divided by 40 + value: 29 + - name: Div44 + description: SYSCLK divided by 44 + value: 30 + - name: Div48 + description: SYSCLK divided by 48 + value: 31 +enum/SW: + bit_size: 2 + variants: + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL + description: PLL used as system clock + value: 2 +enum/TIMSW: + bit_size: 1 + variants: + - name: PCLK2 + description: PCLK2 clock (doubled frequency when prescaled) + value: 0 + - name: PLL + description: PLL vco output (running up to 144 MHz) + value: 1 +enum/USARTSW: + bit_size: 2 + variants: + - name: PCLK + description: PCLK selected as USART clock source + value: 0 + - name: SYSCLK + description: SYSCLK selected as USART clock source + value: 1 + - name: LSE + description: LSE selected as USART clock source + value: 2 + - name: HSI + description: HSI selected as USART clock source + value: 3 +enum/USBPRE: + bit_size: 1 + variants: + - name: Div1_5 + description: PLL clock is divided by 1.5 + value: 0 + - name: Div1 + description: PLL clock is not divided + value: 1 diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index b9f138a..8b044dc 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -1,2548 +1,2535 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: clock control register - byte_offset: 0 - fieldset: CR - - name: PLLCFGR - description: PLL configuration register - byte_offset: 4 - fieldset: PLLCFGR - - name: CFGR - description: clock configuration register - byte_offset: 8 - fieldset: CFGR - - name: CIR - description: clock interrupt register - byte_offset: 12 - fieldset: CIR - - name: AHB1RSTR - description: AHB1 peripheral reset register - byte_offset: 16 - fieldset: AHB1RSTR - - name: AHB2RSTR - description: AHB2 peripheral reset register - byte_offset: 20 - fieldset: AHB2RSTR - - name: AHB3RSTR - description: AHB3 peripheral reset register - byte_offset: 24 - fieldset: AHB3RSTR - - name: APB1RSTR - description: APB1 peripheral reset register - byte_offset: 32 - fieldset: APB1RSTR - - name: APB2RSTR - description: APB2 peripheral reset register - byte_offset: 36 - fieldset: APB2RSTR - - name: AHB1ENR - description: AHB1 peripheral clock register - byte_offset: 48 - fieldset: AHB1ENR - - name: AHB2ENR - description: AHB2 peripheral clock enable register - byte_offset: 52 - fieldset: AHB2ENR - - name: AHB3ENR - description: AHB3 peripheral clock enable register - byte_offset: 56 - fieldset: AHB3ENR - - name: APB1ENR - description: APB1 peripheral clock enable register - byte_offset: 64 - fieldset: APB1ENR - - name: APB2ENR - description: APB2 peripheral clock enable register - byte_offset: 68 - fieldset: APB2ENR - - name: AHB1LPENR - description: AHB1 peripheral clock enable in low power mode register - byte_offset: 80 - fieldset: AHB1LPENR - - name: AHB2LPENR - description: AHB2 peripheral clock enable in low power mode register - byte_offset: 84 - fieldset: AHB2LPENR - - name: AHB3LPENR - description: AHB3 peripheral clock enable in low power mode register - byte_offset: 88 - fieldset: AHB3LPENR - - name: APB1LPENR - description: APB1 peripheral clock enable in low power mode register - byte_offset: 96 - fieldset: APB1LPENR - - name: APB2LPENR - description: APB2 peripheral clock enabled in low power mode register - byte_offset: 100 - fieldset: APB2LPENR - - name: BDCR - description: Backup domain control register - byte_offset: 112 - fieldset: BDCR - - name: CSR - description: clock control & status register - byte_offset: 116 - fieldset: CSR - - name: SSCGR - description: spread spectrum clock generation register - byte_offset: 128 - fieldset: SSCGR - - name: PLLI2SCFGR - description: PLLI2S configuration register - byte_offset: 132 - fieldset: PLLI2SCFGR - - name: PLLSAICFGR - description: RCC PLL configuration register - byte_offset: 136 - fieldset: PLLSAICFGR - - name: DCKCFGR - description: RCC Dedicated Clock Configuration Register - byte_offset: 140 - fieldset: DCKCFGR - - name: CKGATENR - description: Clocks gated enable register - byte_offset: 144 - fieldset: CKGATENR - - name: DCKCFGR2 - description: DCKCFGR2 register - byte_offset: 148 - fieldset: DCKCFGR2 + - name: CR + description: clock control register + byte_offset: 0 + fieldset: CR + - name: PLLCFGR + description: PLL configuration register + byte_offset: 4 + fieldset: PLLCFGR + - name: CFGR + description: clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: CIR + description: clock interrupt register + byte_offset: 12 + fieldset: CIR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 16 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: AHB2 peripheral reset register + byte_offset: 20 + fieldset: AHB2RSTR + - name: AHB3RSTR + description: AHB3 peripheral reset register + byte_offset: 24 + fieldset: AHB3RSTR + - name: APB1RSTR + description: APB1 peripheral reset register + byte_offset: 32 + fieldset: APB1RSTR + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 36 + fieldset: APB2RSTR + - name: AHB1ENR + description: AHB1 peripheral clock register + byte_offset: 48 + fieldset: AHB1ENR + - name: AHB2ENR + description: AHB2 peripheral clock enable register + byte_offset: 52 + fieldset: AHB2ENR + - name: AHB3ENR + description: AHB3 peripheral clock enable register + byte_offset: 56 + fieldset: AHB3ENR + - name: APB1ENR + description: APB1 peripheral clock enable register + byte_offset: 64 + fieldset: APB1ENR + - name: APB2ENR + description: APB2 peripheral clock enable register + byte_offset: 68 + fieldset: APB2ENR + - name: AHB1LPENR + description: AHB1 peripheral clock enable in low power mode register + byte_offset: 80 + fieldset: AHB1LPENR + - name: AHB2LPENR + description: AHB2 peripheral clock enable in low power mode register + byte_offset: 84 + fieldset: AHB2LPENR + - name: AHB3LPENR + description: AHB3 peripheral clock enable in low power mode register + byte_offset: 88 + fieldset: AHB3LPENR + - name: APB1LPENR + description: APB1 peripheral clock enable in low power mode register + byte_offset: 96 + fieldset: APB1LPENR + - name: APB2LPENR + description: APB2 peripheral clock enabled in low power mode register + byte_offset: 100 + fieldset: APB2LPENR + - name: BDCR + description: Backup domain control register + byte_offset: 112 + fieldset: BDCR + - name: CSR + description: clock control & status register + byte_offset: 116 + fieldset: CSR + - name: SSCGR + description: spread spectrum clock generation register + byte_offset: 128 + fieldset: SSCGR + - name: PLLI2SCFGR + description: PLLI2S configuration register + byte_offset: 132 + fieldset: PLLI2SCFGR + - name: PLLSAICFGR + description: RCC PLL configuration register + byte_offset: 136 + fieldset: PLLSAICFGR + - name: DCKCFGR + description: RCC Dedicated Clock Configuration Register + byte_offset: 140 + fieldset: DCKCFGR + - name: CKGATENR + description: Clocks gated enable register + byte_offset: 144 + fieldset: CKGATENR + - name: DCKCFGR2 + description: DCKCFGR2 register + byte_offset: 148 + fieldset: DCKCFGR2 fieldset/AHB1ENR: description: AHB1 peripheral clock register fields: - - name: GPIOAEN - description: IO port A clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: IO port B clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: IO port C clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: IO port D clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: IO port E clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIOFEN - description: IO port F clock enable - bit_offset: 5 - bit_size: 1 - - name: GPIOGEN - description: IO port G clock enable - bit_offset: 6 - bit_size: 1 - - name: GPIOHEN - description: IO port H clock enable - bit_offset: 7 - bit_size: 1 - - name: GPIOIEN - description: IO port I clock enable - bit_offset: 8 - bit_size: 1 - - name: GPIOJEN - description: IO port J clock enable - bit_offset: 9 - bit_size: 1 - - name: GPIOKEN - description: IO port K clock enable - bit_offset: 10 - bit_size: 1 - - name: CRCEN - description: CRC clock enable - bit_offset: 12 - bit_size: 1 - - name: BKPSRAMEN - description: Backup SRAM interface clock enable - bit_offset: 18 - bit_size: 1 - - name: CCMDATARAMEN - description: CCM data RAM clock enable - bit_offset: 20 - bit_size: 1 - - name: DMA1EN - description: DMA1 clock enable - bit_offset: 21 - bit_size: 1 - - name: DMA2EN - description: DMA2 clock enable - bit_offset: 22 - bit_size: 1 - - name: DMA2DEN - description: DMA2D clock enable - bit_offset: 23 - bit_size: 1 - - name: ETHEN - description: Ethernet MAC clock enable - bit_offset: 25 - bit_size: 1 - - name: ETHTXEN - description: Ethernet Transmission clock enable - bit_offset: 26 - bit_size: 1 - - name: ETHRXEN - description: Ethernet Reception clock enable - bit_offset: 27 - bit_size: 1 - - name: ETHPTPEN - description: Ethernet PTP clock enable - bit_offset: 28 - bit_size: 1 - - name: USB_OTG_HSEN - description: USB OTG HS clock enable - bit_offset: 29 - bit_size: 1 - - name: USB_OTG_HSULPIEN - description: USB OTG HSULPI clock enable - bit_offset: 30 - bit_size: 1 + - name: GPIOAEN + description: IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: IO port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: IO port E clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: IO port F clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: IO port G clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: IO port H clock enable + bit_offset: 7 + bit_size: 1 + - name: GPIOIEN + description: IO port I clock enable + bit_offset: 8 + bit_size: 1 + - name: GPIOJEN + description: IO port J clock enable + bit_offset: 9 + bit_size: 1 + - name: GPIOKEN + description: IO port K clock enable + bit_offset: 10 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: BKPSRAMEN + description: Backup SRAM interface clock enable + bit_offset: 18 + bit_size: 1 + - name: CCMDATARAMEN + description: CCM data RAM clock enable + bit_offset: 20 + bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 21 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 22 + bit_size: 1 + - name: DMA2DEN + description: DMA2D clock enable + bit_offset: 23 + bit_size: 1 + - name: ETHEN + description: Ethernet MAC clock enable + bit_offset: 25 + bit_size: 1 + - name: ETHTXEN + description: Ethernet Transmission clock enable + bit_offset: 26 + bit_size: 1 + - name: ETHRXEN + description: Ethernet Reception clock enable + bit_offset: 27 + bit_size: 1 + - name: ETHPTPEN + description: Ethernet PTP clock enable + bit_offset: 28 + bit_size: 1 + - name: USB_OTG_HSEN + description: USB OTG HS clock enable + bit_offset: 29 + bit_size: 1 + - name: USB_OTG_HSULPIEN + description: USB OTG HSULPI clock enable + bit_offset: 30 + bit_size: 1 fieldset/AHB1LPENR: description: AHB1 peripheral clock enable in low power mode register fields: - - name: GPIOALPEN - description: IO port A clock enable during sleep mode - bit_offset: 0 - bit_size: 1 - - name: GPIOBLPEN - description: IO port B clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: GPIOCLPEN - description: IO port C clock enable during Sleep mode - bit_offset: 2 - bit_size: 1 - - name: GPIODLPEN - description: IO port D clock enable during Sleep mode - bit_offset: 3 - bit_size: 1 - - name: GPIOELPEN - description: IO port E clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: GPIOFLPEN - description: IO port F clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: GPIOGLPEN - description: IO port G clock enable during Sleep mode - bit_offset: 6 - bit_size: 1 - - name: GPIOHLPEN - description: IO port H clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 - - name: GPIOILPEN - description: IO port I clock enable during Sleep mode - bit_offset: 8 - bit_size: 1 - - name: GPIOJLPEN - description: IO port J clock enable during Sleep mode - bit_offset: 9 - bit_size: 1 - - name: GPIOKLPEN - description: IO port K clock enable during Sleep mode - bit_offset: 10 - bit_size: 1 - - name: CRCLPEN - description: CRC clock enable during Sleep mode - bit_offset: 12 - bit_size: 1 - - name: FLASHLPEN - description: Flash interface clock enable during Sleep mode - bit_offset: 15 - bit_size: 1 - - name: SRAM1LPEN - description: SRAM 1interface clock enable during Sleep mode - bit_offset: 16 - bit_size: 1 - - name: SRAM2LPEN - description: SRAM 2 interface clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: BKPSRAMLPEN - description: Backup SRAM interface clock enable during Sleep mode - bit_offset: 18 - bit_size: 1 - - name: SRAM3LPEN - description: SRAM 3 interface clock enable during Sleep mode - bit_offset: 19 - bit_size: 1 - - name: DMA1LPEN - description: DMA1 clock enable during Sleep mode - bit_offset: 21 - bit_size: 1 - - name: DMA2LPEN - description: DMA2 clock enable during Sleep mode - bit_offset: 22 - bit_size: 1 - - name: DMA2DLPEN - description: DMA2D clock enable during Sleep mode - bit_offset: 23 - bit_size: 1 - - name: ETHLPEN - description: Ethernet MAC clock enable during Sleep mode - bit_offset: 25 - bit_size: 1 - - name: ETHTXLPEN - description: Ethernet transmission clock enable during Sleep mode - bit_offset: 26 - bit_size: 1 - - name: ETHRXLPEN - description: Ethernet reception clock enable during Sleep mode - bit_offset: 27 - bit_size: 1 - - name: ETHPTPLPEN - description: Ethernet PTP clock enable during Sleep mode - bit_offset: 28 - bit_size: 1 - - name: USB_OTG_HSLPEN - description: USB OTG HS clock enable during Sleep mode - bit_offset: 29 - bit_size: 1 - - name: USB_OTG_HSULPILPEN - description: USB OTG HS ULPI clock enable during Sleep mode - bit_offset: 30 - bit_size: 1 - - name: RNGLPEN - description: RNG clock enable during sleep mode - bit_offset: 31 - bit_size: 1 + - name: GPIOALPEN + description: IO port A clock enable during sleep mode + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: IO port B clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: IO port C clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: GPIODLPEN + description: IO port D clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: GPIOELPEN + description: IO port E clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: GPIOFLPEN + description: IO port F clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: GPIOGLPEN + description: IO port G clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: GPIOHLPEN + description: IO port H clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: GPIOILPEN + description: IO port I clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: GPIOJLPEN + description: IO port J clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: GPIOKLPEN + description: IO port K clock enable during Sleep mode + bit_offset: 10 + bit_size: 1 + - name: CRCLPEN + description: CRC clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: FLASHLPEN + description: Flash interface clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: SRAM1LPEN + description: SRAM 1interface clock enable during Sleep mode + bit_offset: 16 + bit_size: 1 + - name: SRAM2LPEN + description: SRAM 2 interface clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: BKPSRAMLPEN + description: Backup SRAM interface clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: SRAM3LPEN + description: SRAM 3 interface clock enable during Sleep mode + bit_offset: 19 + bit_size: 1 + - name: DMA1LPEN + description: DMA1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: DMA2LPEN + description: DMA2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: DMA2DLPEN + description: DMA2D clock enable during Sleep mode + bit_offset: 23 + bit_size: 1 + - name: ETHLPEN + description: Ethernet MAC clock enable during Sleep mode + bit_offset: 25 + bit_size: 1 + - name: ETHTXLPEN + description: Ethernet transmission clock enable during Sleep mode + bit_offset: 26 + bit_size: 1 + - name: ETHRXLPEN + description: Ethernet reception clock enable during Sleep mode + bit_offset: 27 + bit_size: 1 + - name: ETHPTPLPEN + description: Ethernet PTP clock enable during Sleep mode + bit_offset: 28 + bit_size: 1 + - name: USB_OTG_HSLPEN + description: USB OTG HS clock enable during Sleep mode + bit_offset: 29 + bit_size: 1 + - name: USB_OTG_HSULPILPEN + description: USB OTG HS ULPI clock enable during Sleep mode + bit_offset: 30 + bit_size: 1 + - name: RNGLPEN + description: RNG clock enable during sleep mode + bit_offset: 31 + bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - - name: GPIOARST - description: IO port A reset - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: IO port B reset - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: IO port C reset - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: IO port D reset - bit_offset: 3 - bit_size: 1 - - name: GPIOERST - description: IO port E reset - bit_offset: 4 - bit_size: 1 - - name: GPIOFRST - description: IO port F reset - bit_offset: 5 - bit_size: 1 - - name: GPIOGRST - description: IO port G reset - bit_offset: 6 - bit_size: 1 - - name: GPIOHRST - description: IO port H reset - bit_offset: 7 - bit_size: 1 - - name: GPIOIRST - description: IO port I reset - bit_offset: 8 - bit_size: 1 - - name: GPIOJRST - description: IO port J reset - bit_offset: 9 - bit_size: 1 - - name: GPIOKRST - description: IO port K reset - bit_offset: 10 - bit_size: 1 - - name: CRCRST - description: CRC reset - bit_offset: 12 - bit_size: 1 - - name: DMA1RST - description: DMA2 reset - bit_offset: 21 - bit_size: 1 - - name: DMA2RST - description: DMA2 reset - bit_offset: 22 - bit_size: 1 - - name: DMA2DRST - description: DMA2D reset - bit_offset: 23 - bit_size: 1 - - name: ETHRST - description: Ethernet MAC reset - bit_offset: 25 - bit_size: 1 - - name: USB_OTG_HSRST - description: USB OTG HS module reset - bit_offset: 29 - bit_size: 1 + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 6 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 7 + bit_size: 1 + - name: GPIOIRST + description: IO port I reset + bit_offset: 8 + bit_size: 1 + - name: GPIOJRST + description: IO port J reset + bit_offset: 9 + bit_size: 1 + - name: GPIOKRST + description: IO port K reset + bit_offset: 10 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 + - name: DMA1RST + description: DMA2 reset + bit_offset: 21 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 22 + bit_size: 1 + - name: DMA2DRST + description: DMA2D reset + bit_offset: 23 + bit_size: 1 + - name: ETHRST + description: Ethernet MAC reset + bit_offset: 25 + bit_size: 1 + - name: USB_OTG_HSRST + description: USB OTG HS module reset + bit_offset: 29 + bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - - name: DCMIEN - description: Camera interface enable - bit_offset: 0 - bit_size: 1 - - name: CRYPEN - description: CRYP clock enable - bit_offset: 4 - bit_size: 1 - - name: HASHEN - description: Hash modules clock enable - bit_offset: 5 - bit_size: 1 - - name: RNGEN - description: Random number generator clock enable - bit_offset: 6 - bit_size: 1 - - name: USB_OTG_FSEN - description: USB OTG FS clock enable - bit_offset: 7 - bit_size: 1 + - name: DCMIEN + description: Camera interface enable + bit_offset: 0 + bit_size: 1 + - name: CRYPEN + description: CRYP clock enable + bit_offset: 4 + bit_size: 1 + - name: HASHEN + description: Hash modules clock enable + bit_offset: 5 + bit_size: 1 + - name: RNGEN + description: Random number generator clock enable + bit_offset: 6 + bit_size: 1 + - name: USB_OTG_FSEN + description: USB OTG FS clock enable + bit_offset: 7 + bit_size: 1 fieldset/AHB2LPENR: description: AHB2 peripheral clock enable in low power mode register fields: - - name: DCMILPEN - description: Camera interface enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: FSMCLPEN - description: Flexible memory controller module clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: QSPILPEN - description: QUADSPI memory controller module clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: CRYPLPEN - description: Cryptography modules clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: HASHLPEN - description: Hash modules clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: RNGLPEN - description: Random number generator clock enable during Sleep mode - bit_offset: 6 - bit_size: 1 - - name: USB_OTG_FSLPEN - description: USB OTG FS clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 + - name: DCMILPEN + description: Camera interface enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: FSMCLPEN + description: Flexible memory controller module clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: QSPILPEN + description: QUADSPI memory controller module clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: CRYPLPEN + description: Cryptography modules clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: HASHLPEN + description: Hash modules clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: RNGLPEN + description: Random number generator clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: USB_OTG_FSLPEN + description: USB OTG FS clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - - name: DCMIRST - description: Camera interface reset - bit_offset: 0 - bit_size: 1 - - name: CRYPRST - description: CRYP module reset - bit_offset: 4 - bit_size: 1 - - name: HSAHRST - description: Hash module reset - bit_offset: 5 - bit_size: 1 - - name: RNGRST - description: Random number generator module reset - bit_offset: 6 - bit_size: 1 - - name: USB_OTG_FSRST - description: USB OTG FS module reset - bit_offset: 7 - bit_size: 1 + - name: DCMIRST + description: Camera interface reset + bit_offset: 0 + bit_size: 1 + - name: CRYPRST + description: CRYP module reset + bit_offset: 4 + bit_size: 1 + - name: HSAHRST + description: Hash module reset + bit_offset: 5 + bit_size: 1 + - name: RNGRST + description: Random number generator module reset + bit_offset: 6 + bit_size: 1 + - name: USB_OTG_FSRST + description: USB OTG FS module reset + bit_offset: 7 + bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: - - name: FMCEN - description: Flexible static memory controller module clock enable - bit_offset: 0 - bit_size: 1 - - name: FSMCEN - description: Flexible static memory controller module clock enable - bit_offset: 0 - bit_size: 1 - - name: QUADSPIEN - description: QUADSPI memory controller module clock enable - bit_offset: 1 - bit_size: 1 + - name: FMCEN + description: Flexible static memory controller module clock enable + bit_offset: 0 + bit_size: 1 + - name: FSMCEN + description: Flexible static memory controller module clock enable + bit_offset: 0 + bit_size: 1 + - name: QUADSPIEN + description: QUADSPI memory controller module clock enable + bit_offset: 1 + bit_size: 1 fieldset/AHB3LPENR: description: AHB3 peripheral clock enable in low power mode register fields: - - name: FMCLPEN - description: Flexible static memory controller module clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: FSMCLPEN - description: Flexible static memory controller module clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: QSPILPEN - description: QUADSPI memory controller module clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 + - name: FMCLPEN + description: Flexible static memory controller module clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: FSMCLPEN + description: Flexible static memory controller module clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: QSPILPEN + description: QUADSPI memory controller module clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - - name: FMCRST - description: Flexible static memory controller module reset - bit_offset: 0 - bit_size: 1 - - name: FSMCRST - description: Flexible static memory controller module reset - bit_offset: 0 - bit_size: 1 - - name: QSPIRST - description: QUADSPI module reset - bit_offset: 1 - bit_size: 1 + - name: FMCRST + description: Flexible static memory controller module reset + bit_offset: 0 + bit_size: 1 + - name: FSMCRST + description: Flexible static memory controller module reset + bit_offset: 0 + bit_size: 1 + - name: QSPIRST + description: QUADSPI module reset + bit_offset: 1 + bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register fields: - - name: TIM2EN - description: TIM2 clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: TIM3 clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: TIM4 clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: TIM5 clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: TIM6 clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: TIM7 clock enable - bit_offset: 5 - bit_size: 1 - - name: TIM12EN - description: TIM12 clock enable - bit_offset: 6 - bit_size: 1 - - name: TIM13EN - description: TIM13 clock enable - bit_offset: 7 - bit_size: 1 - - name: TIM14EN - description: TIM14 clock enable - bit_offset: 8 - bit_size: 1 - - name: LPTIM1EN - description: LPTIM1 clock enable - bit_offset: 9 - bit_size: 1 - - name: RTCAPBEN - description: RTC APB clock enable - bit_offset: 10 - bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI2 clock enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI3 clock enable - bit_offset: 15 - bit_size: 1 - - name: SPDIFEN - description: SPDIF-IN clock enable - bit_offset: 16 - bit_size: 1 - - name: USART2EN - description: USART 2 clock enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART3 clock enable - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: UART4 clock enable - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: UART5 clock enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C2 clock enable - bit_offset: 22 - bit_size: 1 - - name: I2C3EN - description: I2C3 clock enable - bit_offset: 23 - bit_size: 1 - - name: FMPI2C1EN - description: FMPI2C1 clock enable - bit_offset: 24 - bit_size: 1 - - name: CAN1EN - description: CAN 1 clock enable - bit_offset: 25 - bit_size: 1 - - name: CAN2EN - description: CAN 2 clock enable - bit_offset: 26 - bit_size: 1 - - name: CAN3EN - description: CAN 3 clock enable - bit_offset: 27 - bit_size: 1 - - name: CECEN - description: CEC interface clock enable - bit_offset: 27 - bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - - name: DACEN - description: DAC interface clock enable - bit_offset: 29 - bit_size: 1 - - name: UART7EN - description: UART7 clock enable - bit_offset: 30 - bit_size: 1 - - name: UART8EN - description: UART8 clock enable - bit_offset: 31 - bit_size: 1 + - name: TIM2EN + description: TIM2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: TIM5 clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM7 clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: TIM12 clock enable + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: TIM13 clock enable + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: TIM14 clock enable + bit_offset: 8 + bit_size: 1 + - name: LPTIM1EN + description: LPTIM1 clock enable + bit_offset: 9 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 clock enable + bit_offset: 15 + bit_size: 1 + - name: SPDIFEN + description: SPDIF-IN clock enable + bit_offset: 16 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 23 + bit_size: 1 + - name: FMPI2C1EN + description: FMPI2C1 clock enable + bit_offset: 24 + bit_size: 1 + - name: CAN1EN + description: CAN 1 clock enable + bit_offset: 25 + bit_size: 1 + - name: CAN2EN + description: CAN 2 clock enable + bit_offset: 26 + bit_size: 1 + - name: CAN3EN + description: CAN 3 clock enable + bit_offset: 27 + bit_size: 1 + - name: CECEN + description: CEC interface clock enable + bit_offset: 27 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: UART7EN + description: UART7 clock enable + bit_offset: 30 + bit_size: 1 + - name: UART8EN + description: UART8 clock enable + bit_offset: 31 + bit_size: 1 fieldset/APB1LPENR: description: APB1 peripheral clock enable in low power mode register fields: - - name: TIM2LPEN - description: TIM2 clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM3LPEN - description: TIM3 clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: TIM4LPEN - description: TIM4 clock enable during Sleep mode - bit_offset: 2 - bit_size: 1 - - name: TIM5LPEN - description: TIM5 clock enable during Sleep mode - bit_offset: 3 - bit_size: 1 - - name: TIM6LPEN - description: TIM6 clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: TIM7LPEN - description: TIM7 clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: TIM12LPEN - description: TIM12 clock enable during Sleep mode - bit_offset: 6 - bit_size: 1 - - name: TIM13LPEN - description: TIM13 clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 - - name: TIM14LPEN - description: TIM14 clock enable during Sleep mode - bit_offset: 8 - bit_size: 1 - - name: LPTIM1LPEN - description: LPTIM1 clock enable during sleep mode - bit_offset: 9 - bit_size: 1 - - name: RTCAPBLPEN - description: RTC APB clock enable during sleep mode - bit_offset: 10 - bit_size: 1 - - name: WWDGLPEN - description: Window watchdog clock enable during Sleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI2LPEN - description: SPI2 clock enable during Sleep mode - bit_offset: 14 - bit_size: 1 - - name: SPI3LPEN - description: SPI3 clock enable during Sleep mode - bit_offset: 15 - bit_size: 1 - - name: SPDIFLPEN - description: SPDIF clock enable during Sleep mode - bit_offset: 16 - bit_size: 1 - - name: USART2LPEN - description: USART2 clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: USART3LPEN - description: USART3 clock enable during Sleep mode - bit_offset: 18 - bit_size: 1 - - name: UART4LPEN - description: UART4 clock enable during Sleep mode - bit_offset: 19 - bit_size: 1 - - name: UART5LPEN - description: UART5 clock enable during Sleep mode - bit_offset: 20 - bit_size: 1 - - name: I2C1LPEN - description: I2C1 clock enable during Sleep mode - bit_offset: 21 - bit_size: 1 - - name: I2C2LPEN - description: I2C2 clock enable during Sleep mode - bit_offset: 22 - bit_size: 1 - - name: I2C3LPEN - description: I2C3 clock enable during Sleep mode - bit_offset: 23 - bit_size: 1 - - name: FMPI2C1LPEN - description: FMPI2C1 clock enable during Sleep - bit_offset: 24 - bit_size: 1 - - name: CAN1LPEN - description: CAN 1 clock enable during Sleep mode - bit_offset: 25 - bit_size: 1 - - name: CAN2LPEN - description: CAN 2 clock enable during Sleep mode - bit_offset: 26 - bit_size: 1 - - name: CAN3LPEN - description: CAN3 clock enable during Sleep mode - bit_offset: 27 - bit_size: 1 - - name: CECLPEN - description: CEC clock enable during Sleep mode - bit_offset: 27 - bit_size: 1 - - name: PWRLPEN - description: Power interface clock enable during Sleep mode - bit_offset: 28 - bit_size: 1 - - name: DACLPEN - description: DAC interface clock enable during Sleep mode - bit_offset: 29 - bit_size: 1 - - name: UART7LPEN - description: UART7 clock enable during Sleep mode - bit_offset: 30 - bit_size: 1 - - name: UART8LPEN - description: UART8 clock enable during Sleep mode - bit_offset: 31 - bit_size: 1 + - name: TIM2LPEN + description: TIM2 clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM3LPEN + description: TIM3 clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: TIM4LPEN + description: TIM4 clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: TIM5LPEN + description: TIM5 clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: TIM6LPEN + description: TIM6 clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: TIM7LPEN + description: TIM7 clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: TIM12LPEN + description: TIM12 clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: TIM13LPEN + description: TIM13 clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: TIM14LPEN + description: TIM14 clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: LPTIM1LPEN + description: LPTIM1 clock enable during sleep mode + bit_offset: 9 + bit_size: 1 + - name: RTCAPBLPEN + description: RTC APB clock enable during sleep mode + bit_offset: 10 + bit_size: 1 + - name: WWDGLPEN + description: Window watchdog clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI2LPEN + description: SPI2 clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: SPI3LPEN + description: SPI3 clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: SPDIFLPEN + description: SPDIF clock enable during Sleep mode + bit_offset: 16 + bit_size: 1 + - name: USART2LPEN + description: USART2 clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: USART3LPEN + description: USART3 clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: UART4LPEN + description: UART4 clock enable during Sleep mode + bit_offset: 19 + bit_size: 1 + - name: UART5LPEN + description: UART5 clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 + - name: I2C1LPEN + description: I2C1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: I2C2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: I2C3LPEN + description: I2C3 clock enable during Sleep mode + bit_offset: 23 + bit_size: 1 + - name: FMPI2C1LPEN + description: FMPI2C1 clock enable during Sleep + bit_offset: 24 + bit_size: 1 + - name: CAN1LPEN + description: CAN 1 clock enable during Sleep mode + bit_offset: 25 + bit_size: 1 + - name: CAN2LPEN + description: CAN 2 clock enable during Sleep mode + bit_offset: 26 + bit_size: 1 + - name: CAN3LPEN + description: CAN3 clock enable during Sleep mode + bit_offset: 27 + bit_size: 1 + - name: CECLPEN + description: CEC clock enable during Sleep mode + bit_offset: 27 + bit_size: 1 + - name: PWRLPEN + description: Power interface clock enable during Sleep mode + bit_offset: 28 + bit_size: 1 + - name: DACLPEN + description: DAC interface clock enable during Sleep mode + bit_offset: 29 + bit_size: 1 + - name: UART7LPEN + description: UART7 clock enable during Sleep mode + bit_offset: 30 + bit_size: 1 + - name: UART8LPEN + description: UART8 clock enable during Sleep mode + bit_offset: 31 + bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register fields: - - name: TIM2RST - description: TIM2 reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: TIM3 reset - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: TIM4 reset - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: TIM5 reset - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: TIM6 reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: TIM7 reset - bit_offset: 5 - bit_size: 1 - - name: TIM12RST - description: TIM12 reset - bit_offset: 6 - bit_size: 1 - - name: TIM13RST - description: TIM13 reset - bit_offset: 7 - bit_size: 1 - - name: TIM14RST - description: TIM14 reset - bit_offset: 8 - bit_size: 1 - - name: LPTIM1RST - description: LPTIM1 reset - bit_offset: 9 - bit_size: 1 - - name: WWDGRST - description: Window watchdog reset - bit_offset: 11 - bit_size: 1 - - name: SPI2RST - description: SPI 2 reset - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: SPI 3 reset - bit_offset: 15 - bit_size: 1 - - name: SPDIFRST - description: SPDIF-IN reset - bit_offset: 16 - bit_size: 1 - - name: USART2RST - description: USART 2 reset - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: USART 3 reset - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: UART 4 reset - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: UART 5 reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C 1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C 2 reset - bit_offset: 22 - bit_size: 1 - - name: I2C3RST - description: I2C3 reset - bit_offset: 23 - bit_size: 1 - - name: FMPI2C1RST - description: FMPI2C1 reset - bit_offset: 24 - bit_size: 1 - - name: CAN1RST - description: CAN1 reset - bit_offset: 25 - bit_size: 1 - - name: CAN2RST - description: CAN2 reset - bit_offset: 26 - bit_size: 1 - - name: CAN3RST - description: CAN 3 reset - bit_offset: 27 - bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - - name: DACRST - description: DAC reset - bit_offset: 29 - bit_size: 1 - - name: UART7RST - description: UART 7 reset - bit_offset: 30 - bit_size: 1 - - name: UART8RST - description: UART 8 reset - bit_offset: 31 - bit_size: 1 + - name: TIM2RST + description: TIM2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: TIM3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: TIM4 reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: TIM5 reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: TIM6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM7 reset + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: TIM12 reset + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: TIM13 reset + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: TIM14 reset + bit_offset: 8 + bit_size: 1 + - name: LPTIM1RST + description: LPTIM1 reset + bit_offset: 9 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI 2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI 3 reset + bit_offset: 15 + bit_size: 1 + - name: SPDIFRST + description: SPDIF-IN reset + bit_offset: 16 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART 3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: UART 4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: UART 5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C 1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C 2 reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 23 + bit_size: 1 + - name: FMPI2C1RST + description: FMPI2C1 reset + bit_offset: 24 + bit_size: 1 + - name: CAN1RST + description: CAN1 reset + bit_offset: 25 + bit_size: 1 + - name: CAN2RST + description: CAN2 reset + bit_offset: 26 + bit_size: 1 + - name: CAN3RST + description: CAN 3 reset + bit_offset: 27 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC reset + bit_offset: 29 + bit_size: 1 + - name: UART7RST + description: UART 7 reset + bit_offset: 30 + bit_size: 1 + - name: UART8RST + description: UART 8 reset + bit_offset: 31 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - - name: TIM1EN - description: TIM1 clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM8EN - description: TIM8 clock enable - bit_offset: 1 - bit_size: 1 - - name: USART1EN - description: USART1 clock enable - bit_offset: 4 - bit_size: 1 - - name: USART6EN - description: USART6 clock enable - bit_offset: 5 - bit_size: 1 - - name: UART9EN - description: UART9 clock enable - bit_offset: 6 - bit_size: 1 - - name: UART10EN - description: UART10 clock enable - bit_offset: 7 - bit_size: 1 - - name: ADC1EN - description: ADC1 clock enable - bit_offset: 8 - bit_size: 1 - - name: ADC2EN - description: ADC2 clock enable - bit_offset: 9 - bit_size: 1 - - name: ADC3EN - description: ADC3 clock enable - bit_offset: 10 - bit_size: 1 - - name: SDIOEN - description: SDIO clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: SPI1 clock enable - bit_offset: 12 - bit_size: 1 - - name: SPI4EN - description: SPI4 clock enable - bit_offset: 13 - bit_size: 1 - - name: SYSCFGEN - description: System configuration controller clock enable - bit_offset: 14 - bit_size: 1 - - name: EXTITEN - description: EXTI ans external IT clock enable - bit_offset: 15 - bit_size: 1 - - name: TIM9EN - description: TIM9 clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM10EN - description: TIM10 clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM11EN - description: TIM11 clock enable - bit_offset: 18 - bit_size: 1 - - name: SPI5EN - description: SPI5 clock enable - bit_offset: 20 - bit_size: 1 - - name: SPI6EN - description: SPI6 clock enable - bit_offset: 21 - bit_size: 1 - - name: SAI1EN - description: SAI 1 clock enable - bit_offset: 22 - bit_size: 1 - - name: SAI2EN - description: SAI2 clock enable - bit_offset: 23 - bit_size: 1 - - name: DFSDMEN - description: DFSDMEN - bit_offset: 24 - bit_size: 1 - - name: DFSDM2EN - description: DFSDM2 clock enable - bit_offset: 25 - bit_size: 1 - - name: LTDCEN - description: LTDC clock enable - bit_offset: 26 - bit_size: 1 - - name: DSIEN - description: DSI clocks enable - bit_offset: 27 - bit_size: 1 + - name: TIM1EN + description: TIM1 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM8EN + description: TIM8 clock enable + bit_offset: 1 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 4 + bit_size: 1 + - name: USART6EN + description: USART6 clock enable + bit_offset: 5 + bit_size: 1 + - name: UART9EN + description: UART9 clock enable + bit_offset: 6 + bit_size: 1 + - name: UART10EN + description: UART10 clock enable + bit_offset: 7 + bit_size: 1 + - name: ADC1EN + description: ADC1 clock enable + bit_offset: 8 + bit_size: 1 + - name: ADC2EN + description: ADC2 clock enable + bit_offset: 9 + bit_size: 1 + - name: ADC3EN + description: ADC3 clock enable + bit_offset: 10 + bit_size: 1 + - name: SDIOEN + description: SDIO clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: SPI4EN + description: SPI4 clock enable + bit_offset: 13 + bit_size: 1 + - name: SYSCFGEN + description: System configuration controller clock enable + bit_offset: 14 + bit_size: 1 + - name: EXTITEN + description: EXTI ans external IT clock enable + bit_offset: 15 + bit_size: 1 + - name: TIM9EN + description: TIM9 clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM10EN + description: TIM10 clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM11EN + description: TIM11 clock enable + bit_offset: 18 + bit_size: 1 + - name: SPI5EN + description: SPI5 clock enable + bit_offset: 20 + bit_size: 1 + - name: SPI6EN + description: SPI6 clock enable + bit_offset: 21 + bit_size: 1 + - name: SAI1EN + description: SAI 1 clock enable + bit_offset: 22 + bit_size: 1 + - name: SAI2EN + description: SAI2 clock enable + bit_offset: 23 + bit_size: 1 + - name: DFSDMEN + description: DFSDMEN + bit_offset: 24 + bit_size: 1 + - name: DFSDM2EN + description: DFSDM2 clock enable + bit_offset: 25 + bit_size: 1 + - name: LTDCEN + description: LTDC clock enable + bit_offset: 26 + bit_size: 1 + - name: DSIEN + description: DSI clocks enable + bit_offset: 27 + bit_size: 1 fieldset/APB2LPENR: description: APB2 peripheral clock enabled in low power mode register fields: - - name: TIM1LPEN - description: TIM1 clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM8LPEN - description: TIM8 clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: USART1LPEN - description: USART1 clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: USART6LPEN - description: USART6 clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: UART9LPEN - description: UART9 clock enable during Sleep mode - bit_offset: 6 - bit_size: 1 - - name: UART10LPEN - description: UART10 clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 - - name: ADC1LPEN - description: ADC1 clock enable during Sleep mode - bit_offset: 8 - bit_size: 1 - - name: ADC2LPEN - description: ADC2 clock enable during Sleep mode - bit_offset: 9 - bit_size: 1 - - name: ADC3LPEN - description: ADC 3 clock enable during Sleep mode - bit_offset: 10 - bit_size: 1 - - name: SDIOLPEN - description: SDIO clock enable during Sleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI1LPEN - description: SPI 1 clock enable during Sleep mode - bit_offset: 12 - bit_size: 1 - - name: SPI4LPEN - description: SPI4 clock enable during Sleep mode - bit_offset: 13 - bit_size: 1 - - name: SYSCFGLPEN - description: System configuration controller clock enable during Sleep mode - bit_offset: 14 - bit_size: 1 - - name: EXTITLPEN - description: EXTI and External IT clock enable during sleep mode - bit_offset: 15 - bit_size: 1 - - name: TIM9LPEN - description: TIM9 clock enable during sleep mode - bit_offset: 16 - bit_size: 1 - - name: TIM10LPEN - description: TIM10 clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: TIM11LPEN - description: TIM11 clock enable during Sleep mode - bit_offset: 18 - bit_size: 1 - - name: SPI5LPEN - description: SPI5 clock enable during Sleep mode - bit_offset: 20 - bit_size: 1 - - name: SPI6LPEN - description: SPI 6 clock enable during Sleep mode - bit_offset: 21 - bit_size: 1 - - name: SAI1LPEN - description: SAI1 clock enable during Sleep mode - bit_offset: 22 - bit_size: 1 - - name: SAI2LPEN - description: SAI2 clock enable - bit_offset: 23 - bit_size: 1 - - name: DFSDMLPEN - description: DFSDMLPEN - bit_offset: 24 - bit_size: 1 - - name: DFSDM2LPEN - description: DFSDM2 clock enable during Sleep mode - bit_offset: 25 - bit_size: 1 - - name: LTDCLPEN - description: LTDC clock enable during Sleep mode - bit_offset: 26 - bit_size: 1 - - name: DSILPEN - description: DSI clocks enable during Sleep mode - bit_offset: 27 - bit_size: 1 + - name: TIM1LPEN + description: TIM1 clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM8LPEN + description: TIM8 clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: USART1LPEN + description: USART1 clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: USART6LPEN + description: USART6 clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: UART9LPEN + description: UART9 clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: UART10LPEN + description: UART10 clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: ADC1LPEN + description: ADC1 clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: ADC2LPEN + description: ADC2 clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: ADC3LPEN + description: ADC 3 clock enable during Sleep mode + bit_offset: 10 + bit_size: 1 + - name: SDIOLPEN + description: SDIO clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI1LPEN + description: SPI 1 clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: SPI4LPEN + description: SPI4 clock enable during Sleep mode + bit_offset: 13 + bit_size: 1 + - name: SYSCFGLPEN + description: System configuration controller clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: EXTITLPEN + description: EXTI and External IT clock enable during sleep mode + bit_offset: 15 + bit_size: 1 + - name: TIM9LPEN + description: TIM9 clock enable during sleep mode + bit_offset: 16 + bit_size: 1 + - name: TIM10LPEN + description: TIM10 clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: TIM11LPEN + description: TIM11 clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: SPI5LPEN + description: SPI5 clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 + - name: SPI6LPEN + description: SPI 6 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: SAI1LPEN + description: SAI1 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: SAI2LPEN + description: SAI2 clock enable + bit_offset: 23 + bit_size: 1 + - name: DFSDMLPEN + description: DFSDMLPEN + bit_offset: 24 + bit_size: 1 + - name: DFSDM2LPEN + description: DFSDM2 clock enable during Sleep mode + bit_offset: 25 + bit_size: 1 + - name: LTDCLPEN + description: LTDC clock enable during Sleep mode + bit_offset: 26 + bit_size: 1 + - name: DSILPEN + description: DSI clocks enable during Sleep mode + bit_offset: 27 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - - name: TIM1RST - description: TIM1 reset - bit_offset: 0 - bit_size: 1 - - name: TIM8RST - description: TIM8 reset - bit_offset: 1 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 4 - bit_size: 1 - - name: USART6RST - description: USART6 reset - bit_offset: 5 - bit_size: 1 - - name: UART9RST - description: UART9 reset - bit_offset: 6 - bit_size: 1 - - name: UART10RST - description: UART10 reset - bit_offset: 7 - bit_size: 1 - - name: ADCRST - description: ADC interface reset (common to all ADCs) - bit_offset: 8 - bit_size: 1 - - name: SDIORST - description: SDIO reset - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: SPI 1 reset - bit_offset: 12 - bit_size: 1 - - name: SPI4RST - description: SPI4 reset - bit_offset: 13 - bit_size: 1 - - name: SYSCFGRST - description: System configuration controller reset - bit_offset: 14 - bit_size: 1 - - name: TIM9RST - description: TIM9 reset - bit_offset: 16 - bit_size: 1 - - name: TIM10RST - description: TIM10 reset - bit_offset: 17 - bit_size: 1 - - name: TIM11RST - description: TIM11 reset - bit_offset: 18 - bit_size: 1 - - name: SPI5RST - description: SPI5 reset - bit_offset: 20 - bit_size: 1 - - name: SPI6RST - description: SPI6 reset - bit_offset: 21 - bit_size: 1 - - name: SAI1RST - description: SAI1 reset - bit_offset: 22 - bit_size: 1 - - name: SAI2RST - description: SAI2 reset - bit_offset: 23 - bit_size: 1 - - name: DFSDMRST - description: DFSDMRST - bit_offset: 24 - bit_size: 1 - - name: DFSDM2RST - description: DFSDM2 reset - bit_offset: 25 - bit_size: 1 - - name: LTDCRST - description: LTDC reset - bit_offset: 26 - bit_size: 1 - - name: DSIRST - description: DSI host reset - bit_offset: 27 - bit_size: 1 + - name: TIM1RST + description: TIM1 reset + bit_offset: 0 + bit_size: 1 + - name: TIM8RST + description: TIM8 reset + bit_offset: 1 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 4 + bit_size: 1 + - name: USART6RST + description: USART6 reset + bit_offset: 5 + bit_size: 1 + - name: UART9RST + description: UART9 reset + bit_offset: 6 + bit_size: 1 + - name: UART10RST + description: UART10 reset + bit_offset: 7 + bit_size: 1 + - name: ADCRST + description: ADC interface reset (common to all ADCs) + bit_offset: 8 + bit_size: 1 + - name: SDIORST + description: SDIO reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: SPI4RST + description: SPI4 reset + bit_offset: 13 + bit_size: 1 + - name: SYSCFGRST + description: System configuration controller reset + bit_offset: 14 + bit_size: 1 + - name: TIM9RST + description: TIM9 reset + bit_offset: 16 + bit_size: 1 + - name: TIM10RST + description: TIM10 reset + bit_offset: 17 + bit_size: 1 + - name: TIM11RST + description: TIM11 reset + bit_offset: 18 + bit_size: 1 + - name: SPI5RST + description: SPI5 reset + bit_offset: 20 + bit_size: 1 + - name: SPI6RST + description: SPI6 reset + bit_offset: 21 + bit_size: 1 + - name: SAI1RST + description: SAI1 reset + bit_offset: 22 + bit_size: 1 + - name: SAI2RST + description: SAI2 reset + bit_offset: 23 + bit_size: 1 + - name: DFSDMRST + description: DFSDMRST + bit_offset: 24 + bit_size: 1 + - name: DFSDM2RST + description: DFSDM2 reset + bit_offset: 25 + bit_size: 1 + - name: LTDCRST + description: LTDC reset + bit_offset: 26 + bit_size: 1 + - name: DSIRST + description: DSI host reset + bit_offset: 27 + bit_size: 1 fieldset/BDCR: description: Backup domain control register fields: - - name: LSEON - description: External low-speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: External low-speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: External low-speed oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: LSEMOD - description: External low-speed oscillator bypass - bit_offset: 3 - bit_size: 1 - enum: LSEMOD - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: Backup domain software reset - bit_offset: 16 - bit_size: 1 + - name: LSEON + description: External low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External low-speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: External low-speed oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEMOD + description: External low-speed oscillator bypass + bit_offset: 3 + bit_size: 1 + enum: LSEMOD + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 fieldset/CFGR: description: clock configuration register fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: System clock switch status - bit_offset: 2 - bit_size: 2 - enum: SWS - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - enum: HPRE - - name: MCO1EN - description: MCO output enable - bit_offset: 8 - bit_size: 1 - - name: MCO2EN - description: MCO output enable - bit_offset: 9 - bit_size: 1 - - name: PPRE1 - description: APB Low speed prescaler (APB1) - bit_offset: 10 - bit_size: 3 - enum: PPRE - - name: PPRE2 - description: APB high-speed prescaler (APB2) - bit_offset: 13 - bit_size: 3 - enum: PPRE - - name: RTCPRE - description: HSE division factor for RTC clock - bit_offset: 16 - bit_size: 5 - - name: MCO1 - description: Microcontroller clock output 1 - bit_offset: 21 - bit_size: 2 - enum: MCO1 - - name: I2SSRC - description: I2S clock selection - bit_offset: 23 - bit_size: 1 - enum: ISSRC - - name: MCO1PRE - description: MCO1 prescaler - bit_offset: 24 - bit_size: 3 - enum: MCOPRE - - name: MCO2PRE - description: MCO2 prescaler - bit_offset: 27 - bit_size: 3 - enum: MCOPRE - - name: MCO2 - description: Microcontroller clock output 2 - bit_offset: 30 - bit_size: 2 - enum: MCO2 + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: MCO1EN + description: MCO output enable + bit_offset: 8 + bit_size: 1 + - name: MCO2EN + description: MCO output enable + bit_offset: 9 + bit_size: 1 + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 10 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high-speed prescaler (APB2) + bit_offset: 13 + bit_size: 3 + enum: PPRE + - name: RTCPRE + description: HSE division factor for RTC clock + bit_offset: 16 + bit_size: 5 + - name: MCO1 + description: Microcontroller clock output 1 + bit_offset: 21 + bit_size: 2 + enum: MCO1 + - name: I2SSRC + description: I2S clock selection + bit_offset: 23 + bit_size: 1 + enum: ISSRC + - name: MCO1PRE + description: MCO1 prescaler + bit_offset: 24 + bit_size: 3 + enum: MCOPRE + - name: MCO2PRE + description: MCO2 prescaler + bit_offset: 27 + bit_size: 3 + enum: MCOPRE + - name: MCO2 + description: Microcontroller clock output 2 + bit_offset: 30 + bit_size: 2 + enum: MCO2 fieldset/CIR: description: clock interrupt register fields: - - name: LSIRDYF - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - - name: HSIRDYF - description: HSI ready interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSERDYF - description: HSE ready interrupt flag - bit_offset: 3 - bit_size: 1 - - name: PLLRDYF - description: Main PLL (PLL) ready interrupt flag - bit_offset: 4 - bit_size: 1 - - name: PLLI2SRDYF - description: PLLI2S ready interrupt flag - bit_offset: 5 - bit_size: 1 - - name: PLLSAIRDYF - description: PLLSAI ready interrupt flag - bit_offset: 6 - bit_size: 1 - - name: CSSF - description: Clock security system interrupt flag - bit_offset: 7 - bit_size: 1 - - name: LSIRDYIE - description: LSI ready interrupt enable - bit_offset: 8 - bit_size: 1 - - name: LSERDYIE - description: LSE ready interrupt enable - bit_offset: 9 - bit_size: 1 - - name: HSIRDYIE - description: HSI ready interrupt enable - bit_offset: 10 - bit_size: 1 - - name: HSERDYIE - description: HSE ready interrupt enable - bit_offset: 11 - bit_size: 1 - - name: PLLRDYIE - description: Main PLL (PLL) ready interrupt enable - bit_offset: 12 - bit_size: 1 - - name: PLLI2SRDYIE - description: PLLI2S ready interrupt enable - bit_offset: 13 - bit_size: 1 - - name: PLLSAIRDYIE - description: PLLSAI Ready Interrupt Enable - bit_offset: 14 - bit_size: 1 - - name: LSIRDYC - description: LSI ready interrupt clear - bit_offset: 16 - bit_size: 1 - - name: LSERDYC - description: LSE ready interrupt clear - bit_offset: 17 - bit_size: 1 - - name: HSIRDYC - description: HSI ready interrupt clear - bit_offset: 18 - bit_size: 1 - - name: HSERDYC - description: HSE ready interrupt clear - bit_offset: 19 - bit_size: 1 - - name: PLLRDYC - description: Main PLL(PLL) ready interrupt clear - bit_offset: 20 - bit_size: 1 - - name: PLLI2SRDYC - description: PLLI2S ready interrupt clear - bit_offset: 21 - bit_size: 1 - - name: PLLSAIRDYC - description: PLLSAI Ready Interrupt Clear - bit_offset: 22 - bit_size: 1 - - name: CSSC - description: Clock security system interrupt clear - bit_offset: 23 - bit_size: 1 + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: Main PLL (PLL) ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLLI2SRDYF + description: PLLI2S ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: PLLSAIRDYF + description: PLLSAI ready interrupt flag + bit_offset: 6 + bit_size: 1 + - name: CSSF + description: Clock security system interrupt flag + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: Main PLL (PLL) ready interrupt enable + bit_offset: 12 + bit_size: 1 + - name: PLLI2SRDYIE + description: PLLI2S ready interrupt enable + bit_offset: 13 + bit_size: 1 + - name: PLLSAIRDYIE + description: PLLSAI Ready Interrupt Enable + bit_offset: 14 + bit_size: 1 + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: Main PLL(PLL) ready interrupt clear + bit_offset: 20 + bit_size: 1 + - name: PLLI2SRDYC + description: PLLI2S ready interrupt clear + bit_offset: 21 + bit_size: 1 + - name: PLLSAIRDYC + description: PLLSAI Ready Interrupt Clear + bit_offset: 22 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 fieldset/CKGATENR: description: clocks gated enable register fields: - - name: AHB2APB1_CKEN - description: AHB to APB1 Bridge clock enable - bit_offset: 0 - bit_size: 1 - - name: AHB2APB2_CKEN - description: AHB to APB2 Bridge clock enable - bit_offset: 1 - bit_size: 1 - - name: CM4DBG_CKEN - description: Cortex M4 ETM clock enable - bit_offset: 2 - bit_size: 1 - - name: SPARE_CKEN - description: Spare clock enable - bit_offset: 3 - bit_size: 1 - - name: SRAM_CKEN - description: SRAM controller clock enable - bit_offset: 4 - bit_size: 1 - - name: FLASH_CKEN - description: Flash interface clock enable - bit_offset: 5 - bit_size: 1 - - name: RCC_CKEN - description: RCC clock enable - bit_offset: 6 - bit_size: 1 - - name: EVTCL_CKEN - description: EVTCL clock enable - bit_offset: 7 - bit_size: 1 + - name: AHB2APB1_CKEN + description: AHB to APB1 Bridge clock enable + bit_offset: 0 + bit_size: 1 + - name: AHB2APB2_CKEN + description: AHB to APB2 Bridge clock enable + bit_offset: 1 + bit_size: 1 + - name: CM4DBG_CKEN + description: Cortex M4 ETM clock enable + bit_offset: 2 + bit_size: 1 + - name: SPARE_CKEN + description: Spare clock enable + bit_offset: 3 + bit_size: 1 + - name: SRAM_CKEN + description: SRAM controller clock enable + bit_offset: 4 + bit_size: 1 + - name: FLASH_CKEN + description: Flash interface clock enable + bit_offset: 5 + bit_size: 1 + - name: RCC_CKEN + description: RCC clock enable + bit_offset: 6 + bit_size: 1 + - name: EVTCL_CKEN + description: EVTCL clock enable + bit_offset: 7 + bit_size: 1 fieldset/CR: description: clock control register fields: - - name: HSION - description: Internal high-speed clock enable - bit_offset: 0 - bit_size: 1 - - name: HSIRDY - description: Internal high-speed clock ready flag - bit_offset: 1 - bit_size: 1 - - name: HSITRIM - description: Internal high-speed clock trimming - bit_offset: 3 - bit_size: 5 - - name: HSICAL - description: Internal high-speed clock calibration - bit_offset: 8 - bit_size: 8 - - name: HSEON - description: HSE clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: HSE clock bypass - bit_offset: 18 - bit_size: 1 - - name: CSSON - description: Clock security system enable - bit_offset: 19 - bit_size: 1 - - name: PLLON - description: Main PLL (PLL) enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: Main PLL (PLL) clock ready flag - bit_offset: 25 - bit_size: 1 - - name: PLLI2SON - description: PLLI2S enable - bit_offset: 26 - bit_size: 1 - - name: PLLI2SRDY - description: PLLI2S clock ready flag - bit_offset: 27 - bit_size: 1 - - name: PLLSAION - description: PLLSAI enable - bit_offset: 28 - bit_size: 1 - - name: PLLSAIRDY - description: PLLSAI clock ready flag - bit_offset: 29 - bit_size: 1 + - name: HSION + description: Internal high-speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal high-speed clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSITRIM + description: Internal high-speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal high-speed clock calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: HSE clock bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: Main PLL (PLL) enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL (PLL) clock ready flag + bit_offset: 25 + bit_size: 1 + - name: PLLI2SON + description: PLLI2S enable + bit_offset: 26 + bit_size: 1 + - name: PLLI2SRDY + description: PLLI2S clock ready flag + bit_offset: 27 + bit_size: 1 + - name: PLLSAION + description: PLLSAI enable + bit_offset: 28 + bit_size: 1 + - name: PLLSAIRDY + description: PLLSAI clock ready flag + bit_offset: 29 + bit_size: 1 fieldset/CSR: description: clock control & status register fields: - - name: LSION - description: Internal low-speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: Internal low-speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: RMVF - description: Remove reset flag - bit_offset: 24 - bit_size: 1 - - name: BORRSTF - description: BOR reset flag - bit_offset: 25 - bit_size: 1 - - name: PADRSTF - description: PIN reset flag - bit_offset: 26 - bit_size: 1 - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: WDGRSTF - description: Independent watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSION + description: Internal low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low-speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + - name: BORRSTF + description: BOR reset flag + bit_offset: 25 + bit_size: 1 + - name: PADRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: WDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 fieldset/DCKCFGR: description: Dedicated Clock Configuration Register fields: - - name: PLLI2SDIVQ - description: PLLI2S division factor for SAI1 clock - bit_offset: 0 - bit_size: 5 - enum: PLLISDIVQ - - name: PLLI2SDIVR - description: PLLI2S division factor for SAI1 A/B clock - bit_offset: 0 - bit_size: 5 - enum: PLLISDIVR - - name: PLLDIVR - description: PLL division factor for SAI1 A/B clock - bit_offset: 8 - bit_size: 5 - enum: PLLDIVR - - name: PLLSAIDIVQ - description: PLLSAI division factor for SAI1 clock - bit_offset: 8 - bit_size: 5 - enum: PLLSAIDIVQ - - name: CKDFSDM2ASEL - description: DFSDM2 audio clock selection - bit_offset: 14 - bit_size: 1 - enum: CKDFSDMASEL - - name: CKDFSDM1ASEL - description: DFSDM1 audio clock selection - bit_offset: 15 - bit_size: 5 - enum: CKDFSDMASEL - - name: PLLSAIDIVR - description: division factor for LCD_CLK - bit_offset: 16 - bit_size: 2 - enum: PLLSAIDIVR - - name: SAI1ASRC - description: SAI1-A clock source selection - bit_offset: 20 - bit_size: 2 - enum: SAIASRC - - name: SAI1SRC - description: SAI1 clock source selection - bit_offset: 20 - bit_size: 2 - enum: SAI1SRC - - name: SAI1BSRC - description: SAI1-B clock source selection - bit_offset: 22 - bit_size: 2 - enum: SAIBSRC - - name: SAI2SRC - description: SAI2 clock source selection - bit_offset: 22 - bit_size: 2 - enum: SAI2SRC - - name: TIMPRE - description: Timers clocks prescalers selection - bit_offset: 24 - bit_size: 1 - enum: TIMPRE - - name: I2S1SRC - description: I2S APB1 clocks source selection (I2S2/3) - bit_offset: 25 - bit_size: 2 - enum: I2S1SRC - - name: I2SSRC - description: I2SSRC - bit_offset: 25 - bit_size: 2 - enum: ISSRC - - name: CK48MSEL - description: 48 MHz clock source selection - bit_offset: 27 - bit_size: 1 - enum: CKMSEL - - name: I2S2SRC - description: I2S APB2 clocks source selection (I2S1/4/5) - bit_offset: 27 - bit_size: 2 - enum: I2S1SRC - - name: SDIOSEL - description: SDIO clock source selection - bit_offset: 28 - bit_size: 1 - enum: SDIOSEL - - name: DSISEL - description: DSI clock source selection - bit_offset: 29 - bit_size: 1 - enum: DSISEL - - name: CKDFSDM1SEL - description: DFSDM1 Kernel clock selection - bit_offset: 31 - bit_size: 1 - enum: CKDFSDMSEL + - name: PLLI2SDIVQ + description: PLLI2S division factor for SAI1 clock + bit_offset: 0 + bit_size: 5 + enum: PLLISDIVQ + - name: PLLI2SDIVR + description: PLLI2S division factor for SAI1 A/B clock + bit_offset: 0 + bit_size: 5 + enum: PLLISDIVR + - name: PLLDIVR + description: PLL division factor for SAI1 A/B clock + bit_offset: 8 + bit_size: 5 + enum: PLLDIVR + - name: PLLSAIDIVQ + description: PLLSAI division factor for SAI1 clock + bit_offset: 8 + bit_size: 5 + enum: PLLSAIDIVQ + - name: CKDFSDM2ASEL + description: DFSDM2 audio clock selection + bit_offset: 14 + bit_size: 1 + enum: CKDFSDMASEL + - name: CKDFSDM1ASEL + description: DFSDM1 audio clock selection + bit_offset: 15 + bit_size: 5 + enum: CKDFSDMASEL + - name: PLLSAIDIVR + description: division factor for LCD_CLK + bit_offset: 16 + bit_size: 2 + enum: PLLSAIDIVR + - name: SAI1ASRC + description: SAI1-A clock source selection + bit_offset: 20 + bit_size: 2 + enum: SAIASRC + - name: SAI1SRC + description: SAI1 clock source selection + bit_offset: 20 + bit_size: 2 + enum: SAI1SRC + - name: SAI1BSRC + description: SAI1-B clock source selection + bit_offset: 22 + bit_size: 2 + enum: SAIBSRC + - name: SAI2SRC + description: SAI2 clock source selection + bit_offset: 22 + bit_size: 2 + enum: SAI2SRC + - name: TIMPRE + description: Timers clocks prescalers selection + bit_offset: 24 + bit_size: 1 + enum: TIMPRE + - name: I2S1SRC + description: I2S APB1 clocks source selection (I2S2/3) + bit_offset: 25 + bit_size: 2 + enum: I2S1SRC + - name: I2SSRC + description: I2SSRC + bit_offset: 25 + bit_size: 2 + enum: ISSRC + - name: CK48MSEL + description: 48 MHz clock source selection + bit_offset: 27 + bit_size: 1 + enum: CKMSEL + - name: I2S2SRC + description: I2S APB2 clocks source selection (I2S1/4/5) + bit_offset: 27 + bit_size: 2 + enum: I2S1SRC + - name: SDIOSEL + description: SDIO clock source selection + bit_offset: 28 + bit_size: 1 + enum: SDIOSEL + - name: DSISEL + description: DSI clock source selection + bit_offset: 29 + bit_size: 1 + enum: DSISEL + - name: CKDFSDM1SEL + description: DFSDM1 Kernel clock selection + bit_offset: 31 + bit_size: 1 + enum: CKDFSDMSEL fieldset/DCKCFGR2: description: dedicated clocks configuration register 2 fields: - - name: FMPI2C1SEL - description: FMPI2C1 kernel clock source selection - bit_offset: 22 - bit_size: 2 - enum: FMPICSEL - - name: CECSEL - description: HDMI CEC clock source selection - bit_offset: 26 - bit_size: 1 - enum: CECSEL - - name: CK48MSEL - description: SDIO/USB clock selection - bit_offset: 27 - bit_size: 1 - enum: CKMSEL - - name: SDIOSEL - description: SDIO clock selection - bit_offset: 28 - bit_size: 1 - enum: SDIOSEL - - name: SPDIFRXSEL - description: SPDIF clock selection - bit_offset: 29 - bit_size: 1 - enum: SPDIFRXSEL - - name: LPTIM1SEL - description: LPTIM1SEL - bit_offset: 30 - bit_size: 2 - enum: LPTIMSEL + - name: FMPI2C1SEL + description: FMPI2C1 kernel clock source selection + bit_offset: 22 + bit_size: 2 + enum: FMPICSEL + - name: CECSEL + description: HDMI CEC clock source selection + bit_offset: 26 + bit_size: 1 + enum: CECSEL + - name: CK48MSEL + description: SDIO/USB clock selection + bit_offset: 27 + bit_size: 1 + enum: CKMSEL + - name: SDIOSEL + description: SDIO clock selection + bit_offset: 28 + bit_size: 1 + enum: SDIOSEL + - name: SPDIFRXSEL + description: SPDIF clock selection + bit_offset: 29 + bit_size: 1 + enum: SPDIFRXSEL + - name: LPTIM1SEL + description: LPTIM1SEL + bit_offset: 30 + bit_size: 2 + enum: LPTIMSEL fieldset/PLLCFGR: description: PLL configuration register fields: - - name: PLLM - description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - bit_offset: 0 - bit_size: 6 - - name: PLLN - description: Main PLL (PLL) multiplication factor for VCO - bit_offset: 6 - bit_size: 9 - - name: PLLP - description: Main PLL (PLL) division factor for main system clock - bit_offset: 16 - bit_size: 2 - enum: PLLP - - name: PLLSRC - description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - bit_offset: 22 - bit_size: 1 - enum: PLLSRC - - name: PLLQ - description: "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks" - bit_offset: 24 - bit_size: 4 - - name: PLLR - description: PLL division factor for I2S and System clocks - bit_offset: 28 - bit_size: 3 + - name: PLLM + description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + bit_offset: 0 + bit_size: 6 + - name: PLLN + description: Main PLL (PLL) multiplication factor for VCO + bit_offset: 6 + bit_size: 9 + - name: PLLP + description: Main PLL (PLL) division factor for main system clock + bit_offset: 16 + bit_size: 2 + enum: PLLP + - name: PLLSRC + description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + bit_offset: 22 + bit_size: 1 + enum: PLLSRC + - name: PLLQ + description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + bit_offset: 24 + bit_size: 4 + - name: PLLR + description: PLL division factor for I2S and System clocks + bit_offset: 28 + bit_size: 3 fieldset/PLLI2SCFGR: description: PLLI2S configuration register fields: - - name: PLLI2SM - description: Division factor for the audio PLL (PLLI2S) input clock - bit_offset: 0 - bit_size: 6 - - name: PLLI2SN - description: PLLI2S multiplication factor for VCO - bit_offset: 6 - bit_size: 9 - - name: PLLI2SP - description: PLLI2S division factor for SPDIF-IN clock - bit_offset: 16 - bit_size: 2 - enum: PLLISP - - name: PLLI2SSRC - description: PLLI2S entry clock source - bit_offset: 22 - bit_size: 1 - enum: PLLISSRC - - name: PLLI2SQ - description: PLLI2S division factor for USB OTG FS/SDIO/RNG clock - bit_offset: 24 - bit_size: 4 - - name: PLLI2SR - description: PLLI2S division factor for I2S clocks - bit_offset: 28 - bit_size: 3 + - name: PLLI2SM + description: Division factor for the audio PLL (PLLI2S) input clock + bit_offset: 0 + bit_size: 6 + - name: PLLI2SN + description: PLLI2S multiplication factor for VCO + bit_offset: 6 + bit_size: 9 + - name: PLLI2SP + description: PLLI2S division factor for SPDIF-IN clock + bit_offset: 16 + bit_size: 2 + enum: PLLISP + - name: PLLI2SSRC + description: PLLI2S entry clock source + bit_offset: 22 + bit_size: 1 + enum: PLLISSRC + - name: PLLI2SQ + description: PLLI2S division factor for USB OTG FS/SDIO/RNG clock + bit_offset: 24 + bit_size: 4 + - name: PLLI2SR + description: PLLI2S division factor for I2S clocks + bit_offset: 28 + bit_size: 3 fieldset/PLLSAICFGR: description: PLL configuration register fields: - - name: PLLSAIM - description: Division factor for audio PLLSAI input clock - bit_offset: 0 - bit_size: 6 - - name: PLLSAIN - description: PLLSAI division factor for VCO - bit_offset: 6 - bit_size: 9 - - name: PLLSAIP - description: PLLSAI division factor for 48 MHz clock - bit_offset: 16 - bit_size: 2 - enum: PLLSAIP - - name: PLLSAIQ - description: PLLSAI division factor for SAI1 clock - bit_offset: 24 - bit_size: 4 - - name: PLLSAIR - description: PLLSAI division factor for LCD clock - bit_offset: 28 - bit_size: 3 + - name: PLLSAIM + description: Division factor for audio PLLSAI input clock + bit_offset: 0 + bit_size: 6 + - name: PLLSAIN + description: PLLSAI division factor for VCO + bit_offset: 6 + bit_size: 9 + - name: PLLSAIP + description: PLLSAI division factor for 48 MHz clock + bit_offset: 16 + bit_size: 2 + enum: PLLSAIP + - name: PLLSAIQ + description: PLLSAI division factor for SAI1 clock + bit_offset: 24 + bit_size: 4 + - name: PLLSAIR + description: PLLSAI division factor for LCD clock + bit_offset: 28 + bit_size: 3 fieldset/SSCGR: description: spread spectrum clock generation register fields: - - name: MODPER - description: Modulation period - bit_offset: 0 - bit_size: 13 - - name: INCSTEP - description: Incrementation step - bit_offset: 13 - bit_size: 15 - - name: SPREADSEL - description: Spread Select - bit_offset: 30 - bit_size: 1 - enum: SPREADSEL - - name: SSCGEN - description: Spread spectrum modulation enable - bit_offset: 31 - bit_size: 1 + - name: MODPER + description: Modulation period + bit_offset: 0 + bit_size: 13 + - name: INCSTEP + description: Incrementation step + bit_offset: 13 + bit_size: 15 + - name: SPREADSEL + description: Spread Select + bit_offset: 30 + bit_size: 1 + enum: SPREADSEL + - name: SSCGEN + description: Spread spectrum modulation enable + bit_offset: 31 + bit_size: 1 enum/CECSEL: bit_size: 1 variants: - - name: LSE - description: LSE clock is selected as HDMI-CEC clock - value: 0 - - name: HSI_Div488 - description: HSI divided by 488 clock is selected as HDMI-CEC clock - value: 1 + - name: LSE + description: LSE clock is selected as HDMI-CEC clock + value: 0 + - name: HSI_Div488 + description: HSI divided by 488 clock is selected as HDMI-CEC clock + value: 1 enum/CKDFSDMASEL: bit_size: 1 variants: - - name: I2S1 - description: CK_I2S_APB1 selected as audio clock - value: 0 - - name: I2S2 - description: CK_I2S_APB2 selected as audio clock - value: 1 + - name: I2S1 + description: CK_I2S_APB1 selected as audio clock + value: 0 + - name: I2S2 + description: CK_I2S_APB2 selected as audio clock + value: 1 enum/CKDFSDMSEL: bit_size: 1 variants: - - name: APB2 - description: APB2 clock used as Kernel clock - value: 0 - - name: SYSCLK - description: System clock used as Kernel clock - value: 1 + - name: APB2 + description: APB2 clock used as Kernel clock + value: 0 + - name: SYSCLK + description: System clock used as Kernel clock + value: 1 enum/CKMSEL: bit_size: 1 variants: - - name: PLL - description: 48MHz clock from PLL is selected - value: 0 - - name: PLLSAI - description: 48MHz clock from PLLSAI is selected - value: 1 + - name: PLL + description: 48MHz clock from PLL is selected + value: 0 + - name: PLLSAI + description: 48MHz clock from PLLSAI is selected + value: 1 enum/DSISEL: bit_size: 1 variants: - - name: DSI_PHY - description: DSI-PHY used as DSI byte lane clock source (usual case) - value: 0 - - name: PLLR - description: "PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)" - value: 1 + - name: DSI_PHY + description: DSI-PHY used as DSI byte lane clock source (usual case) + value: 0 + - name: PLLR + description: PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode) + value: 1 enum/FMPICSEL: bit_size: 2 variants: - - name: APB - description: APB clock selected as I2C clock - value: 0 - - name: SYSCLK - description: System clock selected as I2C clock - value: 1 - - name: HSI - description: HSI clock selected as I2C clock - value: 2 + - name: APB + description: APB clock selected as I2C clock + value: 0 + - name: SYSCLK + description: System clock selected as I2C clock + value: 1 + - name: HSI + description: HSI clock selected as I2C clock + value: 2 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: SYSCLK not divided - value: 0 - - name: Div2 - description: SYSCLK divided by 2 - value: 8 - - name: Div4 - description: SYSCLK divided by 4 - value: 9 - - name: Div8 - description: SYSCLK divided by 8 - value: 10 - - name: Div16 - description: SYSCLK divided by 16 - value: 11 - - name: Div64 - description: SYSCLK divided by 64 - value: 12 - - name: Div128 - description: SYSCLK divided by 128 - value: 13 - - name: Div256 - description: SYSCLK divided by 256 - value: 14 - - name: Div512 - description: SYSCLK divided by 512 - value: 15 + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 enum/I2S1SRC: bit_size: 2 variants: - - name: PLLI2SR - description: I2Sx clock frequency = f(PLLI2S_R) - value: 0 - - name: I2S_CKIN - description: I2Sx clock frequency = I2S_CKIN Alternate function input frequency - value: 1 - - name: PLLR - description: I2Sx clock frequency = f(PLL_R) - value: 2 - - name: HSI_HSE - description: "I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])" - value: 3 + - name: PLLI2SR + description: I2Sx clock frequency = f(PLLI2S_R) + value: 0 + - name: I2S_CKIN + description: I2Sx clock frequency = I2S_CKIN Alternate function input frequency + value: 1 + - name: PLLR + description: I2Sx clock frequency = f(PLL_R) + value: 2 + - name: HSI_HSE + description: I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22]) + value: 3 enum/ISSRC: bit_size: 1 variants: - - name: PLLI2S - description: PLLI2S clock used as I2S clock source - value: 0 - - name: CKIN - description: External clock mapped on the I2S_CKIN pin used as I2S clock source - value: 1 + - name: PLLI2S + description: PLLI2S clock used as I2S clock source + value: 0 + - name: CKIN + description: External clock mapped on the I2S_CKIN pin used as I2S clock source + value: 1 enum/LPTIMSEL: bit_size: 2 variants: - - name: APB1 - description: APB1 clock (PCLK1) selected as LPTILM1 clock - value: 0 - - name: LSI - description: LSI clock is selected as LPTILM1 clock - value: 1 - - name: HSI - description: HSI clock is selected as LPTILM1 clock - value: 2 - - name: LSE - description: LSE clock is selected as LPTILM1 clock - value: 3 + - name: APB1 + description: APB1 clock (PCLK1) selected as LPTILM1 clock + value: 0 + - name: LSI + description: LSI clock is selected as LPTILM1 clock + value: 1 + - name: HSI + description: HSI clock is selected as LPTILM1 clock + value: 2 + - name: LSE + description: LSE clock is selected as LPTILM1 clock + value: 3 enum/LSEMOD: bit_size: 1 variants: - - name: Low - description: LSE oscillator low power mode selection - value: 0 - - name: High - description: LSE oscillator high drive mode selection - value: 1 + - name: Low + description: LSE oscillator low power mode selection + value: 0 + - name: High + description: LSE oscillator high drive mode selection + value: 1 enum/MCO1: bit_size: 2 variants: - - name: HSI - description: HSI clock selected - value: 0 - - name: LSE - description: LSE oscillator selected - value: 1 - - name: HSE - description: HSE oscillator clock selected - value: 2 - - name: PLL - description: PLL clock selected - value: 3 + - name: HSI + description: HSI clock selected + value: 0 + - name: LSE + description: LSE oscillator selected + value: 1 + - name: HSE + description: HSE oscillator clock selected + value: 2 + - name: PLL + description: PLL clock selected + value: 3 enum/MCO2: bit_size: 2 variants: - - name: SYSCLK - description: System clock (SYSCLK) selected - value: 0 - - name: PLLI2S - description: PLLI2S clock selected - value: 1 - - name: HSE - description: HSE oscillator clock selected - value: 2 - - name: PLL - description: PLL clock selected - value: 3 + - name: SYSCLK + description: System clock (SYSCLK) selected + value: 0 + - name: PLLI2S + description: PLLI2S clock selected + value: 1 + - name: HSE + description: HSE oscillator clock selected + value: 2 + - name: PLL + description: PLL clock selected + value: 3 enum/MCOPRE: bit_size: 3 variants: - - name: Div1 - description: No division - value: 0 - - name: Div2 - description: Division by 2 - value: 4 - - name: Div3 - description: Division by 3 - value: 5 - - name: Div4 - description: Division by 4 - value: 6 - - name: Div5 - description: Division by 5 - value: 7 + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 4 + - name: Div3 + description: Division by 3 + value: 5 + - name: Div4 + description: Division by 4 + value: 6 + - name: Div5 + description: Division by 5 + value: 7 enum/PLLDIVR: bit_size: 5 variants: - - name: Div1 - description: PLLSAIDIVQ = /1 - value: 0 - - name: Div2 - description: PLLSAIDIVQ = /2 - value: 1 - - name: Div3 - description: PLLSAIDIVQ = /3 - value: 2 - - name: Div4 - description: PLLSAIDIVQ = /4 - value: 3 - - name: Div5 - description: PLLSAIDIVQ = /5 - value: 4 - - name: Div6 - description: PLLSAIDIVQ = /6 - value: 5 - - name: Div7 - description: PLLSAIDIVQ = /7 - value: 6 - - name: Div8 - description: PLLSAIDIVQ = /8 - value: 7 - - name: Div9 - description: PLLSAIDIVQ = /9 - value: 8 - - name: Div10 - description: PLLSAIDIVQ = /10 - value: 9 - - name: Div11 - description: PLLSAIDIVQ = /11 - value: 10 - - name: Div12 - description: PLLSAIDIVQ = /12 - value: 11 - - name: Div13 - description: PLLSAIDIVQ = /13 - value: 12 - - name: Div14 - description: PLLSAIDIVQ = /14 - value: 13 - - name: Div15 - description: PLLSAIDIVQ = /15 - value: 14 - - name: Div16 - description: PLLSAIDIVQ = /16 - value: 15 - - name: Div17 - description: PLLSAIDIVQ = /17 - value: 16 - - name: Div18 - description: PLLSAIDIVQ = /18 - value: 17 - - name: Div19 - description: PLLSAIDIVQ = /19 - value: 18 - - name: Div20 - description: PLLSAIDIVQ = /20 - value: 19 - - name: Div21 - description: PLLSAIDIVQ = /21 - value: 20 - - name: Div22 - description: PLLSAIDIVQ = /22 - value: 21 - - name: Div23 - description: PLLSAIDIVQ = /23 - value: 22 - - name: Div24 - description: PLLSAIDIVQ = /24 - value: 23 - - name: Div25 - description: PLLSAIDIVQ = /25 - value: 24 - - name: Div26 - description: PLLSAIDIVQ = /26 - value: 25 - - name: Div27 - description: PLLSAIDIVQ = /27 - value: 26 - - name: Div28 - description: PLLSAIDIVQ = /28 - value: 27 - - name: Div29 - description: PLLSAIDIVQ = /29 - value: 28 - - name: Div30 - description: PLLSAIDIVQ = /30 - value: 29 - - name: Div31 - description: PLLSAIDIVQ = /31 - value: 30 - - name: Div32 - description: PLLSAIDIVQ = /32 - value: 31 + - name: Div1 + description: PLLSAIDIVQ = /1 + value: 0 + - name: Div2 + description: PLLSAIDIVQ = /2 + value: 1 + - name: Div3 + description: PLLSAIDIVQ = /3 + value: 2 + - name: Div4 + description: PLLSAIDIVQ = /4 + value: 3 + - name: Div5 + description: PLLSAIDIVQ = /5 + value: 4 + - name: Div6 + description: PLLSAIDIVQ = /6 + value: 5 + - name: Div7 + description: PLLSAIDIVQ = /7 + value: 6 + - name: Div8 + description: PLLSAIDIVQ = /8 + value: 7 + - name: Div9 + description: PLLSAIDIVQ = /9 + value: 8 + - name: Div10 + description: PLLSAIDIVQ = /10 + value: 9 + - name: Div11 + description: PLLSAIDIVQ = /11 + value: 10 + - name: Div12 + description: PLLSAIDIVQ = /12 + value: 11 + - name: Div13 + description: PLLSAIDIVQ = /13 + value: 12 + - name: Div14 + description: PLLSAIDIVQ = /14 + value: 13 + - name: Div15 + description: PLLSAIDIVQ = /15 + value: 14 + - name: Div16 + description: PLLSAIDIVQ = /16 + value: 15 + - name: Div17 + description: PLLSAIDIVQ = /17 + value: 16 + - name: Div18 + description: PLLSAIDIVQ = /18 + value: 17 + - name: Div19 + description: PLLSAIDIVQ = /19 + value: 18 + - name: Div20 + description: PLLSAIDIVQ = /20 + value: 19 + - name: Div21 + description: PLLSAIDIVQ = /21 + value: 20 + - name: Div22 + description: PLLSAIDIVQ = /22 + value: 21 + - name: Div23 + description: PLLSAIDIVQ = /23 + value: 22 + - name: Div24 + description: PLLSAIDIVQ = /24 + value: 23 + - name: Div25 + description: PLLSAIDIVQ = /25 + value: 24 + - name: Div26 + description: PLLSAIDIVQ = /26 + value: 25 + - name: Div27 + description: PLLSAIDIVQ = /27 + value: 26 + - name: Div28 + description: PLLSAIDIVQ = /28 + value: 27 + - name: Div29 + description: PLLSAIDIVQ = /29 + value: 28 + - name: Div30 + description: PLLSAIDIVQ = /30 + value: 29 + - name: Div31 + description: PLLSAIDIVQ = /31 + value: 30 + - name: Div32 + description: PLLSAIDIVQ = /32 + value: 31 enum/PLLISDIVQ: bit_size: 5 variants: - - name: Div1 - description: PLLI2SDIVQ = /1 - value: 0 - - name: Div2 - description: PLLI2SDIVQ = /2 - value: 1 - - name: Div3 - description: PLLI2SDIVQ = /3 - value: 2 - - name: Div4 - description: PLLI2SDIVQ = /4 - value: 3 - - name: Div5 - description: PLLI2SDIVQ = /5 - value: 4 - - name: Div6 - description: PLLI2SDIVQ = /6 - value: 5 - - name: Div7 - description: PLLI2SDIVQ = /7 - value: 6 - - name: Div8 - description: PLLI2SDIVQ = /8 - value: 7 - - name: Div9 - description: PLLI2SDIVQ = /9 - value: 8 - - name: Div10 - description: PLLI2SDIVQ = /10 - value: 9 - - name: Div11 - description: PLLI2SDIVQ = /11 - value: 10 - - name: Div12 - description: PLLI2SDIVQ = /12 - value: 11 - - name: Div13 - description: PLLI2SDIVQ = /13 - value: 12 - - name: Div14 - description: PLLI2SDIVQ = /14 - value: 13 - - name: Div15 - description: PLLI2SDIVQ = /15 - value: 14 - - name: Div16 - description: PLLI2SDIVQ = /16 - value: 15 - - name: Div17 - description: PLLI2SDIVQ = /17 - value: 16 - - name: Div18 - description: PLLI2SDIVQ = /18 - value: 17 - - name: Div19 - description: PLLI2SDIVQ = /19 - value: 18 - - name: Div20 - description: PLLI2SDIVQ = /20 - value: 19 - - name: Div21 - description: PLLI2SDIVQ = /21 - value: 20 - - name: Div22 - description: PLLI2SDIVQ = /22 - value: 21 - - name: Div23 - description: PLLI2SDIVQ = /23 - value: 22 - - name: Div24 - description: PLLI2SDIVQ = /24 - value: 23 - - name: Div25 - description: PLLI2SDIVQ = /25 - value: 24 - - name: Div26 - description: PLLI2SDIVQ = /26 - value: 25 - - name: Div27 - description: PLLI2SDIVQ = /27 - value: 26 - - name: Div28 - description: PLLI2SDIVQ = /28 - value: 27 - - name: Div29 - description: PLLI2SDIVQ = /29 - value: 28 - - name: Div30 - description: PLLI2SDIVQ = /30 - value: 29 - - name: Div31 - description: PLLI2SDIVQ = /31 - value: 30 - - name: Div32 - description: PLLI2SDIVQ = /32 - value: 31 + - name: Div1 + description: PLLI2SDIVQ = /1 + value: 0 + - name: Div2 + description: PLLI2SDIVQ = /2 + value: 1 + - name: Div3 + description: PLLI2SDIVQ = /3 + value: 2 + - name: Div4 + description: PLLI2SDIVQ = /4 + value: 3 + - name: Div5 + description: PLLI2SDIVQ = /5 + value: 4 + - name: Div6 + description: PLLI2SDIVQ = /6 + value: 5 + - name: Div7 + description: PLLI2SDIVQ = /7 + value: 6 + - name: Div8 + description: PLLI2SDIVQ = /8 + value: 7 + - name: Div9 + description: PLLI2SDIVQ = /9 + value: 8 + - name: Div10 + description: PLLI2SDIVQ = /10 + value: 9 + - name: Div11 + description: PLLI2SDIVQ = /11 + value: 10 + - name: Div12 + description: PLLI2SDIVQ = /12 + value: 11 + - name: Div13 + description: PLLI2SDIVQ = /13 + value: 12 + - name: Div14 + description: PLLI2SDIVQ = /14 + value: 13 + - name: Div15 + description: PLLI2SDIVQ = /15 + value: 14 + - name: Div16 + description: PLLI2SDIVQ = /16 + value: 15 + - name: Div17 + description: PLLI2SDIVQ = /17 + value: 16 + - name: Div18 + description: PLLI2SDIVQ = /18 + value: 17 + - name: Div19 + description: PLLI2SDIVQ = /19 + value: 18 + - name: Div20 + description: PLLI2SDIVQ = /20 + value: 19 + - name: Div21 + description: PLLI2SDIVQ = /21 + value: 20 + - name: Div22 + description: PLLI2SDIVQ = /22 + value: 21 + - name: Div23 + description: PLLI2SDIVQ = /23 + value: 22 + - name: Div24 + description: PLLI2SDIVQ = /24 + value: 23 + - name: Div25 + description: PLLI2SDIVQ = /25 + value: 24 + - name: Div26 + description: PLLI2SDIVQ = /26 + value: 25 + - name: Div27 + description: PLLI2SDIVQ = /27 + value: 26 + - name: Div28 + description: PLLI2SDIVQ = /28 + value: 27 + - name: Div29 + description: PLLI2SDIVQ = /29 + value: 28 + - name: Div30 + description: PLLI2SDIVQ = /30 + value: 29 + - name: Div31 + description: PLLI2SDIVQ = /31 + value: 30 + - name: Div32 + description: PLLI2SDIVQ = /32 + value: 31 enum/PLLISDIVR: bit_size: 5 variants: - - name: Div1 - description: PLLI2SDIVQ = /1 - value: 0 - - name: Div2 - description: PLLI2SDIVQ = /2 - value: 1 - - name: Div3 - description: PLLI2SDIVQ = /3 - value: 2 - - name: Div4 - description: PLLI2SDIVQ = /4 - value: 3 - - name: Div5 - description: PLLI2SDIVQ = /5 - value: 4 - - name: Div6 - description: PLLI2SDIVQ = /6 - value: 5 - - name: Div7 - description: PLLI2SDIVQ = /7 - value: 6 - - name: Div8 - description: PLLI2SDIVQ = /8 - value: 7 - - name: Div9 - description: PLLI2SDIVQ = /9 - value: 8 - - name: Div10 - description: PLLI2SDIVQ = /10 - value: 9 - - name: Div11 - description: PLLI2SDIVQ = /11 - value: 10 - - name: Div12 - description: PLLI2SDIVQ = /12 - value: 11 - - name: Div13 - description: PLLI2SDIVQ = /13 - value: 12 - - name: Div14 - description: PLLI2SDIVQ = /14 - value: 13 - - name: Div15 - description: PLLI2SDIVQ = /15 - value: 14 - - name: Div16 - description: PLLI2SDIVQ = /16 - value: 15 - - name: Div17 - description: PLLI2SDIVQ = /17 - value: 16 - - name: Div18 - description: PLLI2SDIVQ = /18 - value: 17 - - name: Div19 - description: PLLI2SDIVQ = /19 - value: 18 - - name: Div20 - description: PLLI2SDIVQ = /20 - value: 19 - - name: Div21 - description: PLLI2SDIVQ = /21 - value: 20 - - name: Div22 - description: PLLI2SDIVQ = /22 - value: 21 - - name: Div23 - description: PLLI2SDIVQ = /23 - value: 22 - - name: Div24 - description: PLLI2SDIVQ = /24 - value: 23 - - name: Div25 - description: PLLI2SDIVQ = /25 - value: 24 - - name: Div26 - description: PLLI2SDIVQ = /26 - value: 25 - - name: Div27 - description: PLLI2SDIVQ = /27 - value: 26 - - name: Div28 - description: PLLI2SDIVQ = /28 - value: 27 - - name: Div29 - description: PLLI2SDIVQ = /29 - value: 28 - - name: Div30 - description: PLLI2SDIVQ = /30 - value: 29 - - name: Div31 - description: PLLI2SDIVQ = /31 - value: 30 - - name: Div32 - description: PLLI2SDIVQ = /32 - value: 31 + - name: Div1 + description: PLLI2SDIVQ = /1 + value: 0 + - name: Div2 + description: PLLI2SDIVQ = /2 + value: 1 + - name: Div3 + description: PLLI2SDIVQ = /3 + value: 2 + - name: Div4 + description: PLLI2SDIVQ = /4 + value: 3 + - name: Div5 + description: PLLI2SDIVQ = /5 + value: 4 + - name: Div6 + description: PLLI2SDIVQ = /6 + value: 5 + - name: Div7 + description: PLLI2SDIVQ = /7 + value: 6 + - name: Div8 + description: PLLI2SDIVQ = /8 + value: 7 + - name: Div9 + description: PLLI2SDIVQ = /9 + value: 8 + - name: Div10 + description: PLLI2SDIVQ = /10 + value: 9 + - name: Div11 + description: PLLI2SDIVQ = /11 + value: 10 + - name: Div12 + description: PLLI2SDIVQ = /12 + value: 11 + - name: Div13 + description: PLLI2SDIVQ = /13 + value: 12 + - name: Div14 + description: PLLI2SDIVQ = /14 + value: 13 + - name: Div15 + description: PLLI2SDIVQ = /15 + value: 14 + - name: Div16 + description: PLLI2SDIVQ = /16 + value: 15 + - name: Div17 + description: PLLI2SDIVQ = /17 + value: 16 + - name: Div18 + description: PLLI2SDIVQ = /18 + value: 17 + - name: Div19 + description: PLLI2SDIVQ = /19 + value: 18 + - name: Div20 + description: PLLI2SDIVQ = /20 + value: 19 + - name: Div21 + description: PLLI2SDIVQ = /21 + value: 20 + - name: Div22 + description: PLLI2SDIVQ = /22 + value: 21 + - name: Div23 + description: PLLI2SDIVQ = /23 + value: 22 + - name: Div24 + description: PLLI2SDIVQ = /24 + value: 23 + - name: Div25 + description: PLLI2SDIVQ = /25 + value: 24 + - name: Div26 + description: PLLI2SDIVQ = /26 + value: 25 + - name: Div27 + description: PLLI2SDIVQ = /27 + value: 26 + - name: Div28 + description: PLLI2SDIVQ = /28 + value: 27 + - name: Div29 + description: PLLI2SDIVQ = /29 + value: 28 + - name: Div30 + description: PLLI2SDIVQ = /30 + value: 29 + - name: Div31 + description: PLLI2SDIVQ = /31 + value: 30 + - name: Div32 + description: PLLI2SDIVQ = /32 + value: 31 enum/PLLISP: bit_size: 2 variants: - - name: Div2 - description: PLL*P=2 - value: 0 - - name: Div4 - description: PLL*P=4 - value: 1 - - name: Div6 - description: PLL*P=6 - value: 2 - - name: Div8 - description: PLL*P=8 - value: 3 + - name: Div2 + description: PLL*P=2 + value: 0 + - name: Div4 + description: PLL*P=4 + value: 1 + - name: Div6 + description: PLL*P=6 + value: 2 + - name: Div8 + description: PLL*P=8 + value: 3 enum/PLLISSRC: bit_size: 1 variants: - - name: HSE_HSI - description: HSE or HSI depending on PLLSRC of PLLCFGR - value: 0 - - name: External - description: External AFI clock (CK_PLLI2S_EXT) selected as PLL clock entry - value: 1 + - name: HSE_HSI + description: HSE or HSI depending on PLLSRC of PLLCFGR + value: 0 + - name: External + description: External AFI clock (CK_PLLI2S_EXT) selected as PLL clock entry + value: 1 enum/PLLP: bit_size: 2 variants: - - name: Div2 - description: PLLP=2 - value: 0 - - name: Div4 - description: PLLP=4 - value: 1 - - name: Div6 - description: PLLP=6 - value: 2 - - name: Div8 - description: PLLP=8 - value: 3 + - name: Div2 + description: PLLP=2 + value: 0 + - name: Div4 + description: PLLP=4 + value: 1 + - name: Div6 + description: PLLP=6 + value: 2 + - name: Div8 + description: PLLP=8 + value: 3 enum/PLLSAIDIVQ: bit_size: 5 variants: - - name: Div1 - description: PLLSAIDIVQ = /1 - value: 0 - - name: Div2 - description: PLLSAIDIVQ = /2 - value: 1 - - name: Div3 - description: PLLSAIDIVQ = /3 - value: 2 - - name: Div4 - description: PLLSAIDIVQ = /4 - value: 3 - - name: Div5 - description: PLLSAIDIVQ = /5 - value: 4 - - name: Div6 - description: PLLSAIDIVQ = /6 - value: 5 - - name: Div7 - description: PLLSAIDIVQ = /7 - value: 6 - - name: Div8 - description: PLLSAIDIVQ = /8 - value: 7 - - name: Div9 - description: PLLSAIDIVQ = /9 - value: 8 - - name: Div10 - description: PLLSAIDIVQ = /10 - value: 9 - - name: Div11 - description: PLLSAIDIVQ = /11 - value: 10 - - name: Div12 - description: PLLSAIDIVQ = /12 - value: 11 - - name: Div13 - description: PLLSAIDIVQ = /13 - value: 12 - - name: Div14 - description: PLLSAIDIVQ = /14 - value: 13 - - name: Div15 - description: PLLSAIDIVQ = /15 - value: 14 - - name: Div16 - description: PLLSAIDIVQ = /16 - value: 15 - - name: Div17 - description: PLLSAIDIVQ = /17 - value: 16 - - name: Div18 - description: PLLSAIDIVQ = /18 - value: 17 - - name: Div19 - description: PLLSAIDIVQ = /19 - value: 18 - - name: Div20 - description: PLLSAIDIVQ = /20 - value: 19 - - name: Div21 - description: PLLSAIDIVQ = /21 - value: 20 - - name: Div22 - description: PLLSAIDIVQ = /22 - value: 21 - - name: Div23 - description: PLLSAIDIVQ = /23 - value: 22 - - name: Div24 - description: PLLSAIDIVQ = /24 - value: 23 - - name: Div25 - description: PLLSAIDIVQ = /25 - value: 24 - - name: Div26 - description: PLLSAIDIVQ = /26 - value: 25 - - name: Div27 - description: PLLSAIDIVQ = /27 - value: 26 - - name: Div28 - description: PLLSAIDIVQ = /28 - value: 27 - - name: Div29 - description: PLLSAIDIVQ = /29 - value: 28 - - name: Div30 - description: PLLSAIDIVQ = /30 - value: 29 - - name: Div31 - description: PLLSAIDIVQ = /31 - value: 30 - - name: Div32 - description: PLLSAIDIVQ = /32 - value: 31 + - name: Div1 + description: PLLSAIDIVQ = /1 + value: 0 + - name: Div2 + description: PLLSAIDIVQ = /2 + value: 1 + - name: Div3 + description: PLLSAIDIVQ = /3 + value: 2 + - name: Div4 + description: PLLSAIDIVQ = /4 + value: 3 + - name: Div5 + description: PLLSAIDIVQ = /5 + value: 4 + - name: Div6 + description: PLLSAIDIVQ = /6 + value: 5 + - name: Div7 + description: PLLSAIDIVQ = /7 + value: 6 + - name: Div8 + description: PLLSAIDIVQ = /8 + value: 7 + - name: Div9 + description: PLLSAIDIVQ = /9 + value: 8 + - name: Div10 + description: PLLSAIDIVQ = /10 + value: 9 + - name: Div11 + description: PLLSAIDIVQ = /11 + value: 10 + - name: Div12 + description: PLLSAIDIVQ = /12 + value: 11 + - name: Div13 + description: PLLSAIDIVQ = /13 + value: 12 + - name: Div14 + description: PLLSAIDIVQ = /14 + value: 13 + - name: Div15 + description: PLLSAIDIVQ = /15 + value: 14 + - name: Div16 + description: PLLSAIDIVQ = /16 + value: 15 + - name: Div17 + description: PLLSAIDIVQ = /17 + value: 16 + - name: Div18 + description: PLLSAIDIVQ = /18 + value: 17 + - name: Div19 + description: PLLSAIDIVQ = /19 + value: 18 + - name: Div20 + description: PLLSAIDIVQ = /20 + value: 19 + - name: Div21 + description: PLLSAIDIVQ = /21 + value: 20 + - name: Div22 + description: PLLSAIDIVQ = /22 + value: 21 + - name: Div23 + description: PLLSAIDIVQ = /23 + value: 22 + - name: Div24 + description: PLLSAIDIVQ = /24 + value: 23 + - name: Div25 + description: PLLSAIDIVQ = /25 + value: 24 + - name: Div26 + description: PLLSAIDIVQ = /26 + value: 25 + - name: Div27 + description: PLLSAIDIVQ = /27 + value: 26 + - name: Div28 + description: PLLSAIDIVQ = /28 + value: 27 + - name: Div29 + description: PLLSAIDIVQ = /29 + value: 28 + - name: Div30 + description: PLLSAIDIVQ = /30 + value: 29 + - name: Div31 + description: PLLSAIDIVQ = /31 + value: 30 + - name: Div32 + description: PLLSAIDIVQ = /32 + value: 31 enum/PLLSAIDIVR: bit_size: 2 variants: - - name: Div2 - description: PLLSAIDIVR = /2 - value: 0 - - name: Div4 - description: PLLSAIDIVR = /4 - value: 1 - - name: Div8 - description: PLLSAIDIVR = /8 - value: 2 - - name: Div16 - description: PLLSAIDIVR = /16 - value: 3 + - name: Div2 + description: PLLSAIDIVR = /2 + value: 0 + - name: Div4 + description: PLLSAIDIVR = /4 + value: 1 + - name: Div8 + description: PLLSAIDIVR = /8 + value: 2 + - name: Div16 + description: PLLSAIDIVR = /16 + value: 3 enum/PLLSAIP: bit_size: 2 variants: - - name: Div2 - description: PLL*P=2 - value: 0 - - name: Div4 - description: PLL*P=4 - value: 1 - - name: Div6 - description: PLL*P=6 - value: 2 - - name: Div8 - description: PLL*P=8 - value: 3 + - name: Div2 + description: PLL*P=2 + value: 0 + - name: Div4 + description: PLL*P=4 + value: 1 + - name: Div6 + description: PLL*P=6 + value: 2 + - name: Div8 + description: PLL*P=8 + value: 3 enum/PLLSRC: bit_size: 1 variants: - - name: HSI - description: HSI clock selected as PLL and PLLI2S clock entry - value: 0 - - name: HSE - description: HSE oscillator clock selected as PLL and PLLI2S clock entry - value: 1 + - name: HSI + description: HSI clock selected as PLL and PLLI2S clock entry + value: 0 + - name: HSE + description: HSE oscillator clock selected as PLL and PLLI2S clock entry + value: 1 enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK divided by 2 - value: 4 - - name: Div4 - description: HCLK divided by 4 - value: 5 - - name: Div8 - description: HCLK divided by 8 - value: 6 - - name: Div16 - description: HCLK divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: HSE oscillator clock divided by a prescaler used as RTC clock - value: 3 + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 enum/SAI1SRC: bit_size: 2 variants: - - name: PLLSAI - description: SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - value: 0 - - name: PLLI2S - description: SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - value: 1 - - name: PLLR - description: SAI1 clock frequency = f(PLL_R) - value: 2 - - name: I2S_CKIN - description: I2S_CKIN Alternate function input frequency - value: 3 + - name: PLLSAI + description: SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + value: 0 + - name: PLLI2S + description: SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + value: 1 + - name: PLLR + description: SAI1 clock frequency = f(PLL_R) + value: 2 + - name: I2S_CKIN + description: I2S_CKIN Alternate function input frequency + value: 3 enum/SAI2SRC: bit_size: 2 variants: - - name: PLLSAI - description: SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - value: 0 - - name: PLLI2S - description: SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - value: 1 - - name: PLLR - description: SAI2 clock frequency = f(PLL_R) - value: 2 - - name: HSI_HSE - description: SAI2 clock frequency = Alternate function input frequency - value: 3 + - name: PLLSAI + description: SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + value: 0 + - name: PLLI2S + description: SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + value: 1 + - name: PLLR + description: SAI2 clock frequency = f(PLL_R) + value: 2 + - name: HSI_HSE + description: SAI2 clock frequency = Alternate function input frequency + value: 3 enum/SAIASRC: bit_size: 2 variants: - - name: PLLSAI - description: SAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - value: 0 - - name: PLLI2S - description: SAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - value: 1 - - name: I2S_CKIN - description: SAI1-A clock frequency = Alternate function input frequency - value: 2 + - name: PLLSAI + description: SAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + value: 0 + - name: PLLI2S + description: SAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + value: 1 + - name: I2S_CKIN + description: SAI1-A clock frequency = Alternate function input frequency + value: 2 enum/SAIBSRC: bit_size: 2 variants: - - name: PLLSAI - description: SAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - value: 0 - - name: PLLI2S - description: SAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - value: 1 - - name: I2S_CKIN - description: SAI1-B clock frequency = Alternate function input frequency - value: 2 + - name: PLLSAI + description: SAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + value: 0 + - name: PLLI2S + description: SAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + value: 1 + - name: I2S_CKIN + description: SAI1-B clock frequency = Alternate function input frequency + value: 2 enum/SDIOSEL: bit_size: 1 variants: - - name: CK48M - description: 48 MHz clock is selected as SD clock - value: 0 - - name: SYSCLK - description: System clock is selected as SD clock - value: 1 + - name: CK48M + description: 48 MHz clock is selected as SD clock + value: 0 + - name: SYSCLK + description: System clock is selected as SD clock + value: 1 enum/SPDIFRXSEL: bit_size: 1 variants: - - name: PLL - description: SPDIF-Rx clock from PLL is selected - value: 0 - - name: PLLI2S - description: SPDIF-Rx clock from PLLI2S is selected - value: 1 + - name: PLL + description: SPDIF-Rx clock from PLL is selected + value: 0 + - name: PLLI2S + description: SPDIF-Rx clock from PLLI2S is selected + value: 1 enum/SPREADSEL: bit_size: 1 variants: - - name: Center - description: Center spread - value: 0 - - name: Down - description: Down spread - value: 1 + - name: Center + description: Center spread + value: 0 + - name: Down + description: Down spread + value: 1 enum/SW: bit_size: 2 variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: HSE - description: HSE selected as system clock - value: 1 - - name: PLL - description: PLL selected as system clock - value: 2 -enum/SWS: - bit_size: 2 - variants: - - name: HSI - description: HSI oscillator used as system clock - value: 0 - - name: HSE - description: HSE oscillator used as system clock - value: 1 - - name: PLL - description: PLL used as system clock - value: 2 + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL + description: PLL used as system clock + value: 2 enum/TIMPRE: bit_size: 1 variants: - - name: Mul2 - description: "If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx" - value: 0 - - name: Mul4 - description: "If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx" - value: 1 + - name: Mul2 + description: If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx + value: 0 + - name: Mul4 + description: If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx + value: 1 diff --git a/data/registers/rcc_f410.yaml b/data/registers/rcc_f410.yaml index b65a21e..98ee613 100644 --- a/data/registers/rcc_f410.yaml +++ b/data/registers/rcc_f410.yaml @@ -1,1007 +1,994 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: clock control register - byte_offset: 0 - fieldset: CR - - name: PLLCFGR - description: PLL configuration register - byte_offset: 4 - fieldset: PLLCFGR - - name: CFGR - description: clock configuration register - byte_offset: 8 - fieldset: CFGR - - name: CIR - description: clock interrupt register - byte_offset: 12 - fieldset: CIR - - name: AHB1RSTR - description: AHB1 peripheral reset register - byte_offset: 16 - fieldset: AHB1RSTR - - name: APB1RSTR - description: APB1 peripheral reset register - byte_offset: 32 - fieldset: APB1RSTR - - name: APB2RSTR - description: APB2 peripheral reset register - byte_offset: 36 - fieldset: APB2RSTR - - name: AHB1ENR - description: AHB1 peripheral clock register - byte_offset: 48 - fieldset: AHB1ENR - - name: APB1ENR - description: APB1 peripheral clock enable register - byte_offset: 64 - fieldset: APB1ENR - - name: APB2ENR - description: APB2 peripheral clock enable register - byte_offset: 68 - fieldset: APB2ENR - - name: AHB1LPENR - description: AHB1 peripheral clock enable in low power mode register - byte_offset: 80 - fieldset: AHB1LPENR - - name: APB1LPENR - description: APB1 peripheral clock enable in low power mode register - byte_offset: 96 - fieldset: APB1LPENR - - name: APB2LPENR - description: APB2 peripheral clock enabled in low power mode register - byte_offset: 100 - fieldset: APB2LPENR - - name: BDCR - description: Backup domain control register - byte_offset: 112 - fieldset: BDCR - - name: CSR - description: clock control & status register - byte_offset: 116 - fieldset: CSR - - name: SSCGR - description: spread spectrum clock generation register - byte_offset: 128 - fieldset: SSCGR - - name: DCKCFGR - description: DCKCFGR register - byte_offset: 140 - fieldset: DCKCFGR - - name: DCKCFGR2 - description: DCKCFGR2 register - byte_offset: 148 - fieldset: DCKCFGR2 + - name: CR + description: clock control register + byte_offset: 0 + fieldset: CR + - name: PLLCFGR + description: PLL configuration register + byte_offset: 4 + fieldset: PLLCFGR + - name: CFGR + description: clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: CIR + description: clock interrupt register + byte_offset: 12 + fieldset: CIR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 16 + fieldset: AHB1RSTR + - name: APB1RSTR + description: APB1 peripheral reset register + byte_offset: 32 + fieldset: APB1RSTR + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 36 + fieldset: APB2RSTR + - name: AHB1ENR + description: AHB1 peripheral clock register + byte_offset: 48 + fieldset: AHB1ENR + - name: APB1ENR + description: APB1 peripheral clock enable register + byte_offset: 64 + fieldset: APB1ENR + - name: APB2ENR + description: APB2 peripheral clock enable register + byte_offset: 68 + fieldset: APB2ENR + - name: AHB1LPENR + description: AHB1 peripheral clock enable in low power mode register + byte_offset: 80 + fieldset: AHB1LPENR + - name: APB1LPENR + description: APB1 peripheral clock enable in low power mode register + byte_offset: 96 + fieldset: APB1LPENR + - name: APB2LPENR + description: APB2 peripheral clock enabled in low power mode register + byte_offset: 100 + fieldset: APB2LPENR + - name: BDCR + description: Backup domain control register + byte_offset: 112 + fieldset: BDCR + - name: CSR + description: clock control & status register + byte_offset: 116 + fieldset: CSR + - name: SSCGR + description: spread spectrum clock generation register + byte_offset: 128 + fieldset: SSCGR + - name: DCKCFGR + description: DCKCFGR register + byte_offset: 140 + fieldset: DCKCFGR + - name: DCKCFGR2 + description: DCKCFGR2 register + byte_offset: 148 + fieldset: DCKCFGR2 fieldset/AHB1ENR: description: AHB1 peripheral clock register fields: - - name: GPIOAEN - description: IO port A clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: IO port B clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: IO port C clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIOHEN - description: IO port H clock enable - bit_offset: 7 - bit_size: 1 - - name: CRCEN - description: CRC clock enable - bit_offset: 12 - bit_size: 1 - - name: DMA1EN - description: DMA1 clock enable - bit_offset: 21 - bit_size: 1 - - name: DMA2EN - description: DMA2 clock enable - bit_offset: 22 - bit_size: 1 - - name: RNGEN - description: RNG clock enable - bit_offset: 31 - bit_size: 1 + - name: GPIOAEN + description: IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIOHEN + description: IO port H clock enable + bit_offset: 7 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 21 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 22 + bit_size: 1 + - name: RNGEN + description: RNG clock enable + bit_offset: 31 + bit_size: 1 fieldset/AHB1LPENR: description: AHB1 peripheral clock enable in low power mode register fields: - - name: GPIOALPEN - description: IO port A clock enable during sleep mode - bit_offset: 0 - bit_size: 1 - - name: GPIOBLPEN - description: IO port B clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: GPIOCLPEN - description: IO port C clock enable during Sleep mode - bit_offset: 2 - bit_size: 1 - - name: GPIOHLPEN - description: IO port H clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 - - name: CRCLPEN - description: CRC clock enable during Sleep mode - bit_offset: 12 - bit_size: 1 - - name: FLASHLPEN - description: Flash interface clock enable during Sleep mode - bit_offset: 15 - bit_size: 1 - - name: SRAM1LPEN - description: SRAM 1interface clock enable during Sleep mode - bit_offset: 16 - bit_size: 1 - - name: DMA1LPEN - description: DMA1 clock enable during Sleep mode - bit_offset: 21 - bit_size: 1 - - name: DMA2LPEN - description: DMA2 clock enable during Sleep mode - bit_offset: 22 - bit_size: 1 - - name: RNGLPEN - description: RNG clock enable during sleep mode - bit_offset: 31 - bit_size: 1 + - name: GPIOALPEN + description: IO port A clock enable during sleep mode + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: IO port B clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: IO port C clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: GPIOHLPEN + description: IO port H clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: CRCLPEN + description: CRC clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: FLASHLPEN + description: Flash interface clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: SRAM1LPEN + description: SRAM 1interface clock enable during Sleep mode + bit_offset: 16 + bit_size: 1 + - name: DMA1LPEN + description: DMA1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: DMA2LPEN + description: DMA2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: RNGLPEN + description: RNG clock enable during sleep mode + bit_offset: 31 + bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - - name: GPIOARST - description: IO port A reset - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: IO port B reset - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: IO port C reset - bit_offset: 2 - bit_size: 1 - - name: GPIOHRST - description: IO port H reset - bit_offset: 7 - bit_size: 1 - - name: CRCRST - description: CRC reset - bit_offset: 12 - bit_size: 1 - - name: DMA1RST - description: DMA2 reset - bit_offset: 21 - bit_size: 1 - - name: DMA2RST - description: DMA2 reset - bit_offset: 22 - bit_size: 1 - - name: RNGRST - description: RNGRST - bit_offset: 31 - bit_size: 1 + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 7 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 + - name: DMA1RST + description: DMA2 reset + bit_offset: 21 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 22 + bit_size: 1 + - name: RNGRST + description: RNGRST + bit_offset: 31 + bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register fields: - - name: TIM5EN - description: TIM5 clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: TIM6 clock enable - bit_offset: 4 - bit_size: 1 - - name: LPTIM1EN - description: LPTIM1 clock enable - bit_offset: 9 - bit_size: 1 - - name: RTCAPBEN - description: RTC APB clock enable - bit_offset: 10 - bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI2 clock enable - bit_offset: 14 - bit_size: 1 - - name: USART2EN - description: USART 2 clock enable - bit_offset: 17 - bit_size: 1 - - name: I2C1EN - description: I2C1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C2 clock enable - bit_offset: 22 - bit_size: 1 - - name: FMPI2C1EN - description: FMPI2C1 clock enable - bit_offset: 24 - bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - - name: DACEN - description: DAC interface clock enable - bit_offset: 29 - bit_size: 1 + - name: TIM5EN + description: TIM5 clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM6 clock enable + bit_offset: 4 + bit_size: 1 + - name: LPTIM1EN + description: LPTIM1 clock enable + bit_offset: 9 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable + bit_offset: 22 + bit_size: 1 + - name: FMPI2C1EN + description: FMPI2C1 clock enable + bit_offset: 24 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 fieldset/APB1LPENR: description: APB1 peripheral clock enable in low power mode register fields: - - name: TIM5LPEN - description: TIM5 clock enable during Sleep mode - bit_offset: 3 - bit_size: 1 - - name: TIM6LPEN - description: TIM6 clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: LPTIM1LPEN - description: LPTIM1 clock enable during sleep mode - bit_offset: 9 - bit_size: 1 - - name: RTCAPBLPEN - description: RTC APB clock enable during sleep mode - bit_offset: 10 - bit_size: 1 - - name: WWDGLPEN - description: Window watchdog clock enable during Sleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI2LPEN - description: SPI2 clock enable during Sleep mode - bit_offset: 14 - bit_size: 1 - - name: USART2LPEN - description: USART2 clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: I2C1LPEN - description: I2C1 clock enable during Sleep mode - bit_offset: 21 - bit_size: 1 - - name: I2C2LPEN - description: I2C2 clock enable during Sleep mode - bit_offset: 22 - bit_size: 1 - - name: FMPI2C1LPEN - description: FMPI2C1 clock enable during Sleep - bit_offset: 24 - bit_size: 1 - - name: PWRLPEN - description: Power interface clock enable during Sleep mode - bit_offset: 28 - bit_size: 1 - - name: DACLPEN - description: DAC interface clock enable during sleep mode - bit_offset: 29 - bit_size: 1 + - name: TIM5LPEN + description: TIM5 clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: TIM6LPEN + description: TIM6 clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: LPTIM1LPEN + description: LPTIM1 clock enable during sleep mode + bit_offset: 9 + bit_size: 1 + - name: RTCAPBLPEN + description: RTC APB clock enable during sleep mode + bit_offset: 10 + bit_size: 1 + - name: WWDGLPEN + description: Window watchdog clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI2LPEN + description: SPI2 clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: USART2LPEN + description: USART2 clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: I2C1LPEN + description: I2C1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: I2C2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: FMPI2C1LPEN + description: FMPI2C1 clock enable during Sleep + bit_offset: 24 + bit_size: 1 + - name: PWRLPEN + description: Power interface clock enable during Sleep mode + bit_offset: 28 + bit_size: 1 + - name: DACLPEN + description: DAC interface clock enable during sleep mode + bit_offset: 29 + bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register fields: - - name: TIM5RST - description: TIM5 reset - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: TIM6 reset - bit_offset: 4 - bit_size: 1 - - name: LPTIM1RST - description: LPTIM1 reset - bit_offset: 9 - bit_size: 1 - - name: WWDGRST - description: Window watchdog reset - bit_offset: 11 - bit_size: 1 - - name: SPI2RST - description: SPI 2 reset - bit_offset: 14 - bit_size: 1 - - name: USART2RST - description: USART 2 reset - bit_offset: 17 - bit_size: 1 - - name: I2C1RST - description: I2C 1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C 2 reset - bit_offset: 22 - bit_size: 1 - - name: FMPI2C1RST - description: FMPI2C1 reset - bit_offset: 24 - bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - - name: DACRST - description: DAC reset - bit_offset: 29 - bit_size: 1 + - name: TIM5RST + description: TIM5 reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: TIM6 reset + bit_offset: 4 + bit_size: 1 + - name: LPTIM1RST + description: LPTIM1 reset + bit_offset: 9 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI 2 reset + bit_offset: 14 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: I2C1RST + description: I2C 1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C 2 reset + bit_offset: 22 + bit_size: 1 + - name: FMPI2C1RST + description: FMPI2C1 reset + bit_offset: 24 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC reset + bit_offset: 29 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - - name: TIM1EN - description: TIM1 clock enable - bit_offset: 0 - bit_size: 1 - - name: USART1EN - description: USART1 clock enable - bit_offset: 4 - bit_size: 1 - - name: USART6EN - description: USART6 clock enable - bit_offset: 5 - bit_size: 1 - - name: ADC1EN - description: ADC1 clock enable - bit_offset: 8 - bit_size: 1 - - name: SPI1EN - description: SPI1 clock enable - bit_offset: 12 - bit_size: 1 - - name: SYSCFGEN - description: System configuration controller clock enable - bit_offset: 14 - bit_size: 1 - - name: EXTITEN - description: EXTI ans external IT clock enable - bit_offset: 15 - bit_size: 1 - - name: TIM9EN - description: TIM9 clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM11EN - description: TIM11 clock enable - bit_offset: 18 - bit_size: 1 - - name: SPI5EN - description: SPI5 clock enable - bit_offset: 20 - bit_size: 1 + - name: TIM1EN + description: TIM1 clock enable + bit_offset: 0 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 4 + bit_size: 1 + - name: USART6EN + description: USART6 clock enable + bit_offset: 5 + bit_size: 1 + - name: ADC1EN + description: ADC1 clock enable + bit_offset: 8 + bit_size: 1 + - name: SPI1EN + description: SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: SYSCFGEN + description: System configuration controller clock enable + bit_offset: 14 + bit_size: 1 + - name: EXTITEN + description: EXTI ans external IT clock enable + bit_offset: 15 + bit_size: 1 + - name: TIM9EN + description: TIM9 clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM11EN + description: TIM11 clock enable + bit_offset: 18 + bit_size: 1 + - name: SPI5EN + description: SPI5 clock enable + bit_offset: 20 + bit_size: 1 fieldset/APB2LPENR: description: APB2 peripheral clock enabled in low power mode register fields: - - name: TIM1LPEN - description: TIM1 clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: USART1LPEN - description: USART1 clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: USART6LPEN - description: USART6 clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: ADC1LPEN - description: ADC1 clock enable during Sleep mode - bit_offset: 8 - bit_size: 1 - - name: SDIOLPEN - description: SDIO clock enable during Sleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI1LPEN - description: SPI 1 clock enable during Sleep mode - bit_offset: 12 - bit_size: 1 - - name: SYSCFGLPEN - description: System configuration controller clock enable during Sleep mode - bit_offset: 14 - bit_size: 1 - - name: EXTITLPEN - description: EXTI and External IT clock enable during sleep mode - bit_offset: 15 - bit_size: 1 - - name: TIM9LPEN - description: TIM9 clock enable during sleep mode - bit_offset: 16 - bit_size: 1 - - name: TIM11LPEN - description: TIM11 clock enable during Sleep mode - bit_offset: 18 - bit_size: 1 - - name: SPI5LPEN - description: SPI5 clock enable during Sleep mode - bit_offset: 20 - bit_size: 1 + - name: TIM1LPEN + description: TIM1 clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: USART1LPEN + description: USART1 clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: USART6LPEN + description: USART6 clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: ADC1LPEN + description: ADC1 clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: SDIOLPEN + description: SDIO clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI1LPEN + description: SPI 1 clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: SYSCFGLPEN + description: System configuration controller clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: EXTITLPEN + description: EXTI and External IT clock enable during sleep mode + bit_offset: 15 + bit_size: 1 + - name: TIM9LPEN + description: TIM9 clock enable during sleep mode + bit_offset: 16 + bit_size: 1 + - name: TIM11LPEN + description: TIM11 clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: SPI5LPEN + description: SPI5 clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - - name: TIM1RST - description: TIM1 reset - bit_offset: 0 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 4 - bit_size: 1 - - name: USART6RST - description: USART6 reset - bit_offset: 5 - bit_size: 1 - - name: ADCRST - description: ADC interface reset (common to all ADCs) - bit_offset: 8 - bit_size: 1 - - name: SPI1RST - description: SPI 1 reset - bit_offset: 12 - bit_size: 1 - - name: SYSCFGRST - description: System configuration controller reset - bit_offset: 14 - bit_size: 1 - - name: TIM9RST - description: TIM9 reset - bit_offset: 16 - bit_size: 1 - - name: TIM11RST - description: TIM11 reset - bit_offset: 18 - bit_size: 1 - - name: SPI5RST - description: SPI5 reset - bit_offset: 20 - bit_size: 1 + - name: TIM1RST + description: TIM1 reset + bit_offset: 0 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 4 + bit_size: 1 + - name: USART6RST + description: USART6 reset + bit_offset: 5 + bit_size: 1 + - name: ADCRST + description: ADC interface reset (common to all ADCs) + bit_offset: 8 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: SYSCFGRST + description: System configuration controller reset + bit_offset: 14 + bit_size: 1 + - name: TIM9RST + description: TIM9 reset + bit_offset: 16 + bit_size: 1 + - name: TIM11RST + description: TIM11 reset + bit_offset: 18 + bit_size: 1 + - name: SPI5RST + description: SPI5 reset + bit_offset: 20 + bit_size: 1 fieldset/BDCR: description: Backup domain control register fields: - - name: LSEON - description: External low-speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: External low-speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: External low-speed oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: Backup domain software reset - bit_offset: 16 - bit_size: 1 + - name: LSEON + description: External low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External low-speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: External low-speed oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 fieldset/CFGR: description: clock configuration register fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: System clock switch status - bit_offset: 2 - bit_size: 2 - enum: SWS - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - enum: HPRE - - name: MCO1EN - description: MCO output enable - bit_offset: 8 - bit_size: 1 - - name: MCO2EN - description: MCO output enable - bit_offset: 9 - bit_size: 1 - - name: PPRE1 - description: APB Low speed prescaler (APB1) - bit_offset: 10 - bit_size: 3 - enum: PPRE - - name: PPRE2 - description: APB high-speed prescaler (APB2) - bit_offset: 13 - bit_size: 3 - enum: PPRE - - name: RTCPRE - description: HSE division factor for RTC clock - bit_offset: 16 - bit_size: 5 - - name: MCO1 - description: Microcontroller clock output 1 - bit_offset: 21 - bit_size: 2 - enum: MCO1 - - name: MCO1PRE - description: MCO1 prescaler - bit_offset: 24 - bit_size: 3 - enum: MCOPRE - - name: MCO2PRE - description: MCO2 prescaler - bit_offset: 27 - bit_size: 3 - enum: MCOPRE - - name: MCO2 - description: Microcontroller clock output 2 - bit_offset: 30 - bit_size: 2 - enum: MCO2 + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: MCO1EN + description: MCO output enable + bit_offset: 8 + bit_size: 1 + - name: MCO2EN + description: MCO output enable + bit_offset: 9 + bit_size: 1 + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 10 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high-speed prescaler (APB2) + bit_offset: 13 + bit_size: 3 + enum: PPRE + - name: RTCPRE + description: HSE division factor for RTC clock + bit_offset: 16 + bit_size: 5 + - name: MCO1 + description: Microcontroller clock output 1 + bit_offset: 21 + bit_size: 2 + enum: MCO1 + - name: MCO1PRE + description: MCO1 prescaler + bit_offset: 24 + bit_size: 3 + enum: MCOPRE + - name: MCO2PRE + description: MCO2 prescaler + bit_offset: 27 + bit_size: 3 + enum: MCOPRE + - name: MCO2 + description: Microcontroller clock output 2 + bit_offset: 30 + bit_size: 2 + enum: MCO2 fieldset/CIR: description: clock interrupt register fields: - - name: LSIRDYF - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - - name: HSIRDYF - description: HSI ready interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSERDYF - description: HSE ready interrupt flag - bit_offset: 3 - bit_size: 1 - - name: PLLRDYF - description: Main PLL (PLL) ready interrupt flag - bit_offset: 4 - bit_size: 1 - - name: CSSF - description: Clock security system interrupt flag - bit_offset: 7 - bit_size: 1 - - name: LSIRDYIE - description: LSI ready interrupt enable - bit_offset: 8 - bit_size: 1 - - name: LSERDYIE - description: LSE ready interrupt enable - bit_offset: 9 - bit_size: 1 - - name: HSIRDYIE - description: HSI ready interrupt enable - bit_offset: 10 - bit_size: 1 - - name: HSERDYIE - description: HSE ready interrupt enable - bit_offset: 11 - bit_size: 1 - - name: PLLRDYIE - description: Main PLL (PLL) ready interrupt enable - bit_offset: 12 - bit_size: 1 - - name: LSIRDYC - description: LSI ready interrupt clear - bit_offset: 16 - bit_size: 1 - - name: LSERDYC - description: LSE ready interrupt clear - bit_offset: 17 - bit_size: 1 - - name: HSIRDYC - description: HSI ready interrupt clear - bit_offset: 18 - bit_size: 1 - - name: HSERDYC - description: HSE ready interrupt clear - bit_offset: 19 - bit_size: 1 - - name: PLLRDYC - description: Main PLL(PLL) ready interrupt clear - bit_offset: 20 - bit_size: 1 - - name: PLLI2SRDYC - description: PLLI2S ready interrupt clear - bit_offset: 21 - bit_size: 1 - - name: CSSC - description: Clock security system interrupt clear - bit_offset: 23 - bit_size: 1 + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: Main PLL (PLL) ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: CSSF + description: Clock security system interrupt flag + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: Main PLL (PLL) ready interrupt enable + bit_offset: 12 + bit_size: 1 + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: Main PLL(PLL) ready interrupt clear + bit_offset: 20 + bit_size: 1 + - name: PLLI2SRDYC + description: PLLI2S ready interrupt clear + bit_offset: 21 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 fieldset/CR: description: clock control register fields: - - name: HSION - description: Internal high-speed clock enable - bit_offset: 0 - bit_size: 1 - - name: HSIRDY - description: Internal high-speed clock ready flag - bit_offset: 1 - bit_size: 1 - - name: HSITRIM - description: Internal high-speed clock trimming - bit_offset: 3 - bit_size: 5 - - name: HSICAL - description: Internal high-speed clock calibration - bit_offset: 8 - bit_size: 8 - - name: HSEON - description: HSE clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: HSE clock bypass - bit_offset: 18 - bit_size: 1 - - name: CSSON - description: Clock security system enable - bit_offset: 19 - bit_size: 1 - - name: PLLON - description: Main PLL (PLL) enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: Main PLL (PLL) clock ready flag - bit_offset: 25 - bit_size: 1 + - name: HSION + description: Internal high-speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal high-speed clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSITRIM + description: Internal high-speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal high-speed clock calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: HSE clock bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: Main PLL (PLL) enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL (PLL) clock ready flag + bit_offset: 25 + bit_size: 1 fieldset/CSR: description: clock control & status register fields: - - name: LSION - description: Internal low-speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: Internal low-speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: RMVF - description: Remove reset flag - bit_offset: 24 - bit_size: 1 - - name: BORRSTF - description: BOR reset flag - bit_offset: 25 - bit_size: 1 - - name: PADRSTF - description: PIN reset flag - bit_offset: 26 - bit_size: 1 - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: WDGRSTF - description: Independent watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSION + description: Internal low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low-speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + - name: BORRSTF + description: BOR reset flag + bit_offset: 25 + bit_size: 1 + - name: PADRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: WDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 fieldset/DCKCFGR: description: DCKCFGR register fields: - - name: TIMPRE - description: TIMPRE - bit_offset: 24 - bit_size: 1 - enum: TIMPRE - - name: I2SSRC - description: I2SSRC - bit_offset: 25 - bit_size: 2 - enum: ISSRC + - name: TIMPRE + description: TIMPRE + bit_offset: 24 + bit_size: 1 + enum: TIMPRE + - name: I2SSRC + description: I2SSRC + bit_offset: 25 + bit_size: 2 + enum: ISSRC fieldset/DCKCFGR2: description: DCKCFGR2 register fields: - - name: FMPI2C1SEL - description: FMPI2C1 kernel clock source selection - bit_offset: 22 - bit_size: 2 - enum: FMPICSEL - - name: LPTIM1SEL - description: LPTIM1SEL - bit_offset: 30 - bit_size: 2 - enum: LPTIMSEL + - name: FMPI2C1SEL + description: FMPI2C1 kernel clock source selection + bit_offset: 22 + bit_size: 2 + enum: FMPICSEL + - name: LPTIM1SEL + description: LPTIM1SEL + bit_offset: 30 + bit_size: 2 + enum: LPTIMSEL fieldset/PLLCFGR: description: PLL configuration register fields: - - name: PLLM - description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - bit_offset: 0 - bit_size: 6 - - name: PLLN - description: Main PLL (PLL) multiplication factor for VCO - bit_offset: 6 - bit_size: 9 - - name: PLLP - description: Main PLL (PLL) division factor for main system clock - bit_offset: 16 - bit_size: 2 - enum: PLLP - - name: PLLSRC - description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - bit_offset: 22 - bit_size: 1 - enum: PLLSRC - - name: PLLQ - description: "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks" - bit_offset: 24 - bit_size: 4 - - name: PLLR - description: PLL division factor for I2S and System clocks - bit_offset: 28 - bit_size: 3 + - name: PLLM + description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + bit_offset: 0 + bit_size: 6 + - name: PLLN + description: Main PLL (PLL) multiplication factor for VCO + bit_offset: 6 + bit_size: 9 + - name: PLLP + description: Main PLL (PLL) division factor for main system clock + bit_offset: 16 + bit_size: 2 + enum: PLLP + - name: PLLSRC + description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + bit_offset: 22 + bit_size: 1 + enum: PLLSRC + - name: PLLQ + description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + bit_offset: 24 + bit_size: 4 + - name: PLLR + description: PLL division factor for I2S and System clocks + bit_offset: 28 + bit_size: 3 fieldset/SSCGR: description: spread spectrum clock generation register fields: - - name: MODPER - description: Modulation period - bit_offset: 0 - bit_size: 13 - - name: INCSTEP - description: Incrementation step - bit_offset: 13 - bit_size: 15 - - name: SPREADSEL - description: Spread Select - bit_offset: 30 - bit_size: 1 - enum: SPREADSEL - - name: SSCGEN - description: Spread spectrum modulation enable - bit_offset: 31 - bit_size: 1 + - name: MODPER + description: Modulation period + bit_offset: 0 + bit_size: 13 + - name: INCSTEP + description: Incrementation step + bit_offset: 13 + bit_size: 15 + - name: SPREADSEL + description: Spread Select + bit_offset: 30 + bit_size: 1 + enum: SPREADSEL + - name: SSCGEN + description: Spread spectrum modulation enable + bit_offset: 31 + bit_size: 1 enum/FMPICSEL: bit_size: 2 variants: - - name: APB - description: APB clock selected as I2C clock - value: 0 - - name: SYSCLK - description: System clock selected as I2C clock - value: 1 - - name: HSI - description: HSI clock selected as I2C clock - value: 2 + - name: APB + description: APB clock selected as I2C clock + value: 0 + - name: SYSCLK + description: System clock selected as I2C clock + value: 1 + - name: HSI + description: HSI clock selected as I2C clock + value: 2 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: SYSCLK not divided - value: 0 - - name: Div2 - description: SYSCLK divided by 2 - value: 8 - - name: Div4 - description: SYSCLK divided by 4 - value: 9 - - name: Div8 - description: SYSCLK divided by 8 - value: 10 - - name: Div16 - description: SYSCLK divided by 16 - value: 11 - - name: Div64 - description: SYSCLK divided by 64 - value: 12 - - name: Div128 - description: SYSCLK divided by 128 - value: 13 - - name: Div256 - description: SYSCLK divided by 256 - value: 14 - - name: Div512 - description: SYSCLK divided by 512 - value: 15 + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 enum/ISSRC: bit_size: 2 variants: - - name: PLLCLKR - description: I2Sx clock frequency = f(PLLCLK_R) - value: 0 - - name: I2S_CKIN - description: I2Sx clock frequency = I2S_CKIN Alternate function input frequency - value: 1 - - name: HSI_HSE - description: "I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])" - value: 3 + - name: PLLCLKR + description: I2Sx clock frequency = f(PLLCLK_R) + value: 0 + - name: I2S_CKIN + description: I2Sx clock frequency = I2S_CKIN Alternate function input frequency + value: 1 + - name: HSI_HSE + description: I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22]) + value: 3 enum/LPTIMSEL: bit_size: 2 variants: - - name: APB1 - description: APB1 clock (PCLK1) selected as LPTILM1 clock - value: 0 - - name: LSI - description: LSI clock is selected as LPTILM1 clock - value: 1 - - name: HSI - description: HSI clock is selected as LPTILM1 clock - value: 2 - - name: LSE - description: LSE clock is selected as LPTILM1 clock - value: 3 + - name: APB1 + description: APB1 clock (PCLK1) selected as LPTILM1 clock + value: 0 + - name: LSI + description: LSI clock is selected as LPTILM1 clock + value: 1 + - name: HSI + description: HSI clock is selected as LPTILM1 clock + value: 2 + - name: LSE + description: LSE clock is selected as LPTILM1 clock + value: 3 enum/MCO1: bit_size: 2 variants: - - name: HSI - description: HSI clock selected - value: 0 - - name: LSE - description: LSE oscillator selected - value: 1 - - name: HSE - description: HSE oscillator clock selected - value: 2 - - name: PLL - description: PLL clock selected - value: 3 + - name: HSI + description: HSI clock selected + value: 0 + - name: LSE + description: LSE oscillator selected + value: 1 + - name: HSE + description: HSE oscillator clock selected + value: 2 + - name: PLL + description: PLL clock selected + value: 3 enum/MCO2: bit_size: 2 variants: - - name: SYSCLK - description: System clock (SYSCLK) selected - value: 0 - - name: PLLI2S - description: PLLI2S clock selected - value: 1 - - name: HSE - description: HSE oscillator clock selected - value: 2 - - name: PLL - description: PLL clock selected - value: 3 + - name: SYSCLK + description: System clock (SYSCLK) selected + value: 0 + - name: PLLI2S + description: PLLI2S clock selected + value: 1 + - name: HSE + description: HSE oscillator clock selected + value: 2 + - name: PLL + description: PLL clock selected + value: 3 enum/MCOPRE: bit_size: 3 variants: - - name: Div1 - description: No division - value: 0 - - name: Div2 - description: Division by 2 - value: 4 - - name: Div3 - description: Division by 3 - value: 5 - - name: Div4 - description: Division by 4 - value: 6 - - name: Div5 - description: Division by 5 - value: 7 + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 4 + - name: Div3 + description: Division by 3 + value: 5 + - name: Div4 + description: Division by 4 + value: 6 + - name: Div5 + description: Division by 5 + value: 7 enum/PLLP: bit_size: 2 variants: - - name: Div2 - description: PLLP=2 - value: 0 - - name: Div4 - description: PLLP=4 - value: 1 - - name: Div6 - description: PLLP=6 - value: 2 - - name: Div8 - description: PLLP=8 - value: 3 + - name: Div2 + description: PLLP=2 + value: 0 + - name: Div4 + description: PLLP=4 + value: 1 + - name: Div6 + description: PLLP=6 + value: 2 + - name: Div8 + description: PLLP=8 + value: 3 enum/PLLSRC: bit_size: 1 variants: - - name: HSI - description: HSI clock selected as PLL and PLLI2S clock entry - value: 0 - - name: HSE - description: HSE oscillator clock selected as PLL and PLLI2S clock entry - value: 1 + - name: HSI + description: HSI clock selected as PLL and PLLI2S clock entry + value: 0 + - name: HSE + description: HSE oscillator clock selected as PLL and PLLI2S clock entry + value: 1 enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK divided by 2 - value: 4 - - name: Div4 - description: HCLK divided by 4 - value: 5 - - name: Div8 - description: HCLK divided by 8 - value: 6 - - name: Div16 - description: HCLK divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: HSE oscillator clock divided by a prescaler used as RTC clock - value: 3 + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 enum/SPREADSEL: bit_size: 1 variants: - - name: Center - description: Center spread - value: 0 - - name: Down - description: Down spread - value: 1 + - name: Center + description: Center spread + value: 0 + - name: Down + description: Down spread + value: 1 enum/SW: bit_size: 2 variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: HSE - description: HSE selected as system clock - value: 1 - - name: PLL - description: PLL selected as system clock - value: 2 -enum/SWS: - bit_size: 2 - variants: - - name: HSI - description: HSI oscillator used as system clock - value: 0 - - name: HSE - description: HSE oscillator used as system clock - value: 1 - - name: PLL - description: PLL used as system clock - value: 2 + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL + description: PLL used as system clock + value: 2 enum/TIMPRE: bit_size: 1 variants: - - name: Mul2 - description: "If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx" - value: 0 - - name: Mul4 - description: "If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx" - value: 1 + - name: Mul2 + description: If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx + value: 0 + - name: Mul4 + description: If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx + value: 1 diff --git a/data/registers/rcc_f7.yaml b/data/registers/rcc_f7.yaml index fc6fe61..1f4f4cc 100644 --- a/data/registers/rcc_f7.yaml +++ b/data/registers/rcc_f7.yaml @@ -1,2255 +1,2242 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: clock control register - byte_offset: 0 - fieldset: CR - - name: PLLCFGR - description: PLL configuration register - byte_offset: 4 - fieldset: PLLCFGR - - name: CFGR - description: clock configuration register - byte_offset: 8 - fieldset: CFGR - - name: CIR - description: clock interrupt register - byte_offset: 12 - fieldset: CIR - - name: AHB1RSTR - description: AHB1 peripheral reset register - byte_offset: 16 - fieldset: AHB1RSTR - - name: AHB2RSTR - description: AHB2 peripheral reset register - byte_offset: 20 - fieldset: AHB2RSTR - - name: AHB3RSTR - description: AHB3 peripheral reset register - byte_offset: 24 - fieldset: AHB3RSTR - - name: APB1RSTR - description: APB1 peripheral reset register - byte_offset: 32 - fieldset: APB1RSTR - - name: APB2RSTR - description: APB2 peripheral reset register - byte_offset: 36 - fieldset: APB2RSTR - - name: AHB1ENR - description: AHB1 peripheral clock register - byte_offset: 48 - fieldset: AHB1ENR - - name: AHB2ENR - description: AHB2 peripheral clock enable register - byte_offset: 52 - fieldset: AHB2ENR - - name: AHB3ENR - description: AHB3 peripheral clock enable register - byte_offset: 56 - fieldset: AHB3ENR - - name: APB1ENR - description: APB1 peripheral clock enable register - byte_offset: 64 - fieldset: APB1ENR - - name: APB2ENR - description: APB2 peripheral clock enable register - byte_offset: 68 - fieldset: APB2ENR - - name: AHB1LPENR - description: AHB1 peripheral clock enable in low power mode register - byte_offset: 80 - fieldset: AHB1LPENR - - name: AHB2LPENR - description: AHB2 peripheral clock enable in low power mode register - byte_offset: 84 - fieldset: AHB2LPENR - - name: AHB3LPENR - description: AHB3 peripheral clock enable in low power mode register - byte_offset: 88 - fieldset: AHB3LPENR - - name: APB1LPENR - description: APB1 peripheral clock enable in low power mode register - byte_offset: 96 - fieldset: APB1LPENR - - name: APB2LPENR - description: APB2 peripheral clock enabled in low power mode register - byte_offset: 100 - fieldset: APB2LPENR - - name: BDCR - description: Backup domain control register - byte_offset: 112 - fieldset: BDCR - - name: CSR - description: clock control & status register - byte_offset: 116 - fieldset: CSR - - name: SSCGR - description: spread spectrum clock generation register - byte_offset: 128 - fieldset: SSCGR - - name: PLLI2SCFGR - description: PLLI2S configuration register - byte_offset: 132 - fieldset: PLLI2SCFGR - - name: PLLSAICFGR - description: PLL configuration register - byte_offset: 136 - fieldset: PLLSAICFGR - - name: DCKCFGR1 - description: dedicated clocks configuration register - byte_offset: 140 - fieldset: DCKCFGR1 - - name: DCKCFGR2 - description: dedicated clocks configuration register - byte_offset: 144 - fieldset: DCKCFGR2 + - name: CR + description: clock control register + byte_offset: 0 + fieldset: CR + - name: PLLCFGR + description: PLL configuration register + byte_offset: 4 + fieldset: PLLCFGR + - name: CFGR + description: clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: CIR + description: clock interrupt register + byte_offset: 12 + fieldset: CIR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 16 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: AHB2 peripheral reset register + byte_offset: 20 + fieldset: AHB2RSTR + - name: AHB3RSTR + description: AHB3 peripheral reset register + byte_offset: 24 + fieldset: AHB3RSTR + - name: APB1RSTR + description: APB1 peripheral reset register + byte_offset: 32 + fieldset: APB1RSTR + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 36 + fieldset: APB2RSTR + - name: AHB1ENR + description: AHB1 peripheral clock register + byte_offset: 48 + fieldset: AHB1ENR + - name: AHB2ENR + description: AHB2 peripheral clock enable register + byte_offset: 52 + fieldset: AHB2ENR + - name: AHB3ENR + description: AHB3 peripheral clock enable register + byte_offset: 56 + fieldset: AHB3ENR + - name: APB1ENR + description: APB1 peripheral clock enable register + byte_offset: 64 + fieldset: APB1ENR + - name: APB2ENR + description: APB2 peripheral clock enable register + byte_offset: 68 + fieldset: APB2ENR + - name: AHB1LPENR + description: AHB1 peripheral clock enable in low power mode register + byte_offset: 80 + fieldset: AHB1LPENR + - name: AHB2LPENR + description: AHB2 peripheral clock enable in low power mode register + byte_offset: 84 + fieldset: AHB2LPENR + - name: AHB3LPENR + description: AHB3 peripheral clock enable in low power mode register + byte_offset: 88 + fieldset: AHB3LPENR + - name: APB1LPENR + description: APB1 peripheral clock enable in low power mode register + byte_offset: 96 + fieldset: APB1LPENR + - name: APB2LPENR + description: APB2 peripheral clock enabled in low power mode register + byte_offset: 100 + fieldset: APB2LPENR + - name: BDCR + description: Backup domain control register + byte_offset: 112 + fieldset: BDCR + - name: CSR + description: clock control & status register + byte_offset: 116 + fieldset: CSR + - name: SSCGR + description: spread spectrum clock generation register + byte_offset: 128 + fieldset: SSCGR + - name: PLLI2SCFGR + description: PLLI2S configuration register + byte_offset: 132 + fieldset: PLLI2SCFGR + - name: PLLSAICFGR + description: PLL configuration register + byte_offset: 136 + fieldset: PLLSAICFGR + - name: DCKCFGR1 + description: dedicated clocks configuration register + byte_offset: 140 + fieldset: DCKCFGR1 + - name: DCKCFGR2 + description: dedicated clocks configuration register + byte_offset: 144 + fieldset: DCKCFGR2 fieldset/AHB1ENR: description: AHB1 peripheral clock register fields: - - name: GPIOAEN - description: IO port A clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: IO port B clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: IO port C clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: IO port D clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: IO port E clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIOFEN - description: IO port F clock enable - bit_offset: 5 - bit_size: 1 - - name: GPIOGEN - description: IO port G clock enable - bit_offset: 6 - bit_size: 1 - - name: GPIOHEN - description: IO port H clock enable - bit_offset: 7 - bit_size: 1 - - name: GPIOIEN - description: IO port I clock enable - bit_offset: 8 - bit_size: 1 - - name: GPIOJEN - description: IO port J clock enable - bit_offset: 9 - bit_size: 1 - - name: GPIOKEN - description: IO port K clock enable - bit_offset: 10 - bit_size: 1 - - name: CRCEN - description: CRC clock enable - bit_offset: 12 - bit_size: 1 - - name: BKPSRAMEN - description: Backup SRAM interface clock enable - bit_offset: 18 - bit_size: 1 - - name: DTCMRAMEN - description: CCM data RAM clock enable - bit_offset: 20 - bit_size: 1 - - name: DMA1EN - description: DMA1 clock enable - bit_offset: 21 - bit_size: 1 - - name: DMA2EN - description: DMA2 clock enable - bit_offset: 22 - bit_size: 1 - - name: DMA2DEN - description: DMA2D clock enable - bit_offset: 23 - bit_size: 1 - - name: ETHEN - description: Ethernet MAC clock enable - bit_offset: 25 - bit_size: 1 - - name: ETHTXEN - description: Ethernet Transmission clock enable - bit_offset: 26 - bit_size: 1 - - name: ETHRXEN - description: Ethernet Reception clock enable - bit_offset: 27 - bit_size: 1 - - name: ETHPTPEN - description: Ethernet PTP clock enable - bit_offset: 28 - bit_size: 1 - - name: USB_OTG_HSEN - description: USB OTG HS clock enable - bit_offset: 29 - bit_size: 1 - - name: USB_OTG_HSULPIEN - description: USB OTG HSULPI clock enable - bit_offset: 30 - bit_size: 1 + - name: GPIOAEN + description: IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: IO port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: IO port E clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: IO port F clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: IO port G clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: IO port H clock enable + bit_offset: 7 + bit_size: 1 + - name: GPIOIEN + description: IO port I clock enable + bit_offset: 8 + bit_size: 1 + - name: GPIOJEN + description: IO port J clock enable + bit_offset: 9 + bit_size: 1 + - name: GPIOKEN + description: IO port K clock enable + bit_offset: 10 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: BKPSRAMEN + description: Backup SRAM interface clock enable + bit_offset: 18 + bit_size: 1 + - name: DTCMRAMEN + description: CCM data RAM clock enable + bit_offset: 20 + bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 21 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 22 + bit_size: 1 + - name: DMA2DEN + description: DMA2D clock enable + bit_offset: 23 + bit_size: 1 + - name: ETHEN + description: Ethernet MAC clock enable + bit_offset: 25 + bit_size: 1 + - name: ETHTXEN + description: Ethernet Transmission clock enable + bit_offset: 26 + bit_size: 1 + - name: ETHRXEN + description: Ethernet Reception clock enable + bit_offset: 27 + bit_size: 1 + - name: ETHPTPEN + description: Ethernet PTP clock enable + bit_offset: 28 + bit_size: 1 + - name: USB_OTG_HSEN + description: USB OTG HS clock enable + bit_offset: 29 + bit_size: 1 + - name: USB_OTG_HSULPIEN + description: USB OTG HSULPI clock enable + bit_offset: 30 + bit_size: 1 fieldset/AHB1LPENR: description: AHB1 peripheral clock enable in low power mode register fields: - - name: GPIOALPEN - description: IO port A clock enable during sleep mode - bit_offset: 0 - bit_size: 1 - - name: GPIOBLPEN - description: IO port B clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: GPIOCLPEN - description: IO port C clock enable during Sleep mode - bit_offset: 2 - bit_size: 1 - - name: GPIODLPEN - description: IO port D clock enable during Sleep mode - bit_offset: 3 - bit_size: 1 - - name: GPIOELPEN - description: IO port E clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: GPIOFLPEN - description: IO port F clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: GPIOGLPEN - description: IO port G clock enable during Sleep mode - bit_offset: 6 - bit_size: 1 - - name: GPIOHLPEN - description: IO port H clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 - - name: GPIOILPEN - description: IO port I clock enable during Sleep mode - bit_offset: 8 - bit_size: 1 - - name: GPIOJLPEN - description: IO port J clock enable during Sleep mode - bit_offset: 9 - bit_size: 1 - - name: GPIOKLPEN - description: IO port K clock enable during Sleep mode - bit_offset: 10 - bit_size: 1 - - name: CRCLPEN - description: CRC clock enable during Sleep mode - bit_offset: 12 - bit_size: 1 - - name: AXILPEN - description: AXI to AHB bridge clock enable during Sleep mode - bit_offset: 13 - bit_size: 1 - - name: FLASHLPEN - description: Flash interface clock enable during Sleep mode - bit_offset: 15 - bit_size: 1 - - name: SRAM1LPEN - description: SRAM 1interface clock enable during Sleep mode - bit_offset: 16 - bit_size: 1 - - name: SRAM2LPEN - description: SRAM 2 interface clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: BKPSRAMLPEN - description: Backup SRAM interface clock enable during Sleep mode - bit_offset: 18 - bit_size: 1 - - name: SRAM3LPEN - description: SRAM 3 interface clock enable during Sleep mode - bit_offset: 19 - bit_size: 1 - - name: DTCMLPEN - description: DTCM RAM interface clock enable during Sleep mode - bit_offset: 20 - bit_size: 1 - - name: DMA1LPEN - description: DMA1 clock enable during Sleep mode - bit_offset: 21 - bit_size: 1 - - name: DMA2LPEN - description: DMA2 clock enable during Sleep mode - bit_offset: 22 - bit_size: 1 - - name: DMA2DLPEN - description: DMA2D clock enable during Sleep mode - bit_offset: 23 - bit_size: 1 - - name: ETHLPEN - description: Ethernet MAC clock enable during Sleep mode - bit_offset: 25 - bit_size: 1 - - name: ETHTXLPEN - description: Ethernet transmission clock enable during Sleep mode - bit_offset: 26 - bit_size: 1 - - name: ETHRXLPEN - description: Ethernet reception clock enable during Sleep mode - bit_offset: 27 - bit_size: 1 - - name: ETHPTPLPEN - description: Ethernet PTP clock enable during Sleep mode - bit_offset: 28 - bit_size: 1 - - name: USB_OTG_HSLPEN - description: USB OTG HS clock enable during Sleep mode - bit_offset: 29 - bit_size: 1 - - name: USB_OTG_HSULPILPEN - description: USB OTG HS ULPI clock enable during Sleep mode - bit_offset: 30 - bit_size: 1 + - name: GPIOALPEN + description: IO port A clock enable during sleep mode + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: IO port B clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: IO port C clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: GPIODLPEN + description: IO port D clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: GPIOELPEN + description: IO port E clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: GPIOFLPEN + description: IO port F clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: GPIOGLPEN + description: IO port G clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: GPIOHLPEN + description: IO port H clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: GPIOILPEN + description: IO port I clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: GPIOJLPEN + description: IO port J clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: GPIOKLPEN + description: IO port K clock enable during Sleep mode + bit_offset: 10 + bit_size: 1 + - name: CRCLPEN + description: CRC clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: AXILPEN + description: AXI to AHB bridge clock enable during Sleep mode + bit_offset: 13 + bit_size: 1 + - name: FLASHLPEN + description: Flash interface clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: SRAM1LPEN + description: SRAM 1interface clock enable during Sleep mode + bit_offset: 16 + bit_size: 1 + - name: SRAM2LPEN + description: SRAM 2 interface clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: BKPSRAMLPEN + description: Backup SRAM interface clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: SRAM3LPEN + description: SRAM 3 interface clock enable during Sleep mode + bit_offset: 19 + bit_size: 1 + - name: DTCMLPEN + description: DTCM RAM interface clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 + - name: DMA1LPEN + description: DMA1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: DMA2LPEN + description: DMA2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: DMA2DLPEN + description: DMA2D clock enable during Sleep mode + bit_offset: 23 + bit_size: 1 + - name: ETHLPEN + description: Ethernet MAC clock enable during Sleep mode + bit_offset: 25 + bit_size: 1 + - name: ETHTXLPEN + description: Ethernet transmission clock enable during Sleep mode + bit_offset: 26 + bit_size: 1 + - name: ETHRXLPEN + description: Ethernet reception clock enable during Sleep mode + bit_offset: 27 + bit_size: 1 + - name: ETHPTPLPEN + description: Ethernet PTP clock enable during Sleep mode + bit_offset: 28 + bit_size: 1 + - name: USB_OTG_HSLPEN + description: USB OTG HS clock enable during Sleep mode + bit_offset: 29 + bit_size: 1 + - name: USB_OTG_HSULPILPEN + description: USB OTG HS ULPI clock enable during Sleep mode + bit_offset: 30 + bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - - name: GPIOARST - description: IO port A reset - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: IO port B reset - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: IO port C reset - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: IO port D reset - bit_offset: 3 - bit_size: 1 - - name: GPIOERST - description: IO port E reset - bit_offset: 4 - bit_size: 1 - - name: GPIOFRST - description: IO port F reset - bit_offset: 5 - bit_size: 1 - - name: GPIOGRST - description: IO port G reset - bit_offset: 6 - bit_size: 1 - - name: GPIOHRST - description: IO port H reset - bit_offset: 7 - bit_size: 1 - - name: GPIOIRST - description: IO port I reset - bit_offset: 8 - bit_size: 1 - - name: GPIOJRST - description: IO port J reset - bit_offset: 9 - bit_size: 1 - - name: GPIOKRST - description: IO port K reset - bit_offset: 10 - bit_size: 1 - - name: CRCRST - description: CRC reset - bit_offset: 12 - bit_size: 1 - - name: DMA1RST - description: DMA2 reset - bit_offset: 21 - bit_size: 1 - - name: DMA2RST - description: DMA2 reset - bit_offset: 22 - bit_size: 1 - - name: DMA2DRST - description: DMA2D reset - bit_offset: 23 - bit_size: 1 - - name: ETHRST - description: Ethernet MAC reset - bit_offset: 25 - bit_size: 1 - - name: USB_OTG_HSRST - description: USB OTG HS module reset - bit_offset: 29 - bit_size: 1 + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 6 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 7 + bit_size: 1 + - name: GPIOIRST + description: IO port I reset + bit_offset: 8 + bit_size: 1 + - name: GPIOJRST + description: IO port J reset + bit_offset: 9 + bit_size: 1 + - name: GPIOKRST + description: IO port K reset + bit_offset: 10 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 + - name: DMA1RST + description: DMA2 reset + bit_offset: 21 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 22 + bit_size: 1 + - name: DMA2DRST + description: DMA2D reset + bit_offset: 23 + bit_size: 1 + - name: ETHRST + description: Ethernet MAC reset + bit_offset: 25 + bit_size: 1 + - name: USB_OTG_HSRST + description: USB OTG HS module reset + bit_offset: 29 + bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - - name: DCMIEN - description: Camera interface enable - bit_offset: 0 - bit_size: 1 - - name: JPEGEN - description: JPEG enable - bit_offset: 1 - bit_size: 1 - - name: AESEN - description: AES module clock enable - bit_offset: 4 - bit_size: 1 - - name: CRYPEN - description: Cryptographic modules clock enable - bit_offset: 4 - bit_size: 1 - - name: HASHEN - description: Hash modules clock enable - bit_offset: 5 - bit_size: 1 - - name: RNGEN - description: Random number generator clock enable - bit_offset: 6 - bit_size: 1 - - name: USB_OTG_FSEN - description: USB OTG FS clock enable - bit_offset: 7 - bit_size: 1 + - name: DCMIEN + description: Camera interface enable + bit_offset: 0 + bit_size: 1 + - name: JPEGEN + description: JPEG enable + bit_offset: 1 + bit_size: 1 + - name: AESEN + description: AES module clock enable + bit_offset: 4 + bit_size: 1 + - name: CRYPEN + description: Cryptographic modules clock enable + bit_offset: 4 + bit_size: 1 + - name: HASHEN + description: Hash modules clock enable + bit_offset: 5 + bit_size: 1 + - name: RNGEN + description: Random number generator clock enable + bit_offset: 6 + bit_size: 1 + - name: USB_OTG_FSEN + description: USB OTG FS clock enable + bit_offset: 7 + bit_size: 1 fieldset/AHB2LPENR: description: AHB2 peripheral clock enable in low power mode register fields: - - name: DCMILPEN - description: Camera interface enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: JPEGLPEN - description: JPEG module enabled during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: AESLPEN - description: AES module clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: CRYPLPEN - description: Cryptography modules clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: HASHLPEN - description: Hash modules clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: RNGLPEN - description: Random number generator clock enable during Sleep mode - bit_offset: 6 - bit_size: 1 - - name: USB_OTG_FSLPEN - description: USB OTG FS clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 + - name: DCMILPEN + description: Camera interface enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: JPEGLPEN + description: JPEG module enabled during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: AESLPEN + description: AES module clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: CRYPLPEN + description: Cryptography modules clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: HASHLPEN + description: Hash modules clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: RNGLPEN + description: Random number generator clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: USB_OTG_FSLPEN + description: USB OTG FS clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - - name: DCMIRST - description: Camera interface reset - bit_offset: 0 - bit_size: 1 - - name: AESRST - description: AES module reset - bit_offset: 4 - bit_size: 1 - - name: CRYPRST - description: Cryptographic module reset - bit_offset: 4 - bit_size: 1 - - name: HSAHRST - description: Hash module reset - bit_offset: 5 - bit_size: 1 - - name: RNGRST - description: Random number generator module reset - bit_offset: 6 - bit_size: 1 - - name: USB_OTG_FSRST - description: USB OTG FS module reset - bit_offset: 7 - bit_size: 1 + - name: DCMIRST + description: Camera interface reset + bit_offset: 0 + bit_size: 1 + - name: AESRST + description: AES module reset + bit_offset: 4 + bit_size: 1 + - name: CRYPRST + description: Cryptographic module reset + bit_offset: 4 + bit_size: 1 + - name: HSAHRST + description: Hash module reset + bit_offset: 5 + bit_size: 1 + - name: RNGRST + description: Random number generator module reset + bit_offset: 6 + bit_size: 1 + - name: USB_OTG_FSRST + description: USB OTG FS module reset + bit_offset: 7 + bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: - - name: FMCEN - description: Flexible memory controller module clock enable - bit_offset: 0 - bit_size: 1 - - name: QUADSPIEN - description: Quad SPI memory controller clock enable - bit_offset: 1 - bit_size: 1 + - name: FMCEN + description: Flexible memory controller module clock enable + bit_offset: 0 + bit_size: 1 + - name: QUADSPIEN + description: Quad SPI memory controller clock enable + bit_offset: 1 + bit_size: 1 fieldset/AHB3LPENR: description: AHB3 peripheral clock enable in low power mode register fields: - - name: FMCLPEN - description: Flexible memory controller module clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: QUADSPILPEN - description: Quand SPI memory controller clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 + - name: FMCLPEN + description: Flexible memory controller module clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: QUADSPILPEN + description: Quand SPI memory controller clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - - name: FMCRST - description: Flexible memory controller module reset - bit_offset: 0 - bit_size: 1 - - name: QUADSPIRST - description: Quad SPI memory controller reset - bit_offset: 1 - bit_size: 1 + - name: FMCRST + description: Flexible memory controller module reset + bit_offset: 0 + bit_size: 1 + - name: QUADSPIRST + description: Quad SPI memory controller reset + bit_offset: 1 + bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register fields: - - name: TIM2EN - description: TIM2 clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: TIM3 clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: TIM4 clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: TIM5 clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: TIM6 clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: TIM7 clock enable - bit_offset: 5 - bit_size: 1 - - name: TIM12EN - description: TIM12 clock enable - bit_offset: 6 - bit_size: 1 - - name: TIM13EN - description: TIM13 clock enable - bit_offset: 7 - bit_size: 1 - - name: TIM14EN - description: TIM14 clock enable - bit_offset: 8 - bit_size: 1 - - name: LPTIM1EN - description: Low power timer 1 clock enable - bit_offset: 9 - bit_size: 1 - - name: RTCEN - description: RTCAPB clock enable - bit_offset: 10 - bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: CAN3EN - description: CAN 3 enable - bit_offset: 13 - bit_size: 1 - - name: SPI2EN - description: SPI2 clock enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI3 clock enable - bit_offset: 15 - bit_size: 1 - - name: SPDIFRXEN - description: SPDIF-RX clock enable - bit_offset: 16 - bit_size: 1 - - name: USART2EN - description: USART 2 clock enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART3 clock enable - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: UART4 clock enable - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: UART5 clock enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C2 clock enable - bit_offset: 22 - bit_size: 1 - - name: I2C3EN - description: I2C3 clock enable - bit_offset: 23 - bit_size: 1 - - name: I2C4EN - description: I2C4 clock enable - bit_offset: 24 - bit_size: 1 - - name: CAN1EN - description: CAN 1 clock enable - bit_offset: 25 - bit_size: 1 - - name: CAN2EN - description: CAN 2 clock enable - bit_offset: 26 - bit_size: 1 - - name: CECEN - description: HDMI-CEN clock enable - bit_offset: 27 - bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - - name: DACEN - description: DAC interface clock enable - bit_offset: 29 - bit_size: 1 - - name: UART7EN - description: UART7 clock enable - bit_offset: 30 - bit_size: 1 - - name: UART8EN - description: UART8 clock enable - bit_offset: 31 - bit_size: 1 + - name: TIM2EN + description: TIM2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: TIM5 clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM7 clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: TIM12 clock enable + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: TIM13 clock enable + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: TIM14 clock enable + bit_offset: 8 + bit_size: 1 + - name: LPTIM1EN + description: Low power timer 1 clock enable + bit_offset: 9 + bit_size: 1 + - name: RTCEN + description: RTCAPB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: CAN3EN + description: CAN 3 enable + bit_offset: 13 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 clock enable + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXEN + description: SPDIF-RX clock enable + bit_offset: 16 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 23 + bit_size: 1 + - name: I2C4EN + description: I2C4 clock enable + bit_offset: 24 + bit_size: 1 + - name: CAN1EN + description: CAN 1 clock enable + bit_offset: 25 + bit_size: 1 + - name: CAN2EN + description: CAN 2 clock enable + bit_offset: 26 + bit_size: 1 + - name: CECEN + description: HDMI-CEN clock enable + bit_offset: 27 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: UART7EN + description: UART7 clock enable + bit_offset: 30 + bit_size: 1 + - name: UART8EN + description: UART8 clock enable + bit_offset: 31 + bit_size: 1 fieldset/APB1LPENR: description: APB1 peripheral clock enable in low power mode register fields: - - name: TIM2LPEN - description: TIM2 clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM3LPEN - description: TIM3 clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: TIM4LPEN - description: TIM4 clock enable during Sleep mode - bit_offset: 2 - bit_size: 1 - - name: TIM5LPEN - description: TIM5 clock enable during Sleep mode - bit_offset: 3 - bit_size: 1 - - name: TIM6LPEN - description: TIM6 clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: TIM7LPEN - description: TIM7 clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: TIM12LPEN - description: TIM12 clock enable during Sleep mode - bit_offset: 6 - bit_size: 1 - - name: TIM13LPEN - description: TIM13 clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 - - name: TIM14LPEN - description: TIM14 clock enable during Sleep mode - bit_offset: 8 - bit_size: 1 - - name: LPTIM1LPEN - description: low power timer 1 clock enable during Sleep mode - bit_offset: 9 - bit_size: 1 - - name: RTCLPEN - description: RTCAPB clock enable during Sleep mode - bit_offset: 10 - bit_size: 1 - - name: WWDGLPEN - description: Window watchdog clock enable during Sleep mode - bit_offset: 11 - bit_size: 1 - - name: CAN3LPEN - description: CAN 3 clock enable during Sleep mode - bit_offset: 13 - bit_size: 1 - - name: SPI2LPEN - description: SPI2 clock enable during Sleep mode - bit_offset: 14 - bit_size: 1 - - name: SPI3LPEN - description: SPI3 clock enable during Sleep mode - bit_offset: 15 - bit_size: 1 - - name: SPDIFRXLPEN - description: SPDIF-RX clock enable during sleep mode - bit_offset: 16 - bit_size: 1 - - name: USART2LPEN - description: USART2 clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: USART3LPEN - description: USART3 clock enable during Sleep mode - bit_offset: 18 - bit_size: 1 - - name: UART4LPEN - description: UART4 clock enable during Sleep mode - bit_offset: 19 - bit_size: 1 - - name: UART5LPEN - description: UART5 clock enable during Sleep mode - bit_offset: 20 - bit_size: 1 - - name: I2C1LPEN - description: I2C1 clock enable during Sleep mode - bit_offset: 21 - bit_size: 1 - - name: I2C2LPEN - description: I2C2 clock enable during Sleep mode - bit_offset: 22 - bit_size: 1 - - name: I2C3LPEN - description: I2C3 clock enable during Sleep mode - bit_offset: 23 - bit_size: 1 - - name: I2C4LPEN - description: I2C4 clock enable during Sleep mode - bit_offset: 24 - bit_size: 1 - - name: CAN1LPEN - description: CAN 1 clock enable during Sleep mode - bit_offset: 25 - bit_size: 1 - - name: CAN2LPEN - description: CAN 2 clock enable during Sleep mode - bit_offset: 26 - bit_size: 1 - - name: CECLPEN - description: HDMI-CEN clock enable during Sleep mode - bit_offset: 27 - bit_size: 1 - - name: PWRLPEN - description: Power interface clock enable during Sleep mode - bit_offset: 28 - bit_size: 1 - - name: DACLPEN - description: DAC interface clock enable during Sleep mode - bit_offset: 29 - bit_size: 1 - - name: UART7LPEN - description: UART7 clock enable during Sleep mode - bit_offset: 30 - bit_size: 1 - - name: UART8LPEN - description: UART8 clock enable during Sleep mode - bit_offset: 31 - bit_size: 1 + - name: TIM2LPEN + description: TIM2 clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM3LPEN + description: TIM3 clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: TIM4LPEN + description: TIM4 clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: TIM5LPEN + description: TIM5 clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: TIM6LPEN + description: TIM6 clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: TIM7LPEN + description: TIM7 clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: TIM12LPEN + description: TIM12 clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: TIM13LPEN + description: TIM13 clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: TIM14LPEN + description: TIM14 clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: LPTIM1LPEN + description: low power timer 1 clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: RTCLPEN + description: RTCAPB clock enable during Sleep mode + bit_offset: 10 + bit_size: 1 + - name: WWDGLPEN + description: Window watchdog clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: CAN3LPEN + description: CAN 3 clock enable during Sleep mode + bit_offset: 13 + bit_size: 1 + - name: SPI2LPEN + description: SPI2 clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: SPI3LPEN + description: SPI3 clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXLPEN + description: SPDIF-RX clock enable during sleep mode + bit_offset: 16 + bit_size: 1 + - name: USART2LPEN + description: USART2 clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: USART3LPEN + description: USART3 clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: UART4LPEN + description: UART4 clock enable during Sleep mode + bit_offset: 19 + bit_size: 1 + - name: UART5LPEN + description: UART5 clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 + - name: I2C1LPEN + description: I2C1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: I2C2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: I2C3LPEN + description: I2C3 clock enable during Sleep mode + bit_offset: 23 + bit_size: 1 + - name: I2C4LPEN + description: I2C4 clock enable during Sleep mode + bit_offset: 24 + bit_size: 1 + - name: CAN1LPEN + description: CAN 1 clock enable during Sleep mode + bit_offset: 25 + bit_size: 1 + - name: CAN2LPEN + description: CAN 2 clock enable during Sleep mode + bit_offset: 26 + bit_size: 1 + - name: CECLPEN + description: HDMI-CEN clock enable during Sleep mode + bit_offset: 27 + bit_size: 1 + - name: PWRLPEN + description: Power interface clock enable during Sleep mode + bit_offset: 28 + bit_size: 1 + - name: DACLPEN + description: DAC interface clock enable during Sleep mode + bit_offset: 29 + bit_size: 1 + - name: UART7LPEN + description: UART7 clock enable during Sleep mode + bit_offset: 30 + bit_size: 1 + - name: UART8LPEN + description: UART8 clock enable during Sleep mode + bit_offset: 31 + bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register fields: - - name: TIM2RST - description: TIM2 reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: TIM3 reset - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: TIM4 reset - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: TIM5 reset - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: TIM6 reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: TIM7 reset - bit_offset: 5 - bit_size: 1 - - name: TIM12RST - description: TIM12 reset - bit_offset: 6 - bit_size: 1 - - name: TIM13RST - description: TIM13 reset - bit_offset: 7 - bit_size: 1 - - name: TIM14RST - description: TIM14 reset - bit_offset: 8 - bit_size: 1 - - name: LPTIM1RST - description: Low power timer 1 reset - bit_offset: 9 - bit_size: 1 - - name: WWDGRST - description: Window watchdog reset - bit_offset: 11 - bit_size: 1 - - name: CAN3RST - description: CAN 3 reset - bit_offset: 13 - bit_size: 1 - - name: SPI2RST - description: SPI 2 reset - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: SPI 3 reset - bit_offset: 15 - bit_size: 1 - - name: SPDIFRXRST - description: SPDIF-RX reset - bit_offset: 16 - bit_size: 1 - - name: USART2RST - description: USART 2 reset - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: USART 3 reset - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: USART 4 reset - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: USART 5 reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C 1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C 2 reset - bit_offset: 22 - bit_size: 1 - - name: I2C3RST - description: I2C3 reset - bit_offset: 23 - bit_size: 1 - - name: I2C4RST - description: I2C 4 reset - bit_offset: 24 - bit_size: 1 - - name: CAN1RST - description: CAN1 reset - bit_offset: 25 - bit_size: 1 - - name: CAN2RST - description: CAN2 reset - bit_offset: 26 - bit_size: 1 - - name: CECRST - description: HDMI-CEC reset - bit_offset: 27 - bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - - name: DACRST - description: DAC reset - bit_offset: 29 - bit_size: 1 - - name: UART7RST - description: UART7 reset - bit_offset: 30 - bit_size: 1 - - name: UART8RST - description: UART8 reset - bit_offset: 31 - bit_size: 1 + - name: TIM2RST + description: TIM2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: TIM3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: TIM4 reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: TIM5 reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: TIM6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM7 reset + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: TIM12 reset + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: TIM13 reset + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: TIM14 reset + bit_offset: 8 + bit_size: 1 + - name: LPTIM1RST + description: Low power timer 1 reset + bit_offset: 9 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: CAN3RST + description: CAN 3 reset + bit_offset: 13 + bit_size: 1 + - name: SPI2RST + description: SPI 2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI 3 reset + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXRST + description: SPDIF-RX reset + bit_offset: 16 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART 3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: USART 4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: USART 5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C 1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C 2 reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 23 + bit_size: 1 + - name: I2C4RST + description: I2C 4 reset + bit_offset: 24 + bit_size: 1 + - name: CAN1RST + description: CAN1 reset + bit_offset: 25 + bit_size: 1 + - name: CAN2RST + description: CAN2 reset + bit_offset: 26 + bit_size: 1 + - name: CECRST + description: HDMI-CEC reset + bit_offset: 27 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC reset + bit_offset: 29 + bit_size: 1 + - name: UART7RST + description: UART7 reset + bit_offset: 30 + bit_size: 1 + - name: UART8RST + description: UART8 reset + bit_offset: 31 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - - name: TIM1EN - description: TIM1 clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM8EN - description: TIM8 clock enable - bit_offset: 1 - bit_size: 1 - - name: USART1EN - description: USART1 clock enable - bit_offset: 4 - bit_size: 1 - - name: USART6EN - description: USART6 clock enable - bit_offset: 5 - bit_size: 1 - - name: SDMMC2EN - description: SDMMC2 clock enable - bit_offset: 7 - bit_size: 1 - - name: ADC1EN - description: ADC1 clock enable - bit_offset: 8 - bit_size: 1 - - name: ADC2EN - description: ADC2 clock enable - bit_offset: 9 - bit_size: 1 - - name: ADC3EN - description: ADC3 clock enable - bit_offset: 10 - bit_size: 1 - - name: SDMMC1EN - description: SDMMC1 clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: SPI1 clock enable - bit_offset: 12 - bit_size: 1 - - name: SPI4EN - description: SPI4 clock enable - bit_offset: 13 - bit_size: 1 - - name: SYSCFGEN - description: System configuration controller clock enable - bit_offset: 14 - bit_size: 1 - - name: TIM9EN - description: TIM9 clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM10EN - description: TIM10 clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM11EN - description: TIM11 clock enable - bit_offset: 18 - bit_size: 1 - - name: SPI5EN - description: SPI5 clock enable - bit_offset: 20 - bit_size: 1 - - name: SPI6EN - description: SPI6 clock enable - bit_offset: 21 - bit_size: 1 - - name: SAI1EN - description: SAI1 clock enable - bit_offset: 22 - bit_size: 1 - - name: SAI2EN - description: SAI2 clock enable - bit_offset: 23 - bit_size: 1 - - name: LTDCEN - description: LTDC clock enable - bit_offset: 26 - bit_size: 1 - - name: DSIEN - description: DSI clock enable - bit_offset: 27 - bit_size: 1 - - name: DFSDM1EN - description: DFSDM1 clock enable - bit_offset: 29 - bit_size: 1 - - name: MDIOSEN - description: MDIO clock enable - bit_offset: 30 - bit_size: 1 - - name: USBPHYCEN - description: USB OTG HS PHY controller clock enable - bit_offset: 31 - bit_size: 1 + - name: TIM1EN + description: TIM1 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM8EN + description: TIM8 clock enable + bit_offset: 1 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 4 + bit_size: 1 + - name: USART6EN + description: USART6 clock enable + bit_offset: 5 + bit_size: 1 + - name: SDMMC2EN + description: SDMMC2 clock enable + bit_offset: 7 + bit_size: 1 + - name: ADC1EN + description: ADC1 clock enable + bit_offset: 8 + bit_size: 1 + - name: ADC2EN + description: ADC2 clock enable + bit_offset: 9 + bit_size: 1 + - name: ADC3EN + description: ADC3 clock enable + bit_offset: 10 + bit_size: 1 + - name: SDMMC1EN + description: SDMMC1 clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: SPI4EN + description: SPI4 clock enable + bit_offset: 13 + bit_size: 1 + - name: SYSCFGEN + description: System configuration controller clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM9EN + description: TIM9 clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM10EN + description: TIM10 clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM11EN + description: TIM11 clock enable + bit_offset: 18 + bit_size: 1 + - name: SPI5EN + description: SPI5 clock enable + bit_offset: 20 + bit_size: 1 + - name: SPI6EN + description: SPI6 clock enable + bit_offset: 21 + bit_size: 1 + - name: SAI1EN + description: SAI1 clock enable + bit_offset: 22 + bit_size: 1 + - name: SAI2EN + description: SAI2 clock enable + bit_offset: 23 + bit_size: 1 + - name: LTDCEN + description: LTDC clock enable + bit_offset: 26 + bit_size: 1 + - name: DSIEN + description: DSI clock enable + bit_offset: 27 + bit_size: 1 + - name: DFSDM1EN + description: DFSDM1 clock enable + bit_offset: 29 + bit_size: 1 + - name: MDIOSEN + description: MDIO clock enable + bit_offset: 30 + bit_size: 1 + - name: USBPHYCEN + description: USB OTG HS PHY controller clock enable + bit_offset: 31 + bit_size: 1 fieldset/APB2LPENR: description: APB2 peripheral clock enabled in low power mode register fields: - - name: TIM1LPEN - description: TIM1 clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM8LPEN - description: TIM8 clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: USART1LPEN - description: USART1 clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: USART6LPEN - description: USART6 clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: SDMMC2LPEN - description: SDMMC2 clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 - - name: ADC1LPEN - description: ADC1 clock enable during Sleep mode - bit_offset: 8 - bit_size: 1 - - name: ADC2LPEN - description: ADC2 clock enable during Sleep mode - bit_offset: 9 - bit_size: 1 - - name: ADC3LPEN - description: ADC 3 clock enable during Sleep mode - bit_offset: 10 - bit_size: 1 - - name: SDMMC1LPEN - description: SDMMC1 clock enable during Sleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI1LPEN - description: SPI 1 clock enable during Sleep mode - bit_offset: 12 - bit_size: 1 - - name: SPI4LPEN - description: SPI 4 clock enable during Sleep mode - bit_offset: 13 - bit_size: 1 - - name: SYSCFGLPEN - description: System configuration controller clock enable during Sleep mode - bit_offset: 14 - bit_size: 1 - - name: TIM9LPEN - description: TIM9 clock enable during sleep mode - bit_offset: 16 - bit_size: 1 - - name: TIM10LPEN - description: TIM10 clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: TIM11LPEN - description: TIM11 clock enable during Sleep mode - bit_offset: 18 - bit_size: 1 - - name: SPI5LPEN - description: SPI 5 clock enable during Sleep mode - bit_offset: 20 - bit_size: 1 - - name: SPI6LPEN - description: SPI 6 clock enable during Sleep mode - bit_offset: 21 - bit_size: 1 - - name: SAI1LPEN - description: SAI1 clock enable during sleep mode - bit_offset: 22 - bit_size: 1 - - name: SAI2LPEN - description: SAI2 clock enable during sleep mode - bit_offset: 23 - bit_size: 1 - - name: LTDCLPEN - description: LTDC clock enable during sleep mode - bit_offset: 26 - bit_size: 1 - - name: DSILPEN - description: DSI clock enable during Sleep mode - bit_offset: 27 - bit_size: 1 - - name: DFSDM1LPEN - description: DFSDM1 clock enable during Sleep mode - bit_offset: 29 - bit_size: 1 - - name: MDIOSLPEN - description: MDIO clock enable during Sleep mode - bit_offset: 30 - bit_size: 1 + - name: TIM1LPEN + description: TIM1 clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM8LPEN + description: TIM8 clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: USART1LPEN + description: USART1 clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: USART6LPEN + description: USART6 clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: SDMMC2LPEN + description: SDMMC2 clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: ADC1LPEN + description: ADC1 clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: ADC2LPEN + description: ADC2 clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: ADC3LPEN + description: ADC 3 clock enable during Sleep mode + bit_offset: 10 + bit_size: 1 + - name: SDMMC1LPEN + description: SDMMC1 clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI1LPEN + description: SPI 1 clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: SPI4LPEN + description: SPI 4 clock enable during Sleep mode + bit_offset: 13 + bit_size: 1 + - name: SYSCFGLPEN + description: System configuration controller clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: TIM9LPEN + description: TIM9 clock enable during sleep mode + bit_offset: 16 + bit_size: 1 + - name: TIM10LPEN + description: TIM10 clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: TIM11LPEN + description: TIM11 clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: SPI5LPEN + description: SPI 5 clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 + - name: SPI6LPEN + description: SPI 6 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: SAI1LPEN + description: SAI1 clock enable during sleep mode + bit_offset: 22 + bit_size: 1 + - name: SAI2LPEN + description: SAI2 clock enable during sleep mode + bit_offset: 23 + bit_size: 1 + - name: LTDCLPEN + description: LTDC clock enable during sleep mode + bit_offset: 26 + bit_size: 1 + - name: DSILPEN + description: DSI clock enable during Sleep mode + bit_offset: 27 + bit_size: 1 + - name: DFSDM1LPEN + description: DFSDM1 clock enable during Sleep mode + bit_offset: 29 + bit_size: 1 + - name: MDIOSLPEN + description: MDIO clock enable during Sleep mode + bit_offset: 30 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - - name: TIM1RST - description: TIM1 reset - bit_offset: 0 - bit_size: 1 - - name: TIM8RST - description: TIM8 reset - bit_offset: 1 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 4 - bit_size: 1 - - name: USART6RST - description: USART6 reset - bit_offset: 5 - bit_size: 1 - - name: SDMMC2RST - description: SDMMC2 reset - bit_offset: 7 - bit_size: 1 - - name: ADCRST - description: ADC interface reset (common to all ADCs) - bit_offset: 8 - bit_size: 1 - - name: SDMMC1RST - description: SDMMC1 reset - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: SPI 1 reset - bit_offset: 12 - bit_size: 1 - - name: SPI4RST - description: SPI4 reset - bit_offset: 13 - bit_size: 1 - - name: SYSCFGRST - description: System configuration controller reset - bit_offset: 14 - bit_size: 1 - - name: TIM9RST - description: TIM9 reset - bit_offset: 16 - bit_size: 1 - - name: TIM10RST - description: TIM10 reset - bit_offset: 17 - bit_size: 1 - - name: TIM11RST - description: TIM11 reset - bit_offset: 18 - bit_size: 1 - - name: SPI5RST - description: SPI5 reset - bit_offset: 20 - bit_size: 1 - - name: SPI6RST - description: SPI6 reset - bit_offset: 21 - bit_size: 1 - - name: SAI1RST - description: SAI1 reset - bit_offset: 22 - bit_size: 1 - - name: SAI2RST - description: SAI2 reset - bit_offset: 23 - bit_size: 1 - - name: LTDCRST - description: LTDC reset - bit_offset: 26 - bit_size: 1 - - name: DSIRST - description: DSI reset - bit_offset: 27 - bit_size: 1 - - name: DFSDM1RST - description: DFSDM 1 reset - bit_offset: 29 - bit_size: 1 - - name: MDIOSRST - description: MDIOS reset - bit_offset: 30 - bit_size: 1 - - name: USBPHYCRST - description: USB OTG HS PHY controller reset - bit_offset: 31 - bit_size: 1 + - name: TIM1RST + description: TIM1 reset + bit_offset: 0 + bit_size: 1 + - name: TIM8RST + description: TIM8 reset + bit_offset: 1 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 4 + bit_size: 1 + - name: USART6RST + description: USART6 reset + bit_offset: 5 + bit_size: 1 + - name: SDMMC2RST + description: SDMMC2 reset + bit_offset: 7 + bit_size: 1 + - name: ADCRST + description: ADC interface reset (common to all ADCs) + bit_offset: 8 + bit_size: 1 + - name: SDMMC1RST + description: SDMMC1 reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: SPI4RST + description: SPI4 reset + bit_offset: 13 + bit_size: 1 + - name: SYSCFGRST + description: System configuration controller reset + bit_offset: 14 + bit_size: 1 + - name: TIM9RST + description: TIM9 reset + bit_offset: 16 + bit_size: 1 + - name: TIM10RST + description: TIM10 reset + bit_offset: 17 + bit_size: 1 + - name: TIM11RST + description: TIM11 reset + bit_offset: 18 + bit_size: 1 + - name: SPI5RST + description: SPI5 reset + bit_offset: 20 + bit_size: 1 + - name: SPI6RST + description: SPI6 reset + bit_offset: 21 + bit_size: 1 + - name: SAI1RST + description: SAI1 reset + bit_offset: 22 + bit_size: 1 + - name: SAI2RST + description: SAI2 reset + bit_offset: 23 + bit_size: 1 + - name: LTDCRST + description: LTDC reset + bit_offset: 26 + bit_size: 1 + - name: DSIRST + description: DSI reset + bit_offset: 27 + bit_size: 1 + - name: DFSDM1RST + description: DFSDM 1 reset + bit_offset: 29 + bit_size: 1 + - name: MDIOSRST + description: MDIOS reset + bit_offset: 30 + bit_size: 1 + - name: USBPHYCRST + description: USB OTG HS PHY controller reset + bit_offset: 31 + bit_size: 1 fieldset/BDCR: description: Backup domain control register fields: - - name: LSEON - description: External low-speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: External low-speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: External low-speed oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: LSEDRV - description: LSE oscillator drive capability - bit_offset: 3 - bit_size: 2 - enum: LSEDRV - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: Backup domain software reset - bit_offset: 16 - bit_size: 1 + - name: LSEON + description: External low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External low-speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: External low-speed oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: LSE oscillator drive capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 fieldset/CFGR: description: clock configuration register fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: System clock switch status - bit_offset: 2 - bit_size: 2 - enum: SWS - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - enum: HPRE - - name: PPRE1 - description: APB Low speed prescaler (APB1) - bit_offset: 10 - bit_size: 3 - enum: PPRE - - name: PPRE2 - description: APB high-speed prescaler (APB2) - bit_offset: 13 - bit_size: 3 - enum: PPRE - - name: RTCPRE - description: HSE division factor for RTC clock - bit_offset: 16 - bit_size: 5 - - name: MCO1 - description: Microcontroller clock output 1 - bit_offset: 21 - bit_size: 2 - enum: MCO1 - - name: I2SSRC - description: I2S clock selection - bit_offset: 23 - bit_size: 1 - enum: ISSRC - - name: MCO1PRE - description: MCO1 prescaler - bit_offset: 24 - bit_size: 3 - enum: MCOPRE - - name: MCO2PRE - description: MCO2 prescaler - bit_offset: 27 - bit_size: 3 - enum: MCOPRE - - name: MCO2 - description: Microcontroller clock output 2 - bit_offset: 30 - bit_size: 2 - enum: MCO2 + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 10 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high-speed prescaler (APB2) + bit_offset: 13 + bit_size: 3 + enum: PPRE + - name: RTCPRE + description: HSE division factor for RTC clock + bit_offset: 16 + bit_size: 5 + - name: MCO1 + description: Microcontroller clock output 1 + bit_offset: 21 + bit_size: 2 + enum: MCO1 + - name: I2SSRC + description: I2S clock selection + bit_offset: 23 + bit_size: 1 + enum: ISSRC + - name: MCO1PRE + description: MCO1 prescaler + bit_offset: 24 + bit_size: 3 + enum: MCOPRE + - name: MCO2PRE + description: MCO2 prescaler + bit_offset: 27 + bit_size: 3 + enum: MCOPRE + - name: MCO2 + description: Microcontroller clock output 2 + bit_offset: 30 + bit_size: 2 + enum: MCO2 fieldset/CIR: description: clock interrupt register fields: - - name: LSIRDYF - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - - name: HSIRDYF - description: HSI ready interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSERDYF - description: HSE ready interrupt flag - bit_offset: 3 - bit_size: 1 - - name: PLLRDYF - description: Main PLL (PLL) ready interrupt flag - bit_offset: 4 - bit_size: 1 - - name: PLLI2SRDYF - description: PLLI2S ready interrupt flag - bit_offset: 5 - bit_size: 1 - - name: PLLSAIRDYF - description: PLLSAI ready interrupt flag - bit_offset: 6 - bit_size: 1 - - name: CSSF - description: Clock security system interrupt flag - bit_offset: 7 - bit_size: 1 - - name: LSIRDYIE - description: LSI ready interrupt enable - bit_offset: 8 - bit_size: 1 - - name: LSERDYIE - description: LSE ready interrupt enable - bit_offset: 9 - bit_size: 1 - - name: HSIRDYIE - description: HSI ready interrupt enable - bit_offset: 10 - bit_size: 1 - - name: HSERDYIE - description: HSE ready interrupt enable - bit_offset: 11 - bit_size: 1 - - name: PLLRDYIE - description: Main PLL (PLL) ready interrupt enable - bit_offset: 12 - bit_size: 1 - - name: PLLI2SRDYIE - description: PLLI2S ready interrupt enable - bit_offset: 13 - bit_size: 1 - - name: PLLSAIRDYIE - description: PLLSAI Ready Interrupt Enable - bit_offset: 14 - bit_size: 1 - - name: LSIRDYC - description: LSI ready interrupt clear - bit_offset: 16 - bit_size: 1 - - name: LSERDYC - description: LSE ready interrupt clear - bit_offset: 17 - bit_size: 1 - - name: HSIRDYC - description: HSI ready interrupt clear - bit_offset: 18 - bit_size: 1 - - name: HSERDYC - description: HSE ready interrupt clear - bit_offset: 19 - bit_size: 1 - - name: PLLRDYC - description: Main PLL(PLL) ready interrupt clear - bit_offset: 20 - bit_size: 1 - - name: PLLI2SRDYC - description: PLLI2S ready interrupt clear - bit_offset: 21 - bit_size: 1 - - name: PLLSAIRDYC - description: PLLSAI Ready Interrupt Clear - bit_offset: 22 - bit_size: 1 - - name: CSSC - description: Clock security system interrupt clear - bit_offset: 23 - bit_size: 1 + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: Main PLL (PLL) ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLLI2SRDYF + description: PLLI2S ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: PLLSAIRDYF + description: PLLSAI ready interrupt flag + bit_offset: 6 + bit_size: 1 + - name: CSSF + description: Clock security system interrupt flag + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: Main PLL (PLL) ready interrupt enable + bit_offset: 12 + bit_size: 1 + - name: PLLI2SRDYIE + description: PLLI2S ready interrupt enable + bit_offset: 13 + bit_size: 1 + - name: PLLSAIRDYIE + description: PLLSAI Ready Interrupt Enable + bit_offset: 14 + bit_size: 1 + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: Main PLL(PLL) ready interrupt clear + bit_offset: 20 + bit_size: 1 + - name: PLLI2SRDYC + description: PLLI2S ready interrupt clear + bit_offset: 21 + bit_size: 1 + - name: PLLSAIRDYC + description: PLLSAI Ready Interrupt Clear + bit_offset: 22 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 fieldset/CR: description: clock control register fields: - - name: HSION - description: Internal high-speed clock enable - bit_offset: 0 - bit_size: 1 - - name: HSIRDY - description: Internal high-speed clock ready flag - bit_offset: 1 - bit_size: 1 - - name: HSITRIM - description: Internal high-speed clock trimming - bit_offset: 3 - bit_size: 5 - - name: HSICAL - description: Internal high-speed clock calibration - bit_offset: 8 - bit_size: 8 - - name: HSEON - description: HSE clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: HSE clock bypass - bit_offset: 18 - bit_size: 1 - - name: CSSON - description: Clock security system enable - bit_offset: 19 - bit_size: 1 - - name: PLLON - description: Main PLL (PLL) enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: Main PLL (PLL) clock ready flag - bit_offset: 25 - bit_size: 1 - - name: PLLI2SON - description: PLLI2S enable - bit_offset: 26 - bit_size: 1 - - name: PLLI2SRDY - description: PLLI2S clock ready flag - bit_offset: 27 - bit_size: 1 - - name: PLLSAION - description: PLLSAI enable - bit_offset: 28 - bit_size: 1 - - name: PLLSAIRDY - description: PLLSAI clock ready flag - bit_offset: 29 - bit_size: 1 + - name: HSION + description: Internal high-speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal high-speed clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSITRIM + description: Internal high-speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal high-speed clock calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: HSE clock bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: Main PLL (PLL) enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL (PLL) clock ready flag + bit_offset: 25 + bit_size: 1 + - name: PLLI2SON + description: PLLI2S enable + bit_offset: 26 + bit_size: 1 + - name: PLLI2SRDY + description: PLLI2S clock ready flag + bit_offset: 27 + bit_size: 1 + - name: PLLSAION + description: PLLSAI enable + bit_offset: 28 + bit_size: 1 + - name: PLLSAIRDY + description: PLLSAI clock ready flag + bit_offset: 29 + bit_size: 1 fieldset/CSR: description: clock control & status register fields: - - name: LSION - description: Internal low-speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: Internal low-speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: RMVF - description: Remove reset flag - bit_offset: 24 - bit_size: 1 - - name: BORRSTF - description: BOR reset flag - bit_offset: 25 - bit_size: 1 - - name: PADRSTF - description: PIN reset flag - bit_offset: 26 - bit_size: 1 - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: WDGRSTF - description: Independent watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSION + description: Internal low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low-speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + - name: BORRSTF + description: BOR reset flag + bit_offset: 25 + bit_size: 1 + - name: PADRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: WDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 fieldset/DCKCFGR1: description: dedicated clocks configuration register fields: - - name: PLLI2SDIVQ - description: PLLI2S division factor for SAI1 clock - bit_offset: 0 - bit_size: 5 - enum: PLLISDIVQ - - name: PLLSAIDIVQ - description: PLLSAI division factor for SAI1 clock - bit_offset: 8 - bit_size: 5 - enum: PLLSAIDIVQ - - name: PLLSAIDIVR - description: division factor for LCD_CLK - bit_offset: 16 - bit_size: 2 - enum: PLLSAIDIVR - - name: SAI1SEL - description: SAI1 clock source selection - bit_offset: 20 - bit_size: 2 - enum: SAISEL - - name: SAI2SEL - description: SAI2 clock source selection - bit_offset: 22 - bit_size: 2 - enum: SAISEL - - name: TIMPRE - description: Timers clocks prescalers selection - bit_offset: 24 - bit_size: 1 - enum: TIMPRE - - name: DFSDM1SEL - description: DFSDM1 clock source selection - bit_offset: 25 - bit_size: 1 - enum: DFSDMSEL - - name: ADFSDM1SEL - description: DFSDM1 AUDIO clock source selection - bit_offset: 26 - bit_size: 1 - enum: ADFSDMSEL + - name: PLLI2SDIVQ + description: PLLI2S division factor for SAI1 clock + bit_offset: 0 + bit_size: 5 + enum: PLLISDIVQ + - name: PLLSAIDIVQ + description: PLLSAI division factor for SAI1 clock + bit_offset: 8 + bit_size: 5 + enum: PLLSAIDIVQ + - name: PLLSAIDIVR + description: division factor for LCD_CLK + bit_offset: 16 + bit_size: 2 + enum: PLLSAIDIVR + - name: SAI1SEL + description: SAI1 clock source selection + bit_offset: 20 + bit_size: 2 + enum: SAISEL + - name: SAI2SEL + description: SAI2 clock source selection + bit_offset: 22 + bit_size: 2 + enum: SAISEL + - name: TIMPRE + description: Timers clocks prescalers selection + bit_offset: 24 + bit_size: 1 + enum: TIMPRE + - name: DFSDM1SEL + description: DFSDM1 clock source selection + bit_offset: 25 + bit_size: 1 + enum: DFSDMSEL + - name: ADFSDM1SEL + description: DFSDM1 AUDIO clock source selection + bit_offset: 26 + bit_size: 1 + enum: ADFSDMSEL fieldset/DCKCFGR2: description: dedicated clocks configuration register fields: - - name: USART1SEL - description: USART 1 clock source selection - bit_offset: 0 - bit_size: 2 - enum: USART1SEL - - name: USART2SEL - description: USART 2 clock source selection - bit_offset: 2 - bit_size: 2 - enum: USART2SEL - - name: USART3SEL - description: USART 3 clock source selection - bit_offset: 4 - bit_size: 2 - enum: USART2SEL - - name: UART4SEL - description: UART 4 clock source selection - bit_offset: 6 - bit_size: 2 - enum: USART2SEL - - name: UART5SEL - description: UART 5 clock source selection - bit_offset: 8 - bit_size: 2 - enum: USART2SEL - - name: USART6SEL - description: USART 6 clock source selection - bit_offset: 10 - bit_size: 2 - enum: USART1SEL - - name: UART7SEL - description: UART 7 clock source selection - bit_offset: 12 - bit_size: 2 - enum: USART2SEL - - name: UART8SEL - description: UART 8 clock source selection - bit_offset: 14 - bit_size: 2 - enum: USART2SEL - - name: I2C1SEL - description: I2C1 clock source selection - bit_offset: 16 - bit_size: 2 - enum: ICSEL - - name: I2C2SEL - description: I2C2 clock source selection - bit_offset: 18 - bit_size: 2 - enum: ICSEL - - name: I2C3SEL - description: I2C3 clock source selection - bit_offset: 20 - bit_size: 2 - enum: ICSEL - - name: I2C4SEL - description: I2C4 clock source selection - bit_offset: 22 - bit_size: 2 - enum: ICSEL - - name: LPTIM1SEL - description: Low power timer 1 clock source selection - bit_offset: 24 - bit_size: 2 - enum: LPTIMSEL - - name: CECSEL - description: HDMI-CEC clock source selection - bit_offset: 26 - bit_size: 1 - enum: CECSEL - - name: CK48MSEL - description: 48MHz clock source selection - bit_offset: 27 - bit_size: 1 - enum: CKMSEL - - name: SDMMC1SEL - description: SDMMC1 clock source selection - bit_offset: 28 - bit_size: 1 - enum: SDMMCSEL - - name: SDMMC2SEL - description: SDMMC2 clock source selection - bit_offset: 29 - bit_size: 1 - enum: SDMMCSEL - - name: DSISEL - description: DSI clock source selection - bit_offset: 30 - bit_size: 1 - enum: DSISEL + - name: USART1SEL + description: USART 1 clock source selection + bit_offset: 0 + bit_size: 2 + enum: USART1SEL + - name: USART2SEL + description: USART 2 clock source selection + bit_offset: 2 + bit_size: 2 + enum: USART2SEL + - name: USART3SEL + description: USART 3 clock source selection + bit_offset: 4 + bit_size: 2 + enum: USART2SEL + - name: UART4SEL + description: UART 4 clock source selection + bit_offset: 6 + bit_size: 2 + enum: USART2SEL + - name: UART5SEL + description: UART 5 clock source selection + bit_offset: 8 + bit_size: 2 + enum: USART2SEL + - name: USART6SEL + description: USART 6 clock source selection + bit_offset: 10 + bit_size: 2 + enum: USART1SEL + - name: UART7SEL + description: UART 7 clock source selection + bit_offset: 12 + bit_size: 2 + enum: USART2SEL + - name: UART8SEL + description: UART 8 clock source selection + bit_offset: 14 + bit_size: 2 + enum: USART2SEL + - name: I2C1SEL + description: I2C1 clock source selection + bit_offset: 16 + bit_size: 2 + enum: ICSEL + - name: I2C2SEL + description: I2C2 clock source selection + bit_offset: 18 + bit_size: 2 + enum: ICSEL + - name: I2C3SEL + description: I2C3 clock source selection + bit_offset: 20 + bit_size: 2 + enum: ICSEL + - name: I2C4SEL + description: I2C4 clock source selection + bit_offset: 22 + bit_size: 2 + enum: ICSEL + - name: LPTIM1SEL + description: Low power timer 1 clock source selection + bit_offset: 24 + bit_size: 2 + enum: LPTIMSEL + - name: CECSEL + description: HDMI-CEC clock source selection + bit_offset: 26 + bit_size: 1 + enum: CECSEL + - name: CK48MSEL + description: 48MHz clock source selection + bit_offset: 27 + bit_size: 1 + enum: CKMSEL + - name: SDMMC1SEL + description: SDMMC1 clock source selection + bit_offset: 28 + bit_size: 1 + enum: SDMMCSEL + - name: SDMMC2SEL + description: SDMMC2 clock source selection + bit_offset: 29 + bit_size: 1 + enum: SDMMCSEL + - name: DSISEL + description: DSI clock source selection + bit_offset: 30 + bit_size: 1 + enum: DSISEL fieldset/PLLCFGR: description: PLL configuration register fields: - - name: PLLM - description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - bit_offset: 0 - bit_size: 6 - - name: PLLN - description: Main PLL (PLL) multiplication factor for VCO - bit_offset: 6 - bit_size: 9 - - name: PLLP - description: Main PLL (PLL) division factor for main system clock - bit_offset: 16 - bit_size: 2 - enum: PLLP - - name: PLLSRC - description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - bit_offset: 22 - bit_size: 1 - enum: PLLSRC - - name: PLLQ - description: "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks" - bit_offset: 24 - bit_size: 4 - - name: PLLR - description: PLL division factor for DSI clock - bit_offset: 28 - bit_size: 3 + - name: PLLM + description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + bit_offset: 0 + bit_size: 6 + - name: PLLN + description: Main PLL (PLL) multiplication factor for VCO + bit_offset: 6 + bit_size: 9 + - name: PLLP + description: Main PLL (PLL) division factor for main system clock + bit_offset: 16 + bit_size: 2 + enum: PLLP + - name: PLLSRC + description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + bit_offset: 22 + bit_size: 1 + enum: PLLSRC + - name: PLLQ + description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + bit_offset: 24 + bit_size: 4 + - name: PLLR + description: PLL division factor for DSI clock + bit_offset: 28 + bit_size: 3 fieldset/PLLI2SCFGR: description: PLLI2S configuration register fields: - - name: PLLI2SN - description: PLLI2S multiplication factor for VCO - bit_offset: 6 - bit_size: 9 - - name: PLLI2SP - description: PLLI2S division factor for SPDIFRX clock - bit_offset: 16 - bit_size: 2 - enum: PLLISP - - name: PLLI2SQ - description: PLLI2S division factor for SAI1 clock - bit_offset: 24 - bit_size: 4 - - name: PLLI2SR - description: PLLI2S division factor for I2S clocks - bit_offset: 28 - bit_size: 3 + - name: PLLI2SN + description: PLLI2S multiplication factor for VCO + bit_offset: 6 + bit_size: 9 + - name: PLLI2SP + description: PLLI2S division factor for SPDIFRX clock + bit_offset: 16 + bit_size: 2 + enum: PLLISP + - name: PLLI2SQ + description: PLLI2S division factor for SAI1 clock + bit_offset: 24 + bit_size: 4 + - name: PLLI2SR + description: PLLI2S division factor for I2S clocks + bit_offset: 28 + bit_size: 3 fieldset/PLLSAICFGR: description: PLL configuration register fields: - - name: PLLSAIN - description: PLLSAI division factor for VCO - bit_offset: 6 - bit_size: 9 - - name: PLLSAIP - description: PLLSAI division factor for 48MHz clock - bit_offset: 16 - bit_size: 2 - enum: PLLSAIP - - name: PLLSAIQ - description: PLLSAI division factor for SAI clock - bit_offset: 24 - bit_size: 4 - - name: PLLSAIR - description: PLLSAI division factor for LCD clock - bit_offset: 28 - bit_size: 3 + - name: PLLSAIN + description: PLLSAI division factor for VCO + bit_offset: 6 + bit_size: 9 + - name: PLLSAIP + description: PLLSAI division factor for 48MHz clock + bit_offset: 16 + bit_size: 2 + enum: PLLSAIP + - name: PLLSAIQ + description: PLLSAI division factor for SAI clock + bit_offset: 24 + bit_size: 4 + - name: PLLSAIR + description: PLLSAI division factor for LCD clock + bit_offset: 28 + bit_size: 3 fieldset/SSCGR: description: spread spectrum clock generation register fields: - - name: MODPER - description: Modulation period - bit_offset: 0 - bit_size: 13 - - name: INCSTEP - description: Incrementation step - bit_offset: 13 - bit_size: 15 - - name: SPREADSEL - description: Spread Select - bit_offset: 30 - bit_size: 1 - enum: SPREADSEL - - name: SSCGEN - description: Spread spectrum modulation enable - bit_offset: 31 - bit_size: 1 + - name: MODPER + description: Modulation period + bit_offset: 0 + bit_size: 13 + - name: INCSTEP + description: Incrementation step + bit_offset: 13 + bit_size: 15 + - name: SPREADSEL + description: Spread Select + bit_offset: 30 + bit_size: 1 + enum: SPREADSEL + - name: SSCGEN + description: Spread spectrum modulation enable + bit_offset: 31 + bit_size: 1 enum/ADFSDMSEL: bit_size: 1 variants: - - name: SAI1 - description: SAI1 clock selected as DFSDM1 Audio clock source - value: 0 - - name: SAI2 - description: SAI2 clock selected as DFSDM1 Audio clock source - value: 1 + - name: SAI1 + description: SAI1 clock selected as DFSDM1 Audio clock source + value: 0 + - name: SAI2 + description: SAI2 clock selected as DFSDM1 Audio clock source + value: 1 enum/CECSEL: bit_size: 1 variants: - - name: LSE - description: LSE clock is selected as HDMI-CEC clock - value: 0 - - name: HSI_Div488 - description: HSI divided by 488 clock is selected as HDMI-CEC clock - value: 1 + - name: LSE + description: LSE clock is selected as HDMI-CEC clock + value: 0 + - name: HSI_Div488 + description: HSI divided by 488 clock is selected as HDMI-CEC clock + value: 1 enum/CKMSEL: bit_size: 1 variants: - - name: PLL - description: 48MHz clock from PLL is selected - value: 0 - - name: PLLSAI - description: 48MHz clock from PLLSAI is selected - value: 1 + - name: PLL + description: 48MHz clock from PLL is selected + value: 0 + - name: PLLSAI + description: 48MHz clock from PLLSAI is selected + value: 1 enum/DFSDMSEL: bit_size: 1 variants: - - name: APB2 - description: APB2 clock (PCLK2) selected as DFSDM1 Kernel clock source - value: 0 - - name: SYSCLK - description: System clock (SYSCLK) clock selected as DFSDM1 Kernel clock source - value: 1 + - name: APB2 + description: APB2 clock (PCLK2) selected as DFSDM1 Kernel clock source + value: 0 + - name: SYSCLK + description: System clock (SYSCLK) clock selected as DFSDM1 Kernel clock source + value: 1 enum/DSISEL: bit_size: 1 variants: - - name: DSI_PHY - description: DSI-PHY used as DSI byte lane clock source (usual case) - value: 0 - - name: PLLR - description: "PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)" - value: 1 + - name: DSI_PHY + description: DSI-PHY used as DSI byte lane clock source (usual case) + value: 0 + - name: PLLR + description: PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode) + value: 1 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: SYSCLK not divided - value: 0 - - name: Div2 - description: SYSCLK divided by 2 - value: 8 - - name: Div4 - description: SYSCLK divided by 4 - value: 9 - - name: Div8 - description: SYSCLK divided by 8 - value: 10 - - name: Div16 - description: SYSCLK divided by 16 - value: 11 - - name: Div64 - description: SYSCLK divided by 64 - value: 12 - - name: Div128 - description: SYSCLK divided by 128 - value: 13 - - name: Div256 - description: SYSCLK divided by 256 - value: 14 - - name: Div512 - description: SYSCLK divided by 512 - value: 15 + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 enum/ICSEL: bit_size: 2 variants: - - name: APB - description: APB clock selected as I2C clock - value: 0 - - name: SYSCLK - description: System clock selected as I2C clock - value: 1 - - name: HSI - description: HSI clock selected as I2C clock - value: 2 + - name: APB + description: APB clock selected as I2C clock + value: 0 + - name: SYSCLK + description: System clock selected as I2C clock + value: 1 + - name: HSI + description: HSI clock selected as I2C clock + value: 2 enum/ISSRC: bit_size: 1 variants: - - name: PLLI2S - description: PLLI2S clock used as I2S clock source - value: 0 - - name: CKIN - description: External clock mapped on the I2S_CKIN pin used as I2S clock source - value: 1 + - name: PLLI2S + description: PLLI2S clock used as I2S clock source + value: 0 + - name: CKIN + description: External clock mapped on the I2S_CKIN pin used as I2S clock source + value: 1 enum/LPTIMSEL: bit_size: 2 variants: - - name: APB1 - description: APB1 clock (PCLK1) selected as LPTILM1 clock - value: 0 - - name: LSI - description: LSI clock is selected as LPTILM1 clock - value: 1 - - name: HSI - description: HSI clock is selected as LPTILM1 clock - value: 2 - - name: LSE - description: LSE clock is selected as LPTILM1 clock - value: 3 + - name: APB1 + description: APB1 clock (PCLK1) selected as LPTILM1 clock + value: 0 + - name: LSI + description: LSI clock is selected as LPTILM1 clock + value: 1 + - name: HSI + description: HSI clock is selected as LPTILM1 clock + value: 2 + - name: LSE + description: LSE clock is selected as LPTILM1 clock + value: 3 enum/LSEDRV: bit_size: 2 variants: - - name: Low - description: Low drive capacity - value: 0 - - name: MediumHigh - description: Medium-high drive capacity - value: 1 - - name: MediumLow - description: Medium-low drive capacity - value: 2 - - name: High - description: High drive capacity - value: 3 + - name: Low + description: Low drive capacity + value: 0 + - name: MediumHigh + description: Medium-high drive capacity + value: 1 + - name: MediumLow + description: Medium-low drive capacity + value: 2 + - name: High + description: High drive capacity + value: 3 enum/MCO1: bit_size: 2 variants: - - name: HSI - description: HSI clock selected - value: 0 - - name: LSE - description: LSE oscillator selected - value: 1 - - name: HSE - description: HSE oscillator clock selected - value: 2 - - name: PLL - description: PLL clock selected - value: 3 + - name: HSI + description: HSI clock selected + value: 0 + - name: LSE + description: LSE oscillator selected + value: 1 + - name: HSE + description: HSE oscillator clock selected + value: 2 + - name: PLL + description: PLL clock selected + value: 3 enum/MCO2: bit_size: 2 variants: - - name: SYSCLK - description: System clock (SYSCLK) selected - value: 0 - - name: PLLI2S - description: PLLI2S clock selected - value: 1 - - name: HSE - description: HSE oscillator clock selected - value: 2 - - name: PLL - description: PLL clock selected - value: 3 + - name: SYSCLK + description: System clock (SYSCLK) selected + value: 0 + - name: PLLI2S + description: PLLI2S clock selected + value: 1 + - name: HSE + description: HSE oscillator clock selected + value: 2 + - name: PLL + description: PLL clock selected + value: 3 enum/MCOPRE: bit_size: 3 variants: - - name: Div1 - description: No division - value: 0 - - name: Div2 - description: Division by 2 - value: 4 - - name: Div3 - description: Division by 3 - value: 5 - - name: Div4 - description: Division by 4 - value: 6 - - name: Div5 - description: Division by 5 - value: 7 + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 4 + - name: Div3 + description: Division by 3 + value: 5 + - name: Div4 + description: Division by 4 + value: 6 + - name: Div5 + description: Division by 5 + value: 7 enum/PLLISDIVQ: bit_size: 5 variants: - - name: Div1 - description: PLLI2SDIVQ = /1 - value: 0 - - name: Div2 - description: PLLI2SDIVQ = /2 - value: 1 - - name: Div3 - description: PLLI2SDIVQ = /3 - value: 2 - - name: Div4 - description: PLLI2SDIVQ = /4 - value: 3 - - name: Div5 - description: PLLI2SDIVQ = /5 - value: 4 - - name: Div6 - description: PLLI2SDIVQ = /6 - value: 5 - - name: Div7 - description: PLLI2SDIVQ = /7 - value: 6 - - name: Div8 - description: PLLI2SDIVQ = /8 - value: 7 - - name: Div9 - description: PLLI2SDIVQ = /9 - value: 8 - - name: Div10 - description: PLLI2SDIVQ = /10 - value: 9 - - name: Div11 - description: PLLI2SDIVQ = /11 - value: 10 - - name: Div12 - description: PLLI2SDIVQ = /12 - value: 11 - - name: Div13 - description: PLLI2SDIVQ = /13 - value: 12 - - name: Div14 - description: PLLI2SDIVQ = /14 - value: 13 - - name: Div15 - description: PLLI2SDIVQ = /15 - value: 14 - - name: Div16 - description: PLLI2SDIVQ = /16 - value: 15 - - name: Div17 - description: PLLI2SDIVQ = /17 - value: 16 - - name: Div18 - description: PLLI2SDIVQ = /18 - value: 17 - - name: Div19 - description: PLLI2SDIVQ = /19 - value: 18 - - name: Div20 - description: PLLI2SDIVQ = /20 - value: 19 - - name: Div21 - description: PLLI2SDIVQ = /21 - value: 20 - - name: Div22 - description: PLLI2SDIVQ = /22 - value: 21 - - name: Div23 - description: PLLI2SDIVQ = /23 - value: 22 - - name: Div24 - description: PLLI2SDIVQ = /24 - value: 23 - - name: Div25 - description: PLLI2SDIVQ = /25 - value: 24 - - name: Div26 - description: PLLI2SDIVQ = /26 - value: 25 - - name: Div27 - description: PLLI2SDIVQ = /27 - value: 26 - - name: Div28 - description: PLLI2SDIVQ = /28 - value: 27 - - name: Div29 - description: PLLI2SDIVQ = /29 - value: 28 - - name: Div30 - description: PLLI2SDIVQ = /30 - value: 29 - - name: Div31 - description: PLLI2SDIVQ = /31 - value: 30 - - name: Div32 - description: PLLI2SDIVQ = /32 - value: 31 + - name: Div1 + description: PLLI2SDIVQ = /1 + value: 0 + - name: Div2 + description: PLLI2SDIVQ = /2 + value: 1 + - name: Div3 + description: PLLI2SDIVQ = /3 + value: 2 + - name: Div4 + description: PLLI2SDIVQ = /4 + value: 3 + - name: Div5 + description: PLLI2SDIVQ = /5 + value: 4 + - name: Div6 + description: PLLI2SDIVQ = /6 + value: 5 + - name: Div7 + description: PLLI2SDIVQ = /7 + value: 6 + - name: Div8 + description: PLLI2SDIVQ = /8 + value: 7 + - name: Div9 + description: PLLI2SDIVQ = /9 + value: 8 + - name: Div10 + description: PLLI2SDIVQ = /10 + value: 9 + - name: Div11 + description: PLLI2SDIVQ = /11 + value: 10 + - name: Div12 + description: PLLI2SDIVQ = /12 + value: 11 + - name: Div13 + description: PLLI2SDIVQ = /13 + value: 12 + - name: Div14 + description: PLLI2SDIVQ = /14 + value: 13 + - name: Div15 + description: PLLI2SDIVQ = /15 + value: 14 + - name: Div16 + description: PLLI2SDIVQ = /16 + value: 15 + - name: Div17 + description: PLLI2SDIVQ = /17 + value: 16 + - name: Div18 + description: PLLI2SDIVQ = /18 + value: 17 + - name: Div19 + description: PLLI2SDIVQ = /19 + value: 18 + - name: Div20 + description: PLLI2SDIVQ = /20 + value: 19 + - name: Div21 + description: PLLI2SDIVQ = /21 + value: 20 + - name: Div22 + description: PLLI2SDIVQ = /22 + value: 21 + - name: Div23 + description: PLLI2SDIVQ = /23 + value: 22 + - name: Div24 + description: PLLI2SDIVQ = /24 + value: 23 + - name: Div25 + description: PLLI2SDIVQ = /25 + value: 24 + - name: Div26 + description: PLLI2SDIVQ = /26 + value: 25 + - name: Div27 + description: PLLI2SDIVQ = /27 + value: 26 + - name: Div28 + description: PLLI2SDIVQ = /28 + value: 27 + - name: Div29 + description: PLLI2SDIVQ = /29 + value: 28 + - name: Div30 + description: PLLI2SDIVQ = /30 + value: 29 + - name: Div31 + description: PLLI2SDIVQ = /31 + value: 30 + - name: Div32 + description: PLLI2SDIVQ = /32 + value: 31 enum/PLLISP: bit_size: 2 variants: - - name: Div2 - description: PLL*P=2 - value: 0 - - name: Div4 - description: PLL*P=4 - value: 1 - - name: Div6 - description: PLL*P=6 - value: 2 - - name: Div8 - description: PLL*P=8 - value: 3 + - name: Div2 + description: PLL*P=2 + value: 0 + - name: Div4 + description: PLL*P=4 + value: 1 + - name: Div6 + description: PLL*P=6 + value: 2 + - name: Div8 + description: PLL*P=8 + value: 3 enum/PLLP: bit_size: 2 variants: - - name: Div2 - description: PLLP=2 - value: 0 - - name: Div4 - description: PLLP=4 - value: 1 - - name: Div6 - description: PLLP=6 - value: 2 - - name: Div8 - description: PLLP=8 - value: 3 + - name: Div2 + description: PLLP=2 + value: 0 + - name: Div4 + description: PLLP=4 + value: 1 + - name: Div6 + description: PLLP=6 + value: 2 + - name: Div8 + description: PLLP=8 + value: 3 enum/PLLSAIDIVQ: bit_size: 5 variants: - - name: Div1 - description: PLLSAIDIVQ = /1 - value: 0 - - name: Div2 - description: PLLSAIDIVQ = /2 - value: 1 - - name: Div3 - description: PLLSAIDIVQ = /3 - value: 2 - - name: Div4 - description: PLLSAIDIVQ = /4 - value: 3 - - name: Div5 - description: PLLSAIDIVQ = /5 - value: 4 - - name: Div6 - description: PLLSAIDIVQ = /6 - value: 5 - - name: Div7 - description: PLLSAIDIVQ = /7 - value: 6 - - name: Div8 - description: PLLSAIDIVQ = /8 - value: 7 - - name: Div9 - description: PLLSAIDIVQ = /9 - value: 8 - - name: Div10 - description: PLLSAIDIVQ = /10 - value: 9 - - name: Div11 - description: PLLSAIDIVQ = /11 - value: 10 - - name: Div12 - description: PLLSAIDIVQ = /12 - value: 11 - - name: Div13 - description: PLLSAIDIVQ = /13 - value: 12 - - name: Div14 - description: PLLSAIDIVQ = /14 - value: 13 - - name: Div15 - description: PLLSAIDIVQ = /15 - value: 14 - - name: Div16 - description: PLLSAIDIVQ = /16 - value: 15 - - name: Div17 - description: PLLSAIDIVQ = /17 - value: 16 - - name: Div18 - description: PLLSAIDIVQ = /18 - value: 17 - - name: Div19 - description: PLLSAIDIVQ = /19 - value: 18 - - name: Div20 - description: PLLSAIDIVQ = /20 - value: 19 - - name: Div21 - description: PLLSAIDIVQ = /21 - value: 20 - - name: Div22 - description: PLLSAIDIVQ = /22 - value: 21 - - name: Div23 - description: PLLSAIDIVQ = /23 - value: 22 - - name: Div24 - description: PLLSAIDIVQ = /24 - value: 23 - - name: Div25 - description: PLLSAIDIVQ = /25 - value: 24 - - name: Div26 - description: PLLSAIDIVQ = /26 - value: 25 - - name: Div27 - description: PLLSAIDIVQ = /27 - value: 26 - - name: Div28 - description: PLLSAIDIVQ = /28 - value: 27 - - name: Div29 - description: PLLSAIDIVQ = /29 - value: 28 - - name: Div30 - description: PLLSAIDIVQ = /30 - value: 29 - - name: Div31 - description: PLLSAIDIVQ = /31 - value: 30 - - name: Div32 - description: PLLSAIDIVQ = /32 - value: 31 + - name: Div1 + description: PLLSAIDIVQ = /1 + value: 0 + - name: Div2 + description: PLLSAIDIVQ = /2 + value: 1 + - name: Div3 + description: PLLSAIDIVQ = /3 + value: 2 + - name: Div4 + description: PLLSAIDIVQ = /4 + value: 3 + - name: Div5 + description: PLLSAIDIVQ = /5 + value: 4 + - name: Div6 + description: PLLSAIDIVQ = /6 + value: 5 + - name: Div7 + description: PLLSAIDIVQ = /7 + value: 6 + - name: Div8 + description: PLLSAIDIVQ = /8 + value: 7 + - name: Div9 + description: PLLSAIDIVQ = /9 + value: 8 + - name: Div10 + description: PLLSAIDIVQ = /10 + value: 9 + - name: Div11 + description: PLLSAIDIVQ = /11 + value: 10 + - name: Div12 + description: PLLSAIDIVQ = /12 + value: 11 + - name: Div13 + description: PLLSAIDIVQ = /13 + value: 12 + - name: Div14 + description: PLLSAIDIVQ = /14 + value: 13 + - name: Div15 + description: PLLSAIDIVQ = /15 + value: 14 + - name: Div16 + description: PLLSAIDIVQ = /16 + value: 15 + - name: Div17 + description: PLLSAIDIVQ = /17 + value: 16 + - name: Div18 + description: PLLSAIDIVQ = /18 + value: 17 + - name: Div19 + description: PLLSAIDIVQ = /19 + value: 18 + - name: Div20 + description: PLLSAIDIVQ = /20 + value: 19 + - name: Div21 + description: PLLSAIDIVQ = /21 + value: 20 + - name: Div22 + description: PLLSAIDIVQ = /22 + value: 21 + - name: Div23 + description: PLLSAIDIVQ = /23 + value: 22 + - name: Div24 + description: PLLSAIDIVQ = /24 + value: 23 + - name: Div25 + description: PLLSAIDIVQ = /25 + value: 24 + - name: Div26 + description: PLLSAIDIVQ = /26 + value: 25 + - name: Div27 + description: PLLSAIDIVQ = /27 + value: 26 + - name: Div28 + description: PLLSAIDIVQ = /28 + value: 27 + - name: Div29 + description: PLLSAIDIVQ = /29 + value: 28 + - name: Div30 + description: PLLSAIDIVQ = /30 + value: 29 + - name: Div31 + description: PLLSAIDIVQ = /31 + value: 30 + - name: Div32 + description: PLLSAIDIVQ = /32 + value: 31 enum/PLLSAIDIVR: bit_size: 2 variants: - - name: Div2 - description: PLLSAIDIVR = /2 - value: 0 - - name: Div4 - description: PLLSAIDIVR = /4 - value: 1 - - name: Div8 - description: PLLSAIDIVR = /8 - value: 2 - - name: Div16 - description: PLLSAIDIVR = /16 - value: 3 + - name: Div2 + description: PLLSAIDIVR = /2 + value: 0 + - name: Div4 + description: PLLSAIDIVR = /4 + value: 1 + - name: Div8 + description: PLLSAIDIVR = /8 + value: 2 + - name: Div16 + description: PLLSAIDIVR = /16 + value: 3 enum/PLLSAIP: bit_size: 2 variants: - - name: Div2 - description: PLL*P=2 - value: 0 - - name: Div4 - description: PLL*P=4 - value: 1 - - name: Div6 - description: PLL*P=6 - value: 2 - - name: Div8 - description: PLL*P=8 - value: 3 + - name: Div2 + description: PLL*P=2 + value: 0 + - name: Div4 + description: PLL*P=4 + value: 1 + - name: Div6 + description: PLL*P=6 + value: 2 + - name: Div8 + description: PLL*P=8 + value: 3 enum/PLLSRC: bit_size: 1 variants: - - name: HSI - description: HSI clock selected as PLL and PLLI2S clock entry - value: 0 - - name: HSE - description: HSE oscillator clock selected as PLL and PLLI2S clock entry - value: 1 + - name: HSI + description: HSI clock selected as PLL and PLLI2S clock entry + value: 0 + - name: HSE + description: HSE oscillator clock selected as PLL and PLLI2S clock entry + value: 1 enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK divided by 2 - value: 4 - - name: Div4 - description: HCLK divided by 4 - value: 5 - - name: Div8 - description: HCLK divided by 8 - value: 6 - - name: Div16 - description: HCLK divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: HSE oscillator clock divided by a prescaler used as RTC clock - value: 3 + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 enum/SAISEL: bit_size: 2 variants: - - name: PLLSAI - description: SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - value: 0 - - name: PLLI2S - description: SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - value: 1 - - name: AFIF - description: SAI2 clock frequency = Alternate function input frequency - value: 2 - - name: HSI_HSE - description: SAI2 clock frequency = HSI or HSE - value: 3 + - name: PLLSAI + description: SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + value: 0 + - name: PLLI2S + description: SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + value: 1 + - name: AFIF + description: SAI2 clock frequency = Alternate function input frequency + value: 2 + - name: HSI_HSE + description: SAI2 clock frequency = HSI or HSE + value: 3 enum/SDMMCSEL: bit_size: 1 variants: - - name: CK48M - description: 48 MHz clock is selected as SD clock - value: 0 - - name: SYSCLK - description: System clock is selected as SD clock - value: 1 + - name: CK48M + description: 48 MHz clock is selected as SD clock + value: 0 + - name: SYSCLK + description: System clock is selected as SD clock + value: 1 enum/SPREADSEL: bit_size: 1 variants: - - name: Center - description: Center spread - value: 0 - - name: Down - description: Down spread - value: 1 + - name: Center + description: Center spread + value: 0 + - name: Down + description: Down spread + value: 1 enum/SW: bit_size: 2 variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: HSE - description: HSE selected as system clock - value: 1 - - name: PLL - description: PLL selected as system clock - value: 2 -enum/SWS: - bit_size: 2 - variants: - - name: HSI - description: HSI oscillator used as system clock - value: 0 - - name: HSE - description: HSE oscillator used as system clock - value: 1 - - name: PLL - description: PLL used as system clock - value: 2 + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL + description: PLL used as system clock + value: 2 enum/TIMPRE: bit_size: 1 variants: - - name: Mul2 - description: "If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx" - value: 0 - - name: Mul4 - description: "If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx" - value: 1 + - name: Mul2 + description: If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx + value: 0 + - name: Mul4 + description: If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx + value: 1 enum/USART1SEL: bit_size: 2 variants: - - name: APB2 - description: APB2 clock (PCLK2) is selected as USART clock - value: 0 - - name: SYSCLK - description: System clock is selected as USART clock - value: 1 - - name: HSI - description: HSI clock is selected as USART clock - value: 2 - - name: LSE - description: LSE clock is selected as USART clock - value: 3 + - name: APB2 + description: APB2 clock (PCLK2) is selected as USART clock + value: 0 + - name: SYSCLK + description: System clock is selected as USART clock + value: 1 + - name: HSI + description: HSI clock is selected as USART clock + value: 2 + - name: LSE + description: LSE clock is selected as USART clock + value: 3 enum/USART2SEL: bit_size: 2 variants: - - name: APB1 - description: APB1 clock (PCLK1) is selected as USART clock - value: 0 - - name: SYSCLK - description: System clock is selected as USART clock - value: 1 - - name: HSI - description: HSI clock is selected as USART clock - value: 2 - - name: LSE - description: LSE clock is selected as USART clock - value: 3 + - name: APB1 + description: APB1 clock (PCLK1) is selected as USART clock + value: 0 + - name: SYSCLK + description: System clock is selected as USART clock + value: 1 + - name: HSI + description: HSI clock is selected as USART clock + value: 2 + - name: LSE + description: LSE clock is selected as USART clock + value: 3 diff --git a/data/registers/rcc_g0.yaml b/data/registers/rcc_g0.yaml index 95a1a46..c6856dc 100644 --- a/data/registers/rcc_g0.yaml +++ b/data/registers/rcc_g0.yaml @@ -1,1639 +1,1638 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: Clock control register - byte_offset: 0 - fieldset: CR - - name: ICSCR - description: Internal clock sources calibration register - byte_offset: 4 - fieldset: ICSCR - - name: CFGR - description: Clock configuration register - byte_offset: 8 - fieldset: CFGR - - name: PLLSYSCFGR - description: PLL configuration register - byte_offset: 12 - fieldset: PLLSYSCFGR - - name: CRRCR - description: RCC clock recovery RC register - byte_offset: 20 - access: Read - fieldset: CRRCR - - name: CIER - description: Clock interrupt enable register - byte_offset: 24 - fieldset: CIER - - name: CIFR - description: Clock interrupt flag register - byte_offset: 28 - access: Read - fieldset: CIFR - - name: CICR - description: Clock interrupt clear register - byte_offset: 32 - access: Write - fieldset: CICR - - name: GPIORSTR - description: GPIO reset register - byte_offset: 36 - fieldset: GPIORSTR - - name: AHBRSTR - description: AHB peripheral reset register - byte_offset: 40 - fieldset: AHBRSTR - - name: APBRSTR1 - description: APB peripheral reset register 1 - byte_offset: 44 - fieldset: APBRSTR1 - - name: APBRSTR2 - description: APB peripheral reset register 2 - byte_offset: 48 - fieldset: APBRSTR2 - - name: GPIOENR - description: GPIO clock enable register - byte_offset: 52 - fieldset: GPIOENR - - name: AHBENR - description: AHB peripheral clock enable register - byte_offset: 56 - fieldset: AHBENR - - name: APBENR1 - description: APB peripheral clock enable register 1 - byte_offset: 60 - fieldset: APBENR1 - - name: APBENR2 - description: APB peripheral clock enable register 2 - byte_offset: 64 - fieldset: APBENR2 - - name: GPIOSMENR - description: GPIO in Sleep mode clock enable register - byte_offset: 68 - fieldset: GPIOSMENR - - name: AHBSMENR - description: AHB peripheral clock enable in Sleep mode register - byte_offset: 72 - fieldset: AHBSMENR - - name: APBSMENR1 - description: APB peripheral clock enable in Sleep mode register 1 - byte_offset: 76 - fieldset: APBSMENR1 - - name: APBSMENR2 - description: APB peripheral clock enable in Sleep mode register 2 - byte_offset: 80 - fieldset: APBSMENR2 - - name: CCIPR - description: Peripherals independent clock configuration register - byte_offset: 84 - fieldset: CCIPR - - name: CCIPR2 - description: Peripherals independent clock configuration register 2 - byte_offset: 88 - fieldset: CCIPR2 - - name: BDCR - description: RTC domain control register - byte_offset: 92 - fieldset: BDCR - - name: CSR - description: Control/status register - byte_offset: 96 - fieldset: CSR + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: Internal clock sources calibration register + byte_offset: 4 + fieldset: ICSCR + - name: CFGR + description: Clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: PLLSYSCFGR + description: PLL configuration register + byte_offset: 12 + fieldset: PLLSYSCFGR + - name: CRRCR + description: RCC clock recovery RC register + byte_offset: 20 + access: Read + fieldset: CRRCR + - name: CIER + description: Clock interrupt enable register + byte_offset: 24 + fieldset: CIER + - name: CIFR + description: Clock interrupt flag register + byte_offset: 28 + access: Read + fieldset: CIFR + - name: CICR + description: Clock interrupt clear register + byte_offset: 32 + access: Write + fieldset: CICR + - name: GPIORSTR + description: GPIO reset register + byte_offset: 36 + fieldset: GPIORSTR + - name: AHBRSTR + description: AHB peripheral reset register + byte_offset: 40 + fieldset: AHBRSTR + - name: APBRSTR1 + description: APB peripheral reset register 1 + byte_offset: 44 + fieldset: APBRSTR1 + - name: APBRSTR2 + description: APB peripheral reset register 2 + byte_offset: 48 + fieldset: APBRSTR2 + - name: GPIOENR + description: GPIO clock enable register + byte_offset: 52 + fieldset: GPIOENR + - name: AHBENR + description: AHB peripheral clock enable register + byte_offset: 56 + fieldset: AHBENR + - name: APBENR1 + description: APB peripheral clock enable register 1 + byte_offset: 60 + fieldset: APBENR1 + - name: APBENR2 + description: APB peripheral clock enable register 2 + byte_offset: 64 + fieldset: APBENR2 + - name: GPIOSMENR + description: GPIO in Sleep mode clock enable register + byte_offset: 68 + fieldset: GPIOSMENR + - name: AHBSMENR + description: AHB peripheral clock enable in Sleep mode register + byte_offset: 72 + fieldset: AHBSMENR + - name: APBSMENR1 + description: APB peripheral clock enable in Sleep mode register 1 + byte_offset: 76 + fieldset: APBSMENR1 + - name: APBSMENR2 + description: APB peripheral clock enable in Sleep mode register 2 + byte_offset: 80 + fieldset: APBSMENR2 + - name: CCIPR + description: Peripherals independent clock configuration register + byte_offset: 84 + fieldset: CCIPR + - name: CCIPR2 + description: Peripherals independent clock configuration register 2 + byte_offset: 88 + fieldset: CCIPR2 + - name: BDCR + description: RTC domain control register + byte_offset: 92 + fieldset: BDCR + - name: CSR + description: Control/status register + byte_offset: 96 + fieldset: CSR fieldset/AHBENR: description: AHB peripheral clock enable register fields: - - name: DMA1EN - description: DMA1 clock enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: DMA2 clock enable - bit_offset: 1 - bit_size: 1 - - name: FLASHEN - description: Flash memory interface clock enable - bit_offset: 8 - bit_size: 1 - - name: CRCEN - description: CRC clock enable - bit_offset: 12 - bit_size: 1 - - name: AESEN - description: AES hardware accelerator - bit_offset: 16 - bit_size: 1 - - name: RNGEN - description: Random number generator clock enable - bit_offset: 18 - bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: FLASHEN + description: Flash memory interface clock enable + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: AESEN + description: AES hardware accelerator + bit_offset: 16 + bit_size: 1 + - name: RNGEN + description: Random number generator clock enable + bit_offset: 18 + bit_size: 1 fieldset/AHBRSTR: description: AHB peripheral reset register fields: - - name: DMA1RST - description: DMA1 reset - bit_offset: 0 - bit_size: 1 - - name: DMA2RST - description: DMA1 reset - bit_offset: 1 - bit_size: 1 - - name: FLASHRST - description: FLASH reset - bit_offset: 8 - bit_size: 1 - - name: CRCRST - description: CRC reset - bit_offset: 12 - bit_size: 1 - - name: AESRST - description: AES hardware accelerator reset - bit_offset: 16 - bit_size: 1 - - name: RNGRST - description: Random number generator reset - bit_offset: 18 - bit_size: 1 + - name: DMA1RST + description: DMA1 reset + bit_offset: 0 + bit_size: 1 + - name: DMA2RST + description: DMA1 reset + bit_offset: 1 + bit_size: 1 + - name: FLASHRST + description: FLASH reset + bit_offset: 8 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 + - name: AESRST + description: AES hardware accelerator reset + bit_offset: 16 + bit_size: 1 + - name: RNGRST + description: Random number generator reset + bit_offset: 18 + bit_size: 1 fieldset/AHBSMENR: description: AHB peripheral clock enable in Sleep mode register fields: - - name: DMA1SMEN - description: DMA1 clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: DMA2SMEN - description: DMA2 clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: FLASHSMEN - description: Flash memory interface clock enable during Sleep mode - bit_offset: 8 - bit_size: 1 - - name: SRAMSMEN - description: SRAM clock enable during Sleep mode - bit_offset: 9 - bit_size: 1 - - name: CRCSMEN - description: CRC clock enable during Sleep mode - bit_offset: 12 - bit_size: 1 - - name: AESSMEN - description: AES hardware accelerator clock enable during Sleep mode - bit_offset: 16 - bit_size: 1 - - name: RNGSMEN - description: Random number generator clock enable during Sleep mode - bit_offset: 18 - bit_size: 1 + - name: DMA1SMEN + description: DMA1 clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: DMA2SMEN + description: DMA2 clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: FLASHSMEN + description: Flash memory interface clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: SRAMSMEN + description: SRAM clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: CRCSMEN + description: CRC clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: AESSMEN + description: AES hardware accelerator clock enable during Sleep mode + bit_offset: 16 + bit_size: 1 + - name: RNGSMEN + description: Random number generator clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 fieldset/APBENR1: description: APB peripheral clock enable register 1 fields: - - name: TIM2EN - description: TIM2 timer clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: TIM3 timer clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: TIM4 timer clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM6EN - description: TIM6 timer clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: TIM7 timer clock enable - bit_offset: 5 - bit_size: 1 - - name: LPUART2EN - description: LPUART2 clock enable - bit_offset: 7 - bit_size: 1 - - name: USART5EN - description: USART5EN - bit_offset: 8 - bit_size: 1 - - name: USART6EN - description: USART6EN - bit_offset: 9 - bit_size: 1 - - name: RTCAPBEN - description: RTC APB clock enable - bit_offset: 10 - bit_size: 1 - - name: WWDGEN - description: WWDG clock enable - bit_offset: 11 - bit_size: 1 - - name: FDCANEN - description: USBEN - bit_offset: 12 - bit_size: 1 - - name: USBEN - description: USBEN - bit_offset: 13 - bit_size: 1 - - name: SPI2EN - description: SPI2 clock enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI3 clock enable - bit_offset: 15 - bit_size: 1 - - name: CRSEN - description: CRSEN - bit_offset: 16 - bit_size: 1 - - name: USART2EN - description: USART2 clock enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART3 clock enable - bit_offset: 18 - bit_size: 1 - - name: USART4EN - description: USART4 clock enable - bit_offset: 19 - bit_size: 1 - - name: LPUART1EN - description: LPUART1 clock enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C2 clock enable - bit_offset: 22 - bit_size: 1 - - name: I2C3EN - description: I2C3 clock enable - bit_offset: 23 - bit_size: 1 - - name: CECEN - description: HDMI CEC clock enable - bit_offset: 24 - bit_size: 1 - - name: UCPD1EN - description: UCPD1 clock enable - bit_offset: 25 - bit_size: 1 - - name: UCPD2EN - description: UCPD2 clock enable - bit_offset: 26 - bit_size: 1 - - name: DBGEN - description: Debug support clock enable - bit_offset: 27 - bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - - name: DAC1EN - description: DAC1 interface clock enable - bit_offset: 29 - bit_size: 1 - - name: LPTIM2EN - description: LPTIM2 clock enable - bit_offset: 30 - bit_size: 1 - - name: LPTIM1EN - description: LPTIM1 clock enable - bit_offset: 31 - bit_size: 1 + - name: TIM2EN + description: TIM2 timer clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM3 timer clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM4 timer clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM6EN + description: TIM6 timer clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM7 timer clock enable + bit_offset: 5 + bit_size: 1 + - name: LPUART2EN + description: LPUART2 clock enable + bit_offset: 7 + bit_size: 1 + - name: USART5EN + description: USART5EN + bit_offset: 8 + bit_size: 1 + - name: USART6EN + description: USART6EN + bit_offset: 9 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: WWDG clock enable + bit_offset: 11 + bit_size: 1 + - name: FDCANEN + description: USBEN + bit_offset: 12 + bit_size: 1 + - name: USBEN + description: USBEN + bit_offset: 13 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 clock enable + bit_offset: 15 + bit_size: 1 + - name: CRSEN + description: CRSEN + bit_offset: 16 + bit_size: 1 + - name: USART2EN + description: USART2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 clock enable + bit_offset: 18 + bit_size: 1 + - name: USART4EN + description: USART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: LPUART1EN + description: LPUART1 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 23 + bit_size: 1 + - name: CECEN + description: HDMI CEC clock enable + bit_offset: 24 + bit_size: 1 + - name: UCPD1EN + description: UCPD1 clock enable + bit_offset: 25 + bit_size: 1 + - name: UCPD2EN + description: UCPD2 clock enable + bit_offset: 26 + bit_size: 1 + - name: DBGEN + description: Debug support clock enable + bit_offset: 27 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DAC1EN + description: DAC1 interface clock enable + bit_offset: 29 + bit_size: 1 + - name: LPTIM2EN + description: LPTIM2 clock enable + bit_offset: 30 + bit_size: 1 + - name: LPTIM1EN + description: LPTIM1 clock enable + bit_offset: 31 + bit_size: 1 fieldset/APBENR2: description: APB peripheral clock enable register 2 fields: - - name: SYSCFGEN - description: "SYSCFG, COMP and VREFBUF clock enable" - bit_offset: 0 - bit_size: 1 - - name: TIM1EN - description: TIM1 timer clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: SPI1 clock enable - bit_offset: 12 - bit_size: 1 - - name: USART1EN - description: USART1 clock enable - bit_offset: 14 - bit_size: 1 - - name: TIM14EN - description: TIM14 timer clock enable - bit_offset: 15 - bit_size: 1 - - name: TIM15EN - description: TIM15 timer clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: TIM16 timer clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: TIM16 timer clock enable - bit_offset: 18 - bit_size: 1 - - name: ADCEN - description: ADC clock enable - bit_offset: 20 - bit_size: 1 + - name: SYSCFGEN + description: SYSCFG, COMP and VREFBUF clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM1EN + description: TIM1 timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM14EN + description: TIM14 timer clock enable + bit_offset: 15 + bit_size: 1 + - name: TIM15EN + description: TIM15 timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM16 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: ADCEN + description: ADC clock enable + bit_offset: 20 + bit_size: 1 fieldset/APBRSTR1: description: APB peripheral reset register 1 fields: - - name: TIM2RST - description: TIM2 timer reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: TIM3 timer reset - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: TIM4 timer reset - bit_offset: 2 - bit_size: 1 - - name: TIM6RST - description: TIM6 timer reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: TIM7 timer reset - bit_offset: 5 - bit_size: 1 - - name: LPUART2RST - description: LPUART2RST - bit_offset: 7 - bit_size: 1 - - name: USART5RST - description: USART5RST - bit_offset: 8 - bit_size: 1 - - name: USART6RST - description: USART6RST - bit_offset: 9 - bit_size: 1 - - name: FDCANRST - description: FDCANRST - bit_offset: 12 - bit_size: 1 - - name: USBRST - description: USBRST - bit_offset: 13 - bit_size: 1 - - name: SPI2RST - description: SPI2 reset - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: SPI3 reset - bit_offset: 15 - bit_size: 1 - - name: CRSRST - description: CRSRST - bit_offset: 16 - bit_size: 1 - - name: USART2RST - description: USART2 reset - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: USART3 reset - bit_offset: 18 - bit_size: 1 - - name: USART4RST - description: USART4 reset - bit_offset: 19 - bit_size: 1 - - name: LPUART1RST - description: LPUART1 reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C2 reset - bit_offset: 22 - bit_size: 1 - - name: I2C3RST - description: I2C3RST reset - bit_offset: 23 - bit_size: 1 - - name: CECRST - description: HDMI CEC reset - bit_offset: 24 - bit_size: 1 - - name: UCPD1RST - description: UCPD1 reset - bit_offset: 25 - bit_size: 1 - - name: UCPD2RST - description: UCPD2 reset - bit_offset: 26 - bit_size: 1 - - name: DBGRST - description: Debug support reset - bit_offset: 27 - bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - - name: DAC1RST - description: DAC1 interface reset - bit_offset: 29 - bit_size: 1 - - name: LPTIM2RST - description: Low Power Timer 2 reset - bit_offset: 30 - bit_size: 1 - - name: LPTIM1RST - description: Low Power Timer 1 reset - bit_offset: 31 - bit_size: 1 + - name: TIM2RST + description: TIM2 timer reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: TIM3 timer reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: TIM4 timer reset + bit_offset: 2 + bit_size: 1 + - name: TIM6RST + description: TIM6 timer reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM7 timer reset + bit_offset: 5 + bit_size: 1 + - name: LPUART2RST + description: LPUART2RST + bit_offset: 7 + bit_size: 1 + - name: USART5RST + description: USART5RST + bit_offset: 8 + bit_size: 1 + - name: USART6RST + description: USART6RST + bit_offset: 9 + bit_size: 1 + - name: FDCANRST + description: FDCANRST + bit_offset: 12 + bit_size: 1 + - name: USBRST + description: USBRST + bit_offset: 13 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: CRSRST + description: CRSRST + bit_offset: 16 + bit_size: 1 + - name: USART2RST + description: USART2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 reset + bit_offset: 18 + bit_size: 1 + - name: USART4RST + description: USART4 reset + bit_offset: 19 + bit_size: 1 + - name: LPUART1RST + description: LPUART1 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3RST reset + bit_offset: 23 + bit_size: 1 + - name: CECRST + description: HDMI CEC reset + bit_offset: 24 + bit_size: 1 + - name: UCPD1RST + description: UCPD1 reset + bit_offset: 25 + bit_size: 1 + - name: UCPD2RST + description: UCPD2 reset + bit_offset: 26 + bit_size: 1 + - name: DBGRST + description: Debug support reset + bit_offset: 27 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DAC1RST + description: DAC1 interface reset + bit_offset: 29 + bit_size: 1 + - name: LPTIM2RST + description: Low Power Timer 2 reset + bit_offset: 30 + bit_size: 1 + - name: LPTIM1RST + description: Low Power Timer 1 reset + bit_offset: 31 + bit_size: 1 fieldset/APBRSTR2: description: APB peripheral reset register 2 fields: - - name: SYSCFGRST - description: "SYSCFG, COMP and VREFBUF reset" - bit_offset: 0 - bit_size: 1 - - name: TIM1RST - description: TIM1 timer reset - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: SPI1 reset - bit_offset: 12 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 14 - bit_size: 1 - - name: TIM14RST - description: TIM14 timer reset - bit_offset: 15 - bit_size: 1 - - name: TIM15RST - description: TIM15 timer reset - bit_offset: 16 - bit_size: 1 - - name: TIM16RST - description: TIM16 timer reset - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: TIM17 timer reset - bit_offset: 18 - bit_size: 1 - - name: ADCRST - description: ADC reset - bit_offset: 20 - bit_size: 1 + - name: SYSCFGRST + description: SYSCFG, COMP and VREFBUF reset + bit_offset: 0 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI1 reset + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM14RST + description: TIM14 timer reset + bit_offset: 15 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: ADCRST + description: ADC reset + bit_offset: 20 + bit_size: 1 fieldset/APBSMENR1: description: APB peripheral clock enable in Sleep mode register 1 fields: - - name: TIM2SMEN - description: TIM2 timer clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM3SMEN - description: TIM3 timer clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: TIM4SMEN - description: TIM4 timer clock enable during Sleep mode - bit_offset: 2 - bit_size: 1 - - name: TIM6SMEN - description: TIM6 timer clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: TIM7SMEN - description: TIM7 timer clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: LPUART2SMEN - description: LPUART2 clock enable - bit_offset: 7 - bit_size: 1 - - name: USART5SMEN - description: USART5 clock enable - bit_offset: 8 - bit_size: 1 - - name: USART6SMEN - description: USART6 clock enable - bit_offset: 9 - bit_size: 1 - - name: RTCAPBSMEN - description: RTC APB clock enable during Sleep mode - bit_offset: 10 - bit_size: 1 - - name: WWDGSMEN - description: WWDG clock enable during Sleep mode - bit_offset: 11 - bit_size: 1 - - name: FDCANSMEN - description: FDCAN clock enable during Sleep mode - bit_offset: 12 - bit_size: 1 - - name: USBSMEN - description: USB clock enable during Sleep mode - bit_offset: 13 - bit_size: 1 - - name: SPI2SMEN - description: SPI2 clock enable during Sleep mode - bit_offset: 14 - bit_size: 1 - - name: SPI3SMEN - description: SPI3 clock enable during Sleep mode - bit_offset: 15 - bit_size: 1 - - name: CRSSSMEN - description: CRSS clock enable during Sleep mode - bit_offset: 16 - bit_size: 1 - - name: USART2SMEN - description: USART2 clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: USART3SMEN - description: USART3 clock enable during Sleep mode - bit_offset: 18 - bit_size: 1 - - name: USART4SMEN - description: USART4 clock enable during Sleep mode - bit_offset: 19 - bit_size: 1 - - name: LPUART1SMEN - description: LPUART1 clock enable during Sleep mode - bit_offset: 20 - bit_size: 1 - - name: I2C1SMEN - description: I2C1 clock enable during Sleep mode - bit_offset: 21 - bit_size: 1 - - name: I2C2SMEN - description: I2C2 clock enable during Sleep mode - bit_offset: 22 - bit_size: 1 - - name: I2C3SMEN - description: I2C3 clock enable during Sleep mode - bit_offset: 23 - bit_size: 1 - - name: CECSMEN - description: HDMI CEC clock enable during Sleep mode - bit_offset: 24 - bit_size: 1 - - name: UCPD1SMEN - description: UCPD1 clock enable during Sleep mode - bit_offset: 25 - bit_size: 1 - - name: UCPD2SMEN - description: UCPD2 clock enable during Sleep mode - bit_offset: 26 - bit_size: 1 - - name: DBGSMEN - description: Debug support clock enable during Sleep mode - bit_offset: 27 - bit_size: 1 - - name: PWRSMEN - description: Power interface clock enable during Sleep mode - bit_offset: 28 - bit_size: 1 - - name: DAC1SMEN - description: DAC1 interface clock enable during Sleep mode - bit_offset: 29 - bit_size: 1 - - name: LPTIM2SMEN - description: Low Power Timer 2 clock enable during Sleep mode - bit_offset: 30 - bit_size: 1 - - name: LPTIM1SMEN - description: Low Power Timer 1 clock enable during Sleep mode - bit_offset: 31 - bit_size: 1 + - name: TIM2SMEN + description: TIM2 timer clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM3SMEN + description: TIM3 timer clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: TIM4SMEN + description: TIM4 timer clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: TIM6SMEN + description: TIM6 timer clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: TIM7SMEN + description: TIM7 timer clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: LPUART2SMEN + description: LPUART2 clock enable + bit_offset: 7 + bit_size: 1 + - name: USART5SMEN + description: USART5 clock enable + bit_offset: 8 + bit_size: 1 + - name: USART6SMEN + description: USART6 clock enable + bit_offset: 9 + bit_size: 1 + - name: RTCAPBSMEN + description: RTC APB clock enable during Sleep mode + bit_offset: 10 + bit_size: 1 + - name: WWDGSMEN + description: WWDG clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: FDCANSMEN + description: FDCAN clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: USBSMEN + description: USB clock enable during Sleep mode + bit_offset: 13 + bit_size: 1 + - name: SPI2SMEN + description: SPI2 clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: SPI3SMEN + description: SPI3 clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: CRSSSMEN + description: CRSS clock enable during Sleep mode + bit_offset: 16 + bit_size: 1 + - name: USART2SMEN + description: USART2 clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: USART3SMEN + description: USART3 clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: USART4SMEN + description: USART4 clock enable during Sleep mode + bit_offset: 19 + bit_size: 1 + - name: LPUART1SMEN + description: LPUART1 clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 + - name: I2C1SMEN + description: I2C1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: I2C2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: I2C3SMEN + description: I2C3 clock enable during Sleep mode + bit_offset: 23 + bit_size: 1 + - name: CECSMEN + description: HDMI CEC clock enable during Sleep mode + bit_offset: 24 + bit_size: 1 + - name: UCPD1SMEN + description: UCPD1 clock enable during Sleep mode + bit_offset: 25 + bit_size: 1 + - name: UCPD2SMEN + description: UCPD2 clock enable during Sleep mode + bit_offset: 26 + bit_size: 1 + - name: DBGSMEN + description: Debug support clock enable during Sleep mode + bit_offset: 27 + bit_size: 1 + - name: PWRSMEN + description: Power interface clock enable during Sleep mode + bit_offset: 28 + bit_size: 1 + - name: DAC1SMEN + description: DAC1 interface clock enable during Sleep mode + bit_offset: 29 + bit_size: 1 + - name: LPTIM2SMEN + description: Low Power Timer 2 clock enable during Sleep mode + bit_offset: 30 + bit_size: 1 + - name: LPTIM1SMEN + description: Low Power Timer 1 clock enable during Sleep mode + bit_offset: 31 + bit_size: 1 fieldset/APBSMENR2: description: APB peripheral clock enable in Sleep mode register 2 fields: - - name: SYSCFGSMEN - description: "SYSCFG, COMP and VREFBUF clock enable during Sleep mode" - bit_offset: 0 - bit_size: 1 - - name: TIM1SMEN - description: TIM1 timer clock enable during Sleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI1SMEN - description: SPI1 clock enable during Sleep mode - bit_offset: 12 - bit_size: 1 - - name: USART1SMEN - description: USART1 clock enable during Sleep mode - bit_offset: 14 - bit_size: 1 - - name: TIM14SMEN - description: TIM14 timer clock enable during Sleep mode - bit_offset: 15 - bit_size: 1 - - name: TIM15SMEN - description: TIM15 timer clock enable during Sleep mode - bit_offset: 16 - bit_size: 1 - - name: TIM16SMEN - description: TIM16 timer clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: TIM17SMEN - description: TIM16 timer clock enable during Sleep mode - bit_offset: 18 - bit_size: 1 - - name: ADCSMEN - description: ADC clock enable during Sleep mode - bit_offset: 20 - bit_size: 1 + - name: SYSCFGSMEN + description: SYSCFG, COMP and VREFBUF clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM1SMEN + description: TIM1 timer clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: SPI1 clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: USART1SMEN + description: USART1 clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: TIM14SMEN + description: TIM14 timer clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: TIM15SMEN + description: TIM15 timer clock enable during Sleep mode + bit_offset: 16 + bit_size: 1 + - name: TIM16SMEN + description: TIM16 timer clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: TIM16 timer clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: ADCSMEN + description: ADC clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 fieldset/BDCR: description: RTC domain control register fields: - - name: LSEON - description: LSE oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: LSE oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: LSE oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: LSEDRV - description: LSE oscillator drive capability - bit_offset: 3 - bit_size: 2 - enum: LSEDRV - - name: LSECSSON - description: CSS on LSE enable - bit_offset: 5 - bit_size: 1 - - name: LSECSSD - description: CSS on LSE failure Detection - bit_offset: 6 - bit_size: 1 - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: RTC domain software reset - bit_offset: 16 - bit_size: 1 - - name: LSCOEN - description: Low-speed clock output (LSCO) enable - bit_offset: 24 - bit_size: 1 - - name: LSCOSEL - description: Low-speed clock output selection - bit_offset: 25 - bit_size: 1 + - name: LSEON + description: LSE oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: LSE oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: LSE oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: LSE oscillator drive capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: CSS on LSE enable + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: CSS on LSE failure Detection + bit_offset: 6 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: RTC domain software reset + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: Low-speed clock output (LSCO) enable + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: Low-speed clock output selection + bit_offset: 25 + bit_size: 1 fieldset/CCIPR: description: Peripherals independent clock configuration register fields: - - name: USART1SEL - description: USART1 clock source selection - bit_offset: 0 - bit_size: 2 - enum: USART1SEL - - name: USART2SEL - description: USART2 clock source selection - bit_offset: 2 - bit_size: 2 - enum: USART2SEL - - name: USART3SEL - description: USART3 clock source selection - bit_offset: 4 - bit_size: 2 - enum: USART3SEL - - name: CECSEL - description: HDMI CEC clock source selection - bit_offset: 6 - bit_size: 1 - enum: CECSEL - - name: LPUART2SEL - description: LPUART2 clock source selection - bit_offset: 8 - bit_size: 2 - enum: LPUART2SEL - - name: LPUART1SEL - description: LPUART1 clock source selection - bit_offset: 10 - bit_size: 2 - enum: LPUART1SEL - - name: I2C1SEL - description: I2C1 clock source selection - bit_offset: 12 - bit_size: 2 - enum: I2C1SEL - - name: I2S2SEL - description: I2S1 clock source selection - bit_offset: 14 - bit_size: 2 - enum: I2C2I2S1SEL - - name: LPTIM1SEL - description: LPTIM1 clock source selection - bit_offset: 18 - bit_size: 2 - enum: LPTIM1SEL - - name: LPTIM2SEL - description: LPTIM2 clock source selection - bit_offset: 20 - bit_size: 2 - enum: LPTIM2SEL - - name: TIM1SEL - description: TIM1 clock source selection - bit_offset: 22 - bit_size: 1 - enum: TIM1SEL - - name: TIM15SEL - description: TIM15 clock source selection - bit_offset: 24 - bit_size: 1 - enum: TIM15SEL - - name: RNGSEL - description: RNG clock source selection - bit_offset: 26 - bit_size: 2 - enum: RNGSEL - - name: RNGDIV - description: Division factor of RNG clock divider - bit_offset: 28 - bit_size: 2 - enum: RNGDIV - - name: ADCSEL - description: ADCs clock source selection - bit_offset: 30 - bit_size: 2 - enum: ADCSEL + - name: USART1SEL + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + enum: USART1SEL + - name: USART2SEL + description: USART2 clock source selection + bit_offset: 2 + bit_size: 2 + enum: USART2SEL + - name: USART3SEL + description: USART3 clock source selection + bit_offset: 4 + bit_size: 2 + enum: USART3SEL + - name: CECSEL + description: HDMI CEC clock source selection + bit_offset: 6 + bit_size: 1 + enum: CECSEL + - name: LPUART2SEL + description: LPUART2 clock source selection + bit_offset: 8 + bit_size: 2 + enum: LPUART2SEL + - name: LPUART1SEL + description: LPUART1 clock source selection + bit_offset: 10 + bit_size: 2 + enum: LPUART1SEL + - name: I2C1SEL + description: I2C1 clock source selection + bit_offset: 12 + bit_size: 2 + enum: I2C1SEL + - name: I2S2SEL + description: I2S1 clock source selection + bit_offset: 14 + bit_size: 2 + enum: I2C2I2S1SEL + - name: LPTIM1SEL + description: LPTIM1 clock source selection + bit_offset: 18 + bit_size: 2 + enum: LPTIM1SEL + - name: LPTIM2SEL + description: LPTIM2 clock source selection + bit_offset: 20 + bit_size: 2 + enum: LPTIM2SEL + - name: TIM1SEL + description: TIM1 clock source selection + bit_offset: 22 + bit_size: 1 + enum: TIM1SEL + - name: TIM15SEL + description: TIM15 clock source selection + bit_offset: 24 + bit_size: 1 + enum: TIM15SEL + - name: RNGSEL + description: RNG clock source selection + bit_offset: 26 + bit_size: 2 + enum: RNGSEL + - name: RNGDIV + description: Division factor of RNG clock divider + bit_offset: 28 + bit_size: 2 + enum: RNGDIV + - name: ADCSEL + description: ADCs clock source selection + bit_offset: 30 + bit_size: 2 + enum: ADCSEL fieldset/CCIPR2: description: Peripherals independent clock configuration register 2 fields: - - name: I2S1SEL - description: I2S1SEL - bit_offset: 0 - bit_size: 2 - enum: I2S1SEL - - name: I2S2SEL - description: I2S2SEL - bit_offset: 2 - bit_size: 2 - enum: I2S2SEL - - name: FDCANSEL - description: FDCANSEL - bit_offset: 8 - bit_size: 2 - enum: FDCANSEL - - name: USBSEL - description: USBSEL - bit_offset: 12 - bit_size: 2 - enum: USBSEL + - name: I2S1SEL + description: I2S1SEL + bit_offset: 0 + bit_size: 2 + enum: I2S1SEL + - name: I2S2SEL + description: I2S2SEL + bit_offset: 2 + bit_size: 2 + enum: I2S2SEL + - name: FDCANSEL + description: FDCANSEL + bit_offset: 8 + bit_size: 2 + enum: FDCANSEL + - name: USBSEL + description: USBSEL + bit_offset: 12 + bit_size: 2 + enum: USBSEL fieldset/CFGR: description: Clock configuration register fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 3 - enum: SW - - name: SWS - description: System clock switch status - bit_offset: 3 - bit_size: 3 - enum: SW - - name: HPRE - description: AHB prescaler - bit_offset: 8 - bit_size: 4 - enum: HPRE - - name: PPRE - description: APB prescaler - bit_offset: 12 - bit_size: 3 - enum: PPRE - - name: MCO2SEL - description: MCO2SEL - bit_offset: 16 - bit_size: 4 - enum: MCOSEL - - name: MCO2PRE - description: MCO2PRE - bit_offset: 20 - bit_size: 4 - enum: MCOPRE - - name: MCOSEL - description: Microcontroller clock output - bit_offset: 24 - bit_size: 3 - enum: MCOSEL - - name: MCOPRE - description: Microcontroller clock output prescaler - bit_offset: 28 - bit_size: 3 - enum: MCOPRE + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 3 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 3 + bit_size: 3 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 8 + bit_size: 4 + enum: HPRE + - name: PPRE + description: APB prescaler + bit_offset: 12 + bit_size: 3 + enum: PPRE + - name: MCO2SEL + description: MCO2SEL + bit_offset: 16 + bit_size: 4 + enum: MCOSEL + - name: MCO2PRE + description: MCO2PRE + bit_offset: 20 + bit_size: 4 + enum: MCOPRE + - name: MCOSEL + description: Microcontroller clock output + bit_offset: 24 + bit_size: 3 + enum: MCOSEL + - name: MCOPRE + description: Microcontroller clock output prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: - - name: LSIRDYC - description: LSI ready interrupt clear - bit_offset: 0 - bit_size: 1 - - name: LSERDYC - description: LSE ready interrupt clear - bit_offset: 1 - bit_size: 1 - - name: HSI48RDYC - description: HSI48RDYC - bit_offset: 2 - bit_size: 1 - - name: HSIRDYC - description: HSI ready interrupt clear - bit_offset: 3 - bit_size: 1 - - name: HSERDYC - description: HSE ready interrupt clear - bit_offset: 4 - bit_size: 1 - - name: PLLSYSRDYC - description: PLL ready interrupt clear - bit_offset: 5 - bit_size: 1 - - name: CSSC - description: Clock security system interrupt clear - bit_offset: 8 - bit_size: 1 - - name: LSECSSC - description: LSE Clock security system interrupt clear - bit_offset: 9 - bit_size: 1 + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 1 + bit_size: 1 + - name: HSI48RDYC + description: HSI48RDYC + bit_offset: 2 + bit_size: 1 + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 4 + bit_size: 1 + - name: PLLSYSRDYC + description: PLL ready interrupt clear + bit_offset: 5 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 8 + bit_size: 1 + - name: LSECSSC + description: LSE Clock security system interrupt clear + bit_offset: 9 + bit_size: 1 fieldset/CIER: description: Clock interrupt enable register fields: - - name: LSIRDYIE - description: LSI ready interrupt enable - bit_offset: 0 - bit_size: 1 - - name: LSERDYIE - description: LSE ready interrupt enable - bit_offset: 1 - bit_size: 1 - - name: HSIRDYIE - description: HSI ready interrupt enable - bit_offset: 3 - bit_size: 1 - - name: HSERDYIE - description: HSE ready interrupt enable - bit_offset: 4 - bit_size: 1 - - name: PLLSYSRDYIE - description: PLL ready interrupt enable - bit_offset: 5 - bit_size: 1 + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 1 + bit_size: 1 + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 4 + bit_size: 1 + - name: PLLSYSRDYIE + description: PLL ready interrupt enable + bit_offset: 5 + bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register fields: - - name: LSIRDYF - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - - name: HSI48RDYF - description: HSI48RDYF - bit_offset: 2 - bit_size: 1 - - name: HSIRDYF - description: HSI ready interrupt flag - bit_offset: 3 - bit_size: 1 - - name: HSERDYF - description: HSE ready interrupt flag - bit_offset: 4 - bit_size: 1 - - name: PLLSYSRDYF - description: PLL ready interrupt flag - bit_offset: 5 - bit_size: 1 - - name: CSSF - description: Clock security system interrupt flag - bit_offset: 8 - bit_size: 1 - - name: LSECSSF - description: LSE Clock security system interrupt flag - bit_offset: 9 - bit_size: 1 + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSI48RDYF + description: HSI48RDYF + bit_offset: 2 + bit_size: 1 + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLLSYSRDYF + description: PLL ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: CSSF + description: Clock security system interrupt flag + bit_offset: 8 + bit_size: 1 + - name: LSECSSF + description: LSE Clock security system interrupt flag + bit_offset: 9 + bit_size: 1 fieldset/CR: description: Clock control register fields: - - name: HSION - description: HSI16 clock enable - bit_offset: 8 - bit_size: 1 - - name: HSIKERON - description: HSI16 always enable for peripheral kernels - bit_offset: 9 - bit_size: 1 - - name: HSIRDY - description: HSI16 clock ready flag - bit_offset: 10 - bit_size: 1 - - name: HSIDIV - description: HSI16 clock division factor - bit_offset: 11 - bit_size: 3 - enum: HSIDIV - - name: HSEON - description: HSE clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: HSE crystal oscillator bypass - bit_offset: 18 - bit_size: 1 - - name: CSSON - description: Clock security system enable - bit_offset: 19 - bit_size: 1 - - name: HSI48ON - description: HSI48ON - bit_offset: 22 - bit_size: 1 - - name: HSI48RDY - description: HSI48RDY - bit_offset: 23 - bit_size: 1 - - name: PLLON - description: PLL enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: PLL clock ready flag - bit_offset: 25 - bit_size: 1 + - name: HSION + description: HSI16 clock enable + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: HSI16 always enable for peripheral kernels + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: HSI16 clock ready flag + bit_offset: 10 + bit_size: 1 + - name: HSIDIV + description: HSI16 clock division factor + bit_offset: 11 + bit_size: 3 + enum: HSIDIV + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: HSE crystal oscillator bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: HSI48ON + description: HSI48ON + bit_offset: 22 + bit_size: 1 + - name: HSI48RDY + description: HSI48RDY + bit_offset: 23 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 fieldset/CRRCR: description: RCC clock recovery RC register fields: - - name: HSI48CAL - description: HSI48 clock calibration - bit_offset: 0 - bit_size: 9 + - name: HSI48CAL + description: HSI48 clock calibration + bit_offset: 0 + bit_size: 9 fieldset/CSR: description: Control/status register fields: - - name: LSION - description: LSI oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: LSI oscillator ready - bit_offset: 1 - bit_size: 1 - - name: RMVF - description: Remove reset flags - bit_offset: 23 - bit_size: 1 - - name: OBLRSTF - description: Option byte loader reset flag - bit_offset: 25 - bit_size: 1 - - name: PINRSTF - description: Pin reset flag - bit_offset: 26 - bit_size: 1 - - name: PWRRSTF - description: BOR or POR/PDR flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: Independent window watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSION + description: LSI oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: LSI oscillator ready + bit_offset: 1 + bit_size: 1 + - name: RMVF + description: Remove reset flags + bit_offset: 23 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: Pin reset flag + bit_offset: 26 + bit_size: 1 + - name: PWRRSTF + description: BOR or POR/PDR flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent window watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 fieldset/GPIOENR: description: GPIO clock enable register fields: - - name: GPIOAEN - description: I/O port A clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: I/O port B clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: I/O port C clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: I/O port D clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOFEN - description: I/O port F clock enable - bit_offset: 5 - bit_size: 1 + - name: GPIOAEN + description: I/O port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: I/O port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: I/O port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: I/O port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOFEN + description: I/O port F clock enable + bit_offset: 5 + bit_size: 1 fieldset/GPIORSTR: description: GPIO reset register fields: - - name: GPIOARST - description: I/O port A reset - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: I/O port B reset - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: I/O port C reset - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: I/O port D reset - bit_offset: 3 - bit_size: 1 - - name: GPIOFRST - description: I/O port F reset - bit_offset: 5 - bit_size: 1 + - name: GPIOARST + description: I/O port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: I/O port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: I/O port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: I/O port D reset + bit_offset: 3 + bit_size: 1 + - name: GPIOFRST + description: I/O port F reset + bit_offset: 5 + bit_size: 1 fieldset/GPIOSMENR: description: GPIO in Sleep mode clock enable register fields: - - name: GPIOASMEN - description: I/O port A clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: GPIOBSMEN - description: I/O port B clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: GPIOCSMEN - description: I/O port C clock enable during Sleep mode - bit_offset: 2 - bit_size: 1 - - name: GPIODSMEN - description: I/O port D clock enable during Sleep mode - bit_offset: 3 - bit_size: 1 - - name: GPIOFSMEN - description: I/O port F clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 + - name: GPIOASMEN + description: I/O port A clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: I/O port B clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: I/O port C clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: GPIODSMEN + description: I/O port D clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: GPIOFSMEN + description: I/O port F clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 fieldset/ICSCR: description: Internal clock sources calibration register fields: - - name: HSICAL - description: HSI16 clock calibration - bit_offset: 0 - bit_size: 8 - - name: HSITRIM - description: HSI16 clock trimming - bit_offset: 8 - bit_size: 7 + - name: HSICAL + description: HSI16 clock calibration + bit_offset: 0 + bit_size: 8 + - name: HSITRIM + description: HSI16 clock trimming + bit_offset: 8 + bit_size: 7 fieldset/PLLSYSCFGR: description: PLL configuration register fields: - - name: PLLSRC - description: PLL input clock source - bit_offset: 0 - bit_size: 2 - enum: PLLSRC - - name: PLLM - description: Division factor M of the PLL input clock divider - bit_offset: 4 - bit_size: 3 - - name: PLLN - description: PLL frequency multiplication factor N - bit_offset: 8 - bit_size: 7 - - name: PLLPEN - description: PLLPCLK clock output enable - bit_offset: 16 - bit_size: 1 - - name: PLLP - description: PLL VCO division factor P for PLLPCLK clock output - bit_offset: 17 - bit_size: 5 - - name: PLLQEN - description: PLLQCLK clock output enable - bit_offset: 24 - bit_size: 1 - - name: PLLQ - description: PLL VCO division factor Q for PLLQCLK clock output - bit_offset: 25 - bit_size: 3 - - name: PLLREN - description: PLLRCLK clock output enable - bit_offset: 28 - bit_size: 1 - - name: PLLR - description: PLL VCO division factor R for PLLRCLK clock output - bit_offset: 29 - bit_size: 3 + - name: PLLSRC + description: PLL input clock source + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: PLLM + description: Division factor M of the PLL input clock divider + bit_offset: 4 + bit_size: 3 + - name: PLLN + description: PLL frequency multiplication factor N + bit_offset: 8 + bit_size: 7 + - name: PLLPEN + description: PLLPCLK clock output enable + bit_offset: 16 + bit_size: 1 + - name: PLLP + description: PLL VCO division factor P for PLLPCLK clock output + bit_offset: 17 + bit_size: 5 + - name: PLLQEN + description: PLLQCLK clock output enable + bit_offset: 24 + bit_size: 1 + - name: PLLQ + description: PLL VCO division factor Q for PLLQCLK clock output + bit_offset: 25 + bit_size: 3 + - name: PLLREN + description: PLLRCLK clock output enable + bit_offset: 28 + bit_size: 1 + - name: PLLR + description: PLL VCO division factor R for PLLRCLK clock output + bit_offset: 29 + bit_size: 3 enum/ADCSEL: bit_size: 2 variants: - - name: SYSCLK - description: SYSCLK used as ADC clock source - value: 0 - - name: PLLPCLK - description: PLLPCLK used as ADC clock source - value: 1 - - name: HSI16 - description: HSI16 used as ADC clock source - value: 2 + - name: SYSCLK + description: SYSCLK used as ADC clock source + value: 0 + - name: PLLPCLK + description: PLLPCLK used as ADC clock source + value: 1 + - name: HSI16 + description: HSI16 used as ADC clock source + value: 2 enum/CECSEL: bit_size: 1 variants: - - name: HSI16_Div488 - description: HSI16 divided by 488 used as CEC clock - value: 0 - - name: LSE - description: LSE used as CEC clock - value: 1 + - name: HSI16_Div488 + description: HSI16 divided by 488 used as CEC clock + value: 0 + - name: LSE + description: LSE used as CEC clock + value: 1 enum/FDCANSEL: bit_size: 2 variants: - - name: PCLK - description: PCLK used as FDCAN clock source - value: 0 - - name: PLLQCLK - description: PLLQCLK used as FDCAN clock source - value: 1 - - name: HSE - description: HSE used as FDCAN clock source - value: 2 + - name: PCLK + description: PCLK used as FDCAN clock source + value: 0 + - name: PLLQCLK + description: PLLQCLK used as FDCAN clock source + value: 1 + - name: HSE + description: HSE used as FDCAN clock source + value: 2 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: SYSCLK not divided - value: 0 - - name: Div2 - description: SYSCLK is divided by 2 - value: 8 - - name: Div4 - description: SYSCLK is divided by 4 - value: 9 - - name: Div8 - description: SYSCLK is divided by 8 - value: 10 - - name: Div16 - description: SYSCLK is divided by 16 - value: 11 - - name: Div64 - description: SYSCLK is divided by 64 - value: 12 - - name: Div128 - description: SYSCLK is divided by 128 - value: 13 - - name: Div256 - description: SYSCLK is divided by 256 - value: 14 - - name: Div512 - description: SYSCLK is divided by 512 - value: 15 + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK is divided by 2 + value: 8 + - name: Div4 + description: SYSCLK is divided by 4 + value: 9 + - name: Div8 + description: SYSCLK is divided by 8 + value: 10 + - name: Div16 + description: SYSCLK is divided by 16 + value: 11 + - name: Div64 + description: SYSCLK is divided by 64 + value: 12 + - name: Div128 + description: SYSCLK is divided by 128 + value: 13 + - name: Div256 + description: SYSCLK is divided by 256 + value: 14 + - name: Div512 + description: SYSCLK is divided by 512 + value: 15 enum/HSIDIV: bit_size: 3 variants: - - name: Div1 - description: HSI clock is not divided - value: 0 - - name: Div2 - description: HSI clock is divided by 2 - value: 1 - - name: Div4 - description: HSI clock is divided by 4 - value: 2 - - name: Div8 - description: HSI clock is divided by 8 - value: 3 - - name: Div16 - description: HSI clock is divided by 16 - value: 4 - - name: Div32 - description: HSI clock is divided by 32 - value: 5 - - name: Div64 - description: HSI clock is divided by 64 - value: 6 - - name: Div128 - description: HSI clock is divided by 128 - value: 7 + - name: Div1 + description: HSI clock is not divided + value: 0 + - name: Div2 + description: HSI clock is divided by 2 + value: 1 + - name: Div4 + description: HSI clock is divided by 4 + value: 2 + - name: Div8 + description: HSI clock is divided by 8 + value: 3 + - name: Div16 + description: HSI clock is divided by 16 + value: 4 + - name: Div32 + description: HSI clock is divided by 32 + value: 5 + - name: Div64 + description: HSI clock is divided by 64 + value: 6 + - name: Div128 + description: HSI clock is divided by 128 + value: 7 enum/I2C1SEL: bit_size: 2 variants: - - name: PCLK - description: PCLK used as I2C1 clock source - value: 0 - - name: SYSCLK - description: SYSCLK used as I2C1 clock source - value: 1 - - name: HSI16 - description: HSI16 used as I2C1 clock source - value: 2 + - name: PCLK + description: PCLK used as I2C1 clock source + value: 0 + - name: SYSCLK + description: SYSCLK used as I2C1 clock source + value: 1 + - name: HSI16 + description: HSI16 used as I2C1 clock source + value: 2 enum/I2C2I2S1SEL: bit_size: 2 variants: - - name: PCLK - description: PCLK used as I2C2/I2S2 clock source - value: 0 - - name: SYSCLK - description: SYSCLK used as I2C2/I2S2 clock source - value: 1 - - name: HSI16 - description: HSI16 used as I2C2/I2S2 clock source - value: 2 - - name: I2S_CKIN - description: External clock used as I2C2/I2S2 clock source - value: 3 + - name: PCLK + description: PCLK used as I2C2/I2S2 clock source + value: 0 + - name: SYSCLK + description: SYSCLK used as I2C2/I2S2 clock source + value: 1 + - name: HSI16 + description: HSI16 used as I2C2/I2S2 clock source + value: 2 + - name: I2S_CKIN + description: External clock used as I2C2/I2S2 clock source + value: 3 enum/I2S1SEL: bit_size: 2 variants: - - name: SYSCLK - description: SYSCLK used as I2S1 clock source - value: 0 - - name: PLLPCLK - description: PLLPCLK used as I2S1 clock source - value: 1 - - name: HSI16 - description: HSI used as I2S1 clock source - value: 2 - - name: I2S_CKIN - description: External clock used as I2S1 clock source - value: 3 + - name: SYSCLK + description: SYSCLK used as I2S1 clock source + value: 0 + - name: PLLPCLK + description: PLLPCLK used as I2S1 clock source + value: 1 + - name: HSI16 + description: HSI used as I2S1 clock source + value: 2 + - name: I2S_CKIN + description: External clock used as I2S1 clock source + value: 3 enum/I2S2SEL: bit_size: 2 variants: - - name: SYSCLK - description: SYSCLK used as I2S2 clock source - value: 0 - - name: PLLPCLK - description: PLLPCLK used as I2S2 clock source - value: 1 - - name: HSI16 - description: HSI used as I2S2 clock source - value: 2 - - name: I2S_CKIN - description: External clock used as I2S2 clock source - value: 3 + - name: SYSCLK + description: SYSCLK used as I2S2 clock source + value: 0 + - name: PLLPCLK + description: PLLPCLK used as I2S2 clock source + value: 1 + - name: HSI16 + description: HSI used as I2S2 clock source + value: 2 + - name: I2S_CKIN + description: External clock used as I2S2 clock source + value: 3 enum/LPTIM1SEL: bit_size: 2 variants: - - name: PCLK - description: PCLK used as LPTIM1 clock source - value: 0 - - name: LSI - description: LSI used as LPTIM1 clock source - value: 1 - - name: HSI16 - description: HSI16 used as LPTIM1 clock source - value: 2 - - name: LSE - description: LSE used as LPTIM1 clock source - value: 3 + - name: PCLK + description: PCLK used as LPTIM1 clock source + value: 0 + - name: LSI + description: LSI used as LPTIM1 clock source + value: 1 + - name: HSI16 + description: HSI16 used as LPTIM1 clock source + value: 2 + - name: LSE + description: LSE used as LPTIM1 clock source + value: 3 enum/LPTIM2SEL: bit_size: 2 variants: - - name: PCLK - description: PCLK used as LPTIM2 clock source - value: 0 - - name: LSI - description: LSI used as LPTIM2 clock source - value: 1 - - name: HSI16 - description: HSI16 used as LPTIM2 clock source - value: 2 - - name: LSE - description: LSE used as LPTIM2 clock source - value: 3 + - name: PCLK + description: PCLK used as LPTIM2 clock source + value: 0 + - name: LSI + description: LSI used as LPTIM2 clock source + value: 1 + - name: HSI16 + description: HSI16 used as LPTIM2 clock source + value: 2 + - name: LSE + description: LSE used as LPTIM2 clock source + value: 3 enum/LPUART1SEL: bit_size: 2 variants: - - name: PCLK - description: PCLK used as LPUART1 clock source - value: 0 - - name: SYSCLK - description: SYSCLK used as LPUART1 clock source - value: 1 - - name: HSI16 - description: HSI16 used as LPUART1 clock source - value: 2 - - name: LSE - description: LSE used as LPUART1 clock source - value: 3 + - name: PCLK + description: PCLK used as LPUART1 clock source + value: 0 + - name: SYSCLK + description: SYSCLK used as LPUART1 clock source + value: 1 + - name: HSI16 + description: HSI16 used as LPUART1 clock source + value: 2 + - name: LSE + description: LSE used as LPUART1 clock source + value: 3 enum/LPUART2SEL: bit_size: 2 variants: - - name: PCLK - description: PCLK used as LPUART2 clock source - value: 0 - - name: SYSCLK - description: SYSCLK used as LPUART2 clock source - value: 1 - - name: HSI16 - description: HSI16 used as LPUART2 clock source - value: 2 - - name: LSE - description: LSE used as LPUART2 clock source - value: 3 + - name: PCLK + description: PCLK used as LPUART2 clock source + value: 0 + - name: SYSCLK + description: SYSCLK used as LPUART2 clock source + value: 1 + - name: HSI16 + description: HSI16 used as LPUART2 clock source + value: 2 + - name: LSE + description: LSE used as LPUART2 clock source + value: 3 enum/LSEDRV: bit_size: 2 variants: - - name: Low - description: Low driving capability - value: 0 - - name: MediumLow - description: Medium low driving capability - value: 1 - - name: MediumHigh - description: Medium high driving capability - value: 2 - - name: High - description: High driving capability - value: 3 + - name: Low + description: Low driving capability + value: 0 + - name: MediumLow + description: Medium low driving capability + value: 1 + - name: MediumHigh + description: Medium high driving capability + value: 2 + - name: High + description: High driving capability + value: 3 enum/MCOPRE: bit_size: 4 variants: - - name: Div1 - description: MCO1 not divided - value: 0 - - name: Div2 - description: MCO clock is divided by 2 - value: 1 - - name: Div4 - description: MCO clock is divided by 4 - value: 2 - - name: Div8 - description: MCO clock is divided by 8 - value: 3 - - name: Div16 - description: MCO clock is divided divided by 16 - value: 4 - - name: Div32 - description: MCO clock is divided divided by 32 - value: 5 - - name: Div64 - description: MCO clock is divided divided by 64 - value: 6 - - name: Div128 - description: MCO clock is divided divided by 128 - value: 7 - - name: Div256 - description: MCO clock is divided divided by 256 - value: 8 - - name: Div512 - description: MCO clock is divided divided by 512 - value: 9 - - name: Div1024 - description: MCO clock is divided divided by 1024 - value: 10 + - name: Div1 + description: MCO1 not divided + value: 0 + - name: Div2 + description: MCO clock is divided by 2 + value: 1 + - name: Div4 + description: MCO clock is divided by 4 + value: 2 + - name: Div8 + description: MCO clock is divided by 8 + value: 3 + - name: Div16 + description: MCO clock is divided divided by 16 + value: 4 + - name: Div32 + description: MCO clock is divided divided by 32 + value: 5 + - name: Div64 + description: MCO clock is divided divided by 64 + value: 6 + - name: Div128 + description: MCO clock is divided divided by 128 + value: 7 + - name: Div256 + description: MCO clock is divided divided by 256 + value: 8 + - name: Div512 + description: MCO clock is divided divided by 512 + value: 9 + - name: Div1024 + description: MCO clock is divided divided by 1024 + value: 10 enum/MCOSEL: bit_size: 4 variants: - - name: NoClock - description: "No clock, MCO output disabled" - value: 0 - - name: SYSCLK - description: SYSCLK selected as MCO source - value: 1 - - name: HSI48 - description: HSI48 selected as MCO source - value: 2 - - name: HSI16 - description: HSI16 selected as MCO source - value: 3 - - name: HSE - description: HSE selected as MCO source - value: 4 - - name: PLLRCLK - description: PLLRCLK selected as MCO source - value: 5 - - name: LSI - description: LSI selected as MCO source - value: 6 - - name: LSE - description: LSE selected as MCO source - value: 7 - - name: PLLPCLK - description: PLLPCLK selected as MCO source - value: 8 - - name: PLLQCLK - description: PLLQCLK selected as MCO source - value: 9 - - name: RTCCLK - description: RTCCLK selected as MCO source - value: 10 - - name: RTC_WKUP - description: RTC_Wakeup selected as MCO source - value: 11 + - name: NoClock + description: No clock, MCO output disabled + value: 0 + - name: SYSCLK + description: SYSCLK selected as MCO source + value: 1 + - name: HSI48 + description: HSI48 selected as MCO source + value: 2 + - name: HSI16 + description: HSI16 selected as MCO source + value: 3 + - name: HSE + description: HSE selected as MCO source + value: 4 + - name: PLLRCLK + description: PLLRCLK selected as MCO source + value: 5 + - name: LSI + description: LSI selected as MCO source + value: 6 + - name: LSE + description: LSE selected as MCO source + value: 7 + - name: PLLPCLK + description: PLLPCLK selected as MCO source + value: 8 + - name: PLLQCLK + description: PLLQCLK selected as MCO source + value: 9 + - name: RTCCLK + description: RTCCLK selected as MCO source + value: 10 + - name: RTC_WKUP + description: RTC_Wakeup selected as MCO source + value: 11 enum/PLLSRC: bit_size: 2 variants: - - name: NoClock - description: No clock selected as PLL entry clock source - value: 0 - - name: HSI16 - description: HSI16 selected as PLL entry clock source - value: 2 - - name: HSE - description: HSE selected as PLL entry clock source - value: 3 + - name: NoClock + description: No clock selected as PLL entry clock source + value: 0 + - name: HSI16 + description: HSI16 selected as PLL entry clock source + value: 2 + - name: HSE + description: HSE selected as PLL entry clock source + value: 3 enum/PPRE: bit_size: 4 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK is divided by 2 - value: 4 - - name: Div4 - description: HCLK is divided by 4 - value: 5 - - name: Div8 - description: HCLK is divided by 8 - value: 6 - - name: Div16 - description: HCLK is divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK is divided by 2 + value: 4 + - name: Div4 + description: HCLK is divided by 4 + value: 5 + - name: Div8 + description: HCLK is divided by 8 + value: 6 + - name: Div16 + description: HCLK is divided by 16 + value: 7 enum/RNGDIV: bit_size: 2 variants: - - name: Div1 - description: RNG clock is not divided - value: 0 - - name: Div2 - description: RNG clock is divided by 2 - value: 1 - - name: Div4 - description: RNG clock is divided by 4 - value: 2 - - name: Div8 - description: RNG clock is divided by 8 - value: 3 + - name: Div1 + description: RNG clock is not divided + value: 0 + - name: Div2 + description: RNG clock is divided by 2 + value: 1 + - name: Div4 + description: RNG clock is divided by 4 + value: 2 + - name: Div8 + description: RNG clock is divided by 8 + value: 3 enum/RNGSEL: bit_size: 2 variants: - - name: NoClock - description: No clock used as RNG clock source - value: 0 - - name: HSI16_Div8 - description: HSI divided by 8 used as RNG clock source - value: 1 - - name: SYSCLK - description: SYSCLK used as RNG clock source - value: 2 - - name: PLLQCLK - description: PLLQCLK used as RNG clock source - value: 3 + - name: NoClock + description: No clock used as RNG clock source + value: 0 + - name: HSI16_Div8 + description: HSI divided by 8 used as RNG clock source + value: 1 + - name: SYSCLK + description: SYSCLK used as RNG clock source + value: 2 + - name: PLLQCLK + description: PLLQCLK used as RNG clock source + value: 3 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock used as RTC clock - value: 0 - - name: LSE - description: LSE used as RTC clock - value: 1 - - name: LSI - description: LSI used as RTC clock - value: 2 - - name: HSE_Div32 - description: HSE divided by 32 used as RTC clock - value: 3 + - name: NoClock + description: No clock used as RTC clock + value: 0 + - name: LSE + description: LSE used as RTC clock + value: 1 + - name: LSI + description: LSI used as RTC clock + value: 2 + - name: HSE_Div32 + description: HSE divided by 32 used as RTC clock + value: 3 enum/SW: bit_size: 3 variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: HSE - description: HSE selected as system clock - value: 1 - - name: PLLRCLK - description: PLLRCLK selected as system clock - value: 2 - - name: LSI - description: LSI selected as system clock - value: 3 - - name: LSE - description: LSE selected as system clock - value: 4 + - name: HSI + description: HSI selected as system clock + value: 0 + - name: HSE + description: HSE selected as system clock + value: 1 + - name: PLLRCLK + description: PLLRCLK selected as system clock + value: 2 + - name: LSI + description: LSI selected as system clock + value: 3 + - name: LSE + description: LSE selected as system clock + value: 4 enum/TIM15SEL: bit_size: 1 variants: - - name: TIMPCLK - description: TIMPCLK used as TIM15 clock source - value: 0 - - name: PLLQCLK - description: PLLQCLK used as TIM15 clock source - value: 1 + - name: TIMPCLK + description: TIMPCLK used as TIM15 clock source + value: 0 + - name: PLLQCLK + description: PLLQCLK used as TIM15 clock source + value: 1 enum/TIM1SEL: bit_size: 1 variants: - - name: TIMPCLK - description: TIMPCLK used as TIM1 clock source - value: 0 - - name: PLLQCLK - description: PLLQCLK used as TIM1 clock source - value: 1 + - name: TIMPCLK + description: TIMPCLK used as TIM1 clock source + value: 0 + - name: PLLQCLK + description: PLLQCLK used as TIM1 clock source + value: 1 enum/USART1SEL: bit_size: 2 variants: - - name: PCLK - description: PCLK used as USART1 clock source - value: 0 - - name: SYSCLK - description: SYSCLK used as USART1 clock source - value: 1 - - name: HSI16 - description: HSI16 used as USART1 clock source - value: 2 - - name: LSE - description: LSE used as USART1 clock source - value: 3 + - name: PCLK + description: PCLK used as USART1 clock source + value: 0 + - name: SYSCLK + description: SYSCLK used as USART1 clock source + value: 1 + - name: HSI16 + description: HSI16 used as USART1 clock source + value: 2 + - name: LSE + description: LSE used as USART1 clock source + value: 3 enum/USART2SEL: bit_size: 2 variants: - - name: PCLK - description: PCLK used as USART2 clock source - value: 0 - - name: SYSCLK - description: SYSCLK used as USART2 clock source - value: 1 - - name: HSI16 - description: HSI16 used as USART2 clock source - value: 2 - - name: LSE - description: LSE used as USART2 clock source - value: 3 + - name: PCLK + description: PCLK used as USART2 clock source + value: 0 + - name: SYSCLK + description: SYSCLK used as USART2 clock source + value: 1 + - name: HSI16 + description: HSI16 used as USART2 clock source + value: 2 + - name: LSE + description: LSE used as USART2 clock source + value: 3 enum/USART3SEL: bit_size: 2 variants: - - name: PCLK - description: PCLK used as USART3 clock source - value: 0 - - name: SYSCLK - description: SYSCLK used as USART3 clock source - value: 1 - - name: HSI16 - description: HSI16 used as USART3 clock source - value: 2 - - name: LSE - description: LSE used as USART3 clock source - value: 3 + - name: PCLK + description: PCLK used as USART3 clock source + value: 0 + - name: SYSCLK + description: SYSCLK used as USART3 clock source + value: 1 + - name: HSI16 + description: HSI16 used as USART3 clock source + value: 2 + - name: LSE + description: LSE used as USART3 clock source + value: 3 enum/USBSEL: bit_size: 2 variants: - - name: HSI48 - description: HSI48 used as USB clock source - value: 0 - - name: PLLQCLK - description: PLLQCLK used as USB clock source - value: 1 - - name: HSE - description: HSE used as USB clock source - value: 2 + - name: HSI48 + description: HSI48 used as USB clock source + value: 0 + - name: PLLQCLK + description: PLLQCLK used as USB clock source + value: 1 + - name: HSE + description: HSE used as USB clock source + value: 2 diff --git a/data/registers/rcc_g4.yaml b/data/registers/rcc_g4.yaml index a254fdc..5c328a3 100644 --- a/data/registers/rcc_g4.yaml +++ b/data/registers/rcc_g4.yaml @@ -1,1491 +1,1504 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: Clock control register - byte_offset: 0 - fieldset: CR - - name: ICSCR - description: Internal clock sources calibration register - byte_offset: 4 - fieldset: ICSCR - - name: CFGR - description: Clock configuration register - byte_offset: 8 - fieldset: CFGR - - name: PLLCFGR - description: PLL configuration register - byte_offset: 12 - fieldset: PLLCFGR - - name: CIER - description: Clock interrupt enable register - byte_offset: 24 - fieldset: CIER - - name: CIFR - description: Clock interrupt flag register - byte_offset: 28 - access: Read - fieldset: CIFR - - name: CICR - description: Clock interrupt clear register - byte_offset: 32 - access: Write - fieldset: CICR - - name: AHB1RSTR - description: AHB1 peripheral reset register - byte_offset: 40 - fieldset: AHB1RSTR - - name: AHB2RSTR - description: AHB2 peripheral reset register - byte_offset: 44 - fieldset: AHB2RSTR - - name: AHB3RSTR - description: AHB3 peripheral reset register - byte_offset: 48 - fieldset: AHB3RSTR - - name: APB1RSTR1 - description: APB1 peripheral reset register 1 - byte_offset: 56 - fieldset: APB1RSTR1 - - name: APB1RSTR2 - description: APB1 peripheral reset register 2 - byte_offset: 60 - fieldset: APB1RSTR2 - - name: APB2RSTR - description: APB2 peripheral reset register - byte_offset: 64 - fieldset: APB2RSTR - - name: AHB1ENR - description: AHB1 peripheral clock enable register - byte_offset: 72 - fieldset: AHB1ENR - - name: AHB2ENR - description: AHB2 peripheral clock enable register - byte_offset: 76 - fieldset: AHB2ENR - - name: AHB3ENR - description: AHB3 peripheral clock enable register - byte_offset: 80 - fieldset: AHB3ENR - - name: APB1ENR1 - description: APB1ENR1 - byte_offset: 88 - fieldset: APB1ENR1 - - name: APB1ENR2 - description: APB1 peripheral clock enable register 2 - byte_offset: 92 - fieldset: APB1ENR2 - - name: APB2ENR - description: APB2ENR - byte_offset: 96 - fieldset: APB2ENR - - name: AHB1SMENR - description: AHB1 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 104 - fieldset: AHB1SMENR - - name: AHB2SMENR - description: AHB2 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 108 - fieldset: AHB2SMENR - - name: AHB3SMENR - description: AHB3 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 112 - fieldset: AHB3SMENR - - name: APB1SMENR1 - description: APB1SMENR1 - byte_offset: 120 - fieldset: APB1SMENR1 - - name: APB1SMENR2 - description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 - byte_offset: 124 - fieldset: APB1SMENR2 - - name: APB2SMENR - description: APB2SMENR - byte_offset: 128 - fieldset: APB2SMENR - - name: CCIPR - description: CCIPR - byte_offset: 136 - fieldset: CCIPR - - name: BDCR - description: BDCR - byte_offset: 144 - fieldset: BDCR - - name: CSR - description: CSR - byte_offset: 148 - fieldset: CSR - - name: CRRCR - description: Clock recovery RC register - byte_offset: 152 - fieldset: CRRCR - - name: CCIPR2 - description: Peripherals independent clock configuration register - byte_offset: 156 - fieldset: CCIPR2 + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: Internal clock sources calibration register + byte_offset: 4 + fieldset: ICSCR + - name: CFGR + description: Clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: PLLCFGR + description: PLL configuration register + byte_offset: 12 + fieldset: PLLCFGR + - name: CIER + description: Clock interrupt enable register + byte_offset: 24 + fieldset: CIER + - name: CIFR + description: Clock interrupt flag register + byte_offset: 28 + access: Read + fieldset: CIFR + - name: CICR + description: Clock interrupt clear register + byte_offset: 32 + access: Write + fieldset: CICR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 40 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: AHB2 peripheral reset register + byte_offset: 44 + fieldset: AHB2RSTR + - name: AHB3RSTR + description: AHB3 peripheral reset register + byte_offset: 48 + fieldset: AHB3RSTR + - name: APB1RSTR1 + description: APB1 peripheral reset register 1 + byte_offset: 56 + fieldset: APB1RSTR1 + - name: APB1RSTR2 + description: APB1 peripheral reset register 2 + byte_offset: 60 + fieldset: APB1RSTR2 + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 64 + fieldset: APB2RSTR + - name: AHB1ENR + description: AHB1 peripheral clock enable register + byte_offset: 72 + fieldset: AHB1ENR + - name: AHB2ENR + description: AHB2 peripheral clock enable register + byte_offset: 76 + fieldset: AHB2ENR + - name: AHB3ENR + description: AHB3 peripheral clock enable register + byte_offset: 80 + fieldset: AHB3ENR + - name: APB1ENR1 + description: APB1ENR1 + byte_offset: 88 + fieldset: APB1ENR1 + - name: APB1ENR2 + description: APB1 peripheral clock enable register 2 + byte_offset: 92 + fieldset: APB1ENR2 + - name: APB2ENR + description: APB2ENR + byte_offset: 96 + fieldset: APB2ENR + - name: AHB1SMENR + description: AHB1 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 104 + fieldset: AHB1SMENR + - name: AHB2SMENR + description: AHB2 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 108 + fieldset: AHB2SMENR + - name: AHB3SMENR + description: AHB3 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 112 + fieldset: AHB3SMENR + - name: APB1SMENR1 + description: APB1SMENR1 + byte_offset: 120 + fieldset: APB1SMENR1 + - name: APB1SMENR2 + description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 + byte_offset: 124 + fieldset: APB1SMENR2 + - name: APB2SMENR + description: APB2SMENR + byte_offset: 128 + fieldset: APB2SMENR + - name: CCIPR + description: CCIPR + byte_offset: 136 + fieldset: CCIPR + - name: BDCR + description: BDCR + byte_offset: 144 + fieldset: BDCR + - name: CSR + description: CSR + byte_offset: 148 + fieldset: CSR + - name: CRRCR + description: Clock recovery RC register + byte_offset: 152 + fieldset: CRRCR + - name: CCIPR2 + description: Peripherals independent clock configuration register + byte_offset: 156 + fieldset: CCIPR2 fieldset/AHB1ENR: description: AHB1 peripheral clock enable register fields: - - name: DMA1EN - description: DMA1 clock enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: DMA2 clock enable - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1EN - description: DMAMUX clock enable - bit_offset: 2 - bit_size: 1 - - name: CORDICEN - description: CORDIC clock enable - bit_offset: 3 - bit_size: 1 - - name: FMACEN - description: FMAC clock enable - bit_offset: 4 - bit_size: 1 - - name: FLASHEN - description: Flash memory interface clock enable - bit_offset: 8 - bit_size: 1 - - name: CRCEN - description: CRC clock enable - bit_offset: 12 - bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1EN + description: DMAMUX clock enable + bit_offset: 2 + bit_size: 1 + - name: CORDICEN + description: CORDIC clock enable + bit_offset: 3 + bit_size: 1 + - name: FMACEN + description: FMAC clock enable + bit_offset: 4 + bit_size: 1 + - name: FLASHEN + description: Flash memory interface clock enable + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - - name: DMA1RST - description: DMA1 reset - bit_offset: 0 - bit_size: 1 - - name: DMA2RST - description: DMA2 reset - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1RST - description: DMAMUX1RST - bit_offset: 2 - bit_size: 1 - - name: CORDICRST - description: CORDIC reset - bit_offset: 3 - bit_size: 1 - - name: FMACRST - description: FMAC reset - bit_offset: 4 - bit_size: 1 - - name: FLASHRST - description: Flash memory interface reset - bit_offset: 8 - bit_size: 1 - - name: CRCRST - description: CRC reset - bit_offset: 12 - bit_size: 1 + - name: DMA1RST + description: DMA1 reset + bit_offset: 0 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1RST + description: DMAMUX1RST + bit_offset: 2 + bit_size: 1 + - name: CORDICRST + description: CORDIC reset + bit_offset: 3 + bit_size: 1 + - name: FMACRST + description: FMAC reset + bit_offset: 4 + bit_size: 1 + - name: FLASHRST + description: Flash memory interface reset + bit_offset: 8 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 fieldset/AHB1SMENR: description: AHB1 peripheral clocks enable in Sleep and Stop modes register fields: - - name: DMA1SMEN - description: DMA1 clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: DMA2SMEN - description: DMA2 clocks enable during Sleep and Stop modes - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1SMEN - description: DMAMUX clock enable during Sleep and Stop modes - bit_offset: 2 - bit_size: 1 - - name: CORDICSMEN - description: CORDIC clock enable during sleep mode - bit_offset: 3 - bit_size: 1 - - name: FMACSMEN - description: FMACSM clock enable - bit_offset: 4 - bit_size: 1 - - name: FLASHSMEN - description: Flash memory interface clocks enable during Sleep and Stop modes - bit_offset: 8 - bit_size: 1 - - name: SRAM1SMEN - description: SRAM1 interface clocks enable during Sleep and Stop modes - bit_offset: 9 - bit_size: 1 - - name: CRCSMEN - description: CRCSMEN - bit_offset: 12 - bit_size: 1 + - name: DMA1SMEN + description: DMA1 clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: DMA2SMEN + description: DMA2 clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1SMEN + description: DMAMUX clock enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: CORDICSMEN + description: CORDIC clock enable during sleep mode + bit_offset: 3 + bit_size: 1 + - name: FMACSMEN + description: FMACSM clock enable + bit_offset: 4 + bit_size: 1 + - name: FLASHSMEN + description: Flash memory interface clocks enable during Sleep and Stop modes + bit_offset: 8 + bit_size: 1 + - name: SRAM1SMEN + description: SRAM1 interface clocks enable during Sleep and Stop modes + bit_offset: 9 + bit_size: 1 + - name: CRCSMEN + description: CRCSMEN + bit_offset: 12 + bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - - name: GPIOAEN - description: IO port A clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: IO port B clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: IO port C clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: IO port D clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: IO port E clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIOFEN - description: IO port F clock enable - bit_offset: 5 - bit_size: 1 - - name: GPIOGEN - description: IO port G clock enable - bit_offset: 6 - bit_size: 1 - - name: ADC12EN - description: ADC clock enable - bit_offset: 13 - bit_size: 1 - - name: ADC345EN - description: DCMI clock enable - bit_offset: 14 - bit_size: 1 - - name: DAC1EN - description: AES accelerator clock enable - bit_offset: 16 - bit_size: 1 - - name: DAC2EN - description: HASH clock enable - bit_offset: 17 - bit_size: 1 - - name: DAC3EN - description: Random Number Generator clock enable - bit_offset: 18 - bit_size: 1 - - name: DAC4EN - description: DAC4 clock enable - bit_offset: 19 - bit_size: 1 - - name: AESEN - description: AES clock enable - bit_offset: 24 - bit_size: 1 - - name: RNGEN - description: Random Number Generator clock enable - bit_offset: 26 - bit_size: 1 + - name: GPIOAEN + description: IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: IO port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: IO port E clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: IO port F clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: IO port G clock enable + bit_offset: 6 + bit_size: 1 + - name: ADC12EN + description: ADC clock enable + bit_offset: 13 + bit_size: 1 + - name: ADC345EN + description: DCMI clock enable + bit_offset: 14 + bit_size: 1 + - name: DAC1EN + description: AES accelerator clock enable + bit_offset: 16 + bit_size: 1 + - name: DAC2EN + description: HASH clock enable + bit_offset: 17 + bit_size: 1 + - name: DAC3EN + description: Random Number Generator clock enable + bit_offset: 18 + bit_size: 1 + - name: DAC4EN + description: DAC4 clock enable + bit_offset: 19 + bit_size: 1 + - name: AESEN + description: AES clock enable + bit_offset: 24 + bit_size: 1 + - name: RNGEN + description: Random Number Generator clock enable + bit_offset: 26 + bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - - name: GPIOARST - description: IO port A reset - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: IO port B reset - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: IO port C reset - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: IO port D reset - bit_offset: 3 - bit_size: 1 - - name: GPIOERST - description: IO port E reset - bit_offset: 4 - bit_size: 1 - - name: GPIOFRST - description: IO port F reset - bit_offset: 5 - bit_size: 1 - - name: GPIOGRST - description: IO port G reset - bit_offset: 6 - bit_size: 1 - - name: ADC12RST - description: ADC reset - bit_offset: 13 - bit_size: 1 - - name: ADC345RST - description: SAR ADC345 interface reset - bit_offset: 14 - bit_size: 1 - - name: DAC1RST - description: DAC1 interface reset - bit_offset: 16 - bit_size: 1 - - name: DAC2RST - description: DAC2 interface reset - bit_offset: 17 - bit_size: 1 - - name: DAC3RST - description: DAC3 interface reset - bit_offset: 18 - bit_size: 1 - - name: DAC4RST - description: DAC4 interface reset - bit_offset: 19 - bit_size: 1 - - name: AESRST - description: Cryptography module reset - bit_offset: 24 - bit_size: 1 - - name: RNGRST - description: Random Number Generator module reset - bit_offset: 26 - bit_size: 1 + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 6 + bit_size: 1 + - name: ADC12RST + description: ADC reset + bit_offset: 13 + bit_size: 1 + - name: ADC345RST + description: SAR ADC345 interface reset + bit_offset: 14 + bit_size: 1 + - name: DAC1RST + description: DAC1 interface reset + bit_offset: 16 + bit_size: 1 + - name: DAC2RST + description: DAC2 interface reset + bit_offset: 17 + bit_size: 1 + - name: DAC3RST + description: DAC3 interface reset + bit_offset: 18 + bit_size: 1 + - name: DAC4RST + description: DAC4 interface reset + bit_offset: 19 + bit_size: 1 + - name: AESRST + description: Cryptography module reset + bit_offset: 24 + bit_size: 1 + - name: RNGRST + description: Random Number Generator module reset + bit_offset: 26 + bit_size: 1 fieldset/AHB2SMENR: description: AHB2 peripheral clocks enable in Sleep and Stop modes register fields: - - name: GPIOASMEN - description: IO port A clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: GPIOBSMEN - description: IO port B clocks enable during Sleep and Stop modes - bit_offset: 1 - bit_size: 1 - - name: GPIOCSMEN - description: IO port C clocks enable during Sleep and Stop modes - bit_offset: 2 - bit_size: 1 - - name: GPIODSMEN - description: IO port D clocks enable during Sleep and Stop modes - bit_offset: 3 - bit_size: 1 - - name: GPIOESMEN - description: IO port E clocks enable during Sleep and Stop modes - bit_offset: 4 - bit_size: 1 - - name: GPIOFSMEN - description: IO port F clocks enable during Sleep and Stop modes - bit_offset: 5 - bit_size: 1 - - name: GPIOGSMEN - description: IO port G clocks enable during Sleep and Stop modes - bit_offset: 6 - bit_size: 1 - - name: CCMSRAMSMEN - description: CCM SRAM interface clocks enable during Sleep and Stop modes - bit_offset: 9 - bit_size: 1 - - name: SRAM2SMEN - description: SRAM2 interface clocks enable during Sleep and Stop modes - bit_offset: 10 - bit_size: 1 - - name: ADC12SMEN - description: ADC clocks enable during Sleep and Stop modes - bit_offset: 13 - bit_size: 1 - - name: ADC345SMEN - description: DCMI clock enable during Sleep and Stop modes - bit_offset: 14 - bit_size: 1 - - name: DAC1SMEN - description: AES accelerator clocks enable during Sleep and Stop modes - bit_offset: 16 - bit_size: 1 - - name: DAC2SMEN - description: HASH clock enable during Sleep and Stop modes - bit_offset: 17 - bit_size: 1 - - name: DAC3SMEN - description: DAC3 clock enable during sleep mode - bit_offset: 18 - bit_size: 1 - - name: DAC4SMEN - description: DAC4 clock enable during sleep mode - bit_offset: 19 - bit_size: 1 - - name: AESMEN - description: Cryptography clock enable during sleep mode - bit_offset: 24 - bit_size: 1 - - name: RNGEN - description: Random Number Generator clock enable during sleep mode - bit_offset: 26 - bit_size: 1 + - name: GPIOASMEN + description: IO port A clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: IO port B clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: IO port C clocks enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: GPIODSMEN + description: IO port D clocks enable during Sleep and Stop modes + bit_offset: 3 + bit_size: 1 + - name: GPIOESMEN + description: IO port E clocks enable during Sleep and Stop modes + bit_offset: 4 + bit_size: 1 + - name: GPIOFSMEN + description: IO port F clocks enable during Sleep and Stop modes + bit_offset: 5 + bit_size: 1 + - name: GPIOGSMEN + description: IO port G clocks enable during Sleep and Stop modes + bit_offset: 6 + bit_size: 1 + - name: CCMSRAMSMEN + description: CCM SRAM interface clocks enable during Sleep and Stop modes + bit_offset: 9 + bit_size: 1 + - name: SRAM2SMEN + description: SRAM2 interface clocks enable during Sleep and Stop modes + bit_offset: 10 + bit_size: 1 + - name: ADC12SMEN + description: ADC clocks enable during Sleep and Stop modes + bit_offset: 13 + bit_size: 1 + - name: ADC345SMEN + description: DCMI clock enable during Sleep and Stop modes + bit_offset: 14 + bit_size: 1 + - name: DAC1SMEN + description: AES accelerator clocks enable during Sleep and Stop modes + bit_offset: 16 + bit_size: 1 + - name: DAC2SMEN + description: HASH clock enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: DAC3SMEN + description: DAC3 clock enable during sleep mode + bit_offset: 18 + bit_size: 1 + - name: DAC4SMEN + description: DAC4 clock enable during sleep mode + bit_offset: 19 + bit_size: 1 + - name: AESMEN + description: Cryptography clock enable during sleep mode + bit_offset: 24 + bit_size: 1 + - name: RNGEN + description: Random Number Generator clock enable during sleep mode + bit_offset: 26 + bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: - - name: FMCEN - description: Flexible memory controller clock enable - bit_offset: 0 - bit_size: 1 - - name: QUADSPIEN - description: QUADSPI memory interface clock enable - bit_offset: 8 - bit_size: 1 + - name: FMCEN + description: Flexible memory controller clock enable + bit_offset: 0 + bit_size: 1 + - name: QUADSPIEN + description: QUADSPI memory interface clock enable + bit_offset: 8 + bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - - name: FMCRST - description: Flexible memory controller reset - bit_offset: 0 - bit_size: 1 - - name: QSPIRST - description: Quad SPI 1 module reset - bit_offset: 8 - bit_size: 1 + - name: FMCRST + description: Flexible memory controller reset + bit_offset: 0 + bit_size: 1 + - name: QSPIRST + description: Quad SPI 1 module reset + bit_offset: 8 + bit_size: 1 fieldset/AHB3SMENR: description: AHB3 peripheral clocks enable in Sleep and Stop modes register fields: - - name: FMCSMEN - description: Flexible memory controller clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: QSPISMEN - description: QUADSPI memory interface clock enable during Sleep and Stop modes - bit_offset: 8 - bit_size: 1 + - name: FMCSMEN + description: Flexible memory controller clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: QSPISMEN + description: QUADSPI memory interface clock enable during Sleep and Stop modes + bit_offset: 8 + bit_size: 1 fieldset/APB1ENR1: description: APB1ENR1 fields: - - name: TIM2EN - description: TIM2 timer clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: TIM3 timer clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: TIM4 timer clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: TIM5 timer clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: TIM6 timer clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: TIM7 timer clock enable - bit_offset: 5 - bit_size: 1 - - name: CRSEN - description: CRSclock enable - bit_offset: 8 - bit_size: 1 - - name: RTCAPBEN - description: RTC APB clock enable - bit_offset: 10 - bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI2 clock enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI3 clock enable - bit_offset: 15 - bit_size: 1 - - name: USART2EN - description: USART2 clock enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART3 clock enable - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: UART4 clock enable - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: UART5 clock enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C2 clock enable - bit_offset: 22 - bit_size: 1 - - name: USBEN - description: USB device clock enable - bit_offset: 23 - bit_size: 1 - - name: FDCANEN - description: FDCAN clock enable - bit_offset: 25 - bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - - name: I2C3EN - description: I2C3 clock enable - bit_offset: 30 - bit_size: 1 - - name: LPTIM1EN - description: Low power timer 1 clock enable - bit_offset: 31 - bit_size: 1 + - name: TIM2EN + description: TIM2 timer clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM3 timer clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM4 timer clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: TIM5 timer clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM6 timer clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM7 timer clock enable + bit_offset: 5 + bit_size: 1 + - name: CRSEN + description: CRSclock enable + bit_offset: 8 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: USB device clock enable + bit_offset: 23 + bit_size: 1 + - name: FDCANEN + description: FDCAN clock enable + bit_offset: 25 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 30 + bit_size: 1 + - name: LPTIM1EN + description: Low power timer 1 clock enable + bit_offset: 31 + bit_size: 1 fieldset/APB1ENR2: description: APB1 peripheral clock enable register 2 fields: - - name: LPUART1EN - description: Low power UART 1 clock enable - bit_offset: 0 - bit_size: 1 - - name: I2C4EN - description: I2C4 clock enable - bit_offset: 1 - bit_size: 1 - - name: UCPD1EN - description: UCPD1 clock enable - bit_offset: 8 - bit_size: 1 + - name: LPUART1EN + description: Low power UART 1 clock enable + bit_offset: 0 + bit_size: 1 + - name: I2C4EN + description: I2C4 clock enable + bit_offset: 1 + bit_size: 1 + - name: UCPD1EN + description: UCPD1 clock enable + bit_offset: 8 + bit_size: 1 fieldset/APB1RSTR1: description: APB1 peripheral reset register 1 fields: - - name: TIM2RST - description: TIM2 timer reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: TIM3 timer reset - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: TIM3 timer reset - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: TIM5 timer reset - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: TIM6 timer reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: TIM7 timer reset - bit_offset: 5 - bit_size: 1 - - name: CRSRST - description: Clock recovery system reset - bit_offset: 8 - bit_size: 1 - - name: SPI2RST - description: SPI2 reset - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: SPI3 reset - bit_offset: 15 - bit_size: 1 - - name: USART2RST - description: USART2 reset - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: USART3 reset - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: UART4 reset - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: UART5 reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C2 reset - bit_offset: 22 - bit_size: 1 - - name: USBRST - description: USBD reset - bit_offset: 23 - bit_size: 1 - - name: FDCANRST - description: FDCAN reset - bit_offset: 25 - bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - - name: I2C3RST - description: I2C3 interface reset - bit_offset: 30 - bit_size: 1 - - name: LPTIM1RST - description: Low Power Timer 1 reset - bit_offset: 31 - bit_size: 1 + - name: TIM2RST + description: TIM2 timer reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: TIM3 timer reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: TIM3 timer reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: TIM5 timer reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: TIM6 timer reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM7 timer reset + bit_offset: 5 + bit_size: 1 + - name: CRSRST + description: Clock recovery system reset + bit_offset: 8 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: UART4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: UART5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: USBD reset + bit_offset: 23 + bit_size: 1 + - name: FDCANRST + description: FDCAN reset + bit_offset: 25 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: I2C3RST + description: I2C3 interface reset + bit_offset: 30 + bit_size: 1 + - name: LPTIM1RST + description: Low Power Timer 1 reset + bit_offset: 31 + bit_size: 1 fieldset/APB1RSTR2: description: APB1 peripheral reset register 2 fields: - - name: LPUART1RST - description: Low-power UART 1 reset - bit_offset: 0 - bit_size: 1 - - name: I2C4RST - description: I2C4 reset - bit_offset: 1 - bit_size: 1 - - name: UCPD1RST - description: UCPD1 reset - bit_offset: 8 - bit_size: 1 + - name: LPUART1RST + description: Low-power UART 1 reset + bit_offset: 0 + bit_size: 1 + - name: I2C4RST + description: I2C4 reset + bit_offset: 1 + bit_size: 1 + - name: UCPD1RST + description: UCPD1 reset + bit_offset: 8 + bit_size: 1 fieldset/APB1SMENR1: description: APB1SMENR1 fields: - - name: TIM2SMEN - description: TIM2 timer clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: TIM3SMEN - description: TIM3 timer clocks enable during Sleep and Stop modes - bit_offset: 1 - bit_size: 1 - - name: TIM4SMEN - description: TIM4 timer clocks enable during Sleep and Stop modes - bit_offset: 2 - bit_size: 1 - - name: TIM5SMEN - description: TIM5 timer clocks enable during Sleep and Stop modes - bit_offset: 3 - bit_size: 1 - - name: TIM6SMEN - description: TIM6 timer clocks enable during Sleep and Stop modes - bit_offset: 4 - bit_size: 1 - - name: TIM7SMEN - description: TIM7 timer clocks enable during Sleep and Stop modes - bit_offset: 5 - bit_size: 1 - - name: CRSSMEN - description: CRS clock enable during sleep mode - bit_offset: 8 - bit_size: 1 - - name: RTCAPBSMEN - description: RTC APB clock enable during Sleep and Stop modes - bit_offset: 10 - bit_size: 1 - - name: WWDGSMEN - description: Window watchdog clocks enable during Sleep and Stop modes - bit_offset: 11 - bit_size: 1 - - name: SPI2SMEN - description: SPI2 clocks enable during Sleep and Stop modes - bit_offset: 14 - bit_size: 1 - - name: SP3SMEN - description: SPI3 clocks enable during Sleep and Stop modes - bit_offset: 15 - bit_size: 1 - - name: USART2SMEN - description: USART2 clocks enable during Sleep and Stop modes - bit_offset: 17 - bit_size: 1 - - name: USART3SMEN - description: USART3 clocks enable during Sleep and Stop modes - bit_offset: 18 - bit_size: 1 - - name: UART4SMEN - description: UART4 clocks enable during Sleep and Stop modes - bit_offset: 19 - bit_size: 1 - - name: UART5SMEN - description: UART5 clocks enable during Sleep and Stop modes - bit_offset: 20 - bit_size: 1 - - name: I2C1SMEN - description: I2C1 clocks enable during Sleep and Stop modes - bit_offset: 21 - bit_size: 1 - - name: I2C2SMEN - description: I2C2 clocks enable during Sleep and Stop modes - bit_offset: 22 - bit_size: 1 - - name: USBSMEN - description: USB device clocks enable during Sleep and Stop modes - bit_offset: 23 - bit_size: 1 - - name: FDCANSMEN - description: FDCAN clock enable during sleep mode - bit_offset: 25 - bit_size: 1 - - name: PWRSMEN - description: Power interface clocks enable during Sleep and Stop modes - bit_offset: 28 - bit_size: 1 - - name: I2C3SMEN - description: I2C3 clocks enable during Sleep and Stop modes - bit_offset: 30 - bit_size: 1 - - name: LPTIM1SMEN - description: Low Power Timer1 clock enable during sleep mode - bit_offset: 31 - bit_size: 1 + - name: TIM2SMEN + description: TIM2 timer clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: TIM3SMEN + description: TIM3 timer clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: TIM4SMEN + description: TIM4 timer clocks enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: TIM5SMEN + description: TIM5 timer clocks enable during Sleep and Stop modes + bit_offset: 3 + bit_size: 1 + - name: TIM6SMEN + description: TIM6 timer clocks enable during Sleep and Stop modes + bit_offset: 4 + bit_size: 1 + - name: TIM7SMEN + description: TIM7 timer clocks enable during Sleep and Stop modes + bit_offset: 5 + bit_size: 1 + - name: CRSSMEN + description: CRS clock enable during sleep mode + bit_offset: 8 + bit_size: 1 + - name: RTCAPBSMEN + description: RTC APB clock enable during Sleep and Stop modes + bit_offset: 10 + bit_size: 1 + - name: WWDGSMEN + description: Window watchdog clocks enable during Sleep and Stop modes + bit_offset: 11 + bit_size: 1 + - name: SPI2SMEN + description: SPI2 clocks enable during Sleep and Stop modes + bit_offset: 14 + bit_size: 1 + - name: SP3SMEN + description: SPI3 clocks enable during Sleep and Stop modes + bit_offset: 15 + bit_size: 1 + - name: USART2SMEN + description: USART2 clocks enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: USART3SMEN + description: USART3 clocks enable during Sleep and Stop modes + bit_offset: 18 + bit_size: 1 + - name: UART4SMEN + description: UART4 clocks enable during Sleep and Stop modes + bit_offset: 19 + bit_size: 1 + - name: UART5SMEN + description: UART5 clocks enable during Sleep and Stop modes + bit_offset: 20 + bit_size: 1 + - name: I2C1SMEN + description: I2C1 clocks enable during Sleep and Stop modes + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: I2C2 clocks enable during Sleep and Stop modes + bit_offset: 22 + bit_size: 1 + - name: USBSMEN + description: USB device clocks enable during Sleep and Stop modes + bit_offset: 23 + bit_size: 1 + - name: FDCANSMEN + description: FDCAN clock enable during sleep mode + bit_offset: 25 + bit_size: 1 + - name: PWRSMEN + description: Power interface clocks enable during Sleep and Stop modes + bit_offset: 28 + bit_size: 1 + - name: I2C3SMEN + description: I2C3 clocks enable during Sleep and Stop modes + bit_offset: 30 + bit_size: 1 + - name: LPTIM1SMEN + description: Low Power Timer1 clock enable during sleep mode + bit_offset: 31 + bit_size: 1 fieldset/APB1SMENR2: description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 fields: - - name: LPUART1SMEN - description: Low power UART 1 clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: I2C4SMEN - description: I2C4 clocks enable during Sleep and Stop modes - bit_offset: 1 - bit_size: 1 - - name: UCPD1SMEN - description: UCPD1 clocks enable during Sleep and Stop modes - bit_offset: 8 - bit_size: 1 + - name: LPUART1SMEN + description: Low power UART 1 clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: I2C4SMEN + description: I2C4 clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: UCPD1SMEN + description: UCPD1 clocks enable during Sleep and Stop modes + bit_offset: 8 + bit_size: 1 fieldset/APB2ENR: description: APB2ENR fields: - - name: SYSCFGEN - description: SYSCFG clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM1EN - description: TIM1 timer clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: SPI1 clock enable - bit_offset: 12 - bit_size: 1 - - name: TIM8EN - description: TIM8 timer clock enable - bit_offset: 13 - bit_size: 1 - - name: USART1EN - description: USART1clock enable - bit_offset: 14 - bit_size: 1 - - name: SPI4EN - description: SPI 4 clock enable - bit_offset: 15 - bit_size: 1 - - name: TIM15EN - description: TIM15 timer clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: TIM16 timer clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: TIM17 timer clock enable - bit_offset: 18 - bit_size: 1 - - name: TIM20EN - description: Timer 20 clock enable - bit_offset: 20 - bit_size: 1 - - name: SAI1EN - description: SAI1 clock enable - bit_offset: 21 - bit_size: 1 - - name: HRTIM1EN - description: HRTIMER clock enable - bit_offset: 26 - bit_size: 1 + - name: SYSCFGEN + description: SYSCFG clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM1EN + description: TIM1 timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: TIM8EN + description: TIM8 timer clock enable + bit_offset: 13 + bit_size: 1 + - name: USART1EN + description: USART1clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI4EN + description: SPI 4 clock enable + bit_offset: 15 + bit_size: 1 + - name: TIM15EN + description: TIM15 timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: TIM20EN + description: Timer 20 clock enable + bit_offset: 20 + bit_size: 1 + - name: SAI1EN + description: SAI1 clock enable + bit_offset: 21 + bit_size: 1 + - name: HRTIM1EN + description: HRTIMER clock enable + bit_offset: 26 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - - name: SYSCFGRST - description: System configuration (SYSCFG) reset - bit_offset: 0 - bit_size: 1 - - name: TIM1RST - description: TIM1 timer reset - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: SPI1 reset - bit_offset: 12 - bit_size: 1 - - name: TIM8RST - description: TIM8 timer reset - bit_offset: 13 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 14 - bit_size: 1 - - name: SPI4RST - description: SPI 4 reset - bit_offset: 15 - bit_size: 1 - - name: TIM15RST - description: TIM15 timer reset - bit_offset: 16 - bit_size: 1 - - name: TIM16RST - description: TIM16 timer reset - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: TIM17 timer reset - bit_offset: 18 - bit_size: 1 - - name: TIM20RST - description: Timer 20 reset - bit_offset: 20 - bit_size: 1 - - name: SAI1RST - description: Serial audio interface 1 (SAI1) reset - bit_offset: 21 - bit_size: 1 - - name: HRTIM1RST - description: HRTIMER reset - bit_offset: 26 - bit_size: 1 + - name: SYSCFGRST + description: System configuration (SYSCFG) reset + bit_offset: 0 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI1 reset + bit_offset: 12 + bit_size: 1 + - name: TIM8RST + description: TIM8 timer reset + bit_offset: 13 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: SPI4RST + description: SPI 4 reset + bit_offset: 15 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: TIM20RST + description: Timer 20 reset + bit_offset: 20 + bit_size: 1 + - name: SAI1RST + description: Serial audio interface 1 (SAI1) reset + bit_offset: 21 + bit_size: 1 + - name: HRTIM1RST + description: HRTIMER reset + bit_offset: 26 + bit_size: 1 fieldset/APB2SMENR: description: APB2SMENR fields: - - name: SYSCFGSMEN - description: SYSCFG clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: TIM1SMEN - description: TIM1 timer clocks enable during Sleep and Stop modes - bit_offset: 11 - bit_size: 1 - - name: SPI1SMEN - description: SPI1 clocks enable during Sleep and Stop modes - bit_offset: 12 - bit_size: 1 - - name: TIM8SMEN - description: TIM8 timer clocks enable during Sleep and Stop modes - bit_offset: 13 - bit_size: 1 - - name: USART1SMEN - description: USART1clocks enable during Sleep and Stop modes - bit_offset: 14 - bit_size: 1 - - name: SPI4SMEN - description: SPI4 timer clocks enable during Sleep and Stop modes - bit_offset: 15 - bit_size: 1 - - name: TIM15SMEN - description: TIM15 timer clocks enable during Sleep and Stop modes - bit_offset: 16 - bit_size: 1 - - name: TIM16SMEN - description: TIM16 timer clocks enable during Sleep and Stop modes - bit_offset: 17 - bit_size: 1 - - name: TIM17SMEN - description: TIM17 timer clocks enable during Sleep and Stop modes - bit_offset: 18 - bit_size: 1 - - name: TIM20SMEN - description: Timer 20clock enable during sleep mode - bit_offset: 20 - bit_size: 1 - - name: SAI1SMEN - description: SAI1 clock enable during sleep mode - bit_offset: 21 - bit_size: 1 - - name: HRTIM1SMEN - description: HRTIMER clock enable during sleep mode - bit_offset: 26 - bit_size: 1 + - name: SYSCFGSMEN + description: SYSCFG clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: TIM1SMEN + description: TIM1 timer clocks enable during Sleep and Stop modes + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: SPI1 clocks enable during Sleep and Stop modes + bit_offset: 12 + bit_size: 1 + - name: TIM8SMEN + description: TIM8 timer clocks enable during Sleep and Stop modes + bit_offset: 13 + bit_size: 1 + - name: USART1SMEN + description: USART1clocks enable during Sleep and Stop modes + bit_offset: 14 + bit_size: 1 + - name: SPI4SMEN + description: SPI4 timer clocks enable during Sleep and Stop modes + bit_offset: 15 + bit_size: 1 + - name: TIM15SMEN + description: TIM15 timer clocks enable during Sleep and Stop modes + bit_offset: 16 + bit_size: 1 + - name: TIM16SMEN + description: TIM16 timer clocks enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: TIM17 timer clocks enable during Sleep and Stop modes + bit_offset: 18 + bit_size: 1 + - name: TIM20SMEN + description: Timer 20clock enable during sleep mode + bit_offset: 20 + bit_size: 1 + - name: SAI1SMEN + description: SAI1 clock enable during sleep mode + bit_offset: 21 + bit_size: 1 + - name: HRTIM1SMEN + description: HRTIMER clock enable during sleep mode + bit_offset: 26 + bit_size: 1 fieldset/BDCR: description: BDCR fields: - - name: LSEON - description: LSE oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: LSE oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: LSE oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: LSEDRV - description: SE oscillator drive capability - bit_offset: 3 - bit_size: 2 - enum: LSEDRV - - name: LSECSSON - description: LSECSSON - bit_offset: 5 - bit_size: 1 - - name: LSECSSD - description: LSECSSD - bit_offset: 6 - bit_size: 1 - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: RTC domain software reset - bit_offset: 16 - bit_size: 1 - - name: LSCOEN - description: Low speed clock output enable - bit_offset: 24 - bit_size: 1 - - name: LSCOSEL - description: Low speed clock output selection - bit_offset: 25 - bit_size: 1 + - name: LSEON + description: LSE oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: LSE oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: LSE oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: SE oscillator drive capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: LSECSSON + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: LSECSSD + bit_offset: 6 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: RTC domain software reset + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: Low speed clock output enable + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: Low speed clock output selection + bit_offset: 25 + bit_size: 1 fieldset/CCIPR: description: CCIPR fields: - - name: USART1SEL - description: USART1 clock source selection - bit_offset: 0 - bit_size: 2 - - name: USART2SEL - description: USART2 clock source selection - bit_offset: 2 - bit_size: 2 - - name: USART3SEL - description: USART3 clock source selection - bit_offset: 4 - bit_size: 2 - - name: UART4SEL - description: UART4 clock source selection - bit_offset: 6 - bit_size: 2 - - name: UART5SEL - description: UART5 clock source selection - bit_offset: 8 - bit_size: 2 - - name: LPUART1SEL - description: LPUART1 clock source selection - bit_offset: 10 - bit_size: 2 - - name: I2C1SEL - description: I2C1 clock source selection - bit_offset: 12 - bit_size: 2 - - name: I2C2SEL - description: I2C2 clock source selection - bit_offset: 14 - bit_size: 2 - - name: I2C3SEL - description: I2C3 clock source selection - bit_offset: 16 - bit_size: 2 - - name: LPTIM1SEL - description: Low power timer 1 clock source selection - bit_offset: 18 - bit_size: 2 - - name: SAI1SEL - description: Low power timer 2 clock source selection - bit_offset: 20 - bit_size: 2 - - name: I2S23SEL - description: SAI1 clock source selection - bit_offset: 22 - bit_size: 2 - - name: FDCANSEL - description: SAI2 clock source selection - bit_offset: 24 - bit_size: 2 - - name: CLK48SEL - description: 48 MHz clock source selection - bit_offset: 26 - bit_size: 2 - enum: CLK48SEL - - name: ADC12SEL - description: ADCs clock source selection - bit_offset: 28 - bit_size: 2 - - name: ADC345SEL - description: ADC3/4/5 clock source selection - bit_offset: 30 - bit_size: 2 + - name: USART1SEL + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + - name: USART2SEL + description: USART2 clock source selection + bit_offset: 2 + bit_size: 2 + - name: USART3SEL + description: USART3 clock source selection + bit_offset: 4 + bit_size: 2 + - name: UART4SEL + description: UART4 clock source selection + bit_offset: 6 + bit_size: 2 + - name: UART5SEL + description: UART5 clock source selection + bit_offset: 8 + bit_size: 2 + - name: LPUART1SEL + description: LPUART1 clock source selection + bit_offset: 10 + bit_size: 2 + - name: I2C1SEL + description: I2C1 clock source selection + bit_offset: 12 + bit_size: 2 + - name: I2C2SEL + description: I2C2 clock source selection + bit_offset: 14 + bit_size: 2 + - name: I2C3SEL + description: I2C3 clock source selection + bit_offset: 16 + bit_size: 2 + - name: LPTIM1SEL + description: Low power timer 1 clock source selection + bit_offset: 18 + bit_size: 2 + - name: SAI1SEL + description: Low power timer 2 clock source selection + bit_offset: 20 + bit_size: 2 + - name: I2S23SEL + description: SAI1 clock source selection + bit_offset: 22 + bit_size: 2 + - name: FDCANSEL + description: SAI2 clock source selection + bit_offset: 24 + bit_size: 2 + - name: CLK48SEL + description: 48 MHz clock source selection + bit_offset: 26 + bit_size: 2 + enum: CLK48SEL + - name: ADC12SEL + description: ADCs clock source selection + bit_offset: 28 + bit_size: 2 + enum: ADCSEL + - name: ADC345SEL + description: ADC3/4/5 clock source selection + bit_offset: 30 + bit_size: 2 + enum: ADCSEL fieldset/CCIPR2: description: Peripherals independent clock configuration register fields: - - name: I2C4SEL - description: I2C4 clock source selection - bit_offset: 0 - bit_size: 2 - - name: QSPISEL - description: Octospi clock source selection - bit_offset: 20 - bit_size: 2 + - name: I2C4SEL + description: I2C4 clock source selection + bit_offset: 0 + bit_size: 2 + - name: QSPISEL + description: Octospi clock source selection + bit_offset: 20 + bit_size: 2 fieldset/CFGR: description: Clock configuration register fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: System clock switch status - bit_offset: 2 - bit_size: 2 - enum: SW - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - enum: HPRE - - name: PPRE1 - description: PB low-speed prescaler (APB1) - bit_offset: 8 - bit_size: 3 - enum: PPRE - - name: PPRE2 - description: APB high-speed prescaler (APB2) - bit_offset: 11 - bit_size: 3 - enum: PPRE - - name: MCOSEL - description: Microcontroller clock output - bit_offset: 24 - bit_size: 4 - enum: MCOSEL - - name: MCOPRE - description: Microcontroller clock output prescaler - bit_offset: 28 - bit_size: 3 - enum: MCOPRE + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: PB low-speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high-speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: MCOSEL + description: Microcontroller clock output + bit_offset: 24 + bit_size: 4 + enum: MCOSEL + - name: MCOPRE + description: Microcontroller clock output prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: - - name: LSIRDYC - description: LSI ready interrupt clear - bit_offset: 0 - bit_size: 1 - - name: LSERDYC - description: LSE ready interrupt clear - bit_offset: 1 - bit_size: 1 - - name: HSIRDYC - description: HSI ready interrupt clear - bit_offset: 3 - bit_size: 1 - - name: HSERDYC - description: HSE ready interrupt clear - bit_offset: 4 - bit_size: 1 - - name: PLLRDYC - description: PLL ready interrupt clear - bit_offset: 5 - bit_size: 1 - - name: CSSC - description: Clock security system interrupt clear - bit_offset: 8 - bit_size: 1 - - name: LSECSSC - description: LSE Clock security system interrupt clear - bit_offset: 9 - bit_size: 1 - - name: HSI48RDYC - description: HSI48 oscillator ready interrupt clear - bit_offset: 10 - bit_size: 1 + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 1 + bit_size: 1 + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 4 + bit_size: 1 + - name: PLLRDYC + description: PLL ready interrupt clear + bit_offset: 5 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 8 + bit_size: 1 + - name: LSECSSC + description: LSE Clock security system interrupt clear + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYC + description: HSI48 oscillator ready interrupt clear + bit_offset: 10 + bit_size: 1 fieldset/CIER: description: Clock interrupt enable register fields: - - name: LSIRDYIE - description: LSI ready interrupt enable - bit_offset: 0 - bit_size: 1 - - name: LSERDYIE - description: LSE ready interrupt enable - bit_offset: 1 - bit_size: 1 - - name: HSIRDYIE - description: HSI ready interrupt enable - bit_offset: 3 - bit_size: 1 - - name: HSERDYIE - description: HSE ready interrupt enable - bit_offset: 4 - bit_size: 1 - - name: PLLRDYIE - description: PLL ready interrupt enable - bit_offset: 5 - bit_size: 1 - - name: LSECSSIE - description: LSE clock security system interrupt enable - bit_offset: 9 - bit_size: 1 - - name: HSI48RDYIE - description: HSI48 ready interrupt enable - bit_offset: 10 - bit_size: 1 + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 1 + bit_size: 1 + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 4 + bit_size: 1 + - name: PLLRDYIE + description: PLL ready interrupt enable + bit_offset: 5 + bit_size: 1 + - name: LSECSSIE + description: LSE clock security system interrupt enable + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYIE + description: HSI48 ready interrupt enable + bit_offset: 10 + bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register fields: - - name: LSIRDYF - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - - name: HSIRDYF - description: HSI ready interrupt flag - bit_offset: 3 - bit_size: 1 - - name: HSERDYF - description: HSE ready interrupt flag - bit_offset: 4 - bit_size: 1 - - name: PLLRDYF - description: PLL ready interrupt flag - bit_offset: 5 - bit_size: 1 - - name: CSSF - description: Clock security system interrupt flag - bit_offset: 8 - bit_size: 1 - - name: LSECSSF - description: LSE Clock security system interrupt flag - bit_offset: 9 - bit_size: 1 - - name: HSI48RDYF - description: HSI48 ready interrupt flag - bit_offset: 10 - bit_size: 1 + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLLRDYF + description: PLL ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: CSSF + description: Clock security system interrupt flag + bit_offset: 8 + bit_size: 1 + - name: LSECSSF + description: LSE Clock security system interrupt flag + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYF + description: HSI48 ready interrupt flag + bit_offset: 10 + bit_size: 1 fieldset/CR: description: Clock control register fields: - - name: HSION - description: HSI clock enable - bit_offset: 8 - bit_size: 1 - - name: HSIKERON - description: HSI always enable for peripheral kernels - bit_offset: 9 - bit_size: 1 - - name: HSIRDY - description: HSI clock ready flag - bit_offset: 10 - bit_size: 1 - - name: HSEON - description: HSE clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: HSE crystal oscillator bypass - bit_offset: 18 - bit_size: 1 - - name: CSSON - description: Clock security system enable - bit_offset: 19 - bit_size: 1 - - name: PLLON - description: Main PLL enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: Main PLL clock ready flag - bit_offset: 25 - bit_size: 1 + - name: HSION + description: HSI clock enable + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: HSI always enable for peripheral kernels + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: HSI clock ready flag + bit_offset: 10 + bit_size: 1 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: HSE crystal oscillator bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: Main PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL clock ready flag + bit_offset: 25 + bit_size: 1 fieldset/CRRCR: description: Clock recovery RC register fields: - - name: HSI48ON - description: HSI48 clock enable - bit_offset: 0 - bit_size: 1 - - name: HSI48RDY - description: HSI48 clock ready flag - bit_offset: 1 - bit_size: 1 - - name: HSI48CAL - description: HSI48 clock calibration - bit_offset: 7 - bit_size: 9 + - name: HSI48ON + description: HSI48 clock enable + bit_offset: 0 + bit_size: 1 + - name: HSI48RDY + description: HSI48 clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSI48CAL + description: HSI48 clock calibration + bit_offset: 7 + bit_size: 9 fieldset/CSR: description: CSR fields: - - name: LSION - description: LSI oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: LSI oscillator ready - bit_offset: 1 - bit_size: 1 - - name: RMVF - description: Remove reset flag - bit_offset: 23 - bit_size: 1 - - name: OBLRSTF - description: Option byte loader reset flag - bit_offset: 25 - bit_size: 1 - - name: PINRSTF - description: Pad reset flag - bit_offset: 26 - bit_size: 1 - - name: BORRSTF - description: BOR flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: Independent window watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSION + description: LSI oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: LSI oscillator ready + bit_offset: 1 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 23 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: Pad reset flag + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: BOR flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent window watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 fieldset/ICSCR: description: Internal clock sources calibration register fields: - - name: HSICAL0 - description: Internal High Speed clock Calibration - bit_offset: 16 - bit_size: 8 - - name: HSITRIM - description: Internal High Speed clock trimming - bit_offset: 24 - bit_size: 7 + - name: HSICAL0 + description: Internal High Speed clock Calibration + bit_offset: 16 + bit_size: 8 + - name: HSITRIM + description: Internal High Speed clock trimming + bit_offset: 24 + bit_size: 7 fieldset/PLLCFGR: description: PLL configuration register fields: - - name: PLLSRC - description: "Main PLL, PLLSAI1 and PLLSAI2 entry clock source" - bit_offset: 0 - bit_size: 2 - enum: PLLSRC - - name: PLLM - description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock - bit_offset: 4 - bit_size: 4 - - name: PLLN - description: Main PLL multiplication factor for VCO - bit_offset: 8 - bit_size: 7 - - name: PLLPEN - description: Main PLL PLLSAI3CLK output enable - bit_offset: 16 - bit_size: 1 - - name: PLLP - description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) - bit_offset: 17 - bit_size: 1 - - name: PLLQEN - description: Main PLL PLLUSB1CLK output enable - bit_offset: 20 - bit_size: 1 - - name: PLLQ - description: Main PLL division factor for PLLUSB1CLK(48 MHz clock) - bit_offset: 21 - bit_size: 2 - - name: PLLREN - description: Main PLL PLLCLK output enable - bit_offset: 24 - bit_size: 1 - - name: PLLR - description: Main PLL division factor for PLLCLK (system clock) - bit_offset: 25 - bit_size: 2 - - name: PLLPDIV - description: Main PLL division factor for PLLSAI2CLK - bit_offset: 27 - bit_size: 5 + - name: PLLSRC + description: Main PLL, PLLSAI1 and PLLSAI2 entry clock source + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: PLLM + description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock + bit_offset: 4 + bit_size: 4 + - name: PLLN + description: Main PLL multiplication factor for VCO + bit_offset: 8 + bit_size: 7 + - name: PLLPEN + description: Main PLL PLLSAI3CLK output enable + bit_offset: 16 + bit_size: 1 + - name: PLLP + description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) + bit_offset: 17 + bit_size: 1 + - name: PLLQEN + description: Main PLL PLLUSB1CLK output enable + bit_offset: 20 + bit_size: 1 + - name: PLLQ + description: Main PLL division factor for PLLUSB1CLK(48 MHz clock) + bit_offset: 21 + bit_size: 2 + - name: PLLREN + description: Main PLL PLLCLK output enable + bit_offset: 24 + bit_size: 1 + - name: PLLR + description: Main PLL division factor for PLLCLK (system clock) + bit_offset: 25 + bit_size: 2 + - name: PLLPDIV + description: Main PLL division factor for PLLSAI2CLK + bit_offset: 27 + bit_size: 5 +enum/ADCSEL: + bit_size: 2 + variants: + - name: NOCLK + description: No clock selected + value: 0 + - name: PLLP + description: PLL 'P' clock selected as ADC clock + value: 1 + - name: SYSCLK + description: System clock selected as ADC clock + value: 2 enum/CLK48SEL: bit_size: 2 variants: - - name: HSI48 - description: HSI48 oscillator clock selected as 48 MHz clock - value: 0 - - name: PLLQCLK - description: PLLQCLK selected as 48 MHz clock - value: 2 + - name: HSI48 + description: HSI48 oscillator clock selected as 48 MHz clock + value: 0 + - name: PLLQCLK + description: PLLQCLK selected as 48 MHz clock + value: 2 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: SYSCLK not divided - value: 0 - - name: Div2 - description: SYSCLK is divided by 2 - value: 8 - - name: Div4 - description: SYSCLK is divided by 4 - value: 9 - - name: Div8 - description: SYSCLK is divided by 8 - value: 10 - - name: Div16 - description: SYSCLK is divided by 16 - value: 11 - - name: Div64 - description: SYSCLK is divided by 64 - value: 12 - - name: Div128 - description: SYSCLK is divided by 128 - value: 13 - - name: Div256 - description: SYSCLK is divided by 256 - value: 14 - - name: Div512 - description: SYSCLK is divided by 512 - value: 15 + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK is divided by 2 + value: 8 + - name: Div4 + description: SYSCLK is divided by 4 + value: 9 + - name: Div8 + description: SYSCLK is divided by 8 + value: 10 + - name: Div16 + description: SYSCLK is divided by 16 + value: 11 + - name: Div64 + description: SYSCLK is divided by 64 + value: 12 + - name: Div128 + description: SYSCLK is divided by 128 + value: 13 + - name: Div256 + description: SYSCLK is divided by 256 + value: 14 + - name: Div512 + description: SYSCLK is divided by 512 + value: 15 enum/LSEDRV: bit_size: 2 variants: - - name: Low - description: Low driving capability - value: 0 - - name: MediumLow - description: Medium low driving capability - value: 1 - - name: MediumHigh - description: Medium high driving capability - value: 2 - - name: High - description: High driving capability - value: 3 + - name: Low + description: Low driving capability + value: 0 + - name: MediumLow + description: Medium low driving capability + value: 1 + - name: MediumHigh + description: Medium high driving capability + value: 2 + - name: High + description: High driving capability + value: 3 enum/MCOPRE: bit_size: 3 variants: - - name: Div1 - description: MCO1 not divided - value: 0 - - name: Div2 - description: MCO clock is divided by 2 - value: 1 - - name: Div4 - description: MCO clock is divided by 4 - value: 2 - - name: Div8 - description: MCO clock is divided by 8 - value: 3 - - name: Div16 - description: MCO clock is divided divided by 16 - value: 4 + - name: Div1 + description: MCO1 not divided + value: 0 + - name: Div2 + description: MCO clock is divided by 2 + value: 1 + - name: Div4 + description: MCO clock is divided by 4 + value: 2 + - name: Div8 + description: MCO clock is divided by 8 + value: 3 + - name: Div16 + description: MCO clock is divided divided by 16 + value: 4 enum/MCOSEL: bit_size: 4 variants: - - name: NoClock - description: "No clock, MCO output disabled" - value: 0 - - name: SYSCLK - description: SYSCLK selected as MCO source - value: 1 - - name: HSI16 - description: HSI16 selected as MCO source - value: 3 - - name: HSE - description: HSE selected as MCO source - value: 4 - - name: PLLCLK - description: Main PLLCLK selected as MCO source - value: 5 - - name: LSI - description: LSI selected as MCO source - value: 6 - - name: LSE - description: LSE selected as MCO source - value: 7 - - name: HSI48 - description: HSI48 selected as MCO source - value: 8 + - name: NoClock + description: No clock, MCO output disabled + value: 0 + - name: SYSCLK + description: SYSCLK selected as MCO source + value: 1 + - name: HSI16 + description: HSI16 selected as MCO source + value: 3 + - name: HSE + description: HSE selected as MCO source + value: 4 + - name: PLLCLK + description: Main PLLCLK selected as MCO source + value: 5 + - name: LSI + description: LSI selected as MCO source + value: 6 + - name: LSE + description: LSE selected as MCO source + value: 7 + - name: HSI48 + description: HSI48 selected as MCO source + value: 8 enum/PLLSRC: bit_size: 2 variants: - - name: NoClock - description: No clock selected as PLL entry clock source - value: 0 - - name: HSI16 - description: HSI16 selected as PLL entry clock source - value: 2 - - name: HSE - description: HSE selected as PLL entry clock source - value: 3 + - name: NoClock + description: No clock selected as PLL entry clock source + value: 0 + - name: HSI16 + description: HSI16 selected as PLL entry clock source + value: 2 + - name: HSE + description: HSE selected as PLL entry clock source + value: 3 enum/PPRE: bit_size: 4 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK is divided by 2 - value: 4 - - name: Div4 - description: HCLK is divided by 4 - value: 5 - - name: Div8 - description: HCLK is divided by 8 - value: 6 - - name: Div16 - description: HCLK is divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK is divided by 2 + value: 4 + - name: Div4 + description: HCLK is divided by 4 + value: 5 + - name: Div8 + description: HCLK is divided by 8 + value: 6 + - name: Div16 + description: HCLK is divided by 16 + value: 7 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock used as RTC clock - value: 0 - - name: LSE - description: LSE used as RTC clock - value: 1 - - name: LSI - description: LSI used as RTC clock - value: 2 - - name: HSE_Div32 - description: HSE divided by 32 used as RTC clock - value: 3 + - name: NoClock + description: No clock used as RTC clock + value: 0 + - name: LSE + description: LSE used as RTC clock + value: 1 + - name: LSI + description: LSI used as RTC clock + value: 2 + - name: HSE_Div32 + description: HSE divided by 32 used as RTC clock + value: 3 enum/SW: bit_size: 2 variants: - - name: HSI16 - description: HSI16 selected as system clock - value: 1 - - name: HSE - description: HSE selected as system clock - value: 2 - - name: PLLRCLK - description: PLLRCLK selected as system clock - value: 3 + - name: HSI16 + description: HSI16 selected as system clock + value: 1 + - name: HSE + description: HSE selected as system clock + value: 2 + - name: PLLRCLK + description: PLLRCLK selected as system clock + value: 3 diff --git a/data/registers/rcc_h5.yaml b/data/registers/rcc_h5.yaml index 8fac1eb..41ee10e 100644 --- a/data/registers/rcc_h5.yaml +++ b/data/registers/rcc_h5.yaml @@ -1,2757 +1,2756 @@ ---- block/RCC: description: Reset and clock controller items: - - name: CR - description: RCC clock control register - byte_offset: 0 - fieldset: CR - - name: HSICFGR - description: RCC HSI calibration register - byte_offset: 16 - fieldset: HSICFGR - - name: CRRCR - description: RCC clock recovery RC register - byte_offset: 20 - fieldset: CRRCR - - name: CSICFGR - description: RCC CSI calibration register - byte_offset: 24 - fieldset: CSICFGR - - name: CFGR - description: RCC clock configuration register - byte_offset: 28 - fieldset: CFGR - - name: CFGR2 - description: RCC CPU domain clock configuration register 2 - byte_offset: 32 - fieldset: CFGR2 - - name: PLLCFGR - description: RCC PLL clock source selection register - array: - len: 3 - stride: 4 - byte_offset: 40 - fieldset: PLLCFGR - - name: PLLDIVR - description: RCC PLL1 dividers register - array: - len: 3 - stride: 8 - byte_offset: 52 - fieldset: PLLDIVR - - name: PLLFRACR - description: RCC PLL1 fractional divider register - array: - len: 3 - stride: 8 - byte_offset: 56 - fieldset: PLLFRACR - - name: CIER - description: RCC clock source interrupt enable register - byte_offset: 80 - fieldset: CIER - - name: CIFR - description: RCC clock source interrupt flag register - byte_offset: 84 - fieldset: CIFR - - name: CICR - description: RCC clock source interrupt clear register - byte_offset: 88 - fieldset: CICR - - name: AHB1RSTR - description: RCC AHB1 reset register - byte_offset: 96 - fieldset: AHB1RSTR - - name: AHB2RSTR - description: RCC AHB2 peripheral reset register - byte_offset: 100 - fieldset: AHB2RSTR - - name: AHB4RSTR - description: RCC AHB4 peripheral reset register - byte_offset: 108 - fieldset: AHB4RSTR - - name: APB1LRSTR - description: RCC APB1 peripheral low reset register - byte_offset: 116 - fieldset: APB1LRSTR - - name: APB1HRSTR - description: RCC APB1 peripheral high reset register - byte_offset: 120 - fieldset: APB1HRSTR - - name: APB2RSTR - description: RCC APB2 peripheral reset register - byte_offset: 124 - fieldset: APB2RSTR - - name: APB3RSTR - description: RCC APB3 peripheral reset register - byte_offset: 128 - fieldset: APB3RSTR - - name: AHB1ENR - description: RCC AHB1 peripherals clock register - byte_offset: 136 - fieldset: AHB1ENR - - name: AHB2ENR - description: RCC AHB2 peripheral clock register - byte_offset: 140 - fieldset: AHB2ENR - - name: AHB4ENR - description: RCC AHB4 peripheral clock register - byte_offset: 148 - fieldset: AHB4ENR - - name: APB1LENR - description: RCC APB1 peripheral clock register - byte_offset: 156 - fieldset: APB1LENR - - name: APB1HENR - description: RCC APB1 peripheral clock register - byte_offset: 160 - fieldset: APB1HENR - - name: APB2ENR - description: RCC APB2 peripheral clock register - byte_offset: 164 - fieldset: APB2ENR - - name: APB3ENR - description: RCC APB3 peripheral clock register - byte_offset: 168 - fieldset: APB3ENR - - name: AHB1LPENR - description: RCC AHB1 sleep clock register - byte_offset: 176 - fieldset: AHB1LPENR - - name: AHB2LPENR - description: RCC AHB2 sleep clock register - byte_offset: 180 - fieldset: AHB2LPENR - - name: AHB4LPENR - description: RCC AHB4 sleep clock register - byte_offset: 188 - fieldset: AHB4LPENR - - name: APB1LLPENR - description: RCC APB1 sleep clock register - byte_offset: 196 - fieldset: APB1LLPENR - - name: APB1HLPENR - description: RCC APB1 sleep clock register - byte_offset: 200 - fieldset: APB1HLPENR - - name: APB2LPENR - description: RCC APB2 sleep clock register - byte_offset: 204 - fieldset: APB2LPENR - - name: APB3LPENR - description: RCC APB3 sleep clock register - byte_offset: 208 - fieldset: APB3LPENR - - name: CCIPR1 - description: RCC kernel clock configuration register - byte_offset: 216 - fieldset: CCIPR1 - - name: CCIPR2 - description: RCC kernel clock configuration register - byte_offset: 220 - fieldset: CCIPR2 - - name: CCIPR3 - description: RCC kernel clock configuration register - byte_offset: 224 - fieldset: CCIPR3 - - name: CCIPR4 - description: RCC kernel clock configuration register - byte_offset: 228 - fieldset: CCIPR4 - - name: CCIPR5 - description: RCC kernel clock configuration register - byte_offset: 232 - fieldset: CCIPR5 - - name: BDCR - description: RCC Backup domain control register - byte_offset: 240 - fieldset: BDCR - - name: RSR - description: RCC reset status register - byte_offset: 244 - fieldset: RSR - - name: SECCFGR - description: RCC secure configuration register - byte_offset: 272 - fieldset: SECCFGR - - name: PRIVCFGR - description: RCC privilege configuration register - byte_offset: 276 - fieldset: PRIVCFGR + - name: CR + description: RCC clock control register + byte_offset: 0 + fieldset: CR + - name: HSICFGR + description: RCC HSI calibration register + byte_offset: 16 + fieldset: HSICFGR + - name: CRRCR + description: RCC clock recovery RC register + byte_offset: 20 + fieldset: CRRCR + - name: CSICFGR + description: RCC CSI calibration register + byte_offset: 24 + fieldset: CSICFGR + - name: CFGR + description: RCC clock configuration register + byte_offset: 28 + fieldset: CFGR + - name: CFGR2 + description: RCC CPU domain clock configuration register 2 + byte_offset: 32 + fieldset: CFGR2 + - name: PLLCFGR + description: RCC PLL clock source selection register + array: + len: 3 + stride: 4 + byte_offset: 40 + fieldset: PLLCFGR + - name: PLLDIVR + description: RCC PLL1 dividers register + array: + len: 3 + stride: 8 + byte_offset: 52 + fieldset: PLLDIVR + - name: PLLFRACR + description: RCC PLL1 fractional divider register + array: + len: 3 + stride: 8 + byte_offset: 56 + fieldset: PLLFRACR + - name: CIER + description: RCC clock source interrupt enable register + byte_offset: 80 + fieldset: CIER + - name: CIFR + description: RCC clock source interrupt flag register + byte_offset: 84 + fieldset: CIFR + - name: CICR + description: RCC clock source interrupt clear register + byte_offset: 88 + fieldset: CICR + - name: AHB1RSTR + description: RCC AHB1 reset register + byte_offset: 96 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: RCC AHB2 peripheral reset register + byte_offset: 100 + fieldset: AHB2RSTR + - name: AHB4RSTR + description: RCC AHB4 peripheral reset register + byte_offset: 108 + fieldset: AHB4RSTR + - name: APB1LRSTR + description: RCC APB1 peripheral low reset register + byte_offset: 116 + fieldset: APB1LRSTR + - name: APB1HRSTR + description: RCC APB1 peripheral high reset register + byte_offset: 120 + fieldset: APB1HRSTR + - name: APB2RSTR + description: RCC APB2 peripheral reset register + byte_offset: 124 + fieldset: APB2RSTR + - name: APB3RSTR + description: RCC APB3 peripheral reset register + byte_offset: 128 + fieldset: APB3RSTR + - name: AHB1ENR + description: RCC AHB1 peripherals clock register + byte_offset: 136 + fieldset: AHB1ENR + - name: AHB2ENR + description: RCC AHB2 peripheral clock register + byte_offset: 140 + fieldset: AHB2ENR + - name: AHB4ENR + description: RCC AHB4 peripheral clock register + byte_offset: 148 + fieldset: AHB4ENR + - name: APB1LENR + description: RCC APB1 peripheral clock register + byte_offset: 156 + fieldset: APB1LENR + - name: APB1HENR + description: RCC APB1 peripheral clock register + byte_offset: 160 + fieldset: APB1HENR + - name: APB2ENR + description: RCC APB2 peripheral clock register + byte_offset: 164 + fieldset: APB2ENR + - name: APB3ENR + description: RCC APB3 peripheral clock register + byte_offset: 168 + fieldset: APB3ENR + - name: AHB1LPENR + description: RCC AHB1 sleep clock register + byte_offset: 176 + fieldset: AHB1LPENR + - name: AHB2LPENR + description: RCC AHB2 sleep clock register + byte_offset: 180 + fieldset: AHB2LPENR + - name: AHB4LPENR + description: RCC AHB4 sleep clock register + byte_offset: 188 + fieldset: AHB4LPENR + - name: APB1LLPENR + description: RCC APB1 sleep clock register + byte_offset: 196 + fieldset: APB1LLPENR + - name: APB1HLPENR + description: RCC APB1 sleep clock register + byte_offset: 200 + fieldset: APB1HLPENR + - name: APB2LPENR + description: RCC APB2 sleep clock register + byte_offset: 204 + fieldset: APB2LPENR + - name: APB3LPENR + description: RCC APB3 sleep clock register + byte_offset: 208 + fieldset: APB3LPENR + - name: CCIPR1 + description: RCC kernel clock configuration register + byte_offset: 216 + fieldset: CCIPR1 + - name: CCIPR2 + description: RCC kernel clock configuration register + byte_offset: 220 + fieldset: CCIPR2 + - name: CCIPR3 + description: RCC kernel clock configuration register + byte_offset: 224 + fieldset: CCIPR3 + - name: CCIPR4 + description: RCC kernel clock configuration register + byte_offset: 228 + fieldset: CCIPR4 + - name: CCIPR5 + description: RCC kernel clock configuration register + byte_offset: 232 + fieldset: CCIPR5 + - name: BDCR + description: RCC Backup domain control register + byte_offset: 240 + fieldset: BDCR + - name: RSR + description: RCC reset status register + byte_offset: 244 + fieldset: RSR + - name: SECCFGR + description: RCC secure configuration register + byte_offset: 272 + fieldset: SECCFGR + - name: PRIVCFGR + description: RCC privilege configuration register + byte_offset: 276 + fieldset: PRIVCFGR fieldset/AHB1ENR: description: RCC AHB1 peripherals clock register fields: - - name: GPDMA1EN - description: "GPDMA1 clock enable\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: GPDMA2EN - description: "GPDMA2 clock enable\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: FLITFEN - description: "Flash interface clock enable\r Set and reset by software." - bit_offset: 8 - bit_size: 1 - - name: CRCEN - description: "CRC clock enable\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: CORDICEN - description: "CORDIC clock enable\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: FMACEN - description: "FMAC clock enable\r Set and reset by software." - bit_offset: 15 - bit_size: 1 - - name: RAMCFGEN - description: "RAMCFG clock enable\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: ETHEN - description: "ETH clock enable\r Set and reset by software" - bit_offset: 19 - bit_size: 1 - - name: ETHTXEN - description: "ETHTX clock enable\r Set and reset by software" - bit_offset: 20 - bit_size: 1 - - name: ETHRXEN - description: "ETHRX clock enable\r Set and reset by software" - bit_offset: 21 - bit_size: 1 - - name: TZSC1EN - description: "TZSC1 clock enable\r Set and reset by software" - bit_offset: 24 - bit_size: 1 - - name: BKPRAMEN - description: "BKPRAM clock enable\r Set and reset by software" - bit_offset: 28 - bit_size: 1 - - name: DCACHEEN - description: "DCACHE clock enable\r Set and reset by software" - bit_offset: 30 - bit_size: 1 - - name: SRAM1EN - description: "SRAM1 clock enable\r Set and reset by software." - bit_offset: 31 - bit_size: 1 + - name: GPDMA1EN + description: "GPDMA1 clock enable\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPDMA2EN + description: "GPDMA2 clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: FLITFEN + description: "Flash interface clock enable\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: "CRC clock enable\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: CORDICEN + description: "CORDIC clock enable\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: FMACEN + description: "FMAC clock enable\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: RAMCFGEN + description: "RAMCFG clock enable\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: ETHEN + description: "ETH clock enable\r Set and reset by software" + bit_offset: 19 + bit_size: 1 + - name: ETHTXEN + description: "ETHTX clock enable\r Set and reset by software" + bit_offset: 20 + bit_size: 1 + - name: ETHRXEN + description: "ETHRX clock enable\r Set and reset by software" + bit_offset: 21 + bit_size: 1 + - name: TZSC1EN + description: "TZSC1 clock enable\r Set and reset by software" + bit_offset: 24 + bit_size: 1 + - name: BKPRAMEN + description: "BKPRAM clock enable\r Set and reset by software" + bit_offset: 28 + bit_size: 1 + - name: DCACHEEN + description: "DCACHE clock enable\r Set and reset by software" + bit_offset: 30 + bit_size: 1 + - name: SRAM1EN + description: "SRAM1 clock enable\r Set and reset by software." + bit_offset: 31 + bit_size: 1 fieldset/AHB1LPENR: description: RCC AHB1 sleep clock register fields: - - name: GPDMA1LPEN - description: "GPDMA1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: GPDMA2LPEN - description: "GPDMA2 clock enable during sleep mode\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: FLITFLPEN - description: "Flash interface (FLITF) clock enable during sleep mode\r Set and reset by software." - bit_offset: 8 - bit_size: 1 - - name: CRCLPEN - description: "CRC clock enable during sleep mode\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: CORDICLPEN - description: "CORDIC clock enable during sleep mode\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: FMACLPEN - description: "FMAC clock enable during sleep mode\r Set and reset by software." - bit_offset: 15 - bit_size: 1 - - name: RAMCFGLPEN - description: "RAMCFG clock enable during sleep mode\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: ETHLPEN - description: "ETH clock enable during Sleep mode\r Set and reset by software" - bit_offset: 19 - bit_size: 1 - - name: ETHTXLPEN - description: "ETHTX clock enable during sleep mode\r Set and reset by software" - bit_offset: 20 - bit_size: 1 - - name: ETHRXLPEN - description: "ETHRX clock enable during sleep mode\r Set and reset by software" - bit_offset: 21 - bit_size: 1 - - name: TZSC1LPEN - description: "TZSC1 clock enable during sleep mode\r Set and reset by software" - bit_offset: 24 - bit_size: 1 - - name: BKPRAMLPEN - description: "BKPRAM clock enable during sleep mode\r Set and reset by software" - bit_offset: 28 - bit_size: 1 - - name: ICACHELPEN - description: "ICACHE clock enable during sleep mode\r Set and reset by software" - bit_offset: 29 - bit_size: 1 - - name: DCACHELPEN - description: "DCACHE clock enable during sleep mode\r Set and reset by software" - bit_offset: 30 - bit_size: 1 - - name: SRAM1LPEN - description: "SRAM1 clock enable during sleep mode\r Set and reset by software" - bit_offset: 31 - bit_size: 1 + - name: GPDMA1LPEN + description: "GPDMA1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPDMA2LPEN + description: "GPDMA2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: FLITFLPEN + description: "Flash interface (FLITF) clock enable during sleep mode\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: CRCLPEN + description: "CRC clock enable during sleep mode\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: CORDICLPEN + description: "CORDIC clock enable during sleep mode\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: FMACLPEN + description: "FMAC clock enable during sleep mode\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: RAMCFGLPEN + description: "RAMCFG clock enable during sleep mode\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: ETHLPEN + description: "ETH clock enable during Sleep mode\r Set and reset by software" + bit_offset: 19 + bit_size: 1 + - name: ETHTXLPEN + description: "ETHTX clock enable during sleep mode\r Set and reset by software" + bit_offset: 20 + bit_size: 1 + - name: ETHRXLPEN + description: "ETHRX clock enable during sleep mode\r Set and reset by software" + bit_offset: 21 + bit_size: 1 + - name: TZSC1LPEN + description: "TZSC1 clock enable during sleep mode\r Set and reset by software" + bit_offset: 24 + bit_size: 1 + - name: BKPRAMLPEN + description: "BKPRAM clock enable during sleep mode\r Set and reset by software" + bit_offset: 28 + bit_size: 1 + - name: ICACHELPEN + description: "ICACHE clock enable during sleep mode\r Set and reset by software" + bit_offset: 29 + bit_size: 1 + - name: DCACHELPEN + description: "DCACHE clock enable during sleep mode\r Set and reset by software" + bit_offset: 30 + bit_size: 1 + - name: SRAM1LPEN + description: "SRAM1 clock enable during sleep mode\r Set and reset by software" + bit_offset: 31 + bit_size: 1 fieldset/AHB1RSTR: description: RCC AHB1 reset register fields: - - name: GPDMA1RST - description: "GPDMA1 block reset\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: GPDMA2RST - description: "GPDMA2 block reset\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: CRCRST - description: CRC block reset Set and reset by software. - bit_offset: 12 - bit_size: 1 - - name: CORDICRST - description: "CORDIC block reset\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: FMACRST - description: "FMAC block reset\r Set and reset by software." - bit_offset: 15 - bit_size: 1 - - name: RAMCFGRST - description: "RAMCFG block reset\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: ETHRST - description: "ETHRST block reset\r Set and reset by software" - bit_offset: 19 - bit_size: 1 - - name: TZSC1RST - description: "TZSC1 reset\r Set and reset by software" - bit_offset: 24 - bit_size: 1 + - name: GPDMA1RST + description: "GPDMA1 block reset\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPDMA2RST + description: "GPDMA2 block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: CRCRST + description: CRC block reset Set and reset by software. + bit_offset: 12 + bit_size: 1 + - name: CORDICRST + description: "CORDIC block reset\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: FMACRST + description: "FMAC block reset\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: RAMCFGRST + description: "RAMCFG block reset\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: ETHRST + description: "ETHRST block reset\r Set and reset by software" + bit_offset: 19 + bit_size: 1 + - name: TZSC1RST + description: "TZSC1 reset\r Set and reset by software" + bit_offset: 24 + bit_size: 1 fieldset/AHB2ENR: description: RCC AHB2 peripheral clock register fields: - - name: GPIOAEN - description: "GPIOA clock enable\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: "GPIOB clock enable\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: "GPIOC clock enable\r Set and reset by software." - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: "GPIOD clock enable\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: "GPIOE clock enable\r Set and reset by software." - bit_offset: 4 - bit_size: 1 - - name: GPIOFEN - description: "GPIOF clock enable\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: GPIOGEN - description: "GPIOG clock enable\r Set and reset by software." - bit_offset: 6 - bit_size: 1 - - name: GPIOHEN - description: "GPIOH clock enable\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - - name: GPIOIEN - description: "GPIOI clock enable\r Set and reset by software." - bit_offset: 8 - bit_size: 1 - - name: ADC12EN - description: "ADC1 and 2 peripherals clock enabled\r Set and reset by software." - bit_offset: 10 - bit_size: 1 - - name: DAC12EN - description: "DAC clock enable\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: DCMI_PSSIEN - description: "digital camera interface clock enable (DCMI or PSSI depending which interface is active)\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: AESEN - description: "AES clock enable\r Set and reset by software." - bit_offset: 16 - bit_size: 1 - - name: HASHEN - description: "HASH clock enable\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: RNGEN - description: "RNG clock enable\r Set and reset by software." - bit_offset: 18 - bit_size: 1 - - name: PKAEN - description: "PKA clock enable\r Set and reset by software." - bit_offset: 19 - bit_size: 1 - - name: SAESEN - description: "SAES clock enable\r Set and reset by software." - bit_offset: 20 - bit_size: 1 - - name: SRAM3EN - description: "SRAM3 clock enable\r Set and reset by software." - bit_offset: 30 - bit_size: 1 - - name: SRAM2EN - description: "SRAM2 clock enable\r Set and reset by software." - bit_offset: 31 - bit_size: 1 + - name: GPIOAEN + description: "GPIOA clock enable\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: "GPIOB clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: "GPIOC clock enable\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: "GPIOD clock enable\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: "GPIOE clock enable\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: "GPIOF clock enable\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: "GPIOG clock enable\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: "GPIOH clock enable\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: GPIOIEN + description: "GPIOI clock enable\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: ADC12EN + description: "ADC1 and 2 peripherals clock enabled\r Set and reset by software." + bit_offset: 10 + bit_size: 1 + - name: DAC12EN + description: "DAC clock enable\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: DCMI_PSSIEN + description: "digital camera interface clock enable (DCMI or PSSI depending which interface is active)\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: AESEN + description: "AES clock enable\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: HASHEN + description: "HASH clock enable\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: "RNG clock enable\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: PKAEN + description: "PKA clock enable\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: SAESEN + description: "SAES clock enable\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: SRAM3EN + description: "SRAM3 clock enable\r Set and reset by software." + bit_offset: 30 + bit_size: 1 + - name: SRAM2EN + description: "SRAM2 clock enable\r Set and reset by software." + bit_offset: 31 + bit_size: 1 fieldset/AHB2LPENR: description: RCC AHB2 sleep clock register fields: - - name: GPIOALPEN - description: "GPIOA clock enable during sleep mode\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: GPIOBLPEN - description: "GPIOB clock enable during sleep mode\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: GPIOCLPEN - description: "GPIOC clock enable during sleep mode\r Set and reset by software." - bit_offset: 2 - bit_size: 1 - - name: GPIODLPEN - description: "GPIOD clock enable during sleep mode\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - - name: GPIOELPEN - description: "GPIOE clock enable during sleep mode\r Set and reset by software." - bit_offset: 4 - bit_size: 1 - - name: GPIOFLPEN - description: "GPIOF clock enable during sleep mode\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: GPIOGLPEN - description: "GPIOG clock enable during sleep mode\r Set and reset by software." - bit_offset: 6 - bit_size: 1 - - name: GPIOHLPEN - description: "GPIOH clock enable during sleep mode\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - - name: GPIOILPEN - description: "GPIOI clock enable during sleep mode\r Set and reset by software." - bit_offset: 8 - bit_size: 1 - - name: ADC12LPEN - description: "ADC1 and 2 peripherals clock enable during sleep mode\r Set and reset by software." - bit_offset: 10 - bit_size: 1 - - name: DAC12LPEN - description: "DAC clock enable during sleep mode\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: DCMI_PSSILPEN - description: "digital camera interface clock enable during sleep mode (DCMI or PSSI depending which interface is active)\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: AESLPEN - description: "AES clock enable during sleep mode\r Set and reset by software." - bit_offset: 16 - bit_size: 1 - - name: HASHLPEN - description: "HASH clock enable during sleep mode\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: RNGLPEN - description: "RNG clock enable during sleep mode\r Set and reset by software." - bit_offset: 18 - bit_size: 1 - - name: PKALPEN - description: "PKA clock enable during sleep mode\r Set and reset by software." - bit_offset: 19 - bit_size: 1 - - name: SAESLPEN - description: "SAES clock enable during sleep mode\r Set and reset by software." - bit_offset: 20 - bit_size: 1 - - name: SRAM2LPEN - description: "SRAM2 clock enable during sleep mode\r Set and reset by software." - bit_offset: 30 - bit_size: 1 - - name: SRAM3LPEN - description: "SRAM3 clock enable during sleep mode\r Set and reset by software." - bit_offset: 31 - bit_size: 1 + - name: GPIOALPEN + description: "GPIOA clock enable during sleep mode\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: "GPIOB clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: "GPIOC clock enable during sleep mode\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODLPEN + description: "GPIOD clock enable during sleep mode\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOELPEN + description: "GPIOE clock enable during sleep mode\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: GPIOFLPEN + description: "GPIOF clock enable during sleep mode\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: GPIOGLPEN + description: "GPIOG clock enable during sleep mode\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: GPIOHLPEN + description: "GPIOH clock enable during sleep mode\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: GPIOILPEN + description: "GPIOI clock enable during sleep mode\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: ADC12LPEN + description: "ADC1 and 2 peripherals clock enable during sleep mode\r Set and reset by software." + bit_offset: 10 + bit_size: 1 + - name: DAC12LPEN + description: "DAC clock enable during sleep mode\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: DCMI_PSSILPEN + description: "digital camera interface clock enable during sleep mode (DCMI or PSSI depending which interface is active)\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: AESLPEN + description: "AES clock enable during sleep mode\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: HASHLPEN + description: "HASH clock enable during sleep mode\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: RNGLPEN + description: "RNG clock enable during sleep mode\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: PKALPEN + description: "PKA clock enable during sleep mode\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: SAESLPEN + description: "SAES clock enable during sleep mode\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: SRAM2LPEN + description: "SRAM2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 30 + bit_size: 1 + - name: SRAM3LPEN + description: "SRAM3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 31 + bit_size: 1 fieldset/AHB2RSTR: description: RCC AHB2 peripheral reset register fields: - - name: GPIOARST - description: "GPIOA block reset\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: "GPIOB block reset\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: "GPIOC block reset\r Set and reset by software." - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: "GPIOD block reset\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - - name: GPIOERST - description: "GPIOE block reset\r Set and reset by software." - bit_offset: 4 - bit_size: 1 - - name: GPIOFRST - description: "GPIOF block reset\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: GPIOGRST - description: "GPIOG block reset\r Set and reset by software." - bit_offset: 6 - bit_size: 1 - - name: GPIOHRST - description: "GPIOH block reset\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - - name: GPIOIRST - description: "GPIOI block reset\r Set and reset by software." - bit_offset: 8 - bit_size: 1 - - name: ADC12RST - description: "ADC1 and 2 blocks reset\r Set and reset by software." - bit_offset: 10 - bit_size: 1 - - name: DAC12RST - description: "DAC block reset\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: DCMI_PSSIRST - description: "digital camera interface block reset (DCMI or PSSI depending which interface is active)\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: AESRST - description: "AES block reset\r Set and reset by software." - bit_offset: 16 - bit_size: 1 - - name: HASHRST - description: "HASH block reset\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: RNGRST - description: "RNG block reset\r Set and reset by software." - bit_offset: 18 - bit_size: 1 - - name: PKARST - description: "PKA block reset\r Set and reset by software." - bit_offset: 19 - bit_size: 1 - - name: SAESRST - description: "SAES block reset\r Set and reset by software." - bit_offset: 20 - bit_size: 1 + - name: GPIOARST + description: "GPIOA block reset\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: "GPIOB block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: "GPIOC block reset\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: "GPIOD block reset\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: "GPIOE block reset\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: "GPIOF block reset\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: "GPIOG block reset\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: GPIOHRST + description: "GPIOH block reset\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: GPIOIRST + description: "GPIOI block reset\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: ADC12RST + description: "ADC1 and 2 blocks reset\r Set and reset by software." + bit_offset: 10 + bit_size: 1 + - name: DAC12RST + description: "DAC block reset\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: DCMI_PSSIRST + description: "digital camera interface block reset (DCMI or PSSI depending which interface is active)\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: AESRST + description: "AES block reset\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: HASHRST + description: "HASH block reset\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: RNGRST + description: "RNG block reset\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: PKARST + description: "PKA block reset\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: SAESRST + description: "SAES block reset\r Set and reset by software." + bit_offset: 20 + bit_size: 1 fieldset/AHB4ENR: description: RCC AHB4 peripheral clock register fields: - - name: OTFDEC1EN - description: "OTFDEC1 clock enable\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - - name: SDMMC1EN - description: SDMMC1 and SDMMC1 delay peripheral clock enable reset - bit_offset: 11 - bit_size: 1 - - name: SDMMC2EN - description: "SDMMC2 and SDMMC2 delay peripheral clock enabled\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: FMCEN - description: "FMC clock enable\r Set and reset by software." - bit_offset: 16 - bit_size: 1 - - name: OCTOSPI1EN - description: "OCTOSPI1 clock enable\r Set and reset by software." - bit_offset: 20 - bit_size: 1 + - name: OTFDEC1EN + description: "OTFDEC1 clock enable\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: SDMMC1EN + description: SDMMC1 and SDMMC1 delay peripheral clock enable reset + bit_offset: 11 + bit_size: 1 + - name: SDMMC2EN + description: "SDMMC2 and SDMMC2 delay peripheral clock enabled\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: FMCEN + description: "FMC clock enable\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: OCTOSPI1EN + description: "OCTOSPI1 clock enable\r Set and reset by software." + bit_offset: 20 + bit_size: 1 fieldset/AHB4LPENR: description: RCC AHB4 sleep clock register fields: - - name: OTFDEC1LPEN - description: "OTFDEC1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - - name: SDMMC1LPEN - description: "SDMMC1 and SDMMC1 delay peripheral clock enable during sleep mode\r Set and reset by software" - bit_offset: 11 - bit_size: 1 - - name: SDMMC2LPEN - description: "SDMMC2 and SDMMC2 delay peripheral clock enable during sleep mode\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: FMCLPEN - description: "FMC clock enable during sleep mode\r Set and reset by software." - bit_offset: 16 - bit_size: 1 - - name: OCTOSPI1LPEN - description: "OCTOSPI1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 20 - bit_size: 1 + - name: OTFDEC1LPEN + description: "OTFDEC1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: SDMMC1LPEN + description: "SDMMC1 and SDMMC1 delay peripheral clock enable during sleep mode\r Set and reset by software" + bit_offset: 11 + bit_size: 1 + - name: SDMMC2LPEN + description: "SDMMC2 and SDMMC2 delay peripheral clock enable during sleep mode\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: FMCLPEN + description: "FMC clock enable during sleep mode\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: OCTOSPI1LPEN + description: "OCTOSPI1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 20 + bit_size: 1 fieldset/AHB4RSTR: description: RCC AHB4 peripheral reset register fields: - - name: OTFDEC1RST - description: "OTFDEC1 block reset\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - - name: SDMMC1RST - description: "SDMMC1 and SDMMC1 delay blocks reset\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: SDMMC2RST - description: "SDMMC2 and SDMMC2 delay blocks reset\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: FMCRST - description: "FMC block reset\r Set and reset by software." - bit_offset: 16 - bit_size: 1 - - name: OCTOSPI1RST - description: "OCTOSPI1 block reset\r Set and reset by software." - bit_offset: 20 - bit_size: 1 + - name: OTFDEC1RST + description: "OTFDEC1 block reset\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: SDMMC1RST + description: "SDMMC1 and SDMMC1 delay blocks reset\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SDMMC2RST + description: "SDMMC2 and SDMMC2 delay blocks reset\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: FMCRST + description: "FMC block reset\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: OCTOSPI1RST + description: "OCTOSPI1 block reset\r Set and reset by software." + bit_offset: 20 + bit_size: 1 fieldset/APB1HENR: description: RCC APB1 peripheral clock register fields: - - name: UART9EN - description: "UART9 clock enable\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: UART12EN - description: "UART12 clock enable\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: DTSEN - description: "DTS clock enable\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - - name: LPTIM2EN - description: "LPTIM2 clock enable\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: FDCAN12EN - description: "FDCAN1 and FDCAN2 peripheral clock enable\r Set and reset by software." - bit_offset: 9 - bit_size: 1 - - name: UCPDEN - description: "UCPD clock enable\r Set and reset by software." - bit_offset: 23 - bit_size: 1 + - name: UART9EN + description: "UART9 clock enable\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: UART12EN + description: "UART12 clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: DTSEN + description: "DTS clock enable\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: LPTIM2EN + description: "LPTIM2 clock enable\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: FDCAN12EN + description: "FDCAN1 and FDCAN2 peripheral clock enable\r Set and reset by software." + bit_offset: 9 + bit_size: 1 + - name: UCPDEN + description: "UCPD clock enable\r Set and reset by software." + bit_offset: 23 + bit_size: 1 fieldset/APB1HLPENR: description: RCC APB1 sleep clock register fields: - - name: UART9LPEN - description: "UART9 clock enable during sleep mode\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: UART12LPEN - description: "UART12 clock enable during sleep mode\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: DTSLPEN - description: "DTS clock enable during sleep mode\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - - name: LPTIM2LPEN - description: "LPTIM2 clock enable during sleep mode\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: FDCAN12LPEN - description: "FDCAN1 and FDCAN2 peripheral clock enable during sleep mode\r Set and reset by software." - bit_offset: 9 - bit_size: 1 - - name: UCPDLPEN - description: "UCPD clock enable during sleep mode\r Set and reset by software." - bit_offset: 23 - bit_size: 1 + - name: UART9LPEN + description: "UART9 clock enable during sleep mode\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: UART12LPEN + description: "UART12 clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: DTSLPEN + description: "DTS clock enable during sleep mode\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: LPTIM2LPEN + description: "LPTIM2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: FDCAN12LPEN + description: "FDCAN1 and FDCAN2 peripheral clock enable during sleep mode\r Set and reset by software." + bit_offset: 9 + bit_size: 1 + - name: UCPDLPEN + description: "UCPD clock enable during sleep mode\r Set and reset by software." + bit_offset: 23 + bit_size: 1 fieldset/APB1HRSTR: description: RCC APB1 peripheral high reset register fields: - - name: UART9RST - description: "UART9 block reset\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: UART12RST - description: "UART12 block reset\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: DTSRST - description: "DTS block reset\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - - name: LPTIM2RST - description: "LPTIM2 block reset\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: FDCAN12RST - description: "FDCAN1 and FDCAN2 blocks reset\r Set and reset by software." - bit_offset: 9 - bit_size: 1 - - name: UCPDRST - description: "UCPD block reset\r Set and reset by software." - bit_offset: 23 - bit_size: 1 + - name: UART9RST + description: "UART9 block reset\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: UART12RST + description: "UART12 block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: DTSRST + description: "DTS block reset\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: LPTIM2RST + description: "LPTIM2 block reset\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: FDCAN12RST + description: "FDCAN1 and FDCAN2 blocks reset\r Set and reset by software." + bit_offset: 9 + bit_size: 1 + - name: UCPDRST + description: "UCPD block reset\r Set and reset by software." + bit_offset: 23 + bit_size: 1 fieldset/APB1LENR: description: RCC APB1 peripheral clock register fields: - - name: TIM2EN - description: "TIM2 clock enable\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: "TIM3 clock enable\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: "TIM4 clock enable\r Set and reset by software." - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: "TIM5 clock enable\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: "TIM6 clock enable\r Set and reset by software." - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: "TIM7 clock enable\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: TIM12EN - description: "TIM12 clock enable\r Set and reset by software." - bit_offset: 6 - bit_size: 1 - - name: TIM13EN - description: "TIM13 clock enable\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - - name: TIM14EN - description: "TIM14 clock enable\r Set and reset by software." - bit_offset: 8 - bit_size: 1 - - name: WWDGEN - description: "WWDG clock enable\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: "SPI2 clock enable\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: "SPI3 clock enable\r Set and reset by software." - bit_offset: 15 - bit_size: 1 - - name: USART2EN - description: "USART2 clock enable\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: "USART3 clock enable\r Set and reset by software." - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: "UART4 clock enable\r Set and reset by software." - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: "UART5 clock enable\r Set and reset by software." - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: "I2C1 clock enable\r Set and reset by software." - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: "I2C2 clock enable\r Set and reset by software." - bit_offset: 22 - bit_size: 1 - - name: I3C1EN - description: "I3C1 clock enable\r Set and reset by software." - bit_offset: 23 - bit_size: 1 - - name: CRSEN - description: "CRS clock enable\r Set and reset by software." - bit_offset: 24 - bit_size: 1 - - name: USART6EN - description: "USART6 clock enable\r Set and reset by software." - bit_offset: 25 - bit_size: 1 - - name: USART10EN - description: "USART10 clock enable\r Set and reset by software." - bit_offset: 26 - bit_size: 1 - - name: USART11EN - description: USART11 clock enable - bit_offset: 27 - bit_size: 1 - - name: CECEN - description: "HDMI-CEC clock enable\r Set and reset by software." - bit_offset: 28 - bit_size: 1 - - name: UART7EN - description: "UART7 clock enable\r Set and reset by software." - bit_offset: 30 - bit_size: 1 - - name: UART8EN - description: "UART8 clock enable\r Set and reset by software." - bit_offset: 31 - bit_size: 1 + - name: TIM2EN + description: "TIM2 clock enable\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: "TIM3 clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: "TIM4 clock enable\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: "TIM5 clock enable\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: "TIM6 clock enable\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: "TIM7 clock enable\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: "TIM12 clock enable\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: "TIM13 clock enable\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: "TIM14 clock enable\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: WWDGEN + description: "WWDG clock enable\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: "SPI2 clock enable\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: "SPI3 clock enable\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: "USART2 clock enable\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: "USART3 clock enable\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: "UART4 clock enable\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: "UART5 clock enable\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: "I2C1 clock enable\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: "I2C2 clock enable\r Set and reset by software." + bit_offset: 22 + bit_size: 1 + - name: I3C1EN + description: "I3C1 clock enable\r Set and reset by software." + bit_offset: 23 + bit_size: 1 + - name: CRSEN + description: "CRS clock enable\r Set and reset by software." + bit_offset: 24 + bit_size: 1 + - name: USART6EN + description: "USART6 clock enable\r Set and reset by software." + bit_offset: 25 + bit_size: 1 + - name: USART10EN + description: "USART10 clock enable\r Set and reset by software." + bit_offset: 26 + bit_size: 1 + - name: USART11EN + description: USART11 clock enable + bit_offset: 27 + bit_size: 1 + - name: CECEN + description: "HDMI-CEC clock enable\r Set and reset by software." + bit_offset: 28 + bit_size: 1 + - name: UART7EN + description: "UART7 clock enable\r Set and reset by software." + bit_offset: 30 + bit_size: 1 + - name: UART8EN + description: "UART8 clock enable\r Set and reset by software." + bit_offset: 31 + bit_size: 1 fieldset/APB1LLPENR: description: RCC APB1 sleep clock register fields: - - name: TIM2LPEN - description: "TIM2 clock enable during sleep mode\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: TIM3LPEN - description: "TIM3 clock enable during sleep mode\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: TIM4LPEN - description: "TIM4 clock enable during sleep mode\r Set and reset by software." - bit_offset: 2 - bit_size: 1 - - name: TIM5LPEN - description: "TIM5 clock enable during sleep mode\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - - name: TIM6LPEN - description: "TIM6 clock enable during sleep mode\r Set and reset by software." - bit_offset: 4 - bit_size: 1 - - name: TIM7LPEN - description: "TIM7 clock enable during sleep mode\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: TIM12LPEN - description: "TIM12 clock enable during sleep mode\r Set and reset by software." - bit_offset: 6 - bit_size: 1 - - name: TIM13LPEN - description: "TIM13 clock enable during sleep mode\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - - name: TIM14LPEN - description: "TIM14 clock enable during sleep mode\r Set and reset by software." - bit_offset: 8 - bit_size: 1 - - name: WWDGLPEN - description: "WWDG clock enable during sleep mode\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: SPI2LPEN - description: "SPI2 clock enable during sleep mode\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: SPI3LPEN - description: "SPI3 clock enable during sleep mode\r Set and reset by software." - bit_offset: 15 - bit_size: 1 - - name: USART2LPEN - description: "USART2 clock enable during sleep mode\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: USART3LPEN - description: "USART3 clock enable during sleep mode\r Set and reset by software." - bit_offset: 18 - bit_size: 1 - - name: UART4LPEN - description: "UART4 clock enable during sleep mode\r Set and reset by software." - bit_offset: 19 - bit_size: 1 - - name: UART5LPEN - description: "UART5 clock enable during sleep mode\r Set and reset by software." - bit_offset: 20 - bit_size: 1 - - name: I2C1LPEN - description: "I2C1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 21 - bit_size: 1 - - name: I2C2LPEN - description: "I2C2 clock enable during sleep mode\r Set and reset by software." - bit_offset: 22 - bit_size: 1 - - name: I3C1LPEN - description: "I3C1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 23 - bit_size: 1 - - name: CRSLPEN - description: "CRS clock enable during sleep mode\r Set and reset by software." - bit_offset: 24 - bit_size: 1 - - name: USART6LPEN - description: "USART6 clock enable during sleep mode\r Set and reset by software." - bit_offset: 25 - bit_size: 1 - - name: USART10LPEN - description: "USART10 clock enable during sleep mode\r Set and reset by software." - bit_offset: 26 - bit_size: 1 - - name: USART11LPEN - description: "USART11 clock enable during sleep mode\r Set and reset by software." - bit_offset: 27 - bit_size: 1 - - name: CECLPEN - description: "HDMI-CEC clock enable during sleep mode\r Set and reset by software." - bit_offset: 28 - bit_size: 1 - - name: UART7LPEN - description: "UART7 clock enable during sleep mode\r Set and reset by software." - bit_offset: 30 - bit_size: 1 - - name: UART8LPEN - description: "UART8 clock enable during sleep mode\r Set and reset by software." - bit_offset: 31 - bit_size: 1 + - name: TIM2LPEN + description: "TIM2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3LPEN + description: "TIM3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: TIM4LPEN + description: "TIM4 clock enable during sleep mode\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: TIM5LPEN + description: "TIM5 clock enable during sleep mode\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: TIM6LPEN + description: "TIM6 clock enable during sleep mode\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7LPEN + description: "TIM7 clock enable during sleep mode\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: TIM12LPEN + description: "TIM12 clock enable during sleep mode\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: TIM13LPEN + description: "TIM13 clock enable during sleep mode\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: TIM14LPEN + description: "TIM14 clock enable during sleep mode\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: WWDGLPEN + description: "WWDG clock enable during sleep mode\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SPI2LPEN + description: "SPI2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: SPI3LPEN + description: "SPI3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: USART2LPEN + description: "USART2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: USART3LPEN + description: "USART3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: UART4LPEN + description: "UART4 clock enable during sleep mode\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: UART5LPEN + description: "UART5 clock enable during sleep mode\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: I2C1LPEN + description: "I2C1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: "I2C2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 22 + bit_size: 1 + - name: I3C1LPEN + description: "I3C1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 23 + bit_size: 1 + - name: CRSLPEN + description: "CRS clock enable during sleep mode\r Set and reset by software." + bit_offset: 24 + bit_size: 1 + - name: USART6LPEN + description: "USART6 clock enable during sleep mode\r Set and reset by software." + bit_offset: 25 + bit_size: 1 + - name: USART10LPEN + description: "USART10 clock enable during sleep mode\r Set and reset by software." + bit_offset: 26 + bit_size: 1 + - name: USART11LPEN + description: "USART11 clock enable during sleep mode\r Set and reset by software." + bit_offset: 27 + bit_size: 1 + - name: CECLPEN + description: "HDMI-CEC clock enable during sleep mode\r Set and reset by software." + bit_offset: 28 + bit_size: 1 + - name: UART7LPEN + description: "UART7 clock enable during sleep mode\r Set and reset by software." + bit_offset: 30 + bit_size: 1 + - name: UART8LPEN + description: "UART8 clock enable during sleep mode\r Set and reset by software." + bit_offset: 31 + bit_size: 1 fieldset/APB1LRSTR: description: RCC APB1 peripheral low reset register fields: - - name: TIM2RST - description: "TIM2 block reset\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: "TIM3 block reset\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: "TIM4 block reset\r Set and reset by software." - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: "TIM5 block reset\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: "TIM6 block reset\r Set and reset by software." - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: "TIM7 block reset\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: TIM12RST - description: "TIM12 block reset\r Set and reset by software." - bit_offset: 6 - bit_size: 1 - - name: TIM13RST - description: "TIM13 block reset t\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - - name: TIM14RST - description: "TIM14 block reset\r Set and reset by software." - bit_offset: 8 - bit_size: 1 - - name: SPI2RST - description: "SPI2 block reset\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: "SPI3 block reset\r Set and reset by software." - bit_offset: 15 - bit_size: 1 - - name: USART2RST - description: "USART2 block reset\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: "USART3 block reset\r Set and reset by software." - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: "UART4 block reset\r Set and reset by software." - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: "UART5 block reset\r Set and reset by software." - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: "I2C1 block reset\r Set and reset by software." - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: "I2C2 block reset\r Set and reset by software." - bit_offset: 22 - bit_size: 1 - - name: I3C1RST - description: "I3C1 block reset\r Set and reset by software." - bit_offset: 23 - bit_size: 1 - - name: CRSRST - description: "CRS block reset\r Set and reset by software." - bit_offset: 24 - bit_size: 1 - - name: USART6RST - description: "USART6 block reset\r Set and reset by software." - bit_offset: 25 - bit_size: 1 - - name: USART10RST - description: "USART10 block reset\r Set and reset by software." - bit_offset: 26 - bit_size: 1 - - name: USART11RST - description: "USART11 block reset\r Set and reset by software." - bit_offset: 27 - bit_size: 1 - - name: CECRST - description: "HDMI-CEC block reset\r Set and reset by software." - bit_offset: 28 - bit_size: 1 - - name: UART7RST - description: "UART7 block reset\r Set and reset by software." - bit_offset: 30 - bit_size: 1 - - name: UART8RST - description: "UART8 block reset\r Set and reset by software." - bit_offset: 31 - bit_size: 1 + - name: TIM2RST + description: "TIM2 block reset\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: "TIM3 block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: "TIM4 block reset\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: "TIM5 block reset\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: "TIM6 block reset\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: "TIM7 block reset\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: "TIM12 block reset\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: "TIM13 block reset t\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: "TIM14 block reset\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: SPI2RST + description: "SPI2 block reset\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: "SPI3 block reset\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: "USART2 block reset\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: "USART3 block reset\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: "UART4 block reset\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: "UART5 block reset\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: "I2C1 block reset\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: "I2C2 block reset\r Set and reset by software." + bit_offset: 22 + bit_size: 1 + - name: I3C1RST + description: "I3C1 block reset\r Set and reset by software." + bit_offset: 23 + bit_size: 1 + - name: CRSRST + description: "CRS block reset\r Set and reset by software." + bit_offset: 24 + bit_size: 1 + - name: USART6RST + description: "USART6 block reset\r Set and reset by software." + bit_offset: 25 + bit_size: 1 + - name: USART10RST + description: "USART10 block reset\r Set and reset by software." + bit_offset: 26 + bit_size: 1 + - name: USART11RST + description: "USART11 block reset\r Set and reset by software." + bit_offset: 27 + bit_size: 1 + - name: CECRST + description: "HDMI-CEC block reset\r Set and reset by software." + bit_offset: 28 + bit_size: 1 + - name: UART7RST + description: "UART7 block reset\r Set and reset by software." + bit_offset: 30 + bit_size: 1 + - name: UART8RST + description: "UART8 block reset\r Set and reset by software." + bit_offset: 31 + bit_size: 1 fieldset/APB2ENR: description: RCC APB2 peripheral clock register fields: - - name: TIM1EN - description: "TIM1 clock enable\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: "SPI1 clock enable\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: TIM8EN - description: "TIM8 clock enable\r Set and reset by software." - bit_offset: 13 - bit_size: 1 - - name: USART1EN - description: "USART1 clock enable\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: TIM15EN - description: "TIM15 clock enable\r Set and reset by software." - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: "TIM16 clock enable\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: "TIM17 clock enable\r Set and reset by software." - bit_offset: 18 - bit_size: 1 - - name: SPI4EN - description: "SPI4 clock enable\r Set and reset by software." - bit_offset: 19 - bit_size: 1 - - name: SPI6EN - description: "SPI6 clock enable\r Set and reset by software." - bit_offset: 20 - bit_size: 1 - - name: SAI1EN - description: "SAI1 clock enable\r Set and reset by software." - bit_offset: 21 - bit_size: 1 - - name: SAI2EN - description: "SAI2 clock enable\r Set and cleared by software." - bit_offset: 22 - bit_size: 1 - - name: USBEN - description: "USB clock enable\r Set and reset by software." - bit_offset: 24 - bit_size: 1 + - name: TIM1EN + description: "TIM1 clock enable\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: "SPI1 clock enable\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: TIM8EN + description: "TIM8 clock enable\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: USART1EN + description: "USART1 clock enable\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: TIM15EN + description: "TIM15 clock enable\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: "TIM16 clock enable\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: "TIM17 clock enable\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: SPI4EN + description: "SPI4 clock enable\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: SPI6EN + description: "SPI6 clock enable\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: SAI1EN + description: "SAI1 clock enable\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: SAI2EN + description: "SAI2 clock enable\r Set and cleared by software." + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: "USB clock enable\r Set and reset by software." + bit_offset: 24 + bit_size: 1 fieldset/APB2LPENR: description: RCC APB2 sleep clock register fields: - - name: TIM1LPEN - description: "TIM1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: SPI1LPEN - description: "SPI1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: TIM8LPEN - description: "TIM8 clock enable during sleep mode\r Set and reset by software." - bit_offset: 13 - bit_size: 1 - - name: USART1LPEN - description: "USART1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: TIM15LPEN - description: "TIM15 clock enable during sleep mode\r Set and reset by software." - bit_offset: 16 - bit_size: 1 - - name: TIM16LPEN - description: "TIM16 clock enable during sleep mode\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: TIM17LPEN - description: "TIM17 clock enable during sleep mode\r Set and reset by software." - bit_offset: 18 - bit_size: 1 - - name: SPI4LPEN - description: "SPI4 clock enable during sleep mode\r Set and reset by software." - bit_offset: 19 - bit_size: 1 - - name: SPI6LPEN - description: "SPI6 clock enable during sleep mode\r Set and reset by software." - bit_offset: 20 - bit_size: 1 - - name: SAI1LPEN - description: "SAI1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 21 - bit_size: 1 - - name: SAI2LPEN - description: "SAI2 clock enable during sleep mode\r Set and reset by software." - bit_offset: 22 - bit_size: 1 - - name: USBLPEN - description: "USB clock enable during sleep mode\r Set and reset by software." - bit_offset: 24 - bit_size: 1 + - name: TIM1LPEN + description: "TIM1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1LPEN + description: "SPI1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: TIM8LPEN + description: "TIM8 clock enable during sleep mode\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: USART1LPEN + description: "USART1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: TIM15LPEN + description: "TIM15 clock enable during sleep mode\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: TIM16LPEN + description: "TIM16 clock enable during sleep mode\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: TIM17LPEN + description: "TIM17 clock enable during sleep mode\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: SPI4LPEN + description: "SPI4 clock enable during sleep mode\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: SPI6LPEN + description: "SPI6 clock enable during sleep mode\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: SAI1LPEN + description: "SAI1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: SAI2LPEN + description: "SAI2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 22 + bit_size: 1 + - name: USBLPEN + description: "USB clock enable during sleep mode\r Set and reset by software." + bit_offset: 24 + bit_size: 1 fieldset/APB2RSTR: description: RCC APB2 peripheral reset register fields: - - name: TIM1RST - description: "TIM1 block reset\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: "SPI1 block reset\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: TIM8RST - description: "TIM8 block reset\r Set and reset by software." - bit_offset: 13 - bit_size: 1 - - name: USART1RST - description: "USART1 block reset\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: TIM15RST - description: "TIM15 block reset\r Set and reset by software." - bit_offset: 16 - bit_size: 1 - - name: TIM16RST - description: "TIM16 block reset\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: "TIM17 block reset\r Set and reset by software." - bit_offset: 18 - bit_size: 1 - - name: SPI4RST - description: "SPI4 block reset\r Set and reset by software." - bit_offset: 19 - bit_size: 1 - - name: SPI6RST - description: "SPI6 block reset\r Set and reset by software." - bit_offset: 20 - bit_size: 1 - - name: SAI1RST - description: "SAI1 block reset\r Set and reset by software." - bit_offset: 21 - bit_size: 1 - - name: SAI2RST - description: "SAI2 block reset\r Set and reset by software." - bit_offset: 22 - bit_size: 1 - - name: USBRST - description: "USB block reset\r Set and reset by software." - bit_offset: 24 - bit_size: 1 + - name: TIM1RST + description: "TIM1 block reset\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: "SPI1 block reset\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: TIM8RST + description: "TIM8 block reset\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: USART1RST + description: "USART1 block reset\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: TIM15RST + description: "TIM15 block reset\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: "TIM16 block reset\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: "TIM17 block reset\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: SPI4RST + description: "SPI4 block reset\r Set and reset by software." + bit_offset: 19 + bit_size: 1 + - name: SPI6RST + description: "SPI6 block reset\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: SAI1RST + description: "SAI1 block reset\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: SAI2RST + description: "SAI2 block reset\r Set and reset by software." + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: "USB block reset\r Set and reset by software." + bit_offset: 24 + bit_size: 1 fieldset/APB3ENR: description: RCC APB3 peripheral clock register fields: - - name: SBSEN - description: "SBS clock enable\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: SPI5EN - description: "SPI5 clock enable\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: LPUART1EN - description: "LPUART1 clock enable\r Set and reset by software." - bit_offset: 6 - bit_size: 1 - - name: I2C3EN - description: "I2C3 clock enable\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - - name: I2C4EN - description: "I2C4 clock enable\r Set and reset by software." - bit_offset: 8 - bit_size: 1 - - name: LPTIM1EN - description: "LPTIM1 clock enable\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: LPTIM3EN - description: "LPTIM3 clock enable\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: LPTIM4EN - description: "LPTIM4 clock enable\r Set and reset by software." - bit_offset: 13 - bit_size: 1 - - name: LPTIM5EN - description: "LPTIM5 clock enable\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: LPTIM6EN - description: "LPTIM6 clock enable\r Set and reset by software." - bit_offset: 15 - bit_size: 1 - - name: VREFEN - description: "VREF clock enable\r Set and reset by software." - bit_offset: 20 - bit_size: 1 - - name: RTCAPBEN - description: "RTC APB interface clock enable\r Set and reset by software." - bit_offset: 21 - bit_size: 1 + - name: SBSEN + description: "SBS clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: SPI5EN + description: "SPI5 clock enable\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: LPUART1EN + description: "LPUART1 clock enable\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: I2C3EN + description: "I2C3 clock enable\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: I2C4EN + description: "I2C4 clock enable\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: LPTIM1EN + description: "LPTIM1 clock enable\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: LPTIM3EN + description: "LPTIM3 clock enable\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: LPTIM4EN + description: "LPTIM4 clock enable\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: LPTIM5EN + description: "LPTIM5 clock enable\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: LPTIM6EN + description: "LPTIM6 clock enable\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: VREFEN + description: "VREF clock enable\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: RTCAPBEN + description: "RTC APB interface clock enable\r Set and reset by software." + bit_offset: 21 + bit_size: 1 fieldset/APB3LPENR: description: RCC APB3 sleep clock register fields: - - name: SBSLPEN - description: "SBS clock enable during sleep mode\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: SPI5LPEN - description: "SPI5 clock enable during Slsleepeep mode\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: LPUART1LPEN - description: "LPUART1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 6 - bit_size: 1 - - name: I2C3LPEN - description: "I2C3 clock enable during sleep mode\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - - name: I2C4LPEN - description: "I2C4 clock enable during sleep mode\r Set and reset by software." - bit_offset: 8 - bit_size: 1 - - name: LPTIM1LPEN - description: "LPTIM1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: LPTIM3LPEN - description: "LPTIM3 clock enable during sleep mode\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: LPTIM4LPEN - description: "LPTIM4 clock enable during sleep mode\r Set and reset by software." - bit_offset: 13 - bit_size: 1 - - name: LPTIM5LPEN - description: "LPTIM5 clock enable during sleep mode\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: LPTIM6LPEN - description: "LPTIM6 clock enable during sleep mode\r Set and reset by software." - bit_offset: 15 - bit_size: 1 - - name: VREFLPEN - description: "VREF clock enable during sleep mode\r Set and reset by software." - bit_offset: 20 - bit_size: 1 - - name: RTCAPBLPEN - description: "RTC APB interface clock enable during sleep mode\r Set and reset by software." - bit_offset: 21 - bit_size: 1 + - name: SBSLPEN + description: "SBS clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: SPI5LPEN + description: "SPI5 clock enable during Slsleepeep mode\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: LPUART1LPEN + description: "LPUART1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: I2C3LPEN + description: "I2C3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: I2C4LPEN + description: "I2C4 clock enable during sleep mode\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: LPTIM1LPEN + description: "LPTIM1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: LPTIM3LPEN + description: "LPTIM3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: LPTIM4LPEN + description: "LPTIM4 clock enable during sleep mode\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: LPTIM5LPEN + description: "LPTIM5 clock enable during sleep mode\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: LPTIM6LPEN + description: "LPTIM6 clock enable during sleep mode\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: VREFLPEN + description: "VREF clock enable during sleep mode\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: RTCAPBLPEN + description: "RTC APB interface clock enable during sleep mode\r Set and reset by software." + bit_offset: 21 + bit_size: 1 fieldset/APB3RSTR: description: RCC APB3 peripheral reset register fields: - - name: SBSRST - description: "SBS block reset\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: SPI5RST - description: "SPI5 block reset\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: LPUART1RST - description: "LPUART1 block reset\r Set and reset by software." - bit_offset: 6 - bit_size: 1 - - name: I2C3RST - description: "I2C3 block reset\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - - name: I2C4RST - description: "I2C4 block reset\r Set and reset by software." - bit_offset: 8 - bit_size: 1 - - name: LPTIM1RST - description: "LPTIM1 block reset\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: LPTIM3RST - description: "LPTIM3 block reset\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: LPTIM4RST - description: "LPTIM4 block reset\r Set and reset by software." - bit_offset: 13 - bit_size: 1 - - name: LPTIM5RST - description: "LPTIM5 block reset\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: LPTIM6RST - description: "LPTIM6 block reset\r Set and reset by software." - bit_offset: 15 - bit_size: 1 - - name: VREFRST - description: "VREF block reset\r Set and reset by software." - bit_offset: 20 - bit_size: 1 + - name: SBSRST + description: "SBS block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: SPI5RST + description: "SPI5 block reset\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: LPUART1RST + description: "LPUART1 block reset\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: I2C3RST + description: "I2C3 block reset\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: I2C4RST + description: "I2C4 block reset\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: LPTIM1RST + description: "LPTIM1 block reset\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: LPTIM3RST + description: "LPTIM3 block reset\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: LPTIM4RST + description: "LPTIM4 block reset\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: LPTIM5RST + description: "LPTIM5 block reset\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: LPTIM6RST + description: "LPTIM6 block reset\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: VREFRST + description: "VREF block reset\r Set and reset by software." + bit_offset: 20 + bit_size: 1 fieldset/BDCR: description: RCC Backup domain control register fields: - - name: LSEON - description: "LSE oscillator enabled\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: "LSE oscillator ready\r Set and reset by hardware to indicate when the LSE is stable.\r This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0." - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: "LSE oscillator bypass\r Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1)" - bit_offset: 2 - bit_size: 1 - - name: LSEDRV - description: "LSE oscillator driving capability\r Set by software to select the driving capability of the LSE oscillator.\r These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0)." - bit_offset: 3 - bit_size: 2 - enum: LSEDRV - - name: LSECSSON - description: "LSE clock security system enable\r Set by software to enable the clock security system on 32 kHz oscillator.\r LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON." - bit_offset: 5 - bit_size: 1 - - name: LSECSSD - description: "LSE clock security system failure detection\r Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator." - bit_offset: 6 - bit_size: 1 - - name: LSEEXT - description: "low-speed external clock type in bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the LSEON bit, to be used by the device.\r The LSEEXT bit can be written only if the LSE oscillator is disabled." - bit_offset: 7 - bit_size: 1 - enum: LSEEXT - - name: RTCSEL - description: "RTC clock source selection\r Set by software to select the clock source for the RTC.\r These bits can be written only one time (except in case of failure detection on LSE).\r These bits must be written before LSECSSON is enabled.\r The VSWRST bit can be used to reset them, then it can be written one time again.\r If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST)." - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: "RTC clock enable\r Set and reset by software." - bit_offset: 15 - bit_size: 1 - - name: VSWRST - description: "VSwitch domain software reset\r Set and reset by software." - bit_offset: 16 - bit_size: 1 - - name: LSCOEN - description: "Low-speed clock output (LSCO) enable\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: LSCOSEL - description: "Low-speed clock output selection\r Set and cleared by software." - bit_offset: 25 - bit_size: 1 - enum: LSCOSEL - - name: LSION - description: "LSI oscillator enable\r Set and cleared by software." - bit_offset: 26 - bit_size: 1 - - name: LSIRDY - description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is stable.\r After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles.\r This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0." - bit_offset: 27 - bit_size: 1 + - name: LSEON + description: "LSE oscillator enabled\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: "LSE oscillator ready\r Set and reset by hardware to indicate when the LSE is stable.\r This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0." + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: "LSE oscillator bypass\r Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1)" + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: "LSE oscillator driving capability\r Set by software to select the driving capability of the LSE oscillator.\r These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0)." + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: "LSE clock security system enable\r Set by software to enable the clock security system on 32 kHz oscillator.\r LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON." + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: "LSE clock security system failure detection\r Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator." + bit_offset: 6 + bit_size: 1 + - name: LSEEXT + description: "low-speed external clock type in bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the LSEON bit, to be used by the device.\r The LSEEXT bit can be written only if the LSE oscillator is disabled." + bit_offset: 7 + bit_size: 1 + enum: LSEEXT + - name: RTCSEL + description: "RTC clock source selection\r Set by software to select the clock source for the RTC.\r These bits can be written only one time (except in case of failure detection on LSE).\r These bits must be written before LSECSSON is enabled.\r The VSWRST bit can be used to reset them, then it can be written one time again.\r If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST)." + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: "RTC clock enable\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: VSWRST + description: "VSwitch domain software reset\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: "Low-speed clock output (LSCO) enable\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: "Low-speed clock output selection\r Set and cleared by software." + bit_offset: 25 + bit_size: 1 + enum: LSCOSEL + - name: LSION + description: "LSI oscillator enable\r Set and cleared by software." + bit_offset: 26 + bit_size: 1 + - name: LSIRDY + description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is stable.\r After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles.\r This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0." + bit_offset: 27 + bit_size: 1 fieldset/CCIPR1: description: RCC kernel clock configuration register fields: - - name: USART1SEL - description: "USART1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" - bit_offset: 0 - bit_size: 3 - enum: USARTSEL - - name: USART2SEL - description: "USART2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" - bit_offset: 3 - bit_size: 3 - enum: USARTSEL - - name: USART3SEL - description: "USART3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" - bit_offset: 6 - bit_size: 3 - enum: USARTSEL - - name: UART4SEL - description: "UART4 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 9 - bit_size: 3 - enum: UARTSEL - - name: UART5SEL - description: "UART5 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 12 - bit_size: 3 - enum: UARTSEL - - name: USART6SEL - description: "USART6 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 15 - bit_size: 3 - enum: USARTSEL - - name: UART7SEL - description: "UART7 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 18 - bit_size: 3 - enum: UARTSEL - - name: UART8SEL - description: "UART8 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 21 - bit_size: 3 - enum: UARTSEL - - name: UART9SEL - description: "UART9 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 24 - bit_size: 3 - enum: UARTSEL - - name: USART10SEL - description: "USART10 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 27 - bit_size: 3 - enum: USARTSEL - - name: TIMICSEL - description: "TIM12, TIM15 and LPTIM2 input capture source selection\r Set and reset by software." - bit_offset: 31 - bit_size: 1 - enum: TIMICSEL + - name: USART1SEL + description: "USART1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 0 + bit_size: 3 + enum: USARTSEL + - name: USART2SEL + description: "USART2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 3 + bit_size: 3 + enum: USARTSEL + - name: USART3SEL + description: "USART3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 6 + bit_size: 3 + enum: USARTSEL + - name: UART4SEL + description: "UART4 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 9 + bit_size: 3 + enum: UARTSEL + - name: UART5SEL + description: "UART5 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 12 + bit_size: 3 + enum: UARTSEL + - name: USART6SEL + description: "USART6 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 15 + bit_size: 3 + enum: USARTSEL + - name: UART7SEL + description: "UART7 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 18 + bit_size: 3 + enum: UARTSEL + - name: UART8SEL + description: "UART8 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 21 + bit_size: 3 + enum: UARTSEL + - name: UART9SEL + description: "UART9 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 24 + bit_size: 3 + enum: UARTSEL + - name: USART10SEL + description: "USART10 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 27 + bit_size: 3 + enum: USARTSEL + - name: TIMICSEL + description: "TIM12, TIM15 and LPTIM2 input capture source selection\r Set and reset by software." + bit_offset: 31 + bit_size: 1 + enum: TIMICSEL fieldset/CCIPR2: description: RCC kernel clock configuration register fields: - - name: USART11SEL - description: "USART11 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" - bit_offset: 0 - bit_size: 3 - enum: USARTSEL - - name: USART12SEL - description: "USART12 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" - bit_offset: 4 - bit_size: 3 - enum: USARTSEL - - name: LPTIM1SEL - description: "LPTIM1 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 8 - bit_size: 3 - enum: LPTIMSEL - - name: LPTIM2SEL - description: "LPTIM2 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 12 - bit_size: 3 - enum: LPTIMSEL - - name: LPTIM3SEL - description: "LPTIM3 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 16 - bit_size: 3 - enum: LPTIMSEL - - name: LPTIM4SEL - description: "LPTIM4 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 20 - bit_size: 3 - enum: LPTIMSEL - - name: LPTIM5SEL - description: "LPTIM5 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 24 - bit_size: 3 - enum: LPTIMSEL - - name: LPTIM6SEL - description: "LPTIM6 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 28 - bit_size: 3 - enum: LPTIMSEL + - name: USART11SEL + description: "USART11 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 0 + bit_size: 3 + enum: USARTSEL + - name: USART12SEL + description: "USART12 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 4 + bit_size: 3 + enum: USARTSEL + - name: LPTIM1SEL + description: "LPTIM1 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 8 + bit_size: 3 + enum: LPTIMSEL + - name: LPTIM2SEL + description: "LPTIM2 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 12 + bit_size: 3 + enum: LPTIMSEL + - name: LPTIM3SEL + description: "LPTIM3 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 16 + bit_size: 3 + enum: LPTIMSEL + - name: LPTIM4SEL + description: "LPTIM4 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 20 + bit_size: 3 + enum: LPTIMSEL + - name: LPTIM5SEL + description: "LPTIM5 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 24 + bit_size: 3 + enum: LPTIMSEL + - name: LPTIM6SEL + description: "LPTIM6 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 28 + bit_size: 3 + enum: LPTIMSEL fieldset/CCIPR3: description: RCC kernel clock configuration register fields: - - name: SPI1SEL - description: "SPI1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" - bit_offset: 0 - bit_size: 3 - enum: SPI1SEL - - name: SPI2SEL - description: "SPI2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" - bit_offset: 3 - bit_size: 3 - enum: SPI2SEL - - name: SPI3SEL - description: "SPI3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" - bit_offset: 6 - bit_size: 3 - enum: SPI3SEL - - name: SPI4SEL - description: "SPI4 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 9 - bit_size: 3 - enum: SPI4SEL - - name: SPI5SEL - description: "SPI5 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 12 - bit_size: 3 - enum: SPI5SEL - - name: SPI6SEL - description: "SPI6 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 15 - bit_size: 3 - enum: SPI6SEL - - name: LPUART1SEL - description: "LPUART1 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 24 - bit_size: 3 - enum: LPUARTSEL + - name: SPI1SEL + description: "SPI1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 0 + bit_size: 3 + enum: SPI1SEL + - name: SPI2SEL + description: "SPI2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 3 + bit_size: 3 + enum: SPI2SEL + - name: SPI3SEL + description: "SPI3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 6 + bit_size: 3 + enum: SPI3SEL + - name: SPI4SEL + description: "SPI4 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 9 + bit_size: 3 + enum: SPI4SEL + - name: SPI5SEL + description: "SPI5 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 12 + bit_size: 3 + enum: SPI5SEL + - name: SPI6SEL + description: "SPI6 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 15 + bit_size: 3 + enum: SPI6SEL + - name: LPUART1SEL + description: "LPUART1 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 24 + bit_size: 3 + enum: LPUARTSEL fieldset/CCIPR4: description: RCC kernel clock configuration register fields: - - name: OCTOSPI1SEL - description: "OCTOSPI1 kernel clock source selection\r Set and reset by software." - bit_offset: 0 - bit_size: 2 - enum: OCTOSPISEL - - name: SYSTICKSEL - description: "SYSTICK clock source selection\r Note: rcc_hclk frequency must be four times higher than\r lsi_ker_ck/lse_ck (period (LSI/LSE) ≥ 4 * period (HCLK)." - bit_offset: 2 - bit_size: 2 - enum: SYSTICKSEL - - name: USBSEL - description: USB kernel clock source selection - bit_offset: 4 - bit_size: 2 - enum: USBSEL - - name: SDMMC1SEL - description: SDMMC1 kernel clock source selection - bit_offset: 6 - bit_size: 1 - enum: SDMMCSEL - - name: SDMMC2SEL - description: SDMMC2 kernel clock source selection - bit_offset: 7 - bit_size: 1 - enum: SDMMCSEL - - name: I2C1SEL - description: I2C1 kernel clock source selection - bit_offset: 16 - bit_size: 2 - enum: ICSEL - - name: I2C2SEL - description: I2C2 kernel clock source selection - bit_offset: 18 - bit_size: 2 - enum: ICSEL - - name: I2C3SEL - description: I2C3 kernel clock source selection - bit_offset: 20 - bit_size: 2 - enum: ICSEL - - name: I2C4SEL - description: I2C4 kernel clock source selection - bit_offset: 22 - bit_size: 2 - enum: ICSEL - - name: I3C1SEL - description: I3C1 kernel clock source selection - bit_offset: 24 - bit_size: 2 - enum: ICSEL + - name: OCTOSPI1SEL + description: "OCTOSPI1 kernel clock source selection\r Set and reset by software." + bit_offset: 0 + bit_size: 2 + enum: OCTOSPISEL + - name: SYSTICKSEL + description: "SYSTICK clock source selection\r Note: rcc_hclk frequency must be four times higher than\r lsi_ker_ck/lse_ck (period (LSI/LSE) ≥ 4 * period (HCLK)." + bit_offset: 2 + bit_size: 2 + enum: SYSTICKSEL + - name: USBSEL + description: USB kernel clock source selection + bit_offset: 4 + bit_size: 2 + enum: USBSEL + - name: SDMMC1SEL + description: SDMMC1 kernel clock source selection + bit_offset: 6 + bit_size: 1 + enum: SDMMCSEL + - name: SDMMC2SEL + description: SDMMC2 kernel clock source selection + bit_offset: 7 + bit_size: 1 + enum: SDMMCSEL + - name: I2C1SEL + description: I2C1 kernel clock source selection + bit_offset: 16 + bit_size: 2 + enum: ICSEL + - name: I2C2SEL + description: I2C2 kernel clock source selection + bit_offset: 18 + bit_size: 2 + enum: ICSEL + - name: I2C3SEL + description: I2C3 kernel clock source selection + bit_offset: 20 + bit_size: 2 + enum: ICSEL + - name: I2C4SEL + description: I2C4 kernel clock source selection + bit_offset: 22 + bit_size: 2 + enum: ICSEL + - name: I3C1SEL + description: I3C1 kernel clock source selection + bit_offset: 24 + bit_size: 2 + enum: ICSEL fieldset/CCIPR5: description: RCC kernel clock configuration register fields: - - name: ADCDACSEL - description: "ADC and DAC kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 0 - bit_size: 3 - enum: ADCDACSEL - - name: DACSEL - description: DAC hold clock - bit_offset: 3 - bit_size: 1 - enum: DACSEL - - name: RNGSEL - description: RNG kernel clock source selection - bit_offset: 4 - bit_size: 2 - enum: RNGSEL - - name: CECSEL - description: HSMI-CEC kernel clock source selection - bit_offset: 6 - bit_size: 2 - enum: CECSEL - - name: FDCAN12SEL - description: FDCAN1 and FDCAN2 kernel clock source selection - bit_offset: 8 - bit_size: 2 - enum: FDCANSEL - - name: SAI1SEL - description: "SAI1 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 16 - bit_size: 3 - enum: SAISEL - - name: SAI2SEL - description: "SAI2 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 19 - bit_size: 3 - enum: SAISEL - - name: CKPERSEL - description: per_ck clock source selection - bit_offset: 30 - bit_size: 2 - enum: CKPERSEL + - name: ADCDACSEL + description: "ADC and DAC kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 0 + bit_size: 3 + enum: ADCDACSEL + - name: DACSEL + description: DAC hold clock + bit_offset: 3 + bit_size: 1 + enum: DACSEL + - name: RNGSEL + description: RNG kernel clock source selection + bit_offset: 4 + bit_size: 2 + enum: RNGSEL + - name: CECSEL + description: HSMI-CEC kernel clock source selection + bit_offset: 6 + bit_size: 2 + enum: CECSEL + - name: FDCAN12SEL + description: FDCAN1 and FDCAN2 kernel clock source selection + bit_offset: 8 + bit_size: 2 + enum: FDCANSEL + - name: SAI1SEL + description: "SAI1 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 16 + bit_size: 3 + enum: SAISEL + - name: SAI2SEL + description: "SAI2 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 19 + bit_size: 3 + enum: SAISEL + - name: CKPERSEL + description: per_ck clock source selection + bit_offset: 30 + bit_size: 2 + enum: CKPERSEL fieldset/CFGR: description: RCC clock configuration register fields: - - name: SW - description: "system clock and trace clock switch\r Set and reset by software to select system clock and trace clock sources (sys_ck).\r Set by hardware in order to:\r -\tforce the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode\r -\tforce the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock\r others: reserved" - bit_offset: 0 - bit_size: 3 - enum: SW - - name: SWS - description: "system clock switch status\r Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset).\r others: reserved" - bit_offset: 3 - bit_size: 3 - enum: SW - - name: STOPWUCK - description: "system clock selection after a wakeup from system Stop\r Set and reset by software to select the system wakeup clock from system Stop.\r The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. 0: HSI selected as wakeup clock from system Stop (default after reset)\r STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10)." - bit_offset: 6 - bit_size: 1 - enum: STOPWUCK - - name: STOPKERWUCK - description: "kernel clock selection after a wakeup from system Stop\r Set and reset by software to select the kernel wakeup clock from system Stop." - bit_offset: 7 - bit_size: 1 - enum: STOPKERWUCK - - name: RTCPRE - description: "HSE division factor for RTC clock\r Set and cleared by software to divide the HSE to generate a clock for RTC.\r Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source.\r ..." - bit_offset: 8 - bit_size: 6 - - name: TIMPRE - description: "timers clocks prescaler selection\r This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains." - bit_offset: 15 - bit_size: 1 - enum: TIMPRE - - name: MCO1PRE - description: "MCO1 prescaler\r Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." - bit_offset: 18 - bit_size: 4 - - name: MCO1 - description: "Microcontroller clock output 1\r Set and cleared by software. Clock source selection may generate glitches on MCO1.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" - bit_offset: 22 - bit_size: 3 - enum: MCO1 - - name: MCO2PRE - description: "MCO2 prescaler\r Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." - bit_offset: 25 - bit_size: 4 - - name: MCO2 - description: "microcontroller clock output 2\r Set and cleared by software. Clock source selection may generate glitches on MCO2.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" - bit_offset: 29 - bit_size: 3 - enum: MCO2 + - name: SW + description: "system clock and trace clock switch\r Set and reset by software to select system clock and trace clock sources (sys_ck).\r Set by hardware in order to:\r -\tforce the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode\r -\tforce the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock\r others: reserved" + bit_offset: 0 + bit_size: 3 + enum: SW + - name: SWS + description: "system clock switch status\r Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset).\r others: reserved" + bit_offset: 3 + bit_size: 3 + enum: SW + - name: STOPWUCK + description: "system clock selection after a wakeup from system Stop\r Set and reset by software to select the system wakeup clock from system Stop.\r The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. 0: HSI selected as wakeup clock from system Stop (default after reset)\r STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10)." + bit_offset: 6 + bit_size: 1 + enum: STOPWUCK + - name: STOPKERWUCK + description: "kernel clock selection after a wakeup from system Stop\r Set and reset by software to select the kernel wakeup clock from system Stop." + bit_offset: 7 + bit_size: 1 + enum: STOPKERWUCK + - name: RTCPRE + description: "HSE division factor for RTC clock\r Set and cleared by software to divide the HSE to generate a clock for RTC.\r Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source.\r ..." + bit_offset: 8 + bit_size: 6 + - name: TIMPRE + description: "timers clocks prescaler selection\r This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains." + bit_offset: 15 + bit_size: 1 + enum: TIMPRE + - name: MCO1PRE + description: "MCO1 prescaler\r Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." + bit_offset: 18 + bit_size: 4 + - name: MCO1 + description: "Microcontroller clock output 1\r Set and cleared by software. Clock source selection may generate glitches on MCO1.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" + bit_offset: 22 + bit_size: 3 + enum: MCO1 + - name: MCO2PRE + description: "MCO2 prescaler\r Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." + bit_offset: 25 + bit_size: 4 + - name: MCO2 + description: "microcontroller clock output 2\r Set and cleared by software. Clock source selection may generate glitches on MCO2.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" + bit_offset: 29 + bit_size: 3 + enum: MCO2 fieldset/CFGR2: description: RCC CPU domain clock configuration register 2 fields: - - name: HPRE - description: "AHB prescaler\r Set and reset by software to control the division factor of rcc_hclk. Changing\r this division ratio has an impact on the frequency of all bus matrix clocks\r 0xxx: rcc_hclk = sys_ck (default after reset)" - bit_offset: 0 - bit_size: 4 - enum: HPRE - - name: PPRE1 - description: "APB low-speed prescaler (APB1)\r Set and reset by software to control the division factor of rcc_pclk1.\r The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write.\r 0xx: rcc_pclk1 = rcc_hclk1 (default after reset)" - bit_offset: 4 - bit_size: 3 - enum: PPRE - - name: PPRE2 - description: "APB high-speed prescaler (APB2)\r Set and reset by software to control APB high-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write.\r 0xx: rcc_pclk2 = rcc_hclk1" - bit_offset: 8 - bit_size: 3 - enum: PPRE - - name: PPRE3 - description: "APB low-speed prescaler (APB3)\r Set and reset by software to control APB low-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write.\r 0xx: rcc_pclk3 = rcc_hclk1" - bit_offset: 12 - bit_size: 3 - enum: PPRE - - name: AHB1DIS - description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1\r peripherals from RCC_AHB1ENR are used and when their clocks are disabled in\r RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks from\r RCC_AHB1ENR are off.\r enable control bits" - bit_offset: 16 - bit_size: 1 - - name: AHB2DIS - description: "AHB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2\r peripherals from RCC_AHB2ENR are used and when their clocks are disabled in\r RCC_AHB2ENR. When this bit is set, all the AHB2 peripherals clocks from\r RCC_AHB2ENR are off.\r enable control bits" - bit_offset: 17 - bit_size: 1 - - name: AHB4DIS - description: "AHB4 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB4\r peripherals from RCC_AHB4ENR are used and when their clocks are disabled in\r RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from\r RCC_AHB4ENR are off.\r enable control bits" - bit_offset: 19 - bit_size: 1 - - name: APB1DIS - description: "APB1 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB1\r peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR.\r When this bit is set, all the APB1 peripherals clocks are off, except for IWDG.\r control bits" - bit_offset: 20 - bit_size: 1 - - name: APB2DIS - description: "APB2 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB2\r peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is\r set, all the APB2 peripherals clocks are off.\r control bits" - bit_offset: 21 - bit_size: 1 - - name: APB3DIS - description: "APB3 clock disable value.Set and cleared by software\r This bit can be set in order to further reduce power consumption, when none of the APB3\r peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is\r set, all the APB3 peripherals clocks are off.\r control bits" - bit_offset: 22 - bit_size: 1 + - name: HPRE + description: "AHB prescaler\r Set and reset by software to control the division factor of rcc_hclk. Changing\r this division ratio has an impact on the frequency of all bus matrix clocks\r 0xxx: rcc_hclk = sys_ck (default after reset)" + bit_offset: 0 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: "APB low-speed prescaler (APB1)\r Set and reset by software to control the division factor of rcc_pclk1.\r The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write.\r 0xx: rcc_pclk1 = rcc_hclk1 (default after reset)" + bit_offset: 4 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: "APB high-speed prescaler (APB2)\r Set and reset by software to control APB high-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write.\r 0xx: rcc_pclk2 = rcc_hclk1" + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE3 + description: "APB low-speed prescaler (APB3)\r Set and reset by software to control APB low-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write.\r 0xx: rcc_pclk3 = rcc_hclk1" + bit_offset: 12 + bit_size: 3 + enum: PPRE + - name: AHB1DIS + description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1\r peripherals from RCC_AHB1ENR are used and when their clocks are disabled in\r RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks from\r RCC_AHB1ENR are off.\r enable control bits" + bit_offset: 16 + bit_size: 1 + - name: AHB2DIS + description: "AHB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2\r peripherals from RCC_AHB2ENR are used and when their clocks are disabled in\r RCC_AHB2ENR. When this bit is set, all the AHB2 peripherals clocks from\r RCC_AHB2ENR are off.\r enable control bits" + bit_offset: 17 + bit_size: 1 + - name: AHB4DIS + description: "AHB4 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB4\r peripherals from RCC_AHB4ENR are used and when their clocks are disabled in\r RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from\r RCC_AHB4ENR are off.\r enable control bits" + bit_offset: 19 + bit_size: 1 + - name: APB1DIS + description: "APB1 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB1\r peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR.\r When this bit is set, all the APB1 peripherals clocks are off, except for IWDG.\r control bits" + bit_offset: 20 + bit_size: 1 + - name: APB2DIS + description: "APB2 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB2\r peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is\r set, all the APB2 peripherals clocks are off.\r control bits" + bit_offset: 21 + bit_size: 1 + - name: APB3DIS + description: "APB3 clock disable value.Set and cleared by software\r This bit can be set in order to further reduce power consumption, when none of the APB3\r peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is\r set, all the APB3 peripherals clocks are off.\r control bits" + bit_offset: 22 + bit_size: 1 fieldset/CICR: description: RCC clock source interrupt clear register fields: - - name: LSIRDYC - description: "LSI ready interrupt clear\r Set by software to clear LSIRDYF.\r Reset by hardware when clear done." - bit_offset: 0 - bit_size: 1 - - name: LSERDYC - description: "LSE ready interrupt clear\r Set by software to clear LSERDYF.\r Reset by hardware when clear done." - bit_offset: 1 - bit_size: 1 - - name: CSIRDYC - description: "HSI ready interrupt clear\r Set by software to clear CSIRDYF.\r Reset by hardware when clear done." - bit_offset: 2 - bit_size: 1 - - name: HSIRDYC - description: "HSI ready interrupt clear\r Set by software to clear HSIRDYF.\r Reset by hardware when clear done." - bit_offset: 3 - bit_size: 1 - - name: HSERDYC - description: "HSE ready interrupt clear\r Set by software to clear HSERDYF.\r Reset by hardware when clear done." - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYC - description: "HSI48 ready interrupt clear\r Set by software to clear HSI48RDYF.\r Reset by hardware when clear done." - bit_offset: 5 - bit_size: 1 - - name: PLLRDYC - description: "PLL1 ready interrupt clear\r Set by software to clear PLL1RDYF.\r Reset by hardware when clear done." - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: HSECSSC - description: "HSE clock security system interrupt clear\r Set by software to clear HSECSSF.\r Reset by hardware when clear done." - bit_offset: 10 - bit_size: 1 + - name: LSIRDYC + description: "LSI ready interrupt clear\r Set by software to clear LSIRDYF.\r Reset by hardware when clear done." + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: "LSE ready interrupt clear\r Set by software to clear LSERDYF.\r Reset by hardware when clear done." + bit_offset: 1 + bit_size: 1 + - name: CSIRDYC + description: "HSI ready interrupt clear\r Set by software to clear CSIRDYF.\r Reset by hardware when clear done." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYC + description: "HSI ready interrupt clear\r Set by software to clear HSIRDYF.\r Reset by hardware when clear done." + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: "HSE ready interrupt clear\r Set by software to clear HSERDYF.\r Reset by hardware when clear done." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYC + description: "HSI48 ready interrupt clear\r Set by software to clear HSI48RDYF.\r Reset by hardware when clear done." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYC + description: "PLL1 ready interrupt clear\r Set by software to clear PLL1RDYF.\r Reset by hardware when clear done." + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: HSECSSC + description: "HSE clock security system interrupt clear\r Set by software to clear HSECSSF.\r Reset by hardware when clear done." + bit_offset: 10 + bit_size: 1 fieldset/CIER: description: RCC clock source interrupt enable register fields: - - name: LSIRDYIE - description: "LSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization." - bit_offset: 0 - bit_size: 1 - - name: LSERDYIE - description: "LSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization." - bit_offset: 1 - bit_size: 1 - - name: CSIRDYIE - description: "CSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization." - bit_offset: 2 - bit_size: 1 - - name: HSIRDYIE - description: "HSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization." - bit_offset: 3 - bit_size: 1 - - name: HSERDYIE - description: "HSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization." - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYIE - description: "HSI48 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization." - bit_offset: 5 - bit_size: 1 - - name: PLLRDYIE - description: "PLL1 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by PLL1 lock." - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 + - name: LSIRDYIE + description: "LSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization." + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: "LSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization." + bit_offset: 1 + bit_size: 1 + - name: CSIRDYIE + description: "CSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYIE + description: "HSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization." + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: "HSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYIE + description: "HSI48 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYIE + description: "PLL1 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by PLL1 lock." + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 fieldset/CIFR: description: RCC clock source interrupt flag register fields: - - name: LSIRDYF - description: "LSI ready interrupt flag\r Reset by software by writing LSIRDYC bit.\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set." - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: "LSE ready interrupt flag\r Reset by software by writing LSERDYC bit.\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set." - bit_offset: 1 - bit_size: 1 - - name: CSIRDYF - description: "CSI ready interrupt flag\r Reset by software by writing CSIRDYC bit.\r Set by hardware when the CSI clock becomes stable and CSIRDYIE is set." - bit_offset: 2 - bit_size: 1 - - name: HSIRDYF - description: "HSI ready interrupt flag\r Reset by software by writing HSIRDYC bit.\r Set by hardware when the HSI clock becomes stable and HSIRDYIE is set." - bit_offset: 3 - bit_size: 1 - - name: HSERDYF - description: "HSE ready interrupt flag\r Reset by software by writing HSERDYC bit.\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set." - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYF - description: "HSI48 ready interrupt flag\r Reset by software by writing HSI48RDYC bit.\r Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set." - bit_offset: 5 - bit_size: 1 - - name: PLLRDYF - description: "PLL1 ready interrupt flag\r Reset by software by writing PLL1RDYC bit.\r Set by hardware when the PLL1 locks and PLL1RDYIE is set." - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: HSECSSF - description: "HSE clock security system interrupt flag\r Reset by software by writing HSECSSC bit.\r Set by hardware in case of HSE clock failure." - bit_offset: 10 - bit_size: 1 + - name: LSIRDYF + description: "LSI ready interrupt flag\r Reset by software by writing LSIRDYC bit.\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set." + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: "LSE ready interrupt flag\r Reset by software by writing LSERDYC bit.\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set." + bit_offset: 1 + bit_size: 1 + - name: CSIRDYF + description: "CSI ready interrupt flag\r Reset by software by writing CSIRDYC bit.\r Set by hardware when the CSI clock becomes stable and CSIRDYIE is set." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYF + description: "HSI ready interrupt flag\r Reset by software by writing HSIRDYC bit.\r Set by hardware when the HSI clock becomes stable and HSIRDYIE is set." + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: "HSE ready interrupt flag\r Reset by software by writing HSERDYC bit.\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYF + description: "HSI48 ready interrupt flag\r Reset by software by writing HSI48RDYC bit.\r Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYF + description: "PLL1 ready interrupt flag\r Reset by software by writing PLL1RDYC bit.\r Set by hardware when the PLL1 locks and PLL1RDYIE is set." + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: HSECSSF + description: "HSE clock security system interrupt flag\r Reset by software by writing HSECSSC bit.\r Set by hardware in case of HSE clock failure." + bit_offset: 10 + bit_size: 1 fieldset/CR: description: RCC clock control register fields: - - name: HSION - description: "HSI clock enable\r Set and cleared by software.\r Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source.\r This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." - bit_offset: 0 - bit_size: 1 - - name: HSIRDY - description: "HSI clock ready flag\r Set by hardware to indicate that the HSI oscillator is stable." - bit_offset: 1 - bit_size: 1 - - name: HSIKERON - description: "HSI clock enable in Stop mode\r Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION." - bit_offset: 2 - bit_size: 1 - - name: HSIDIV - description: "HSI clock divider\r Set and reset by software.\r These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The\r HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored." - bit_offset: 3 - bit_size: 2 - enum: HSIDIV - - name: HSIDIVF - description: "HSI divider flag\r Set and reset by hardware.\r As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the\r current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV." - bit_offset: 5 - bit_size: 1 - - name: CSION - description: "CSI clock enable\r Set and reset by software to enable/disable CSI clock for system and/or peripheral.\r Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." - bit_offset: 8 - bit_size: 1 - - name: CSIRDY - description: "CSI clock ready flag\r Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request)." - bit_offset: 9 - bit_size: 1 - - name: CSIKERON - description: "CSI clock enable in Stop mode\r Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION." - bit_offset: 10 - bit_size: 1 - - name: HSI48ON - description: "HSI48 clock enable\r Set by software and cleared by software or by the hardware when the system enters to Stop\r or Standby mode." - bit_offset: 12 - bit_size: 1 - - name: HSI48RDY - description: "HSI48 clock ready flag\r Set by hardware to indicate that the HSI48 oscillator is stable." - bit_offset: 13 - bit_size: 1 - - name: HSEON - description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE when entering Stop or Standby mode.\r This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the\r HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable." - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: "HSE clock bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device.\r The HSEBYP bit can be written only if the HSE oscillator is disabled." - bit_offset: 18 - bit_size: 1 - - name: HSECSSON - description: "HSE clock security system enable\r Set by software to enable clock security system on HSE.\r This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected." - bit_offset: 19 - bit_size: 1 - - name: HSEEXT - description: "external high speed clock type in Bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled." - bit_offset: 20 - bit_size: 1 - enum: HSEEXT - - name: PLLON - description: "PLL1 enable\r Set and cleared by software to enable PLL1.\r Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents\r writing this bit to 0, if the PLL1 output is used as the system clock." - bit_offset: 24 - bit_size: 1 - array: - len: 3 - stride: 2 - - name: PLLRDY - description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked." - bit_offset: 25 - bit_size: 1 - array: - len: 3 - stride: 2 + - name: HSION + description: "HSI clock enable\r Set and cleared by software.\r Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source.\r This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: "HSI clock ready flag\r Set by hardware to indicate that the HSI oscillator is stable." + bit_offset: 1 + bit_size: 1 + - name: HSIKERON + description: "HSI clock enable in Stop mode\r Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION." + bit_offset: 2 + bit_size: 1 + - name: HSIDIV + description: "HSI clock divider\r Set and reset by software.\r These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The\r HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored." + bit_offset: 3 + bit_size: 2 + enum: HSIDIV + - name: HSIDIVF + description: "HSI divider flag\r Set and reset by hardware.\r As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the\r current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV." + bit_offset: 5 + bit_size: 1 + - name: CSION + description: "CSI clock enable\r Set and reset by software to enable/disable CSI clock for system and/or peripheral.\r Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." + bit_offset: 8 + bit_size: 1 + - name: CSIRDY + description: "CSI clock ready flag\r Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request)." + bit_offset: 9 + bit_size: 1 + - name: CSIKERON + description: "CSI clock enable in Stop mode\r Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION." + bit_offset: 10 + bit_size: 1 + - name: HSI48ON + description: "HSI48 clock enable\r Set by software and cleared by software or by the hardware when the system enters to Stop\r or Standby mode." + bit_offset: 12 + bit_size: 1 + - name: HSI48RDY + description: "HSI48 clock ready flag\r Set by hardware to indicate that the HSI48 oscillator is stable." + bit_offset: 13 + bit_size: 1 + - name: HSEON + description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE when entering Stop or Standby mode.\r This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the\r HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable." + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: "HSE clock bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device.\r The HSEBYP bit can be written only if the HSE oscillator is disabled." + bit_offset: 18 + bit_size: 1 + - name: HSECSSON + description: "HSE clock security system enable\r Set by software to enable clock security system on HSE.\r This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected." + bit_offset: 19 + bit_size: 1 + - name: HSEEXT + description: "external high speed clock type in Bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled." + bit_offset: 20 + bit_size: 1 + enum: HSEEXT + - name: PLLON + description: "PLL1 enable\r Set and cleared by software to enable PLL1.\r Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents\r writing this bit to 0, if the PLL1 output is used as the system clock." + bit_offset: 24 + bit_size: 1 + array: + len: 3 + stride: 2 + - name: PLLRDY + description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked." + bit_offset: 25 + bit_size: 1 + array: + len: 3 + stride: 2 fieldset/CRRCR: description: RCC clock recovery RC register fields: - - name: HSI48CAL - description: "Internal RC 48 MHz clock calibration\r Set by hardware by option-byte loading during system reset NRESET. Read-only." - bit_offset: 0 - bit_size: 10 + - name: HSI48CAL + description: "Internal RC 48 MHz clock calibration\r Set by hardware by option-byte loading during system reset NRESET. Read-only." + bit_offset: 0 + bit_size: 10 fieldset/CSICFGR: description: RCC CSI calibration register fields: - - name: CSICAL - description: "CSI clock calibration\r Set by hardware by option byte loading during system reset NRESET. Adjusted by software through trimming bits CSITRIM.\r This field represents the sum of engineering option byte calibration value and CSITRIM bits value." - bit_offset: 0 - bit_size: 8 - - name: CSITRIM - description: "CSI clock trimming\r Set by software to adjust calibration.\r CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_OPT) in order to form the calibration trimming value.\r CSICAL = CSITRIM + FLASH_CSI_OPT.\r Note: The reset value of the field is 0x20." - bit_offset: 16 - bit_size: 6 + - name: CSICAL + description: "CSI clock calibration\r Set by hardware by option byte loading during system reset NRESET. Adjusted by software through trimming bits CSITRIM.\r This field represents the sum of engineering option byte calibration value and CSITRIM bits value." + bit_offset: 0 + bit_size: 8 + - name: CSITRIM + description: "CSI clock trimming\r Set by software to adjust calibration.\r CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_OPT) in order to form the calibration trimming value.\r CSICAL = CSITRIM + FLASH_CSI_OPT.\r Note: The reset value of the field is 0x20." + bit_offset: 16 + bit_size: 6 fieldset/HSICFGR: description: RCC HSI calibration register fields: - - name: HSICAL - description: "HSI clock calibration\r Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM.\r This field represents the sum of engineering option byte calibration value and HSITRIM bits value." - bit_offset: 0 - bit_size: 12 - - name: HSITRIM - description: "HSI clock trimming\r Set by software to adjust calibration.\r HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_OPT) in order to form the calibration trimming value.\r HSICAL = HSITRIM + FLASH_HSI_OPT.\r After a change of HSITRIM it takes one system clock cycle before the new HSITRIM value is updated\r Note: The reset value of the field is 0x40." - bit_offset: 16 - bit_size: 7 + - name: HSICAL + description: "HSI clock calibration\r Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM.\r This field represents the sum of engineering option byte calibration value and HSITRIM bits value." + bit_offset: 0 + bit_size: 12 + - name: HSITRIM + description: "HSI clock trimming\r Set by software to adjust calibration.\r HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_OPT) in order to form the calibration trimming value.\r HSICAL = HSITRIM + FLASH_HSI_OPT.\r After a change of HSITRIM it takes one system clock cycle before the new HSITRIM value is updated\r Note: The reset value of the field is 0x40." + bit_offset: 16 + bit_size: 7 fieldset/PLLCFGR: description: RCC PLL clock source selection register fields: - - name: PLLSRC - description: "DIVMx and PLLs clock source selection\r Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled.\r In order to save power, when no PLL is used, the value of PLL1SRC must be set to '00'. 00: no clock send to DIVMx divider and PLLs (default after reset)." - bit_offset: 0 - bit_size: 2 - enum: PLLSRC - - name: PLLRGE - description: "PLL1 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1." - bit_offset: 2 - bit_size: 2 - enum: PLLRGE - - name: PLLFRACEN - description: "PLL1 fractional latch enable\r Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator.\r In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator." - bit_offset: 4 - bit_size: 1 - - name: PLLVCOSEL - description: "PLL1 VCO selection\r Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1." - bit_offset: 5 - bit_size: 1 - enum: PLLVCOSEL - - name: DIVM - description: "prescaler for PLL1\r Set and cleared by software to configure the prescaler of the PLL1.\r The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1).\r In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0.\r ...\r ..." - bit_offset: 8 - bit_size: 6 - - name: PLLPEN - description: "PLL1 DIVP divider output enable\r Set and reset by software to enable the pll1_p_ck output of the PLL1.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled." - bit_offset: 16 - bit_size: 1 - - name: PLLQEN - description: "PLL1 DIVQ divider output enable\r Set and reset by software to enable the pll1_q_ck output of the PLL1.\r In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." - bit_offset: 17 - bit_size: 1 - - name: PLLREN - description: "PLL1 DIVR divider output enable\r Set and reset by software to enable the pll1_r_ck output of the PLL1.\r To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." - bit_offset: 18 - bit_size: 1 + - name: PLLSRC + description: "DIVMx and PLLs clock source selection\r Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled.\r In order to save power, when no PLL is used, the value of PLL1SRC must be set to '00'. 00: no clock send to DIVMx divider and PLLs (default after reset)." + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: PLLRGE + description: "PLL1 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1." + bit_offset: 2 + bit_size: 2 + enum: PLLRGE + - name: PLLFRACEN + description: "PLL1 fractional latch enable\r Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator.\r In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator." + bit_offset: 4 + bit_size: 1 + - name: PLLVCOSEL + description: "PLL1 VCO selection\r Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1." + bit_offset: 5 + bit_size: 1 + enum: PLLVCOSEL + - name: DIVM + description: "prescaler for PLL1\r Set and cleared by software to configure the prescaler of the PLL1.\r The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1).\r In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0.\r ...\r ..." + bit_offset: 8 + bit_size: 6 + - name: PLLPEN + description: "PLL1 DIVP divider output enable\r Set and reset by software to enable the pll1_p_ck output of the PLL1.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled." + bit_offset: 16 + bit_size: 1 + - name: PLLQEN + description: "PLL1 DIVQ divider output enable\r Set and reset by software to enable the pll1_q_ck output of the PLL1.\r In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." + bit_offset: 17 + bit_size: 1 + - name: PLLREN + description: "PLL1 DIVR divider output enable\r Set and reset by software to enable the pll1_r_ck output of the PLL1.\r To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." + bit_offset: 18 + bit_size: 1 fieldset/PLLDIVR: description: RCC PLL1 dividers register fields: - - name: PLLN - description: "Multiplication factor for PLL1VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved" - bit_offset: 0 - bit_size: 9 - - name: PLLP - description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..." - bit_offset: 9 - bit_size: 7 - - name: PLLQ - description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." - bit_offset: 16 - bit_size: 7 - - name: PLLR - description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." - bit_offset: 24 - bit_size: 7 + - name: PLLN + description: "Multiplication factor for PLL1VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved" + bit_offset: 0 + bit_size: 9 + - name: PLLP + description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..." + bit_offset: 9 + bit_size: 7 + - name: PLLQ + description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." + bit_offset: 16 + bit_size: 7 + - name: PLLR + description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." + bit_offset: 24 + bit_size: 7 fieldset/PLLFRACR: description: RCC PLL1 fractional divider register fields: - - name: PLLFRACN - description: "fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:\r * 128 to 560 MHz if PLL1VCOSEL = 0\r * \t150 to 420 MHz if PLL1VCOSEL = 1\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with\r * \tPLL1N between 8 and 420\r * \tPLL1FRACN can be between 0 and 213- 1\r * \tThe input frequency Fref1_ck must be between 1 and 16 MHz.\r To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r * \tSet the bit PLL1FRACEN to 0\r * \tWrite the new fractional value into PLL1FRACN\r * \tSet the bit PLL1FRACEN to 1" - bit_offset: 3 - bit_size: 13 + - name: PLLFRACN + description: "fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:\r * 128 to 560 MHz if PLL1VCOSEL = 0\r * \t150 to 420 MHz if PLL1VCOSEL = 1\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with\r * \tPLL1N between 8 and 420\r * \tPLL1FRACN can be between 0 and 213- 1\r * \tThe input frequency Fref1_ck must be between 1 and 16 MHz.\r To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r * \tSet the bit PLL1FRACEN to 0\r * \tWrite the new fractional value into PLL1FRACN\r * \tSet the bit PLL1FRACEN to 1" + bit_offset: 3 + bit_size: 13 fieldset/PRIVCFGR: description: RCC privilege configuration register fields: - - name: SPRIV - description: "RCC secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access." - bit_offset: 0 - bit_size: 1 - enum: SPRIV - - name: NSPRIV - description: "RCC non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure." - bit_offset: 1 - bit_size: 1 - enum: NSPRIV + - name: SPRIV + description: "RCC secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access." + bit_offset: 0 + bit_size: 1 + enum: SPRIV + - name: NSPRIV + description: "RCC non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure." + bit_offset: 1 + bit_size: 1 + enum: NSPRIV fieldset/RSR: description: RCC reset status register fields: - - name: RMVF - description: "remove reset flag\r Set and reset by software to reset the value of the reset flags." - bit_offset: 23 - bit_size: 1 - - name: PINRSTF - description: "pin reset flag (NRST)\r Reset by software by writing the RMVF bit.\r Set by hardware when a reset from pin occurs." - bit_offset: 26 - bit_size: 1 - - name: BORRSTF - description: "BOR reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a BOR reset occurs (pwr_bor_rst)." - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: "system reset from CPU reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M33." - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: "independent watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when an independent watchdog reset occurs." - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: "window watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a window watchdog reset occurs." - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: "Low-power reset flag\r Set by hardware when a reset occurs due to Stop or Standby mode entry, whereas the corresponding nRST_STOP, nRST_STBY option bit is cleared.\r Cleared by writing to the RMVF bit." - bit_offset: 31 - bit_size: 1 + - name: RMVF + description: "remove reset flag\r Set and reset by software to reset the value of the reset flags." + bit_offset: 23 + bit_size: 1 + - name: PINRSTF + description: "pin reset flag (NRST)\r Reset by software by writing the RMVF bit.\r Set by hardware when a reset from pin occurs." + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: "BOR reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a BOR reset occurs (pwr_bor_rst)." + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: "system reset from CPU reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M33." + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: "independent watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when an independent watchdog reset occurs." + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: "window watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a window watchdog reset occurs." + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: "Low-power reset flag\r Set by hardware when a reset occurs due to Stop or Standby mode entry, whereas the corresponding nRST_STOP, nRST_STBY option bit is cleared.\r Cleared by writing to the RMVF bit." + bit_offset: 31 + bit_size: 1 fieldset/SECCFGR: description: RCC secure configuration register fields: - - name: HSISEC - description: "HSI clock configuration and status bits security\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - enum: SEC - - name: HSESEC - description: "HSE clock configuration bits, status bits and HSE_CSS security\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - enum: SEC - - name: CSISEC - description: "CSI clock configuration and status bits security\r Set and reset by software." - bit_offset: 2 - bit_size: 1 - enum: SEC - - name: LSISEC - description: "LSI clock configuration and status bits security\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - enum: SEC - - name: LSESEC - description: "LSE clock configuration and status bits security\r Set and reset by software." - bit_offset: 4 - bit_size: 1 - enum: SEC - - name: SYSCLKSEC - description: "SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - enum: SEC - - name: PRESCSEC - description: "AHBx/APBx prescaler configuration bits security\r Set and reset by software." - bit_offset: 6 - bit_size: 1 - enum: SEC - - name: PLLSEC - description: "PLL1 clock configuration and status bits security\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - array: - len: 3 - stride: 1 - enum: SEC - - name: HSI48SEC - description: "HSI48 clock configuration and status bits security\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - enum: SEC - - name: RMVFSEC - description: "Remove reset flag security\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - enum: SEC - - name: CKPERSELSEC - description: "per_ck selection security\r Set and reset by software." - bit_offset: 13 - bit_size: 1 - enum: SEC + - name: HSISEC + description: "HSI clock configuration and status bits security\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + enum: SEC + - name: HSESEC + description: "HSE clock configuration bits, status bits and HSE_CSS security\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + enum: SEC + - name: CSISEC + description: "CSI clock configuration and status bits security\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + enum: SEC + - name: LSISEC + description: "LSI clock configuration and status bits security\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + enum: SEC + - name: LSESEC + description: "LSE clock configuration and status bits security\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + enum: SEC + - name: SYSCLKSEC + description: "SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + enum: SEC + - name: PRESCSEC + description: "AHBx/APBx prescaler configuration bits security\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + enum: SEC + - name: PLLSEC + description: "PLL1 clock configuration and status bits security\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: SEC + - name: HSI48SEC + description: "HSI48 clock configuration and status bits security\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + enum: SEC + - name: RMVFSEC + description: "Remove reset flag security\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + enum: SEC + - name: CKPERSELSEC + description: "per_ck selection security\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + enum: SEC enum/ADCDACSEL: bit_size: 3 variants: - - name: HCLK - description: rcc_hclk selected as kernel clock (default after reset) - value: 0 - - name: SYSCLK - description: sys_ck selected as kernel clock - value: 1 - - name: PLL2_R - description: pll2_r_ck selected as kernel clock - value: 2 - - name: HSE - description: hse_ck selected as kernel clock - value: 3 - - name: HSI_KER - description: hsi_ker_ck selected as kernel clock - value: 4 - - name: CSI_KER - description: csi_ker_ck selected as kernel clock - value: 5 + - name: HCLK + description: rcc_hclk selected as kernel clock (default after reset) + value: 0 + - name: SYSCLK + description: sys_ck selected as kernel clock + value: 1 + - name: PLL2_R + description: pll2_r_ck selected as kernel clock + value: 2 + - name: HSE + description: hse_ck selected as kernel clock + value: 3 + - name: HSI_KER + description: hsi_ker_ck selected as kernel clock + value: 4 + - name: CSI_KER + description: csi_ker_ck selected as kernel clock + value: 5 enum/CECSEL: bit_size: 2 variants: - - name: LSE - description: lse_ck selected as kernel clock (default after reset) - value: 0 - - name: LSI_KER - description: lsi_ker_ck selected as kernel clock - value: 1 - - name: CSI_KER_DIV_122 - description: csi_ker_ck/122 selected as kernel clock - value: 2 + - name: LSE + description: lse_ck selected as kernel clock (default after reset) + value: 0 + - name: LSI_KER + description: lsi_ker_ck selected as kernel clock + value: 1 + - name: CSI_KER_DIV_122 + description: csi_ker_ck/122 selected as kernel clock + value: 2 enum/CKPERSEL: bit_size: 2 variants: - - name: HSI - description: hsi_ker_ck selected as kernel clock (default after reset) - value: 0 - - name: CSI - description: csi_ker_ck selected as kernel clock - value: 1 - - name: HSE - description: hse_ck selected as kernel clock - value: 2 + - name: HSI + description: hsi_ker_ck selected as kernel clock (default after reset) + value: 0 + - name: CSI + description: csi_ker_ck selected as kernel clock + value: 1 + - name: HSE + description: hse_ck selected as kernel clock + value: 2 enum/DACSEL: bit_size: 1 variants: - - name: DAC_HOLD - description: dac_hold_ck selected as kernel clock (default after reset) - value: 0 - - name: DAC_HOLD_2 - description: dac_hold_ck selected as kernel clock - value: 1 + - name: DAC_HOLD + description: dac_hold_ck selected as kernel clock (default after reset) + value: 0 + - name: DAC_HOLD_2 + description: dac_hold_ck selected as kernel clock + value: 1 enum/FDCANSEL: bit_size: 2 variants: - - name: HSE - description: hse_ck selected as kernel clock (default after reset) - value: 0 - - name: PLL1_Q - description: pll1_q_ck selected as kernel clock - value: 1 - - name: PLL2_Q - description: pll2_q_ck selected as kernel clock - value: 2 + - name: HSE + description: hse_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock + value: 1 + - name: PLL2_Q + description: pll2_q_ck selected as kernel clock + value: 2 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: sys_ck not divided - value: 0 - - name: Div2 - description: sys_ck divided by 2 - value: 8 - - name: Div4 - description: sys_ck divided by 4 - value: 9 - - name: Div8 - description: sys_ck divided by 8 - value: 10 - - name: Div16 - description: sys_ck divided by 16 - value: 11 - - name: Div64 - description: sys_ck divided by 64 - value: 12 - - name: Div128 - description: sys_ck divided by 128 - value: 13 - - name: Div256 - description: sys_ck divided by 256 - value: 14 - - name: Div512 - description: sys_ck divided by 512 - value: 15 + - name: Div1 + description: sys_ck not divided + value: 0 + - name: Div2 + description: sys_ck divided by 2 + value: 8 + - name: Div4 + description: sys_ck divided by 4 + value: 9 + - name: Div8 + description: sys_ck divided by 8 + value: 10 + - name: Div16 + description: sys_ck divided by 16 + value: 11 + - name: Div64 + description: sys_ck divided by 64 + value: 12 + - name: Div128 + description: sys_ck divided by 128 + value: 13 + - name: Div256 + description: sys_ck divided by 256 + value: 14 + - name: Div512 + description: sys_ck divided by 512 + value: 15 enum/HSEEXT: bit_size: 1 variants: - - name: Analog - description: HSE in analog mode (default after reset) - value: 0 - - name: Digital - description: HSE in digital mode - value: 1 + - name: Analog + description: HSE in analog mode (default after reset) + value: 0 + - name: Digital + description: HSE in digital mode + value: 1 enum/HSIDIV: bit_size: 2 variants: - - name: Div1 - description: No division - value: 0 - - name: Div2 - description: Division by 2 - value: 1 - - name: Div4 - description: Division by 4 - value: 2 - - name: Div8 - description: Division by 8 - value: 3 + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 enum/ICSEL: bit_size: 2 variants: - - name: RCC_PCLK1 - description: rcc_pclk1 selected as peripheral clock - value: 0 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 1 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 2 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 3 + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 2 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 3 enum/LPTIMSEL: bit_size: 3 variants: - - name: RCC_PCLK3 - description: rcc_pclk3 selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 2 - - name: LSE - description: LSE selected as peripheral clock - value: 3 - - name: LSI - description: LSI selected as peripheral clock - value: 4 - - name: PER - description: PER selected as peripheral clock - value: 5 + - name: RCC_PCLK3 + description: rcc_pclk3 selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 2 + - name: LSE + description: LSE selected as peripheral clock + value: 3 + - name: LSI + description: LSI selected as peripheral clock + value: 4 + - name: PER + description: PER selected as peripheral clock + value: 5 enum/LPUARTSEL: bit_size: 3 variants: - - name: RCC_PCLK3 - description: rcc_pclk3 selected as kernel clock (default after reset) - value: 0 - - name: PLL2_Q - description: pll2_q_ck selected as kernel clock - value: 1 - - name: PLL3_1 - description: pll3_q_ck selected as kernel clock - value: 2 - - name: HSI_KER - description: hsi_ker_ck selected as kernel clock - value: 3 - - name: CSI_KER - description: csi_ker_ck selected as kernel clock - value: 4 - - name: LSE - description: lse_ck selected as kernel clock - value: 5 + - name: RCC_PCLK3 + description: rcc_pclk3 selected as kernel clock (default after reset) + value: 0 + - name: PLL2_Q + description: pll2_q_ck selected as kernel clock + value: 1 + - name: PLL3_1 + description: pll3_q_ck selected as kernel clock + value: 2 + - name: HSI_KER + description: hsi_ker_ck selected as kernel clock + value: 3 + - name: CSI_KER + description: csi_ker_ck selected as kernel clock + value: 4 + - name: LSE + description: lse_ck selected as kernel clock + value: 5 enum/LSCOSEL: bit_size: 1 variants: - - name: LSI - description: LSI clock selected - value: 0 - - name: LSE - description: LSE clock selected - value: 1 + - name: LSI + description: LSI clock selected + value: 0 + - name: LSE + description: LSE clock selected + value: 1 enum/LSEDRV: bit_size: 2 variants: - - name: Lowest - description: Lowest LSE oscillator driving capability - value: 0 - - name: MediumLow - description: Medium low LSE oscillator driving capability - value: 1 - - name: MediumHigh - description: Medium high LSE oscillator driving capability - value: 2 - - name: Highest - description: Highest LSE oscillator driving capability - value: 3 + - name: Lowest + description: Lowest LSE oscillator driving capability + value: 0 + - name: MediumLow + description: Medium low LSE oscillator driving capability + value: 1 + - name: MediumHigh + description: Medium high LSE oscillator driving capability + value: 2 + - name: Highest + description: Highest LSE oscillator driving capability + value: 3 enum/LSEEXT: bit_size: 1 variants: - - name: Analog - description: LSE in analog mode (default after Backup domain reset) - value: 0 - - name: Digital - description: LSE in digital mode (do not use if RTC is active). - value: 1 + - name: Analog + description: LSE in analog mode (default after Backup domain reset) + value: 0 + - name: Digital + description: LSE in digital mode (do not use if RTC is active). + value: 1 enum/MCO1: bit_size: 3 variants: - - name: HSI - description: HSI selected for micro-controller clock output - value: 0 - - name: LSE - description: LSE selected for micro-controller clock output - value: 1 - - name: HSE - description: HSE selected for micro-controller clock output - value: 2 - - name: PLL1_Q - description: pll1_q selected for micro-controller clock output - value: 3 - - name: HSI48 - description: HSI48 selected for micro-controller clock output - value: 4 + - name: HSI + description: HSI selected for micro-controller clock output + value: 0 + - name: LSE + description: LSE selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_Q + description: pll1_q selected for micro-controller clock output + value: 3 + - name: HSI48 + description: HSI48 selected for micro-controller clock output + value: 4 enum/MCO2: bit_size: 3 variants: - - name: SYSCLK - description: System clock selected for micro-controller clock output - value: 0 - - name: PLL2_P - description: pll2_p selected for micro-controller clock output - value: 1 - - name: HSE - description: HSE selected for micro-controller clock output - value: 2 - - name: PLL1_P - description: pll1_p selected for micro-controller clock output - value: 3 - - name: CSI - description: CSI selected for micro-controller clock output - value: 4 - - name: LSI - description: LSI selected for micro-controller clock output - value: 5 + - name: SYSCLK + description: System clock selected for micro-controller clock output + value: 0 + - name: PLL2_P + description: pll2_p selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_P + description: pll1_p selected for micro-controller clock output + value: 3 + - name: CSI + description: CSI selected for micro-controller clock output + value: 4 + - name: LSI + description: LSI selected for micro-controller clock output + value: 5 enum/NSPRIV: bit_size: 1 variants: - - name: B_0x0 - description: Read and write to RCC non-secure functions can be done by privileged or unprivileged access. - value: 0 - - name: B_0x1 - description: Read and write to RCC non-secure functions can be done by privileged access only - value: 1 + - name: B_0x0 + description: Read and write to RCC non-secure functions can be done by privileged or unprivileged access. + value: 0 + - name: B_0x1 + description: Read and write to RCC non-secure functions can be done by privileged access only + value: 1 enum/OCTOSPISEL: bit_size: 2 variants: - - name: RCC_HCLK4 - description: rcc_hclk4 selected as kernel clock (default after reset) - value: 0 - - name: PLL1_Q - description: pll1_q_ck selected as kernel clock - value: 1 - - name: PLL2_R - description: pll2_r_ck selected as kernel clock - value: 2 - - name: PER_CLK - description: per_ck selected as kernel clock - value: 3 + - name: RCC_HCLK4 + description: rcc_hclk4 selected as kernel clock (default after reset) + value: 0 + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock + value: 1 + - name: PLL2_R + description: pll2_r_ck selected as kernel clock + value: 2 + - name: PER_CLK + description: per_ck selected as kernel clock + value: 3 enum/PLLRGE: bit_size: 2 variants: - - name: Range1 - description: Frequency is between 1 and 2 MHz - value: 0 - - name: Range2 - description: Frequency is between 2 and 4 MHz - value: 1 - - name: Range4 - description: Frequency is between 4 and 8 MHz - value: 2 - - name: Range8 - description: Frequency is between 8 and 16 MHz - value: 3 + - name: Range1 + description: Frequency is between 1 and 2 MHz + value: 0 + - name: Range2 + description: Frequency is between 2 and 4 MHz + value: 1 + - name: Range4 + description: Frequency is between 4 and 8 MHz + value: 2 + - name: Range8 + description: Frequency is between 8 and 16 MHz + value: 3 enum/PLLSRC: bit_size: 2 variants: - - name: None - description: no clock send to DIVMx divider and PLLs (default after reset) - value: 0 - - name: HSI - description: HSI selected as PLL clock (hsi_ck) - value: 1 - - name: CSI - description: CSI selected as PLL clock (csi_ck) - value: 2 - - name: HSE - description: HSE selected as PLL clock (hse_ck) - value: 3 + - name: None + description: no clock send to DIVMx divider and PLLs (default after reset) + value: 0 + - name: HSI + description: HSI selected as PLL clock (hsi_ck) + value: 1 + - name: CSI + description: CSI selected as PLL clock (csi_ck) + value: 2 + - name: HSE + description: HSE selected as PLL clock (hse_ck) + value: 3 enum/PLLVCOSEL: bit_size: 1 variants: - - name: WideVCO - description: VCO frequency range 192 to 836 MHz - value: 0 - - name: MediumVCO - description: VCO frequency range 150 to 420 MHz - value: 1 + - name: WideVCO + description: VCO frequency range 192 to 836 MHz + value: 0 + - name: MediumVCO + description: VCO frequency range 150 to 420 MHz + value: 1 enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: rcc_pclk3 = rcc_hclk1 / 1 - value: 0 - - name: Div2 - description: rcc_pclk3 = rcc_hclk1 / 2 - value: 4 - - name: Div4 - description: rcc_pclk3 = rcc_hclk1 / 4 - value: 5 - - name: Div8 - description: rcc_pclk3 = rcc_hclk1 / 8 - value: 6 - - name: Div16 - description: rcc_pclk3 = rcc_hclk1 / 16 - value: 7 + - name: Div1 + description: rcc_pclk3 = rcc_hclk1 / 1 + value: 0 + - name: Div2 + description: rcc_pclk3 = rcc_hclk1 / 2 + value: 4 + - name: Div4 + description: rcc_pclk3 = rcc_hclk1 / 4 + value: 5 + - name: Div8 + description: rcc_pclk3 = rcc_hclk1 / 8 + value: 6 + - name: Div16 + description: rcc_pclk3 = rcc_hclk1 / 16 + value: 7 enum/RNGSEL: bit_size: 2 variants: - - name: HSI48_KER - description: hsi48_ker_ck selected as kernel clock (default after reset) - value: 0 - - name: PLL1_Q - description: pll1_q_ck selected as kernel clock - value: 1 - - name: LSE - description: lse_ck selected as kernel clock - value: 2 - - name: LSI_KER - description: lsi_ker_ck selected as kernel clock - value: 3 + - name: HSI48_KER + description: hsi48_ker_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock + value: 1 + - name: LSE + description: lse_ck selected as kernel clock + value: 2 + - name: LSI_KER + description: lsi_ker_ck selected as kernel clock + value: 3 enum/RTCSEL: bit_size: 2 variants: - - name: None - description: no clock (default after Backup domain reset) - value: 0 - - name: LSE - description: LSE selected as RTC clock - value: 1 - - name: LSI - description: LSI selected as RTC clock - value: 2 - - name: HSE_DIV_RTCPRE - description: HSE divided by RTCPRE value selected as RTC clock - value: 3 + - name: NoClock + description: no clock (default after Backup domain reset) + value: 0 + - name: LSE + description: LSE selected as RTC clock + value: 1 + - name: LSI + description: LSI selected as RTC clock + value: 2 + - name: HSE_DIV_RTCPRE + description: HSE divided by RTCPRE value selected as RTC clock + value: 3 enum/SAISEL: bit_size: 3 variants: - - name: PLL1_Q - description: pll1_q_ck selected as kernel clock (default after reset) - value: 0 - - name: PLL2_P - description: pll2_p_ck selected as kernel clock - value: 1 - - name: PLL3_P - description: pll3_p_ck selected as kernel clock - value: 2 - - name: AUDIOCLK - description: AUDIOCLK selected as kernel clock - value: 3 - - name: PER - description: per_ck selected as kernel clock - value: 4 + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL2_P + description: pll2_p_ck selected as kernel clock + value: 1 + - name: PLL3_P + description: pll3_p_ck selected as kernel clock + value: 2 + - name: AUDIOCLK + description: AUDIOCLK selected as kernel clock + value: 3 + - name: PER + description: per_ck selected as kernel clock + value: 4 enum/SDMMCSEL: bit_size: 1 variants: - - name: PLL1_Q - description: pll1_q_ck selected as kernel clock (default after reset) - value: 0 - - name: PLL2_R - description: pll2_r_ck selected as kernel clock - value: 1 + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL2_R + description: pll2_r_ck selected as kernel clock + value: 1 enum/SEC: bit_size: 1 variants: - - name: NonSecure - description: non secure - value: 0 - - name: Secure - description: secure - value: 1 + - name: NonSecure + description: non secure + value: 0 + - name: Secure + description: secure + value: 1 enum/SPI1SEL: bit_size: 3 variants: - - name: PLL1_Q - description: pll1_q_ck selected as kernel clock (default after reset) - value: 0 - - name: PLL2_P - description: pll2_p_ck selected as kernel clock - value: 1 - - name: PLL3_P - description: pll3_p_ck selected as kernel clock - value: 2 - - name: AUDIOCLK - description: AUDIOCLK selected as kernel clock - value: 3 - - name: PER - description: per_ck selected as kernel clock - value: 4 + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL2_P + description: pll2_p_ck selected as kernel clock + value: 1 + - name: PLL3_P + description: pll3_p_ck selected as kernel clock + value: 2 + - name: AUDIOCLK + description: AUDIOCLK selected as kernel clock + value: 3 + - name: PER + description: per_ck selected as kernel clock + value: 4 enum/SPI2SEL: bit_size: 3 variants: - - name: PLL1_Q - description: pll1_q_ck selected as kernel clock (default after reset) - value: 0 - - name: PLL2_P - description: pll2_p_ck selected as kernel clock - value: 1 - - name: PLL3_P - description: pll3_p_ck selected as kernel clock - value: 2 - - name: AUDIOCLK - description: AUDIOCLK selected as kernel clock - value: 3 - - name: PER - description: per_ck selected as kernel clock - value: 4 + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL2_P + description: pll2_p_ck selected as kernel clock + value: 1 + - name: PLL3_P + description: pll3_p_ck selected as kernel clock + value: 2 + - name: AUDIOCLK + description: AUDIOCLK selected as kernel clock + value: 3 + - name: PER + description: per_ck selected as kernel clock + value: 4 enum/SPI3SEL: bit_size: 3 variants: - - name: PLL1_Q - description: pll1_q_ck selected as kernel clock (default after reset) - value: 0 - - name: PLL2_P - description: pll2_p_ck selected as kernel clock - value: 1 - - name: PLL3_P - description: pll3_p_ck selected as kernel clock - value: 2 - - name: AUDIOCLK - description: AUDIOCLK selected as kernel clock - value: 3 - - name: PER - description: per_ck selected as kernel clock - value: 4 + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL2_P + description: pll2_p_ck selected as kernel clock + value: 1 + - name: PLL3_P + description: pll3_p_ck selected as kernel clock + value: 2 + - name: AUDIOCLK + description: AUDIOCLK selected as kernel clock + value: 3 + - name: PER + description: per_ck selected as kernel clock + value: 4 enum/SPI4SEL: bit_size: 3 variants: - - name: RCC_PCLK2 - description: rcc_pclk2 selected as kernel clock (default after reset) - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: HSE - description: HSE selected as peripheral clock - value: 5 + - name: RCC_PCLK2 + description: rcc_pclk2 selected as kernel clock (default after reset) + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: HSE + description: HSE selected as peripheral clock + value: 5 enum/SPI5SEL: bit_size: 3 variants: - - name: RCC_PCLK3 - description: rcc_pclk3 selected as kernel clock (default after reset) - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: HSE - description: HSE selected as peripheral clock - value: 5 + - name: RCC_PCLK3 + description: rcc_pclk3 selected as kernel clock (default after reset) + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: HSE + description: HSE selected as peripheral clock + value: 5 enum/SPI6SEL: bit_size: 3 variants: - - name: RCC_PCLK4 - description: rcc_pclk4 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: HSE - description: HSE selected as peripheral clock - value: 5 + - name: RCC_PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: HSE + description: HSE selected as peripheral clock + value: 5 enum/SPRIV: bit_size: 1 variants: - - name: Any - description: Read and write to RCC secure functions can be done by privileged or unprivileged access. - value: 0 - - name: Privileged - description: Read and write to RCC secure functions can be done by privileged access only - value: 1 + - name: Any + description: Read and write to RCC secure functions can be done by privileged or unprivileged access. + value: 0 + - name: Privileged + description: Read and write to RCC secure functions can be done by privileged access only + value: 1 enum/STOPKERWUCK: bit_size: 1 variants: - - name: HSI - description: HSI selected as wakeup clock from system Stop (default after reset) - value: 0 - - name: CSI - description: CSI selected as wakeup clock from system Stop - value: 1 + - name: HSI + description: HSI selected as wakeup clock from system Stop (default after reset) + value: 0 + - name: CSI + description: CSI selected as wakeup clock from system Stop + value: 1 enum/STOPWUCK: bit_size: 1 variants: - - name: CSI - description: CSI selected as wakeup clock from system Stop - value: 1 + - name: CSI + description: CSI selected as wakeup clock from system Stop + value: 1 enum/SW: bit_size: 3 variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: CSI - description: CSI selected as system clock - value: 1 - - name: HSE - description: HSE selected as system clock - value: 2 - - name: PLL1 - description: PLL1 selected as system clock - value: 3 + - name: HSI + description: HSI selected as system clock + value: 0 + - name: CSI + description: CSI selected as system clock + value: 1 + - name: HSE + description: HSE selected as system clock + value: 2 + - name: PLL1 + description: PLL1 selected as system clock + value: 3 enum/SYSTICKSEL: bit_size: 2 variants: - - name: HCLK_DIV_8 - description: rcc_hclk/8 selected as clock source (default after reset) - value: 0 - - name: LSI_KER - description: "lsi_ker_ck[1] selected as clock source" - value: 1 - - name: LSE - description: "lse_ck[1] selected as clock source" - value: 2 + - name: HCLK_DIV_8 + description: rcc_hclk/8 selected as clock source (default after reset) + value: 0 + - name: LSI_KER + description: lsi_ker_ck[1] selected as clock source + value: 1 + - name: LSE + description: lse_ck[1] selected as clock source + value: 2 enum/TIMICSEL: bit_size: 1 variants: - - name: B_0x0 - description: No internal clock available for timers input capture (default after reset) - value: 0 - - name: B_0x1 - description: "hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture" - value: 1 + - name: B_0x0 + description: No internal clock available for timers input capture (default after reset) + value: 0 + - name: B_0x1 + description: hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture + value: 1 enum/TIMPRE: bit_size: 1 variants: - - name: DefaultX2 - description: "The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 (default after reset)" - value: 0 - - name: DefaultX4 - description: "The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2" - value: 1 + - name: DefaultX2 + description: The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 (default after reset) + value: 0 + - name: DefaultX4 + description: The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2 + value: 1 enum/UARTSEL: bit_size: 3 variants: - - name: RCC_PCLK1 - description: rcc_pclk1 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: LSE - description: LSE selected as peripheral clock - value: 5 + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 enum/USARTSEL: bit_size: 3 variants: - - name: RCC_PCLK2 - description: rcc_pclk2 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: LSE - description: LSE selected as peripheral clock - value: 5 + - name: RCC_PCLK2 + description: rcc_pclk2 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 enum/USBSEL: bit_size: 2 variants: - - name: DISABLE - description: Disable the kernel clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI48 - description: HSI48 selected as peripheral clock - value: 3 + - name: DISABLE + description: Disable the kernel clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI48 + description: HSI48 selected as peripheral clock + value: 3 diff --git a/data/registers/rcc_h50.yaml b/data/registers/rcc_h50.yaml index 9fb305f..0fcf371 100644 --- a/data/registers/rcc_h50.yaml +++ b/data/registers/rcc_h50.yaml @@ -1,1751 +1,1750 @@ ---- block/RCC: description: Reset and clock controller items: - - name: CR - description: RCC clock control register - byte_offset: 0 - fieldset: CR - - name: HSICFGR - description: RCC HSI calibration register - byte_offset: 16 - fieldset: HSICFGR - - name: CRRCR - description: RCC clock recovery RC register - byte_offset: 20 - fieldset: CRRCR - - name: CSICFGR - description: RCC CSI calibration register - byte_offset: 24 - fieldset: CSICFGR - - name: CFGR - description: RCC clock configuration register - byte_offset: 28 - fieldset: CFGR - - name: CFGR2 - description: RCC CPU domain clock configuration register 2 - byte_offset: 32 - fieldset: CFGR2 - - name: PLLCFGR - description: RCC PLL clock source selection register - array: - len: 2 - stride: 4 - byte_offset: 40 - fieldset: PLLCFGR - - name: PLLDIVR - description: RCC PLL1 dividers register - array: - len: 2 - stride: 8 - byte_offset: 52 - fieldset: PLLDIVR - - name: PLLFRACR - description: RCC PLL1 fractional divider register - array: - len: 2 - stride: 8 - byte_offset: 56 - fieldset: PLLFRACR - - name: CIER - description: RCC clock source interrupt enable register - byte_offset: 80 - fieldset: CIER - - name: CIFR - description: RCC clock source interrupt flag register - byte_offset: 84 - fieldset: CIFR - - name: CICR - description: RCC clock source interrupt clear register - byte_offset: 88 - fieldset: CICR - - name: AHB1RSTR - description: RCC AHB1 reset register - byte_offset: 96 - fieldset: AHB1RSTR - - name: AHB2RSTR - description: RCC AHB2 peripheral reset register - byte_offset: 100 - fieldset: AHB2RSTR - - name: APB1LRSTR - description: RCC APB1 peripheral low reset register - byte_offset: 116 - fieldset: APB1LRSTR - - name: APB1HRSTR - description: RCC APB1 peripheral high reset register - byte_offset: 120 - fieldset: APB1HRSTR - - name: APB2RSTR - description: RCC APB2 peripheral reset register - byte_offset: 124 - fieldset: APB2RSTR - - name: APB3RSTR - description: RCC APB3 peripheral reset register - byte_offset: 128 - fieldset: APB3RSTR - - name: AHB1ENR - description: RCC AHB1 peripherals clock register - byte_offset: 136 - fieldset: AHB1ENR - - name: AHB2ENR - description: RCC AHB2 peripheral clock register - byte_offset: 140 - fieldset: AHB2ENR - - name: APB1LENR - description: RCC APB1 peripheral clock register - byte_offset: 156 - fieldset: APB1LENR - - name: APB1HENR - description: RCC APB1 peripheral clock register - byte_offset: 160 - fieldset: APB1HENR - - name: APB2ENR - description: RCC APB2 peripheral clock register - byte_offset: 164 - fieldset: APB2ENR - - name: APB3ENR - description: RCC APB3 peripheral clock register - byte_offset: 168 - fieldset: APB3ENR - - name: AHB1LPENR - description: RCC AHB1 sleep clock register - byte_offset: 176 - fieldset: AHB1LPENR - - name: AHB2LPENR - description: RCC AHB2 sleep clock register - byte_offset: 180 - fieldset: AHB2LPENR - - name: APB1LLPENR - description: RCC APB1 sleep clock register - byte_offset: 196 - fieldset: APB1LLPENR - - name: APB1HLPENR - description: RCC APB1 sleep clock register - byte_offset: 200 - fieldset: APB1HLPENR - - name: APB2LPENR - description: RCC APB2 sleep clock register - byte_offset: 204 - fieldset: APB2LPENR - - name: APB3LPENR - description: RCC APB3 sleep clock register - byte_offset: 208 - fieldset: APB3LPENR - - name: CCIPR1 - description: RCC kernel clock configuration register - byte_offset: 216 - fieldset: CCIPR1 - - name: CCIPR2 - description: RCC kernel clock configuration register - byte_offset: 220 - fieldset: CCIPR2 - - name: CCIPR3 - description: RCC kernel clock configuration register - byte_offset: 224 - fieldset: CCIPR3 - - name: CCIPR4 - description: RCC kernel clock configuration register - byte_offset: 228 - fieldset: CCIPR4 - - name: CCIPR5 - description: RCC kernel clock configuration register - byte_offset: 232 - fieldset: CCIPR5 - - name: BDCR - description: RCC Backup domain control register - byte_offset: 240 - fieldset: BDCR - - name: RSR - description: RCC reset status register - byte_offset: 244 - fieldset: RSR + - name: CR + description: RCC clock control register + byte_offset: 0 + fieldset: CR + - name: HSICFGR + description: RCC HSI calibration register + byte_offset: 16 + fieldset: HSICFGR + - name: CRRCR + description: RCC clock recovery RC register + byte_offset: 20 + fieldset: CRRCR + - name: CSICFGR + description: RCC CSI calibration register + byte_offset: 24 + fieldset: CSICFGR + - name: CFGR + description: RCC clock configuration register + byte_offset: 28 + fieldset: CFGR + - name: CFGR2 + description: RCC CPU domain clock configuration register 2 + byte_offset: 32 + fieldset: CFGR2 + - name: PLLCFGR + description: RCC PLL clock source selection register + array: + len: 2 + stride: 4 + byte_offset: 40 + fieldset: PLLCFGR + - name: PLLDIVR + description: RCC PLL1 dividers register + array: + len: 2 + stride: 8 + byte_offset: 52 + fieldset: PLLDIVR + - name: PLLFRACR + description: RCC PLL1 fractional divider register + array: + len: 2 + stride: 8 + byte_offset: 56 + fieldset: PLLFRACR + - name: CIER + description: RCC clock source interrupt enable register + byte_offset: 80 + fieldset: CIER + - name: CIFR + description: RCC clock source interrupt flag register + byte_offset: 84 + fieldset: CIFR + - name: CICR + description: RCC clock source interrupt clear register + byte_offset: 88 + fieldset: CICR + - name: AHB1RSTR + description: RCC AHB1 reset register + byte_offset: 96 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: RCC AHB2 peripheral reset register + byte_offset: 100 + fieldset: AHB2RSTR + - name: APB1LRSTR + description: RCC APB1 peripheral low reset register + byte_offset: 116 + fieldset: APB1LRSTR + - name: APB1HRSTR + description: RCC APB1 peripheral high reset register + byte_offset: 120 + fieldset: APB1HRSTR + - name: APB2RSTR + description: RCC APB2 peripheral reset register + byte_offset: 124 + fieldset: APB2RSTR + - name: APB3RSTR + description: RCC APB3 peripheral reset register + byte_offset: 128 + fieldset: APB3RSTR + - name: AHB1ENR + description: RCC AHB1 peripherals clock register + byte_offset: 136 + fieldset: AHB1ENR + - name: AHB2ENR + description: RCC AHB2 peripheral clock register + byte_offset: 140 + fieldset: AHB2ENR + - name: APB1LENR + description: RCC APB1 peripheral clock register + byte_offset: 156 + fieldset: APB1LENR + - name: APB1HENR + description: RCC APB1 peripheral clock register + byte_offset: 160 + fieldset: APB1HENR + - name: APB2ENR + description: RCC APB2 peripheral clock register + byte_offset: 164 + fieldset: APB2ENR + - name: APB3ENR + description: RCC APB3 peripheral clock register + byte_offset: 168 + fieldset: APB3ENR + - name: AHB1LPENR + description: RCC AHB1 sleep clock register + byte_offset: 176 + fieldset: AHB1LPENR + - name: AHB2LPENR + description: RCC AHB2 sleep clock register + byte_offset: 180 + fieldset: AHB2LPENR + - name: APB1LLPENR + description: RCC APB1 sleep clock register + byte_offset: 196 + fieldset: APB1LLPENR + - name: APB1HLPENR + description: RCC APB1 sleep clock register + byte_offset: 200 + fieldset: APB1HLPENR + - name: APB2LPENR + description: RCC APB2 sleep clock register + byte_offset: 204 + fieldset: APB2LPENR + - name: APB3LPENR + description: RCC APB3 sleep clock register + byte_offset: 208 + fieldset: APB3LPENR + - name: CCIPR1 + description: RCC kernel clock configuration register + byte_offset: 216 + fieldset: CCIPR1 + - name: CCIPR2 + description: RCC kernel clock configuration register + byte_offset: 220 + fieldset: CCIPR2 + - name: CCIPR3 + description: RCC kernel clock configuration register + byte_offset: 224 + fieldset: CCIPR3 + - name: CCIPR4 + description: RCC kernel clock configuration register + byte_offset: 228 + fieldset: CCIPR4 + - name: CCIPR5 + description: RCC kernel clock configuration register + byte_offset: 232 + fieldset: CCIPR5 + - name: BDCR + description: RCC Backup domain control register + byte_offset: 240 + fieldset: BDCR + - name: RSR + description: RCC reset status register + byte_offset: 244 + fieldset: RSR fieldset/AHB1ENR: description: RCC AHB1 peripherals clock register fields: - - name: GPDMA1EN - description: "GPDMA1 clock enable\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: GPDMA2EN - description: "GPDMA2 clock enable\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: FLITFEN - description: "Flash interface clock enable\r Set and reset by software." - bit_offset: 8 - bit_size: 1 - - name: CRCEN - description: "CRC clock enable\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: RAMCFGEN - description: "RAMCFG clock enable\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: BKPRAMEN - description: "BKPRAM clock enable\r Set and reset by software" - bit_offset: 28 - bit_size: 1 - - name: SRAM1EN - description: "SRAM1 clock enable\r Set and reset by software." - bit_offset: 31 - bit_size: 1 + - name: GPDMA1EN + description: "GPDMA1 clock enable\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPDMA2EN + description: "GPDMA2 clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: FLITFEN + description: "Flash interface clock enable\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: "CRC clock enable\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: RAMCFGEN + description: "RAMCFG clock enable\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: BKPRAMEN + description: "BKPRAM clock enable\r Set and reset by software" + bit_offset: 28 + bit_size: 1 + - name: SRAM1EN + description: "SRAM1 clock enable\r Set and reset by software." + bit_offset: 31 + bit_size: 1 fieldset/AHB1LPENR: description: RCC AHB1 sleep clock register fields: - - name: GPDMA1LPEN - description: "GPDMA1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: GPDMA2LPEN - description: "GPDMA2 clock enable during sleep mode\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: FLITFLPEN - description: "Flash interface (FLITF) clock enable during sleep mode\r Set and reset by software." - bit_offset: 8 - bit_size: 1 - - name: CRCLPEN - description: "CRC clock enable during sleep mode\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: RAMCFGLPEN - description: "RAMCFG clock enable during sleep mode\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: BKPRAMLPEN - description: "BKPRAM clock enable during sleep mode\r Set and reset by software" - bit_offset: 28 - bit_size: 1 - - name: ICACHELPEN - description: "ICACHE clock enable during sleep mode\r Set and reset by software" - bit_offset: 29 - bit_size: 1 - - name: SRAM1LPEN - description: "SRAM1 clock enable during sleep mode\r Set and reset by software" - bit_offset: 31 - bit_size: 1 + - name: GPDMA1LPEN + description: "GPDMA1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPDMA2LPEN + description: "GPDMA2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: FLITFLPEN + description: "Flash interface (FLITF) clock enable during sleep mode\r Set and reset by software." + bit_offset: 8 + bit_size: 1 + - name: CRCLPEN + description: "CRC clock enable during sleep mode\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: RAMCFGLPEN + description: "RAMCFG clock enable during sleep mode\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: BKPRAMLPEN + description: "BKPRAM clock enable during sleep mode\r Set and reset by software" + bit_offset: 28 + bit_size: 1 + - name: ICACHELPEN + description: "ICACHE clock enable during sleep mode\r Set and reset by software" + bit_offset: 29 + bit_size: 1 + - name: SRAM1LPEN + description: "SRAM1 clock enable during sleep mode\r Set and reset by software" + bit_offset: 31 + bit_size: 1 fieldset/AHB1RSTR: description: RCC AHB1 reset register fields: - - name: GPDMA1RST - description: "GPDMA1 block reset\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: GPDMA2RST - description: "GPDMA2 block reset\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: CRCRST - description: CRC block reset Set and reset by software. - bit_offset: 12 - bit_size: 1 - - name: RAMCFGRST - description: "RAMCFG block reset\r Set and reset by software." - bit_offset: 17 - bit_size: 1 + - name: GPDMA1RST + description: "GPDMA1 block reset\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPDMA2RST + description: "GPDMA2 block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: CRCRST + description: CRC block reset Set and reset by software. + bit_offset: 12 + bit_size: 1 + - name: RAMCFGRST + description: "RAMCFG block reset\r Set and reset by software." + bit_offset: 17 + bit_size: 1 fieldset/AHB2ENR: description: RCC AHB2 peripheral clock register fields: - - name: GPIOAEN - description: "GPIOA clock enable\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: "GPIOB clock enable\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: "GPIOC clock enable\r Set and reset by software." - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: "GPIOD clock enable\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - - name: GPIOHEN - description: "GPIOH clock enable\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - - name: ADC1EN - description: "ADC1 peripherals clock enabled\r Set and reset by software." - bit_offset: 10 - bit_size: 1 - - name: DAC12EN - description: "DAC clock enable\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: HASHEN - description: "HASH clock enable\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: RNGEN - description: "RNG clock enable\r Set and reset by software." - bit_offset: 18 - bit_size: 1 - - name: SRAM2EN - description: "SRAM2 clock enable\r Set and reset by software." - bit_offset: 30 - bit_size: 1 + - name: GPIOAEN + description: "GPIOA clock enable\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: "GPIOB clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: "GPIOC clock enable\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: "GPIOD clock enable\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOHEN + description: "GPIOH clock enable\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: ADC1EN + description: "ADC1 peripherals clock enabled\r Set and reset by software." + bit_offset: 10 + bit_size: 1 + - name: DAC12EN + description: "DAC clock enable\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: HASHEN + description: "HASH clock enable\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: "RNG clock enable\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: SRAM2EN + description: "SRAM2 clock enable\r Set and reset by software." + bit_offset: 30 + bit_size: 1 fieldset/AHB2LPENR: description: RCC AHB2 sleep clock register fields: - - name: GPIOALPEN - description: "GPIOA clock enable during sleep mode\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: GPIOBLPEN - description: "GPIOB clock enable during sleep mode\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: GPIOCLPEN - description: "GPIOC clock enable during sleep mode\r Set and reset by software." - bit_offset: 2 - bit_size: 1 - - name: GPIODLPEN - description: "GPIOD clock enable during sleep mode\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - - name: GPIOHLPEN - description: "GPIOH clock enable during sleep mode\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - - name: ADC1LPEN - description: "ADC1 peripherals clock enable during sleep mode\r Set and reset by software." - bit_offset: 10 - bit_size: 1 - - name: DAC12LPEN - description: "DAC clock enable during sleep mode\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: HASHLPEN - description: "HASH clock enable during sleep mode\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: RNGLPEN - description: "RNG clock enable during sleep mode\r Set and reset by software." - bit_offset: 18 - bit_size: 1 - - name: SRAM2LPEN - description: "SRAM2 clock enable during sleep mode\r Set and reset by software." - bit_offset: 30 - bit_size: 1 + - name: GPIOALPEN + description: "GPIOA clock enable during sleep mode\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: "GPIOB clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: "GPIOC clock enable during sleep mode\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODLPEN + description: "GPIOD clock enable during sleep mode\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOHLPEN + description: "GPIOH clock enable during sleep mode\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: ADC1LPEN + description: "ADC1 peripherals clock enable during sleep mode\r Set and reset by software." + bit_offset: 10 + bit_size: 1 + - name: DAC12LPEN + description: "DAC clock enable during sleep mode\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: HASHLPEN + description: "HASH clock enable during sleep mode\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: RNGLPEN + description: "RNG clock enable during sleep mode\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: SRAM2LPEN + description: "SRAM2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 30 + bit_size: 1 fieldset/AHB2RSTR: description: RCC AHB2 peripheral reset register fields: - - name: GPIOARST - description: "GPIOA block reset\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: "GPIOB block reset\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: "GPIOC block reset\r Set and reset by software." - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: "GPIOD block reset\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - - name: GPIOHRST - description: "GPIOH block reset\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - - name: ADC1RST - description: "ADC1 block reset\r Set and reset by software." - bit_offset: 10 - bit_size: 1 - - name: DAC12RST - description: "DAC block reset\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: HASHRST - description: "HASH block reset\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: RNGRST - description: "RNG block reset\r Set and reset by software." - bit_offset: 18 - bit_size: 1 + - name: GPIOARST + description: "GPIOA block reset\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: "GPIOB block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: "GPIOC block reset\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: "GPIOD block reset\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOHRST + description: "GPIOH block reset\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: ADC1RST + description: "ADC1 block reset\r Set and reset by software." + bit_offset: 10 + bit_size: 1 + - name: DAC12RST + description: "DAC block reset\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: HASHRST + description: "HASH block reset\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: RNGRST + description: "RNG block reset\r Set and reset by software." + bit_offset: 18 + bit_size: 1 fieldset/APB1HENR: description: RCC APB1 peripheral clock register fields: - - name: DTSEN - description: "DTS clock enable\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - - name: LPTIM2EN - description: "LPTIM2 clock enable\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: FDCAN1EN - description: "FDCAN1 peripheral clock enable\r Set and reset by software." - bit_offset: 9 - bit_size: 1 + - name: DTSEN + description: "DTS clock enable\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: LPTIM2EN + description: "LPTIM2 clock enable\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: FDCAN1EN + description: "FDCAN1 peripheral clock enable\r Set and reset by software." + bit_offset: 9 + bit_size: 1 fieldset/APB1HLPENR: description: RCC APB1 sleep clock register fields: - - name: DTSLPEN - description: "DTS clock enable during sleep mode\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - - name: LPTIM2LPEN - description: "LPTIM2 clock enable during sleep mode\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: FDCAN1LPEN - description: "FDCAN1 peripheral clock enable during sleep mode\r Set and reset by software." - bit_offset: 9 - bit_size: 1 + - name: DTSLPEN + description: "DTS clock enable during sleep mode\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: LPTIM2LPEN + description: "LPTIM2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: FDCAN1LPEN + description: "FDCAN1 peripheral clock enable during sleep mode\r Set and reset by software." + bit_offset: 9 + bit_size: 1 fieldset/APB1HRSTR: description: RCC APB1 peripheral high reset register fields: - - name: DTSRST - description: "DTS block reset\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - - name: LPTIM2RST - description: "LPTIM2 block reset\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: FDCAN1RST - description: "FDCAN1 block reset\r Set and reset by software." - bit_offset: 9 - bit_size: 1 + - name: DTSRST + description: "DTS block reset\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: LPTIM2RST + description: "LPTIM2 block reset\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: FDCAN1RST + description: "FDCAN1 block reset\r Set and reset by software." + bit_offset: 9 + bit_size: 1 fieldset/APB1LENR: description: RCC APB1 peripheral clock register fields: - - name: TIM2EN - description: "TIM2 clock enable\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: "TIM3 clock enable\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: TIM6EN - description: "TIM6 clock enable\r Set and reset by software." - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: "TIM7 clock enable\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: WWDGEN - description: "WWDG clock enable\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: OPAMPEN - description: "OPAMP clock enable\r Set and reset by software." - bit_offset: 13 - bit_size: 1 - - name: SPI2EN - description: "SPI2 clock enable\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: "SPI3 clock enable\r Set and reset by software." - bit_offset: 15 - bit_size: 1 - - name: COMPEN - description: "COMP clock enable\r Set and reset by software." - bit_offset: 16 - bit_size: 1 - - name: USART2EN - description: "USART2 clock enable\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: "USART3 clock enable\r Set and reset by software." - bit_offset: 18 - bit_size: 1 - - name: I2C1EN - description: "I2C1 clock enable\r Set and reset by software." - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: "I2C2 clock enable\r Set and reset by software." - bit_offset: 22 - bit_size: 1 - - name: I3C1EN - description: "I3C1 clock enable\r Set and reset by software." - bit_offset: 23 - bit_size: 1 - - name: CRSEN - description: "CRS clock enable\r Set and reset by software." - bit_offset: 24 - bit_size: 1 + - name: TIM2EN + description: "TIM2 clock enable\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: "TIM3 clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: TIM6EN + description: "TIM6 clock enable\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: "TIM7 clock enable\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: WWDGEN + description: "WWDG clock enable\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: OPAMPEN + description: "OPAMP clock enable\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: SPI2EN + description: "SPI2 clock enable\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: "SPI3 clock enable\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: COMPEN + description: "COMP clock enable\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: USART2EN + description: "USART2 clock enable\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: "USART3 clock enable\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: I2C1EN + description: "I2C1 clock enable\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: "I2C2 clock enable\r Set and reset by software." + bit_offset: 22 + bit_size: 1 + - name: I3C1EN + description: "I3C1 clock enable\r Set and reset by software." + bit_offset: 23 + bit_size: 1 + - name: CRSEN + description: "CRS clock enable\r Set and reset by software." + bit_offset: 24 + bit_size: 1 fieldset/APB1LLPENR: description: RCC APB1 sleep clock register fields: - - name: TIM2LPEN - description: "TIM2 clock enable during sleep mode\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: TIM3LPEN - description: "TIM3 clock enable during sleep mode\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: TIM6LPEN - description: "TIM6 clock enable during sleep mode\r Set and reset by software." - bit_offset: 4 - bit_size: 1 - - name: TIM7LPEN - description: "TIM7 clock enable during sleep mode\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: WWDGLPEN - description: "WWDG clock enable during sleep mode\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: OPAMPLPEN - description: "OPAMP clock enable during sleep mode\r Set and reset by software." - bit_offset: 13 - bit_size: 1 - - name: SPI2LPEN - description: "SPI2 clock enable during sleep mode\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: SPI3LPEN - description: "SPI3 clock enable during sleep mode\r Set and reset by software." - bit_offset: 15 - bit_size: 1 - - name: COMPLPEN - description: "COMP clock enable during sleep mode\r Set and reset by software." - bit_offset: 16 - bit_size: 1 - - name: USART2LPEN - description: "USART2 clock enable during sleep mode\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: USART3LPEN - description: "USART3 clock enable during sleep mode\r Set and reset by software." - bit_offset: 18 - bit_size: 1 - - name: I2C1LPEN - description: "I2C1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 21 - bit_size: 1 - - name: I2C2LPEN - description: "I2C2 clock enable during sleep mode\r Set and reset by software." - bit_offset: 22 - bit_size: 1 - - name: I3C1LPEN - description: "I3C1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 23 - bit_size: 1 - - name: CRSLPEN - description: "CRS clock enable during sleep mode\r Set and reset by software." - bit_offset: 24 - bit_size: 1 + - name: TIM2LPEN + description: "TIM2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3LPEN + description: "TIM3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: TIM6LPEN + description: "TIM6 clock enable during sleep mode\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7LPEN + description: "TIM7 clock enable during sleep mode\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: WWDGLPEN + description: "WWDG clock enable during sleep mode\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: OPAMPLPEN + description: "OPAMP clock enable during sleep mode\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: SPI2LPEN + description: "SPI2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: SPI3LPEN + description: "SPI3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: COMPLPEN + description: "COMP clock enable during sleep mode\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: USART2LPEN + description: "USART2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: USART3LPEN + description: "USART3 clock enable during sleep mode\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: I2C1LPEN + description: "I2C1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: "I2C2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 22 + bit_size: 1 + - name: I3C1LPEN + description: "I3C1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 23 + bit_size: 1 + - name: CRSLPEN + description: "CRS clock enable during sleep mode\r Set and reset by software." + bit_offset: 24 + bit_size: 1 fieldset/APB1LRSTR: description: RCC APB1 peripheral low reset register fields: - - name: TIM2RST - description: "TIM2 block reset\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: "TIM3 block reset\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: TIM6RST - description: "TIM6 block reset\r Set and reset by software." - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: "TIM7 block reset\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - - name: OPAMPRST - description: "OPAMP block reset\r Set and reset by software." - bit_offset: 13 - bit_size: 1 - - name: SPI2RST - description: "SPI2 block reset\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: "SPI3 block reset\r Set and reset by software." - bit_offset: 15 - bit_size: 1 - - name: COMPRST - description: "COMP block reset\r Set and reset by software." - bit_offset: 16 - bit_size: 1 - - name: USART2RST - description: "USART2 block reset\r Set and reset by software." - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: "USART3 block reset\r Set and reset by software." - bit_offset: 18 - bit_size: 1 - - name: I2C1RST - description: "I2C1 block reset\r Set and reset by software." - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: "I2C2 block reset\r Set and reset by software." - bit_offset: 22 - bit_size: 1 - - name: I3C1RST - description: "I3C1 block reset\r Set and reset by software." - bit_offset: 23 - bit_size: 1 - - name: CRSRST - description: "CRS block reset\r Set and reset by software." - bit_offset: 24 - bit_size: 1 + - name: TIM2RST + description: "TIM2 block reset\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: "TIM3 block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: TIM6RST + description: "TIM6 block reset\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: "TIM7 block reset\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: OPAMPRST + description: "OPAMP block reset\r Set and reset by software." + bit_offset: 13 + bit_size: 1 + - name: SPI2RST + description: "SPI2 block reset\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: "SPI3 block reset\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: COMPRST + description: "COMP block reset\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: USART2RST + description: "USART2 block reset\r Set and reset by software." + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: "USART3 block reset\r Set and reset by software." + bit_offset: 18 + bit_size: 1 + - name: I2C1RST + description: "I2C1 block reset\r Set and reset by software." + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: "I2C2 block reset\r Set and reset by software." + bit_offset: 22 + bit_size: 1 + - name: I3C1RST + description: "I3C1 block reset\r Set and reset by software." + bit_offset: 23 + bit_size: 1 + - name: CRSRST + description: "CRS block reset\r Set and reset by software." + bit_offset: 24 + bit_size: 1 fieldset/APB2ENR: description: RCC APB2 peripheral clock register fields: - - name: TIM1EN - description: "TIM1 clock enable\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: "SPI1 clock enable\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: USART1EN - description: "USART1 clock enable\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: USBEN - description: "USB clock enable\r Set and reset by software." - bit_offset: 24 - bit_size: 1 + - name: TIM1EN + description: "TIM1 clock enable\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: "SPI1 clock enable\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: "USART1 clock enable\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: USBEN + description: "USB clock enable\r Set and reset by software." + bit_offset: 24 + bit_size: 1 fieldset/APB2LPENR: description: RCC APB2 sleep clock register fields: - - name: TIM1LPEN - description: "TIM1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: SPI1LPEN - description: "SPI1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: USART1LPEN - description: "USART1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: USBLPEN - description: "USB clock enable during sleep mode\r Set and reset by software." - bit_offset: 24 - bit_size: 1 + - name: TIM1LPEN + description: "TIM1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1LPEN + description: "SPI1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: USART1LPEN + description: "USART1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: USBLPEN + description: "USB clock enable during sleep mode\r Set and reset by software." + bit_offset: 24 + bit_size: 1 fieldset/APB2RSTR: description: RCC APB2 peripheral reset register fields: - - name: TIM1RST - description: "TIM1 block reset\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: "SPI1 block reset\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - - name: USART1RST - description: "USART1 block reset\r Set and reset by software." - bit_offset: 14 - bit_size: 1 - - name: USBRST - description: "USB block reset\r Set and reset by software." - bit_offset: 24 - bit_size: 1 + - name: TIM1RST + description: "TIM1 block reset\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: "SPI1 block reset\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: "USART1 block reset\r Set and reset by software." + bit_offset: 14 + bit_size: 1 + - name: USBRST + description: "USB block reset\r Set and reset by software." + bit_offset: 24 + bit_size: 1 fieldset/APB3ENR: description: RCC APB3 peripheral clock register fields: - - name: SBSEN - description: "SBS clock enable\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: LPUART1EN - description: "LPUART1 clock enable\r Set and reset by software." - bit_offset: 6 - bit_size: 1 - - name: I3C2EN - description: "I3C2EN clock enable\r Set and reset by software." - bit_offset: 9 - bit_size: 1 - - name: LPTIM1EN - description: "LPTIM1 clock enable\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: VREFEN - description: "VREF clock enable\r Set and reset by software." - bit_offset: 20 - bit_size: 1 - - name: RTCAPBEN - description: "RTC APB interface clock enable\r Set and reset by software." - bit_offset: 21 - bit_size: 1 + - name: SBSEN + description: "SBS clock enable\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: LPUART1EN + description: "LPUART1 clock enable\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: I3C2EN + description: "I3C2EN clock enable\r Set and reset by software." + bit_offset: 9 + bit_size: 1 + - name: LPTIM1EN + description: "LPTIM1 clock enable\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: VREFEN + description: "VREF clock enable\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: RTCAPBEN + description: "RTC APB interface clock enable\r Set and reset by software." + bit_offset: 21 + bit_size: 1 fieldset/APB3LPENR: description: RCC APB3 sleep clock register fields: - - name: SBSLPEN - description: "SBS clock enable during sleep mode\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: LPUART1LPEN - description: "LPUART1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 6 - bit_size: 1 - - name: I3C2LPEN - description: "I3C2 clock enable during sleep mode\r Set and reset by software." - bit_offset: 9 - bit_size: 1 - - name: LPTIM1LPEN - description: "LPTIM1 clock enable during sleep mode\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: VREFLPEN - description: "VREF clock enable during sleep mode\r Set and reset by software." - bit_offset: 20 - bit_size: 1 - - name: RTCAPBLPEN - description: "RTC APB interface clock enable during sleep mode\r Set and reset by software." - bit_offset: 21 - bit_size: 1 + - name: SBSLPEN + description: "SBS clock enable during sleep mode\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: LPUART1LPEN + description: "LPUART1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: I3C2LPEN + description: "I3C2 clock enable during sleep mode\r Set and reset by software." + bit_offset: 9 + bit_size: 1 + - name: LPTIM1LPEN + description: "LPTIM1 clock enable during sleep mode\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: VREFLPEN + description: "VREF clock enable during sleep mode\r Set and reset by software." + bit_offset: 20 + bit_size: 1 + - name: RTCAPBLPEN + description: "RTC APB interface clock enable during sleep mode\r Set and reset by software." + bit_offset: 21 + bit_size: 1 fieldset/APB3RSTR: description: RCC APB3 peripheral reset register fields: - - name: SBSRST - description: "SBS block reset\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - - name: LPUART1RST - description: "LPUART1 block reset\r Set and reset by software." - bit_offset: 6 - bit_size: 1 - - name: I3C2RST - description: "I3C2RST block reset\r Set and reset by software." - bit_offset: 9 - bit_size: 1 - - name: LPTIM1RST - description: "LPTIM1 block reset\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - - name: VREFRST - description: "VREF block reset\r Set and reset by software." - bit_offset: 20 - bit_size: 1 + - name: SBSRST + description: "SBS block reset\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: LPUART1RST + description: "LPUART1 block reset\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: I3C2RST + description: "I3C2RST block reset\r Set and reset by software." + bit_offset: 9 + bit_size: 1 + - name: LPTIM1RST + description: "LPTIM1 block reset\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + - name: VREFRST + description: "VREF block reset\r Set and reset by software." + bit_offset: 20 + bit_size: 1 fieldset/BDCR: description: RCC Backup domain control register fields: - - name: LSEON - description: "LSE oscillator enabled\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: "LSE oscillator ready\r Set and reset by hardware to indicate when the LSE is stable.\r This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0." - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: "LSE oscillator bypass\r Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1)" - bit_offset: 2 - bit_size: 1 - - name: LSEDRV - description: "LSE oscillator driving capability\r Set by software to select the driving capability of the LSE oscillator.\r These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0)." - bit_offset: 3 - bit_size: 2 - enum: LSEDRV - - name: LSECSSON - description: "LSE clock security system enable\r Set by software to enable the clock security system on 32 kHz oscillator.\r LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON." - bit_offset: 5 - bit_size: 1 - - name: LSECSSD - description: "LSE clock security system failure detection\r Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator." - bit_offset: 6 - bit_size: 1 - - name: LSEEXT - description: "low-speed external clock type in bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the LSEON bit, to be used by the device.\r The LSEEXT bit can be written only if the LSE oscillator is disabled." - bit_offset: 7 - bit_size: 1 - enum: LSEEXT - - name: RTCSEL - description: "RTC clock source selection\r Set by software to select the clock source for the RTC.\r These bits can be written only one time (except in case of failure detection on LSE).\r These bits must be written before LSECSSON is enabled.\r The VSWRST bit can be used to reset them, then it can be written one time again.\r If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST)." - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: "RTC clock enable\r Set and reset by software." - bit_offset: 15 - bit_size: 1 - - name: VSWRST - description: "VSwitch domain software reset\r Set and reset by software." - bit_offset: 16 - bit_size: 1 - - name: LSCOEN - description: "Low-speed clock output (LSCO) enable\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: LSCOSEL - description: "Low-speed clock output selection\r Set and cleared by software." - bit_offset: 25 - bit_size: 1 - enum: LSCOSEL - - name: LSION - description: "LSI oscillator enable\r Set and cleared by software." - bit_offset: 26 - bit_size: 1 - - name: LSIRDY - description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is stable.\r After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles.\r This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0." - bit_offset: 27 - bit_size: 1 + - name: LSEON + description: "LSE oscillator enabled\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: "LSE oscillator ready\r Set and reset by hardware to indicate when the LSE is stable.\r This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0." + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: "LSE oscillator bypass\r Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1)" + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: "LSE oscillator driving capability\r Set by software to select the driving capability of the LSE oscillator.\r These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0)." + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: "LSE clock security system enable\r Set by software to enable the clock security system on 32 kHz oscillator.\r LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON." + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: "LSE clock security system failure detection\r Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator." + bit_offset: 6 + bit_size: 1 + - name: LSEEXT + description: "low-speed external clock type in bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the LSEON bit, to be used by the device.\r The LSEEXT bit can be written only if the LSE oscillator is disabled." + bit_offset: 7 + bit_size: 1 + enum: LSEEXT + - name: RTCSEL + description: "RTC clock source selection\r Set by software to select the clock source for the RTC.\r These bits can be written only one time (except in case of failure detection on LSE).\r These bits must be written before LSECSSON is enabled.\r The VSWRST bit can be used to reset them, then it can be written one time again.\r If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST)." + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: "RTC clock enable\r Set and reset by software." + bit_offset: 15 + bit_size: 1 + - name: VSWRST + description: "VSwitch domain software reset\r Set and reset by software." + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: "Low-speed clock output (LSCO) enable\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: "Low-speed clock output selection\r Set and cleared by software." + bit_offset: 25 + bit_size: 1 + enum: LSCOSEL + - name: LSION + description: "LSI oscillator enable\r Set and cleared by software." + bit_offset: 26 + bit_size: 1 + - name: LSIRDY + description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is stable.\r After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles.\r This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0." + bit_offset: 27 + bit_size: 1 fieldset/CCIPR1: description: RCC kernel clock configuration register fields: - - name: USART1SEL - description: "USART1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" - bit_offset: 0 - bit_size: 3 - enum: USARTSEL - - name: USART2SEL - description: "USART2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" - bit_offset: 3 - bit_size: 3 - enum: USARTSEL - - name: USART3SEL - description: "USART3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" - bit_offset: 6 - bit_size: 3 - enum: USARTSEL - - name: TIMICSEL - description: "TIM2, TIM3 and LPTIM2 input capture source selection\r Set and reset by software." - bit_offset: 31 - bit_size: 1 - enum: TIMICSEL + - name: USART1SEL + description: "USART1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 0 + bit_size: 3 + enum: USARTSEL + - name: USART2SEL + description: "USART2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 3 + bit_size: 3 + enum: USARTSEL + - name: USART3SEL + description: "USART3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 6 + bit_size: 3 + enum: USARTSEL + - name: TIMICSEL + description: "TIM2, TIM3 and LPTIM2 input capture source selection\r Set and reset by software." + bit_offset: 31 + bit_size: 1 + enum: TIMICSEL fieldset/CCIPR2: description: RCC kernel clock configuration register fields: - - name: LPTIM1SEL - description: "LPTIM1 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 8 - bit_size: 3 - enum: LPTIMSEL - - name: LPTIM2SEL - description: "LPTIM2 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 12 - bit_size: 3 - enum: LPTIMSEL + - name: LPTIM1SEL + description: "LPTIM1 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 8 + bit_size: 3 + enum: LPTIMSEL + - name: LPTIM2SEL + description: "LPTIM2 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 12 + bit_size: 3 + enum: LPTIMSEL fieldset/CCIPR3: description: RCC kernel clock configuration register fields: - - name: SPI1SEL - description: "SPI1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" - bit_offset: 0 - bit_size: 3 - enum: SPISEL - - name: SPI2SEL - description: "SPI2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" - bit_offset: 3 - bit_size: 3 - enum: SPISEL - - name: SPI3SEL - description: "SPI3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" - bit_offset: 6 - bit_size: 3 - enum: SPISEL - - name: LPUART1SEL - description: "LPUART1 kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 24 - bit_size: 3 - enum: LPUARTSEL + - name: SPI1SEL + description: "SPI1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 0 + bit_size: 3 + enum: SPISEL + - name: SPI2SEL + description: "SPI2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 3 + bit_size: 3 + enum: SPISEL + - name: SPI3SEL + description: "SPI3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" + bit_offset: 6 + bit_size: 3 + enum: SPISEL + - name: LPUART1SEL + description: "LPUART1 kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 24 + bit_size: 3 + enum: LPUARTSEL fieldset/CCIPR4: description: RCC kernel clock configuration register fields: - - name: SYSTICKSEL - description: "SYSTICK clock source selection\r Note: rcc_hclk frequency must be four times higher than\r lsi_ker_ck/lse_ck (period (LSI/LSE) ≥ 4 * period (HCLK)." - bit_offset: 2 - bit_size: 2 - enum: SYSTICKSEL - - name: USBSEL - description: USB kernel clock source selection - bit_offset: 4 - bit_size: 2 - enum: USBSEL - - name: I2C1SEL - description: I2C1 kernel clock source selection - bit_offset: 16 - bit_size: 2 - enum: ICSEL - - name: I2C2SEL - description: I2C2 kernel clock source selection - bit_offset: 18 - bit_size: 2 - enum: ICSEL - - name: I3C1SEL - description: I3C1 kernel clock source selection - bit_offset: 24 - bit_size: 2 - enum: ICSEL - - name: I3C2SEL - description: I3C2 kernel clock source selection - bit_offset: 26 - bit_size: 2 - enum: ICSEL + - name: SYSTICKSEL + description: "SYSTICK clock source selection\r Note: rcc_hclk frequency must be four times higher than\r lsi_ker_ck/lse_ck (period (LSI/LSE) ≥ 4 * period (HCLK)." + bit_offset: 2 + bit_size: 2 + enum: SYSTICKSEL + - name: USBSEL + description: USB kernel clock source selection + bit_offset: 4 + bit_size: 2 + enum: USBSEL + - name: I2C1SEL + description: I2C1 kernel clock source selection + bit_offset: 16 + bit_size: 2 + enum: ICSEL + - name: I2C2SEL + description: I2C2 kernel clock source selection + bit_offset: 18 + bit_size: 2 + enum: ICSEL + - name: I3C1SEL + description: I3C1 kernel clock source selection + bit_offset: 24 + bit_size: 2 + enum: ICSEL + - name: I3C2SEL + description: I3C2 kernel clock source selection + bit_offset: 26 + bit_size: 2 + enum: ICSEL fieldset/CCIPR5: description: RCC kernel clock configuration register fields: - - name: ADCDACSEL - description: "ADC and DAC kernel clock source selection\r others: reserved, the kernel clock is disabled" - bit_offset: 0 - bit_size: 3 - enum: ADCDACSEL - - name: DACSEL - description: DAC hold clock - bit_offset: 3 - bit_size: 1 - enum: DACSEL - - name: RNGSEL - description: RNG kernel clock source selection - bit_offset: 4 - bit_size: 2 - enum: RNGSEL - - name: FDCAN1SEL - description: FDCAN1 kernel clock source selection - bit_offset: 8 - bit_size: 2 - enum: FDCANSEL - - name: CKPERSEL - description: per_ck clock source selection - bit_offset: 30 - bit_size: 2 - enum: CKPERSEL + - name: ADCDACSEL + description: "ADC and DAC kernel clock source selection\r others: reserved, the kernel clock is disabled" + bit_offset: 0 + bit_size: 3 + enum: ADCDACSEL + - name: DACSEL + description: DAC hold clock + bit_offset: 3 + bit_size: 1 + enum: DACSEL + - name: RNGSEL + description: RNG kernel clock source selection + bit_offset: 4 + bit_size: 2 + enum: RNGSEL + - name: FDCAN1SEL + description: FDCAN1 kernel clock source selection + bit_offset: 8 + bit_size: 2 + enum: FDCANSEL + - name: CKPERSEL + description: per_ck clock source selection + bit_offset: 30 + bit_size: 2 + enum: CKPERSEL fieldset/CFGR: description: RCC clock configuration register fields: - - name: SW - description: "system clock and trace clock switch\r Set and reset by software to select system clock and trace clock sources (sys_ck).\r Set by hardware in order to:\r -\tforce the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode\r -\tforce the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock\r others: reserved" - bit_offset: 0 - bit_size: 3 - enum: SW - - name: SWS - description: "system clock switch status\r Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset).\r others: reserved" - bit_offset: 3 - bit_size: 3 - enum: SW - - name: STOPWUCK - description: "system clock selection after a wakeup from system Stop\r Set and reset by software to select the system wakeup clock from system Stop.\r The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. 0: HSI selected as wakeup clock from system Stop (default after reset)\r STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10)." - bit_offset: 6 - bit_size: 1 - enum: STOPWUCK - - name: STOPKERWUCK - description: "kernel clock selection after a wakeup from system Stop\r Set and reset by software to select the kernel wakeup clock from system Stop." - bit_offset: 7 - bit_size: 1 - enum: STOPKERWUCK - - name: RTCPRE - description: "HSE division factor for RTC clock\r Set and cleared by software to divide the HSE to generate a clock for RTC.\r Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source.\r ..." - bit_offset: 8 - bit_size: 6 - - name: TIMPRE - description: "timers clocks prescaler selection\r This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains." - bit_offset: 15 - bit_size: 1 - enum: TIMPRE - - name: MCO1PRE - description: "MCO1 prescaler\r Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." - bit_offset: 18 - bit_size: 4 - - name: MCO1 - description: "Microcontroller clock output 1\r Set and cleared by software. Clock source selection may generate glitches on MCO1.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" - bit_offset: 22 - bit_size: 3 - enum: MCO1 - - name: MCO2PRE - description: "MCO2 prescaler\r Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." - bit_offset: 25 - bit_size: 4 - - name: MCO2 - description: "microcontroller clock output 2\r Set and cleared by software. Clock source selection may generate glitches on MCO2.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" - bit_offset: 29 - bit_size: 3 - enum: MCO2 + - name: SW + description: "system clock and trace clock switch\r Set and reset by software to select system clock and trace clock sources (sys_ck).\r Set by hardware in order to:\r -\tforce the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode\r -\tforce the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock\r others: reserved" + bit_offset: 0 + bit_size: 3 + enum: SW + - name: SWS + description: "system clock switch status\r Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset).\r others: reserved" + bit_offset: 3 + bit_size: 3 + enum: SW + - name: STOPWUCK + description: "system clock selection after a wakeup from system Stop\r Set and reset by software to select the system wakeup clock from system Stop.\r The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. 0: HSI selected as wakeup clock from system Stop (default after reset)\r STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10)." + bit_offset: 6 + bit_size: 1 + enum: STOPWUCK + - name: STOPKERWUCK + description: "kernel clock selection after a wakeup from system Stop\r Set and reset by software to select the kernel wakeup clock from system Stop." + bit_offset: 7 + bit_size: 1 + enum: STOPKERWUCK + - name: RTCPRE + description: "HSE division factor for RTC clock\r Set and cleared by software to divide the HSE to generate a clock for RTC.\r Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source.\r ..." + bit_offset: 8 + bit_size: 6 + - name: TIMPRE + description: "timers clocks prescaler selection\r This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains." + bit_offset: 15 + bit_size: 1 + enum: TIMPRE + - name: MCO1PRE + description: "MCO1 prescaler\r Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." + bit_offset: 18 + bit_size: 4 + - name: MCO1 + description: "Microcontroller clock output 1\r Set and cleared by software. Clock source selection may generate glitches on MCO1.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" + bit_offset: 22 + bit_size: 3 + enum: MCO1 + - name: MCO2PRE + description: "MCO2 prescaler\r Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." + bit_offset: 25 + bit_size: 4 + - name: MCO2 + description: "microcontroller clock output 2\r Set and cleared by software. Clock source selection may generate glitches on MCO2.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" + bit_offset: 29 + bit_size: 3 + enum: MCO2 fieldset/CFGR2: description: RCC CPU domain clock configuration register 2 fields: - - name: HPRE - description: "AHB prescaler\r Set and reset by software to control the division factor of rcc_hclk. Changing\r this division ratio has an impact on the frequency of all bus matrix clocks\r 0xxx: rcc_hclk = sys_ck (default after reset)" - bit_offset: 0 - bit_size: 4 - enum: HPRE - - name: PPRE1 - description: "APB low-speed prescaler (APB1)\r Set and reset by software to control the division factor of rcc_pclk1.\r The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write.\r 0xx: rcc_pclk1 = rcc_hclk1 (default after reset)" - bit_offset: 4 - bit_size: 3 - enum: PPRE - - name: PPRE2 - description: "APB high-speed prescaler (APB2)\r Set and reset by software to control APB high-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write.\r 0xx: rcc_pclk2 = rcc_hclk1" - bit_offset: 8 - bit_size: 3 - enum: PPRE - - name: PPRE3 - description: "APB low-speed prescaler (APB3)\r Set and reset by software to control APB low-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write.\r 0xx: rcc_pclk3 = rcc_hclk1" - bit_offset: 12 - bit_size: 3 - enum: PPRE - - name: AHB1DIS - description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1\r peripherals from RCC_AHB1ENR are used and when their clocks are disabled in\r RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks from\r RCC_AHB1ENR are off.\r enable control bits" - bit_offset: 16 - bit_size: 1 - - name: AHB2DIS - description: "AHB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2\r peripherals from RCC_AHB2ENR are used and when their clocks are disabled in\r RCC_AHB2ENR. When this bit is set, all the AHB2 peripherals clocks from\r RCC_AHB2ENR are off.\r enable control bits" - bit_offset: 17 - bit_size: 1 - - name: AHB4DIS - description: "AHB4 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB4\r peripherals from RCC_AHB4ENR are used and when their clocks are disabled in\r RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from\r RCC_AHB4ENR are off.\r enable control bits" - bit_offset: 19 - bit_size: 1 - - name: APB1DIS - description: "APB1 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB1\r peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR.\r When this bit is set, all the APB1 peripherals clocks are off, except for IWDG.\r control bits" - bit_offset: 20 - bit_size: 1 - - name: APB2DIS - description: "APB2 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB2\r peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is\r set, all the APB2 peripherals clocks are off.\r control bits" - bit_offset: 21 - bit_size: 1 - - name: APB3DIS - description: "APB3 clock disable value.Set and cleared by software\r This bit can be set in order to further reduce power consumption, when none of the APB3\r peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is\r set, all the APB3 peripherals clocks are off.\r control bits" - bit_offset: 22 - bit_size: 1 + - name: HPRE + description: "AHB prescaler\r Set and reset by software to control the division factor of rcc_hclk. Changing\r this division ratio has an impact on the frequency of all bus matrix clocks\r 0xxx: rcc_hclk = sys_ck (default after reset)" + bit_offset: 0 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: "APB low-speed prescaler (APB1)\r Set and reset by software to control the division factor of rcc_pclk1.\r The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write.\r 0xx: rcc_pclk1 = rcc_hclk1 (default after reset)" + bit_offset: 4 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: "APB high-speed prescaler (APB2)\r Set and reset by software to control APB high-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write.\r 0xx: rcc_pclk2 = rcc_hclk1" + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE3 + description: "APB low-speed prescaler (APB3)\r Set and reset by software to control APB low-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write.\r 0xx: rcc_pclk3 = rcc_hclk1" + bit_offset: 12 + bit_size: 3 + enum: PPRE + - name: AHB1DIS + description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1\r peripherals from RCC_AHB1ENR are used and when their clocks are disabled in\r RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks from\r RCC_AHB1ENR are off.\r enable control bits" + bit_offset: 16 + bit_size: 1 + - name: AHB2DIS + description: "AHB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2\r peripherals from RCC_AHB2ENR are used and when their clocks are disabled in\r RCC_AHB2ENR. When this bit is set, all the AHB2 peripherals clocks from\r RCC_AHB2ENR are off.\r enable control bits" + bit_offset: 17 + bit_size: 1 + - name: AHB4DIS + description: "AHB4 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB4\r peripherals from RCC_AHB4ENR are used and when their clocks are disabled in\r RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from\r RCC_AHB4ENR are off.\r enable control bits" + bit_offset: 19 + bit_size: 1 + - name: APB1DIS + description: "APB1 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB1\r peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR.\r When this bit is set, all the APB1 peripherals clocks are off, except for IWDG.\r control bits" + bit_offset: 20 + bit_size: 1 + - name: APB2DIS + description: "APB2 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB2\r peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is\r set, all the APB2 peripherals clocks are off.\r control bits" + bit_offset: 21 + bit_size: 1 + - name: APB3DIS + description: "APB3 clock disable value.Set and cleared by software\r This bit can be set in order to further reduce power consumption, when none of the APB3\r peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is\r set, all the APB3 peripherals clocks are off.\r control bits" + bit_offset: 22 + bit_size: 1 fieldset/CICR: description: RCC clock source interrupt clear register fields: - - name: LSIRDYC - description: "LSI ready interrupt clear\r Set by software to clear LSIRDYF.\r Reset by hardware when clear done." - bit_offset: 0 - bit_size: 1 - - name: LSERDYC - description: "LSE ready interrupt clear\r Set by software to clear LSERDYF.\r Reset by hardware when clear done." - bit_offset: 1 - bit_size: 1 - - name: CSIRDYC - description: "HSI ready interrupt clear\r Set by software to clear CSIRDYF.\r Reset by hardware when clear done." - bit_offset: 2 - bit_size: 1 - - name: HSIRDYC - description: "HSI ready interrupt clear\r Set by software to clear HSIRDYF.\r Reset by hardware when clear done." - bit_offset: 3 - bit_size: 1 - - name: HSERDYC - description: "HSE ready interrupt clear\r Set by software to clear HSERDYF.\r Reset by hardware when clear done." - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYC - description: "HSI48 ready interrupt clear\r Set by software to clear HSI48RDYF.\r Reset by hardware when clear done." - bit_offset: 5 - bit_size: 1 - - name: PLLRDYC - description: "PLL1 ready interrupt clear\r Set by software to clear PLL1RDYF.\r Reset by hardware when clear done." - bit_offset: 6 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: HSECSSC - description: "HSE clock security system interrupt clear\r Set by software to clear HSECSSF.\r Reset by hardware when clear done." - bit_offset: 10 - bit_size: 1 + - name: LSIRDYC + description: "LSI ready interrupt clear\r Set by software to clear LSIRDYF.\r Reset by hardware when clear done." + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: "LSE ready interrupt clear\r Set by software to clear LSERDYF.\r Reset by hardware when clear done." + bit_offset: 1 + bit_size: 1 + - name: CSIRDYC + description: "HSI ready interrupt clear\r Set by software to clear CSIRDYF.\r Reset by hardware when clear done." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYC + description: "HSI ready interrupt clear\r Set by software to clear HSIRDYF.\r Reset by hardware when clear done." + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: "HSE ready interrupt clear\r Set by software to clear HSERDYF.\r Reset by hardware when clear done." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYC + description: "HSI48 ready interrupt clear\r Set by software to clear HSI48RDYF.\r Reset by hardware when clear done." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYC + description: "PLL1 ready interrupt clear\r Set by software to clear PLL1RDYF.\r Reset by hardware when clear done." + bit_offset: 6 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: HSECSSC + description: "HSE clock security system interrupt clear\r Set by software to clear HSECSSF.\r Reset by hardware when clear done." + bit_offset: 10 + bit_size: 1 fieldset/CIER: description: RCC clock source interrupt enable register fields: - - name: LSIRDYIE - description: "LSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization." - bit_offset: 0 - bit_size: 1 - - name: LSERDYIE - description: "LSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization." - bit_offset: 1 - bit_size: 1 - - name: CSIRDYIE - description: "CSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization." - bit_offset: 2 - bit_size: 1 - - name: HSIRDYIE - description: "HSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization." - bit_offset: 3 - bit_size: 1 - - name: HSERDYIE - description: "HSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization." - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYIE - description: "HSI48 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization." - bit_offset: 5 - bit_size: 1 - - name: PLLRDYIE - description: "PLL1 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by PLL1 lock." - bit_offset: 6 - bit_size: 1 - array: - len: 2 - stride: 1 + - name: LSIRDYIE + description: "LSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization." + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: "LSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization." + bit_offset: 1 + bit_size: 1 + - name: CSIRDYIE + description: "CSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYIE + description: "HSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization." + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: "HSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYIE + description: "HSI48 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYIE + description: "PLL1 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by PLL1 lock." + bit_offset: 6 + bit_size: 1 + array: + len: 2 + stride: 1 fieldset/CIFR: description: RCC clock source interrupt flag register fields: - - name: LSIRDYF - description: "LSI ready interrupt flag\r Reset by software by writing LSIRDYC bit.\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set." - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: "LSE ready interrupt flag\r Reset by software by writing LSERDYC bit.\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set." - bit_offset: 1 - bit_size: 1 - - name: CSIRDYF - description: "CSI ready interrupt flag\r Reset by software by writing CSIRDYC bit.\r Set by hardware when the CSI clock becomes stable and CSIRDYIE is set." - bit_offset: 2 - bit_size: 1 - - name: HSIRDYF - description: "HSI ready interrupt flag\r Reset by software by writing HSIRDYC bit.\r Set by hardware when the HSI clock becomes stable and HSIRDYIE is set." - bit_offset: 3 - bit_size: 1 - - name: HSERDYF - description: "HSE ready interrupt flag\r Reset by software by writing HSERDYC bit.\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set." - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYF - description: "HSI48 ready interrupt flag\r Reset by software by writing HSI48RDYC bit.\r Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set." - bit_offset: 5 - bit_size: 1 - - name: PLLRDYF - description: "PLL1 ready interrupt flag\r Reset by software by writing PLL1RDYC bit.\r Set by hardware when the PLL1 locks and PLL1RDYIE is set." - bit_offset: 6 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: HSECSSF - description: "HSE clock security system interrupt flag\r Reset by software by writing HSECSSC bit.\r Set by hardware in case of HSE clock failure." - bit_offset: 10 - bit_size: 1 + - name: LSIRDYF + description: "LSI ready interrupt flag\r Reset by software by writing LSIRDYC bit.\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set." + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: "LSE ready interrupt flag\r Reset by software by writing LSERDYC bit.\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set." + bit_offset: 1 + bit_size: 1 + - name: CSIRDYF + description: "CSI ready interrupt flag\r Reset by software by writing CSIRDYC bit.\r Set by hardware when the CSI clock becomes stable and CSIRDYIE is set." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYF + description: "HSI ready interrupt flag\r Reset by software by writing HSIRDYC bit.\r Set by hardware when the HSI clock becomes stable and HSIRDYIE is set." + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: "HSE ready interrupt flag\r Reset by software by writing HSERDYC bit.\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYF + description: "HSI48 ready interrupt flag\r Reset by software by writing HSI48RDYC bit.\r Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYF + description: "PLL1 ready interrupt flag\r Reset by software by writing PLL1RDYC bit.\r Set by hardware when the PLL1 locks and PLL1RDYIE is set." + bit_offset: 6 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: HSECSSF + description: "HSE clock security system interrupt flag\r Reset by software by writing HSECSSC bit.\r Set by hardware in case of HSE clock failure." + bit_offset: 10 + bit_size: 1 fieldset/CR: description: RCC clock control register fields: - - name: HSION - description: "HSI clock enable\r Set and cleared by software.\r Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source.\r This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." - bit_offset: 0 - bit_size: 1 - - name: HSIRDY - description: "HSI clock ready flag\r Set by hardware to indicate that the HSI oscillator is stable." - bit_offset: 1 - bit_size: 1 - - name: HSIKERON - description: "HSI clock enable in Stop mode\r Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION." - bit_offset: 2 - bit_size: 1 - - name: HSIDIV - description: "HSI clock divider\r Set and reset by software.\r These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The\r HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored." - bit_offset: 3 - bit_size: 2 - enum: HSIDIV - - name: HSIDIVF - description: "HSI divider flag\r Set and reset by hardware.\r As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the\r current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV." - bit_offset: 5 - bit_size: 1 - - name: CSION - description: "CSI clock enable\r Set and reset by software to enable/disable CSI clock for system and/or peripheral.\r Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." - bit_offset: 8 - bit_size: 1 - - name: CSIRDY - description: "CSI clock ready flag\r Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request)." - bit_offset: 9 - bit_size: 1 - - name: CSIKERON - description: "CSI clock enable in Stop mode\r Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION." - bit_offset: 10 - bit_size: 1 - - name: HSI48ON - description: "HSI48 clock enable\r Set by software and cleared by software or by the hardware when the system enters to Stop\r or Standby mode." - bit_offset: 12 - bit_size: 1 - - name: HSI48RDY - description: "HSI48 clock ready flag\r Set by hardware to indicate that the HSI48 oscillator is stable." - bit_offset: 13 - bit_size: 1 - - name: HSEON - description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE when entering Stop or Standby mode.\r This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the\r HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable." - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: "HSE clock bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device.\r The HSEBYP bit can be written only if the HSE oscillator is disabled." - bit_offset: 18 - bit_size: 1 - - name: HSECSSON - description: "HSE clock security system enable\r Set by software to enable clock security system on HSE.\r This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected." - bit_offset: 19 - bit_size: 1 - - name: HSEEXT - description: "external high speed clock type in Bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled." - bit_offset: 20 - bit_size: 1 - enum: HSEEXT - - name: PLLON - description: "PLL1 enable\r Set and cleared by software to enable PLL1.\r Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents\r writing this bit to 0, if the PLL1 output is used as the system clock." - bit_offset: 24 - bit_size: 1 - array: - len: 2 - stride: 2 - - name: PLLRDY - description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked." - bit_offset: 25 - bit_size: 1 - array: - len: 2 - stride: 2 + - name: HSION + description: "HSI clock enable\r Set and cleared by software.\r Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source.\r This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: "HSI clock ready flag\r Set by hardware to indicate that the HSI oscillator is stable." + bit_offset: 1 + bit_size: 1 + - name: HSIKERON + description: "HSI clock enable in Stop mode\r Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION." + bit_offset: 2 + bit_size: 1 + - name: HSIDIV + description: "HSI clock divider\r Set and reset by software.\r These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The\r HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored." + bit_offset: 3 + bit_size: 2 + enum: HSIDIV + - name: HSIDIVF + description: "HSI divider flag\r Set and reset by hardware.\r As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the\r current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV." + bit_offset: 5 + bit_size: 1 + - name: CSION + description: "CSI clock enable\r Set and reset by software to enable/disable CSI clock for system and/or peripheral.\r Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." + bit_offset: 8 + bit_size: 1 + - name: CSIRDY + description: "CSI clock ready flag\r Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request)." + bit_offset: 9 + bit_size: 1 + - name: CSIKERON + description: "CSI clock enable in Stop mode\r Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION." + bit_offset: 10 + bit_size: 1 + - name: HSI48ON + description: "HSI48 clock enable\r Set by software and cleared by software or by the hardware when the system enters to Stop\r or Standby mode." + bit_offset: 12 + bit_size: 1 + - name: HSI48RDY + description: "HSI48 clock ready flag\r Set by hardware to indicate that the HSI48 oscillator is stable." + bit_offset: 13 + bit_size: 1 + - name: HSEON + description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE when entering Stop or Standby mode.\r This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the\r HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable." + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: "HSE clock bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device.\r The HSEBYP bit can be written only if the HSE oscillator is disabled." + bit_offset: 18 + bit_size: 1 + - name: HSECSSON + description: "HSE clock security system enable\r Set by software to enable clock security system on HSE.\r This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected." + bit_offset: 19 + bit_size: 1 + - name: HSEEXT + description: "external high speed clock type in Bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled." + bit_offset: 20 + bit_size: 1 + enum: HSEEXT + - name: PLLON + description: "PLL1 enable\r Set and cleared by software to enable PLL1.\r Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents\r writing this bit to 0, if the PLL1 output is used as the system clock." + bit_offset: 24 + bit_size: 1 + array: + len: 2 + stride: 2 + - name: PLLRDY + description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked." + bit_offset: 25 + bit_size: 1 + array: + len: 2 + stride: 2 fieldset/CRRCR: description: RCC clock recovery RC register fields: - - name: HSI48CAL - description: "Internal RC 48 MHz clock calibration\r Set by hardware by option-byte loading during system reset NRESET. Read-only." - bit_offset: 0 - bit_size: 10 + - name: HSI48CAL + description: "Internal RC 48 MHz clock calibration\r Set by hardware by option-byte loading during system reset NRESET. Read-only." + bit_offset: 0 + bit_size: 10 fieldset/CSICFGR: description: RCC CSI calibration register fields: - - name: CSICAL - description: "CSI clock calibration\r Set by hardware by option byte loading during system reset NRESET. Adjusted by software through trimming bits CSITRIM.\r This field represents the sum of engineering option byte calibration value and CSITRIM bits value." - bit_offset: 0 - bit_size: 8 - - name: CSITRIM - description: "CSI clock trimming\r Set by software to adjust calibration.\r CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_OPT) in order to form the calibration trimming value.\r CSICAL = CSITRIM + FLASH_CSI_OPT.\r Note: The reset value of the field is 0x20." - bit_offset: 16 - bit_size: 6 + - name: CSICAL + description: "CSI clock calibration\r Set by hardware by option byte loading during system reset NRESET. Adjusted by software through trimming bits CSITRIM.\r This field represents the sum of engineering option byte calibration value and CSITRIM bits value." + bit_offset: 0 + bit_size: 8 + - name: CSITRIM + description: "CSI clock trimming\r Set by software to adjust calibration.\r CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_OPT) in order to form the calibration trimming value.\r CSICAL = CSITRIM + FLASH_CSI_OPT.\r Note: The reset value of the field is 0x20." + bit_offset: 16 + bit_size: 6 fieldset/HSICFGR: description: RCC HSI calibration register fields: - - name: HSICAL - description: "HSI clock calibration\r Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM.\r This field represents the sum of engineering option byte calibration value and HSITRIM bits value." - bit_offset: 0 - bit_size: 12 - - name: HSITRIM - description: "HSI clock trimming\r Set by software to adjust calibration.\r HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_OPT) in order to form the calibration trimming value.\r HSICAL = HSITRIM + FLASH_HSI_OPT.\r After a change of HSITRIM it takes one system clock cycle before the new HSITRIM value is updated\r Note: The reset value of the field is 0x40." - bit_offset: 16 - bit_size: 7 + - name: HSICAL + description: "HSI clock calibration\r Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM.\r This field represents the sum of engineering option byte calibration value and HSITRIM bits value." + bit_offset: 0 + bit_size: 12 + - name: HSITRIM + description: "HSI clock trimming\r Set by software to adjust calibration.\r HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_OPT) in order to form the calibration trimming value.\r HSICAL = HSITRIM + FLASH_HSI_OPT.\r After a change of HSITRIM it takes one system clock cycle before the new HSITRIM value is updated\r Note: The reset value of the field is 0x40." + bit_offset: 16 + bit_size: 7 fieldset/PLLCFGR: description: RCC PLL clock source selection register fields: - - name: PLLSRC - description: "DIVMx and PLLs clock source selection\r Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled.\r In order to save power, when no PLL is used, the value of PLL1SRC must be set to '00'. 00: no clock send to DIVMx divider and PLLs (default after reset)." - bit_offset: 0 - bit_size: 2 - enum: PLLSRC - - name: PLLRGE - description: "PLL1 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1." - bit_offset: 2 - bit_size: 2 - enum: PLLRGE - - name: PLLFRACEN - description: "PLL1 fractional latch enable\r Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator.\r In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator." - bit_offset: 4 - bit_size: 1 - - name: PLLVCOSEL - description: "PLL1 VCO selection\r Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1." - bit_offset: 5 - bit_size: 1 - enum: PLLVCOSEL - - name: DIVM - description: "prescaler for PLL1\r Set and cleared by software to configure the prescaler of the PLL1.\r The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1).\r In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0.\r ...\r ..." - bit_offset: 8 - bit_size: 6 - - name: PLLPEN - description: "PLL1 DIVP divider output enable\r Set and reset by software to enable the pll1_p_ck output of the PLL1.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled." - bit_offset: 16 - bit_size: 1 - - name: PLLQEN - description: "PLL1 DIVQ divider output enable\r Set and reset by software to enable the pll1_q_ck output of the PLL1.\r In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." - bit_offset: 17 - bit_size: 1 - - name: PLLREN - description: "PLL1 DIVR divider output enable\r Set and reset by software to enable the pll1_r_ck output of the PLL1.\r To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." - bit_offset: 18 - bit_size: 1 + - name: PLLSRC + description: "DIVMx and PLLs clock source selection\r Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled.\r In order to save power, when no PLL is used, the value of PLL1SRC must be set to '00'. 00: no clock send to DIVMx divider and PLLs (default after reset)." + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: PLLRGE + description: "PLL1 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1." + bit_offset: 2 + bit_size: 2 + enum: PLLRGE + - name: PLLFRACEN + description: "PLL1 fractional latch enable\r Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator.\r In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator." + bit_offset: 4 + bit_size: 1 + - name: PLLVCOSEL + description: "PLL1 VCO selection\r Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1." + bit_offset: 5 + bit_size: 1 + enum: PLLVCOSEL + - name: DIVM + description: "prescaler for PLL1\r Set and cleared by software to configure the prescaler of the PLL1.\r The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1).\r In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0.\r ...\r ..." + bit_offset: 8 + bit_size: 6 + - name: PLLPEN + description: "PLL1 DIVP divider output enable\r Set and reset by software to enable the pll1_p_ck output of the PLL1.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled." + bit_offset: 16 + bit_size: 1 + - name: PLLQEN + description: "PLL1 DIVQ divider output enable\r Set and reset by software to enable the pll1_q_ck output of the PLL1.\r In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." + bit_offset: 17 + bit_size: 1 + - name: PLLREN + description: "PLL1 DIVR divider output enable\r Set and reset by software to enable the pll1_r_ck output of the PLL1.\r To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." + bit_offset: 18 + bit_size: 1 fieldset/PLLDIVR: description: RCC PLL1 dividers register fields: - - name: PLLN - description: "Multiplication factor for PLL1VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved" - bit_offset: 0 - bit_size: 9 - - name: PLLP - description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..." - bit_offset: 9 - bit_size: 7 - - name: PLLQ - description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." - bit_offset: 16 - bit_size: 7 - - name: PLLR - description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." - bit_offset: 24 - bit_size: 7 + - name: PLLN + description: "Multiplication factor for PLL1VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved" + bit_offset: 0 + bit_size: 9 + - name: PLLP + description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..." + bit_offset: 9 + bit_size: 7 + - name: PLLQ + description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." + bit_offset: 16 + bit_size: 7 + - name: PLLR + description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." + bit_offset: 24 + bit_size: 7 fieldset/PLLFRACR: description: RCC PLL1 fractional divider register fields: - - name: PLLFRACN - description: "fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:\r * 128 to 560 MHz if PLL1VCOSEL = 0\r * \t150 to 420 MHz if PLL1VCOSEL = 1\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with\r * \tPLL1N between 8 and 420\r * \tPLL1FRACN can be between 0 and 213- 1\r * \tThe input frequency Fref1_ck must be between 1 and 16 MHz.\r To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r * \tSet the bit PLL1FRACEN to 0\r * \tWrite the new fractional value into PLL1FRACN\r * \tSet the bit PLL1FRACEN to 1" - bit_offset: 3 - bit_size: 13 + - name: PLLFRACN + description: "fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:\r * 128 to 560 MHz if PLL1VCOSEL = 0\r * \t150 to 420 MHz if PLL1VCOSEL = 1\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with\r * \tPLL1N between 8 and 420\r * \tPLL1FRACN can be between 0 and 213- 1\r * \tThe input frequency Fref1_ck must be between 1 and 16 MHz.\r To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r * \tSet the bit PLL1FRACEN to 0\r * \tWrite the new fractional value into PLL1FRACN\r * \tSet the bit PLL1FRACEN to 1" + bit_offset: 3 + bit_size: 13 fieldset/RSR: description: RCC reset status register fields: - - name: RMVF - description: "remove reset flag\r Set and reset by software to reset the value of the reset flags." - bit_offset: 23 - bit_size: 1 - - name: PINRSTF - description: "pin reset flag (NRST)\r Reset by software by writing the RMVF bit.\r Set by hardware when a reset from pin occurs." - bit_offset: 26 - bit_size: 1 - - name: BORRSTF - description: "BOR reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a BOR reset occurs (pwr_bor_rst)." - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: "system reset from CPU reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M33." - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: "independent watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when an independent watchdog reset occurs." - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: "window watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a window watchdog reset occurs." - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: "Low-power reset flag\r Set by hardware when a reset occurs due to Stop or Standby mode entry, whereas the corresponding nRST_STOP, nRST_STBY option bit is cleared.\r Cleared by writing to the RMVF bit." - bit_offset: 31 - bit_size: 1 + - name: RMVF + description: "remove reset flag\r Set and reset by software to reset the value of the reset flags." + bit_offset: 23 + bit_size: 1 + - name: PINRSTF + description: "pin reset flag (NRST)\r Reset by software by writing the RMVF bit.\r Set by hardware when a reset from pin occurs." + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: "BOR reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a BOR reset occurs (pwr_bor_rst)." + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: "system reset from CPU reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M33." + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: "independent watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when an independent watchdog reset occurs." + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: "window watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a window watchdog reset occurs." + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: "Low-power reset flag\r Set by hardware when a reset occurs due to Stop or Standby mode entry, whereas the corresponding nRST_STOP, nRST_STBY option bit is cleared.\r Cleared by writing to the RMVF bit." + bit_offset: 31 + bit_size: 1 enum/ADCDACSEL: bit_size: 3 variants: - - name: HCLK - description: rcc_hclk selected as kernel clock (default after reset) - value: 0 - - name: SYSCLK - description: sys_ck selected as kernel clock - value: 1 - - name: PLL2_R - description: pll2_r_ck selected as kernel clock - value: 2 - - name: HSE - description: hse_ck selected as kernel clock - value: 3 - - name: HSI_KER - description: hsi_ker_ck selected as kernel clock - value: 4 - - name: CSI_KER - description: csi_ker_ck selected as kernel clock - value: 5 + - name: HCLK + description: rcc_hclk selected as kernel clock (default after reset) + value: 0 + - name: SYSCLK + description: sys_ck selected as kernel clock + value: 1 + - name: PLL2_R + description: pll2_r_ck selected as kernel clock + value: 2 + - name: HSE + description: hse_ck selected as kernel clock + value: 3 + - name: HSI_KER + description: hsi_ker_ck selected as kernel clock + value: 4 + - name: CSI_KER + description: csi_ker_ck selected as kernel clock + value: 5 enum/CKPERSEL: bit_size: 2 variants: - - name: HSI - description: hsi_ker_ck selected as kernel clock (default after reset) - value: 0 - - name: CSI - description: csi_ker_ck selected as kernel clock - value: 1 - - name: HSE - description: hse_ck selected as kernel clock - value: 2 + - name: HSI + description: hsi_ker_ck selected as kernel clock (default after reset) + value: 0 + - name: CSI + description: csi_ker_ck selected as kernel clock + value: 1 + - name: HSE + description: hse_ck selected as kernel clock + value: 2 enum/DACSEL: bit_size: 1 variants: - - name: DAC_HOLD - description: dac_hold_ck selected as kernel clock (default after reset) - value: 0 - - name: DAC_HOLD_2 - description: dac_hold_ck selected as kernel clock - value: 1 + - name: DAC_HOLD + description: dac_hold_ck selected as kernel clock (default after reset) + value: 0 + - name: DAC_HOLD_2 + description: dac_hold_ck selected as kernel clock + value: 1 enum/FDCANSEL: bit_size: 2 variants: - - name: HSE - description: hse_ck selected as kernel clock (default after reset) - value: 0 - - name: PLL1_Q - description: pll1_q_ck selected as kernel clock - value: 1 - - name: PLL2_Q - description: pll2_q_ck selected as kernel clock - value: 2 + - name: HSE + description: hse_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock + value: 1 + - name: PLL2_Q + description: pll2_q_ck selected as kernel clock + value: 2 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: sys_ck not divided - value: 0 - - name: Div2 - description: sys_ck divided by 2 - value: 8 - - name: Div4 - description: sys_ck divided by 4 - value: 9 - - name: Div8 - description: sys_ck divided by 8 - value: 10 - - name: Div16 - description: sys_ck divided by 16 - value: 11 - - name: Div64 - description: sys_ck divided by 64 - value: 12 - - name: Div128 - description: sys_ck divided by 128 - value: 13 - - name: Div256 - description: sys_ck divided by 256 - value: 14 - - name: Div512 - description: sys_ck divided by 512 - value: 15 + - name: Div1 + description: sys_ck not divided + value: 0 + - name: Div2 + description: sys_ck divided by 2 + value: 8 + - name: Div4 + description: sys_ck divided by 4 + value: 9 + - name: Div8 + description: sys_ck divided by 8 + value: 10 + - name: Div16 + description: sys_ck divided by 16 + value: 11 + - name: Div64 + description: sys_ck divided by 64 + value: 12 + - name: Div128 + description: sys_ck divided by 128 + value: 13 + - name: Div256 + description: sys_ck divided by 256 + value: 14 + - name: Div512 + description: sys_ck divided by 512 + value: 15 enum/HSEEXT: bit_size: 1 variants: - - name: Analog - description: HSE in analog mode (default after reset) - value: 0 - - name: Digital - description: HSE in digital mode - value: 1 + - name: Analog + description: HSE in analog mode (default after reset) + value: 0 + - name: Digital + description: HSE in digital mode + value: 1 enum/HSIDIV: bit_size: 2 variants: - - name: Div1 - description: No division - value: 0 - - name: Div2 - description: Division by 2 - value: 1 - - name: Div4 - description: Division by 4 - value: 2 - - name: Div8 - description: Division by 8 - value: 3 + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 enum/ICSEL: bit_size: 2 variants: - - name: RCC_PCLK1 - description: rcc_pclk1 selected as peripheral clock - value: 0 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 1 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 2 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 3 + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 2 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 3 enum/LPTIMSEL: bit_size: 3 variants: - - name: RCC_PCLK3 - description: rcc_pclk3 selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: LSE - description: LSE selected as peripheral clock - value: 3 - - name: LSI - description: LSI selected as peripheral clock - value: 4 - - name: PER - description: PER selected as peripheral clock - value: 5 + - name: RCC_PCLK3 + description: rcc_pclk3 selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: LSE + description: LSE selected as peripheral clock + value: 3 + - name: LSI + description: LSI selected as peripheral clock + value: 4 + - name: PER + description: PER selected as peripheral clock + value: 5 enum/LPUARTSEL: bit_size: 3 variants: - - name: RCC_PCLK3 - description: rcc_pclk3 selected as kernel clock (default after reset) - value: 0 - - name: PLL2_Q - description: pll2_q_ck selected as kernel clock - value: 1 - - name: HSI_KER - description: hsi_ker_ck selected as kernel clock - value: 3 - - name: CSI_KER - description: csi_ker_ck selected as kernel clock - value: 4 - - name: LSE - description: lse_ck selected as kernel clock - value: 5 + - name: RCC_PCLK3 + description: rcc_pclk3 selected as kernel clock (default after reset) + value: 0 + - name: PLL2_Q + description: pll2_q_ck selected as kernel clock + value: 1 + - name: HSI_KER + description: hsi_ker_ck selected as kernel clock + value: 3 + - name: CSI_KER + description: csi_ker_ck selected as kernel clock + value: 4 + - name: LSE + description: lse_ck selected as kernel clock + value: 5 enum/LSCOSEL: bit_size: 1 variants: - - name: LSI - description: LSI clock selected - value: 0 - - name: LSE - description: LSE clock selected - value: 1 + - name: LSI + description: LSI clock selected + value: 0 + - name: LSE + description: LSE clock selected + value: 1 enum/LSEDRV: bit_size: 2 variants: - - name: Lowest - description: Lowest LSE oscillator driving capability - value: 0 - - name: MediumLow - description: Medium low LSE oscillator driving capability - value: 1 - - name: MediumHigh - description: Medium high LSE oscillator driving capability - value: 2 - - name: Highest - description: Highest LSE oscillator driving capability - value: 3 + - name: Lowest + description: Lowest LSE oscillator driving capability + value: 0 + - name: MediumLow + description: Medium low LSE oscillator driving capability + value: 1 + - name: MediumHigh + description: Medium high LSE oscillator driving capability + value: 2 + - name: Highest + description: Highest LSE oscillator driving capability + value: 3 enum/LSEEXT: bit_size: 1 variants: - - name: Analog - description: LSE in analog mode (default after Backup domain reset) - value: 0 - - name: Digital - description: LSE in digital mode (do not use if RTC is active). - value: 1 + - name: Analog + description: LSE in analog mode (default after Backup domain reset) + value: 0 + - name: Digital + description: LSE in digital mode (do not use if RTC is active). + value: 1 enum/MCO1: bit_size: 3 variants: - - name: HSI - description: HSI selected for micro-controller clock output - value: 0 - - name: LSE - description: LSE selected for micro-controller clock output - value: 1 - - name: HSE - description: HSE selected for micro-controller clock output - value: 2 - - name: PLL1_Q - description: pll1_q selected for micro-controller clock output - value: 3 - - name: HSI48 - description: HSI48 selected for micro-controller clock output - value: 4 + - name: HSI + description: HSI selected for micro-controller clock output + value: 0 + - name: LSE + description: LSE selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_Q + description: pll1_q selected for micro-controller clock output + value: 3 + - name: HSI48 + description: HSI48 selected for micro-controller clock output + value: 4 enum/MCO2: bit_size: 3 variants: - - name: SYSCLK - description: System clock selected for micro-controller clock output - value: 0 - - name: PLL2_P - description: pll2_p selected for micro-controller clock output - value: 1 - - name: HSE - description: HSE selected for micro-controller clock output - value: 2 - - name: PLL1_P - description: pll1_p selected for micro-controller clock output - value: 3 - - name: CSI - description: CSI selected for micro-controller clock output - value: 4 - - name: LSI - description: LSI selected for micro-controller clock output - value: 5 + - name: SYSCLK + description: System clock selected for micro-controller clock output + value: 0 + - name: PLL2_P + description: pll2_p selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_P + description: pll1_p selected for micro-controller clock output + value: 3 + - name: CSI + description: CSI selected for micro-controller clock output + value: 4 + - name: LSI + description: LSI selected for micro-controller clock output + value: 5 enum/PLLRGE: bit_size: 2 variants: - - name: Range1 - description: Frequency is between 1 and 2 MHz - value: 0 - - name: Range2 - description: Frequency is between 2 and 4 MHz - value: 1 - - name: Range4 - description: Frequency is between 4 and 8 MHz - value: 2 - - name: Range8 - description: Frequency is between 8 and 16 MHz - value: 3 + - name: Range1 + description: Frequency is between 1 and 2 MHz + value: 0 + - name: Range2 + description: Frequency is between 2 and 4 MHz + value: 1 + - name: Range4 + description: Frequency is between 4 and 8 MHz + value: 2 + - name: Range8 + description: Frequency is between 8 and 16 MHz + value: 3 enum/PLLSRC: bit_size: 2 variants: - - name: None - description: no clock send to DIVMx divider and PLLs (default after reset) - value: 0 - - name: HSI - description: HSI selected as PLL clock (hsi_ck) - value: 1 - - name: CSI - description: CSI selected as PLL clock (csi_ck) - value: 2 - - name: HSE - description: HSE selected as PLL clock (hse_ck) - value: 3 + - name: None + description: no clock send to DIVMx divider and PLLs (default after reset) + value: 0 + - name: HSI + description: HSI selected as PLL clock (hsi_ck) + value: 1 + - name: CSI + description: CSI selected as PLL clock (csi_ck) + value: 2 + - name: HSE + description: HSE selected as PLL clock (hse_ck) + value: 3 enum/PLLVCOSEL: bit_size: 1 variants: - - name: WideVCO - description: VCO frequency range 192 to 836 MHz - value: 0 - - name: MediumVCO - description: VCO frequency range 150 to 420 MHz - value: 1 + - name: WideVCO + description: VCO frequency range 192 to 836 MHz + value: 0 + - name: MediumVCO + description: VCO frequency range 150 to 420 MHz + value: 1 enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: rcc_pclk3 = rcc_hclk1 / 1 - value: 0 - - name: Div2 - description: rcc_pclk3 = rcc_hclk1 / 2 - value: 4 - - name: Div4 - description: rcc_pclk3 = rcc_hclk1 / 4 - value: 5 - - name: Div8 - description: rcc_pclk3 = rcc_hclk1 / 8 - value: 6 - - name: Div16 - description: rcc_pclk3 = rcc_hclk1 / 16 - value: 7 + - name: Div1 + description: rcc_pclk3 = rcc_hclk1 / 1 + value: 0 + - name: Div2 + description: rcc_pclk3 = rcc_hclk1 / 2 + value: 4 + - name: Div4 + description: rcc_pclk3 = rcc_hclk1 / 4 + value: 5 + - name: Div8 + description: rcc_pclk3 = rcc_hclk1 / 8 + value: 6 + - name: Div16 + description: rcc_pclk3 = rcc_hclk1 / 16 + value: 7 enum/RNGSEL: bit_size: 2 variants: - - name: HSI48_KER - description: hsi48_ker_ck selected as kernel clock (default after reset) - value: 0 - - name: PLL1_Q - description: pll1_q_ck selected as kernel clock - value: 1 - - name: LSE - description: lse_ck selected as kernel clock - value: 2 - - name: LSI_KER - description: lsi_ker_ck selected as kernel clock - value: 3 + - name: HSI48_KER + description: hsi48_ker_ck selected as kernel clock (default after reset) + value: 0 + - name: PLL1_Q + description: pll1_q_ck selected as kernel clock + value: 1 + - name: LSE + description: lse_ck selected as kernel clock + value: 2 + - name: LSI_KER + description: lsi_ker_ck selected as kernel clock + value: 3 enum/RTCSEL: bit_size: 2 variants: - - name: None - description: no clock (default after Backup domain reset) - value: 0 - - name: LSE - description: LSE selected as RTC clock - value: 1 - - name: LSI - description: LSI selected as RTC clock - value: 2 - - name: HSE_DIV_RTCPRE - description: HSE divided by RTCPRE value selected as RTC clock - value: 3 + - name: NoClock + description: no clock (default after Backup domain reset) + value: 0 + - name: LSE + description: LSE selected as RTC clock + value: 1 + - name: LSI + description: LSI selected as RTC clock + value: 2 + - name: HSE_DIV_RTCPRE + description: HSE divided by RTCPRE value selected as RTC clock + value: 3 enum/SPISEL: bit_size: 3 variants: - - name: RCC_PCLK4 - description: rcc_pclk4 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 + - name: RCC_PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 enum/STOPKERWUCK: bit_size: 1 variants: - - name: HSI - description: HSI selected as wakeup clock from system Stop (default after reset) - value: 0 - - name: CSI - description: CSI selected as wakeup clock from system Stop - value: 1 + - name: HSI + description: HSI selected as wakeup clock from system Stop (default after reset) + value: 0 + - name: CSI + description: CSI selected as wakeup clock from system Stop + value: 1 enum/STOPWUCK: bit_size: 1 variants: - - name: CSI - description: CSI selected as wakeup clock from system Stop - value: 1 + - name: CSI + description: CSI selected as wakeup clock from system Stop + value: 1 enum/SW: bit_size: 3 variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: CSI - description: CSI selected as system clock - value: 1 - - name: HSE - description: HSE selected as system clock - value: 2 - - name: PLL1 - description: PLL1 selected as system clock - value: 3 + - name: HSI + description: HSI selected as system clock + value: 0 + - name: CSI + description: CSI selected as system clock + value: 1 + - name: HSE + description: HSE selected as system clock + value: 2 + - name: PLL1 + description: PLL1 selected as system clock + value: 3 enum/SYSTICKSEL: bit_size: 2 variants: - - name: HCLK_DIV_8 - description: rcc_hclk/8 selected as clock source (default after reset) - value: 0 - - name: LSI_KER - description: "lsi_ker_ck[1] selected as clock source" - value: 1 - - name: LSE - description: "lse_ck[1] selected as clock source" - value: 2 + - name: HCLK_DIV_8 + description: rcc_hclk/8 selected as clock source (default after reset) + value: 0 + - name: LSI_KER + description: lsi_ker_ck[1] selected as clock source + value: 1 + - name: LSE + description: lse_ck[1] selected as clock source + value: 2 enum/TIMICSEL: bit_size: 1 variants: - - name: B_0x0 - description: No internal clock available for timers input capture (default after reset) - value: 0 - - name: B_0x1 - description: "hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture" - value: 1 + - name: B_0x0 + description: No internal clock available for timers input capture (default after reset) + value: 0 + - name: B_0x1 + description: hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture + value: 1 enum/TIMPRE: bit_size: 1 variants: - - name: DefaultX2 - description: "The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 (default after reset)" - value: 0 - - name: DefaultX4 - description: "The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2" - value: 1 + - name: DefaultX2 + description: The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 (default after reset) + value: 0 + - name: DefaultX4 + description: The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2 + value: 1 enum/USARTSEL: bit_size: 3 variants: - - name: RCC_PCLK2 - description: rcc_pclk2 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: LSE - description: LSE selected as peripheral clock - value: 5 + - name: RCC_PCLK2 + description: rcc_pclk2 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 enum/USBSEL: bit_size: 2 variants: - - name: DISABLE - description: Disable the kernel clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: HSI48 - description: HSI48 selected as peripheral clock - value: 3 + - name: DISABLE + description: Disable the kernel clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: HSI48 + description: HSI48 selected as peripheral clock + value: 3 diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index fd9da11..fe7e7eb 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -1,4319 +1,4052 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: clock control register - byte_offset: 0 - fieldset: CR - - name: HSICFGR - description: RCC HSI configuration register - byte_offset: 4 - fieldset: HSICFGR - - name: CRRCR - description: RCC Clock Recovery RC Register - byte_offset: 8 - access: Read - fieldset: CRRCR - - name: CSICFGR - description: RCC CSI configuration register - byte_offset: 12 - fieldset: CSICFGR - - name: CFGR - description: RCC Clock Configuration Register - byte_offset: 16 - fieldset: CFGR - - name: D1CFGR - description: RCC Domain 1 Clock Configuration Register - byte_offset: 24 - fieldset: D1CFGR - - name: D2CFGR - description: RCC Domain 2 Clock Configuration Register - byte_offset: 28 - fieldset: D2CFGR - - name: D3CFGR - description: RCC Domain 3 Clock Configuration Register - byte_offset: 32 - fieldset: D3CFGR - - name: PLLCKSELR - description: RCC PLLs Clock Source Selection Register - byte_offset: 40 - fieldset: PLLCKSELR - - name: PLLCFGR - description: RCC PLLs Configuration Register - byte_offset: 44 - fieldset: PLLCFGR - - name: PLLDIVR - description: RCC PLL1 Dividers Configuration Register - array: - len: 3 - stride: 8 - byte_offset: 48 - fieldset: PLL1DIVR - - name: PLLFRACR - description: RCC PLL1 Fractional Divider Register - array: - len: 3 - stride: 8 - byte_offset: 52 - fieldset: PLL1FRACR - - name: D1CCIPR - description: RCC Domain 1 Kernel Clock Configuration Register - byte_offset: 76 - fieldset: D1CCIPR - - name: D2CCIP1R - description: RCC Domain 2 Kernel Clock Configuration Register - byte_offset: 80 - fieldset: D2CCIP1R - - name: D2CCIP2R - description: RCC Domain 2 Kernel Clock Configuration Register - byte_offset: 84 - fieldset: D2CCIP2R - - name: D3CCIPR - description: RCC Domain 3 Kernel Clock Configuration Register - byte_offset: 88 - fieldset: D3CCIPR - - name: CIER - description: RCC Clock Source Interrupt Enable Register - byte_offset: 96 - fieldset: CIER - - name: CIFR - description: RCC Clock Source Interrupt Flag Register - byte_offset: 100 - access: Read - fieldset: CIFR - - name: CICR - description: RCC Clock Source Interrupt Clear Register - byte_offset: 104 - fieldset: CICR - - name: BDCR - description: RCC Backup Domain Control Register - byte_offset: 112 - fieldset: BDCR - - name: CSR - description: RCC Clock Control and Status Register - byte_offset: 116 - fieldset: CSR - - name: AHB3RSTR - description: RCC AHB3 Reset Register - byte_offset: 124 - fieldset: AHB3RSTR - - name: AHB1RSTR - description: RCC AHB1 Peripheral Reset Register - byte_offset: 128 - fieldset: AHB1RSTR - - name: AHB2RSTR - description: RCC AHB2 Peripheral Reset Register - byte_offset: 132 - fieldset: AHB2RSTR - - name: AHB4RSTR - description: RCC AHB4 Peripheral Reset Register - byte_offset: 136 - fieldset: AHB4RSTR - - name: APB3RSTR - description: RCC APB3 Peripheral Reset Register - byte_offset: 140 - fieldset: APB3RSTR - - name: APB1LRSTR - description: RCC APB1 Peripheral Reset Register - byte_offset: 144 - fieldset: APB1LRSTR - - name: APB1HRSTR - description: RCC APB1 Peripheral Reset Register - byte_offset: 148 - fieldset: APB1HRSTR - - name: APB2RSTR - description: RCC APB2 Peripheral Reset Register - byte_offset: 152 - fieldset: APB2RSTR - - name: APB4RSTR - description: RCC APB4 Peripheral Reset Register - byte_offset: 156 - fieldset: APB4RSTR - - name: GCR - description: Global Control Register - byte_offset: 160 - fieldset: GCR - - name: D3AMR - description: RCC D3 Autonomous mode Register - byte_offset: 168 - fieldset: D3AMR - - name: RSR - description: RCC Reset Status Register - byte_offset: 208 - fieldset: RSR - - name: AHB3ENR - description: RCC AHB3 Clock Register - byte_offset: 212 - fieldset: AHB3ENR - - name: AHB1ENR - description: RCC AHB1 Clock Register - byte_offset: 216 - fieldset: AHB1ENR - - name: AHB2ENR - description: RCC AHB2 Clock Register - byte_offset: 220 - fieldset: AHB2ENR - - name: AHB4ENR - description: RCC AHB4 Clock Register - byte_offset: 224 - fieldset: AHB4ENR - - name: APB3ENR - description: RCC APB3 Clock Register - byte_offset: 228 - fieldset: APB3ENR - - name: APB1LENR - description: RCC APB1 Clock Register - byte_offset: 232 - fieldset: APB1LENR - - name: APB1HENR - description: RCC APB1 Clock Register - byte_offset: 236 - fieldset: APB1HENR - - name: APB2ENR - description: RCC APB2 Clock Register - byte_offset: 240 - fieldset: APB2ENR - - name: APB4ENR - description: RCC APB4 Clock Register - byte_offset: 244 - fieldset: APB4ENR - - name: AHB3LPENR - description: RCC AHB3 Sleep Clock Register - byte_offset: 252 - fieldset: AHB3LPENR - - name: AHB1LPENR - description: RCC AHB1 Sleep Clock Register - byte_offset: 256 - fieldset: AHB1LPENR - - name: AHB2LPENR - description: RCC AHB2 Sleep Clock Register - byte_offset: 260 - fieldset: AHB2LPENR - - name: AHB4LPENR - description: RCC AHB4 Sleep Clock Register - byte_offset: 264 - fieldset: AHB4LPENR - - name: APB3LPENR - description: RCC APB3 Sleep Clock Register - byte_offset: 268 - fieldset: APB3LPENR - - name: APB1LLPENR - description: RCC APB1 Low Sleep Clock Register - byte_offset: 272 - fieldset: APB1LLPENR - - name: APB1HLPENR - description: RCC APB1 High Sleep Clock Register - byte_offset: 276 - fieldset: APB1HLPENR - - name: APB2LPENR - description: RCC APB2 Sleep Clock Register - byte_offset: 280 - fieldset: APB2LPENR - - name: APB4LPENR - description: RCC APB4 Sleep Clock Register - byte_offset: 284 - fieldset: APB4LPENR - - name: C1_RSR - description: RCC Reset Status Register - byte_offset: 304 - fieldset: C1_RSR - - name: C1_AHB3ENR - description: RCC AHB3 Clock Register - byte_offset: 308 - fieldset: C1_AHB3ENR - - name: C1_AHB1ENR - description: RCC AHB1 Clock Register - byte_offset: 312 - fieldset: C1_AHB1ENR - - name: C1_AHB2ENR - description: RCC AHB2 Clock Register - byte_offset: 316 - fieldset: C1_AHB2ENR - - name: C1_AHB4ENR - description: RCC AHB4 Clock Register - byte_offset: 320 - fieldset: C1_AHB4ENR - - name: C1_APB3ENR - description: RCC APB3 Clock Register - byte_offset: 324 - fieldset: C1_APB3ENR - - name: C1_APB1LENR - description: RCC APB1 Clock Register - byte_offset: 328 - fieldset: C1_APB1LENR - - name: C1_APB1HENR - description: RCC APB1 Clock Register - byte_offset: 332 - fieldset: C1_APB1HENR - - name: C1_APB2ENR - description: RCC APB2 Clock Register - byte_offset: 336 - fieldset: C1_APB2ENR - - name: C1_APB4ENR - description: RCC APB4 Clock Register - byte_offset: 340 - fieldset: C1_APB4ENR - - name: C1_AHB3LPENR - description: RCC AHB3 Sleep Clock Register - byte_offset: 348 - fieldset: C1_AHB3LPENR - - name: C1_AHB1LPENR - description: RCC AHB1 Sleep Clock Register - byte_offset: 352 - fieldset: C1_AHB1LPENR - - name: C1_AHB2LPENR - description: RCC AHB2 Sleep Clock Register - byte_offset: 356 - fieldset: C1_AHB2LPENR - - name: C1_AHB4LPENR - description: RCC AHB4 Sleep Clock Register - byte_offset: 360 - fieldset: C1_AHB4LPENR - - name: C1_APB3LPENR - description: RCC APB3 Sleep Clock Register - byte_offset: 364 - fieldset: C1_APB3LPENR - - name: C1_APB1LLPENR - description: RCC APB1 Low Sleep Clock Register - byte_offset: 368 - fieldset: C1_APB1LLPENR - - name: C1_APB1HLPENR - description: RCC APB1 High Sleep Clock Register - byte_offset: 372 - fieldset: C1_APB1HLPENR - - name: C1_APB2LPENR - description: RCC APB2 Sleep Clock Register - byte_offset: 376 - fieldset: C1_APB2LPENR - - name: C1_APB4LPENR - description: RCC APB4 Sleep Clock Register - byte_offset: 380 - fieldset: C1_APB4LPENR + - name: CR + description: clock control register + byte_offset: 0 + fieldset: CR + - name: HSICFGR + description: RCC HSI configuration register + byte_offset: 4 + fieldset: HSICFGR + - name: CRRCR + description: RCC Clock Recovery RC Register + byte_offset: 8 + access: Read + fieldset: CRRCR + - name: CSICFGR + description: RCC CSI configuration register + byte_offset: 12 + fieldset: CSICFGR + - name: CFGR + description: RCC Clock Configuration Register + byte_offset: 16 + fieldset: CFGR + - name: D1CFGR + description: RCC Domain 1 Clock Configuration Register + byte_offset: 24 + fieldset: D1CFGR + - name: D2CFGR + description: RCC Domain 2 Clock Configuration Register + byte_offset: 28 + fieldset: D2CFGR + - name: D3CFGR + description: RCC Domain 3 Clock Configuration Register + byte_offset: 32 + fieldset: D3CFGR + - name: PLLCKSELR + description: RCC PLLs Clock Source Selection Register + byte_offset: 40 + fieldset: PLLCKSELR + - name: PLLCFGR + description: RCC PLLs Configuration Register + byte_offset: 44 + fieldset: PLLCFGR + - name: PLLDIVR + description: RCC PLL1 Dividers Configuration Register + array: + len: 3 + stride: 8 + byte_offset: 48 + fieldset: PLLDIVR + - name: PLLFRACR + description: RCC PLL1 Fractional Divider Register + array: + len: 3 + stride: 8 + byte_offset: 52 + fieldset: PLLFRACR + - name: D1CCIPR + description: RCC Domain 1 Kernel Clock Configuration Register + byte_offset: 76 + fieldset: D1CCIPR + - name: D2CCIP1R + description: RCC Domain 2 Kernel Clock Configuration Register + byte_offset: 80 + fieldset: D2CCIP1R + - name: D2CCIP2R + description: RCC Domain 2 Kernel Clock Configuration Register + byte_offset: 84 + fieldset: D2CCIP2R + - name: D3CCIPR + description: RCC Domain 3 Kernel Clock Configuration Register + byte_offset: 88 + fieldset: D3CCIPR + - name: CIER + description: RCC Clock Source Interrupt Enable Register + byte_offset: 96 + fieldset: CIER + - name: CIFR + description: RCC Clock Source Interrupt Flag Register + byte_offset: 100 + access: Read + fieldset: CIFR + - name: CICR + description: RCC Clock Source Interrupt Clear Register + byte_offset: 104 + fieldset: CICR + - name: BDCR + description: RCC Backup Domain Control Register + byte_offset: 112 + fieldset: BDCR + - name: CSR + description: RCC Clock Control and Status Register + byte_offset: 116 + fieldset: CSR + - name: AHB3RSTR + description: RCC AHB3 Reset Register + byte_offset: 124 + fieldset: AHB3RSTR + - name: AHB1RSTR + description: RCC AHB1 Peripheral Reset Register + byte_offset: 128 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: RCC AHB2 Peripheral Reset Register + byte_offset: 132 + fieldset: AHB2RSTR + - name: AHB4RSTR + description: RCC AHB4 Peripheral Reset Register + byte_offset: 136 + fieldset: AHB4RSTR + - name: APB3RSTR + description: RCC APB3 Peripheral Reset Register + byte_offset: 140 + fieldset: APB3RSTR + - name: APB1LRSTR + description: RCC APB1 Peripheral Reset Register + byte_offset: 144 + fieldset: APB1LRSTR + - name: APB1HRSTR + description: RCC APB1 Peripheral Reset Register + byte_offset: 148 + fieldset: APB1HRSTR + - name: APB2RSTR + description: RCC APB2 Peripheral Reset Register + byte_offset: 152 + fieldset: APB2RSTR + - name: APB4RSTR + description: RCC APB4 Peripheral Reset Register + byte_offset: 156 + fieldset: APB4RSTR + - name: GCR + description: Global Control Register + byte_offset: 160 + fieldset: GCR + - name: D3AMR + description: RCC D3 Autonomous mode Register + byte_offset: 168 + fieldset: D3AMR + - name: RSR + description: RCC Reset Status Register + byte_offset: 208 + fieldset: RSR + - name: AHB3ENR + description: RCC AHB3 Clock Register + byte_offset: 212 + fieldset: AHB3ENR + - name: AHB1ENR + description: RCC AHB1 Clock Register + byte_offset: 216 + fieldset: AHB1ENR + - name: AHB2ENR + description: RCC AHB2 Clock Register + byte_offset: 220 + fieldset: AHB2ENR + - name: AHB4ENR + description: RCC AHB4 Clock Register + byte_offset: 224 + fieldset: AHB4ENR + - name: APB3ENR + description: RCC APB3 Clock Register + byte_offset: 228 + fieldset: APB3ENR + - name: APB1LENR + description: RCC APB1 Clock Register + byte_offset: 232 + fieldset: APB1LENR + - name: APB1HENR + description: RCC APB1 Clock Register + byte_offset: 236 + fieldset: APB1HENR + - name: APB2ENR + description: RCC APB2 Clock Register + byte_offset: 240 + fieldset: APB2ENR + - name: APB4ENR + description: RCC APB4 Clock Register + byte_offset: 244 + fieldset: APB4ENR + - name: AHB3LPENR + description: RCC AHB3 Sleep Clock Register + byte_offset: 252 + fieldset: AHB3LPENR + - name: AHB1LPENR + description: RCC AHB1 Sleep Clock Register + byte_offset: 256 + fieldset: AHB1LPENR + - name: AHB2LPENR + description: RCC AHB2 Sleep Clock Register + byte_offset: 260 + fieldset: AHB2LPENR + - name: AHB4LPENR + description: RCC AHB4 Sleep Clock Register + byte_offset: 264 + fieldset: AHB4LPENR + - name: APB3LPENR + description: RCC APB3 Sleep Clock Register + byte_offset: 268 + fieldset: APB3LPENR + - name: APB1LLPENR + description: RCC APB1 Low Sleep Clock Register + byte_offset: 272 + fieldset: APB1LLPENR + - name: APB1HLPENR + description: RCC APB1 High Sleep Clock Register + byte_offset: 276 + fieldset: APB1HLPENR + - name: APB2LPENR + description: RCC APB2 Sleep Clock Register + byte_offset: 280 + fieldset: APB2LPENR + - name: APB4LPENR + description: RCC APB4 Sleep Clock Register + byte_offset: 284 + fieldset: APB4LPENR + - name: C1_RSR + description: RCC Reset Status Register + byte_offset: 304 + fieldset: C1_RSR + - name: C1_AHB3ENR + description: RCC AHB3 Clock Register + byte_offset: 308 + fieldset: C1_AHB3ENR + - name: C1_AHB1ENR + description: RCC AHB1 Clock Register + byte_offset: 312 + fieldset: C1_AHB1ENR + - name: C1_AHB2ENR + description: RCC AHB2 Clock Register + byte_offset: 316 + fieldset: C1_AHB2ENR + - name: C1_AHB4ENR + description: RCC AHB4 Clock Register + byte_offset: 320 + fieldset: C1_AHB4ENR + - name: C1_APB3ENR + description: RCC APB3 Clock Register + byte_offset: 324 + fieldset: C1_APB3ENR + - name: C1_APB1LENR + description: RCC APB1 Clock Register + byte_offset: 328 + fieldset: C1_APB1LENR + - name: C1_APB1HENR + description: RCC APB1 Clock Register + byte_offset: 332 + fieldset: C1_APB1HENR + - name: C1_APB2ENR + description: RCC APB2 Clock Register + byte_offset: 336 + fieldset: C1_APB2ENR + - name: C1_APB4ENR + description: RCC APB4 Clock Register + byte_offset: 340 + fieldset: C1_APB4ENR + - name: C1_AHB3LPENR + description: RCC AHB3 Sleep Clock Register + byte_offset: 348 + fieldset: C1_AHB3LPENR + - name: C1_AHB1LPENR + description: RCC AHB1 Sleep Clock Register + byte_offset: 352 + fieldset: C1_AHB1LPENR + - name: C1_AHB2LPENR + description: RCC AHB2 Sleep Clock Register + byte_offset: 356 + fieldset: C1_AHB2LPENR + - name: C1_AHB4LPENR + description: RCC AHB4 Sleep Clock Register + byte_offset: 360 + fieldset: C1_AHB4LPENR + - name: C1_APB3LPENR + description: RCC APB3 Sleep Clock Register + byte_offset: 364 + fieldset: C1_APB3LPENR + - name: C1_APB1LLPENR + description: RCC APB1 Low Sleep Clock Register + byte_offset: 368 + fieldset: C1_APB1LLPENR + - name: C1_APB1HLPENR + description: RCC APB1 High Sleep Clock Register + byte_offset: 372 + fieldset: C1_APB1HLPENR + - name: C1_APB2LPENR + description: RCC APB2 Sleep Clock Register + byte_offset: 376 + fieldset: C1_APB2LPENR + - name: C1_APB4LPENR + description: RCC APB4 Sleep Clock Register + byte_offset: 380 + fieldset: C1_APB4LPENR fieldset/AHB1ENR: description: RCC AHB1 Clock Register fields: - - name: DMA1EN - description: DMA1 Clock Enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: DMA2 Clock Enable - bit_offset: 1 - bit_size: 1 - - name: ADC12EN - description: ADC1/2 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - - name: ARTEN - description: ART Clock Enable - bit_offset: 14 - bit_size: 1 - - name: ETH1MACEN - description: Ethernet MAC bus interface Clock Enable - bit_offset: 15 - bit_size: 1 - - name: ETH1TXEN - description: Ethernet Transmission Clock Enable - bit_offset: 16 - bit_size: 1 - - name: ETH1RXEN - description: Ethernet Reception Clock Enable - bit_offset: 17 - bit_size: 1 - - name: USB_OTG_HSEN - description: USB_OTG_HS Peripheral Clocks Enable - bit_offset: 25 - bit_size: 1 - - name: USB_OTG_HS_ULPIEN - description: USB_OTG_HS ULPI clock enable - bit_offset: 26 - bit_size: 1 - - name: USB_OTG_FSEN - description: USB_OTG_FS Peripheral Clocks Enable - bit_offset: 27 - bit_size: 1 - - name: USB_OTG_FS_ULPIEN - description: USB_OTG_FS ULPI clock enable - bit_offset: 28 - bit_size: 1 + - name: DMA1EN + description: DMA1 Clock Enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 Clock Enable + bit_offset: 1 + bit_size: 1 + - name: ADC12EN + description: ADC1/2 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + - name: ARTEN + description: ART Clock Enable + bit_offset: 14 + bit_size: 1 + - name: ETH1MACEN + description: Ethernet MAC bus interface Clock Enable + bit_offset: 15 + bit_size: 1 + - name: ETH1TXEN + description: Ethernet Transmission Clock Enable + bit_offset: 16 + bit_size: 1 + - name: ETH1RXEN + description: Ethernet Reception Clock Enable + bit_offset: 17 + bit_size: 1 + - name: USB_OTG_HSEN + description: USB_OTG_HS Peripheral Clocks Enable + bit_offset: 25 + bit_size: 1 + - name: USB_OTG_HS_ULPIEN + description: USB_OTG_HS ULPI clock enable + bit_offset: 26 + bit_size: 1 + - name: USB_OTG_FSEN + description: USB_OTG_FS Peripheral Clocks Enable + bit_offset: 27 + bit_size: 1 + - name: USB_OTG_FS_ULPIEN + description: USB_OTG_FS ULPI clock enable + bit_offset: 28 + bit_size: 1 fieldset/AHB1LPENR: description: RCC AHB1 Sleep Clock Register fields: - - name: DMA1LPEN - description: DMA1 Clock Enable During CSleep Mode - bit_offset: 0 - bit_size: 1 - - name: DMA2LPEN - description: DMA2 Clock Enable During CSleep Mode - bit_offset: 1 - bit_size: 1 - - name: ADC12LPEN - description: ADC1/2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - name: ARTLPEN - description: ART Clock Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - - name: ETH1MACLPEN - description: Ethernet MAC bus interface Clock Enable During CSleep Mode - bit_offset: 15 - bit_size: 1 - - name: ETH1TXLPEN - description: Ethernet Transmission Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: ETH1RXLPEN - description: Ethernet Reception Clock Enable During CSleep Mode - bit_offset: 17 - bit_size: 1 - - name: USB_OTG_HSLPEN - description: USB_OTG_HS peripheral clock enable during CSleep mode - bit_offset: 25 - bit_size: 1 - - name: USB_OTG_HS_ULPILPEN - description: USB_PHY1 clock enable during CSleep mode - bit_offset: 26 - bit_size: 1 - - name: USB_OTG_FSLPEN - description: USB_OTG_FS peripheral clock enable during CSleep mode - bit_offset: 27 - bit_size: 1 - - name: USB_OTG_FS_ULPILPEN - description: USB_PHY2 clocks enable during CSleep mode - bit_offset: 28 - bit_size: 1 + - name: DMA1LPEN + description: DMA1 Clock Enable During CSleep Mode + bit_offset: 0 + bit_size: 1 + - name: DMA2LPEN + description: DMA2 Clock Enable During CSleep Mode + bit_offset: 1 + bit_size: 1 + - name: ADC12LPEN + description: ADC1/2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: ARTLPEN + description: ART Clock Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + - name: ETH1MACLPEN + description: Ethernet MAC bus interface Clock Enable During CSleep Mode + bit_offset: 15 + bit_size: 1 + - name: ETH1TXLPEN + description: Ethernet Transmission Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: ETH1RXLPEN + description: Ethernet Reception Clock Enable During CSleep Mode + bit_offset: 17 + bit_size: 1 + - name: USB_OTG_HSLPEN + description: USB_OTG_HS peripheral clock enable during CSleep mode + bit_offset: 25 + bit_size: 1 + - name: USB_OTG_HS_ULPILPEN + description: USB_PHY1 clock enable during CSleep mode + bit_offset: 26 + bit_size: 1 + - name: USB_OTG_FSLPEN + description: USB_OTG_FS peripheral clock enable during CSleep mode + bit_offset: 27 + bit_size: 1 + - name: USB_OTG_FS_ULPILPEN + description: USB_PHY2 clocks enable during CSleep mode + bit_offset: 28 + bit_size: 1 fieldset/AHB1RSTR: description: RCC AHB1 Peripheral Reset Register fields: - - name: DMA1RST - description: DMA1 block reset - bit_offset: 0 - bit_size: 1 - - name: DMA2RST - description: DMA2 block reset - bit_offset: 1 - bit_size: 1 - - name: ADC12RST - description: ADC1&2 block reset - bit_offset: 5 - bit_size: 1 - - name: ARTRST - description: ART block reset - bit_offset: 14 - bit_size: 1 - - name: ETH1MACRST - description: ETH1MAC block reset - bit_offset: 15 - bit_size: 1 - - name: USB_OTG_HSRST - description: USB_OTG_HS block reset - bit_offset: 25 - bit_size: 1 - - name: USB_OTG_FSRST - description: USB_OTG_FS block reset - bit_offset: 27 - bit_size: 1 + - name: DMA1RST + description: DMA1 block reset + bit_offset: 0 + bit_size: 1 + - name: DMA2RST + description: DMA2 block reset + bit_offset: 1 + bit_size: 1 + - name: ADC12RST + description: ADC1&2 block reset + bit_offset: 5 + bit_size: 1 + - name: ARTRST + description: ART block reset + bit_offset: 14 + bit_size: 1 + - name: ETH1MACRST + description: ETH1MAC block reset + bit_offset: 15 + bit_size: 1 + - name: USB_OTG_HSRST + description: USB_OTG_HS block reset + bit_offset: 25 + bit_size: 1 + - name: USB_OTG_FSRST + description: USB_OTG_FS block reset + bit_offset: 27 + bit_size: 1 fieldset/AHB2ENR: description: RCC AHB2 Clock Register fields: - - name: DCMIEN - description: DCMI peripheral clock - bit_offset: 0 - bit_size: 1 - - name: CRYPTEN - description: CRYPT peripheral clock enable - bit_offset: 4 - bit_size: 1 - - name: HASHEN - description: HASH peripheral clock enable - bit_offset: 5 - bit_size: 1 - - name: RNGEN - description: RNG peripheral clocks enable - bit_offset: 6 - bit_size: 1 - - name: SDMMC2EN - description: SDMMC2 and SDMMC2 delay clock enable - bit_offset: 9 - bit_size: 1 - - name: FMACEN - description: FMAC enable - bit_offset: 16 - bit_size: 1 - - name: CORDICEN - description: CORDIC enable - bit_offset: 17 - bit_size: 1 - - name: SRAM1EN - description: SRAM1 block enable - bit_offset: 29 - bit_size: 1 - - name: SRAM2EN - description: SRAM2 block enable - bit_offset: 30 - bit_size: 1 - - name: SRAM3EN - description: SRAM3 block enable - bit_offset: 31 - bit_size: 1 + - name: DCMIEN + description: DCMI peripheral clock + bit_offset: 0 + bit_size: 1 + - name: CRYPTEN + description: CRYPT peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: HASHEN + description: HASH peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: RNGEN + description: RNG peripheral clocks enable + bit_offset: 6 + bit_size: 1 + - name: SDMMC2EN + description: SDMMC2 and SDMMC2 delay clock enable + bit_offset: 9 + bit_size: 1 + - name: FMACEN + description: FMAC enable + bit_offset: 16 + bit_size: 1 + - name: CORDICEN + description: CORDIC enable + bit_offset: 17 + bit_size: 1 + - name: SRAM1EN + description: SRAM1 block enable + bit_offset: 29 + bit_size: 1 + - name: SRAM2EN + description: SRAM2 block enable + bit_offset: 30 + bit_size: 1 + - name: SRAM3EN + description: SRAM3 block enable + bit_offset: 31 + bit_size: 1 fieldset/AHB2LPENR: description: RCC AHB2 Sleep Clock Register fields: - - name: DCMILPEN - description: DCMI peripheral clock enable during csleep mode - bit_offset: 0 - bit_size: 1 - - name: CRYPTLPEN - description: CRYPT peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - name: HASHLPEN - description: HASH peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - name: RNGLPEN - description: RNG peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - - name: SDMMC2LPEN - description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - - name: FMACLPEN - description: FMAC enable during CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: CORDICLPEN - description: CORDIC enable during CSleep Mode - bit_offset: 17 - bit_size: 1 - - name: SRAM1LPEN - description: SRAM1 Clock Enable During CSleep Mode - bit_offset: 29 - bit_size: 1 - - name: SRAM2LPEN - description: SRAM2 Clock Enable During CSleep Mode - bit_offset: 30 - bit_size: 1 - - name: SRAM3LPEN - description: SRAM3 Clock Enable During CSleep Mode - bit_offset: 31 - bit_size: 1 + - name: DCMILPEN + description: DCMI peripheral clock enable during csleep mode + bit_offset: 0 + bit_size: 1 + - name: CRYPTLPEN + description: CRYPT peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: HASHLPEN + description: HASH peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: RNGLPEN + description: RNG peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + - name: SDMMC2LPEN + description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + - name: FMACLPEN + description: FMAC enable during CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: CORDICLPEN + description: CORDIC enable during CSleep Mode + bit_offset: 17 + bit_size: 1 + - name: SRAM1LPEN + description: SRAM1 Clock Enable During CSleep Mode + bit_offset: 29 + bit_size: 1 + - name: SRAM2LPEN + description: SRAM2 Clock Enable During CSleep Mode + bit_offset: 30 + bit_size: 1 + - name: SRAM3LPEN + description: SRAM3 Clock Enable During CSleep Mode + bit_offset: 31 + bit_size: 1 fieldset/AHB2RSTR: description: RCC AHB2 Peripheral Reset Register fields: - - name: DCMIRST - description: DCMI block reset - bit_offset: 0 - bit_size: 1 - - name: CRYPTRST - description: Cryptography block reset - bit_offset: 4 - bit_size: 1 - - name: HASHRST - description: Hash block reset - bit_offset: 5 - bit_size: 1 - - name: RNGRST - description: Random Number Generator block reset - bit_offset: 6 - bit_size: 1 - - name: SDMMC2RST - description: SDMMC2 and SDMMC2 Delay block reset - bit_offset: 9 - bit_size: 1 - - name: FMACRST - description: FMAC reset - bit_offset: 16 - bit_size: 1 - - name: CORDICRST - description: CORDIC reset - bit_offset: 17 - bit_size: 1 + - name: DCMIRST + description: DCMI block reset + bit_offset: 0 + bit_size: 1 + - name: CRYPTRST + description: Cryptography block reset + bit_offset: 4 + bit_size: 1 + - name: HASHRST + description: Hash block reset + bit_offset: 5 + bit_size: 1 + - name: RNGRST + description: Random Number Generator block reset + bit_offset: 6 + bit_size: 1 + - name: SDMMC2RST + description: SDMMC2 and SDMMC2 Delay block reset + bit_offset: 9 + bit_size: 1 + - name: FMACRST + description: FMAC reset + bit_offset: 16 + bit_size: 1 + - name: CORDICRST + description: CORDIC reset + bit_offset: 17 + bit_size: 1 fieldset/AHB3ENR: description: RCC AHB3 Clock Register fields: - - name: MDMAEN - description: MDMA Peripheral Clock Enable - bit_offset: 0 - bit_size: 1 - - name: DMA2DEN - description: DMA2D Peripheral Clock Enable - bit_offset: 4 - bit_size: 1 - - name: JPGDECEN - description: JPGDEC Peripheral Clock Enable - bit_offset: 5 - bit_size: 1 - - name: FMCEN - description: FMC Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - - name: QUADSPIEN - description: QUADSPI and QUADSPI Delay Clock Enable - bit_offset: 14 - bit_size: 1 - - name: SDMMC1EN - description: SDMMC1 and SDMMC1 Delay Clock Enable - bit_offset: 16 - bit_size: 1 - - name: OCTOSPI2EN - description: OCTOSPI2 and OCTOSPI2 delay block enable - bit_offset: 19 - bit_size: 1 - - name: IOMNGREN - description: OCTOSPI IO manager enable - bit_offset: 21 - bit_size: 1 - - name: OTFD1EN - description: OTFDEC1 enable - bit_offset: 22 - bit_size: 1 - - name: OTFD2EN - description: OTFDEC2 enable - bit_offset: 23 - bit_size: 1 - - name: DTCM1EN - description: D1 DTCM1 block enable - bit_offset: 28 - bit_size: 1 - - name: DTCM2EN - description: D1 DTCM2 block enable - bit_offset: 29 - bit_size: 1 - - name: ITCM1EN - description: D1 ITCM block enable - bit_offset: 30 - bit_size: 1 - - name: AXISRAMEN - description: AXISRAM block enable - bit_offset: 31 - bit_size: 1 + - name: MDMAEN + description: MDMA Peripheral Clock Enable + bit_offset: 0 + bit_size: 1 + - name: DMA2DEN + description: DMA2D Peripheral Clock Enable + bit_offset: 4 + bit_size: 1 + - name: JPGDECEN + description: JPGDEC Peripheral Clock Enable + bit_offset: 5 + bit_size: 1 + - name: FMCEN + description: FMC Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + - name: QUADSPIEN + description: QUADSPI and QUADSPI Delay Clock Enable + bit_offset: 14 + bit_size: 1 + - name: SDMMC1EN + description: SDMMC1 and SDMMC1 Delay Clock Enable + bit_offset: 16 + bit_size: 1 + - name: OCTOSPI2EN + description: OCTOSPI2 and OCTOSPI2 delay block enable + bit_offset: 19 + bit_size: 1 + - name: IOMNGREN + description: OCTOSPI IO manager enable + bit_offset: 21 + bit_size: 1 + - name: OTFD1EN + description: OTFDEC1 enable + bit_offset: 22 + bit_size: 1 + - name: OTFD2EN + description: OTFDEC2 enable + bit_offset: 23 + bit_size: 1 + - name: DTCM1EN + description: D1 DTCM1 block enable + bit_offset: 28 + bit_size: 1 + - name: DTCM2EN + description: D1 DTCM2 block enable + bit_offset: 29 + bit_size: 1 + - name: ITCM1EN + description: D1 ITCM block enable + bit_offset: 30 + bit_size: 1 + - name: AXISRAMEN + description: AXISRAM block enable + bit_offset: 31 + bit_size: 1 fieldset/AHB3LPENR: description: RCC AHB3 Sleep Clock Register fields: - - name: MDMALPEN - description: MDMA Clock Enable During CSleep Mode - bit_offset: 0 - bit_size: 1 - - name: DMA2DLPEN - description: DMA2D Clock Enable During CSleep Mode - bit_offset: 4 - bit_size: 1 - - name: JPGDECLPEN - description: JPGDEC Clock Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - name: FLASHLPEN - description: FLASH Clock Enable During CSleep Mode - bit_offset: 8 - bit_size: 1 - - name: FMCLPEN - description: FMC Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - - name: QSPILPEN - description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - - name: SDMMC1LPEN - description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: OCTOSPI2LPEN - description: OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode - bit_offset: 19 - bit_size: 1 - - name: IOMNGRLPEN - description: OCTOSPI IO manager enable during CSleep Mode - bit_offset: 21 - bit_size: 1 - - name: OTFD1LPEN - description: OTFDEC1 enable during CSleep Mode - bit_offset: 22 - bit_size: 1 - - name: OTFD2LPEN - description: OTFDEC2 enable during CSleep Mode - bit_offset: 23 - bit_size: 1 - - name: D1DTCM1LPEN - description: D1DTCM1 Block Clock Enable During CSleep mode - bit_offset: 28 - bit_size: 1 - - name: DTCM2LPEN - description: D1 DTCM2 Block Clock Enable During CSleep mode - bit_offset: 29 - bit_size: 1 - - name: ITCMLPEN - description: D1ITCM Block Clock Enable During CSleep mode - bit_offset: 30 - bit_size: 1 - - name: AXISRAMLPEN - description: AXISRAM Block Clock Enable During CSleep mode - bit_offset: 31 - bit_size: 1 + - name: MDMALPEN + description: MDMA Clock Enable During CSleep Mode + bit_offset: 0 + bit_size: 1 + - name: DMA2DLPEN + description: DMA2D Clock Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + - name: JPGDECLPEN + description: JPGDEC Clock Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: FLASHLPEN + description: FLASH Clock Enable During CSleep Mode + bit_offset: 8 + bit_size: 1 + - name: FMCLPEN + description: FMC Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + - name: QSPILPEN + description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + - name: SDMMC1LPEN + description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: OCTOSPI2LPEN + description: OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode + bit_offset: 19 + bit_size: 1 + - name: IOMNGRLPEN + description: OCTOSPI IO manager enable during CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: OTFD1LPEN + description: OTFDEC1 enable during CSleep Mode + bit_offset: 22 + bit_size: 1 + - name: OTFD2LPEN + description: OTFDEC2 enable during CSleep Mode + bit_offset: 23 + bit_size: 1 + - name: D1DTCM1LPEN + description: D1DTCM1 Block Clock Enable During CSleep mode + bit_offset: 28 + bit_size: 1 + - name: DTCM2LPEN + description: D1 DTCM2 Block Clock Enable During CSleep mode + bit_offset: 29 + bit_size: 1 + - name: ITCMLPEN + description: D1ITCM Block Clock Enable During CSleep mode + bit_offset: 30 + bit_size: 1 + - name: AXISRAMLPEN + description: AXISRAM Block Clock Enable During CSleep mode + bit_offset: 31 + bit_size: 1 fieldset/AHB3RSTR: description: RCC AHB3 Reset Register fields: - - name: MDMARST - description: MDMA block reset - bit_offset: 0 - bit_size: 1 - - name: DMA2DRST - description: DMA2D block reset - bit_offset: 4 - bit_size: 1 - - name: JPGDECRST - description: JPGDEC block reset - bit_offset: 5 - bit_size: 1 - - name: FMCRST - description: FMC block reset - bit_offset: 12 - bit_size: 1 - - name: QSPIRST - description: QUADSPI and QUADSPI delay block reset - bit_offset: 14 - bit_size: 1 - - name: SDMMC1RST - description: SDMMC1 and SDMMC1 delay block reset - bit_offset: 16 - bit_size: 1 - - name: OCTOSPI2RST - description: OCTOSPI2 and OCTOSPI2 delay block reset - bit_offset: 19 - bit_size: 1 - - name: IOMNGRRST - description: OCTOSPI IO manager reset - bit_offset: 21 - bit_size: 1 - - name: OTFD1RST - description: OTFDEC1 reset - bit_offset: 22 - bit_size: 1 - - name: OTFD2RST - description: OTFDEC2 reset - bit_offset: 23 - bit_size: 1 - - name: CPURST - description: CPU reset - bit_offset: 31 - bit_size: 1 + - name: MDMARST + description: MDMA block reset + bit_offset: 0 + bit_size: 1 + - name: DMA2DRST + description: DMA2D block reset + bit_offset: 4 + bit_size: 1 + - name: JPGDECRST + description: JPGDEC block reset + bit_offset: 5 + bit_size: 1 + - name: FMCRST + description: FMC block reset + bit_offset: 12 + bit_size: 1 + - name: QSPIRST + description: QUADSPI and QUADSPI delay block reset + bit_offset: 14 + bit_size: 1 + - name: SDMMC1RST + description: SDMMC1 and SDMMC1 delay block reset + bit_offset: 16 + bit_size: 1 + - name: OCTOSPI2RST + description: OCTOSPI2 and OCTOSPI2 delay block reset + bit_offset: 19 + bit_size: 1 + - name: IOMNGRRST + description: OCTOSPI IO manager reset + bit_offset: 21 + bit_size: 1 + - name: OTFD1RST + description: OTFDEC1 reset + bit_offset: 22 + bit_size: 1 + - name: OTFD2RST + description: OTFDEC2 reset + bit_offset: 23 + bit_size: 1 + - name: CPURST + description: CPU reset + bit_offset: 31 + bit_size: 1 fieldset/AHB4ENR: description: RCC AHB4 Clock Register fields: - - name: GPIOAEN - description: 0GPIO peripheral clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: 0GPIO peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: 0GPIO peripheral clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: 0GPIO peripheral clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: 0GPIO peripheral clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIOFEN - description: 0GPIO peripheral clock enable - bit_offset: 5 - bit_size: 1 - - name: GPIOGEN - description: 0GPIO peripheral clock enable - bit_offset: 6 - bit_size: 1 - - name: GPIOHEN - description: 0GPIO peripheral clock enable - bit_offset: 7 - bit_size: 1 - - name: GPIOIEN - description: 0GPIO peripheral clock enable - bit_offset: 8 - bit_size: 1 - - name: GPIOJEN - description: 0GPIO peripheral clock enable - bit_offset: 9 - bit_size: 1 - - name: GPIOKEN - description: 0GPIO peripheral clock enable - bit_offset: 10 - bit_size: 1 - - name: CRCEN - description: CRC peripheral clock enable - bit_offset: 19 - bit_size: 1 - - name: BDMAEN - description: BDMA and DMAMUX2 Clock Enable - bit_offset: 21 - bit_size: 1 - - name: ADC3EN - description: ADC3 Peripheral Clocks Enable - bit_offset: 24 - bit_size: 1 - - name: HSEMEN - description: HSEM peripheral clock enable - bit_offset: 25 - bit_size: 1 - - name: BKPSRAMEN - description: Backup RAM Clock Enable - bit_offset: 28 - bit_size: 1 + - name: GPIOAEN + description: 0GPIO peripheral clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: 0GPIO peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: 0GPIO peripheral clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: 0GPIO peripheral clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: 0GPIO peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: 0GPIO peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: 0GPIO peripheral clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: 0GPIO peripheral clock enable + bit_offset: 7 + bit_size: 1 + - name: GPIOIEN + description: 0GPIO peripheral clock enable + bit_offset: 8 + bit_size: 1 + - name: GPIOJEN + description: 0GPIO peripheral clock enable + bit_offset: 9 + bit_size: 1 + - name: GPIOKEN + description: 0GPIO peripheral clock enable + bit_offset: 10 + bit_size: 1 + - name: CRCEN + description: CRC peripheral clock enable + bit_offset: 19 + bit_size: 1 + - name: BDMAEN + description: BDMA and DMAMUX2 Clock Enable + bit_offset: 21 + bit_size: 1 + - name: ADC3EN + description: ADC3 Peripheral Clocks Enable + bit_offset: 24 + bit_size: 1 + - name: HSEMEN + description: HSEM peripheral clock enable + bit_offset: 25 + bit_size: 1 + - name: BKPSRAMEN + description: Backup RAM Clock Enable + bit_offset: 28 + bit_size: 1 fieldset/AHB4LPENR: description: RCC AHB4 Sleep Clock Register fields: - - name: GPIOALPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - - name: GPIOBLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: GPIOCLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 2 - bit_size: 1 - - name: GPIODLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - - name: GPIOELPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - name: GPIOFLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - name: GPIOGLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - - name: GPIOHLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 7 - bit_size: 1 - - name: GPIOILPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 8 - bit_size: 1 - - name: GPIOJLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 9 - bit_size: 1 - - name: GPIOKLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 10 - bit_size: 1 - - name: CRCLPEN - description: CRC peripheral clock enable during CSleep mode - bit_offset: 19 - bit_size: 1 - - name: BDMALPEN - description: BDMA Clock Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - - name: ADC3LPEN - description: ADC3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 24 - bit_size: 1 - - name: BKPSRAMLPEN - description: Backup RAM Clock Enable During CSleep Mode - bit_offset: 28 - bit_size: 1 - - name: SRAM4LPEN - description: SRAM4 Clock Enable During CSleep Mode - bit_offset: 29 - bit_size: 1 + - name: GPIOALPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 2 + bit_size: 1 + - name: GPIODLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + - name: GPIOELPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: GPIOFLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: GPIOGLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + - name: GPIOHLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 7 + bit_size: 1 + - name: GPIOILPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 8 + bit_size: 1 + - name: GPIOJLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 9 + bit_size: 1 + - name: GPIOKLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 10 + bit_size: 1 + - name: CRCLPEN + description: CRC peripheral clock enable during CSleep mode + bit_offset: 19 + bit_size: 1 + - name: BDMALPEN + description: BDMA Clock Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: ADC3LPEN + description: ADC3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 24 + bit_size: 1 + - name: BKPSRAMLPEN + description: Backup RAM Clock Enable During CSleep Mode + bit_offset: 28 + bit_size: 1 + - name: SRAM4LPEN + description: SRAM4 Clock Enable During CSleep Mode + bit_offset: 29 + bit_size: 1 fieldset/AHB4RSTR: description: RCC AHB4 Peripheral Reset Register fields: - - name: GPIOARST - description: GPIO block reset - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: GPIO block reset - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: GPIO block reset - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: GPIO block reset - bit_offset: 3 - bit_size: 1 - - name: GPIOERST - description: GPIO block reset - bit_offset: 4 - bit_size: 1 - - name: GPIOFRST - description: GPIO block reset - bit_offset: 5 - bit_size: 1 - - name: GPIOGRST - description: GPIO block reset - bit_offset: 6 - bit_size: 1 - - name: GPIOHRST - description: GPIO block reset - bit_offset: 7 - bit_size: 1 - - name: GPIOIRST - description: GPIO block reset - bit_offset: 8 - bit_size: 1 - - name: GPIOJRST - description: GPIO block reset - bit_offset: 9 - bit_size: 1 - - name: GPIOKRST - description: GPIO block reset - bit_offset: 10 - bit_size: 1 - - name: CRCRST - description: CRC block reset - bit_offset: 19 - bit_size: 1 - - name: BDMARST - description: BDMA block reset - bit_offset: 21 - bit_size: 1 - - name: ADC3RST - description: ADC3 block reset - bit_offset: 24 - bit_size: 1 - - name: HSEMRST - description: HSEM block reset - bit_offset: 25 - bit_size: 1 + - name: GPIOARST + description: GPIO block reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: GPIO block reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: GPIO block reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: GPIO block reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: GPIO block reset + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: GPIO block reset + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: GPIO block reset + bit_offset: 6 + bit_size: 1 + - name: GPIOHRST + description: GPIO block reset + bit_offset: 7 + bit_size: 1 + - name: GPIOIRST + description: GPIO block reset + bit_offset: 8 + bit_size: 1 + - name: GPIOJRST + description: GPIO block reset + bit_offset: 9 + bit_size: 1 + - name: GPIOKRST + description: GPIO block reset + bit_offset: 10 + bit_size: 1 + - name: CRCRST + description: CRC block reset + bit_offset: 19 + bit_size: 1 + - name: BDMARST + description: BDMA block reset + bit_offset: 21 + bit_size: 1 + - name: ADC3RST + description: ADC3 block reset + bit_offset: 24 + bit_size: 1 + - name: HSEMRST + description: HSEM block reset + bit_offset: 25 + bit_size: 1 fieldset/APB1HENR: description: RCC APB1 Clock Register fields: - - name: CRSEN - description: Clock Recovery System peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: SWPEN - description: SWPMI Peripheral Clocks Enable - bit_offset: 2 - bit_size: 1 - - name: OPAMPEN - description: OPAMP peripheral clock enable - bit_offset: 4 - bit_size: 1 - - name: MDIOSEN - description: MDIOS peripheral clock enable - bit_offset: 5 - bit_size: 1 - - name: FDCANEN - description: FDCAN Peripheral Clocks Enable - bit_offset: 8 - bit_size: 1 - - name: TIM23EN - description: TIM23 block enable - bit_offset: 24 - bit_size: 1 - - name: TIM24EN - description: TIM24 block enable - bit_offset: 25 - bit_size: 1 + - name: CRSEN + description: Clock Recovery System peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: SWPEN + description: SWPMI Peripheral Clocks Enable + bit_offset: 2 + bit_size: 1 + - name: OPAMPEN + description: OPAMP peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: MDIOSEN + description: MDIOS peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: FDCANEN + description: FDCAN Peripheral Clocks Enable + bit_offset: 8 + bit_size: 1 + - name: TIM23EN + description: TIM23 block enable + bit_offset: 24 + bit_size: 1 + - name: TIM24EN + description: TIM24 block enable + bit_offset: 25 + bit_size: 1 fieldset/APB1HLPENR: description: RCC APB1 High Sleep Clock Register fields: - - name: CRSLPEN - description: Clock Recovery System peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: SWPLPEN - description: SWPMI Peripheral Clocks Enable During CSleep Mode - bit_offset: 2 - bit_size: 1 - - name: OPAMPLPEN - description: OPAMP peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - name: MDIOSLPEN - description: MDIOS peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - name: FDCANLPEN - description: FDCAN Peripheral Clocks Enable During CSleep Mode - bit_offset: 8 - bit_size: 1 - - name: TIM23LPEN - description: TIM23 block enable during CSleep Mode - bit_offset: 24 - bit_size: 1 - - name: TIM24LPEN - description: TIM24 block enable during CSleep Mode - bit_offset: 25 - bit_size: 1 + - name: CRSLPEN + description: Clock Recovery System peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: SWPLPEN + description: SWPMI Peripheral Clocks Enable During CSleep Mode + bit_offset: 2 + bit_size: 1 + - name: OPAMPLPEN + description: OPAMP peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: MDIOSLPEN + description: MDIOS peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: FDCANLPEN + description: FDCAN Peripheral Clocks Enable During CSleep Mode + bit_offset: 8 + bit_size: 1 + - name: TIM23LPEN + description: TIM23 block enable during CSleep Mode + bit_offset: 24 + bit_size: 1 + - name: TIM24LPEN + description: TIM24 block enable during CSleep Mode + bit_offset: 25 + bit_size: 1 fieldset/APB1HRSTR: description: RCC APB1 Peripheral Reset Register fields: - - name: CRSRST - description: Clock Recovery System reset - bit_offset: 1 - bit_size: 1 - - name: SWPRST - description: SWPMI block reset - bit_offset: 2 - bit_size: 1 - - name: OPAMPRST - description: OPAMP block reset - bit_offset: 4 - bit_size: 1 - - name: MDIOSRST - description: MDIOS block reset - bit_offset: 5 - bit_size: 1 - - name: FDCANRST - description: FDCAN block reset - bit_offset: 8 - bit_size: 1 - - name: TIM23RST - description: TIM23 block reset - bit_offset: 24 - bit_size: 1 - - name: TIM24RST - description: TIM24 block reset - bit_offset: 25 - bit_size: 1 + - name: CRSRST + description: Clock Recovery System reset + bit_offset: 1 + bit_size: 1 + - name: SWPRST + description: SWPMI block reset + bit_offset: 2 + bit_size: 1 + - name: OPAMPRST + description: OPAMP block reset + bit_offset: 4 + bit_size: 1 + - name: MDIOSRST + description: MDIOS block reset + bit_offset: 5 + bit_size: 1 + - name: FDCANRST + description: FDCAN block reset + bit_offset: 8 + bit_size: 1 + - name: TIM23RST + description: TIM23 block reset + bit_offset: 24 + bit_size: 1 + - name: TIM24RST + description: TIM24 block reset + bit_offset: 25 + bit_size: 1 fieldset/APB1LENR: description: RCC APB1 Clock Register fields: - - name: TIM2EN - description: TIM peripheral clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: TIM peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: TIM peripheral clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: TIM peripheral clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: TIM peripheral clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: TIM peripheral clock enable - bit_offset: 5 - bit_size: 1 - - name: TIM12EN - description: TIM peripheral clock enable - bit_offset: 6 - bit_size: 1 - - name: TIM13EN - description: TIM peripheral clock enable - bit_offset: 7 - bit_size: 1 - - name: TIM14EN - description: TIM peripheral clock enable - bit_offset: 8 - bit_size: 1 - - name: LPTIM1EN - description: LPTIM1 Peripheral Clocks Enable - bit_offset: 9 - bit_size: 1 - - name: WWDG2EN - description: WWDG2 peripheral clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI2 Peripheral Clocks Enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI3 Peripheral Clocks Enable - bit_offset: 15 - bit_size: 1 - - name: SPDIFRXEN - description: SPDIFRX Peripheral Clocks Enable - bit_offset: 16 - bit_size: 1 - - name: USART2EN - description: USART2 Peripheral Clocks Enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART3 Peripheral Clocks Enable - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: UART4 Peripheral Clocks Enable - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: UART5 Peripheral Clocks Enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C1 Peripheral Clocks Enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C2 Peripheral Clocks Enable - bit_offset: 22 - bit_size: 1 - - name: I2C3EN - description: I2C3 Peripheral Clocks Enable - bit_offset: 23 - bit_size: 1 - - name: I2C5EN - description: "I2C5 Peripheral Clocks\r Enable" - bit_offset: 25 - bit_size: 1 - - name: CECEN - description: HDMI-CEC peripheral clock enable - bit_offset: 27 - bit_size: 1 - - name: DAC12EN - description: DAC1&2 peripheral clock enable - bit_offset: 29 - bit_size: 1 - - name: UART7EN - description: UART7 Peripheral Clocks Enable - bit_offset: 30 - bit_size: 1 - - name: UART8EN - description: UART8 Peripheral Clocks Enable - bit_offset: 31 - bit_size: 1 + - name: TIM2EN + description: TIM peripheral clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM peripheral clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: TIM peripheral clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: TIM peripheral clock enable + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: TIM peripheral clock enable + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: TIM peripheral clock enable + bit_offset: 8 + bit_size: 1 + - name: LPTIM1EN + description: LPTIM1 Peripheral Clocks Enable + bit_offset: 9 + bit_size: 1 + - name: WWDG2EN + description: WWDG2 peripheral clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 Peripheral Clocks Enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 Peripheral Clocks Enable + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXEN + description: SPDIFRX Peripheral Clocks Enable + bit_offset: 16 + bit_size: 1 + - name: USART2EN + description: USART2 Peripheral Clocks Enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 Peripheral Clocks Enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 Peripheral Clocks Enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 Peripheral Clocks Enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 Peripheral Clocks Enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 Peripheral Clocks Enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: I2C3 Peripheral Clocks Enable + bit_offset: 23 + bit_size: 1 + - name: I2C5EN + description: "I2C5 Peripheral Clocks\r Enable" + bit_offset: 25 + bit_size: 1 + - name: CECEN + description: HDMI-CEC peripheral clock enable + bit_offset: 27 + bit_size: 1 + - name: DAC12EN + description: DAC1&2 peripheral clock enable + bit_offset: 29 + bit_size: 1 + - name: UART7EN + description: UART7 Peripheral Clocks Enable + bit_offset: 30 + bit_size: 1 + - name: UART8EN + description: UART8 Peripheral Clocks Enable + bit_offset: 31 + bit_size: 1 fieldset/APB1LLPENR: description: RCC APB1 Low Sleep Clock Register fields: - - name: TIM2LPEN - description: TIM2 peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM3LPEN - description: TIM3 peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: TIM4LPEN - description: TIM4 peripheral clock enable during CSleep mode - bit_offset: 2 - bit_size: 1 - - name: TIM5LPEN - description: TIM5 peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - - name: TIM6LPEN - description: TIM6 peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - name: TIM7LPEN - description: TIM7 peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - name: TIM12LPEN - description: TIM12 peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - - name: TIM13LPEN - description: TIM13 peripheral clock enable during CSleep mode - bit_offset: 7 - bit_size: 1 - - name: TIM14LPEN - description: TIM14 peripheral clock enable during CSleep mode - bit_offset: 8 - bit_size: 1 - - name: LPTIM1LPEN - description: LPTIM1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - - name: WWDG2LPEN - description: WWDG2 peripheral Clocks Enable During CSleep Mode - bit_offset: 11 - bit_size: 1 - - name: SPI2LPEN - description: SPI2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - - name: SPI3LPEN - description: SPI3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 15 - bit_size: 1 - - name: SPDIFRXLPEN - description: SPDIFRX Peripheral Clocks Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: USART2LPEN - description: USART2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 17 - bit_size: 1 - - name: USART3LPEN - description: USART3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 18 - bit_size: 1 - - name: UART4LPEN - description: UART4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 19 - bit_size: 1 - - name: UART5LPEN - description: UART5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 20 - bit_size: 1 - - name: I2C1LPEN - description: I2C1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - - name: I2C2LPEN - description: I2C2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 22 - bit_size: 1 - - name: I2C3LPEN - description: I2C3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 23 - bit_size: 1 - - name: I2C5LPEN - description: I2C5 block enable during CSleep Mode - bit_offset: 25 - bit_size: 1 - - name: CECLPEN - description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode - bit_offset: 27 - bit_size: 1 - - name: DAC12LPEN - description: DAC1/2 peripheral clock enable during CSleep mode - bit_offset: 29 - bit_size: 1 - - name: UART7LPEN - description: UART7 Peripheral Clocks Enable During CSleep Mode - bit_offset: 30 - bit_size: 1 - - name: UART8LPEN - description: UART8 Peripheral Clocks Enable During CSleep Mode - bit_offset: 31 - bit_size: 1 + - name: TIM2LPEN + description: TIM2 peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM3LPEN + description: TIM3 peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: TIM4LPEN + description: TIM4 peripheral clock enable during CSleep mode + bit_offset: 2 + bit_size: 1 + - name: TIM5LPEN + description: TIM5 peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + - name: TIM6LPEN + description: TIM6 peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: TIM7LPEN + description: TIM7 peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: TIM12LPEN + description: TIM12 peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + - name: TIM13LPEN + description: TIM13 peripheral clock enable during CSleep mode + bit_offset: 7 + bit_size: 1 + - name: TIM14LPEN + description: TIM14 peripheral clock enable during CSleep mode + bit_offset: 8 + bit_size: 1 + - name: LPTIM1LPEN + description: LPTIM1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + - name: WWDG2LPEN + description: WWDG2 peripheral Clocks Enable During CSleep Mode + bit_offset: 11 + bit_size: 1 + - name: SPI2LPEN + description: SPI2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + - name: SPI3LPEN + description: SPI3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXLPEN + description: SPDIFRX Peripheral Clocks Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: USART2LPEN + description: USART2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 17 + bit_size: 1 + - name: USART3LPEN + description: USART3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 18 + bit_size: 1 + - name: UART4LPEN + description: UART4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 19 + bit_size: 1 + - name: UART5LPEN + description: UART5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 20 + bit_size: 1 + - name: I2C1LPEN + description: I2C1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: I2C2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 22 + bit_size: 1 + - name: I2C3LPEN + description: I2C3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 23 + bit_size: 1 + - name: I2C5LPEN + description: I2C5 block enable during CSleep Mode + bit_offset: 25 + bit_size: 1 + - name: CECLPEN + description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode + bit_offset: 27 + bit_size: 1 + - name: DAC12LPEN + description: DAC1/2 peripheral clock enable during CSleep mode + bit_offset: 29 + bit_size: 1 + - name: UART7LPEN + description: UART7 Peripheral Clocks Enable During CSleep Mode + bit_offset: 30 + bit_size: 1 + - name: UART8LPEN + description: UART8 Peripheral Clocks Enable During CSleep Mode + bit_offset: 31 + bit_size: 1 fieldset/APB1LRSTR: description: RCC APB1 Peripheral Reset Register fields: - - name: TIM2RST - description: TIM block reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: TIM block reset - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: TIM block reset - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: TIM block reset - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: TIM block reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: TIM block reset - bit_offset: 5 - bit_size: 1 - - name: TIM12RST - description: TIM block reset - bit_offset: 6 - bit_size: 1 - - name: TIM13RST - description: TIM block reset - bit_offset: 7 - bit_size: 1 - - name: TIM14RST - description: TIM block reset - bit_offset: 8 - bit_size: 1 - - name: LPTIM1RST - description: TIM block reset - bit_offset: 9 - bit_size: 1 - - name: SPI2RST - description: SPI2 block reset - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: SPI3 block reset - bit_offset: 15 - bit_size: 1 - - name: SPDIFRXRST - description: SPDIFRX block reset - bit_offset: 16 - bit_size: 1 - - name: USART2RST - description: USART2 block reset - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: USART3 block reset - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: UART4 block reset - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: UART5 block reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C1 block reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C2 block reset - bit_offset: 22 - bit_size: 1 - - name: I2C3RST - description: I2C3 block reset - bit_offset: 23 - bit_size: 1 - - name: I2C5RST - description: I2C5 block reset - bit_offset: 25 - bit_size: 1 - - name: CECRST - description: HDMI-CEC block reset - bit_offset: 27 - bit_size: 1 - - name: DAC12RST - description: DAC1 and 2 Blocks Reset - bit_offset: 29 - bit_size: 1 - - name: UART7RST - description: UART7 block reset - bit_offset: 30 - bit_size: 1 - - name: UART8RST - description: UART8 block reset - bit_offset: 31 - bit_size: 1 + - name: TIM2RST + description: TIM block reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: TIM block reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: TIM block reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: TIM block reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: TIM block reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM block reset + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: TIM block reset + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: TIM block reset + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: TIM block reset + bit_offset: 8 + bit_size: 1 + - name: LPTIM1RST + description: TIM block reset + bit_offset: 9 + bit_size: 1 + - name: SPI2RST + description: SPI2 block reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 block reset + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXRST + description: SPDIFRX block reset + bit_offset: 16 + bit_size: 1 + - name: USART2RST + description: USART2 block reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 block reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: UART4 block reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: UART5 block reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 block reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 block reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 block reset + bit_offset: 23 + bit_size: 1 + - name: I2C5RST + description: I2C5 block reset + bit_offset: 25 + bit_size: 1 + - name: CECRST + description: HDMI-CEC block reset + bit_offset: 27 + bit_size: 1 + - name: DAC12RST + description: DAC1 and 2 Blocks Reset + bit_offset: 29 + bit_size: 1 + - name: UART7RST + description: UART7 block reset + bit_offset: 30 + bit_size: 1 + - name: UART8RST + description: UART8 block reset + bit_offset: 31 + bit_size: 1 fieldset/APB2ENR: description: RCC APB2 Clock Register fields: - - name: TIM1EN - description: TIM1 peripheral clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM8EN - description: TIM8 peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: USART1EN - description: USART1 Peripheral Clocks Enable - bit_offset: 4 - bit_size: 1 - - name: USART6EN - description: USART6 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - - name: UART9EN - description: "UART9 Peripheral Clocks\r Enable" - bit_offset: 6 - bit_size: 1 - - name: USART10EN - description: "USART10 Peripheral Clocks\r Enable" - bit_offset: 7 - bit_size: 1 - - name: SPI1EN - description: SPI1 Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - - name: SPI4EN - description: SPI4 Peripheral Clocks Enable - bit_offset: 13 - bit_size: 1 - - name: TIM15EN - description: TIM15 peripheral clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: TIM16 peripheral clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: TIM17 peripheral clock enable - bit_offset: 18 - bit_size: 1 - - name: SPI5EN - description: SPI5 Peripheral Clocks Enable - bit_offset: 20 - bit_size: 1 - - name: SAI1EN - description: SAI1 Peripheral Clocks Enable - bit_offset: 22 - bit_size: 1 - - name: SAI2EN - description: SAI2 Peripheral Clocks Enable - bit_offset: 23 - bit_size: 1 - - name: SAI3EN - description: SAI3 Peripheral Clocks Enable - bit_offset: 24 - bit_size: 1 - - name: DFSDM1EN - description: DFSDM1 Peripheral Clocks Enable - bit_offset: 28 - bit_size: 1 - - name: HRTIMEN - description: HRTIM peripheral clock enable - bit_offset: 29 - bit_size: 1 + - name: TIM1EN + description: TIM1 peripheral clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM8EN + description: TIM8 peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: USART1EN + description: USART1 Peripheral Clocks Enable + bit_offset: 4 + bit_size: 1 + - name: USART6EN + description: USART6 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + - name: UART9EN + description: "UART9 Peripheral Clocks\r Enable" + bit_offset: 6 + bit_size: 1 + - name: USART10EN + description: "USART10 Peripheral Clocks\r Enable" + bit_offset: 7 + bit_size: 1 + - name: SPI1EN + description: SPI1 Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + - name: SPI4EN + description: SPI4 Peripheral Clocks Enable + bit_offset: 13 + bit_size: 1 + - name: TIM15EN + description: TIM15 peripheral clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 peripheral clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 peripheral clock enable + bit_offset: 18 + bit_size: 1 + - name: SPI5EN + description: SPI5 Peripheral Clocks Enable + bit_offset: 20 + bit_size: 1 + - name: SAI1EN + description: SAI1 Peripheral Clocks Enable + bit_offset: 22 + bit_size: 1 + - name: SAI2EN + description: SAI2 Peripheral Clocks Enable + bit_offset: 23 + bit_size: 1 + - name: SAI3EN + description: SAI3 Peripheral Clocks Enable + bit_offset: 24 + bit_size: 1 + - name: DFSDM1EN + description: DFSDM1 Peripheral Clocks Enable + bit_offset: 28 + bit_size: 1 + - name: HRTIMEN + description: HRTIM peripheral clock enable + bit_offset: 29 + bit_size: 1 fieldset/APB2LPENR: description: RCC APB2 Sleep Clock Register fields: - - name: TIM1LPEN - description: TIM1 peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM8LPEN - description: TIM8 peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: USART1LPEN - description: USART1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 4 - bit_size: 1 - - name: USART6LPEN - description: USART6 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - name: SPI1LPEN - description: SPI1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - - name: SPI4LPEN - description: SPI4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 13 - bit_size: 1 - - name: TIM15LPEN - description: TIM15 peripheral clock enable during CSleep mode - bit_offset: 16 - bit_size: 1 - - name: TIM16LPEN - description: TIM16 peripheral clock enable during CSleep mode - bit_offset: 17 - bit_size: 1 - - name: TIM17LPEN - description: TIM17 peripheral clock enable during CSleep mode - bit_offset: 18 - bit_size: 1 - - name: SPI5LPEN - description: SPI5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 20 - bit_size: 1 - - name: SAI1LPEN - description: SAI1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 22 - bit_size: 1 - - name: SAI2LPEN - description: SAI2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 23 - bit_size: 1 - - name: SAI3LPEN - description: SAI3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 24 - bit_size: 1 - - name: DFSDM1LPEN - description: DFSDM1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 28 - bit_size: 1 - - name: HRTIMLPEN - description: HRTIM peripheral clock enable during CSleep mode - bit_offset: 29 - bit_size: 1 + - name: TIM1LPEN + description: TIM1 peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM8LPEN + description: TIM8 peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: USART1LPEN + description: USART1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + - name: USART6LPEN + description: USART6 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: SPI1LPEN + description: SPI1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + - name: SPI4LPEN + description: SPI4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 13 + bit_size: 1 + - name: TIM15LPEN + description: TIM15 peripheral clock enable during CSleep mode + bit_offset: 16 + bit_size: 1 + - name: TIM16LPEN + description: TIM16 peripheral clock enable during CSleep mode + bit_offset: 17 + bit_size: 1 + - name: TIM17LPEN + description: TIM17 peripheral clock enable during CSleep mode + bit_offset: 18 + bit_size: 1 + - name: SPI5LPEN + description: SPI5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 20 + bit_size: 1 + - name: SAI1LPEN + description: SAI1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 22 + bit_size: 1 + - name: SAI2LPEN + description: SAI2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 23 + bit_size: 1 + - name: SAI3LPEN + description: SAI3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 24 + bit_size: 1 + - name: DFSDM1LPEN + description: DFSDM1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 28 + bit_size: 1 + - name: HRTIMLPEN + description: HRTIM peripheral clock enable during CSleep mode + bit_offset: 29 + bit_size: 1 fieldset/APB2RSTR: description: RCC APB2 Peripheral Reset Register fields: - - name: TIM1RST - description: TIM1 block reset - bit_offset: 0 - bit_size: 1 - - name: TIM8RST - description: TIM8 block reset - bit_offset: 1 - bit_size: 1 - - name: USART1RST - description: USART1 block reset - bit_offset: 4 - bit_size: 1 - - name: USART6RST - description: USART6 block reset - bit_offset: 5 - bit_size: 1 - - name: UART9RST - description: UART9 block reset - bit_offset: 6 - bit_size: 1 - - name: USART10RST - description: USART10 block reset - bit_offset: 7 - bit_size: 1 - - name: SPI1RST - description: SPI1 block reset - bit_offset: 12 - bit_size: 1 - - name: SPI4RST - description: SPI4 block reset - bit_offset: 13 - bit_size: 1 - - name: TIM15RST - description: TIM15 block reset - bit_offset: 16 - bit_size: 1 - - name: TIM16RST - description: TIM16 block reset - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: TIM17 block reset - bit_offset: 18 - bit_size: 1 - - name: SPI5RST - description: SPI5 block reset - bit_offset: 20 - bit_size: 1 - - name: SAI1RST - description: SAI1 block reset - bit_offset: 22 - bit_size: 1 - - name: SAI2RST - description: SAI2 block reset - bit_offset: 23 - bit_size: 1 - - name: SAI3RST - description: SAI3 block reset - bit_offset: 24 - bit_size: 1 - - name: DFSDM1RST - description: DFSDM1 block reset - bit_offset: 28 - bit_size: 1 - - name: HRTIMRST - description: HRTIM block reset - bit_offset: 29 - bit_size: 1 + - name: TIM1RST + description: TIM1 block reset + bit_offset: 0 + bit_size: 1 + - name: TIM8RST + description: TIM8 block reset + bit_offset: 1 + bit_size: 1 + - name: USART1RST + description: USART1 block reset + bit_offset: 4 + bit_size: 1 + - name: USART6RST + description: USART6 block reset + bit_offset: 5 + bit_size: 1 + - name: UART9RST + description: UART9 block reset + bit_offset: 6 + bit_size: 1 + - name: USART10RST + description: USART10 block reset + bit_offset: 7 + bit_size: 1 + - name: SPI1RST + description: SPI1 block reset + bit_offset: 12 + bit_size: 1 + - name: SPI4RST + description: SPI4 block reset + bit_offset: 13 + bit_size: 1 + - name: TIM15RST + description: TIM15 block reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 block reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 block reset + bit_offset: 18 + bit_size: 1 + - name: SPI5RST + description: SPI5 block reset + bit_offset: 20 + bit_size: 1 + - name: SAI1RST + description: SAI1 block reset + bit_offset: 22 + bit_size: 1 + - name: SAI2RST + description: SAI2 block reset + bit_offset: 23 + bit_size: 1 + - name: SAI3RST + description: SAI3 block reset + bit_offset: 24 + bit_size: 1 + - name: DFSDM1RST + description: DFSDM1 block reset + bit_offset: 28 + bit_size: 1 + - name: HRTIMRST + description: HRTIM block reset + bit_offset: 29 + bit_size: 1 fieldset/APB3ENR: description: RCC APB3 Clock Register fields: - - name: LTDCEN - description: LTDC peripheral clock enable - bit_offset: 3 - bit_size: 1 - - name: DSIEN - description: DSI Peripheral clocks enable - bit_offset: 4 - bit_size: 1 - - name: WWDG1EN - description: WWDG1 Clock Enable - bit_offset: 6 - bit_size: 1 + - name: LTDCEN + description: LTDC peripheral clock enable + bit_offset: 3 + bit_size: 1 + - name: DSIEN + description: DSI Peripheral clocks enable + bit_offset: 4 + bit_size: 1 + - name: WWDG1EN + description: WWDG1 Clock Enable + bit_offset: 6 + bit_size: 1 fieldset/APB3LPENR: description: RCC APB3 Sleep Clock Register fields: - - name: LTDCLPEN - description: LTDC peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - - name: DSILPEN - description: DSI Peripheral Clock Enable During CSleep Mode - bit_offset: 4 - bit_size: 1 - - name: WWDG1LPEN - description: WWDG1 Clock Enable During CSleep Mode - bit_offset: 6 - bit_size: 1 + - name: LTDCLPEN + description: LTDC peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + - name: DSILPEN + description: DSI Peripheral Clock Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + - name: WWDG1LPEN + description: WWDG1 Clock Enable During CSleep Mode + bit_offset: 6 + bit_size: 1 fieldset/APB3RSTR: description: RCC APB3 Peripheral Reset Register fields: - - name: LTDCRST - description: LTDC block reset - bit_offset: 3 - bit_size: 1 - - name: DSIRST - description: DSI block reset - bit_offset: 4 - bit_size: 1 + - name: LTDCRST + description: LTDC block reset + bit_offset: 3 + bit_size: 1 + - name: DSIRST + description: DSI block reset + bit_offset: 4 + bit_size: 1 fieldset/APB4ENR: description: RCC APB4 Clock Register fields: - - name: SYSCFGEN - description: SYSCFG peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: LPUART1EN - description: LPUART1 Peripheral Clocks Enable - bit_offset: 3 - bit_size: 1 - - name: SPI6EN - description: SPI6 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - - name: I2C4EN - description: I2C4 Peripheral Clocks Enable - bit_offset: 7 - bit_size: 1 - - name: LPTIM2EN - description: LPTIM2 Peripheral Clocks Enable - bit_offset: 9 - bit_size: 1 - - name: LPTIM3EN - description: LPTIM3 Peripheral Clocks Enable - bit_offset: 10 - bit_size: 1 - - name: LPTIM4EN - description: LPTIM4 Peripheral Clocks Enable - bit_offset: 11 - bit_size: 1 - - name: LPTIM5EN - description: LPTIM5 Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - - name: DAC2EN - description: DAC2 (containing one converter) peripheral clock enable - bit_offset: 13 - bit_size: 1 - - name: COMP12EN - description: COMP1/2 peripheral clock enable - bit_offset: 14 - bit_size: 1 - - name: VREFEN - description: VREF peripheral clock enable - bit_offset: 15 - bit_size: 1 - - name: RTCAPBEN - description: RTC APB Clock Enable - bit_offset: 16 - bit_size: 1 - - name: SAI4EN - description: SAI4 Peripheral Clocks Enable - bit_offset: 21 - bit_size: 1 - - name: DTSEN - description: Digital temperature sensor block enable - bit_offset: 26 - bit_size: 1 + - name: SYSCFGEN + description: SYSCFG peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: LPUART1EN + description: LPUART1 Peripheral Clocks Enable + bit_offset: 3 + bit_size: 1 + - name: SPI6EN + description: SPI6 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + - name: I2C4EN + description: I2C4 Peripheral Clocks Enable + bit_offset: 7 + bit_size: 1 + - name: LPTIM2EN + description: LPTIM2 Peripheral Clocks Enable + bit_offset: 9 + bit_size: 1 + - name: LPTIM3EN + description: LPTIM3 Peripheral Clocks Enable + bit_offset: 10 + bit_size: 1 + - name: LPTIM4EN + description: LPTIM4 Peripheral Clocks Enable + bit_offset: 11 + bit_size: 1 + - name: LPTIM5EN + description: LPTIM5 Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + - name: DAC2EN + description: DAC2 (containing one converter) peripheral clock enable + bit_offset: 13 + bit_size: 1 + - name: COMP12EN + description: COMP1/2 peripheral clock enable + bit_offset: 14 + bit_size: 1 + - name: VREFEN + description: VREF peripheral clock enable + bit_offset: 15 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB Clock Enable + bit_offset: 16 + bit_size: 1 + - name: SAI4EN + description: SAI4 Peripheral Clocks Enable + bit_offset: 21 + bit_size: 1 + - name: DTSEN + description: Digital temperature sensor block enable + bit_offset: 26 + bit_size: 1 fieldset/APB4LPENR: description: RCC APB4 Sleep Clock Register fields: - - name: SYSCFGLPEN - description: SYSCFG peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: LPUART1LPEN - description: LPUART1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 3 - bit_size: 1 - - name: SPI6LPEN - description: SPI6 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - name: I2C4LPEN - description: I2C4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 7 - bit_size: 1 - - name: LPTIM2LPEN - description: LPTIM2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - - name: LPTIM3LPEN - description: LPTIM3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 10 - bit_size: 1 - - name: LPTIM4LPEN - description: LPTIM4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 11 - bit_size: 1 - - name: LPTIM5LPEN - description: LPTIM5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - - name: DAC2LPEN - description: DAC2 (containing one converter) peripheral clock enable during CSleep mode - bit_offset: 13 - bit_size: 1 - - name: COMP12LPEN - description: COMP1/2 peripheral clock enable during CSleep mode - bit_offset: 14 - bit_size: 1 - - name: VREFLPEN - description: VREF peripheral clock enable during CSleep mode - bit_offset: 15 - bit_size: 1 - - name: RTCAPBLPEN - description: RTC APB Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: SAI4LPEN - description: SAI4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - - name: DTSLPEN - description: Digital temperature sensor block enable during CSleep Mode - bit_offset: 26 - bit_size: 1 + - name: SYSCFGLPEN + description: SYSCFG peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: LPUART1LPEN + description: LPUART1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 3 + bit_size: 1 + - name: SPI6LPEN + description: SPI6 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: I2C4LPEN + description: I2C4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 7 + bit_size: 1 + - name: LPTIM2LPEN + description: LPTIM2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + - name: LPTIM3LPEN + description: LPTIM3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 10 + bit_size: 1 + - name: LPTIM4LPEN + description: LPTIM4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 11 + bit_size: 1 + - name: LPTIM5LPEN + description: LPTIM5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + - name: DAC2LPEN + description: DAC2 (containing one converter) peripheral clock enable during CSleep mode + bit_offset: 13 + bit_size: 1 + - name: COMP12LPEN + description: COMP1/2 peripheral clock enable during CSleep mode + bit_offset: 14 + bit_size: 1 + - name: VREFLPEN + description: VREF peripheral clock enable during CSleep mode + bit_offset: 15 + bit_size: 1 + - name: RTCAPBLPEN + description: RTC APB Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: SAI4LPEN + description: SAI4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: DTSLPEN + description: Digital temperature sensor block enable during CSleep Mode + bit_offset: 26 + bit_size: 1 fieldset/APB4RSTR: description: RCC APB4 Peripheral Reset Register fields: - - name: SYSCFGRST - description: SYSCFG block reset - bit_offset: 1 - bit_size: 1 - - name: LPUART1RST - description: LPUART1 block reset - bit_offset: 3 - bit_size: 1 - - name: SPI6RST - description: SPI6 block reset - bit_offset: 5 - bit_size: 1 - - name: I2C4RST - description: I2C4 block reset - bit_offset: 7 - bit_size: 1 - - name: LPTIM2RST - description: LPTIM2 block reset - bit_offset: 9 - bit_size: 1 - - name: LPTIM3RST - description: LPTIM3 block reset - bit_offset: 10 - bit_size: 1 - - name: LPTIM4RST - description: LPTIM4 block reset - bit_offset: 11 - bit_size: 1 - - name: LPTIM5RST - description: LPTIM5 block reset - bit_offset: 12 - bit_size: 1 - - name: DAC2RST - description: DAC2 (containing one converter) reset - bit_offset: 13 - bit_size: 1 - - name: COMP12RST - description: COMP12 Blocks Reset - bit_offset: 14 - bit_size: 1 - - name: VREFRST - description: VREF block reset - bit_offset: 15 - bit_size: 1 - - name: SAI4RST - description: SAI4 block reset - bit_offset: 21 - bit_size: 1 - - name: DTSRST - description: Digital temperature sensor block reset - bit_offset: 26 - bit_size: 1 + - name: SYSCFGRST + description: SYSCFG block reset + bit_offset: 1 + bit_size: 1 + - name: LPUART1RST + description: LPUART1 block reset + bit_offset: 3 + bit_size: 1 + - name: SPI6RST + description: SPI6 block reset + bit_offset: 5 + bit_size: 1 + - name: I2C4RST + description: I2C4 block reset + bit_offset: 7 + bit_size: 1 + - name: LPTIM2RST + description: LPTIM2 block reset + bit_offset: 9 + bit_size: 1 + - name: LPTIM3RST + description: LPTIM3 block reset + bit_offset: 10 + bit_size: 1 + - name: LPTIM4RST + description: LPTIM4 block reset + bit_offset: 11 + bit_size: 1 + - name: LPTIM5RST + description: LPTIM5 block reset + bit_offset: 12 + bit_size: 1 + - name: DAC2RST + description: DAC2 (containing one converter) reset + bit_offset: 13 + bit_size: 1 + - name: COMP12RST + description: COMP12 Blocks Reset + bit_offset: 14 + bit_size: 1 + - name: VREFRST + description: VREF block reset + bit_offset: 15 + bit_size: 1 + - name: SAI4RST + description: SAI4 block reset + bit_offset: 21 + bit_size: 1 + - name: DTSRST + description: Digital temperature sensor block reset + bit_offset: 26 + bit_size: 1 fieldset/BDCR: description: RCC Backup Domain Control Register fields: - - name: LSEON - description: LSE oscillator enabled - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: LSE oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: LSE oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: LSEDRV - description: LSE oscillator driving capability - bit_offset: 3 - bit_size: 2 - enum: LSEDRV - - name: LSECSSON - description: LSE clock security system enable - bit_offset: 5 - bit_size: 1 - - name: LSECSSD - description: LSE clock security system failure detection - bit_offset: 6 - bit_size: 1 - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: VSwitch domain software reset - bit_offset: 16 - bit_size: 1 + - name: LSEON + description: LSE oscillator enabled + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: LSE oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: LSE oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: LSE oscillator driving capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: LSE clock security system enable + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: LSE clock security system failure detection + bit_offset: 6 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: VSwitch domain software reset + bit_offset: 16 + bit_size: 1 fieldset/C1_AHB1ENR: description: RCC AHB1 Clock Register fields: - - name: DMA1EN - description: DMA1 Clock Enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: DMA2 Clock Enable - bit_offset: 1 - bit_size: 1 - - name: ADC12EN - description: ADC1/2 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - - name: ARTEN - description: ART Clock Enable - bit_offset: 14 - bit_size: 1 - - name: ETH1MACEN - description: Ethernet MAC bus interface Clock Enable - bit_offset: 15 - bit_size: 1 - - name: ETH1TXEN - description: Ethernet Transmission Clock Enable - bit_offset: 16 - bit_size: 1 - - name: ETH1RXEN - description: Ethernet Reception Clock Enable - bit_offset: 17 - bit_size: 1 - - name: USB_OTG_HSEN - description: USB_OTG_HS Peripheral Clocks Enable - bit_offset: 25 - bit_size: 1 - - name: USB_OTG_HS_ULPIEN - description: USB_PHY1 Clocks Enable - bit_offset: 26 - bit_size: 1 - - name: USB_OTG_FSEN - description: USB_OTG_FS Peripheral Clocks Enable - bit_offset: 27 - bit_size: 1 - - name: USB_OTG_FS_ULPIEN - description: USB_PHY2 Clocks Enable - bit_offset: 28 - bit_size: 1 + - name: DMA1EN + description: DMA1 Clock Enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 Clock Enable + bit_offset: 1 + bit_size: 1 + - name: ADC12EN + description: ADC1/2 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + - name: ARTEN + description: ART Clock Enable + bit_offset: 14 + bit_size: 1 + - name: ETH1MACEN + description: Ethernet MAC bus interface Clock Enable + bit_offset: 15 + bit_size: 1 + - name: ETH1TXEN + description: Ethernet Transmission Clock Enable + bit_offset: 16 + bit_size: 1 + - name: ETH1RXEN + description: Ethernet Reception Clock Enable + bit_offset: 17 + bit_size: 1 + - name: USB_OTG_HSEN + description: USB_OTG_HS Peripheral Clocks Enable + bit_offset: 25 + bit_size: 1 + - name: USB_OTG_HS_ULPIEN + description: USB_PHY1 Clocks Enable + bit_offset: 26 + bit_size: 1 + - name: USB_OTG_FSEN + description: USB_OTG_FS Peripheral Clocks Enable + bit_offset: 27 + bit_size: 1 + - name: USB_OTG_FS_ULPIEN + description: USB_PHY2 Clocks Enable + bit_offset: 28 + bit_size: 1 fieldset/C1_AHB1LPENR: description: RCC AHB1 Sleep Clock Register fields: - - name: DMA1LPEN - description: DMA1 Clock Enable During CSleep Mode - bit_offset: 0 - bit_size: 1 - - name: DMA2LPEN - description: DMA2 Clock Enable During CSleep Mode - bit_offset: 1 - bit_size: 1 - - name: ADC12LPEN - description: ADC1/2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - name: ARTLPEN - description: ART Clock Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - - name: ETH1MACLPEN - description: Ethernet MAC bus interface Clock Enable During CSleep Mode - bit_offset: 15 - bit_size: 1 - - name: ETH1TXLPEN - description: Ethernet Transmission Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: ETH1RXLPEN - description: Ethernet Reception Clock Enable During CSleep Mode - bit_offset: 17 - bit_size: 1 - - name: USB_OTG_HSLPEN - description: USB_OTG_HS peripheral clock enable during CSleep mode - bit_offset: 25 - bit_size: 1 - - name: USB_OTG_HS_ULPILPEN - description: USB_PHY1 clock enable during CSleep mode - bit_offset: 26 - bit_size: 1 - - name: USB_OTG_FSLPEN - description: USB_OTG_FS peripheral clock enable during CSleep mode - bit_offset: 27 - bit_size: 1 - - name: USB_OTG_FS_ULPILPEN - description: USB_PHY2 clocks enable during CSleep mode - bit_offset: 28 - bit_size: 1 + - name: DMA1LPEN + description: DMA1 Clock Enable During CSleep Mode + bit_offset: 0 + bit_size: 1 + - name: DMA2LPEN + description: DMA2 Clock Enable During CSleep Mode + bit_offset: 1 + bit_size: 1 + - name: ADC12LPEN + description: ADC1/2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: ARTLPEN + description: ART Clock Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + - name: ETH1MACLPEN + description: Ethernet MAC bus interface Clock Enable During CSleep Mode + bit_offset: 15 + bit_size: 1 + - name: ETH1TXLPEN + description: Ethernet Transmission Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: ETH1RXLPEN + description: Ethernet Reception Clock Enable During CSleep Mode + bit_offset: 17 + bit_size: 1 + - name: USB_OTG_HSLPEN + description: USB_OTG_HS peripheral clock enable during CSleep mode + bit_offset: 25 + bit_size: 1 + - name: USB_OTG_HS_ULPILPEN + description: USB_PHY1 clock enable during CSleep mode + bit_offset: 26 + bit_size: 1 + - name: USB_OTG_FSLPEN + description: USB_OTG_FS peripheral clock enable during CSleep mode + bit_offset: 27 + bit_size: 1 + - name: USB_OTG_FS_ULPILPEN + description: USB_PHY2 clocks enable during CSleep mode + bit_offset: 28 + bit_size: 1 fieldset/C1_AHB2ENR: description: RCC AHB2 Clock Register fields: - - name: DCMIEN - description: DCMI peripheral clock - bit_offset: 0 - bit_size: 1 - - name: CRYPTEN - description: CRYPT peripheral clock enable - bit_offset: 4 - bit_size: 1 - - name: HASHEN - description: HASH peripheral clock enable - bit_offset: 5 - bit_size: 1 - - name: RNGEN - description: RNG peripheral clocks enable - bit_offset: 6 - bit_size: 1 - - name: SDMMC2EN - description: SDMMC2 and SDMMC2 delay clock enable - bit_offset: 9 - bit_size: 1 - - name: SRAM1EN - description: SRAM1 block enable - bit_offset: 29 - bit_size: 1 - - name: SRAM2EN - description: SRAM2 block enable - bit_offset: 30 - bit_size: 1 - - name: SRAM3EN - description: SRAM3 block enable - bit_offset: 31 - bit_size: 1 + - name: DCMIEN + description: DCMI peripheral clock + bit_offset: 0 + bit_size: 1 + - name: CRYPTEN + description: CRYPT peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: HASHEN + description: HASH peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: RNGEN + description: RNG peripheral clocks enable + bit_offset: 6 + bit_size: 1 + - name: SDMMC2EN + description: SDMMC2 and SDMMC2 delay clock enable + bit_offset: 9 + bit_size: 1 + - name: SRAM1EN + description: SRAM1 block enable + bit_offset: 29 + bit_size: 1 + - name: SRAM2EN + description: SRAM2 block enable + bit_offset: 30 + bit_size: 1 + - name: SRAM3EN + description: SRAM3 block enable + bit_offset: 31 + bit_size: 1 fieldset/C1_AHB2LPENR: description: RCC AHB2 Sleep Clock Register fields: - - name: DCMILPEN - description: DCMI peripheral clock enable during csleep mode - bit_offset: 0 - bit_size: 1 - - name: CRYPTLPEN - description: CRYPT peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - name: HASHLPEN - description: HASH peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - name: RNGLPEN - description: RNG peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - - name: SDMMC2LPEN - description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - - name: FMACLPEN - description: FMAC enable during CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: CORDICLPEN - description: CORDIC enable during CSleep Mode - bit_offset: 17 - bit_size: 1 - - name: SRAM1LPEN - description: SRAM1 Clock Enable During CSleep Mode - bit_offset: 29 - bit_size: 1 - - name: SRAM2LPEN - description: SRAM2 Clock Enable During CSleep Mode - bit_offset: 30 - bit_size: 1 - - name: SRAM3LPEN - description: SRAM3 Clock Enable During CSleep Mode - bit_offset: 31 - bit_size: 1 + - name: DCMILPEN + description: DCMI peripheral clock enable during csleep mode + bit_offset: 0 + bit_size: 1 + - name: CRYPTLPEN + description: CRYPT peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: HASHLPEN + description: HASH peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: RNGLPEN + description: RNG peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + - name: SDMMC2LPEN + description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + - name: FMACLPEN + description: FMAC enable during CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: CORDICLPEN + description: CORDIC enable during CSleep Mode + bit_offset: 17 + bit_size: 1 + - name: SRAM1LPEN + description: SRAM1 Clock Enable During CSleep Mode + bit_offset: 29 + bit_size: 1 + - name: SRAM2LPEN + description: SRAM2 Clock Enable During CSleep Mode + bit_offset: 30 + bit_size: 1 + - name: SRAM3LPEN + description: SRAM3 Clock Enable During CSleep Mode + bit_offset: 31 + bit_size: 1 fieldset/C1_AHB3ENR: description: RCC AHB3 Clock Register fields: - - name: MDMAEN - description: MDMA Peripheral Clock Enable - bit_offset: 0 - bit_size: 1 - - name: DMA2DEN - description: DMA2D Peripheral Clock Enable - bit_offset: 4 - bit_size: 1 - - name: JPGDECEN - description: JPGDEC Peripheral Clock Enable - bit_offset: 5 - bit_size: 1 - - name: FMCEN - description: FMC Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - - name: QUADSPIEN - description: QUADSPI and QUADSPI Delay Clock Enable - bit_offset: 14 - bit_size: 1 - - name: SDMMC1EN - description: SDMMC1 and SDMMC1 Delay Clock Enable - bit_offset: 16 - bit_size: 1 + - name: MDMAEN + description: MDMA Peripheral Clock Enable + bit_offset: 0 + bit_size: 1 + - name: DMA2DEN + description: DMA2D Peripheral Clock Enable + bit_offset: 4 + bit_size: 1 + - name: JPGDECEN + description: JPGDEC Peripheral Clock Enable + bit_offset: 5 + bit_size: 1 + - name: FMCEN + description: FMC Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + - name: QUADSPIEN + description: QUADSPI and QUADSPI Delay Clock Enable + bit_offset: 14 + bit_size: 1 + - name: SDMMC1EN + description: SDMMC1 and SDMMC1 Delay Clock Enable + bit_offset: 16 + bit_size: 1 fieldset/C1_AHB3LPENR: description: RCC AHB3 Sleep Clock Register fields: - - name: MDMALPEN - description: MDMA Clock Enable During CSleep Mode - bit_offset: 0 - bit_size: 1 - - name: DMA2DLPEN - description: DMA2D Clock Enable During CSleep Mode - bit_offset: 4 - bit_size: 1 - - name: JPGDECLPEN - description: JPGDEC Clock Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - name: FLASHPREN - description: Flash interface clock enable during csleep mode - bit_offset: 8 - bit_size: 1 - - name: FMCLPEN - description: FMC Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - - name: QSPILPEN - description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - - name: SDMMC1LPEN - description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: OCTOSPI2LPEN - description: OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode - bit_offset: 19 - bit_size: 1 - - name: IOMNGRLPEN - description: OCTOSPI IO manager enable during CSleep Mode - bit_offset: 21 - bit_size: 1 - - name: OTFD1LPEN - description: OTFDEC1 enable during CSleep Mode - bit_offset: 22 - bit_size: 1 - - name: OTFD2LPEN - description: OTFDEC2 enable during CSleep Mode - bit_offset: 23 - bit_size: 1 - - name: D1DTCM1LPEN - description: D1DTCM1 Block Clock Enable During CSleep mode - bit_offset: 28 - bit_size: 1 - - name: DTCM2LPEN - description: D1 DTCM2 Block Clock Enable During CSleep mode - bit_offset: 29 - bit_size: 1 - - name: ITCMLPEN - description: D1ITCM Block Clock Enable During CSleep mode - bit_offset: 30 - bit_size: 1 - - name: AXISRAMLPEN - description: AXISRAM Block Clock Enable During CSleep mode - bit_offset: 31 - bit_size: 1 + - name: MDMALPEN + description: MDMA Clock Enable During CSleep Mode + bit_offset: 0 + bit_size: 1 + - name: DMA2DLPEN + description: DMA2D Clock Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + - name: JPGDECLPEN + description: JPGDEC Clock Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: FLASHPREN + description: Flash interface clock enable during csleep mode + bit_offset: 8 + bit_size: 1 + - name: FMCLPEN + description: FMC Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + - name: QSPILPEN + description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + - name: SDMMC1LPEN + description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: OCTOSPI2LPEN + description: OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode + bit_offset: 19 + bit_size: 1 + - name: IOMNGRLPEN + description: OCTOSPI IO manager enable during CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: OTFD1LPEN + description: OTFDEC1 enable during CSleep Mode + bit_offset: 22 + bit_size: 1 + - name: OTFD2LPEN + description: OTFDEC2 enable during CSleep Mode + bit_offset: 23 + bit_size: 1 + - name: D1DTCM1LPEN + description: D1DTCM1 Block Clock Enable During CSleep mode + bit_offset: 28 + bit_size: 1 + - name: DTCM2LPEN + description: D1 DTCM2 Block Clock Enable During CSleep mode + bit_offset: 29 + bit_size: 1 + - name: ITCMLPEN + description: D1ITCM Block Clock Enable During CSleep mode + bit_offset: 30 + bit_size: 1 + - name: AXISRAMLPEN + description: AXISRAM Block Clock Enable During CSleep mode + bit_offset: 31 + bit_size: 1 fieldset/C1_AHB4ENR: description: RCC AHB4 Clock Register fields: - - name: GPIOAEN - description: 0GPIO peripheral clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: 0GPIO peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: 0GPIO peripheral clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: 0GPIO peripheral clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: 0GPIO peripheral clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIOFEN - description: 0GPIO peripheral clock enable - bit_offset: 5 - bit_size: 1 - - name: GPIOGEN - description: 0GPIO peripheral clock enable - bit_offset: 6 - bit_size: 1 - - name: GPIOHEN - description: 0GPIO peripheral clock enable - bit_offset: 7 - bit_size: 1 - - name: GPIOIEN - description: 0GPIO peripheral clock enable - bit_offset: 8 - bit_size: 1 - - name: GPIOJEN - description: 0GPIO peripheral clock enable - bit_offset: 9 - bit_size: 1 - - name: GPIOKEN - description: 0GPIO peripheral clock enable - bit_offset: 10 - bit_size: 1 - - name: CRCEN - description: CRC peripheral clock enable - bit_offset: 19 - bit_size: 1 - - name: BDMAEN - description: BDMA and DMAMUX2 Clock Enable - bit_offset: 21 - bit_size: 1 - - name: ADC3EN - description: ADC3 Peripheral Clocks Enable - bit_offset: 24 - bit_size: 1 - - name: HSEMEN - description: HSEM peripheral clock enable - bit_offset: 25 - bit_size: 1 - - name: BKPSRAMEN - description: Backup RAM Clock Enable - bit_offset: 28 - bit_size: 1 + - name: GPIOAEN + description: 0GPIO peripheral clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: 0GPIO peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: 0GPIO peripheral clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: 0GPIO peripheral clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: 0GPIO peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: 0GPIO peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: 0GPIO peripheral clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: 0GPIO peripheral clock enable + bit_offset: 7 + bit_size: 1 + - name: GPIOIEN + description: 0GPIO peripheral clock enable + bit_offset: 8 + bit_size: 1 + - name: GPIOJEN + description: 0GPIO peripheral clock enable + bit_offset: 9 + bit_size: 1 + - name: GPIOKEN + description: 0GPIO peripheral clock enable + bit_offset: 10 + bit_size: 1 + - name: CRCEN + description: CRC peripheral clock enable + bit_offset: 19 + bit_size: 1 + - name: BDMAEN + description: BDMA and DMAMUX2 Clock Enable + bit_offset: 21 + bit_size: 1 + - name: ADC3EN + description: ADC3 Peripheral Clocks Enable + bit_offset: 24 + bit_size: 1 + - name: HSEMEN + description: HSEM peripheral clock enable + bit_offset: 25 + bit_size: 1 + - name: BKPSRAMEN + description: Backup RAM Clock Enable + bit_offset: 28 + bit_size: 1 fieldset/C1_AHB4LPENR: description: RCC AHB4 Sleep Clock Register fields: - - name: GPIOALPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - - name: GPIOBLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: GPIOCLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 2 - bit_size: 1 - - name: GPIODLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - - name: GPIOELPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - name: GPIOFLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - name: GPIOGLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - - name: GPIOHLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 7 - bit_size: 1 - - name: GPIOILPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 8 - bit_size: 1 - - name: GPIOJLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 9 - bit_size: 1 - - name: GPIOKLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 10 - bit_size: 1 - - name: CRCLPEN - description: CRC peripheral clock enable during CSleep mode - bit_offset: 19 - bit_size: 1 - - name: BDMALPEN - description: BDMA Clock Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - - name: ADC3LPEN - description: ADC3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 24 - bit_size: 1 - - name: BKPSRAMLPEN - description: Backup RAM Clock Enable During CSleep Mode - bit_offset: 28 - bit_size: 1 - - name: SRAM4LPEN - description: SRAM4 Clock Enable During CSleep Mode - bit_offset: 29 - bit_size: 1 + - name: GPIOALPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 2 + bit_size: 1 + - name: GPIODLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + - name: GPIOELPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: GPIOFLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: GPIOGLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + - name: GPIOHLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 7 + bit_size: 1 + - name: GPIOILPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 8 + bit_size: 1 + - name: GPIOJLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 9 + bit_size: 1 + - name: GPIOKLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 10 + bit_size: 1 + - name: CRCLPEN + description: CRC peripheral clock enable during CSleep mode + bit_offset: 19 + bit_size: 1 + - name: BDMALPEN + description: BDMA Clock Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: ADC3LPEN + description: ADC3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 24 + bit_size: 1 + - name: BKPSRAMLPEN + description: Backup RAM Clock Enable During CSleep Mode + bit_offset: 28 + bit_size: 1 + - name: SRAM4LPEN + description: SRAM4 Clock Enable During CSleep Mode + bit_offset: 29 + bit_size: 1 fieldset/C1_APB1HENR: description: RCC APB1 Clock Register fields: - - name: CRSEN - description: Clock Recovery System peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: SWPEN - description: SWPMI Peripheral Clocks Enable - bit_offset: 2 - bit_size: 1 - - name: OPAMPEN - description: OPAMP peripheral clock enable - bit_offset: 4 - bit_size: 1 - - name: MDIOSEN - description: MDIOS peripheral clock enable - bit_offset: 5 - bit_size: 1 - - name: FDCANEN - description: FDCAN Peripheral Clocks Enable - bit_offset: 8 - bit_size: 1 + - name: CRSEN + description: Clock Recovery System peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: SWPEN + description: SWPMI Peripheral Clocks Enable + bit_offset: 2 + bit_size: 1 + - name: OPAMPEN + description: OPAMP peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: MDIOSEN + description: MDIOS peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: FDCANEN + description: FDCAN Peripheral Clocks Enable + bit_offset: 8 + bit_size: 1 fieldset/C1_APB1HLPENR: description: RCC APB1 High Sleep Clock Register fields: - - name: CRSLPEN - description: Clock Recovery System peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: SWPLPEN - description: SWPMI Peripheral Clocks Enable During CSleep Mode - bit_offset: 2 - bit_size: 1 - - name: OPAMPLPEN - description: OPAMP peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - name: MDIOSLPEN - description: MDIOS peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - name: FDCANLPEN - description: FDCAN Peripheral Clocks Enable During CSleep Mode - bit_offset: 8 - bit_size: 1 - - name: TIM23LPEN - description: TIM23 block enable during CSleep Mode - bit_offset: 24 - bit_size: 1 - - name: TIM24LPEN - description: TIM24 block enable during CSleep Mode - bit_offset: 25 - bit_size: 1 + - name: CRSLPEN + description: Clock Recovery System peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: SWPLPEN + description: SWPMI Peripheral Clocks Enable During CSleep Mode + bit_offset: 2 + bit_size: 1 + - name: OPAMPLPEN + description: OPAMP peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: MDIOSLPEN + description: MDIOS peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: FDCANLPEN + description: FDCAN Peripheral Clocks Enable During CSleep Mode + bit_offset: 8 + bit_size: 1 + - name: TIM23LPEN + description: TIM23 block enable during CSleep Mode + bit_offset: 24 + bit_size: 1 + - name: TIM24LPEN + description: TIM24 block enable during CSleep Mode + bit_offset: 25 + bit_size: 1 fieldset/C1_APB1LENR: description: RCC APB1 Clock Register fields: - - name: TIM2EN - description: TIM peripheral clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: TIM peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: TIM peripheral clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: TIM peripheral clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: TIM peripheral clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: TIM peripheral clock enable - bit_offset: 5 - bit_size: 1 - - name: TIM12EN - description: TIM peripheral clock enable - bit_offset: 6 - bit_size: 1 - - name: TIM13EN - description: TIM peripheral clock enable - bit_offset: 7 - bit_size: 1 - - name: TIM14EN - description: TIM peripheral clock enable - bit_offset: 8 - bit_size: 1 - - name: LPTIM1EN - description: LPTIM1 Peripheral Clocks Enable - bit_offset: 9 - bit_size: 1 - - name: WWDG2EN - description: WWDG2 peripheral clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI2 Peripheral Clocks Enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI3 Peripheral Clocks Enable - bit_offset: 15 - bit_size: 1 - - name: SPDIFRXEN - description: SPDIFRX Peripheral Clocks Enable - bit_offset: 16 - bit_size: 1 - - name: USART2EN - description: USART2 Peripheral Clocks Enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART3 Peripheral Clocks Enable - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: UART4 Peripheral Clocks Enable - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: UART5 Peripheral Clocks Enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C1 Peripheral Clocks Enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C2 Peripheral Clocks Enable - bit_offset: 22 - bit_size: 1 - - name: I2C3EN - description: I2C3 Peripheral Clocks Enable - bit_offset: 23 - bit_size: 1 - - name: I2C5EN - description: "I2C5 Peripheral Clocks\r Enable" - bit_offset: 25 - bit_size: 1 - - name: CECEN - description: HDMI-CEC peripheral clock enable - bit_offset: 27 - bit_size: 1 - - name: DAC12EN - description: DAC1&2 peripheral clock enable - bit_offset: 29 - bit_size: 1 - - name: UART7EN - description: UART7 Peripheral Clocks Enable - bit_offset: 30 - bit_size: 1 - - name: UART8EN - description: UART8 Peripheral Clocks Enable - bit_offset: 31 - bit_size: 1 + - name: TIM2EN + description: TIM peripheral clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM peripheral clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: TIM peripheral clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: TIM peripheral clock enable + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: TIM peripheral clock enable + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: TIM peripheral clock enable + bit_offset: 8 + bit_size: 1 + - name: LPTIM1EN + description: LPTIM1 Peripheral Clocks Enable + bit_offset: 9 + bit_size: 1 + - name: WWDG2EN + description: WWDG2 peripheral clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 Peripheral Clocks Enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 Peripheral Clocks Enable + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXEN + description: SPDIFRX Peripheral Clocks Enable + bit_offset: 16 + bit_size: 1 + - name: USART2EN + description: USART2 Peripheral Clocks Enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 Peripheral Clocks Enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 Peripheral Clocks Enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 Peripheral Clocks Enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 Peripheral Clocks Enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 Peripheral Clocks Enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: I2C3 Peripheral Clocks Enable + bit_offset: 23 + bit_size: 1 + - name: I2C5EN + description: "I2C5 Peripheral Clocks\r Enable" + bit_offset: 25 + bit_size: 1 + - name: CECEN + description: HDMI-CEC peripheral clock enable + bit_offset: 27 + bit_size: 1 + - name: DAC12EN + description: DAC1&2 peripheral clock enable + bit_offset: 29 + bit_size: 1 + - name: UART7EN + description: UART7 Peripheral Clocks Enable + bit_offset: 30 + bit_size: 1 + - name: UART8EN + description: UART8 Peripheral Clocks Enable + bit_offset: 31 + bit_size: 1 fieldset/C1_APB1LLPENR: description: RCC APB1 Low Sleep Clock Register fields: - - name: TIM2LPEN - description: TIM2 peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM3LPEN - description: TIM3 peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: TIM4LPEN - description: TIM4 peripheral clock enable during CSleep mode - bit_offset: 2 - bit_size: 1 - - name: TIM5LPEN - description: TIM5 peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - - name: TIM6LPEN - description: TIM6 peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - name: TIM7LPEN - description: TIM7 peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - name: TIM12LPEN - description: TIM12 peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - - name: TIM13LPEN - description: TIM13 peripheral clock enable during CSleep mode - bit_offset: 7 - bit_size: 1 - - name: TIM14LPEN - description: TIM14 peripheral clock enable during CSleep mode - bit_offset: 8 - bit_size: 1 - - name: LPTIM1LPEN - description: LPTIM1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - - name: WWDG2LPEN - description: WWDG2 peripheral Clocks Enable During CSleep Mode - bit_offset: 11 - bit_size: 1 - - name: SPI2LPEN - description: SPI2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - - name: SPI3LPEN - description: SPI3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 15 - bit_size: 1 - - name: SPDIFRXLPEN - description: SPDIFRX Peripheral Clocks Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: USART2LPEN - description: USART2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 17 - bit_size: 1 - - name: USART3LPEN - description: USART3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 18 - bit_size: 1 - - name: UART4LPEN - description: UART4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 19 - bit_size: 1 - - name: UART5LPEN - description: UART5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 20 - bit_size: 1 - - name: I2C1LPEN - description: I2C1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - - name: I2C2LPEN - description: I2C2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 22 - bit_size: 1 - - name: I2C3LPEN - description: I2C3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 23 - bit_size: 1 - - name: I2C5LPEN - description: I2C5 block enable during CSleep Mode - bit_offset: 25 - bit_size: 1 - - name: CECLPEN - description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode - bit_offset: 27 - bit_size: 1 - - name: DAC12LPEN - description: DAC1/2 peripheral clock enable during CSleep mode - bit_offset: 29 - bit_size: 1 - - name: UART7LPEN - description: UART7 Peripheral Clocks Enable During CSleep Mode - bit_offset: 30 - bit_size: 1 - - name: UART8LPEN - description: UART8 Peripheral Clocks Enable During CSleep Mode - bit_offset: 31 - bit_size: 1 + - name: TIM2LPEN + description: TIM2 peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM3LPEN + description: TIM3 peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: TIM4LPEN + description: TIM4 peripheral clock enable during CSleep mode + bit_offset: 2 + bit_size: 1 + - name: TIM5LPEN + description: TIM5 peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + - name: TIM6LPEN + description: TIM6 peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: TIM7LPEN + description: TIM7 peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: TIM12LPEN + description: TIM12 peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + - name: TIM13LPEN + description: TIM13 peripheral clock enable during CSleep mode + bit_offset: 7 + bit_size: 1 + - name: TIM14LPEN + description: TIM14 peripheral clock enable during CSleep mode + bit_offset: 8 + bit_size: 1 + - name: LPTIM1LPEN + description: LPTIM1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + - name: WWDG2LPEN + description: WWDG2 peripheral Clocks Enable During CSleep Mode + bit_offset: 11 + bit_size: 1 + - name: SPI2LPEN + description: SPI2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + - name: SPI3LPEN + description: SPI3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXLPEN + description: SPDIFRX Peripheral Clocks Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: USART2LPEN + description: USART2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 17 + bit_size: 1 + - name: USART3LPEN + description: USART3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 18 + bit_size: 1 + - name: UART4LPEN + description: UART4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 19 + bit_size: 1 + - name: UART5LPEN + description: UART5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 20 + bit_size: 1 + - name: I2C1LPEN + description: I2C1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: I2C2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 22 + bit_size: 1 + - name: I2C3LPEN + description: I2C3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 23 + bit_size: 1 + - name: I2C5LPEN + description: I2C5 block enable during CSleep Mode + bit_offset: 25 + bit_size: 1 + - name: CECLPEN + description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode + bit_offset: 27 + bit_size: 1 + - name: DAC12LPEN + description: DAC1/2 peripheral clock enable during CSleep mode + bit_offset: 29 + bit_size: 1 + - name: UART7LPEN + description: UART7 Peripheral Clocks Enable During CSleep Mode + bit_offset: 30 + bit_size: 1 + - name: UART8LPEN + description: UART8 Peripheral Clocks Enable During CSleep Mode + bit_offset: 31 + bit_size: 1 fieldset/C1_APB2ENR: description: RCC APB2 Clock Register fields: - - name: TIM1EN - description: TIM1 peripheral clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM8EN - description: TIM8 peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: USART1EN - description: USART1 Peripheral Clocks Enable - bit_offset: 4 - bit_size: 1 - - name: USART6EN - description: USART6 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - - name: UART9EN - description: "UART9 Peripheral Clocks\r Enable" - bit_offset: 6 - bit_size: 1 - - name: USART10EN - description: "USART10 Peripheral Clocks\r Enable" - bit_offset: 7 - bit_size: 1 - - name: SPI1EN - description: SPI1 Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - - name: SPI4EN - description: SPI4 Peripheral Clocks Enable - bit_offset: 13 - bit_size: 1 - - name: TIM15EN - description: TIM15 peripheral clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: TIM16 peripheral clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: TIM17 peripheral clock enable - bit_offset: 18 - bit_size: 1 - - name: SPI5EN - description: SPI5 Peripheral Clocks Enable - bit_offset: 20 - bit_size: 1 - - name: SAI1EN - description: SAI1 Peripheral Clocks Enable - bit_offset: 22 - bit_size: 1 - - name: SAI2EN - description: SAI2 Peripheral Clocks Enable - bit_offset: 23 - bit_size: 1 - - name: SAI3EN - description: SAI3 Peripheral Clocks Enable - bit_offset: 24 - bit_size: 1 - - name: DFSDM1EN - description: DFSDM1 Peripheral Clocks Enable - bit_offset: 28 - bit_size: 1 - - name: HRTIMEN - description: HRTIM peripheral clock enable - bit_offset: 29 - bit_size: 1 + - name: TIM1EN + description: TIM1 peripheral clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM8EN + description: TIM8 peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: USART1EN + description: USART1 Peripheral Clocks Enable + bit_offset: 4 + bit_size: 1 + - name: USART6EN + description: USART6 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + - name: UART9EN + description: "UART9 Peripheral Clocks\r Enable" + bit_offset: 6 + bit_size: 1 + - name: USART10EN + description: "USART10 Peripheral Clocks\r Enable" + bit_offset: 7 + bit_size: 1 + - name: SPI1EN + description: SPI1 Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + - name: SPI4EN + description: SPI4 Peripheral Clocks Enable + bit_offset: 13 + bit_size: 1 + - name: TIM15EN + description: TIM15 peripheral clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 peripheral clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 peripheral clock enable + bit_offset: 18 + bit_size: 1 + - name: SPI5EN + description: SPI5 Peripheral Clocks Enable + bit_offset: 20 + bit_size: 1 + - name: SAI1EN + description: SAI1 Peripheral Clocks Enable + bit_offset: 22 + bit_size: 1 + - name: SAI2EN + description: SAI2 Peripheral Clocks Enable + bit_offset: 23 + bit_size: 1 + - name: SAI3EN + description: SAI3 Peripheral Clocks Enable + bit_offset: 24 + bit_size: 1 + - name: DFSDM1EN + description: DFSDM1 Peripheral Clocks Enable + bit_offset: 28 + bit_size: 1 + - name: HRTIMEN + description: HRTIM peripheral clock enable + bit_offset: 29 + bit_size: 1 fieldset/C1_APB2LPENR: description: RCC APB2 Sleep Clock Register fields: - - name: TIM1LPEN - description: TIM1 peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM8LPEN - description: TIM8 peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: USART1LPEN - description: USART1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 4 - bit_size: 1 - - name: USART6LPEN - description: USART6 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - name: SPI1LPEN - description: SPI1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - - name: SPI4LPEN - description: SPI4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 13 - bit_size: 1 - - name: TIM15LPEN - description: TIM15 peripheral clock enable during CSleep mode - bit_offset: 16 - bit_size: 1 - - name: TIM16LPEN - description: TIM16 peripheral clock enable during CSleep mode - bit_offset: 17 - bit_size: 1 - - name: TIM17LPEN - description: TIM17 peripheral clock enable during CSleep mode - bit_offset: 18 - bit_size: 1 - - name: SPI5LPEN - description: SPI5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 20 - bit_size: 1 - - name: SAI1LPEN - description: SAI1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 22 - bit_size: 1 - - name: SAI2LPEN - description: SAI2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 23 - bit_size: 1 - - name: SAI3LPEN - description: SAI3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 24 - bit_size: 1 - - name: DFSDM1LPEN - description: DFSDM1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 28 - bit_size: 1 - - name: HRTIMLPEN - description: HRTIM peripheral clock enable during CSleep mode - bit_offset: 29 - bit_size: 1 + - name: TIM1LPEN + description: TIM1 peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM8LPEN + description: TIM8 peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: USART1LPEN + description: USART1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + - name: USART6LPEN + description: USART6 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: SPI1LPEN + description: SPI1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + - name: SPI4LPEN + description: SPI4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 13 + bit_size: 1 + - name: TIM15LPEN + description: TIM15 peripheral clock enable during CSleep mode + bit_offset: 16 + bit_size: 1 + - name: TIM16LPEN + description: TIM16 peripheral clock enable during CSleep mode + bit_offset: 17 + bit_size: 1 + - name: TIM17LPEN + description: TIM17 peripheral clock enable during CSleep mode + bit_offset: 18 + bit_size: 1 + - name: SPI5LPEN + description: SPI5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 20 + bit_size: 1 + - name: SAI1LPEN + description: SAI1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 22 + bit_size: 1 + - name: SAI2LPEN + description: SAI2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 23 + bit_size: 1 + - name: SAI3LPEN + description: SAI3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 24 + bit_size: 1 + - name: DFSDM1LPEN + description: DFSDM1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 28 + bit_size: 1 + - name: HRTIMLPEN + description: HRTIM peripheral clock enable during CSleep mode + bit_offset: 29 + bit_size: 1 fieldset/C1_APB3ENR: description: RCC APB3 Clock Register fields: - - name: LTDCEN - description: LTDC peripheral clock enable - bit_offset: 3 - bit_size: 1 - - name: DSIEN - description: DSI Peripheral clocks enable - bit_offset: 4 - bit_size: 1 - - name: WWDG1EN - description: WWDG1 Clock Enable - bit_offset: 6 - bit_size: 1 + - name: LTDCEN + description: LTDC peripheral clock enable + bit_offset: 3 + bit_size: 1 + - name: DSIEN + description: DSI Peripheral clocks enable + bit_offset: 4 + bit_size: 1 + - name: WWDG1EN + description: WWDG1 Clock Enable + bit_offset: 6 + bit_size: 1 fieldset/C1_APB3LPENR: description: RCC APB3 Sleep Clock Register fields: - - name: LTDCLPEN - description: LTDC peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - - name: DSILPEN - description: DSI Peripheral Clock Enable During CSleep Mode - bit_offset: 4 - bit_size: 1 - - name: WWDG1LPEN - description: WWDG1 Clock Enable During CSleep Mode - bit_offset: 6 - bit_size: 1 + - name: LTDCLPEN + description: LTDC peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + - name: DSILPEN + description: DSI Peripheral Clock Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + - name: WWDG1LPEN + description: WWDG1 Clock Enable During CSleep Mode + bit_offset: 6 + bit_size: 1 fieldset/C1_APB4ENR: description: RCC APB4 Clock Register fields: - - name: SYSCFGEN - description: SYSCFG peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: LPUART1EN - description: LPUART1 Peripheral Clocks Enable - bit_offset: 3 - bit_size: 1 - - name: SPI6EN - description: SPI6 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - - name: I2C4EN - description: I2C4 Peripheral Clocks Enable - bit_offset: 7 - bit_size: 1 - - name: LPTIM2EN - description: LPTIM2 Peripheral Clocks Enable - bit_offset: 9 - bit_size: 1 - - name: LPTIM3EN - description: LPTIM3 Peripheral Clocks Enable - bit_offset: 10 - bit_size: 1 - - name: LPTIM4EN - description: LPTIM4 Peripheral Clocks Enable - bit_offset: 11 - bit_size: 1 - - name: LPTIM5EN - description: LPTIM5 Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - - name: COMP12EN - description: COMP1/2 peripheral clock enable - bit_offset: 14 - bit_size: 1 - - name: VREFEN - description: VREF peripheral clock enable - bit_offset: 15 - bit_size: 1 - - name: RTCAPBEN - description: RTC APB Clock Enable - bit_offset: 16 - bit_size: 1 - - name: SAI4EN - description: SAI4 Peripheral Clocks Enable - bit_offset: 21 - bit_size: 1 + - name: SYSCFGEN + description: SYSCFG peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: LPUART1EN + description: LPUART1 Peripheral Clocks Enable + bit_offset: 3 + bit_size: 1 + - name: SPI6EN + description: SPI6 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + - name: I2C4EN + description: I2C4 Peripheral Clocks Enable + bit_offset: 7 + bit_size: 1 + - name: LPTIM2EN + description: LPTIM2 Peripheral Clocks Enable + bit_offset: 9 + bit_size: 1 + - name: LPTIM3EN + description: LPTIM3 Peripheral Clocks Enable + bit_offset: 10 + bit_size: 1 + - name: LPTIM4EN + description: LPTIM4 Peripheral Clocks Enable + bit_offset: 11 + bit_size: 1 + - name: LPTIM5EN + description: LPTIM5 Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + - name: COMP12EN + description: COMP1/2 peripheral clock enable + bit_offset: 14 + bit_size: 1 + - name: VREFEN + description: VREF peripheral clock enable + bit_offset: 15 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB Clock Enable + bit_offset: 16 + bit_size: 1 + - name: SAI4EN + description: SAI4 Peripheral Clocks Enable + bit_offset: 21 + bit_size: 1 fieldset/C1_APB4LPENR: description: RCC APB4 Sleep Clock Register fields: - - name: SYSCFGLPEN - description: SYSCFG peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: LPUART1LPEN - description: LPUART1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 3 - bit_size: 1 - - name: SPI6LPEN - description: SPI6 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - name: I2C4LPEN - description: I2C4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 7 - bit_size: 1 - - name: LPTIM2LPEN - description: LPTIM2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - - name: LPTIM3LPEN - description: LPTIM3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 10 - bit_size: 1 - - name: LPTIM4LPEN - description: LPTIM4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 11 - bit_size: 1 - - name: LPTIM5LPEN - description: LPTIM5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - - name: COMP12LPEN - description: COMP1/2 peripheral clock enable during CSleep mode - bit_offset: 14 - bit_size: 1 - - name: VREFLPEN - description: VREF peripheral clock enable during CSleep mode - bit_offset: 15 - bit_size: 1 - - name: RTCAPBLPEN - description: RTC APB Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: SAI4LPEN - description: SAI4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - - name: DTSLPEN - description: Digital temperature sensor block enable during CSleep Mode - bit_offset: 26 - bit_size: 1 + - name: SYSCFGLPEN + description: SYSCFG peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: LPUART1LPEN + description: LPUART1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 3 + bit_size: 1 + - name: SPI6LPEN + description: SPI6 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: I2C4LPEN + description: I2C4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 7 + bit_size: 1 + - name: LPTIM2LPEN + description: LPTIM2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + - name: LPTIM3LPEN + description: LPTIM3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 10 + bit_size: 1 + - name: LPTIM4LPEN + description: LPTIM4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 11 + bit_size: 1 + - name: LPTIM5LPEN + description: LPTIM5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + - name: COMP12LPEN + description: COMP1/2 peripheral clock enable during CSleep mode + bit_offset: 14 + bit_size: 1 + - name: VREFLPEN + description: VREF peripheral clock enable during CSleep mode + bit_offset: 15 + bit_size: 1 + - name: RTCAPBLPEN + description: RTC APB Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: SAI4LPEN + description: SAI4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: DTSLPEN + description: Digital temperature sensor block enable during CSleep Mode + bit_offset: 26 + bit_size: 1 fieldset/C1_RSR: description: RCC Reset Status Register fields: - - name: RMVF - description: Remove reset flag - bit_offset: 16 - bit_size: 1 - - name: CPURSTF - description: CPU reset flag - bit_offset: 17 - bit_size: 1 - - name: D1RSTF - description: D1 domain power switch reset flag - bit_offset: 19 - bit_size: 1 - - name: D2RSTF - description: D2 domain power switch reset flag - bit_offset: 20 - bit_size: 1 - - name: BORRSTF - description: BOR reset flag - bit_offset: 21 - bit_size: 1 - - name: PINRSTF - description: Pin reset flag (NRST) - bit_offset: 22 - bit_size: 1 - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 23 - bit_size: 1 - - name: SFTRSTF - description: System reset from CPU reset flag - bit_offset: 24 - bit_size: 1 - - name: IWDG1RSTF - description: Independent Watchdog reset flag - bit_offset: 26 - bit_size: 1 - - name: WWDG1RSTF - description: Window Watchdog reset flag - bit_offset: 28 - bit_size: 1 - - name: LPWRRSTF - description: Reset due to illegal D1 DStandby or CPU CStop flag - bit_offset: 30 - bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 16 + bit_size: 1 + - name: CPURSTF + description: CPU reset flag + bit_offset: 17 + bit_size: 1 + - name: D1RSTF + description: D1 domain power switch reset flag + bit_offset: 19 + bit_size: 1 + - name: D2RSTF + description: D2 domain power switch reset flag + bit_offset: 20 + bit_size: 1 + - name: BORRSTF + description: BOR reset flag + bit_offset: 21 + bit_size: 1 + - name: PINRSTF + description: Pin reset flag (NRST) + bit_offset: 22 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 23 + bit_size: 1 + - name: SFTRSTF + description: System reset from CPU reset flag + bit_offset: 24 + bit_size: 1 + - name: IWDG1RSTF + description: Independent Watchdog reset flag + bit_offset: 26 + bit_size: 1 + - name: WWDG1RSTF + description: Window Watchdog reset flag + bit_offset: 28 + bit_size: 1 + - name: LPWRRSTF + description: Reset due to illegal D1 DStandby or CPU CStop flag + bit_offset: 30 + bit_size: 1 fieldset/CFGR: description: RCC Clock Configuration Register fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 3 - enum: SW - - name: SWS - description: System clock switch status - bit_offset: 3 - bit_size: 3 - enum: SWS - - name: STOPWUCK - description: System clock selection after a wake up from system Stop - bit_offset: 6 - bit_size: 1 - enum: STOPWUCK - - name: STOPKERWUCK - description: Kernel clock selection after a wake up from system Stop - bit_offset: 7 - bit_size: 1 - enum: STOPWUCK - - name: RTCPRE - description: HSE division factor for RTC clock - bit_offset: 8 - bit_size: 6 - - name: HRTIMSEL - description: High Resolution Timer clock prescaler selection - bit_offset: 14 - bit_size: 1 - enum: HRTIMSEL - - name: TIMPRE - description: Timers clocks prescaler selection - bit_offset: 15 - bit_size: 1 - enum: TIMPRE - - name: MCO1PRE - description: MCO1 prescaler - bit_offset: 18 - bit_size: 4 - - name: MCO1 - description: Micro-controller clock output 1 - bit_offset: 22 - bit_size: 3 - enum: MCO1 - - name: MCO2PRE - description: MCO2 prescaler - bit_offset: 25 - bit_size: 4 - - name: MCO2 - description: Micro-controller clock output 2 - bit_offset: 29 - bit_size: 3 - enum: MCO2 + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 3 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 3 + bit_size: 3 + enum: SW + - name: STOPWUCK + description: System clock selection after a wake up from system Stop + bit_offset: 6 + bit_size: 1 + enum: STOPWUCK + - name: STOPKERWUCK + description: Kernel clock selection after a wake up from system Stop + bit_offset: 7 + bit_size: 1 + enum: STOPWUCK + - name: RTCPRE + description: HSE division factor for RTC clock + bit_offset: 8 + bit_size: 6 + - name: HRTIMSEL + description: High Resolution Timer clock prescaler selection + bit_offset: 14 + bit_size: 1 + enum: HRTIMSEL + - name: TIMPRE + description: Timers clocks prescaler selection + bit_offset: 15 + bit_size: 1 + enum: TIMPRE + - name: MCO1PRE + description: MCO1 prescaler + bit_offset: 18 + bit_size: 4 + - name: MCO1 + description: Micro-controller clock output 1 + bit_offset: 22 + bit_size: 3 + enum: MCO1 + - name: MCO2PRE + description: MCO2 prescaler + bit_offset: 25 + bit_size: 4 + - name: MCO2 + description: Micro-controller clock output 2 + bit_offset: 29 + bit_size: 3 + enum: MCO2 fieldset/CICR: description: RCC Clock Source Interrupt Clear Register fields: - - name: LSIRDYC - description: LSI ready Interrupt Clear - bit_offset: 0 - bit_size: 1 - - name: LSERDYC - description: LSE ready Interrupt Clear - bit_offset: 1 - bit_size: 1 - - name: HSIRDYC - description: HSI ready Interrupt Clear - bit_offset: 2 - bit_size: 1 - - name: HSERDYC - description: HSE ready Interrupt Clear - bit_offset: 3 - bit_size: 1 - - name: HSE_ready_Interrupt_Clear - description: CSI ready Interrupt Clear - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYC - description: RC48 ready Interrupt Clear - bit_offset: 5 - bit_size: 1 - - name: PLLRDYC - description: PLL1 ready Interrupt Clear - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: LSECSSC - description: LSE clock security system Interrupt Clear - bit_offset: 9 - bit_size: 1 - - name: HSECSSC - description: HSE clock security system Interrupt Clear - bit_offset: 10 - bit_size: 1 + - name: LSIRDYC + description: LSI ready Interrupt Clear + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: LSE ready Interrupt Clear + bit_offset: 1 + bit_size: 1 + - name: HSIRDYC + description: HSI ready Interrupt Clear + bit_offset: 2 + bit_size: 1 + - name: HSERDYC + description: HSE ready Interrupt Clear + bit_offset: 3 + bit_size: 1 + - name: HSE_ready_Interrupt_Clear + description: CSI ready Interrupt Clear + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYC + description: RC48 ready Interrupt Clear + bit_offset: 5 + bit_size: 1 + - name: PLLRDYC + description: PLL1 ready Interrupt Clear + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: LSECSSC + description: LSE clock security system Interrupt Clear + bit_offset: 9 + bit_size: 1 + - name: HSECSSC + description: HSE clock security system Interrupt Clear + bit_offset: 10 + bit_size: 1 fieldset/CIER: description: RCC Clock Source Interrupt Enable Register fields: - - name: LSIRDYIE - description: LSI ready Interrupt Enable - bit_offset: 0 - bit_size: 1 - - name: LSERDYIE - description: LSE ready Interrupt Enable - bit_offset: 1 - bit_size: 1 - - name: HSIRDYIE - description: HSI ready Interrupt Enable - bit_offset: 2 - bit_size: 1 - - name: HSERDYIE - description: HSE ready Interrupt Enable - bit_offset: 3 - bit_size: 1 - - name: CSIRDYIE - description: CSI ready Interrupt Enable - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYIE - description: RC48 ready Interrupt Enable - bit_offset: 5 - bit_size: 1 - - name: PLLRDYIE - description: PLL1 ready Interrupt Enable - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: LSECSSIE - description: LSE clock security system Interrupt Enable - bit_offset: 9 - bit_size: 1 + - name: LSIRDYIE + description: LSI ready Interrupt Enable + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: LSE ready Interrupt Enable + bit_offset: 1 + bit_size: 1 + - name: HSIRDYIE + description: HSI ready Interrupt Enable + bit_offset: 2 + bit_size: 1 + - name: HSERDYIE + description: HSE ready Interrupt Enable + bit_offset: 3 + bit_size: 1 + - name: CSIRDYIE + description: CSI ready Interrupt Enable + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYIE + description: RC48 ready Interrupt Enable + bit_offset: 5 + bit_size: 1 + - name: PLLRDYIE + description: PLL1 ready Interrupt Enable + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: LSECSSIE + description: LSE clock security system Interrupt Enable + bit_offset: 9 + bit_size: 1 fieldset/CIFR: description: RCC Clock Source Interrupt Flag Register fields: - - name: LSIRDYF - description: LSI ready Interrupt Flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE ready Interrupt Flag - bit_offset: 1 - bit_size: 1 - - name: HSIRDYF - description: HSI ready Interrupt Flag - bit_offset: 2 - bit_size: 1 - - name: HSERDYF - description: HSE ready Interrupt Flag - bit_offset: 3 - bit_size: 1 - - name: CSIRDY - description: CSI ready Interrupt Flag - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYF - description: RC48 ready Interrupt Flag - bit_offset: 5 - bit_size: 1 - - name: PLLRDYF - description: PLL1 ready Interrupt Flag - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: LSECSSF - description: LSE clock security system Interrupt Flag - bit_offset: 9 - bit_size: 1 - - name: HSECSSF - description: HSE clock security system Interrupt Flag - bit_offset: 10 - bit_size: 1 + - name: LSIRDYF + description: LSI ready Interrupt Flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready Interrupt Flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI ready Interrupt Flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE ready Interrupt Flag + bit_offset: 3 + bit_size: 1 + - name: CSIRDY + description: CSI ready Interrupt Flag + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYF + description: RC48 ready Interrupt Flag + bit_offset: 5 + bit_size: 1 + - name: PLLRDYF + description: PLL1 ready Interrupt Flag + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: LSECSSF + description: LSE clock security system Interrupt Flag + bit_offset: 9 + bit_size: 1 + - name: HSECSSF + description: HSE clock security system Interrupt Flag + bit_offset: 10 + bit_size: 1 fieldset/CR: description: clock control register fields: - - name: HSION - description: Internal high-speed clock enable - bit_offset: 0 - bit_size: 1 - - name: HSIKERON - description: High Speed Internal clock enable in Stop mode - bit_offset: 1 - bit_size: 1 - - name: HSIRDY - description: HSI clock ready flag - bit_offset: 2 - bit_size: 1 - - name: HSIDIV - description: HSI clock divider - bit_offset: 3 - bit_size: 2 - enum: HSIDIV - - name: HSIDIVF - description: HSI divider flag - bit_offset: 5 - bit_size: 1 - - name: CSION - description: CSI clock enable - bit_offset: 7 - bit_size: 1 - - name: CSIRDY - description: CSI clock ready flag - bit_offset: 8 - bit_size: 1 - - name: CSIKERON - description: CSI clock enable in Stop mode - bit_offset: 9 - bit_size: 1 - - name: HSI48ON - description: RC48 clock enable - bit_offset: 12 - bit_size: 1 - - name: HSI48RDY - description: RC48 clock ready flag - bit_offset: 13 - bit_size: 1 - - name: D1CKRDY - description: D1 domain clocks ready flag - bit_offset: 14 - bit_size: 1 - - name: D2CKRDY - description: D2 domain clocks ready flag - bit_offset: 15 - bit_size: 1 - - name: HSEON - description: HSE clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: HSE clock bypass - bit_offset: 18 - bit_size: 1 - - name: HSECSSON - description: HSE Clock Security System enable - bit_offset: 19 - bit_size: 1 - - name: PLLON - description: PLL1 enable - bit_offset: 24 - bit_size: 1 - array: - len: 3 - stride: 2 - - name: PLLRDY - description: PLL1 clock ready flag - bit_offset: 25 - bit_size: 1 - array: - len: 3 - stride: 2 + - name: HSION + description: Internal high-speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIKERON + description: High Speed Internal clock enable in Stop mode + bit_offset: 1 + bit_size: 1 + - name: HSIRDY + description: HSI clock ready flag + bit_offset: 2 + bit_size: 1 + - name: HSIDIV + description: HSI clock divider + bit_offset: 3 + bit_size: 2 + enum: HSIDIV + - name: HSIDIVF + description: HSI divider flag + bit_offset: 5 + bit_size: 1 + - name: CSION + description: CSI clock enable + bit_offset: 7 + bit_size: 1 + - name: CSIRDY + description: CSI clock ready flag + bit_offset: 8 + bit_size: 1 + - name: CSIKERON + description: CSI clock enable in Stop mode + bit_offset: 9 + bit_size: 1 + - name: HSI48ON + description: RC48 clock enable + bit_offset: 12 + bit_size: 1 + - name: HSI48RDY + description: RC48 clock ready flag + bit_offset: 13 + bit_size: 1 + - name: D1CKRDY + description: D1 domain clocks ready flag + bit_offset: 14 + bit_size: 1 + - name: D2CKRDY + description: D2 domain clocks ready flag + bit_offset: 15 + bit_size: 1 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: HSE clock bypass + bit_offset: 18 + bit_size: 1 + - name: HSECSSON + description: HSE Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL1 enable + bit_offset: 24 + bit_size: 1 + array: + len: 3 + stride: 2 + - name: PLLRDY + description: PLL1 clock ready flag + bit_offset: 25 + bit_size: 1 + array: + len: 3 + stride: 2 fieldset/CRRCR: description: RCC Clock Recovery RC Register fields: - - name: HSI48CAL - description: Internal RC 48 MHz clock calibration - bit_offset: 0 - bit_size: 10 + - name: HSI48CAL + description: Internal RC 48 MHz clock calibration + bit_offset: 0 + bit_size: 10 fieldset/CSICFGR: description: RCC CSI configuration register fields: - - name: CSICAL - description: CSI clock calibration - bit_offset: 0 - bit_size: 9 - - name: CSITRIM - description: CSI clock trimming - bit_offset: 24 - bit_size: 6 + - name: CSICAL + description: CSI clock calibration + bit_offset: 0 + bit_size: 9 + - name: CSITRIM + description: CSI clock trimming + bit_offset: 24 + bit_size: 6 fieldset/CSR: description: RCC Clock Control and Status Register fields: - - name: LSION - description: LSI oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: LSI oscillator ready - bit_offset: 1 - bit_size: 1 + - name: LSION + description: LSI oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: LSI oscillator ready + bit_offset: 1 + bit_size: 1 fieldset/D1CCIPR: description: RCC Domain 1 Kernel Clock Configuration Register fields: - - name: FMCSEL - description: FMC kernel clock source selection - bit_offset: 0 - bit_size: 2 - enum: FMCSEL - - name: QSPISEL - description: QUADSPI kernel clock source selection - bit_offset: 4 - bit_size: 2 - enum: FMCSEL - - name: DSISEL - description: kernel clock source selection - bit_offset: 8 - bit_size: 1 - - name: SDMMCSEL - description: SDMMC kernel clock source selection - bit_offset: 16 - bit_size: 1 - enum: SDMMCSEL - - name: CKPERSEL - description: per_ck clock source selection - bit_offset: 28 - bit_size: 2 - enum: CKPERSEL + - name: FMCSEL + description: FMC kernel clock source selection + bit_offset: 0 + bit_size: 2 + enum: FMCSEL + - name: QSPISEL + description: QUADSPI kernel clock source selection + bit_offset: 4 + bit_size: 2 + enum: FMCSEL + - name: DSISEL + description: kernel clock source selection + bit_offset: 8 + bit_size: 1 + - name: SDMMCSEL + description: SDMMC kernel clock source selection + bit_offset: 16 + bit_size: 1 + enum: SDMMCSEL + - name: CKPERSEL + description: per_ck clock source selection + bit_offset: 28 + bit_size: 2 + enum: CKPERSEL fieldset/D1CFGR: description: RCC Domain 1 Clock Configuration Register fields: - - name: HPRE - description: D1 domain AHB prescaler - bit_offset: 0 - bit_size: 4 - enum: HPRE - - name: D1PPRE - description: D1 domain APB3 prescaler - bit_offset: 4 - bit_size: 3 - enum: DPPRE - - name: D1CPRE - description: D1 domain Core prescaler - bit_offset: 8 - bit_size: 4 - enum: HPRE + - name: HPRE + description: D1 domain AHB prescaler + bit_offset: 0 + bit_size: 4 + enum: HPRE + - name: D1PPRE + description: D1 domain APB3 prescaler + bit_offset: 4 + bit_size: 3 + enum: PPRE + - name: D1CPRE + description: D1 domain Core prescaler + bit_offset: 8 + bit_size: 4 + enum: HPRE fieldset/D2CCIP1R: description: RCC Domain 2 Kernel Clock Configuration Register fields: - - name: SAI1SEL - description: SAI1 and DFSDM1 kernel Aclk clock source selection - bit_offset: 0 - bit_size: 3 - enum: SAISEL - - name: SAI23SEL - description: SAI2 and SAI3 kernel clock source selection - bit_offset: 6 - bit_size: 3 - enum: SAISEL - - name: SPI123SEL - description: "SPI/I2S1,2 and 3 kernel clock source selection" - bit_offset: 12 - bit_size: 3 - enum: SAISEL - - name: SPI45SEL - description: SPI4 and 5 kernel clock source selection - bit_offset: 16 - bit_size: 3 - enum: SPI45SEL - - name: SPDIFRXSEL - description: SPDIFRX kernel clock source selection - bit_offset: 20 - bit_size: 2 - enum: SPDIFRXSEL - - name: DFSDM1SEL - description: DFSDM1 kernel Clk clock source selection - bit_offset: 24 - bit_size: 1 - enum: DFSDMSEL - - name: FDCANSEL - description: FDCAN kernel clock source selection - bit_offset: 28 - bit_size: 2 - enum: FDCANSEL - - name: SWPSEL - description: SWPMI kernel clock source selection - bit_offset: 31 - bit_size: 1 - enum: SWPSEL + - name: SAI1SEL + description: SAI1 and DFSDM1 kernel Aclk clock source selection + bit_offset: 0 + bit_size: 3 + enum: SAISEL + - name: SAI23SEL + description: SAI2 and SAI3 kernel clock source selection + bit_offset: 6 + bit_size: 3 + enum: SAISEL + - name: SPI123SEL + description: SPI/I2S1,2 and 3 kernel clock source selection + bit_offset: 12 + bit_size: 3 + enum: SAISEL + - name: SPI45SEL + description: SPI4 and 5 kernel clock source selection + bit_offset: 16 + bit_size: 3 + enum: SPI45SEL + - name: SPDIFRXSEL + description: SPDIFRX kernel clock source selection + bit_offset: 20 + bit_size: 2 + enum: SPDIFRXSEL + - name: DFSDM1SEL + description: DFSDM1 kernel Clk clock source selection + bit_offset: 24 + bit_size: 1 + enum: DFSDMSEL + - name: FDCANSEL + description: FDCAN kernel clock source selection + bit_offset: 28 + bit_size: 2 + enum: FDCANSEL + - name: SWPSEL + description: SWPMI kernel clock source selection + bit_offset: 31 + bit_size: 1 + enum: SWPSEL fieldset/D2CCIP2R: description: RCC Domain 2 Kernel Clock Configuration Register fields: - - name: USART234578SEL - description: "USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection" - bit_offset: 0 - bit_size: 3 - enum: USART234578SEL - - name: USART16910SEL - description: "USART1, 6, 9 and 10 kernel clock source selection" - bit_offset: 3 - bit_size: 3 - enum: USART16910SEL - - name: RNGSEL - description: RNG kernel clock source selection - bit_offset: 8 - bit_size: 2 - enum: RNGSEL - - name: I2C1235SEL - description: "I2C1,2,3 kernel clock source selection" - bit_offset: 12 - bit_size: 2 - enum: I2C1235SEL - - name: USBSEL - description: USBOTG 1 and 2 kernel clock source selection - bit_offset: 20 - bit_size: 2 - enum: USBSEL - - name: CECSEL - description: HDMI-CEC kernel clock source selection - bit_offset: 22 - bit_size: 2 - enum: CECSEL - - name: LPTIM1SEL - description: LPTIM1 kernel clock source selection - bit_offset: 28 - bit_size: 3 - enum: LPTIM1SEL + - name: USART234578SEL + description: USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection + bit_offset: 0 + bit_size: 3 + enum: USART234578SEL + - name: USART16910SEL + description: USART1, 6, 9 and 10 kernel clock source selection + bit_offset: 3 + bit_size: 3 + enum: USART16910SEL + - name: RNGSEL + description: RNG kernel clock source selection + bit_offset: 8 + bit_size: 2 + enum: RNGSEL + - name: I2C1235SEL + description: I2C1,2,3 kernel clock source selection + bit_offset: 12 + bit_size: 2 + enum: I2C1235SEL + - name: USBSEL + description: USBOTG 1 and 2 kernel clock source selection + bit_offset: 20 + bit_size: 2 + enum: USBSEL + - name: CECSEL + description: HDMI-CEC kernel clock source selection + bit_offset: 22 + bit_size: 2 + enum: CECSEL + - name: LPTIM1SEL + description: LPTIM1 kernel clock source selection + bit_offset: 28 + bit_size: 3 + enum: LPTIM1SEL fieldset/D2CFGR: description: RCC Domain 2 Clock Configuration Register fields: - - name: D2PPRE1 - description: D2 domain APB1 prescaler - bit_offset: 4 - bit_size: 3 - enum: DPPRE - - name: D2PPRE2 - description: D2 domain APB2 prescaler - bit_offset: 8 - bit_size: 3 - enum: DPPRE + - name: D2PPRE1 + description: D2 domain APB1 prescaler + bit_offset: 4 + bit_size: 3 + enum: PPRE + - name: D2PPRE2 + description: D2 domain APB2 prescaler + bit_offset: 8 + bit_size: 3 + enum: PPRE fieldset/D3AMR: description: RCC D3 Autonomous mode Register fields: - - name: BDMAAMEN - description: BDMA and DMAMUX Autonomous mode enable - bit_offset: 0 - bit_size: 1 - - name: LPUART1AMEN - description: LPUART1 Autonomous mode enable - bit_offset: 3 - bit_size: 1 - - name: SPI6AMEN - description: SPI6 Autonomous mode enable - bit_offset: 5 - bit_size: 1 - - name: I2C4AMEN - description: I2C4 Autonomous mode enable - bit_offset: 7 - bit_size: 1 - - name: LPTIM2AMEN - description: LPTIM2 Autonomous mode enable - bit_offset: 9 - bit_size: 1 - - name: LPTIM3AMEN - description: LPTIM3 Autonomous mode enable - bit_offset: 10 - bit_size: 1 - - name: LPTIM4AMEN - description: LPTIM4 Autonomous mode enable - bit_offset: 11 - bit_size: 1 - - name: LPTIM5AMEN - description: LPTIM5 Autonomous mode enable - bit_offset: 12 - bit_size: 1 - - name: DAC2AMEN - description: DAC2 (containing one converter) Autonomous mode enable - bit_offset: 13 - bit_size: 1 - - name: COMP12AMEN - description: COMP12 Autonomous mode enable - bit_offset: 14 - bit_size: 1 - - name: VREFAMEN - description: VREF Autonomous mode enable - bit_offset: 15 - bit_size: 1 - - name: RTCAMEN - description: RTC Autonomous mode enable - bit_offset: 16 - bit_size: 1 - - name: CRCAMEN - description: CRC Autonomous mode enable - bit_offset: 19 - bit_size: 1 - - name: SAI4AMEN - description: SAI4 Autonomous mode enable - bit_offset: 21 - bit_size: 1 - - name: ADC3AMEN - description: ADC3 Autonomous mode enable - bit_offset: 24 - bit_size: 1 - - name: DTSAMEN - description: Digital temperature sensor Autonomous mode enable - bit_offset: 26 - bit_size: 1 - - name: BKPSRAMAMEN - description: Backup RAM Autonomous mode enable - bit_offset: 28 - bit_size: 1 - - name: SRAM4AMEN - description: SRAM4 Autonomous mode enable - bit_offset: 29 - bit_size: 1 + - name: BDMAAMEN + description: BDMA and DMAMUX Autonomous mode enable + bit_offset: 0 + bit_size: 1 + - name: LPUART1AMEN + description: LPUART1 Autonomous mode enable + bit_offset: 3 + bit_size: 1 + - name: SPI6AMEN + description: SPI6 Autonomous mode enable + bit_offset: 5 + bit_size: 1 + - name: I2C4AMEN + description: I2C4 Autonomous mode enable + bit_offset: 7 + bit_size: 1 + - name: LPTIM2AMEN + description: LPTIM2 Autonomous mode enable + bit_offset: 9 + bit_size: 1 + - name: LPTIM3AMEN + description: LPTIM3 Autonomous mode enable + bit_offset: 10 + bit_size: 1 + - name: LPTIM4AMEN + description: LPTIM4 Autonomous mode enable + bit_offset: 11 + bit_size: 1 + - name: LPTIM5AMEN + description: LPTIM5 Autonomous mode enable + bit_offset: 12 + bit_size: 1 + - name: DAC2AMEN + description: DAC2 (containing one converter) Autonomous mode enable + bit_offset: 13 + bit_size: 1 + - name: COMP12AMEN + description: COMP12 Autonomous mode enable + bit_offset: 14 + bit_size: 1 + - name: VREFAMEN + description: VREF Autonomous mode enable + bit_offset: 15 + bit_size: 1 + - name: RTCAMEN + description: RTC Autonomous mode enable + bit_offset: 16 + bit_size: 1 + - name: CRCAMEN + description: CRC Autonomous mode enable + bit_offset: 19 + bit_size: 1 + - name: SAI4AMEN + description: SAI4 Autonomous mode enable + bit_offset: 21 + bit_size: 1 + - name: ADC3AMEN + description: ADC3 Autonomous mode enable + bit_offset: 24 + bit_size: 1 + - name: DTSAMEN + description: Digital temperature sensor Autonomous mode enable + bit_offset: 26 + bit_size: 1 + - name: BKPSRAMAMEN + description: Backup RAM Autonomous mode enable + bit_offset: 28 + bit_size: 1 + - name: SRAM4AMEN + description: SRAM4 Autonomous mode enable + bit_offset: 29 + bit_size: 1 fieldset/D3CCIPR: description: RCC Domain 3 Kernel Clock Configuration Register fields: - - name: LPUART1SEL - description: LPUART1 kernel clock source selection - bit_offset: 0 - bit_size: 3 - enum: LPUARTSEL - - name: I2C4SEL - description: I2C4 kernel clock source selection - bit_offset: 8 - bit_size: 2 - enum: I2C4SEL - - name: LPTIM2SEL - description: LPTIM2 kernel clock source selection - bit_offset: 10 - bit_size: 3 - enum: LPTIM2SEL - - name: LPTIM345SEL - description: "LPTIM3,4,5 kernel clock source selection" - bit_offset: 13 - bit_size: 3 - enum: LPTIM2SEL - - name: ADCSEL - description: SAR ADC kernel clock source selection - bit_offset: 16 - bit_size: 2 - enum: ADCSEL - - name: SAI4ASEL - description: Sub-Block A of SAI4 kernel clock source selection - bit_offset: 21 - bit_size: 3 - enum: SAIASEL - - name: SAI4BSEL - description: Sub-Block B of SAI4 kernel clock source selection - bit_offset: 24 - bit_size: 3 - enum: SAIASEL - - name: DFSDM2SEL - description: DFSDM2 kernel clock source selection - bit_offset: 27 - bit_size: 1 - - name: SPI6SEL - description: SPI6 kernel clock source selection - bit_offset: 28 - bit_size: 3 - enum: SPI6SEL + - name: LPUART1SEL + description: LPUART1 kernel clock source selection + bit_offset: 0 + bit_size: 3 + enum: LPUARTSEL + - name: I2C4SEL + description: I2C4 kernel clock source selection + bit_offset: 8 + bit_size: 2 + enum: I2C4SEL + - name: LPTIM2SEL + description: LPTIM2 kernel clock source selection + bit_offset: 10 + bit_size: 3 + enum: LPTIM2SEL + - name: LPTIM345SEL + description: LPTIM3,4,5 kernel clock source selection + bit_offset: 13 + bit_size: 3 + enum: LPTIM2SEL + - name: ADCSEL + description: SAR ADC kernel clock source selection + bit_offset: 16 + bit_size: 2 + enum: ADCSEL + - name: SAI4ASEL + description: Sub-Block A of SAI4 kernel clock source selection + bit_offset: 21 + bit_size: 3 + enum: SAIASEL + - name: SAI4BSEL + description: Sub-Block B of SAI4 kernel clock source selection + bit_offset: 24 + bit_size: 3 + enum: SAIASEL + - name: DFSDM2SEL + description: DFSDM2 kernel clock source selection + bit_offset: 27 + bit_size: 1 + - name: SPI6SEL + description: SPI6 kernel clock source selection + bit_offset: 28 + bit_size: 3 + enum: SPI6SEL fieldset/D3CFGR: description: RCC Domain 3 Clock Configuration Register fields: - - name: D3PPRE - description: D3 domain APB4 prescaler - bit_offset: 4 - bit_size: 3 - enum: DPPRE + - name: D3PPRE + description: D3 domain APB4 prescaler + bit_offset: 4 + bit_size: 3 + enum: PPRE fieldset/GCR: description: Global Control Register fields: - - name: WW1RSC - description: WWDG1 reset scope control - bit_offset: 0 - bit_size: 1 - - name: WW2RSC - description: WWDG2 reset scope control - bit_offset: 1 - bit_size: 1 - - name: BOOT_C1 - description: Force allow CPU1 to boot - bit_offset: 2 - bit_size: 1 - - name: BOOT_C2 - description: Force allow CPU2 to boot - bit_offset: 3 - bit_size: 1 + - name: WW1RSC + description: WWDG1 reset scope control + bit_offset: 0 + bit_size: 1 + - name: WW2RSC + description: WWDG2 reset scope control + bit_offset: 1 + bit_size: 1 + - name: BOOT_C1 + description: Force allow CPU1 to boot + bit_offset: 2 + bit_size: 1 + - name: BOOT_C2 + description: Force allow CPU2 to boot + bit_offset: 3 + bit_size: 1 fieldset/HSICFGR: description: RCC HSI configuration register fields: - - name: HSICAL - description: HSI clock calibration - bit_offset: 0 - bit_size: 12 - - name: HSITRIM - description: HSI clock trimming - bit_offset: 24 - bit_size: 7 + - name: HSICAL + description: HSI clock calibration + bit_offset: 0 + bit_size: 12 + - name: HSITRIM + description: HSI clock trimming + bit_offset: 24 + bit_size: 7 fieldset/ICSCR: description: RCC Internal Clock Source Calibration Register fields: - - name: HSICAL - description: HSI clock calibration - bit_offset: 0 - bit_size: 12 - - name: HSITRIM - description: HSI clock trimming - bit_offset: 12 - bit_size: 6 - - name: CSICAL - description: CSI clock calibration - bit_offset: 18 - bit_size: 8 - - name: CSITRIM - description: CSI clock trimming - bit_offset: 26 - bit_size: 5 -fieldset/PLL1DIVR: - description: RCC PLL1 Dividers Configuration Register - fields: - - name: DIVN1 - description: Multiplication factor for PLL1 VCO - bit_offset: 0 - bit_size: 9 - - name: DIVP1 - description: PLL1 DIVP division factor - bit_offset: 9 - bit_size: 7 - enum: DIVP - - name: DIVQ1 - description: PLL1 DIVQ division factor - bit_offset: 16 - bit_size: 7 - - name: DIVR1 - description: PLL1 DIVR division factor - bit_offset: 24 - bit_size: 7 -fieldset/PLL1FRACR: - description: RCC PLL1 Fractional Divider Register - fields: - - name: FRACN1 - description: Fractional part of the multiplication factor for PLL1 VCO - bit_offset: 3 - bit_size: 13 -fieldset/PLL2DIVR: - description: RCC PLL2 Dividers Configuration Register - fields: - - name: DIVN2 - description: Multiplication factor for PLL1 VCO - bit_offset: 0 - bit_size: 9 - - name: DIVP2 - description: PLL1 DIVP division factor - bit_offset: 9 - bit_size: 7 - - name: DIVQ2 - description: PLL1 DIVQ division factor - bit_offset: 16 - bit_size: 7 - - name: DIVR2 - description: PLL1 DIVR division factor - bit_offset: 24 - bit_size: 7 -fieldset/PLL2FRACR: - description: RCC PLL2 Fractional Divider Register - fields: - - name: FRACN2 - description: Fractional part of the multiplication factor for PLL VCO - bit_offset: 3 - bit_size: 13 -fieldset/PLL3DIVR: - description: RCC PLL3 Dividers Configuration Register - fields: - - name: DIVN3 - description: Multiplication factor for PLL1 VCO - bit_offset: 0 - bit_size: 9 - - name: DIVP3 - description: PLL DIVP division factor - bit_offset: 9 - bit_size: 7 - - name: DIVQ3 - description: PLL DIVQ division factor - bit_offset: 16 - bit_size: 7 - - name: DIVR3 - description: PLL DIVR division factor - bit_offset: 24 - bit_size: 7 -fieldset/PLL3FRACR: - description: RCC PLL3 Fractional Divider Register - fields: - - name: FRACN3 - description: Fractional part of the multiplication factor for PLL3 VCO - bit_offset: 3 - bit_size: 13 + - name: HSICAL + description: HSI clock calibration + bit_offset: 0 + bit_size: 12 + - name: HSITRIM + description: HSI clock trimming + bit_offset: 12 + bit_size: 6 + - name: CSICAL + description: CSI clock calibration + bit_offset: 18 + bit_size: 8 + - name: CSITRIM + description: CSI clock trimming + bit_offset: 26 + bit_size: 5 fieldset/PLLCFGR: description: RCC PLLs Configuration Register fields: - - name: PLLFRACEN - description: PLL1 fractional latch enable - bit_offset: 0 - bit_size: 1 - array: - len: 3 - stride: 4 - - name: PLLVCOSEL - description: PLL1 VCO selection - bit_offset: 1 - bit_size: 1 - array: - len: 3 - stride: 4 - enum: PLLVCOSEL - - name: PLLRGE - description: PLL1 input frequency range - bit_offset: 2 - bit_size: 2 - array: - len: 3 - stride: 4 - enum: PLLRGE - - name: DIVPEN - description: PLL1 DIVP divider output enable - bit_offset: 16 - bit_size: 1 - array: - len: 3 - stride: 3 - - name: DIVQEN - description: PLL1 DIVQ divider output enable - bit_offset: 17 - bit_size: 1 - array: - len: 3 - stride: 3 - - name: DIVREN - description: PLL1 DIVR divider output enable - bit_offset: 18 - bit_size: 1 - array: - len: 3 - stride: 3 + - name: PLLFRACEN + description: PLL1 fractional latch enable + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 4 + - name: PLLVCOSEL + description: PLL1 VCO selection + bit_offset: 1 + bit_size: 1 + array: + len: 3 + stride: 4 + enum: PLLVCOSEL + - name: PLLRGE + description: PLL1 input frequency range + bit_offset: 2 + bit_size: 2 + array: + len: 3 + stride: 4 + enum: PLLRGE + - name: DIVPEN + description: PLL1 DIVP divider output enable + bit_offset: 16 + bit_size: 1 + array: + len: 3 + stride: 3 + - name: DIVQEN + description: PLL1 DIVQ divider output enable + bit_offset: 17 + bit_size: 1 + array: + len: 3 + stride: 3 + - name: DIVREN + description: PLL1 DIVR divider output enable + bit_offset: 18 + bit_size: 1 + array: + len: 3 + stride: 3 fieldset/PLLCKSELR: description: RCC PLLs Clock Source Selection Register fields: - - name: PLLSRC - description: DIVMx and PLLs clock source selection - bit_offset: 0 - bit_size: 2 - enum: PLLSRC - - name: DIVM - description: Prescaler for PLL1 - bit_offset: 4 - bit_size: 6 - array: - len: 3 - stride: 8 + - name: PLLSRC + description: DIVMx and PLLs clock source selection + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: DIVM + description: Prescaler for PLL1 + bit_offset: 4 + bit_size: 6 + array: + len: 3 + stride: 8 +fieldset/PLLDIVR: + description: RCC PLL1 Dividers Configuration Register + fields: + - name: PLLN + description: Multiplication factor for PLL1 VCO + bit_offset: 0 + bit_size: 9 + - name: PLLP + description: PLL DIVP division factor + bit_offset: 9 + bit_size: 7 + - name: PLLQ + description: PLL DIVQ division factor + bit_offset: 16 + bit_size: 7 + - name: PLLR + description: PLL DIVR division factor + bit_offset: 24 + bit_size: 7 +fieldset/PLLFRACR: + description: RCC PLL Fractional Divider Register + fields: + - name: FRACN + description: Fractional part of the multiplication factor for PLL VCO + bit_offset: 3 + bit_size: 13 fieldset/RSR: description: RCC Reset Status Register fields: - - name: RMVF - description: Remove reset flag - bit_offset: 16 - bit_size: 1 - - name: CPURSTF - description: CPU reset flag - bit_offset: 17 - bit_size: 1 - - name: D1RSTF - description: D1 domain power switch reset flag - bit_offset: 19 - bit_size: 1 - - name: D2RSTF - description: D2 domain power switch reset flag - bit_offset: 20 - bit_size: 1 - - name: BORRSTF - description: BOR reset flag - bit_offset: 21 - bit_size: 1 - - name: PINRSTF - description: Pin reset flag (NRST) - bit_offset: 22 - bit_size: 1 - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 23 - bit_size: 1 - - name: SFTRSTF - description: System reset from CPU reset flag - bit_offset: 24 - bit_size: 1 - - name: IWDG1RSTF - description: Independent Watchdog reset flag - bit_offset: 26 - bit_size: 1 - - name: WWDG1RSTF - description: Window Watchdog reset flag - bit_offset: 28 - bit_size: 1 - - name: LPWRRSTF - description: Reset due to illegal D1 DStandby or CPU CStop flag - bit_offset: 30 - bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 16 + bit_size: 1 + - name: CPURSTF + description: CPU reset flag + bit_offset: 17 + bit_size: 1 + - name: D1RSTF + description: D1 domain power switch reset flag + bit_offset: 19 + bit_size: 1 + - name: D2RSTF + description: D2 domain power switch reset flag + bit_offset: 20 + bit_size: 1 + - name: BORRSTF + description: BOR reset flag + bit_offset: 21 + bit_size: 1 + - name: PINRSTF + description: Pin reset flag (NRST) + bit_offset: 22 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 23 + bit_size: 1 + - name: SFTRSTF + description: System reset from CPU reset flag + bit_offset: 24 + bit_size: 1 + - name: IWDG1RSTF + description: Independent Watchdog reset flag + bit_offset: 26 + bit_size: 1 + - name: WWDG1RSTF + description: Window Watchdog reset flag + bit_offset: 28 + bit_size: 1 + - name: LPWRRSTF + description: Reset due to illegal D1 DStandby or CPU CStop flag + bit_offset: 30 + bit_size: 1 enum/ADCSEL: bit_size: 2 variants: - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 0 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 1 - - name: PER - description: PER selected as peripheral clock - value: 2 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: PER + description: PER selected as peripheral clock + value: 2 enum/CECSEL: bit_size: 2 variants: - - name: LSE - description: LSE selected as peripheral clock - value: 0 - - name: LSI - description: LSI selected as peripheral clock - value: 1 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 2 + - name: LSE + description: LSE selected as peripheral clock + value: 0 + - name: LSI + description: LSI selected as peripheral clock + value: 1 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 2 enum/CKPERSEL: bit_size: 2 variants: - - name: HSI - description: HSI selected as peripheral clock - value: 0 - - name: CSI - description: CSI selected as peripheral clock - value: 1 - - name: HSE - description: HSE selected as peripheral clock - value: 2 + - name: HSI + description: HSI selected as peripheral clock + value: 0 + - name: CSI + description: CSI selected as peripheral clock + value: 1 + - name: HSE + description: HSE selected as peripheral clock + value: 2 enum/DFSDMSEL: bit_size: 1 variants: - - name: RCC_PCLK2 - description: rcc_pclk2 selected as peripheral clock - value: 0 - - name: SYS - description: System clock selected as peripheral clock - value: 1 -enum/DIVP: - bit_size: 7 - variants: - - name: Div1 - description: pll_p_ck = vco_ck - value: 0 - - name: Div2 - description: pll_p_ck = vco_ck / 2 - value: 1 - - name: Div4 - description: pll_p_ck = vco_ck / 4 - value: 3 - - name: Div6 - description: pll_p_ck = vco_ck / 6 - value: 5 - - name: Div8 - description: pll_p_ck = vco_ck / 8 - value: 7 - - name: Div10 - description: pll_p_ck = vco_ck / 10 - value: 9 - - name: Div12 - description: pll_p_ck = vco_ck / 12 - value: 11 - - name: Div14 - description: pll_p_ck = vco_ck / 14 - value: 13 - - name: Div16 - description: pll_p_ck = vco_ck / 16 - value: 15 - - name: Div18 - description: pll_p_ck = vco_ck / 18 - value: 17 - - name: Div20 - description: pll_p_ck = vco_ck / 20 - value: 19 - - name: Div22 - description: pll_p_ck = vco_ck / 22 - value: 21 - - name: Div24 - description: pll_p_ck = vco_ck / 24 - value: 23 - - name: Div26 - description: pll_p_ck = vco_ck / 26 - value: 25 - - name: Div28 - description: pll_p_ck = vco_ck / 28 - value: 27 - - name: Div30 - description: pll_p_ck = vco_ck / 30 - value: 29 - - name: Div32 - description: pll_p_ck = vco_ck / 32 - value: 31 - - name: Div34 - description: pll_p_ck = vco_ck / 34 - value: 33 - - name: Div36 - description: pll_p_ck = vco_ck / 36 - value: 35 - - name: Div38 - description: pll_p_ck = vco_ck / 38 - value: 37 - - name: Div40 - description: pll_p_ck = vco_ck / 40 - value: 39 - - name: Div42 - description: pll_p_ck = vco_ck / 42 - value: 41 - - name: Div44 - description: pll_p_ck = vco_ck / 44 - value: 43 - - name: Div46 - description: pll_p_ck = vco_ck / 46 - value: 45 - - name: Div48 - description: pll_p_ck = vco_ck / 48 - value: 47 - - name: Div50 - description: pll_p_ck = vco_ck / 50 - value: 49 - - name: Div52 - description: pll_p_ck = vco_ck / 52 - value: 51 - - name: Div54 - description: pll_p_ck = vco_ck / 54 - value: 53 - - name: Div56 - description: pll_p_ck = vco_ck / 56 - value: 55 - - name: Div58 - description: pll_p_ck = vco_ck / 58 - value: 57 - - name: Div60 - description: pll_p_ck = vco_ck / 60 - value: 59 - - name: Div62 - description: pll_p_ck = vco_ck / 62 - value: 61 - - name: Div64 - description: pll_p_ck = vco_ck / 64 - value: 63 - - name: Div66 - description: pll_p_ck = vco_ck / 66 - value: 65 - - name: Div68 - description: pll_p_ck = vco_ck / 68 - value: 67 - - name: Div70 - description: pll_p_ck = vco_ck / 70 - value: 69 - - name: Div72 - description: pll_p_ck = vco_ck / 72 - value: 71 - - name: Div74 - description: pll_p_ck = vco_ck / 74 - value: 73 - - name: Div76 - description: pll_p_ck = vco_ck / 76 - value: 75 - - name: Div78 - description: pll_p_ck = vco_ck / 78 - value: 77 - - name: Div80 - description: pll_p_ck = vco_ck / 80 - value: 79 - - name: Div82 - description: pll_p_ck = vco_ck / 82 - value: 81 - - name: Div84 - description: pll_p_ck = vco_ck / 84 - value: 83 - - name: Div86 - description: pll_p_ck = vco_ck / 86 - value: 85 - - name: Div88 - description: pll_p_ck = vco_ck / 88 - value: 87 - - name: Div90 - description: pll_p_ck = vco_ck / 90 - value: 89 - - name: Div92 - description: pll_p_ck = vco_ck / 92 - value: 91 - - name: Div94 - description: pll_p_ck = vco_ck / 94 - value: 93 - - name: Div96 - description: pll_p_ck = vco_ck / 96 - value: 95 - - name: Div98 - description: pll_p_ck = vco_ck / 98 - value: 97 - - name: Div100 - description: pll_p_ck = vco_ck / 100 - value: 99 - - name: Div102 - description: pll_p_ck = vco_ck / 102 - value: 101 - - name: Div104 - description: pll_p_ck = vco_ck / 104 - value: 103 - - name: Div106 - description: pll_p_ck = vco_ck / 106 - value: 105 - - name: Div108 - description: pll_p_ck = vco_ck / 108 - value: 107 - - name: Div110 - description: pll_p_ck = vco_ck / 110 - value: 109 - - name: Div112 - description: pll_p_ck = vco_ck / 112 - value: 111 - - name: Div114 - description: pll_p_ck = vco_ck / 114 - value: 113 - - name: Div116 - description: pll_p_ck = vco_ck / 116 - value: 115 - - name: Div118 - description: pll_p_ck = vco_ck / 118 - value: 117 - - name: Div120 - description: pll_p_ck = vco_ck / 120 - value: 119 - - name: Div122 - description: pll_p_ck = vco_ck / 122 - value: 121 - - name: Div124 - description: pll_p_ck = vco_ck / 124 - value: 123 - - name: Div126 - description: pll_p_ck = vco_ck / 126 - value: 125 - - name: Div128 - description: pll_p_ck = vco_ck / 128 - value: 127 -enum/DPPRE: - bit_size: 3 - variants: - - name: Div1 - description: rcc_hclk not divided - value: 0 - - name: Div2 - description: rcc_hclk divided by 2 - value: 4 - - name: Div4 - description: rcc_hclk divided by 4 - value: 5 - - name: Div8 - description: rcc_hclk divided by 8 - value: 6 - - name: Div16 - description: rcc_hclk divided by 16 - value: 7 + - name: RCC_PCLK2 + description: rcc_pclk2 selected as peripheral clock + value: 0 + - name: SYS + description: System clock selected as peripheral clock + value: 1 enum/FDCANSEL: bit_size: 2 variants: - - name: HSE - description: HSE selected as peripheral clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 2 + - name: HSE + description: HSE selected as peripheral clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 2 enum/FMCSEL: bit_size: 2 variants: - - name: RCC_HCLK3 - description: rcc_hclk3 selected as peripheral clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: PLL2_R - description: pll2_r selected as peripheral clock - value: 2 - - name: PER - description: PER selected as peripheral clock - value: 3 + - name: RCC_HCLK3 + description: rcc_hclk3 selected as peripheral clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: PLL2_R + description: pll2_r selected as peripheral clock + value: 2 + - name: PER + description: PER selected as peripheral clock + value: 3 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: sys_ck not divided - value: 0 - - name: Div2 - description: sys_ck divided by 2 - value: 8 - - name: Div4 - description: sys_ck divided by 4 - value: 9 - - name: Div8 - description: sys_ck divided by 8 - value: 10 - - name: Div16 - description: sys_ck divided by 16 - value: 11 - - name: Div64 - description: sys_ck divided by 64 - value: 12 - - name: Div128 - description: sys_ck divided by 128 - value: 13 - - name: Div256 - description: sys_ck divided by 256 - value: 14 - - name: Div512 - description: sys_ck divided by 512 - value: 15 + - name: Div1 + description: sys_ck not divided + value: 0 + - name: Div2 + description: sys_ck divided by 2 + value: 8 + - name: Div4 + description: sys_ck divided by 4 + value: 9 + - name: Div8 + description: sys_ck divided by 8 + value: 10 + - name: Div16 + description: sys_ck divided by 16 + value: 11 + - name: Div64 + description: sys_ck divided by 64 + value: 12 + - name: Div128 + description: sys_ck divided by 128 + value: 13 + - name: Div256 + description: sys_ck divided by 256 + value: 14 + - name: Div512 + description: sys_ck divided by 512 + value: 15 enum/HRTIMSEL: bit_size: 1 variants: - - name: TIMY_KER - description: The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck) - value: 0 - - name: C_CK - description: The HRTIM prescaler clock source is the CPU clock (c_ck) - value: 1 + - name: TIMY_KER + description: The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck) + value: 0 + - name: C_CK + description: The HRTIM prescaler clock source is the CPU clock (c_ck) + value: 1 enum/HSIDIV: bit_size: 2 variants: - - name: Div1 - description: No division - value: 0 - - name: Div2 - description: Division by 2 - value: 1 - - name: Div4 - description: Division by 4 - value: 2 - - name: Div8 - description: Division by 8 - value: 3 + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 enum/I2C1235SEL: bit_size: 2 variants: - - name: RCC_PCLK1 - description: rcc_pclk1 selected as peripheral clock - value: 0 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 1 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 2 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 3 + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 2 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 3 enum/I2C4SEL: bit_size: 2 variants: - - name: RCC_PCLK4 - description: rcc_pclk4 selected as peripheral clock - value: 0 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 1 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 2 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 3 + - name: RCC_PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 2 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 3 enum/LPTIM1SEL: bit_size: 3 variants: - - name: RCC_PCLK1 - description: rcc_pclk1 selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 2 - - name: LSE - description: LSE selected as peripheral clock - value: 3 - - name: LSI - description: LSI selected as peripheral clock - value: 4 - - name: PER - description: PER selected as peripheral clock - value: 5 + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 2 + - name: LSE + description: LSE selected as peripheral clock + value: 3 + - name: LSI + description: LSI selected as peripheral clock + value: 4 + - name: PER + description: PER selected as peripheral clock + value: 5 enum/LPTIM2SEL: bit_size: 3 variants: - - name: RCC_PCLK4 - description: rcc_pclk4 selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 2 - - name: LSE - description: LSE selected as peripheral clock - value: 3 - - name: LSI - description: LSI selected as peripheral clock - value: 4 - - name: PER - description: PER selected as peripheral clock - value: 5 + - name: RCC_PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 2 + - name: LSE + description: LSE selected as peripheral clock + value: 3 + - name: LSI + description: LSI selected as peripheral clock + value: 4 + - name: PER + description: PER selected as peripheral clock + value: 5 enum/LPUARTSEL: bit_size: 3 variants: - - name: RCC_PCLK_D3 - description: rcc_pclk_d3 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: LSE - description: LSE selected as peripheral clock - value: 5 + - name: RCC_PCLK_D3 + description: rcc_pclk_d3 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 enum/LSEDRV: bit_size: 2 variants: - - name: Lowest - description: Lowest LSE oscillator driving capability - value: 0 - - name: MediumLow - description: Medium low LSE oscillator driving capability - value: 1 - - name: MediumHigh - description: Medium high LSE oscillator driving capability - value: 2 - - name: Highest - description: Highest LSE oscillator driving capability - value: 3 + - name: Lowest + description: Lowest LSE oscillator driving capability + value: 0 + - name: MediumLow + description: Medium low LSE oscillator driving capability + value: 1 + - name: MediumHigh + description: Medium high LSE oscillator driving capability + value: 2 + - name: Highest + description: Highest LSE oscillator driving capability + value: 3 enum/MCO1: bit_size: 3 variants: - - name: HSI - description: HSI selected for micro-controller clock output - value: 0 - - name: LSE - description: LSE selected for micro-controller clock output - value: 1 - - name: HSE - description: HSE selected for micro-controller clock output - value: 2 - - name: PLL1_Q - description: pll1_q selected for micro-controller clock output - value: 3 - - name: HSI48 - description: HSI48 selected for micro-controller clock output - value: 4 + - name: HSI + description: HSI selected for micro-controller clock output + value: 0 + - name: LSE + description: LSE selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_Q + description: pll1_q selected for micro-controller clock output + value: 3 + - name: HSI48 + description: HSI48 selected for micro-controller clock output + value: 4 enum/MCO2: bit_size: 3 variants: - - name: SYSCLK - description: System clock selected for micro-controller clock output - value: 0 - - name: PLL2_P - description: pll2_p selected for micro-controller clock output - value: 1 - - name: HSE - description: HSE selected for micro-controller clock output - value: 2 - - name: PLL1_P - description: pll1_p selected for micro-controller clock output - value: 3 - - name: CSI - description: CSI selected for micro-controller clock output - value: 4 - - name: LSI - description: LSI selected for micro-controller clock output - value: 5 + - name: SYSCLK + description: System clock selected for micro-controller clock output + value: 0 + - name: PLL2_P + description: pll2_p selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_P + description: pll1_p selected for micro-controller clock output + value: 3 + - name: CSI + description: CSI selected for micro-controller clock output + value: 4 + - name: LSI + description: LSI selected for micro-controller clock output + value: 5 enum/PLLRGE: bit_size: 2 variants: - - name: Range1 - description: Frequency is between 1 and 2 MHz - value: 0 - - name: Range2 - description: Frequency is between 2 and 4 MHz - value: 1 - - name: Range4 - description: Frequency is between 4 and 8 MHz - value: 2 - - name: Range8 - description: Frequency is between 8 and 16 MHz - value: 3 + - name: Range1 + description: Frequency is between 1 and 2 MHz + value: 0 + - name: Range2 + description: Frequency is between 2 and 4 MHz + value: 1 + - name: Range4 + description: Frequency is between 4 and 8 MHz + value: 2 + - name: Range8 + description: Frequency is between 8 and 16 MHz + value: 3 enum/PLLSRC: bit_size: 2 variants: - - name: HSI - description: HSI selected as PLL clock - value: 0 - - name: CSI - description: CSI selected as PLL clock - value: 1 - - name: HSE - description: HSE selected as PLL clock - value: 2 - - name: None - description: No clock sent to DIVMx dividers and PLLs - value: 3 + - name: HSI + description: HSI selected as PLL clock + value: 0 + - name: CSI + description: CSI selected as PLL clock + value: 1 + - name: HSE + description: HSE selected as PLL clock + value: 2 + - name: None + description: No clock sent to DIVMx dividers and PLLs + value: 3 enum/PLLVCOSEL: bit_size: 1 variants: - - name: WideVCO - description: VCO frequency range 192 to 836 MHz - value: 0 - - name: MediumVCO - description: VCO frequency range 150 to 420 MHz - value: 1 + - name: WideVCO + description: VCO frequency range 192 to 836 MHz + value: 0 + - name: MediumVCO + description: VCO frequency range 150 to 420 MHz + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: rcc_hclk not divided + value: 0 + - name: Div2 + description: rcc_hclk divided by 2 + value: 4 + - name: Div4 + description: rcc_hclk divided by 4 + value: 5 + - name: Div8 + description: rcc_hclk divided by 8 + value: 6 + - name: Div16 + description: rcc_hclk divided by 16 + value: 7 enum/RNGSEL: bit_size: 2 variants: - - name: HSI48 - description: HSI48 selected as peripheral clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: LSE - description: LSE selected as peripheral clock - value: 2 - - name: LSI - description: LSI selected as peripheral clock - value: 3 + - name: HSI48 + description: HSI48 selected as peripheral clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: LSE + description: LSE selected as peripheral clock + value: 2 + - name: LSI + description: LSI selected as peripheral clock + value: 3 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: HSE oscillator clock divided by a prescaler used as RTC clock - value: 3 + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 enum/SAIASEL: bit_size: 3 variants: - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: PLL3_P - description: pll3_p selected as peripheral clock - value: 2 - - name: I2S_CKIN - description: i2s_ckin selected as peripheral clock - value: 3 - - name: PER - description: PER selected as peripheral clock - value: 4 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_P + description: pll3_p selected as peripheral clock + value: 2 + - name: I2S_CKIN + description: i2s_ckin selected as peripheral clock + value: 3 + - name: PER + description: PER selected as peripheral clock + value: 4 enum/SAISEL: bit_size: 3 variants: - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: PLL3_P - description: pll3_p selected as peripheral clock - value: 2 - - name: I2S_CKIN - description: I2S_CKIN selected as peripheral clock - value: 3 - - name: PER - description: PER selected as peripheral clock - value: 4 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_P + description: pll3_p selected as peripheral clock + value: 2 + - name: I2S_CKIN + description: I2S_CKIN selected as peripheral clock + value: 3 + - name: PER + description: PER selected as peripheral clock + value: 4 enum/SDMMCSEL: bit_size: 1 variants: - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 0 - - name: PLL2_R - description: pll2_r selected as peripheral clock - value: 1 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_R + description: pll2_r selected as peripheral clock + value: 1 enum/SPDIFRXSEL: bit_size: 2 variants: - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 0 - - name: PLL2_R - description: pll2_r selected as peripheral clock - value: 1 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_R + description: pll2_r selected as peripheral clock + value: 1 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 enum/SPI45SEL: bit_size: 3 variants: - - name: APB - description: APB clock selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: HSE - description: HSE selected as peripheral clock - value: 5 + - name: APB + description: APB clock selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: HSE + description: HSE selected as peripheral clock + value: 5 enum/SPI6SEL: bit_size: 3 variants: - - name: RCC_PCLK4 - description: rcc_pclk4 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: HSE - description: HSE selected as peripheral clock - value: 5 + - name: RCC_PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: HSE + description: HSE selected as peripheral clock + value: 5 enum/STOPWUCK: bit_size: 1 variants: - - name: HSI - description: HSI selected as wake up clock from system Stop - value: 0 - - name: CSI - description: CSI selected as wake up clock from system Stop - value: 1 + - name: HSI + description: HSI selected as wake up clock from system Stop + value: 0 + - name: CSI + description: CSI selected as wake up clock from system Stop + value: 1 enum/SW: bit_size: 3 variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: CSI - description: CSI selected as system clock - value: 1 - - name: HSE - description: HSE selected as system clock - value: 2 - - name: PLL1 - description: PLL1 selected as system clock - value: 3 + - name: HSI + description: HSI selected as system clock + value: 0 + - name: CSI + description: CSI selected as system clock + value: 1 + - name: HSE + description: HSE selected as system clock + value: 2 + - name: PLL1 + description: PLL1 selected as system clock + value: 3 enum/SWPSEL: bit_size: 1 variants: - - name: PCLK - description: pclk selected as peripheral clock - value: 0 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 1 -enum/SWS: - bit_size: 3 - variants: - - name: HSI - description: HSI oscillator used as system clock - value: 0 - - name: CSI - description: CSI oscillator used as system clock - value: 1 - - name: HSE - description: HSE oscillator used as system clock - value: 2 - - name: PLL1 - description: PLL1 used as system clock - value: 3 + - name: PCLK + description: pclk selected as peripheral clock + value: 0 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 1 enum/TIMPRE: bit_size: 1 variants: - - name: DefaultX2 - description: Timer kernel clock equal to 2x pclk by default - value: 0 - - name: DefaultX4 - description: Timer kernel clock equal to 4x pclk by default - value: 1 + - name: DefaultX2 + description: Timer kernel clock equal to 2x pclk by default + value: 0 + - name: DefaultX4 + description: Timer kernel clock equal to 4x pclk by default + value: 1 enum/USART16910SEL: bit_size: 3 variants: - - name: RCC_PCLK2 - description: rcc_pclk2 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: LSE - description: LSE selected as peripheral clock - value: 5 + - name: RCC_PCLK2 + description: rcc_pclk2 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 enum/USART234578SEL: bit_size: 3 variants: - - name: RCC_PCLK1 - description: rcc_pclk1 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: LSE - description: LSE selected as peripheral clock - value: 5 + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 enum/USBSEL: bit_size: 2 variants: - - name: DISABLE - description: Disable the kernel clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI48 - description: HSI48 selected as peripheral clock - value: 3 + - name: DISABLE + description: Disable the kernel clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI48 + description: HSI48 selected as peripheral clock + value: 3 diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml index ef8723b..27535a0 100644 --- a/data/registers/rcc_h7ab.yaml +++ b/data/registers/rcc_h7ab.yaml @@ -1,3254 +1,2987 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: clock control register - byte_offset: 0 - fieldset: CR - - name: HSICFGR - description: RCC HSI configuration register - byte_offset: 4 - fieldset: HSICFGR - - name: CRRCR - description: RCC Clock Recovery RC Register - byte_offset: 8 - access: Read - fieldset: CRRCR - - name: CSICFGR - description: RCC CSI configuration register - byte_offset: 12 - fieldset: CSICFGR - - name: CFGR - description: RCC Clock Configuration Register - byte_offset: 16 - fieldset: CFGR - - name: D1CFGR - description: RCC Domain 1 Clock Configuration Register - byte_offset: 24 - fieldset: D1CFGR - - name: D2CFGR - description: RCC Domain 2 Clock Configuration Register - byte_offset: 28 - fieldset: D2CFGR - - name: D3CFGR - description: RCC Domain 3 Clock Configuration Register - byte_offset: 32 - fieldset: D3CFGR - - name: PLLCKSELR - description: RCC PLLs Clock Source Selection Register - byte_offset: 40 - fieldset: PLLCKSELR - - name: PLLCFGR - description: RCC PLLs Configuration Register - byte_offset: 44 - fieldset: PLLCFGR - - name: PLLDIVR - description: RCC PLL1 Dividers Configuration Register - array: - len: 3 - stride: 8 - byte_offset: 48 - fieldset: PLL1DIVR - - name: PLLFRACR - description: RCC PLL1 Fractional Divider Register - array: - len: 3 - stride: 8 - byte_offset: 52 - fieldset: PLL1FRACR - - name: D1CCIPR - description: RCC Domain 1 Kernel Clock Configuration Register - byte_offset: 76 - fieldset: D1CCIPR - - name: D2CCIP1R - description: RCC Domain 2 Kernel Clock Configuration Register - byte_offset: 80 - fieldset: D2CCIP1R - - name: D2CCIP2R - description: RCC Domain 2 Kernel Clock Configuration Register - byte_offset: 84 - fieldset: D2CCIP2R - - name: D3CCIPR - description: RCC Domain 3 Kernel Clock Configuration Register - byte_offset: 88 - fieldset: D3CCIPR - - name: CIER - description: RCC Clock Source Interrupt Enable Register - byte_offset: 96 - fieldset: CIER - - name: CIFR - description: RCC Clock Source Interrupt Flag Register - byte_offset: 100 - access: Read - fieldset: CIFR - - name: CICR - description: RCC Clock Source Interrupt Clear Register - byte_offset: 104 - fieldset: CICR - - name: BDCR - description: RCC Backup Domain Control Register - byte_offset: 112 - fieldset: BDCR - - name: CSR - description: RCC Clock Control and Status Register - byte_offset: 116 - fieldset: CSR - - name: AHB3RSTR - description: RCC AHB3 Reset Register - byte_offset: 124 - fieldset: AHB3RSTR - - name: AHB1RSTR - description: RCC AHB1 Peripheral Reset Register - byte_offset: 128 - fieldset: AHB1RSTR - - name: AHB2RSTR - description: RCC AHB2 Peripheral Reset Register - byte_offset: 132 - fieldset: AHB2RSTR - - name: AHB4RSTR - description: RCC AHB4 Peripheral Reset Register - byte_offset: 136 - fieldset: AHB4RSTR - - name: APB3RSTR - description: RCC APB3 Peripheral Reset Register - byte_offset: 140 - fieldset: APB3RSTR - - name: APB1LRSTR - description: RCC APB1 Peripheral Reset Register - byte_offset: 144 - fieldset: APB1LRSTR - - name: APB1HRSTR - description: RCC APB1 Peripheral Reset Register - byte_offset: 148 - fieldset: APB1HRSTR - - name: APB2RSTR - description: RCC APB2 Peripheral Reset Register - byte_offset: 152 - fieldset: APB2RSTR - - name: APB4RSTR - description: RCC APB4 Peripheral Reset Register - byte_offset: 156 - fieldset: APB4RSTR - - name: GCR - description: Global Control Register - byte_offset: 160 - fieldset: GCR - - name: D3AMR - description: RCC D3 Autonomous mode Register - byte_offset: 168 - fieldset: D3AMR - - name: RSR - description: RCC Reset Status Register - byte_offset: 304 - fieldset: RSR - - name: AHB3ENR - description: RCC AHB3 Clock Register - byte_offset: 308 - fieldset: AHB3ENR - - name: AHB1ENR - description: RCC AHB1 Clock Register - byte_offset: 312 - fieldset: AHB1ENR - - name: AHB2ENR - description: RCC AHB2 Clock Register - byte_offset: 316 - fieldset: AHB2ENR - - name: AHB4ENR - description: RCC AHB4 Clock Register - byte_offset: 320 - fieldset: AHB4ENR - - name: APB3ENR - description: RCC APB3 Clock Register - byte_offset: 324 - fieldset: APB3ENR - - name: APB1LENR - description: RCC APB1 Clock Register - byte_offset: 328 - fieldset: APB1LENR - - name: APB1HENR - description: RCC APB1 Clock Register - byte_offset: 332 - fieldset: APB1HENR - - name: APB2ENR - description: RCC APB2 Clock Register - byte_offset: 336 - fieldset: APB2ENR - - name: APB4ENR - description: RCC APB4 Clock Register - byte_offset: 340 - fieldset: APB4ENR - - name: AHB3LPENR - description: RCC AHB3 Sleep Clock Register - byte_offset: 348 - fieldset: AHB3LPENR - - name: AHB1LPENR - description: RCC AHB1 Sleep Clock Register - byte_offset: 352 - fieldset: AHB1LPENR - - name: AHB2LPENR - description: RCC AHB2 Sleep Clock Register - byte_offset: 356 - fieldset: AHB2LPENR - - name: AHB4LPENR - description: RCC AHB4 Sleep Clock Register - byte_offset: 360 - fieldset: AHB4LPENR - - name: APB3LPENR - description: RCC APB3 Sleep Clock Register - byte_offset: 364 - fieldset: APB3LPENR - - name: APB1LLPENR - description: RCC APB1 Low Sleep Clock Register - byte_offset: 368 - fieldset: APB1LLPENR - - name: APB1HLPENR - description: RCC APB1 High Sleep Clock Register - byte_offset: 372 - fieldset: APB1HLPENR - - name: APB2LPENR - description: RCC APB2 Sleep Clock Register - byte_offset: 376 - fieldset: APB2LPENR - - name: APB4LPENR - description: RCC APB4 Sleep Clock Register - byte_offset: 380 - fieldset: APB4LPENR + - name: CR + description: clock control register + byte_offset: 0 + fieldset: CR + - name: HSICFGR + description: RCC HSI configuration register + byte_offset: 4 + fieldset: HSICFGR + - name: CRRCR + description: RCC Clock Recovery RC Register + byte_offset: 8 + access: Read + fieldset: CRRCR + - name: CSICFGR + description: RCC CSI configuration register + byte_offset: 12 + fieldset: CSICFGR + - name: CFGR + description: RCC Clock Configuration Register + byte_offset: 16 + fieldset: CFGR + - name: D1CFGR + description: RCC Domain 1 Clock Configuration Register + byte_offset: 24 + fieldset: D1CFGR + - name: D2CFGR + description: RCC Domain 2 Clock Configuration Register + byte_offset: 28 + fieldset: D2CFGR + - name: D3CFGR + description: RCC Domain 3 Clock Configuration Register + byte_offset: 32 + fieldset: D3CFGR + - name: PLLCKSELR + description: RCC PLLs Clock Source Selection Register + byte_offset: 40 + fieldset: PLLCKSELR + - name: PLLCFGR + description: RCC PLLs Configuration Register + byte_offset: 44 + fieldset: PLLCFGR + - name: PLLDIVR + description: RCC PLL1 Dividers Configuration Register + array: + len: 3 + stride: 8 + byte_offset: 48 + fieldset: PLLDIVR + - name: PLLFRACR + description: RCC PLL1 Fractional Divider Register + array: + len: 3 + stride: 8 + byte_offset: 52 + fieldset: PLLFRACR + - name: D1CCIPR + description: RCC Domain 1 Kernel Clock Configuration Register + byte_offset: 76 + fieldset: D1CCIPR + - name: D2CCIP1R + description: RCC Domain 2 Kernel Clock Configuration Register + byte_offset: 80 + fieldset: D2CCIP1R + - name: D2CCIP2R + description: RCC Domain 2 Kernel Clock Configuration Register + byte_offset: 84 + fieldset: D2CCIP2R + - name: D3CCIPR + description: RCC Domain 3 Kernel Clock Configuration Register + byte_offset: 88 + fieldset: D3CCIPR + - name: CIER + description: RCC Clock Source Interrupt Enable Register + byte_offset: 96 + fieldset: CIER + - name: CIFR + description: RCC Clock Source Interrupt Flag Register + byte_offset: 100 + access: Read + fieldset: CIFR + - name: CICR + description: RCC Clock Source Interrupt Clear Register + byte_offset: 104 + fieldset: CICR + - name: BDCR + description: RCC Backup Domain Control Register + byte_offset: 112 + fieldset: BDCR + - name: CSR + description: RCC Clock Control and Status Register + byte_offset: 116 + fieldset: CSR + - name: AHB3RSTR + description: RCC AHB3 Reset Register + byte_offset: 124 + fieldset: AHB3RSTR + - name: AHB1RSTR + description: RCC AHB1 Peripheral Reset Register + byte_offset: 128 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: RCC AHB2 Peripheral Reset Register + byte_offset: 132 + fieldset: AHB2RSTR + - name: AHB4RSTR + description: RCC AHB4 Peripheral Reset Register + byte_offset: 136 + fieldset: AHB4RSTR + - name: APB3RSTR + description: RCC APB3 Peripheral Reset Register + byte_offset: 140 + fieldset: APB3RSTR + - name: APB1LRSTR + description: RCC APB1 Peripheral Reset Register + byte_offset: 144 + fieldset: APB1LRSTR + - name: APB1HRSTR + description: RCC APB1 Peripheral Reset Register + byte_offset: 148 + fieldset: APB1HRSTR + - name: APB2RSTR + description: RCC APB2 Peripheral Reset Register + byte_offset: 152 + fieldset: APB2RSTR + - name: APB4RSTR + description: RCC APB4 Peripheral Reset Register + byte_offset: 156 + fieldset: APB4RSTR + - name: GCR + description: Global Control Register + byte_offset: 160 + fieldset: GCR + - name: D3AMR + description: RCC D3 Autonomous mode Register + byte_offset: 168 + fieldset: D3AMR + - name: RSR + description: RCC Reset Status Register + byte_offset: 304 + fieldset: RSR + - name: AHB3ENR + description: RCC AHB3 Clock Register + byte_offset: 308 + fieldset: AHB3ENR + - name: AHB1ENR + description: RCC AHB1 Clock Register + byte_offset: 312 + fieldset: AHB1ENR + - name: AHB2ENR + description: RCC AHB2 Clock Register + byte_offset: 316 + fieldset: AHB2ENR + - name: AHB4ENR + description: RCC AHB4 Clock Register + byte_offset: 320 + fieldset: AHB4ENR + - name: APB3ENR + description: RCC APB3 Clock Register + byte_offset: 324 + fieldset: APB3ENR + - name: APB1LENR + description: RCC APB1 Clock Register + byte_offset: 328 + fieldset: APB1LENR + - name: APB1HENR + description: RCC APB1 Clock Register + byte_offset: 332 + fieldset: APB1HENR + - name: APB2ENR + description: RCC APB2 Clock Register + byte_offset: 336 + fieldset: APB2ENR + - name: APB4ENR + description: RCC APB4 Clock Register + byte_offset: 340 + fieldset: APB4ENR + - name: AHB3LPENR + description: RCC AHB3 Sleep Clock Register + byte_offset: 348 + fieldset: AHB3LPENR + - name: AHB1LPENR + description: RCC AHB1 Sleep Clock Register + byte_offset: 352 + fieldset: AHB1LPENR + - name: AHB2LPENR + description: RCC AHB2 Sleep Clock Register + byte_offset: 356 + fieldset: AHB2LPENR + - name: AHB4LPENR + description: RCC AHB4 Sleep Clock Register + byte_offset: 360 + fieldset: AHB4LPENR + - name: APB3LPENR + description: RCC APB3 Sleep Clock Register + byte_offset: 364 + fieldset: APB3LPENR + - name: APB1LLPENR + description: RCC APB1 Low Sleep Clock Register + byte_offset: 368 + fieldset: APB1LLPENR + - name: APB1HLPENR + description: RCC APB1 High Sleep Clock Register + byte_offset: 372 + fieldset: APB1HLPENR + - name: APB2LPENR + description: RCC APB2 Sleep Clock Register + byte_offset: 376 + fieldset: APB2LPENR + - name: APB4LPENR + description: RCC APB4 Sleep Clock Register + byte_offset: 380 + fieldset: APB4LPENR fieldset/AHB1ENR: description: RCC AHB1 Clock Register fields: - - name: DMA1EN - description: DMA1 Clock Enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: DMA2 Clock Enable - bit_offset: 1 - bit_size: 1 - - name: ADC12EN - description: ADC1/2 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - - name: ARTEN - description: ART Clock Enable - bit_offset: 14 - bit_size: 1 - - name: ETH1MACEN - description: Ethernet MAC bus interface Clock Enable - bit_offset: 15 - bit_size: 1 - - name: ETH1TXEN - description: Ethernet Transmission Clock Enable - bit_offset: 16 - bit_size: 1 - - name: ETH1RXEN - description: Ethernet Reception Clock Enable - bit_offset: 17 - bit_size: 1 - - name: USB_OTG_HSEN - description: USB_OTG_HS Peripheral Clocks Enable - bit_offset: 25 - bit_size: 1 - - name: USB_OTG_HS_ULPIEN - description: USB_OTG_HS ULPI clock enable - bit_offset: 26 - bit_size: 1 - - name: USB_OTG_FSEN - description: USB_OTG_FS Peripheral Clocks Enable - bit_offset: 27 - bit_size: 1 - - name: USB_OTG_FS_ULPIEN - description: USB_OTG_FS ULPI clock enable - bit_offset: 28 - bit_size: 1 + - name: DMA1EN + description: DMA1 Clock Enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 Clock Enable + bit_offset: 1 + bit_size: 1 + - name: ADC12EN + description: ADC1/2 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + - name: ARTEN + description: ART Clock Enable + bit_offset: 14 + bit_size: 1 + - name: ETH1MACEN + description: Ethernet MAC bus interface Clock Enable + bit_offset: 15 + bit_size: 1 + - name: ETH1TXEN + description: Ethernet Transmission Clock Enable + bit_offset: 16 + bit_size: 1 + - name: ETH1RXEN + description: Ethernet Reception Clock Enable + bit_offset: 17 + bit_size: 1 + - name: USB_OTG_HSEN + description: USB_OTG_HS Peripheral Clocks Enable + bit_offset: 25 + bit_size: 1 + - name: USB_OTG_HS_ULPIEN + description: USB_OTG_HS ULPI clock enable + bit_offset: 26 + bit_size: 1 + - name: USB_OTG_FSEN + description: USB_OTG_FS Peripheral Clocks Enable + bit_offset: 27 + bit_size: 1 + - name: USB_OTG_FS_ULPIEN + description: USB_OTG_FS ULPI clock enable + bit_offset: 28 + bit_size: 1 fieldset/AHB1LPENR: description: RCC AHB1 Sleep Clock Register fields: - - name: DMA1LPEN - description: DMA1 Clock Enable During CSleep Mode - bit_offset: 0 - bit_size: 1 - - name: DMA2LPEN - description: DMA2 Clock Enable During CSleep Mode - bit_offset: 1 - bit_size: 1 - - name: ADC12LPEN - description: ADC1/2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - name: ARTLPEN - description: ART Clock Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - - name: ETH1MACLPEN - description: Ethernet MAC bus interface Clock Enable During CSleep Mode - bit_offset: 15 - bit_size: 1 - - name: ETH1TXLPEN - description: Ethernet Transmission Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: ETH1RXLPEN - description: Ethernet Reception Clock Enable During CSleep Mode - bit_offset: 17 - bit_size: 1 - - name: USB_OTG_HSLPEN - description: USB_OTG_HS peripheral clock enable during CSleep mode - bit_offset: 25 - bit_size: 1 - - name: USB_OTG_HS_ULPILPEN - description: USB_PHY1 clock enable during CSleep mode - bit_offset: 26 - bit_size: 1 - - name: USB_OTG_FSLPEN - description: USB_OTG_FS peripheral clock enable during CSleep mode - bit_offset: 27 - bit_size: 1 - - name: USB_OTG_FS_ULPILPEN - description: USB_PHY2 clocks enable during CSleep mode - bit_offset: 28 - bit_size: 1 + - name: DMA1LPEN + description: DMA1 Clock Enable During CSleep Mode + bit_offset: 0 + bit_size: 1 + - name: DMA2LPEN + description: DMA2 Clock Enable During CSleep Mode + bit_offset: 1 + bit_size: 1 + - name: ADC12LPEN + description: ADC1/2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: ARTLPEN + description: ART Clock Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + - name: ETH1MACLPEN + description: Ethernet MAC bus interface Clock Enable During CSleep Mode + bit_offset: 15 + bit_size: 1 + - name: ETH1TXLPEN + description: Ethernet Transmission Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: ETH1RXLPEN + description: Ethernet Reception Clock Enable During CSleep Mode + bit_offset: 17 + bit_size: 1 + - name: USB_OTG_HSLPEN + description: USB_OTG_HS peripheral clock enable during CSleep mode + bit_offset: 25 + bit_size: 1 + - name: USB_OTG_HS_ULPILPEN + description: USB_PHY1 clock enable during CSleep mode + bit_offset: 26 + bit_size: 1 + - name: USB_OTG_FSLPEN + description: USB_OTG_FS peripheral clock enable during CSleep mode + bit_offset: 27 + bit_size: 1 + - name: USB_OTG_FS_ULPILPEN + description: USB_PHY2 clocks enable during CSleep mode + bit_offset: 28 + bit_size: 1 fieldset/AHB1RSTR: description: RCC AHB1 Peripheral Reset Register fields: - - name: DMA1RST - description: DMA1 block reset - bit_offset: 0 - bit_size: 1 - - name: DMA2RST - description: DMA2 block reset - bit_offset: 1 - bit_size: 1 - - name: ADC12RST - description: ADC1&2 block reset - bit_offset: 5 - bit_size: 1 - - name: ARTRST - description: ART block reset - bit_offset: 14 - bit_size: 1 - - name: ETH1MACRST - description: ETH1MAC block reset - bit_offset: 15 - bit_size: 1 - - name: USB_OTG_HSRST - description: USB_OTG_HS block reset - bit_offset: 25 - bit_size: 1 - - name: USB_OTG_FSRST - description: USB_OTG_FS block reset - bit_offset: 27 - bit_size: 1 + - name: DMA1RST + description: DMA1 block reset + bit_offset: 0 + bit_size: 1 + - name: DMA2RST + description: DMA2 block reset + bit_offset: 1 + bit_size: 1 + - name: ADC12RST + description: ADC1&2 block reset + bit_offset: 5 + bit_size: 1 + - name: ARTRST + description: ART block reset + bit_offset: 14 + bit_size: 1 + - name: ETH1MACRST + description: ETH1MAC block reset + bit_offset: 15 + bit_size: 1 + - name: USB_OTG_HSRST + description: USB_OTG_HS block reset + bit_offset: 25 + bit_size: 1 + - name: USB_OTG_FSRST + description: USB_OTG_FS block reset + bit_offset: 27 + bit_size: 1 fieldset/AHB2ENR: description: RCC AHB2 Clock Register fields: - - name: DCMIEN - description: DCMI peripheral clock - bit_offset: 0 - bit_size: 1 - - name: CRYPTEN - description: CRYPT peripheral clock enable - bit_offset: 4 - bit_size: 1 - - name: HASHEN - description: HASH peripheral clock enable - bit_offset: 5 - bit_size: 1 - - name: RNGEN - description: RNG peripheral clocks enable - bit_offset: 6 - bit_size: 1 - - name: SDMMC2EN - description: SDMMC2 and SDMMC2 delay clock enable - bit_offset: 9 - bit_size: 1 - - name: BDMA1EN - description: BDMA1 clock enable - bit_offset: 11 - bit_size: 1 - - name: FMACEN - description: FMAC enable - bit_offset: 16 - bit_size: 1 - - name: CORDICEN - description: CORDIC enable - bit_offset: 17 - bit_size: 1 - - name: SRAM1EN - description: SRAM1 block enable - bit_offset: 29 - bit_size: 1 - - name: SRAM2EN - description: SRAM2 block enable - bit_offset: 30 - bit_size: 1 - - name: SRAM3EN - description: SRAM3 block enable - bit_offset: 31 - bit_size: 1 + - name: DCMIEN + description: DCMI peripheral clock + bit_offset: 0 + bit_size: 1 + - name: CRYPTEN + description: CRYPT peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: HASHEN + description: HASH peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: RNGEN + description: RNG peripheral clocks enable + bit_offset: 6 + bit_size: 1 + - name: SDMMC2EN + description: SDMMC2 and SDMMC2 delay clock enable + bit_offset: 9 + bit_size: 1 + - name: BDMA1EN + description: BDMA1 clock enable + bit_offset: 11 + bit_size: 1 + - name: FMACEN + description: FMAC enable + bit_offset: 16 + bit_size: 1 + - name: CORDICEN + description: CORDIC enable + bit_offset: 17 + bit_size: 1 + - name: SRAM1EN + description: SRAM1 block enable + bit_offset: 29 + bit_size: 1 + - name: SRAM2EN + description: SRAM2 block enable + bit_offset: 30 + bit_size: 1 + - name: SRAM3EN + description: SRAM3 block enable + bit_offset: 31 + bit_size: 1 fieldset/AHB2LPENR: description: RCC AHB2 Sleep Clock Register fields: - - name: DCMILPEN - description: DCMI peripheral clock enable during csleep mode - bit_offset: 0 - bit_size: 1 - - name: CRYPTLPEN - description: CRYPT peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - name: HASHLPEN - description: HASH peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - name: RNGLPEN - description: RNG peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - - name: SDMMC2LPEN - description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - - name: BDMA1LPEN - description: BDMA1 Clock Enable During CSleep Mode - bit_offset: 11 - bit_size: 1 - - name: FMACLPEN - description: FMAC enable during CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: CORDICLPEN - description: CORDIC enable during CSleep Mode - bit_offset: 17 - bit_size: 1 - - name: SRAM1LPEN - description: SRAM1 Clock Enable During CSleep Mode - bit_offset: 29 - bit_size: 1 - - name: SRAM2LPEN - description: SRAM2 Clock Enable During CSleep Mode - bit_offset: 30 - bit_size: 1 - - name: SRAM3LPEN - description: SRAM3 Clock Enable During CSleep Mode - bit_offset: 31 - bit_size: 1 + - name: DCMILPEN + description: DCMI peripheral clock enable during csleep mode + bit_offset: 0 + bit_size: 1 + - name: CRYPTLPEN + description: CRYPT peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: HASHLPEN + description: HASH peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: RNGLPEN + description: RNG peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + - name: SDMMC2LPEN + description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + - name: BDMA1LPEN + description: BDMA1 Clock Enable During CSleep Mode + bit_offset: 11 + bit_size: 1 + - name: FMACLPEN + description: FMAC enable during CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: CORDICLPEN + description: CORDIC enable during CSleep Mode + bit_offset: 17 + bit_size: 1 + - name: SRAM1LPEN + description: SRAM1 Clock Enable During CSleep Mode + bit_offset: 29 + bit_size: 1 + - name: SRAM2LPEN + description: SRAM2 Clock Enable During CSleep Mode + bit_offset: 30 + bit_size: 1 + - name: SRAM3LPEN + description: SRAM3 Clock Enable During CSleep Mode + bit_offset: 31 + bit_size: 1 fieldset/AHB2RSTR: description: RCC AHB2 Peripheral Reset Register fields: - - name: DCMIRST - description: DCMI block reset - bit_offset: 0 - bit_size: 1 - - name: CRYPTRST - description: Cryptography block reset - bit_offset: 4 - bit_size: 1 - - name: HASHRST - description: Hash block reset - bit_offset: 5 - bit_size: 1 - - name: RNGRST - description: Random Number Generator block reset - bit_offset: 6 - bit_size: 1 - - name: SDMMC2RST - description: SDMMC2 and SDMMC2 Delay block reset - bit_offset: 9 - bit_size: 1 - - name: BDMA1RST - description: BDMA1 block reset - bit_offset: 11 - bit_size: 1 - - name: FMACRST - description: FMAC reset - bit_offset: 16 - bit_size: 1 - - name: CORDICRST - description: CORDIC reset - bit_offset: 17 - bit_size: 1 + - name: DCMIRST + description: DCMI block reset + bit_offset: 0 + bit_size: 1 + - name: CRYPTRST + description: Cryptography block reset + bit_offset: 4 + bit_size: 1 + - name: HASHRST + description: Hash block reset + bit_offset: 5 + bit_size: 1 + - name: RNGRST + description: Random Number Generator block reset + bit_offset: 6 + bit_size: 1 + - name: SDMMC2RST + description: SDMMC2 and SDMMC2 Delay block reset + bit_offset: 9 + bit_size: 1 + - name: BDMA1RST + description: BDMA1 block reset + bit_offset: 11 + bit_size: 1 + - name: FMACRST + description: FMAC reset + bit_offset: 16 + bit_size: 1 + - name: CORDICRST + description: CORDIC reset + bit_offset: 17 + bit_size: 1 fieldset/AHB3ENR: description: RCC AHB3 Clock Register fields: - - name: MDMAEN - description: MDMA Peripheral Clock Enable - bit_offset: 0 - bit_size: 1 - - name: DMA2DEN - description: DMA2D Peripheral Clock Enable - bit_offset: 4 - bit_size: 1 - - name: JPGDECEN - description: JPGDEC Peripheral Clock Enable - bit_offset: 5 - bit_size: 1 - - name: FMCEN - description: FMC Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - - name: QUADSPIEN - description: QUADSPI and QUADSPI Delay Clock Enable - bit_offset: 14 - bit_size: 1 - - name: SDMMC1EN - description: SDMMC1 and SDMMC1 Delay Clock Enable - bit_offset: 16 - bit_size: 1 - - name: OCTOSPI2EN - description: OCTOSPI2 and OCTOSPI2 delay block enable - bit_offset: 19 - bit_size: 1 - - name: IOMNGREN - description: OCTOSPI IO manager enable - bit_offset: 21 - bit_size: 1 - - name: OTFD1EN - description: OTFDEC1 enable - bit_offset: 22 - bit_size: 1 - - name: OTFD2EN - description: OTFDEC2 enable - bit_offset: 23 - bit_size: 1 - - name: DTCM1EN - description: D1 DTCM1 block enable - bit_offset: 28 - bit_size: 1 - - name: DTCM2EN - description: D1 DTCM2 block enable - bit_offset: 29 - bit_size: 1 - - name: ITCM1EN - description: D1 ITCM block enable - bit_offset: 30 - bit_size: 1 - - name: AXISRAMEN - description: AXISRAM block enable - bit_offset: 31 - bit_size: 1 + - name: MDMAEN + description: MDMA Peripheral Clock Enable + bit_offset: 0 + bit_size: 1 + - name: DMA2DEN + description: DMA2D Peripheral Clock Enable + bit_offset: 4 + bit_size: 1 + - name: JPGDECEN + description: JPGDEC Peripheral Clock Enable + bit_offset: 5 + bit_size: 1 + - name: FMCEN + description: FMC Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + - name: QUADSPIEN + description: QUADSPI and QUADSPI Delay Clock Enable + bit_offset: 14 + bit_size: 1 + - name: SDMMC1EN + description: SDMMC1 and SDMMC1 Delay Clock Enable + bit_offset: 16 + bit_size: 1 + - name: OCTOSPI2EN + description: OCTOSPI2 and OCTOSPI2 delay block enable + bit_offset: 19 + bit_size: 1 + - name: IOMNGREN + description: OCTOSPI IO manager enable + bit_offset: 21 + bit_size: 1 + - name: OTFD1EN + description: OTFDEC1 enable + bit_offset: 22 + bit_size: 1 + - name: OTFD2EN + description: OTFDEC2 enable + bit_offset: 23 + bit_size: 1 + - name: DTCM1EN + description: D1 DTCM1 block enable + bit_offset: 28 + bit_size: 1 + - name: DTCM2EN + description: D1 DTCM2 block enable + bit_offset: 29 + bit_size: 1 + - name: ITCM1EN + description: D1 ITCM block enable + bit_offset: 30 + bit_size: 1 + - name: AXISRAMEN + description: AXISRAM block enable + bit_offset: 31 + bit_size: 1 fieldset/AHB3LPENR: description: RCC AHB3 Sleep Clock Register fields: - - name: MDMALPEN - description: MDMA Clock Enable During CSleep Mode - bit_offset: 0 - bit_size: 1 - - name: DMA2DLPEN - description: DMA2D Clock Enable During CSleep Mode - bit_offset: 4 - bit_size: 1 - - name: JPGDECLPEN - description: JPGDEC Clock Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - name: FLASHLPEN - description: FLASH Clock Enable During CSleep Mode - bit_offset: 8 - bit_size: 1 - - name: FMCLPEN - description: FMC Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - - name: QSPILPEN - description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - - name: SDMMC1LPEN - description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: OCTOSPI2LPEN - description: OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode - bit_offset: 19 - bit_size: 1 - - name: IOMNGRLPEN - description: OCTOSPI IO manager enable during CSleep Mode - bit_offset: 21 - bit_size: 1 - - name: OTFD1LPEN - description: OTFDEC1 enable during CSleep Mode - bit_offset: 22 - bit_size: 1 - - name: OTFD2LPEN - description: OTFDEC2 enable during CSleep Mode - bit_offset: 23 - bit_size: 1 - - name: D1DTCM1LPEN - description: D1DTCM1 Block Clock Enable During CSleep mode - bit_offset: 28 - bit_size: 1 - - name: DTCM2LPEN - description: D1 DTCM2 Block Clock Enable During CSleep mode - bit_offset: 29 - bit_size: 1 - - name: ITCMLPEN - description: D1ITCM Block Clock Enable During CSleep mode - bit_offset: 30 - bit_size: 1 - - name: AXISRAMLPEN - description: AXISRAM Block Clock Enable During CSleep mode - bit_offset: 31 - bit_size: 1 + - name: MDMALPEN + description: MDMA Clock Enable During CSleep Mode + bit_offset: 0 + bit_size: 1 + - name: DMA2DLPEN + description: DMA2D Clock Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + - name: JPGDECLPEN + description: JPGDEC Clock Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: FLASHLPEN + description: FLASH Clock Enable During CSleep Mode + bit_offset: 8 + bit_size: 1 + - name: FMCLPEN + description: FMC Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + - name: QSPILPEN + description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + - name: SDMMC1LPEN + description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: OCTOSPI2LPEN + description: OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode + bit_offset: 19 + bit_size: 1 + - name: IOMNGRLPEN + description: OCTOSPI IO manager enable during CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: OTFD1LPEN + description: OTFDEC1 enable during CSleep Mode + bit_offset: 22 + bit_size: 1 + - name: OTFD2LPEN + description: OTFDEC2 enable during CSleep Mode + bit_offset: 23 + bit_size: 1 + - name: D1DTCM1LPEN + description: D1DTCM1 Block Clock Enable During CSleep mode + bit_offset: 28 + bit_size: 1 + - name: DTCM2LPEN + description: D1 DTCM2 Block Clock Enable During CSleep mode + bit_offset: 29 + bit_size: 1 + - name: ITCMLPEN + description: D1ITCM Block Clock Enable During CSleep mode + bit_offset: 30 + bit_size: 1 + - name: AXISRAMLPEN + description: AXISRAM Block Clock Enable During CSleep mode + bit_offset: 31 + bit_size: 1 fieldset/AHB3RSTR: description: RCC AHB3 Reset Register fields: - - name: MDMARST - description: MDMA block reset - bit_offset: 0 - bit_size: 1 - - name: DMA2DRST - description: DMA2D block reset - bit_offset: 4 - bit_size: 1 - - name: JPGDECRST - description: JPGDEC block reset - bit_offset: 5 - bit_size: 1 - - name: FMCRST - description: FMC block reset - bit_offset: 12 - bit_size: 1 - - name: QSPIRST - description: QUADSPI and QUADSPI delay block reset - bit_offset: 14 - bit_size: 1 - - name: SDMMC1RST - description: SDMMC1 and SDMMC1 delay block reset - bit_offset: 16 - bit_size: 1 - - name: OCTOSPI2RST - description: OCTOSPI2 and OCTOSPI2 delay block reset - bit_offset: 19 - bit_size: 1 - - name: IOMNGRRST - description: OCTOSPI IO manager reset - bit_offset: 21 - bit_size: 1 - - name: OTFD1RST - description: OTFDEC1 reset - bit_offset: 22 - bit_size: 1 - - name: OTFD2RST - description: OTFDEC2 reset - bit_offset: 23 - bit_size: 1 - - name: CPURST - description: CPU reset - bit_offset: 31 - bit_size: 1 + - name: MDMARST + description: MDMA block reset + bit_offset: 0 + bit_size: 1 + - name: DMA2DRST + description: DMA2D block reset + bit_offset: 4 + bit_size: 1 + - name: JPGDECRST + description: JPGDEC block reset + bit_offset: 5 + bit_size: 1 + - name: FMCRST + description: FMC block reset + bit_offset: 12 + bit_size: 1 + - name: QSPIRST + description: QUADSPI and QUADSPI delay block reset + bit_offset: 14 + bit_size: 1 + - name: SDMMC1RST + description: SDMMC1 and SDMMC1 delay block reset + bit_offset: 16 + bit_size: 1 + - name: OCTOSPI2RST + description: OCTOSPI2 and OCTOSPI2 delay block reset + bit_offset: 19 + bit_size: 1 + - name: IOMNGRRST + description: OCTOSPI IO manager reset + bit_offset: 21 + bit_size: 1 + - name: OTFD1RST + description: OTFDEC1 reset + bit_offset: 22 + bit_size: 1 + - name: OTFD2RST + description: OTFDEC2 reset + bit_offset: 23 + bit_size: 1 + - name: CPURST + description: CPU reset + bit_offset: 31 + bit_size: 1 fieldset/AHB4ENR: description: RCC AHB4 Clock Register fields: - - name: GPIOAEN - description: 0GPIO peripheral clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: 0GPIO peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: 0GPIO peripheral clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: 0GPIO peripheral clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: 0GPIO peripheral clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIOFEN - description: 0GPIO peripheral clock enable - bit_offset: 5 - bit_size: 1 - - name: GPIOGEN - description: 0GPIO peripheral clock enable - bit_offset: 6 - bit_size: 1 - - name: GPIOHEN - description: 0GPIO peripheral clock enable - bit_offset: 7 - bit_size: 1 - - name: GPIOIEN - description: 0GPIO peripheral clock enable - bit_offset: 8 - bit_size: 1 - - name: GPIOJEN - description: 0GPIO peripheral clock enable - bit_offset: 9 - bit_size: 1 - - name: GPIOKEN - description: 0GPIO peripheral clock enable - bit_offset: 10 - bit_size: 1 - - name: CRCEN - description: CRC peripheral clock enable - bit_offset: 19 - bit_size: 1 - - name: BDMA2EN - description: BDMA2 and DMAMUX2 Clock Enable - bit_offset: 21 - bit_size: 1 - - name: BDMAEN - description: BDMA and DMAMUX2 Clock Enable - bit_offset: 21 - bit_size: 1 - - name: ADC3EN - description: ADC3 Peripheral Clocks Enable - bit_offset: 24 - bit_size: 1 - - name: HSEMEN - description: HSEM peripheral clock enable - bit_offset: 25 - bit_size: 1 - - name: BKPSRAMEN - description: Backup RAM Clock Enable - bit_offset: 28 - bit_size: 1 + - name: GPIOAEN + description: 0GPIO peripheral clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: 0GPIO peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: 0GPIO peripheral clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: 0GPIO peripheral clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: 0GPIO peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: 0GPIO peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: 0GPIO peripheral clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: 0GPIO peripheral clock enable + bit_offset: 7 + bit_size: 1 + - name: GPIOIEN + description: 0GPIO peripheral clock enable + bit_offset: 8 + bit_size: 1 + - name: GPIOJEN + description: 0GPIO peripheral clock enable + bit_offset: 9 + bit_size: 1 + - name: GPIOKEN + description: 0GPIO peripheral clock enable + bit_offset: 10 + bit_size: 1 + - name: CRCEN + description: CRC peripheral clock enable + bit_offset: 19 + bit_size: 1 + - name: BDMA2EN + description: BDMA2 and DMAMUX2 Clock Enable + bit_offset: 21 + bit_size: 1 + - name: BDMAEN + description: BDMA and DMAMUX2 Clock Enable + bit_offset: 21 + bit_size: 1 + - name: ADC3EN + description: ADC3 Peripheral Clocks Enable + bit_offset: 24 + bit_size: 1 + - name: HSEMEN + description: HSEM peripheral clock enable + bit_offset: 25 + bit_size: 1 + - name: BKPSRAMEN + description: Backup RAM Clock Enable + bit_offset: 28 + bit_size: 1 fieldset/AHB4LPENR: description: RCC AHB4 Sleep Clock Register fields: - - name: GPIOALPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - - name: GPIOBLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: GPIOCLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 2 - bit_size: 1 - - name: GPIODLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - - name: GPIOELPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - name: GPIOFLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - name: GPIOGLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - - name: GPIOHLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 7 - bit_size: 1 - - name: GPIOILPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 8 - bit_size: 1 - - name: GPIOJLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 9 - bit_size: 1 - - name: GPIOKLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 10 - bit_size: 1 - - name: CRCLPEN - description: CRC peripheral clock enable during CSleep mode - bit_offset: 19 - bit_size: 1 - - name: BDMA2LPEN - description: BDMA2 Clock Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - - name: BDMALPEN - description: BDMA Clock Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - - name: ADC3LPEN - description: ADC3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 24 - bit_size: 1 - - name: BKPSRAMLPEN - description: Backup RAM Clock Enable During CSleep Mode - bit_offset: 28 - bit_size: 1 - - name: SRAM4LPEN - description: SRAM4 Clock Enable During CSleep Mode - bit_offset: 29 - bit_size: 1 + - name: GPIOALPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 2 + bit_size: 1 + - name: GPIODLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + - name: GPIOELPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: GPIOFLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: GPIOGLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + - name: GPIOHLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 7 + bit_size: 1 + - name: GPIOILPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 8 + bit_size: 1 + - name: GPIOJLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 9 + bit_size: 1 + - name: GPIOKLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 10 + bit_size: 1 + - name: CRCLPEN + description: CRC peripheral clock enable during CSleep mode + bit_offset: 19 + bit_size: 1 + - name: BDMA2LPEN + description: BDMA2 Clock Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: BDMALPEN + description: BDMA Clock Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: ADC3LPEN + description: ADC3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 24 + bit_size: 1 + - name: BKPSRAMLPEN + description: Backup RAM Clock Enable During CSleep Mode + bit_offset: 28 + bit_size: 1 + - name: SRAM4LPEN + description: SRAM4 Clock Enable During CSleep Mode + bit_offset: 29 + bit_size: 1 fieldset/AHB4RSTR: description: RCC AHB4 Peripheral Reset Register fields: - - name: GPIOARST - description: GPIO block reset - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: GPIO block reset - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: GPIO block reset - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: GPIO block reset - bit_offset: 3 - bit_size: 1 - - name: GPIOERST - description: GPIO block reset - bit_offset: 4 - bit_size: 1 - - name: GPIOFRST - description: GPIO block reset - bit_offset: 5 - bit_size: 1 - - name: GPIOGRST - description: GPIO block reset - bit_offset: 6 - bit_size: 1 - - name: GPIOHRST - description: GPIO block reset - bit_offset: 7 - bit_size: 1 - - name: GPIOIRST - description: GPIO block reset - bit_offset: 8 - bit_size: 1 - - name: GPIOJRST - description: GPIO block reset - bit_offset: 9 - bit_size: 1 - - name: GPIOKRST - description: GPIO block reset - bit_offset: 10 - bit_size: 1 - - name: CRCRST - description: CRC block reset - bit_offset: 19 - bit_size: 1 - - name: BDMA2RST - description: BDMA2 block reset - bit_offset: 21 - bit_size: 1 - - name: BDMARST - description: BDMA block reset - bit_offset: 21 - bit_size: 1 - - name: ADC3RST - description: ADC3 block reset - bit_offset: 24 - bit_size: 1 - - name: HSEMRST - description: HSEM block reset - bit_offset: 25 - bit_size: 1 + - name: GPIOARST + description: GPIO block reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: GPIO block reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: GPIO block reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: GPIO block reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: GPIO block reset + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: GPIO block reset + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: GPIO block reset + bit_offset: 6 + bit_size: 1 + - name: GPIOHRST + description: GPIO block reset + bit_offset: 7 + bit_size: 1 + - name: GPIOIRST + description: GPIO block reset + bit_offset: 8 + bit_size: 1 + - name: GPIOJRST + description: GPIO block reset + bit_offset: 9 + bit_size: 1 + - name: GPIOKRST + description: GPIO block reset + bit_offset: 10 + bit_size: 1 + - name: CRCRST + description: CRC block reset + bit_offset: 19 + bit_size: 1 + - name: BDMA2RST + description: BDMA2 block reset + bit_offset: 21 + bit_size: 1 + - name: BDMARST + description: BDMA block reset + bit_offset: 21 + bit_size: 1 + - name: ADC3RST + description: ADC3 block reset + bit_offset: 24 + bit_size: 1 + - name: HSEMRST + description: HSEM block reset + bit_offset: 25 + bit_size: 1 fieldset/APB1HENR: description: RCC APB1 Clock Register fields: - - name: CRSEN - description: Clock Recovery System peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: SWPEN - description: SWPMI Peripheral Clocks Enable - bit_offset: 2 - bit_size: 1 - - name: OPAMPEN - description: OPAMP peripheral clock enable - bit_offset: 4 - bit_size: 1 - - name: MDIOSEN - description: MDIOS peripheral clock enable - bit_offset: 5 - bit_size: 1 - - name: FDCANEN - description: FDCAN Peripheral Clocks Enable - bit_offset: 8 - bit_size: 1 - - name: TIM23EN - description: TIM23 block enable - bit_offset: 24 - bit_size: 1 - - name: TIM24EN - description: TIM24 block enable - bit_offset: 25 - bit_size: 1 + - name: CRSEN + description: Clock Recovery System peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: SWPEN + description: SWPMI Peripheral Clocks Enable + bit_offset: 2 + bit_size: 1 + - name: OPAMPEN + description: OPAMP peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: MDIOSEN + description: MDIOS peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: FDCANEN + description: FDCAN Peripheral Clocks Enable + bit_offset: 8 + bit_size: 1 + - name: TIM23EN + description: TIM23 block enable + bit_offset: 24 + bit_size: 1 + - name: TIM24EN + description: TIM24 block enable + bit_offset: 25 + bit_size: 1 fieldset/APB1HLPENR: description: RCC APB1 High Sleep Clock Register fields: - - name: CRSLPEN - description: Clock Recovery System peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: SWPLPEN - description: SWPMI Peripheral Clocks Enable During CSleep Mode - bit_offset: 2 - bit_size: 1 - - name: OPAMPLPEN - description: OPAMP peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - name: MDIOSLPEN - description: MDIOS peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - name: FDCANLPEN - description: FDCAN Peripheral Clocks Enable During CSleep Mode - bit_offset: 8 - bit_size: 1 - - name: TIM23LPEN - description: TIM23 block enable during CSleep Mode - bit_offset: 24 - bit_size: 1 - - name: TIM24LPEN - description: TIM24 block enable during CSleep Mode - bit_offset: 25 - bit_size: 1 + - name: CRSLPEN + description: Clock Recovery System peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: SWPLPEN + description: SWPMI Peripheral Clocks Enable During CSleep Mode + bit_offset: 2 + bit_size: 1 + - name: OPAMPLPEN + description: OPAMP peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: MDIOSLPEN + description: MDIOS peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: FDCANLPEN + description: FDCAN Peripheral Clocks Enable During CSleep Mode + bit_offset: 8 + bit_size: 1 + - name: TIM23LPEN + description: TIM23 block enable during CSleep Mode + bit_offset: 24 + bit_size: 1 + - name: TIM24LPEN + description: TIM24 block enable during CSleep Mode + bit_offset: 25 + bit_size: 1 fieldset/APB1HRSTR: description: RCC APB1 Peripheral Reset Register fields: - - name: CRSRST - description: Clock Recovery System reset - bit_offset: 1 - bit_size: 1 - - name: SWPRST - description: SWPMI block reset - bit_offset: 2 - bit_size: 1 - - name: OPAMPRST - description: OPAMP block reset - bit_offset: 4 - bit_size: 1 - - name: MDIOSRST - description: MDIOS block reset - bit_offset: 5 - bit_size: 1 - - name: FDCANRST - description: FDCAN block reset - bit_offset: 8 - bit_size: 1 - - name: TIM23RST - description: TIM23 block reset - bit_offset: 24 - bit_size: 1 - - name: TIM24RST - description: TIM24 block reset - bit_offset: 25 - bit_size: 1 + - name: CRSRST + description: Clock Recovery System reset + bit_offset: 1 + bit_size: 1 + - name: SWPRST + description: SWPMI block reset + bit_offset: 2 + bit_size: 1 + - name: OPAMPRST + description: OPAMP block reset + bit_offset: 4 + bit_size: 1 + - name: MDIOSRST + description: MDIOS block reset + bit_offset: 5 + bit_size: 1 + - name: FDCANRST + description: FDCAN block reset + bit_offset: 8 + bit_size: 1 + - name: TIM23RST + description: TIM23 block reset + bit_offset: 24 + bit_size: 1 + - name: TIM24RST + description: TIM24 block reset + bit_offset: 25 + bit_size: 1 fieldset/APB1LENR: description: RCC APB1 Clock Register fields: - - name: TIM2EN - description: TIM peripheral clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: TIM peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: TIM peripheral clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: TIM peripheral clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: TIM peripheral clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: TIM peripheral clock enable - bit_offset: 5 - bit_size: 1 - - name: TIM12EN - description: TIM peripheral clock enable - bit_offset: 6 - bit_size: 1 - - name: TIM13EN - description: TIM peripheral clock enable - bit_offset: 7 - bit_size: 1 - - name: TIM14EN - description: TIM peripheral clock enable - bit_offset: 8 - bit_size: 1 - - name: LPTIM1EN - description: LPTIM1 Peripheral Clocks Enable - bit_offset: 9 - bit_size: 1 - - name: WWDG2EN - description: WWDG2 peripheral clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI2 Peripheral Clocks Enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI3 Peripheral Clocks Enable - bit_offset: 15 - bit_size: 1 - - name: SPDIFRXEN - description: SPDIFRX Peripheral Clocks Enable - bit_offset: 16 - bit_size: 1 - - name: USART2EN - description: USART2 Peripheral Clocks Enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART3 Peripheral Clocks Enable - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: UART4 Peripheral Clocks Enable - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: UART5 Peripheral Clocks Enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C1 Peripheral Clocks Enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C2 Peripheral Clocks Enable - bit_offset: 22 - bit_size: 1 - - name: I2C3EN - description: I2C3 Peripheral Clocks Enable - bit_offset: 23 - bit_size: 1 - - name: I2C5EN - description: "I2C5 Peripheral Clocks\r Enable" - bit_offset: 25 - bit_size: 1 - - name: CECEN - description: HDMI-CEC peripheral clock enable - bit_offset: 27 - bit_size: 1 - - name: DAC1EN - description: DAC1 (containing two converters) peripheral clock enable - bit_offset: 29 - bit_size: 1 - - name: UART7EN - description: UART7 Peripheral Clocks Enable - bit_offset: 30 - bit_size: 1 - - name: UART8EN - description: UART8 Peripheral Clocks Enable - bit_offset: 31 - bit_size: 1 + - name: TIM2EN + description: TIM peripheral clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM peripheral clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: TIM peripheral clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: TIM peripheral clock enable + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: TIM peripheral clock enable + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: TIM peripheral clock enable + bit_offset: 8 + bit_size: 1 + - name: LPTIM1EN + description: LPTIM1 Peripheral Clocks Enable + bit_offset: 9 + bit_size: 1 + - name: WWDG2EN + description: WWDG2 peripheral clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 Peripheral Clocks Enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 Peripheral Clocks Enable + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXEN + description: SPDIFRX Peripheral Clocks Enable + bit_offset: 16 + bit_size: 1 + - name: USART2EN + description: USART2 Peripheral Clocks Enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 Peripheral Clocks Enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 Peripheral Clocks Enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 Peripheral Clocks Enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 Peripheral Clocks Enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 Peripheral Clocks Enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: I2C3 Peripheral Clocks Enable + bit_offset: 23 + bit_size: 1 + - name: I2C5EN + description: "I2C5 Peripheral Clocks\r Enable" + bit_offset: 25 + bit_size: 1 + - name: CECEN + description: HDMI-CEC peripheral clock enable + bit_offset: 27 + bit_size: 1 + - name: DAC1EN + description: DAC1 (containing two converters) peripheral clock enable + bit_offset: 29 + bit_size: 1 + - name: UART7EN + description: UART7 Peripheral Clocks Enable + bit_offset: 30 + bit_size: 1 + - name: UART8EN + description: UART8 Peripheral Clocks Enable + bit_offset: 31 + bit_size: 1 fieldset/APB1LLPENR: description: RCC APB1 Low Sleep Clock Register fields: - - name: TIM2LPEN - description: TIM2 peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM3LPEN - description: TIM3 peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: TIM4LPEN - description: TIM4 peripheral clock enable during CSleep mode - bit_offset: 2 - bit_size: 1 - - name: TIM5LPEN - description: TIM5 peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - - name: TIM6LPEN - description: TIM6 peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - name: TIM7LPEN - description: TIM7 peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - name: TIM12LPEN - description: TIM12 peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - - name: TIM13LPEN - description: TIM13 peripheral clock enable during CSleep mode - bit_offset: 7 - bit_size: 1 - - name: TIM14LPEN - description: TIM14 peripheral clock enable during CSleep mode - bit_offset: 8 - bit_size: 1 - - name: LPTIM1LPEN - description: LPTIM1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - - name: WWDG2LPEN - description: WWDG2 peripheral Clocks Enable During CSleep Mode - bit_offset: 11 - bit_size: 1 - - name: SPI2LPEN - description: SPI2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - - name: SPI3LPEN - description: SPI3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 15 - bit_size: 1 - - name: SPDIFRXLPEN - description: SPDIFRX Peripheral Clocks Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: USART2LPEN - description: USART2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 17 - bit_size: 1 - - name: USART3LPEN - description: USART3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 18 - bit_size: 1 - - name: UART4LPEN - description: UART4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 19 - bit_size: 1 - - name: UART5LPEN - description: UART5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 20 - bit_size: 1 - - name: I2C1LPEN - description: I2C1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - - name: I2C2LPEN - description: I2C2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 22 - bit_size: 1 - - name: I2C3LPEN - description: I2C3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 23 - bit_size: 1 - - name: I2C5LPEN - description: I2C5 block enable during CSleep Mode - bit_offset: 25 - bit_size: 1 - - name: CECLPEN - description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode - bit_offset: 27 - bit_size: 1 - - name: DAC1LPEN - description: DAC1 (containing two converters) peripheral clock enable during CSleep mode - bit_offset: 29 - bit_size: 1 - - name: UART7LPEN - description: UART7 Peripheral Clocks Enable During CSleep Mode - bit_offset: 30 - bit_size: 1 - - name: UART8LPEN - description: UART8 Peripheral Clocks Enable During CSleep Mode - bit_offset: 31 - bit_size: 1 + - name: TIM2LPEN + description: TIM2 peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM3LPEN + description: TIM3 peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: TIM4LPEN + description: TIM4 peripheral clock enable during CSleep mode + bit_offset: 2 + bit_size: 1 + - name: TIM5LPEN + description: TIM5 peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + - name: TIM6LPEN + description: TIM6 peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: TIM7LPEN + description: TIM7 peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: TIM12LPEN + description: TIM12 peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + - name: TIM13LPEN + description: TIM13 peripheral clock enable during CSleep mode + bit_offset: 7 + bit_size: 1 + - name: TIM14LPEN + description: TIM14 peripheral clock enable during CSleep mode + bit_offset: 8 + bit_size: 1 + - name: LPTIM1LPEN + description: LPTIM1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + - name: WWDG2LPEN + description: WWDG2 peripheral Clocks Enable During CSleep Mode + bit_offset: 11 + bit_size: 1 + - name: SPI2LPEN + description: SPI2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + - name: SPI3LPEN + description: SPI3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXLPEN + description: SPDIFRX Peripheral Clocks Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: USART2LPEN + description: USART2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 17 + bit_size: 1 + - name: USART3LPEN + description: USART3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 18 + bit_size: 1 + - name: UART4LPEN + description: UART4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 19 + bit_size: 1 + - name: UART5LPEN + description: UART5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 20 + bit_size: 1 + - name: I2C1LPEN + description: I2C1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: I2C2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 22 + bit_size: 1 + - name: I2C3LPEN + description: I2C3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 23 + bit_size: 1 + - name: I2C5LPEN + description: I2C5 block enable during CSleep Mode + bit_offset: 25 + bit_size: 1 + - name: CECLPEN + description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode + bit_offset: 27 + bit_size: 1 + - name: DAC1LPEN + description: DAC1 (containing two converters) peripheral clock enable during CSleep mode + bit_offset: 29 + bit_size: 1 + - name: UART7LPEN + description: UART7 Peripheral Clocks Enable During CSleep Mode + bit_offset: 30 + bit_size: 1 + - name: UART8LPEN + description: UART8 Peripheral Clocks Enable During CSleep Mode + bit_offset: 31 + bit_size: 1 fieldset/APB1LRSTR: description: RCC APB1 Peripheral Reset Register fields: - - name: TIM2RST - description: TIM block reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: TIM block reset - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: TIM block reset - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: TIM block reset - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: TIM block reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: TIM block reset - bit_offset: 5 - bit_size: 1 - - name: TIM12RST - description: TIM block reset - bit_offset: 6 - bit_size: 1 - - name: TIM13RST - description: TIM block reset - bit_offset: 7 - bit_size: 1 - - name: TIM14RST - description: TIM block reset - bit_offset: 8 - bit_size: 1 - - name: LPTIM1RST - description: TIM block reset - bit_offset: 9 - bit_size: 1 - - name: SPI2RST - description: SPI2 block reset - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: SPI3 block reset - bit_offset: 15 - bit_size: 1 - - name: SPDIFRXRST - description: SPDIFRX block reset - bit_offset: 16 - bit_size: 1 - - name: USART2RST - description: USART2 block reset - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: USART3 block reset - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: UART4 block reset - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: UART5 block reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C1 block reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C2 block reset - bit_offset: 22 - bit_size: 1 - - name: I2C3RST - description: I2C3 block reset - bit_offset: 23 - bit_size: 1 - - name: I2C5RST - description: I2C5 block reset - bit_offset: 25 - bit_size: 1 - - name: CECRST - description: HDMI-CEC block reset - bit_offset: 27 - bit_size: 1 - - name: DAC1RST - description: DAC1 (containing two converters) reset - bit_offset: 29 - bit_size: 1 - - name: UART7RST - description: UART7 block reset - bit_offset: 30 - bit_size: 1 - - name: UART8RST - description: UART8 block reset - bit_offset: 31 - bit_size: 1 + - name: TIM2RST + description: TIM block reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: TIM block reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: TIM block reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: TIM block reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: TIM block reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM block reset + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: TIM block reset + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: TIM block reset + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: TIM block reset + bit_offset: 8 + bit_size: 1 + - name: LPTIM1RST + description: TIM block reset + bit_offset: 9 + bit_size: 1 + - name: SPI2RST + description: SPI2 block reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 block reset + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXRST + description: SPDIFRX block reset + bit_offset: 16 + bit_size: 1 + - name: USART2RST + description: USART2 block reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 block reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: UART4 block reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: UART5 block reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 block reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 block reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 block reset + bit_offset: 23 + bit_size: 1 + - name: I2C5RST + description: I2C5 block reset + bit_offset: 25 + bit_size: 1 + - name: CECRST + description: HDMI-CEC block reset + bit_offset: 27 + bit_size: 1 + - name: DAC1RST + description: DAC1 (containing two converters) reset + bit_offset: 29 + bit_size: 1 + - name: UART7RST + description: UART7 block reset + bit_offset: 30 + bit_size: 1 + - name: UART8RST + description: UART8 block reset + bit_offset: 31 + bit_size: 1 fieldset/APB2ENR: description: RCC APB2 Clock Register fields: - - name: TIM1EN - description: TIM1 peripheral clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM8EN - description: TIM8 peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: USART1EN - description: USART1 Peripheral Clocks Enable - bit_offset: 4 - bit_size: 1 - - name: USART6EN - description: USART6 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - - name: UART9EN - description: "UART9 Peripheral Clocks\r Enable" - bit_offset: 6 - bit_size: 1 - - name: USART10EN - description: "USART10 Peripheral Clocks\r Enable" - bit_offset: 7 - bit_size: 1 - - name: SPI1EN - description: SPI1 Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - - name: SPI4EN - description: SPI4 Peripheral Clocks Enable - bit_offset: 13 - bit_size: 1 - - name: TIM15EN - description: TIM15 peripheral clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: TIM16 peripheral clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: TIM17 peripheral clock enable - bit_offset: 18 - bit_size: 1 - - name: SPI5EN - description: SPI5 Peripheral Clocks Enable - bit_offset: 20 - bit_size: 1 - - name: SAI1EN - description: SAI1 Peripheral Clocks Enable - bit_offset: 22 - bit_size: 1 - - name: SAI2EN - description: SAI2 Peripheral Clocks Enable - bit_offset: 23 - bit_size: 1 - - name: SAI3EN - description: SAI3 Peripheral Clocks Enable - bit_offset: 24 - bit_size: 1 - - name: DFSDM1EN - description: DFSDM1 Peripheral Clocks Enable - bit_offset: 28 - bit_size: 1 - - name: HRTIMEN - description: HRTIM peripheral clock enable - bit_offset: 29 - bit_size: 1 + - name: TIM1EN + description: TIM1 peripheral clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM8EN + description: TIM8 peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: USART1EN + description: USART1 Peripheral Clocks Enable + bit_offset: 4 + bit_size: 1 + - name: USART6EN + description: USART6 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + - name: UART9EN + description: "UART9 Peripheral Clocks\r Enable" + bit_offset: 6 + bit_size: 1 + - name: USART10EN + description: "USART10 Peripheral Clocks\r Enable" + bit_offset: 7 + bit_size: 1 + - name: SPI1EN + description: SPI1 Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + - name: SPI4EN + description: SPI4 Peripheral Clocks Enable + bit_offset: 13 + bit_size: 1 + - name: TIM15EN + description: TIM15 peripheral clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 peripheral clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 peripheral clock enable + bit_offset: 18 + bit_size: 1 + - name: SPI5EN + description: SPI5 Peripheral Clocks Enable + bit_offset: 20 + bit_size: 1 + - name: SAI1EN + description: SAI1 Peripheral Clocks Enable + bit_offset: 22 + bit_size: 1 + - name: SAI2EN + description: SAI2 Peripheral Clocks Enable + bit_offset: 23 + bit_size: 1 + - name: SAI3EN + description: SAI3 Peripheral Clocks Enable + bit_offset: 24 + bit_size: 1 + - name: DFSDM1EN + description: DFSDM1 Peripheral Clocks Enable + bit_offset: 28 + bit_size: 1 + - name: HRTIMEN + description: HRTIM peripheral clock enable + bit_offset: 29 + bit_size: 1 fieldset/APB2LPENR: description: RCC APB2 Sleep Clock Register fields: - - name: TIM1LPEN - description: TIM1 peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM8LPEN - description: TIM8 peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: USART1LPEN - description: USART1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 4 - bit_size: 1 - - name: USART6LPEN - description: USART6 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - name: SPI1LPEN - description: SPI1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - - name: SPI4LPEN - description: SPI4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 13 - bit_size: 1 - - name: TIM15LPEN - description: TIM15 peripheral clock enable during CSleep mode - bit_offset: 16 - bit_size: 1 - - name: TIM16LPEN - description: TIM16 peripheral clock enable during CSleep mode - bit_offset: 17 - bit_size: 1 - - name: TIM17LPEN - description: TIM17 peripheral clock enable during CSleep mode - bit_offset: 18 - bit_size: 1 - - name: SPI5LPEN - description: SPI5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 20 - bit_size: 1 - - name: SAI1LPEN - description: SAI1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 22 - bit_size: 1 - - name: SAI2LPEN - description: SAI2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 23 - bit_size: 1 - - name: SAI3LPEN - description: SAI3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 24 - bit_size: 1 - - name: DFSDM1LPEN - description: DFSDM1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 28 - bit_size: 1 - - name: HRTIMLPEN - description: HRTIM peripheral clock enable during CSleep mode - bit_offset: 29 - bit_size: 1 + - name: TIM1LPEN + description: TIM1 peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM8LPEN + description: TIM8 peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: USART1LPEN + description: USART1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + - name: USART6LPEN + description: USART6 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: SPI1LPEN + description: SPI1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + - name: SPI4LPEN + description: SPI4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 13 + bit_size: 1 + - name: TIM15LPEN + description: TIM15 peripheral clock enable during CSleep mode + bit_offset: 16 + bit_size: 1 + - name: TIM16LPEN + description: TIM16 peripheral clock enable during CSleep mode + bit_offset: 17 + bit_size: 1 + - name: TIM17LPEN + description: TIM17 peripheral clock enable during CSleep mode + bit_offset: 18 + bit_size: 1 + - name: SPI5LPEN + description: SPI5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 20 + bit_size: 1 + - name: SAI1LPEN + description: SAI1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 22 + bit_size: 1 + - name: SAI2LPEN + description: SAI2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 23 + bit_size: 1 + - name: SAI3LPEN + description: SAI3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 24 + bit_size: 1 + - name: DFSDM1LPEN + description: DFSDM1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 28 + bit_size: 1 + - name: HRTIMLPEN + description: HRTIM peripheral clock enable during CSleep mode + bit_offset: 29 + bit_size: 1 fieldset/APB2RSTR: description: RCC APB2 Peripheral Reset Register fields: - - name: TIM1RST - description: TIM1 block reset - bit_offset: 0 - bit_size: 1 - - name: TIM8RST - description: TIM8 block reset - bit_offset: 1 - bit_size: 1 - - name: USART1RST - description: USART1 block reset - bit_offset: 4 - bit_size: 1 - - name: USART6RST - description: USART6 block reset - bit_offset: 5 - bit_size: 1 - - name: UART9RST - description: UART9 block reset - bit_offset: 6 - bit_size: 1 - - name: USART10RST - description: USART10 block reset - bit_offset: 7 - bit_size: 1 - - name: SPI1RST - description: SPI1 block reset - bit_offset: 12 - bit_size: 1 - - name: SPI4RST - description: SPI4 block reset - bit_offset: 13 - bit_size: 1 - - name: TIM15RST - description: TIM15 block reset - bit_offset: 16 - bit_size: 1 - - name: TIM16RST - description: TIM16 block reset - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: TIM17 block reset - bit_offset: 18 - bit_size: 1 - - name: SPI5RST - description: SPI5 block reset - bit_offset: 20 - bit_size: 1 - - name: SAI1RST - description: SAI1 block reset - bit_offset: 22 - bit_size: 1 - - name: SAI2RST - description: SAI2 block reset - bit_offset: 23 - bit_size: 1 - - name: SAI3RST - description: SAI3 block reset - bit_offset: 24 - bit_size: 1 - - name: DFSDM1RST - description: DFSDM1 block reset - bit_offset: 28 - bit_size: 1 - - name: HRTIMRST - description: HRTIM block reset - bit_offset: 29 - bit_size: 1 + - name: TIM1RST + description: TIM1 block reset + bit_offset: 0 + bit_size: 1 + - name: TIM8RST + description: TIM8 block reset + bit_offset: 1 + bit_size: 1 + - name: USART1RST + description: USART1 block reset + bit_offset: 4 + bit_size: 1 + - name: USART6RST + description: USART6 block reset + bit_offset: 5 + bit_size: 1 + - name: UART9RST + description: UART9 block reset + bit_offset: 6 + bit_size: 1 + - name: USART10RST + description: USART10 block reset + bit_offset: 7 + bit_size: 1 + - name: SPI1RST + description: SPI1 block reset + bit_offset: 12 + bit_size: 1 + - name: SPI4RST + description: SPI4 block reset + bit_offset: 13 + bit_size: 1 + - name: TIM15RST + description: TIM15 block reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 block reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 block reset + bit_offset: 18 + bit_size: 1 + - name: SPI5RST + description: SPI5 block reset + bit_offset: 20 + bit_size: 1 + - name: SAI1RST + description: SAI1 block reset + bit_offset: 22 + bit_size: 1 + - name: SAI2RST + description: SAI2 block reset + bit_offset: 23 + bit_size: 1 + - name: SAI3RST + description: SAI3 block reset + bit_offset: 24 + bit_size: 1 + - name: DFSDM1RST + description: DFSDM1 block reset + bit_offset: 28 + bit_size: 1 + - name: HRTIMRST + description: HRTIM block reset + bit_offset: 29 + bit_size: 1 fieldset/APB3ENR: description: RCC APB3 Clock Register fields: - - name: LTDCEN - description: LTDC peripheral clock enable - bit_offset: 3 - bit_size: 1 - - name: DSIEN - description: DSI Peripheral clocks enable - bit_offset: 4 - bit_size: 1 - - name: WWDG1EN - description: WWDG1 Clock Enable - bit_offset: 6 - bit_size: 1 + - name: LTDCEN + description: LTDC peripheral clock enable + bit_offset: 3 + bit_size: 1 + - name: DSIEN + description: DSI Peripheral clocks enable + bit_offset: 4 + bit_size: 1 + - name: WWDG1EN + description: WWDG1 Clock Enable + bit_offset: 6 + bit_size: 1 fieldset/APB3LPENR: description: RCC APB3 Sleep Clock Register fields: - - name: LTDCLPEN - description: LTDC peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - - name: DSILPEN - description: DSI Peripheral Clock Enable During CSleep Mode - bit_offset: 4 - bit_size: 1 - - name: WWDG1LPEN - description: WWDG1 Clock Enable During CSleep Mode - bit_offset: 6 - bit_size: 1 + - name: LTDCLPEN + description: LTDC peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + - name: DSILPEN + description: DSI Peripheral Clock Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + - name: WWDG1LPEN + description: WWDG1 Clock Enable During CSleep Mode + bit_offset: 6 + bit_size: 1 fieldset/APB3RSTR: description: RCC APB3 Peripheral Reset Register fields: - - name: LTDCRST - description: LTDC block reset - bit_offset: 3 - bit_size: 1 - - name: DSIRST - description: DSI block reset - bit_offset: 4 - bit_size: 1 + - name: LTDCRST + description: LTDC block reset + bit_offset: 3 + bit_size: 1 + - name: DSIRST + description: DSI block reset + bit_offset: 4 + bit_size: 1 fieldset/APB4ENR: description: RCC APB4 Clock Register fields: - - name: SYSCFGEN - description: SYSCFG peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: LPUART1EN - description: LPUART1 Peripheral Clocks Enable - bit_offset: 3 - bit_size: 1 - - name: SPI6EN - description: SPI6 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - - name: I2C4EN - description: I2C4 Peripheral Clocks Enable - bit_offset: 7 - bit_size: 1 - - name: LPTIM2EN - description: LPTIM2 Peripheral Clocks Enable - bit_offset: 9 - bit_size: 1 - - name: LPTIM3EN - description: LPTIM3 Peripheral Clocks Enable - bit_offset: 10 - bit_size: 1 - - name: LPTIM4EN - description: LPTIM4 Peripheral Clocks Enable - bit_offset: 11 - bit_size: 1 - - name: LPTIM5EN - description: LPTIM5 Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - - name: DAC2EN - description: DAC2 (containing one converter) peripheral clock enable - bit_offset: 13 - bit_size: 1 - - name: COMP12EN - description: COMP1/2 peripheral clock enable - bit_offset: 14 - bit_size: 1 - - name: VREFEN - description: VREF peripheral clock enable - bit_offset: 15 - bit_size: 1 - - name: RTCAPBEN - description: RTC APB Clock Enable - bit_offset: 16 - bit_size: 1 - - name: SAI4EN - description: SAI4 Peripheral Clocks Enable - bit_offset: 21 - bit_size: 1 - - name: DTSEN - description: Digital temperature sensor block enable - bit_offset: 26 - bit_size: 1 + - name: SYSCFGEN + description: SYSCFG peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: LPUART1EN + description: LPUART1 Peripheral Clocks Enable + bit_offset: 3 + bit_size: 1 + - name: SPI6EN + description: SPI6 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + - name: I2C4EN + description: I2C4 Peripheral Clocks Enable + bit_offset: 7 + bit_size: 1 + - name: LPTIM2EN + description: LPTIM2 Peripheral Clocks Enable + bit_offset: 9 + bit_size: 1 + - name: LPTIM3EN + description: LPTIM3 Peripheral Clocks Enable + bit_offset: 10 + bit_size: 1 + - name: LPTIM4EN + description: LPTIM4 Peripheral Clocks Enable + bit_offset: 11 + bit_size: 1 + - name: LPTIM5EN + description: LPTIM5 Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + - name: DAC2EN + description: DAC2 (containing one converter) peripheral clock enable + bit_offset: 13 + bit_size: 1 + - name: COMP12EN + description: COMP1/2 peripheral clock enable + bit_offset: 14 + bit_size: 1 + - name: VREFEN + description: VREF peripheral clock enable + bit_offset: 15 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB Clock Enable + bit_offset: 16 + bit_size: 1 + - name: SAI4EN + description: SAI4 Peripheral Clocks Enable + bit_offset: 21 + bit_size: 1 + - name: DTSEN + description: Digital temperature sensor block enable + bit_offset: 26 + bit_size: 1 fieldset/APB4LPENR: description: RCC APB4 Sleep Clock Register fields: - - name: SYSCFGLPEN - description: SYSCFG peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: LPUART1LPEN - description: LPUART1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 3 - bit_size: 1 - - name: SPI6LPEN - description: SPI6 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - name: I2C4LPEN - description: I2C4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 7 - bit_size: 1 - - name: LPTIM2LPEN - description: LPTIM2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - - name: LPTIM3LPEN - description: LPTIM3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 10 - bit_size: 1 - - name: LPTIM4LPEN - description: LPTIM4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 11 - bit_size: 1 - - name: LPTIM5LPEN - description: LPTIM5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - - name: DAC2LPEN - description: DAC2 (containing one converter) peripheral clock enable during CSleep mode - bit_offset: 13 - bit_size: 1 - - name: COMP12LPEN - description: COMP1/2 peripheral clock enable during CSleep mode - bit_offset: 14 - bit_size: 1 - - name: VREFLPEN - description: VREF peripheral clock enable during CSleep mode - bit_offset: 15 - bit_size: 1 - - name: RTCAPBLPEN - description: RTC APB Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: SAI4LPEN - description: SAI4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - - name: DTSLPEN - description: Digital temperature sensor block enable during CSleep Mode - bit_offset: 26 - bit_size: 1 + - name: SYSCFGLPEN + description: SYSCFG peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: LPUART1LPEN + description: LPUART1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 3 + bit_size: 1 + - name: SPI6LPEN + description: SPI6 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: I2C4LPEN + description: I2C4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 7 + bit_size: 1 + - name: LPTIM2LPEN + description: LPTIM2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + - name: LPTIM3LPEN + description: LPTIM3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 10 + bit_size: 1 + - name: LPTIM4LPEN + description: LPTIM4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 11 + bit_size: 1 + - name: LPTIM5LPEN + description: LPTIM5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + - name: DAC2LPEN + description: DAC2 (containing one converter) peripheral clock enable during CSleep mode + bit_offset: 13 + bit_size: 1 + - name: COMP12LPEN + description: COMP1/2 peripheral clock enable during CSleep mode + bit_offset: 14 + bit_size: 1 + - name: VREFLPEN + description: VREF peripheral clock enable during CSleep mode + bit_offset: 15 + bit_size: 1 + - name: RTCAPBLPEN + description: RTC APB Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: SAI4LPEN + description: SAI4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: DTSLPEN + description: Digital temperature sensor block enable during CSleep Mode + bit_offset: 26 + bit_size: 1 fieldset/APB4RSTR: description: RCC APB4 Peripheral Reset Register fields: - - name: SYSCFGRST - description: SYSCFG block reset - bit_offset: 1 - bit_size: 1 - - name: LPUART1RST - description: LPUART1 block reset - bit_offset: 3 - bit_size: 1 - - name: SPI6RST - description: SPI6 block reset - bit_offset: 5 - bit_size: 1 - - name: I2C4RST - description: I2C4 block reset - bit_offset: 7 - bit_size: 1 - - name: LPTIM2RST - description: LPTIM2 block reset - bit_offset: 9 - bit_size: 1 - - name: LPTIM3RST - description: LPTIM3 block reset - bit_offset: 10 - bit_size: 1 - - name: LPTIM4RST - description: LPTIM4 block reset - bit_offset: 11 - bit_size: 1 - - name: LPTIM5RST - description: LPTIM5 block reset - bit_offset: 12 - bit_size: 1 - - name: DAC2RST - description: DAC2 (containing one converter) reset - bit_offset: 13 - bit_size: 1 - - name: COMP12RST - description: COMP12 Blocks Reset - bit_offset: 14 - bit_size: 1 - - name: VREFRST - description: VREF block reset - bit_offset: 15 - bit_size: 1 - - name: SAI4RST - description: SAI4 block reset - bit_offset: 21 - bit_size: 1 - - name: DTSRST - description: Digital temperature sensor block reset - bit_offset: 26 - bit_size: 1 + - name: SYSCFGRST + description: SYSCFG block reset + bit_offset: 1 + bit_size: 1 + - name: LPUART1RST + description: LPUART1 block reset + bit_offset: 3 + bit_size: 1 + - name: SPI6RST + description: SPI6 block reset + bit_offset: 5 + bit_size: 1 + - name: I2C4RST + description: I2C4 block reset + bit_offset: 7 + bit_size: 1 + - name: LPTIM2RST + description: LPTIM2 block reset + bit_offset: 9 + bit_size: 1 + - name: LPTIM3RST + description: LPTIM3 block reset + bit_offset: 10 + bit_size: 1 + - name: LPTIM4RST + description: LPTIM4 block reset + bit_offset: 11 + bit_size: 1 + - name: LPTIM5RST + description: LPTIM5 block reset + bit_offset: 12 + bit_size: 1 + - name: DAC2RST + description: DAC2 (containing one converter) reset + bit_offset: 13 + bit_size: 1 + - name: COMP12RST + description: COMP12 Blocks Reset + bit_offset: 14 + bit_size: 1 + - name: VREFRST + description: VREF block reset + bit_offset: 15 + bit_size: 1 + - name: SAI4RST + description: SAI4 block reset + bit_offset: 21 + bit_size: 1 + - name: DTSRST + description: Digital temperature sensor block reset + bit_offset: 26 + bit_size: 1 fieldset/BDCR: description: RCC Backup Domain Control Register fields: - - name: LSEON - description: LSE oscillator enabled - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: LSE oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: LSE oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: LSEDRV - description: LSE oscillator driving capability - bit_offset: 3 - bit_size: 2 - enum: LSEDRV - - name: LSECSSON - description: LSE clock security system enable - bit_offset: 5 - bit_size: 1 - - name: LSECSSD - description: LSE clock security system failure detection - bit_offset: 6 - bit_size: 1 - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: VSwitch domain software reset - bit_offset: 16 - bit_size: 1 + - name: LSEON + description: LSE oscillator enabled + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: LSE oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: LSE oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: LSE oscillator driving capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: LSE clock security system enable + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: LSE clock security system failure detection + bit_offset: 6 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: VSwitch domain software reset + bit_offset: 16 + bit_size: 1 fieldset/CFGR: description: RCC Clock Configuration Register fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 3 - enum: SW - - name: SWS - description: System clock switch status - bit_offset: 3 - bit_size: 3 - enum: SWS - - name: STOPWUCK - description: System clock selection after a wake up from system Stop - bit_offset: 6 - bit_size: 1 - enum: STOPWUCK - - name: STOPKERWUCK - description: Kernel clock selection after a wake up from system Stop - bit_offset: 7 - bit_size: 1 - enum: STOPWUCK - - name: RTCPRE - description: HSE division factor for RTC clock - bit_offset: 8 - bit_size: 6 - - name: HRTIMSEL - description: High Resolution Timer clock prescaler selection - bit_offset: 14 - bit_size: 1 - enum: HRTIMSEL - - name: TIMPRE - description: Timers clocks prescaler selection - bit_offset: 15 - bit_size: 1 - enum: TIMPRE - - name: MCO1PRE - description: MCO1 prescaler - bit_offset: 18 - bit_size: 4 - - name: MCO1 - description: Micro-controller clock output 1 - bit_offset: 22 - bit_size: 3 - enum: MCO1 - - name: MCO2PRE - description: MCO2 prescaler - bit_offset: 25 - bit_size: 4 - - name: MCO2 - description: Micro-controller clock output 2 - bit_offset: 29 - bit_size: 3 - enum: MCO2 + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 3 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 3 + bit_size: 3 + enum: SW + - name: STOPWUCK + description: System clock selection after a wake up from system Stop + bit_offset: 6 + bit_size: 1 + enum: STOPWUCK + - name: STOPKERWUCK + description: Kernel clock selection after a wake up from system Stop + bit_offset: 7 + bit_size: 1 + enum: STOPWUCK + - name: RTCPRE + description: HSE division factor for RTC clock + bit_offset: 8 + bit_size: 6 + - name: HRTIMSEL + description: High Resolution Timer clock prescaler selection + bit_offset: 14 + bit_size: 1 + enum: HRTIMSEL + - name: TIMPRE + description: Timers clocks prescaler selection + bit_offset: 15 + bit_size: 1 + enum: TIMPRE + - name: MCO1PRE + description: MCO1 prescaler + bit_offset: 18 + bit_size: 4 + - name: MCO1 + description: Micro-controller clock output 1 + bit_offset: 22 + bit_size: 3 + enum: MCO1 + - name: MCO2PRE + description: MCO2 prescaler + bit_offset: 25 + bit_size: 4 + - name: MCO2 + description: Micro-controller clock output 2 + bit_offset: 29 + bit_size: 3 + enum: MCO2 fieldset/CICR: description: RCC Clock Source Interrupt Clear Register fields: - - name: LSIRDYC - description: LSI ready Interrupt Clear - bit_offset: 0 - bit_size: 1 - - name: LSERDYC - description: LSE ready Interrupt Clear - bit_offset: 1 - bit_size: 1 - - name: HSIRDYC - description: HSI ready Interrupt Clear - bit_offset: 2 - bit_size: 1 - - name: HSERDYC - description: HSE ready Interrupt Clear - bit_offset: 3 - bit_size: 1 - - name: HSE_ready_Interrupt_Clear - description: CSI ready Interrupt Clear - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYC - description: RC48 ready Interrupt Clear - bit_offset: 5 - bit_size: 1 - - name: PLLRDYC - description: PLL1 ready Interrupt Clear - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: LSECSSC - description: LSE clock security system Interrupt Clear - bit_offset: 9 - bit_size: 1 - - name: HSECSSC - description: HSE clock security system Interrupt Clear - bit_offset: 10 - bit_size: 1 + - name: LSIRDYC + description: LSI ready Interrupt Clear + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: LSE ready Interrupt Clear + bit_offset: 1 + bit_size: 1 + - name: HSIRDYC + description: HSI ready Interrupt Clear + bit_offset: 2 + bit_size: 1 + - name: HSERDYC + description: HSE ready Interrupt Clear + bit_offset: 3 + bit_size: 1 + - name: HSE_ready_Interrupt_Clear + description: CSI ready Interrupt Clear + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYC + description: RC48 ready Interrupt Clear + bit_offset: 5 + bit_size: 1 + - name: PLLRDYC + description: PLL1 ready Interrupt Clear + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: LSECSSC + description: LSE clock security system Interrupt Clear + bit_offset: 9 + bit_size: 1 + - name: HSECSSC + description: HSE clock security system Interrupt Clear + bit_offset: 10 + bit_size: 1 fieldset/CIER: description: RCC Clock Source Interrupt Enable Register fields: - - name: LSIRDYIE - description: LSI ready Interrupt Enable - bit_offset: 0 - bit_size: 1 - - name: LSERDYIE - description: LSE ready Interrupt Enable - bit_offset: 1 - bit_size: 1 - - name: HSIRDYIE - description: HSI ready Interrupt Enable - bit_offset: 2 - bit_size: 1 - - name: HSERDYIE - description: HSE ready Interrupt Enable - bit_offset: 3 - bit_size: 1 - - name: CSIRDYIE - description: CSI ready Interrupt Enable - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYIE - description: RC48 ready Interrupt Enable - bit_offset: 5 - bit_size: 1 - - name: PLLRDYIE - description: PLL1 ready Interrupt Enable - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: LSECSSIE - description: LSE clock security system Interrupt Enable - bit_offset: 9 - bit_size: 1 + - name: LSIRDYIE + description: LSI ready Interrupt Enable + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: LSE ready Interrupt Enable + bit_offset: 1 + bit_size: 1 + - name: HSIRDYIE + description: HSI ready Interrupt Enable + bit_offset: 2 + bit_size: 1 + - name: HSERDYIE + description: HSE ready Interrupt Enable + bit_offset: 3 + bit_size: 1 + - name: CSIRDYIE + description: CSI ready Interrupt Enable + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYIE + description: RC48 ready Interrupt Enable + bit_offset: 5 + bit_size: 1 + - name: PLLRDYIE + description: PLL1 ready Interrupt Enable + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: LSECSSIE + description: LSE clock security system Interrupt Enable + bit_offset: 9 + bit_size: 1 fieldset/CIFR: description: RCC Clock Source Interrupt Flag Register fields: - - name: LSIRDYF - description: LSI ready Interrupt Flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE ready Interrupt Flag - bit_offset: 1 - bit_size: 1 - - name: HSIRDYF - description: HSI ready Interrupt Flag - bit_offset: 2 - bit_size: 1 - - name: HSERDYF - description: HSE ready Interrupt Flag - bit_offset: 3 - bit_size: 1 - - name: CSIRDY - description: CSI ready Interrupt Flag - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYF - description: RC48 ready Interrupt Flag - bit_offset: 5 - bit_size: 1 - - name: PLLRDYF - description: PLL1 ready Interrupt Flag - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: LSECSSF - description: LSE clock security system Interrupt Flag - bit_offset: 9 - bit_size: 1 - - name: HSECSSF - description: HSE clock security system Interrupt Flag - bit_offset: 10 - bit_size: 1 + - name: LSIRDYF + description: LSI ready Interrupt Flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready Interrupt Flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI ready Interrupt Flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE ready Interrupt Flag + bit_offset: 3 + bit_size: 1 + - name: CSIRDY + description: CSI ready Interrupt Flag + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYF + description: RC48 ready Interrupt Flag + bit_offset: 5 + bit_size: 1 + - name: PLLRDYF + description: PLL1 ready Interrupt Flag + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: LSECSSF + description: LSE clock security system Interrupt Flag + bit_offset: 9 + bit_size: 1 + - name: HSECSSF + description: HSE clock security system Interrupt Flag + bit_offset: 10 + bit_size: 1 fieldset/CR: description: clock control register fields: - - name: HSION - description: Internal high-speed clock enable - bit_offset: 0 - bit_size: 1 - - name: HSIKERON - description: High Speed Internal clock enable in Stop mode - bit_offset: 1 - bit_size: 1 - - name: HSIRDY - description: HSI clock ready flag - bit_offset: 2 - bit_size: 1 - - name: HSIDIV - description: HSI clock divider - bit_offset: 3 - bit_size: 2 - enum: HSIDIV - - name: HSIDIVF - description: HSI divider flag - bit_offset: 5 - bit_size: 1 - - name: CSION - description: CSI clock enable - bit_offset: 7 - bit_size: 1 - - name: CSIRDY - description: CSI clock ready flag - bit_offset: 8 - bit_size: 1 - - name: CSIKERON - description: CSI clock enable in Stop mode - bit_offset: 9 - bit_size: 1 - - name: HSI48ON - description: RC48 clock enable - bit_offset: 12 - bit_size: 1 - - name: HSI48RDY - description: RC48 clock ready flag - bit_offset: 13 - bit_size: 1 - - name: D1CKRDY - description: D1 domain clocks ready flag - bit_offset: 14 - bit_size: 1 - - name: D2CKRDY - description: D2 domain clocks ready flag - bit_offset: 15 - bit_size: 1 - - name: HSEON - description: HSE clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: HSE clock bypass - bit_offset: 18 - bit_size: 1 - - name: HSECSSON - description: HSE Clock Security System enable - bit_offset: 19 - bit_size: 1 - - name: PLLON - description: PLL1 enable - bit_offset: 24 - bit_size: 1 - array: - len: 3 - stride: 2 - - name: PLLRDY - description: PLL1 clock ready flag - bit_offset: 25 - bit_size: 1 - array: - len: 3 - stride: 2 + - name: HSION + description: Internal high-speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIKERON + description: High Speed Internal clock enable in Stop mode + bit_offset: 1 + bit_size: 1 + - name: HSIRDY + description: HSI clock ready flag + bit_offset: 2 + bit_size: 1 + - name: HSIDIV + description: HSI clock divider + bit_offset: 3 + bit_size: 2 + enum: HSIDIV + - name: HSIDIVF + description: HSI divider flag + bit_offset: 5 + bit_size: 1 + - name: CSION + description: CSI clock enable + bit_offset: 7 + bit_size: 1 + - name: CSIRDY + description: CSI clock ready flag + bit_offset: 8 + bit_size: 1 + - name: CSIKERON + description: CSI clock enable in Stop mode + bit_offset: 9 + bit_size: 1 + - name: HSI48ON + description: RC48 clock enable + bit_offset: 12 + bit_size: 1 + - name: HSI48RDY + description: RC48 clock ready flag + bit_offset: 13 + bit_size: 1 + - name: D1CKRDY + description: D1 domain clocks ready flag + bit_offset: 14 + bit_size: 1 + - name: D2CKRDY + description: D2 domain clocks ready flag + bit_offset: 15 + bit_size: 1 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: HSE clock bypass + bit_offset: 18 + bit_size: 1 + - name: HSECSSON + description: HSE Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL1 enable + bit_offset: 24 + bit_size: 1 + array: + len: 3 + stride: 2 + - name: PLLRDY + description: PLL1 clock ready flag + bit_offset: 25 + bit_size: 1 + array: + len: 3 + stride: 2 fieldset/CRRCR: description: RCC Clock Recovery RC Register fields: - - name: HSI48CAL - description: Internal RC 48 MHz clock calibration - bit_offset: 0 - bit_size: 10 + - name: HSI48CAL + description: Internal RC 48 MHz clock calibration + bit_offset: 0 + bit_size: 10 fieldset/CSICFGR: description: RCC CSI configuration register fields: - - name: CSICAL - description: CSI clock calibration - bit_offset: 0 - bit_size: 9 - - name: CSITRIM - description: CSI clock trimming - bit_offset: 24 - bit_size: 6 + - name: CSICAL + description: CSI clock calibration + bit_offset: 0 + bit_size: 9 + - name: CSITRIM + description: CSI clock trimming + bit_offset: 24 + bit_size: 6 fieldset/CSR: description: RCC Clock Control and Status Register fields: - - name: LSION - description: LSI oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: LSI oscillator ready - bit_offset: 1 - bit_size: 1 + - name: LSION + description: LSI oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: LSI oscillator ready + bit_offset: 1 + bit_size: 1 fieldset/D1CCIPR: description: RCC Domain 1 Kernel Clock Configuration Register fields: - - name: FMCSEL - description: FMC kernel clock source selection - bit_offset: 0 - bit_size: 2 - enum: FMCSEL - - name: OCTOSPISEL - description: OCTOSPI kernel clock source selection - bit_offset: 4 - bit_size: 2 - enum: FMCSEL - - name: DSISEL - description: kernel clock source selection - bit_offset: 8 - bit_size: 1 - - name: SDMMCSEL - description: SDMMC kernel clock source selection - bit_offset: 16 - bit_size: 1 - enum: SDMMCSEL - - name: CKPERSEL - description: per_ck clock source selection - bit_offset: 28 - bit_size: 2 - enum: CKPERSEL + - name: FMCSEL + description: FMC kernel clock source selection + bit_offset: 0 + bit_size: 2 + enum: FMCSEL + - name: OCTOSPISEL + description: OCTOSPI kernel clock source selection + bit_offset: 4 + bit_size: 2 + enum: FMCSEL + - name: DSISEL + description: kernel clock source selection + bit_offset: 8 + bit_size: 1 + - name: SDMMCSEL + description: SDMMC kernel clock source selection + bit_offset: 16 + bit_size: 1 + enum: SDMMCSEL + - name: CKPERSEL + description: per_ck clock source selection + bit_offset: 28 + bit_size: 2 + enum: CKPERSEL fieldset/D1CFGR: description: RCC Domain 1 Clock Configuration Register fields: - - name: HPRE - description: D1 domain AHB prescaler - bit_offset: 0 - bit_size: 4 - enum: HPRE - - name: D1PPRE - description: D1 domain APB3 prescaler - bit_offset: 4 - bit_size: 3 - enum: DPPRE - - name: D1CPRE - description: D1 domain Core prescaler - bit_offset: 8 - bit_size: 4 - enum: HPRE + - name: HPRE + description: D1 domain AHB prescaler + bit_offset: 0 + bit_size: 4 + enum: HPRE + - name: D1PPRE + description: D1 domain APB3 prescaler + bit_offset: 4 + bit_size: 3 + enum: PPRE + - name: D1CPRE + description: D1 domain Core prescaler + bit_offset: 8 + bit_size: 4 + enum: HPRE fieldset/D2CCIP1R: description: RCC Domain 2 Kernel Clock Configuration Register fields: - - name: SAI1SEL - description: SAI1 and DFSDM1 kernel Aclk clock source selection - bit_offset: 0 - bit_size: 3 - enum: SAISEL - - name: SAI2ASEL - description: SAI2 kernel clock source A source selection - bit_offset: 6 - bit_size: 3 - enum: SAIASEL - - name: SAI2BSEL - description: SAI2 kernel clock source B source selection - bit_offset: 9 - bit_size: 3 - enum: SAIASEL - - name: SPI123SEL - description: "SPI/I2S1,2 and 3 kernel clock source selection" - bit_offset: 12 - bit_size: 3 - enum: SAISEL - - name: SPI45SEL - description: SPI4 and 5 kernel clock source selection - bit_offset: 16 - bit_size: 3 - enum: SPI45SEL - - name: SPDIFRXSEL - description: SPDIFRX kernel clock source selection - bit_offset: 20 - bit_size: 2 - enum: SPDIFRXSEL - - name: DFSDM1SEL - description: DFSDM1 kernel Clk clock source selection - bit_offset: 24 - bit_size: 1 - enum: DFSDMSEL - - name: FDCANSEL - description: FDCAN kernel clock source selection - bit_offset: 28 - bit_size: 2 - enum: FDCANSEL - - name: SWPSEL - description: SWPMI kernel clock source selection - bit_offset: 31 - bit_size: 1 - enum: SWPSEL + - name: SAI1SEL + description: SAI1 and DFSDM1 kernel Aclk clock source selection + bit_offset: 0 + bit_size: 3 + enum: SAISEL + - name: SAI2ASEL + description: SAI2 kernel clock source A source selection + bit_offset: 6 + bit_size: 3 + enum: SAIASEL + - name: SAI2BSEL + description: SAI2 kernel clock source B source selection + bit_offset: 9 + bit_size: 3 + enum: SAIASEL + - name: SPI123SEL + description: SPI/I2S1,2 and 3 kernel clock source selection + bit_offset: 12 + bit_size: 3 + enum: SAISEL + - name: SPI45SEL + description: SPI4 and 5 kernel clock source selection + bit_offset: 16 + bit_size: 3 + enum: SPI45SEL + - name: SPDIFRXSEL + description: SPDIFRX kernel clock source selection + bit_offset: 20 + bit_size: 2 + enum: SPDIFRXSEL + - name: DFSDM1SEL + description: DFSDM1 kernel Clk clock source selection + bit_offset: 24 + bit_size: 1 + enum: DFSDMSEL + - name: FDCANSEL + description: FDCAN kernel clock source selection + bit_offset: 28 + bit_size: 2 + enum: FDCANSEL + - name: SWPSEL + description: SWPMI kernel clock source selection + bit_offset: 31 + bit_size: 1 + enum: SWPSEL fieldset/D2CCIP2R: description: RCC Domain 2 Kernel Clock Configuration Register fields: - - name: USART234578SEL - description: "USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection" - bit_offset: 0 - bit_size: 3 - enum: USART234578SEL - - name: USART16910SEL - description: "USART1, 6, 9 and 10 kernel clock source selection" - bit_offset: 3 - bit_size: 3 - enum: USART16910SEL - - name: RNGSEL - description: RNG kernel clock source selection - bit_offset: 8 - bit_size: 2 - enum: RNGSEL - - name: I2C1235SEL - description: "I2C1,2,3 kernel clock source selection" - bit_offset: 12 - bit_size: 2 - enum: I2C1235SEL - - name: USBSEL - description: USBOTG 1 and 2 kernel clock source selection - bit_offset: 20 - bit_size: 2 - enum: USBSEL - - name: CECSEL - description: HDMI-CEC kernel clock source selection - bit_offset: 22 - bit_size: 2 - enum: CECSEL - - name: LPTIM1SEL - description: LPTIM1 kernel clock source selection - bit_offset: 28 - bit_size: 3 - enum: LPTIM1SEL + - name: USART234578SEL + description: USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection + bit_offset: 0 + bit_size: 3 + enum: USART234578SEL + - name: USART16910SEL + description: USART1, 6, 9 and 10 kernel clock source selection + bit_offset: 3 + bit_size: 3 + enum: USART16910SEL + - name: RNGSEL + description: RNG kernel clock source selection + bit_offset: 8 + bit_size: 2 + enum: RNGSEL + - name: I2C1235SEL + description: I2C1,2,3 kernel clock source selection + bit_offset: 12 + bit_size: 2 + enum: I2C1235SEL + - name: USBSEL + description: USBOTG 1 and 2 kernel clock source selection + bit_offset: 20 + bit_size: 2 + enum: USBSEL + - name: CECSEL + description: HDMI-CEC kernel clock source selection + bit_offset: 22 + bit_size: 2 + enum: CECSEL + - name: LPTIM1SEL + description: LPTIM1 kernel clock source selection + bit_offset: 28 + bit_size: 3 + enum: LPTIM1SEL fieldset/D2CFGR: description: RCC Domain 2 Clock Configuration Register fields: - - name: D2PPRE1 - description: D2 domain APB1 prescaler - bit_offset: 4 - bit_size: 3 - enum: DPPRE - - name: D2PPRE2 - description: D2 domain APB2 prescaler - bit_offset: 8 - bit_size: 3 - enum: DPPRE + - name: D2PPRE1 + description: D2 domain APB1 prescaler + bit_offset: 4 + bit_size: 3 + enum: PPRE + - name: D2PPRE2 + description: D2 domain APB2 prescaler + bit_offset: 8 + bit_size: 3 + enum: PPRE fieldset/D3AMR: description: RCC D3 Autonomous mode Register fields: - - name: BDMA2AMEN - description: BDMA2 and DMAMUX Autonomous mode enable - bit_offset: 0 - bit_size: 1 - - name: BDMAAMEN - description: BDMA and DMAMUX Autonomous mode enable - bit_offset: 0 - bit_size: 1 - - name: LPUART1AMEN - description: LPUART1 Autonomous mode enable - bit_offset: 3 - bit_size: 1 - - name: SPI6AMEN - description: SPI6 Autonomous mode enable - bit_offset: 5 - bit_size: 1 - - name: I2C4AMEN - description: I2C4 Autonomous mode enable - bit_offset: 7 - bit_size: 1 - - name: LPTIM2AMEN - description: LPTIM2 Autonomous mode enable - bit_offset: 9 - bit_size: 1 - - name: LPTIM3AMEN - description: LPTIM3 Autonomous mode enable - bit_offset: 10 - bit_size: 1 - - name: LPTIM4AMEN - description: LPTIM4 Autonomous mode enable - bit_offset: 11 - bit_size: 1 - - name: LPTIM5AMEN - description: LPTIM5 Autonomous mode enable - bit_offset: 12 - bit_size: 1 - - name: DAC2AMEN - description: DAC2 (containing one converter) Autonomous mode enable - bit_offset: 13 - bit_size: 1 - - name: COMP12AMEN - description: COMP12 Autonomous mode enable - bit_offset: 14 - bit_size: 1 - - name: VREFAMEN - description: VREF Autonomous mode enable - bit_offset: 15 - bit_size: 1 - - name: RTCAMEN - description: RTC Autonomous mode enable - bit_offset: 16 - bit_size: 1 - - name: CRCAMEN - description: CRC Autonomous mode enable - bit_offset: 19 - bit_size: 1 - - name: SAI4AMEN - description: SAI4 Autonomous mode enable - bit_offset: 21 - bit_size: 1 - - name: ADC3AMEN - description: ADC3 Autonomous mode enable - bit_offset: 24 - bit_size: 1 - - name: DTSAMEN - description: Digital temperature sensor Autonomous mode enable - bit_offset: 26 - bit_size: 1 - - name: BKPSRAMAMEN - description: Backup RAM Autonomous mode enable - bit_offset: 28 - bit_size: 1 - - name: SRAM4AMEN - description: SRAM4 Autonomous mode enable - bit_offset: 29 - bit_size: 1 + - name: BDMA2AMEN + description: BDMA2 and DMAMUX Autonomous mode enable + bit_offset: 0 + bit_size: 1 + - name: BDMAAMEN + description: BDMA and DMAMUX Autonomous mode enable + bit_offset: 0 + bit_size: 1 + - name: LPUART1AMEN + description: LPUART1 Autonomous mode enable + bit_offset: 3 + bit_size: 1 + - name: SPI6AMEN + description: SPI6 Autonomous mode enable + bit_offset: 5 + bit_size: 1 + - name: I2C4AMEN + description: I2C4 Autonomous mode enable + bit_offset: 7 + bit_size: 1 + - name: LPTIM2AMEN + description: LPTIM2 Autonomous mode enable + bit_offset: 9 + bit_size: 1 + - name: LPTIM3AMEN + description: LPTIM3 Autonomous mode enable + bit_offset: 10 + bit_size: 1 + - name: LPTIM4AMEN + description: LPTIM4 Autonomous mode enable + bit_offset: 11 + bit_size: 1 + - name: LPTIM5AMEN + description: LPTIM5 Autonomous mode enable + bit_offset: 12 + bit_size: 1 + - name: DAC2AMEN + description: DAC2 (containing one converter) Autonomous mode enable + bit_offset: 13 + bit_size: 1 + - name: COMP12AMEN + description: COMP12 Autonomous mode enable + bit_offset: 14 + bit_size: 1 + - name: VREFAMEN + description: VREF Autonomous mode enable + bit_offset: 15 + bit_size: 1 + - name: RTCAMEN + description: RTC Autonomous mode enable + bit_offset: 16 + bit_size: 1 + - name: CRCAMEN + description: CRC Autonomous mode enable + bit_offset: 19 + bit_size: 1 + - name: SAI4AMEN + description: SAI4 Autonomous mode enable + bit_offset: 21 + bit_size: 1 + - name: ADC3AMEN + description: ADC3 Autonomous mode enable + bit_offset: 24 + bit_size: 1 + - name: DTSAMEN + description: Digital temperature sensor Autonomous mode enable + bit_offset: 26 + bit_size: 1 + - name: BKPSRAMAMEN + description: Backup RAM Autonomous mode enable + bit_offset: 28 + bit_size: 1 + - name: SRAM4AMEN + description: SRAM4 Autonomous mode enable + bit_offset: 29 + bit_size: 1 fieldset/D3CCIPR: description: RCC Domain 3 Kernel Clock Configuration Register fields: - - name: LPUART1SEL - description: LPUART1 kernel clock source selection - bit_offset: 0 - bit_size: 3 - enum: LPUARTSEL - - name: I2C4SEL - description: I2C4 kernel clock source selection - bit_offset: 8 - bit_size: 2 - enum: I2C4SEL - - name: LPTIM2SEL - description: LPTIM2 kernel clock source selection - bit_offset: 10 - bit_size: 3 - enum: LPTIM2SEL - - name: LPTIM345SEL - description: "LPTIM3,4,5 kernel clock source selection" - bit_offset: 13 - bit_size: 3 - enum: LPTIM2SEL - - name: ADCSEL - description: SAR ADC kernel clock source selection - bit_offset: 16 - bit_size: 2 - enum: ADCSEL - - name: DFSDM2SEL - description: DFSDM2 kernel clock source selection - bit_offset: 27 - bit_size: 1 - - name: SPI6SEL - description: SPI6 kernel clock source selection - bit_offset: 28 - bit_size: 3 - enum: SPI6SEL + - name: LPUART1SEL + description: LPUART1 kernel clock source selection + bit_offset: 0 + bit_size: 3 + enum: LPUARTSEL + - name: I2C4SEL + description: I2C4 kernel clock source selection + bit_offset: 8 + bit_size: 2 + enum: I2C4SEL + - name: LPTIM2SEL + description: LPTIM2 kernel clock source selection + bit_offset: 10 + bit_size: 3 + enum: LPTIM2SEL + - name: LPTIM345SEL + description: LPTIM3,4,5 kernel clock source selection + bit_offset: 13 + bit_size: 3 + enum: LPTIM2SEL + - name: ADCSEL + description: SAR ADC kernel clock source selection + bit_offset: 16 + bit_size: 2 + enum: ADCSEL + - name: DFSDM2SEL + description: DFSDM2 kernel clock source selection + bit_offset: 27 + bit_size: 1 + - name: SPI6SEL + description: SPI6 kernel clock source selection + bit_offset: 28 + bit_size: 3 + enum: SPI6SEL fieldset/D3CFGR: description: RCC Domain 3 Clock Configuration Register fields: - - name: D3PPRE - description: D3 domain APB4 prescaler - bit_offset: 4 - bit_size: 3 - enum: DPPRE + - name: D3PPRE + description: D3 domain APB4 prescaler + bit_offset: 4 + bit_size: 3 + enum: PPRE fieldset/GCR: description: Global Control Register fields: - - name: WW1RSC - description: WWDG1 reset scope control - bit_offset: 0 - bit_size: 1 + - name: WW1RSC + description: WWDG1 reset scope control + bit_offset: 0 + bit_size: 1 fieldset/HSICFGR: description: RCC HSI configuration register fields: - - name: HSICAL - description: HSI clock calibration - bit_offset: 0 - bit_size: 12 - - name: HSITRIM - description: HSI clock trimming - bit_offset: 24 - bit_size: 7 -fieldset/PLL1DIVR: - description: RCC PLL1 Dividers Configuration Register - fields: - - name: DIVN1 - description: Multiplication factor for PLL1 VCO - bit_offset: 0 - bit_size: 9 - - name: DIVP1 - description: PLL1 DIVP division factor - bit_offset: 9 - bit_size: 7 - enum: DIVP - - name: DIVQ1 - description: PLL1 DIVQ division factor - bit_offset: 16 - bit_size: 7 - - name: DIVR1 - description: PLL1 DIVR division factor - bit_offset: 24 - bit_size: 7 -fieldset/PLL1FRACR: - description: RCC PLL1 Fractional Divider Register - fields: - - name: FRACN1 - description: Fractional part of the multiplication factor for PLL1 VCO - bit_offset: 3 - bit_size: 13 -fieldset/PLL2DIVR: - description: RCC PLL2 Dividers Configuration Register - fields: - - name: DIVN2 - description: Multiplication factor for PLL1 VCO - bit_offset: 0 - bit_size: 9 - - name: DIVP2 - description: PLL1 DIVP division factor - bit_offset: 9 - bit_size: 7 - - name: DIVQ2 - description: PLL1 DIVQ division factor - bit_offset: 16 - bit_size: 7 - - name: DIVR2 - description: PLL1 DIVR division factor - bit_offset: 24 - bit_size: 7 -fieldset/PLL2FRACR: - description: RCC PLL2 Fractional Divider Register - fields: - - name: FRACN2 - description: Fractional part of the multiplication factor for PLL VCO - bit_offset: 3 - bit_size: 13 -fieldset/PLL3DIVR: - description: RCC PLL3 Dividers Configuration Register - fields: - - name: DIVN3 - description: Multiplication factor for PLL1 VCO - bit_offset: 0 - bit_size: 9 - - name: DIVP3 - description: PLL DIVP division factor - bit_offset: 9 - bit_size: 7 - - name: DIVQ3 - description: PLL DIVQ division factor - bit_offset: 16 - bit_size: 7 - - name: DIVR3 - description: PLL DIVR division factor - bit_offset: 24 - bit_size: 7 -fieldset/PLL3FRACR: - description: RCC PLL3 Fractional Divider Register - fields: - - name: FRACN3 - description: Fractional part of the multiplication factor for PLL3 VCO - bit_offset: 3 - bit_size: 13 + - name: HSICAL + description: HSI clock calibration + bit_offset: 0 + bit_size: 12 + - name: HSITRIM + description: HSI clock trimming + bit_offset: 24 + bit_size: 7 fieldset/PLLCFGR: description: RCC PLLs Configuration Register fields: - - name: PLLFRACEN - description: PLL1 fractional latch enable - bit_offset: 0 - bit_size: 1 - array: - len: 3 - stride: 4 - - name: PLLVCOSEL - description: PLL1 VCO selection - bit_offset: 1 - bit_size: 1 - array: - len: 3 - stride: 4 - enum: PLLVCOSEL - - name: PLLRGE - description: PLL1 input frequency range - bit_offset: 2 - bit_size: 2 - array: - len: 3 - stride: 4 - enum: PLLRGE - - name: DIVPEN - description: PLL1 DIVP divider output enable - bit_offset: 16 - bit_size: 1 - array: - len: 3 - stride: 3 - - name: DIVQEN - description: PLL1 DIVQ divider output enable - bit_offset: 17 - bit_size: 1 - array: - len: 3 - stride: 3 - - name: DIVREN - description: PLL1 DIVR divider output enable - bit_offset: 18 - bit_size: 1 - array: - len: 3 - stride: 3 + - name: PLLFRACEN + description: PLL1 fractional latch enable + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 4 + - name: PLLVCOSEL + description: PLL1 VCO selection + bit_offset: 1 + bit_size: 1 + array: + len: 3 + stride: 4 + enum: PLLVCOSEL + - name: PLLRGE + description: PLL1 input frequency range + bit_offset: 2 + bit_size: 2 + array: + len: 3 + stride: 4 + enum: PLLRGE + - name: DIVPEN + description: PLL1 DIVP divider output enable + bit_offset: 16 + bit_size: 1 + array: + len: 3 + stride: 3 + - name: DIVQEN + description: PLL1 DIVQ divider output enable + bit_offset: 17 + bit_size: 1 + array: + len: 3 + stride: 3 + - name: DIVREN + description: PLL1 DIVR divider output enable + bit_offset: 18 + bit_size: 1 + array: + len: 3 + stride: 3 fieldset/PLLCKSELR: description: RCC PLLs Clock Source Selection Register fields: - - name: PLLSRC - description: DIVMx and PLLs clock source selection - bit_offset: 0 - bit_size: 2 - enum: PLLSRC - - name: DIVM - description: Prescaler for PLL1 - bit_offset: 4 - bit_size: 6 - array: - len: 3 - stride: 8 + - name: PLLSRC + description: DIVMx and PLLs clock source selection + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: DIVM + description: Prescaler for PLL1 + bit_offset: 4 + bit_size: 6 + array: + len: 3 + stride: 8 +fieldset/PLLDIVR: + description: RCC PLL1 Dividers Configuration Register + fields: + - name: PLLN + description: Multiplication factor for PLL1 VCO + bit_offset: 0 + bit_size: 9 + - name: PLLP + description: PLL DIVP division factor + bit_offset: 9 + bit_size: 7 + - name: PLLQ + description: PLL DIVQ division factor + bit_offset: 16 + bit_size: 7 + - name: PLLR + description: PLL DIVR division factor + bit_offset: 24 + bit_size: 7 +fieldset/PLLFRACR: + description: RCC PLL Fractional Divider Register + fields: + - name: FRACN + description: Fractional part of the multiplication factor for PLL VCO + bit_offset: 3 + bit_size: 13 fieldset/RSR: description: RCC Reset Status Register fields: - - name: RMVF - description: Remove reset flag - bit_offset: 16 - bit_size: 1 - - name: CPURSTF - description: CPU reset flag - bit_offset: 17 - bit_size: 1 - - name: D1RSTF - description: D1 domain power switch reset flag - bit_offset: 19 - bit_size: 1 - - name: D2RSTF - description: D2 domain power switch reset flag - bit_offset: 20 - bit_size: 1 - - name: BORRSTF - description: BOR reset flag - bit_offset: 21 - bit_size: 1 - - name: PINRSTF - description: Pin reset flag (NRST) - bit_offset: 22 - bit_size: 1 - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 23 - bit_size: 1 - - name: SFTRSTF - description: System reset from CPU reset flag - bit_offset: 24 - bit_size: 1 - - name: IWDG1RSTF - description: Independent Watchdog reset flag - bit_offset: 26 - bit_size: 1 - - name: WWDG1RSTF - description: Window Watchdog reset flag - bit_offset: 28 - bit_size: 1 - - name: LPWRRSTF - description: Reset due to illegal D1 DStandby or CPU CStop flag - bit_offset: 30 - bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 16 + bit_size: 1 + - name: CPURSTF + description: CPU reset flag + bit_offset: 17 + bit_size: 1 + - name: D1RSTF + description: D1 domain power switch reset flag + bit_offset: 19 + bit_size: 1 + - name: D2RSTF + description: D2 domain power switch reset flag + bit_offset: 20 + bit_size: 1 + - name: BORRSTF + description: BOR reset flag + bit_offset: 21 + bit_size: 1 + - name: PINRSTF + description: Pin reset flag (NRST) + bit_offset: 22 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 23 + bit_size: 1 + - name: SFTRSTF + description: System reset from CPU reset flag + bit_offset: 24 + bit_size: 1 + - name: IWDG1RSTF + description: Independent Watchdog reset flag + bit_offset: 26 + bit_size: 1 + - name: WWDG1RSTF + description: Window Watchdog reset flag + bit_offset: 28 + bit_size: 1 + - name: LPWRRSTF + description: Reset due to illegal D1 DStandby or CPU CStop flag + bit_offset: 30 + bit_size: 1 enum/ADCSEL: bit_size: 2 variants: - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 0 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 1 - - name: PER - description: PER selected as peripheral clock - value: 2 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: PER + description: PER selected as peripheral clock + value: 2 enum/CECSEL: bit_size: 2 variants: - - name: LSE - description: LSE selected as peripheral clock - value: 0 - - name: LSI - description: LSI selected as peripheral clock - value: 1 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 2 + - name: LSE + description: LSE selected as peripheral clock + value: 0 + - name: LSI + description: LSI selected as peripheral clock + value: 1 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 2 enum/CKPERSEL: bit_size: 2 variants: - - name: HSI - description: HSI selected as peripheral clock - value: 0 - - name: CSI - description: CSI selected as peripheral clock - value: 1 - - name: HSE - description: HSE selected as peripheral clock - value: 2 + - name: HSI + description: HSI selected as peripheral clock + value: 0 + - name: CSI + description: CSI selected as peripheral clock + value: 1 + - name: HSE + description: HSE selected as peripheral clock + value: 2 enum/DFSDMSEL: bit_size: 1 variants: - - name: RCC_PCLK2 - description: rcc_pclk2 selected as peripheral clock - value: 0 - - name: SYS - description: System clock selected as peripheral clock - value: 1 -enum/DIVP: - bit_size: 7 - variants: - - name: Div1 - description: pll_p_ck = vco_ck - value: 0 - - name: Div2 - description: pll_p_ck = vco_ck / 2 - value: 1 - - name: Div4 - description: pll_p_ck = vco_ck / 4 - value: 3 - - name: Div6 - description: pll_p_ck = vco_ck / 6 - value: 5 - - name: Div8 - description: pll_p_ck = vco_ck / 8 - value: 7 - - name: Div10 - description: pll_p_ck = vco_ck / 10 - value: 9 - - name: Div12 - description: pll_p_ck = vco_ck / 12 - value: 11 - - name: Div14 - description: pll_p_ck = vco_ck / 14 - value: 13 - - name: Div16 - description: pll_p_ck = vco_ck / 16 - value: 15 - - name: Div18 - description: pll_p_ck = vco_ck / 18 - value: 17 - - name: Div20 - description: pll_p_ck = vco_ck / 20 - value: 19 - - name: Div22 - description: pll_p_ck = vco_ck / 22 - value: 21 - - name: Div24 - description: pll_p_ck = vco_ck / 24 - value: 23 - - name: Div26 - description: pll_p_ck = vco_ck / 26 - value: 25 - - name: Div28 - description: pll_p_ck = vco_ck / 28 - value: 27 - - name: Div30 - description: pll_p_ck = vco_ck / 30 - value: 29 - - name: Div32 - description: pll_p_ck = vco_ck / 32 - value: 31 - - name: Div34 - description: pll_p_ck = vco_ck / 34 - value: 33 - - name: Div36 - description: pll_p_ck = vco_ck / 36 - value: 35 - - name: Div38 - description: pll_p_ck = vco_ck / 38 - value: 37 - - name: Div40 - description: pll_p_ck = vco_ck / 40 - value: 39 - - name: Div42 - description: pll_p_ck = vco_ck / 42 - value: 41 - - name: Div44 - description: pll_p_ck = vco_ck / 44 - value: 43 - - name: Div46 - description: pll_p_ck = vco_ck / 46 - value: 45 - - name: Div48 - description: pll_p_ck = vco_ck / 48 - value: 47 - - name: Div50 - description: pll_p_ck = vco_ck / 50 - value: 49 - - name: Div52 - description: pll_p_ck = vco_ck / 52 - value: 51 - - name: Div54 - description: pll_p_ck = vco_ck / 54 - value: 53 - - name: Div56 - description: pll_p_ck = vco_ck / 56 - value: 55 - - name: Div58 - description: pll_p_ck = vco_ck / 58 - value: 57 - - name: Div60 - description: pll_p_ck = vco_ck / 60 - value: 59 - - name: Div62 - description: pll_p_ck = vco_ck / 62 - value: 61 - - name: Div64 - description: pll_p_ck = vco_ck / 64 - value: 63 - - name: Div66 - description: pll_p_ck = vco_ck / 66 - value: 65 - - name: Div68 - description: pll_p_ck = vco_ck / 68 - value: 67 - - name: Div70 - description: pll_p_ck = vco_ck / 70 - value: 69 - - name: Div72 - description: pll_p_ck = vco_ck / 72 - value: 71 - - name: Div74 - description: pll_p_ck = vco_ck / 74 - value: 73 - - name: Div76 - description: pll_p_ck = vco_ck / 76 - value: 75 - - name: Div78 - description: pll_p_ck = vco_ck / 78 - value: 77 - - name: Div80 - description: pll_p_ck = vco_ck / 80 - value: 79 - - name: Div82 - description: pll_p_ck = vco_ck / 82 - value: 81 - - name: Div84 - description: pll_p_ck = vco_ck / 84 - value: 83 - - name: Div86 - description: pll_p_ck = vco_ck / 86 - value: 85 - - name: Div88 - description: pll_p_ck = vco_ck / 88 - value: 87 - - name: Div90 - description: pll_p_ck = vco_ck / 90 - value: 89 - - name: Div92 - description: pll_p_ck = vco_ck / 92 - value: 91 - - name: Div94 - description: pll_p_ck = vco_ck / 94 - value: 93 - - name: Div96 - description: pll_p_ck = vco_ck / 96 - value: 95 - - name: Div98 - description: pll_p_ck = vco_ck / 98 - value: 97 - - name: Div100 - description: pll_p_ck = vco_ck / 100 - value: 99 - - name: Div102 - description: pll_p_ck = vco_ck / 102 - value: 101 - - name: Div104 - description: pll_p_ck = vco_ck / 104 - value: 103 - - name: Div106 - description: pll_p_ck = vco_ck / 106 - value: 105 - - name: Div108 - description: pll_p_ck = vco_ck / 108 - value: 107 - - name: Div110 - description: pll_p_ck = vco_ck / 110 - value: 109 - - name: Div112 - description: pll_p_ck = vco_ck / 112 - value: 111 - - name: Div114 - description: pll_p_ck = vco_ck / 114 - value: 113 - - name: Div116 - description: pll_p_ck = vco_ck / 116 - value: 115 - - name: Div118 - description: pll_p_ck = vco_ck / 118 - value: 117 - - name: Div120 - description: pll_p_ck = vco_ck / 120 - value: 119 - - name: Div122 - description: pll_p_ck = vco_ck / 122 - value: 121 - - name: Div124 - description: pll_p_ck = vco_ck / 124 - value: 123 - - name: Div126 - description: pll_p_ck = vco_ck / 126 - value: 125 - - name: Div128 - description: pll_p_ck = vco_ck / 128 - value: 127 -enum/DPPRE: - bit_size: 3 - variants: - - name: Div1 - description: rcc_hclk not divided - value: 0 - - name: Div2 - description: rcc_hclk divided by 2 - value: 4 - - name: Div4 - description: rcc_hclk divided by 4 - value: 5 - - name: Div8 - description: rcc_hclk divided by 8 - value: 6 - - name: Div16 - description: rcc_hclk divided by 16 - value: 7 + - name: RCC_PCLK2 + description: rcc_pclk2 selected as peripheral clock + value: 0 + - name: SYS + description: System clock selected as peripheral clock + value: 1 enum/FDCANSEL: bit_size: 2 variants: - - name: HSE - description: HSE selected as peripheral clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 2 + - name: HSE + description: HSE selected as peripheral clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 2 enum/FMCSEL: bit_size: 2 variants: - - name: RCC_HCLK3 - description: rcc_hclk3 selected as peripheral clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: PLL2_R - description: pll2_r selected as peripheral clock - value: 2 - - name: PER - description: PER selected as peripheral clock - value: 3 + - name: RCC_HCLK3 + description: rcc_hclk3 selected as peripheral clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: PLL2_R + description: pll2_r selected as peripheral clock + value: 2 + - name: PER + description: PER selected as peripheral clock + value: 3 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: sys_ck not divided - value: 0 - - name: Div2 - description: sys_ck divided by 2 - value: 8 - - name: Div4 - description: sys_ck divided by 4 - value: 9 - - name: Div8 - description: sys_ck divided by 8 - value: 10 - - name: Div16 - description: sys_ck divided by 16 - value: 11 - - name: Div64 - description: sys_ck divided by 64 - value: 12 - - name: Div128 - description: sys_ck divided by 128 - value: 13 - - name: Div256 - description: sys_ck divided by 256 - value: 14 - - name: Div512 - description: sys_ck divided by 512 - value: 15 + - name: Div1 + description: sys_ck not divided + value: 0 + - name: Div2 + description: sys_ck divided by 2 + value: 8 + - name: Div4 + description: sys_ck divided by 4 + value: 9 + - name: Div8 + description: sys_ck divided by 8 + value: 10 + - name: Div16 + description: sys_ck divided by 16 + value: 11 + - name: Div64 + description: sys_ck divided by 64 + value: 12 + - name: Div128 + description: sys_ck divided by 128 + value: 13 + - name: Div256 + description: sys_ck divided by 256 + value: 14 + - name: Div512 + description: sys_ck divided by 512 + value: 15 enum/HRTIMSEL: bit_size: 1 variants: - - name: TIMY_KER - description: The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck) - value: 0 - - name: C_CK - description: The HRTIM prescaler clock source is the CPU clock (c_ck) - value: 1 + - name: TIMY_KER + description: The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck) + value: 0 + - name: C_CK + description: The HRTIM prescaler clock source is the CPU clock (c_ck) + value: 1 enum/HSIDIV: bit_size: 2 variants: - - name: Div1 - description: No division - value: 0 - - name: Div2 - description: Division by 2 - value: 1 - - name: Div4 - description: Division by 4 - value: 2 - - name: Div8 - description: Division by 8 - value: 3 + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 enum/I2C1235SEL: bit_size: 2 variants: - - name: RCC_PCLK1 - description: rcc_pclk1 selected as peripheral clock - value: 0 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 1 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 2 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 3 + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 2 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 3 enum/I2C4SEL: bit_size: 2 variants: - - name: RCC_PCLK4 - description: rcc_pclk4 selected as peripheral clock - value: 0 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 1 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 2 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 3 + - name: RCC_PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 2 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 3 enum/LPTIM1SEL: bit_size: 3 variants: - - name: RCC_PCLK1 - description: rcc_pclk1 selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 2 - - name: LSE - description: LSE selected as peripheral clock - value: 3 - - name: LSI - description: LSI selected as peripheral clock - value: 4 - - name: PER - description: PER selected as peripheral clock - value: 5 + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 2 + - name: LSE + description: LSE selected as peripheral clock + value: 3 + - name: LSI + description: LSI selected as peripheral clock + value: 4 + - name: PER + description: PER selected as peripheral clock + value: 5 enum/LPTIM2SEL: bit_size: 3 variants: - - name: RCC_PCLK4 - description: rcc_pclk4 selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 2 - - name: LSE - description: LSE selected as peripheral clock - value: 3 - - name: LSI - description: LSI selected as peripheral clock - value: 4 - - name: PER - description: PER selected as peripheral clock - value: 5 + - name: RCC_PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 2 + - name: LSE + description: LSE selected as peripheral clock + value: 3 + - name: LSI + description: LSI selected as peripheral clock + value: 4 + - name: PER + description: PER selected as peripheral clock + value: 5 enum/LPUARTSEL: bit_size: 3 variants: - - name: RCC_PCLK_D3 - description: rcc_pclk_d3 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: LSE - description: LSE selected as peripheral clock - value: 5 + - name: RCC_PCLK_D3 + description: rcc_pclk_d3 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 enum/LSEDRV: bit_size: 2 variants: - - name: Lowest - description: Lowest LSE oscillator driving capability - value: 0 - - name: MediumLow - description: Medium low LSE oscillator driving capability - value: 1 - - name: MediumHigh - description: Medium high LSE oscillator driving capability - value: 2 - - name: Highest - description: Highest LSE oscillator driving capability - value: 3 + - name: Lowest + description: Lowest LSE oscillator driving capability + value: 0 + - name: MediumLow + description: Medium low LSE oscillator driving capability + value: 1 + - name: MediumHigh + description: Medium high LSE oscillator driving capability + value: 2 + - name: Highest + description: Highest LSE oscillator driving capability + value: 3 enum/MCO1: bit_size: 3 variants: - - name: HSI - description: HSI selected for micro-controller clock output - value: 0 - - name: LSE - description: LSE selected for micro-controller clock output - value: 1 - - name: HSE - description: HSE selected for micro-controller clock output - value: 2 - - name: PLL1_Q - description: pll1_q selected for micro-controller clock output - value: 3 - - name: HSI48 - description: HSI48 selected for micro-controller clock output - value: 4 + - name: HSI + description: HSI selected for micro-controller clock output + value: 0 + - name: LSE + description: LSE selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_Q + description: pll1_q selected for micro-controller clock output + value: 3 + - name: HSI48 + description: HSI48 selected for micro-controller clock output + value: 4 enum/MCO2: bit_size: 3 variants: - - name: SYSCLK - description: System clock selected for micro-controller clock output - value: 0 - - name: PLL2_P - description: pll2_p selected for micro-controller clock output - value: 1 - - name: HSE - description: HSE selected for micro-controller clock output - value: 2 - - name: PLL1_P - description: pll1_p selected for micro-controller clock output - value: 3 - - name: CSI - description: CSI selected for micro-controller clock output - value: 4 - - name: LSI - description: LSI selected for micro-controller clock output - value: 5 + - name: SYSCLK + description: System clock selected for micro-controller clock output + value: 0 + - name: PLL2_P + description: pll2_p selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_P + description: pll1_p selected for micro-controller clock output + value: 3 + - name: CSI + description: CSI selected for micro-controller clock output + value: 4 + - name: LSI + description: LSI selected for micro-controller clock output + value: 5 enum/PLLRGE: bit_size: 2 variants: - - name: Range1 - description: Frequency is between 1 and 2 MHz - value: 0 - - name: Range2 - description: Frequency is between 2 and 4 MHz - value: 1 - - name: Range4 - description: Frequency is between 4 and 8 MHz - value: 2 - - name: Range8 - description: Frequency is between 8 and 16 MHz - value: 3 + - name: Range1 + description: Frequency is between 1 and 2 MHz + value: 0 + - name: Range2 + description: Frequency is between 2 and 4 MHz + value: 1 + - name: Range4 + description: Frequency is between 4 and 8 MHz + value: 2 + - name: Range8 + description: Frequency is between 8 and 16 MHz + value: 3 enum/PLLSRC: bit_size: 2 variants: - - name: HSI - description: HSI selected as PLL clock - value: 0 - - name: CSI - description: CSI selected as PLL clock - value: 1 - - name: HSE - description: HSE selected as PLL clock - value: 2 - - name: None - description: No clock sent to DIVMx dividers and PLLs - value: 3 + - name: HSI + description: HSI selected as PLL clock + value: 0 + - name: CSI + description: CSI selected as PLL clock + value: 1 + - name: HSE + description: HSE selected as PLL clock + value: 2 + - name: None + description: No clock sent to DIVMx dividers and PLLs + value: 3 enum/PLLVCOSEL: bit_size: 1 variants: - - name: WideVCO - description: VCO frequency range 192 to 836 MHz - value: 0 - - name: MediumVCO - description: VCO frequency range 150 to 420 MHz - value: 1 + - name: WideVCO + description: VCO frequency range 192 to 836 MHz + value: 0 + - name: MediumVCO + description: VCO frequency range 150 to 420 MHz + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: rcc_hclk not divided + value: 0 + - name: Div2 + description: rcc_hclk divided by 2 + value: 4 + - name: Div4 + description: rcc_hclk divided by 4 + value: 5 + - name: Div8 + description: rcc_hclk divided by 8 + value: 6 + - name: Div16 + description: rcc_hclk divided by 16 + value: 7 enum/RNGSEL: bit_size: 2 variants: - - name: HSI48 - description: HSI48 selected as peripheral clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: LSE - description: LSE selected as peripheral clock - value: 2 - - name: LSI - description: LSI selected as peripheral clock - value: 3 + - name: HSI48 + description: HSI48 selected as peripheral clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: LSE + description: LSE selected as peripheral clock + value: 2 + - name: LSI + description: LSI selected as peripheral clock + value: 3 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: HSE oscillator clock divided by a prescaler used as RTC clock - value: 3 + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 enum/SAIASEL: bit_size: 3 variants: - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: PLL3_P - description: pll3_p selected as peripheral clock - value: 2 - - name: I2S_CKIN - description: i2s_ckin selected as peripheral clock - value: 3 - - name: PER - description: PER selected as peripheral clock - value: 4 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_P + description: pll3_p selected as peripheral clock + value: 2 + - name: I2S_CKIN + description: i2s_ckin selected as peripheral clock + value: 3 + - name: PER + description: PER selected as peripheral clock + value: 4 enum/SAISEL: bit_size: 3 variants: - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: PLL3_P - description: pll3_p selected as peripheral clock - value: 2 - - name: I2S_CKIN - description: I2S_CKIN selected as peripheral clock - value: 3 - - name: PER - description: PER selected as peripheral clock - value: 4 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_P + description: pll3_p selected as peripheral clock + value: 2 + - name: I2S_CKIN + description: I2S_CKIN selected as peripheral clock + value: 3 + - name: PER + description: PER selected as peripheral clock + value: 4 enum/SDMMCSEL: bit_size: 1 variants: - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 0 - - name: PLL2_R - description: pll2_r selected as peripheral clock - value: 1 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_R + description: pll2_r selected as peripheral clock + value: 1 enum/SPDIFRXSEL: bit_size: 2 variants: - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 0 - - name: PLL2_R - description: pll2_r selected as peripheral clock - value: 1 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_R + description: pll2_r selected as peripheral clock + value: 1 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 enum/SPI45SEL: bit_size: 3 variants: - - name: APB - description: APB clock selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: HSE - description: HSE selected as peripheral clock - value: 5 + - name: APB + description: APB clock selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: HSE + description: HSE selected as peripheral clock + value: 5 enum/SPI6SEL: bit_size: 3 variants: - - name: RCC_PCLK4 - description: rcc_pclk4 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: HSE - description: HSE selected as peripheral clock - value: 5 + - name: RCC_PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: HSE + description: HSE selected as peripheral clock + value: 5 enum/STOPWUCK: bit_size: 1 variants: - - name: HSI - description: HSI selected as wake up clock from system Stop - value: 0 - - name: CSI - description: CSI selected as wake up clock from system Stop - value: 1 + - name: HSI + description: HSI selected as wake up clock from system Stop + value: 0 + - name: CSI + description: CSI selected as wake up clock from system Stop + value: 1 enum/SW: bit_size: 3 variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: CSI - description: CSI selected as system clock - value: 1 - - name: HSE - description: HSE selected as system clock - value: 2 - - name: PLL1 - description: PLL1 selected as system clock - value: 3 + - name: HSI + description: HSI selected as system clock + value: 0 + - name: CSI + description: CSI selected as system clock + value: 1 + - name: HSE + description: HSE selected as system clock + value: 2 + - name: PLL1 + description: PLL1 selected as system clock + value: 3 enum/SWPSEL: bit_size: 1 variants: - - name: PCLK - description: pclk selected as peripheral clock - value: 0 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 1 -enum/SWS: - bit_size: 3 - variants: - - name: HSI - description: HSI oscillator used as system clock - value: 0 - - name: CSI - description: CSI oscillator used as system clock - value: 1 - - name: HSE - description: HSE oscillator used as system clock - value: 2 - - name: PLL1 - description: PLL1 used as system clock - value: 3 + - name: PCLK + description: pclk selected as peripheral clock + value: 0 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 1 enum/TIMPRE: bit_size: 1 variants: - - name: DefaultX2 - description: Timer kernel clock equal to 2x pclk by default - value: 0 - - name: DefaultX4 - description: Timer kernel clock equal to 4x pclk by default - value: 1 + - name: DefaultX2 + description: Timer kernel clock equal to 2x pclk by default + value: 0 + - name: DefaultX4 + description: Timer kernel clock equal to 4x pclk by default + value: 1 enum/USART16910SEL: bit_size: 3 variants: - - name: RCC_PCLK2 - description: rcc_pclk2 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: LSE - description: LSE selected as peripheral clock - value: 5 + - name: RCC_PCLK2 + description: rcc_pclk2 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 enum/USART234578SEL: bit_size: 3 variants: - - name: RCC_PCLK1 - description: rcc_pclk1 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: LSE - description: LSE selected as peripheral clock - value: 5 + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 enum/USBSEL: bit_size: 2 variants: - - name: DISABLE - description: Disable the kernel clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI48 - description: HSI48 selected as peripheral clock - value: 3 + - name: DISABLE + description: Disable the kernel clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI48 + description: HSI48 selected as peripheral clock + value: 3 diff --git a/data/registers/rcc_l0.yaml b/data/registers/rcc_l0.yaml index f8dbf82..ba1202e 100644 --- a/data/registers/rcc_l0.yaml +++ b/data/registers/rcc_l0.yaml @@ -1,1261 +1,1260 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: Clock control register - byte_offset: 0 - fieldset: CR - - name: ICSCR - description: Internal clock sources calibration register - byte_offset: 4 - fieldset: ICSCR - - name: CRRCR - description: Clock recovery RC register - byte_offset: 8 - fieldset: CRRCR - - name: CFGR - description: Clock configuration register - byte_offset: 12 - fieldset: CFGR - - name: CIER - description: Clock interrupt enable register - byte_offset: 16 - access: Read - fieldset: CIER - - name: CIFR - description: Clock interrupt flag register - byte_offset: 20 - access: Read - fieldset: CIFR - - name: CICR - description: Clock interrupt clear register - byte_offset: 24 - access: Read - fieldset: CICR - - name: GPIORSTR - description: GPIO reset register - byte_offset: 28 - fieldset: GPIORSTR - - name: AHBRSTR - description: AHB peripheral reset register - byte_offset: 32 - fieldset: AHBRSTR - - name: APB2RSTR - description: APB2 peripheral reset register - byte_offset: 36 - fieldset: APB2RSTR - - name: APB1RSTR - description: APB1 peripheral reset register - byte_offset: 40 - fieldset: APB1RSTR - - name: GPIOENR - description: GPIO clock enable register - byte_offset: 44 - fieldset: GPIOENR - - name: AHBENR - description: AHB peripheral clock enable register - byte_offset: 48 - fieldset: AHBENR - - name: APB2ENR - description: APB2 peripheral clock enable register - byte_offset: 52 - fieldset: APB2ENR - - name: APB1ENR - description: APB1 peripheral clock enable register - byte_offset: 56 - fieldset: APB1ENR - - name: GPIOSMEN - description: GPIO clock enable in sleep mode register - byte_offset: 60 - fieldset: GPIOSMEN - - name: AHBSMENR - description: AHB peripheral clock enable in sleep mode register - byte_offset: 64 - fieldset: AHBSMENR - - name: APB2SMENR - description: APB2 peripheral clock enable in sleep mode register - byte_offset: 68 - fieldset: APB2SMENR - - name: APB1SMENR - description: APB1 peripheral clock enable in sleep mode register - byte_offset: 72 - fieldset: APB1SMENR - - name: CCIPR - description: Clock configuration register - byte_offset: 76 - fieldset: CCIPR - - name: CSR - description: Control and status register - byte_offset: 80 - fieldset: CSR + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: Internal clock sources calibration register + byte_offset: 4 + fieldset: ICSCR + - name: CRRCR + description: Clock recovery RC register + byte_offset: 8 + fieldset: CRRCR + - name: CFGR + description: Clock configuration register + byte_offset: 12 + fieldset: CFGR + - name: CIER + description: Clock interrupt enable register + byte_offset: 16 + access: Read + fieldset: CIER + - name: CIFR + description: Clock interrupt flag register + byte_offset: 20 + access: Read + fieldset: CIFR + - name: CICR + description: Clock interrupt clear register + byte_offset: 24 + access: Read + fieldset: CICR + - name: GPIORSTR + description: GPIO reset register + byte_offset: 28 + fieldset: GPIORSTR + - name: AHBRSTR + description: AHB peripheral reset register + byte_offset: 32 + fieldset: AHBRSTR + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 36 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register + byte_offset: 40 + fieldset: APB1RSTR + - name: GPIOENR + description: GPIO clock enable register + byte_offset: 44 + fieldset: GPIOENR + - name: AHBENR + description: AHB peripheral clock enable register + byte_offset: 48 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register + byte_offset: 52 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register + byte_offset: 56 + fieldset: APB1ENR + - name: GPIOSMEN + description: GPIO clock enable in sleep mode register + byte_offset: 60 + fieldset: GPIOSMEN + - name: AHBSMENR + description: AHB peripheral clock enable in sleep mode register + byte_offset: 64 + fieldset: AHBSMENR + - name: APB2SMENR + description: APB2 peripheral clock enable in sleep mode register + byte_offset: 68 + fieldset: APB2SMENR + - name: APB1SMENR + description: APB1 peripheral clock enable in sleep mode register + byte_offset: 72 + fieldset: APB1SMENR + - name: CCIPR + description: Clock configuration register + byte_offset: 76 + fieldset: CCIPR + - name: CSR + description: Control and status register + byte_offset: 80 + fieldset: CSR fieldset/AHBENR: description: AHB peripheral clock enable register fields: - - name: DMA1EN - description: DMA clock enable - bit_offset: 0 - bit_size: 1 - - name: MIFEN - description: NVM interface clock enable - bit_offset: 8 - bit_size: 1 - - name: CRCEN - description: CRC clock enable - bit_offset: 12 - bit_size: 1 - - name: TOUCHEN - description: Touch Sensing clock enable - bit_offset: 16 - bit_size: 1 - - name: RNGEN - description: Random Number Generator clock enable - bit_offset: 20 - bit_size: 1 - - name: CRYPEN - description: Crypto clock enable - bit_offset: 24 - bit_size: 1 + - name: DMA1EN + description: DMA clock enable + bit_offset: 0 + bit_size: 1 + - name: MIFEN + description: NVM interface clock enable + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: TOUCHEN + description: Touch Sensing clock enable + bit_offset: 16 + bit_size: 1 + - name: RNGEN + description: Random Number Generator clock enable + bit_offset: 20 + bit_size: 1 + - name: CRYPEN + description: Crypto clock enable + bit_offset: 24 + bit_size: 1 fieldset/AHBRSTR: description: AHB peripheral reset register fields: - - name: DMA1RST - description: DMA reset - bit_offset: 0 - bit_size: 1 - - name: MIFRST - description: Memory interface reset - bit_offset: 8 - bit_size: 1 - - name: CRCRST - description: Test integration module reset - bit_offset: 12 - bit_size: 1 - - name: TOUCHRST - description: Touch Sensing reset - bit_offset: 16 - bit_size: 1 - - name: RNGRST - description: Random Number Generator module reset - bit_offset: 20 - bit_size: 1 - - name: CRYPRST - description: Crypto module reset - bit_offset: 24 - bit_size: 1 + - name: DMA1RST + description: DMA reset + bit_offset: 0 + bit_size: 1 + - name: MIFRST + description: Memory interface reset + bit_offset: 8 + bit_size: 1 + - name: CRCRST + description: Test integration module reset + bit_offset: 12 + bit_size: 1 + - name: TOUCHRST + description: Touch Sensing reset + bit_offset: 16 + bit_size: 1 + - name: RNGRST + description: Random Number Generator module reset + bit_offset: 20 + bit_size: 1 + - name: CRYPRST + description: Crypto module reset + bit_offset: 24 + bit_size: 1 fieldset/AHBSMENR: description: AHB peripheral clock enable in sleep mode register fields: - - name: DMA1SMEN - description: DMA clock enable during sleep mode - bit_offset: 0 - bit_size: 1 - - name: MIFSMEN - description: NVM interface clock enable during sleep mode - bit_offset: 8 - bit_size: 1 - - name: SRAMSMEN - description: SRAM interface clock enable during sleep mode - bit_offset: 9 - bit_size: 1 - - name: CRCSMEN - description: CRC clock enable during sleep mode - bit_offset: 12 - bit_size: 1 - - name: TOUCHSMEN - description: Touch Sensing clock enable during sleep mode - bit_offset: 16 - bit_size: 1 - - name: RNGSMEN - description: Random Number Generator clock enable during sleep mode - bit_offset: 20 - bit_size: 1 - - name: CRYPSMEN - description: Crypto clock enable during sleep mode - bit_offset: 24 - bit_size: 1 + - name: DMA1SMEN + description: DMA clock enable during sleep mode + bit_offset: 0 + bit_size: 1 + - name: MIFSMEN + description: NVM interface clock enable during sleep mode + bit_offset: 8 + bit_size: 1 + - name: SRAMSMEN + description: SRAM interface clock enable during sleep mode + bit_offset: 9 + bit_size: 1 + - name: CRCSMEN + description: CRC clock enable during sleep mode + bit_offset: 12 + bit_size: 1 + - name: TOUCHSMEN + description: Touch Sensing clock enable during sleep mode + bit_offset: 16 + bit_size: 1 + - name: RNGSMEN + description: Random Number Generator clock enable during sleep mode + bit_offset: 20 + bit_size: 1 + - name: CRYPSMEN + description: Crypto clock enable during sleep mode + bit_offset: 24 + bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register fields: - - name: TIM2EN - description: Timer2 clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: Timer 3 clock enbale - bit_offset: 1 - bit_size: 1 - - name: TIM6EN - description: Timer 6 clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: Timer 7 clock enable - bit_offset: 5 - bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI2 clock enable - bit_offset: 14 - bit_size: 1 - - name: USART2EN - description: UART2 clock enable - bit_offset: 17 - bit_size: 1 - - name: LPUART1EN - description: LPUART1 clock enable - bit_offset: 18 - bit_size: 1 - - name: USART4EN - description: USART4 clock enable - bit_offset: 19 - bit_size: 1 - - name: USART5EN - description: USART5 clock enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C2 clock enable - bit_offset: 22 - bit_size: 1 - - name: USBEN - description: USB clock enable - bit_offset: 23 - bit_size: 1 - - name: CRSEN - description: Clock recovery system clock enable - bit_offset: 27 - bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - - name: DACEN - description: DAC interface clock enable - bit_offset: 29 - bit_size: 1 - - name: I2C3EN - description: I2C3 clock enable - bit_offset: 30 - bit_size: 1 - - name: LPTIM1EN - description: Low power timer clock enable - bit_offset: 31 - bit_size: 1 + - name: TIM2EN + description: Timer2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enbale + bit_offset: 1 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: Timer 7 clock enable + bit_offset: 5 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: USART2EN + description: UART2 clock enable + bit_offset: 17 + bit_size: 1 + - name: LPUART1EN + description: LPUART1 clock enable + bit_offset: 18 + bit_size: 1 + - name: USART4EN + description: USART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: USART5EN + description: USART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: USB clock enable + bit_offset: 23 + bit_size: 1 + - name: CRSEN + description: Clock recovery system clock enable + bit_offset: 27 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 30 + bit_size: 1 + - name: LPTIM1EN + description: Low power timer clock enable + bit_offset: 31 + bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register fields: - - name: TIM2RST - description: Timer 2 reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: Timer 3 reset - bit_offset: 1 - bit_size: 1 - - name: TIM6RST - description: Timer 6 reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: Timer 7 reset - bit_offset: 5 - bit_size: 1 - - name: WWDGRST - description: Window watchdog reset - bit_offset: 11 - bit_size: 1 - - name: SPI2RST - description: SPI2 reset - bit_offset: 14 - bit_size: 1 - - name: USART2RST - description: USART2 reset - bit_offset: 17 - bit_size: 1 - - name: LPUART1RST - description: LPUART1 reset - bit_offset: 18 - bit_size: 1 - - name: USART4RST - description: USART4 reset - bit_offset: 19 - bit_size: 1 - - name: USART5RST - description: USART5 reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C2 reset - bit_offset: 22 - bit_size: 1 - - name: USBRST - description: USB reset - bit_offset: 23 - bit_size: 1 - - name: CRSRST - description: Clock recovery system reset - bit_offset: 27 - bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - - name: DACRST - description: DAC interface reset - bit_offset: 29 - bit_size: 1 - - name: I2C3RST - description: I2C3 reset - bit_offset: 30 - bit_size: 1 - - name: LPTIM1RST - description: Low power timer reset - bit_offset: 31 - bit_size: 1 + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM6RST + description: Timer 6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: Timer 7 reset + bit_offset: 5 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: USART2RST + description: USART2 reset + bit_offset: 17 + bit_size: 1 + - name: LPUART1RST + description: LPUART1 reset + bit_offset: 18 + bit_size: 1 + - name: USART4RST + description: USART4 reset + bit_offset: 19 + bit_size: 1 + - name: USART5RST + description: USART5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: USB reset + bit_offset: 23 + bit_size: 1 + - name: CRSRST + description: Clock recovery system reset + bit_offset: 27 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 30 + bit_size: 1 + - name: LPTIM1RST + description: Low power timer reset + bit_offset: 31 + bit_size: 1 fieldset/APB1SMENR: description: APB1 peripheral clock enable in sleep mode register fields: - - name: TIM2SMEN - description: Timer2 clock enable during sleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM3SMEN - description: Timer 3 clock enable during sleep mode - bit_offset: 1 - bit_size: 1 - - name: TIM6SMEN - description: Timer 6 clock enable during sleep mode - bit_offset: 4 - bit_size: 1 - - name: TIM7SMEN - description: Timer 7 clock enable during sleep mode - bit_offset: 5 - bit_size: 1 - - name: WWDGSMEN - description: Window watchdog clock enable during sleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI2SMEN - description: SPI2 clock enable during sleep mode - bit_offset: 14 - bit_size: 1 - - name: USART2SMEN - description: UART2 clock enable during sleep mode - bit_offset: 17 - bit_size: 1 - - name: LPUART1SMEN - description: LPUART1 clock enable during sleep mode - bit_offset: 18 - bit_size: 1 - - name: USART4SMEN - description: USART4 clock enabe during sleep mode - bit_offset: 19 - bit_size: 1 - - name: USART5SMEN - description: USART5 clock enable during sleep mode - bit_offset: 20 - bit_size: 1 - - name: I2C1SMEN - description: I2C1 clock enable during sleep mode - bit_offset: 21 - bit_size: 1 - - name: I2C2SMEN - description: I2C2 clock enable during sleep mode - bit_offset: 22 - bit_size: 1 - - name: USBSMEN - description: USB clock enable during sleep mode - bit_offset: 23 - bit_size: 1 - - name: CRSSMEN - description: Clock recovery system clock enable during sleep mode - bit_offset: 27 - bit_size: 1 - - name: PWRSMEN - description: Power interface clock enable during sleep mode - bit_offset: 28 - bit_size: 1 - - name: DACSMEN - description: DAC interface clock enable during sleep mode - bit_offset: 29 - bit_size: 1 - - name: I2C3SMEN - description: I2C3 clock enable during sleep mode - bit_offset: 30 - bit_size: 1 - - name: LPTIM1SMEN - description: Low power timer clock enable during sleep mode - bit_offset: 31 - bit_size: 1 + - name: TIM2SMEN + description: Timer2 clock enable during sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM3SMEN + description: Timer 3 clock enable during sleep mode + bit_offset: 1 + bit_size: 1 + - name: TIM6SMEN + description: Timer 6 clock enable during sleep mode + bit_offset: 4 + bit_size: 1 + - name: TIM7SMEN + description: Timer 7 clock enable during sleep mode + bit_offset: 5 + bit_size: 1 + - name: WWDGSMEN + description: Window watchdog clock enable during sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI2SMEN + description: SPI2 clock enable during sleep mode + bit_offset: 14 + bit_size: 1 + - name: USART2SMEN + description: UART2 clock enable during sleep mode + bit_offset: 17 + bit_size: 1 + - name: LPUART1SMEN + description: LPUART1 clock enable during sleep mode + bit_offset: 18 + bit_size: 1 + - name: USART4SMEN + description: USART4 clock enabe during sleep mode + bit_offset: 19 + bit_size: 1 + - name: USART5SMEN + description: USART5 clock enable during sleep mode + bit_offset: 20 + bit_size: 1 + - name: I2C1SMEN + description: I2C1 clock enable during sleep mode + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: I2C2 clock enable during sleep mode + bit_offset: 22 + bit_size: 1 + - name: USBSMEN + description: USB clock enable during sleep mode + bit_offset: 23 + bit_size: 1 + - name: CRSSMEN + description: Clock recovery system clock enable during sleep mode + bit_offset: 27 + bit_size: 1 + - name: PWRSMEN + description: Power interface clock enable during sleep mode + bit_offset: 28 + bit_size: 1 + - name: DACSMEN + description: DAC interface clock enable during sleep mode + bit_offset: 29 + bit_size: 1 + - name: I2C3SMEN + description: I2C3 clock enable during sleep mode + bit_offset: 30 + bit_size: 1 + - name: LPTIM1SMEN + description: Low power timer clock enable during sleep mode + bit_offset: 31 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - - name: SYSCFGEN - description: System configuration controller clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM21EN - description: TIM21 timer clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM22EN - description: TIM22 timer clock enable - bit_offset: 5 - bit_size: 1 - - name: FWEN - description: Firewall clock enable - bit_offset: 7 - bit_size: 1 - - name: ADCEN - description: ADC clock enable - bit_offset: 9 - bit_size: 1 - - name: SPI1EN - description: SPI1 clock enable - bit_offset: 12 - bit_size: 1 - - name: USART1EN - description: USART1 clock enable - bit_offset: 14 - bit_size: 1 - - name: DBGEN - description: DBG clock enable - bit_offset: 22 - bit_size: 1 + - name: SYSCFGEN + description: System configuration controller clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM21EN + description: TIM21 timer clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM22EN + description: TIM22 timer clock enable + bit_offset: 5 + bit_size: 1 + - name: FWEN + description: Firewall clock enable + bit_offset: 7 + bit_size: 1 + - name: ADCEN + description: ADC clock enable + bit_offset: 9 + bit_size: 1 + - name: SPI1EN + description: SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 + - name: DBGEN + description: DBG clock enable + bit_offset: 22 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - - name: SYSCFGRST - description: System configuration controller reset - bit_offset: 0 - bit_size: 1 - - name: TIM21RST - description: TIM21 timer reset - bit_offset: 2 - bit_size: 1 - - name: TIM22RST - description: TIM22 timer reset - bit_offset: 5 - bit_size: 1 - - name: ADCRST - description: ADC interface reset - bit_offset: 9 - bit_size: 1 - - name: SPI1RST - description: SPI 1 reset - bit_offset: 12 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 14 - bit_size: 1 - - name: DBGRST - description: DBG reset - bit_offset: 22 - bit_size: 1 + - name: SYSCFGRST + description: System configuration controller reset + bit_offset: 0 + bit_size: 1 + - name: TIM21RST + description: TIM21 timer reset + bit_offset: 2 + bit_size: 1 + - name: TIM22RST + description: TIM22 timer reset + bit_offset: 5 + bit_size: 1 + - name: ADCRST + description: ADC interface reset + bit_offset: 9 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: DBGRST + description: DBG reset + bit_offset: 22 + bit_size: 1 fieldset/APB2SMENR: description: APB2 peripheral clock enable in sleep mode register fields: - - name: SYSCFGSMEN - description: System configuration controller clock enable during sleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM21SMEN - description: TIM21 timer clock enable during sleep mode - bit_offset: 2 - bit_size: 1 - - name: TIM22SMEN - description: TIM22 timer clock enable during sleep mode - bit_offset: 5 - bit_size: 1 - - name: ADCSMEN - description: ADC clock enable during sleep mode - bit_offset: 9 - bit_size: 1 - - name: SPI1SMEN - description: SPI1 clock enable during sleep mode - bit_offset: 12 - bit_size: 1 - - name: USART1SMEN - description: USART1 clock enable during sleep mode - bit_offset: 14 - bit_size: 1 - - name: DBGSMEN - description: DBG clock enable during sleep mode - bit_offset: 22 - bit_size: 1 + - name: SYSCFGSMEN + description: System configuration controller clock enable during sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM21SMEN + description: TIM21 timer clock enable during sleep mode + bit_offset: 2 + bit_size: 1 + - name: TIM22SMEN + description: TIM22 timer clock enable during sleep mode + bit_offset: 5 + bit_size: 1 + - name: ADCSMEN + description: ADC clock enable during sleep mode + bit_offset: 9 + bit_size: 1 + - name: SPI1SMEN + description: SPI1 clock enable during sleep mode + bit_offset: 12 + bit_size: 1 + - name: USART1SMEN + description: USART1 clock enable during sleep mode + bit_offset: 14 + bit_size: 1 + - name: DBGSMEN + description: DBG clock enable during sleep mode + bit_offset: 22 + bit_size: 1 fieldset/CCIPR: description: Clock configuration register fields: - - name: USART1SEL - description: USART1 clock source selection - bit_offset: 0 - bit_size: 2 - enum: UARTSEL - - name: USART2SEL - description: USART2 clock source selection - bit_offset: 2 - bit_size: 2 - enum: UARTSEL - - name: LPUART1SEL - description: LPUART1 clock source selection - bit_offset: 10 - bit_size: 2 - enum: UARTSEL - - name: I2C1SEL - description: I2C1 clock source selection - bit_offset: 12 - bit_size: 2 - enum: ICSEL - - name: I2C3SEL - description: I2C3 clock source selection - bit_offset: 16 - bit_size: 2 - enum: ICSEL - - name: LPTIM1SEL - description: Low Power Timer clock source selection - bit_offset: 18 - bit_size: 2 - enum: LPTIMSEL - - name: HSI48MSEL - description: 48 MHz HSI48 clock source selection - bit_offset: 26 - bit_size: 1 + - name: USART1SEL + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + enum: UARTSEL + - name: USART2SEL + description: USART2 clock source selection + bit_offset: 2 + bit_size: 2 + enum: UARTSEL + - name: LPUART1SEL + description: LPUART1 clock source selection + bit_offset: 10 + bit_size: 2 + enum: UARTSEL + - name: I2C1SEL + description: I2C1 clock source selection + bit_offset: 12 + bit_size: 2 + enum: ICSEL + - name: I2C3SEL + description: I2C3 clock source selection + bit_offset: 16 + bit_size: 2 + enum: ICSEL + - name: LPTIM1SEL + description: Low Power Timer clock source selection + bit_offset: 18 + bit_size: 2 + enum: LPTIMSEL + - name: HSI48MSEL + description: 48 MHz HSI48 clock source selection + bit_offset: 26 + bit_size: 1 fieldset/CFGR: description: Clock configuration register fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: System clock switch status - bit_offset: 2 - bit_size: 2 - enum: SW - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - enum: HPRE - - name: PPRE1 - description: APB low-speed prescaler (APB1) - bit_offset: 8 - bit_size: 3 - enum: PPRE - - name: PPRE2 - description: APB high-speed prescaler (APB2) - bit_offset: 11 - bit_size: 3 - enum: PPRE - - name: STOPWUCK - description: Wake-up from stop clock selection - bit_offset: 15 - bit_size: 1 - enum: STOPWUCK - - name: PLLSRC - description: PLL entry clock source - bit_offset: 16 - bit_size: 1 - enum: PLLSRC - - name: PLLMUL - description: PLL multiplication factor - bit_offset: 18 - bit_size: 4 - enum: PLLMUL - - name: PLLDIV - description: PLL output division - bit_offset: 22 - bit_size: 2 - enum: PLLDIV - - name: MCOSEL - description: Microcontroller clock output selection - bit_offset: 24 - bit_size: 3 - enum: MCOSEL - - name: MCOPRE - description: Microcontroller clock output prescaler - bit_offset: 28 - bit_size: 3 - enum: MCOPRE + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB low-speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high-speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: STOPWUCK + description: Wake-up from stop clock selection + bit_offset: 15 + bit_size: 1 + enum: STOPWUCK + - name: PLLSRC + description: PLL entry clock source + bit_offset: 16 + bit_size: 1 + enum: PLLSRC + - name: PLLMUL + description: PLL multiplication factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: PLLDIV + description: PLL output division + bit_offset: 22 + bit_size: 2 + enum: PLLDIV + - name: MCOSEL + description: Microcontroller clock output selection + bit_offset: 24 + bit_size: 3 + enum: MCOSEL + - name: MCOPRE + description: Microcontroller clock output prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: - - name: LSIRDYC - description: LSI ready Interrupt clear - bit_offset: 0 - bit_size: 1 - - name: LSERDYC - description: LSE ready Interrupt clear - bit_offset: 1 - bit_size: 1 - - name: HSI16RDYC - description: HSI16 ready Interrupt clear - bit_offset: 2 - bit_size: 1 - - name: HSERDYC - description: HSE ready Interrupt clear - bit_offset: 3 - bit_size: 1 - - name: PLLRDYC - description: PLL ready Interrupt clear - bit_offset: 4 - bit_size: 1 - - name: MSIRDYC - description: MSI ready Interrupt clear - bit_offset: 5 - bit_size: 1 - - name: HSI48RDYC - description: HSI48 ready Interrupt clear - bit_offset: 6 - bit_size: 1 - - name: CSSLSEC - description: LSE Clock Security System Interrupt clear - bit_offset: 7 - bit_size: 1 - - name: CSSHSEC - description: Clock Security System Interrupt clear - bit_offset: 8 - bit_size: 1 + - name: LSIRDYC + description: LSI ready Interrupt clear + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: LSE ready Interrupt clear + bit_offset: 1 + bit_size: 1 + - name: HSI16RDYC + description: HSI16 ready Interrupt clear + bit_offset: 2 + bit_size: 1 + - name: HSERDYC + description: HSE ready Interrupt clear + bit_offset: 3 + bit_size: 1 + - name: PLLRDYC + description: PLL ready Interrupt clear + bit_offset: 4 + bit_size: 1 + - name: MSIRDYC + description: MSI ready Interrupt clear + bit_offset: 5 + bit_size: 1 + - name: HSI48RDYC + description: HSI48 ready Interrupt clear + bit_offset: 6 + bit_size: 1 + - name: CSSLSEC + description: LSE Clock Security System Interrupt clear + bit_offset: 7 + bit_size: 1 + - name: CSSHSEC + description: Clock Security System Interrupt clear + bit_offset: 8 + bit_size: 1 fieldset/CIER: description: Clock interrupt enable register fields: - - name: LSIRDYIE - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYIE - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - - name: HSI16RDYIE - description: HSI16 ready interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSERDYIE - description: HSE ready interrupt flag - bit_offset: 3 - bit_size: 1 - - name: PLLRDYIE - description: PLL ready interrupt flag - bit_offset: 4 - bit_size: 1 - - name: MSIRDYIE - description: MSI ready interrupt flag - bit_offset: 5 - bit_size: 1 - - name: HSI48RDYIE - description: HSI48 ready interrupt flag - bit_offset: 6 - bit_size: 1 - - name: CSSLSE - description: LSE CSS interrupt flag - bit_offset: 7 - bit_size: 1 + - name: LSIRDYIE + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSI16RDYIE + description: HSI16 ready interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYIE + description: HSE ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYIE + description: PLL ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: MSIRDYIE + description: MSI ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: HSI48RDYIE + description: HSI48 ready interrupt flag + bit_offset: 6 + bit_size: 1 + - name: CSSLSE + description: LSE CSS interrupt flag + bit_offset: 7 + bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register fields: - - name: LSIRDYF - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - - name: HSI16RDYF - description: HSI16 ready interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSERDYF - description: HSE ready interrupt flag - bit_offset: 3 - bit_size: 1 - - name: PLLRDYF - description: PLL ready interrupt flag - bit_offset: 4 - bit_size: 1 - - name: MSIRDYF - description: MSI ready interrupt flag - bit_offset: 5 - bit_size: 1 - - name: HSI48RDYF - description: HSI48 ready interrupt flag - bit_offset: 6 - bit_size: 1 - - name: CSSLSEF - description: LSE Clock Security System Interrupt flag - bit_offset: 7 - bit_size: 1 - - name: CSSHSEF - description: Clock Security System Interrupt flag - bit_offset: 8 - bit_size: 1 + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSI16RDYF + description: HSI16 ready interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: PLL ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: MSIRDYF + description: MSI ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: HSI48RDYF + description: HSI48 ready interrupt flag + bit_offset: 6 + bit_size: 1 + - name: CSSLSEF + description: LSE Clock Security System Interrupt flag + bit_offset: 7 + bit_size: 1 + - name: CSSHSEF + description: Clock Security System Interrupt flag + bit_offset: 8 + bit_size: 1 fieldset/CR: description: Clock control register fields: - - name: HSI16ON - description: 16 MHz high-speed internal clock enable - bit_offset: 0 - bit_size: 1 - - name: HSI16KERON - description: High-speed internal clock enable bit for some IP kernels - bit_offset: 1 - bit_size: 1 - - name: HSI16RDYF - description: Internal high-speed clock ready flag - bit_offset: 2 - bit_size: 1 - - name: HSI16DIVEN - description: HSI16DIVEN - bit_offset: 3 - bit_size: 1 - - name: HSI16DIVF - description: HSI16DIVF - bit_offset: 4 - bit_size: 1 - - name: HSI16OUTEN - description: 16 MHz high-speed internal clock output enable - bit_offset: 5 - bit_size: 1 - - name: MSION - description: MSI clock enable - bit_offset: 8 - bit_size: 1 - - name: MSIRDY - description: MSI clock ready flag - bit_offset: 9 - bit_size: 1 - - name: HSEON - description: HSE clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: HSE clock bypass - bit_offset: 18 - bit_size: 1 - - name: CSSHSEON - description: Clock security system on HSE enable - bit_offset: 19 - bit_size: 1 - - name: RTCPRE - description: TC/LCD prescaler - bit_offset: 20 - bit_size: 2 - enum: RTCPRE - - name: PLLON - description: PLL enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: PLL clock ready flag - bit_offset: 25 - bit_size: 1 + - name: HSI16ON + description: 16 MHz high-speed internal clock enable + bit_offset: 0 + bit_size: 1 + - name: HSI16KERON + description: High-speed internal clock enable bit for some IP kernels + bit_offset: 1 + bit_size: 1 + - name: HSI16RDYF + description: Internal high-speed clock ready flag + bit_offset: 2 + bit_size: 1 + - name: HSI16DIVEN + description: HSI16DIVEN + bit_offset: 3 + bit_size: 1 + - name: HSI16DIVF + description: HSI16DIVF + bit_offset: 4 + bit_size: 1 + - name: HSI16OUTEN + description: 16 MHz high-speed internal clock output enable + bit_offset: 5 + bit_size: 1 + - name: MSION + description: MSI clock enable + bit_offset: 8 + bit_size: 1 + - name: MSIRDY + description: MSI clock ready flag + bit_offset: 9 + bit_size: 1 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: HSE clock bypass + bit_offset: 18 + bit_size: 1 + - name: CSSHSEON + description: Clock security system on HSE enable + bit_offset: 19 + bit_size: 1 + - name: RTCPRE + description: TC/LCD prescaler + bit_offset: 20 + bit_size: 2 + enum: RTCPRE + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 fieldset/CRRCR: description: Clock recovery RC register fields: - - name: HSI48ON - description: 48MHz HSI clock enable - bit_offset: 0 - bit_size: 1 - - name: HSI48RDY - description: 48MHz HSI clock ready flag - bit_offset: 1 - bit_size: 1 - - name: HSI48DIV6EN - description: 48 MHz HSI clock divided by 6 output enable - bit_offset: 2 - bit_size: 1 - - name: HSI48CAL - description: 48 MHz HSI clock calibration - bit_offset: 8 - bit_size: 8 + - name: HSI48ON + description: 48MHz HSI clock enable + bit_offset: 0 + bit_size: 1 + - name: HSI48RDY + description: 48MHz HSI clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSI48DIV6EN + description: 48 MHz HSI clock divided by 6 output enable + bit_offset: 2 + bit_size: 1 + - name: HSI48CAL + description: 48 MHz HSI clock calibration + bit_offset: 8 + bit_size: 8 fieldset/CSR: description: Control and status register fields: - - name: LSION - description: Internal low-speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: Internal low-speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEON - description: External low-speed oscillator enable - bit_offset: 8 - bit_size: 1 - - name: LSERDY - description: External low-speed oscillator ready - bit_offset: 9 - bit_size: 1 - - name: LSEBYP - description: External low-speed oscillator bypass - bit_offset: 10 - bit_size: 1 - - name: LSEDRV - description: LSEDRV - bit_offset: 11 - bit_size: 2 - enum: LSEDRV - - name: CSSLSEON - description: CSSLSEON - bit_offset: 13 - bit_size: 1 - - name: CSSLSED - description: CSS on LSE failure detection flag - bit_offset: 14 - bit_size: 1 - - name: RTCSEL - description: RTC and LCD clock source selection - bit_offset: 16 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 18 - bit_size: 1 - - name: RTCRST - description: RTC software reset - bit_offset: 19 - bit_size: 1 - - name: RMVF - description: Remove reset flag - bit_offset: 23 - bit_size: 1 - - name: FWRSTF - description: Firewall reset flag - bit_offset: 24 - bit_size: 1 - - name: OBLRSTF - description: OBLRSTF - bit_offset: 25 - bit_size: 1 - - name: PINRSTF - description: PIN reset flag - bit_offset: 26 - bit_size: 1 - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: Independent watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSION + description: Internal low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low-speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEON + description: External low-speed oscillator enable + bit_offset: 8 + bit_size: 1 + - name: LSERDY + description: External low-speed oscillator ready + bit_offset: 9 + bit_size: 1 + - name: LSEBYP + description: External low-speed oscillator bypass + bit_offset: 10 + bit_size: 1 + - name: LSEDRV + description: LSEDRV + bit_offset: 11 + bit_size: 2 + enum: LSEDRV + - name: CSSLSEON + description: CSSLSEON + bit_offset: 13 + bit_size: 1 + - name: CSSLSED + description: CSS on LSE failure detection flag + bit_offset: 14 + bit_size: 1 + - name: RTCSEL + description: RTC and LCD clock source selection + bit_offset: 16 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 18 + bit_size: 1 + - name: RTCRST + description: RTC software reset + bit_offset: 19 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 23 + bit_size: 1 + - name: FWRSTF + description: Firewall reset flag + bit_offset: 24 + bit_size: 1 + - name: OBLRSTF + description: OBLRSTF + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 fieldset/GPIOENR: description: GPIO clock enable register fields: - - name: GPIOAEN - description: IO port A clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: IO port B clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: IO port A clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: I/O port D clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: IO port E clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIOHEN - description: I/O port H clock enable - bit_offset: 7 - bit_size: 1 + - name: GPIOAEN + description: IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: IO port A clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: I/O port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: IO port E clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOHEN + description: I/O port H clock enable + bit_offset: 7 + bit_size: 1 fieldset/GPIORSTR: description: GPIO reset register fields: - - name: GPIOARST - description: I/O port A reset - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: I/O port B reset - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: I/O port A reset - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: I/O port D reset - bit_offset: 3 - bit_size: 1 - - name: GPIOERST - description: I/O port E reset - bit_offset: 4 - bit_size: 1 - - name: GPIOHRST - description: I/O port H reset - bit_offset: 7 - bit_size: 1 + - name: GPIOARST + description: I/O port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: I/O port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: I/O port A reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: I/O port D reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: I/O port E reset + bit_offset: 4 + bit_size: 1 + - name: GPIOHRST + description: I/O port H reset + bit_offset: 7 + bit_size: 1 fieldset/GPIOSMEN: description: GPIO clock enable in sleep mode register fields: - - name: GPIOASMEN - description: Port A clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: GPIOBSMEN - description: Port B clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: GPIOCSMEN - description: Port C clock enable during Sleep mode - bit_offset: 2 - bit_size: 1 - - name: GPIODSMEN - description: Port D clock enable during Sleep mode - bit_offset: 3 - bit_size: 1 - - name: GPIOESMEN - description: Port E clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: GPIOHSMEN - description: Port H clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 + - name: GPIOASMEN + description: Port A clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: Port B clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: Port C clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: GPIODSMEN + description: Port D clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: GPIOESMEN + description: Port E clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: GPIOHSMEN + description: Port H clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 fieldset/ICSCR: description: Internal clock sources calibration register fields: - - name: HSI16CAL - description: nternal high speed clock calibration - bit_offset: 0 - bit_size: 8 - - name: HSI16TRIM - description: High speed internal clock trimming - bit_offset: 8 - bit_size: 5 - - name: MSIRANGE - description: MSI clock ranges - bit_offset: 13 - bit_size: 3 - enum: MSIRANGE - - name: MSICAL - description: MSI clock calibration - bit_offset: 16 - bit_size: 8 - - name: MSITRIM - description: MSI clock trimming - bit_offset: 24 - bit_size: 8 + - name: HSI16CAL + description: nternal high speed clock calibration + bit_offset: 0 + bit_size: 8 + - name: HSI16TRIM + description: High speed internal clock trimming + bit_offset: 8 + bit_size: 5 + - name: MSIRANGE + description: MSI clock ranges + bit_offset: 13 + bit_size: 3 + enum: MSIRANGE + - name: MSICAL + description: MSI clock calibration + bit_offset: 16 + bit_size: 8 + - name: MSITRIM + description: MSI clock trimming + bit_offset: 24 + bit_size: 8 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: system clock not divided - value: 0 - - name: Div2 - description: system clock divided by 2 - value: 8 - - name: Div4 - description: system clock divided by 4 - value: 9 - - name: Div8 - description: system clock divided by 8 - value: 10 - - name: Div16 - description: system clock divided by 16 - value: 11 - - name: Div64 - description: system clock divided by 64 - value: 12 - - name: Div128 - description: system clock divided by 128 - value: 13 - - name: Div256 - description: system clock divided by 256 - value: 14 - - name: Div512 - description: system clock divided by 512 - value: 15 + - name: Div1 + description: system clock not divided + value: 0 + - name: Div2 + description: system clock divided by 2 + value: 8 + - name: Div4 + description: system clock divided by 4 + value: 9 + - name: Div8 + description: system clock divided by 8 + value: 10 + - name: Div16 + description: system clock divided by 16 + value: 11 + - name: Div64 + description: system clock divided by 64 + value: 12 + - name: Div128 + description: system clock divided by 128 + value: 13 + - name: Div256 + description: system clock divided by 256 + value: 14 + - name: Div512 + description: system clock divided by 512 + value: 15 enum/ICSEL: bit_size: 2 variants: - - name: APB - description: APB clock selected as peripheral clock - value: 0 - - name: SYSTEM - description: System clock selected as peripheral clock - value: 1 - - name: HSI16 - description: HSI16 clock selected as peripheral clock - value: 2 + - name: APB + description: APB clock selected as peripheral clock + value: 0 + - name: SYSTEM + description: System clock selected as peripheral clock + value: 1 + - name: HSI16 + description: HSI16 clock selected as peripheral clock + value: 2 enum/LPTIMSEL: bit_size: 2 variants: - - name: APB - description: APB clock selected as Timer clock - value: 0 - - name: LSI - description: LSI clock selected as Timer clock - value: 1 - - name: HSI16 - description: HSI16 clock selected as Timer clock - value: 2 - - name: LSE - description: LSE clock selected as Timer clock - value: 3 + - name: APB + description: APB clock selected as Timer clock + value: 0 + - name: LSI + description: LSI clock selected as Timer clock + value: 1 + - name: HSI16 + description: HSI16 clock selected as Timer clock + value: 2 + - name: LSE + description: LSE clock selected as Timer clock + value: 3 enum/LSEDRV: bit_size: 2 variants: - - name: Low - description: Lowest drive - value: 0 - - name: MediumLow - description: Medium low drive - value: 1 - - name: MediumHigh - description: Medium high drive - value: 2 - - name: High - description: Highest drive - value: 3 + - name: Low + description: Lowest drive + value: 0 + - name: MediumLow + description: Medium low drive + value: 1 + - name: MediumHigh + description: Medium high drive + value: 2 + - name: High + description: Highest drive + value: 3 enum/MCOPRE: bit_size: 3 variants: - - name: Div1 - description: No division - value: 0 - - name: Div2 - description: Division by 2 - value: 1 - - name: Div4 - description: Division by 4 - value: 2 - - name: Div8 - description: Division by 8 - value: 3 - - name: Div16 - description: Division by 16 - value: 4 + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 + - name: Div16 + description: Division by 16 + value: 4 enum/MCOSEL: bit_size: 4 variants: - - name: NoClock - description: No clock - value: 0 - - name: SYSCLK - description: SYSCLK clock selected - value: 1 - - name: HSI16 - description: HSI oscillator clock selected - value: 2 - - name: MSI - description: MSI oscillator clock selected - value: 3 - - name: HSE - description: HSE oscillator clock selected - value: 4 - - name: PLL - description: PLL clock selected - value: 5 - - name: LSI - description: LSI oscillator clock selected - value: 6 - - name: LSE - description: LSE oscillator clock selected - value: 7 + - name: NoClock + description: No clock + value: 0 + - name: SYSCLK + description: SYSCLK clock selected + value: 1 + - name: HSI16 + description: HSI oscillator clock selected + value: 2 + - name: MSI + description: MSI oscillator clock selected + value: 3 + - name: HSE + description: HSE oscillator clock selected + value: 4 + - name: PLL + description: PLL clock selected + value: 5 + - name: LSI + description: LSI oscillator clock selected + value: 6 + - name: LSE + description: LSE oscillator clock selected + value: 7 enum/MSIRANGE: bit_size: 3 variants: - - name: Range0 - description: range 0 around 65.536 kHz - value: 0 - - name: Range1 - description: range 1 around 131.072 kHz - value: 1 - - name: Range2 - description: range 2 around 262.144 kHz - value: 2 - - name: Range3 - description: range 3 around 524.288 kHz - value: 3 - - name: Range4 - description: range 4 around 1.048 MHz - value: 4 - - name: Range5 - description: range 5 around 2.097 MHz (reset value) - value: 5 - - name: Range6 - description: range 6 around 4.194 MHz - value: 6 - - name: Range7 - description: not allowed - value: 7 + - name: Range0 + description: range 0 around 65.536 kHz + value: 0 + - name: Range1 + description: range 1 around 131.072 kHz + value: 1 + - name: Range2 + description: range 2 around 262.144 kHz + value: 2 + - name: Range3 + description: range 3 around 524.288 kHz + value: 3 + - name: Range4 + description: range 4 around 1.048 MHz + value: 4 + - name: Range5 + description: range 5 around 2.097 MHz (reset value) + value: 5 + - name: Range6 + description: range 6 around 4.194 MHz + value: 6 + - name: Range7 + description: not allowed + value: 7 enum/PLLDIV: bit_size: 2 variants: - - name: Div2 - description: PLLVCO / 2 - value: 1 - - name: Div3 - description: PLLVCO / 3 - value: 2 - - name: Div4 - description: PLLVCO / 4 - value: 3 + - name: Div2 + description: PLLVCO / 2 + value: 1 + - name: Div3 + description: PLLVCO / 3 + value: 2 + - name: Div4 + description: PLLVCO / 4 + value: 3 enum/PLLMUL: bit_size: 4 variants: - - name: Mul3 - description: PLL clock entry x 3 - value: 0 - - name: Mul4 - description: PLL clock entry x 4 - value: 1 - - name: Mul6 - description: PLL clock entry x 6 - value: 2 - - name: Mul8 - description: PLL clock entry x 8 - value: 3 - - name: Mul12 - description: PLL clock entry x 12 - value: 4 - - name: Mul16 - description: PLL clock entry x 16 - value: 5 - - name: Mul24 - description: PLL clock entry x 24 - value: 6 - - name: Mul32 - description: PLL clock entry x 32 - value: 7 - - name: Mul48 - description: PLL clock entry x 48 - value: 8 + - name: Mul3 + description: PLL clock entry x 3 + value: 0 + - name: Mul4 + description: PLL clock entry x 4 + value: 1 + - name: Mul6 + description: PLL clock entry x 6 + value: 2 + - name: Mul8 + description: PLL clock entry x 8 + value: 3 + - name: Mul12 + description: PLL clock entry x 12 + value: 4 + - name: Mul16 + description: PLL clock entry x 16 + value: 5 + - name: Mul24 + description: PLL clock entry x 24 + value: 6 + - name: Mul32 + description: PLL clock entry x 32 + value: 7 + - name: Mul48 + description: PLL clock entry x 48 + value: 8 enum/PLLSRC: bit_size: 1 variants: - - name: HSI16 - description: HSI selected as PLL input clock - value: 0 - - name: HSE - description: HSE selected as PLL input clock - value: 1 + - name: HSI16 + description: HSI selected as PLL input clock + value: 0 + - name: HSE + description: HSE selected as PLL input clock + value: 1 enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK divided by 2 - value: 4 - - name: Div4 - description: HCLK divided by 4 - value: 5 - - name: Div8 - description: HCLK divided by 8 - value: 6 - - name: Div16 - description: HCLK divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 enum/RTCPRE: bit_size: 2 variants: - - name: Div2 - description: HSE divided by 2 - value: 0 - - name: Div4 - description: HSE divided by 4 - value: 1 - - name: Div8 - description: HSE divided by 8 - value: 2 - - name: Div16 - description: HSE divided by 16 - value: 3 + - name: Div2 + description: HSE divided by 2 + value: 0 + - name: Div4 + description: HSE divided by 4 + value: 1 + - name: Div8 + description: HSE divided by 8 + value: 2 + - name: Div16 + description: HSE divided by 16 + value: 3 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: "HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock" - value: 3 + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock + value: 3 enum/STOPWUCK: bit_size: 1 variants: - - name: MSI - description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock - value: 0 - - name: HSI16 - description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1) - value: 1 + - name: MSI + description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock + value: 0 + - name: HSI16 + description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1) + value: 1 enum/SW: bit_size: 2 variants: - - name: MSI - description: MSI oscillator used as system clock - value: 0 - - name: HSI16 - description: HSI oscillator used as system clock - value: 1 - - name: HSE - description: HSE oscillator used as system clock - value: 2 - - name: PLL - description: PLL used as system clock - value: 3 + - name: MSI + description: MSI oscillator used as system clock + value: 0 + - name: HSI16 + description: HSI oscillator used as system clock + value: 1 + - name: HSE + description: HSE oscillator used as system clock + value: 2 + - name: PLL + description: PLL used as system clock + value: 3 enum/UARTSEL: bit_size: 2 variants: - - name: APB - description: APB clock selected as peripheral clock - value: 0 - - name: SYSTEM - description: System clock selected as peripheral clock - value: 1 - - name: HSI16 - description: HSI16 clock selected as peripheral clock - value: 2 - - name: LSE - description: LSE clock selected as peripheral clock - value: 3 + - name: APB + description: APB clock selected as peripheral clock + value: 0 + - name: SYSTEM + description: System clock selected as peripheral clock + value: 1 + - name: HSI16 + description: HSI16 clock selected as peripheral clock + value: 2 + - name: LSE + description: LSE clock selected as peripheral clock + value: 3 diff --git a/data/registers/rcc_l1.yaml b/data/registers/rcc_l1.yaml index f7995d5..540fb3a 100644 --- a/data/registers/rcc_l1.yaml +++ b/data/registers/rcc_l1.yaml @@ -1,1051 +1,1050 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: Clock control register - byte_offset: 0 - fieldset: CR - - name: ICSCR - description: Internal clock sources calibration register - byte_offset: 4 - fieldset: ICSCR - - name: CFGR - description: Clock configuration register - byte_offset: 8 - fieldset: CFGR - - name: CIR - description: Clock interrupt register - byte_offset: 12 - fieldset: CIR - - name: AHBRSTR - description: AHB peripheral reset register - byte_offset: 16 - fieldset: AHBRSTR - - name: APB2RSTR - description: APB2 peripheral reset register - byte_offset: 20 - fieldset: APB2RSTR - - name: APB1RSTR - description: APB1 peripheral reset register - byte_offset: 24 - fieldset: APB1RSTR - - name: AHBENR - description: AHB peripheral clock enable register - byte_offset: 28 - fieldset: AHBENR - - name: APB2ENR - description: APB2 peripheral clock enable register - byte_offset: 32 - fieldset: APB2ENR - - name: APB1ENR - description: APB1 peripheral clock enable register - byte_offset: 36 - fieldset: APB1ENR - - name: AHBLPENR - description: AHB peripheral clock enable in low power mode register - byte_offset: 40 - fieldset: AHBLPENR - - name: APB2LPENR - description: APB2 peripheral clock enable in low power mode register - byte_offset: 44 - fieldset: APB2LPENR - - name: APB1LPENR - description: APB1 peripheral clock enable in low power mode register - byte_offset: 48 - fieldset: APB1LPENR - - name: CSR - description: Control/status register - byte_offset: 52 - fieldset: CSR + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: Internal clock sources calibration register + byte_offset: 4 + fieldset: ICSCR + - name: CFGR + description: Clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: CIR + description: Clock interrupt register + byte_offset: 12 + fieldset: CIR + - name: AHBRSTR + description: AHB peripheral reset register + byte_offset: 16 + fieldset: AHBRSTR + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 20 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register + byte_offset: 24 + fieldset: APB1RSTR + - name: AHBENR + description: AHB peripheral clock enable register + byte_offset: 28 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register + byte_offset: 32 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register + byte_offset: 36 + fieldset: APB1ENR + - name: AHBLPENR + description: AHB peripheral clock enable in low power mode register + byte_offset: 40 + fieldset: AHBLPENR + - name: APB2LPENR + description: APB2 peripheral clock enable in low power mode register + byte_offset: 44 + fieldset: APB2LPENR + - name: APB1LPENR + description: APB1 peripheral clock enable in low power mode register + byte_offset: 48 + fieldset: APB1LPENR + - name: CSR + description: Control/status register + byte_offset: 52 + fieldset: CSR fieldset/AHBENR: description: AHB peripheral clock enable register fields: - - name: GPIOAEN - description: IO port A clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: IO port B clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: IO port C clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: IO port D clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: IO port E clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIOHEN - description: IO port H clock enable - bit_offset: 5 - bit_size: 1 - - name: GPIOFEN - description: IO port F clock enable - bit_offset: 6 - bit_size: 1 - - name: GPIOGEN - description: IO port G clock enable - bit_offset: 7 - bit_size: 1 - - name: CRCEN - description: CRC clock enable - bit_offset: 12 - bit_size: 1 - - name: FLASHEN - description: FLASH clock enable - bit_offset: 15 - bit_size: 1 - - name: DMA1EN - description: DMA1 clock enable - bit_offset: 24 - bit_size: 1 - - name: DMA2EN - description: DMA2 clock enable - bit_offset: 25 - bit_size: 1 - - name: FSMCEN - description: FSMCEN - bit_offset: 30 - bit_size: 1 + - name: GPIOAEN + description: IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: IO port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: IO port E clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOHEN + description: IO port H clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOFEN + description: IO port F clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOGEN + description: IO port G clock enable + bit_offset: 7 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: FLASHEN + description: FLASH clock enable + bit_offset: 15 + bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 24 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 25 + bit_size: 1 + - name: FSMCEN + description: FSMCEN + bit_offset: 30 + bit_size: 1 fieldset/AHBLPENR: description: AHB peripheral clock enable in low power mode register fields: - - name: GPIOALPEN - description: IO port A clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: GPIOBLPEN - description: IO port B clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: GPIOCLPEN - description: IO port C clock enable during Sleep mode - bit_offset: 2 - bit_size: 1 - - name: GPIODLPEN - description: IO port D clock enable during Sleep mode - bit_offset: 3 - bit_size: 1 - - name: GPIOELPEN - description: IO port E clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: GPIOHLPEN - description: IO port H clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: GPIOFLPEN - description: IO port F clock enable during Sleep mode - bit_offset: 6 - bit_size: 1 - - name: GPIOGLPEN - description: IO port G clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 - - name: CRCLPEN - description: CRC clock enable during Sleep mode - bit_offset: 12 - bit_size: 1 - - name: FLASHLPEN - description: FLASH clock enable during Sleep mode - bit_offset: 15 - bit_size: 1 - - name: SRAMLPEN - description: SRAM clock enable during Sleep mode - bit_offset: 16 - bit_size: 1 - - name: DMA1LPEN - description: DMA1 clock enable during Sleep mode - bit_offset: 24 - bit_size: 1 - - name: DMA2LPEN - description: DMA2 clock enable during Sleep mode - bit_offset: 25 - bit_size: 1 + - name: GPIOALPEN + description: IO port A clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: IO port B clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: IO port C clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: GPIODLPEN + description: IO port D clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: GPIOELPEN + description: IO port E clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: GPIOHLPEN + description: IO port H clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: GPIOFLPEN + description: IO port F clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: GPIOGLPEN + description: IO port G clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: CRCLPEN + description: CRC clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: FLASHLPEN + description: FLASH clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: SRAMLPEN + description: SRAM clock enable during Sleep mode + bit_offset: 16 + bit_size: 1 + - name: DMA1LPEN + description: DMA1 clock enable during Sleep mode + bit_offset: 24 + bit_size: 1 + - name: DMA2LPEN + description: DMA2 clock enable during Sleep mode + bit_offset: 25 + bit_size: 1 fieldset/AHBRSTR: description: AHB peripheral reset register fields: - - name: GPIOARST - description: IO port A reset - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: IO port B reset - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: IO port C reset - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: IO port D reset - bit_offset: 3 - bit_size: 1 - - name: GPIOERST - description: IO port E reset - bit_offset: 4 - bit_size: 1 - - name: GPIOHRST - description: IO port H reset - bit_offset: 5 - bit_size: 1 - - name: GPIOFRST - description: IO port F reset - bit_offset: 6 - bit_size: 1 - - name: GPIOGRST - description: IO port G reset - bit_offset: 7 - bit_size: 1 - - name: CRCRST - description: CRC reset - bit_offset: 12 - bit_size: 1 - - name: FLASHRST - description: FLASH reset - bit_offset: 15 - bit_size: 1 - - name: DMA1RST - description: DMA1 reset - bit_offset: 24 - bit_size: 1 - - name: DMA2RST - description: DMA2 reset - bit_offset: 25 - bit_size: 1 - - name: FSMCRST - description: FSMC reset - bit_offset: 30 - bit_size: 1 + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 4 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 5 + bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 6 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 7 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 + - name: FLASHRST + description: FLASH reset + bit_offset: 15 + bit_size: 1 + - name: DMA1RST + description: DMA1 reset + bit_offset: 24 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 25 + bit_size: 1 + - name: FSMCRST + description: FSMC reset + bit_offset: 30 + bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register fields: - - name: TIM2EN - description: Timer 2 clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: Timer 3 clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: Timer 4 clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: Timer 5 clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: Timer 6 clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: Timer 7 clock enable - bit_offset: 5 - bit_size: 1 - - name: LCDEN - description: LCD clock enable - bit_offset: 9 - bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI 2 clock enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI 3 clock enable - bit_offset: 15 - bit_size: 1 - - name: USART2EN - description: USART 2 clock enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART 3 clock enable - bit_offset: 18 - bit_size: 1 - - name: USART4EN - description: UART 4 clock enable - bit_offset: 19 - bit_size: 1 - - name: USART5EN - description: UART 5 clock enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C 1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C 2 clock enable - bit_offset: 22 - bit_size: 1 - - name: USBEN - description: USB clock enable - bit_offset: 23 - bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - - name: DACEN - description: DAC interface clock enable - bit_offset: 29 - bit_size: 1 - - name: COMPEN - description: COMP interface clock enable - bit_offset: 31 - bit_size: 1 + - name: TIM2EN + description: Timer 2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: Timer 4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: Timer 5 clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: Timer 7 clock enable + bit_offset: 5 + bit_size: 1 + - name: LCDEN + description: LCD clock enable + bit_offset: 9 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI 2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI 3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART 3 clock enable + bit_offset: 18 + bit_size: 1 + - name: USART4EN + description: UART 4 clock enable + bit_offset: 19 + bit_size: 1 + - name: USART5EN + description: UART 5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C 2 clock enable + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: USB clock enable + bit_offset: 23 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: COMPEN + description: COMP interface clock enable + bit_offset: 31 + bit_size: 1 fieldset/APB1LPENR: description: APB1 peripheral clock enable in low power mode register fields: - - name: TIM2LPEN - description: Timer 2 clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM3LPEN - description: Timer 3 clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: TIM4LPEN - description: Timer 4 clock enable during Sleep mode - bit_offset: 2 - bit_size: 1 - - name: TIM6LPEN - description: Timer 6 clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: TIM7LPEN - description: Timer 7 clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: LCDLPEN - description: LCD clock enable during Sleep mode - bit_offset: 9 - bit_size: 1 - - name: WWDGLPEN - description: Window watchdog clock enable during Sleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI2LPEN - description: SPI 2 clock enable during Sleep mode - bit_offset: 14 - bit_size: 1 - - name: USART2LPEN - description: USART 2 clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: USART3LPEN - description: USART 3 clock enable during Sleep mode - bit_offset: 18 - bit_size: 1 - - name: I2C1LPEN - description: I2C 1 clock enable during Sleep mode - bit_offset: 21 - bit_size: 1 - - name: I2C2LPEN - description: I2C 2 clock enable during Sleep mode - bit_offset: 22 - bit_size: 1 - - name: USBLPEN - description: USB clock enable during Sleep mode - bit_offset: 23 - bit_size: 1 - - name: PWRLPEN - description: Power interface clock enable during Sleep mode - bit_offset: 28 - bit_size: 1 - - name: DACLPEN - description: DAC interface clock enable during Sleep mode - bit_offset: 29 - bit_size: 1 - - name: COMPLPEN - description: COMP interface clock enable during Sleep mode - bit_offset: 31 - bit_size: 1 + - name: TIM2LPEN + description: Timer 2 clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM3LPEN + description: Timer 3 clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: TIM4LPEN + description: Timer 4 clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: TIM6LPEN + description: Timer 6 clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: TIM7LPEN + description: Timer 7 clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: LCDLPEN + description: LCD clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: WWDGLPEN + description: Window watchdog clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI2LPEN + description: SPI 2 clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: USART2LPEN + description: USART 2 clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: USART3LPEN + description: USART 3 clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: I2C1LPEN + description: I2C 1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: I2C 2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: USBLPEN + description: USB clock enable during Sleep mode + bit_offset: 23 + bit_size: 1 + - name: PWRLPEN + description: Power interface clock enable during Sleep mode + bit_offset: 28 + bit_size: 1 + - name: DACLPEN + description: DAC interface clock enable during Sleep mode + bit_offset: 29 + bit_size: 1 + - name: COMPLPEN + description: COMP interface clock enable during Sleep mode + bit_offset: 31 + bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register fields: - - name: TIM2RST - description: Timer 2 reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: Timer 3 reset - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: Timer 4 reset - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: Timer 5 reset - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: Timer 6reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: Timer 7 reset - bit_offset: 5 - bit_size: 1 - - name: LCDRST - description: LCD reset - bit_offset: 9 - bit_size: 1 - - name: WWDRST - description: Window watchdog reset - bit_offset: 11 - bit_size: 1 - - name: SPI2RST - description: SPI 2 reset - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: SPI 3 reset - bit_offset: 15 - bit_size: 1 - - name: USART2RST - description: USART 2 reset - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: USART 3 reset - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: UART 4 reset - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: UART 5 reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C 1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C 2 reset - bit_offset: 22 - bit_size: 1 - - name: USBRST - description: USB reset - bit_offset: 23 - bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - - name: DACRST - description: DAC interface reset - bit_offset: 29 - bit_size: 1 - - name: COMPRST - description: COMP interface reset - bit_offset: 31 - bit_size: 1 + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: Timer 4 reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: Timer 5 reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: Timer 6reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: Timer 7 reset + bit_offset: 5 + bit_size: 1 + - name: LCDRST + description: LCD reset + bit_offset: 9 + bit_size: 1 + - name: WWDRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI 2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI 3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART 3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: UART 4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: UART 5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C 1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C 2 reset + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: USB reset + bit_offset: 23 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 + - name: COMPRST + description: COMP interface reset + bit_offset: 31 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - - name: SYSCFGEN - description: System configuration controller clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM9EN - description: TIM9 timer clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM10EN - description: TIM10 timer clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM11EN - description: TIM11 timer clock enable - bit_offset: 4 - bit_size: 1 - - name: ADC1EN - description: ADC1 interface clock enable - bit_offset: 9 - bit_size: 1 - - name: SDIOEN - description: SDIO clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: SPI 1 clock enable - bit_offset: 12 - bit_size: 1 - - name: USART1EN - description: USART1 clock enable - bit_offset: 14 - bit_size: 1 + - name: SYSCFGEN + description: System configuration controller clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM9EN + description: TIM9 timer clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM10EN + description: TIM10 timer clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM11EN + description: TIM11 timer clock enable + bit_offset: 4 + bit_size: 1 + - name: ADC1EN + description: ADC1 interface clock enable + bit_offset: 9 + bit_size: 1 + - name: SDIOEN + description: SDIO clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 fieldset/APB2LPENR: description: APB2 peripheral clock enable in low power mode register fields: - - name: SYSCFGLPEN - description: System configuration controller clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM9LPEN - description: TIM9 timer clock enable during Sleep mode - bit_offset: 2 - bit_size: 1 - - name: TIM10LPEN - description: TIM10 timer clock enable during Sleep mode - bit_offset: 3 - bit_size: 1 - - name: TIM11LPEN - description: TIM11 timer clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: ADC1LPEN - description: ADC1 interface clock enable during Sleep mode - bit_offset: 9 - bit_size: 1 - - name: SDIOLPEN - description: SDIO clock enable during Sleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI1LPEN - description: SPI 1 clock enable during Sleep mode - bit_offset: 12 - bit_size: 1 - - name: USART1LPEN - description: USART1 clock enable during Sleep mode - bit_offset: 14 - bit_size: 1 + - name: SYSCFGLPEN + description: System configuration controller clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM9LPEN + description: TIM9 timer clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: TIM10LPEN + description: TIM10 timer clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: TIM11LPEN + description: TIM11 timer clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: ADC1LPEN + description: ADC1 interface clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: SDIOLPEN + description: SDIO clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI1LPEN + description: SPI 1 clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: USART1LPEN + description: USART1 clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - - name: SYSCFGRST - description: SYSCFGRST - bit_offset: 0 - bit_size: 1 - - name: TIM9RST - description: TIM9RST - bit_offset: 2 - bit_size: 1 - - name: TM10RST - description: TM10RST - bit_offset: 3 - bit_size: 1 - - name: TM11RST - description: TM11RST - bit_offset: 4 - bit_size: 1 - - name: ADC1RST - description: ADC1RST - bit_offset: 9 - bit_size: 1 - - name: SDIORST - description: SDIORST - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: SPI1RST - bit_offset: 12 - bit_size: 1 - - name: USART1RST - description: USART1RST - bit_offset: 14 - bit_size: 1 + - name: SYSCFGRST + description: SYSCFGRST + bit_offset: 0 + bit_size: 1 + - name: TIM9RST + description: TIM9RST + bit_offset: 2 + bit_size: 1 + - name: TM10RST + description: TM10RST + bit_offset: 3 + bit_size: 1 + - name: TM11RST + description: TM11RST + bit_offset: 4 + bit_size: 1 + - name: ADC1RST + description: ADC1RST + bit_offset: 9 + bit_size: 1 + - name: SDIORST + description: SDIORST + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI1RST + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1RST + bit_offset: 14 + bit_size: 1 fieldset/CFGR: description: Clock configuration register fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: System clock switch status - bit_offset: 2 - bit_size: 2 - enum: SW - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - enum: HPRE - - name: PPRE1 - description: APB low-speed prescaler (APB1) - bit_offset: 8 - bit_size: 3 - enum: PPRE - - name: PPRE2 - description: APB high-speed prescaler (APB2) - bit_offset: 11 - bit_size: 3 - enum: PPRE - - name: PLLSRC - description: PLL entry clock source - bit_offset: 16 - bit_size: 1 - enum: PLLSRC - - name: PLLMUL - description: PLL multiplication factor - bit_offset: 18 - bit_size: 4 - enum: PLLMUL - - name: PLLDIV - description: PLL output division - bit_offset: 22 - bit_size: 2 - enum: PLLDIV - - name: MCOSEL - description: Microcontroller clock output selection - bit_offset: 24 - bit_size: 3 - enum: MCOSEL - - name: MCOPRE - description: Microcontroller clock output prescaler - bit_offset: 28 - bit_size: 3 - enum: MCOPRE + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB low-speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high-speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: PLLSRC + description: PLL entry clock source + bit_offset: 16 + bit_size: 1 + enum: PLLSRC + - name: PLLMUL + description: PLL multiplication factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: PLLDIV + description: PLL output division + bit_offset: 22 + bit_size: 2 + enum: PLLDIV + - name: MCOSEL + description: Microcontroller clock output selection + bit_offset: 24 + bit_size: 3 + enum: MCOSEL + - name: MCOPRE + description: Microcontroller clock output prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE fieldset/CIR: description: Clock interrupt register fields: - - name: LSIRDYF - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - - name: HSIRDYF - description: HSI ready interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSERDYF - description: HSE ready interrupt flag - bit_offset: 3 - bit_size: 1 - - name: PLLRDYF - description: PLL ready interrupt flag - bit_offset: 4 - bit_size: 1 - - name: MSIRDYF - description: MSI ready interrupt flag - bit_offset: 5 - bit_size: 1 - - name: CSSF - description: Clock security system interrupt flag - bit_offset: 7 - bit_size: 1 - - name: LSIRDYIE - description: LSI ready interrupt enable - bit_offset: 8 - bit_size: 1 - - name: LSERDYIE - description: LSE ready interrupt enable - bit_offset: 9 - bit_size: 1 - - name: HSIRDYIE - description: HSI ready interrupt enable - bit_offset: 10 - bit_size: 1 - - name: HSERDYIE - description: HSE ready interrupt enable - bit_offset: 11 - bit_size: 1 - - name: PLLRDYIE - description: PLL ready interrupt enable - bit_offset: 12 - bit_size: 1 - - name: MSIRDYIE - description: MSI ready interrupt enable - bit_offset: 13 - bit_size: 1 - - name: LSIRDYC - description: LSI ready interrupt clear - bit_offset: 16 - bit_size: 1 - - name: LSERDYC - description: LSE ready interrupt clear - bit_offset: 17 - bit_size: 1 - - name: HSIRDYC - description: HSI ready interrupt clear - bit_offset: 18 - bit_size: 1 - - name: HSERDYC - description: HSE ready interrupt clear - bit_offset: 19 - bit_size: 1 - - name: PLLRDYC - description: PLL ready interrupt clear - bit_offset: 20 - bit_size: 1 - - name: MSIRDYC - description: MSI ready interrupt clear - bit_offset: 21 - bit_size: 1 - - name: CSSC - description: Clock security system interrupt clear - bit_offset: 23 - bit_size: 1 + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: PLL ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: MSIRDYF + description: MSI ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: CSSF + description: Clock security system interrupt flag + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: PLL ready interrupt enable + bit_offset: 12 + bit_size: 1 + - name: MSIRDYIE + description: MSI ready interrupt enable + bit_offset: 13 + bit_size: 1 + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: PLL ready interrupt clear + bit_offset: 20 + bit_size: 1 + - name: MSIRDYC + description: MSI ready interrupt clear + bit_offset: 21 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 fieldset/CR: description: Clock control register fields: - - name: HSION - description: Internal high-speed clock enable - bit_offset: 0 - bit_size: 1 - - name: HSIRDY - description: Internal high-speed clock ready flag - bit_offset: 1 - bit_size: 1 - - name: MSION - description: MSI clock enable - bit_offset: 8 - bit_size: 1 - - name: MSIRDY - description: MSI clock ready flag - bit_offset: 9 - bit_size: 1 - - name: HSEON - description: HSE clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: HSE clock bypass - bit_offset: 18 - bit_size: 1 - - name: PLLON - description: PLL enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: PLL clock ready flag - bit_offset: 25 - bit_size: 1 - - name: CSSON - description: Clock security system enable - bit_offset: 28 - bit_size: 1 - - name: RTCPRE - description: RTC/LCD prescaler - bit_offset: 29 - bit_size: 2 - enum: RTCPRE + - name: HSION + description: Internal high-speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal high-speed clock ready flag + bit_offset: 1 + bit_size: 1 + - name: MSION + description: MSI clock enable + bit_offset: 8 + bit_size: 1 + - name: MSIRDY + description: MSI clock ready flag + bit_offset: 9 + bit_size: 1 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: HSE clock bypass + bit_offset: 18 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 + - name: CSSON + description: Clock security system enable + bit_offset: 28 + bit_size: 1 + - name: RTCPRE + description: RTC/LCD prescaler + bit_offset: 29 + bit_size: 2 + enum: RTCPRE fieldset/CSR: description: Control and status register fields: - - name: LSION - description: Internal low-speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: Internal low-speed oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEON - description: External low-speed oscillator enable - bit_offset: 8 - bit_size: 1 - - name: LSERDY - description: External low-speed oscillator ready - bit_offset: 9 - bit_size: 1 - - name: LSEBYP - description: External low-speed oscillator bypass - bit_offset: 10 - bit_size: 1 - - name: RTCSEL - description: RTC and LCD clock source selection - bit_offset: 16 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 22 - bit_size: 1 - - name: RTCRST - description: RTC software reset - bit_offset: 23 - bit_size: 1 - - name: RMVF - description: Remove reset flag - bit_offset: 24 - bit_size: 1 - - name: PINRSTF - description: PIN reset flag - bit_offset: 26 - bit_size: 1 - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: Independent watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSION + description: Internal low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low-speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEON + description: External low-speed oscillator enable + bit_offset: 8 + bit_size: 1 + - name: LSERDY + description: External low-speed oscillator ready + bit_offset: 9 + bit_size: 1 + - name: LSEBYP + description: External low-speed oscillator bypass + bit_offset: 10 + bit_size: 1 + - name: RTCSEL + description: RTC and LCD clock source selection + bit_offset: 16 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 22 + bit_size: 1 + - name: RTCRST + description: RTC software reset + bit_offset: 23 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 fieldset/ICSCR: description: Internal clock sources calibration register fields: - - name: HSICAL - description: nternal high speed clock calibration - bit_offset: 0 - bit_size: 8 - - name: HSITRIM - description: High speed internal clock trimming - bit_offset: 8 - bit_size: 5 - - name: MSIRANGE - description: MSI clock ranges - bit_offset: 13 - bit_size: 3 - enum: MSIRANGE - - name: MSICAL - description: MSI clock calibration - bit_offset: 16 - bit_size: 8 - - name: MSITRIM - description: MSI clock trimming - bit_offset: 24 - bit_size: 8 + - name: HSICAL + description: nternal high speed clock calibration + bit_offset: 0 + bit_size: 8 + - name: HSITRIM + description: High speed internal clock trimming + bit_offset: 8 + bit_size: 5 + - name: MSIRANGE + description: MSI clock ranges + bit_offset: 13 + bit_size: 3 + enum: MSIRANGE + - name: MSICAL + description: MSI clock calibration + bit_offset: 16 + bit_size: 8 + - name: MSITRIM + description: MSI clock trimming + bit_offset: 24 + bit_size: 8 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: system clock not divided - value: 0 - - name: Div2 - description: system clock divided by 2 - value: 8 - - name: Div4 - description: system clock divided by 4 - value: 9 - - name: Div8 - description: system clock divided by 8 - value: 10 - - name: Div16 - description: system clock divided by 16 - value: 11 - - name: Div64 - description: system clock divided by 64 - value: 12 - - name: Div128 - description: system clock divided by 128 - value: 13 - - name: Div256 - description: system clock divided by 256 - value: 14 - - name: Div512 - description: system clock divided by 512 - value: 15 + - name: Div1 + description: system clock not divided + value: 0 + - name: Div2 + description: system clock divided by 2 + value: 8 + - name: Div4 + description: system clock divided by 4 + value: 9 + - name: Div8 + description: system clock divided by 8 + value: 10 + - name: Div16 + description: system clock divided by 16 + value: 11 + - name: Div64 + description: system clock divided by 64 + value: 12 + - name: Div128 + description: system clock divided by 128 + value: 13 + - name: Div256 + description: system clock divided by 256 + value: 14 + - name: Div512 + description: system clock divided by 512 + value: 15 enum/MCOPRE: bit_size: 3 variants: - - name: Div1 - description: No division - value: 0 - - name: Div2 - description: Division by 2 - value: 1 - - name: Div4 - description: Division by 4 - value: 2 - - name: Div8 - description: Division by 8 - value: 3 - - name: Div16 - description: Division by 16 - value: 4 + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 + - name: Div16 + description: Division by 16 + value: 4 enum/MCOSEL: bit_size: 4 variants: - - name: NoClock - description: No clock - value: 0 - - name: SYSCLK - description: SYSCLK clock selected - value: 1 - - name: HSI - description: HSI oscillator clock selected - value: 2 - - name: MSI - description: MSI oscillator clock selected - value: 3 - - name: HSE - description: HSE oscillator clock selected - value: 4 - - name: PLL - description: PLL clock selected - value: 5 - - name: LSI - description: LSI oscillator clock selected - value: 6 - - name: LSE - description: LSE oscillator clock selected - value: 7 + - name: NoClock + description: No clock + value: 0 + - name: SYSCLK + description: SYSCLK clock selected + value: 1 + - name: HSI + description: HSI oscillator clock selected + value: 2 + - name: MSI + description: MSI oscillator clock selected + value: 3 + - name: HSE + description: HSE oscillator clock selected + value: 4 + - name: PLL + description: PLL clock selected + value: 5 + - name: LSI + description: LSI oscillator clock selected + value: 6 + - name: LSE + description: LSE oscillator clock selected + value: 7 enum/MSIRANGE: bit_size: 3 variants: - - name: Range0 - description: range 0 around 65.536 kHz - value: 0 - - name: Range1 - description: range 1 around 131.072 kHz - value: 1 - - name: Range2 - description: range 2 around 262.144 kHz - value: 2 - - name: Range3 - description: range 3 around 524.288 kHz - value: 3 - - name: Range4 - description: range 4 around 1.048 MHz - value: 4 - - name: Range5 - description: range 5 around 2.097 MHz (reset value) - value: 5 - - name: Range6 - description: range 6 around 4.194 MHz - value: 6 - - name: Range7 - description: not allowed - value: 7 + - name: Range0 + description: range 0 around 65.536 kHz + value: 0 + - name: Range1 + description: range 1 around 131.072 kHz + value: 1 + - name: Range2 + description: range 2 around 262.144 kHz + value: 2 + - name: Range3 + description: range 3 around 524.288 kHz + value: 3 + - name: Range4 + description: range 4 around 1.048 MHz + value: 4 + - name: Range5 + description: range 5 around 2.097 MHz (reset value) + value: 5 + - name: Range6 + description: range 6 around 4.194 MHz + value: 6 + - name: Range7 + description: not allowed + value: 7 enum/PLLDIV: bit_size: 2 variants: - - name: Div2 - description: PLLVCO / 2 - value: 1 - - name: Div3 - description: PLLVCO / 3 - value: 2 - - name: Div4 - description: PLLVCO / 4 - value: 3 + - name: Div2 + description: PLLVCO / 2 + value: 1 + - name: Div3 + description: PLLVCO / 3 + value: 2 + - name: Div4 + description: PLLVCO / 4 + value: 3 enum/PLLMUL: bit_size: 4 variants: - - name: Mul3 - description: PLL clock entry x 3 - value: 0 - - name: Mul4 - description: PLL clock entry x 4 - value: 1 - - name: Mul6 - description: PLL clock entry x 6 - value: 2 - - name: Mul8 - description: PLL clock entry x 8 - value: 3 - - name: Mul12 - description: PLL clock entry x 12 - value: 4 - - name: Mul16 - description: PLL clock entry x 16 - value: 5 - - name: Mul24 - description: PLL clock entry x 24 - value: 6 - - name: Mul32 - description: PLL clock entry x 32 - value: 7 - - name: Mul48 - description: PLL clock entry x 48 - value: 8 + - name: Mul3 + description: PLL clock entry x 3 + value: 0 + - name: Mul4 + description: PLL clock entry x 4 + value: 1 + - name: Mul6 + description: PLL clock entry x 6 + value: 2 + - name: Mul8 + description: PLL clock entry x 8 + value: 3 + - name: Mul12 + description: PLL clock entry x 12 + value: 4 + - name: Mul16 + description: PLL clock entry x 16 + value: 5 + - name: Mul24 + description: PLL clock entry x 24 + value: 6 + - name: Mul32 + description: PLL clock entry x 32 + value: 7 + - name: Mul48 + description: PLL clock entry x 48 + value: 8 enum/PLLSRC: bit_size: 1 variants: - - name: HSI - description: HSI selected as PLL input clock - value: 0 - - name: HSE - description: HSE selected as PLL input clock - value: 1 + - name: HSI + description: HSI selected as PLL input clock + value: 0 + - name: HSE + description: HSE selected as PLL input clock + value: 1 enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK divided by 2 - value: 4 - - name: Div4 - description: HCLK divided by 4 - value: 5 - - name: Div8 - description: HCLK divided by 8 - value: 6 - - name: Div16 - description: HCLK divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 enum/RTCPRE: bit_size: 2 variants: - - name: Div2 - description: HSE divided by 2 - value: 0 - - name: Div4 - description: HSE divided by 4 - value: 1 - - name: Div8 - description: HSE divided by 8 - value: 2 - - name: Div16 - description: HSE divided by 16 - value: 3 + - name: Div2 + description: HSE divided by 2 + value: 0 + - name: Div4 + description: HSE divided by 4 + value: 1 + - name: Div8 + description: HSE divided by 8 + value: 2 + - name: Div16 + description: HSE divided by 16 + value: 3 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: "HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock" - value: 3 + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock + value: 3 enum/SW: bit_size: 2 variants: - - name: MSI - description: MSI oscillator used as system clock - value: 0 - - name: HSI - description: HSI oscillator used as system clock - value: 1 - - name: HSE - description: HSE oscillator used as system clock - value: 2 - - name: PLL - description: PLL used as system clock - value: 3 + - name: MSI + description: MSI oscillator used as system clock + value: 0 + - name: HSI + description: HSI oscillator used as system clock + value: 1 + - name: HSE + description: HSE oscillator used as system clock + value: 2 + - name: PLL + description: PLL used as system clock + value: 3 diff --git a/data/registers/rcc_l4.yaml b/data/registers/rcc_l4.yaml index 4fd140e..3a95b4b 100644 --- a/data/registers/rcc_l4.yaml +++ b/data/registers/rcc_l4.yaml @@ -1,1910 +1,1909 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: Clock control register - byte_offset: 0 - fieldset: CR - - name: ICSCR - description: Internal clock sources calibration register - byte_offset: 4 - fieldset: ICSCR - - name: CFGR - description: Clock configuration register - byte_offset: 8 - fieldset: CFGR - - name: PLLCFGR - description: PLL configuration register - byte_offset: 12 - fieldset: PLLCFGR - - name: PLLSAI1CFGR - description: PLLSAI1 configuration register - byte_offset: 16 - fieldset: PLLSAI1CFGR - - name: PLLSAI2CFGR - description: PLLSAI2 configuration register - byte_offset: 20 - fieldset: PLLSAI2CFGR - - name: CIER - description: Clock interrupt enable register - byte_offset: 24 - fieldset: CIER - - name: CIFR - description: Clock interrupt flag register - byte_offset: 28 - access: Read - fieldset: CIFR - - name: CICR - description: Clock interrupt clear register - byte_offset: 32 - access: Write - fieldset: CICR - - name: AHB1RSTR - description: AHB1 peripheral reset register - byte_offset: 40 - fieldset: AHB1RSTR - - name: AHB2RSTR - description: AHB2 peripheral reset register - byte_offset: 44 - fieldset: AHB2RSTR - - name: AHB3RSTR - description: AHB3 peripheral reset register - byte_offset: 48 - fieldset: AHB3RSTR - - name: APB1RSTR1 - description: APB1 peripheral reset register 1 - byte_offset: 56 - fieldset: APB1RSTR1 - - name: APB1RSTR2 - description: APB1 peripheral reset register 2 - byte_offset: 60 - fieldset: APB1RSTR2 - - name: APB2RSTR - description: APB2 peripheral reset register - byte_offset: 64 - fieldset: APB2RSTR - - name: AHB1ENR - description: AHB1 peripheral clock enable register - byte_offset: 72 - fieldset: AHB1ENR - - name: AHB2ENR - description: AHB2 peripheral clock enable register - byte_offset: 76 - fieldset: AHB2ENR - - name: AHB3ENR - description: AHB3 peripheral clock enable register - byte_offset: 80 - fieldset: AHB3ENR - - name: APB1ENR1 - description: APB1ENR1 - byte_offset: 88 - fieldset: APB1ENR1 - - name: APB1ENR2 - description: APB1 peripheral clock enable register 2 - byte_offset: 92 - fieldset: APB1ENR2 - - name: APB2ENR - description: APB2ENR - byte_offset: 96 - fieldset: APB2ENR - - name: AHB1SMENR - description: AHB1 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 104 - fieldset: AHB1SMENR - - name: AHB2SMENR - description: AHB2 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 108 - fieldset: AHB2SMENR - - name: AHB3SMENR - description: AHB3 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 112 - fieldset: AHB3SMENR - - name: APB1SMENR1 - description: APB1SMENR1 - byte_offset: 120 - fieldset: APB1SMENR1 - - name: APB1SMENR2 - description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 - byte_offset: 124 - fieldset: APB1SMENR2 - - name: APB2SMENR - description: APB2SMENR - byte_offset: 128 - fieldset: APB2SMENR - - name: CCIPR - description: CCIPR - byte_offset: 136 - fieldset: CCIPR - - name: BDCR - description: BDCR - byte_offset: 144 - fieldset: BDCR - - name: CSR - description: CSR - byte_offset: 148 - fieldset: CSR - - name: CRRCR - description: Clock recovery RC register - byte_offset: 152 - fieldset: CRRCR - - name: CCIPR2 - description: Peripherals independent clock configuration register - byte_offset: 156 - fieldset: CCIPR2 + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: Internal clock sources calibration register + byte_offset: 4 + fieldset: ICSCR + - name: CFGR + description: Clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: PLLCFGR + description: PLL configuration register + byte_offset: 12 + fieldset: PLLCFGR + - name: PLLSAI1CFGR + description: PLLSAI1 configuration register + byte_offset: 16 + fieldset: PLLSAI1CFGR + - name: PLLSAI2CFGR + description: PLLSAI2 configuration register + byte_offset: 20 + fieldset: PLLSAI2CFGR + - name: CIER + description: Clock interrupt enable register + byte_offset: 24 + fieldset: CIER + - name: CIFR + description: Clock interrupt flag register + byte_offset: 28 + access: Read + fieldset: CIFR + - name: CICR + description: Clock interrupt clear register + byte_offset: 32 + access: Write + fieldset: CICR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 40 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: AHB2 peripheral reset register + byte_offset: 44 + fieldset: AHB2RSTR + - name: AHB3RSTR + description: AHB3 peripheral reset register + byte_offset: 48 + fieldset: AHB3RSTR + - name: APB1RSTR1 + description: APB1 peripheral reset register 1 + byte_offset: 56 + fieldset: APB1RSTR1 + - name: APB1RSTR2 + description: APB1 peripheral reset register 2 + byte_offset: 60 + fieldset: APB1RSTR2 + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 64 + fieldset: APB2RSTR + - name: AHB1ENR + description: AHB1 peripheral clock enable register + byte_offset: 72 + fieldset: AHB1ENR + - name: AHB2ENR + description: AHB2 peripheral clock enable register + byte_offset: 76 + fieldset: AHB2ENR + - name: AHB3ENR + description: AHB3 peripheral clock enable register + byte_offset: 80 + fieldset: AHB3ENR + - name: APB1ENR1 + description: APB1ENR1 + byte_offset: 88 + fieldset: APB1ENR1 + - name: APB1ENR2 + description: APB1 peripheral clock enable register 2 + byte_offset: 92 + fieldset: APB1ENR2 + - name: APB2ENR + description: APB2ENR + byte_offset: 96 + fieldset: APB2ENR + - name: AHB1SMENR + description: AHB1 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 104 + fieldset: AHB1SMENR + - name: AHB2SMENR + description: AHB2 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 108 + fieldset: AHB2SMENR + - name: AHB3SMENR + description: AHB3 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 112 + fieldset: AHB3SMENR + - name: APB1SMENR1 + description: APB1SMENR1 + byte_offset: 120 + fieldset: APB1SMENR1 + - name: APB1SMENR2 + description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 + byte_offset: 124 + fieldset: APB1SMENR2 + - name: APB2SMENR + description: APB2SMENR + byte_offset: 128 + fieldset: APB2SMENR + - name: CCIPR + description: CCIPR + byte_offset: 136 + fieldset: CCIPR + - name: BDCR + description: BDCR + byte_offset: 144 + fieldset: BDCR + - name: CSR + description: CSR + byte_offset: 148 + fieldset: CSR + - name: CRRCR + description: Clock recovery RC register + byte_offset: 152 + fieldset: CRRCR + - name: CCIPR2 + description: Peripherals independent clock configuration register + byte_offset: 156 + fieldset: CCIPR2 fieldset/AHB1ENR: description: AHB1 peripheral clock enable register fields: - - name: DMA1EN - description: DMA1 clock enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: DMA2 clock enable - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1EN - description: DMAMUX clock enable - bit_offset: 2 - bit_size: 1 - - name: FLASHEN - description: Flash memory interface clock enable - bit_offset: 8 - bit_size: 1 - - name: CRCEN - description: CRC clock enable - bit_offset: 12 - bit_size: 1 - - name: TSCEN - description: Touch Sensing Controller clock enable - bit_offset: 16 - bit_size: 1 - - name: DMA2DEN - description: DMA2D clock enable - bit_offset: 17 - bit_size: 1 - - name: GFXMMUEN - description: Graphic MMU clock enable - bit_offset: 18 - bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1EN + description: DMAMUX clock enable + bit_offset: 2 + bit_size: 1 + - name: FLASHEN + description: Flash memory interface clock enable + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: TSCEN + description: Touch Sensing Controller clock enable + bit_offset: 16 + bit_size: 1 + - name: DMA2DEN + description: DMA2D clock enable + bit_offset: 17 + bit_size: 1 + - name: GFXMMUEN + description: Graphic MMU clock enable + bit_offset: 18 + bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - - name: DMA1RST - description: DMA1 reset - bit_offset: 0 - bit_size: 1 - - name: DMA2RST - description: DMA2 reset - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1RST - description: DMAMUX1RST - bit_offset: 2 - bit_size: 1 - - name: FLASHRST - description: Flash memory interface reset - bit_offset: 8 - bit_size: 1 - - name: CRCRST - description: CRC reset - bit_offset: 12 - bit_size: 1 - - name: TSCRST - description: Touch Sensing Controller reset - bit_offset: 16 - bit_size: 1 - - name: DMA2DRST - description: DMA2D reset - bit_offset: 17 - bit_size: 1 - - name: GFXMMURST - description: GFXMMU reset - bit_offset: 18 - bit_size: 1 + - name: DMA1RST + description: DMA1 reset + bit_offset: 0 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1RST + description: DMAMUX1RST + bit_offset: 2 + bit_size: 1 + - name: FLASHRST + description: Flash memory interface reset + bit_offset: 8 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 + - name: TSCRST + description: Touch Sensing Controller reset + bit_offset: 16 + bit_size: 1 + - name: DMA2DRST + description: DMA2D reset + bit_offset: 17 + bit_size: 1 + - name: GFXMMURST + description: GFXMMU reset + bit_offset: 18 + bit_size: 1 fieldset/AHB1SMENR: description: AHB1 peripheral clocks enable in Sleep and Stop modes register fields: - - name: DMA1SMEN - description: DMA1 clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: DMA2SMEN - description: DMA2 clocks enable during Sleep and Stop modes - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1SMEN - description: DMAMUX clock enable during Sleep and Stop modes - bit_offset: 2 - bit_size: 1 - - name: FLASHSMEN - description: Flash memory interface clocks enable during Sleep and Stop modes - bit_offset: 8 - bit_size: 1 - - name: SRAM1SMEN - description: SRAM1 interface clocks enable during Sleep and Stop modes - bit_offset: 9 - bit_size: 1 - - name: CRCSMEN - description: CRCSMEN - bit_offset: 12 - bit_size: 1 - - name: TSCSMEN - description: Touch Sensing Controller clocks enable during Sleep and Stop modes - bit_offset: 16 - bit_size: 1 - - name: DMA2DSMEN - description: DMA2D clock enable during Sleep and Stop modes - bit_offset: 17 - bit_size: 1 - - name: GFXMMUSMEN - description: GFXMMU clock enable during Sleep and Stop modes - bit_offset: 18 - bit_size: 1 + - name: DMA1SMEN + description: DMA1 clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: DMA2SMEN + description: DMA2 clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1SMEN + description: DMAMUX clock enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: FLASHSMEN + description: Flash memory interface clocks enable during Sleep and Stop modes + bit_offset: 8 + bit_size: 1 + - name: SRAM1SMEN + description: SRAM1 interface clocks enable during Sleep and Stop modes + bit_offset: 9 + bit_size: 1 + - name: CRCSMEN + description: CRCSMEN + bit_offset: 12 + bit_size: 1 + - name: TSCSMEN + description: Touch Sensing Controller clocks enable during Sleep and Stop modes + bit_offset: 16 + bit_size: 1 + - name: DMA2DSMEN + description: DMA2D clock enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: GFXMMUSMEN + description: GFXMMU clock enable during Sleep and Stop modes + bit_offset: 18 + bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - - name: GPIOAEN - description: IO port A clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: IO port B clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: IO port C clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: IO port D clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: IO port E clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIOFEN - description: IO port F clock enable - bit_offset: 5 - bit_size: 1 - - name: GPIOGEN - description: IO port G clock enable - bit_offset: 6 - bit_size: 1 - - name: GPIOHEN - description: IO port H clock enable - bit_offset: 7 - bit_size: 1 - - name: GPIOIEN - description: IO port I clock enable - bit_offset: 8 - bit_size: 1 - - name: USB_OTG_FSEN - description: OTG full speed clock enable - bit_offset: 12 - bit_size: 1 - - name: ADCEN - description: ADC clock enable - bit_offset: 13 - bit_size: 1 - - name: DCMIEN - description: DCMI clock enable - bit_offset: 14 - bit_size: 1 - - name: AESEN - description: AES accelerator clock enable - bit_offset: 16 - bit_size: 1 - - name: HASHEN - description: HASH clock enable - bit_offset: 17 - bit_size: 1 - - name: RNGEN - description: Random Number Generator clock enable - bit_offset: 18 - bit_size: 1 - - name: OSPIMEN - description: OctoSPI IO manager clock enable - bit_offset: 20 - bit_size: 1 - - name: SDMMC1EN - description: SDMMC1 clock enable - bit_offset: 22 - bit_size: 1 + - name: GPIOAEN + description: IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: IO port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: IO port E clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: IO port F clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: IO port G clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: IO port H clock enable + bit_offset: 7 + bit_size: 1 + - name: GPIOIEN + description: IO port I clock enable + bit_offset: 8 + bit_size: 1 + - name: USB_OTG_FSEN + description: OTG full speed clock enable + bit_offset: 12 + bit_size: 1 + - name: ADCEN + description: ADC clock enable + bit_offset: 13 + bit_size: 1 + - name: DCMIEN + description: DCMI clock enable + bit_offset: 14 + bit_size: 1 + - name: AESEN + description: AES accelerator clock enable + bit_offset: 16 + bit_size: 1 + - name: HASHEN + description: HASH clock enable + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: Random Number Generator clock enable + bit_offset: 18 + bit_size: 1 + - name: OSPIMEN + description: OctoSPI IO manager clock enable + bit_offset: 20 + bit_size: 1 + - name: SDMMC1EN + description: SDMMC1 clock enable + bit_offset: 22 + bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - - name: GPIOARST - description: IO port A reset - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: IO port B reset - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: IO port C reset - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: IO port D reset - bit_offset: 3 - bit_size: 1 - - name: GPIOERST - description: IO port E reset - bit_offset: 4 - bit_size: 1 - - name: GPIOFRST - description: IO port F reset - bit_offset: 5 - bit_size: 1 - - name: GPIOGRST - description: IO port G reset - bit_offset: 6 - bit_size: 1 - - name: GPIOHRST - description: IO port H reset - bit_offset: 7 - bit_size: 1 - - name: GPIOIRST - description: IO port I reset - bit_offset: 8 - bit_size: 1 - - name: USB_OTG_FSRST - description: USB OTG FS reset - bit_offset: 12 - bit_size: 1 - - name: ADCRST - description: ADC reset - bit_offset: 13 - bit_size: 1 - - name: DCMIRST - description: Digital Camera Interface reset - bit_offset: 14 - bit_size: 1 - - name: AESRST - description: AES hardware accelerator reset - bit_offset: 16 - bit_size: 1 - - name: HASHRST - description: Hash reset - bit_offset: 17 - bit_size: 1 - - name: RNGRST - description: Random number generator reset - bit_offset: 18 - bit_size: 1 - - name: OSPIMRST - description: OCTOSPI IO manager reset - bit_offset: 20 - bit_size: 1 - - name: SDMMC1RST - description: SDMMC1 reset - bit_offset: 22 - bit_size: 1 + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 6 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 7 + bit_size: 1 + - name: GPIOIRST + description: IO port I reset + bit_offset: 8 + bit_size: 1 + - name: USB_OTG_FSRST + description: USB OTG FS reset + bit_offset: 12 + bit_size: 1 + - name: ADCRST + description: ADC reset + bit_offset: 13 + bit_size: 1 + - name: DCMIRST + description: Digital Camera Interface reset + bit_offset: 14 + bit_size: 1 + - name: AESRST + description: AES hardware accelerator reset + bit_offset: 16 + bit_size: 1 + - name: HASHRST + description: Hash reset + bit_offset: 17 + bit_size: 1 + - name: RNGRST + description: Random number generator reset + bit_offset: 18 + bit_size: 1 + - name: OSPIMRST + description: OCTOSPI IO manager reset + bit_offset: 20 + bit_size: 1 + - name: SDMMC1RST + description: SDMMC1 reset + bit_offset: 22 + bit_size: 1 fieldset/AHB2SMENR: description: AHB2 peripheral clocks enable in Sleep and Stop modes register fields: - - name: GPIOASMEN - description: IO port A clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: GPIOBSMEN - description: IO port B clocks enable during Sleep and Stop modes - bit_offset: 1 - bit_size: 1 - - name: GPIOCSMEN - description: IO port C clocks enable during Sleep and Stop modes - bit_offset: 2 - bit_size: 1 - - name: GPIODSMEN - description: IO port D clocks enable during Sleep and Stop modes - bit_offset: 3 - bit_size: 1 - - name: GPIOESMEN - description: IO port E clocks enable during Sleep and Stop modes - bit_offset: 4 - bit_size: 1 - - name: GPIOFSMEN - description: IO port F clocks enable during Sleep and Stop modes - bit_offset: 5 - bit_size: 1 - - name: GPIOGSMEN - description: IO port G clocks enable during Sleep and Stop modes - bit_offset: 6 - bit_size: 1 - - name: GPIOHSMEN - description: IO port H clocks enable during Sleep and Stop modes - bit_offset: 7 - bit_size: 1 - - name: GPIOISMEN - description: IO port I clocks enable during Sleep and Stop modes - bit_offset: 8 - bit_size: 1 - - name: SRAM2SMEN - description: SRAM2 interface clocks enable during Sleep and Stop modes - bit_offset: 9 - bit_size: 1 - - name: SRAM3SMEN - description: SRAM2 interface clocks enable during Sleep and Stop modes - bit_offset: 10 - bit_size: 1 - - name: USB_OTG_FSSMEN - description: OTG full speed clocks enable during Sleep and Stop modes - bit_offset: 12 - bit_size: 1 - - name: ADCFSSMEN - description: ADC clocks enable during Sleep and Stop modes - bit_offset: 13 - bit_size: 1 - - name: DCMISMEN - description: DCMI clock enable during Sleep and Stop modes - bit_offset: 14 - bit_size: 1 - - name: AESSMEN - description: AES accelerator clocks enable during Sleep and Stop modes - bit_offset: 16 - bit_size: 1 - - name: HASH1SMEN - description: HASH clock enable during Sleep and Stop modes - bit_offset: 17 - bit_size: 1 - - name: HASHSMEN - description: HASH clock enable during Sleep and Stop modes - bit_offset: 17 - bit_size: 1 - - name: RNGSMEN - description: Random Number Generator clocks enable during Sleep and Stop modes - bit_offset: 18 - bit_size: 1 - - name: OSPIMSMEN - description: OctoSPI IO manager clocks enable during Sleep and Stop modes - bit_offset: 20 - bit_size: 1 - - name: SDMMC1SMEN - description: SDMMC1 clocks enable during Sleep and Stop modes - bit_offset: 22 - bit_size: 1 + - name: GPIOASMEN + description: IO port A clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: IO port B clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: IO port C clocks enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: GPIODSMEN + description: IO port D clocks enable during Sleep and Stop modes + bit_offset: 3 + bit_size: 1 + - name: GPIOESMEN + description: IO port E clocks enable during Sleep and Stop modes + bit_offset: 4 + bit_size: 1 + - name: GPIOFSMEN + description: IO port F clocks enable during Sleep and Stop modes + bit_offset: 5 + bit_size: 1 + - name: GPIOGSMEN + description: IO port G clocks enable during Sleep and Stop modes + bit_offset: 6 + bit_size: 1 + - name: GPIOHSMEN + description: IO port H clocks enable during Sleep and Stop modes + bit_offset: 7 + bit_size: 1 + - name: GPIOISMEN + description: IO port I clocks enable during Sleep and Stop modes + bit_offset: 8 + bit_size: 1 + - name: SRAM2SMEN + description: SRAM2 interface clocks enable during Sleep and Stop modes + bit_offset: 9 + bit_size: 1 + - name: SRAM3SMEN + description: SRAM2 interface clocks enable during Sleep and Stop modes + bit_offset: 10 + bit_size: 1 + - name: USB_OTG_FSSMEN + description: OTG full speed clocks enable during Sleep and Stop modes + bit_offset: 12 + bit_size: 1 + - name: ADCFSSMEN + description: ADC clocks enable during Sleep and Stop modes + bit_offset: 13 + bit_size: 1 + - name: DCMISMEN + description: DCMI clock enable during Sleep and Stop modes + bit_offset: 14 + bit_size: 1 + - name: AESSMEN + description: AES accelerator clocks enable during Sleep and Stop modes + bit_offset: 16 + bit_size: 1 + - name: HASH1SMEN + description: HASH clock enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: HASHSMEN + description: HASH clock enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: RNGSMEN + description: Random Number Generator clocks enable during Sleep and Stop modes + bit_offset: 18 + bit_size: 1 + - name: OSPIMSMEN + description: OctoSPI IO manager clocks enable during Sleep and Stop modes + bit_offset: 20 + bit_size: 1 + - name: SDMMC1SMEN + description: SDMMC1 clocks enable during Sleep and Stop modes + bit_offset: 22 + bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: - - name: FMCEN - description: Flexible memory controller clock enable - bit_offset: 0 - bit_size: 1 - - name: QUADSPIEN - description: QUADSPIEN - bit_offset: 8 - bit_size: 1 - - name: OSPI2EN - description: OSPI2EN memory interface clock enable - bit_offset: 9 - bit_size: 1 + - name: FMCEN + description: Flexible memory controller clock enable + bit_offset: 0 + bit_size: 1 + - name: QUADSPIEN + description: QUADSPIEN + bit_offset: 8 + bit_size: 1 + - name: OSPI2EN + description: OSPI2EN memory interface clock enable + bit_offset: 9 + bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - - name: FMCRST - description: Flexible memory controller reset - bit_offset: 0 - bit_size: 1 - - name: QSPIRST - description: Quad SPI memory interface reset - bit_offset: 8 - bit_size: 1 - - name: OSPI2RST - description: OctOSPI2 memory interface reset - bit_offset: 9 - bit_size: 1 + - name: FMCRST + description: Flexible memory controller reset + bit_offset: 0 + bit_size: 1 + - name: QSPIRST + description: Quad SPI memory interface reset + bit_offset: 8 + bit_size: 1 + - name: OSPI2RST + description: OctOSPI2 memory interface reset + bit_offset: 9 + bit_size: 1 fieldset/AHB3SMENR: description: AHB3 peripheral clocks enable in Sleep and Stop modes register fields: - - name: FMCSMEN - description: Flexible memory controller clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: QSPISMEN - description: QSPISMEN - bit_offset: 8 - bit_size: 1 - - name: OCTOSPI2 - description: OctoSPI2 memory interface clocks enable during Sleep and Stop modes - bit_offset: 9 - bit_size: 1 + - name: FMCSMEN + description: Flexible memory controller clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: QSPISMEN + description: QSPISMEN + bit_offset: 8 + bit_size: 1 + - name: OCTOSPI2 + description: OctoSPI2 memory interface clocks enable during Sleep and Stop modes + bit_offset: 9 + bit_size: 1 fieldset/APB1ENR1: description: APB1ENR1 fields: - - name: TIM2EN - description: TIM2 timer clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: TIM3 timer clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: TIM4 timer clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: TIM5 timer clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: TIM6 timer clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: TIM7 timer clock enable - bit_offset: 5 - bit_size: 1 - - name: LCDEN - description: LCD clock enable - bit_offset: 9 - bit_size: 1 - - name: RTCAPBEN - description: RTC APB clock enable - bit_offset: 10 - bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI2 clock enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI3 clock enable - bit_offset: 15 - bit_size: 1 - - name: USART2EN - description: USART2 clock enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART3 clock enable - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: UART4 clock enable - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: UART5 clock enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C2 clock enable - bit_offset: 22 - bit_size: 1 - - name: I2C3EN - description: I2C3 clock enable - bit_offset: 23 - bit_size: 1 - - name: CRSEN - description: Clock Recovery System clock enable - bit_offset: 24 - bit_size: 1 - - name: CAN1EN - description: CAN1 clock enable - bit_offset: 25 - bit_size: 1 - - name: CAN2EN - description: CAN2 clock enable - bit_offset: 26 - bit_size: 1 - - name: USBEN - description: USB FS clock enable - bit_offset: 26 - bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - - name: DAC1EN - description: DAC1 interface clock enable - bit_offset: 29 - bit_size: 1 - - name: OPAMPEN - description: OPAMP interface clock enable - bit_offset: 30 - bit_size: 1 - - name: LPTIM1EN - description: Low power timer 1 clock enable - bit_offset: 31 - bit_size: 1 + - name: TIM2EN + description: TIM2 timer clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM3 timer clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM4 timer clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: TIM5 timer clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM6 timer clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM7 timer clock enable + bit_offset: 5 + bit_size: 1 + - name: LCDEN + description: LCD clock enable + bit_offset: 9 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 23 + bit_size: 1 + - name: CRSEN + description: Clock Recovery System clock enable + bit_offset: 24 + bit_size: 1 + - name: CAN1EN + description: CAN1 clock enable + bit_offset: 25 + bit_size: 1 + - name: CAN2EN + description: CAN2 clock enable + bit_offset: 26 + bit_size: 1 + - name: USBEN + description: USB FS clock enable + bit_offset: 26 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DAC1EN + description: DAC1 interface clock enable + bit_offset: 29 + bit_size: 1 + - name: OPAMPEN + description: OPAMP interface clock enable + bit_offset: 30 + bit_size: 1 + - name: LPTIM1EN + description: Low power timer 1 clock enable + bit_offset: 31 + bit_size: 1 fieldset/APB1ENR2: description: APB1 peripheral clock enable register 2 fields: - - name: LPUART1EN - description: Low power UART 1 clock enable - bit_offset: 0 - bit_size: 1 - - name: I2C4EN - description: I2C4 clock enable - bit_offset: 1 - bit_size: 1 - - name: SWPMI1EN - description: Single wire protocol clock enable - bit_offset: 2 - bit_size: 1 - - name: LPTIM2EN - description: LPTIM2EN - bit_offset: 5 - bit_size: 1 - - name: DFSDMEN - description: DFSDMEN enable - bit_offset: 24 - bit_size: 1 + - name: LPUART1EN + description: Low power UART 1 clock enable + bit_offset: 0 + bit_size: 1 + - name: I2C4EN + description: I2C4 clock enable + bit_offset: 1 + bit_size: 1 + - name: SWPMI1EN + description: Single wire protocol clock enable + bit_offset: 2 + bit_size: 1 + - name: LPTIM2EN + description: LPTIM2EN + bit_offset: 5 + bit_size: 1 + - name: DFSDMEN + description: DFSDMEN enable + bit_offset: 24 + bit_size: 1 fieldset/APB1RSTR1: description: APB1 peripheral reset register 1 fields: - - name: TIM2RST - description: TIM2 timer reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: TIM3 timer reset - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: TIM3 timer reset - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: TIM5 timer reset - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: TIM6 timer reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: TIM7 timer reset - bit_offset: 5 - bit_size: 1 - - name: LCDRST - description: LCD interface reset - bit_offset: 9 - bit_size: 1 - - name: SPI2RST - description: SPI2 reset - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: SPI3 reset - bit_offset: 15 - bit_size: 1 - - name: USART2RST - description: USART2 reset - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: USART3 reset - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: UART4 reset - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: UART5 reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C2 reset - bit_offset: 22 - bit_size: 1 - - name: I2C3RST - description: I2C3 reset - bit_offset: 23 - bit_size: 1 - - name: CRSRST - description: CRS reset - bit_offset: 24 - bit_size: 1 - - name: CAN1RST - description: CAN1 reset - bit_offset: 25 - bit_size: 1 - - name: CAN2RST - description: CAN2 reset - bit_offset: 26 - bit_size: 1 - - name: USBRST - description: USB FS reset - bit_offset: 26 - bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - - name: DAC1RST - description: DAC1 interface reset - bit_offset: 29 - bit_size: 1 - - name: OPAMPRST - description: OPAMP interface reset - bit_offset: 30 - bit_size: 1 - - name: LPTIM1RST - description: Low Power Timer 1 reset - bit_offset: 31 - bit_size: 1 + - name: TIM2RST + description: TIM2 timer reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: TIM3 timer reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: TIM3 timer reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: TIM5 timer reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: TIM6 timer reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM7 timer reset + bit_offset: 5 + bit_size: 1 + - name: LCDRST + description: LCD interface reset + bit_offset: 9 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: UART4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: UART5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 23 + bit_size: 1 + - name: CRSRST + description: CRS reset + bit_offset: 24 + bit_size: 1 + - name: CAN1RST + description: CAN1 reset + bit_offset: 25 + bit_size: 1 + - name: CAN2RST + description: CAN2 reset + bit_offset: 26 + bit_size: 1 + - name: USBRST + description: USB FS reset + bit_offset: 26 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DAC1RST + description: DAC1 interface reset + bit_offset: 29 + bit_size: 1 + - name: OPAMPRST + description: OPAMP interface reset + bit_offset: 30 + bit_size: 1 + - name: LPTIM1RST + description: Low Power Timer 1 reset + bit_offset: 31 + bit_size: 1 fieldset/APB1RSTR2: description: APB1 peripheral reset register 2 fields: - - name: LPUART1RST - description: Low-power UART 1 reset - bit_offset: 0 - bit_size: 1 - - name: I2C4RST - description: I2C4 reset - bit_offset: 1 - bit_size: 1 - - name: SWPMI1RST - description: Single wire protocol reset - bit_offset: 2 - bit_size: 1 - - name: LPTIM2RST - description: Low-power timer 2 reset - bit_offset: 5 - bit_size: 1 + - name: LPUART1RST + description: Low-power UART 1 reset + bit_offset: 0 + bit_size: 1 + - name: I2C4RST + description: I2C4 reset + bit_offset: 1 + bit_size: 1 + - name: SWPMI1RST + description: Single wire protocol reset + bit_offset: 2 + bit_size: 1 + - name: LPTIM2RST + description: Low-power timer 2 reset + bit_offset: 5 + bit_size: 1 fieldset/APB1SMENR1: description: APB1SMENR1 fields: - - name: TIM2SMEN - description: TIM2 timer clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: TIM3SMEN - description: TIM3 timer clocks enable during Sleep and Stop modes - bit_offset: 1 - bit_size: 1 - - name: TIM4SMEN - description: TIM4 timer clocks enable during Sleep and Stop modes - bit_offset: 2 - bit_size: 1 - - name: TIM5SMEN - description: TIM5 timer clocks enable during Sleep and Stop modes - bit_offset: 3 - bit_size: 1 - - name: TIM6SMEN - description: TIM6 timer clocks enable during Sleep and Stop modes - bit_offset: 4 - bit_size: 1 - - name: TIM7SMEN - description: TIM7 timer clocks enable during Sleep and Stop modes - bit_offset: 5 - bit_size: 1 - - name: LCDSMEN - description: LCD clocks enable during Sleep and Stop modes - bit_offset: 9 - bit_size: 1 - - name: RTCAPBSMEN - description: RTC APB clock enable during Sleep and Stop modes - bit_offset: 10 - bit_size: 1 - - name: WWDGSMEN - description: Window watchdog clocks enable during Sleep and Stop modes - bit_offset: 11 - bit_size: 1 - - name: SPI2SMEN - description: SPI2 clocks enable during Sleep and Stop modes - bit_offset: 14 - bit_size: 1 - - name: SP3SMEN - description: SPI3 clocks enable during Sleep and Stop modes - bit_offset: 15 - bit_size: 1 - - name: USART2SMEN - description: USART2 clocks enable during Sleep and Stop modes - bit_offset: 17 - bit_size: 1 - - name: USART3SMEN - description: USART3 clocks enable during Sleep and Stop modes - bit_offset: 18 - bit_size: 1 - - name: UART4SMEN - description: UART4 clocks enable during Sleep and Stop modes - bit_offset: 19 - bit_size: 1 - - name: UART5SMEN - description: UART5 clocks enable during Sleep and Stop modes - bit_offset: 20 - bit_size: 1 - - name: I2C1SMEN - description: I2C1 clocks enable during Sleep and Stop modes - bit_offset: 21 - bit_size: 1 - - name: I2C2SMEN - description: I2C2 clocks enable during Sleep and Stop modes - bit_offset: 22 - bit_size: 1 - - name: I2C3SMEN - description: I2C3 clocks enable during Sleep and Stop modes - bit_offset: 23 - bit_size: 1 - - name: CRSSMEN - description: CRS clock enable during Sleep and Stop modes - bit_offset: 24 - bit_size: 1 - - name: CAN1SMEN - description: CAN1 clocks enable during Sleep and Stop modes - bit_offset: 25 - bit_size: 1 - - name: CAN2SMEN - description: CAN2 clocks enable during Sleep and Stop modes - bit_offset: 26 - bit_size: 1 - - name: USBSMEN - description: USB FS clock enable during Sleep and Stop modes - bit_offset: 26 - bit_size: 1 - - name: PWRSMEN - description: Power interface clocks enable during Sleep and Stop modes - bit_offset: 28 - bit_size: 1 - - name: DAC1SMEN - description: DAC1 interface clocks enable during Sleep and Stop modes - bit_offset: 29 - bit_size: 1 - - name: OPAMPSMEN - description: OPAMP interface clocks enable during Sleep and Stop modes - bit_offset: 30 - bit_size: 1 - - name: LPTIM1SMEN - description: Low power timer 1 clocks enable during Sleep and Stop modes - bit_offset: 31 - bit_size: 1 + - name: TIM2SMEN + description: TIM2 timer clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: TIM3SMEN + description: TIM3 timer clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: TIM4SMEN + description: TIM4 timer clocks enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: TIM5SMEN + description: TIM5 timer clocks enable during Sleep and Stop modes + bit_offset: 3 + bit_size: 1 + - name: TIM6SMEN + description: TIM6 timer clocks enable during Sleep and Stop modes + bit_offset: 4 + bit_size: 1 + - name: TIM7SMEN + description: TIM7 timer clocks enable during Sleep and Stop modes + bit_offset: 5 + bit_size: 1 + - name: LCDSMEN + description: LCD clocks enable during Sleep and Stop modes + bit_offset: 9 + bit_size: 1 + - name: RTCAPBSMEN + description: RTC APB clock enable during Sleep and Stop modes + bit_offset: 10 + bit_size: 1 + - name: WWDGSMEN + description: Window watchdog clocks enable during Sleep and Stop modes + bit_offset: 11 + bit_size: 1 + - name: SPI2SMEN + description: SPI2 clocks enable during Sleep and Stop modes + bit_offset: 14 + bit_size: 1 + - name: SP3SMEN + description: SPI3 clocks enable during Sleep and Stop modes + bit_offset: 15 + bit_size: 1 + - name: USART2SMEN + description: USART2 clocks enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: USART3SMEN + description: USART3 clocks enable during Sleep and Stop modes + bit_offset: 18 + bit_size: 1 + - name: UART4SMEN + description: UART4 clocks enable during Sleep and Stop modes + bit_offset: 19 + bit_size: 1 + - name: UART5SMEN + description: UART5 clocks enable during Sleep and Stop modes + bit_offset: 20 + bit_size: 1 + - name: I2C1SMEN + description: I2C1 clocks enable during Sleep and Stop modes + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: I2C2 clocks enable during Sleep and Stop modes + bit_offset: 22 + bit_size: 1 + - name: I2C3SMEN + description: I2C3 clocks enable during Sleep and Stop modes + bit_offset: 23 + bit_size: 1 + - name: CRSSMEN + description: CRS clock enable during Sleep and Stop modes + bit_offset: 24 + bit_size: 1 + - name: CAN1SMEN + description: CAN1 clocks enable during Sleep and Stop modes + bit_offset: 25 + bit_size: 1 + - name: CAN2SMEN + description: CAN2 clocks enable during Sleep and Stop modes + bit_offset: 26 + bit_size: 1 + - name: USBSMEN + description: USB FS clock enable during Sleep and Stop modes + bit_offset: 26 + bit_size: 1 + - name: PWRSMEN + description: Power interface clocks enable during Sleep and Stop modes + bit_offset: 28 + bit_size: 1 + - name: DAC1SMEN + description: DAC1 interface clocks enable during Sleep and Stop modes + bit_offset: 29 + bit_size: 1 + - name: OPAMPSMEN + description: OPAMP interface clocks enable during Sleep and Stop modes + bit_offset: 30 + bit_size: 1 + - name: LPTIM1SMEN + description: Low power timer 1 clocks enable during Sleep and Stop modes + bit_offset: 31 + bit_size: 1 fieldset/APB1SMENR2: description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 fields: - - name: LPUART1SMEN - description: Low power UART 1 clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: I2C4SMEN - description: I2C4 clocks enable during Sleep and Stop modes - bit_offset: 1 - bit_size: 1 - - name: SWPMI1SMEN - description: Single wire protocol clocks enable during Sleep and Stop modes - bit_offset: 2 - bit_size: 1 - - name: LPTIM2SMEN - description: LPTIM2SMEN - bit_offset: 5 - bit_size: 1 + - name: LPUART1SMEN + description: Low power UART 1 clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: I2C4SMEN + description: I2C4 clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: SWPMI1SMEN + description: Single wire protocol clocks enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: LPTIM2SMEN + description: LPTIM2SMEN + bit_offset: 5 + bit_size: 1 fieldset/APB2ENR: description: APB2ENR fields: - - name: SYSCFGEN - description: SYSCFG clock enable - bit_offset: 0 - bit_size: 1 - - name: FWEN - description: Firewall clock enable - bit_offset: 7 - bit_size: 1 - - name: SDMMCEN - description: SDMMC clock enable - bit_offset: 10 - bit_size: 1 - - name: TIM1EN - description: TIM1 timer clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: SPI1 clock enable - bit_offset: 12 - bit_size: 1 - - name: TIM8EN - description: TIM8 timer clock enable - bit_offset: 13 - bit_size: 1 - - name: USART1EN - description: USART1clock enable - bit_offset: 14 - bit_size: 1 - - name: TIM15EN - description: TIM15 timer clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: TIM16 timer clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: TIM17 timer clock enable - bit_offset: 18 - bit_size: 1 - - name: SAI1EN - description: SAI1 clock enable - bit_offset: 21 - bit_size: 1 - - name: SAI2EN - description: SAI2 clock enable - bit_offset: 22 - bit_size: 1 - - name: DFSDM1EN - description: DFSDM timer clock enable - bit_offset: 24 - bit_size: 1 - - name: DFSDMEN - description: DFSDM timer clock enable - bit_offset: 24 - bit_size: 1 - - name: LTDCEN - description: LCD-TFT clock enable - bit_offset: 26 - bit_size: 1 - - name: DSIEN - description: DSI clock enable - bit_offset: 27 - bit_size: 1 + - name: SYSCFGEN + description: SYSCFG clock enable + bit_offset: 0 + bit_size: 1 + - name: FWEN + description: Firewall clock enable + bit_offset: 7 + bit_size: 1 + - name: SDMMCEN + description: SDMMC clock enable + bit_offset: 10 + bit_size: 1 + - name: TIM1EN + description: TIM1 timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: TIM8EN + description: TIM8 timer clock enable + bit_offset: 13 + bit_size: 1 + - name: USART1EN + description: USART1clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM15EN + description: TIM15 timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: SAI1EN + description: SAI1 clock enable + bit_offset: 21 + bit_size: 1 + - name: SAI2EN + description: SAI2 clock enable + bit_offset: 22 + bit_size: 1 + - name: DFSDM1EN + description: DFSDM timer clock enable + bit_offset: 24 + bit_size: 1 + - name: DFSDMEN + description: DFSDM timer clock enable + bit_offset: 24 + bit_size: 1 + - name: LTDCEN + description: LCD-TFT clock enable + bit_offset: 26 + bit_size: 1 + - name: DSIEN + description: DSI clock enable + bit_offset: 27 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - - name: SYSCFGRST - description: System configuration (SYSCFG) reset - bit_offset: 0 - bit_size: 1 - - name: SDMMCRST - description: SDMMC reset - bit_offset: 10 - bit_size: 1 - - name: TIM1RST - description: TIM1 timer reset - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: SPI1 reset - bit_offset: 12 - bit_size: 1 - - name: TIM8RST - description: TIM8 timer reset - bit_offset: 13 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 14 - bit_size: 1 - - name: TIM15RST - description: TIM15 timer reset - bit_offset: 16 - bit_size: 1 - - name: TIM16RST - description: TIM16 timer reset - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: TIM17 timer reset - bit_offset: 18 - bit_size: 1 - - name: SAI1RST - description: Serial audio interface 1 (SAI1) reset - bit_offset: 21 - bit_size: 1 - - name: SAI2RST - description: Serial audio interface 2 (SAI2) reset - bit_offset: 22 - bit_size: 1 - - name: DFSDM1RST - description: Digital filters for sigma-delata modulators (DFSDM) reset - bit_offset: 24 - bit_size: 1 - - name: DFSDMRST - description: DFSDM filter reset - bit_offset: 24 - bit_size: 1 - - name: LTDCRST - description: LCD-TFT reset - bit_offset: 26 - bit_size: 1 - - name: DSIRST - description: DSI reset - bit_offset: 27 - bit_size: 1 + - name: SYSCFGRST + description: System configuration (SYSCFG) reset + bit_offset: 0 + bit_size: 1 + - name: SDMMCRST + description: SDMMC reset + bit_offset: 10 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI1 reset + bit_offset: 12 + bit_size: 1 + - name: TIM8RST + description: TIM8 timer reset + bit_offset: 13 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: SAI1RST + description: Serial audio interface 1 (SAI1) reset + bit_offset: 21 + bit_size: 1 + - name: SAI2RST + description: Serial audio interface 2 (SAI2) reset + bit_offset: 22 + bit_size: 1 + - name: DFSDM1RST + description: Digital filters for sigma-delata modulators (DFSDM) reset + bit_offset: 24 + bit_size: 1 + - name: DFSDMRST + description: DFSDM filter reset + bit_offset: 24 + bit_size: 1 + - name: LTDCRST + description: LCD-TFT reset + bit_offset: 26 + bit_size: 1 + - name: DSIRST + description: DSI reset + bit_offset: 27 + bit_size: 1 fieldset/APB2SMENR: description: APB2SMENR fields: - - name: SYSCFGSMEN - description: SYSCFG clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: SDMMCSMEN - description: SDMMC clocks enable during Sleep and Stop modes - bit_offset: 10 - bit_size: 1 - - name: TIM1SMEN - description: TIM1 timer clocks enable during Sleep and Stop modes - bit_offset: 11 - bit_size: 1 - - name: SPI1SMEN - description: SPI1 clocks enable during Sleep and Stop modes - bit_offset: 12 - bit_size: 1 - - name: TIM8SMEN - description: TIM8 timer clocks enable during Sleep and Stop modes - bit_offset: 13 - bit_size: 1 - - name: USART1SMEN - description: USART1clocks enable during Sleep and Stop modes - bit_offset: 14 - bit_size: 1 - - name: TIM15SMEN - description: TIM15 timer clocks enable during Sleep and Stop modes - bit_offset: 16 - bit_size: 1 - - name: TIM16SMEN - description: TIM16 timer clocks enable during Sleep and Stop modes - bit_offset: 17 - bit_size: 1 - - name: TIM17SMEN - description: TIM17 timer clocks enable during Sleep and Stop modes - bit_offset: 18 - bit_size: 1 - - name: SAI1SMEN - description: SAI1 clocks enable during Sleep and Stop modes - bit_offset: 21 - bit_size: 1 - - name: SAI2SMEN - description: SAI2 clocks enable during Sleep and Stop modes - bit_offset: 22 - bit_size: 1 - - name: DFSDM1SMEN - description: DFSDM timer clocks enable during Sleep and Stop modes - bit_offset: 24 - bit_size: 1 - - name: DFSDMSMEN - description: DFSDM timer clocks enable during Sleep and Stop modes - bit_offset: 24 - bit_size: 1 - - name: LTDCSMEN - description: LCD-TFT timer clocks enable during Sleep and Stop modes - bit_offset: 26 - bit_size: 1 - - name: DSISMEN - description: DSI clocks enable during Sleep and Stop modes - bit_offset: 27 - bit_size: 1 + - name: SYSCFGSMEN + description: SYSCFG clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: SDMMCSMEN + description: SDMMC clocks enable during Sleep and Stop modes + bit_offset: 10 + bit_size: 1 + - name: TIM1SMEN + description: TIM1 timer clocks enable during Sleep and Stop modes + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: SPI1 clocks enable during Sleep and Stop modes + bit_offset: 12 + bit_size: 1 + - name: TIM8SMEN + description: TIM8 timer clocks enable during Sleep and Stop modes + bit_offset: 13 + bit_size: 1 + - name: USART1SMEN + description: USART1clocks enable during Sleep and Stop modes + bit_offset: 14 + bit_size: 1 + - name: TIM15SMEN + description: TIM15 timer clocks enable during Sleep and Stop modes + bit_offset: 16 + bit_size: 1 + - name: TIM16SMEN + description: TIM16 timer clocks enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: TIM17 timer clocks enable during Sleep and Stop modes + bit_offset: 18 + bit_size: 1 + - name: SAI1SMEN + description: SAI1 clocks enable during Sleep and Stop modes + bit_offset: 21 + bit_size: 1 + - name: SAI2SMEN + description: SAI2 clocks enable during Sleep and Stop modes + bit_offset: 22 + bit_size: 1 + - name: DFSDM1SMEN + description: DFSDM timer clocks enable during Sleep and Stop modes + bit_offset: 24 + bit_size: 1 + - name: DFSDMSMEN + description: DFSDM timer clocks enable during Sleep and Stop modes + bit_offset: 24 + bit_size: 1 + - name: LTDCSMEN + description: LCD-TFT timer clocks enable during Sleep and Stop modes + bit_offset: 26 + bit_size: 1 + - name: DSISMEN + description: DSI clocks enable during Sleep and Stop modes + bit_offset: 27 + bit_size: 1 fieldset/BDCR: description: BDCR fields: - - name: LSEON - description: LSE oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: LSE oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: LSE oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: LSEDRV - description: SE oscillator drive capability - bit_offset: 3 - bit_size: 2 - enum: LSEDRV - - name: LSECSSON - description: LSECSSON - bit_offset: 5 - bit_size: 1 - - name: LSECSSD - description: LSECSSD - bit_offset: 6 - bit_size: 1 - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: Backup domain software reset - bit_offset: 16 - bit_size: 1 - - name: LSCOEN - description: Low speed clock output enable - bit_offset: 24 - bit_size: 1 - - name: LSCOSEL - description: Low speed clock output selection - bit_offset: 25 - bit_size: 1 + - name: LSEON + description: LSE oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: LSE oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: LSE oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: SE oscillator drive capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: LSECSSON + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: LSECSSD + bit_offset: 6 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: Low speed clock output enable + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: Low speed clock output selection + bit_offset: 25 + bit_size: 1 fieldset/CCIPR: description: CCIPR fields: - - name: USART1SEL - description: USART1 clock source selection - bit_offset: 0 - bit_size: 2 - - name: USART2SEL - description: USART2 clock source selection - bit_offset: 2 - bit_size: 2 - - name: USART3SEL - description: USART3 clock source selection - bit_offset: 4 - bit_size: 2 - - name: UART4SEL - description: UART4 clock source selection - bit_offset: 6 - bit_size: 2 - - name: UART5SEL - description: UART5 clock source selection - bit_offset: 8 - bit_size: 2 - - name: LPUART1SEL - description: LPUART1 clock source selection - bit_offset: 10 - bit_size: 2 - - name: I2C1SEL - description: I2C1 clock source selection - bit_offset: 12 - bit_size: 2 - - name: I2C2SEL - description: I2C2 clock source selection - bit_offset: 14 - bit_size: 2 - - name: I2C3SEL - description: I2C3 clock source selection - bit_offset: 16 - bit_size: 2 - - name: LPTIM1SEL - description: Low power timer 1 clock source selection - bit_offset: 18 - bit_size: 2 - - name: LPTIM2SEL - description: Low power timer 2 clock source selection - bit_offset: 20 - bit_size: 2 - - name: SAI1SEL - description: SAI1 clock source selection - bit_offset: 22 - bit_size: 2 - - name: SAI2SEL - description: SAI2 clock source selection - bit_offset: 24 - bit_size: 2 - - name: CLK48SEL - description: 48 MHz clock source selection - bit_offset: 26 - bit_size: 2 - - name: ADCSEL - description: ADCs clock source selection - bit_offset: 28 - bit_size: 2 - - name: SWPMI1SEL - description: SWPMI1 clock source selection - bit_offset: 30 - bit_size: 1 - - name: DFSDMSEL - description: DFSDM clock source selection - bit_offset: 31 - bit_size: 1 + - name: USART1SEL + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + - name: USART2SEL + description: USART2 clock source selection + bit_offset: 2 + bit_size: 2 + - name: USART3SEL + description: USART3 clock source selection + bit_offset: 4 + bit_size: 2 + - name: UART4SEL + description: UART4 clock source selection + bit_offset: 6 + bit_size: 2 + - name: UART5SEL + description: UART5 clock source selection + bit_offset: 8 + bit_size: 2 + - name: LPUART1SEL + description: LPUART1 clock source selection + bit_offset: 10 + bit_size: 2 + - name: I2C1SEL + description: I2C1 clock source selection + bit_offset: 12 + bit_size: 2 + - name: I2C2SEL + description: I2C2 clock source selection + bit_offset: 14 + bit_size: 2 + - name: I2C3SEL + description: I2C3 clock source selection + bit_offset: 16 + bit_size: 2 + - name: LPTIM1SEL + description: Low power timer 1 clock source selection + bit_offset: 18 + bit_size: 2 + - name: LPTIM2SEL + description: Low power timer 2 clock source selection + bit_offset: 20 + bit_size: 2 + - name: SAI1SEL + description: SAI1 clock source selection + bit_offset: 22 + bit_size: 2 + - name: SAI2SEL + description: SAI2 clock source selection + bit_offset: 24 + bit_size: 2 + - name: CLK48SEL + description: 48 MHz clock source selection + bit_offset: 26 + bit_size: 2 + - name: ADCSEL + description: ADCs clock source selection + bit_offset: 28 + bit_size: 2 + - name: SWPMI1SEL + description: SWPMI1 clock source selection + bit_offset: 30 + bit_size: 1 + - name: DFSDMSEL + description: DFSDM clock source selection + bit_offset: 31 + bit_size: 1 fieldset/CCIPR2: description: Peripherals independent clock configuration register fields: - - name: I2C4SEL - description: I2C4 clock source selection - bit_offset: 0 - bit_size: 2 - - name: DFSDMSEL - description: Digital filter for sigma delta modulator kernel clock source selection - bit_offset: 2 - bit_size: 1 - - name: ADFSDMSEL - description: Digital filter for sigma delta modulator audio clock source selection - bit_offset: 3 - bit_size: 2 - - name: SAI1SEL - description: SAI1 clock source selection - bit_offset: 5 - bit_size: 3 - - name: SAI2SEL - description: SAI2 clock source selection - bit_offset: 8 - bit_size: 3 - - name: DSISEL - description: clock selection - bit_offset: 12 - bit_size: 1 - - name: SDMMCSEL - description: SDMMC clock selection - bit_offset: 14 - bit_size: 1 - - name: PLLSAI2DIVR - description: division factor for LTDC clock - bit_offset: 16 - bit_size: 2 - - name: OSPISEL - description: Octospi clock source selection - bit_offset: 20 - bit_size: 2 + - name: I2C4SEL + description: I2C4 clock source selection + bit_offset: 0 + bit_size: 2 + - name: DFSDMSEL + description: Digital filter for sigma delta modulator kernel clock source selection + bit_offset: 2 + bit_size: 1 + - name: ADFSDMSEL + description: Digital filter for sigma delta modulator audio clock source selection + bit_offset: 3 + bit_size: 2 + - name: SAI1SEL + description: SAI1 clock source selection + bit_offset: 5 + bit_size: 3 + - name: SAI2SEL + description: SAI2 clock source selection + bit_offset: 8 + bit_size: 3 + - name: DSISEL + description: clock selection + bit_offset: 12 + bit_size: 1 + - name: SDMMCSEL + description: SDMMC clock selection + bit_offset: 14 + bit_size: 1 + - name: PLLSAI2DIVR + description: division factor for LTDC clock + bit_offset: 16 + bit_size: 2 + - name: OSPISEL + description: Octospi clock source selection + bit_offset: 20 + bit_size: 2 fieldset/CFGR: description: Clock configuration register fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: System clock switch status - bit_offset: 2 - bit_size: 2 - enum: SW - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - enum: HPRE - - name: PPRE1 - description: APB low-speed prescaler (APB1) - bit_offset: 8 - bit_size: 3 - enum: PPRE - - name: PPRE2 - description: APB high-speed prescaler (APB2) - bit_offset: 11 - bit_size: 3 - enum: PPRE - - name: STOPWUCK - description: Wakeup from Stop and CSS backup clock selection - bit_offset: 15 - bit_size: 1 - enum: STOPWUCK - - name: MCOSEL - description: Microcontroller clock output selection - bit_offset: 24 - bit_size: 4 - enum: MCOSEL - - name: MCOPRE - description: Microcontroller clock output prescaler - bit_offset: 28 - bit_size: 3 - enum: MCOPRE + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB low-speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high-speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: STOPWUCK + description: Wakeup from Stop and CSS backup clock selection + bit_offset: 15 + bit_size: 1 + enum: STOPWUCK + - name: MCOSEL + description: Microcontroller clock output selection + bit_offset: 24 + bit_size: 4 + enum: MCOSEL + - name: MCOPRE + description: Microcontroller clock output prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: - - name: LSIRDYC - description: LSI ready interrupt clear - bit_offset: 0 - bit_size: 1 - - name: LSERDYC - description: LSE ready interrupt clear - bit_offset: 1 - bit_size: 1 - - name: MSIRDYC - description: MSI ready interrupt clear - bit_offset: 2 - bit_size: 1 - - name: HSIRDYC - description: HSI ready interrupt clear - bit_offset: 3 - bit_size: 1 - - name: HSERDYC - description: HSE ready interrupt clear - bit_offset: 4 - bit_size: 1 - - name: PLLRDYC - description: PLL ready interrupt clear - bit_offset: 5 - bit_size: 1 - - name: PLLSAI1RDYC - description: PLLSAI1 ready interrupt clear - bit_offset: 6 - bit_size: 1 - - name: PLLSAI2RDYC - description: PLLSAI2 ready interrupt clear - bit_offset: 7 - bit_size: 1 - - name: CSSC - description: Clock security system interrupt clear - bit_offset: 8 - bit_size: 1 - - name: LSECSSC - description: LSE Clock security system interrupt clear - bit_offset: 9 - bit_size: 1 - - name: HSI48RDYC - description: HSI48 oscillator ready interrupt clear - bit_offset: 10 - bit_size: 1 + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 1 + bit_size: 1 + - name: MSIRDYC + description: MSI ready interrupt clear + bit_offset: 2 + bit_size: 1 + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 4 + bit_size: 1 + - name: PLLRDYC + description: PLL ready interrupt clear + bit_offset: 5 + bit_size: 1 + - name: PLLSAI1RDYC + description: PLLSAI1 ready interrupt clear + bit_offset: 6 + bit_size: 1 + - name: PLLSAI2RDYC + description: PLLSAI2 ready interrupt clear + bit_offset: 7 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 8 + bit_size: 1 + - name: LSECSSC + description: LSE Clock security system interrupt clear + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYC + description: HSI48 oscillator ready interrupt clear + bit_offset: 10 + bit_size: 1 fieldset/CIER: description: Clock interrupt enable register fields: - - name: LSIRDYIE - description: LSI ready interrupt enable - bit_offset: 0 - bit_size: 1 - - name: LSERDYIE - description: LSE ready interrupt enable - bit_offset: 1 - bit_size: 1 - - name: MSIRDYIE - description: MSI ready interrupt enable - bit_offset: 2 - bit_size: 1 - - name: HSIRDYIE - description: HSI ready interrupt enable - bit_offset: 3 - bit_size: 1 - - name: HSERDYIE - description: HSE ready interrupt enable - bit_offset: 4 - bit_size: 1 - - name: PLLRDYIE - description: PLL ready interrupt enable - bit_offset: 5 - bit_size: 1 - - name: PLLSAI1RDYIE - description: PLLSAI1 ready interrupt enable - bit_offset: 6 - bit_size: 1 - - name: PLLSAI2RDYIE - description: PLLSAI2 ready interrupt enable - bit_offset: 7 - bit_size: 1 - - name: LSECSSIE - description: LSE clock security system interrupt enable - bit_offset: 9 - bit_size: 1 - - name: HSI48RDYIE - description: HSI48 ready interrupt enable - bit_offset: 10 - bit_size: 1 + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 1 + bit_size: 1 + - name: MSIRDYIE + description: MSI ready interrupt enable + bit_offset: 2 + bit_size: 1 + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 4 + bit_size: 1 + - name: PLLRDYIE + description: PLL ready interrupt enable + bit_offset: 5 + bit_size: 1 + - name: PLLSAI1RDYIE + description: PLLSAI1 ready interrupt enable + bit_offset: 6 + bit_size: 1 + - name: PLLSAI2RDYIE + description: PLLSAI2 ready interrupt enable + bit_offset: 7 + bit_size: 1 + - name: LSECSSIE + description: LSE clock security system interrupt enable + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYIE + description: HSI48 ready interrupt enable + bit_offset: 10 + bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register fields: - - name: LSIRDYF - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - - name: MSIRDYF - description: MSI ready interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSIRDYF - description: HSI ready interrupt flag - bit_offset: 3 - bit_size: 1 - - name: HSERDYF - description: HSE ready interrupt flag - bit_offset: 4 - bit_size: 1 - - name: PLLRDYF - description: PLL ready interrupt flag - bit_offset: 5 - bit_size: 1 - - name: PLLSAI1RDYF - description: PLLSAI1 ready interrupt flag - bit_offset: 6 - bit_size: 1 - - name: PLLSAI2RDYF - description: PLLSAI2 ready interrupt flag - bit_offset: 7 - bit_size: 1 - - name: CSSF - description: Clock security system interrupt flag - bit_offset: 8 - bit_size: 1 - - name: LSECSSF - description: LSE Clock security system interrupt flag - bit_offset: 9 - bit_size: 1 - - name: HSI48RDYF - description: HSI48 ready interrupt flag - bit_offset: 10 - bit_size: 1 + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: MSIRDYF + description: MSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLLRDYF + description: PLL ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: PLLSAI1RDYF + description: PLLSAI1 ready interrupt flag + bit_offset: 6 + bit_size: 1 + - name: PLLSAI2RDYF + description: PLLSAI2 ready interrupt flag + bit_offset: 7 + bit_size: 1 + - name: CSSF + description: Clock security system interrupt flag + bit_offset: 8 + bit_size: 1 + - name: LSECSSF + description: LSE Clock security system interrupt flag + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYF + description: HSI48 ready interrupt flag + bit_offset: 10 + bit_size: 1 fieldset/CR: description: Clock control register fields: - - name: MSION - description: MSI clock enable - bit_offset: 0 - bit_size: 1 - - name: MSIRDY - description: MSI clock ready flag - bit_offset: 1 - bit_size: 1 - - name: MSIPLLEN - description: MSI clock PLL enable - bit_offset: 2 - bit_size: 1 - - name: MSIRGSEL - description: MSI clock range selection - bit_offset: 3 - bit_size: 1 - - name: MSIRANGE - description: MSI clock ranges - bit_offset: 4 - bit_size: 4 - enum: MSIRANGE - - name: HSION - description: HSI clock enable - bit_offset: 8 - bit_size: 1 - - name: HSIKERON - description: HSI always enable for peripheral kernels - bit_offset: 9 - bit_size: 1 - - name: HSIRDY - description: HSI clock ready flag - bit_offset: 10 - bit_size: 1 - - name: HSIASFS - description: HSI automatic start from Stop - bit_offset: 11 - bit_size: 1 - - name: HSEON - description: HSE clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: HSE crystal oscillator bypass - bit_offset: 18 - bit_size: 1 - - name: CSSON - description: Clock security system enable - bit_offset: 19 - bit_size: 1 - - name: PLLON - description: Main PLL enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: Main PLL clock ready flag - bit_offset: 25 - bit_size: 1 - - name: PLLSAI1ON - description: SAI1 PLL enable - bit_offset: 26 - bit_size: 1 - - name: PLLSAI1RDY - description: SAI1 PLL clock ready flag - bit_offset: 27 - bit_size: 1 - - name: PLLSAI2ON - description: SAI2 PLL enable - bit_offset: 28 - bit_size: 1 - - name: PLLSAI2RDY - description: SAI2 PLL clock ready flag - bit_offset: 29 - bit_size: 1 + - name: MSION + description: MSI clock enable + bit_offset: 0 + bit_size: 1 + - name: MSIRDY + description: MSI clock ready flag + bit_offset: 1 + bit_size: 1 + - name: MSIPLLEN + description: MSI clock PLL enable + bit_offset: 2 + bit_size: 1 + - name: MSIRGSEL + description: MSI clock range selection + bit_offset: 3 + bit_size: 1 + - name: MSIRANGE + description: MSI clock ranges + bit_offset: 4 + bit_size: 4 + enum: MSIRANGE + - name: HSION + description: HSI clock enable + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: HSI always enable for peripheral kernels + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: HSI clock ready flag + bit_offset: 10 + bit_size: 1 + - name: HSIASFS + description: HSI automatic start from Stop + bit_offset: 11 + bit_size: 1 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: HSE crystal oscillator bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: Main PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL clock ready flag + bit_offset: 25 + bit_size: 1 + - name: PLLSAI1ON + description: SAI1 PLL enable + bit_offset: 26 + bit_size: 1 + - name: PLLSAI1RDY + description: SAI1 PLL clock ready flag + bit_offset: 27 + bit_size: 1 + - name: PLLSAI2ON + description: SAI2 PLL enable + bit_offset: 28 + bit_size: 1 + - name: PLLSAI2RDY + description: SAI2 PLL clock ready flag + bit_offset: 29 + bit_size: 1 fieldset/CRRCR: description: Clock recovery RC register fields: - - name: HSI48ON - description: HSI48 clock enable - bit_offset: 0 - bit_size: 1 - - name: HSI48RDY - description: HSI48 clock ready flag - bit_offset: 1 - bit_size: 1 - - name: HSI48CAL - description: HSI48 clock calibration - bit_offset: 7 - bit_size: 9 + - name: HSI48ON + description: HSI48 clock enable + bit_offset: 0 + bit_size: 1 + - name: HSI48RDY + description: HSI48 clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSI48CAL + description: HSI48 clock calibration + bit_offset: 7 + bit_size: 9 fieldset/CSR: description: CSR fields: - - name: LSION - description: LSI oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: LSI oscillator ready - bit_offset: 1 - bit_size: 1 - - name: MSISRANGE - description: SI range after Standby mode - bit_offset: 8 - bit_size: 4 - - name: RMVF - description: Remove reset flag - bit_offset: 23 - bit_size: 1 - - name: FWRSTF - description: Firewall reset flag - bit_offset: 24 - bit_size: 1 - - name: OBLRSTF - description: Option byte loader reset flag - bit_offset: 25 - bit_size: 1 - - name: PINRSTF - description: Pin reset flag - bit_offset: 26 - bit_size: 1 - - name: BORRSTF - description: BOR flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: Independent window watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSION + description: LSI oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: LSI oscillator ready + bit_offset: 1 + bit_size: 1 + - name: MSISRANGE + description: SI range after Standby mode + bit_offset: 8 + bit_size: 4 + - name: RMVF + description: Remove reset flag + bit_offset: 23 + bit_size: 1 + - name: FWRSTF + description: Firewall reset flag + bit_offset: 24 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: Pin reset flag + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: BOR flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent window watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 fieldset/ICSCR: description: Internal clock sources calibration register fields: - - name: MSICAL - description: MSI clock calibration - bit_offset: 0 - bit_size: 8 - - name: MSITRIM - description: MSI clock trimming - bit_offset: 8 - bit_size: 8 - - name: HSICAL - description: HSI clock calibration - bit_offset: 16 - bit_size: 8 - - name: HSITRIM - description: HSI clock trimming - bit_offset: 24 - bit_size: 7 + - name: MSICAL + description: MSI clock calibration + bit_offset: 0 + bit_size: 8 + - name: MSITRIM + description: MSI clock trimming + bit_offset: 8 + bit_size: 8 + - name: HSICAL + description: HSI clock calibration + bit_offset: 16 + bit_size: 8 + - name: HSITRIM + description: HSI clock trimming + bit_offset: 24 + bit_size: 7 fieldset/PLLCFGR: description: PLL configuration register fields: - - name: PLLSRC - description: "Main PLL, PLLSAI1 and PLLSAI2 entry clock source" - bit_offset: 0 - bit_size: 2 - enum: PLLSRC - - name: PLLM - description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock - bit_offset: 4 - bit_size: 4 - - name: PLLN - description: Main PLL multiplication factor for VCO - bit_offset: 8 - bit_size: 7 - - name: PLLPEN - description: Main PLL PLLSAI3CLK output enable - bit_offset: 16 - bit_size: 1 - - name: PLLP - description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) - bit_offset: 17 - bit_size: 1 - - name: PLLQEN - description: Main PLL PLLUSB1CLK output enable - bit_offset: 20 - bit_size: 1 - - name: PLLQ - description: Main PLL division factor for PLLUSB1CLK(48 MHz clock) - bit_offset: 21 - bit_size: 2 - - name: PLLREN - description: Main PLL PLLCLK output enable - bit_offset: 24 - bit_size: 1 - - name: PLLR - description: Main PLL division factor for PLLCLK (system clock) - bit_offset: 25 - bit_size: 2 - - name: PLLPDIV - description: Main PLL division factor for PLLSAI2CLK - bit_offset: 27 - bit_size: 5 + - name: PLLSRC + description: Main PLL, PLLSAI1 and PLLSAI2 entry clock source + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: PLLM + description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock + bit_offset: 4 + bit_size: 4 + - name: PLLN + description: Main PLL multiplication factor for VCO + bit_offset: 8 + bit_size: 7 + - name: PLLPEN + description: Main PLL PLLSAI3CLK output enable + bit_offset: 16 + bit_size: 1 + - name: PLLP + description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) + bit_offset: 17 + bit_size: 1 + - name: PLLQEN + description: Main PLL PLLUSB1CLK output enable + bit_offset: 20 + bit_size: 1 + - name: PLLQ + description: Main PLL division factor for PLLUSB1CLK(48 MHz clock) + bit_offset: 21 + bit_size: 2 + - name: PLLREN + description: Main PLL PLLCLK output enable + bit_offset: 24 + bit_size: 1 + - name: PLLR + description: Main PLL division factor for PLLCLK (system clock) + bit_offset: 25 + bit_size: 2 + - name: PLLPDIV + description: Main PLL division factor for PLLSAI2CLK + bit_offset: 27 + bit_size: 5 fieldset/PLLSAI1CFGR: description: PLLSAI1 configuration register fields: - - name: PLLSAI1M - description: Division factor for PLLSAI1 input clock - bit_offset: 4 - bit_size: 4 - - name: PLLSAI1N - description: SAI1PLL multiplication factor for VCO - bit_offset: 8 - bit_size: 7 - - name: PLLSAI1PEN - description: SAI1PLL PLLSAI1CLK output enable - bit_offset: 16 - bit_size: 1 - - name: PLLSAI1P - description: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) - bit_offset: 17 - bit_size: 1 - - name: PLLSAI1QEN - description: SAI1PLL PLLUSB2CLK output enable - bit_offset: 20 - bit_size: 1 - - name: PLLSAI1Q - description: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) - bit_offset: 21 - bit_size: 2 - - name: PLLSAI1REN - description: PLLSAI1 PLLADC1CLK output enable - bit_offset: 24 - bit_size: 1 - - name: PLLSAI1R - description: PLLSAI1 division factor for PLLADC1CLK (ADC clock) - bit_offset: 25 - bit_size: 2 - - name: PLLSAI1PDIV - description: PLLSAI1 division factor for PLLSAI1CLK - bit_offset: 27 - bit_size: 5 + - name: PLLSAI1M + description: Division factor for PLLSAI1 input clock + bit_offset: 4 + bit_size: 4 + - name: PLLSAI1N + description: SAI1PLL multiplication factor for VCO + bit_offset: 8 + bit_size: 7 + - name: PLLSAI1PEN + description: SAI1PLL PLLSAI1CLK output enable + bit_offset: 16 + bit_size: 1 + - name: PLLSAI1P + description: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) + bit_offset: 17 + bit_size: 1 + - name: PLLSAI1QEN + description: SAI1PLL PLLUSB2CLK output enable + bit_offset: 20 + bit_size: 1 + - name: PLLSAI1Q + description: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) + bit_offset: 21 + bit_size: 2 + - name: PLLSAI1REN + description: PLLSAI1 PLLADC1CLK output enable + bit_offset: 24 + bit_size: 1 + - name: PLLSAI1R + description: PLLSAI1 division factor for PLLADC1CLK (ADC clock) + bit_offset: 25 + bit_size: 2 + - name: PLLSAI1PDIV + description: PLLSAI1 division factor for PLLSAI1CLK + bit_offset: 27 + bit_size: 5 fieldset/PLLSAI2CFGR: description: PLLSAI2 configuration register fields: - - name: PLLSAI2M - description: Division factor for PLLSAI2 input clock - bit_offset: 4 - bit_size: 4 - - name: PLLSAI2N - description: SAI2PLL multiplication factor for VCO - bit_offset: 8 - bit_size: 7 - - name: PLLSAI2PEN - description: SAI2PLL PLLSAI2CLK output enable - bit_offset: 16 - bit_size: 1 - - name: PLLSAI2P - description: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock) - bit_offset: 17 - bit_size: 1 - - name: PLLSAI2QEN - description: PLLSAI2 division factor for PLLDISCLK - bit_offset: 20 - bit_size: 1 - - name: PLLSAI2Q - description: SAI2PLL PLLSAI2CLK output enable - bit_offset: 21 - bit_size: 2 - - name: PLLSAI2REN - description: PLLSAI2 PLLADC2CLK output enable - bit_offset: 24 - bit_size: 1 - - name: PLLSAI2R - description: PLLSAI2 division factor for PLLADC2CLK (ADC clock) - bit_offset: 25 - bit_size: 2 - - name: PLLSAI2PDIV - description: PLLSAI2 division factor for PLLSAI2CLK - bit_offset: 27 - bit_size: 5 + - name: PLLSAI2M + description: Division factor for PLLSAI2 input clock + bit_offset: 4 + bit_size: 4 + - name: PLLSAI2N + description: SAI2PLL multiplication factor for VCO + bit_offset: 8 + bit_size: 7 + - name: PLLSAI2PEN + description: SAI2PLL PLLSAI2CLK output enable + bit_offset: 16 + bit_size: 1 + - name: PLLSAI2P + description: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock) + bit_offset: 17 + bit_size: 1 + - name: PLLSAI2QEN + description: PLLSAI2 division factor for PLLDISCLK + bit_offset: 20 + bit_size: 1 + - name: PLLSAI2Q + description: SAI2PLL PLLSAI2CLK output enable + bit_offset: 21 + bit_size: 2 + - name: PLLSAI2REN + description: PLLSAI2 PLLADC2CLK output enable + bit_offset: 24 + bit_size: 1 + - name: PLLSAI2R + description: PLLSAI2 division factor for PLLADC2CLK (ADC clock) + bit_offset: 25 + bit_size: 2 + - name: PLLSAI2PDIV + description: PLLSAI2 division factor for PLLSAI2CLK + bit_offset: 27 + bit_size: 5 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: system clock not divided - value: 0 - - name: Div2 - description: system clock divided by 2 - value: 8 - - name: Div4 - description: system clock divided by 4 - value: 9 - - name: Div8 - description: system clock divided by 8 - value: 10 - - name: Div16 - description: system clock divided by 16 - value: 11 - - name: Div64 - description: system clock divided by 64 - value: 12 - - name: Div128 - description: system clock divided by 128 - value: 13 - - name: Div256 - description: system clock divided by 256 - value: 14 - - name: Div512 - description: system clock divided by 512 - value: 15 + - name: Div1 + description: system clock not divided + value: 0 + - name: Div2 + description: system clock divided by 2 + value: 8 + - name: Div4 + description: system clock divided by 4 + value: 9 + - name: Div8 + description: system clock divided by 8 + value: 10 + - name: Div16 + description: system clock divided by 16 + value: 11 + - name: Div64 + description: system clock divided by 64 + value: 12 + - name: Div128 + description: system clock divided by 128 + value: 13 + - name: Div256 + description: system clock divided by 256 + value: 14 + - name: Div512 + description: system clock divided by 512 + value: 15 enum/LSEDRV: bit_size: 2 variants: - - name: Low - description: Lowest drive - value: 0 - - name: MediumLow - description: Medium low drive - value: 1 - - name: MediumHigh - description: Medium high drive - value: 2 - - name: High - description: Highest drive - value: 3 + - name: Low + description: Lowest drive + value: 0 + - name: MediumLow + description: Medium low drive + value: 1 + - name: MediumHigh + description: Medium high drive + value: 2 + - name: High + description: Highest drive + value: 3 enum/MCOPRE: bit_size: 3 variants: - - name: Div1 - description: No division - value: 0 - - name: Div2 - description: Division by 2 - value: 1 - - name: Div4 - description: Division by 4 - value: 2 - - name: Div8 - description: Division by 8 - value: 3 - - name: Div16 - description: Division by 16 - value: 4 + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 + - name: Div16 + description: Division by 16 + value: 4 enum/MCOSEL: bit_size: 4 variants: - - name: NoClock - description: No clock - value: 0 - - name: SYSCLK - description: SYSCLK clock selected - value: 1 - - name: MSI - description: MSI oscillator clock selected - value: 2 - - name: HSI16 - description: HSI oscillator clock selected - value: 3 - - name: HSE - description: HSE oscillator clock selected - value: 4 - - name: PLL - description: PLL clock selected - value: 5 - - name: LSI - description: LSI oscillator clock selected - value: 6 - - name: LSE - description: LSE oscillator clock selected - value: 7 - - name: HSI48 - description: HSI48 oscillator clock selected - value: 8 + - name: NoClock + description: No clock + value: 0 + - name: SYSCLK + description: SYSCLK clock selected + value: 1 + - name: MSI + description: MSI oscillator clock selected + value: 2 + - name: HSI16 + description: HSI oscillator clock selected + value: 3 + - name: HSE + description: HSE oscillator clock selected + value: 4 + - name: PLL + description: PLL clock selected + value: 5 + - name: LSI + description: LSI oscillator clock selected + value: 6 + - name: LSE + description: LSE oscillator clock selected + value: 7 + - name: HSI48 + description: HSI48 oscillator clock selected + value: 8 enum/MSIRANGE: bit_size: 4 variants: - - name: Range100K - description: range 0 around 100 kHz - value: 0 - - name: Range200K - description: range 1 around 200 kHz - value: 1 - - name: Range400K - description: range 2 around 400 kHz - value: 2 - - name: Range800K - description: range 3 around 800 kHz - value: 3 - - name: Range1M - description: range 4 around 1 MHz - value: 4 - - name: Range2M - description: range 5 around 2 MHz - value: 5 - - name: Range4M - description: range 6 around 4 MHz - value: 6 - - name: Range8M - description: range 7 around 8 MHz - value: 7 - - name: Range16M - description: range 8 around 16 MHz - value: 8 - - name: Range24M - description: range 9 around 24 MHz - value: 9 - - name: Range32M - description: range 10 around 32 MHz - value: 10 - - name: Range48M - description: range 11 around 48 MHz - value: 11 + - name: Range100K + description: range 0 around 100 kHz + value: 0 + - name: Range200K + description: range 1 around 200 kHz + value: 1 + - name: Range400K + description: range 2 around 400 kHz + value: 2 + - name: Range800K + description: range 3 around 800 kHz + value: 3 + - name: Range1M + description: range 4 around 1 MHz + value: 4 + - name: Range2M + description: range 5 around 2 MHz + value: 5 + - name: Range4M + description: range 6 around 4 MHz + value: 6 + - name: Range8M + description: range 7 around 8 MHz + value: 7 + - name: Range16M + description: range 8 around 16 MHz + value: 8 + - name: Range24M + description: range 9 around 24 MHz + value: 9 + - name: Range32M + description: range 10 around 32 MHz + value: 10 + - name: Range48M + description: range 11 around 48 MHz + value: 11 enum/PLLSRC: bit_size: 2 variants: - - name: None - description: No clock sent to PLL - value: 0 - - name: MSI - description: MSI selected as PLL input clock - value: 1 - - name: HSI16 - description: HSI selected as PLL input clock - value: 2 - - name: HSE - description: HSE selected as PLL input clock - value: 3 + - name: None + description: No clock sent to PLL + value: 0 + - name: MSI + description: MSI selected as PLL input clock + value: 1 + - name: HSI16 + description: HSI selected as PLL input clock + value: 2 + - name: HSE + description: HSE selected as PLL input clock + value: 3 enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK divided by 2 - value: 4 - - name: Div4 - description: HCLK divided by 4 - value: 5 - - name: Div8 - description: HCLK divided by 8 - value: 6 - - name: Div16 - description: HCLK divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: HSE oscillator clock divided by 32 used as the RTC clock - value: 3 + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by 32 used as the RTC clock + value: 3 enum/STOPWUCK: bit_size: 1 variants: - - name: MSI - description: MSI oscillator selected as wake-up from Stop clock - value: 0 - - name: HSI16 - description: HSI oscillator selected as wake-up from Stop clock - value: 1 + - name: MSI + description: MSI oscillator selected as wake-up from Stop clock + value: 0 + - name: HSI16 + description: HSI oscillator selected as wake-up from Stop clock + value: 1 enum/SW: bit_size: 2 variants: - - name: MSI - description: MSI selected as system clock - value: 0 - - name: HSI16 - description: HSI selected as system clock - value: 1 - - name: HSE - description: HSE selected as system clock - value: 2 - - name: PLL - description: PLL selected as system clock - value: 3 + - name: MSI + description: MSI selected as system clock + value: 0 + - name: HSI16 + description: HSI selected as system clock + value: 1 + - name: HSE + description: HSE selected as system clock + value: 2 + - name: PLL + description: PLL selected as system clock + value: 3 diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml index 9cf1aaa..1ab2625 100644 --- a/data/registers/rcc_l5.yaml +++ b/data/registers/rcc_l5.yaml @@ -1,2202 +1,2201 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: Clock control register - byte_offset: 0 - fieldset: CR - - name: ICSCR - description: Internal clock sources calibration register - byte_offset: 4 - fieldset: ICSCR - - name: CFGR - description: Clock configuration register - byte_offset: 8 - fieldset: CFGR - - name: PLLCFGR - description: PLL configuration register - byte_offset: 12 - fieldset: PLLCFGR - - name: PLLSAI1CFGR - description: PLLSAI1 configuration register - byte_offset: 16 - fieldset: PLLSAI1CFGR - - name: PLLSAI2CFGR - description: PLLSAI2 configuration register - byte_offset: 20 - fieldset: PLLSAI2CFGR - - name: CIER - description: Clock interrupt enable register - byte_offset: 24 - fieldset: CIER - - name: CIFR - description: Clock interrupt flag register - byte_offset: 28 - access: Read - fieldset: CIFR - - name: CICR - description: Clock interrupt clear register - byte_offset: 32 - access: Write - fieldset: CICR - - name: AHB1RSTR - description: AHB1 peripheral reset register - byte_offset: 40 - fieldset: AHB1RSTR - - name: AHB2RSTR - description: AHB2 peripheral reset register - byte_offset: 44 - fieldset: AHB2RSTR - - name: AHB3RSTR - description: AHB3 peripheral reset register - byte_offset: 48 - fieldset: AHB3RSTR - - name: APB1RSTR1 - description: APB1 peripheral reset register 1 - byte_offset: 56 - fieldset: APB1RSTR1 - - name: APB1RSTR2 - description: APB1 peripheral reset register 2 - byte_offset: 60 - fieldset: APB1RSTR2 - - name: APB2RSTR - description: APB2 peripheral reset register - byte_offset: 64 - fieldset: APB2RSTR - - name: AHB1ENR - description: AHB1 peripheral clock enable register - byte_offset: 72 - fieldset: AHB1ENR - - name: AHB2ENR - description: AHB2 peripheral clock enable register - byte_offset: 76 - fieldset: AHB2ENR - - name: AHB3ENR - description: AHB3 peripheral clock enable register - byte_offset: 80 - fieldset: AHB3ENR - - name: APB1ENR1 - description: APB1ENR1 - byte_offset: 88 - fieldset: APB1ENR1 - - name: APB1ENR2 - description: APB1 peripheral clock enable register 2 - byte_offset: 92 - fieldset: APB1ENR2 - - name: APB2ENR - description: APB2ENR - byte_offset: 96 - fieldset: APB2ENR - - name: AHB1SMENR - description: AHB1 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 104 - fieldset: AHB1SMENR - - name: AHB2SMENR - description: AHB2 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 108 - fieldset: AHB2SMENR - - name: AHB3SMENR - description: AHB3 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 112 - fieldset: AHB3SMENR - - name: APB1SMENR1 - description: APB1SMENR1 - byte_offset: 120 - fieldset: APB1SMENR1 - - name: APB1SMENR2 - description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 - byte_offset: 124 - fieldset: APB1SMENR2 - - name: APB2SMENR - description: APB2SMENR - byte_offset: 128 - fieldset: APB2SMENR - - name: CCIPR1 - description: CCIPR1 - byte_offset: 136 - fieldset: CCIPR1 - - name: BDCR - description: BDCR - byte_offset: 144 - fieldset: BDCR - - name: CSR - description: CSR - byte_offset: 148 - fieldset: CSR - - name: CRRCR - description: Clock recovery RC register - byte_offset: 152 - fieldset: CRRCR - - name: CCIPR2 - description: Peripherals independent clock configuration register - byte_offset: 156 - fieldset: CCIPR2 - - name: SECCFGR - description: RCC secure configuration register - byte_offset: 184 - fieldset: SECCFGR - - name: SECSR - description: RCC secure status register - byte_offset: 188 - fieldset: SECSR - - name: AHB1SECSR - description: RCC AHB1 security status register - byte_offset: 232 - access: Read - fieldset: AHB1SECSR - - name: AHB2SECSR - description: RCC AHB2 security status register - byte_offset: 236 - access: Read - fieldset: AHB2SECSR - - name: AHB3SECSR - description: RCC AHB3 security status register - byte_offset: 240 - access: Read - fieldset: AHB3SECSR - - name: APB1SECSR1 - description: RCC APB1 security status register 1 - byte_offset: 248 - access: Read - fieldset: APB1SECSR1 - - name: APB1SECSR2 - description: RCC APB1 security status register 2 - byte_offset: 252 - access: Read - fieldset: APB1SECSR2 - - name: APB2SECSR - description: RCC APB2 security status register - byte_offset: 256 - access: Read - fieldset: APB2SECSR + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: Internal clock sources calibration register + byte_offset: 4 + fieldset: ICSCR + - name: CFGR + description: Clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: PLLCFGR + description: PLL configuration register + byte_offset: 12 + fieldset: PLLCFGR + - name: PLLSAI1CFGR + description: PLLSAI1 configuration register + byte_offset: 16 + fieldset: PLLSAI1CFGR + - name: PLLSAI2CFGR + description: PLLSAI2 configuration register + byte_offset: 20 + fieldset: PLLSAI2CFGR + - name: CIER + description: Clock interrupt enable register + byte_offset: 24 + fieldset: CIER + - name: CIFR + description: Clock interrupt flag register + byte_offset: 28 + access: Read + fieldset: CIFR + - name: CICR + description: Clock interrupt clear register + byte_offset: 32 + access: Write + fieldset: CICR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 40 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: AHB2 peripheral reset register + byte_offset: 44 + fieldset: AHB2RSTR + - name: AHB3RSTR + description: AHB3 peripheral reset register + byte_offset: 48 + fieldset: AHB3RSTR + - name: APB1RSTR1 + description: APB1 peripheral reset register 1 + byte_offset: 56 + fieldset: APB1RSTR1 + - name: APB1RSTR2 + description: APB1 peripheral reset register 2 + byte_offset: 60 + fieldset: APB1RSTR2 + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 64 + fieldset: APB2RSTR + - name: AHB1ENR + description: AHB1 peripheral clock enable register + byte_offset: 72 + fieldset: AHB1ENR + - name: AHB2ENR + description: AHB2 peripheral clock enable register + byte_offset: 76 + fieldset: AHB2ENR + - name: AHB3ENR + description: AHB3 peripheral clock enable register + byte_offset: 80 + fieldset: AHB3ENR + - name: APB1ENR1 + description: APB1ENR1 + byte_offset: 88 + fieldset: APB1ENR1 + - name: APB1ENR2 + description: APB1 peripheral clock enable register 2 + byte_offset: 92 + fieldset: APB1ENR2 + - name: APB2ENR + description: APB2ENR + byte_offset: 96 + fieldset: APB2ENR + - name: AHB1SMENR + description: AHB1 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 104 + fieldset: AHB1SMENR + - name: AHB2SMENR + description: AHB2 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 108 + fieldset: AHB2SMENR + - name: AHB3SMENR + description: AHB3 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 112 + fieldset: AHB3SMENR + - name: APB1SMENR1 + description: APB1SMENR1 + byte_offset: 120 + fieldset: APB1SMENR1 + - name: APB1SMENR2 + description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 + byte_offset: 124 + fieldset: APB1SMENR2 + - name: APB2SMENR + description: APB2SMENR + byte_offset: 128 + fieldset: APB2SMENR + - name: CCIPR1 + description: CCIPR1 + byte_offset: 136 + fieldset: CCIPR1 + - name: BDCR + description: BDCR + byte_offset: 144 + fieldset: BDCR + - name: CSR + description: CSR + byte_offset: 148 + fieldset: CSR + - name: CRRCR + description: Clock recovery RC register + byte_offset: 152 + fieldset: CRRCR + - name: CCIPR2 + description: Peripherals independent clock configuration register + byte_offset: 156 + fieldset: CCIPR2 + - name: SECCFGR + description: RCC secure configuration register + byte_offset: 184 + fieldset: SECCFGR + - name: SECSR + description: RCC secure status register + byte_offset: 188 + fieldset: SECSR + - name: AHB1SECSR + description: RCC AHB1 security status register + byte_offset: 232 + access: Read + fieldset: AHB1SECSR + - name: AHB2SECSR + description: RCC AHB2 security status register + byte_offset: 236 + access: Read + fieldset: AHB2SECSR + - name: AHB3SECSR + description: RCC AHB3 security status register + byte_offset: 240 + access: Read + fieldset: AHB3SECSR + - name: APB1SECSR1 + description: RCC APB1 security status register 1 + byte_offset: 248 + access: Read + fieldset: APB1SECSR1 + - name: APB1SECSR2 + description: RCC APB1 security status register 2 + byte_offset: 252 + access: Read + fieldset: APB1SECSR2 + - name: APB2SECSR + description: RCC APB2 security status register + byte_offset: 256 + access: Read + fieldset: APB2SECSR fieldset/AHB1ENR: description: AHB1 peripheral clock enable register fields: - - name: DMA1EN - description: DMA1 clock enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: DMA2 clock enable - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1EN - description: DMAMUX clock enable - bit_offset: 2 - bit_size: 1 - - name: FLASHEN - description: Flash memory interface clock enable - bit_offset: 8 - bit_size: 1 - - name: CRCEN - description: CRC clock enable - bit_offset: 12 - bit_size: 1 - - name: TSCEN - description: Touch Sensing Controller clock enable - bit_offset: 16 - bit_size: 1 - - name: GTZCEN - description: GTZCEN - bit_offset: 22 - bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1EN + description: DMAMUX clock enable + bit_offset: 2 + bit_size: 1 + - name: FLASHEN + description: Flash memory interface clock enable + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: TSCEN + description: Touch Sensing Controller clock enable + bit_offset: 16 + bit_size: 1 + - name: GTZCEN + description: GTZCEN + bit_offset: 22 + bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - - name: DMA1RST - description: DMA1 reset - bit_offset: 0 - bit_size: 1 - - name: DMA2RST - description: DMA2 reset - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1RST - description: DMAMUX1RST - bit_offset: 2 - bit_size: 1 - - name: FLASHRST - description: Flash memory interface reset - bit_offset: 8 - bit_size: 1 - - name: CRCRST - description: CRC reset - bit_offset: 12 - bit_size: 1 - - name: TSCRST - description: Touch Sensing Controller reset - bit_offset: 16 - bit_size: 1 - - name: GTZCRST - description: GTZC reset - bit_offset: 22 - bit_size: 1 + - name: DMA1RST + description: DMA1 reset + bit_offset: 0 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1RST + description: DMAMUX1RST + bit_offset: 2 + bit_size: 1 + - name: FLASHRST + description: Flash memory interface reset + bit_offset: 8 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 + - name: TSCRST + description: Touch Sensing Controller reset + bit_offset: 16 + bit_size: 1 + - name: GTZCRST + description: GTZC reset + bit_offset: 22 + bit_size: 1 fieldset/AHB1SECSR: description: RCC AHB1 security status register fields: - - name: DMA1SECF - description: DMA1SECF - bit_offset: 0 - bit_size: 1 - - name: DMA2SECF - description: DMA2SECF - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1SECF - description: DMAMUX1SECF - bit_offset: 2 - bit_size: 1 - - name: FLASHSECF - description: FLASHSECF - bit_offset: 8 - bit_size: 1 - - name: SRAM1SECF - description: SRAM1SECF - bit_offset: 9 - bit_size: 1 - - name: CRCSECF - description: CRCSECF - bit_offset: 12 - bit_size: 1 - - name: TSCSECF - description: TSCSECF - bit_offset: 16 - bit_size: 1 - - name: GTZCSECF - description: GTZCSECF - bit_offset: 22 - bit_size: 1 - - name: ICACHESECF - description: ICACHESECF - bit_offset: 23 - bit_size: 1 + - name: DMA1SECF + description: DMA1SECF + bit_offset: 0 + bit_size: 1 + - name: DMA2SECF + description: DMA2SECF + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1SECF + description: DMAMUX1SECF + bit_offset: 2 + bit_size: 1 + - name: FLASHSECF + description: FLASHSECF + bit_offset: 8 + bit_size: 1 + - name: SRAM1SECF + description: SRAM1SECF + bit_offset: 9 + bit_size: 1 + - name: CRCSECF + description: CRCSECF + bit_offset: 12 + bit_size: 1 + - name: TSCSECF + description: TSCSECF + bit_offset: 16 + bit_size: 1 + - name: GTZCSECF + description: GTZCSECF + bit_offset: 22 + bit_size: 1 + - name: ICACHESECF + description: ICACHESECF + bit_offset: 23 + bit_size: 1 fieldset/AHB1SMENR: description: AHB1 peripheral clocks enable in Sleep and Stop modes register fields: - - name: DMA1SMEN - description: DMA1 clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: DMA2SMEN - description: DMA2 clocks enable during Sleep and Stop modes - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1SMEN - description: DMAMUX clock enable during Sleep and Stop modes - bit_offset: 2 - bit_size: 1 - - name: FLASHSMEN - description: Flash memory interface clocks enable during Sleep and Stop modes - bit_offset: 8 - bit_size: 1 - - name: SRAM1SMEN - description: SRAM1 interface clocks enable during Sleep and Stop modes - bit_offset: 9 - bit_size: 1 - - name: CRCSMEN - description: CRCSMEN - bit_offset: 12 - bit_size: 1 - - name: TSCSMEN - description: Touch Sensing Controller clocks enable during Sleep and Stop modes - bit_offset: 16 - bit_size: 1 - - name: GTZCSMEN - description: GTZCSMEN - bit_offset: 22 - bit_size: 1 - - name: ICACHESMEN - description: ICACHESMEN - bit_offset: 23 - bit_size: 1 + - name: DMA1SMEN + description: DMA1 clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: DMA2SMEN + description: DMA2 clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1SMEN + description: DMAMUX clock enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: FLASHSMEN + description: Flash memory interface clocks enable during Sleep and Stop modes + bit_offset: 8 + bit_size: 1 + - name: SRAM1SMEN + description: SRAM1 interface clocks enable during Sleep and Stop modes + bit_offset: 9 + bit_size: 1 + - name: CRCSMEN + description: CRCSMEN + bit_offset: 12 + bit_size: 1 + - name: TSCSMEN + description: Touch Sensing Controller clocks enable during Sleep and Stop modes + bit_offset: 16 + bit_size: 1 + - name: GTZCSMEN + description: GTZCSMEN + bit_offset: 22 + bit_size: 1 + - name: ICACHESMEN + description: ICACHESMEN + bit_offset: 23 + bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - - name: GPIOAEN - description: IO port A clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: IO port B clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: IO port C clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: IO port D clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: IO port E clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIOFEN - description: IO port F clock enable - bit_offset: 5 - bit_size: 1 - - name: GPIOGEN - description: IO port G clock enable - bit_offset: 6 - bit_size: 1 - - name: GPIOHEN - description: IO port H clock enable - bit_offset: 7 - bit_size: 1 - - name: ADCEN - description: ADC clock enable - bit_offset: 13 - bit_size: 1 - - name: AESEN - description: AES accelerator clock enable - bit_offset: 16 - bit_size: 1 - - name: HASHEN - description: HASH clock enable - bit_offset: 17 - bit_size: 1 - - name: RNGEN - description: Random Number Generator clock enable - bit_offset: 18 - bit_size: 1 - - name: PKAEN - description: PKAEN - bit_offset: 19 - bit_size: 1 - - name: OTFDEC1EN - description: OTFDEC1EN - bit_offset: 21 - bit_size: 1 - - name: SDMMC1EN - description: SDMMC1 clock enable - bit_offset: 22 - bit_size: 1 + - name: GPIOAEN + description: IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: IO port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: IO port E clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: IO port F clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: IO port G clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: IO port H clock enable + bit_offset: 7 + bit_size: 1 + - name: ADCEN + description: ADC clock enable + bit_offset: 13 + bit_size: 1 + - name: AESEN + description: AES accelerator clock enable + bit_offset: 16 + bit_size: 1 + - name: HASHEN + description: HASH clock enable + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: Random Number Generator clock enable + bit_offset: 18 + bit_size: 1 + - name: PKAEN + description: PKAEN + bit_offset: 19 + bit_size: 1 + - name: OTFDEC1EN + description: OTFDEC1EN + bit_offset: 21 + bit_size: 1 + - name: SDMMC1EN + description: SDMMC1 clock enable + bit_offset: 22 + bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - - name: GPIOARST - description: IO port A reset - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: IO port B reset - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: IO port C reset - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: IO port D reset - bit_offset: 3 - bit_size: 1 - - name: GPIOERST - description: IO port E reset - bit_offset: 4 - bit_size: 1 - - name: GPIOFRST - description: IO port F reset - bit_offset: 5 - bit_size: 1 - - name: GPIOGRST - description: IO port G reset - bit_offset: 6 - bit_size: 1 - - name: GPIOHRST - description: IO port H reset - bit_offset: 7 - bit_size: 1 - - name: ADCRST - description: ADC reset - bit_offset: 13 - bit_size: 1 - - name: AESRST - description: AES hardware accelerator reset - bit_offset: 16 - bit_size: 1 - - name: HASHRST - description: Hash reset - bit_offset: 17 - bit_size: 1 - - name: RNGRST - description: Random number generator reset - bit_offset: 18 - bit_size: 1 - - name: PKARST - description: PKARST - bit_offset: 19 - bit_size: 1 - - name: OTFDEC1RST - description: OTFDEC1RST - bit_offset: 21 - bit_size: 1 - - name: SDMMC1RST - description: SDMMC1 reset - bit_offset: 22 - bit_size: 1 + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 6 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 7 + bit_size: 1 + - name: ADCRST + description: ADC reset + bit_offset: 13 + bit_size: 1 + - name: AESRST + description: AES hardware accelerator reset + bit_offset: 16 + bit_size: 1 + - name: HASHRST + description: Hash reset + bit_offset: 17 + bit_size: 1 + - name: RNGRST + description: Random number generator reset + bit_offset: 18 + bit_size: 1 + - name: PKARST + description: PKARST + bit_offset: 19 + bit_size: 1 + - name: OTFDEC1RST + description: OTFDEC1RST + bit_offset: 21 + bit_size: 1 + - name: SDMMC1RST + description: SDMMC1 reset + bit_offset: 22 + bit_size: 1 fieldset/AHB2SECSR: description: RCC AHB2 security status register fields: - - name: GPIOASECF - description: GPIOASECF - bit_offset: 0 - bit_size: 1 - - name: GPIOBSECF - description: GPIOBSECF - bit_offset: 1 - bit_size: 1 - - name: GPIOCSECF - description: GPIOCSECF - bit_offset: 2 - bit_size: 1 - - name: GPIODSECF - description: GPIODSECF - bit_offset: 3 - bit_size: 1 - - name: GPIOESECF - description: GPIOESECF - bit_offset: 4 - bit_size: 1 - - name: GPIOFSECF - description: GPIOFSECF - bit_offset: 5 - bit_size: 1 - - name: GPIOGSECF - description: GPIOGSECF - bit_offset: 6 - bit_size: 1 - - name: GPIOHSECF - description: GPIOHSECF - bit_offset: 7 - bit_size: 1 - - name: SRAM2SECF - description: SRAM2SECF - bit_offset: 9 - bit_size: 1 - - name: OTFDEC1SECF - description: OTFDEC1SECF - bit_offset: 21 - bit_size: 1 - - name: SDMMC1SECF - description: SDMMC1SECF - bit_offset: 22 - bit_size: 1 + - name: GPIOASECF + description: GPIOASECF + bit_offset: 0 + bit_size: 1 + - name: GPIOBSECF + description: GPIOBSECF + bit_offset: 1 + bit_size: 1 + - name: GPIOCSECF + description: GPIOCSECF + bit_offset: 2 + bit_size: 1 + - name: GPIODSECF + description: GPIODSECF + bit_offset: 3 + bit_size: 1 + - name: GPIOESECF + description: GPIOESECF + bit_offset: 4 + bit_size: 1 + - name: GPIOFSECF + description: GPIOFSECF + bit_offset: 5 + bit_size: 1 + - name: GPIOGSECF + description: GPIOGSECF + bit_offset: 6 + bit_size: 1 + - name: GPIOHSECF + description: GPIOHSECF + bit_offset: 7 + bit_size: 1 + - name: SRAM2SECF + description: SRAM2SECF + bit_offset: 9 + bit_size: 1 + - name: OTFDEC1SECF + description: OTFDEC1SECF + bit_offset: 21 + bit_size: 1 + - name: SDMMC1SECF + description: SDMMC1SECF + bit_offset: 22 + bit_size: 1 fieldset/AHB2SMENR: description: AHB2 peripheral clocks enable in Sleep and Stop modes register fields: - - name: GPIOASMEN - description: IO port A clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: GPIOBSMEN - description: IO port B clocks enable during Sleep and Stop modes - bit_offset: 1 - bit_size: 1 - - name: GPIOCSMEN - description: IO port C clocks enable during Sleep and Stop modes - bit_offset: 2 - bit_size: 1 - - name: GPIODSMEN - description: IO port D clocks enable during Sleep and Stop modes - bit_offset: 3 - bit_size: 1 - - name: GPIOESMEN - description: IO port E clocks enable during Sleep and Stop modes - bit_offset: 4 - bit_size: 1 - - name: GPIOFSMEN - description: IO port F clocks enable during Sleep and Stop modes - bit_offset: 5 - bit_size: 1 - - name: GPIOGSMEN - description: IO port G clocks enable during Sleep and Stop modes - bit_offset: 6 - bit_size: 1 - - name: GPIOHSMEN - description: IO port H clocks enable during Sleep and Stop modes - bit_offset: 7 - bit_size: 1 - - name: SRAM2SMEN - description: SRAM2 interface clocks enable during Sleep and Stop modes - bit_offset: 9 - bit_size: 1 - - name: ADCFSSMEN - description: ADC clocks enable during Sleep and Stop modes - bit_offset: 13 - bit_size: 1 - - name: AESSMEN - description: AES accelerator clocks enable during Sleep and Stop modes - bit_offset: 16 - bit_size: 1 - - name: HASHSMEN - description: HASH clock enable during Sleep and Stop modes - bit_offset: 17 - bit_size: 1 - - name: RNGSMEN - description: Random Number Generator clocks enable during Sleep and Stop modes - bit_offset: 18 - bit_size: 1 - - name: PKASMEN - description: PKASMEN - bit_offset: 19 - bit_size: 1 - - name: OTFDEC1SMEN - description: OTFDEC1SMEN - bit_offset: 21 - bit_size: 1 - - name: SDMMC1SMEN - description: SDMMC1 clocks enable during Sleep and Stop modes - bit_offset: 22 - bit_size: 1 + - name: GPIOASMEN + description: IO port A clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: IO port B clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: IO port C clocks enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: GPIODSMEN + description: IO port D clocks enable during Sleep and Stop modes + bit_offset: 3 + bit_size: 1 + - name: GPIOESMEN + description: IO port E clocks enable during Sleep and Stop modes + bit_offset: 4 + bit_size: 1 + - name: GPIOFSMEN + description: IO port F clocks enable during Sleep and Stop modes + bit_offset: 5 + bit_size: 1 + - name: GPIOGSMEN + description: IO port G clocks enable during Sleep and Stop modes + bit_offset: 6 + bit_size: 1 + - name: GPIOHSMEN + description: IO port H clocks enable during Sleep and Stop modes + bit_offset: 7 + bit_size: 1 + - name: SRAM2SMEN + description: SRAM2 interface clocks enable during Sleep and Stop modes + bit_offset: 9 + bit_size: 1 + - name: ADCFSSMEN + description: ADC clocks enable during Sleep and Stop modes + bit_offset: 13 + bit_size: 1 + - name: AESSMEN + description: AES accelerator clocks enable during Sleep and Stop modes + bit_offset: 16 + bit_size: 1 + - name: HASHSMEN + description: HASH clock enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: RNGSMEN + description: Random Number Generator clocks enable during Sleep and Stop modes + bit_offset: 18 + bit_size: 1 + - name: PKASMEN + description: PKASMEN + bit_offset: 19 + bit_size: 1 + - name: OTFDEC1SMEN + description: OTFDEC1SMEN + bit_offset: 21 + bit_size: 1 + - name: SDMMC1SMEN + description: SDMMC1 clocks enable during Sleep and Stop modes + bit_offset: 22 + bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: - - name: FMCEN - description: Flexible memory controller clock enable - bit_offset: 0 - bit_size: 1 - - name: OSPI1EN - description: OSPI1EN - bit_offset: 8 - bit_size: 1 + - name: FMCEN + description: Flexible memory controller clock enable + bit_offset: 0 + bit_size: 1 + - name: OSPI1EN + description: OSPI1EN + bit_offset: 8 + bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - - name: FMCRST - description: Flexible memory controller reset - bit_offset: 0 - bit_size: 1 - - name: OSPI1RST - description: OSPI1RST - bit_offset: 8 - bit_size: 1 + - name: FMCRST + description: Flexible memory controller reset + bit_offset: 0 + bit_size: 1 + - name: OSPI1RST + description: OSPI1RST + bit_offset: 8 + bit_size: 1 fieldset/AHB3SECSR: description: RCC AHB3 security status register fields: - - name: FSMCSECF - description: FSMCSECF - bit_offset: 0 - bit_size: 1 - - name: OSPI1SECF - description: OSPI1SECF - bit_offset: 8 - bit_size: 1 + - name: FSMCSECF + description: FSMCSECF + bit_offset: 0 + bit_size: 1 + - name: OSPI1SECF + description: OSPI1SECF + bit_offset: 8 + bit_size: 1 fieldset/AHB3SMENR: description: AHB3 peripheral clocks enable in Sleep and Stop modes register fields: - - name: FMCSMEN - description: Flexible memory controller clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: OSPI1SMEN - description: OSPI1SMEN - bit_offset: 8 - bit_size: 1 + - name: FMCSMEN + description: Flexible memory controller clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: OSPI1SMEN + description: OSPI1SMEN + bit_offset: 8 + bit_size: 1 fieldset/APB1ENR1: description: APB1ENR1 fields: - - name: TIM2EN - description: TIM2 timer clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: TIM3 timer clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: TIM4 timer clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: TIM5 timer clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: TIM6 timer clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: TIM7 timer clock enable - bit_offset: 5 - bit_size: 1 - - name: RTCAPBEN - description: RTC APB clock enable - bit_offset: 10 - bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI2 clock enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI3 clock enable - bit_offset: 15 - bit_size: 1 - - name: USART2EN - description: USART2 clock enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART3 clock enable - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: UART4 clock enable - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: UART5 clock enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C2 clock enable - bit_offset: 22 - bit_size: 1 - - name: I2C3EN - description: I2C3 clock enable - bit_offset: 23 - bit_size: 1 - - name: CRSEN - description: Clock Recovery System clock enable - bit_offset: 24 - bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - - name: DAC1EN - description: DAC1 interface clock enable - bit_offset: 29 - bit_size: 1 - - name: OPAMPEN - description: OPAMP interface clock enable - bit_offset: 30 - bit_size: 1 - - name: LPTIM1EN - description: Low power timer 1 clock enable - bit_offset: 31 - bit_size: 1 + - name: TIM2EN + description: TIM2 timer clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM3 timer clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM4 timer clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: TIM5 timer clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM6 timer clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM7 timer clock enable + bit_offset: 5 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 23 + bit_size: 1 + - name: CRSEN + description: Clock Recovery System clock enable + bit_offset: 24 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DAC1EN + description: DAC1 interface clock enable + bit_offset: 29 + bit_size: 1 + - name: OPAMPEN + description: OPAMP interface clock enable + bit_offset: 30 + bit_size: 1 + - name: LPTIM1EN + description: Low power timer 1 clock enable + bit_offset: 31 + bit_size: 1 fieldset/APB1ENR2: description: APB1 peripheral clock enable register 2 fields: - - name: LPUART1EN - description: Low power UART 1 clock enable - bit_offset: 0 - bit_size: 1 - - name: I2C4EN - description: I2C4 clock enable - bit_offset: 1 - bit_size: 1 - - name: LPTIM2EN - description: LPTIM2EN - bit_offset: 5 - bit_size: 1 - - name: LPTIM3EN - description: LPTIM3EN - bit_offset: 6 - bit_size: 1 - - name: FDCAN1EN - description: FDCAN1EN - bit_offset: 9 - bit_size: 1 - - name: USBEN - description: USBEN - bit_offset: 21 - bit_size: 1 - - name: UCPD1EN - description: UCPD1EN - bit_offset: 23 - bit_size: 1 + - name: LPUART1EN + description: Low power UART 1 clock enable + bit_offset: 0 + bit_size: 1 + - name: I2C4EN + description: I2C4 clock enable + bit_offset: 1 + bit_size: 1 + - name: LPTIM2EN + description: LPTIM2EN + bit_offset: 5 + bit_size: 1 + - name: LPTIM3EN + description: LPTIM3EN + bit_offset: 6 + bit_size: 1 + - name: FDCAN1EN + description: FDCAN1EN + bit_offset: 9 + bit_size: 1 + - name: USBEN + description: USBEN + bit_offset: 21 + bit_size: 1 + - name: UCPD1EN + description: UCPD1EN + bit_offset: 23 + bit_size: 1 fieldset/APB1RSTR1: description: APB1 peripheral reset register 1 fields: - - name: TIM2RST - description: TIM2 timer reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: TIM3 timer reset - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: TIM3 timer reset - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: TIM5 timer reset - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: TIM6 timer reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: TIM7 timer reset - bit_offset: 5 - bit_size: 1 - - name: SPI2RST - description: SPI2 reset - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: SPI3 reset - bit_offset: 15 - bit_size: 1 - - name: USART2RST - description: USART2 reset - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: USART3 reset - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: UART4 reset - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: UART5 reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C2 reset - bit_offset: 22 - bit_size: 1 - - name: I2C3RST - description: I2C3 reset - bit_offset: 23 - bit_size: 1 - - name: CRSRST - description: CRS reset - bit_offset: 24 - bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - - name: DAC1RST - description: DAC1 interface reset - bit_offset: 29 - bit_size: 1 - - name: OPAMPRST - description: OPAMP interface reset - bit_offset: 30 - bit_size: 1 - - name: LPTIM1RST - description: Low Power Timer 1 reset - bit_offset: 31 - bit_size: 1 + - name: TIM2RST + description: TIM2 timer reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: TIM3 timer reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: TIM3 timer reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: TIM5 timer reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: TIM6 timer reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM7 timer reset + bit_offset: 5 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: UART4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: UART5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 23 + bit_size: 1 + - name: CRSRST + description: CRS reset + bit_offset: 24 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DAC1RST + description: DAC1 interface reset + bit_offset: 29 + bit_size: 1 + - name: OPAMPRST + description: OPAMP interface reset + bit_offset: 30 + bit_size: 1 + - name: LPTIM1RST + description: Low Power Timer 1 reset + bit_offset: 31 + bit_size: 1 fieldset/APB1RSTR2: description: APB1 peripheral reset register 2 fields: - - name: LPUART1RST - description: Low-power UART 1 reset - bit_offset: 0 - bit_size: 1 - - name: I2C4RST - description: I2C4 reset - bit_offset: 1 - bit_size: 1 - - name: LPTIM2RST - description: Low-power timer 2 reset - bit_offset: 5 - bit_size: 1 - - name: LPTIM3RST - description: LPTIM3RST - bit_offset: 6 - bit_size: 1 - - name: FDCAN1RST - description: FDCAN1RST - bit_offset: 9 - bit_size: 1 - - name: USBRST - description: USBRST - bit_offset: 21 - bit_size: 1 - - name: UCPD1RST - description: UCPD1RST - bit_offset: 23 - bit_size: 1 + - name: LPUART1RST + description: Low-power UART 1 reset + bit_offset: 0 + bit_size: 1 + - name: I2C4RST + description: I2C4 reset + bit_offset: 1 + bit_size: 1 + - name: LPTIM2RST + description: Low-power timer 2 reset + bit_offset: 5 + bit_size: 1 + - name: LPTIM3RST + description: LPTIM3RST + bit_offset: 6 + bit_size: 1 + - name: FDCAN1RST + description: FDCAN1RST + bit_offset: 9 + bit_size: 1 + - name: USBRST + description: USBRST + bit_offset: 21 + bit_size: 1 + - name: UCPD1RST + description: UCPD1RST + bit_offset: 23 + bit_size: 1 fieldset/APB1SECSR1: description: RCC APB1 security status register 1 fields: - - name: TIM2SECF - description: TIM2SECF - bit_offset: 0 - bit_size: 1 - - name: TIM3SECF - description: TIM3SECF - bit_offset: 1 - bit_size: 1 - - name: TIM4SECF - description: TIM4SECF - bit_offset: 2 - bit_size: 1 - - name: TIM5SECF - description: TIM5SECF - bit_offset: 3 - bit_size: 1 - - name: TIM6SECF - description: TIM6SECF - bit_offset: 4 - bit_size: 1 - - name: TIM7SECF - description: TIM7SECF - bit_offset: 5 - bit_size: 1 - - name: RTCAPBSECF - description: RTCAPBSECF - bit_offset: 10 - bit_size: 1 - - name: WWDGSECF - description: WWDGSECF - bit_offset: 11 - bit_size: 1 - - name: SPI2SECF - description: SPI2SECF - bit_offset: 14 - bit_size: 1 - - name: SPI3SECF - description: SPI3SECF - bit_offset: 15 - bit_size: 1 - - name: UART2SECF - description: UART2SECF - bit_offset: 17 - bit_size: 1 - - name: UART3SECF - description: UART3SECF - bit_offset: 18 - bit_size: 1 - - name: UART4SECF - description: UART4SECF - bit_offset: 19 - bit_size: 1 - - name: UART5SECF - description: UART5SECF - bit_offset: 20 - bit_size: 1 - - name: I2C1SECF - description: I2C1SECF - bit_offset: 21 - bit_size: 1 - - name: I2C2SECF - description: I2C2SECF - bit_offset: 22 - bit_size: 1 - - name: I2C3SECF - description: I2C3SECF - bit_offset: 23 - bit_size: 1 - - name: CRSSECF - description: CRSSECF - bit_offset: 24 - bit_size: 1 - - name: PWRSECF - description: PWRSECF - bit_offset: 28 - bit_size: 1 - - name: DACSECF - description: DACSECF - bit_offset: 29 - bit_size: 1 - - name: OPAMPSECF - description: OPAMPSECF - bit_offset: 30 - bit_size: 1 - - name: LPTIM1SECF - description: LPTIM1SECF - bit_offset: 31 - bit_size: 1 + - name: TIM2SECF + description: TIM2SECF + bit_offset: 0 + bit_size: 1 + - name: TIM3SECF + description: TIM3SECF + bit_offset: 1 + bit_size: 1 + - name: TIM4SECF + description: TIM4SECF + bit_offset: 2 + bit_size: 1 + - name: TIM5SECF + description: TIM5SECF + bit_offset: 3 + bit_size: 1 + - name: TIM6SECF + description: TIM6SECF + bit_offset: 4 + bit_size: 1 + - name: TIM7SECF + description: TIM7SECF + bit_offset: 5 + bit_size: 1 + - name: RTCAPBSECF + description: RTCAPBSECF + bit_offset: 10 + bit_size: 1 + - name: WWDGSECF + description: WWDGSECF + bit_offset: 11 + bit_size: 1 + - name: SPI2SECF + description: SPI2SECF + bit_offset: 14 + bit_size: 1 + - name: SPI3SECF + description: SPI3SECF + bit_offset: 15 + bit_size: 1 + - name: UART2SECF + description: UART2SECF + bit_offset: 17 + bit_size: 1 + - name: UART3SECF + description: UART3SECF + bit_offset: 18 + bit_size: 1 + - name: UART4SECF + description: UART4SECF + bit_offset: 19 + bit_size: 1 + - name: UART5SECF + description: UART5SECF + bit_offset: 20 + bit_size: 1 + - name: I2C1SECF + description: I2C1SECF + bit_offset: 21 + bit_size: 1 + - name: I2C2SECF + description: I2C2SECF + bit_offset: 22 + bit_size: 1 + - name: I2C3SECF + description: I2C3SECF + bit_offset: 23 + bit_size: 1 + - name: CRSSECF + description: CRSSECF + bit_offset: 24 + bit_size: 1 + - name: PWRSECF + description: PWRSECF + bit_offset: 28 + bit_size: 1 + - name: DACSECF + description: DACSECF + bit_offset: 29 + bit_size: 1 + - name: OPAMPSECF + description: OPAMPSECF + bit_offset: 30 + bit_size: 1 + - name: LPTIM1SECF + description: LPTIM1SECF + bit_offset: 31 + bit_size: 1 fieldset/APB1SECSR2: description: RCC APB1 security status register 2 fields: - - name: LPUART1SECF - description: LPUART1SECF - bit_offset: 0 - bit_size: 1 - - name: I2C4SECF - description: I2C4SECF - bit_offset: 1 - bit_size: 1 - - name: LPTIM2SECF - description: LPTIM2SECF - bit_offset: 5 - bit_size: 1 - - name: LPTIM3SECF - description: LPTIM3SECF - bit_offset: 6 - bit_size: 1 - - name: FDCAN1SECF - description: FDCAN1SECF - bit_offset: 9 - bit_size: 1 - - name: USBSECF - description: USBSECF - bit_offset: 21 - bit_size: 1 - - name: UCPD1SECF - description: UCPD1SECF - bit_offset: 23 - bit_size: 1 + - name: LPUART1SECF + description: LPUART1SECF + bit_offset: 0 + bit_size: 1 + - name: I2C4SECF + description: I2C4SECF + bit_offset: 1 + bit_size: 1 + - name: LPTIM2SECF + description: LPTIM2SECF + bit_offset: 5 + bit_size: 1 + - name: LPTIM3SECF + description: LPTIM3SECF + bit_offset: 6 + bit_size: 1 + - name: FDCAN1SECF + description: FDCAN1SECF + bit_offset: 9 + bit_size: 1 + - name: USBSECF + description: USBSECF + bit_offset: 21 + bit_size: 1 + - name: UCPD1SECF + description: UCPD1SECF + bit_offset: 23 + bit_size: 1 fieldset/APB1SMENR1: description: APB1SMENR1 fields: - - name: TIM2SMEN - description: TIM2 timer clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: TIM3SMEN - description: TIM3 timer clocks enable during Sleep and Stop modes - bit_offset: 1 - bit_size: 1 - - name: TIM4SMEN - description: TIM4 timer clocks enable during Sleep and Stop modes - bit_offset: 2 - bit_size: 1 - - name: TIM5SMEN - description: TIM5 timer clocks enable during Sleep and Stop modes - bit_offset: 3 - bit_size: 1 - - name: TIM6SMEN - description: TIM6 timer clocks enable during Sleep and Stop modes - bit_offset: 4 - bit_size: 1 - - name: TIM7SMEN - description: TIM7 timer clocks enable during Sleep and Stop modes - bit_offset: 5 - bit_size: 1 - - name: RTCAPBSMEN - description: RTC APB clock enable during Sleep and Stop modes - bit_offset: 10 - bit_size: 1 - - name: WWDGSMEN - description: Window watchdog clocks enable during Sleep and Stop modes - bit_offset: 11 - bit_size: 1 - - name: SPI2SMEN - description: SPI2 clocks enable during Sleep and Stop modes - bit_offset: 14 - bit_size: 1 - - name: SP3SMEN - description: SPI3 clocks enable during Sleep and Stop modes - bit_offset: 15 - bit_size: 1 - - name: USART2SMEN - description: USART2 clocks enable during Sleep and Stop modes - bit_offset: 17 - bit_size: 1 - - name: USART3SMEN - description: USART3 clocks enable during Sleep and Stop modes - bit_offset: 18 - bit_size: 1 - - name: UART4SMEN - description: UART4 clocks enable during Sleep and Stop modes - bit_offset: 19 - bit_size: 1 - - name: UART5SMEN - description: UART5 clocks enable during Sleep and Stop modes - bit_offset: 20 - bit_size: 1 - - name: I2C1SMEN - description: I2C1 clocks enable during Sleep and Stop modes - bit_offset: 21 - bit_size: 1 - - name: I2C2SMEN - description: I2C2 clocks enable during Sleep and Stop modes - bit_offset: 22 - bit_size: 1 - - name: I2C3SMEN - description: I2C3 clocks enable during Sleep and Stop modes - bit_offset: 23 - bit_size: 1 - - name: CRSSMEN - description: CRS clock enable during Sleep and Stop modes - bit_offset: 24 - bit_size: 1 - - name: PWRSMEN - description: Power interface clocks enable during Sleep and Stop modes - bit_offset: 28 - bit_size: 1 - - name: DAC1SMEN - description: DAC1 interface clocks enable during Sleep and Stop modes - bit_offset: 29 - bit_size: 1 - - name: OPAMPSMEN - description: OPAMP interface clocks enable during Sleep and Stop modes - bit_offset: 30 - bit_size: 1 - - name: LPTIM1SMEN - description: Low power timer 1 clocks enable during Sleep and Stop modes - bit_offset: 31 - bit_size: 1 + - name: TIM2SMEN + description: TIM2 timer clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: TIM3SMEN + description: TIM3 timer clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: TIM4SMEN + description: TIM4 timer clocks enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: TIM5SMEN + description: TIM5 timer clocks enable during Sleep and Stop modes + bit_offset: 3 + bit_size: 1 + - name: TIM6SMEN + description: TIM6 timer clocks enable during Sleep and Stop modes + bit_offset: 4 + bit_size: 1 + - name: TIM7SMEN + description: TIM7 timer clocks enable during Sleep and Stop modes + bit_offset: 5 + bit_size: 1 + - name: RTCAPBSMEN + description: RTC APB clock enable during Sleep and Stop modes + bit_offset: 10 + bit_size: 1 + - name: WWDGSMEN + description: Window watchdog clocks enable during Sleep and Stop modes + bit_offset: 11 + bit_size: 1 + - name: SPI2SMEN + description: SPI2 clocks enable during Sleep and Stop modes + bit_offset: 14 + bit_size: 1 + - name: SP3SMEN + description: SPI3 clocks enable during Sleep and Stop modes + bit_offset: 15 + bit_size: 1 + - name: USART2SMEN + description: USART2 clocks enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: USART3SMEN + description: USART3 clocks enable during Sleep and Stop modes + bit_offset: 18 + bit_size: 1 + - name: UART4SMEN + description: UART4 clocks enable during Sleep and Stop modes + bit_offset: 19 + bit_size: 1 + - name: UART5SMEN + description: UART5 clocks enable during Sleep and Stop modes + bit_offset: 20 + bit_size: 1 + - name: I2C1SMEN + description: I2C1 clocks enable during Sleep and Stop modes + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: I2C2 clocks enable during Sleep and Stop modes + bit_offset: 22 + bit_size: 1 + - name: I2C3SMEN + description: I2C3 clocks enable during Sleep and Stop modes + bit_offset: 23 + bit_size: 1 + - name: CRSSMEN + description: CRS clock enable during Sleep and Stop modes + bit_offset: 24 + bit_size: 1 + - name: PWRSMEN + description: Power interface clocks enable during Sleep and Stop modes + bit_offset: 28 + bit_size: 1 + - name: DAC1SMEN + description: DAC1 interface clocks enable during Sleep and Stop modes + bit_offset: 29 + bit_size: 1 + - name: OPAMPSMEN + description: OPAMP interface clocks enable during Sleep and Stop modes + bit_offset: 30 + bit_size: 1 + - name: LPTIM1SMEN + description: Low power timer 1 clocks enable during Sleep and Stop modes + bit_offset: 31 + bit_size: 1 fieldset/APB1SMENR2: description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 fields: - - name: LPUART1SMEN - description: Low power UART 1 clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: I2C4SMEN - description: I2C4 clocks enable during Sleep and Stop modes - bit_offset: 1 - bit_size: 1 - - name: LPTIM2SMEN - description: LPTIM2SMEN - bit_offset: 5 - bit_size: 1 - - name: LPTIM3SMEN - description: LPTIM3SMEN - bit_offset: 6 - bit_size: 1 - - name: FDCAN1SMEN - description: FDCAN1SMEN - bit_offset: 9 - bit_size: 1 - - name: USBSMEN - description: USBSMEN - bit_offset: 21 - bit_size: 1 - - name: UCPD1SMEN - description: UCPD1SMEN - bit_offset: 23 - bit_size: 1 + - name: LPUART1SMEN + description: Low power UART 1 clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: I2C4SMEN + description: I2C4 clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: LPTIM2SMEN + description: LPTIM2SMEN + bit_offset: 5 + bit_size: 1 + - name: LPTIM3SMEN + description: LPTIM3SMEN + bit_offset: 6 + bit_size: 1 + - name: FDCAN1SMEN + description: FDCAN1SMEN + bit_offset: 9 + bit_size: 1 + - name: USBSMEN + description: USBSMEN + bit_offset: 21 + bit_size: 1 + - name: UCPD1SMEN + description: UCPD1SMEN + bit_offset: 23 + bit_size: 1 fieldset/APB2ENR: description: APB2ENR fields: - - name: SYSCFGEN - description: SYSCFG clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM1EN - description: TIM1 timer clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: SPI1 clock enable - bit_offset: 12 - bit_size: 1 - - name: TIM8EN - description: TIM8 timer clock enable - bit_offset: 13 - bit_size: 1 - - name: USART1EN - description: USART1clock enable - bit_offset: 14 - bit_size: 1 - - name: TIM15EN - description: TIM15 timer clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: TIM16 timer clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: TIM17 timer clock enable - bit_offset: 18 - bit_size: 1 - - name: SAI1EN - description: SAI1 clock enable - bit_offset: 21 - bit_size: 1 - - name: SAI2EN - description: SAI2 clock enable - bit_offset: 22 - bit_size: 1 - - name: DFSDM1EN - description: DFSDM timer clock enable - bit_offset: 24 - bit_size: 1 + - name: SYSCFGEN + description: SYSCFG clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM1EN + description: TIM1 timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: TIM8EN + description: TIM8 timer clock enable + bit_offset: 13 + bit_size: 1 + - name: USART1EN + description: USART1clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM15EN + description: TIM15 timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: SAI1EN + description: SAI1 clock enable + bit_offset: 21 + bit_size: 1 + - name: SAI2EN + description: SAI2 clock enable + bit_offset: 22 + bit_size: 1 + - name: DFSDM1EN + description: DFSDM timer clock enable + bit_offset: 24 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - - name: SYSCFGRST - description: System configuration (SYSCFG) reset - bit_offset: 0 - bit_size: 1 - - name: TIM1RST - description: TIM1 timer reset - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: SPI1 reset - bit_offset: 12 - bit_size: 1 - - name: TIM8RST - description: TIM8 timer reset - bit_offset: 13 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 14 - bit_size: 1 - - name: TIM15RST - description: TIM15 timer reset - bit_offset: 16 - bit_size: 1 - - name: TIM16RST - description: TIM16 timer reset - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: TIM17 timer reset - bit_offset: 18 - bit_size: 1 - - name: SAI1RST - description: Serial audio interface 1 (SAI1) reset - bit_offset: 21 - bit_size: 1 - - name: SAI2RST - description: Serial audio interface 2 (SAI2) reset - bit_offset: 22 - bit_size: 1 - - name: DFSDM1RST - description: Digital filters for sigma-delata modulators (DFSDM) reset - bit_offset: 24 - bit_size: 1 + - name: SYSCFGRST + description: System configuration (SYSCFG) reset + bit_offset: 0 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI1 reset + bit_offset: 12 + bit_size: 1 + - name: TIM8RST + description: TIM8 timer reset + bit_offset: 13 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: SAI1RST + description: Serial audio interface 1 (SAI1) reset + bit_offset: 21 + bit_size: 1 + - name: SAI2RST + description: Serial audio interface 2 (SAI2) reset + bit_offset: 22 + bit_size: 1 + - name: DFSDM1RST + description: Digital filters for sigma-delata modulators (DFSDM) reset + bit_offset: 24 + bit_size: 1 fieldset/APB2SECSR: description: RCC APB2 security status register fields: - - name: SYSCFGSECF - description: SYSCFGSECF - bit_offset: 0 - bit_size: 1 - - name: TIM1SECF - description: TIM1SECF - bit_offset: 11 - bit_size: 1 - - name: SPI1SECF - description: SPI1SECF - bit_offset: 12 - bit_size: 1 - - name: TIM8SECF - description: TIM8SECF - bit_offset: 13 - bit_size: 1 - - name: USART1SECF - description: USART1SECF - bit_offset: 14 - bit_size: 1 - - name: TIM15SECF - description: TIM15SECF - bit_offset: 16 - bit_size: 1 - - name: TIM16SECF - description: TIM16SECF - bit_offset: 17 - bit_size: 1 - - name: TIM17SECF - description: TIM17SECF - bit_offset: 18 - bit_size: 1 - - name: SAI1SECF - description: SAI1SECF - bit_offset: 21 - bit_size: 1 - - name: SAI2SECF - description: SAI2SECF - bit_offset: 22 - bit_size: 1 - - name: DFSDM1SECF - description: DFSDM1SECF - bit_offset: 24 - bit_size: 1 + - name: SYSCFGSECF + description: SYSCFGSECF + bit_offset: 0 + bit_size: 1 + - name: TIM1SECF + description: TIM1SECF + bit_offset: 11 + bit_size: 1 + - name: SPI1SECF + description: SPI1SECF + bit_offset: 12 + bit_size: 1 + - name: TIM8SECF + description: TIM8SECF + bit_offset: 13 + bit_size: 1 + - name: USART1SECF + description: USART1SECF + bit_offset: 14 + bit_size: 1 + - name: TIM15SECF + description: TIM15SECF + bit_offset: 16 + bit_size: 1 + - name: TIM16SECF + description: TIM16SECF + bit_offset: 17 + bit_size: 1 + - name: TIM17SECF + description: TIM17SECF + bit_offset: 18 + bit_size: 1 + - name: SAI1SECF + description: SAI1SECF + bit_offset: 21 + bit_size: 1 + - name: SAI2SECF + description: SAI2SECF + bit_offset: 22 + bit_size: 1 + - name: DFSDM1SECF + description: DFSDM1SECF + bit_offset: 24 + bit_size: 1 fieldset/APB2SMENR: description: APB2SMENR fields: - - name: SYSCFGSMEN - description: SYSCFG clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: TIM1SMEN - description: TIM1 timer clocks enable during Sleep and Stop modes - bit_offset: 11 - bit_size: 1 - - name: SPI1SMEN - description: SPI1 clocks enable during Sleep and Stop modes - bit_offset: 12 - bit_size: 1 - - name: TIM8SMEN - description: TIM8 timer clocks enable during Sleep and Stop modes - bit_offset: 13 - bit_size: 1 - - name: USART1SMEN - description: USART1clocks enable during Sleep and Stop modes - bit_offset: 14 - bit_size: 1 - - name: TIM15SMEN - description: TIM15 timer clocks enable during Sleep and Stop modes - bit_offset: 16 - bit_size: 1 - - name: TIM16SMEN - description: TIM16 timer clocks enable during Sleep and Stop modes - bit_offset: 17 - bit_size: 1 - - name: TIM17SMEN - description: TIM17 timer clocks enable during Sleep and Stop modes - bit_offset: 18 - bit_size: 1 - - name: SAI1SMEN - description: SAI1 clocks enable during Sleep and Stop modes - bit_offset: 21 - bit_size: 1 - - name: SAI2SMEN - description: SAI2 clocks enable during Sleep and Stop modes - bit_offset: 22 - bit_size: 1 - - name: DFSDM1SMEN - description: DFSDM timer clocks enable during Sleep and Stop modes - bit_offset: 24 - bit_size: 1 + - name: SYSCFGSMEN + description: SYSCFG clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: TIM1SMEN + description: TIM1 timer clocks enable during Sleep and Stop modes + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: SPI1 clocks enable during Sleep and Stop modes + bit_offset: 12 + bit_size: 1 + - name: TIM8SMEN + description: TIM8 timer clocks enable during Sleep and Stop modes + bit_offset: 13 + bit_size: 1 + - name: USART1SMEN + description: USART1clocks enable during Sleep and Stop modes + bit_offset: 14 + bit_size: 1 + - name: TIM15SMEN + description: TIM15 timer clocks enable during Sleep and Stop modes + bit_offset: 16 + bit_size: 1 + - name: TIM16SMEN + description: TIM16 timer clocks enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: TIM17 timer clocks enable during Sleep and Stop modes + bit_offset: 18 + bit_size: 1 + - name: SAI1SMEN + description: SAI1 clocks enable during Sleep and Stop modes + bit_offset: 21 + bit_size: 1 + - name: SAI2SMEN + description: SAI2 clocks enable during Sleep and Stop modes + bit_offset: 22 + bit_size: 1 + - name: DFSDM1SMEN + description: DFSDM timer clocks enable during Sleep and Stop modes + bit_offset: 24 + bit_size: 1 fieldset/BDCR: description: BDCR fields: - - name: LSEON - description: LSE oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: LSE oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: LSE oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: LSEDRV - description: SE oscillator drive capability - bit_offset: 3 - bit_size: 2 - enum: LSEDRV - - name: LSECSSON - description: LSECSSON - bit_offset: 5 - bit_size: 1 - - name: LSECSSD - description: LSECSSD - bit_offset: 6 - bit_size: 1 - - name: LSESYSEN - description: LSESYSEN - bit_offset: 7 - bit_size: 1 - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: LSESYSRDY - description: LSESYSRDY - bit_offset: 11 - bit_size: 1 - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: Backup domain software reset - bit_offset: 16 - bit_size: 1 - - name: LSCOEN - description: Low speed clock output enable - bit_offset: 24 - bit_size: 1 - - name: LSCOSEL - description: Low speed clock output selection - bit_offset: 25 - bit_size: 1 - enum: LSCOSEL + - name: LSEON + description: LSE oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: LSE oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: LSE oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: SE oscillator drive capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: LSECSSON + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: LSECSSD + bit_offset: 6 + bit_size: 1 + - name: LSESYSEN + description: LSESYSEN + bit_offset: 7 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: LSESYSRDY + description: LSESYSRDY + bit_offset: 11 + bit_size: 1 + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: Low speed clock output enable + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: Low speed clock output selection + bit_offset: 25 + bit_size: 1 + enum: LSCOSEL fieldset/CCIPR1: description: CCIPR1 fields: - - name: USART1SEL - description: USART1 clock source selection - bit_offset: 0 - bit_size: 2 - - name: USART2SEL - description: USART2 clock source selection - bit_offset: 2 - bit_size: 2 - - name: USART3SEL - description: USART3 clock source selection - bit_offset: 4 - bit_size: 2 - - name: UART4SEL - description: UART4 clock source selection - bit_offset: 6 - bit_size: 2 - - name: UART5SEL - description: UART5 clock source selection - bit_offset: 8 - bit_size: 2 - - name: LPUART1SEL - description: LPUART1 clock source selection - bit_offset: 10 - bit_size: 2 - - name: I2C1SEL - description: I2C1 clock source selection - bit_offset: 12 - bit_size: 2 - - name: I2C2SEL - description: I2C2 clock source selection - bit_offset: 14 - bit_size: 2 - - name: I2C3SEL - description: I2C3 clock source selection - bit_offset: 16 - bit_size: 2 - - name: LPTIM1SEL - description: Low power timer 1 clock source selection - bit_offset: 18 - bit_size: 2 - - name: LPTIM2SEL - description: Low power timer 2 clock source selection - bit_offset: 20 - bit_size: 2 - - name: LPTIM3SEL - description: Low-power timer 3 clock source selection - bit_offset: 22 - bit_size: 2 - - name: FDCANSEL - description: FDCAN clock source selection - bit_offset: 24 - bit_size: 2 - - name: CLK48MSEL - description: 48 MHz clock source selection - bit_offset: 26 - bit_size: 2 - - name: ADCSEL - description: ADCs clock source selection - bit_offset: 28 - bit_size: 2 + - name: USART1SEL + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + - name: USART2SEL + description: USART2 clock source selection + bit_offset: 2 + bit_size: 2 + - name: USART3SEL + description: USART3 clock source selection + bit_offset: 4 + bit_size: 2 + - name: UART4SEL + description: UART4 clock source selection + bit_offset: 6 + bit_size: 2 + - name: UART5SEL + description: UART5 clock source selection + bit_offset: 8 + bit_size: 2 + - name: LPUART1SEL + description: LPUART1 clock source selection + bit_offset: 10 + bit_size: 2 + - name: I2C1SEL + description: I2C1 clock source selection + bit_offset: 12 + bit_size: 2 + - name: I2C2SEL + description: I2C2 clock source selection + bit_offset: 14 + bit_size: 2 + - name: I2C3SEL + description: I2C3 clock source selection + bit_offset: 16 + bit_size: 2 + - name: LPTIM1SEL + description: Low power timer 1 clock source selection + bit_offset: 18 + bit_size: 2 + - name: LPTIM2SEL + description: Low power timer 2 clock source selection + bit_offset: 20 + bit_size: 2 + - name: LPTIM3SEL + description: Low-power timer 3 clock source selection + bit_offset: 22 + bit_size: 2 + - name: FDCANSEL + description: FDCAN clock source selection + bit_offset: 24 + bit_size: 2 + - name: CLK48MSEL + description: 48 MHz clock source selection + bit_offset: 26 + bit_size: 2 + - name: ADCSEL + description: ADCs clock source selection + bit_offset: 28 + bit_size: 2 fieldset/CCIPR2: description: Peripherals independent clock configuration register fields: - - name: I2C4SEL - description: I2C4 clock source selection - bit_offset: 0 - bit_size: 2 - - name: DFSDMSEL - description: Digital filter for sigma delta modulator kernel clock source selection - bit_offset: 2 - bit_size: 1 - - name: ADFSDMSEL - description: Digital filter for sigma delta modulator audio clock source selection - bit_offset: 3 - bit_size: 2 - - name: SAI1SEL - description: SAI1 clock source selection - bit_offset: 5 - bit_size: 3 - - name: SAI2SEL - description: SAI2 clock source selection - bit_offset: 8 - bit_size: 3 - - name: SDMMCSEL - description: SDMMC clock selection - bit_offset: 14 - bit_size: 1 - - name: OSPISEL - description: Octospi clock source selection - bit_offset: 20 - bit_size: 2 + - name: I2C4SEL + description: I2C4 clock source selection + bit_offset: 0 + bit_size: 2 + - name: DFSDMSEL + description: Digital filter for sigma delta modulator kernel clock source selection + bit_offset: 2 + bit_size: 1 + - name: ADFSDMSEL + description: Digital filter for sigma delta modulator audio clock source selection + bit_offset: 3 + bit_size: 2 + - name: SAI1SEL + description: SAI1 clock source selection + bit_offset: 5 + bit_size: 3 + - name: SAI2SEL + description: SAI2 clock source selection + bit_offset: 8 + bit_size: 3 + - name: SDMMCSEL + description: SDMMC clock selection + bit_offset: 14 + bit_size: 1 + - name: OSPISEL + description: Octospi clock source selection + bit_offset: 20 + bit_size: 2 fieldset/CFGR: description: Clock configuration register fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: System clock switch status - bit_offset: 2 - bit_size: 2 - enum: SW - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - enum: HPRE - - name: PPRE1 - description: APB low-speed prescaler (APB1) - bit_offset: 8 - bit_size: 3 - enum: PPRE - - name: PPRE2 - description: APB high-speed prescaler (APB2) - bit_offset: 11 - bit_size: 3 - enum: PPRE - - name: STOPWUCK - description: Wakeup from Stop and CSS backup clock selection - bit_offset: 15 - bit_size: 1 - enum: STOPWUCK - - name: MCOSEL - description: Microcontroller clock output selection - bit_offset: 24 - bit_size: 4 - enum: MCOSEL - - name: MCOPRE - description: Microcontroller clock output prescaler - bit_offset: 28 - bit_size: 3 - enum: MCOPRE + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB low-speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high-speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: STOPWUCK + description: Wakeup from Stop and CSS backup clock selection + bit_offset: 15 + bit_size: 1 + enum: STOPWUCK + - name: MCOSEL + description: Microcontroller clock output selection + bit_offset: 24 + bit_size: 4 + enum: MCOSEL + - name: MCOPRE + description: Microcontroller clock output prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: - - name: LSIRDYC - description: LSI ready interrupt clear - bit_offset: 0 - bit_size: 1 - - name: LSERDYC - description: LSE ready interrupt clear - bit_offset: 1 - bit_size: 1 - - name: MSIRDYC - description: MSI ready interrupt clear - bit_offset: 2 - bit_size: 1 - - name: HSIRDYC - description: HSI ready interrupt clear - bit_offset: 3 - bit_size: 1 - - name: HSERDYC - description: HSE ready interrupt clear - bit_offset: 4 - bit_size: 1 - - name: PLLRDYC - description: PLL ready interrupt clear - bit_offset: 5 - bit_size: 1 - - name: PLLSAI1RDYC - description: PLLSAI1 ready interrupt clear - bit_offset: 6 - bit_size: 1 - - name: PLLSAI2RDYC - description: PLLSAI2 ready interrupt clear - bit_offset: 7 - bit_size: 1 - - name: CSSC - description: Clock security system interrupt clear - bit_offset: 8 - bit_size: 1 - - name: LSECSSC - description: LSE Clock security system interrupt clear - bit_offset: 9 - bit_size: 1 - - name: HSI48RDYC - description: HSI48 oscillator ready interrupt clear - bit_offset: 10 - bit_size: 1 + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 1 + bit_size: 1 + - name: MSIRDYC + description: MSI ready interrupt clear + bit_offset: 2 + bit_size: 1 + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 4 + bit_size: 1 + - name: PLLRDYC + description: PLL ready interrupt clear + bit_offset: 5 + bit_size: 1 + - name: PLLSAI1RDYC + description: PLLSAI1 ready interrupt clear + bit_offset: 6 + bit_size: 1 + - name: PLLSAI2RDYC + description: PLLSAI2 ready interrupt clear + bit_offset: 7 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 8 + bit_size: 1 + - name: LSECSSC + description: LSE Clock security system interrupt clear + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYC + description: HSI48 oscillator ready interrupt clear + bit_offset: 10 + bit_size: 1 fieldset/CIER: description: Clock interrupt enable register fields: - - name: LSIRDYIE - description: LSI ready interrupt enable - bit_offset: 0 - bit_size: 1 - - name: LSERDYIE - description: LSE ready interrupt enable - bit_offset: 1 - bit_size: 1 - - name: MSIRDYIE - description: MSI ready interrupt enable - bit_offset: 2 - bit_size: 1 - - name: HSIRDYIE - description: HSI ready interrupt enable - bit_offset: 3 - bit_size: 1 - - name: HSERDYIE - description: HSE ready interrupt enable - bit_offset: 4 - bit_size: 1 - - name: PLLRDYIE - description: PLL ready interrupt enable - bit_offset: 5 - bit_size: 1 - - name: PLLSAI1RDYIE - description: PLLSAI1 ready interrupt enable - bit_offset: 6 - bit_size: 1 - - name: PLLSAI2RDYIE - description: PLLSAI2 ready interrupt enable - bit_offset: 7 - bit_size: 1 - - name: LSECSSIE - description: LSE clock security system interrupt enable - bit_offset: 9 - bit_size: 1 - - name: HSI48RDYIE - description: HSI48 ready interrupt enable - bit_offset: 10 - bit_size: 1 + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 1 + bit_size: 1 + - name: MSIRDYIE + description: MSI ready interrupt enable + bit_offset: 2 + bit_size: 1 + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 4 + bit_size: 1 + - name: PLLRDYIE + description: PLL ready interrupt enable + bit_offset: 5 + bit_size: 1 + - name: PLLSAI1RDYIE + description: PLLSAI1 ready interrupt enable + bit_offset: 6 + bit_size: 1 + - name: PLLSAI2RDYIE + description: PLLSAI2 ready interrupt enable + bit_offset: 7 + bit_size: 1 + - name: LSECSSIE + description: LSE clock security system interrupt enable + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYIE + description: HSI48 ready interrupt enable + bit_offset: 10 + bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register fields: - - name: LSIRDYF - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - - name: MSIRDYF - description: MSI ready interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSIRDYF - description: HSI ready interrupt flag - bit_offset: 3 - bit_size: 1 - - name: HSERDYF - description: HSE ready interrupt flag - bit_offset: 4 - bit_size: 1 - - name: PLLRDYF - description: PLL ready interrupt flag - bit_offset: 5 - bit_size: 1 - - name: PLLSAI1RDYF - description: PLLSAI1 ready interrupt flag - bit_offset: 6 - bit_size: 1 - - name: PLLSAI2RDYF - description: PLLSAI2 ready interrupt flag - bit_offset: 7 - bit_size: 1 - - name: CSSF - description: Clock security system interrupt flag - bit_offset: 8 - bit_size: 1 - - name: LSECSSF - description: LSE Clock security system interrupt flag - bit_offset: 9 - bit_size: 1 - - name: HSI48RDYF - description: HSI48 ready interrupt flag - bit_offset: 10 - bit_size: 1 + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: MSIRDYF + description: MSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLLRDYF + description: PLL ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: PLLSAI1RDYF + description: PLLSAI1 ready interrupt flag + bit_offset: 6 + bit_size: 1 + - name: PLLSAI2RDYF + description: PLLSAI2 ready interrupt flag + bit_offset: 7 + bit_size: 1 + - name: CSSF + description: Clock security system interrupt flag + bit_offset: 8 + bit_size: 1 + - name: LSECSSF + description: LSE Clock security system interrupt flag + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYF + description: HSI48 ready interrupt flag + bit_offset: 10 + bit_size: 1 fieldset/CR: description: Clock control register fields: - - name: MSION - description: MSI clock enable - bit_offset: 0 - bit_size: 1 - - name: MSIRDY - description: MSI clock ready flag - bit_offset: 1 - bit_size: 1 - - name: MSIPLLEN - description: MSI clock PLL enable - bit_offset: 2 - bit_size: 1 - - name: MSIRGSEL - description: MSI clock range selection - bit_offset: 3 - bit_size: 1 - - name: MSIRANGE - description: MSI clock ranges - bit_offset: 4 - bit_size: 4 - enum: MSIRANGE - - name: HSION - description: HSI clock enable - bit_offset: 8 - bit_size: 1 - - name: HSIKERON - description: HSI always enable for peripheral kernels - bit_offset: 9 - bit_size: 1 - - name: HSIRDY - description: HSI clock ready flag - bit_offset: 10 - bit_size: 1 - - name: HSIASFS - description: HSI automatic start from Stop - bit_offset: 11 - bit_size: 1 - - name: HSEON - description: HSE clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: HSE crystal oscillator bypass - bit_offset: 18 - bit_size: 1 - - name: CSSON - description: Clock security system enable - bit_offset: 19 - bit_size: 1 - - name: PLLON - description: Main PLL enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: Main PLL clock ready flag - bit_offset: 25 - bit_size: 1 - - name: PLLSAI1ON - description: SAI1 PLL enable - bit_offset: 26 - bit_size: 1 - - name: PLLSAI1RDY - description: SAI1 PLL clock ready flag - bit_offset: 27 - bit_size: 1 - - name: PLLSAI2ON - description: SAI2 PLL enable - bit_offset: 28 - bit_size: 1 - - name: PLLSAI2RDY - description: SAI2 PLL clock ready flag - bit_offset: 29 - bit_size: 1 - - name: PRIV - description: PRIV - bit_offset: 31 - bit_size: 1 + - name: MSION + description: MSI clock enable + bit_offset: 0 + bit_size: 1 + - name: MSIRDY + description: MSI clock ready flag + bit_offset: 1 + bit_size: 1 + - name: MSIPLLEN + description: MSI clock PLL enable + bit_offset: 2 + bit_size: 1 + - name: MSIRGSEL + description: MSI clock range selection + bit_offset: 3 + bit_size: 1 + - name: MSIRANGE + description: MSI clock ranges + bit_offset: 4 + bit_size: 4 + enum: MSIRANGE + - name: HSION + description: HSI clock enable + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: HSI always enable for peripheral kernels + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: HSI clock ready flag + bit_offset: 10 + bit_size: 1 + - name: HSIASFS + description: HSI automatic start from Stop + bit_offset: 11 + bit_size: 1 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: HSE crystal oscillator bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: Main PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL clock ready flag + bit_offset: 25 + bit_size: 1 + - name: PLLSAI1ON + description: SAI1 PLL enable + bit_offset: 26 + bit_size: 1 + - name: PLLSAI1RDY + description: SAI1 PLL clock ready flag + bit_offset: 27 + bit_size: 1 + - name: PLLSAI2ON + description: SAI2 PLL enable + bit_offset: 28 + bit_size: 1 + - name: PLLSAI2RDY + description: SAI2 PLL clock ready flag + bit_offset: 29 + bit_size: 1 + - name: PRIV + description: PRIV + bit_offset: 31 + bit_size: 1 fieldset/CRRCR: description: Clock recovery RC register fields: - - name: HSI48ON - description: HSI48 clock enable - bit_offset: 0 - bit_size: 1 - - name: HSI48RDY - description: HSI48 clock ready flag - bit_offset: 1 - bit_size: 1 - - name: HSI48CAL - description: HSI48 clock calibration - bit_offset: 7 - bit_size: 9 + - name: HSI48ON + description: HSI48 clock enable + bit_offset: 0 + bit_size: 1 + - name: HSI48RDY + description: HSI48 clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSI48CAL + description: HSI48 clock calibration + bit_offset: 7 + bit_size: 9 fieldset/CSR: description: CSR fields: - - name: LSION - description: LSI oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: LSI oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSIPREDIV - description: LSIPREDIV - bit_offset: 4 - bit_size: 1 - - name: MSISRANGE - description: SI range after Standby mode - bit_offset: 8 - bit_size: 4 - - name: RMVF - description: Remove reset flag - bit_offset: 23 - bit_size: 1 - - name: OBLRSTF - description: Option byte loader reset flag - bit_offset: 25 - bit_size: 1 - - name: PINRSTF - description: Pin reset flag - bit_offset: 26 - bit_size: 1 - - name: BORRSTF - description: BOR flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: Independent window watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSION + description: LSI oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: LSI oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSIPREDIV + description: LSIPREDIV + bit_offset: 4 + bit_size: 1 + - name: MSISRANGE + description: SI range after Standby mode + bit_offset: 8 + bit_size: 4 + - name: RMVF + description: Remove reset flag + bit_offset: 23 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: Pin reset flag + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: BOR flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent window watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 fieldset/ICSCR: description: Internal clock sources calibration register fields: - - name: MSICAL - description: MSI clock calibration - bit_offset: 0 - bit_size: 8 - - name: MSITRIM - description: MSI clock trimming - bit_offset: 8 - bit_size: 8 - - name: HSICAL - description: HSI clock calibration - bit_offset: 16 - bit_size: 8 - - name: HSITRIM - description: HSI clock trimming - bit_offset: 24 - bit_size: 7 + - name: MSICAL + description: MSI clock calibration + bit_offset: 0 + bit_size: 8 + - name: MSITRIM + description: MSI clock trimming + bit_offset: 8 + bit_size: 8 + - name: HSICAL + description: HSI clock calibration + bit_offset: 16 + bit_size: 8 + - name: HSITRIM + description: HSI clock trimming + bit_offset: 24 + bit_size: 7 fieldset/PLLCFGR: description: PLL configuration register fields: - - name: PLLSRC - description: "Main PLL, PLLSAI1 and PLLSAI2 entry clock source" - bit_offset: 0 - bit_size: 2 - enum: PLLSRC - - name: PLLM - description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock - bit_offset: 4 - bit_size: 4 - - name: PLLN - description: Main PLL multiplication factor for VCO - bit_offset: 8 - bit_size: 7 - - name: PLLPEN - description: Main PLL PLLSAI3CLK output enable - bit_offset: 16 - bit_size: 1 - - name: PLLP - description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) - bit_offset: 17 - bit_size: 1 - - name: PLLQEN - description: Main PLL PLLUSB1CLK output enable - bit_offset: 20 - bit_size: 1 - - name: PLLQ - description: Main PLL division factor for PLLUSB1CLK(48 MHz clock) - bit_offset: 21 - bit_size: 2 - - name: PLLREN - description: Main PLL PLLCLK output enable - bit_offset: 24 - bit_size: 1 - - name: PLLR - description: Main PLL division factor for PLLCLK (system clock) - bit_offset: 25 - bit_size: 2 - - name: PLLPDIV - description: Main PLL division factor for PLLSAI2CLK - bit_offset: 27 - bit_size: 5 + - name: PLLSRC + description: Main PLL, PLLSAI1 and PLLSAI2 entry clock source + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: PLLM + description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock + bit_offset: 4 + bit_size: 4 + - name: PLLN + description: Main PLL multiplication factor for VCO + bit_offset: 8 + bit_size: 7 + - name: PLLPEN + description: Main PLL PLLSAI3CLK output enable + bit_offset: 16 + bit_size: 1 + - name: PLLP + description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) + bit_offset: 17 + bit_size: 1 + - name: PLLQEN + description: Main PLL PLLUSB1CLK output enable + bit_offset: 20 + bit_size: 1 + - name: PLLQ + description: Main PLL division factor for PLLUSB1CLK(48 MHz clock) + bit_offset: 21 + bit_size: 2 + - name: PLLREN + description: Main PLL PLLCLK output enable + bit_offset: 24 + bit_size: 1 + - name: PLLR + description: Main PLL division factor for PLLCLK (system clock) + bit_offset: 25 + bit_size: 2 + - name: PLLPDIV + description: Main PLL division factor for PLLSAI2CLK + bit_offset: 27 + bit_size: 5 fieldset/PLLSAI1CFGR: description: PLLSAI1 configuration register fields: - - name: PLLSAI1SRC - description: PLLSAI1SRC - bit_offset: 0 - bit_size: 2 - - name: PLLSAI1M - description: Division factor for PLLSAI1 input clock - bit_offset: 4 - bit_size: 4 - - name: PLLSAI1N - description: SAI1PLL multiplication factor for VCO - bit_offset: 8 - bit_size: 7 - - name: PLLSAI1PEN - description: SAI1PLL PLLSAI1CLK output enable - bit_offset: 16 - bit_size: 1 - - name: PLLSAI1P - description: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) - bit_offset: 17 - bit_size: 1 - - name: PLLSAI1QEN - description: SAI1PLL PLLUSB2CLK output enable - bit_offset: 20 - bit_size: 1 - - name: PLLSAI1Q - description: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) - bit_offset: 21 - bit_size: 2 - - name: PLLSAI1REN - description: PLLSAI1 PLLADC1CLK output enable - bit_offset: 24 - bit_size: 1 - - name: PLLSAI1R - description: PLLSAI1 division factor for PLLADC1CLK (ADC clock) - bit_offset: 25 - bit_size: 2 - - name: PLLSAI1PDIV - description: PLLSAI1 division factor for PLLSAI1CLK - bit_offset: 27 - bit_size: 5 + - name: PLLSAI1SRC + description: PLLSAI1SRC + bit_offset: 0 + bit_size: 2 + - name: PLLSAI1M + description: Division factor for PLLSAI1 input clock + bit_offset: 4 + bit_size: 4 + - name: PLLSAI1N + description: SAI1PLL multiplication factor for VCO + bit_offset: 8 + bit_size: 7 + - name: PLLSAI1PEN + description: SAI1PLL PLLSAI1CLK output enable + bit_offset: 16 + bit_size: 1 + - name: PLLSAI1P + description: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) + bit_offset: 17 + bit_size: 1 + - name: PLLSAI1QEN + description: SAI1PLL PLLUSB2CLK output enable + bit_offset: 20 + bit_size: 1 + - name: PLLSAI1Q + description: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) + bit_offset: 21 + bit_size: 2 + - name: PLLSAI1REN + description: PLLSAI1 PLLADC1CLK output enable + bit_offset: 24 + bit_size: 1 + - name: PLLSAI1R + description: PLLSAI1 division factor for PLLADC1CLK (ADC clock) + bit_offset: 25 + bit_size: 2 + - name: PLLSAI1PDIV + description: PLLSAI1 division factor for PLLSAI1CLK + bit_offset: 27 + bit_size: 5 fieldset/PLLSAI2CFGR: description: PLLSAI2 configuration register fields: - - name: PLLSAI2SRC - description: PLLSAI2SRC - bit_offset: 0 - bit_size: 2 - - name: PLLSAI2M - description: Division factor for PLLSAI2 input clock - bit_offset: 4 - bit_size: 4 - - name: PLLSAI2N - description: SAI2PLL multiplication factor for VCO - bit_offset: 8 - bit_size: 7 - - name: PLLSAI2PEN - description: SAI2PLL PLLSAI2CLK output enable - bit_offset: 16 - bit_size: 1 - - name: PLLSAI2P - description: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock) - bit_offset: 17 - bit_size: 1 - - name: PLLSAI2PDIV - description: PLLSAI2 division factor for PLLSAI2CLK - bit_offset: 27 - bit_size: 5 + - name: PLLSAI2SRC + description: PLLSAI2SRC + bit_offset: 0 + bit_size: 2 + - name: PLLSAI2M + description: Division factor for PLLSAI2 input clock + bit_offset: 4 + bit_size: 4 + - name: PLLSAI2N + description: SAI2PLL multiplication factor for VCO + bit_offset: 8 + bit_size: 7 + - name: PLLSAI2PEN + description: SAI2PLL PLLSAI2CLK output enable + bit_offset: 16 + bit_size: 1 + - name: PLLSAI2P + description: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock) + bit_offset: 17 + bit_size: 1 + - name: PLLSAI2PDIV + description: PLLSAI2 division factor for PLLSAI2CLK + bit_offset: 27 + bit_size: 5 fieldset/SECCFGR: description: RCC secure configuration register fields: - - name: HSISEC - description: HSISEC - bit_offset: 0 - bit_size: 1 - - name: HSESEC - description: HSESEC - bit_offset: 1 - bit_size: 1 - - name: MSISEC - description: MSISEC - bit_offset: 2 - bit_size: 1 - - name: LSISEC - description: LSISEC - bit_offset: 3 - bit_size: 1 - - name: LSESEC - description: LSESEC - bit_offset: 4 - bit_size: 1 - - name: SYSCLKSEC - description: SYSCLKSEC - bit_offset: 5 - bit_size: 1 - - name: PRESCSEC - description: PRESCSEC - bit_offset: 6 - bit_size: 1 - - name: PLLSEC - description: PLLSEC - bit_offset: 7 - bit_size: 1 - - name: PLLSAI1SEC - description: PLLSAI1SEC - bit_offset: 8 - bit_size: 1 - - name: PLLSAI2SEC - description: PLLSAI2SEC - bit_offset: 9 - bit_size: 1 - - name: CLK48MSEC - description: CLK48MSEC - bit_offset: 10 - bit_size: 1 - - name: HSI48SEC - description: HSI48SEC - bit_offset: 11 - bit_size: 1 - - name: RMVFSEC - description: RMVFSEC - bit_offset: 12 - bit_size: 1 + - name: HSISEC + description: HSISEC + bit_offset: 0 + bit_size: 1 + - name: HSESEC + description: HSESEC + bit_offset: 1 + bit_size: 1 + - name: MSISEC + description: MSISEC + bit_offset: 2 + bit_size: 1 + - name: LSISEC + description: LSISEC + bit_offset: 3 + bit_size: 1 + - name: LSESEC + description: LSESEC + bit_offset: 4 + bit_size: 1 + - name: SYSCLKSEC + description: SYSCLKSEC + bit_offset: 5 + bit_size: 1 + - name: PRESCSEC + description: PRESCSEC + bit_offset: 6 + bit_size: 1 + - name: PLLSEC + description: PLLSEC + bit_offset: 7 + bit_size: 1 + - name: PLLSAI1SEC + description: PLLSAI1SEC + bit_offset: 8 + bit_size: 1 + - name: PLLSAI2SEC + description: PLLSAI2SEC + bit_offset: 9 + bit_size: 1 + - name: CLK48MSEC + description: CLK48MSEC + bit_offset: 10 + bit_size: 1 + - name: HSI48SEC + description: HSI48SEC + bit_offset: 11 + bit_size: 1 + - name: RMVFSEC + description: RMVFSEC + bit_offset: 12 + bit_size: 1 fieldset/SECSR: description: RCC secure status register fields: - - name: HSISECF - description: HSISECF - bit_offset: 0 - bit_size: 1 - - name: HSESECF - description: HSESECF - bit_offset: 1 - bit_size: 1 - - name: MSISECF - description: MSISECF - bit_offset: 2 - bit_size: 1 - - name: LSISECF - description: LSISECF - bit_offset: 3 - bit_size: 1 - - name: LSESECF - description: LSESECF - bit_offset: 4 - bit_size: 1 - - name: SYSCLKSECF - description: SYSCLKSECF - bit_offset: 5 - bit_size: 1 - - name: PRESCSECF - description: PRESCSECF - bit_offset: 6 - bit_size: 1 - - name: PLLSECF - description: PLLSECF - bit_offset: 7 - bit_size: 1 - - name: PLLSAI1SECF - description: PLLSAI1SECF - bit_offset: 8 - bit_size: 1 - - name: PLLSAI2SECF - description: PLLSAI2SECF - bit_offset: 9 - bit_size: 1 - - name: CLK48MSECF - description: CLK48MSECF - bit_offset: 10 - bit_size: 1 - - name: HSI48SECF - description: HSI48SECF - bit_offset: 11 - bit_size: 1 - - name: RMVFSECF - description: RMVFSECF - bit_offset: 12 - bit_size: 1 + - name: HSISECF + description: HSISECF + bit_offset: 0 + bit_size: 1 + - name: HSESECF + description: HSESECF + bit_offset: 1 + bit_size: 1 + - name: MSISECF + description: MSISECF + bit_offset: 2 + bit_size: 1 + - name: LSISECF + description: LSISECF + bit_offset: 3 + bit_size: 1 + - name: LSESECF + description: LSESECF + bit_offset: 4 + bit_size: 1 + - name: SYSCLKSECF + description: SYSCLKSECF + bit_offset: 5 + bit_size: 1 + - name: PRESCSECF + description: PRESCSECF + bit_offset: 6 + bit_size: 1 + - name: PLLSECF + description: PLLSECF + bit_offset: 7 + bit_size: 1 + - name: PLLSAI1SECF + description: PLLSAI1SECF + bit_offset: 8 + bit_size: 1 + - name: PLLSAI2SECF + description: PLLSAI2SECF + bit_offset: 9 + bit_size: 1 + - name: CLK48MSECF + description: CLK48MSECF + bit_offset: 10 + bit_size: 1 + - name: HSI48SECF + description: HSI48SECF + bit_offset: 11 + bit_size: 1 + - name: RMVFSECF + description: RMVFSECF + bit_offset: 12 + bit_size: 1 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: SYSCLK not divided - value: 0 - - name: Div2 - description: SYSCLK divided by 2 - value: 8 - - name: Div4 - description: SYSCLK divided by 4 - value: 9 - - name: Div8 - description: SYSCLK divided by 8 - value: 10 - - name: Div16 - description: SYSCLK divided by 16 - value: 11 - - name: Div64 - description: SYSCLK divided by 64 - value: 12 - - name: Div128 - description: SYSCLK divided by 128 - value: 13 - - name: Div256 - description: SYSCLK divided by 256 - value: 14 - - name: Div512 - description: SYSCLK divided by 512 - value: 15 + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 enum/LSCOSEL: bit_size: 1 variants: - - name: LSI - description: "LSI clock selected\"" - value: 0 - - name: LSE - description: LSE clock selected - value: 1 + - name: LSI + description: LSI clock selected" + value: 0 + - name: LSE + description: LSE clock selected + value: 1 enum/LSEDRV: bit_size: 2 variants: - - name: Lower - description: "'Xtal mode' lower driving capability" - value: 0 - - name: MediumLow - description: "'Xtal mode' medium low driving capability" - value: 1 - - name: MediumHigh - description: "'Xtal mode' medium high driving capability" - value: 2 - - name: Higher - description: "'Xtal mode' higher driving capability" - value: 3 + - name: Lower + description: '''Xtal mode'' lower driving capability' + value: 0 + - name: MediumLow + description: '''Xtal mode'' medium low driving capability' + value: 1 + - name: MediumHigh + description: '''Xtal mode'' medium high driving capability' + value: 2 + - name: Higher + description: '''Xtal mode'' higher driving capability' + value: 3 enum/MCOPRE: bit_size: 3 variants: - - name: Div1 - description: MCO divided by 1 - value: 0 - - name: Div2 - description: MCO divided by 2 - value: 1 - - name: Div4 - description: MCO divided by 4 - value: 2 - - name: Div8 - description: MCO divided by 8 - value: 3 - - name: Div16 - description: MCO divided by 16 - value: 4 + - name: Div1 + description: MCO divided by 1 + value: 0 + - name: Div2 + description: MCO divided by 2 + value: 1 + - name: Div4 + description: MCO divided by 4 + value: 2 + - name: Div8 + description: MCO divided by 8 + value: 3 + - name: Div16 + description: MCO divided by 16 + value: 4 enum/MCOSEL: bit_size: 4 variants: - - name: None - description: "MCO output disabled, no clock on MCO" - value: 0 - - name: SYSCLK - description: SYSCLK system clock selected - value: 1 - - name: MSI - description: MSI clock selected - value: 2 - - name: HSI - description: HSI clock selected - value: 3 - - name: HSE - description: HSE clock selected - value: 4 - - name: PLL - description: Main PLL clock selected - value: 5 - - name: LSI - description: LSI clock selected - value: 6 - - name: LSE - description: LSE clock selected - value: 7 - - name: HSI48 - description: Internal HSI48 clock selected - value: 8 + - name: None + description: MCO output disabled, no clock on MCO + value: 0 + - name: SYSCLK + description: SYSCLK system clock selected + value: 1 + - name: MSI + description: MSI clock selected + value: 2 + - name: HSI + description: HSI clock selected + value: 3 + - name: HSE + description: HSE clock selected + value: 4 + - name: PLL + description: Main PLL clock selected + value: 5 + - name: LSI + description: LSI clock selected + value: 6 + - name: LSE + description: LSE clock selected + value: 7 + - name: HSI48 + description: Internal HSI48 clock selected + value: 8 enum/MSIRANGE: bit_size: 4 variants: - - name: Range100K - description: range 0 around 100 kHz - value: 0 - - name: Range200K - description: range 1 around 200 kHz - value: 1 - - name: Range400K - description: range 2 around 400 kHz - value: 2 - - name: Range800K - description: range 3 around 800 kHz - value: 3 - - name: Range1M - description: range 4 around 1 MHz - value: 4 - - name: Range2M - description: range 5 around 2 MHz - value: 5 - - name: Range4M - description: range 6 around 4 MHz - value: 6 - - name: Range8M - description: range 7 around 8 MHz - value: 7 - - name: Range16M - description: range 8 around 16 MHz - value: 8 - - name: Range24M - description: range 9 around 24 MHz - value: 9 - - name: Range32M - description: range 10 around 32 MHz - value: 10 - - name: Range48M - description: range 11 around 48 MHz - value: 11 + - name: Range100K + description: range 0 around 100 kHz + value: 0 + - name: Range200K + description: range 1 around 200 kHz + value: 1 + - name: Range400K + description: range 2 around 400 kHz + value: 2 + - name: Range800K + description: range 3 around 800 kHz + value: 3 + - name: Range1M + description: range 4 around 1 MHz + value: 4 + - name: Range2M + description: range 5 around 2 MHz + value: 5 + - name: Range4M + description: range 6 around 4 MHz + value: 6 + - name: Range8M + description: range 7 around 8 MHz + value: 7 + - name: Range16M + description: range 8 around 16 MHz + value: 8 + - name: Range24M + description: range 9 around 24 MHz + value: 9 + - name: Range32M + description: range 10 around 32 MHz + value: 10 + - name: Range48M + description: range 11 around 48 MHz + value: 11 enum/PLLSRC: bit_size: 2 variants: - - name: None - description: No clock sent to PLL - value: 0 - - name: MSI - description: MSI selected as PLL input clock - value: 1 - - name: HSI16 - description: HSI selected as PLL input clock - value: 2 - - name: HSE - description: HSE selected as PLL input clock - value: 3 + - name: None + description: No clock sent to PLL + value: 0 + - name: MSI + description: MSI selected as PLL input clock + value: 1 + - name: HSI16 + description: HSI selected as PLL input clock + value: 2 + - name: HSE + description: HSE selected as PLL input clock + value: 3 enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK divided by 2 - value: 4 - - name: Div4 - description: HCLK divided by 4 - value: 5 - - name: Div8 - description: HCLK divided by 8 - value: 6 - - name: Div16 - description: HCLK divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: HSE oscillator clock divided by a prescaler used as RTC clock - value: 3 + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 enum/STOPWUCK: bit_size: 1 variants: - - name: MSI - description: MSI oscillator selected as wake-up from Stop clock and CSS backup clock - value: 0 - - name: HSI16 - description: HSI oscillator selected as wake-up from stop clock and CSS backup clock - value: 1 + - name: MSI + description: MSI oscillator selected as wake-up from Stop clock and CSS backup clock + value: 0 + - name: HSI16 + description: HSI oscillator selected as wake-up from stop clock and CSS backup clock + value: 1 enum/SW: bit_size: 2 variants: - - name: MSI - description: MSI selected as system clock - value: 0 - - name: HSI16 - description: HSI selected as system clock - value: 1 - - name: HSE - description: HSE selected as system clock - value: 2 - - name: PLL - description: PLL selected as system clock - value: 3 + - name: MSI + description: MSI selected as system clock + value: 0 + - name: HSI16 + description: HSI selected as system clock + value: 1 + - name: HSE + description: HSE selected as system clock + value: 2 + - name: PLL + description: PLL selected as system clock + value: 3 diff --git a/data/registers/rcc_u5.yaml b/data/registers/rcc_u5.yaml index 9e5efbb..7768b0d 100644 --- a/data/registers/rcc_u5.yaml +++ b/data/registers/rcc_u5.yaml @@ -1,3240 +1,3239 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: RCC clock control register - byte_offset: 0 - fieldset: CR - - name: ICSCR1 - description: RCC internal clock sources calibration register 1 - byte_offset: 8 - fieldset: ICSCR1 - - name: ICSCR2 - description: RCC internal clock sources calibration register 2 - byte_offset: 12 - fieldset: ICSCR2 - - name: ICSCR3 - description: RCC internal clock sources calibration register 3 - byte_offset: 16 - fieldset: ICSCR3 - - name: CRRCR - description: RCC clock recovery RC register - byte_offset: 20 - fieldset: CRRCR - - name: CFGR1 - description: RCC clock configuration register 1 - byte_offset: 28 - fieldset: CFGR1 - - name: CFGR2 - description: RCC clock configuration register 2 - byte_offset: 32 - fieldset: CFGR2 - - name: CFGR3 - description: RCC clock configuration register 3 - byte_offset: 36 - fieldset: CFGR3 - - name: PLL1CFGR - description: RCC PLL1 configuration register - byte_offset: 40 - fieldset: PLL1CFGR - - name: PLL2CFGR - description: RCC PLL2 configuration register - byte_offset: 44 - fieldset: PLL2CFGR - - name: PLL3CFGR - description: RCC PLL3 configuration register - byte_offset: 48 - fieldset: PLL3CFGR - - name: PLL1DIVR - description: RCC PLL1 dividers register - byte_offset: 52 - fieldset: PLL1DIVR - - name: PLL1FRACR - description: RCC PLL1 fractional divider register - byte_offset: 56 - fieldset: PLL1FRACR - - name: PLL2DIVR - description: RCC PLL2 dividers configuration register - byte_offset: 60 - fieldset: PLL2DIVR - - name: PLL2FRACR - description: RCC PLL2 fractional divider register - byte_offset: 64 - fieldset: PLL2FRACR - - name: PLL3DIVR - description: RCC PLL3 dividers configuration register - byte_offset: 68 - fieldset: PLL3DIVR - - name: PLL3FRACR - description: RCC PLL3 fractional divider register - byte_offset: 72 - fieldset: PLL3FRACR - - name: CIER - description: RCC clock interrupt enable register - byte_offset: 80 - fieldset: CIER - - name: CIFR - description: RCC clock interrupt flag register - byte_offset: 84 - fieldset: CIFR - - name: CICR - description: RCC clock interrupt clear register - byte_offset: 88 - fieldset: CICR - - name: AHB1RSTR - description: RCC AHB1 peripheral reset register - byte_offset: 96 - fieldset: AHB1RSTR - - name: AHB2RSTR1 - description: RCC AHB2 peripheral reset register 1 - byte_offset: 100 - fieldset: AHB2RSTR1 - - name: AHB2RSTR2 - description: RCC AHB2 peripheral reset register 2 - byte_offset: 104 - fieldset: AHB2RSTR2 - - name: AHB3RSTR - description: RCC AHB3 peripheral reset register - byte_offset: 108 - fieldset: AHB3RSTR - - name: APB1RSTR1 - description: RCC APB1 peripheral reset register 1 - byte_offset: 116 - fieldset: APB1RSTR1 - - name: APB1RSTR2 - description: RCC APB1 peripheral reset register 2 - byte_offset: 120 - fieldset: APB1RSTR2 - - name: APB2RSTR - description: RCC APB2 peripheral reset register - byte_offset: 124 - fieldset: APB2RSTR - - name: APB3RSTR - description: RCC APB3 peripheral reset register - byte_offset: 128 - fieldset: APB3RSTR - - name: AHB1ENR - description: RCC AHB1 peripheral clock enable register - byte_offset: 136 - fieldset: AHB1ENR - - name: AHB2ENR1 - description: RCC AHB2 peripheral clock enable register 1 - byte_offset: 140 - fieldset: AHB2ENR1 - - name: AHB2ENR2 - description: RCC AHB2 peripheral clock enable register 2 - byte_offset: 144 - fieldset: AHB2ENR2 - - name: AHB3ENR - description: RCC AHB3 peripheral clock enable register - byte_offset: 148 - fieldset: AHB3ENR - - name: APB1ENR1 - description: RCC APB1 peripheral clock enable register 1 - byte_offset: 156 - fieldset: APB1ENR1 - - name: APB1ENR2 - description: RCC APB1 peripheral clock enable register 2 - byte_offset: 160 - fieldset: APB1ENR2 - - name: APB2ENR - description: RCC APB2 peripheral clock enable register - byte_offset: 164 - fieldset: APB2ENR - - name: APB3ENR - description: RCC APB3 peripheral clock enable register - byte_offset: 168 - fieldset: APB3ENR - - name: AHB1SMENR - description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 176 - fieldset: AHB1SMENR - - name: AHB2SMENR1 - description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1" - byte_offset: 180 - fieldset: AHB2SMENR1 - - name: AHB2SMENR2 - description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2" - byte_offset: 184 - fieldset: AHB2SMENR2 - - name: AHB3SMENR - description: RCC AHB3 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 188 - fieldset: AHB3SMENR - - name: APB1SMENR1 - description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1" - byte_offset: 196 - fieldset: APB1SMENR1 - - name: APB1SMENR2 - description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2" - byte_offset: 200 - fieldset: APB1SMENR2 - - name: APB2SMENR - description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 204 - fieldset: APB2SMENR - - name: APB3SMENR - description: RCC APB3 peripheral clock enable in Sleep and Stop modes register - byte_offset: 208 - fieldset: APB3SMENR - - name: SRDAMR - description: RCC SmartRun domain peripheral autonomous mode register - byte_offset: 216 - fieldset: SRDAMR - - name: CCIPR1 - description: RCC peripherals independent clock configuration register 1 - byte_offset: 224 - fieldset: CCIPR1 - - name: CCIPR2 - description: RCC peripherals independent clock configuration register 2 - byte_offset: 228 - fieldset: CCIPR2 - - name: CCIPR3 - description: RCC peripherals independent clock configuration register 3 - byte_offset: 232 - fieldset: CCIPR3 - - name: BDCR - description: RCC Backup domain control register - byte_offset: 240 - fieldset: BDCR - - name: CSR - description: RCC control/status register - byte_offset: 244 - fieldset: CSR - - name: SECCFGR - description: RCC secure configuration register - byte_offset: 272 - fieldset: SECCFGR - - name: PRIVCFGR - description: RCC privilege configuration register - byte_offset: 276 - fieldset: PRIVCFGR + - name: CR + description: RCC clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR1 + description: RCC internal clock sources calibration register 1 + byte_offset: 8 + fieldset: ICSCR1 + - name: ICSCR2 + description: RCC internal clock sources calibration register 2 + byte_offset: 12 + fieldset: ICSCR2 + - name: ICSCR3 + description: RCC internal clock sources calibration register 3 + byte_offset: 16 + fieldset: ICSCR3 + - name: CRRCR + description: RCC clock recovery RC register + byte_offset: 20 + fieldset: CRRCR + - name: CFGR1 + description: RCC clock configuration register 1 + byte_offset: 28 + fieldset: CFGR1 + - name: CFGR2 + description: RCC clock configuration register 2 + byte_offset: 32 + fieldset: CFGR2 + - name: CFGR3 + description: RCC clock configuration register 3 + byte_offset: 36 + fieldset: CFGR3 + - name: PLL1CFGR + description: RCC PLL1 configuration register + byte_offset: 40 + fieldset: PLL1CFGR + - name: PLL2CFGR + description: RCC PLL2 configuration register + byte_offset: 44 + fieldset: PLL2CFGR + - name: PLL3CFGR + description: RCC PLL3 configuration register + byte_offset: 48 + fieldset: PLL3CFGR + - name: PLL1DIVR + description: RCC PLL1 dividers register + byte_offset: 52 + fieldset: PLL1DIVR + - name: PLL1FRACR + description: RCC PLL1 fractional divider register + byte_offset: 56 + fieldset: PLL1FRACR + - name: PLL2DIVR + description: RCC PLL2 dividers configuration register + byte_offset: 60 + fieldset: PLL2DIVR + - name: PLL2FRACR + description: RCC PLL2 fractional divider register + byte_offset: 64 + fieldset: PLL2FRACR + - name: PLL3DIVR + description: RCC PLL3 dividers configuration register + byte_offset: 68 + fieldset: PLL3DIVR + - name: PLL3FRACR + description: RCC PLL3 fractional divider register + byte_offset: 72 + fieldset: PLL3FRACR + - name: CIER + description: RCC clock interrupt enable register + byte_offset: 80 + fieldset: CIER + - name: CIFR + description: RCC clock interrupt flag register + byte_offset: 84 + fieldset: CIFR + - name: CICR + description: RCC clock interrupt clear register + byte_offset: 88 + fieldset: CICR + - name: AHB1RSTR + description: RCC AHB1 peripheral reset register + byte_offset: 96 + fieldset: AHB1RSTR + - name: AHB2RSTR1 + description: RCC AHB2 peripheral reset register 1 + byte_offset: 100 + fieldset: AHB2RSTR1 + - name: AHB2RSTR2 + description: RCC AHB2 peripheral reset register 2 + byte_offset: 104 + fieldset: AHB2RSTR2 + - name: AHB3RSTR + description: RCC AHB3 peripheral reset register + byte_offset: 108 + fieldset: AHB3RSTR + - name: APB1RSTR1 + description: RCC APB1 peripheral reset register 1 + byte_offset: 116 + fieldset: APB1RSTR1 + - name: APB1RSTR2 + description: RCC APB1 peripheral reset register 2 + byte_offset: 120 + fieldset: APB1RSTR2 + - name: APB2RSTR + description: RCC APB2 peripheral reset register + byte_offset: 124 + fieldset: APB2RSTR + - name: APB3RSTR + description: RCC APB3 peripheral reset register + byte_offset: 128 + fieldset: APB3RSTR + - name: AHB1ENR + description: RCC AHB1 peripheral clock enable register + byte_offset: 136 + fieldset: AHB1ENR + - name: AHB2ENR1 + description: RCC AHB2 peripheral clock enable register 1 + byte_offset: 140 + fieldset: AHB2ENR1 + - name: AHB2ENR2 + description: RCC AHB2 peripheral clock enable register 2 + byte_offset: 144 + fieldset: AHB2ENR2 + - name: AHB3ENR + description: RCC AHB3 peripheral clock enable register + byte_offset: 148 + fieldset: AHB3ENR + - name: APB1ENR1 + description: RCC APB1 peripheral clock enable register 1 + byte_offset: 156 + fieldset: APB1ENR1 + - name: APB1ENR2 + description: RCC APB1 peripheral clock enable register 2 + byte_offset: 160 + fieldset: APB1ENR2 + - name: APB2ENR + description: RCC APB2 peripheral clock enable register + byte_offset: 164 + fieldset: APB2ENR + - name: APB3ENR + description: RCC APB3 peripheral clock enable register + byte_offset: 168 + fieldset: APB3ENR + - name: AHB1SMENR + description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 176 + fieldset: AHB1SMENR + - name: AHB2SMENR1 + description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1" + byte_offset: 180 + fieldset: AHB2SMENR1 + - name: AHB2SMENR2 + description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2" + byte_offset: 184 + fieldset: AHB2SMENR2 + - name: AHB3SMENR + description: RCC AHB3 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 188 + fieldset: AHB3SMENR + - name: APB1SMENR1 + description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1" + byte_offset: 196 + fieldset: APB1SMENR1 + - name: APB1SMENR2 + description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2" + byte_offset: 200 + fieldset: APB1SMENR2 + - name: APB2SMENR + description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 204 + fieldset: APB2SMENR + - name: APB3SMENR + description: RCC APB3 peripheral clock enable in Sleep and Stop modes register + byte_offset: 208 + fieldset: APB3SMENR + - name: SRDAMR + description: RCC SmartRun domain peripheral autonomous mode register + byte_offset: 216 + fieldset: SRDAMR + - name: CCIPR1 + description: RCC peripherals independent clock configuration register 1 + byte_offset: 224 + fieldset: CCIPR1 + - name: CCIPR2 + description: RCC peripherals independent clock configuration register 2 + byte_offset: 228 + fieldset: CCIPR2 + - name: CCIPR3 + description: RCC peripherals independent clock configuration register 3 + byte_offset: 232 + fieldset: CCIPR3 + - name: BDCR + description: RCC Backup domain control register + byte_offset: 240 + fieldset: BDCR + - name: CSR + description: RCC control/status register + byte_offset: 244 + fieldset: CSR + - name: SECCFGR + description: RCC secure configuration register + byte_offset: 272 + fieldset: SECCFGR + - name: PRIVCFGR + description: RCC privilege configuration register + byte_offset: 276 + fieldset: PRIVCFGR fieldset/AHB1ENR: description: RCC AHB1 peripheral clock enable register fields: - - name: GPDMA1EN - description: "GPDMA1 clock enable\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: CORDICEN - description: "CORDIC clock enable\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: FMACEN - description: "FMAC clock enable\r Set and reset by software." - bit_offset: 2 - bit_size: 1 - - name: MDF1EN - description: "MDF1 clock enable\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - - name: FLASHEN - description: "FLASH clock enable\r Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode." - bit_offset: 8 - bit_size: 1 - - name: CRCEN - description: "CRC clock enable\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: JPEGEN - description: "JPEG clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 15 - bit_size: 1 - - name: TSCEN - description: "Touch sensing controller clock enable\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: RAMCFGEN - description: "RAMCFG clock enable\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: DMA2DEN - description: "DMA2D clock enable\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: GFXMMUEN - description: "GFXMMU clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 19 - bit_size: 1 - - name: GPU2DEN - description: "GPU2D clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 20 - bit_size: 1 - - name: DCACHE2EN - description: "DCACHE2 clock enable \r This bit is set and reset by software.\r Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 21 - bit_size: 1 - - name: GTZC1EN - description: "GTZC1 clock enable\r Set and reset by software." - bit_offset: 24 - bit_size: 1 - - name: BKPSRAMEN - description: "BKPSRAM clock enable\r Set and reset by software." - bit_offset: 28 - bit_size: 1 - - name: DCACHE1EN - description: "DCACHE1 clock enable\r Set and reset by software.\r Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2 or FSMC, even if the DCACHE1 is bypassed." - bit_offset: 30 - bit_size: 1 - - name: SRAM1EN - description: "SRAM1 clock enable\r Set and reset by software." - bit_offset: 31 - bit_size: 1 + - name: GPDMA1EN + description: "GPDMA1 clock enable\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: CORDICEN + description: "CORDIC clock enable\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: FMACEN + description: "FMAC clock enable\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: MDF1EN + description: "MDF1 clock enable\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: FLASHEN + description: "FLASH clock enable\r Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode." + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: "CRC clock enable\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: JPEGEN + description: "JPEG clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 15 + bit_size: 1 + - name: TSCEN + description: "Touch sensing controller clock enable\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: RAMCFGEN + description: "RAMCFG clock enable\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: DMA2DEN + description: "DMA2D clock enable\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: GFXMMUEN + description: "GFXMMU clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 19 + bit_size: 1 + - name: GPU2DEN + description: "GPU2D clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 20 + bit_size: 1 + - name: DCACHE2EN + description: "DCACHE2 clock enable \r This bit is set and reset by software.\r Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 21 + bit_size: 1 + - name: GTZC1EN + description: "GTZC1 clock enable\r Set and reset by software." + bit_offset: 24 + bit_size: 1 + - name: BKPSRAMEN + description: "BKPSRAM clock enable\r Set and reset by software." + bit_offset: 28 + bit_size: 1 + - name: DCACHE1EN + description: "DCACHE1 clock enable\r Set and reset by software.\r Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2 or FSMC, even if the DCACHE1 is bypassed." + bit_offset: 30 + bit_size: 1 + - name: SRAM1EN + description: "SRAM1 clock enable\r Set and reset by software." + bit_offset: 31 + bit_size: 1 fieldset/AHB1RSTR: description: RCC AHB1 peripheral reset register fields: - - name: GPDMA1RST - description: "GPDMA1 reset\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: CORDICRST - description: "CORDIC reset\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: FMACRST - description: "FMAC reset\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: MDF1RST - description: "MDF1 reset\r Set and cleared by software." - bit_offset: 3 - bit_size: 1 - - name: CRCRST - description: "CRC reset\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: JPEGRST - description: "JPEG reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 15 - bit_size: 1 - - name: TSCRST - description: "TSC reset\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: RAMCFGRST - description: "RAMCFG reset\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: DMA2DRST - description: "DMA2D reset\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: GFXMMURST - description: "GFXMMU reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 19 - bit_size: 1 - - name: GPU2DRST - description: "GPU2D reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 20 - bit_size: 1 + - name: GPDMA1RST + description: "GPDMA1 reset\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: CORDICRST + description: "CORDIC reset\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: FMACRST + description: "FMAC reset\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: MDF1RST + description: "MDF1 reset\r Set and cleared by software." + bit_offset: 3 + bit_size: 1 + - name: CRCRST + description: "CRC reset\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: JPEGRST + description: "JPEG reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 15 + bit_size: 1 + - name: TSCRST + description: "TSC reset\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: RAMCFGRST + description: "RAMCFG reset\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: DMA2DRST + description: "DMA2D reset\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: GFXMMURST + description: "GFXMMU reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 19 + bit_size: 1 + - name: GPU2DRST + description: "GPU2D reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 20 + bit_size: 1 fieldset/AHB1SMENR: description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register fields: - - name: GPDMA1SMEN - description: "GPDMA1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 0 - bit_size: 1 - - name: CORDICSMEN - description: "CORDIC clocks enable during Sleep and Stop modes\r Set and cleared by software during Sleep mode." - bit_offset: 1 - bit_size: 1 - - name: FMACSMEN - description: "FMAC clocks enable during Sleep and Stop modes.\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: MDF1SMEN - description: "MDF1 clocks enable during Sleep and Stop modes.\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 3 - bit_size: 1 - - name: FLASHSMEN - description: "FLASH clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 8 - bit_size: 1 - - name: CRCSMEN - description: "CRC clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: JPEGSMEN - description: "JPEG clocks enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 15 - bit_size: 1 - - name: TSCSMEN - description: "TSC clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: RAMCFGSMEN - description: "RAMCFG clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: DMA2DSMEN - description: "DMA2D clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: GFXMMUSMEN - description: "GFXMMU clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 19 - bit_size: 1 - - name: GPU2DSMEN - description: "GPU2D clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 20 - bit_size: 1 - - name: DCACHE2SMEN - description: "DCACHE2 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 21 - bit_size: 1 - - name: GTZC1SMEN - description: "GTZC1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: BKPSRAMSMEN - description: "BKPSRAM clocks enable during Sleep and Stop modes\r Set and cleared by software" - bit_offset: 28 - bit_size: 1 - - name: ICACHESMEN - description: "ICACHE clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 29 - bit_size: 1 - - name: DCACHE1SMEN - description: "DCACHE1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 30 - bit_size: 1 - - name: SRAM1SMEN - description: "SRAM1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 31 - bit_size: 1 + - name: GPDMA1SMEN + description: "GPDMA1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 0 + bit_size: 1 + - name: CORDICSMEN + description: "CORDIC clocks enable during Sleep and Stop modes\r Set and cleared by software during Sleep mode." + bit_offset: 1 + bit_size: 1 + - name: FMACSMEN + description: "FMAC clocks enable during Sleep and Stop modes.\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: MDF1SMEN + description: "MDF1 clocks enable during Sleep and Stop modes.\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 3 + bit_size: 1 + - name: FLASHSMEN + description: "FLASH clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 8 + bit_size: 1 + - name: CRCSMEN + description: "CRC clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: JPEGSMEN + description: "JPEG clocks enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 15 + bit_size: 1 + - name: TSCSMEN + description: "TSC clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: RAMCFGSMEN + description: "RAMCFG clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: DMA2DSMEN + description: "DMA2D clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: GFXMMUSMEN + description: "GFXMMU clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 19 + bit_size: 1 + - name: GPU2DSMEN + description: "GPU2D clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 20 + bit_size: 1 + - name: DCACHE2SMEN + description: "DCACHE2 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 21 + bit_size: 1 + - name: GTZC1SMEN + description: "GTZC1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: BKPSRAMSMEN + description: "BKPSRAM clocks enable during Sleep and Stop modes\r Set and cleared by software" + bit_offset: 28 + bit_size: 1 + - name: ICACHESMEN + description: "ICACHE clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 29 + bit_size: 1 + - name: DCACHE1SMEN + description: "DCACHE1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 30 + bit_size: 1 + - name: SRAM1SMEN + description: "SRAM1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 31 + bit_size: 1 fieldset/AHB2ENR1: description: RCC AHB2 peripheral clock enable register 1 fields: - - name: GPIOAEN - description: "IO port A clock enable\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: "IO port B clock enable\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: "IO port C clock enable\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: "IO port D clock enable\r Set and cleared by software." - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: "IO port E clock enable\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: GPIOFEN - description: "IO port F clock enable\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: GPIOGEN - description: "IO port G clock enable\r Set and cleared by software." - bit_offset: 6 - bit_size: 1 - - name: GPIOHEN - description: "IO port H clock enable\r Set and cleared by software." - bit_offset: 7 - bit_size: 1 - - name: GPIOIEN - description: "IO port I clock enable\r Set and cleared by software." - bit_offset: 8 - bit_size: 1 - - name: GPIOJEN - description: "I/O port J clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 9 - bit_size: 1 - - name: ADC12EN - description: "ADC1 and ADC2 clock enable\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx." - bit_offset: 10 - bit_size: 1 - - name: DCMIEN - description: "DCMI and PSSI clock enable\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: USB_OTG_FSEN - description: "OTG_FS clock enable\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: USB_OTG_HSEN - description: "OTG_HS clock enable\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: USB_OTG_HS_PHYEN - description: "OTG_HS PHY clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 15 - bit_size: 1 - - name: AESEN - description: "AES clock enable\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: HASHEN - description: "HASH clock enable\r Set and cleared by software" - bit_offset: 17 - bit_size: 1 - - name: RNGEN - description: "RNG clock enable\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: PKAEN - description: "PKA clock enable\r Set and cleared by software." - bit_offset: 19 - bit_size: 1 - - name: SAESEN - description: "SAES clock enable\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 - - name: OCTOSPIMEN - description: "OCTOSPIM clock enable\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: OTFDEC1EN - description: "OTFDEC1 clock enable\r Set and cleared by software." - bit_offset: 23 - bit_size: 1 - - name: OTFDEC2EN - description: "OTFDEC2 clock enable\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: SDMMC1EN - description: "SDMMC1 clock enable\r Set and cleared by software." - bit_offset: 27 - bit_size: 1 - - name: SDMMC2EN - description: "SDMMC2 clock enable\r Set and cleared by software." - bit_offset: 28 - bit_size: 1 - - name: SRAM2EN - description: "SRAM2 clock enable\r Set and reset by software." - bit_offset: 30 - bit_size: 1 - - name: SRAM3EN - description: "SRAM3 clock enable\r Set and reset by software." - bit_offset: 31 - bit_size: 1 + - name: GPIOAEN + description: "IO port A clock enable\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: "IO port B clock enable\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: "IO port C clock enable\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: "IO port D clock enable\r Set and cleared by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: "IO port E clock enable\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: "IO port F clock enable\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: "IO port G clock enable\r Set and cleared by software." + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: "IO port H clock enable\r Set and cleared by software." + bit_offset: 7 + bit_size: 1 + - name: GPIOIEN + description: "IO port I clock enable\r Set and cleared by software." + bit_offset: 8 + bit_size: 1 + - name: GPIOJEN + description: "I/O port J clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 9 + bit_size: 1 + - name: ADC12EN + description: "ADC1 and ADC2 clock enable\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx." + bit_offset: 10 + bit_size: 1 + - name: DCMIEN + description: "DCMI and PSSI clock enable\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: USB_OTG_FSEN + description: "OTG_FS clock enable\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: USB_OTG_HSEN + description: "OTG_HS clock enable\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: USB_OTG_HS_PHYEN + description: "OTG_HS PHY clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 15 + bit_size: 1 + - name: AESEN + description: "AES clock enable\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: HASHEN + description: "HASH clock enable\r Set and cleared by software" + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: "RNG clock enable\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: PKAEN + description: "PKA clock enable\r Set and cleared by software." + bit_offset: 19 + bit_size: 1 + - name: SAESEN + description: "SAES clock enable\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 + - name: OCTOSPIMEN + description: "OCTOSPIM clock enable\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: OTFDEC1EN + description: "OTFDEC1 clock enable\r Set and cleared by software." + bit_offset: 23 + bit_size: 1 + - name: OTFDEC2EN + description: "OTFDEC2 clock enable\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: SDMMC1EN + description: "SDMMC1 clock enable\r Set and cleared by software." + bit_offset: 27 + bit_size: 1 + - name: SDMMC2EN + description: "SDMMC2 clock enable\r Set and cleared by software." + bit_offset: 28 + bit_size: 1 + - name: SRAM2EN + description: "SRAM2 clock enable\r Set and reset by software." + bit_offset: 30 + bit_size: 1 + - name: SRAM3EN + description: "SRAM3 clock enable\r Set and reset by software." + bit_offset: 31 + bit_size: 1 fieldset/AHB2ENR2: description: RCC AHB2 peripheral clock enable register 2 fields: - - name: FSMCEN - description: "FSMC clock enable\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: OCTOSPI1EN - description: "OCTOSPI1 clock enable\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: OCTOSPI2EN - description: "OCTOSPI2 clock enable\r Set and cleared by software." - bit_offset: 8 - bit_size: 1 - - name: HSPI1EN - description: "HSPI1 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 12 - bit_size: 1 - - name: SRAM6EN - description: "SRAM6 clock enable \r This bit is set and reset by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 30 - bit_size: 1 - - name: SRAM5EN - description: "SRAM5 clock enable \r This bit is set and reset by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 31 - bit_size: 1 + - name: FSMCEN + description: "FSMC clock enable\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: OCTOSPI1EN + description: "OCTOSPI1 clock enable\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: OCTOSPI2EN + description: "OCTOSPI2 clock enable\r Set and cleared by software." + bit_offset: 8 + bit_size: 1 + - name: HSPI1EN + description: "HSPI1 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 12 + bit_size: 1 + - name: SRAM6EN + description: "SRAM6 clock enable \r This bit is set and reset by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 30 + bit_size: 1 + - name: SRAM5EN + description: "SRAM5 clock enable \r This bit is set and reset by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 31 + bit_size: 1 fieldset/AHB2RSTR1: description: RCC AHB2 peripheral reset register 1 fields: - - name: GPIOARST - description: "IO port A reset\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: "IO port B reset\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: "IO port C reset\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: "IO port D reset\r Set and cleared by software." - bit_offset: 3 - bit_size: 1 - - name: GPIOERST - description: "IO port E reset\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: GPIOFRST - description: "IO port F reset\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: GPIOGRST - description: "IO port G reset\r Set and cleared by software." - bit_offset: 6 - bit_size: 1 - - name: GPIOHRST - description: "IO port H reset\r Set and cleared by software." - bit_offset: 7 - bit_size: 1 - - name: GPIOIRST - description: "IO port I reset\r Set and cleared by software." - bit_offset: 8 - bit_size: 1 - - name: GPIOJRST - description: "I/O port J reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 9 - bit_size: 1 - - name: ADC12RST - description: "ADC1 and ADC2 reset\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx." - bit_offset: 10 - bit_size: 1 - - name: DCMIRST - description: "DCMI and PSSI reset\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: USB_OTG_FSRST - description: "OTG_FS reset\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: USB_OTG_HSRST - description: "OTG_HS reset\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: AESRST - description: "AES hardware accelerator reset\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: HASHRST - description: "Hash reset\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: RNGRST - description: "Random number generator reset\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: PKARST - description: "PKA reset\r Set and cleared by software." - bit_offset: 19 - bit_size: 1 - - name: SAESRST - description: "SAES hardware accelerator reset\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 - - name: OCTOSPIMRST - description: "OCTOSPIM reset\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: OTFDEC1RST - description: "OTFDEC1 reset\r Set and cleared by software." - bit_offset: 23 - bit_size: 1 - - name: OTFDEC2RST - description: "OTFDEC2 reset\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: SDMMC1RST - description: "SDMMC1 reset\r Set and cleared by software." - bit_offset: 27 - bit_size: 1 - - name: SDMMC2RST - description: "SDMMC2 reset\r Set and cleared by software." - bit_offset: 28 - bit_size: 1 + - name: GPIOARST + description: "IO port A reset\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: "IO port B reset\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: "IO port C reset\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: "IO port D reset\r Set and cleared by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: "IO port E reset\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: "IO port F reset\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: "IO port G reset\r Set and cleared by software." + bit_offset: 6 + bit_size: 1 + - name: GPIOHRST + description: "IO port H reset\r Set and cleared by software." + bit_offset: 7 + bit_size: 1 + - name: GPIOIRST + description: "IO port I reset\r Set and cleared by software." + bit_offset: 8 + bit_size: 1 + - name: GPIOJRST + description: "I/O port J reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 9 + bit_size: 1 + - name: ADC12RST + description: "ADC1 and ADC2 reset\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx." + bit_offset: 10 + bit_size: 1 + - name: DCMIRST + description: "DCMI and PSSI reset\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: USB_OTG_FSRST + description: "OTG_FS reset\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: USB_OTG_HSRST + description: "OTG_HS reset\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: AESRST + description: "AES hardware accelerator reset\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: HASHRST + description: "Hash reset\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: RNGRST + description: "Random number generator reset\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: PKARST + description: "PKA reset\r Set and cleared by software." + bit_offset: 19 + bit_size: 1 + - name: SAESRST + description: "SAES hardware accelerator reset\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 + - name: OCTOSPIMRST + description: "OCTOSPIM reset\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: OTFDEC1RST + description: "OTFDEC1 reset\r Set and cleared by software." + bit_offset: 23 + bit_size: 1 + - name: OTFDEC2RST + description: "OTFDEC2 reset\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: SDMMC1RST + description: "SDMMC1 reset\r Set and cleared by software." + bit_offset: 27 + bit_size: 1 + - name: SDMMC2RST + description: "SDMMC2 reset\r Set and cleared by software." + bit_offset: 28 + bit_size: 1 fieldset/AHB2RSTR2: description: RCC AHB2 peripheral reset register 2 fields: - - name: FSMCRST - description: "Flexible memory controller reset\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: OCTOSPI1RST - description: "OCTOSPI1 reset\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: OCTOSPI2RST - description: "OCTOSPI2 reset\r Set and cleared by software." - bit_offset: 8 - bit_size: 1 - - name: HSPI1RST - description: "HSPI1 reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 12 - bit_size: 1 + - name: FSMCRST + description: "Flexible memory controller reset\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: OCTOSPI1RST + description: "OCTOSPI1 reset\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: OCTOSPI2RST + description: "OCTOSPI2 reset\r Set and cleared by software." + bit_offset: 8 + bit_size: 1 + - name: HSPI1RST + description: "HSPI1 reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 12 + bit_size: 1 fieldset/AHB2SMENR1: description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1" fields: - - name: GPIOASMEN - description: "IO port A clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: GPIOBSMEN - description: "IO port B clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: GPIOCSMEN - description: "IO port C clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: GPIODSMEN - description: "IO port D clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 3 - bit_size: 1 - - name: GPIOESMEN - description: "IO port E clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: GPIOFSMEN - description: "IO port F clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: GPIOGSMEN - description: "IO port G clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 6 - bit_size: 1 - - name: GPIOHSMEN - description: "IO port H clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 7 - bit_size: 1 - - name: GPIOISMEN - description: "IO port I clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 8 - bit_size: 1 - - name: GPIOJSMEN - description: "I/O port J clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 9 - bit_size: 1 - - name: ADC12SMEN - description: "ADC1 and ADC2 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585 and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx." - bit_offset: 10 - bit_size: 1 - - name: DCMISMEN - description: "DCMI and PSSI clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: USB_OTG_FSSMEN - description: "OTG_FS clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: USB_OTG_HSSMEN - description: "OTG_HS clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: USB_OTG_HS_PHYSMEN - description: "OTG_HS PHY clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 15 - bit_size: 1 - - name: AESSMEN - description: "AES clock enable during Sleep and Stop modes\r Set and cleared by software" - bit_offset: 16 - bit_size: 1 - - name: HASHSMEN - description: "HASH clock enable during Sleep and Stop modes\r Set and cleared by software" - bit_offset: 17 - bit_size: 1 - - name: RNGSMEN - description: "Random number generator (RNG) clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: PKASMEN - description: "PKA clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 19 - bit_size: 1 - - name: SAESSMEN - description: "SAES accelerator clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 - - name: OCTOSPIMSMEN - description: "OCTOSPIM clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: OTFDEC1SMEN - description: "OTFDEC1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 23 - bit_size: 1 - - name: OTFDEC2SMEN - description: "OTFDEC2 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: SDMMC1SMEN - description: "SDMMC1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 27 - bit_size: 1 - - name: SDMMC2SMEN - description: "SDMMC2 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 28 - bit_size: 1 - - name: SRAM2SMEN - description: "SRAM2 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 30 - bit_size: 1 - - name: SRAM3SMEN - description: "SRAM3 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 31 - bit_size: 1 + - name: GPIOASMEN + description: "IO port A clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: "IO port B clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: "IO port C clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODSMEN + description: "IO port D clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOESMEN + description: "IO port E clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: GPIOFSMEN + description: "IO port F clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: GPIOGSMEN + description: "IO port G clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 6 + bit_size: 1 + - name: GPIOHSMEN + description: "IO port H clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 7 + bit_size: 1 + - name: GPIOISMEN + description: "IO port I clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 8 + bit_size: 1 + - name: GPIOJSMEN + description: "I/O port J clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 9 + bit_size: 1 + - name: ADC12SMEN + description: "ADC1 and ADC2 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585 and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx." + bit_offset: 10 + bit_size: 1 + - name: DCMISMEN + description: "DCMI and PSSI clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: USB_OTG_FSSMEN + description: "OTG_FS clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: USB_OTG_HSSMEN + description: "OTG_HS clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: USB_OTG_HS_PHYSMEN + description: "OTG_HS PHY clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 15 + bit_size: 1 + - name: AESSMEN + description: "AES clock enable during Sleep and Stop modes\r Set and cleared by software" + bit_offset: 16 + bit_size: 1 + - name: HASHSMEN + description: "HASH clock enable during Sleep and Stop modes\r Set and cleared by software" + bit_offset: 17 + bit_size: 1 + - name: RNGSMEN + description: "Random number generator (RNG) clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: PKASMEN + description: "PKA clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 19 + bit_size: 1 + - name: SAESSMEN + description: "SAES accelerator clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 + - name: OCTOSPIMSMEN + description: "OCTOSPIM clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: OTFDEC1SMEN + description: "OTFDEC1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 23 + bit_size: 1 + - name: OTFDEC2SMEN + description: "OTFDEC2 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: SDMMC1SMEN + description: "SDMMC1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 27 + bit_size: 1 + - name: SDMMC2SMEN + description: "SDMMC2 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 28 + bit_size: 1 + - name: SRAM2SMEN + description: "SRAM2 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 30 + bit_size: 1 + - name: SRAM3SMEN + description: "SRAM3 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 31 + bit_size: 1 fieldset/AHB2SMENR2: description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2" fields: - - name: FSMCSMEN - description: "FSMC clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: OCTOSPI1SMEN - description: "OCTOSPI1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: OCTOSPI2SMEN - description: "OCTOSPI2 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 8 - bit_size: 1 - - name: HSPI1SMEN - description: "HSPI1 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 12 - bit_size: 1 - - name: SRAM6SMEN - description: "SRAM6 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 30 - bit_size: 1 - - name: SRAM5SMEN - description: "SRAM5 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 31 - bit_size: 1 + - name: FSMCSMEN + description: "FSMC clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: OCTOSPI1SMEN + description: "OCTOSPI1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: OCTOSPI2SMEN + description: "OCTOSPI2 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 8 + bit_size: 1 + - name: HSPI1SMEN + description: "HSPI1 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 12 + bit_size: 1 + - name: SRAM6SMEN + description: "SRAM6 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 30 + bit_size: 1 + - name: SRAM5SMEN + description: "SRAM5 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 31 + bit_size: 1 fieldset/AHB3ENR: description: RCC AHB3 peripheral clock enable register fields: - - name: LPGPIO1EN - description: "LPGPIO1 enable\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: PWREN - description: "PWR clock enable\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: ADC4EN - description: "ADC4 clock enable\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: DAC1EN - description: "DAC1 clock enable\r Set and cleared by software." - bit_offset: 6 - bit_size: 1 - - name: LPDMA1EN - description: "LPDMA1 clock enable\r Set and cleared by software." - bit_offset: 9 - bit_size: 1 - - name: ADF1EN - description: "ADF1 clock enable\r Set and cleared by software." - bit_offset: 10 - bit_size: 1 - - name: GTZC2EN - description: "GTZC2 clock enable\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: SRAM4EN - description: "SRAM4 clock enable\r Set and reset by software." - bit_offset: 31 - bit_size: 1 + - name: LPGPIO1EN + description: "LPGPIO1 enable\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: PWREN + description: "PWR clock enable\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: ADC4EN + description: "ADC4 clock enable\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: DAC1EN + description: "DAC1 clock enable\r Set and cleared by software." + bit_offset: 6 + bit_size: 1 + - name: LPDMA1EN + description: "LPDMA1 clock enable\r Set and cleared by software." + bit_offset: 9 + bit_size: 1 + - name: ADF1EN + description: "ADF1 clock enable\r Set and cleared by software." + bit_offset: 10 + bit_size: 1 + - name: GTZC2EN + description: "GTZC2 clock enable\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: SRAM4EN + description: "SRAM4 clock enable\r Set and reset by software." + bit_offset: 31 + bit_size: 1 fieldset/AHB3RSTR: description: RCC AHB3 peripheral reset register fields: - - name: LPGPIO1RST - description: "LPGPIO1 reset\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: ADC4RST - description: "ADC4 reset\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: DAC1RST - description: "DAC1 reset\r Set and cleared by software." - bit_offset: 6 - bit_size: 1 - - name: LPDMA1RST - description: "LPDMA1 reset\r Set and cleared by software." - bit_offset: 9 - bit_size: 1 - - name: ADF1RST - description: "ADF1 reset\r Set and cleared by software." - bit_offset: 10 - bit_size: 1 + - name: LPGPIO1RST + description: "LPGPIO1 reset\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: ADC4RST + description: "ADC4 reset\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: DAC1RST + description: "DAC1 reset\r Set and cleared by software." + bit_offset: 6 + bit_size: 1 + - name: LPDMA1RST + description: "LPDMA1 reset\r Set and cleared by software." + bit_offset: 9 + bit_size: 1 + - name: ADF1RST + description: "ADF1 reset\r Set and cleared by software." + bit_offset: 10 + bit_size: 1 fieldset/AHB3SMENR: description: RCC AHB3 peripheral clocks enable in Sleep and Stop modes register fields: - - name: LPGPIO1SMEN - description: "LPGPIO1 enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: PWRSMEN - description: "PWR clock enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: ADC4SMEN - description: "ADC4 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 5 - bit_size: 1 - - name: DAC1SMEN - description: "DAC1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 6 - bit_size: 1 - - name: LPDMA1SMEN - description: "LPDMA1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 9 - bit_size: 1 - - name: ADF1SMEN - description: "ADF1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 10 - bit_size: 1 - - name: GTZC2SMEN - description: "GTZC2 clock enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: SRAM4SMEN - description: "SRAM4 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 31 - bit_size: 1 + - name: LPGPIO1SMEN + description: "LPGPIO1 enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: PWRSMEN + description: "PWR clock enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: ADC4SMEN + description: "ADC4 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 5 + bit_size: 1 + - name: DAC1SMEN + description: "DAC1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 6 + bit_size: 1 + - name: LPDMA1SMEN + description: "LPDMA1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 9 + bit_size: 1 + - name: ADF1SMEN + description: "ADF1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 10 + bit_size: 1 + - name: GTZC2SMEN + description: "GTZC2 clock enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: SRAM4SMEN + description: "SRAM4 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 31 + bit_size: 1 fieldset/APB1ENR1: description: RCC APB1 peripheral clock enable register 1 fields: - - name: TIM2EN - description: "TIM2 clock enable\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: "TIM3 clock enable\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: "TIM4 clock enable\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: "TIM5 clock enable\r Set and cleared by software." - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: "TIM6 clock enable\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: "TIM7 clock enable\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: WWDGEN - description: "WWDG clock enable\r Set by software to enable the window watchdog clock. Reset by hardware system reset.\r This bit can also be set by hardware if the WWDG_SW option bit is reset." - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: "SPI2 clock enable\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: USART2EN - description: "USART2 clock enable\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: "USART3 clock enable\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: "UART4 clock enable\r Set and cleared by software." - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: "UART5 clock enable\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: "I2C1 clock enable\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: "I2C2 clock enable\r Set and cleared by software." - bit_offset: 22 - bit_size: 1 - - name: CRSEN - description: "CRS clock enable\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: USART6EN - description: "USART6 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 25 - bit_size: 1 + - name: TIM2EN + description: "TIM2 clock enable\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: "TIM3 clock enable\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: "TIM4 clock enable\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: "TIM5 clock enable\r Set and cleared by software." + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: "TIM6 clock enable\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: "TIM7 clock enable\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: WWDGEN + description: "WWDG clock enable\r Set by software to enable the window watchdog clock. Reset by hardware system reset.\r This bit can also be set by hardware if the WWDG_SW option bit is reset." + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: "SPI2 clock enable\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: USART2EN + description: "USART2 clock enable\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: "USART3 clock enable\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: "UART4 clock enable\r Set and cleared by software." + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: "UART5 clock enable\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: "I2C1 clock enable\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: "I2C2 clock enable\r Set and cleared by software." + bit_offset: 22 + bit_size: 1 + - name: CRSEN + description: "CRS clock enable\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: USART6EN + description: "USART6 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 25 + bit_size: 1 fieldset/APB1ENR2: description: RCC APB1 peripheral clock enable register 2 fields: - - name: I2C4EN - description: "I2C4 clock enable\r Set and cleared by software" - bit_offset: 1 - bit_size: 1 - - name: LPTIM2EN - description: "LPTIM2 clock enable\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: I2C5EN - description: "I2C5 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 6 - bit_size: 1 - - name: I2C6EN - description: "I2C6 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 7 - bit_size: 1 - - name: FDCAN1EN - description: "FDCAN1 clock enable\r Set and cleared by software." - bit_offset: 9 - bit_size: 1 - - name: UCPD1EN - description: "UCPD1 clock enable\r Set and cleared by software." - bit_offset: 23 - bit_size: 1 + - name: I2C4EN + description: "I2C4 clock enable\r Set and cleared by software" + bit_offset: 1 + bit_size: 1 + - name: LPTIM2EN + description: "LPTIM2 clock enable\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: I2C5EN + description: "I2C5 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 6 + bit_size: 1 + - name: I2C6EN + description: "I2C6 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 7 + bit_size: 1 + - name: FDCAN1EN + description: "FDCAN1 clock enable\r Set and cleared by software." + bit_offset: 9 + bit_size: 1 + - name: UCPD1EN + description: "UCPD1 clock enable\r Set and cleared by software." + bit_offset: 23 + bit_size: 1 fieldset/APB1RSTR1: description: RCC APB1 peripheral reset register 1 fields: - - name: TIM2RST - description: "TIM2 reset\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: "TIM3 reset\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: "TIM4 reset\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: "TIM5 reset\r Set and cleared by software." - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: "TIM6 reset\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: "TIM7 reset\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: SPI2RST - description: "SPI2 reset\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: USART2RST - description: "USART2 reset\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: "USART3 reset\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: "UART4 reset\r Set and cleared by software." - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: "UART5 reset\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: "I2C1 reset\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: "I2C2 reset\r Set and cleared by software." - bit_offset: 22 - bit_size: 1 - - name: CRSRST - description: "CRS reset\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: USART6RST - description: "USART6 reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 25 - bit_size: 1 + - name: TIM2RST + description: "TIM2 reset\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: "TIM3 reset\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: "TIM4 reset\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: "TIM5 reset\r Set and cleared by software." + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: "TIM6 reset\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: "TIM7 reset\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: SPI2RST + description: "SPI2 reset\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: USART2RST + description: "USART2 reset\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: "USART3 reset\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: "UART4 reset\r Set and cleared by software." + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: "UART5 reset\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: "I2C1 reset\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: "I2C2 reset\r Set and cleared by software." + bit_offset: 22 + bit_size: 1 + - name: CRSRST + description: "CRS reset\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: USART6RST + description: "USART6 reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 25 + bit_size: 1 fieldset/APB1RSTR2: description: RCC APB1 peripheral reset register 2 fields: - - name: I2C4RST - description: "I2C4 reset\r Set and cleared by software" - bit_offset: 1 - bit_size: 1 - - name: LPTIM2RST - description: "LPTIM2 reset\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: I2C5RST - description: "I2C5 reset\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 6 - bit_size: 1 - - name: I2C6RST - description: "I2C6 reset\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 7 - bit_size: 1 - - name: FDCAN1RST - description: "FDCAN1 reset\r Set and cleared by software." - bit_offset: 9 - bit_size: 1 - - name: UCPD1RST - description: "UCPD1 reset\r Set and cleared by software." - bit_offset: 23 - bit_size: 1 + - name: I2C4RST + description: "I2C4 reset\r Set and cleared by software" + bit_offset: 1 + bit_size: 1 + - name: LPTIM2RST + description: "LPTIM2 reset\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: I2C5RST + description: "I2C5 reset\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 6 + bit_size: 1 + - name: I2C6RST + description: "I2C6 reset\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 7 + bit_size: 1 + - name: FDCAN1RST + description: "FDCAN1 reset\r Set and cleared by software." + bit_offset: 9 + bit_size: 1 + - name: UCPD1RST + description: "UCPD1 reset\r Set and cleared by software." + bit_offset: 23 + bit_size: 1 fieldset/APB1SMENR1: description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1" fields: - - name: TIM2SMEN - description: "TIM2 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: TIM3SMEN - description: "TIM3 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: TIM4SMEN - description: "TIM4 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: TIM5SMEN - description: "TIM5 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 3 - bit_size: 1 - - name: TIM6SMEN - description: "TIM6 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: TIM7SMEN - description: "TIM7 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: WWDGSMEN - description: "Window watchdog clocks enable during Sleep and Stop modes\r Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated." - bit_offset: 11 - bit_size: 1 - - name: SPI2SMEN - description: "SPI2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 14 - bit_size: 1 - - name: USART2SMEN - description: "USART2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 17 - bit_size: 1 - - name: USART3SMEN - description: "USART3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 18 - bit_size: 1 - - name: UART4SMEN - description: "UART4 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 19 - bit_size: 1 - - name: UART5SMEN - description: "UART5 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 20 - bit_size: 1 - - name: I2C1SMEN - description: "I2C1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 21 - bit_size: 1 - - name: I2C2SMEN - description: "I2C2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 22 - bit_size: 1 - - name: CRSSMEN - description: "CRS clock enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: USART6SMEN - description: "USART6 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 25 - bit_size: 1 + - name: TIM2SMEN + description: "TIM2 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3SMEN + description: "TIM3 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: TIM4SMEN + description: "TIM4 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: TIM5SMEN + description: "TIM5 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 3 + bit_size: 1 + - name: TIM6SMEN + description: "TIM6 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7SMEN + description: "TIM7 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: WWDGSMEN + description: "Window watchdog clocks enable during Sleep and Stop modes\r Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated." + bit_offset: 11 + bit_size: 1 + - name: SPI2SMEN + description: "SPI2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 14 + bit_size: 1 + - name: USART2SMEN + description: "USART2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 17 + bit_size: 1 + - name: USART3SMEN + description: "USART3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 18 + bit_size: 1 + - name: UART4SMEN + description: "UART4 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 19 + bit_size: 1 + - name: UART5SMEN + description: "UART5 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 20 + bit_size: 1 + - name: I2C1SMEN + description: "I2C1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: "I2C2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 22 + bit_size: 1 + - name: CRSSMEN + description: "CRS clock enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: USART6SMEN + description: "USART6 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 25 + bit_size: 1 fieldset/APB1SMENR2: description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2" fields: - - name: I2C4SMEN - description: "I2C4 clocks enable during Sleep and Stop modes\r Set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 1 - bit_size: 1 - - name: LPTIM2SMEN - description: "LPTIM2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 5 - bit_size: 1 - - name: I2C5SMEN - description: "I2C5 clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 6 - bit_size: 1 - - name: I2C6SMEN - description: "I2C6 clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 7 - bit_size: 1 - - name: FDCAN1SMEN - description: "FDCAN1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 9 - bit_size: 1 - - name: UCPD1SMEN - description: "UCPD1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 23 - bit_size: 1 + - name: I2C4SMEN + description: "I2C4 clocks enable during Sleep and Stop modes\r Set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 1 + bit_size: 1 + - name: LPTIM2SMEN + description: "LPTIM2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 5 + bit_size: 1 + - name: I2C5SMEN + description: "I2C5 clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 6 + bit_size: 1 + - name: I2C6SMEN + description: "I2C6 clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 7 + bit_size: 1 + - name: FDCAN1SMEN + description: "FDCAN1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 9 + bit_size: 1 + - name: UCPD1SMEN + description: "UCPD1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 23 + bit_size: 1 fieldset/APB2ENR: description: RCC APB2 peripheral clock enable register fields: - - name: TIM1EN - description: "TIM1 clock enable\r Set and cleared by software." - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: "SPI1 clock enable\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: TIM8EN - description: "TIM8 clock enable\r Set and cleared by software." - bit_offset: 13 - bit_size: 1 - - name: USART1EN - description: "USART1clock enable\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: TIM15EN - description: "TIM15 clock enable\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: "TIM16 clock enable\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: "TIM17 clock enable\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: SAI1EN - description: "SAI1 clock enable\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: SAI2EN - description: "SAI2 clock enable\r Set and cleared by software." - bit_offset: 22 - bit_size: 1 - - name: USBEN - description: "USB clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 24 - bit_size: 1 - - name: GFXTIMEN - description: "GFXTIM clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 25 - bit_size: 1 - - name: LTDCEN - description: "LTDC clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 26 - bit_size: 1 - - name: DSIEN - description: "DSI clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 27 - bit_size: 1 + - name: TIM1EN + description: "TIM1 clock enable\r Set and cleared by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: "SPI1 clock enable\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: TIM8EN + description: "TIM8 clock enable\r Set and cleared by software." + bit_offset: 13 + bit_size: 1 + - name: USART1EN + description: "USART1clock enable\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: TIM15EN + description: "TIM15 clock enable\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: "TIM16 clock enable\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: "TIM17 clock enable\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: SAI1EN + description: "SAI1 clock enable\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: SAI2EN + description: "SAI2 clock enable\r Set and cleared by software." + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: "USB clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 24 + bit_size: 1 + - name: GFXTIMEN + description: "GFXTIM clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 25 + bit_size: 1 + - name: LTDCEN + description: "LTDC clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 26 + bit_size: 1 + - name: DSIEN + description: "DSI clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 27 + bit_size: 1 fieldset/APB2RSTR: description: RCC APB2 peripheral reset register fields: - - name: TIM1RST - description: "TIM1 reset\r Set and cleared by software." - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: "SPI1 reset\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: TIM8RST - description: "TIM8 reset\r Set and cleared by software." - bit_offset: 13 - bit_size: 1 - - name: USART1RST - description: "USART1 reset\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: TIM15RST - description: "TIM15 reset\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: TIM16RST - description: "TIM16 reset\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: "TIM17 reset\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: SAI1RST - description: "SAI1 reset\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: SAI2RST - description: "SAI2 reset\r Set and cleared by software." - bit_offset: 22 - bit_size: 1 - - name: USBRST - description: "USB reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 24 - bit_size: 1 - - name: GFXTIMRST - description: "GFXTIM reset\r This bit is set and cleared by software.\r Note: .This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 25 - bit_size: 1 - - name: LTDCRST - description: "LTDC reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 26 - bit_size: 1 - - name: DSIRST - description: "DSI reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 27 - bit_size: 1 + - name: TIM1RST + description: "TIM1 reset\r Set and cleared by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: "SPI1 reset\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: TIM8RST + description: "TIM8 reset\r Set and cleared by software." + bit_offset: 13 + bit_size: 1 + - name: USART1RST + description: "USART1 reset\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: TIM15RST + description: "TIM15 reset\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: "TIM16 reset\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: "TIM17 reset\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: SAI1RST + description: "SAI1 reset\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: SAI2RST + description: "SAI2 reset\r Set and cleared by software." + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: "USB reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 24 + bit_size: 1 + - name: GFXTIMRST + description: "GFXTIM reset\r This bit is set and cleared by software.\r Note: .This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 25 + bit_size: 1 + - name: LTDCRST + description: "LTDC reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 26 + bit_size: 1 + - name: DSIRST + description: "DSI reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 27 + bit_size: 1 fieldset/APB2SMENR: description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register fields: - - name: TIM1SMEN - description: "TIM1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 11 - bit_size: 1 - - name: SPI1SMEN - description: "SPI1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 12 - bit_size: 1 - - name: TIM8SMEN - description: "TIM8 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 13 - bit_size: 1 - - name: USART1SMEN - description: "USART1clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 14 - bit_size: 1 - - name: TIM15SMEN - description: "TIM15 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: TIM16SMEN - description: "TIM16 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: TIM17SMEN - description: "TIM17 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: SAI1SMEN - description: "SAI1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: SAI2SMEN - description: "SAI2 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 22 - bit_size: 1 - - name: USBSMEN - description: "USB clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 24 - bit_size: 1 - - name: GFXTIMSMEN - description: "GFXTIM clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 25 - bit_size: 1 - - name: LTDCSMEN - description: "LTDC clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 26 - bit_size: 1 - - name: DSISMEN - description: "DSI clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 27 - bit_size: 1 + - name: TIM1SMEN + description: "TIM1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: "SPI1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 12 + bit_size: 1 + - name: TIM8SMEN + description: "TIM8 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 13 + bit_size: 1 + - name: USART1SMEN + description: "USART1clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 14 + bit_size: 1 + - name: TIM15SMEN + description: "TIM15 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: TIM16SMEN + description: "TIM16 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: "TIM17 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: SAI1SMEN + description: "SAI1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: SAI2SMEN + description: "SAI2 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 22 + bit_size: 1 + - name: USBSMEN + description: "USB clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 24 + bit_size: 1 + - name: GFXTIMSMEN + description: "GFXTIM clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 25 + bit_size: 1 + - name: LTDCSMEN + description: "LTDC clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 26 + bit_size: 1 + - name: DSISMEN + description: "DSI clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 27 + bit_size: 1 fieldset/APB3ENR: description: RCC APB3 peripheral clock enable register fields: - - name: SYSCFGEN - description: "SYSCFG clock enable\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: SPI3EN - description: "SPI3 clock enable\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: LPUART1EN - description: "LPUART1 clock enable\r Set and cleared by software." - bit_offset: 6 - bit_size: 1 - - name: I2C3EN - description: "I2C3 clock enable\r Set and cleared by software." - bit_offset: 7 - bit_size: 1 - - name: LPTIM1EN - description: "LPTIM1 clock enable\r Set and cleared by software." - bit_offset: 11 - bit_size: 1 - - name: LPTIM3EN - description: "LPTIM3 clock enable\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: LPTIM4EN - description: "LPTIM4 clock enable\r Set and cleared by software." - bit_offset: 13 - bit_size: 1 - - name: OPAMPEN - description: "OPAMP clock enable\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: COMPEN - description: "COMP clock enable\r Set and cleared by software." - bit_offset: 15 - bit_size: 1 - - name: VREFEN - description: "VREFBUF clock enable\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 - - name: RTCAPBEN - description: "RTC and TAMP APB clock enable\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 + - name: SYSCFGEN + description: "SYSCFG clock enable\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: SPI3EN + description: "SPI3 clock enable\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: LPUART1EN + description: "LPUART1 clock enable\r Set and cleared by software." + bit_offset: 6 + bit_size: 1 + - name: I2C3EN + description: "I2C3 clock enable\r Set and cleared by software." + bit_offset: 7 + bit_size: 1 + - name: LPTIM1EN + description: "LPTIM1 clock enable\r Set and cleared by software." + bit_offset: 11 + bit_size: 1 + - name: LPTIM3EN + description: "LPTIM3 clock enable\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: LPTIM4EN + description: "LPTIM4 clock enable\r Set and cleared by software." + bit_offset: 13 + bit_size: 1 + - name: OPAMPEN + description: "OPAMP clock enable\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: COMPEN + description: "COMP clock enable\r Set and cleared by software." + bit_offset: 15 + bit_size: 1 + - name: VREFEN + description: "VREFBUF clock enable\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 + - name: RTCAPBEN + description: "RTC and TAMP APB clock enable\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 fieldset/APB3RSTR: description: RCC APB3 peripheral reset register fields: - - name: SYSCFGRST - description: "SYSCFG reset\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: SPI3RST - description: "SPI3 reset\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: LPUART1RST - description: "LPUART1 reset\r Set and cleared by software." - bit_offset: 6 - bit_size: 1 - - name: I2C3RST - description: "I2C3 reset\r Set and cleared by software." - bit_offset: 7 - bit_size: 1 - - name: LPTIM1RST - description: "LPTIM1 reset\r Set and cleared by software." - bit_offset: 11 - bit_size: 1 - - name: LPTIM3RST - description: "LPTIM3 reset\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: LPTIM4RST - description: "LPTIM4 reset\r Set and cleared by software." - bit_offset: 13 - bit_size: 1 - - name: OPAMPRST - description: "OPAMP reset\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: COMPRST - description: "COMP reset\r Set and cleared by software." - bit_offset: 15 - bit_size: 1 - - name: VREFRST - description: "VREFBUF reset\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 + - name: SYSCFGRST + description: "SYSCFG reset\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: SPI3RST + description: "SPI3 reset\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: LPUART1RST + description: "LPUART1 reset\r Set and cleared by software." + bit_offset: 6 + bit_size: 1 + - name: I2C3RST + description: "I2C3 reset\r Set and cleared by software." + bit_offset: 7 + bit_size: 1 + - name: LPTIM1RST + description: "LPTIM1 reset\r Set and cleared by software." + bit_offset: 11 + bit_size: 1 + - name: LPTIM3RST + description: "LPTIM3 reset\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: LPTIM4RST + description: "LPTIM4 reset\r Set and cleared by software." + bit_offset: 13 + bit_size: 1 + - name: OPAMPRST + description: "OPAMP reset\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: COMPRST + description: "COMP reset\r Set and cleared by software." + bit_offset: 15 + bit_size: 1 + - name: VREFRST + description: "VREFBUF reset\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 fieldset/APB3SMENR: description: RCC APB3 peripheral clock enable in Sleep and Stop modes register fields: - - name: SYSCFGSMEN - description: "SYSCFG clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: SPI3SMEN - description: "SPI3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 5 - bit_size: 1 - - name: LPUART1SMEN - description: "LPUART1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 6 - bit_size: 1 - - name: I2C3SMEN - description: "I2C3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 7 - bit_size: 1 - - name: LPTIM1SMEN - description: "LPTIM1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 11 - bit_size: 1 - - name: LPTIM3SMEN - description: "LPTIM3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 12 - bit_size: 1 - - name: LPTIM4SMEN - description: "LPTIM4 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 13 - bit_size: 1 - - name: OPAMPSMEN - description: "OPAMP clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: COMPSMEN - description: "COMP clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 15 - bit_size: 1 - - name: VREFSMEN - description: "VREFBUF clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 - - name: RTCAPBSMEN - description: "RTC and TAMP APB clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 21 - bit_size: 1 + - name: SYSCFGSMEN + description: "SYSCFG clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: SPI3SMEN + description: "SPI3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 5 + bit_size: 1 + - name: LPUART1SMEN + description: "LPUART1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 6 + bit_size: 1 + - name: I2C3SMEN + description: "I2C3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 7 + bit_size: 1 + - name: LPTIM1SMEN + description: "LPTIM1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 11 + bit_size: 1 + - name: LPTIM3SMEN + description: "LPTIM3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 12 + bit_size: 1 + - name: LPTIM4SMEN + description: "LPTIM4 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 13 + bit_size: 1 + - name: OPAMPSMEN + description: "OPAMP clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: COMPSMEN + description: "COMP clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 15 + bit_size: 1 + - name: VREFSMEN + description: "VREFBUF clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 + - name: RTCAPBSMEN + description: "RTC and TAMP APB clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 21 + bit_size: 1 fieldset/BDCR: description: RCC Backup domain control register fields: - - name: LSEON - description: "LSE oscillator enable\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: "LSE oscillator ready\r Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles." - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: "LSE oscillator bypass\r Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0)." - bit_offset: 2 - bit_size: 1 - - name: LSEDRV - description: "LSE oscillator drive capability\r Set by software to modulate the drive capability of the LSE oscillator. This field can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).\r Note: The oscillator is in 'Xtal mode when it is not in bypass mode." - bit_offset: 3 - bit_size: 2 - enum: LSEDRV - - name: LSECSSON - description: "CSS on LSE enable\r Set by software to enable the CSS on LSE. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case, the software must disable the LSECSSON bit." - bit_offset: 5 - bit_size: 1 - - name: LSECSSD - description: "CSS on LSE failure Detection\r Set by hardware to indicate when a failure is detected by the CCS on the external 32 kHz oscillator (LSE)." - bit_offset: 6 - bit_size: 1 - - name: LSESYSEN - description: "LSE system clock (LSESYS) enable\r Set by software to enable always the LSE system clock generated by RCC. This clock can be used by any peripheral when its source clock is the LSE or at system level in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed.\r The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by the CSS on LSE, by a peripheral or any other source clock using LSE." - bit_offset: 7 - bit_size: 1 - - name: RTCSEL - description: "RTC and TAMP clock source selection\r Set by software to select the clock source for the RTC and TAMP . Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them." - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: LSESYSRDY - description: "LSE system clock (LSESYS) ready\r Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles.\r The LSE clock must be already enabled and stable (LSEON and LSERDY are set).\r When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles." - bit_offset: 11 - bit_size: 1 - - name: LSEGFON - description: "LSE clock glitch filter enable\r Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0)" - bit_offset: 12 - bit_size: 1 - - name: RTCEN - description: "RTC and TAMP clock enable\r Set and cleared by software." - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: "Backup domain software reset\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: LSCOEN - description: "Low-speed clock output (LSCO) enable\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: LSCOSEL - description: "Low-speed clock output selection\r Set and cleared by software." - bit_offset: 25 - bit_size: 1 - enum: LSCOSEL - - name: LSION - description: "LSI oscillator enable\r Set and cleared by software." - bit_offset: 26 - bit_size: 1 - - name: LSIRDY - description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0." - bit_offset: 27 - bit_size: 1 - - name: LSIPREDIV - description: "Low-speed clock divider configuration\r Set and cleared by software to enable the LSI division. This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC." - bit_offset: 28 - bit_size: 1 - enum: LSIPREDIV + - name: LSEON + description: "LSE oscillator enable\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: "LSE oscillator ready\r Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles." + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: "LSE oscillator bypass\r Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0)." + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: "LSE oscillator drive capability\r Set by software to modulate the drive capability of the LSE oscillator. This field can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).\r Note: The oscillator is in 'Xtal mode when it is not in bypass mode." + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: "CSS on LSE enable\r Set by software to enable the CSS on LSE. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case, the software must disable the LSECSSON bit." + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: "CSS on LSE failure Detection\r Set by hardware to indicate when a failure is detected by the CCS on the external 32 kHz oscillator (LSE)." + bit_offset: 6 + bit_size: 1 + - name: LSESYSEN + description: "LSE system clock (LSESYS) enable\r Set by software to enable always the LSE system clock generated by RCC. This clock can be used by any peripheral when its source clock is the LSE or at system level in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed.\r The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by the CSS on LSE, by a peripheral or any other source clock using LSE." + bit_offset: 7 + bit_size: 1 + - name: RTCSEL + description: "RTC and TAMP clock source selection\r Set by software to select the clock source for the RTC and TAMP . Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them." + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: LSESYSRDY + description: "LSE system clock (LSESYS) ready\r Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles.\r The LSE clock must be already enabled and stable (LSEON and LSERDY are set).\r When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles." + bit_offset: 11 + bit_size: 1 + - name: LSEGFON + description: "LSE clock glitch filter enable\r Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0)" + bit_offset: 12 + bit_size: 1 + - name: RTCEN + description: "RTC and TAMP clock enable\r Set and cleared by software." + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: "Backup domain software reset\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: "Low-speed clock output (LSCO) enable\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: "Low-speed clock output selection\r Set and cleared by software." + bit_offset: 25 + bit_size: 1 + enum: LSCOSEL + - name: LSION + description: "LSI oscillator enable\r Set and cleared by software." + bit_offset: 26 + bit_size: 1 + - name: LSIRDY + description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0." + bit_offset: 27 + bit_size: 1 + - name: LSIPREDIV + description: "Low-speed clock divider configuration\r Set and cleared by software to enable the LSI division. This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC." + bit_offset: 28 + bit_size: 1 + enum: LSIPREDIV fieldset/CCIPR1: description: RCC peripherals independent clock configuration register 1 fields: - - name: USART1SEL - description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." - bit_offset: 0 - bit_size: 2 - enum: USARTSEL - - name: USART2SEL - description: "USART2 kernel clock source selection\r This bits are used to select the USART2 kernel clock source.\r Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." - bit_offset: 2 - bit_size: 2 - enum: USARTSEL - - name: USART3SEL - description: "USART3 kernel clock source selection\r This bits are used to select the USART3 kernel clock source.\r Note: The USART3 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." - bit_offset: 4 - bit_size: 2 - enum: USARTSEL - - name: UART4SEL - description: "UART4 kernel clock source selection\r This bits are used to select the UART4 kernel clock source.\r Note: The UART4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." - bit_offset: 6 - bit_size: 2 - enum: UARTSEL - - name: UART5SEL - description: "UART5 kernel clock source selection\r These bits are used to select the UART5 kernel clock source.\r Note: The UART5 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." - bit_offset: 8 - bit_size: 2 - enum: UARTSEL - - name: I2C1SEL - description: "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." - bit_offset: 10 - bit_size: 2 - enum: ICSEL - - name: I2C2SEL - description: "I2C2 kernel clock source selection\r These bits are used to select the I2C2 kernel clock source.\r Note: The I2C2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." - bit_offset: 12 - bit_size: 2 - enum: ICSEL - - name: I2C4SEL - description: "I2C4 kernel clock source selection\r These bits are used to select the I2C4 kernel clock source.\r Note: The I2C4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." - bit_offset: 14 - bit_size: 2 - enum: ICSEL - - name: SPI2SEL - description: "SPI2 kernel clock source selection\r These bits are used to select the SPI2 kernel clock source.\r Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." - bit_offset: 16 - bit_size: 2 - enum: SPISEL - - name: LPTIM2SEL - description: "Low-power timer 2 kernel clock source selection\r These bits are used to select the LPTIM2 kernel clock source.\r Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1." - bit_offset: 18 - bit_size: 2 - enum: LPTIMSEL - - name: SPI1SEL - description: "SPI1 kernel clock source selection\r These bits are used to select the SPI1 kernel clock source.\r Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." - bit_offset: 20 - bit_size: 2 - enum: SPISEL - - name: SYSTICKSEL - description: "SysTick clock source selection\r These bits are used to select the SysTick clock source.\r Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry." - bit_offset: 22 - bit_size: 2 - enum: SYSTICKSEL - - name: FDCAN1SEL - description: "FDCAN1 kernel clock source selection\r These bits are used to select the FDCAN1 kernel clock source." - bit_offset: 24 - bit_size: 2 - enum: FDCANSEL - - name: ICLKSEL - description: "intermediate clock source selection\r These bits are used to select the clock source used by OTG_FS and SDMMC." - bit_offset: 26 - bit_size: 2 - enum: ICLKSEL - - name: TIMICSEL - description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture\r When the TIMICSEL2 bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4 or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS.\r When TIMICSEL2 is cleared, the HSI, MSIK and MSIS clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r 0xx: HSI, MSIK and MSIS dividers disabled\r Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division." - bit_offset: 29 - bit_size: 3 - enum: TIMICSEL + - name: USART1SEL + description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." + bit_offset: 0 + bit_size: 2 + enum: USARTSEL + - name: USART2SEL + description: "USART2 kernel clock source selection\r This bits are used to select the USART2 kernel clock source.\r Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." + bit_offset: 2 + bit_size: 2 + enum: USARTSEL + - name: USART3SEL + description: "USART3 kernel clock source selection\r This bits are used to select the USART3 kernel clock source.\r Note: The USART3 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." + bit_offset: 4 + bit_size: 2 + enum: USARTSEL + - name: UART4SEL + description: "UART4 kernel clock source selection\r This bits are used to select the UART4 kernel clock source.\r Note: The UART4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." + bit_offset: 6 + bit_size: 2 + enum: UARTSEL + - name: UART5SEL + description: "UART5 kernel clock source selection\r These bits are used to select the UART5 kernel clock source.\r Note: The UART5 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." + bit_offset: 8 + bit_size: 2 + enum: UARTSEL + - name: I2C1SEL + description: "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." + bit_offset: 10 + bit_size: 2 + enum: ICSEL + - name: I2C2SEL + description: "I2C2 kernel clock source selection\r These bits are used to select the I2C2 kernel clock source.\r Note: The I2C2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." + bit_offset: 12 + bit_size: 2 + enum: ICSEL + - name: I2C4SEL + description: "I2C4 kernel clock source selection\r These bits are used to select the I2C4 kernel clock source.\r Note: The I2C4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." + bit_offset: 14 + bit_size: 2 + enum: ICSEL + - name: SPI2SEL + description: "SPI2 kernel clock source selection\r These bits are used to select the SPI2 kernel clock source.\r Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." + bit_offset: 16 + bit_size: 2 + enum: SPISEL + - name: LPTIM2SEL + description: "Low-power timer 2 kernel clock source selection\r These bits are used to select the LPTIM2 kernel clock source.\r Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1." + bit_offset: 18 + bit_size: 2 + enum: LPTIMSEL + - name: SPI1SEL + description: "SPI1 kernel clock source selection\r These bits are used to select the SPI1 kernel clock source.\r Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." + bit_offset: 20 + bit_size: 2 + enum: SPISEL + - name: SYSTICKSEL + description: "SysTick clock source selection\r These bits are used to select the SysTick clock source.\r Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry." + bit_offset: 22 + bit_size: 2 + enum: SYSTICKSEL + - name: FDCAN1SEL + description: "FDCAN1 kernel clock source selection\r These bits are used to select the FDCAN1 kernel clock source." + bit_offset: 24 + bit_size: 2 + enum: FDCANSEL + - name: ICLKSEL + description: "intermediate clock source selection\r These bits are used to select the clock source used by OTG_FS and SDMMC." + bit_offset: 26 + bit_size: 2 + enum: ICLKSEL + - name: TIMICSEL + description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture\r When the TIMICSEL2 bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4 or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS.\r When TIMICSEL2 is cleared, the HSI, MSIK and MSIS clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r 0xx: HSI, MSIK and MSIS dividers disabled\r Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division." + bit_offset: 29 + bit_size: 3 + enum: TIMICSEL fieldset/CCIPR2: description: RCC peripherals independent clock configuration register 2 fields: - - name: MDF1SEL - description: "MDF1 kernel clock source selection\r These bits are used to select the MDF1 kernel clock source.\r others: reserved" - bit_offset: 0 - bit_size: 3 - enum: MDFSEL - - name: SAI1SEL - description: "SAI1 kernel clock source selection\r These bits are used to select the SAI1 kernel clock source.\r others: reserved\r Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible." - bit_offset: 5 - bit_size: 3 - enum: SAISEL - - name: SAI2SEL - description: "SAI2 kernel clock source selection\r These bits are used to select the SAI2 kernel clock source.\r others: reserved\r Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible." - bit_offset: 8 - bit_size: 3 - enum: SAISEL - - name: SAESSEL - description: "SAES kernel clock source selection\r This bit is used to select the SAES kernel clock source." - bit_offset: 11 - bit_size: 1 - enum: SAESSEL - - name: RNGSEL - description: "RNGSEL kernel clock source selection\r These bits are used to select the RNG kernel clock source." - bit_offset: 12 - bit_size: 2 - enum: RNGSEL - - name: SDMMCSEL - description: "SDMMC1 and SDMMC2 kernel clock source selection\r This bit is used to select the SDMMC kernel clock source. It is recommended to change this bit only after reset and before enabling the SDMMC." - bit_offset: 14 - bit_size: 1 - enum: SDMMCSEL - - name: DSISEL - description: "DSI kernel clock source selection\r This bit is used to select the DSI kernel clock source.\r This bit is only available on some devices in the STM32U5 Series. \r Refer to the device datasheet for availability of its associated peripheral. \r Note: If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 15 - bit_size: 1 - enum: DSISEL - - name: USART6SEL - description: "USART6 kernel clock source selection\r These bits are used to select the USART6 kernel clock source.\r The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." - bit_offset: 16 - bit_size: 2 - enum: USARTSEL - - name: LTDCSEL - description: "LTDC kernel clock source selection\r This bit is used to select the LTDC kernel clock source.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 18 - bit_size: 1 - enum: LTDCSEL - - name: OCTOSPISEL - description: "OCTOSPI1 and OCTOSPI2 kernel clock source selection\r These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source." - bit_offset: 20 - bit_size: 2 - enum: OCTOSPISEL - - name: HSPI1SEL - description: "HSPI1 kernel clock source selection\r These bits are used to select the HSPI1 kernel clock source.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." - bit_offset: 22 - bit_size: 2 - enum: HSPISEL - - name: I2C5SEL - description: "I2C5 kernel clock source selection\r These bits are used to select the I2C5 kernel clock source.\r The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." - bit_offset: 24 - bit_size: 2 - enum: ICSEL - - name: I2C6SEL - description: "I2C6 kernel clock source selection\r These bits are used to select the I2C6 kernel clock source.\r The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." - bit_offset: 26 - bit_size: 2 - enum: ICSEL - - name: OTGHSSEL - description: "OTG_HS PHY kernel clock source selection\r These bits are used to select the OTG_HS PHY kernel clock source.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." - bit_offset: 30 - bit_size: 2 - enum: OTGHSSEL + - name: MDF1SEL + description: "MDF1 kernel clock source selection\r These bits are used to select the MDF1 kernel clock source.\r others: reserved" + bit_offset: 0 + bit_size: 3 + enum: MDFSEL + - name: SAI1SEL + description: "SAI1 kernel clock source selection\r These bits are used to select the SAI1 kernel clock source.\r others: reserved\r Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible." + bit_offset: 5 + bit_size: 3 + enum: SAISEL + - name: SAI2SEL + description: "SAI2 kernel clock source selection\r These bits are used to select the SAI2 kernel clock source.\r others: reserved\r Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible." + bit_offset: 8 + bit_size: 3 + enum: SAISEL + - name: SAESSEL + description: "SAES kernel clock source selection\r This bit is used to select the SAES kernel clock source." + bit_offset: 11 + bit_size: 1 + enum: SAESSEL + - name: RNGSEL + description: "RNGSEL kernel clock source selection\r These bits are used to select the RNG kernel clock source." + bit_offset: 12 + bit_size: 2 + enum: RNGSEL + - name: SDMMCSEL + description: "SDMMC1 and SDMMC2 kernel clock source selection\r This bit is used to select the SDMMC kernel clock source. It is recommended to change this bit only after reset and before enabling the SDMMC." + bit_offset: 14 + bit_size: 1 + enum: SDMMCSEL + - name: DSISEL + description: "DSI kernel clock source selection\r This bit is used to select the DSI kernel clock source.\r This bit is only available on some devices in the STM32U5 Series. \r Refer to the device datasheet for availability of its associated peripheral. \r Note: If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 15 + bit_size: 1 + enum: DSISEL + - name: USART6SEL + description: "USART6 kernel clock source selection\r These bits are used to select the USART6 kernel clock source.\r The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." + bit_offset: 16 + bit_size: 2 + enum: USARTSEL + - name: LTDCSEL + description: "LTDC kernel clock source selection\r This bit is used to select the LTDC kernel clock source.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 18 + bit_size: 1 + enum: LTDCSEL + - name: OCTOSPISEL + description: "OCTOSPI1 and OCTOSPI2 kernel clock source selection\r These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source." + bit_offset: 20 + bit_size: 2 + enum: OCTOSPISEL + - name: HSPI1SEL + description: "HSPI1 kernel clock source selection\r These bits are used to select the HSPI1 kernel clock source.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." + bit_offset: 22 + bit_size: 2 + enum: HSPISEL + - name: I2C5SEL + description: "I2C5 kernel clock source selection\r These bits are used to select the I2C5 kernel clock source.\r The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." + bit_offset: 24 + bit_size: 2 + enum: ICSEL + - name: I2C6SEL + description: "I2C6 kernel clock source selection\r These bits are used to select the I2C6 kernel clock source.\r The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." + bit_offset: 26 + bit_size: 2 + enum: ICSEL + - name: OTGHSSEL + description: "OTG_HS PHY kernel clock source selection\r These bits are used to select the OTG_HS PHY kernel clock source.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." + bit_offset: 30 + bit_size: 2 + enum: OTGHSSEL fieldset/CCIPR3: description: RCC peripherals independent clock configuration register 3 fields: - - name: LPUART1SEL - description: "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r others: reserved\r Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16, LSE or MSIK." - bit_offset: 0 - bit_size: 3 - enum: LPUARTSEL - - name: SPI3SEL - description: "SPI3 kernel clock source selection\r These bits are used to select the SPI3 kernel clock source.\r Note: The SPI3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK." - bit_offset: 3 - bit_size: 2 - enum: SPISEL - - name: I2C3SEL - description: "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Note: The I2C3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK." - bit_offset: 6 - bit_size: 2 - enum: ICSEL - - name: LPTIM34SEL - description: "LPTIM3 and LPTIM4 kernel clock source selection\r These bits are used to select the LPTIM3 and LPTIM4 kernel clock source.\r Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1 or MSIK with MSIKERON = 1." - bit_offset: 8 - bit_size: 2 - enum: LPTIMSEL - - name: LPTIM1SEL - description: "LPTIM1 kernel clock source selection\r These bits are used to select the LPTIM1 kernel clock source.\r Note: The LPTIM1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1 or MSIK with MSIKERON = 1." - bit_offset: 10 - bit_size: 2 - enum: LPTIMSEL - - name: ADCDACSEL - description: "ADC1, ADC4 and DAC1 kernel clock source selection\r These bits are used to select the ADC1, ADC4 and DAC1 kernel clock source.\r others: reserved\r Note: The ADC1, ADC4 and DAC1 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK (only ADC4 and DAC1 are functional in Stop 2 mode)." - bit_offset: 12 - bit_size: 3 - enum: ADCDACSEL - - name: DAC1SEL - description: "DAC1 sample and hold clock source selection\r This bit is used to select the DAC1 sample and hold clock source." - bit_offset: 15 - bit_size: 1 - enum: DACSEL - - name: ADF1SEL - description: "ADF1 kernel clock source selection\r These bits are used to select the ADF1 kernel clock source.\r others: reserved\r Note: The ADF1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK." - bit_offset: 16 - bit_size: 3 - enum: ADFSEL + - name: LPUART1SEL + description: "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r others: reserved\r Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16, LSE or MSIK." + bit_offset: 0 + bit_size: 3 + enum: LPUARTSEL + - name: SPI3SEL + description: "SPI3 kernel clock source selection\r These bits are used to select the SPI3 kernel clock source.\r Note: The SPI3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK." + bit_offset: 3 + bit_size: 2 + enum: SPISEL + - name: I2C3SEL + description: "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Note: The I2C3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK." + bit_offset: 6 + bit_size: 2 + enum: ICSEL + - name: LPTIM34SEL + description: "LPTIM3 and LPTIM4 kernel clock source selection\r These bits are used to select the LPTIM3 and LPTIM4 kernel clock source.\r Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1 or MSIK with MSIKERON = 1." + bit_offset: 8 + bit_size: 2 + enum: LPTIMSEL + - name: LPTIM1SEL + description: "LPTIM1 kernel clock source selection\r These bits are used to select the LPTIM1 kernel clock source.\r Note: The LPTIM1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1 or MSIK with MSIKERON = 1." + bit_offset: 10 + bit_size: 2 + enum: LPTIMSEL + - name: ADCDACSEL + description: "ADC1, ADC4 and DAC1 kernel clock source selection\r These bits are used to select the ADC1, ADC4 and DAC1 kernel clock source.\r others: reserved\r Note: The ADC1, ADC4 and DAC1 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK (only ADC4 and DAC1 are functional in Stop 2 mode)." + bit_offset: 12 + bit_size: 3 + enum: ADCDACSEL + - name: DAC1SEL + description: "DAC1 sample and hold clock source selection\r This bit is used to select the DAC1 sample and hold clock source." + bit_offset: 15 + bit_size: 1 + enum: DACSEL + - name: ADF1SEL + description: "ADF1 kernel clock source selection\r These bits are used to select the ADF1 kernel clock source.\r others: reserved\r Note: The ADF1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK." + bit_offset: 16 + bit_size: 3 + enum: ADFSEL fieldset/CFGR1: description: RCC clock configuration register 1 fields: - - name: SW - description: "system clock switch\r Set and cleared by software to select system clock source (SYSCLK).\r Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI16 oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value." - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: "system clock switch status\r Set and cleared by hardware to indicate which clock source is used as system clock." - bit_offset: 2 - bit_size: 2 - enum: SW - - name: STOPWUCK - description: "wakeup from Stop and CSS backup clock selection\r Set and cleared by software to select the system clock used when exiting Stop mode.\r The selected clock is also used as emergency clock for the clock security system on HSE. Warning: STOPWUCK must not be modified when the CSS is enabled by HSECSSON bit in RCC_CR and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW = 10)." - bit_offset: 4 - bit_size: 1 - enum: STOPWUCK - - name: STOPKERWUCK - description: "wakeup from Stop kernel clock automatic enable selection\r Set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals." - bit_offset: 5 - bit_size: 1 - enum: STOPKERWUCK - - name: MCOSEL - description: "microcontroller clock output\r Set and cleared by software.\r Others: reserved\r Note: This clock output may have some truncated cycles at startup or during MCO clock source switching." - bit_offset: 24 - bit_size: 4 - enum: MCOSEL - - name: MCOPRE - description: "microcontroller clock output prescaler\r Set and cleared by software.\r It is highly recommended to change this prescaler before MCO output is enabled.\r Others: not allowed" - bit_offset: 28 - bit_size: 3 - enum: MCOPRE + - name: SW + description: "system clock switch\r Set and cleared by software to select system clock source (SYSCLK).\r Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI16 oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value." + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: "system clock switch status\r Set and cleared by hardware to indicate which clock source is used as system clock." + bit_offset: 2 + bit_size: 2 + enum: SW + - name: STOPWUCK + description: "wakeup from Stop and CSS backup clock selection\r Set and cleared by software to select the system clock used when exiting Stop mode.\r The selected clock is also used as emergency clock for the clock security system on HSE. Warning: STOPWUCK must not be modified when the CSS is enabled by HSECSSON bit in RCC_CR and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW = 10)." + bit_offset: 4 + bit_size: 1 + enum: STOPWUCK + - name: STOPKERWUCK + description: "wakeup from Stop kernel clock automatic enable selection\r Set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals." + bit_offset: 5 + bit_size: 1 + enum: STOPKERWUCK + - name: MCOSEL + description: "microcontroller clock output\r Set and cleared by software.\r Others: reserved\r Note: This clock output may have some truncated cycles at startup or during MCO clock source switching." + bit_offset: 24 + bit_size: 4 + enum: MCOSEL + - name: MCOPRE + description: "microcontroller clock output prescaler\r Set and cleared by software.\r It is highly recommended to change this prescaler before MCO output is enabled.\r Others: not allowed" + bit_offset: 28 + bit_size: 3 + enum: MCOPRE fieldset/CFGR2: description: RCC clock configuration register 2 fields: - - name: HPRE - description: "AHB prescaler\r Set and cleared by software to control the division factor of the AHB clock (HCLK).\r Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account.\r 0xxx: SYSCLK not divided" - bit_offset: 0 - bit_size: 4 - enum: HPRE - - name: PPRE1 - description: "APB1 prescaler\r Set and cleared by software to control the division factor of the APB1 clock (PCLK1).\r 0xx: HCLK not divided" - bit_offset: 4 - bit_size: 3 - enum: PPRE - - name: PPRE2 - description: "APB2 prescaler\r Set and cleared by software to control the division factor of the APB2 clock (PCLK2).\r 0xx: HCLK not divided" - bit_offset: 8 - bit_size: 3 - enum: PPRE - - name: DPRE - description: "DSI PHY prescaler\r This bitfiled is set and cleared by software to control the division factor of DSI PHY bus clock (DCLK).\r 0xx: DCLK not divided\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." - bit_offset: 12 - bit_size: 3 - enum: DPRE - - name: AHB1DIS - description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1." - bit_offset: 16 - bit_size: 1 - - name: AHB2DIS1 - description: "AHB2_1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3." - bit_offset: 17 - bit_size: 1 - - name: AHB2DIS2 - description: "AHB2_2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2EBNR2 are off." - bit_offset: 18 - bit_size: 1 - - name: APB1DIS - description: "APB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG." - bit_offset: 19 - bit_size: 1 - - name: APB2DIS - description: "APB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off." - bit_offset: 20 - bit_size: 1 + - name: HPRE + description: "AHB prescaler\r Set and cleared by software to control the division factor of the AHB clock (HCLK).\r Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account.\r 0xxx: SYSCLK not divided" + bit_offset: 0 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: "APB1 prescaler\r Set and cleared by software to control the division factor of the APB1 clock (PCLK1).\r 0xx: HCLK not divided" + bit_offset: 4 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: "APB2 prescaler\r Set and cleared by software to control the division factor of the APB2 clock (PCLK2).\r 0xx: HCLK not divided" + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: DPRE + description: "DSI PHY prescaler\r This bitfiled is set and cleared by software to control the division factor of DSI PHY bus clock (DCLK).\r 0xx: DCLK not divided\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." + bit_offset: 12 + bit_size: 3 + enum: DPRE + - name: AHB1DIS + description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1." + bit_offset: 16 + bit_size: 1 + - name: AHB2DIS1 + description: "AHB2_1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3." + bit_offset: 17 + bit_size: 1 + - name: AHB2DIS2 + description: "AHB2_2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2EBNR2 are off." + bit_offset: 18 + bit_size: 1 + - name: APB1DIS + description: "APB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG." + bit_offset: 19 + bit_size: 1 + - name: APB2DIS + description: "APB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off." + bit_offset: 20 + bit_size: 1 fieldset/CFGR3: description: RCC clock configuration register 3 fields: - - name: PPRE3 - description: "APB3 prescaler\r Set and cleared by software to control the division factor of the APB3 clock (PCLK3).\r 0xx: HCLK not divided" - bit_offset: 4 - bit_size: 3 - enum: PPRE - - name: AHB3DIS - description: "AHB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4." - bit_offset: 16 - bit_size: 1 - - name: APB3DIS - description: "APB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off." - bit_offset: 17 - bit_size: 1 + - name: PPRE3 + description: "APB3 prescaler\r Set and cleared by software to control the division factor of the APB3 clock (PCLK3).\r 0xx: HCLK not divided" + bit_offset: 4 + bit_size: 3 + enum: PPRE + - name: AHB3DIS + description: "AHB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4." + bit_offset: 16 + bit_size: 1 + - name: APB3DIS + description: "APB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off." + bit_offset: 17 + bit_size: 1 fieldset/CICR: description: RCC clock interrupt clear register fields: - - name: LSIRDYC - description: "LSI ready interrupt clear\r Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect." - bit_offset: 0 - bit_size: 1 - - name: LSERDYC - description: "LSE ready interrupt clear\r Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect." - bit_offset: 1 - bit_size: 1 - - name: MSISRDYC - description: "MSIS ready interrupt clear\r Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect." - bit_offset: 2 - bit_size: 1 - - name: HSIRDYC - description: "HSI16 ready interrupt clear\r Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect." - bit_offset: 3 - bit_size: 1 - - name: HSERDYC - description: "HSE ready interrupt clear\r Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect." - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYC - description: "HSI48 ready interrupt clear\r Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect." - bit_offset: 5 - bit_size: 1 - - name: PLLRDYC - description: "PLL1 ready interrupt clear\r Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect." - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: CSSC - description: "Clock security system interrupt clear\r Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect." - bit_offset: 10 - bit_size: 1 - - name: MSIKRDYC - description: "MSIK oscillator ready interrupt clear\r Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect." - bit_offset: 11 - bit_size: 1 - - name: SHSIRDYC - description: "SHSI oscillator ready interrupt clear\r Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect." - bit_offset: 12 - bit_size: 1 + - name: LSIRDYC + description: "LSI ready interrupt clear\r Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect." + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: "LSE ready interrupt clear\r Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect." + bit_offset: 1 + bit_size: 1 + - name: MSISRDYC + description: "MSIS ready interrupt clear\r Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYC + description: "HSI16 ready interrupt clear\r Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect." + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: "HSE ready interrupt clear\r Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYC + description: "HSI48 ready interrupt clear\r Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYC + description: "PLL1 ready interrupt clear\r Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect." + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: CSSC + description: "Clock security system interrupt clear\r Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect." + bit_offset: 10 + bit_size: 1 + - name: MSIKRDYC + description: "MSIK oscillator ready interrupt clear\r Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect." + bit_offset: 11 + bit_size: 1 + - name: SHSIRDYC + description: "SHSI oscillator ready interrupt clear\r Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect." + bit_offset: 12 + bit_size: 1 fieldset/CIER: description: RCC clock interrupt enable register fields: - - name: LSIRDYIE - description: "LSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization." - bit_offset: 0 - bit_size: 1 - - name: LSERDYIE - description: "LSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization." - bit_offset: 1 - bit_size: 1 - - name: MSISRDYIE - description: "MSIS ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization." - bit_offset: 2 - bit_size: 1 - - name: HSIRDYIE - description: "HSI16 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization." - bit_offset: 3 - bit_size: 1 - - name: HSERDYIE - description: "HSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization." - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYIE - description: "HSI48 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization." - bit_offset: 5 - bit_size: 1 - - name: PLLRDYIE - description: "PLL ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by PLL1 lock." - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: MSIKRDYIE - description: "MSIK ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization." - bit_offset: 11 - bit_size: 1 - - name: SHSIRDYIE - description: "SHSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization." - bit_offset: 12 - bit_size: 1 + - name: LSIRDYIE + description: "LSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization." + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: "LSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization." + bit_offset: 1 + bit_size: 1 + - name: MSISRDYIE + description: "MSIS ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYIE + description: "HSI16 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization." + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: "HSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYIE + description: "HSI48 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYIE + description: "PLL ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by PLL1 lock." + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: MSIKRDYIE + description: "MSIK ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization." + bit_offset: 11 + bit_size: 1 + - name: SHSIRDYIE + description: "SHSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization." + bit_offset: 12 + bit_size: 1 fieldset/CIFR: description: RCC clock interrupt flag register fields: - - name: LSIRDYF - description: "LSI ready interrupt flag\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.\r Cleared by software setting the LSIRDYC bit." - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: "LSE ready interrupt flag\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set.\r Cleared by software setting the LSERDYC bit." - bit_offset: 1 - bit_size: 1 - - name: MSISRDYF - description: "MSIS ready interrupt flag\r Set by hardware when the MSIS clock becomes stable and MSISRDYIE is set.\r Cleared by software setting the MSISRDYC bit." - bit_offset: 2 - bit_size: 1 - - name: HSIRDYF - description: "HSI16 ready interrupt flag\r Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Cleared by software setting the HSIRDYC bit." - bit_offset: 3 - bit_size: 1 - - name: HSERDYF - description: "HSE ready interrupt flag\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set.\r Cleared by software setting the HSERDYC bit." - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYF - description: "HSI48 ready interrupt flag\r Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set.\r Cleared by software setting the HSI48RDYC bit." - bit_offset: 5 - bit_size: 1 - - name: PLLRDYF - description: "PLL1 ready interrupt flag\r Set by hardware when the PLL1 locks and PLL1RDYIE is set.\r Cleared by software setting the PLL1RDYC bit." - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: CSSF - description: "Clock security system interrupt flag\r Set by hardware when a failure is detected in the HSE oscillator.\r Cleared by software setting the CSSC bit." - bit_offset: 10 - bit_size: 1 - - name: MSIKRDYF - description: "MSIK ready interrupt flag\r Set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set.\r Cleared by software setting the MSIKRDYC bit." - bit_offset: 11 - bit_size: 1 - - name: SHSIRDYF - description: "SHSI ready interrupt flag\r Set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set.\r Cleared by software setting the SHSIRDYC bit." - bit_offset: 12 - bit_size: 1 + - name: LSIRDYF + description: "LSI ready interrupt flag\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.\r Cleared by software setting the LSIRDYC bit." + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: "LSE ready interrupt flag\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set.\r Cleared by software setting the LSERDYC bit." + bit_offset: 1 + bit_size: 1 + - name: MSISRDYF + description: "MSIS ready interrupt flag\r Set by hardware when the MSIS clock becomes stable and MSISRDYIE is set.\r Cleared by software setting the MSISRDYC bit." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYF + description: "HSI16 ready interrupt flag\r Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Cleared by software setting the HSIRDYC bit." + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: "HSE ready interrupt flag\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set.\r Cleared by software setting the HSERDYC bit." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYF + description: "HSI48 ready interrupt flag\r Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set.\r Cleared by software setting the HSI48RDYC bit." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYF + description: "PLL1 ready interrupt flag\r Set by hardware when the PLL1 locks and PLL1RDYIE is set.\r Cleared by software setting the PLL1RDYC bit." + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: CSSF + description: "Clock security system interrupt flag\r Set by hardware when a failure is detected in the HSE oscillator.\r Cleared by software setting the CSSC bit." + bit_offset: 10 + bit_size: 1 + - name: MSIKRDYF + description: "MSIK ready interrupt flag\r Set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set.\r Cleared by software setting the MSIKRDYC bit." + bit_offset: 11 + bit_size: 1 + - name: SHSIRDYF + description: "SHSI ready interrupt flag\r Set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set.\r Cleared by software setting the SHSIRDYC bit." + bit_offset: 12 + bit_size: 1 fieldset/CR: description: RCC clock control register fields: - - name: MSISON - description: "MSIS clock enable\r Set and cleared by software.\r Cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when exiting Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator.\r Set by hardware when used directly or indirectly as system clock." - bit_offset: 0 - bit_size: 1 - - name: MSIKERON - description: "MSI enable for some peripheral kernels\r Set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI ON in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see autonomous mode for more details).\r The MSIKERON must be configured at 0 before entering Stop 3 mode." - bit_offset: 1 - bit_size: 1 - - name: MSISRDY - description: "MSIS clock ready flag\r Set by hardware to indicate that the MSIS oscillator is stable. This bit is set only when MSIS is enabled by software by setting MSISON.\r Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles." - bit_offset: 2 - bit_size: 1 - - name: MSIPLLEN - description: "MSI clock PLL-mode enable\r Set and cleared by software to enable/disable the PLL part of the MSI clock source.\r MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready.\r This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR)." - bit_offset: 3 - bit_size: 1 - - name: MSIKON - description: "MSIK clock enable\r Set and cleared by software.\r Cleared by hardware to stop the MSIK when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode.\r Set by hardware to force the MSIK oscillator ON when STOPWUCK = 0 or STOPKERWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator." - bit_offset: 4 - bit_size: 1 - - name: MSIKRDY - description: "MSIK clock ready flag\r Set by hardware to indicate that the MSIK is stable. This bit is set only when MSI kernel oscillator is enabled by software by setting MSIKON.\r Note: Once the MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles." - bit_offset: 5 - bit_size: 1 - - name: MSIPLLSEL - description: "MSI clock with PLL mode selection\r Set and cleared by software to select which MSI output clock uses the PLL mode. This bit can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0).\r Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to the both clocks outputs." - bit_offset: 6 - bit_size: 1 - enum: MSIPLLSEL - - name: MSIPLLFAST - description: "MSI PLL mode fast startup\r Set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock\r source. This bit is used only if PLL mode is selected (MSIPLLEN = 1).\r The fast start-up feature is not active the first time the PLL mode is selected. The fast start-up is active when the MSI in PLL mode returns from switch off." - bit_offset: 7 - bit_size: 1 - enum: MSIPLLFAST - - name: HSION - description: "HSI16 clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the HSI16 oscillator ON when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator.\r This bit is set by hardware if the HSI16 is used directly or indirectly as system clock." - bit_offset: 8 - bit_size: 1 - - name: HSIKERON - description: "HSI16 enable for some peripheral kernels\r Set and cleared by software to force HSI16 ON even in Stop modes. Keeping the HSI16 ON in Stop mode allows the communication speed not to be reduced by the HSI16 startup time. This bit has no effect on HSION value.\r Refer to for more details.\r The HSIKERON must be configured at 0 before entering Stop 3 mode." - bit_offset: 9 - bit_size: 1 - - name: HSIRDY - description: "HSI16 clock ready flag\r Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION.\r Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles." - bit_offset: 10 - bit_size: 1 - - name: HSI48ON - description: "HSI48 clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes." - bit_offset: 12 - bit_size: 1 - - name: HSI48RDY - description: "HSI48 clock ready flag\r Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON." - bit_offset: 13 - bit_size: 1 - - name: SHSION - description: "SHSI clock enable\r Set and cleared by software.\r Cleared by hardware to stop the SHSI when entering in Stop, Standby or Shutdown modes." - bit_offset: 14 - bit_size: 1 - - name: SHSIRDY - description: "SHSI clock ready flag\r Set by hardware to indicate that the SHSI oscillator is stable. This bit is set only when SHSI is enabled by software by setting SHSION.\r Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles." - bit_offset: 15 - bit_size: 1 - - name: HSEON - description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock." - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable.\r Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles." - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: "HSE crystal oscillator bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled." - bit_offset: 18 - bit_size: 1 - - name: CSSON - description: "Clock security system enable\r Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset." - bit_offset: 19 - bit_size: 1 - - name: HSEEXT - description: "HSE external clock bypass mode\r Set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled." - bit_offset: 20 - bit_size: 1 - enum: HSEEXT - - name: PLLON - description: "PLL1 enable\r Set and cleared by software to enable the main PLL.\r Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock." - bit_offset: 24 - bit_size: 1 - array: - len: 3 - stride: 2 - - name: PLLRDY - description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked." - bit_offset: 25 - bit_size: 1 - array: - len: 3 - stride: 2 + - name: MSISON + description: "MSIS clock enable\r Set and cleared by software.\r Cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when exiting Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator.\r Set by hardware when used directly or indirectly as system clock." + bit_offset: 0 + bit_size: 1 + - name: MSIKERON + description: "MSI enable for some peripheral kernels\r Set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI ON in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see autonomous mode for more details).\r The MSIKERON must be configured at 0 before entering Stop 3 mode." + bit_offset: 1 + bit_size: 1 + - name: MSISRDY + description: "MSIS clock ready flag\r Set by hardware to indicate that the MSIS oscillator is stable. This bit is set only when MSIS is enabled by software by setting MSISON.\r Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles." + bit_offset: 2 + bit_size: 1 + - name: MSIPLLEN + description: "MSI clock PLL-mode enable\r Set and cleared by software to enable/disable the PLL part of the MSI clock source.\r MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready.\r This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR)." + bit_offset: 3 + bit_size: 1 + - name: MSIKON + description: "MSIK clock enable\r Set and cleared by software.\r Cleared by hardware to stop the MSIK when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode.\r Set by hardware to force the MSIK oscillator ON when STOPWUCK = 0 or STOPKERWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator." + bit_offset: 4 + bit_size: 1 + - name: MSIKRDY + description: "MSIK clock ready flag\r Set by hardware to indicate that the MSIK is stable. This bit is set only when MSI kernel oscillator is enabled by software by setting MSIKON.\r Note: Once the MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles." + bit_offset: 5 + bit_size: 1 + - name: MSIPLLSEL + description: "MSI clock with PLL mode selection\r Set and cleared by software to select which MSI output clock uses the PLL mode. This bit can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0).\r Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to the both clocks outputs." + bit_offset: 6 + bit_size: 1 + enum: MSIPLLSEL + - name: MSIPLLFAST + description: "MSI PLL mode fast startup\r Set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock\r source. This bit is used only if PLL mode is selected (MSIPLLEN = 1).\r The fast start-up feature is not active the first time the PLL mode is selected. The fast start-up is active when the MSI in PLL mode returns from switch off." + bit_offset: 7 + bit_size: 1 + enum: MSIPLLFAST + - name: HSION + description: "HSI16 clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the HSI16 oscillator ON when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator.\r This bit is set by hardware if the HSI16 is used directly or indirectly as system clock." + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: "HSI16 enable for some peripheral kernels\r Set and cleared by software to force HSI16 ON even in Stop modes. Keeping the HSI16 ON in Stop mode allows the communication speed not to be reduced by the HSI16 startup time. This bit has no effect on HSION value.\r Refer to for more details.\r The HSIKERON must be configured at 0 before entering Stop 3 mode." + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: "HSI16 clock ready flag\r Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION.\r Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles." + bit_offset: 10 + bit_size: 1 + - name: HSI48ON + description: "HSI48 clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes." + bit_offset: 12 + bit_size: 1 + - name: HSI48RDY + description: "HSI48 clock ready flag\r Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON." + bit_offset: 13 + bit_size: 1 + - name: SHSION + description: "SHSI clock enable\r Set and cleared by software.\r Cleared by hardware to stop the SHSI when entering in Stop, Standby or Shutdown modes." + bit_offset: 14 + bit_size: 1 + - name: SHSIRDY + description: "SHSI clock ready flag\r Set by hardware to indicate that the SHSI oscillator is stable. This bit is set only when SHSI is enabled by software by setting SHSION.\r Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles." + bit_offset: 15 + bit_size: 1 + - name: HSEON + description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock." + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable.\r Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles." + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: "HSE crystal oscillator bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled." + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: "Clock security system enable\r Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset." + bit_offset: 19 + bit_size: 1 + - name: HSEEXT + description: "HSE external clock bypass mode\r Set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled." + bit_offset: 20 + bit_size: 1 + enum: HSEEXT + - name: PLLON + description: "PLL1 enable\r Set and cleared by software to enable the main PLL.\r Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock." + bit_offset: 24 + bit_size: 1 + array: + len: 3 + stride: 2 + - name: PLLRDY + description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked." + bit_offset: 25 + bit_size: 1 + array: + len: 3 + stride: 2 fieldset/CRRCR: description: RCC clock recovery RC register fields: - - name: HSI48CAL - description: "HSI48 clock calibration\r These bits are initialized at startup with the factory-programmed HSI48 calibration trim value." - bit_offset: 0 - bit_size: 9 + - name: HSI48CAL + description: "HSI48 clock calibration\r These bits are initialized at startup with the factory-programmed HSI48 calibration trim value." + bit_offset: 0 + bit_size: 9 fieldset/CSR: description: RCC control/status register fields: - - name: MSIKSRANGE - description: "MSIK range after Standby mode\r Set by software to chose the MSIK frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSIKSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSIKSRANGE does not change the current MSIK frequency." - bit_offset: 8 - bit_size: 4 - enum: MSIXSRANGE - - name: MSISSRANGE - description: "MSIS range after Standby mode\r Set by software to chose the MSIS frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSISSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSISSRANGE does not change the current MSIS frequency." - bit_offset: 12 - bit_size: 4 - enum: MSIXSRANGE - - name: RMVF - description: "Remove reset flag\r Set by software to clear the reset flags." - bit_offset: 23 - bit_size: 1 - - name: OBLRSTF - description: "Option byte loader reset flag\r Set by hardware when a reset from the option byte loading occurs.\r Cleared by writing to the RMVF bit." - bit_offset: 25 - bit_size: 1 - - name: PINRSTF - description: "NRST pin reset flag\r Set by hardware when a reset from the NRST pin occurs.\r Cleared by writing to the RMVF bit." - bit_offset: 26 - bit_size: 1 - - name: BORRSTF - description: "BOR flag\r Set by hardware when a BOR occurs.\r Cleared by writing to the RMVF bit." - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: "Software reset flag\r Set by hardware when a software reset occurs.\r Cleared by writing to the RMVF bit." - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: "Independent watchdog reset flag\r Set by hardware when an independent watchdog reset domain occurs.\r Cleared by writing to the RMVF bit." - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: "Window watchdog reset flag\r Set by hardware when a window watchdog reset occurs.\r Cleared by writing to the RMVF bit." - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: "Low-power reset flag\r Set by hardware when a reset occurs due to Stop, Standby or Shutdown mode entry, whereas the corresponding nRST_STOP, nRST_STBY or nRST_SHDW option bit is cleared.\r Cleared by writing to the RMVF bit." - bit_offset: 31 - bit_size: 1 + - name: MSIKSRANGE + description: "MSIK range after Standby mode\r Set by software to chose the MSIK frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSIKSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSIKSRANGE does not change the current MSIK frequency." + bit_offset: 8 + bit_size: 4 + enum: MSIXSRANGE + - name: MSISSRANGE + description: "MSIS range after Standby mode\r Set by software to chose the MSIS frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSISSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSISSRANGE does not change the current MSIS frequency." + bit_offset: 12 + bit_size: 4 + enum: MSIXSRANGE + - name: RMVF + description: "Remove reset flag\r Set by software to clear the reset flags." + bit_offset: 23 + bit_size: 1 + - name: OBLRSTF + description: "Option byte loader reset flag\r Set by hardware when a reset from the option byte loading occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: "NRST pin reset flag\r Set by hardware when a reset from the NRST pin occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: "BOR flag\r Set by hardware when a BOR occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: "Software reset flag\r Set by hardware when a software reset occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: "Independent watchdog reset flag\r Set by hardware when an independent watchdog reset domain occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: "Window watchdog reset flag\r Set by hardware when a window watchdog reset occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: "Low-power reset flag\r Set by hardware when a reset occurs due to Stop, Standby or Shutdown mode entry, whereas the corresponding nRST_STOP, nRST_STBY or nRST_SHDW option bit is cleared.\r Cleared by writing to the RMVF bit." + bit_offset: 31 + bit_size: 1 fieldset/ICSCR1: description: RCC internal clock sources calibration register 1 fields: - - name: MSICAL3 - description: "MSIRC3 clock calibration for MSI ranges 12 to 15\r These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level." - bit_offset: 0 - bit_size: 5 - - name: MSICAL2 - description: "MSIRC2 clock calibration for MSI ranges 8 to 11\r These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2[4:0] and the factory calibration trim value MSIRC2[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level." - bit_offset: 5 - bit_size: 5 - - name: MSICAL1 - description: "MSIRC1 clock calibration for MSI ranges 4 to 7\r These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1[4:0] and the factory calibration trim value MSIRC1[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level." - bit_offset: 10 - bit_size: 5 - - name: MSICAL0 - description: "MSIRC0 clock calibration for MSI ranges 0 to 3\r These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0[4:0] and the factory-programmed calibration trim value MSIRC0[4:0]." - bit_offset: 15 - bit_size: 5 - - name: MSIBIAS - description: "MSI bias mode selection\r Set by software to select the MSI bias mode. By default, the MSI bias is in continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy." - bit_offset: 22 - bit_size: 1 - enum: MSIBIAS - - name: MSIRGSEL - description: "MSI clock range selection\r Set by software to select the MSIS and MSIK clocks range with MSISRANGE[3:0] and MSIKRANGE[3:0]. Write 0 has no effect.\r After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR." - bit_offset: 23 - bit_size: 1 - enum: MSIRGSEL - - name: MSIKRANGE - description: "MSIK clock ranges\r These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available:\r Note: MSIKRANGE can be modified when MSIK is OFF (MSISON = 0) or when MSIK is ready (MSIKRDY = 1). MSIKRANGE must NOT be modified when MSIK is ON and NOT ready (MSIKON = 1 and MSIKRDY = 0)\r MSIKRANGE is kept when the device wakes up from Stop mode, except when the MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into Range 2 (24 MHz)." - bit_offset: 24 - bit_size: 4 - enum: MSIRANGE - - name: MSISRANGE - description: "MSIS clock ranges\r These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available:\r Note: MSISRANGE can be modified when MSIS is OFF (MSISON = 0) or when MSIS is ready (MSISRDY = 1). MSISRANGE must NOT be modified when MSIS is ON and NOT ready (MSISON = 1 and MSISRDY = 0)\r MSISRANGE is kept when the device wakes up from Stop mode, except when the MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into Range 2 (24 MHz)." - bit_offset: 28 - bit_size: 4 - enum: MSIRANGE + - name: MSICAL3 + description: "MSIRC3 clock calibration for MSI ranges 12 to 15\r These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level." + bit_offset: 0 + bit_size: 5 + - name: MSICAL2 + description: "MSIRC2 clock calibration for MSI ranges 8 to 11\r These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2[4:0] and the factory calibration trim value MSIRC2[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level." + bit_offset: 5 + bit_size: 5 + - name: MSICAL1 + description: "MSIRC1 clock calibration for MSI ranges 4 to 7\r These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1[4:0] and the factory calibration trim value MSIRC1[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level." + bit_offset: 10 + bit_size: 5 + - name: MSICAL0 + description: "MSIRC0 clock calibration for MSI ranges 0 to 3\r These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0[4:0] and the factory-programmed calibration trim value MSIRC0[4:0]." + bit_offset: 15 + bit_size: 5 + - name: MSIBIAS + description: "MSI bias mode selection\r Set by software to select the MSI bias mode. By default, the MSI bias is in continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy." + bit_offset: 22 + bit_size: 1 + enum: MSIBIAS + - name: MSIRGSEL + description: "MSI clock range selection\r Set by software to select the MSIS and MSIK clocks range with MSISRANGE[3:0] and MSIKRANGE[3:0]. Write 0 has no effect.\r After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR." + bit_offset: 23 + bit_size: 1 + enum: MSIRGSEL + - name: MSIKRANGE + description: "MSIK clock ranges\r These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available:\r Note: MSIKRANGE can be modified when MSIK is OFF (MSISON = 0) or when MSIK is ready (MSIKRDY = 1). MSIKRANGE must NOT be modified when MSIK is ON and NOT ready (MSIKON = 1 and MSIKRDY = 0)\r MSIKRANGE is kept when the device wakes up from Stop mode, except when the MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into Range 2 (24 MHz)." + bit_offset: 24 + bit_size: 4 + enum: MSIRANGE + - name: MSISRANGE + description: "MSIS clock ranges\r These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available:\r Note: MSISRANGE can be modified when MSIS is OFF (MSISON = 0) or when MSIS is ready (MSISRDY = 1). MSISRANGE must NOT be modified when MSIS is ON and NOT ready (MSISON = 1 and MSISRDY = 0)\r MSISRANGE is kept when the device wakes up from Stop mode, except when the MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into Range 2 (24 MHz)." + bit_offset: 28 + bit_size: 4 + enum: MSIRANGE fieldset/ICSCR2: description: RCC internal clock sources calibration register 2 fields: - - name: MSITRIM3 - description: "MSI clock trimming for ranges 12 to 15\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." - bit_offset: 0 - bit_size: 5 - - name: MSITRIM2 - description: "MSI clock trimming for ranges 8 to 11\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." - bit_offset: 5 - bit_size: 5 - - name: MSITRIM1 - description: "MSI clock trimming for ranges 4 to 7\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." - bit_offset: 10 - bit_size: 5 - - name: MSITRIM0 - description: "MSI clock trimming for ranges 0 to 3\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." - bit_offset: 15 - bit_size: 5 + - name: MSITRIM3 + description: "MSI clock trimming for ranges 12 to 15\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." + bit_offset: 0 + bit_size: 5 + - name: MSITRIM2 + description: "MSI clock trimming for ranges 8 to 11\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." + bit_offset: 5 + bit_size: 5 + - name: MSITRIM1 + description: "MSI clock trimming for ranges 4 to 7\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." + bit_offset: 10 + bit_size: 5 + - name: MSITRIM0 + description: "MSI clock trimming for ranges 0 to 3\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." + bit_offset: 15 + bit_size: 5 fieldset/ICSCR3: description: RCC internal clock sources calibration register 3 fields: - - name: HSICAL - description: "HSI clock calibration\r These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value." - bit_offset: 0 - bit_size: 12 - - name: HSITRIM - description: "HSI clock trimming\r These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI." - bit_offset: 16 - bit_size: 5 + - name: HSICAL + description: "HSI clock calibration\r These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value." + bit_offset: 0 + bit_size: 12 + - name: HSITRIM + description: "HSI clock trimming\r These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI." + bit_offset: 16 + bit_size: 5 fieldset/PLL1CFGR: description: RCC PLL1 configuration register fields: - - name: PLLSRC - description: "PLL1 entry clock source\r Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled.\r In order to save power, when no PLL1 is used, the value of PLL1SRC must be 0." - bit_offset: 0 - bit_size: 2 - enum: PLLSRC - - name: PLLRGE - description: "PLL1 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL1.\r This bit must be written before enabling the PLL1.\r 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz" - bit_offset: 2 - bit_size: 2 - enum: PLLRGE - - name: PLLFRACEN - description: "PLL1 fractional latch enable\r Set and reset by software to latch the content of PLL1FRACN into the ΣΠmodulator.\r In order to latch the PLL1FRACN value into the ΣΠmodulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see for details)." - bit_offset: 4 - bit_size: 1 - - name: PLLM - description: "Prescaler for PLL1\r Set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." - bit_offset: 8 - bit_size: 4 - enum: PLLM - - name: PLLMBOOST - description: "Prescaler for EPOD booster input clock\r Set and cleared by software to configure the prescaler of the PLL1, used for the EPOD booster. The EPOD booster input frequency is PLL1 input clock frequency/PLL1MBOOST.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0) and EPOD Boost mode is disabled (see ).\r others: reserved" - bit_offset: 12 - bit_size: 4 - enum: PLLMBOOST - - name: PLLPEN - description: "PLL1 DIVP divider output enable\r Set and reset by software to enable the pll1_p_ck output of the PLL1.\r To save power, PLL1PEN and PLL1P bits must be set to 0 when the pll1_p_ck is not used.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." - bit_offset: 16 - bit_size: 1 - - name: PLLQEN - description: "PLL1 DIVQ divider output enable\r Set and reset by software to enable the pll1_q_ck output of the PLL1.\r To save power, PLL1QEN and PLL1Q bits must be set to 0 when the pll1_q_ck is not used.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." - bit_offset: 17 - bit_size: 1 - - name: PLLREN - description: "PLL1 DIVR divider output enable\r Set and reset by software to enable the pll1_r_ck output of the PLL1.\r To save power, PLL1RENPLL2REN and PLL1R bits must be set to 0 when the pll1_r_ck is not used.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." - bit_offset: 18 - bit_size: 1 + - name: PLLSRC + description: "PLL1 entry clock source\r Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled.\r In order to save power, when no PLL1 is used, the value of PLL1SRC must be 0." + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: PLLRGE + description: "PLL1 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL1.\r This bit must be written before enabling the PLL1.\r 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz" + bit_offset: 2 + bit_size: 2 + enum: PLLRGE + - name: PLLFRACEN + description: "PLL1 fractional latch enable\r Set and reset by software to latch the content of PLL1FRACN into the ΣΠmodulator.\r In order to latch the PLL1FRACN value into the ΣΠmodulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see for details)." + bit_offset: 4 + bit_size: 1 + - name: PLLM + description: "Prescaler for PLL1\r Set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." + bit_offset: 8 + bit_size: 4 + enum: PLLM + - name: PLLMBOOST + description: "Prescaler for EPOD booster input clock\r Set and cleared by software to configure the prescaler of the PLL1, used for the EPOD booster. The EPOD booster input frequency is PLL1 input clock frequency/PLL1MBOOST.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0) and EPOD Boost mode is disabled (see ).\r others: reserved" + bit_offset: 12 + bit_size: 4 + enum: PLLMBOOST + - name: PLLPEN + description: "PLL1 DIVP divider output enable\r Set and reset by software to enable the pll1_p_ck output of the PLL1.\r To save power, PLL1PEN and PLL1P bits must be set to 0 when the pll1_p_ck is not used.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." + bit_offset: 16 + bit_size: 1 + - name: PLLQEN + description: "PLL1 DIVQ divider output enable\r Set and reset by software to enable the pll1_q_ck output of the PLL1.\r To save power, PLL1QEN and PLL1Q bits must be set to 0 when the pll1_q_ck is not used.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." + bit_offset: 17 + bit_size: 1 + - name: PLLREN + description: "PLL1 DIVR divider output enable\r Set and reset by software to enable the pll1_r_ck output of the PLL1.\r To save power, PLL1RENPLL2REN and PLL1R bits must be set to 0 when the pll1_r_ck is not used.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." + bit_offset: 18 + bit_size: 1 fieldset/PLL1DIVR: description: RCC PLL1 dividers register fields: - - name: PLLN - description: "Multiplication factor for PLL1 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with:\r PLL1N between 4 and 512\r input frequency Fref1_ck between 4 and 16 MHz" - bit_offset: 0 - bit_size: 9 - - name: PLLP - description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..." - bit_offset: 9 - bit_size: 7 - - name: PLLQ - description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." - bit_offset: 16 - bit_size: 7 - - name: PLLR - description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." - bit_offset: 24 - bit_size: 7 + - name: PLLN + description: "Multiplication factor for PLL1 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with:\r PLL1N between 4 and 512\r input frequency Fref1_ck between 4 and 16 MHz" + bit_offset: 0 + bit_size: 9 + - name: PLLP + description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..." + bit_offset: 9 + bit_size: 7 + - name: PLLQ + description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." + bit_offset: 16 + bit_size: 7 + - name: PLLR + description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." + bit_offset: 24 + bit_size: 7 fieldset/PLL1FRACR: description: RCC PLL1 fractional divider register fields: - - name: PLLFRACN - description: "Fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with:\r PLL1N must be between 4 and 512.\r PLL1FRACN can be between 0 and 213- 1.\r The input frequency Fref1_ck must be between 4 and 16 MHz.\r To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL1FRACEN to 0.\r Write the new fractional value into PLL1FRACN.\r Set the bit PLL1FRACEN to 1." - bit_offset: 3 - bit_size: 13 + - name: PLLFRACN + description: "Fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with:\r PLL1N must be between 4 and 512.\r PLL1FRACN can be between 0 and 213- 1.\r The input frequency Fref1_ck must be between 4 and 16 MHz.\r To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL1FRACEN to 0.\r Write the new fractional value into PLL1FRACN.\r Set the bit PLL1FRACEN to 1." + bit_offset: 3 + bit_size: 13 fieldset/PLL2CFGR: description: RCC PLL2 configuration register fields: - - name: PLLSRC - description: "PLL2 entry clock source\r Set and cleared by software to select PLL2 clock source. These bits can be written only when the PLL2 is disabled.\r In order to save power, when no PLL2 is used, the value of PLL2SRC must be 0." - bit_offset: 0 - bit_size: 2 - enum: PLLSRC - - name: PLLRGE - description: "PLL2 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL2.\r This bit must be written before enabling the PLL2.\r 00-01-10: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz" - bit_offset: 2 - bit_size: 2 - enum: PLLRGE - - name: PLLFRACEN - description: "PLL2 fractional latch enable\r Set and reset by software to latch the content of PLL2FRACN into the ΣΠmodulator.\r In order to latch the PLL2FRACN value into the ΣΠmodulator, PLL2FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL2FRACN into the modulator (see for details)." - bit_offset: 4 - bit_size: 1 - - name: PLLM - description: "Prescaler for PLL2\r Set and cleared by software to configure the prescaler of the PLL2. The VCO2 input frequency is PLL2 input clock frequency/PLL2M.\r This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..." - bit_offset: 8 - bit_size: 4 - enum: PLLM - - name: PLLPEN - description: "PLL2 DIVP divider output enable\r Set and reset by software to enable the pll2_p_ck output of the PLL2.\r To save power, PLL2PEN and PLL2P bits must be set to 0 when the pll2_p_ck is not used.\r This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0)." - bit_offset: 16 - bit_size: 1 - - name: PLLQEN - description: "PLL2 DIVQ divider output enable\r Set and reset by software to enable the pll2_q_ck output of the PLL2.\r To save power, PLL2QEN and PLL2Q bits must be set to 0 when the pll2_q_ck is not used.\r This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0." - bit_offset: 17 - bit_size: 1 - - name: PLLREN - description: "PLL2 DIVR divider output enable\r Set and reset by software to enable the pll2_r_ck output of the PLL2.\r To save power, PLL2REN and PLL2R bits must be set to 0 when the pll2_r_ck is not used.\r This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0)." - bit_offset: 18 - bit_size: 1 + - name: PLLSRC + description: "PLL2 entry clock source\r Set and cleared by software to select PLL2 clock source. These bits can be written only when the PLL2 is disabled.\r In order to save power, when no PLL2 is used, the value of PLL2SRC must be 0." + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: PLLRGE + description: "PLL2 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL2.\r This bit must be written before enabling the PLL2.\r 00-01-10: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz" + bit_offset: 2 + bit_size: 2 + enum: PLLRGE + - name: PLLFRACEN + description: "PLL2 fractional latch enable\r Set and reset by software to latch the content of PLL2FRACN into the ΣΠmodulator.\r In order to latch the PLL2FRACN value into the ΣΠmodulator, PLL2FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL2FRACN into the modulator (see for details)." + bit_offset: 4 + bit_size: 1 + - name: PLLM + description: "Prescaler for PLL2\r Set and cleared by software to configure the prescaler of the PLL2. The VCO2 input frequency is PLL2 input clock frequency/PLL2M.\r This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..." + bit_offset: 8 + bit_size: 4 + enum: PLLM + - name: PLLPEN + description: "PLL2 DIVP divider output enable\r Set and reset by software to enable the pll2_p_ck output of the PLL2.\r To save power, PLL2PEN and PLL2P bits must be set to 0 when the pll2_p_ck is not used.\r This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0)." + bit_offset: 16 + bit_size: 1 + - name: PLLQEN + description: "PLL2 DIVQ divider output enable\r Set and reset by software to enable the pll2_q_ck output of the PLL2.\r To save power, PLL2QEN and PLL2Q bits must be set to 0 when the pll2_q_ck is not used.\r This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0." + bit_offset: 17 + bit_size: 1 + - name: PLLREN + description: "PLL2 DIVR divider output enable\r Set and reset by software to enable the pll2_r_ck output of the PLL2.\r To save power, PLL2REN and PLL2R bits must be set to 0 when the pll2_r_ck is not used.\r This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0)." + bit_offset: 18 + bit_size: 1 fieldset/PLL2DIVR: description: RCC PLL2 dividers configuration register fields: - - name: PLLN - description: "Multiplication factor for PLL2 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref2_ck x PLL2N, when fractional value 0 has been loaded into PLL2FRACN, with:\r PLL2N between 4 and 512\r input frequency Fref2_ck between 1MHz and 16MHz" - bit_offset: 0 - bit_size: 9 - - name: PLLP - description: "PLL2 DIVP division factor\r Set and reset by software to control the frequency of the pll2_p_ck clock.\r These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..." - bit_offset: 9 - bit_size: 7 - - name: PLLQ - description: "PLL2 DIVQ division factor\r Set and reset by software to control the frequency of the pll2_q_ck clock.\r These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..." - bit_offset: 16 - bit_size: 7 - - name: PLLR - description: "PLL2 DIVR division factor\r Set and reset by software to control the frequency of the pll2_r_ck clock.\r These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..." - bit_offset: 24 - bit_size: 7 + - name: PLLN + description: "Multiplication factor for PLL2 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref2_ck x PLL2N, when fractional value 0 has been loaded into PLL2FRACN, with:\r PLL2N between 4 and 512\r input frequency Fref2_ck between 1MHz and 16MHz" + bit_offset: 0 + bit_size: 9 + - name: PLLP + description: "PLL2 DIVP division factor\r Set and reset by software to control the frequency of the pll2_p_ck clock.\r These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..." + bit_offset: 9 + bit_size: 7 + - name: PLLQ + description: "PLL2 DIVQ division factor\r Set and reset by software to control the frequency of the pll2_q_ck clock.\r These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..." + bit_offset: 16 + bit_size: 7 + - name: PLLR + description: "PLL2 DIVR division factor\r Set and reset by software to control the frequency of the pll2_r_ck clock.\r These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..." + bit_offset: 24 + bit_size: 7 fieldset/PLL2FRACR: description: RCC PLL2 fractional divider register fields: - - name: PLLFRACN - description: "Fractional part of the multiplication factor for PLL2 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO.\r VCO output frequency = Fref2_ck x (PLL2N + (PLL2FRACN / 213)), with\r PLL2N must be between 4 and 512.\r PLL2FRACN can be between 0 and 213 - 1.\r The input frequency Fref2_ck must be between 4 and 16 MHz.\r In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL2FRACEN to 0.\r Write the new fractional value into PLL2FRACN.\r Set the bit PLL2FRACEN to 1." - bit_offset: 3 - bit_size: 13 + - name: PLLFRACN + description: "Fractional part of the multiplication factor for PLL2 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO.\r VCO output frequency = Fref2_ck x (PLL2N + (PLL2FRACN / 213)), with\r PLL2N must be between 4 and 512.\r PLL2FRACN can be between 0 and 213 - 1.\r The input frequency Fref2_ck must be between 4 and 16 MHz.\r In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL2FRACEN to 0.\r Write the new fractional value into PLL2FRACN.\r Set the bit PLL2FRACEN to 1." + bit_offset: 3 + bit_size: 13 fieldset/PLL3CFGR: description: RCC PLL3 configuration register fields: - - name: PLLSRC - description: "PLL3 entry clock source\r Set and cleared by software to select PLL3 clock source. These bits can be written only when the PLL3 is disabled.\r In order to save power, when no PLL3 is used, the value of PLL3SRC must be 00." - bit_offset: 0 - bit_size: 2 - enum: PLLSRC - - name: PLLRGE - description: "PLL3 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL3.\r This bit must be written before enabling the PLL3.\r 00-01-10: PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz" - bit_offset: 2 - bit_size: 2 - enum: PLLRGE - - name: PLLFRACEN - description: "PLL3 fractional latch enable\r Set and reset by software to latch the content of PLL3FRACN into the ΣΠmodulator.\r In order to latch the PLL3FRACN value into the ΣΠmodulator, PLL3FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL3FRACN into the modulator (see for details)." - bit_offset: 4 - bit_size: 1 - - name: PLLM - description: "Prescaler for PLL3\r Set and cleared by software to configure the prescaler of the PLL3. The VCO3 input frequency is PLL3 input clock frequency/PLL3M.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..." - bit_offset: 8 - bit_size: 4 - enum: PLLM - - name: PLLPEN - description: "PLL3 DIVP divider output enable\r Set and reset by software to enable the pll3_p_ck output of the PLL3.\r To save power, PLL3PEN and PLL3P bits must be set to 0 when the pll3_p_ck is not used.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0)." - bit_offset: 16 - bit_size: 1 - - name: PLLQEN - description: "PLL3 DIVQ divider output enable\r Set and reset by software to enable the pll3_q_ck output of the PLL3.\r To save power, PLL3QEN and PLL3Q bits must be set to 0 when the pll3_q_ck is not used.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0)." - bit_offset: 17 - bit_size: 1 - - name: PLLREN - description: "PLL3 DIVR divider output enable\r Set and reset by software to enable the pll3_r_ck output of the PLL3.\r To save power, PLL3REN and PLL3R bits must be set to 0 when the pll3_r_ck is not used.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0)." - bit_offset: 18 - bit_size: 1 + - name: PLLSRC + description: "PLL3 entry clock source\r Set and cleared by software to select PLL3 clock source. These bits can be written only when the PLL3 is disabled.\r In order to save power, when no PLL3 is used, the value of PLL3SRC must be 00." + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: PLLRGE + description: "PLL3 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL3.\r This bit must be written before enabling the PLL3.\r 00-01-10: PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz" + bit_offset: 2 + bit_size: 2 + enum: PLLRGE + - name: PLLFRACEN + description: "PLL3 fractional latch enable\r Set and reset by software to latch the content of PLL3FRACN into the ΣΠmodulator.\r In order to latch the PLL3FRACN value into the ΣΠmodulator, PLL3FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL3FRACN into the modulator (see for details)." + bit_offset: 4 + bit_size: 1 + - name: PLLM + description: "Prescaler for PLL3\r Set and cleared by software to configure the prescaler of the PLL3. The VCO3 input frequency is PLL3 input clock frequency/PLL3M.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..." + bit_offset: 8 + bit_size: 4 + enum: PLLM + - name: PLLPEN + description: "PLL3 DIVP divider output enable\r Set and reset by software to enable the pll3_p_ck output of the PLL3.\r To save power, PLL3PEN and PLL3P bits must be set to 0 when the pll3_p_ck is not used.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0)." + bit_offset: 16 + bit_size: 1 + - name: PLLQEN + description: "PLL3 DIVQ divider output enable\r Set and reset by software to enable the pll3_q_ck output of the PLL3.\r To save power, PLL3QEN and PLL3Q bits must be set to 0 when the pll3_q_ck is not used.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0)." + bit_offset: 17 + bit_size: 1 + - name: PLLREN + description: "PLL3 DIVR divider output enable\r Set and reset by software to enable the pll3_r_ck output of the PLL3.\r To save power, PLL3REN and PLL3R bits must be set to 0 when the pll3_r_ck is not used.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0)." + bit_offset: 18 + bit_size: 1 fieldset/PLL3DIVR: description: RCC PLL3 dividers configuration register fields: - - name: PLLN - description: "Multiplication factor for PLL3 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref3_ck x PLL3N, when fractional value 0 has been loaded into PLL3FRACN, with:\r PLL3N between 4 and 512\r input frequency Fref3_ck between 4 and 16MHz" - bit_offset: 0 - bit_size: 9 - - name: PLLP - description: "PLL3 DIVP division factor\r Set and reset by software to control the frequency of the pll3_p_ck clock.\r These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..." - bit_offset: 9 - bit_size: 7 - - name: PLLQ - description: "PLL3 DIVQ division factor\r Set and reset by software to control the frequency of the pll3_q_ck clock.\r These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..." - bit_offset: 16 - bit_size: 7 - - name: PLLR - description: "PLL3 DIVR division factor\r Set and reset by software to control the frequency of the pll3_r_ck clock.\r These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..." - bit_offset: 24 - bit_size: 7 + - name: PLLN + description: "Multiplication factor for PLL3 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref3_ck x PLL3N, when fractional value 0 has been loaded into PLL3FRACN, with:\r PLL3N between 4 and 512\r input frequency Fref3_ck between 4 and 16MHz" + bit_offset: 0 + bit_size: 9 + - name: PLLP + description: "PLL3 DIVP division factor\r Set and reset by software to control the frequency of the pll3_p_ck clock.\r These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..." + bit_offset: 9 + bit_size: 7 + - name: PLLQ + description: "PLL3 DIVQ division factor\r Set and reset by software to control the frequency of the pll3_q_ck clock.\r These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..." + bit_offset: 16 + bit_size: 7 + - name: PLLR + description: "PLL3 DIVR division factor\r Set and reset by software to control the frequency of the pll3_r_ck clock.\r These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..." + bit_offset: 24 + bit_size: 7 fieldset/PLL3FRACR: description: RCC PLL3 fractional divider register fields: - - name: PLLFRACN - description: "Fractional part of the multiplication factor for PLL3 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO.\r VCO output frequency = Fref3_ck x (PLL3N + (PLL3FRACN / 213)), with:\r PLL3N must be between 4 and 512.\r PLL3FRACN can be between 0 and 213 - 1.\r The input frequency Fref3_ck must be between 4 and 16 MHz.\r In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL3FRACEN to 0.\r Write the new fractional value into PLL3FRACN.\r Set the bit PLL3FRACEN to 1." - bit_offset: 3 - bit_size: 13 + - name: PLLFRACN + description: "Fractional part of the multiplication factor for PLL3 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO.\r VCO output frequency = Fref3_ck x (PLL3N + (PLL3FRACN / 213)), with:\r PLL3N must be between 4 and 512.\r PLL3FRACN can be between 0 and 213 - 1.\r The input frequency Fref3_ck must be between 4 and 16 MHz.\r In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL3FRACEN to 0.\r Write the new fractional value into PLL3FRACN.\r Set the bit PLL3FRACEN to 1." + bit_offset: 3 + bit_size: 13 fieldset/PRIVCFGR: description: RCC privilege configuration register fields: - - name: SPRIV - description: "RCC secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access." - bit_offset: 0 - bit_size: 1 - enum: PRIV - - name: NSPRIV - description: "RCC non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure." - bit_offset: 1 - bit_size: 1 - enum: PRIV + - name: SPRIV + description: "RCC secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access." + bit_offset: 0 + bit_size: 1 + enum: PRIV + - name: NSPRIV + description: "RCC non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure." + bit_offset: 1 + bit_size: 1 + enum: PRIV fieldset/SECCFGR: description: RCC secure configuration register fields: - - name: HSISEC - description: "HSI clock configuration and status bits security\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - enum: SECURITY - - name: HSESEC - description: "HSE clock configuration bits, status bits and HSE_CSS security\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - enum: SECURITY - - name: MSISEC - description: "MSI clock configuration and status bits security\r Set and reset by software." - bit_offset: 2 - bit_size: 1 - enum: SECURITY - - name: LSISEC - description: "LSI clock configuration and status bits security\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - enum: SECURITY - - name: LSESEC - description: "LSE clock configuration and status bits security\r Set and reset by software." - bit_offset: 4 - bit_size: 1 - enum: SECURITY - - name: SYSCLKSEC - description: "SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - enum: SECURITY - - name: PRESCSEC - description: "AHBx/APBx prescaler configuration bits security\r Set and reset by software." - bit_offset: 6 - bit_size: 1 - enum: SECURITY - - name: PLLSEC - description: "PLL1 clock configuration and status bits security\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - array: - len: 3 - stride: 1 - enum: SECURITY - - name: ICLKSEC - description: "intermediate clock source selection security\r Set and reset by software." - bit_offset: 10 - bit_size: 1 - enum: SECURITY - - name: HSI48SEC - description: "HSI48 clock configuration and status bits security\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - enum: SECURITY - - name: RMVFSEC - description: "Remove reset flag security\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - enum: SECURITY + - name: HSISEC + description: "HSI clock configuration and status bits security\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + enum: SECURITY + - name: HSESEC + description: "HSE clock configuration bits, status bits and HSE_CSS security\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + enum: SECURITY + - name: MSISEC + description: "MSI clock configuration and status bits security\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + enum: SECURITY + - name: LSISEC + description: "LSI clock configuration and status bits security\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + enum: SECURITY + - name: LSESEC + description: "LSE clock configuration and status bits security\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + enum: SECURITY + - name: SYSCLKSEC + description: "SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + enum: SECURITY + - name: PRESCSEC + description: "AHBx/APBx prescaler configuration bits security\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + enum: SECURITY + - name: PLLSEC + description: "PLL1 clock configuration and status bits security\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: SECURITY + - name: ICLKSEC + description: "intermediate clock source selection security\r Set and reset by software." + bit_offset: 10 + bit_size: 1 + enum: SECURITY + - name: HSI48SEC + description: "HSI48 clock configuration and status bits security\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + enum: SECURITY + - name: RMVFSEC + description: "Remove reset flag security\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + enum: SECURITY fieldset/SRDAMR: description: RCC SmartRun domain peripheral autonomous mode register fields: - - name: SPI3AMEN - description: "SPI3 autonomous mode enable in Stop 0,1, 2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 5 - bit_size: 1 - - name: LPUART1AMEN - description: "LPUART1 autonomous mode enable in Stop 0,1, 2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 6 - bit_size: 1 - - name: I2C3AMEN - description: "I2C3 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 7 - bit_size: 1 - - name: LPTIM1AMEN - description: "LPTIM1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 11 - bit_size: 1 - - name: LPTIM3AMEN - description: "LPTIM3 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 12 - bit_size: 1 - - name: LPTIM4AMEN - description: "LPTIM4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 13 - bit_size: 1 - - name: OPAMPAMEN - description: "OPAMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: COMPAMEN - description: "COMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." - bit_offset: 15 - bit_size: 1 - - name: VREFAMEN - description: "VREFBUF autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 - - name: RTCAPBAMEN - description: "RTC and TAMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 21 - bit_size: 1 - - name: ADC4AMEN - description: "ADC4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 25 - bit_size: 1 - - name: LPGPIO1AMEN - description: "LPGPIO1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." - bit_offset: 26 - bit_size: 1 - - name: DAC1AMEN - description: "DAC1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 27 - bit_size: 1 - - name: LPDMA1AMEN - description: "LPDMA1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 28 - bit_size: 1 - - name: ADF1AMEN - description: "ADF1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 29 - bit_size: 1 - - name: SRAM4AMEN - description: "SRAM4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." - bit_offset: 31 - bit_size: 1 + - name: SPI3AMEN + description: "SPI3 autonomous mode enable in Stop 0,1, 2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 5 + bit_size: 1 + - name: LPUART1AMEN + description: "LPUART1 autonomous mode enable in Stop 0,1, 2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 6 + bit_size: 1 + - name: I2C3AMEN + description: "I2C3 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 7 + bit_size: 1 + - name: LPTIM1AMEN + description: "LPTIM1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 11 + bit_size: 1 + - name: LPTIM3AMEN + description: "LPTIM3 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 12 + bit_size: 1 + - name: LPTIM4AMEN + description: "LPTIM4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 13 + bit_size: 1 + - name: OPAMPAMEN + description: "OPAMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: COMPAMEN + description: "COMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." + bit_offset: 15 + bit_size: 1 + - name: VREFAMEN + description: "VREFBUF autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 + - name: RTCAPBAMEN + description: "RTC and TAMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 21 + bit_size: 1 + - name: ADC4AMEN + description: "ADC4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 25 + bit_size: 1 + - name: LPGPIO1AMEN + description: "LPGPIO1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." + bit_offset: 26 + bit_size: 1 + - name: DAC1AMEN + description: "DAC1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 27 + bit_size: 1 + - name: LPDMA1AMEN + description: "LPDMA1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 28 + bit_size: 1 + - name: ADF1AMEN + description: "ADF1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 29 + bit_size: 1 + - name: SRAM4AMEN + description: "SRAM4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." + bit_offset: 31 + bit_size: 1 enum/ADCDACSEL: bit_size: 3 variants: - - name: HCLK - description: HCLK clock selected - value: 0 - - name: SYSCLK - description: SYSCLK selected - value: 1 - - name: PLL2_R - description: PLL2 R (pll2_r_ck) selected - value: 2 - - name: HSE - description: HSE clock selected - value: 3 - - name: HSI16 - description: HSI16 clock selected - value: 4 - - name: MSI_K - description: MSIK clock selected - value: 5 + - name: HCLK + description: HCLK clock selected + value: 0 + - name: SYSCLK + description: SYSCLK selected + value: 1 + - name: PLL2_R + description: PLL2 R (pll2_r_ck) selected + value: 2 + - name: HSE + description: HSE clock selected + value: 3 + - name: HSI16 + description: HSI16 clock selected + value: 4 + - name: MSI_K + description: MSIK clock selected + value: 5 enum/ADFSEL: bit_size: 3 variants: - - name: HCLK - description: HCLK selected - value: 0 - - name: PLL1_P - description: PLL1 P (pll1_p_ck) selected - value: 1 - - name: PLL3_Q - description: PLL3 Q (pll3_q_ck) selected - value: 2 - - name: AUDIOCLK - description: input pin AUDIOCLK selected - value: 3 - - name: MSIK - description: MSIK clock selected - value: 4 + - name: HCLK + description: HCLK selected + value: 0 + - name: PLL1_P + description: PLL1 P (pll1_p_ck) selected + value: 1 + - name: PLL3_Q + description: PLL3 Q (pll3_q_ck) selected + value: 2 + - name: AUDIOCLK + description: input pin AUDIOCLK selected + value: 3 + - name: MSIK + description: MSIK clock selected + value: 4 enum/DACSEL: bit_size: 1 variants: - - name: LSE - description: LSE selected - value: 0 - - name: LSI - description: LSI selected - value: 1 + - name: LSE + description: LSE selected + value: 0 + - name: LSI + description: LSI selected + value: 1 enum/DPRE: bit_size: 3 variants: - - name: NONE - description: DCLK not divided - value: 0 - - name: DIV2 - description: DCLK divided by 2 - value: 4 - - name: DIV4 - description: DCLK divided by 4 - value: 5 - - name: DIV8 - description: DCLK divided by 8 - value: 6 - - name: DIV16 - description: DCLK divided by 16 - value: 7 + - name: Div1 + description: DCLK not divided + value: 0 + - name: Div2 + description: DCLK divided by 2 + value: 4 + - name: Div4 + description: DCLK divided by 4 + value: 5 + - name: Div8 + description: DCLK divided by 8 + value: 6 + - name: Div16 + description: DCLK divided by 16 + value: 7 enum/DSISEL: bit_size: 1 variants: - - name: PLL3_P - description: PLL3 “P” (pll3_p_ck) selected - value: 0 - - name: DCLK - description: DSI PHY PLL output selected - value: 1 + - name: PLL3_P + description: PLL3 “P” (pll3_p_ck) selected + value: 0 + - name: DCLK + description: DSI PHY PLL output selected + value: 1 enum/FDCANSEL: bit_size: 2 variants: - - name: HSE - description: HSE clock selected - value: 0 - - name: PLL1_Q - description: PLL1 Q (pll1_q_ck) selected - value: 1 - - name: PLL2_P - description: PLL2 P (pll2_p_ck) selected - value: 2 + - name: HSE + description: HSE clock selected + value: 0 + - name: PLL1_Q + description: PLL1 Q (pll1_q_ck) selected + value: 1 + - name: PLL2_P + description: PLL2 P (pll2_p_ck) selected + value: 2 enum/HPRE: bit_size: 4 variants: - - name: NONE - description: SYSCLK not divided - value: 0 - - name: DIV2 - description: SYSCLK divided by 2 - value: 8 - - name: DIV4 - description: SYSCLK divided by 4 - value: 9 - - name: DIV8 - description: SYSCLK divided by 8 - value: 10 - - name: DIV16 - description: SYSCLK divided by 16 - value: 11 - - name: DIV64 - description: SYSCLK divided by 64 - value: 12 - - name: DIV128 - description: SYSCLK divided by 128 - value: 13 - - name: DIV256 - description: SYSCLK divided by 256 - value: 14 - - name: DIV512 - description: SYSCLK divided by 512 - value: 15 + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 enum/HSEEXT: bit_size: 1 variants: - - name: ANALOG - description: external HSE clock analog mode - value: 0 - - name: DIGITAL - description: external HSE clock digital mode (through I/O Schmitt trigger) - value: 1 + - name: ANALOG + description: external HSE clock analog mode + value: 0 + - name: DIGITAL + description: external HSE clock digital mode (through I/O Schmitt trigger) + value: 1 enum/HSPISEL: bit_size: 2 variants: - - name: SYSCLK - description: SYSCLK selected - value: 0 - - name: PLL1_Q - description: "PLL1 “Q” (pll1_q_ck) selected, can be up to 200 MHz" - value: 1 - - name: PLL2_Q - description: "PLL2 “Q” (pll2_q_ck) selected, can be up to 200 MHz" - value: 2 - - name: PLL3_R - description: "PLL3 “R” (pll3_r_ck) selected, can be up to 200 MHz" - value: 3 + - name: SYSCLK + description: SYSCLK selected + value: 0 + - name: PLL1_Q + description: PLL1 “Q” (pll1_q_ck) selected, can be up to 200 MHz + value: 1 + - name: PLL2_Q + description: PLL2 “Q” (pll2_q_ck) selected, can be up to 200 MHz + value: 2 + - name: PLL3_R + description: PLL3 “R” (pll3_r_ck) selected, can be up to 200 MHz + value: 3 enum/ICLKSEL: bit_size: 2 variants: - - name: HSI48 - description: HSI48 clock selected - value: 0 - - name: PLL2_Q - description: PLL2 Q (pll2_q_ck) selected - value: 1 - - name: PLL1_Q - description: PLL1 Q (pll1_q_ck) selected - value: 2 - - name: MSIK - description: MSIK clock selected - value: 3 + - name: HSI48 + description: HSI48 clock selected + value: 0 + - name: PLL2_Q + description: PLL2 Q (pll2_q_ck) selected + value: 1 + - name: PLL1_Q + description: PLL1 Q (pll1_q_ck) selected + value: 2 + - name: MSIK + description: MSIK clock selected + value: 3 enum/ICSEL: bit_size: 2 variants: - - name: PCLK1 - description: PCLK1 selected - value: 0 - - name: SYSCLK - description: SYSCLK selected - value: 1 - - name: HSI16 - description: HSI16 selected - value: 2 - - name: MSIK - description: MSIK selected - value: 3 + - name: PCLK1 + description: PCLK1 selected + value: 0 + - name: SYSCLK + description: SYSCLK selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 + - name: MSIK + description: MSIK selected + value: 3 enum/LPTIMSEL: bit_size: 2 variants: - - name: PCLK1 - description: PCLK1 selected - value: 0 - - name: LSI - description: LSI selected - value: 1 - - name: HSI16 - description: HSI16 selected - value: 2 - - name: LSE - description: LSE selected - value: 3 + - name: PCLK1 + description: PCLK1 selected + value: 0 + - name: LSI + description: LSI selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 + - name: LSE + description: LSE selected + value: 3 enum/LPUARTSEL: bit_size: 3 variants: - - name: PCLK3 - description: PCLK3 selected - value: 0 - - name: SYSCLK - description: SYSCLK selected - value: 1 - - name: HSI16 - description: HSI16 selected - value: 2 - - name: LSE - description: LSE selected - value: 3 - - name: MSIK - description: MSIK selected - value: 4 + - name: PCLK3 + description: PCLK3 selected + value: 0 + - name: SYSCLK + description: SYSCLK selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 + - name: LSE + description: LSE selected + value: 3 + - name: MSIK + description: MSIK selected + value: 4 enum/LSCOSEL: bit_size: 1 variants: - - name: LSI - description: LSI clock selected - value: 0 - - name: LSE - description: LSE clock selected - value: 1 + - name: LSI + description: LSI clock selected + value: 0 + - name: LSE + description: LSE clock selected + value: 1 enum/LSEDRV: bit_size: 2 variants: - - name: LOW - description: "'Xtal mode lower driving capability" - value: 0 - - name: MEDIUM_LOW - description: "'Xtal mode medium-low driving capability" - value: 1 - - name: MEDIUM_HIGH - description: "'Xtal mode medium-high driving capability" - value: 2 - - name: HIGH - description: "'Xtal mode higher driving capability" - value: 3 + - name: LOW + description: '''Xtal mode lower driving capability' + value: 0 + - name: MEDIUM_LOW + description: '''Xtal mode medium-low driving capability' + value: 1 + - name: MEDIUM_HIGH + description: '''Xtal mode medium-high driving capability' + value: 2 + - name: HIGH + description: '''Xtal mode higher driving capability' + value: 3 enum/LSIPREDIV: bit_size: 1 variants: - - name: NONE - description: LSI not divided - value: 0 - - name: DIV_128 - description: LSI divided by 128 - value: 1 + - name: Div1 + description: LSI not divided + value: 0 + - name: Div128 + description: LSI divided by 128 + value: 1 enum/LTDCSEL: bit_size: 1 variants: - - name: PLL3_R - description: PLL3 “R” (pll3_r_ck) selected - value: 0 - - name: PLL2_R - description: PLL2 “R” (pll2_r_ck) selected - value: 1 + - name: PLL3_R + description: PLL3 “R” (pll3_r_ck) selected + value: 0 + - name: PLL2_R + description: PLL2 “R” (pll2_r_ck) selected + value: 1 enum/MCOPRE: bit_size: 3 variants: - - name: NONE - description: MCO divided by 1 - value: 0 - - name: DIV2 - description: MCO divided by 2 - value: 1 - - name: DIV4 - description: MCO divided by 4 - value: 2 - - name: DIV8 - description: MCO divided by 8 - value: 3 - - name: DIV16 - description: MCO divided by 16 - value: 4 + - name: Div1 + description: MCO divided by 1 + value: 0 + - name: Div2 + description: MCO divided by 2 + value: 1 + - name: Div4 + description: MCO divided by 4 + value: 2 + - name: Div8 + description: MCO divided by 8 + value: 3 + - name: Div16 + description: MCO divided by 16 + value: 4 enum/MCOSEL: bit_size: 4 variants: - - name: DISABLE - description: "MCO output disabled, no clock on MCO" - value: 0 - - name: SYSCLK - description: SYSCLK system clock selected - value: 1 - - name: MSIS - description: MSIS clock selected - value: 2 - - name: HSI16 - description: HSI16 clock selected - value: 3 - - name: HSE - description: HSE clock selected - value: 4 - - name: PLL1_R - description: Main PLL clock pll1_r_ck selected - value: 5 - - name: LSI - description: LSI clock selected - value: 6 - - name: LSE - description: LSE clock selected - value: 7 - - name: HSI48 - description: Internal HSI48 clock selected - value: 8 - - name: MSIK - description: MSIK clock selected - value: 9 + - name: DISABLE + description: MCO output disabled, no clock on MCO + value: 0 + - name: SYSCLK + description: SYSCLK system clock selected + value: 1 + - name: MSIS + description: MSIS clock selected + value: 2 + - name: HSI16 + description: HSI16 clock selected + value: 3 + - name: HSE + description: HSE clock selected + value: 4 + - name: PLL1_R + description: Main PLL clock pll1_r_ck selected + value: 5 + - name: LSI + description: LSI clock selected + value: 6 + - name: LSE + description: LSE clock selected + value: 7 + - name: HSI48 + description: Internal HSI48 clock selected + value: 8 + - name: MSIK + description: MSIK clock selected + value: 9 enum/MDFSEL: bit_size: 3 variants: - - name: HCLK - description: HCLK selected - value: 0 - - name: PLL1_P - description: PLL1 P (pll1_p_ck) selected - value: 1 - - name: PLL3_Q - description: PLL3 Q (pll3_q_ck) selected - value: 2 - - name: AUDIOCLK - description: input pin AUDIOCLK selected - value: 3 - - name: MSIK - description: MSIK clock selected - value: 4 + - name: HCLK + description: HCLK selected + value: 0 + - name: PLL1_P + description: PLL1 P (pll1_p_ck) selected + value: 1 + - name: PLL3_Q + description: PLL3 Q (pll3_q_ck) selected + value: 2 + - name: AUDIOCLK + description: input pin AUDIOCLK selected + value: 3 + - name: MSIK + description: MSIK clock selected + value: 4 enum/MSIBIAS: bit_size: 1 variants: - - name: CONTINUOUS - description: MSI bias continuous mode (clock accuracy fast settling time) - value: 0 - - name: SAMPLING - description: MSI bias sampling mode (ultra-low-power mode) - value: 1 + - name: CONTINUOUS + description: MSI bias continuous mode (clock accuracy fast settling time) + value: 0 + - name: SAMPLING + description: MSI bias sampling mode (ultra-low-power mode) + value: 1 enum/MSIPLLFAST: bit_size: 1 variants: - - name: NORMAL - description: MSI PLL normal start-up - value: 0 - - name: FAST - description: MSI PLL fast start-up - value: 1 + - name: NORMAL + description: MSI PLL normal start-up + value: 0 + - name: FAST + description: MSI PLL fast start-up + value: 1 enum/MSIPLLSEL: bit_size: 1 variants: - - name: MSIK - description: PLL mode applied to MSIK (MSI kernel) clock output - value: 0 - - name: MSIS - description: PLL mode applied to MSIS (MSI system) clock output - value: 1 + - name: MSIK + description: PLL mode applied to MSIK (MSI kernel) clock output + value: 0 + - name: MSIS + description: PLL mode applied to MSIS (MSI system) clock output + value: 1 enum/MSIRANGE: bit_size: 4 variants: - - name: RANGE_48MHZ - description: range 0 around 48 MHz - value: 0 - - name: RANGE_24MHZ - description: range 1 around 24 MHz - value: 1 - - name: RANGE_16MHZ - description: range 2 around 16 MHz - value: 2 - - name: RANGE_12MHZ - description: range 3 around 12 MHz - value: 3 - - name: RANGE_4MHZ - description: range 4 around 4 MHz (reset value) - value: 4 - - name: RANGE_2MHZ - description: range 5 around 2 MHz - value: 5 - - name: RANGE_1_33MHZ - description: range 6 around 1.33 MHz - value: 6 - - name: RANGE_1MHZ - description: range 7 around 1 MHz - value: 7 - - name: RANGE_3_072MHZ - description: range 8 around 3.072 MHz - value: 8 - - name: RANGE_1_536MHZ - description: range 9 around 1.536 MHz - value: 9 - - name: RANGE_1_024MHZ - description: range 10 around 1.024 MHz - value: 10 - - name: RANGE_768KHZ - description: range 11 around 768 kHz - value: 11 - - name: RANGE_400KHZ - description: range 12 around 400 kHz - value: 12 - - name: RANGE_200KHZ - description: range 13 around 200 kHz - value: 13 - - name: RANGE_133KHZ - description: range 14 around 133 kHz - value: 14 - - name: RANGE_100KHZ - description: range 15 around 100 kHz - value: 15 + - name: RANGE_48MHZ + description: range 0 around 48 MHz + value: 0 + - name: RANGE_24MHZ + description: range 1 around 24 MHz + value: 1 + - name: RANGE_16MHZ + description: range 2 around 16 MHz + value: 2 + - name: RANGE_12MHZ + description: range 3 around 12 MHz + value: 3 + - name: RANGE_4MHZ + description: range 4 around 4 MHz (reset value) + value: 4 + - name: RANGE_2MHZ + description: range 5 around 2 MHz + value: 5 + - name: RANGE_1_33MHZ + description: range 6 around 1.33 MHz + value: 6 + - name: RANGE_1MHZ + description: range 7 around 1 MHz + value: 7 + - name: RANGE_3_072MHZ + description: range 8 around 3.072 MHz + value: 8 + - name: RANGE_1_536MHZ + description: range 9 around 1.536 MHz + value: 9 + - name: RANGE_1_024MHZ + description: range 10 around 1.024 MHz + value: 10 + - name: RANGE_768KHZ + description: range 11 around 768 kHz + value: 11 + - name: RANGE_400KHZ + description: range 12 around 400 kHz + value: 12 + - name: RANGE_200KHZ + description: range 13 around 200 kHz + value: 13 + - name: RANGE_133KHZ + description: range 14 around 133 kHz + value: 14 + - name: RANGE_100KHZ + description: range 15 around 100 kHz + value: 15 enum/MSIRGSEL: bit_size: 1 variants: - - name: RCC_CSR - description: "MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR" - value: 0 - - name: RCC_ICSCR1 - description: "MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1" - value: 1 + - name: RCC_CSR + description: MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR + value: 0 + - name: RCC_ICSCR1 + description: MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1 + value: 1 enum/MSIXSRANGE: bit_size: 4 variants: - - name: RANGE_4MHZ - description: range 4 around 4M Hz (reset value) - value: 4 - - name: RANGE_2MHZ - description: range 5 around 2 MHz - value: 5 - - name: RANGE_1_5MHZ - description: range 6 around 1.5 MHz - value: 6 - - name: RANGE_1MHZ - description: range 7 around 1 MHz - value: 7 - - name: RANGE_3_072MHZ - description: range 8 around 3.072 MHz - value: 8 + - name: RANGE_4MHZ + description: range 4 around 4M Hz (reset value) + value: 4 + - name: RANGE_2MHZ + description: range 5 around 2 MHz + value: 5 + - name: RANGE_1_5MHZ + description: range 6 around 1.5 MHz + value: 6 + - name: RANGE_1MHZ + description: range 7 around 1 MHz + value: 7 + - name: RANGE_3_072MHZ + description: range 8 around 3.072 MHz + value: 8 enum/OCTOSPISEL: bit_size: 2 variants: - - name: SYSCLK - description: SYSCLK selected - value: 0 - - name: MSIK - description: MSIK selected - value: 1 - - name: PLL1_Q - description: "PLL1 Q (pll1_q_ck) selected, can be up to 200 MHz" - value: 2 - - name: PLL2_Q - description: "PLL2 Q (pll2_q_ck) selected, can be up to 200 MHz" - value: 3 + - name: SYSCLK + description: SYSCLK selected + value: 0 + - name: MSIK + description: MSIK selected + value: 1 + - name: PLL1_Q + description: PLL1 Q (pll1_q_ck) selected, can be up to 200 MHz + value: 2 + - name: PLL2_Q + description: PLL2 Q (pll2_q_ck) selected, can be up to 200 MHz + value: 3 enum/OTGHSSEL: bit_size: 2 variants: - - name: HSE - description: HSE selected - value: 0 - - name: PLL1_P - description: "PLL1 “P” (pll1_q_ck) selected," - value: 1 - - name: HSE_DIV2 - description: HSE/2 selected - value: 2 - - name: PLL1_P_DIV2 - description: PLL1 “P” divided by 2 (pll1_p_ck/2) selected - value: 3 + - name: HSE + description: HSE selected + value: 0 + - name: PLL1_P + description: PLL1 “P” (pll1_q_ck) selected, + value: 1 + - name: HSE_DIV2 + description: HSE/2 selected + value: 2 + - name: PLL1_P_DIV2 + description: PLL1 “P” divided by 2 (pll1_p_ck/2) selected + value: 3 enum/PLLM: bit_size: 4 variants: - - name: BYPASS - description: division by 1 (bypass) - value: 0 - - name: DIV2 - description: division by 2 - value: 1 - - name: DIV3 - description: division by 3 - value: 2 - - name: DIV16 - description: division by 16 - value: 15 + - name: BYPASS + description: division by 1 (bypass) + value: 0 + - name: Div2 + description: division by 2 + value: 1 + - name: Div3 + description: division by 3 + value: 2 + - name: Div16 + description: division by 16 + value: 15 enum/PLLMBOOST: bit_size: 4 variants: - - name: BYPASS - description: division by 1 (bypass) - value: 0 - - name: DIV2 - description: division by 2 - value: 1 - - name: DIV4 - description: division by 4 - value: 2 - - name: DIV6 - description: division by 6 - value: 3 - - name: DIV8 - description: division by 8 - value: 4 - - name: DIV10 - description: division by 10 - value: 5 - - name: DIV12 - description: division by 12 - value: 6 - - name: DIV14 - description: division by 14 - value: 7 - - name: DIV16 - description: division by 16 - value: 8 + - name: BYPASS + description: division by 1 (bypass) + value: 0 + - name: Div2 + description: division by 2 + value: 1 + - name: Div4 + description: division by 4 + value: 2 + - name: Div6 + description: division by 6 + value: 3 + - name: Div8 + description: division by 8 + value: 4 + - name: Div10 + description: division by 10 + value: 5 + - name: Div12 + description: division by 12 + value: 6 + - name: Div14 + description: division by 14 + value: 7 + - name: Div16 + description: division by 16 + value: 8 enum/PLLRGE: bit_size: 2 variants: - - name: FREQ_4TO8MHZ - description: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz - value: 0 - - name: FREQ_8TO16MHZ - description: PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz - value: 3 + - name: FREQ_4TO8MHZ + description: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz + value: 0 + - name: FREQ_8TO16MHZ + description: PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz + value: 3 enum/PLLSRC: bit_size: 2 variants: - - name: NONE - description: No clock sent to PLL3 - value: 0 - - name: MSIS - description: MSIS clock selected as PLL3 clock entry - value: 1 - - name: HSI16 - description: HSI16 clock selected as PLL3 clock entry - value: 2 - - name: HSE - description: HSE clock selected as PLL3 clock entry - value: 3 + - name: NONE + description: No clock sent to PLL3 + value: 0 + - name: MSIS + description: MSIS clock selected as PLL3 clock entry + value: 1 + - name: HSI16 + description: HSI16 clock selected as PLL3 clock entry + value: 2 + - name: HSE + description: HSE clock selected as PLL3 clock entry + value: 3 enum/PPRE: bit_size: 3 variants: - - name: NONE - description: HCLK not divided - value: 0 - - name: DIV2 - description: HCLK divided by 2 - value: 4 - - name: DIV4 - description: HCLK divided by 4 - value: 5 - - name: DIV8 - description: HCLK divided by 8 - value: 6 - - name: DIV16 - description: HCLK divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 enum/PRIV: bit_size: 1 variants: - - name: UNPRIVILEGED - description: Read and write to secure functions can be done by privileged or unprivileged access. - value: 0 - - name: PRIVILEGED - description: Read and write to secure functions can be done by privileged access only. - value: 1 + - name: UNPRIVILEGED + description: Read and write to secure functions can be done by privileged or unprivileged access. + value: 0 + - name: PRIVILEGED + description: Read and write to secure functions can be done by privileged access only. + value: 1 enum/RNGSEL: bit_size: 2 variants: - - name: HSI48 - description: HSI48 selected - value: 0 - - name: HSI48_DIV2 - description: "HSI48 / 2 selected, can be used in Range 4" - value: 1 - - name: HSI16 - description: HSI16 selected - value: 2 + - name: HSI48 + description: HSI48 selected + value: 0 + - name: HSI48_DIV2 + description: HSI48 / 2 selected, can be used in Range 4 + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 enum/RTCSEL: bit_size: 2 variants: - - name: NONE - description: No clock selected - value: 0 - - name: LSE - description: LSE oscillator clock selected - value: 1 - - name: LSI - description: LSI oscillator clock selected - value: 2 - - name: HSE - description: HSE oscillator clock divided by 32 selected - value: 3 + - name: NoClock + description: No clock selected + value: 0 + - name: LSE + description: LSE oscillator clock selected + value: 1 + - name: LSI + description: LSI oscillator clock selected + value: 2 + - name: HSE + description: HSE oscillator clock divided by 32 selected + value: 3 enum/SAESSEL: bit_size: 1 variants: - - name: SHSI - description: SHSI selected - value: 0 - - name: SHSI_DIV2 - description: "SHSI / 2 selected, can be used in Range 4" - value: 1 + - name: SHSI + description: SHSI selected + value: 0 + - name: SHSI_DIV2 + description: SHSI / 2 selected, can be used in Range 4 + value: 1 enum/SAISEL: bit_size: 3 variants: - - name: PLL2_P - description: PLL2 P (pll2_p_ck) selected - value: 0 - - name: PLL3_P - description: PLL3 P (pll3_p_ck) selected - value: 1 - - name: PLL1_P - description: PLL1 P (pll1_p_ck) selected - value: 2 - - name: AUDIOCLK - description: input pin AUDIOCLK selected - value: 3 - - name: HSI16 - description: HSI16 clock selected - value: 4 + - name: PLL2_P + description: PLL2 P (pll2_p_ck) selected + value: 0 + - name: PLL3_P + description: PLL3 P (pll3_p_ck) selected + value: 1 + - name: PLL1_P + description: PLL1 P (pll1_p_ck) selected + value: 2 + - name: AUDIOCLK + description: input pin AUDIOCLK selected + value: 3 + - name: HSI16 + description: HSI16 clock selected + value: 4 enum/SDMMCSEL: bit_size: 1 variants: - - name: ICLK - description: ICLK clock selected - value: 0 - - name: PLL1_P - description: "PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode)" - value: 1 + - name: ICLK + description: ICLK clock selected + value: 0 + - name: PLL1_P + description: PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) + value: 1 enum/SECURITY: bit_size: 1 variants: - - name: NON_SECURE - description: non secure - value: 0 - - name: SECURE - description: secure - value: 1 + - name: NON_SECURE + description: non secure + value: 0 + - name: SECURE + description: secure + value: 1 enum/SPISEL: bit_size: 2 variants: - - name: PCLK2 - description: PCLK2 selected - value: 0 - - name: SYSCLK - description: SYSCLK selected - value: 1 - - name: HSI16 - description: HSI16 selected - value: 2 - - name: MSIK - description: MSIK selected - value: 3 + - name: PCLK2 + description: PCLK2 selected + value: 0 + - name: SYSCLK + description: SYSCLK selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 + - name: MSIK + description: MSIK selected + value: 3 enum/STOPKERWUCK: bit_size: 1 variants: - - name: MSIK - description: MSIK oscillator automatically enabled when exiting Stop mode - value: 0 - - name: HSI16 - description: HSI16 oscillator automatically enabled when exiting Stop mode - value: 1 + - name: MSIK + description: MSIK oscillator automatically enabled when exiting Stop mode + value: 0 + - name: HSI16 + description: HSI16 oscillator automatically enabled when exiting Stop mode + value: 1 enum/STOPWUCK: bit_size: 1 variants: - - name: MSIS - description: MSIS oscillator selected as wakeup from stop clock and CSS backup clock - value: 0 - - name: HSI16 - description: HSI16 oscillator selected as wakeup from stop clock and CSS backup clock - value: 1 + - name: MSIS + description: MSIS oscillator selected as wakeup from stop clock and CSS backup clock + value: 0 + - name: HSI16 + description: HSI16 oscillator selected as wakeup from stop clock and CSS backup clock + value: 1 enum/SW: bit_size: 2 variants: - - name: MSIS - description: MSIS selected as system clock - value: 0 - - name: HSI16 - description: HSI16 selected as system clock - value: 1 - - name: HSE - description: HSE selected as system clock - value: 2 - - name: PLL1R - description: PLL pll1_r_ck selected as system clock - value: 3 + - name: MSIS + description: MSIS selected as system clock + value: 0 + - name: HSI16 + description: HSI16 selected as system clock + value: 1 + - name: HSE + description: HSE selected as system clock + value: 2 + - name: PLL1_R + description: PLL pll1_r_ck selected as system clock + value: 3 enum/SYSTICKSEL: bit_size: 2 variants: - - name: HCLK_DIV8 - description: HCLK/8 selected - value: 0 - - name: LSI - description: LSI selected - value: 1 - - name: LSE - description: LSE selected - value: 2 + - name: HCLK_DIV8 + description: HCLK/8 selected + value: 0 + - name: LSI + description: LSI selected + value: 1 + - name: LSE + description: LSE selected + value: 2 enum/TIMICSEL: bit_size: 3 variants: - - name: NONE - description: "No sources can be selected by TIM16, TIM17 and LPTIM2 as internal input capture" - value: 0 - - name: HSI256_MSIS1024_MSIS4 - description: "HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture" - value: 4 - - name: HSI256_MSIS1024_MSIK4 - description: "HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture" - value: 5 - - name: HSI256_MSIK1024_MSIS4 - description: "HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture" - value: 6 - - name: HSI256_MSIK1024_MSIK4 - description: "HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture" - value: 7 + - name: NONE + description: No sources can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + value: 0 + - name: HSI256_MSIS1024_MSIS4 + description: HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + value: 4 + - name: HSI256_MSIS1024_MSIK4 + description: HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + value: 5 + - name: HSI256_MSIK1024_MSIS4 + description: HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + value: 6 + - name: HSI256_MSIK1024_MSIK4 + description: HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + value: 7 enum/UARTSEL: bit_size: 2 variants: - - name: PCLK1 - description: PCLK1 selected - value: 0 - - name: SYSCLK - description: SYSCLK selected - value: 1 - - name: HSI16 - description: HSI16 selected - value: 2 - - name: LSE - description: LSE selected - value: 3 + - name: PCLK1 + description: PCLK1 selected + value: 0 + - name: SYSCLK + description: SYSCLK selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 + - name: LSE + description: LSE selected + value: 3 enum/USARTSEL: bit_size: 2 variants: - - name: PCLK2 - description: PCLK2 selected - value: 0 - - name: SYSCLK - description: SYSCLK selected - value: 1 - - name: HSI16 - description: HSI16 selected - value: 2 - - name: LSE - description: LSE selected - value: 3 + - name: PCLK2 + description: PCLK2 selected + value: 0 + - name: SYSCLK + description: SYSCLK selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 + - name: LSE + description: LSE selected + value: 3 diff --git a/data/registers/rcc_wb.yaml b/data/registers/rcc_wb.yaml index 6739c08..a0c7adc 100644 --- a/data/registers/rcc_wb.yaml +++ b/data/registers/rcc_wb.yaml @@ -1,1638 +1,1719 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: Clock control register - byte_offset: 0 - fieldset: CR - - name: ICSCR - description: Internal clock sources calibration register - byte_offset: 4 - fieldset: ICSCR - - name: CFGR - description: Clock configuration register - byte_offset: 8 - fieldset: CFGR - - name: PLLCFGR - description: PLLSYS configuration register - byte_offset: 12 - fieldset: PLLCFGR - - name: PLLSAI1CFGR - description: PLLSAI1 configuration register - byte_offset: 16 - fieldset: PLLSAI1CFGR - - name: CIER - description: Clock interrupt enable register - byte_offset: 24 - fieldset: CIER - - name: CIFR - description: Clock interrupt flag register - byte_offset: 28 - access: Read - fieldset: CIFR - - name: CICR - description: Clock interrupt clear register - byte_offset: 32 - access: Write - fieldset: CICR - - name: SMPSCR - description: Step Down converter control register - byte_offset: 36 - fieldset: SMPSCR - - name: AHB1RSTR - description: AHB1 peripheral reset register - byte_offset: 40 - fieldset: AHB1RSTR - - name: AHB2RSTR - description: AHB2 peripheral reset register - byte_offset: 44 - fieldset: AHB2RSTR - - name: AHB3RSTR - description: AHB3 peripheral reset register - byte_offset: 48 - fieldset: AHB3RSTR - - name: APB1RSTR1 - description: APB1 peripheral reset register 1 - byte_offset: 56 - fieldset: APB1RSTR1 - - name: APB1RSTR2 - description: APB1 peripheral reset register 2 - byte_offset: 60 - fieldset: APB1RSTR2 - - name: APB2RSTR - description: APB2 peripheral reset register - byte_offset: 64 - fieldset: APB2RSTR - - name: APB3RSTR - description: APB3 peripheral reset register - byte_offset: 68 - fieldset: APB3RSTR - - name: AHB1ENR - description: AHB1 peripheral clock enable register - byte_offset: 72 - fieldset: AHB1ENR - - name: AHB2ENR - description: AHB2 peripheral clock enable register - byte_offset: 76 - fieldset: AHB2ENR - - name: AHB3ENR - description: AHB3 peripheral clock enable register - byte_offset: 80 - fieldset: AHB3ENR - - name: APB1ENR1 - description: APB1ENR1 - byte_offset: 88 - fieldset: APB1ENR1 - - name: APB1ENR2 - description: APB1 peripheral clock enable register 2 - byte_offset: 92 - fieldset: APB1ENR2 - - name: APB2ENR - description: APB2ENR - byte_offset: 96 - fieldset: APB2ENR - - name: AHB1SMENR - description: AHB1 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 104 - fieldset: AHB1SMENR - - name: AHB2SMENR - description: AHB2 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 108 - fieldset: AHB2SMENR - - name: AHB3SMENR - description: AHB3 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 112 - fieldset: AHB3SMENR - - name: APB1SMENR1 - description: APB1SMENR1 - byte_offset: 120 - fieldset: APB1SMENR1 - - name: APB1SMENR2 - description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 - byte_offset: 124 - fieldset: APB1SMENR2 - - name: APB2SMENR - description: APB2SMENR - byte_offset: 128 - fieldset: APB2SMENR - - name: CCIPR - description: CCIPR - byte_offset: 136 - fieldset: CCIPR - - name: BDCR - description: BDCR - byte_offset: 144 - fieldset: BDCR - - name: CSR - description: CSR - byte_offset: 148 - fieldset: CSR - - name: CRRCR - description: Clock recovery RC register - byte_offset: 152 - fieldset: CRRCR - - name: HSECR - description: Clock HSE register - byte_offset: 156 - fieldset: HSECR - - name: EXTCFGR - description: Extended clock recovery register - byte_offset: 264 - fieldset: EXTCFGR - - name: C2AHB1ENR - description: CPU2 AHB1 peripheral clock enable register - byte_offset: 328 - fieldset: C2AHB1ENR - - name: C2AHB2ENR - description: CPU2 AHB2 peripheral clock enable register - byte_offset: 332 - fieldset: C2AHB2ENR - - name: C2AHB3ENR - description: CPU2 AHB3 peripheral clock enable register - byte_offset: 336 - fieldset: C2AHB3ENR - - name: C2APB1ENR1 - description: CPU2 APB1ENR1 - byte_offset: 344 - fieldset: C2APB1ENR1 - - name: C2APB1ENR2 - description: CPU2 APB1 peripheral clock enable register 2 - byte_offset: 348 - fieldset: C2APB1ENR2 - - name: C2APB2ENR - description: CPU2 APB2ENR - byte_offset: 352 - fieldset: C2APB2ENR - - name: C2APB3ENR - description: CPU2 APB3ENR - byte_offset: 356 - fieldset: C2APB3ENR - - name: C2AHB1SMENR - description: CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 360 - fieldset: C2AHB1SMENR - - name: C2AHB2SMENR - description: CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 364 - fieldset: C2AHB2SMENR - - name: C2AHB3SMENR - description: CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 368 - fieldset: C2AHB3SMENR - - name: C2APB1SMENR1 - description: CPU2 APB1SMENR1 - byte_offset: 376 - fieldset: C2APB1SMENR1 - - name: C2APB1SMENR2 - description: CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2 - byte_offset: 380 - fieldset: C2APB1SMENR2 - - name: C2APB2SMENR - description: CPU2 APB2SMENR - byte_offset: 384 - fieldset: C2APB2SMENR - - name: C2APB3SMENR - description: CPU2 APB3SMENR - byte_offset: 388 - fieldset: C2APB3SMENR + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: Internal clock sources calibration register + byte_offset: 4 + fieldset: ICSCR + - name: CFGR + description: Clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: PLLCFGR + description: PLLSYS configuration register + byte_offset: 12 + fieldset: PLLCFGR + - name: PLLSAI1CFGR + description: PLLSAI1 configuration register + byte_offset: 16 + fieldset: PLLSAI1CFGR + - name: CIER + description: Clock interrupt enable register + byte_offset: 24 + fieldset: CIER + - name: CIFR + description: Clock interrupt flag register + byte_offset: 28 + access: Read + fieldset: CIFR + - name: CICR + description: Clock interrupt clear register + byte_offset: 32 + access: Write + fieldset: CICR + - name: SMPSCR + description: Step Down converter control register + byte_offset: 36 + fieldset: SMPSCR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 40 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: AHB2 peripheral reset register + byte_offset: 44 + fieldset: AHB2RSTR + - name: AHB3RSTR + description: AHB3 peripheral reset register + byte_offset: 48 + fieldset: AHB3RSTR + - name: APB1RSTR1 + description: APB1 peripheral reset register 1 + byte_offset: 56 + fieldset: APB1RSTR1 + - name: APB1RSTR2 + description: APB1 peripheral reset register 2 + byte_offset: 60 + fieldset: APB1RSTR2 + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 64 + fieldset: APB2RSTR + - name: APB3RSTR + description: APB3 peripheral reset register + byte_offset: 68 + fieldset: APB3RSTR + - name: AHB1ENR + description: AHB1 peripheral clock enable register + byte_offset: 72 + fieldset: AHB1ENR + - name: AHB2ENR + description: AHB2 peripheral clock enable register + byte_offset: 76 + fieldset: AHB2ENR + - name: AHB3ENR + description: AHB3 peripheral clock enable register + byte_offset: 80 + fieldset: AHB3ENR + - name: APB1ENR1 + description: APB1ENR1 + byte_offset: 88 + fieldset: APB1ENR1 + - name: APB1ENR2 + description: APB1 peripheral clock enable register 2 + byte_offset: 92 + fieldset: APB1ENR2 + - name: APB2ENR + description: APB2ENR + byte_offset: 96 + fieldset: APB2ENR + - name: AHB1SMENR + description: AHB1 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 104 + fieldset: AHB1SMENR + - name: AHB2SMENR + description: AHB2 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 108 + fieldset: AHB2SMENR + - name: AHB3SMENR + description: AHB3 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 112 + fieldset: AHB3SMENR + - name: APB1SMENR1 + description: APB1SMENR1 + byte_offset: 120 + fieldset: APB1SMENR1 + - name: APB1SMENR2 + description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 + byte_offset: 124 + fieldset: APB1SMENR2 + - name: APB2SMENR + description: APB2SMENR + byte_offset: 128 + fieldset: APB2SMENR + - name: CCIPR + description: CCIPR + byte_offset: 136 + fieldset: CCIPR + - name: BDCR + description: BDCR + byte_offset: 144 + fieldset: BDCR + - name: CSR + description: CSR + byte_offset: 148 + fieldset: CSR + - name: CRRCR + description: Clock recovery RC register + byte_offset: 152 + fieldset: CRRCR + - name: HSECR + description: Clock HSE register + byte_offset: 156 + fieldset: HSECR + - name: EXTCFGR + description: Extended clock recovery register + byte_offset: 264 + fieldset: EXTCFGR + - name: C2AHB1ENR + description: CPU2 AHB1 peripheral clock enable register + byte_offset: 328 + fieldset: C2AHB1ENR + - name: C2AHB2ENR + description: CPU2 AHB2 peripheral clock enable register + byte_offset: 332 + fieldset: C2AHB2ENR + - name: C2AHB3ENR + description: CPU2 AHB3 peripheral clock enable register + byte_offset: 336 + fieldset: C2AHB3ENR + - name: C2APB1ENR1 + description: CPU2 APB1ENR1 + byte_offset: 344 + fieldset: C2APB1ENR1 + - name: C2APB1ENR2 + description: CPU2 APB1 peripheral clock enable register 2 + byte_offset: 348 + fieldset: C2APB1ENR2 + - name: C2APB2ENR + description: CPU2 APB2ENR + byte_offset: 352 + fieldset: C2APB2ENR + - name: C2APB3ENR + description: CPU2 APB3ENR + byte_offset: 356 + fieldset: C2APB3ENR + - name: C2AHB1SMENR + description: CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 360 + fieldset: C2AHB1SMENR + - name: C2AHB2SMENR + description: CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 364 + fieldset: C2AHB2SMENR + - name: C2AHB3SMENR + description: CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 368 + fieldset: C2AHB3SMENR + - name: C2APB1SMENR1 + description: CPU2 APB1SMENR1 + byte_offset: 376 + fieldset: C2APB1SMENR1 + - name: C2APB1SMENR2 + description: CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2 + byte_offset: 380 + fieldset: C2APB1SMENR2 + - name: C2APB2SMENR + description: CPU2 APB2SMENR + byte_offset: 384 + fieldset: C2APB2SMENR + - name: C2APB3SMENR + description: CPU2 APB3SMENR + byte_offset: 388 + fieldset: C2APB3SMENR fieldset/AHB1ENR: description: AHB1 peripheral clock enable register fields: - - name: DMA1EN - description: DMA1 clock enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: DMA2 clock enable - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1EN - description: DMAMUX clock enable - bit_offset: 2 - bit_size: 1 - - name: CRCEN - description: CPU1 CRC clock enable - bit_offset: 12 - bit_size: 1 - - name: TSCEN - description: Touch Sensing Controller clock enable - bit_offset: 16 - bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1EN + description: DMAMUX clock enable + bit_offset: 2 + bit_size: 1 + - name: CRCEN + description: CPU1 CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: TSCEN + description: Touch Sensing Controller clock enable + bit_offset: 16 + bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - - name: DMA1RST - description: DMA1 reset - bit_offset: 0 - bit_size: 1 - - name: DMA2RST - description: DMA2 reset - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1RST - description: DMAMUX reset - bit_offset: 2 - bit_size: 1 - - name: CRCRST - description: CRC reset - bit_offset: 12 - bit_size: 1 - - name: TSCRST - description: Touch Sensing Controller reset - bit_offset: 16 - bit_size: 1 + - name: DMA1RST + description: DMA1 reset + bit_offset: 0 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1RST + description: DMAMUX reset + bit_offset: 2 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 + - name: TSCRST + description: Touch Sensing Controller reset + bit_offset: 16 + bit_size: 1 fieldset/AHB1SMENR: description: AHB1 peripheral clocks enable in Sleep and Stop modes register fields: - - name: DMA1SMEN - description: CPU1 DMA1 clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: DMA2SMEN - description: CPU1 DMA2 clocks enable during Sleep and Stop modes - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1SMEN - description: CPU1 DMAMUX clocks enable during Sleep and Stop modes - bit_offset: 2 - bit_size: 1 - - name: SRAM1SMEN - description: CPU1 SRAM1 interface clocks enable during Sleep and Stop modes - bit_offset: 9 - bit_size: 1 - - name: CRCSMEN - description: CPU1 CRCSMEN - bit_offset: 12 - bit_size: 1 - - name: TSCSMEN - description: CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes - bit_offset: 16 - bit_size: 1 + - name: DMA1SMEN + description: CPU1 DMA1 clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: DMA2SMEN + description: CPU1 DMA2 clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1SMEN + description: CPU1 DMAMUX clocks enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: SRAM1SMEN + description: CPU1 SRAM1 interface clocks enable during Sleep and Stop modes + bit_offset: 9 + bit_size: 1 + - name: CRCSMEN + description: CPU1 CRCSMEN + bit_offset: 12 + bit_size: 1 + - name: TSCSMEN + description: CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes + bit_offset: 16 + bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - - name: GPIOAEN - description: IO port A clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: IO port B clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: IO port C clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: IO port D clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: IO port E clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIOHEN - description: IO port H clock enable - bit_offset: 7 - bit_size: 1 - - name: ADCEN - description: ADC clock enable - bit_offset: 13 - bit_size: 1 - - name: AES1EN - description: AES1 accelerator clock enable - bit_offset: 16 - bit_size: 1 + - name: GPIOAEN + description: IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: IO port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: IO port E clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOHEN + description: IO port H clock enable + bit_offset: 7 + bit_size: 1 + - name: ADCEN + description: ADC clock enable + bit_offset: 13 + bit_size: 1 + - name: AES1EN + description: AES1 accelerator clock enable + bit_offset: 16 + bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - - name: GPIOARST - description: IO port A reset - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: IO port B reset - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: IO port C reset - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: IO port D reset - bit_offset: 3 - bit_size: 1 - - name: GPIOERST - description: IO port E reset - bit_offset: 4 - bit_size: 1 - - name: GPIOHRST - description: IO port H reset - bit_offset: 7 - bit_size: 1 - - name: ADCRST - description: ADC reset - bit_offset: 13 - bit_size: 1 - - name: AES1RST - description: AES1 hardware accelerator reset - bit_offset: 16 - bit_size: 1 + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 4 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 7 + bit_size: 1 + - name: ADCRST + description: ADC reset + bit_offset: 13 + bit_size: 1 + - name: AES1RST + description: AES1 hardware accelerator reset + bit_offset: 16 + bit_size: 1 fieldset/AHB2SMENR: description: AHB2 peripheral clocks enable in Sleep and Stop modes register fields: - - name: GPIOASMEN - description: CPU1 IO port A clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: GPIOBSMEN - description: CPU1 IO port B clocks enable during Sleep and Stop modes - bit_offset: 1 - bit_size: 1 - - name: GPIOCSMEN - description: CPU1 IO port C clocks enable during Sleep and Stop modes - bit_offset: 2 - bit_size: 1 - - name: GPIODSMEN - description: CPU1 IO port D clocks enable during Sleep and Stop modes - bit_offset: 3 - bit_size: 1 - - name: GPIOESMEN - description: CPU1 IO port E clocks enable during Sleep and Stop modes - bit_offset: 4 - bit_size: 1 - - name: GPIOHSMEN - description: CPU1 IO port H clocks enable during Sleep and Stop modes - bit_offset: 7 - bit_size: 1 - - name: ADCFSSMEN - description: CPU1 ADC clocks enable during Sleep and Stop modes - bit_offset: 13 - bit_size: 1 - - name: AES1SMEN - description: CPU1 AES1 accelerator clocks enable during Sleep and Stop modes - bit_offset: 16 - bit_size: 1 + - name: GPIOASMEN + description: CPU1 IO port A clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: CPU1 IO port B clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: CPU1 IO port C clocks enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: GPIODSMEN + description: CPU1 IO port D clocks enable during Sleep and Stop modes + bit_offset: 3 + bit_size: 1 + - name: GPIOESMEN + description: CPU1 IO port E clocks enable during Sleep and Stop modes + bit_offset: 4 + bit_size: 1 + - name: GPIOHSMEN + description: CPU1 IO port H clocks enable during Sleep and Stop modes + bit_offset: 7 + bit_size: 1 + - name: ADCFSSMEN + description: CPU1 ADC clocks enable during Sleep and Stop modes + bit_offset: 13 + bit_size: 1 + - name: AES1SMEN + description: CPU1 AES1 accelerator clocks enable during Sleep and Stop modes + bit_offset: 16 + bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: - - name: QUADSPIEN - description: QUADSPIEN - bit_offset: 8 - bit_size: 1 - - name: PKAEN - description: PKAEN - bit_offset: 16 - bit_size: 1 - - name: AES2EN - description: AES2EN - bit_offset: 17 - bit_size: 1 - - name: RNGEN - description: RNGEN - bit_offset: 18 - bit_size: 1 - - name: HSEMEN - description: HSEMEN - bit_offset: 19 - bit_size: 1 - - name: IPCCEN - description: IPCCEN - bit_offset: 20 - bit_size: 1 - - name: FLASHEN - description: FLASHEN - bit_offset: 25 - bit_size: 1 + - name: QUADSPIEN + description: QUADSPIEN + bit_offset: 8 + bit_size: 1 + - name: PKAEN + description: PKAEN + bit_offset: 16 + bit_size: 1 + - name: AES2EN + description: AES2EN + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: RNGEN + bit_offset: 18 + bit_size: 1 + - name: HSEMEN + description: HSEMEN + bit_offset: 19 + bit_size: 1 + - name: IPCCEN + description: IPCCEN + bit_offset: 20 + bit_size: 1 + - name: FLASHEN + description: FLASHEN + bit_offset: 25 + bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - - name: QSPIRST - description: Quad SPI memory interface reset - bit_offset: 8 - bit_size: 1 - - name: PKARST - description: PKA interface reset - bit_offset: 16 - bit_size: 1 - - name: AES2RST - description: AES2 interface reset - bit_offset: 17 - bit_size: 1 - - name: RNGRST - description: RNG interface reset - bit_offset: 18 - bit_size: 1 - - name: HSEMRST - description: HSEM interface reset - bit_offset: 19 - bit_size: 1 - - name: IPCCRST - description: IPCC interface reset - bit_offset: 20 - bit_size: 1 - - name: FLASHRST - description: Flash interface reset - bit_offset: 25 - bit_size: 1 + - name: QSPIRST + description: Quad SPI memory interface reset + bit_offset: 8 + bit_size: 1 + - name: PKARST + description: PKA interface reset + bit_offset: 16 + bit_size: 1 + - name: AES2RST + description: AES2 interface reset + bit_offset: 17 + bit_size: 1 + - name: RNGRST + description: RNG interface reset + bit_offset: 18 + bit_size: 1 + - name: HSEMRST + description: HSEM interface reset + bit_offset: 19 + bit_size: 1 + - name: IPCCRST + description: IPCC interface reset + bit_offset: 20 + bit_size: 1 + - name: FLASHRST + description: Flash interface reset + bit_offset: 25 + bit_size: 1 fieldset/AHB3SMENR: description: AHB3 peripheral clocks enable in Sleep and Stop modes register fields: - - name: QSPISMEN - description: QSPISMEN - bit_offset: 8 - bit_size: 1 - - name: PKASMEN - description: PKA accelerator clocks enable during CPU1 sleep mode - bit_offset: 16 - bit_size: 1 - - name: AES2SMEN - description: AES2 accelerator clocks enable during CPU1 sleep mode - bit_offset: 17 - bit_size: 1 - - name: RNGSMEN - description: True RNG clocks enable during CPU1 sleep mode - bit_offset: 18 - bit_size: 1 - - name: SRAM2SMEN - description: SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode - bit_offset: 24 - bit_size: 1 - - name: FLASHSMEN - description: Flash interface clocks enable during CPU1 sleep mode - bit_offset: 25 - bit_size: 1 + - name: QSPISMEN + description: QSPISMEN + bit_offset: 8 + bit_size: 1 + - name: PKASMEN + description: PKA accelerator clocks enable during CPU1 sleep mode + bit_offset: 16 + bit_size: 1 + - name: AES2SMEN + description: AES2 accelerator clocks enable during CPU1 sleep mode + bit_offset: 17 + bit_size: 1 + - name: RNGSMEN + description: True RNG clocks enable during CPU1 sleep mode + bit_offset: 18 + bit_size: 1 + - name: SRAM2SMEN + description: SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode + bit_offset: 24 + bit_size: 1 + - name: FLASHSMEN + description: Flash interface clocks enable during CPU1 sleep mode + bit_offset: 25 + bit_size: 1 fieldset/APB1ENR1: description: APB1ENR1 fields: - - name: TIM2EN - description: CPU1 TIM2 timer clock enable - bit_offset: 0 - bit_size: 1 - - name: LCDEN - description: CPU1 LCD clock enable - bit_offset: 9 - bit_size: 1 - - name: RTCAPBEN - description: CPU1 RTC APB clock enable - bit_offset: 10 - bit_size: 1 - - name: WWDGEN - description: CPU1 Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: CPU1 SPI2 clock enable - bit_offset: 14 - bit_size: 1 - - name: I2C1EN - description: CPU1 I2C1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C3EN - description: CPU1 I2C3 clock enable - bit_offset: 23 - bit_size: 1 - - name: CRSEN - description: CPU1 CRS clock enable - bit_offset: 24 - bit_size: 1 - - name: USBEN - description: CPU1 USB clock enable - bit_offset: 26 - bit_size: 1 - - name: LPTIM1EN - description: CPU1 Low power timer 1 clock enable - bit_offset: 31 - bit_size: 1 + - name: TIM2EN + description: CPU1 TIM2 timer clock enable + bit_offset: 0 + bit_size: 1 + - name: LCDEN + description: CPU1 LCD clock enable + bit_offset: 9 + bit_size: 1 + - name: RTCAPBEN + description: CPU1 RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: CPU1 Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: CPU1 SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: I2C1EN + description: CPU1 I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C3EN + description: CPU1 I2C3 clock enable + bit_offset: 23 + bit_size: 1 + - name: CRSEN + description: CPU1 CRS clock enable + bit_offset: 24 + bit_size: 1 + - name: USBEN + description: CPU1 USB clock enable + bit_offset: 26 + bit_size: 1 + - name: LPTIM1EN + description: CPU1 Low power timer 1 clock enable + bit_offset: 31 + bit_size: 1 fieldset/APB1ENR2: description: APB1 peripheral clock enable register 2 fields: - - name: LPUART1EN - description: CPU1 Low power UART 1 clock enable - bit_offset: 0 - bit_size: 1 - - name: LPTIM2EN - description: CPU1 LPTIM2EN - bit_offset: 5 - bit_size: 1 + - name: LPUART1EN + description: CPU1 Low power UART 1 clock enable + bit_offset: 0 + bit_size: 1 + - name: LPTIM2EN + description: CPU1 LPTIM2EN + bit_offset: 5 + bit_size: 1 fieldset/APB1RSTR1: description: APB1 peripheral reset register 1 fields: - - name: TIM2RST - description: TIM2 timer reset - bit_offset: 0 - bit_size: 1 - - name: LCDRST - description: LCD interface reset - bit_offset: 9 - bit_size: 1 - - name: SPI2RST - description: SPI2 reset - bit_offset: 14 - bit_size: 1 - - name: I2C1RST - description: I2C1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C3RST - description: I2C3 reset - bit_offset: 23 - bit_size: 1 - - name: CRSRST - description: CRS reset - bit_offset: 24 - bit_size: 1 - - name: USBRST - description: USB FS reset - bit_offset: 26 - bit_size: 1 - - name: LPTIM1RST - description: Low Power Timer 1 reset - bit_offset: 31 - bit_size: 1 + - name: TIM2RST + description: TIM2 timer reset + bit_offset: 0 + bit_size: 1 + - name: LCDRST + description: LCD interface reset + bit_offset: 9 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 23 + bit_size: 1 + - name: CRSRST + description: CRS reset + bit_offset: 24 + bit_size: 1 + - name: USBRST + description: USB FS reset + bit_offset: 26 + bit_size: 1 + - name: LPTIM1RST + description: Low Power Timer 1 reset + bit_offset: 31 + bit_size: 1 fieldset/APB1RSTR2: description: APB1 peripheral reset register 2 fields: - - name: LPUART1RST - description: Low-power UART 1 reset - bit_offset: 0 - bit_size: 1 - - name: LPTIM2RST - description: Low-power timer 2 reset - bit_offset: 5 - bit_size: 1 + - name: LPUART1RST + description: Low-power UART 1 reset + bit_offset: 0 + bit_size: 1 + - name: LPTIM2RST + description: Low-power timer 2 reset + bit_offset: 5 + bit_size: 1 fieldset/APB1SMENR1: description: APB1SMENR1 fields: - - name: TIM2SMEN - description: TIM2 timer clocks enable during CPU1 Sleep mode - bit_offset: 0 - bit_size: 1 - - name: LCDSMEN - description: LCD clocks enable during CPU1 Sleep mode - bit_offset: 9 - bit_size: 1 - - name: RTCAPBSMEN - description: RTC APB clocks enable during CPU1 Sleep mode - bit_offset: 10 - bit_size: 1 - - name: WWDGSMEN - description: Window watchdog clocks enable during CPU1 Sleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI2SMEN - description: SPI2 clocks enable during CPU1 Sleep mode - bit_offset: 14 - bit_size: 1 - - name: I2C1SMEN - description: I2C1 clocks enable during CPU1 Sleep mode - bit_offset: 21 - bit_size: 1 - - name: I2C3SMEN - description: I2C3 clocks enable during CPU1 Sleep mode - bit_offset: 23 - bit_size: 1 - - name: CRSMEN - description: CRS clocks enable during CPU1 Sleep mode - bit_offset: 24 - bit_size: 1 - - name: USBSMEN - description: USB FS clocks enable during CPU1 Sleep mode - bit_offset: 26 - bit_size: 1 - - name: LPTIM1SMEN - description: Low power timer 1 clocks enable during CPU1 Sleep mode - bit_offset: 31 - bit_size: 1 + - name: TIM2SMEN + description: TIM2 timer clocks enable during CPU1 Sleep mode + bit_offset: 0 + bit_size: 1 + - name: LCDSMEN + description: LCD clocks enable during CPU1 Sleep mode + bit_offset: 9 + bit_size: 1 + - name: RTCAPBSMEN + description: RTC APB clocks enable during CPU1 Sleep mode + bit_offset: 10 + bit_size: 1 + - name: WWDGSMEN + description: Window watchdog clocks enable during CPU1 Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI2SMEN + description: SPI2 clocks enable during CPU1 Sleep mode + bit_offset: 14 + bit_size: 1 + - name: I2C1SMEN + description: I2C1 clocks enable during CPU1 Sleep mode + bit_offset: 21 + bit_size: 1 + - name: I2C3SMEN + description: I2C3 clocks enable during CPU1 Sleep mode + bit_offset: 23 + bit_size: 1 + - name: CRSMEN + description: CRS clocks enable during CPU1 Sleep mode + bit_offset: 24 + bit_size: 1 + - name: USBSMEN + description: USB FS clocks enable during CPU1 Sleep mode + bit_offset: 26 + bit_size: 1 + - name: LPTIM1SMEN + description: Low power timer 1 clocks enable during CPU1 Sleep mode + bit_offset: 31 + bit_size: 1 fieldset/APB1SMENR2: description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 fields: - - name: LPUART1SMEN - description: Low power UART 1 clocks enable during CPU1 Sleep mode - bit_offset: 0 - bit_size: 1 - - name: LPTIM2SMEN - description: Low power timer 2 clocks enable during CPU1 Sleep mode - bit_offset: 5 - bit_size: 1 + - name: LPUART1SMEN + description: Low power UART 1 clocks enable during CPU1 Sleep mode + bit_offset: 0 + bit_size: 1 + - name: LPTIM2SMEN + description: Low power timer 2 clocks enable during CPU1 Sleep mode + bit_offset: 5 + bit_size: 1 fieldset/APB2ENR: description: APB2ENR fields: - - name: TIM1EN - description: CPU1 TIM1 timer clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: CPU1 SPI1 clock enable - bit_offset: 12 - bit_size: 1 - - name: USART1EN - description: CPU1 USART1clock enable - bit_offset: 14 - bit_size: 1 - - name: TIM16EN - description: CPU1 TIM16 timer clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: CPU1 TIM17 timer clock enable - bit_offset: 18 - bit_size: 1 - - name: SAI1EN - description: CPU1 SAI1 clock enable - bit_offset: 21 - bit_size: 1 + - name: TIM1EN + description: CPU1 TIM1 timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: CPU1 SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: CPU1 USART1clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM16EN + description: CPU1 TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: CPU1 TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: SAI1EN + description: CPU1 SAI1 clock enable + bit_offset: 21 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - - name: TIM1RST - description: TIM1 timer reset - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: SPI1 reset - bit_offset: 12 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 14 - bit_size: 1 - - name: TIM16RST - description: TIM16 timer reset - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: TIM17 timer reset - bit_offset: 18 - bit_size: 1 - - name: SAI1RST - description: Serial audio interface 1 (SAI1) reset - bit_offset: 21 - bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI1 reset + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: SAI1RST + description: Serial audio interface 1 (SAI1) reset + bit_offset: 21 + bit_size: 1 fieldset/APB2SMENR: description: APB2SMENR fields: - - name: TIM1SMEN - description: TIM1 timer clocks enable during CPU1 Sleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI1SMEN - description: SPI1 clocks enable during CPU1 Sleep mode - bit_offset: 12 - bit_size: 1 - - name: USART1SMEN - description: USART1clocks enable during CPU1 Sleep mode - bit_offset: 14 - bit_size: 1 - - name: TIM16SMEN - description: TIM16 timer clocks enable during CPU1 Sleep mode - bit_offset: 17 - bit_size: 1 - - name: TIM17SMEN - description: TIM17 timer clocks enable during CPU1 Sleep mode - bit_offset: 18 - bit_size: 1 - - name: SAI1SMEN - description: SAI1 clocks enable during CPU1 Sleep mode - bit_offset: 21 - bit_size: 1 + - name: TIM1SMEN + description: TIM1 timer clocks enable during CPU1 Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: SPI1 clocks enable during CPU1 Sleep mode + bit_offset: 12 + bit_size: 1 + - name: USART1SMEN + description: USART1clocks enable during CPU1 Sleep mode + bit_offset: 14 + bit_size: 1 + - name: TIM16SMEN + description: TIM16 timer clocks enable during CPU1 Sleep mode + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: TIM17 timer clocks enable during CPU1 Sleep mode + bit_offset: 18 + bit_size: 1 + - name: SAI1SMEN + description: SAI1 clocks enable during CPU1 Sleep mode + bit_offset: 21 + bit_size: 1 fieldset/APB3RSTR: description: APB3 peripheral reset register fields: - - name: RFRST - description: Radio system BLE reset - bit_offset: 0 - bit_size: 1 + - name: RFRST + description: Radio system BLE reset + bit_offset: 0 + bit_size: 1 fieldset/BDCR: description: BDCR fields: - - name: LSEON - description: LSE oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: LSE oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: LSE oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: LSEDRV - description: SE oscillator drive capability - bit_offset: 3 - bit_size: 2 - - name: LSECSSON - description: LSECSSON - bit_offset: 5 - bit_size: 1 - - name: LSECSSD_ - description: CSS on LSE failure detection - bit_offset: 6 - bit_size: 1 - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: Backup domain software reset - bit_offset: 16 - bit_size: 1 - - name: LSCOEN - description: Low speed clock output enable - bit_offset: 24 - bit_size: 1 - - name: LSCOSEL - description: Low speed clock output selection - bit_offset: 25 - bit_size: 2 + - name: LSEON + description: LSE oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: LSE oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: LSE oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: SE oscillator drive capability + bit_offset: 3 + bit_size: 2 + - name: LSECSSON + description: LSECSSON + bit_offset: 5 + bit_size: 1 + - name: LSECSSD_ + description: CSS on LSE failure detection + bit_offset: 6 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: Low speed clock output enable + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: Low speed clock output selection + bit_offset: 25 + bit_size: 2 fieldset/C2AHB1ENR: description: CPU2 AHB1 peripheral clock enable register fields: - - name: DMA1EN - description: CPU2 DMA1 clock enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: CPU2 DMA2 clock enable - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1EN - description: CPU2 DMAMUX clock enable - bit_offset: 2 - bit_size: 1 - - name: SRAM1EN - description: CPU2 SRAM1 clock enable - bit_offset: 9 - bit_size: 1 - - name: CRCEN - description: CPU2 CRC clock enable - bit_offset: 12 - bit_size: 1 - - name: TSCEN - description: CPU2 Touch Sensing Controller clock enable - bit_offset: 16 - bit_size: 1 + - name: DMA1EN + description: CPU2 DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: CPU2 DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1EN + description: CPU2 DMAMUX clock enable + bit_offset: 2 + bit_size: 1 + - name: SRAM1EN + description: CPU2 SRAM1 clock enable + bit_offset: 9 + bit_size: 1 + - name: CRCEN + description: CPU2 CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: TSCEN + description: CPU2 Touch Sensing Controller clock enable + bit_offset: 16 + bit_size: 1 fieldset/C2AHB1SMENR: description: CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register fields: - - name: DMA1SMEN - description: CPU2 DMA1 clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: DMA2SMEN - description: CPU2 DMA2 clocks enable during Sleep and Stop modes - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1SMEN - description: CPU2 DMAMUX clocks enable during Sleep and Stop modes - bit_offset: 2 - bit_size: 1 - - name: SRAM1SMEN - description: SRAM1 interface clock enable during CPU1 CSleep mode - bit_offset: 9 - bit_size: 1 - - name: CRCSMEN - description: CPU2 CRCSMEN - bit_offset: 12 - bit_size: 1 - - name: TSCSMEN - description: CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes - bit_offset: 16 - bit_size: 1 + - name: DMA1SMEN + description: CPU2 DMA1 clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: DMA2SMEN + description: CPU2 DMA2 clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1SMEN + description: CPU2 DMAMUX clocks enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: SRAM1SMEN + description: SRAM1 interface clock enable during CPU1 CSleep mode + bit_offset: 9 + bit_size: 1 + - name: CRCSMEN + description: CPU2 CRCSMEN + bit_offset: 12 + bit_size: 1 + - name: TSCSMEN + description: CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes + bit_offset: 16 + bit_size: 1 fieldset/C2AHB2ENR: description: CPU2 AHB2 peripheral clock enable register fields: - - name: GPIOAEN - description: CPU2 IO port A clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: CPU2 IO port B clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: CPU2 IO port C clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: CPU2 IO port D clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: CPU2 IO port E clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIOHEN - description: CPU2 IO port H clock enable - bit_offset: 7 - bit_size: 1 - - name: ADCEN - description: CPU2 ADC clock enable - bit_offset: 13 - bit_size: 1 - - name: AES1EN - description: CPU2 AES1 accelerator clock enable - bit_offset: 16 - bit_size: 1 + - name: GPIOAEN + description: CPU2 IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: CPU2 IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: CPU2 IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: CPU2 IO port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: CPU2 IO port E clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOHEN + description: CPU2 IO port H clock enable + bit_offset: 7 + bit_size: 1 + - name: ADCEN + description: CPU2 ADC clock enable + bit_offset: 13 + bit_size: 1 + - name: AES1EN + description: CPU2 AES1 accelerator clock enable + bit_offset: 16 + bit_size: 1 fieldset/C2AHB2SMENR: description: CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register fields: - - name: GPIOASMEN - description: CPU2 IO port A clocks enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 - - name: GPIOBSMEN - description: CPU2 IO port B clocks enable during Sleep and Stop modes - bit_offset: 1 - bit_size: 1 - - name: GPIOCSMEN - description: CPU2 IO port C clocks enable during Sleep and Stop modes - bit_offset: 2 - bit_size: 1 - - name: GPIODSMEN - description: CPU2 IO port D clocks enable during Sleep and Stop modes - bit_offset: 3 - bit_size: 1 - - name: GPIOESMEN - description: CPU2 IO port E clocks enable during Sleep and Stop modes - bit_offset: 4 - bit_size: 1 - - name: GPIOHSMEN - description: CPU2 IO port H clocks enable during Sleep and Stop modes - bit_offset: 7 - bit_size: 1 - - name: ADCFSSMEN - description: CPU2 ADC clocks enable during Sleep and Stop modes - bit_offset: 13 - bit_size: 1 - - name: AES1SMEN - description: CPU2 AES1 accelerator clocks enable during Sleep and Stop modes - bit_offset: 16 - bit_size: 1 + - name: GPIOASMEN + description: CPU2 IO port A clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: CPU2 IO port B clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: CPU2 IO port C clocks enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: GPIODSMEN + description: CPU2 IO port D clocks enable during Sleep and Stop modes + bit_offset: 3 + bit_size: 1 + - name: GPIOESMEN + description: CPU2 IO port E clocks enable during Sleep and Stop modes + bit_offset: 4 + bit_size: 1 + - name: GPIOHSMEN + description: CPU2 IO port H clocks enable during Sleep and Stop modes + bit_offset: 7 + bit_size: 1 + - name: ADCFSSMEN + description: CPU2 ADC clocks enable during Sleep and Stop modes + bit_offset: 13 + bit_size: 1 + - name: AES1SMEN + description: CPU2 AES1 accelerator clocks enable during Sleep and Stop modes + bit_offset: 16 + bit_size: 1 fieldset/C2AHB3ENR: description: CPU2 AHB3 peripheral clock enable register fields: - - name: PKAEN - description: CPU2 PKAEN - bit_offset: 16 - bit_size: 1 - - name: AES2EN - description: CPU2 AES2EN - bit_offset: 17 - bit_size: 1 - - name: RNGEN - description: CPU2 RNGEN - bit_offset: 18 - bit_size: 1 - - name: HSEMEN - description: CPU2 HSEMEN - bit_offset: 19 - bit_size: 1 - - name: IPCCEN - description: CPU2 IPCCEN - bit_offset: 20 - bit_size: 1 - - name: FLASHEN - description: CPU2 FLASHEN - bit_offset: 25 - bit_size: 1 + - name: PKAEN + description: CPU2 PKAEN + bit_offset: 16 + bit_size: 1 + - name: AES2EN + description: CPU2 AES2EN + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: CPU2 RNGEN + bit_offset: 18 + bit_size: 1 + - name: HSEMEN + description: CPU2 HSEMEN + bit_offset: 19 + bit_size: 1 + - name: IPCCEN + description: CPU2 IPCCEN + bit_offset: 20 + bit_size: 1 + - name: FLASHEN + description: CPU2 FLASHEN + bit_offset: 25 + bit_size: 1 fieldset/C2AHB3SMENR: description: CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register fields: - - name: PKASMEN - description: PKA accelerator clocks enable during CPU2 sleep modes - bit_offset: 16 - bit_size: 1 - - name: AES2SMEN - description: AES2 accelerator clocks enable during CPU2 sleep modes - bit_offset: 17 - bit_size: 1 - - name: RNGSMEN - description: True RNG clocks enable during CPU2 sleep modes - bit_offset: 18 - bit_size: 1 - - name: SRAM2SMEN - description: SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes - bit_offset: 24 - bit_size: 1 - - name: FLASHSMEN - description: Flash interface clocks enable during CPU2 sleep modes - bit_offset: 25 - bit_size: 1 + - name: PKASMEN + description: PKA accelerator clocks enable during CPU2 sleep modes + bit_offset: 16 + bit_size: 1 + - name: AES2SMEN + description: AES2 accelerator clocks enable during CPU2 sleep modes + bit_offset: 17 + bit_size: 1 + - name: RNGSMEN + description: True RNG clocks enable during CPU2 sleep modes + bit_offset: 18 + bit_size: 1 + - name: SRAM2SMEN + description: SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes + bit_offset: 24 + bit_size: 1 + - name: FLASHSMEN + description: Flash interface clocks enable during CPU2 sleep modes + bit_offset: 25 + bit_size: 1 fieldset/C2APB1ENR1: description: CPU2 APB1ENR1 fields: - - name: TIM2EN - description: CPU2 TIM2 timer clock enable - bit_offset: 0 - bit_size: 1 - - name: LCDEN - description: CPU2 LCD clock enable - bit_offset: 9 - bit_size: 1 - - name: RTCAPBEN - description: CPU2 RTC APB clock enable - bit_offset: 10 - bit_size: 1 - - name: SPI2EN - description: CPU2 SPI2 clock enable - bit_offset: 14 - bit_size: 1 - - name: I2C1EN - description: CPU2 I2C1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C3EN - description: CPU2 I2C3 clock enable - bit_offset: 23 - bit_size: 1 - - name: CRSEN - description: CPU2 CRS clock enable - bit_offset: 24 - bit_size: 1 - - name: USBEN - description: CPU2 USB clock enable - bit_offset: 26 - bit_size: 1 - - name: LPTIM1EN - description: CPU2 Low power timer 1 clock enable - bit_offset: 31 - bit_size: 1 + - name: TIM2EN + description: CPU2 TIM2 timer clock enable + bit_offset: 0 + bit_size: 1 + - name: LCDEN + description: CPU2 LCD clock enable + bit_offset: 9 + bit_size: 1 + - name: RTCAPBEN + description: CPU2 RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: SPI2EN + description: CPU2 SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: I2C1EN + description: CPU2 I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C3EN + description: CPU2 I2C3 clock enable + bit_offset: 23 + bit_size: 1 + - name: CRSEN + description: CPU2 CRS clock enable + bit_offset: 24 + bit_size: 1 + - name: USBEN + description: CPU2 USB clock enable + bit_offset: 26 + bit_size: 1 + - name: LPTIM1EN + description: CPU2 Low power timer 1 clock enable + bit_offset: 31 + bit_size: 1 fieldset/C2APB1ENR2: description: CPU2 APB1 peripheral clock enable register 2 fields: - - name: LPUART1EN - description: CPU2 Low power UART 1 clock enable - bit_offset: 0 - bit_size: 1 - - name: LPTIM2EN - description: CPU2 LPTIM2EN - bit_offset: 5 - bit_size: 1 + - name: LPUART1EN + description: CPU2 Low power UART 1 clock enable + bit_offset: 0 + bit_size: 1 + - name: LPTIM2EN + description: CPU2 LPTIM2EN + bit_offset: 5 + bit_size: 1 fieldset/C2APB1SMENR1: description: CPU2 APB1SMENR1 fields: - - name: TIM2SMEN - description: TIM2 timer clocks enable during CPU2 Sleep mode - bit_offset: 0 - bit_size: 1 - - name: LCDSMEN - description: LCD clocks enable during CPU2 Sleep mode - bit_offset: 9 - bit_size: 1 - - name: RTCAPBSMEN - description: RTC APB clocks enable during CPU2 Sleep mode - bit_offset: 10 - bit_size: 1 - - name: SPI2SMEN - description: SPI2 clocks enable during CPU2 Sleep mode - bit_offset: 14 - bit_size: 1 - - name: I2C1SMEN - description: I2C1 clocks enable during CPU2 Sleep mode - bit_offset: 21 - bit_size: 1 - - name: I2C3SMEN - description: I2C3 clocks enable during CPU2 Sleep mode - bit_offset: 23 - bit_size: 1 - - name: CRSMEN - description: CRS clocks enable during CPU2 Sleep mode - bit_offset: 24 - bit_size: 1 - - name: USBSMEN - description: USB FS clocks enable during CPU2 Sleep mode - bit_offset: 26 - bit_size: 1 - - name: LPTIM1SMEN - description: Low power timer 1 clocks enable during CPU2 Sleep mode - bit_offset: 31 - bit_size: 1 + - name: TIM2SMEN + description: TIM2 timer clocks enable during CPU2 Sleep mode + bit_offset: 0 + bit_size: 1 + - name: LCDSMEN + description: LCD clocks enable during CPU2 Sleep mode + bit_offset: 9 + bit_size: 1 + - name: RTCAPBSMEN + description: RTC APB clocks enable during CPU2 Sleep mode + bit_offset: 10 + bit_size: 1 + - name: SPI2SMEN + description: SPI2 clocks enable during CPU2 Sleep mode + bit_offset: 14 + bit_size: 1 + - name: I2C1SMEN + description: I2C1 clocks enable during CPU2 Sleep mode + bit_offset: 21 + bit_size: 1 + - name: I2C3SMEN + description: I2C3 clocks enable during CPU2 Sleep mode + bit_offset: 23 + bit_size: 1 + - name: CRSMEN + description: CRS clocks enable during CPU2 Sleep mode + bit_offset: 24 + bit_size: 1 + - name: USBSMEN + description: USB FS clocks enable during CPU2 Sleep mode + bit_offset: 26 + bit_size: 1 + - name: LPTIM1SMEN + description: Low power timer 1 clocks enable during CPU2 Sleep mode + bit_offset: 31 + bit_size: 1 fieldset/C2APB1SMENR2: description: CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2 fields: - - name: LPUART1SMEN - description: Low power UART 1 clocks enable during CPU2 Sleep mode - bit_offset: 0 - bit_size: 1 - - name: LPTIM2SMEN - description: Low power timer 2 clocks enable during CPU2 Sleep mode - bit_offset: 5 - bit_size: 1 + - name: LPUART1SMEN + description: Low power UART 1 clocks enable during CPU2 Sleep mode + bit_offset: 0 + bit_size: 1 + - name: LPTIM2SMEN + description: Low power timer 2 clocks enable during CPU2 Sleep mode + bit_offset: 5 + bit_size: 1 fieldset/C2APB2ENR: description: CPU2 APB2ENR fields: - - name: TIM1EN - description: CPU2 TIM1 timer clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: CPU2 SPI1 clock enable - bit_offset: 12 - bit_size: 1 - - name: USART1EN - description: CPU2 USART1clock enable - bit_offset: 14 - bit_size: 1 - - name: TIM16EN - description: CPU2 TIM16 timer clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: CPU2 TIM17 timer clock enable - bit_offset: 18 - bit_size: 1 - - name: SAI1EN - description: CPU2 SAI1 clock enable - bit_offset: 21 - bit_size: 1 + - name: TIM1EN + description: CPU2 TIM1 timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: CPU2 SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: CPU2 USART1clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM16EN + description: CPU2 TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: CPU2 TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: SAI1EN + description: CPU2 SAI1 clock enable + bit_offset: 21 + bit_size: 1 fieldset/C2APB2SMENR: description: CPU2 APB2SMENR fields: - - name: TIM1SMEN - description: TIM1 timer clocks enable during CPU2 Sleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI1SMEN - description: SPI1 clocks enable during CPU2 Sleep mode - bit_offset: 12 - bit_size: 1 - - name: USART1SMEN - description: USART1clocks enable during CPU2 Sleep mode - bit_offset: 14 - bit_size: 1 - - name: TIM16SMEN - description: TIM16 timer clocks enable during CPU2 Sleep mode - bit_offset: 17 - bit_size: 1 - - name: TIM17SMEN - description: TIM17 timer clocks enable during CPU2 Sleep mode - bit_offset: 18 - bit_size: 1 - - name: SAI1SMEN - description: SAI1 clocks enable during CPU2 Sleep mode - bit_offset: 21 - bit_size: 1 + - name: TIM1SMEN + description: TIM1 timer clocks enable during CPU2 Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: SPI1 clocks enable during CPU2 Sleep mode + bit_offset: 12 + bit_size: 1 + - name: USART1SMEN + description: USART1clocks enable during CPU2 Sleep mode + bit_offset: 14 + bit_size: 1 + - name: TIM16SMEN + description: TIM16 timer clocks enable during CPU2 Sleep mode + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: TIM17 timer clocks enable during CPU2 Sleep mode + bit_offset: 18 + bit_size: 1 + - name: SAI1SMEN + description: SAI1 clocks enable during CPU2 Sleep mode + bit_offset: 21 + bit_size: 1 fieldset/C2APB3ENR: description: CPU2 APB3ENR fields: - - name: BLEEN - description: CPU2 BLE interface clock enable - bit_offset: 0 - bit_size: 1 - - name: EN802 - description: CPU2 802.15.4 interface clock enable - bit_offset: 1 - bit_size: 1 + - name: BLEEN + description: CPU2 BLE interface clock enable + bit_offset: 0 + bit_size: 1 + - name: EN802 + description: CPU2 802.15.4 interface clock enable + bit_offset: 1 + bit_size: 1 fieldset/C2APB3SMENR: description: CPU2 APB3SMENR fields: - - name: BLESMEN - description: BLE interface clocks enable during CPU2 Sleep mode - bit_offset: 0 - bit_size: 1 - - name: SMEN802 - description: 802.15.4 interface clocks enable during CPU2 Sleep modes - bit_offset: 1 - bit_size: 1 + - name: BLESMEN + description: BLE interface clocks enable during CPU2 Sleep mode + bit_offset: 0 + bit_size: 1 + - name: SMEN802 + description: 802.15.4 interface clocks enable during CPU2 Sleep modes + bit_offset: 1 + bit_size: 1 fieldset/CCIPR: description: CCIPR fields: - - name: USART1SEL - description: USART1 clock source selection - bit_offset: 0 - bit_size: 2 - - name: LPUART1SEL - description: LPUART1 clock source selection - bit_offset: 10 - bit_size: 2 - - name: I2C1SEL - description: I2C1 clock source selection - bit_offset: 12 - bit_size: 2 - - name: I2C3SEL - description: I2C3 clock source selection - bit_offset: 16 - bit_size: 2 - - name: LPTIM1SEL - description: Low power timer 1 clock source selection - bit_offset: 18 - bit_size: 2 - - name: LPTIM2SEL - description: Low power timer 2 clock source selection - bit_offset: 20 - bit_size: 2 - - name: SAI1SEL - description: SAI1 clock source selection - bit_offset: 22 - bit_size: 2 - - name: CLK48SEL - description: 48 MHz clock source selection - bit_offset: 26 - bit_size: 2 - - name: ADCSEL - description: ADCs clock source selection - bit_offset: 28 - bit_size: 2 - - name: RNGSEL - description: RNG clock source selection - bit_offset: 30 - bit_size: 2 + - name: USART1SEL + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + - name: LPUART1SEL + description: LPUART1 clock source selection + bit_offset: 10 + bit_size: 2 + - name: I2C1SEL + description: I2C1 clock source selection + bit_offset: 12 + bit_size: 2 + - name: I2C3SEL + description: I2C3 clock source selection + bit_offset: 16 + bit_size: 2 + - name: LPTIM1SEL + description: Low power timer 1 clock source selection + bit_offset: 18 + bit_size: 2 + - name: LPTIM2SEL + description: Low power timer 2 clock source selection + bit_offset: 20 + bit_size: 2 + - name: SAI1SEL + description: SAI1 clock source selection + bit_offset: 22 + bit_size: 2 + - name: CLK48SEL + description: 48 MHz clock source selection + bit_offset: 26 + bit_size: 2 + - name: ADCSEL + description: ADCs clock source selection + bit_offset: 28 + bit_size: 2 + - name: RNGSEL + description: RNG clock source selection + bit_offset: 30 + bit_size: 2 fieldset/CFGR: description: Clock configuration register fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 2 - - name: SWS - description: System clock switch status - bit_offset: 2 - bit_size: 2 - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - - name: PPRE1 - description: PB low-speed prescaler (APB1) - bit_offset: 8 - bit_size: 3 - - name: PPRE2 - description: APB high-speed prescaler (APB2) - bit_offset: 11 - bit_size: 3 - - name: STOPWUCK - description: Wakeup from Stop and CSS backup clock selection - bit_offset: 15 - bit_size: 1 - - name: HPREF - description: AHB prescaler flag - bit_offset: 16 - bit_size: 1 - - name: PPRE1F - description: APB1 prescaler flag - bit_offset: 17 - bit_size: 1 - - name: PPRE2F - description: APB2 prescaler flag - bit_offset: 18 - bit_size: 1 - - name: MCOSEL - description: Microcontroller clock output - bit_offset: 24 - bit_size: 4 - - name: MCOPRE - description: Microcontroller clock output prescaler - bit_offset: 28 - bit_size: 3 + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: PB low-speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high-speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: STOPWUCK + description: Wakeup from Stop and CSS backup clock selection + bit_offset: 15 + bit_size: 1 + - name: HPREF + description: AHB prescaler flag + bit_offset: 16 + bit_size: 1 + - name: PPRE1F + description: APB1 prescaler flag + bit_offset: 17 + bit_size: 1 + - name: PPRE2F + description: APB2 prescaler flag + bit_offset: 18 + bit_size: 1 + - name: MCOSEL + description: Microcontroller clock output + bit_offset: 24 + bit_size: 4 + - name: MCOPRE + description: Microcontroller clock output prescaler + bit_offset: 28 + bit_size: 3 fieldset/CICR: description: Clock interrupt clear register fields: - - name: LSI1RDYC - description: LSI1 ready interrupt clear - bit_offset: 0 - bit_size: 1 - - name: LSERDYC - description: LSE ready interrupt clear - bit_offset: 1 - bit_size: 1 - - name: MSIRDYC - description: MSI ready interrupt clear - bit_offset: 2 - bit_size: 1 - - name: HSIRDYC - description: HSI ready interrupt clear - bit_offset: 3 - bit_size: 1 - - name: HSERDYC - description: HSE ready interrupt clear - bit_offset: 4 - bit_size: 1 - - name: PLLRDYC - description: PLL ready interrupt clear - bit_offset: 5 - bit_size: 1 - - name: PLLSAI1RDYC - description: PLLSAI1 ready interrupt clear - bit_offset: 6 - bit_size: 1 - - name: HSECSSC - description: HSE Clock security system interrupt clear - bit_offset: 8 - bit_size: 1 - - name: LSECSSC - description: LSE Clock security system interrupt clear - bit_offset: 9 - bit_size: 1 - - name: HSI48RDYC - description: HSI48 ready interrupt clear - bit_offset: 10 - bit_size: 1 - - name: LSI2RDYC - description: LSI2 ready interrupt clear - bit_offset: 11 - bit_size: 1 + - name: LSI1RDYC + description: LSI1 ready interrupt clear + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 1 + bit_size: 1 + - name: MSIRDYC + description: MSI ready interrupt clear + bit_offset: 2 + bit_size: 1 + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 4 + bit_size: 1 + - name: PLLRDYC + description: PLL ready interrupt clear + bit_offset: 5 + bit_size: 1 + - name: PLLSAI1RDYC + description: PLLSAI1 ready interrupt clear + bit_offset: 6 + bit_size: 1 + - name: HSECSSC + description: HSE Clock security system interrupt clear + bit_offset: 8 + bit_size: 1 + - name: LSECSSC + description: LSE Clock security system interrupt clear + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYC + description: HSI48 ready interrupt clear + bit_offset: 10 + bit_size: 1 + - name: LSI2RDYC + description: LSI2 ready interrupt clear + bit_offset: 11 + bit_size: 1 fieldset/CIER: description: Clock interrupt enable register fields: - - name: LSI1RDYIE - description: LSI1 ready interrupt enable - bit_offset: 0 - bit_size: 1 - - name: LSERDYIE - description: LSE ready interrupt enable - bit_offset: 1 - bit_size: 1 - - name: MSIRDYIE - description: MSI ready interrupt enable - bit_offset: 2 - bit_size: 1 - - name: HSIRDYIE - description: HSI ready interrupt enable - bit_offset: 3 - bit_size: 1 - - name: HSERDYIE - description: HSE ready interrupt enable - bit_offset: 4 - bit_size: 1 - - name: PLLRDYIE - description: PLLSYS ready interrupt enable - bit_offset: 5 - bit_size: 1 - - name: PLLSAI1RDYIE - description: PLLSAI1 ready interrupt enable - bit_offset: 6 - bit_size: 1 - - name: LSECSSIE - description: LSE clock security system interrupt enable - bit_offset: 9 - bit_size: 1 - - name: HSI48RDYIE - description: HSI48 ready interrupt enable - bit_offset: 10 - bit_size: 1 - - name: LSI2RDYIE - description: LSI2 ready interrupt enable - bit_offset: 11 - bit_size: 1 + - name: LSI1RDYIE + description: LSI1 ready interrupt enable + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 1 + bit_size: 1 + - name: MSIRDYIE + description: MSI ready interrupt enable + bit_offset: 2 + bit_size: 1 + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 4 + bit_size: 1 + - name: PLLRDYIE + description: PLLSYS ready interrupt enable + bit_offset: 5 + bit_size: 1 + - name: PLLSAI1RDYIE + description: PLLSAI1 ready interrupt enable + bit_offset: 6 + bit_size: 1 + - name: LSECSSIE + description: LSE clock security system interrupt enable + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYIE + description: HSI48 ready interrupt enable + bit_offset: 10 + bit_size: 1 + - name: LSI2RDYIE + description: LSI2 ready interrupt enable + bit_offset: 11 + bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register fields: - - name: LSI1RDYF - description: LSI1 ready interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - - name: MSIRDYF - description: MSI ready interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSIRDYF - description: HSI ready interrupt flag - bit_offset: 3 - bit_size: 1 - - name: HSERDYF - description: HSE ready interrupt flag - bit_offset: 4 - bit_size: 1 - - name: PLLRDYF - description: PLL ready interrupt flag - bit_offset: 5 - bit_size: 1 - - name: PLLSAI1RDYF - description: PLLSAI1 ready interrupt flag - bit_offset: 6 - bit_size: 1 - - name: HSECSSF - description: HSE Clock security system interrupt flag - bit_offset: 8 - bit_size: 1 - - name: LSECSSF - description: LSE Clock security system interrupt flag - bit_offset: 9 - bit_size: 1 - - name: HSI48RDYF - description: HSI48 ready interrupt flag - bit_offset: 10 - bit_size: 1 - - name: LSI2RDYF - description: LSI2 ready interrupt flag - bit_offset: 11 - bit_size: 1 + - name: LSI1RDYF + description: LSI1 ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: MSIRDYF + description: MSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLLRDYF + description: PLL ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: PLLSAI1RDYF + description: PLLSAI1 ready interrupt flag + bit_offset: 6 + bit_size: 1 + - name: HSECSSF + description: HSE Clock security system interrupt flag + bit_offset: 8 + bit_size: 1 + - name: LSECSSF + description: LSE Clock security system interrupt flag + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYF + description: HSI48 ready interrupt flag + bit_offset: 10 + bit_size: 1 + - name: LSI2RDYF + description: LSI2 ready interrupt flag + bit_offset: 11 + bit_size: 1 fieldset/CR: description: Clock control register fields: - - name: MSION - description: MSI clock enable - bit_offset: 0 - bit_size: 1 - - name: MSIRDY - description: MSI clock ready flag - bit_offset: 1 - bit_size: 1 - - name: MSIPLLEN - description: MSI clock PLL enable - bit_offset: 2 - bit_size: 1 - - name: MSIRANGE - description: MSI clock ranges - bit_offset: 4 - bit_size: 4 - - name: HSION - description: HSI clock enabled - bit_offset: 8 - bit_size: 1 - - name: HSIKERON - description: HSI always enable for peripheral kernels - bit_offset: 9 - bit_size: 1 - - name: HSIRDY - description: HSI clock ready flag - bit_offset: 10 - bit_size: 1 - - name: HSIASFS - description: HSI automatic start from Stop - bit_offset: 11 - bit_size: 1 - - name: HSIKERDY - description: HSI kernel clock ready flag for peripherals requests - bit_offset: 12 - bit_size: 1 - - name: HSEON - description: HSE clock enabled - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: HSE crystal oscillator bypass - bit_offset: 18 - bit_size: 1 - - name: CSSON - description: HSE Clock security system enable - bit_offset: 19 - bit_size: 1 - - name: HSEPRE - description: HSE sysclk and PLL M divider prescaler - bit_offset: 20 - bit_size: 1 - - name: PLLON - description: Main PLL enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: Main PLL clock ready flag - bit_offset: 25 - bit_size: 1 - - name: PLLSAI1ON - description: SAI1 PLL enable - bit_offset: 26 - bit_size: 1 - - name: PLLSAI1RDY - description: SAI1 PLL clock ready flag - bit_offset: 27 - bit_size: 1 + - name: MSION + description: MSI clock enable + bit_offset: 0 + bit_size: 1 + - name: MSIRDY + description: MSI clock ready flag + bit_offset: 1 + bit_size: 1 + - name: MSIPLLEN + description: MSI clock PLL enable + bit_offset: 2 + bit_size: 1 + - name: MSIRANGE + description: MSI clock ranges + bit_offset: 4 + bit_size: 4 + - name: HSION + description: HSI clock enabled + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: HSI always enable for peripheral kernels + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: HSI clock ready flag + bit_offset: 10 + bit_size: 1 + - name: HSIASFS + description: HSI automatic start from Stop + bit_offset: 11 + bit_size: 1 + - name: HSIKERDY + description: HSI kernel clock ready flag for peripherals requests + bit_offset: 12 + bit_size: 1 + - name: HSEON + description: HSE clock enabled + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: HSE crystal oscillator bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: HSE Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: HSEPRE + description: HSE sysclk and PLL M divider prescaler + bit_offset: 20 + bit_size: 1 + - name: PLLON + description: Main PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL clock ready flag + bit_offset: 25 + bit_size: 1 + - name: PLLSAI1ON + description: SAI1 PLL enable + bit_offset: 26 + bit_size: 1 + - name: PLLSAI1RDY + description: SAI1 PLL clock ready flag + bit_offset: 27 + bit_size: 1 fieldset/CRRCR: description: Clock recovery RC register fields: - - name: HSI48ON - description: HSI48 oscillator enabled - bit_offset: 0 - bit_size: 1 - - name: HSI48RDY - description: HSI48 clock ready - bit_offset: 1 - bit_size: 1 - - name: HSI48CAL - description: HSI48 clock calibration - bit_offset: 7 - bit_size: 9 + - name: HSI48ON + description: HSI48 oscillator enabled + bit_offset: 0 + bit_size: 1 + - name: HSI48RDY + description: HSI48 clock ready + bit_offset: 1 + bit_size: 1 + - name: HSI48CAL + description: HSI48 clock calibration + bit_offset: 7 + bit_size: 9 fieldset/CSR: description: CSR fields: - - name: LSI1ON - description: LSI1 oscillator enabled - bit_offset: 0 - bit_size: 1 - - name: LSI1RDY - description: LSI1 oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSI2ON - description: LSI2 oscillator enabled - bit_offset: 2 - bit_size: 1 - - name: LSI2RDY - description: LSI2 oscillator ready - bit_offset: 3 - bit_size: 1 - - name: LSI2TRIMEN - description: LSI2 oscillator trimming enable - bit_offset: 4 - bit_size: 1 - - name: LSI2TRIMOK - description: LSI2 oscillator trim OK - bit_offset: 5 - bit_size: 1 - - name: LSI2BW - description: LSI2 oscillator bias configuration - bit_offset: 8 - bit_size: 4 - - name: RFWKPSEL - description: RF system wakeup clock source selection - bit_offset: 14 - bit_size: 2 - - name: RFRSTS - description: Radio system BLE and 802.15.4 reset status - bit_offset: 16 - bit_size: 1 - - name: RMVF - description: Remove reset flag - bit_offset: 23 - bit_size: 1 - - name: OBLRSTF - description: Option byte loader reset flag - bit_offset: 25 - bit_size: 1 - - name: PINRSTF - description: Pin reset flag - bit_offset: 26 - bit_size: 1 - - name: BORRSTF - description: BOR flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: Independent window watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSI1ON + description: LSI1 oscillator enabled + bit_offset: 0 + bit_size: 1 + - name: LSI1RDY + description: LSI1 oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSI2ON + description: LSI2 oscillator enabled + bit_offset: 2 + bit_size: 1 + - name: LSI2RDY + description: LSI2 oscillator ready + bit_offset: 3 + bit_size: 1 + - name: LSI2TRIMEN + description: LSI2 oscillator trimming enable + bit_offset: 4 + bit_size: 1 + - name: LSI2TRIMOK + description: LSI2 oscillator trim OK + bit_offset: 5 + bit_size: 1 + - name: LSI2BW + description: LSI2 oscillator bias configuration + bit_offset: 8 + bit_size: 4 + - name: RFWKPSEL + description: RF system wakeup clock source selection + bit_offset: 14 + bit_size: 2 + - name: RFRSTS + description: Radio system BLE and 802.15.4 reset status + bit_offset: 16 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 23 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: Pin reset flag + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: BOR flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent window watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 fieldset/EXTCFGR: description: Extended clock recovery register fields: - - name: SHDHPRE - description: Shared AHB prescaler - bit_offset: 0 - bit_size: 4 - - name: C2HPRE - description: CPU2 AHB prescaler - bit_offset: 4 - bit_size: 4 - - name: SHDHPREF - description: Shared AHB prescaler flag - bit_offset: 16 - bit_size: 1 - - name: C2HPREF - description: CPU2 AHB prescaler flag - bit_offset: 17 - bit_size: 1 - - name: RFCSS - description: RF clock source selected - bit_offset: 20 - bit_size: 1 + - name: SHDHPRE + description: Shared AHB prescaler + bit_offset: 0 + bit_size: 4 + - name: C2HPRE + description: CPU2 AHB prescaler + bit_offset: 4 + bit_size: 4 + - name: SHDHPREF + description: Shared AHB prescaler flag + bit_offset: 16 + bit_size: 1 + - name: C2HPREF + description: CPU2 AHB prescaler flag + bit_offset: 17 + bit_size: 1 + - name: RFCSS + description: RF clock source selected + bit_offset: 20 + bit_size: 1 fieldset/HSECR: description: Clock HSE register fields: - - name: UNLOCKED - description: Register lock system - bit_offset: 0 - bit_size: 1 - - name: HSES - description: HSE Sense amplifier threshold - bit_offset: 3 - bit_size: 1 - - name: HSEGMC - description: HSE current control - bit_offset: 4 - bit_size: 3 - - name: HSETUNE - description: HSE capacitor tuning - bit_offset: 8 - bit_size: 6 + - name: UNLOCKED + description: Register lock system + bit_offset: 0 + bit_size: 1 + - name: HSES + description: HSE Sense amplifier threshold + bit_offset: 3 + bit_size: 1 + - name: HSEGMC + description: HSE current control + bit_offset: 4 + bit_size: 3 + - name: HSETUNE + description: HSE capacitor tuning + bit_offset: 8 + bit_size: 6 fieldset/ICSCR: description: Internal clock sources calibration register fields: - - name: MSICAL - description: MSI clock calibration - bit_offset: 0 - bit_size: 8 - - name: MSITRIM - description: MSI clock trimming - bit_offset: 8 - bit_size: 8 - - name: HSICAL - description: HSI clock calibration - bit_offset: 16 - bit_size: 8 - - name: HSITRIM - description: HSI clock trimming - bit_offset: 24 - bit_size: 7 + - name: MSICAL + description: MSI clock calibration + bit_offset: 0 + bit_size: 8 + - name: MSITRIM + description: MSI clock trimming + bit_offset: 8 + bit_size: 8 + - name: HSICAL + description: HSI clock calibration + bit_offset: 16 + bit_size: 8 + - name: HSITRIM + description: HSI clock trimming + bit_offset: 24 + bit_size: 7 fieldset/PLLCFGR: description: PLLSYS configuration register fields: - - name: PLLSRC - description: "Main PLL, PLLSAI1 and PLLSAI2 entry clock source" - bit_offset: 0 - bit_size: 2 - - name: PLLM - description: Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock - bit_offset: 4 - bit_size: 3 - - name: PLLN - description: Main PLLSYS multiplication factor N - bit_offset: 8 - bit_size: 7 - - name: PLLPEN - description: Main PLLSYSP output enable - bit_offset: 16 - bit_size: 1 - - name: PLLP - description: Main PLL division factor P for PPLSYSSAICLK - bit_offset: 17 - bit_size: 5 - - name: PLLQEN - description: Main PLLSYSQ output enable - bit_offset: 24 - bit_size: 1 - - name: PLLQ - description: Main PLLSYS division factor Q for PLLSYSUSBCLK - bit_offset: 25 - bit_size: 3 - - name: PLLREN - description: Main PLLSYSR PLLCLK output enable - bit_offset: 28 - bit_size: 1 - - name: PLLR - description: Main PLLSYS division factor R for SYSCLK (system clock) - bit_offset: 29 - bit_size: 3 + - name: PLLSRC + description: Main PLL, PLLSAI1 and PLLSAI2 entry clock source + bit_offset: 0 + bit_size: 2 + - name: PLLM + description: Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock + bit_offset: 4 + bit_size: 3 + - name: PLLN + description: Main PLLSYS multiplication factor N + bit_offset: 8 + bit_size: 7 + - name: PLLPEN + description: Main PLLSYSP output enable + bit_offset: 16 + bit_size: 1 + - name: PLLP + description: Main PLL division factor P for PPLSYSSAICLK + bit_offset: 17 + bit_size: 5 + - name: PLLQEN + description: Main PLLSYSQ output enable + bit_offset: 24 + bit_size: 1 + - name: PLLQ + description: Main PLLSYS division factor Q for PLLSYSUSBCLK + bit_offset: 25 + bit_size: 3 + - name: PLLREN + description: Main PLLSYSR PLLCLK output enable + bit_offset: 28 + bit_size: 1 + - name: PLLR + description: Main PLLSYS division factor R for SYSCLK (system clock) + bit_offset: 29 + bit_size: 3 fieldset/PLLSAI1CFGR: description: PLLSAI1 configuration register fields: - - name: PLLN - description: SAIPLL multiplication factor for VCO - bit_offset: 8 - bit_size: 7 - - name: PLLPEN - description: SAIPLL PLLSAI1CLK output enable - bit_offset: 16 - bit_size: 1 - - name: PLLP - description: SAI1PLL division factor P for PLLSAICLK (SAI1clock) - bit_offset: 17 - bit_size: 5 - - name: PLLQEN - description: SAIPLL PLLSAIUSBCLK output enable - bit_offset: 24 - bit_size: 1 - - name: PLLQ - description: SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock) - bit_offset: 25 - bit_size: 3 - - name: PLLREN - description: PLLSAI PLLADC1CLK output enable - bit_offset: 28 - bit_size: 1 - - name: PLLR - description: PLLSAI division factor R for PLLADC1CLK (ADC clock) - bit_offset: 29 - bit_size: 3 + - name: PLLN + description: SAIPLL multiplication factor for VCO + bit_offset: 8 + bit_size: 7 + - name: PLLPEN + description: SAIPLL PLLSAI1CLK output enable + bit_offset: 16 + bit_size: 1 + - name: PLLP + description: SAI1PLL division factor P for PLLSAICLK (SAI1clock) + bit_offset: 17 + bit_size: 5 + - name: PLLQEN + description: SAIPLL PLLSAIUSBCLK output enable + bit_offset: 24 + bit_size: 1 + - name: PLLQ + description: SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock) + bit_offset: 25 + bit_size: 3 + - name: PLLREN + description: PLLSAI PLLADC1CLK output enable + bit_offset: 28 + bit_size: 1 + - name: PLLR + description: PLLSAI division factor R for PLLADC1CLK (ADC clock) + bit_offset: 29 + bit_size: 3 fieldset/SMPSCR: description: Step Down converter control register fields: - - name: SMPSSEL - description: Step Down converter clock selection - bit_offset: 0 - bit_size: 2 - - name: SMPSDIV - description: Step Down converter clock prescaler - bit_offset: 4 - bit_size: 2 - - name: SMPSSWS - description: Step Down converter clock switch status - bit_offset: 8 - bit_size: 2 + - name: SMPSSEL + description: Step Down converter clock selection + bit_offset: 0 + bit_size: 2 + - name: SMPSDIV + description: Step Down converter clock prescaler + bit_offset: 4 + bit_size: 2 + - name: SMPSSWS + description: Step Down converter clock switch status + bit_offset: 8 + bit_size: 2 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: DCLK not divided + value: 0 + - name: Div3 + description: hclk = SYSCLK divided by 3 + value: 1 + - name: Div5 + description: hclk = SYSCLK divided by 5 + value: 2 + - name: Div6 + description: hclk = SYSCLK divided by 6 + value: 5 + - name: Div10 + description: hclk = SYSCLK divided by 8 + value: 6 + - name: Div32 + description: hclk = SYSCLK divided by 32 + value: 7 + - name: Div2 + description: hclk = SYSCLK divided by 2 + value: 8 + - name: Div4 + description: hclk = SYSCLK divided by 4 + value: 9 + - name: Div8 + description: hclk = SYSCLK divided by 8 + value: 10 + - name: Div16 + description: hclk = SYSCLK divided by 16 + value: 11 + - name: Div64 + description: hclk = SYSCLK divided by 64 + value: 12 + - name: Div128 + description: hclk = SYSCLK divided by 128 + value: 13 + - name: Div256 + description: hclk = SYSCLK divided by 256 + value: 14 + - name: Div512 + description: hclk = SYSCLK divided by 256 + value: 15 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock selected + value: 0 + - name: LSE + description: LSE oscillator clock selected + value: 1 + - name: LSI + description: LSI oscillator clock selected + value: 2 + - name: HSE + description: HSE oscillator clock divided by 32 selected + value: 3 diff --git a/data/registers/rcc_wba.yaml b/data/registers/rcc_wba.yaml new file mode 100644 index 0000000..6748bfd --- /dev/null +++ b/data/registers/rcc_wba.yaml @@ -0,0 +1,1572 @@ +block/RCC: + description: Reset and clock control + items: + - name: CR + description: RCC clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR3 + description: RCC internal clock sources calibration register 3 + byte_offset: 16 + fieldset: ICSCR3 + - name: CFGR1 + description: RCC clock configuration register 1 + byte_offset: 28 + fieldset: CFGR1 + - name: CFGR2 + description: RCC clock configuration register 2 + byte_offset: 32 + fieldset: CFGR2 + - name: CFGR3 + description: RCC clock configuration register 3 + byte_offset: 36 + fieldset: CFGR3 + - name: PLL1CFGR + description: RCC PLL1 configuration register + byte_offset: 40 + fieldset: PLL1CFGR + - name: PLL1DIVR + description: RCC PLL1 dividers register + byte_offset: 52 + fieldset: PLL1DIVR + - name: PLL1FRACR + description: RCC PLL1 fractional divider register + byte_offset: 56 + fieldset: PLL1FRACR + - name: CIER + description: RCC clock interrupt enable register + byte_offset: 80 + fieldset: CIER + - name: CIFR + description: RCC clock interrupt flag register + byte_offset: 84 + fieldset: CIFR + - name: CICR + description: RCC clock interrupt clear register + byte_offset: 88 + fieldset: CICR + - name: AHB1RSTR + description: RCC AHB1 peripheral reset register + byte_offset: 96 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: RCC AHB2 peripheral reset register + byte_offset: 100 + fieldset: AHB2RSTR + - name: AHB4RSTR + description: RCC AHB4 peripheral reset register + byte_offset: 108 + fieldset: AHB4RSTR + - name: AHB5RSTR + description: RCC AHB5 peripheral reset register + byte_offset: 112 + fieldset: AHB5RSTR + - name: APB1RSTR1 + description: RCC APB1 peripheral reset register 1 + byte_offset: 116 + fieldset: APB1RSTR1 + - name: APB1RSTR2 + description: RCC APB1 peripheral reset register 2 + byte_offset: 120 + fieldset: APB1RSTR2 + - name: APB2RSTR + description: RCC APB2 peripheral reset register + byte_offset: 124 + fieldset: APB2RSTR + - name: APB7RSTR + description: RCC APB7 peripheral reset register + byte_offset: 128 + fieldset: APB7RSTR + - name: AHB1ENR + description: RCC AHB1 peripheral clock enable register + byte_offset: 136 + fieldset: AHB1ENR + - name: AHB2ENR + description: RCC AHB2 peripheral clock enable register + byte_offset: 140 + fieldset: AHB2ENR + - name: AHB4ENR + description: RCC AHB4 peripheral clock enable register + byte_offset: 148 + fieldset: AHB4ENR + - name: AHB5ENR + description: RCC AHB5 peripheral clock enable register + byte_offset: 152 + fieldset: AHB5ENR + - name: APB1ENR1 + description: RCC APB1 peripheral clock enable register 1 + byte_offset: 156 + fieldset: APB1ENR1 + - name: APB1ENR2 + description: RCC APB1 peripheral clock enable register 2 + byte_offset: 160 + fieldset: APB1ENR2 + - name: APB2ENR + description: RCC APB2 peripheral clock enable register + byte_offset: 164 + fieldset: APB2ENR + - name: APB7ENR + description: RCC APB7 peripheral clock enable register + byte_offset: 168 + fieldset: APB7ENR + - name: AHB1SMENR + description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 176 + fieldset: AHB1SMENR + - name: AHB2SMENR + description: RCC AHB2 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 180 + fieldset: AHB2SMENR + - name: AHB4SMENR + description: RCC AHB4 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 188 + fieldset: AHB4SMENR + - name: AHB5SMENR + description: RCC AHB5 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 192 + fieldset: AHB5SMENR + - name: APB1SMENR1 + description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1" + byte_offset: 196 + fieldset: APB1SMENR1 + - name: APB1SMENR2 + description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes \tregister 2" + byte_offset: 200 + fieldset: APB1SMENR2 + - name: APB2SMENR + description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 204 + fieldset: APB2SMENR + - name: APB7SMENR + description: RCC APB7 peripheral clock enable in Sleep and Stop modes register + byte_offset: 208 + fieldset: APB7SMENR + - name: CCIPR1 + description: RCC peripherals independent clock configuration register 1 + byte_offset: 224 + fieldset: CCIPR1 + - name: CCIPR2 + description: RCC peripherals independent clock configuration register 2 + byte_offset: 228 + fieldset: CCIPR2 + - name: CCIPR3 + description: RCC peripherals independent clock configuration register 3 + byte_offset: 232 + fieldset: CCIPR3 + - name: BDCR + description: RCC backup domain control register + byte_offset: 240 + fieldset: BDCR + - name: CSR + description: RCC control/status register + byte_offset: 244 + fieldset: CSR + - name: SECCFGR + description: RCC secure configuration register + byte_offset: 272 + fieldset: SECCFGR + - name: PRIVCFGR + description: RCC privilege configuration register + byte_offset: 276 + fieldset: PRIVCFGR + - name: CFGR4 + description: RCC clock configuration register 2 + byte_offset: 512 + fieldset: CFGR4 + - name: RADIOENR + description: RCC RADIO peripheral clock enable register + byte_offset: 520 + fieldset: RADIOENR + - name: ECSCR1 + description: RCC external clock sources calibration register 1 + byte_offset: 528 + fieldset: ECSCR1 +fieldset/AHB1ENR: + description: RCC AHB1 peripheral clock enable register + fields: + - name: GPDMA1EN + description: "GPDMA1 bus clock enable\r Set and cleared by software.\r Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: FLASHEN + description: "FLASH bus clock enable\r Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode.\r Can only be accessed secured when the Flash security state is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: "CRC bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 12 + bit_size: 1 + - name: TSCEN + description: "Touch sensing controller bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 16 + bit_size: 1 + - name: RAMCFGEN + description: "RAMCFG bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RAMCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: GTZC1EN + description: "GTZC1 bus clock enable \r Set and reset by software.\r Can only be accessed secure when device is secure (TZEN = 1). When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 24 + bit_size: 1 + - name: SRAM1EN + description: "SRAM1 bus clock enable \r Set and reset by software.\r Access can be secured by GTZC_MPCBB1 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 31 + bit_size: 1 +fieldset/AHB1RSTR: + description: RCC AHB1 peripheral reset register + fields: + - name: GPDMA1RST + description: "GPDMA1 reset\r Set and cleared by software.\r Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: CRCRST + description: "CRC reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 12 + bit_size: 1 + - name: TSCRST + description: "TSC reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 16 + bit_size: 1 +fieldset/AHB1SMENR: + description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register + fields: + - name: GPDMA1SMEN + description: "GPDMA1 bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 0 + bit_size: 1 + - name: FLASHSMEN + description: "FLASH bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Can only be accessed secured when the Flash security state is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 8 + bit_size: 1 + - name: CRCSMEN + description: "CRC bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 12 + bit_size: 1 + - name: TSCSMEN + description: "TSC bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.." + bit_offset: 16 + bit_size: 1 + - name: RAMCFGSMEN + description: "RAMCFG bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RAMCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: GTZC1SMEN + description: "GTZC1 bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Can only be accessed secure when one device is secure (TZEN = 1). When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 24 + bit_size: 1 + - name: ICACHESMEN + description: "ICACHE bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC ICACHE_REGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.." + bit_offset: 29 + bit_size: 1 + - name: SRAM1SMEN + description: "SRAM1 bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_MPCBB1 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 31 + bit_size: 1 +fieldset/AHB2ENR: + description: RCC AHB2 peripheral clock enable register + fields: + - name: GPIOAEN + description: "IO port A bus clock enable\r Set and cleared by software.\r Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: "IO port B bus clock enable\r Set and cleared by software.\r Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: "IO port C bus clock enable\r Set and cleared by software.\r Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 2 + bit_size: 1 + - name: GPIOHEN + description: "IO port H bus clock enable\r Set and cleared by software.\r Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 7 + bit_size: 1 + - name: AESEN + description: "AES bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 16 + bit_size: 1 + - name: HASHEN + description: "HASH bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: "RNG bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 18 + bit_size: 1 + - name: SAESEN + description: "SAES bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 19 + bit_size: 1 + - name: HSEMEN + description: "HSEM bus clock enable\r Set and cleared by software.\r Can only be accessed secure when one or more features in the HSEM is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 20 + bit_size: 1 + - name: PKAEN + description: "PKA bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 21 + bit_size: 1 + - name: SRAM2EN + description: "SRAM2 bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_MPCBB2 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 30 + bit_size: 1 +fieldset/AHB2RSTR: + description: RCC AHB2 peripheral reset register + fields: + - name: GPIOARST + description: "IO port A reset\r Set and cleared by software.\r Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: "IO port B reset\r Set and cleared by software.\r Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: "IO port C reset\r Set and cleared by software.\r Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 2 + bit_size: 1 + - name: GPIOHRST + description: "IO port H reset\r Set and cleared by software.\r Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 7 + bit_size: 1 + - name: AESRST + description: "AES hardware accelerator reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 16 + bit_size: 1 + - name: HASHRST + description: "Hash reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: RNGRST + description: "Random number generator reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 18 + bit_size: 1 + - name: SAESRST + description: "SAES hardware accelerator reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 19 + bit_size: 1 + - name: HSEMRST + description: "HSEM hardware accelerator reset\r Set and cleared by software.\r Can only be accessed secure when one or more features in the HSEM is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 20 + bit_size: 1 + - name: PKARST + description: "PKA reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 21 + bit_size: 1 +fieldset/AHB2SMENR: + description: RCC AHB2 peripheral clocks enable in Sleep and Stop modes register + fields: + - name: GPIOASMEN + description: "IO port A bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: "IO port B bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: "IO port C bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 2 + bit_size: 1 + - name: GPIOHSMEN + description: "IO port H bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 7 + bit_size: 1 + - name: AESSMEN + description: "AES bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 16 + bit_size: 1 + - name: HASHSMEN + description: "HASH bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: RNGSMEN + description: "Random number generator (RNG) bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 18 + bit_size: 1 + - name: SAESSMEN + description: "SAES accelerator bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 19 + bit_size: 1 + - name: PKASMEN + description: "PKA bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 21 + bit_size: 1 + - name: SRAM2SMEN + description: "SRAM2 bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_MPCBB2 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 30 + bit_size: 1 +fieldset/AHB4ENR: + description: RCC AHB4 peripheral clock enable register + fields: + - name: PWREN + description: "PWR bus clock enable\r Set and cleared by software.\r Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 2 + bit_size: 1 + - name: ADC4EN + description: "ADC4 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 5 + bit_size: 1 +fieldset/AHB4RSTR: + description: RCC AHB4 peripheral reset register + fields: + - name: ADC4RST + description: "ADC4 reset\r Set and cleared by software.\r Access can be secred by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 5 + bit_size: 1 +fieldset/AHB4SMENR: + description: RCC AHB4 peripheral clocks enable in Sleep and Stop modes register + fields: + - name: PWRSMEN + description: "PWR bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 2 + bit_size: 1 + - name: ADC4SMEN + description: "ADC4 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 5 + bit_size: 1 +fieldset/AHB5ENR: + description: RCC AHB5 peripheral clock enable register + fields: + - name: RADIOEN + description: "2.4 GHz RADIO bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Before accessing the 2.4 GHz RADIO sleep timers registers the RADIOCLKRDY bit must be checked.\r Note: When RADIOSMEN and STRADIOCLKON are both cleared, RADIOCLKRDY bit must be re-checked when exiting low-power modes (Sleep and Stop)." + bit_offset: 0 + bit_size: 1 +fieldset/AHB5RSTR: + description: RCC AHB5 peripheral reset register + fields: + - name: RADIORST + description: "2.4 GHz RADIO reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 +fieldset/AHB5SMENR: + description: RCC AHB5 peripheral clocks enable in Sleep and Stop modes register + fields: + - name: RADIOSMEN + description: "2.4 GHz RADIO bus clock enable during Sleep and Stop modes when the 2.4 GHz RADIO is active.\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 +fieldset/APB1ENR1: + description: RCC APB1 peripheral clock enable register 1 + fields: + - name: TIM2EN + description: "TIM2 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: "TIM3 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: WWDGEN + description: "WWDG bus clock enable\r Set by software to enable the window watchdog bus clock. Reset by hardware system reset.\r This bit can also be set by hardware if the WWDG_SW option bit is reset.\r Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 11 + bit_size: 1 + - name: USART2EN + description: "USART2 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC USART2SEC When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.." + bit_offset: 17 + bit_size: 1 + - name: I2C1EN + description: "I2C1 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 21 + bit_size: 1 +fieldset/APB1ENR2: + description: RCC APB1 peripheral clock enable register 2 + fields: + - name: LPTIM2EN + description: "LPTIM2 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 5 + bit_size: 1 +fieldset/APB1RSTR1: + description: RCC APB1 peripheral reset register 1 + fields: + - name: TIM2RST + description: "TIM2 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: "TIM3 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: USART2RST + description: "USART2 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC UART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: I2C1RST + description: "I2C1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 21 + bit_size: 1 +fieldset/APB1RSTR2: + description: RCC APB1 peripheral reset register 2 + fields: + - name: LPTIM2RST + description: "LPTIM2 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 5 + bit_size: 1 +fieldset/APB1SMENR1: + description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1" + fields: + - name: TIM2SMEN + description: "TIM2 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: TIM3SMEN + description: "TIM3 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: WWDGSMEN + description: "Window watchdog bus clock enable during Sleep and Stop modes\r Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated.\r Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 11 + bit_size: 1 + - name: USART2SMEN + description: "USART2 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 17 + bit_size: 1 + - name: I2C1SMEN + description: "I2C1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 21 + bit_size: 1 +fieldset/APB1SMENR2: + description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes \tregister 2" + fields: + - name: LPTIM2SMEN + description: "LPTIM2 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 5 + bit_size: 1 +fieldset/APB2ENR: + description: RCC APB2 peripheral clock enable register + fields: + - name: TIM1EN + description: "TIM1 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: "SPI1 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: "USART1bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 14 + bit_size: 1 + - name: TIM16EN + description: "TIM16 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: "TIM17 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 18 + bit_size: 1 +fieldset/APB2RSTR: + description: RCC APB2 peripheral reset register + fields: + - name: TIM1RST + description: "TIM1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: "SPI1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: "USART1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 14 + bit_size: 1 + - name: TIM16RST + description: "TIM16 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: "TIM17 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 18 + bit_size: 1 +fieldset/APB2SMENR: + description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register + fields: + - name: TIM1SMEN + description: "TIM1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: "SPI1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 12 + bit_size: 1 + - name: USART1SMEN + description: "USART1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 14 + bit_size: 1 + - name: TIM16SMEN + description: "TIM16 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: "TIM17 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 18 + bit_size: 1 +fieldset/APB7ENR: + description: RCC APB7 peripheral clock enable register + fields: + - name: SYSCFGEN + description: "SYSCFG bus clock enable\r Set and cleared by software.\r Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: SPI3EN + description: "SPI3 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 5 + bit_size: 1 + - name: LPUART1EN + description: "LPUART1 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 6 + bit_size: 1 + - name: I2C3EN + description: "I2C3 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 7 + bit_size: 1 + - name: LPTIM1EN + description: "LPTIM1 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 11 + bit_size: 1 + - name: RTCAPBEN + description: "RTC and TAMP bus clock enable\r Set and cleared by software.\r Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 21 + bit_size: 1 +fieldset/APB7RSTR: + description: RCC APB7 peripheral reset register + fields: + - name: SYSCFGRST + description: "SYSCFG reset\r Set and cleared by software.\r Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: SPI3RST + description: "SPI3 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 5 + bit_size: 1 + - name: LPUART1RST + description: "LPUART1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 6 + bit_size: 1 + - name: I2C3RST + description: "I2C3 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 7 + bit_size: 1 + - name: LPTIM1RST + description: "LPTIM1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 11 + bit_size: 1 +fieldset/APB7SMENR: + description: RCC APB7 peripheral clock enable in Sleep and Stop modes register + fields: + - name: SYSCFGSMEN + description: "SYSCFG bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: SPI3SMEN + description: "SPI3 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 5 + bit_size: 1 + - name: LPUART1SMEN + description: "LPUART1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 6 + bit_size: 1 + - name: I2C3SMEN + description: "I2C3 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 7 + bit_size: 1 + - name: LPTIM1SMEN + description: "LPTIM1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 11 + bit_size: 1 + - name: RTCAPBSMEN + description: "RTC and TAMP APB clock enable during Sleep and Stop modes\r Set and cleared by software.\r Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 21 + bit_size: 1 +fieldset/BDCR: + description: RCC backup domain control register + fields: + - name: LSEON + description: "LSE oscillator enable\r Set and cleared by software.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: "LSE oscillator ready\r Set and cleared by hardware to indicate when the external 32�kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: "LSE oscillator bypass\r Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32�kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: "LSE oscillator drive capability\r Set by software to modulate the drive capability of the LSE oscillator. LSEDRV must be programmed to a different value than 0 before enabling the LSE oscillator in ‘Xtal’ mode.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The oscillator is in ‘Xtal mode’ when it is not in bypass mode." + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: "Low speed external clock security enable\r Set by software to enable the LSECSS. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware) and after the RTCSEL bit is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD�=�1). In that case, the software must disable the LSECSSON bit.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: "Low speed external clock security, LSE failure Detection\r Set by hardware to indicate when a failure is detected by the LSECCS on the external 32�kHz oscillator.\r Reset when LSCSSON bit is cleared.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 6 + bit_size: 1 + - name: LSESYSEN + description: "LSE system clock (LSESYS) enable\r Set by software to enable the LSE system clock generated by RCC. The lsesys clock is used for peripherals (USART, LPUART, LPTIM, RNG, 2.4 GHz RADIO) and functions (LSCO, MCO, TIM triggers, LPTIM trigger) excluding the RTC, TAMP and LSECSS.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 7 + bit_size: 1 + - name: RTCSEL + description: "RTC and TAMP kernel clock source enable and selection\r Set by software to enable and select the clock source for the RTC.\r Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: LSESYSRDY + description: "LSE system clock (LSESYS) ready\r Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles.\r The LSE clock must be already enabled and stable (LSEON and LSERDY are set). \r When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 11 + bit_size: 1 + - name: LSEGFON + description: "LSE clock glitch filter enable\r Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0).\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 12 + bit_size: 1 + - name: LSETRIM + description: "LSE trimming\r These bits are initialized at startup and after OBL_LAUNCH with SBF cleared with the factory-programmed LSE calibration value.\r Set and cleared by software. These bits must be modified only once after a BOR reset or an OBL_LAUNCH and before enabling LSE with LSEON (when both LSEON = 0 and LSERDY�= 0).\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: OBL_LAUNCH of this field occurs only when SBF is cleared and must then only be started by software when LSE oscillator is disabled, LSEON = 0 and LSERDY = 0." + bit_offset: 13 + bit_size: 2 + enum: LSETRIM + - name: BDRST + description: "Backup domain software reset\r Set and cleared by software.\r Can only be accessed secure when one or more features in the RTC or TAMP is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 16 + bit_size: 1 + - name: RADIOSTSEL + description: "2.4 GHz RADIO sleep timer kernel clock enable and selection\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 18 + bit_size: 2 + enum: RADIOSTSEL + - name: LSCOEN + description: "Low-speed clock output (LSCO) enable\r Set and cleared by software.\r Access can be secured by RCC LSISEC and/or RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: "Low-speed clock output selection\r Set and cleared by software.\r Access can be secured by RCC LSISEC and/or RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 25 + bit_size: 1 + enum: LSCOSEL + - name: LSI1ON + description: "LSI1 oscillator enable\r Set and cleared by software.\r Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 26 + bit_size: 1 + - name: LSI1RDY + description: "LSI1 oscillator ready\r Set and cleared by hardware to indicate when the LSI1 oscillator is stable. After the LSI1ON bit is cleared, LSI1RDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI1 is used by IWDG or RTC, even if LSI1ON = 0.\r Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 27 + bit_size: 1 + - name: LSI1PREDIV + description: "LSI1 Low-speed clock divider configuration\r Set and cleared by software to enable the LSI1 division. This bit can be written only when the LSI1 is disabled (LSI1ON = 0 and LSI1RDY = 0). The LSI1PREDIV cannot be changed if the LSI1 is used by the IWDG or by the RTC.\r Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 28 + bit_size: 1 + enum: LSIPREDIV +fieldset/CCIPR1: + description: RCC peripherals independent clock configuration register 1 + fields: + - name: USART1SEL + description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." + bit_offset: 0 + bit_size: 2 + enum: USARTSEL + - name: USART2SEL + description: "USART2 kernel clock source selection\r This bits are used to select the USART2 kernel clock source.\r Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." + bit_offset: 2 + bit_size: 2 + enum: USARTSEL + - name: I2C1SEL + description: "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16." + bit_offset: 10 + bit_size: 2 + enum: ICSEL + - name: LPTIM2SEL + description: "Low-power timer 2 kernel clock source selection\r These bits are used to select the LPTIM2 kernel clock source.\r Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1." + bit_offset: 18 + bit_size: 2 + enum: LPTIMSEL + - name: SPI1SEL + description: "SPI1 kernel clock source selection\r These bits are used to select the SPI1 kernel clock source.\r Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16." + bit_offset: 20 + bit_size: 2 + enum: SPISEL + - name: SYSTICKSEL + description: "SysTick clock source selection\r These bits are used to select the SysTick clock source.\r Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one hclk1 cycle is introduced, due to the LSE or LSI sampling with hclk1 in the SysTick circuitry." + bit_offset: 22 + bit_size: 2 + enum: SYSTICKSEL + - name: TIMICSEL + description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture \r When the TIMICSEL bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected to HSI16/256. \r When TIMICSEL is cleared, the HSI16, clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r Access can be secured by GTZC_TZSC TIM16SEC, TIM17SEC, or LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The clock division must be disabled (TIMICSEL configured to 0) before selecting or changing a clock sources division." + bit_offset: 31 + bit_size: 1 + enum: TIMICSEL +fieldset/CCIPR2: + description: RCC peripherals independent clock configuration register 2 + fields: + - name: RNGSEL + description: "RNGSEL kernel clock source selection\r These bits allow to select the RNG kernel clock source.\r Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 12 + bit_size: 2 + enum: RNGSEL +fieldset/CCIPR3: + description: RCC peripherals independent clock configuration register 3 + fields: + - name: LPUART1SEL + description: "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPUART1 is functional in Stop modes only when the kernel clock is HSI16 or LSE." + bit_offset: 0 + bit_size: 2 + enum: LPUARTSEL + - name: SPI3SEL + description: "SPI3 kernel clock source selection\r These bits are used to select the SPI3 kernel clock source.\r Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The SPI3 is functional in Stop modes only when the kernel clock is HSI16." + bit_offset: 3 + bit_size: 2 + enum: SPISEL + - name: I2C3SEL + description: "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The I2C3 is functional in Stop modes only when the kernel clock is HSI16" + bit_offset: 6 + bit_size: 2 + enum: ICSEL + - name: LPTIM1SEL + description: "LPTIM1 kernel clock source selection\r These bits are used to select the LPTIM1 kernel clock source.\r Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPTIM1 is functional in Stop modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1." + bit_offset: 10 + bit_size: 2 + enum: LPTIMSEL + - name: ADCSEL + description: "ADC4 kernel clock source selection\r These bits are used to select the ADC4 kernel clock source.\r Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r others: reserved\r Note: The ADC4 is functional in Stop modes only when the kernel clock is HSI16." + bit_offset: 12 + bit_size: 3 + enum: ADCSEL +fieldset/CFGR1: + description: RCC clock configuration register 1 + fields: + - name: SW + description: "system clock switch\r Set and cleared by software to select system clock source (SYSCLK).\r Cleared by hardware when entering Stop and Standby modes\r When selecting HSE32 directly or indirectly as system clock and HSE32 oscillator clock security fails, cleared by hardware." + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: "system clock switch status\r Set and cleared by hardware to indicate which clock source is used as system clock." + bit_offset: 2 + bit_size: 2 + enum: SW + - name: MCOSEL + description: "microcontroller clock output\r Set and cleared by software.\r others: reserved\r Note: This clock output may have some truncated cycles at startup or during MCO clock source switching." + bit_offset: 24 + bit_size: 4 + enum: MCOSEL + - name: MCOPRE + description: "microcontroller clock output prescaler\r Set and cleared by software.\r It is highly recommended to change this prescaler before MCO output is enabled.\r others: not allowed" + bit_offset: 28 + bit_size: 3 + enum: MCOPRE +fieldset/CFGR2: + description: RCC clock configuration register 2 + fields: + - name: HPRE + description: "AHB1, AHB2 and AHB4 prescaler\r Set and cleared by software to control the division factor of the AHB1, AHB2 and AHB4 clock (hclk1).\r The software must limit the incremental frequency step by setting these bits correctly to ensure that the hclk1 maximum incremental frequency step does not exceed the maximum allowed incremental frequency step (for more details, refer to Table�99: SYSCLK and bus maximum frequency). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account.\r 0xx: hclk1 = SYSCLK not divided" + bit_offset: 0 + bit_size: 3 + enum: HPRE + - name: PPRE1 + description: "APB1 prescaler\r Set and cleared by software to control the division factor of the APB1 clock (pclk1).\r 0xx: pclk1 = hclk1 not divided" + bit_offset: 4 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: "APB2 prescaler\r Set and cleared by software to control the division factor of the APB2 clock (pclk2).\r 0xx: pclk2 = hclk1 not divided" + bit_offset: 8 + bit_size: 3 + enum: PPRE +fieldset/CFGR3: + description: RCC clock configuration register 3 + fields: + - name: PPRE7 + description: "APB7 prescaler\r Set and cleared by software to control the division factor of the APB7 clock (pclk7).\r 0xx: hclk1 not divided" + bit_offset: 4 + bit_size: 3 + enum: PPRE +fieldset/CFGR4: + description: RCC clock configuration register 2 + fields: + - name: HPRE5 + description: "AHB5 prescaler when SWS select PLL1\r Set and cleared by software to control the division factor of the AHB5 clock (hclk5).\r Must not be changed when SYSCLK source indicated by SWS is PLL1.\r When SYSCLK source indicated by SWS is not PLL1: HPRE5 is not taken into account.\r When SYSCLK source indicated by SWS is PLL1: HPRE5 is taken into account, from the moment the system clock switch occurs\r Depending on the device voltage range, the software must set these bits correctly to ensure that the AHB5 frequency does not exceed the maximum allowed frequency (for more details, refer to Table�99: SYSCLK and bus maximum frequency). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account.\r 0xx: hclk5 = SYSCLK not divided" + bit_offset: 0 + bit_size: 3 + enum: HPRE5 + - name: HDIV5 + description: "AHB5 divider when SWS select HSI16 or HSE32\r Set and reset by software.\r Set to 1 by hardware when entering Stop 1 mode.\r When SYSCLK source indicated by SWS is HSI16 or HSE32: HDIV5 is taken into account\r When SYSCLK source indicated by SWS is PLL1: HDIV5 is taken not taken into account\r Depending on the device voltage range, the software must set this bit correctly to ensure that the AHB5 frequency does not exceed the maximum allowed frequency (for more details, refer to Table�99). After a write operation to this bit and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account." + bit_offset: 4 + bit_size: 1 + enum: HDIV5 +fieldset/CICR: + description: RCC clock interrupt clear register + fields: + - name: LSI1RDYC + description: "LSI1 ready interrupt clear\r Writing this bit to 1 clears the LSI1RDYF flag. Writing 0 has no effect.\r Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: "LSE ready interrupt clear\r Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect.\r Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: HSIRDYC + description: "HSI16 ready interrupt clear\r Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect.\\\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: "HSE32 ready interrupt clear\r Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 4 + bit_size: 1 + - name: PLLRDYC + description: "PLL1 ready interrupt clear\r Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect.\r Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 6 + bit_size: 1 + - name: HSECSSC + description: "High speed external clock security system interrupt clear\r Writing this bit to 1 clears the HSECSSF flag. Writing 0 has no effect.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 10 + bit_size: 1 +fieldset/CIER: + description: RCC clock interrupt enable register + fields: + - name: LSI1RDYIE + description: "LSI1 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI1 oscillator stabilization.\r Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: "LSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.\r Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: HSIRDYIE + description: "HSI16 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: "HSE32 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSE32 oscillator stabilization.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 4 + bit_size: 1 + - name: PLLRDYIE + description: "PLL1 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by PLL1 lock.\r Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 6 + bit_size: 1 +fieldset/CIFR: + description: RCC clock interrupt flag register + fields: + - name: LSI1RDYF + description: "LSI1 ready interrupt flag\r Set by hardware when the LSI1 clock becomes stable and LSI1RDYIE is set.\r Cleared by software setting the LSI1RDYC bit.\r Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: "LSE ready interrupt flag\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set.\r Cleared by software setting the LSERDYC bit.\r Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: "HSI16 ready interrupt flag\r Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see CR). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Cleared by software setting the HSIRDYC bit." + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: "HSE32 ready interrupt flag\r Set by hardware when the HSE32 clock becomes stable and HSERDYIE is set.\r Cleared by software setting the HSERDYC bit.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 4 + bit_size: 1 + - name: PLLRDYF + description: "PLL1 ready interrupt flag\r Set by hardware when the PLL1 locks and PLL1RDYIE is set.\r Cleared by software setting the PLL1RDYC bit.\r Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 6 + bit_size: 1 + - name: HSECSSF + description: "HSE32 clock security system interrupt flag\r Set by hardware when a clock security failure is detected in the HSE32 oscillator.\r Cleared by software setting the HSECSSC bit.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 10 + bit_size: 1 +fieldset/CR: + description: RCC clock control register + fields: + - name: HSION + description: "HSI16 clock enable\r Set and cleared by software.\r Cleared by hardware when entering Stop and Standby modes. \r Set by hardware to force the HSI16 oscillator on when exiting Stop and Standby modes.\r Set by hardware to force the HSI16 oscillator on in case of clock security failure of the HSE32 crystal oscillator.\r This bit is set by hardware if the HSI16 is used directly or indirectly as system clock.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: "HSI16 enable for some peripheral kernels\r Set and cleared by software to force HSI16 oscillator on even in Stop modes. \r Keeping the HSI16 oscillator on in Stop modes allows the communication speed not to be reduced by the HSI16 oscillator startup time. This bit has no effect on register bit HSION value.\r Cleared by hardware when entering Standby modes. \r Refer to Peripherals clock gating and autonomous mode for more details.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: "HSI16 clock ready flag\r Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles." + bit_offset: 10 + bit_size: 1 + - name: HSEON + description: "HSE32 clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE32 clock for the CPU when entering Stop and Standby modes and on a HSECSS failure.\r When the HSE32 is used as 2.4 GHz RADIO kernel clock, enabled by RADIOEN and RADIOSMEN and the 2.4 GHz RADIO is active, HSEON is not be cleared when entering low power mode. In this case only Stop 0 mode is entered as low power mode.\r This bit cannot be reset if the HSE32 oscillator is used directly or indirectly as the system clock.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: "HSE32 clock ready flag\r Set by hardware to indicate that the HSE32 oscillator is stable. This bit is set both when HSE32 is enabled by software by setting HSEON and when requested as kernel clock by the 2.4 GHz RADIO.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: HSECSSON + description: "HSE32 clock security system enable\r Set by software to enable the HSE32 clock security system. When HSECSSON is set, the clock detector is enabled by hardware when the HSE32 oscillator is ready and disabled by hardware if a HSE32 clock failure is detected. This bit is set only and is cleared by reset.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 19 + bit_size: 1 + - name: HSEPRE + description: "HSE32 clock for SYSCLK prescaler\r Set and cleared by software to control the division factor of the HSE32 clock for SYSCLK.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 20 + bit_size: 1 + enum: HSEPRE + - name: PLLON + description: "PLL1 enable\r Set and cleared by software to enable the main PLL.\r Cleared by hardware when entering Stop or Standby modes and when PLL1 on HSE32 is selected as sysclk, on a HSECSS failure.\r This bit cannot be reset if the PLL1 clock is used as the system clock.\r Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked.\r Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 25 + bit_size: 1 +fieldset/CSR: + description: RCC control/status register + fields: + - name: RMVF + description: "Remove reset flag\r Set by software to clear the reset flags.\r Access can be secured by RCC RMVFSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 23 + bit_size: 1 + - name: OBLRSTF + description: "Option byte loader reset flag\r Set by hardware when a reset from the option byte loading occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: "NRST pin reset flag\r Set by hardware when a reset from the NRST pin occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: "BOR flag\r Set by hardware when a BOR occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: "Software reset flag\r Set by hardware when a software reset occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: "Independent watchdog reset flag\r Set by hardware when an independent watchdog reset domain occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: "Window watchdog reset flag\r Set by hardware when a window watchdog reset occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: "Low-power reset flag\r Set by hardware when a reset occurs due to illegal Stop and Standby modes entry.\r Cleared by writing to the RMVF bit." + bit_offset: 31 + bit_size: 1 +fieldset/ECSCR1: + description: RCC external clock sources calibration register 1 + fields: + - name: HSETRIM + description: "HSE32 clock trimming \r These bits provide user-programmable capacitor trimming value. It can be programmed to adjust the HSE32 oscillator frequency." + bit_offset: 16 + bit_size: 6 +fieldset/ICSCR3: + description: RCC internal clock sources calibration register 3 + fields: + - name: HSICAL + description: "HSI16 clock calibration\r These bits are initialized at startup with the factory-programmed HSI16 calibration value. When HSITRIM[4:0] is written, HSICAL[11:0] is updated with the sum of HSITRIM[4:0] and the initial factory trim value." + bit_offset: 0 + bit_size: 12 + - name: HSITRIM + description: "HSI16 clock trimming \r These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI16." + bit_offset: 16 + bit_size: 5 +fieldset/PLL1CFGR: + description: RCC PLL1 configuration register + fields: + - name: PLLSRC + description: "PLL1 entry clock source\r Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled.\r Cleared by hardware when entering Stop or Standby modes. \r Note: In order to save power, when no PLL1 clock is used, the value of PLL1SRC must be 0." + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: PLLRGE + description: "PLL1 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL1.\r This bit must be written before enabling the PLL1.\r 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz" + bit_offset: 2 + bit_size: 2 + enum: PLLRGE + - name: PLLFRACEN + description: "PLL1 fractional latch enable\r Set and reset by software to latch the content of PLL1FRACN into the ΣΔ modulator.\r In order to latch the PLL1FRACN value into the ΣΔ modulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see PLL1 initialization phase for details)." + bit_offset: 4 + bit_size: 1 + - name: PLLM + description: "Prescaler for PLL1\r Set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). \r ..." + bit_offset: 8 + bit_size: 3 + - name: PLLPEN + description: "PLL1 DIVP divider output enable\r Set and reset by software to enable the pll1pclk output of the PLL1.\r To save power, PLL1PEN and PLL1P bits must be set to 0 when the pll1pclk is not used. \r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." + bit_offset: 16 + bit_size: 1 + - name: PLLQEN + description: "PLL1 DIVQ divider output enable\r Set and reset by software to enable the pll1qclk output of the PLL1.\r To save power, PLL1QEN and PLL1Q bits must be set to 0 when the pll1qclk is not used. \r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." + bit_offset: 17 + bit_size: 1 + - name: PLLREN + description: "PLL1 DIVR divider output enable\r Set and cleared by software to enable the pll1rclk output of the PLL1.\r To save power, PLL1REN and PLL1R bits must be set to 0 when the pll1rclk is not used.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." + bit_offset: 18 + bit_size: 1 + - name: PLLRCLKPRE + description: "pll1rclk clock for SYSCLK prescaler division enable\r Set and cleared by software to control the division of the pll1rclk clock for SYSCLK." + bit_offset: 20 + bit_size: 1 + enum: PLLRCLKPRE + - name: PLLRCLKPRESTEP + description: "pll1rclk clock for SYSCLK prescaler division step selection\r Set and cleared by software to control the division step of the pll1rclk clock for SYSCLK." + bit_offset: 21 + bit_size: 1 + enum: PLLRCLKPRESTEP + - name: PLLRCLKPRERDY + description: "pll1rclkpre not divided ready.\r Set by hardware after PLL1RCLKPRE has been set from divided to not divide, to indicate that the pll1rclk not divided is available on sysclkpre." + bit_offset: 22 + bit_size: 1 +fieldset/PLL1DIVR: + description: RCC PLL1 dividers register + fields: + - name: PLLN + description: "Multiplication factor for PLL1 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r others: reserved\r VCO output frequency = Fref1_ck x multiplication factor for PLL1 VCO, when fractional value 0 has been loaded into PLL1FRACN, with: \r Multiplication factor for PLL1 VCO between 4 and 512\r input frequency Fref1_ck between 4 and 16�MHz" + bit_offset: 0 + bit_size: 9 + - name: PLLP + description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1pclk clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..." + bit_offset: 9 + bit_size: 7 + - name: PLLQ + description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the PLl1QCLK clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." + bit_offset: 16 + bit_size: 7 + - name: PLLR + description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1rclk clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." + bit_offset: 24 + bit_size: 7 +fieldset/PLL1FRACR: + description: RCC PLL1 fractional divider register + fields: + - name: PLLFRACN + description: "Fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r VCO output frequency = Fref1_ck x [multiplication factor for PLL1 VCO + (PLL1FRACN / 213)], with: \r Multiplication factor for PLL1 VCO must be between 4 and 512.\r PLL1FRACN can be between 0 and 213- 1.\r The input frequency Fref1_ck must be between 4 and 16 MHz. \r To change the used fractional value on-the-fly even if the PLL1 is enabled, the application must proceed as follows:\r Set the bit PLL1FRACEN to 0. \r Write the new fractional value into PLL1FRACN. \r Set the bit PLL1FRACEN to 1." + bit_offset: 3 + bit_size: 13 +fieldset/PRIVCFGR: + description: RCC privilege configuration register + fields: + - name: SPRIV + description: "RCC secure functions privilege configuration\r Set and reset by software.\r This bit can be written only by a secure privileged access." + bit_offset: 0 + bit_size: 1 + - name: NSPRIV + description: "RCC non-secure functions privilege configuration\r Set and reset by software.\r This bit can be written only by privileged access, secure or non-secure." + bit_offset: 1 + bit_size: 1 +fieldset/RADIOENR: + description: RCC RADIO peripheral clock enable register + fields: + - name: BBCLKEN + description: "2.4 GHz RADIO baseband kernel clock (aclk) enable\r Set and cleared by software.\r Note: The HSE32 oscillator needs to be enabled by either HSEON or STRADIOCLKON." + bit_offset: 1 + bit_size: 1 + - name: STRADIOCLKON + description: "2.4 GHz RADIO bus clock enable and HSE32 oscillator enable by 2.4 GHz RADIO sleep timer wakeup event\r Set by hardware on a 2.4 GHz RADIO sleep timer wakeup event.\r Cleared by software writing zero to this bit.\r Note: Before accessing the 2.4 GHz RADIO registers the RADIOCLKRDY bit must be checked." + bit_offset: 16 + bit_size: 1 + - name: RADIOCLKRDY + description: "2.4 GHz RADIO bus clock ready.\r Set and cleared by hardware to indicate that the 2.4 GHz RADIO bus clock is ready and the 2.4 GHz RADIO registers can be accessed.\r Note: Once both RADIOEN and STRADIOCLKON are cleared, RADIOCLKRDY goes low after three hclk5 clock cycles." + bit_offset: 17 + bit_size: 1 +fieldset/SECCFGR: + description: RCC secure configuration register + fields: + - name: HSISEC + description: "HSI16 clock configuration and status bits security\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: HSESEC + description: "HSE32 clock configuration bits, status bits and HSECSS security\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: LSISEC + description: "LSI clock configuration and status bits security\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: LSESEC + description: "LSE clock configuration and status bits security\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: SYSCLKSEC + description: "SYSCLK selection, clock output on MCO configuration security\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: PRESCSEC + description: "AHBx/APBx prescaler configuration bits security\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: PLLSEC + description: "PLL1 clock configuration and status bits security\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: RMVFSEC + description: "Remove reset flag security\r Set and reset by software." + bit_offset: 12 + bit_size: 1 +enum/ADCSEL: + bit_size: 3 + variants: + - name: HCLK1 + description: hclk1 clock selected + value: 0 + - name: SYSCLK + description: SYSCLK selected + value: 1 + - name: PLL1_P + description: pll1pclk selected + value: 2 + - name: HSE32 + description: HSE32 clock selected + value: 3 + - name: HSI16 + description: HSI16 clock selected + value: 4 +enum/HDIV5: + bit_size: 1 + variants: + - name: Div1 + description: hclk5 = SYSCLK not divided + value: 0 + - name: Div2 + description: hclk5 = SYSCLK divided by 2 + value: 1 +enum/HPRE: + bit_size: 3 + variants: + - name: Div1 + description: DCLK not divided + value: 0 + - name: Div2 + description: hclk = SYSCLK divided by 2 + value: 4 + - name: Div4 + description: hclk = SYSCLK divided by 4 + value: 5 + - name: Div8 + description: hclk = SYSCLK divided by 8 + value: 6 + - name: Div16 + description: hclk = SYSCLK divided by 16 + value: 7 +enum/HPRE5: + bit_size: 3 + variants: + - name: Div1 + description: DCLK not divided + value: 0 + - name: Div2 + description: hclk5 = SYSCLK divided by 2 + value: 4 + - name: Div3 + description: hclk5 = SYSCLK divided by 3 + value: 5 + - name: Div4 + description: hclk5 = SYSCLK divided by 4 + value: 6 + - name: Div6 + description: hclk5 = SYSCLK divided by 6 + value: 7 +enum/HSEPRE: + bit_size: 1 + variants: + - name: Div1 + description: HSE32 not divided, SYSCLK = HSE32 + value: 0 + - name: Div2 + description: HSE32 divided, SYSCLK = HSE32/2 + value: 1 +enum/ICSEL: + bit_size: 2 + variants: + - name: PCLK1 + description: pclk1 selected + value: 0 + - name: SYSCLK + description: SYSCLK selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 +enum/LPTIMSEL: + bit_size: 2 + variants: + - name: PCLK7 + description: pclk7 selected. + value: 0 + - name: LSI + description: LSI selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 + - name: LSE + description: LSE selected + value: 3 +enum/LPUARTSEL: + bit_size: 2 + variants: + - name: PCLK7 + description: pclk7 selected + value: 0 + - name: SYSCLK + description: SYSCLK selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 + - name: LSE + description: LSE selected + value: 3 +enum/LSCOSEL: + bit_size: 1 + variants: + - name: LSI + description: LSI clock selected + value: 0 + - name: LSE + description: LSE clock selected + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - name: LOW + description: '''Xtal mode lower driving capability' + value: 0 + - name: MEDIUM_LOW + description: '''Xtal mode medium-low driving capability' + value: 1 + - name: MEDIUM_HIGH + description: '''Xtal mode medium-high driving capability' + value: 2 + - name: HIGH + description: '''Xtal mode higher driving capability' + value: 3 +enum/LSETRIM: + bit_size: 2 + variants: + - name: R5_4 + description: current source resistance 5/4 x R + value: 0 + - name: R + description: current source resistance R + value: 1 + - name: R3_4 + description: current source resistance 3/4 x R + value: 2 + - name: R2_3 + description: current source resistance 2/3 x R + value: 3 +enum/LSIPREDIV: + bit_size: 1 + variants: + - name: Div1 + description: LSI not divided + value: 0 + - name: Div128 + description: LSI divided by 128 + value: 1 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: MCO divided by 1 + value: 0 + - name: Div2 + description: MCO divided by 2 + value: 1 + - name: Div4 + description: MCO divided by 4 + value: 2 + - name: Div8 + description: MCO divided by 8 + value: 3 + - name: Div16 + description: MCO divided by 16 + value: 4 +enum/MCOSEL: + bit_size: 4 + variants: + - name: DISABLED + description: MCO output disabled, no clock on MCO + value: 0 + - name: SYSCLKPRE + description: sysclkpre system clock after PLL1RCLKPRE division selected + value: 1 + - name: HSI16 + description: HSI16 clock selected + value: 3 + - name: HSE32 + description: HSE32 clock selected + value: 4 + - name: PLL1_R + description: pll1rclk clock selected + value: 5 + - name: LSI + description: LSI clock selected + value: 6 + - name: LSE + description: LSE clock selected + value: 7 + - name: PLL1_P + description: pll1pclk clock selected + value: 8 + - name: PLL1_Q + description: pll1qclk clock selected + value: 9 + - name: HCLK5 + description: hclk5 clock selected + value: 10 +enum/PLLRCLKPRE: + bit_size: 1 + variants: + - name: Div1 + description: pll1rclk not divided, sysclkpre = pll1rclk + value: 0 + - name: Divided + description: pll1rclk divided, sysclkpre = pll1rclk divided + value: 1 +enum/PLLRCLKPRESTEP: + bit_size: 1 + variants: + - name: STEP2 + description: pll1rclk 2-step division + value: 0 + - name: STEP3 + description: pll1rclk 3-step division + value: 1 +enum/PLLRGE: + bit_size: 2 + variants: + - name: FREQ_4TO8MHZ + description: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz + value: 0 + - name: FREQ_8TO16MHZ + description: PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz + value: 3 +enum/PLLSRC: + bit_size: 2 + variants: + - name: NONE + description: no clock sent to PLL1 + value: 0 + - name: HSI16 + description: HSI16 clock selected as PLL1 clock entry + value: 2 + - name: HSE32 + description: HSE32 clock after HSEPRE divider selected as PLL1 clock entry + value: 3 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/RADIOSTSEL: + bit_size: 2 + variants: + - name: None + description: no clock selected, 2.4 GHz RADIO sleep timer kernel clock disabled + value: 0 + - name: LSE + description: LSE oscillator clock selected + value: 1 + - name: HSE32 + description: HSE32 oscillator clock divided by 1000 selected + value: 3 +enum/RNGSEL: + bit_size: 2 + variants: + - name: LSE + description: LSE selected + value: 0 + - name: LSI + description: LSI selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 + - name: PLL1_Q + description: pll1qclk divide by 2 selected + value: 3 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: no clock selected, RTC and TAMP kernel clock disabled + value: 0 + - name: LSE + description: LSE oscillator clock selected, and enabled + value: 1 + - name: LSI + description: LSI oscillator clock selected, and enabled + value: 2 + - name: HSE32 + description: HSE32 oscillator clock divided by 32 selected, and enabled + value: 3 +enum/SPISEL: + bit_size: 2 + variants: + - name: PCLK2 + description: pclk2 selected + value: 0 + - name: SYSCLK + description: SYSCLK selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 +enum/SW: + bit_size: 2 + variants: + - name: HSI16 + description: HSI16 selected as system clock + value: 0 + - name: HSE32 + description: HSE32 or HSE32/2, as defined by HSEPRE, selected as system clock + value: 2 + - name: PLL1_R + description: pll1rclk selected as system clock + value: 3 +enum/SYSTICKSEL: + bit_size: 2 + variants: + - name: HCLK1_DIV8 + description: hclk1 divided by 8 selected + value: 0 + - name: LSI + description: LSI selected + value: 1 + - name: LSE + description: LSE selected + value: 2 +enum/TIMICSEL: + bit_size: 1 + variants: + - name: Div1 + description: HSI16 divider disabled + value: 0 + - name: HSI16_DIV_256 + description: HSI16/256 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + value: 1 +enum/USARTSEL: + bit_size: 2 + variants: + - name: PCLK1 + description: pclk1 selected + value: 0 + - name: SYSCLK + description: SYSCLK selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 + - name: LSE + description: LSE selected + value: 3 diff --git a/data/registers/rcc_wl5.yaml b/data/registers/rcc_wl5.yaml index 828c986..a8ee025 100644 --- a/data/registers/rcc_wl5.yaml +++ b/data/registers/rcc_wl5.yaml @@ -1,1424 +1,1571 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: Clock control register - byte_offset: 0 - fieldset: CR - - name: ICSCR - description: Internal clock sources calibration register - byte_offset: 4 - fieldset: ICSCR - - name: CFGR - description: Clock configuration register - byte_offset: 8 - fieldset: CFGR - - name: PLLCFGR - description: PLL configuration register - byte_offset: 12 - fieldset: PLLCFGR - - name: CIER - description: Clock interrupt enable register - byte_offset: 24 - fieldset: CIER - - name: CIFR - description: Clock interrupt flag register - byte_offset: 28 - access: Read - fieldset: CIFR - - name: CICR - description: Clock interrupt clear register - byte_offset: 32 - access: Write - fieldset: CICR - - name: AHB1RSTR - description: AHB1 peripheral reset register - byte_offset: 40 - fieldset: AHB1RSTR - - name: AHB2RSTR - description: AHB2 peripheral reset register - byte_offset: 44 - fieldset: AHB2RSTR - - name: AHB3RSTR - description: AHB3 peripheral reset register - byte_offset: 48 - fieldset: AHB3RSTR - - name: APB1RSTR1 - description: APB1 peripheral reset register 1 - byte_offset: 56 - fieldset: APB1RSTR1 - - name: APB1RSTR2 - description: APB1 peripheral reset register 2 - byte_offset: 60 - fieldset: APB1RSTR2 - - name: APB2RSTR - description: APB2 peripheral reset register - byte_offset: 64 - fieldset: APB2RSTR - - name: APB3RSTR - description: APB3 peripheral reset register - byte_offset: 68 - fieldset: APB3RSTR - - name: AHB1ENR - description: AHB1 peripheral clock enable register - byte_offset: 72 - fieldset: AHB1ENR - - name: AHB2ENR - description: AHB2 peripheral clock enable register - byte_offset: 76 - fieldset: AHB2ENR - - name: AHB3ENR - description: AHB3 peripheral clock enable register - byte_offset: 80 - fieldset: AHB3ENR - - name: APB1ENR1 - description: APB1 peripheral clock enable register 1 - byte_offset: 88 - fieldset: APB1ENR1 - - name: APB1ENR2 - description: APB1 peripheral clock enable register 2 - byte_offset: 92 - fieldset: APB1ENR2 - - name: APB2ENR - description: APB2 peripheral clock enable register - byte_offset: 96 - fieldset: APB2ENR - - name: APB3ENR - description: APB3 peripheral clock enable register - byte_offset: 100 - fieldset: APB3ENR - - name: AHB1SMENR - description: AHB1 peripheral clocks enable in Sleep modes register - byte_offset: 104 - fieldset: AHB1SMENR - - name: AHB2SMENR - description: AHB2 peripheral clocks enable in Sleep modes register - byte_offset: 108 - fieldset: AHB2SMENR - - name: AHB3SMENR - description: AHB3 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 112 - fieldset: AHB3SMENR - - name: APB1SMENR1 - description: APB1 peripheral clocks enable in Sleep mode register 1 - byte_offset: 120 - fieldset: APB1SMENR1 - - name: APB1SMENR2 - description: APB1 peripheral clocks enable in Sleep mode register 2 - byte_offset: 124 - fieldset: APB1SMENR2 - - name: APB2SMENR - description: APB2 peripheral clocks enable in Sleep mode register - byte_offset: 128 - fieldset: APB2SMENR - - name: APB3SMENR - description: APB3 peripheral clock enable in Sleep mode register - byte_offset: 132 - fieldset: APB3SMENR - - name: CCIPR - description: Peripherals independent clock configuration register - byte_offset: 136 - fieldset: CCIPR - - name: BDCR - description: Backup domain control register - byte_offset: 144 - fieldset: BDCR - - name: CSR - description: Control/status register - byte_offset: 148 - fieldset: CSR - - name: EXTCFGR - description: Extended clock recovery register - byte_offset: 264 - fieldset: EXTCFGR - - name: C2AHB1ENR - description: CPU2 AHB1 peripheral clock enable register - byte_offset: 328 - fieldset: C2AHB1ENR - - name: C2AHB2ENR - description: CPU2 AHB2 peripheral clock enable register - byte_offset: 332 - fieldset: C2AHB2ENR - - name: C2AHB3ENR - description: "CPU2 AHB3 peripheral clock enable register [dual core device only]" - byte_offset: 336 - fieldset: C2AHB3ENR - - name: C2APB1ENR1 - description: "CPU2 APB1 peripheral clock enable register 1 [dual core device only]" - byte_offset: 344 - fieldset: C2APB1ENR1 - - name: C2APB1ENR2 - description: "CPU2 APB1 peripheral clock enable register 2 [dual core device only]" - byte_offset: 348 - fieldset: C2APB1ENR2 - - name: C2APB2ENR - description: "CPU2 APB2 peripheral clock enable register [dual core device only]" - byte_offset: 352 - fieldset: C2APB2ENR - - name: C2APB3ENR - description: "CPU2 APB3 peripheral clock enable register [dual core device only]" - byte_offset: 356 - fieldset: C2APB3ENR - - name: C2AHB1SMENR - description: "CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only]" - byte_offset: 360 - fieldset: C2AHB1SMENR - - name: C2AHB2SMENR - description: "CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only]" - byte_offset: 364 - fieldset: C2AHB2SMENR - - name: C2AHB3SMENR - description: "CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only]" - byte_offset: 368 - fieldset: C2AHB3SMENR - - name: C2APB1SMENR1 - description: "CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only]" - byte_offset: 376 - fieldset: C2APB1SMENR1 - - name: C2APB1SMENR2 - description: "CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only]" - byte_offset: 380 - fieldset: C2APB1SMENR2 - - name: C2APB2SMENR - description: "CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only]" - byte_offset: 384 - fieldset: C2APB2SMENR - - name: C2APB3SMENR - description: "CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only]" - byte_offset: 388 - fieldset: C2APB3SMENR + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: Internal clock sources calibration register + byte_offset: 4 + fieldset: ICSCR + - name: CFGR + description: Clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: PLLCFGR + description: PLL configuration register + byte_offset: 12 + fieldset: PLLCFGR + - name: CIER + description: Clock interrupt enable register + byte_offset: 24 + fieldset: CIER + - name: CIFR + description: Clock interrupt flag register + byte_offset: 28 + access: Read + fieldset: CIFR + - name: CICR + description: Clock interrupt clear register + byte_offset: 32 + access: Write + fieldset: CICR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 40 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: AHB2 peripheral reset register + byte_offset: 44 + fieldset: AHB2RSTR + - name: AHB3RSTR + description: AHB3 peripheral reset register + byte_offset: 48 + fieldset: AHB3RSTR + - name: APB1RSTR1 + description: APB1 peripheral reset register 1 + byte_offset: 56 + fieldset: APB1RSTR1 + - name: APB1RSTR2 + description: APB1 peripheral reset register 2 + byte_offset: 60 + fieldset: APB1RSTR2 + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 64 + fieldset: APB2RSTR + - name: APB3RSTR + description: APB3 peripheral reset register + byte_offset: 68 + fieldset: APB3RSTR + - name: AHB1ENR + description: AHB1 peripheral clock enable register + byte_offset: 72 + fieldset: AHB1ENR + - name: AHB2ENR + description: AHB2 peripheral clock enable register + byte_offset: 76 + fieldset: AHB2ENR + - name: AHB3ENR + description: AHB3 peripheral clock enable register + byte_offset: 80 + fieldset: AHB3ENR + - name: APB1ENR1 + description: APB1 peripheral clock enable register 1 + byte_offset: 88 + fieldset: APB1ENR1 + - name: APB1ENR2 + description: APB1 peripheral clock enable register 2 + byte_offset: 92 + fieldset: APB1ENR2 + - name: APB2ENR + description: APB2 peripheral clock enable register + byte_offset: 96 + fieldset: APB2ENR + - name: APB3ENR + description: APB3 peripheral clock enable register + byte_offset: 100 + fieldset: APB3ENR + - name: AHB1SMENR + description: AHB1 peripheral clocks enable in Sleep modes register + byte_offset: 104 + fieldset: AHB1SMENR + - name: AHB2SMENR + description: AHB2 peripheral clocks enable in Sleep modes register + byte_offset: 108 + fieldset: AHB2SMENR + - name: AHB3SMENR + description: AHB3 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 112 + fieldset: AHB3SMENR + - name: APB1SMENR1 + description: APB1 peripheral clocks enable in Sleep mode register 1 + byte_offset: 120 + fieldset: APB1SMENR1 + - name: APB1SMENR2 + description: APB1 peripheral clocks enable in Sleep mode register 2 + byte_offset: 124 + fieldset: APB1SMENR2 + - name: APB2SMENR + description: APB2 peripheral clocks enable in Sleep mode register + byte_offset: 128 + fieldset: APB2SMENR + - name: APB3SMENR + description: APB3 peripheral clock enable in Sleep mode register + byte_offset: 132 + fieldset: APB3SMENR + - name: CCIPR + description: Peripherals independent clock configuration register + byte_offset: 136 + fieldset: CCIPR + - name: BDCR + description: Backup domain control register + byte_offset: 144 + fieldset: BDCR + - name: CSR + description: Control/status register + byte_offset: 148 + fieldset: CSR + - name: EXTCFGR + description: Extended clock recovery register + byte_offset: 264 + fieldset: EXTCFGR + - name: C2AHB1ENR + description: CPU2 AHB1 peripheral clock enable register + byte_offset: 328 + fieldset: C2AHB1ENR + - name: C2AHB2ENR + description: CPU2 AHB2 peripheral clock enable register + byte_offset: 332 + fieldset: C2AHB2ENR + - name: C2AHB3ENR + description: CPU2 AHB3 peripheral clock enable register [dual core device only] + byte_offset: 336 + fieldset: C2AHB3ENR + - name: C2APB1ENR1 + description: CPU2 APB1 peripheral clock enable register 1 [dual core device only] + byte_offset: 344 + fieldset: C2APB1ENR1 + - name: C2APB1ENR2 + description: CPU2 APB1 peripheral clock enable register 2 [dual core device only] + byte_offset: 348 + fieldset: C2APB1ENR2 + - name: C2APB2ENR + description: CPU2 APB2 peripheral clock enable register [dual core device only] + byte_offset: 352 + fieldset: C2APB2ENR + - name: C2APB3ENR + description: CPU2 APB3 peripheral clock enable register [dual core device only] + byte_offset: 356 + fieldset: C2APB3ENR + - name: C2AHB1SMENR + description: CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only] + byte_offset: 360 + fieldset: C2AHB1SMENR + - name: C2AHB2SMENR + description: CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only] + byte_offset: 364 + fieldset: C2AHB2SMENR + - name: C2AHB3SMENR + description: CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only] + byte_offset: 368 + fieldset: C2AHB3SMENR + - name: C2APB1SMENR1 + description: CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only] + byte_offset: 376 + fieldset: C2APB1SMENR1 + - name: C2APB1SMENR2 + description: CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only] + byte_offset: 380 + fieldset: C2APB1SMENR2 + - name: C2APB2SMENR + description: CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only] + byte_offset: 384 + fieldset: C2APB2SMENR + - name: C2APB3SMENR + description: CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only] + byte_offset: 388 + fieldset: C2APB3SMENR fieldset/AHB1ENR: description: AHB1 peripheral clock enable register fields: - - name: DMA1EN - description: CPU1 DMA1 clock enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: CPU1 DMA2 clock enable - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1EN - description: CPU1 DMAMUX1 clock enable - bit_offset: 2 - bit_size: 1 - - name: CRCEN - description: CPU1 CRC clock enable - bit_offset: 12 - bit_size: 1 + - name: DMA1EN + description: CPU1 DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: CPU1 DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1EN + description: CPU1 DMAMUX1 clock enable + bit_offset: 2 + bit_size: 1 + - name: CRCEN + description: CPU1 CRC clock enable + bit_offset: 12 + bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - - name: DMA1RST - description: DMA1 reset - bit_offset: 0 - bit_size: 1 - - name: DMA2RST - description: DMA2 reset - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1RST - description: DMAMUX1 reset - bit_offset: 2 - bit_size: 1 - - name: CRCRST - description: CRC reset - bit_offset: 12 - bit_size: 1 + - name: DMA1RST + description: DMA1 reset + bit_offset: 0 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1RST + description: DMAMUX1 reset + bit_offset: 2 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 fieldset/AHB1SMENR: description: AHB1 peripheral clocks enable in Sleep modes register fields: - - name: DMA1SMEN - description: DMA1 clock enable during CPU1 CSleep mode. - bit_offset: 0 - bit_size: 1 - - name: DMA2SMEN - description: DMA2 clock enable during CPU1 CSleep mode - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1SMEN - description: DMAMUX1 clock enable during CPU1 CSleep mode. - bit_offset: 2 - bit_size: 1 - - name: CRCSMEN - description: CRC clock enable during CPU1 CSleep mode. - bit_offset: 12 - bit_size: 1 + - name: DMA1SMEN + description: DMA1 clock enable during CPU1 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: DMA2SMEN + description: DMA2 clock enable during CPU1 CSleep mode + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1SMEN + description: DMAMUX1 clock enable during CPU1 CSleep mode. + bit_offset: 2 + bit_size: 1 + - name: CRCSMEN + description: CRC clock enable during CPU1 CSleep mode. + bit_offset: 12 + bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - - name: GPIOAEN - description: CPU1 IO port A clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: CPU1 IO port B clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: CPU1 IO port C clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIOHEN - description: CPU1 IO port H clock enable - bit_offset: 7 - bit_size: 1 + - name: GPIOAEN + description: CPU1 IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: CPU1 IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: CPU1 IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIOHEN + description: CPU1 IO port H clock enable + bit_offset: 7 + bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - - name: GPIOARST - description: IO port A reset - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: IO port B reset - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: IO port C reset - bit_offset: 2 - bit_size: 1 - - name: GPIOHRST - description: IO port H reset - bit_offset: 7 - bit_size: 1 + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 7 + bit_size: 1 fieldset/AHB2SMENR: description: AHB2 peripheral clocks enable in Sleep modes register fields: - - name: GPIOASMEN - description: IO port A clock enable during CPU1 CSleep mode. - bit_offset: 0 - bit_size: 1 - - name: GPIOBSMEN - description: IO port B clock enable during CPU1 CSleep mode. - bit_offset: 1 - bit_size: 1 - - name: GPIOCSMEN - description: IO port C clock enable during CPU1 CSleep mode. - bit_offset: 2 - bit_size: 1 - - name: GPIOHSMEN - description: IO port H clock enable during CPU1 CSleep mode. - bit_offset: 7 - bit_size: 1 + - name: GPIOASMEN + description: IO port A clock enable during CPU1 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: IO port B clock enable during CPU1 CSleep mode. + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: IO port C clock enable during CPU1 CSleep mode. + bit_offset: 2 + bit_size: 1 + - name: GPIOHSMEN + description: IO port H clock enable during CPU1 CSleep mode. + bit_offset: 7 + bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: - - name: PKAEN - description: PKAEN - bit_offset: 16 - bit_size: 1 - - name: AESEN - description: AESEN - bit_offset: 17 - bit_size: 1 - - name: RNGEN - description: RNGEN - bit_offset: 18 - bit_size: 1 - - name: HSEMEN - description: HSEMEN - bit_offset: 19 - bit_size: 1 - - name: IPCCEN - description: IPCCEN - bit_offset: 20 - bit_size: 1 - - name: FLASHEN - description: CPU1 Flash interface clock enable - bit_offset: 25 - bit_size: 1 + - name: PKAEN + description: PKAEN + bit_offset: 16 + bit_size: 1 + - name: AESEN + description: AESEN + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: RNGEN + bit_offset: 18 + bit_size: 1 + - name: HSEMEN + description: HSEMEN + bit_offset: 19 + bit_size: 1 + - name: IPCCEN + description: IPCCEN + bit_offset: 20 + bit_size: 1 + - name: FLASHEN + description: CPU1 Flash interface clock enable + bit_offset: 25 + bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - - name: PKARST - description: PKARST - bit_offset: 16 - bit_size: 1 - - name: AESRST - description: AESRST - bit_offset: 17 - bit_size: 1 - - name: RNGRST - description: RNGRST - bit_offset: 18 - bit_size: 1 - - name: HSEMRST - description: HSEMRST - bit_offset: 19 - bit_size: 1 - - name: IPCCRST - description: IPCCRST - bit_offset: 20 - bit_size: 1 - - name: FLASHRST - description: Flash interface reset - bit_offset: 25 - bit_size: 1 + - name: PKARST + description: PKARST + bit_offset: 16 + bit_size: 1 + - name: AESRST + description: AESRST + bit_offset: 17 + bit_size: 1 + - name: RNGRST + description: RNGRST + bit_offset: 18 + bit_size: 1 + - name: HSEMRST + description: HSEMRST + bit_offset: 19 + bit_size: 1 + - name: IPCCRST + description: IPCCRST + bit_offset: 20 + bit_size: 1 + - name: FLASHRST + description: Flash interface reset + bit_offset: 25 + bit_size: 1 fieldset/AHB3SMENR: description: AHB3 peripheral clocks enable in Sleep and Stop modes register fields: - - name: PKASMEN - description: PKA accelerator clock enable during CPU1 CSleep mode. - bit_offset: 16 - bit_size: 1 - - name: AESSMEN - description: AES accelerator clock enable during CPU1 CSleep mode. - bit_offset: 17 - bit_size: 1 - - name: RNGSMEN - description: True RNG clocks enable during CPU1 Csleep and CStop modes - bit_offset: 18 - bit_size: 1 - - name: SRAM1SMEN - description: SRAM1 interface clock enable during CPU1 CSleep mode. - bit_offset: 23 - bit_size: 1 - - name: SRAM2SMEN - description: SRAM2 memory interface clock enable during CPU1 CSleep mode - bit_offset: 24 - bit_size: 1 - - name: FLASHSMEN - description: Flash interface clock enable during CPU1 CSleep mode. - bit_offset: 25 - bit_size: 1 + - name: PKASMEN + description: PKA accelerator clock enable during CPU1 CSleep mode. + bit_offset: 16 + bit_size: 1 + - name: AESSMEN + description: AES accelerator clock enable during CPU1 CSleep mode. + bit_offset: 17 + bit_size: 1 + - name: RNGSMEN + description: True RNG clocks enable during CPU1 Csleep and CStop modes + bit_offset: 18 + bit_size: 1 + - name: SRAM1SMEN + description: SRAM1 interface clock enable during CPU1 CSleep mode. + bit_offset: 23 + bit_size: 1 + - name: SRAM2SMEN + description: SRAM2 memory interface clock enable during CPU1 CSleep mode + bit_offset: 24 + bit_size: 1 + - name: FLASHSMEN + description: Flash interface clock enable during CPU1 CSleep mode. + bit_offset: 25 + bit_size: 1 fieldset/APB1ENR1: description: APB1 peripheral clock enable register 1 fields: - - name: TIM2EN - description: CPU1 TIM2 timer clock enable - bit_offset: 0 - bit_size: 1 - - name: RTCAPBEN - description: CPU1 RTC APB clock enable - bit_offset: 10 - bit_size: 1 - - name: WWDGEN - description: CPU1 Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: CPU1 SPI2 clock enable - bit_offset: 14 - bit_size: 1 - - name: USART2EN - description: CPU1 USART2 clock enable - bit_offset: 17 - bit_size: 1 - - name: I2C1EN - description: CPU1 I2C1 clocks enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: CPU1 I2C2 clocks enable - bit_offset: 22 - bit_size: 1 - - name: I2C3EN - description: CPU1 I2C3 clocks enable - bit_offset: 23 - bit_size: 1 - - name: DAC1EN - description: CPU1 DAC1 clock enable - bit_offset: 29 - bit_size: 1 - - name: LPTIM1EN - description: CPU1 Low power timer 1 clocks enable - bit_offset: 31 - bit_size: 1 + - name: TIM2EN + description: CPU1 TIM2 timer clock enable + bit_offset: 0 + bit_size: 1 + - name: RTCAPBEN + description: CPU1 RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: CPU1 Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: CPU1 SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: USART2EN + description: CPU1 USART2 clock enable + bit_offset: 17 + bit_size: 1 + - name: I2C1EN + description: CPU1 I2C1 clocks enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: CPU1 I2C2 clocks enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: CPU1 I2C3 clocks enable + bit_offset: 23 + bit_size: 1 + - name: DAC1EN + description: CPU1 DAC1 clock enable + bit_offset: 29 + bit_size: 1 + - name: LPTIM1EN + description: CPU1 Low power timer 1 clocks enable + bit_offset: 31 + bit_size: 1 fieldset/APB1ENR2: description: APB1 peripheral clock enable register 2 fields: - - name: LPUART1EN - description: CPU1 Low power UART 1 clocks enable - bit_offset: 0 - bit_size: 1 - - name: LPTIM2EN - description: CPU1 Low power timer 2 clocks enable - bit_offset: 5 - bit_size: 1 - - name: LPTIM3EN - description: CPU1 Low power timer 3 clocks enable - bit_offset: 6 - bit_size: 1 + - name: LPUART1EN + description: CPU1 Low power UART 1 clocks enable + bit_offset: 0 + bit_size: 1 + - name: LPTIM2EN + description: CPU1 Low power timer 2 clocks enable + bit_offset: 5 + bit_size: 1 + - name: LPTIM3EN + description: CPU1 Low power timer 3 clocks enable + bit_offset: 6 + bit_size: 1 fieldset/APB1RSTR1: description: APB1 peripheral reset register 1 fields: - - name: TIM2RST - description: TIM2 timer reset - bit_offset: 0 - bit_size: 1 - - name: SPI2RST - description: SPI2 reset - bit_offset: 14 - bit_size: 1 - - name: USART2RST - description: USART2 reset - bit_offset: 17 - bit_size: 1 - - name: I2C1RST - description: I2C1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C2 reset - bit_offset: 22 - bit_size: 1 - - name: I2C3RST - description: I2C3 reset - bit_offset: 23 - bit_size: 1 - - name: DACRST - description: DAC1 reset - bit_offset: 29 - bit_size: 1 - - name: LPTIM1RST - description: Low Power Timer 1 reset - bit_offset: 31 - bit_size: 1 + - name: TIM2RST + description: TIM2 timer reset + bit_offset: 0 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: USART2RST + description: USART2 reset + bit_offset: 17 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 23 + bit_size: 1 + - name: DACRST + description: DAC1 reset + bit_offset: 29 + bit_size: 1 + - name: LPTIM1RST + description: Low Power Timer 1 reset + bit_offset: 31 + bit_size: 1 fieldset/APB1RSTR2: description: APB1 peripheral reset register 2 fields: - - name: LPUART1RST - description: Low-power UART 1 reset - bit_offset: 0 - bit_size: 1 - - name: LPTIM2RST - description: Low-power timer 2 reset - bit_offset: 5 - bit_size: 1 - - name: LPTIM3RST - description: Low-power timer 3 reset - bit_offset: 6 - bit_size: 1 + - name: LPUART1RST + description: Low-power UART 1 reset + bit_offset: 0 + bit_size: 1 + - name: LPTIM2RST + description: Low-power timer 2 reset + bit_offset: 5 + bit_size: 1 + - name: LPTIM3RST + description: Low-power timer 3 reset + bit_offset: 6 + bit_size: 1 fieldset/APB1SMENR1: description: APB1 peripheral clocks enable in Sleep mode register 1 fields: - - name: TIM2SMEN - description: TIM2 timer clock enable during CPU1 CSleep mode. - bit_offset: 0 - bit_size: 1 - - name: RTCAPBSMEN - description: RTC bus clock enable during CPU1 CSleep mode. - bit_offset: 10 - bit_size: 1 - - name: WWDGSMEN - description: Window watchdog clocks enable during CPU1 CSleep mode. - bit_offset: 11 - bit_size: 1 - - name: SPI2SMEN - description: SPI2 clock enable during CPU1 CSleep mode. - bit_offset: 14 - bit_size: 1 - - name: USART2SMEN - description: USART2 clock enable during CPU1 CSleep mode. - bit_offset: 17 - bit_size: 1 - - name: I2C1SMEN - description: I2C1 clock enable during CPU1 Csleep and CStop modes - bit_offset: 21 - bit_size: 1 - - name: I2C2SMEN - description: I2C2 clock enable during CPU1 Csleep and CStop modes - bit_offset: 22 - bit_size: 1 - - name: I2C3SMEN - description: I2C3 clock enable during CPU1 Csleep and CStop modes - bit_offset: 23 - bit_size: 1 - - name: DACSMEN - description: DAC1 clock enable during CPU1 CSleep mode. - bit_offset: 29 - bit_size: 1 - - name: LPTIM1SMEN - description: Low power timer 1 clock enable during CPU1 Csleep and CStop mode - bit_offset: 31 - bit_size: 1 + - name: TIM2SMEN + description: TIM2 timer clock enable during CPU1 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: RTCAPBSMEN + description: RTC bus clock enable during CPU1 CSleep mode. + bit_offset: 10 + bit_size: 1 + - name: WWDGSMEN + description: Window watchdog clocks enable during CPU1 CSleep mode. + bit_offset: 11 + bit_size: 1 + - name: SPI2SMEN + description: SPI2 clock enable during CPU1 CSleep mode. + bit_offset: 14 + bit_size: 1 + - name: USART2SMEN + description: USART2 clock enable during CPU1 CSleep mode. + bit_offset: 17 + bit_size: 1 + - name: I2C1SMEN + description: I2C1 clock enable during CPU1 Csleep and CStop modes + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: I2C2 clock enable during CPU1 Csleep and CStop modes + bit_offset: 22 + bit_size: 1 + - name: I2C3SMEN + description: I2C3 clock enable during CPU1 Csleep and CStop modes + bit_offset: 23 + bit_size: 1 + - name: DACSMEN + description: DAC1 clock enable during CPU1 CSleep mode. + bit_offset: 29 + bit_size: 1 + - name: LPTIM1SMEN + description: Low power timer 1 clock enable during CPU1 Csleep and CStop mode + bit_offset: 31 + bit_size: 1 fieldset/APB1SMENR2: description: APB1 peripheral clocks enable in Sleep mode register 2 fields: - - name: LPUART1SMEN - description: Low power UART 1 clock enable during CPU1 Csleep and CStop modes. - bit_offset: 0 - bit_size: 1 - - name: LPTIM2SMEN - description: Low power timer 2 clock enable during CPU1 Csleep and CStop modes - bit_offset: 5 - bit_size: 1 - - name: LPTIM3SMEN - description: Low power timer 3 clock enable during CPU1 Csleep and CStop modes - bit_offset: 6 - bit_size: 1 + - name: LPUART1SMEN + description: Low power UART 1 clock enable during CPU1 Csleep and CStop modes. + bit_offset: 0 + bit_size: 1 + - name: LPTIM2SMEN + description: Low power timer 2 clock enable during CPU1 Csleep and CStop modes + bit_offset: 5 + bit_size: 1 + - name: LPTIM3SMEN + description: Low power timer 3 clock enable during CPU1 Csleep and CStop modes + bit_offset: 6 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - - name: ADCEN - description: CPU1 ADC clocks enable - bit_offset: 9 - bit_size: 1 - - name: TIM1EN - description: CPU1 TIM1 timer clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: CPU1 SPI1 clock enable - bit_offset: 12 - bit_size: 1 - - name: USART1EN - description: CPU1 USART1clocks enable - bit_offset: 14 - bit_size: 1 - - name: TIM16EN - description: CPU1 TIM16 timer clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: CPU1 TIM17 timer clock enable - bit_offset: 18 - bit_size: 1 + - name: ADCEN + description: CPU1 ADC clocks enable + bit_offset: 9 + bit_size: 1 + - name: TIM1EN + description: CPU1 TIM1 timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: CPU1 SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: CPU1 USART1clocks enable + bit_offset: 14 + bit_size: 1 + - name: TIM16EN + description: CPU1 TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: CPU1 TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - - name: ADCRST - description: ADC reset - bit_offset: 9 - bit_size: 1 - - name: TIM1RST - description: TIM1 timer reset - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: SPI1 reset - bit_offset: 12 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 14 - bit_size: 1 - - name: TIM16RST - description: TIM16 timer reset - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: TIM17 timer reset - bit_offset: 18 - bit_size: 1 + - name: ADCRST + description: ADC reset + bit_offset: 9 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI1 reset + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 fieldset/APB2SMENR: description: APB2 peripheral clocks enable in Sleep mode register fields: - - name: ADCSMEN - description: ADC clocks enable during CPU1 Csleep and CStop modes - bit_offset: 9 - bit_size: 1 - - name: TIM1SMEN - description: TIM1 timer clock enable during CPU1 CSleep mode. - bit_offset: 11 - bit_size: 1 - - name: SPI1SMEN - description: SPI1 clock enable during CPU1 CSleep mode. - bit_offset: 12 - bit_size: 1 - - name: USART1SMEN - description: USART1 clock enable during CPU1 Csleep and CStop modes. - bit_offset: 14 - bit_size: 1 - - name: TIM16SMEN - description: TIM16 timer clock enable during CPU1 CSleep mode. - bit_offset: 17 - bit_size: 1 - - name: TIM17SMEN - description: TIM17 timer clock enable during CPU1 CSleep mode. - bit_offset: 18 - bit_size: 1 + - name: ADCSMEN + description: ADC clocks enable during CPU1 Csleep and CStop modes + bit_offset: 9 + bit_size: 1 + - name: TIM1SMEN + description: TIM1 timer clock enable during CPU1 CSleep mode. + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: SPI1 clock enable during CPU1 CSleep mode. + bit_offset: 12 + bit_size: 1 + - name: USART1SMEN + description: USART1 clock enable during CPU1 Csleep and CStop modes. + bit_offset: 14 + bit_size: 1 + - name: TIM16SMEN + description: TIM16 timer clock enable during CPU1 CSleep mode. + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: TIM17 timer clock enable during CPU1 CSleep mode. + bit_offset: 18 + bit_size: 1 fieldset/APB3ENR: description: APB3 peripheral clock enable register fields: - - name: SUBGHZSPIEN - description: sub-GHz radio SPI clock enable - bit_offset: 0 - bit_size: 1 + - name: SUBGHZSPIEN + description: sub-GHz radio SPI clock enable + bit_offset: 0 + bit_size: 1 fieldset/APB3RSTR: description: APB3 peripheral reset register fields: - - name: SUBGHZSPIRST - description: Sub-GHz radio SPI reset - bit_offset: 0 - bit_size: 1 + - name: SUBGHZSPIRST + description: Sub-GHz radio SPI reset + bit_offset: 0 + bit_size: 1 fieldset/APB3SMENR: description: APB3 peripheral clock enable in Sleep mode register fields: - - name: SUBGHZSPISMEN - description: Sub-GHz radio SPI clock enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 + - name: SUBGHZSPISMEN + description: Sub-GHz radio SPI clock enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 fieldset/BDCR: description: Backup domain control register fields: - - name: LSEON - description: LSE oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: LSE oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: LSE oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: LSEDRV - description: LSE oscillator drive capability - bit_offset: 3 - bit_size: 2 - - name: LSECSSON - description: CSS on LSE enable - bit_offset: 5 - bit_size: 1 - - name: LSECSSD - description: CSS on LSE failure Detection - bit_offset: 6 - bit_size: 1 - - name: LSESYSEN - description: LSE system clock enable - bit_offset: 7 - bit_size: 1 - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - - name: LSESYSRDY - description: LSE system clock ready - bit_offset: 11 - bit_size: 1 - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: Backup domain software reset - bit_offset: 16 - bit_size: 1 - - name: LSCOEN - description: Low speed clock output enable - bit_offset: 24 - bit_size: 1 - - name: LSCOSEL - description: Low speed clock output selection - bit_offset: 25 - bit_size: 1 + - name: LSEON + description: LSE oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: LSE oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: LSE oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: LSE oscillator drive capability + bit_offset: 3 + bit_size: 2 + - name: LSECSSON + description: CSS on LSE enable + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: CSS on LSE failure Detection + bit_offset: 6 + bit_size: 1 + - name: LSESYSEN + description: LSE system clock enable + bit_offset: 7 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: LSESYSRDY + description: LSE system clock ready + bit_offset: 11 + bit_size: 1 + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: Low speed clock output enable + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: Low speed clock output selection + bit_offset: 25 + bit_size: 1 fieldset/C2AHB1ENR: description: CPU2 AHB1 peripheral clock enable register fields: - - name: DMA1EN - description: CPU2 DMA1 clock enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: CPU2 DMA2 clock enable - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1EN - description: CPU2 DMAMUX1 clock enable - bit_offset: 2 - bit_size: 1 - - name: CRCEN - description: CPU2 CRC clock enable - bit_offset: 12 - bit_size: 1 + - name: DMA1EN + description: CPU2 DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: CPU2 DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1EN + description: CPU2 DMAMUX1 clock enable + bit_offset: 2 + bit_size: 1 + - name: CRCEN + description: CPU2 CRC clock enable + bit_offset: 12 + bit_size: 1 fieldset/C2AHB1SMENR: - description: "CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only]" + description: CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only] fields: - - name: DMA1SMEN - description: DMA1 clock enable during CPU2 CSleep mode. - bit_offset: 0 - bit_size: 1 - - name: DMA2SMEN - description: DMA2 clock enable during CPU2 CSleep mode. - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1SMEN - description: DMAMUX1 clock enable during CPU2 CSleep mode. - bit_offset: 2 - bit_size: 1 - - name: CRCSMEN - description: CRC clock enable during CPU2 CSleep mode. - bit_offset: 12 - bit_size: 1 + - name: DMA1SMEN + description: DMA1 clock enable during CPU2 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: DMA2SMEN + description: DMA2 clock enable during CPU2 CSleep mode. + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1SMEN + description: DMAMUX1 clock enable during CPU2 CSleep mode. + bit_offset: 2 + bit_size: 1 + - name: CRCSMEN + description: CRC clock enable during CPU2 CSleep mode. + bit_offset: 12 + bit_size: 1 fieldset/C2AHB2ENR: description: CPU2 AHB2 peripheral clock enable register fields: - - name: GPIOAEN - description: CPU2 IO port A clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: CPU2 IO port B clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: CPU2 IO port C clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIOHEN - description: CPU2 IO port H clock enable - bit_offset: 7 - bit_size: 1 + - name: GPIOAEN + description: CPU2 IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: CPU2 IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: CPU2 IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIOHEN + description: CPU2 IO port H clock enable + bit_offset: 7 + bit_size: 1 fieldset/C2AHB2SMENR: - description: "CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only]" + description: CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only] fields: - - name: GPIOASMEN - description: IO port A clock enable during CPU2 CSleep mode. - bit_offset: 0 - bit_size: 1 - - name: GPIOBSMEN - description: IO port B clock enable during CPU2 CSleep mode. - bit_offset: 1 - bit_size: 1 - - name: GPIOCSMEN - description: IO port C clock enable during CPU2 CSleep mode. - bit_offset: 2 - bit_size: 1 - - name: GPIOHSMEN - description: IO port H clock enable during CPU2 CSleep mode. - bit_offset: 7 - bit_size: 1 + - name: GPIOASMEN + description: IO port A clock enable during CPU2 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: IO port B clock enable during CPU2 CSleep mode. + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: IO port C clock enable during CPU2 CSleep mode. + bit_offset: 2 + bit_size: 1 + - name: GPIOHSMEN + description: IO port H clock enable during CPU2 CSleep mode. + bit_offset: 7 + bit_size: 1 fieldset/C2AHB3ENR: - description: "CPU2 AHB3 peripheral clock enable register [dual core device only]" + description: CPU2 AHB3 peripheral clock enable register [dual core device only] fields: - - name: PKAEN - description: CPU2 PKA accelerator clock enable - bit_offset: 16 - bit_size: 1 - - name: AESEN - description: CPU2 AES accelerator clock enable - bit_offset: 17 - bit_size: 1 - - name: RNGEN - description: CPU2 True RNG clocks enable - bit_offset: 18 - bit_size: 1 - - name: HSEMEN - description: CPU2 HSEM clock enable - bit_offset: 19 - bit_size: 1 - - name: IPCCEN - description: CPU2 IPCC interface clock enable - bit_offset: 20 - bit_size: 1 - - name: FLASHEN - description: CPU2 Flash interface clock enable - bit_offset: 25 - bit_size: 1 + - name: PKAEN + description: CPU2 PKA accelerator clock enable + bit_offset: 16 + bit_size: 1 + - name: AESEN + description: CPU2 AES accelerator clock enable + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: CPU2 True RNG clocks enable + bit_offset: 18 + bit_size: 1 + - name: HSEMEN + description: CPU2 HSEM clock enable + bit_offset: 19 + bit_size: 1 + - name: IPCCEN + description: CPU2 IPCC interface clock enable + bit_offset: 20 + bit_size: 1 + - name: FLASHEN + description: CPU2 Flash interface clock enable + bit_offset: 25 + bit_size: 1 fieldset/C2AHB3SMENR: - description: "CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only]" + description: CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only] fields: - - name: PKASMEN - description: PKA accelerator clock enable during CPU2 CSleep mode. - bit_offset: 16 - bit_size: 1 - - name: AESSMEN - description: AES accelerator clock enable during CPU2 CSleep mode. - bit_offset: 17 - bit_size: 1 - - name: RNGSMEN - description: True RNG clock enable during CPU2 CSleep and CStop mode. - bit_offset: 18 - bit_size: 1 - - name: SRAM1SMEN - description: SRAM1 interface clock enable during CPU2 CSleep mode. - bit_offset: 23 - bit_size: 1 - - name: SRAM2SMEN - description: SRAM2 memory interface clock enable during CPU2 CSleep mode. - bit_offset: 24 - bit_size: 1 - - name: FLASHSMEN - description: Flash interface clock enable during CPU2 CSleep mode. - bit_offset: 25 - bit_size: 1 + - name: PKASMEN + description: PKA accelerator clock enable during CPU2 CSleep mode. + bit_offset: 16 + bit_size: 1 + - name: AESSMEN + description: AES accelerator clock enable during CPU2 CSleep mode. + bit_offset: 17 + bit_size: 1 + - name: RNGSMEN + description: True RNG clock enable during CPU2 CSleep and CStop mode. + bit_offset: 18 + bit_size: 1 + - name: SRAM1SMEN + description: SRAM1 interface clock enable during CPU2 CSleep mode. + bit_offset: 23 + bit_size: 1 + - name: SRAM2SMEN + description: SRAM2 memory interface clock enable during CPU2 CSleep mode. + bit_offset: 24 + bit_size: 1 + - name: FLASHSMEN + description: Flash interface clock enable during CPU2 CSleep mode. + bit_offset: 25 + bit_size: 1 fieldset/C2APB1ENR1: - description: "CPU2 APB1 peripheral clock enable register 1 [dual core device only]" + description: CPU2 APB1 peripheral clock enable register 1 [dual core device only] fields: - - name: TIM2EN - description: CPU2 TIM2 timer clock enable - bit_offset: 0 - bit_size: 1 - - name: RTCAPBEN - description: CPU2 RTC APB clock enable - bit_offset: 10 - bit_size: 1 - - name: SPI2EN - description: CPU2 SPI2 clock enable - bit_offset: 14 - bit_size: 1 - - name: USART2EN - description: CPU2 USART2 clock enable - bit_offset: 17 - bit_size: 1 - - name: I2C1EN - description: CPU2 I2C1 clocks enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: CPU2 I2C2 clocks enable - bit_offset: 22 - bit_size: 1 - - name: I2C3EN - description: CPU2 I2C3 clocks enable - bit_offset: 23 - bit_size: 1 - - name: DAC1EN - description: CPU2 DAC1 clock enable - bit_offset: 29 - bit_size: 1 - - name: LPTIM1EN - description: CPU2 Low power timer 1 clocks enable - bit_offset: 31 - bit_size: 1 + - name: TIM2EN + description: CPU2 TIM2 timer clock enable + bit_offset: 0 + bit_size: 1 + - name: RTCAPBEN + description: CPU2 RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: SPI2EN + description: CPU2 SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: USART2EN + description: CPU2 USART2 clock enable + bit_offset: 17 + bit_size: 1 + - name: I2C1EN + description: CPU2 I2C1 clocks enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: CPU2 I2C2 clocks enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: CPU2 I2C3 clocks enable + bit_offset: 23 + bit_size: 1 + - name: DAC1EN + description: CPU2 DAC1 clock enable + bit_offset: 29 + bit_size: 1 + - name: LPTIM1EN + description: CPU2 Low power timer 1 clocks enable + bit_offset: 31 + bit_size: 1 fieldset/C2APB1ENR2: - description: "CPU2 APB1 peripheral clock enable register 2 [dual core device only]" + description: CPU2 APB1 peripheral clock enable register 2 [dual core device only] fields: - - name: LPUART1EN - description: CPU2 Low power UART 1 clocks enable - bit_offset: 0 - bit_size: 1 - - name: LPTIM2EN - description: CPU2 Low power timer 2 clocks enable - bit_offset: 5 - bit_size: 1 - - name: LPTIM3EN - description: CPU2 Low power timer 3 clocks enable - bit_offset: 6 - bit_size: 1 + - name: LPUART1EN + description: CPU2 Low power UART 1 clocks enable + bit_offset: 0 + bit_size: 1 + - name: LPTIM2EN + description: CPU2 Low power timer 2 clocks enable + bit_offset: 5 + bit_size: 1 + - name: LPTIM3EN + description: CPU2 Low power timer 3 clocks enable + bit_offset: 6 + bit_size: 1 fieldset/C2APB1SMENR1: - description: "CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only]" + description: CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only] fields: - - name: TIM2SMEN - description: TIM2 timer clock enable during CPU2 CSleep mode. - bit_offset: 0 - bit_size: 1 - - name: RTCAPBSMEN - description: RTC bus clock enable during CPU2 CSleep mode. - bit_offset: 10 - bit_size: 1 - - name: SPI2SMEN - description: SPI2 clock enable during CPU2 CSleep mode. - bit_offset: 14 - bit_size: 1 - - name: USART2SMEN - description: USART2 clock enable during CPU2 CSleep mode. - bit_offset: 17 - bit_size: 1 - - name: I2C1SMEN - description: I2C1 clock enable during CPU2 CSleep and CStop modes - bit_offset: 21 - bit_size: 1 - - name: I2C2SMEN - description: I2C2 clock enable during CPU2 CSleep and CStop modes - bit_offset: 22 - bit_size: 1 - - name: I2C3SMEN - description: I2C3 clock enable during CPU2 CSleep and CStop modes - bit_offset: 23 - bit_size: 1 - - name: DAC1SMEN - description: DAC1 clock enable during CPU2 CSleep mode. - bit_offset: 29 - bit_size: 1 - - name: LPTIM1SMEN - description: Low power timer 1 clock enable during CPU2 CSleep and CStop mode - bit_offset: 31 - bit_size: 1 + - name: TIM2SMEN + description: TIM2 timer clock enable during CPU2 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: RTCAPBSMEN + description: RTC bus clock enable during CPU2 CSleep mode. + bit_offset: 10 + bit_size: 1 + - name: SPI2SMEN + description: SPI2 clock enable during CPU2 CSleep mode. + bit_offset: 14 + bit_size: 1 + - name: USART2SMEN + description: USART2 clock enable during CPU2 CSleep mode. + bit_offset: 17 + bit_size: 1 + - name: I2C1SMEN + description: I2C1 clock enable during CPU2 CSleep and CStop modes + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: I2C2 clock enable during CPU2 CSleep and CStop modes + bit_offset: 22 + bit_size: 1 + - name: I2C3SMEN + description: I2C3 clock enable during CPU2 CSleep and CStop modes + bit_offset: 23 + bit_size: 1 + - name: DAC1SMEN + description: DAC1 clock enable during CPU2 CSleep mode. + bit_offset: 29 + bit_size: 1 + - name: LPTIM1SMEN + description: Low power timer 1 clock enable during CPU2 CSleep and CStop mode + bit_offset: 31 + bit_size: 1 fieldset/C2APB1SMENR2: - description: "CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only]" + description: CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only] fields: - - name: LPUART1SMEN - description: Low power UART 1 clock enable during CPU2 CSleep and CStop mode - bit_offset: 0 - bit_size: 1 - - name: LPTIM2SMEN - description: Low power timer 2 clocks enable during CPU2 CSleep and CStop modes. - bit_offset: 5 - bit_size: 1 - - name: LPTIM3SMEN - description: Low power timer 3 clocks enable during CPU2 CSleep and CStop modes. - bit_offset: 6 - bit_size: 1 + - name: LPUART1SMEN + description: Low power UART 1 clock enable during CPU2 CSleep and CStop mode + bit_offset: 0 + bit_size: 1 + - name: LPTIM2SMEN + description: Low power timer 2 clocks enable during CPU2 CSleep and CStop modes. + bit_offset: 5 + bit_size: 1 + - name: LPTIM3SMEN + description: Low power timer 3 clocks enable during CPU2 CSleep and CStop modes. + bit_offset: 6 + bit_size: 1 fieldset/C2APB2ENR: - description: "CPU2 APB2 peripheral clock enable register [dual core device only]" + description: CPU2 APB2 peripheral clock enable register [dual core device only] fields: - - name: ADCEN - description: ADC clocks enable - bit_offset: 9 - bit_size: 1 - - name: TIM1EN - description: CPU2 TIM1 timer clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: CPU2 SPI1 clock enable - bit_offset: 12 - bit_size: 1 - - name: USART1EN - description: CPU2 USART1clocks enable - bit_offset: 14 - bit_size: 1 - - name: TIM16EN - description: CPU2 TIM16 timer clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: CPU2 TIM17 timer clock enable - bit_offset: 18 - bit_size: 1 + - name: ADCEN + description: ADC clocks enable + bit_offset: 9 + bit_size: 1 + - name: TIM1EN + description: CPU2 TIM1 timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: CPU2 SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: CPU2 USART1clocks enable + bit_offset: 14 + bit_size: 1 + - name: TIM16EN + description: CPU2 TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: CPU2 TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 fieldset/C2APB2SMENR: - description: "CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only]" + description: CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only] fields: - - name: ADCSMEN - description: ADC clocks enable during CPU2 Csleep and CStop modes - bit_offset: 9 - bit_size: 1 - - name: TIM1SMEN - description: TIM1 timer clock enable during CPU2 CSleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI1SMEN - description: SPI1 clock enable during CPU2 CSleep mode - bit_offset: 12 - bit_size: 1 - - name: USART1SMEN - description: USART1clock enable during CPU2 CSleep and CStop mode - bit_offset: 14 - bit_size: 1 - - name: TIM16SMEN - description: TIM16 timer clock enable during CPU2 CSleep mode - bit_offset: 17 - bit_size: 1 - - name: TIM17SMEN - description: TIM17 timer clock enable during CPU2 CSleep mode - bit_offset: 18 - bit_size: 1 + - name: ADCSMEN + description: ADC clocks enable during CPU2 Csleep and CStop modes + bit_offset: 9 + bit_size: 1 + - name: TIM1SMEN + description: TIM1 timer clock enable during CPU2 CSleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: SPI1 clock enable during CPU2 CSleep mode + bit_offset: 12 + bit_size: 1 + - name: USART1SMEN + description: USART1clock enable during CPU2 CSleep and CStop mode + bit_offset: 14 + bit_size: 1 + - name: TIM16SMEN + description: TIM16 timer clock enable during CPU2 CSleep mode + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: TIM17 timer clock enable during CPU2 CSleep mode + bit_offset: 18 + bit_size: 1 fieldset/C2APB3ENR: - description: "CPU2 APB3 peripheral clock enable register [dual core device only]" + description: CPU2 APB3 peripheral clock enable register [dual core device only] fields: - - name: SUBGHZSPIEN - description: CPU2 sub-GHz radio SPI clock enable - bit_offset: 0 - bit_size: 1 + - name: SUBGHZSPIEN + description: CPU2 sub-GHz radio SPI clock enable + bit_offset: 0 + bit_size: 1 fieldset/C2APB3SMENR: - description: "CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only]" + description: CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only] fields: - - name: SUBGHZSPISMEN - description: sub-GHz radio SPI clock enable during CPU2 CSleep and CStop modes - bit_offset: 0 - bit_size: 1 + - name: SUBGHZSPISMEN + description: sub-GHz radio SPI clock enable during CPU2 CSleep and CStop modes + bit_offset: 0 + bit_size: 1 fieldset/CCIPR: description: Peripherals independent clock configuration register fields: - - name: USART1SEL - description: USART1 clock source selection - bit_offset: 0 - bit_size: 2 - - name: USART2SEL - description: USART2 clock source selection - bit_offset: 2 - bit_size: 2 - - name: SPI2SEL - description: SPI2 I2S clock source selection - bit_offset: 8 - bit_size: 2 - - name: LPUART1SEL - description: LPUART1 clock source selection - bit_offset: 10 - bit_size: 2 - - name: I2C1SEL - description: I2C1 clock source selection - bit_offset: 12 - bit_size: 2 - - name: I2C2SEL - description: I2C2 clock source selection - bit_offset: 14 - bit_size: 2 - - name: I2C3SEL - description: I2C3 clock source selection - bit_offset: 16 - bit_size: 2 - - name: LPTIM1SEL - description: Low power timer 1 clock source selection - bit_offset: 18 - bit_size: 2 - - name: LPTIM2SEL - description: Low power timer 2 clock source selection - bit_offset: 20 - bit_size: 2 - - name: LPTIM3SEL - description: Low power timer 3 clock source selection - bit_offset: 22 - bit_size: 2 - - name: ADCSEL - description: ADC clock source selection - bit_offset: 28 - bit_size: 2 - - name: RNGSEL - description: RNG clock source selection - bit_offset: 30 - bit_size: 2 + - name: USART1SEL + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + - name: USART2SEL + description: USART2 clock source selection + bit_offset: 2 + bit_size: 2 + - name: SPI2SEL + description: SPI2 I2S clock source selection + bit_offset: 8 + bit_size: 2 + - name: LPUART1SEL + description: LPUART1 clock source selection + bit_offset: 10 + bit_size: 2 + - name: I2C1SEL + description: I2C1 clock source selection + bit_offset: 12 + bit_size: 2 + - name: I2C2SEL + description: I2C2 clock source selection + bit_offset: 14 + bit_size: 2 + - name: I2C3SEL + description: I2C3 clock source selection + bit_offset: 16 + bit_size: 2 + - name: LPTIM1SEL + description: Low power timer 1 clock source selection + bit_offset: 18 + bit_size: 2 + - name: LPTIM2SEL + description: Low power timer 2 clock source selection + bit_offset: 20 + bit_size: 2 + - name: LPTIM3SEL + description: Low power timer 3 clock source selection + bit_offset: 22 + bit_size: 2 + - name: ADCSEL + description: ADC clock source selection + bit_offset: 28 + bit_size: 2 + enum: ADCSEL + - name: RNGSEL + description: RNG clock source selection + bit_offset: 30 + bit_size: 2 fieldset/CFGR: description: Clock configuration register fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 2 - - name: SWS - description: System clock switch status - bit_offset: 2 - bit_size: 2 - - name: HPRE - description: "HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)" - bit_offset: 4 - bit_size: 4 - - name: PPRE1 - description: PCLK1 low-speed prescaler (APB1) - bit_offset: 8 - bit_size: 3 - - name: PPRE2 - description: PCLK2 high-speed prescaler (APB2) - bit_offset: 11 - bit_size: 3 - - name: STOPWUCK - description: Wakeup from Stop and CSS backup clock selection - bit_offset: 15 - bit_size: 1 - - name: HPREF - description: "HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1)" - bit_offset: 16 - bit_size: 1 - - name: PPRE1F - description: PCLK1 prescaler flag (APB1) - bit_offset: 17 - bit_size: 1 - - name: PPRE2F - description: PCLK2 prescaler flag (APB2) - bit_offset: 18 - bit_size: 1 - - name: MCOSEL - description: Microcontroller clock output - bit_offset: 24 - bit_size: 4 - - name: MCOPRE - description: Microcontroller clock output prescaler - bit_offset: 28 - bit_size: 3 + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + - name: HPRE + description: HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.) + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: PCLK1 low-speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: PCLK2 high-speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: STOPWUCK + description: Wakeup from Stop and CSS backup clock selection + bit_offset: 15 + bit_size: 1 + - name: HPREF + description: HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1) + bit_offset: 16 + bit_size: 1 + - name: PPRE1F + description: PCLK1 prescaler flag (APB1) + bit_offset: 17 + bit_size: 1 + - name: PPRE2F + description: PCLK2 prescaler flag (APB2) + bit_offset: 18 + bit_size: 1 + - name: MCOSEL + description: Microcontroller clock output + bit_offset: 24 + bit_size: 4 + enum: MCOSEL + - name: MCOPRE + description: Microcontroller clock output prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: - - name: LSIRDYC - description: LSI ready interrupt clear - bit_offset: 0 - bit_size: 1 - - name: LSERDYC - description: LSE ready interrupt clear - bit_offset: 1 - bit_size: 1 - - name: MSIRDYC - description: MSI ready interrupt clear - bit_offset: 2 - bit_size: 1 - - name: HSIRDYC - description: HSI16 ready interrupt clear - bit_offset: 3 - bit_size: 1 - - name: HSERDYC - description: HSE32 ready interrupt clear - bit_offset: 4 - bit_size: 1 - - name: PLLRDYC - description: PLL ready interrupt clear - bit_offset: 5 - bit_size: 1 - - name: CSSC - description: HSE32 Clock security system interrupt clear - bit_offset: 8 - bit_size: 1 - - name: LSECSSC - description: LSE Clock security system interrupt clear - bit_offset: 9 - bit_size: 1 + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 1 + bit_size: 1 + - name: MSIRDYC + description: MSI ready interrupt clear + bit_offset: 2 + bit_size: 1 + - name: HSIRDYC + description: HSI16 ready interrupt clear + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: HSE32 ready interrupt clear + bit_offset: 4 + bit_size: 1 + - name: PLLRDYC + description: PLL ready interrupt clear + bit_offset: 5 + bit_size: 1 + - name: CSSC + description: HSE32 Clock security system interrupt clear + bit_offset: 8 + bit_size: 1 + - name: LSECSSC + description: LSE Clock security system interrupt clear + bit_offset: 9 + bit_size: 1 fieldset/CIER: description: Clock interrupt enable register fields: - - name: LSIRDYIE - description: LSI ready interrupt enable - bit_offset: 0 - bit_size: 1 - - name: LSERDYIE - description: LSE ready interrupt enable - bit_offset: 1 - bit_size: 1 - - name: MSIRDYIE - description: MSI ready interrupt enable - bit_offset: 2 - bit_size: 1 - - name: HSIRDYIE - description: HSI16 ready interrupt enable - bit_offset: 3 - bit_size: 1 - - name: HSERDYIE - description: HSE32 ready interrupt enable - bit_offset: 4 - bit_size: 1 - - name: PLLRDYIE - description: PLL ready interrupt enable - bit_offset: 5 - bit_size: 1 - - name: LSECSSIE - description: LSE clock security system interrupt enable - bit_offset: 9 - bit_size: 1 + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 1 + bit_size: 1 + - name: MSIRDYIE + description: MSI ready interrupt enable + bit_offset: 2 + bit_size: 1 + - name: HSIRDYIE + description: HSI16 ready interrupt enable + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: HSE32 ready interrupt enable + bit_offset: 4 + bit_size: 1 + - name: PLLRDYIE + description: PLL ready interrupt enable + bit_offset: 5 + bit_size: 1 + - name: LSECSSIE + description: LSE clock security system interrupt enable + bit_offset: 9 + bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register fields: - - name: LSIRDYF - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - - name: MSIRDYF - description: MSI ready interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSIRDYF - description: HSI16 ready interrupt flag - bit_offset: 3 - bit_size: 1 - - name: HSERDYF - description: HSE32 ready interrupt flag - bit_offset: 4 - bit_size: 1 - - name: PLLRDYF - description: PLL ready interrupt flag - bit_offset: 5 - bit_size: 1 - - name: CSSF - description: HSE32 Clock security system interrupt flag - bit_offset: 8 - bit_size: 1 - - name: LSECSSF - description: LSE Clock security system interrupt flag - bit_offset: 9 - bit_size: 1 + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: MSIRDYF + description: MSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSIRDYF + description: HSI16 ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: HSE32 ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLLRDYF + description: PLL ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: CSSF + description: HSE32 Clock security system interrupt flag + bit_offset: 8 + bit_size: 1 + - name: LSECSSF + description: LSE Clock security system interrupt flag + bit_offset: 9 + bit_size: 1 fieldset/CR: description: Clock control register fields: - - name: MSION - description: MSI clock enable - bit_offset: 0 - bit_size: 1 - - name: MSIRDY - description: MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready) - bit_offset: 1 - bit_size: 1 - - name: MSIPLLEN - description: MSI clock PLL enable - bit_offset: 2 - bit_size: 1 - - name: MSIRGSEL - description: MSI range control selection - bit_offset: 3 - bit_size: 1 - - name: MSIRANGE - description: MSI clock ranges - bit_offset: 4 - bit_size: 4 - - name: HSION - description: HSI16 clock enable - bit_offset: 8 - bit_size: 1 - - name: HSIKERON - description: HSI16 always enable for peripheral kernel clocks. - bit_offset: 9 - bit_size: 1 - - name: HSIRDY - description: HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready) - bit_offset: 10 - bit_size: 1 - - name: HSIASFS - description: HSI16 automatic start from Stop - bit_offset: 11 - bit_size: 1 - - name: HSIKERDY - description: HSI16 kernel clock ready flag for peripherals requests. - bit_offset: 12 - bit_size: 1 - - name: HSEON - description: HSE32 clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: HSE32 clock ready flag - bit_offset: 17 - bit_size: 1 - - name: CSSON - description: HSE32 Clock security system enable - bit_offset: 19 - bit_size: 1 - - name: HSEPRE - description: HSE32 sysclk prescaler - bit_offset: 20 - bit_size: 1 - - name: HSEBYPPWR - description: Enable HSE32 VDDTCXO output on package pin PB0-VDDTCXO. - bit_offset: 21 - bit_size: 1 - - name: PLLON - description: Main PLL enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: Main PLL clock ready flag - bit_offset: 25 - bit_size: 1 + - name: MSION + description: MSI clock enable + bit_offset: 0 + bit_size: 1 + - name: MSIRDY + description: MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready) + bit_offset: 1 + bit_size: 1 + - name: MSIPLLEN + description: MSI clock PLL enable + bit_offset: 2 + bit_size: 1 + - name: MSIRGSEL + description: MSI range control selection + bit_offset: 3 + bit_size: 1 + - name: MSIRANGE + description: MSI clock ranges + bit_offset: 4 + bit_size: 4 + - name: HSION + description: HSI16 clock enable + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: HSI16 always enable for peripheral kernel clocks. + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready) + bit_offset: 10 + bit_size: 1 + - name: HSIASFS + description: HSI16 automatic start from Stop + bit_offset: 11 + bit_size: 1 + - name: HSIKERDY + description: HSI16 kernel clock ready flag for peripherals requests. + bit_offset: 12 + bit_size: 1 + - name: HSEON + description: HSE32 clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE32 clock ready flag + bit_offset: 17 + bit_size: 1 + - name: CSSON + description: HSE32 Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: HSEPRE + description: HSE32 sysclk prescaler + bit_offset: 20 + bit_size: 1 + - name: HSEBYPPWR + description: Enable HSE32 VDDTCXO output on package pin PB0-VDDTCXO. + bit_offset: 21 + bit_size: 1 + - name: PLLON + description: Main PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL clock ready flag + bit_offset: 25 + bit_size: 1 fieldset/CSR: description: Control/status register fields: - - name: LSION - description: LSI oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: LSI oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSIPRE - description: LSI frequency prescaler - bit_offset: 4 - bit_size: 1 - - name: MSISRANGE - description: MSI clock ranges - bit_offset: 8 - bit_size: 4 - - name: RFRSTF - description: Radio in reset status flag - bit_offset: 14 - bit_size: 1 - - name: RFRST - description: Radio reset - bit_offset: 15 - bit_size: 1 - - name: RMVF - description: Remove reset flag - bit_offset: 23 - bit_size: 1 - - name: RFILARSTF - description: Radio illegal access flag - bit_offset: 24 - bit_size: 1 - - name: OBLRSTF - description: Option byte loader reset flag - bit_offset: 25 - bit_size: 1 - - name: PINRSTF - description: Pin reset flag - bit_offset: 26 - bit_size: 1 - - name: BORRSTF - description: BOR flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: Independent window watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSION + description: LSI oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: LSI oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSIPRE + description: LSI frequency prescaler + bit_offset: 4 + bit_size: 1 + - name: MSISRANGE + description: MSI clock ranges + bit_offset: 8 + bit_size: 4 + - name: RFRSTF + description: Radio in reset status flag + bit_offset: 14 + bit_size: 1 + - name: RFRST + description: Radio reset + bit_offset: 15 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 23 + bit_size: 1 + - name: RFILARSTF + description: Radio illegal access flag + bit_offset: 24 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: Pin reset flag + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: BOR flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent window watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 fieldset/EXTCFGR: description: Extended clock recovery register fields: - - name: SHDHPRE - description: "HCLK3 shared prescaler (AHB3, Flash, and SRAM2)" - bit_offset: 0 - bit_size: 4 - - name: C2HPRE - description: "[dual core device only] HCLK2 prescaler (CPU2)" - bit_offset: 4 - bit_size: 4 - - name: SHDHPREF - description: "HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2)" - bit_offset: 16 - bit_size: 1 - - name: C2HPREF - description: CLK2 prescaler flag (CPU2) - bit_offset: 17 - bit_size: 1 + - name: SHDHPRE + description: HCLK3 shared prescaler (AHB3, Flash, and SRAM2) + bit_offset: 0 + bit_size: 4 + - name: C2HPRE + description: '[dual core device only] HCLK2 prescaler (CPU2)' + bit_offset: 4 + bit_size: 4 + - name: SHDHPREF + description: HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2) + bit_offset: 16 + bit_size: 1 + - name: C2HPREF + description: CLK2 prescaler flag (CPU2) + bit_offset: 17 + bit_size: 1 fieldset/ICSCR: description: Internal clock sources calibration register fields: - - name: MSICAL - description: MSI clock calibration - bit_offset: 0 - bit_size: 8 - - name: MSITRIM - description: MSI clock trimming - bit_offset: 8 - bit_size: 8 - - name: HSICAL - description: HSI16 clock calibration - bit_offset: 16 - bit_size: 8 - - name: HSITRIM - description: HSI16 clock trimming - bit_offset: 24 - bit_size: 7 + - name: MSICAL + description: MSI clock calibration + bit_offset: 0 + bit_size: 8 + - name: MSITRIM + description: MSI clock trimming + bit_offset: 8 + bit_size: 8 + - name: HSICAL + description: HSI16 clock calibration + bit_offset: 16 + bit_size: 8 + - name: HSITRIM + description: HSI16 clock trimming + bit_offset: 24 + bit_size: 7 fieldset/PLLCFGR: description: PLL configuration register fields: - - name: PLLSRC - description: Main PLL entry clock source - bit_offset: 0 - bit_size: 2 - - name: PLLM - description: Division factor for the main PLL input clock - bit_offset: 4 - bit_size: 3 - - name: PLLN - description: Main PLL multiplication factor for VCO - bit_offset: 8 - bit_size: 7 - - name: PLLPEN - description: Main PLL PLLPCLK output enable - bit_offset: 16 - bit_size: 1 - - name: PLLP - description: Main PLL division factor for PLLPCLK. - bit_offset: 17 - bit_size: 5 - - name: PLLQEN - description: Main PLL PLLQCLK output enable - bit_offset: 24 - bit_size: 1 - - name: PLLQ - description: Main PLL division factor for PLLQCLK - bit_offset: 25 - bit_size: 3 - - name: PLLREN - description: Main PLL PLLRCLK output enable - bit_offset: 28 - bit_size: 1 - - name: PLLR - description: Main PLL division factor for PLLRCLK - bit_offset: 29 - bit_size: 3 + - name: PLLSRC + description: Main PLL entry clock source + bit_offset: 0 + bit_size: 2 + - name: PLLM + description: Division factor for the main PLL input clock + bit_offset: 4 + bit_size: 3 + - name: PLLN + description: Main PLL multiplication factor for VCO + bit_offset: 8 + bit_size: 7 + - name: PLLPEN + description: Main PLL PLLPCLK output enable + bit_offset: 16 + bit_size: 1 + - name: PLLP + description: Main PLL division factor for PLLPCLK. + bit_offset: 17 + bit_size: 5 + - name: PLLQEN + description: Main PLL PLLQCLK output enable + bit_offset: 24 + bit_size: 1 + - name: PLLQ + description: Main PLL division factor for PLLQCLK + bit_offset: 25 + bit_size: 3 + - name: PLLREN + description: Main PLL PLLRCLK output enable + bit_offset: 28 + bit_size: 1 + - name: PLLR + description: Main PLL division factor for PLLRCLK + bit_offset: 29 + bit_size: 3 +enum/ADCSEL: + bit_size: 2 + variants: + - name: HSI16 + description: HSI16 used as ADC clock source + value: 1 + - name: PLLPCLK + description: PLLPCLK used as ADC clock source + value: 2 + - name: SYSCLK + description: SYSCLK used as ADC clock source + value: 3 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: DCLK not divided + value: 0 + - name: Div3 + description: hclk = SYSCLK divided by 3 + value: 1 + - name: Div5 + description: hclk = SYSCLK divided by 5 + value: 2 + - name: Div6 + description: hclk = SYSCLK divided by 6 + value: 5 + - name: Div10 + description: hclk = SYSCLK divided by 8 + value: 6 + - name: Div32 + description: hclk = SYSCLK divided by 32 + value: 7 + - name: Div2 + description: hclk = SYSCLK divided by 2 + value: 8 + - name: Div4 + description: hclk = SYSCLK divided by 4 + value: 9 + - name: Div8 + description: hclk = SYSCLK divided by 8 + value: 10 + - name: Div16 + description: hclk = SYSCLK divided by 16 + value: 11 + - name: Div64 + description: hclk = SYSCLK divided by 64 + value: 12 + - name: Div128 + description: hclk = SYSCLK divided by 128 + value: 13 + - name: Div256 + description: hclk = SYSCLK divided by 256 + value: 14 + - name: Div512 + description: hclk = SYSCLK divided by 256 + value: 15 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 + - name: Div16 + description: Division by 16 + value: 4 +enum/MCOSEL: + bit_size: 4 + variants: + - name: NoClock + description: No clock + value: 0 + - name: SYSCLK + description: SYSCLK clock selected + value: 1 + - name: MSI + description: MSI oscillator clock selected + value: 2 + - name: HSI16 + description: HSI oscillator clock selected + value: 3 + - name: HSE32 + description: HSE32 oscillator clock selected + value: 4 + - name: PLLRCLK + description: Main PLLRCLK clock selected + value: 5 + - name: LSI + description: LSI oscillator clock selected + value: 6 + - name: LSE + description: LSE oscillator clock selected + value: 8 + - name: PLLPCLK + description: Main PLLCLK oscillator clock selected + value: 13 + - name: PLLQCLK + description: Main PLLQCLK oscillator clock selected + value: 14 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock selected + value: 0 + - name: LSE + description: LSE oscillator clock selected + value: 1 + - name: LSI + description: LSI oscillator clock selected + value: 2 + - name: HSE + description: HSE oscillator clock divided by 32 selected + value: 3 diff --git a/data/registers/rcc_wle.yaml b/data/registers/rcc_wle.yaml index c130d96..17d34f8 100644 --- a/data/registers/rcc_wle.yaml +++ b/data/registers/rcc_wle.yaml @@ -1,1046 +1,1193 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: Clock control register - byte_offset: 0 - fieldset: CR - - name: ICSCR - description: Internal clock sources calibration register - byte_offset: 4 - fieldset: ICSCR - - name: CFGR - description: Clock configuration register - byte_offset: 8 - fieldset: CFGR - - name: PLLCFGR - description: PLL configuration register - byte_offset: 12 - fieldset: PLLCFGR - - name: CIER - description: Clock interrupt enable register - byte_offset: 24 - fieldset: CIER - - name: CIFR - description: Clock interrupt flag register - byte_offset: 28 - access: Read - fieldset: CIFR - - name: CICR - description: Clock interrupt clear register - byte_offset: 32 - access: Write - fieldset: CICR - - name: AHB1RSTR - description: AHB1 peripheral reset register - byte_offset: 40 - fieldset: AHB1RSTR - - name: AHB2RSTR - description: AHB2 peripheral reset register - byte_offset: 44 - fieldset: AHB2RSTR - - name: AHB3RSTR - description: AHB3 peripheral reset register - byte_offset: 48 - fieldset: AHB3RSTR - - name: APB1RSTR1 - description: APB1 peripheral reset register 1 - byte_offset: 56 - fieldset: APB1RSTR1 - - name: APB1RSTR2 - description: APB1 peripheral reset register 2 - byte_offset: 60 - fieldset: APB1RSTR2 - - name: APB2RSTR - description: APB2 peripheral reset register - byte_offset: 64 - fieldset: APB2RSTR - - name: APB3RSTR - description: APB3 peripheral reset register - byte_offset: 68 - fieldset: APB3RSTR - - name: AHB1ENR - description: AHB1 peripheral clock enable register - byte_offset: 72 - fieldset: AHB1ENR - - name: AHB2ENR - description: AHB2 peripheral clock enable register - byte_offset: 76 - fieldset: AHB2ENR - - name: AHB3ENR - description: AHB3 peripheral clock enable register - byte_offset: 80 - fieldset: AHB3ENR - - name: APB1ENR1 - description: APB1 peripheral clock enable register 1 - byte_offset: 88 - fieldset: APB1ENR1 - - name: APB1ENR2 - description: APB1 peripheral clock enable register 2 - byte_offset: 92 - fieldset: APB1ENR2 - - name: APB2ENR - description: APB2 peripheral clock enable register - byte_offset: 96 - fieldset: APB2ENR - - name: APB3ENR - description: APB3 peripheral clock enable register - byte_offset: 100 - fieldset: APB3ENR - - name: AHB1SMENR - description: AHB1 peripheral clocks enable in Sleep modes register - byte_offset: 104 - fieldset: AHB1SMENR - - name: AHB2SMENR - description: AHB2 peripheral clocks enable in Sleep modes register - byte_offset: 108 - fieldset: AHB2SMENR - - name: AHB3SMENR - description: AHB3 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 112 - fieldset: AHB3SMENR - - name: APB1SMENR1 - description: APB1 peripheral clocks enable in Sleep mode register 1 - byte_offset: 120 - fieldset: APB1SMENR1 - - name: APB1SMENR2 - description: APB1 peripheral clocks enable in Sleep mode register 2 - byte_offset: 124 - fieldset: APB1SMENR2 - - name: APB2SMENR - description: APB2 peripheral clocks enable in Sleep mode register - byte_offset: 128 - fieldset: APB2SMENR - - name: APB3SMENR - description: APB3 peripheral clock enable in Sleep mode register - byte_offset: 132 - fieldset: APB3SMENR - - name: CCIPR - description: Peripherals independent clock configuration register - byte_offset: 136 - fieldset: CCIPR - - name: BDCR - description: Backup domain control register - byte_offset: 144 - fieldset: BDCR - - name: CSR - description: Control/status register - byte_offset: 148 - fieldset: CSR - - name: EXTCFGR - description: Extended clock recovery register - byte_offset: 264 - fieldset: EXTCFGR + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: Internal clock sources calibration register + byte_offset: 4 + fieldset: ICSCR + - name: CFGR + description: Clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: PLLCFGR + description: PLL configuration register + byte_offset: 12 + fieldset: PLLCFGR + - name: CIER + description: Clock interrupt enable register + byte_offset: 24 + fieldset: CIER + - name: CIFR + description: Clock interrupt flag register + byte_offset: 28 + access: Read + fieldset: CIFR + - name: CICR + description: Clock interrupt clear register + byte_offset: 32 + access: Write + fieldset: CICR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 40 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: AHB2 peripheral reset register + byte_offset: 44 + fieldset: AHB2RSTR + - name: AHB3RSTR + description: AHB3 peripheral reset register + byte_offset: 48 + fieldset: AHB3RSTR + - name: APB1RSTR1 + description: APB1 peripheral reset register 1 + byte_offset: 56 + fieldset: APB1RSTR1 + - name: APB1RSTR2 + description: APB1 peripheral reset register 2 + byte_offset: 60 + fieldset: APB1RSTR2 + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 64 + fieldset: APB2RSTR + - name: APB3RSTR + description: APB3 peripheral reset register + byte_offset: 68 + fieldset: APB3RSTR + - name: AHB1ENR + description: AHB1 peripheral clock enable register + byte_offset: 72 + fieldset: AHB1ENR + - name: AHB2ENR + description: AHB2 peripheral clock enable register + byte_offset: 76 + fieldset: AHB2ENR + - name: AHB3ENR + description: AHB3 peripheral clock enable register + byte_offset: 80 + fieldset: AHB3ENR + - name: APB1ENR1 + description: APB1 peripheral clock enable register 1 + byte_offset: 88 + fieldset: APB1ENR1 + - name: APB1ENR2 + description: APB1 peripheral clock enable register 2 + byte_offset: 92 + fieldset: APB1ENR2 + - name: APB2ENR + description: APB2 peripheral clock enable register + byte_offset: 96 + fieldset: APB2ENR + - name: APB3ENR + description: APB3 peripheral clock enable register + byte_offset: 100 + fieldset: APB3ENR + - name: AHB1SMENR + description: AHB1 peripheral clocks enable in Sleep modes register + byte_offset: 104 + fieldset: AHB1SMENR + - name: AHB2SMENR + description: AHB2 peripheral clocks enable in Sleep modes register + byte_offset: 108 + fieldset: AHB2SMENR + - name: AHB3SMENR + description: AHB3 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 112 + fieldset: AHB3SMENR + - name: APB1SMENR1 + description: APB1 peripheral clocks enable in Sleep mode register 1 + byte_offset: 120 + fieldset: APB1SMENR1 + - name: APB1SMENR2 + description: APB1 peripheral clocks enable in Sleep mode register 2 + byte_offset: 124 + fieldset: APB1SMENR2 + - name: APB2SMENR + description: APB2 peripheral clocks enable in Sleep mode register + byte_offset: 128 + fieldset: APB2SMENR + - name: APB3SMENR + description: APB3 peripheral clock enable in Sleep mode register + byte_offset: 132 + fieldset: APB3SMENR + - name: CCIPR + description: Peripherals independent clock configuration register + byte_offset: 136 + fieldset: CCIPR + - name: BDCR + description: Backup domain control register + byte_offset: 144 + fieldset: BDCR + - name: CSR + description: Control/status register + byte_offset: 148 + fieldset: CSR + - name: EXTCFGR + description: Extended clock recovery register + byte_offset: 264 + fieldset: EXTCFGR fieldset/AHB1ENR: description: AHB1 peripheral clock enable register fields: - - name: DMA1EN - description: CPU1 DMA1 clock enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: CPU1 DMA2 clock enable - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1EN - description: CPU1 DMAMUX1 clock enable - bit_offset: 2 - bit_size: 1 - - name: CRCEN - description: CPU1 CRC clock enable - bit_offset: 12 - bit_size: 1 + - name: DMA1EN + description: CPU1 DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: CPU1 DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1EN + description: CPU1 DMAMUX1 clock enable + bit_offset: 2 + bit_size: 1 + - name: CRCEN + description: CPU1 CRC clock enable + bit_offset: 12 + bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - - name: DMA1RST - description: DMA1 reset - bit_offset: 0 - bit_size: 1 - - name: DMA2RST - description: DMA2 reset - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1RST - description: DMAMUX1 reset - bit_offset: 2 - bit_size: 1 - - name: CRCRST - description: CRC reset - bit_offset: 12 - bit_size: 1 + - name: DMA1RST + description: DMA1 reset + bit_offset: 0 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1RST + description: DMAMUX1 reset + bit_offset: 2 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 fieldset/AHB1SMENR: description: AHB1 peripheral clocks enable in Sleep modes register fields: - - name: DMA1SMEN - description: DMA1 clock enable during CPU1 CSleep mode. - bit_offset: 0 - bit_size: 1 - - name: DMA2SMEN - description: DMA2 clock enable during CPU1 CSleep mode - bit_offset: 1 - bit_size: 1 - - name: DMAMUX1SMEN - description: DMAMUX1 clock enable during CPU1 CSleep mode. - bit_offset: 2 - bit_size: 1 - - name: CRCSMEN - description: CRC clock enable during CPU1 CSleep mode. - bit_offset: 12 - bit_size: 1 + - name: DMA1SMEN + description: DMA1 clock enable during CPU1 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: DMA2SMEN + description: DMA2 clock enable during CPU1 CSleep mode + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1SMEN + description: DMAMUX1 clock enable during CPU1 CSleep mode. + bit_offset: 2 + bit_size: 1 + - name: CRCSMEN + description: CRC clock enable during CPU1 CSleep mode. + bit_offset: 12 + bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - - name: GPIOAEN - description: CPU1 IO port A clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: CPU1 IO port B clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: CPU1 IO port C clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIOHEN - description: CPU1 IO port H clock enable - bit_offset: 7 - bit_size: 1 + - name: GPIOAEN + description: CPU1 IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: CPU1 IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: CPU1 IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIOHEN + description: CPU1 IO port H clock enable + bit_offset: 7 + bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - - name: GPIOARST - description: IO port A reset - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: IO port B reset - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: IO port C reset - bit_offset: 2 - bit_size: 1 - - name: GPIOHRST - description: IO port H reset - bit_offset: 7 - bit_size: 1 + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 7 + bit_size: 1 fieldset/AHB2SMENR: description: AHB2 peripheral clocks enable in Sleep modes register fields: - - name: GPIOASMEN - description: IO port A clock enable during CPU1 CSleep mode. - bit_offset: 0 - bit_size: 1 - - name: GPIOBSMEN - description: IO port B clock enable during CPU1 CSleep mode. - bit_offset: 1 - bit_size: 1 - - name: GPIOCSMEN - description: IO port C clock enable during CPU1 CSleep mode. - bit_offset: 2 - bit_size: 1 - - name: GPIOHSMEN - description: IO port H clock enable during CPU1 CSleep mode. - bit_offset: 7 - bit_size: 1 + - name: GPIOASMEN + description: IO port A clock enable during CPU1 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: IO port B clock enable during CPU1 CSleep mode. + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: IO port C clock enable during CPU1 CSleep mode. + bit_offset: 2 + bit_size: 1 + - name: GPIOHSMEN + description: IO port H clock enable during CPU1 CSleep mode. + bit_offset: 7 + bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: - - name: PKAEN - description: PKAEN - bit_offset: 16 - bit_size: 1 - - name: AESEN - description: AESEN - bit_offset: 17 - bit_size: 1 - - name: RNGEN - description: RNGEN - bit_offset: 18 - bit_size: 1 - - name: HSEMEN - description: HSEMEN - bit_offset: 19 - bit_size: 1 - - name: FLASHEN - description: CPU1 Flash interface clock enable - bit_offset: 25 - bit_size: 1 + - name: PKAEN + description: PKAEN + bit_offset: 16 + bit_size: 1 + - name: AESEN + description: AESEN + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: RNGEN + bit_offset: 18 + bit_size: 1 + - name: HSEMEN + description: HSEMEN + bit_offset: 19 + bit_size: 1 + - name: FLASHEN + description: CPU1 Flash interface clock enable + bit_offset: 25 + bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - - name: PKARST - description: PKARST - bit_offset: 16 - bit_size: 1 - - name: AESRST - description: AESRST - bit_offset: 17 - bit_size: 1 - - name: RNGRST - description: RNGRST - bit_offset: 18 - bit_size: 1 - - name: HSEMRST - description: HSEMRST - bit_offset: 19 - bit_size: 1 - - name: FLASHRST - description: Flash interface reset - bit_offset: 25 - bit_size: 1 + - name: PKARST + description: PKARST + bit_offset: 16 + bit_size: 1 + - name: AESRST + description: AESRST + bit_offset: 17 + bit_size: 1 + - name: RNGRST + description: RNGRST + bit_offset: 18 + bit_size: 1 + - name: HSEMRST + description: HSEMRST + bit_offset: 19 + bit_size: 1 + - name: FLASHRST + description: Flash interface reset + bit_offset: 25 + bit_size: 1 fieldset/AHB3SMENR: description: AHB3 peripheral clocks enable in Sleep and Stop modes register fields: - - name: PKASMEN - description: PKA accelerator clock enable during CPU1 CSleep mode. - bit_offset: 16 - bit_size: 1 - - name: AESSMEN - description: AES accelerator clock enable during CPU1 CSleep mode. - bit_offset: 17 - bit_size: 1 - - name: RNGSMEN - description: True RNG clocks enable during CPU1 Csleep and CStop modes - bit_offset: 18 - bit_size: 1 - - name: SRAM1SMEN - description: SRAM1 interface clock enable during CPU1 CSleep mode. - bit_offset: 23 - bit_size: 1 - - name: SRAM2SMEN - description: SRAM2 memory interface clock enable during CPU1 CSleep mode - bit_offset: 24 - bit_size: 1 - - name: FLASHSMEN - description: Flash interface clock enable during CPU1 CSleep mode. - bit_offset: 25 - bit_size: 1 + - name: PKASMEN + description: PKA accelerator clock enable during CPU1 CSleep mode. + bit_offset: 16 + bit_size: 1 + - name: AESSMEN + description: AES accelerator clock enable during CPU1 CSleep mode. + bit_offset: 17 + bit_size: 1 + - name: RNGSMEN + description: True RNG clocks enable during CPU1 Csleep and CStop modes + bit_offset: 18 + bit_size: 1 + - name: SRAM1SMEN + description: SRAM1 interface clock enable during CPU1 CSleep mode. + bit_offset: 23 + bit_size: 1 + - name: SRAM2SMEN + description: SRAM2 memory interface clock enable during CPU1 CSleep mode + bit_offset: 24 + bit_size: 1 + - name: FLASHSMEN + description: Flash interface clock enable during CPU1 CSleep mode. + bit_offset: 25 + bit_size: 1 fieldset/APB1ENR1: description: APB1 peripheral clock enable register 1 fields: - - name: TIM2EN - description: CPU1 TIM2 timer clock enable - bit_offset: 0 - bit_size: 1 - - name: RTCAPBEN - description: CPU1 RTC APB clock enable - bit_offset: 10 - bit_size: 1 - - name: WWDGEN - description: CPU1 Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: CPU1 SPI2 clock enable - bit_offset: 14 - bit_size: 1 - - name: USART2EN - description: CPU1 USART2 clock enable - bit_offset: 17 - bit_size: 1 - - name: I2C1EN - description: CPU1 I2C1 clocks enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: CPU1 I2C2 clocks enable - bit_offset: 22 - bit_size: 1 - - name: I2C3EN - description: CPU1 I2C3 clocks enable - bit_offset: 23 - bit_size: 1 - - name: DAC1EN - description: CPU1 DAC1 clock enable - bit_offset: 29 - bit_size: 1 - - name: LPTIM1EN - description: CPU1 Low power timer 1 clocks enable - bit_offset: 31 - bit_size: 1 + - name: TIM2EN + description: CPU1 TIM2 timer clock enable + bit_offset: 0 + bit_size: 1 + - name: RTCAPBEN + description: CPU1 RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: CPU1 Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: CPU1 SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: USART2EN + description: CPU1 USART2 clock enable + bit_offset: 17 + bit_size: 1 + - name: I2C1EN + description: CPU1 I2C1 clocks enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: CPU1 I2C2 clocks enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: CPU1 I2C3 clocks enable + bit_offset: 23 + bit_size: 1 + - name: DAC1EN + description: CPU1 DAC1 clock enable + bit_offset: 29 + bit_size: 1 + - name: LPTIM1EN + description: CPU1 Low power timer 1 clocks enable + bit_offset: 31 + bit_size: 1 fieldset/APB1ENR2: description: APB1 peripheral clock enable register 2 fields: - - name: LPUART1EN - description: CPU1 Low power UART 1 clocks enable - bit_offset: 0 - bit_size: 1 - - name: LPTIM2EN - description: CPU1 Low power timer 2 clocks enable - bit_offset: 5 - bit_size: 1 - - name: LPTIM3EN - description: CPU1 Low power timer 3 clocks enable - bit_offset: 6 - bit_size: 1 + - name: LPUART1EN + description: CPU1 Low power UART 1 clocks enable + bit_offset: 0 + bit_size: 1 + - name: LPTIM2EN + description: CPU1 Low power timer 2 clocks enable + bit_offset: 5 + bit_size: 1 + - name: LPTIM3EN + description: CPU1 Low power timer 3 clocks enable + bit_offset: 6 + bit_size: 1 fieldset/APB1RSTR1: description: APB1 peripheral reset register 1 fields: - - name: TIM2RST - description: TIM2 timer reset - bit_offset: 0 - bit_size: 1 - - name: SPI2RST - description: SPI2 reset - bit_offset: 14 - bit_size: 1 - - name: USART2RST - description: USART2 reset - bit_offset: 17 - bit_size: 1 - - name: I2C1RST - description: I2C1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C2 reset - bit_offset: 22 - bit_size: 1 - - name: I2C3RST - description: I2C3 reset - bit_offset: 23 - bit_size: 1 - - name: DACRST - description: DAC reset - bit_offset: 29 - bit_size: 1 - - name: LPTIM1RST - description: Low Power Timer 1 reset - bit_offset: 31 - bit_size: 1 + - name: TIM2RST + description: TIM2 timer reset + bit_offset: 0 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: USART2RST + description: USART2 reset + bit_offset: 17 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 23 + bit_size: 1 + - name: DACRST + description: DAC reset + bit_offset: 29 + bit_size: 1 + - name: LPTIM1RST + description: Low Power Timer 1 reset + bit_offset: 31 + bit_size: 1 fieldset/APB1RSTR2: description: APB1 peripheral reset register 2 fields: - - name: LPUART1RST - description: Low-power UART 1 reset - bit_offset: 0 - bit_size: 1 - - name: LPTIM2RST - description: Low-power timer 2 reset - bit_offset: 5 - bit_size: 1 - - name: LPTIM3RST - description: Low-power timer 3 reset - bit_offset: 6 - bit_size: 1 + - name: LPUART1RST + description: Low-power UART 1 reset + bit_offset: 0 + bit_size: 1 + - name: LPTIM2RST + description: Low-power timer 2 reset + bit_offset: 5 + bit_size: 1 + - name: LPTIM3RST + description: Low-power timer 3 reset + bit_offset: 6 + bit_size: 1 fieldset/APB1SMENR1: description: APB1 peripheral clocks enable in Sleep mode register 1 fields: - - name: TIM2SMEN - description: TIM2 timer clock enable during CPU1 CSleep mode. - bit_offset: 0 - bit_size: 1 - - name: RTCAPBSMEN - description: RTC bus clock enable during CPU1 CSleep mode. - bit_offset: 10 - bit_size: 1 - - name: WWDGSMEN - description: Window watchdog clocks enable during CPU1 CSleep mode. - bit_offset: 11 - bit_size: 1 - - name: SPI2SMEN - description: SPI2 clock enable during CPU1 CSleep mode. - bit_offset: 14 - bit_size: 1 - - name: USART2SMEN - description: USART2 clock enable during CPU1 CSleep mode. - bit_offset: 17 - bit_size: 1 - - name: I2C1SMEN - description: I2C1 clock enable during CPU1 Csleep and CStop modes - bit_offset: 21 - bit_size: 1 - - name: I2C2SMEN - description: I2C2 clock enable during CPU1 Csleep and CStop modes - bit_offset: 22 - bit_size: 1 - - name: I2C3SMEN - description: I2C3 clock enable during CPU1 Csleep and CStop modes - bit_offset: 23 - bit_size: 1 - - name: DACSMEN - description: DAC clock enable during CPU1 CSleep mode. - bit_offset: 29 - bit_size: 1 - - name: LPTIM1SMEN - description: Low power timer 1 clock enable during CPU1 Csleep and CStop mode - bit_offset: 31 - bit_size: 1 + - name: TIM2SMEN + description: TIM2 timer clock enable during CPU1 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: RTCAPBSMEN + description: RTC bus clock enable during CPU1 CSleep mode. + bit_offset: 10 + bit_size: 1 + - name: WWDGSMEN + description: Window watchdog clocks enable during CPU1 CSleep mode. + bit_offset: 11 + bit_size: 1 + - name: SPI2SMEN + description: SPI2 clock enable during CPU1 CSleep mode. + bit_offset: 14 + bit_size: 1 + - name: USART2SMEN + description: USART2 clock enable during CPU1 CSleep mode. + bit_offset: 17 + bit_size: 1 + - name: I2C1SMEN + description: I2C1 clock enable during CPU1 Csleep and CStop modes + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: I2C2 clock enable during CPU1 Csleep and CStop modes + bit_offset: 22 + bit_size: 1 + - name: I2C3SMEN + description: I2C3 clock enable during CPU1 Csleep and CStop modes + bit_offset: 23 + bit_size: 1 + - name: DACSMEN + description: DAC clock enable during CPU1 CSleep mode. + bit_offset: 29 + bit_size: 1 + - name: LPTIM1SMEN + description: Low power timer 1 clock enable during CPU1 Csleep and CStop mode + bit_offset: 31 + bit_size: 1 fieldset/APB1SMENR2: description: APB1 peripheral clocks enable in Sleep mode register 2 fields: - - name: LPUART1SMEN - description: Low power UART 1 clock enable during CPU1 Csleep and CStop modes. - bit_offset: 0 - bit_size: 1 - - name: LPTIM2SMEN - description: Low power timer 2 clock enable during CPU1 Csleep and CStop modes - bit_offset: 5 - bit_size: 1 - - name: LPTIM3SMEN - description: Low power timer 3 clock enable during CPU1 Csleep and CStop modes - bit_offset: 6 - bit_size: 1 + - name: LPUART1SMEN + description: Low power UART 1 clock enable during CPU1 Csleep and CStop modes. + bit_offset: 0 + bit_size: 1 + - name: LPTIM2SMEN + description: Low power timer 2 clock enable during CPU1 Csleep and CStop modes + bit_offset: 5 + bit_size: 1 + - name: LPTIM3SMEN + description: Low power timer 3 clock enable during CPU1 Csleep and CStop modes + bit_offset: 6 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - - name: ADCEN - description: CPU1 ADC clocks enable - bit_offset: 9 - bit_size: 1 - - name: TIM1EN - description: CPU1 TIM1 timer clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: CPU1 SPI1 clock enable - bit_offset: 12 - bit_size: 1 - - name: USART1EN - description: CPU1 USART1clocks enable - bit_offset: 14 - bit_size: 1 - - name: TIM16EN - description: CPU1 TIM16 timer clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: CPU1 TIM17 timer clock enable - bit_offset: 18 - bit_size: 1 + - name: ADCEN + description: CPU1 ADC clocks enable + bit_offset: 9 + bit_size: 1 + - name: TIM1EN + description: CPU1 TIM1 timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: CPU1 SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: CPU1 USART1clocks enable + bit_offset: 14 + bit_size: 1 + - name: TIM16EN + description: CPU1 TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: CPU1 TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - - name: ADCRST - description: ADC reset - bit_offset: 9 - bit_size: 1 - - name: TIM1RST - description: TIM1 timer reset - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: SPI1 reset - bit_offset: 12 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 14 - bit_size: 1 - - name: TIM16RST - description: TIM16 timer reset - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: TIM17 timer reset - bit_offset: 18 - bit_size: 1 + - name: ADCRST + description: ADC reset + bit_offset: 9 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI1 reset + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 fieldset/APB2SMENR: description: APB2 peripheral clocks enable in Sleep mode register fields: - - name: ADCSMEN - description: ADC clocks enable during CPU1 Csleep and CStop modes - bit_offset: 9 - bit_size: 1 - - name: TIM1SMEN - description: TIM1 timer clock enable during CPU1 CSleep mode. - bit_offset: 11 - bit_size: 1 - - name: SPI1SMEN - description: SPI1 clock enable during CPU1 CSleep mode. - bit_offset: 12 - bit_size: 1 - - name: USART1SMEN - description: USART1 clock enable during CPU1 Csleep and CStop modes. - bit_offset: 14 - bit_size: 1 - - name: TIM16SMEN - description: TIM16 timer clock enable during CPU1 CSleep mode. - bit_offset: 17 - bit_size: 1 - - name: TIM17SMEN - description: TIM17 timer clock enable during CPU1 CSleep mode. - bit_offset: 18 - bit_size: 1 + - name: ADCSMEN + description: ADC clocks enable during CPU1 Csleep and CStop modes + bit_offset: 9 + bit_size: 1 + - name: TIM1SMEN + description: TIM1 timer clock enable during CPU1 CSleep mode. + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: SPI1 clock enable during CPU1 CSleep mode. + bit_offset: 12 + bit_size: 1 + - name: USART1SMEN + description: USART1 clock enable during CPU1 Csleep and CStop modes. + bit_offset: 14 + bit_size: 1 + - name: TIM16SMEN + description: TIM16 timer clock enable during CPU1 CSleep mode. + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: TIM17 timer clock enable during CPU1 CSleep mode. + bit_offset: 18 + bit_size: 1 fieldset/APB3ENR: description: APB3 peripheral clock enable register fields: - - name: SUBGHZSPIEN - description: sub-GHz radio SPI clock enable - bit_offset: 0 - bit_size: 1 + - name: SUBGHZSPIEN + description: sub-GHz radio SPI clock enable + bit_offset: 0 + bit_size: 1 fieldset/APB3RSTR: description: APB3 peripheral reset register fields: - - name: SUBGHZSPIRST - description: Sub-GHz radio SPI reset - bit_offset: 0 - bit_size: 1 + - name: SUBGHZSPIRST + description: Sub-GHz radio SPI reset + bit_offset: 0 + bit_size: 1 fieldset/APB3SMENR: description: APB3 peripheral clock enable in Sleep mode register fields: - - name: SUBGHZSPISMEN - description: Sub-GHz radio SPI clock enable during Sleep and Stop modes - bit_offset: 0 - bit_size: 1 + - name: SUBGHZSPISMEN + description: Sub-GHz radio SPI clock enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 fieldset/BDCR: description: Backup domain control register fields: - - name: LSEON - description: LSE oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: LSE oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: LSE oscillator bypass - bit_offset: 2 - bit_size: 1 - - name: LSEDRV - description: LSE oscillator drive capability - bit_offset: 3 - bit_size: 2 - - name: LSECSSON - description: CSS on LSE enable - bit_offset: 5 - bit_size: 1 - - name: LSECSSD - description: CSS on LSE failure Detection - bit_offset: 6 - bit_size: 1 - - name: LSESYSEN - description: LSE system clock enable - bit_offset: 7 - bit_size: 1 - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - - name: LSESYSRDY - description: LSE system clock ready - bit_offset: 11 - bit_size: 1 - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: Backup domain software reset - bit_offset: 16 - bit_size: 1 - - name: LSCOEN - description: Low speed clock output enable - bit_offset: 24 - bit_size: 1 - - name: LSCOSEL - description: Low speed clock output selection - bit_offset: 25 - bit_size: 1 + - name: LSEON + description: LSE oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: LSE oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: LSE oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: LSE oscillator drive capability + bit_offset: 3 + bit_size: 2 + - name: LSECSSON + description: CSS on LSE enable + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: CSS on LSE failure Detection + bit_offset: 6 + bit_size: 1 + - name: LSESYSEN + description: LSE system clock enable + bit_offset: 7 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: LSESYSRDY + description: LSE system clock ready + bit_offset: 11 + bit_size: 1 + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: Low speed clock output enable + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: Low speed clock output selection + bit_offset: 25 + bit_size: 1 fieldset/CCIPR: description: Peripherals independent clock configuration register fields: - - name: USART1SEL - description: USART1 clock source selection - bit_offset: 0 - bit_size: 2 - - name: USART2SEL - description: USART2 clock source selection - bit_offset: 2 - bit_size: 2 - - name: SPI2SEL - description: SPI2 I2S clock source selection - bit_offset: 8 - bit_size: 2 - - name: LPUART1SEL - description: LPUART1 clock source selection - bit_offset: 10 - bit_size: 2 - - name: I2C1SEL - description: I2C1 clock source selection - bit_offset: 12 - bit_size: 2 - - name: I2C2SEL - description: I2C2 clock source selection - bit_offset: 14 - bit_size: 2 - - name: I2C3SEL - description: I2C3 clock source selection - bit_offset: 16 - bit_size: 2 - - name: LPTIM1SEL - description: Low power timer 1 clock source selection - bit_offset: 18 - bit_size: 2 - - name: LPTIM2SEL - description: Low power timer 2 clock source selection - bit_offset: 20 - bit_size: 2 - - name: LPTIM3SEL - description: Low power timer 3 clock source selection - bit_offset: 22 - bit_size: 2 - - name: ADCSEL - description: ADC clock source selection - bit_offset: 28 - bit_size: 2 - - name: RNGSEL - description: RNG clock source selection - bit_offset: 30 - bit_size: 2 + - name: USART1SEL + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + - name: USART2SEL + description: USART2 clock source selection + bit_offset: 2 + bit_size: 2 + - name: SPI2SEL + description: SPI2 I2S clock source selection + bit_offset: 8 + bit_size: 2 + - name: LPUART1SEL + description: LPUART1 clock source selection + bit_offset: 10 + bit_size: 2 + - name: I2C1SEL + description: I2C1 clock source selection + bit_offset: 12 + bit_size: 2 + - name: I2C2SEL + description: I2C2 clock source selection + bit_offset: 14 + bit_size: 2 + - name: I2C3SEL + description: I2C3 clock source selection + bit_offset: 16 + bit_size: 2 + - name: LPTIM1SEL + description: Low power timer 1 clock source selection + bit_offset: 18 + bit_size: 2 + - name: LPTIM2SEL + description: Low power timer 2 clock source selection + bit_offset: 20 + bit_size: 2 + - name: LPTIM3SEL + description: Low power timer 3 clock source selection + bit_offset: 22 + bit_size: 2 + - name: ADCSEL + description: ADC clock source selection + bit_offset: 28 + bit_size: 2 + enum: ADCSEL + - name: RNGSEL + description: RNG clock source selection + bit_offset: 30 + bit_size: 2 fieldset/CFGR: description: Clock configuration register fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 2 - - name: SWS - description: System clock switch status - bit_offset: 2 - bit_size: 2 - - name: HPRE - description: "HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)" - bit_offset: 4 - bit_size: 4 - - name: PPRE1 - description: PCLK1 low-speed prescaler (APB1) - bit_offset: 8 - bit_size: 3 - - name: PPRE2 - description: PCLK2 high-speed prescaler (APB2) - bit_offset: 11 - bit_size: 3 - - name: STOPWUCK - description: Wakeup from Stop and CSS backup clock selection - bit_offset: 15 - bit_size: 1 - - name: HPREF - description: "HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1)" - bit_offset: 16 - bit_size: 1 - - name: PPRE1F - description: PCLK1 prescaler flag (APB1) - bit_offset: 17 - bit_size: 1 - - name: PPRE2F - description: PCLK2 prescaler flag (APB2) - bit_offset: 18 - bit_size: 1 - - name: MCOSEL - description: Microcontroller clock output - bit_offset: 24 - bit_size: 4 - - name: MCOPRE - description: Microcontroller clock output prescaler - bit_offset: 28 - bit_size: 3 + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + - name: HPRE + description: HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.) + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: PCLK1 low-speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: PCLK2 high-speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: STOPWUCK + description: Wakeup from Stop and CSS backup clock selection + bit_offset: 15 + bit_size: 1 + - name: HPREF + description: HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1) + bit_offset: 16 + bit_size: 1 + - name: PPRE1F + description: PCLK1 prescaler flag (APB1) + bit_offset: 17 + bit_size: 1 + - name: PPRE2F + description: PCLK2 prescaler flag (APB2) + bit_offset: 18 + bit_size: 1 + - name: MCOSEL + description: Microcontroller clock output + bit_offset: 24 + bit_size: 4 + enum: MCOSEL + - name: MCOPRE + description: Microcontroller clock output prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: - - name: LSIRDYC - description: LSI ready interrupt clear - bit_offset: 0 - bit_size: 1 - - name: LSERDYC - description: LSE ready interrupt clear - bit_offset: 1 - bit_size: 1 - - name: MSIRDYC - description: MSI ready interrupt clear - bit_offset: 2 - bit_size: 1 - - name: HSIRDYC - description: HSI16 ready interrupt clear - bit_offset: 3 - bit_size: 1 - - name: HSERDYC - description: HSE32 ready interrupt clear - bit_offset: 4 - bit_size: 1 - - name: PLLRDYC - description: PLL ready interrupt clear - bit_offset: 5 - bit_size: 1 - - name: CSSC - description: HSE32 Clock security system interrupt clear - bit_offset: 8 - bit_size: 1 - - name: LSECSSC - description: LSE Clock security system interrupt clear - bit_offset: 9 - bit_size: 1 + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 1 + bit_size: 1 + - name: MSIRDYC + description: MSI ready interrupt clear + bit_offset: 2 + bit_size: 1 + - name: HSIRDYC + description: HSI16 ready interrupt clear + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: HSE32 ready interrupt clear + bit_offset: 4 + bit_size: 1 + - name: PLLRDYC + description: PLL ready interrupt clear + bit_offset: 5 + bit_size: 1 + - name: CSSC + description: HSE32 Clock security system interrupt clear + bit_offset: 8 + bit_size: 1 + - name: LSECSSC + description: LSE Clock security system interrupt clear + bit_offset: 9 + bit_size: 1 fieldset/CIER: description: Clock interrupt enable register fields: - - name: LSIRDYIE - description: LSI ready interrupt enable - bit_offset: 0 - bit_size: 1 - - name: LSERDYIE - description: LSE ready interrupt enable - bit_offset: 1 - bit_size: 1 - - name: MSIRDYIE - description: MSI ready interrupt enable - bit_offset: 2 - bit_size: 1 - - name: HSIRDYIE - description: HSI16 ready interrupt enable - bit_offset: 3 - bit_size: 1 - - name: HSERDYIE - description: HSE32 ready interrupt enable - bit_offset: 4 - bit_size: 1 - - name: PLLRDYIE - description: PLL ready interrupt enable - bit_offset: 5 - bit_size: 1 - - name: LSECSSIE - description: LSE clock security system interrupt enable - bit_offset: 9 - bit_size: 1 + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 1 + bit_size: 1 + - name: MSIRDYIE + description: MSI ready interrupt enable + bit_offset: 2 + bit_size: 1 + - name: HSIRDYIE + description: HSI16 ready interrupt enable + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: HSE32 ready interrupt enable + bit_offset: 4 + bit_size: 1 + - name: PLLRDYIE + description: PLL ready interrupt enable + bit_offset: 5 + bit_size: 1 + - name: LSECSSIE + description: LSE clock security system interrupt enable + bit_offset: 9 + bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register fields: - - name: LSIRDYF - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - - name: MSIRDYF - description: MSI ready interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSIRDYF - description: HSI16 ready interrupt flag - bit_offset: 3 - bit_size: 1 - - name: HSERDYF - description: HSE32 ready interrupt flag - bit_offset: 4 - bit_size: 1 - - name: PLLRDYF - description: PLL ready interrupt flag - bit_offset: 5 - bit_size: 1 - - name: CSSF - description: HSE32 Clock security system interrupt flag - bit_offset: 8 - bit_size: 1 - - name: LSECSSF - description: LSE Clock security system interrupt flag - bit_offset: 9 - bit_size: 1 + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: MSIRDYF + description: MSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSIRDYF + description: HSI16 ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: HSE32 ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLLRDYF + description: PLL ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: CSSF + description: HSE32 Clock security system interrupt flag + bit_offset: 8 + bit_size: 1 + - name: LSECSSF + description: LSE Clock security system interrupt flag + bit_offset: 9 + bit_size: 1 fieldset/CR: description: Clock control register fields: - - name: MSION - description: MSI clock enable - bit_offset: 0 - bit_size: 1 - - name: MSIRDY - description: MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready) - bit_offset: 1 - bit_size: 1 - - name: MSIPLLEN - description: MSI clock PLL enable - bit_offset: 2 - bit_size: 1 - - name: MSIRGSEL - description: MSI range control selection - bit_offset: 3 - bit_size: 1 - - name: MSIRANGE - description: MSI clock ranges - bit_offset: 4 - bit_size: 4 - - name: HSION - description: HSI16 clock enable - bit_offset: 8 - bit_size: 1 - - name: HSIKERON - description: HSI16 always enable for peripheral kernel clocks. - bit_offset: 9 - bit_size: 1 - - name: HSIRDY - description: HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready) - bit_offset: 10 - bit_size: 1 - - name: HSIASFS - description: HSI16 automatic start from Stop - bit_offset: 11 - bit_size: 1 - - name: HSIKERDY - description: HSI16 kernel clock ready flag for peripherals requests. - bit_offset: 12 - bit_size: 1 - - name: HSEON - description: HSE32 clock enable - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: HSE32 clock ready flag - bit_offset: 17 - bit_size: 1 - - name: CSSON - description: HSE32 Clock security system enable - bit_offset: 19 - bit_size: 1 - - name: HSEPRE - description: HSE32 sysclk prescaler - bit_offset: 20 - bit_size: 1 - - name: HSEBYPPWR - description: Enable HSE32 VDDTCXO output on package pin PB0-VDDTCXO. - bit_offset: 21 - bit_size: 1 - - name: PLLON - description: Main PLL enable - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: Main PLL clock ready flag - bit_offset: 25 - bit_size: 1 + - name: MSION + description: MSI clock enable + bit_offset: 0 + bit_size: 1 + - name: MSIRDY + description: MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready) + bit_offset: 1 + bit_size: 1 + - name: MSIPLLEN + description: MSI clock PLL enable + bit_offset: 2 + bit_size: 1 + - name: MSIRGSEL + description: MSI range control selection + bit_offset: 3 + bit_size: 1 + - name: MSIRANGE + description: MSI clock ranges + bit_offset: 4 + bit_size: 4 + - name: HSION + description: HSI16 clock enable + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: HSI16 always enable for peripheral kernel clocks. + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready) + bit_offset: 10 + bit_size: 1 + - name: HSIASFS + description: HSI16 automatic start from Stop + bit_offset: 11 + bit_size: 1 + - name: HSIKERDY + description: HSI16 kernel clock ready flag for peripherals requests. + bit_offset: 12 + bit_size: 1 + - name: HSEON + description: HSE32 clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE32 clock ready flag + bit_offset: 17 + bit_size: 1 + - name: CSSON + description: HSE32 Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: HSEPRE + description: HSE32 sysclk prescaler + bit_offset: 20 + bit_size: 1 + - name: HSEBYPPWR + description: Enable HSE32 VDDTCXO output on package pin PB0-VDDTCXO. + bit_offset: 21 + bit_size: 1 + - name: PLLON + description: Main PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL clock ready flag + bit_offset: 25 + bit_size: 1 fieldset/CSR: description: Control/status register fields: - - name: LSION - description: LSI oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: LSI oscillator ready - bit_offset: 1 - bit_size: 1 - - name: LSIPRE - description: LSI frequency prescaler - bit_offset: 4 - bit_size: 1 - - name: MSISRANGE - description: MSI clock ranges - bit_offset: 8 - bit_size: 4 - - name: RFRSTF - description: Radio in reset status flag - bit_offset: 14 - bit_size: 1 - - name: RFRST - description: Radio reset - bit_offset: 15 - bit_size: 1 - - name: RMVF - description: Remove reset flag - bit_offset: 23 - bit_size: 1 - - name: RFILARSTF - description: Radio illegal access flag - bit_offset: 24 - bit_size: 1 - - name: OBLRSTF - description: Option byte loader reset flag - bit_offset: 25 - bit_size: 1 - - name: PINRSTF - description: Pin reset flag - bit_offset: 26 - bit_size: 1 - - name: BORRSTF - description: BOR flag - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: Independent window watchdog reset flag - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 + - name: LSION + description: LSI oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: LSI oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSIPRE + description: LSI frequency prescaler + bit_offset: 4 + bit_size: 1 + - name: MSISRANGE + description: MSI clock ranges + bit_offset: 8 + bit_size: 4 + - name: RFRSTF + description: Radio in reset status flag + bit_offset: 14 + bit_size: 1 + - name: RFRST + description: Radio reset + bit_offset: 15 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 23 + bit_size: 1 + - name: RFILARSTF + description: Radio illegal access flag + bit_offset: 24 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: Pin reset flag + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: BOR flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent window watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 fieldset/EXTCFGR: description: Extended clock recovery register fields: - - name: SHDHPRE - description: "HCLK3 shared prescaler (AHB3, Flash, and SRAM2)" - bit_offset: 0 - bit_size: 4 - - name: SHDHPREF - description: "HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2)" - bit_offset: 16 - bit_size: 1 + - name: SHDHPRE + description: HCLK3 shared prescaler (AHB3, Flash, and SRAM2) + bit_offset: 0 + bit_size: 4 + - name: SHDHPREF + description: HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2) + bit_offset: 16 + bit_size: 1 fieldset/ICSCR: description: Internal clock sources calibration register fields: - - name: MSICAL - description: MSI clock calibration - bit_offset: 0 - bit_size: 8 - - name: MSITRIM - description: MSI clock trimming - bit_offset: 8 - bit_size: 8 - - name: HSICAL - description: HSI16 clock calibration - bit_offset: 16 - bit_size: 8 - - name: HSITRIM - description: HSI16 clock trimming - bit_offset: 24 - bit_size: 7 + - name: MSICAL + description: MSI clock calibration + bit_offset: 0 + bit_size: 8 + - name: MSITRIM + description: MSI clock trimming + bit_offset: 8 + bit_size: 8 + - name: HSICAL + description: HSI16 clock calibration + bit_offset: 16 + bit_size: 8 + - name: HSITRIM + description: HSI16 clock trimming + bit_offset: 24 + bit_size: 7 fieldset/PLLCFGR: description: PLL configuration register fields: - - name: PLLSRC - description: Main PLL entry clock source - bit_offset: 0 - bit_size: 2 - - name: PLLM - description: Division factor for the main PLL input clock - bit_offset: 4 - bit_size: 3 - - name: PLLN - description: Main PLL multiplication factor for VCO - bit_offset: 8 - bit_size: 7 - - name: PLLPEN - description: Main PLL PLLPCLK output enable - bit_offset: 16 - bit_size: 1 - - name: PLLP - description: Main PLL division factor for PLLPCLK. - bit_offset: 17 - bit_size: 5 - - name: PLLQEN - description: Main PLL PLLQCLK output enable - bit_offset: 24 - bit_size: 1 - - name: PLLQ - description: Main PLL division factor for PLLQCLK - bit_offset: 25 - bit_size: 3 - - name: PLLREN - description: Main PLL PLLRCLK output enable - bit_offset: 28 - bit_size: 1 - - name: PLLR - description: Main PLL division factor for PLLRCLK - bit_offset: 29 - bit_size: 3 + - name: PLLSRC + description: Main PLL entry clock source + bit_offset: 0 + bit_size: 2 + - name: PLLM + description: Division factor for the main PLL input clock + bit_offset: 4 + bit_size: 3 + - name: PLLN + description: Main PLL multiplication factor for VCO + bit_offset: 8 + bit_size: 7 + - name: PLLPEN + description: Main PLL PLLPCLK output enable + bit_offset: 16 + bit_size: 1 + - name: PLLP + description: Main PLL division factor for PLLPCLK. + bit_offset: 17 + bit_size: 5 + - name: PLLQEN + description: Main PLL PLLQCLK output enable + bit_offset: 24 + bit_size: 1 + - name: PLLQ + description: Main PLL division factor for PLLQCLK + bit_offset: 25 + bit_size: 3 + - name: PLLREN + description: Main PLL PLLRCLK output enable + bit_offset: 28 + bit_size: 1 + - name: PLLR + description: Main PLL division factor for PLLRCLK + bit_offset: 29 + bit_size: 3 +enum/ADCSEL: + bit_size: 2 + variants: + - name: HSI16 + description: HSI16 used as ADC clock source + value: 1 + - name: PLLPCLK + description: PLLPCLK used as ADC clock source + value: 2 + - name: SYSCLK + description: SYSCLK used as ADC clock source + value: 3 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: DCLK not divided + value: 0 + - name: Div3 + description: hclk = SYSCLK divided by 3 + value: 1 + - name: Div5 + description: hclk = SYSCLK divided by 5 + value: 2 + - name: Div6 + description: hclk = SYSCLK divided by 6 + value: 5 + - name: Div10 + description: hclk = SYSCLK divided by 8 + value: 6 + - name: Div32 + description: hclk = SYSCLK divided by 32 + value: 7 + - name: Div2 + description: hclk = SYSCLK divided by 2 + value: 8 + - name: Div4 + description: hclk = SYSCLK divided by 4 + value: 9 + - name: Div8 + description: hclk = SYSCLK divided by 8 + value: 10 + - name: Div16 + description: hclk = SYSCLK divided by 16 + value: 11 + - name: Div64 + description: hclk = SYSCLK divided by 64 + value: 12 + - name: Div128 + description: hclk = SYSCLK divided by 128 + value: 13 + - name: Div256 + description: hclk = SYSCLK divided by 256 + value: 14 + - name: Div512 + description: hclk = SYSCLK divided by 256 + value: 15 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 + - name: Div16 + description: Division by 16 + value: 4 +enum/MCOSEL: + bit_size: 4 + variants: + - name: NoClock + description: No clock + value: 0 + - name: SYSCLK + description: SYSCLK clock selected + value: 1 + - name: MSI + description: MSI oscillator clock selected + value: 2 + - name: HSI16 + description: HSI oscillator clock selected + value: 3 + - name: HSE32 + description: HSE32 oscillator clock selected + value: 4 + - name: PLLRCLK + description: Main PLLRCLK clock selected + value: 5 + - name: LSI + description: LSI oscillator clock selected + value: 6 + - name: LSE + description: LSE oscillator clock selected + value: 8 + - name: PLLPCLK + description: Main PLLCLK oscillator clock selected + value: 13 + - name: PLLQCLK + description: Main PLLQCLK oscillator clock selected + value: 14 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock selected + value: 0 + - name: LSE + description: LSE oscillator clock selected + value: 1 + - name: LSI + description: LSI oscillator clock selected + value: 2 + - name: HSE + description: HSE oscillator clock divided by 32 selected + value: 3 diff --git a/data/registers/rng_v1.yaml b/data/registers/rng_v1.yaml index bb95691..fef8acb 100644 --- a/data/registers/rng_v1.yaml +++ b/data/registers/rng_v1.yaml @@ -1,54 +1,53 @@ ---- block/RNG: description: Random number generator items: - - name: CR - description: control register - byte_offset: 0 - fieldset: CR - - name: SR - description: status register - byte_offset: 4 - fieldset: SR - - name: DR - description: data register - byte_offset: 8 - access: Read + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: SR + description: status register + byte_offset: 4 + fieldset: SR + - name: DR + description: data register + byte_offset: 8 + access: Read fieldset/CR: description: control register fields: - - name: RNGEN - description: Random number generator enable - bit_offset: 2 - bit_size: 1 - - name: IE - description: Interrupt enable - bit_offset: 3 - bit_size: 1 - - name: CED - description: Clock error detection - bit_offset: 5 - bit_size: 1 + - name: RNGEN + description: Random number generator enable + bit_offset: 2 + bit_size: 1 + - name: IE + description: Interrupt enable + bit_offset: 3 + bit_size: 1 + - name: CED + description: Clock error detection + bit_offset: 5 + bit_size: 1 fieldset/SR: description: status register fields: - - name: DRDY - description: Data ready - bit_offset: 0 - bit_size: 1 - - name: CECS - description: Clock error current status - bit_offset: 1 - bit_size: 1 - - name: SECS - description: Seed error current status - bit_offset: 2 - bit_size: 1 - - name: CEIS - description: Clock error interrupt status - bit_offset: 5 - bit_size: 1 - - name: SEIS - description: Seed error interrupt status - bit_offset: 6 - bit_size: 1 + - name: DRDY + description: Data ready + bit_offset: 0 + bit_size: 1 + - name: CECS + description: Clock error current status + bit_offset: 1 + bit_size: 1 + - name: SECS + description: Seed error current status + bit_offset: 2 + bit_size: 1 + - name: CEIS + description: Clock error interrupt status + bit_offset: 5 + bit_size: 1 + - name: SEIS + description: Seed error interrupt status + bit_offset: 6 + bit_size: 1 diff --git a/data/registers/rng_v2.yaml b/data/registers/rng_v2.yaml index a90b9a8..fd856a4 100644 --- a/data/registers/rng_v2.yaml +++ b/data/registers/rng_v2.yaml @@ -1,192 +1,191 @@ ---- block/RNG: description: Random number generator items: - - name: CR - description: control register - byte_offset: 0 - fieldset: CR - - name: SR - description: status register - byte_offset: 4 - fieldset: SR - - name: DR - description: data register - byte_offset: 8 - access: Read - - name: HTCR - description: health test control register - byte_offset: 16 - fieldset: HTCR + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: SR + description: status register + byte_offset: 4 + fieldset: SR + - name: DR + description: data register + byte_offset: 8 + access: Read + - name: HTCR + description: health test control register + byte_offset: 16 + fieldset: HTCR fieldset/CR: description: control register fields: - - name: RNGEN - description: Random number generator enable - bit_offset: 2 - bit_size: 1 - - name: IE - description: Interrupt enable - bit_offset: 3 - bit_size: 1 - - name: CED - description: Clock error detection - bit_offset: 5 - bit_size: 1 - - name: RNG_CONFIG3 - description: RNG configuration 3 - bit_offset: 8 - bit_size: 4 - enum: RNG_CONFIG3 - - name: NISTC - description: Non NIST compliant - bit_offset: 12 - bit_size: 1 - enum: NISTC - - name: RNG_CONFIG2 - description: RNG configuration 2 - bit_offset: 13 - bit_size: 3 - enum: RNG_CONFIG2 - - name: CLKDIV - description: Clock divider factor - bit_offset: 16 - bit_size: 4 - enum: CLKDIV - - name: RNG_CONFIG1 - description: RNG configuration 1 - bit_offset: 20 - bit_size: 6 - enum: RNG_CONFIG1 - - name: CONDRST - description: Conditioning soft reset - bit_offset: 30 - bit_size: 1 - - name: CONFIGLOCK - description: Config Lock - bit_offset: 31 - bit_size: 1 -fieldset/SR: - description: status register - fields: - - name: DRDY - description: Data ready - bit_offset: 0 - bit_size: 1 - - name: CECS - description: Clock error current status - bit_offset: 1 - bit_size: 1 - - name: SECS - description: Seed error current status - bit_offset: 2 - bit_size: 1 - - name: CEIS - description: Clock error interrupt status - bit_offset: 5 - bit_size: 1 - - name: SEIS - description: Seed error interrupt status - bit_offset: 6 - bit_size: 1 + - name: RNGEN + description: Random number generator enable + bit_offset: 2 + bit_size: 1 + - name: IE + description: Interrupt enable + bit_offset: 3 + bit_size: 1 + - name: CED + description: Clock error detection + bit_offset: 5 + bit_size: 1 + - name: RNG_CONFIG3 + description: RNG configuration 3 + bit_offset: 8 + bit_size: 4 + enum: RNG_CONFIG3 + - name: NISTC + description: Non NIST compliant + bit_offset: 12 + bit_size: 1 + enum: NISTC + - name: RNG_CONFIG2 + description: RNG configuration 2 + bit_offset: 13 + bit_size: 3 + enum: RNG_CONFIG2 + - name: CLKDIV + description: Clock divider factor + bit_offset: 16 + bit_size: 4 + enum: CLKDIV + - name: RNG_CONFIG1 + description: RNG configuration 1 + bit_offset: 20 + bit_size: 6 + enum: RNG_CONFIG1 + - name: CONDRST + description: Conditioning soft reset + bit_offset: 30 + bit_size: 1 + - name: CONFIGLOCK + description: Config Lock + bit_offset: 31 + bit_size: 1 fieldset/HTCR: description: Health test control register fields: - - name: HTCFG - description: Health test configuration - bit_offset: 0 - bit_size: 32 - enum: HTCFG + - name: HTCFG + description: Health test configuration + bit_offset: 0 + bit_size: 32 + enum: HTCFG +fieldset/SR: + description: status register + fields: + - name: DRDY + description: Data ready + bit_offset: 0 + bit_size: 1 + - name: CECS + description: Clock error current status + bit_offset: 1 + bit_size: 1 + - name: SECS + description: Seed error current status + bit_offset: 2 + bit_size: 1 + - name: CEIS + description: Clock error interrupt status + bit_offset: 5 + bit_size: 1 + - name: SEIS + description: Seed error interrupt status + bit_offset: 6 + bit_size: 1 enum/CLKDIV: bit_size: 4 variants: - - name: NoDiv - description: Internal RNG clock after divider is similar to incoming RNG clock - value: 0 - - name: Div_2_1 - description: Divide RNG clock by 2^1 - value: 1 - - name: Div_2_2 - description: Divide RNG clock by 2^2 - value: 2 - - name: Div_2_3 - description: Divide RNG clock by 2^3 - value: 3 - - name: Div_2_4 - description: Divide RNG clock by 2^4 - value: 4 - - name: Div_2_5 - description: Divide RNG clock by 2^5 - value: 5 - - name: Div_2_6 - description: Divide RNG clock by 2^6 - value: 6 - - name: Div_2_7 - description: Divide RNG clock by 2^7 - value: 7 - - name: Div_2_8 - description: Divide RNG clock by 2^8 - value: 8 - - name: Div_2_9 - description: Divide RNG clock by 2^9 - value: 9 - - name: Div_2_10 - description: Divide RNG clock by 2^10 - value: 10 - - name: Div_2_11 - description: Divide RNG clock by 2^11 - value: 11 - - name: Div_2_12 - description: Divide RNG clock by 2^12 - value: 12 - - name: Div_2_13 - description: Divide RNG clock by 2^13 - value: 13 - - name: Div_2_14 - description: Divide RNG clock by 2^14 - value: 14 - - name: Div_2_15 - description: Divide RNG clock by 2^15 - value: 15 + - name: NoDiv + description: Internal RNG clock after divider is similar to incoming RNG clock + value: 0 + - name: Div_2_1 + description: Divide RNG clock by 2^1 + value: 1 + - name: Div_2_2 + description: Divide RNG clock by 2^2 + value: 2 + - name: Div_2_3 + description: Divide RNG clock by 2^3 + value: 3 + - name: Div_2_4 + description: Divide RNG clock by 2^4 + value: 4 + - name: Div_2_5 + description: Divide RNG clock by 2^5 + value: 5 + - name: Div_2_6 + description: Divide RNG clock by 2^6 + value: 6 + - name: Div_2_7 + description: Divide RNG clock by 2^7 + value: 7 + - name: Div_2_8 + description: Divide RNG clock by 2^8 + value: 8 + - name: Div_2_9 + description: Divide RNG clock by 2^9 + value: 9 + - name: Div_2_10 + description: Divide RNG clock by 2^10 + value: 10 + - name: Div_2_11 + description: Divide RNG clock by 2^11 + value: 11 + - name: Div_2_12 + description: Divide RNG clock by 2^12 + value: 12 + - name: Div_2_13 + description: Divide RNG clock by 2^13 + value: 13 + - name: Div_2_14 + description: Divide RNG clock by 2^14 + value: 14 + - name: Div_2_15 + description: Divide RNG clock by 2^15 + value: 15 enum/HTCFG: bit_size: 32 variants: - - name: Recommended - description: Recommended value for RNG certification (0x0000_AA74) - value: 43636 - - name: Magic - description: Magic number to be written before any write (0x1759_0ABC) - value: 391711420 + - name: Recommended + description: Recommended value for RNG certification (0x0000_AA74) + value: 43636 + - name: Magic + description: Magic number to be written before any write (0x1759_0ABC) + value: 391711420 enum/NISTC: bit_size: 1 variants: - - name: Default - description: Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used - value: 0 - - name: Custom - description: Custom values for NIST compliant RNG - value: 1 + - name: Default + description: Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used + value: 0 + - name: Custom + description: Custom values for NIST compliant RNG + value: 1 enum/RNG_CONFIG1: bit_size: 6 variants: - - name: ConfigA - description: Recommended value for config A (NIST certifiable) - value: 15 - - name: ConfigB - description: Recommended value for config B (not NIST certifiable) - value: 24 + - name: ConfigA + description: Recommended value for config A (NIST certifiable) + value: 15 + - name: ConfigB + description: Recommended value for config B (not NIST certifiable) + value: 24 enum/RNG_CONFIG2: bit_size: 3 variants: - - name: ConfigA_B - description: Recommended value for config A and B - value: 0 + - name: ConfigA_B + description: Recommended value for config A and B + value: 0 enum/RNG_CONFIG3: bit_size: 4 variants: - - name: ConfigB - description: Recommended value for config B (not NIST certifiable) - value: 0 - - name: ConfigA - description: Recommended value for config A (NIST certifiable) - value: 13 + - name: ConfigB + description: Recommended value for config B (not NIST certifiable) + value: 0 + - name: ConfigA + description: Recommended value for config A (NIST certifiable) + value: 13 diff --git a/data/registers/rng_v3.yaml b/data/registers/rng_v3.yaml index 5530968..7d59727 100644 --- a/data/registers/rng_v3.yaml +++ b/data/registers/rng_v3.yaml @@ -1,196 +1,195 @@ ---- block/RNG: description: Random number generator items: - - name: CR - description: control register - byte_offset: 0 - fieldset: CR - - name: SR - description: status register - byte_offset: 4 - fieldset: SR - - name: DR - description: data register - byte_offset: 8 - access: Read - - name: HTCR - description: health test control register - byte_offset: 16 - fieldset: HTCR + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: SR + description: status register + byte_offset: 4 + fieldset: SR + - name: DR + description: data register + byte_offset: 8 + access: Read + - name: HTCR + description: health test control register + byte_offset: 16 + fieldset: HTCR fieldset/CR: description: control register fields: - - name: RNGEN - description: Random number generator enable - bit_offset: 2 - bit_size: 1 - - name: IE - description: Interrupt enable - bit_offset: 3 - bit_size: 1 - - name: CED - description: Clock error detection - bit_offset: 5 - bit_size: 1 - - name: ARDIS - description: Auto reset disable - bit_offset: 7 - bit_size: 1 - - name: RNG_CONFIG3 - description: RNG configuration 3 - bit_offset: 8 - bit_size: 4 - enum: RNG_CONFIG3 - - name: NISTC - description: Non NIST compliant - bit_offset: 12 - bit_size: 1 - enum: NISTC - - name: RNG_CONFIG2 - description: RNG configuration 2 - bit_offset: 13 - bit_size: 3 - enum: RNG_CONFIG2 - - name: CLKDIV - description: Clock divider factor - bit_offset: 16 - bit_size: 4 - enum: CLKDIV - - name: RNG_CONFIG1 - description: RNG configuration 1 - bit_offset: 20 - bit_size: 6 - enum: RNG_CONFIG1 - - name: CONDRST - description: Conditioning soft reset - bit_offset: 30 - bit_size: 1 - - name: CONFIGLOCK - description: Config Lock - bit_offset: 31 - bit_size: 1 -fieldset/SR: - description: status register - fields: - - name: DRDY - description: Data ready - bit_offset: 0 - bit_size: 1 - - name: CECS - description: Clock error current status - bit_offset: 1 - bit_size: 1 - - name: SECS - description: Seed error current status - bit_offset: 2 - bit_size: 1 - - name: CEIS - description: Clock error interrupt status - bit_offset: 5 - bit_size: 1 - - name: SEIS - description: Seed error interrupt status - bit_offset: 6 - bit_size: 1 + - name: RNGEN + description: Random number generator enable + bit_offset: 2 + bit_size: 1 + - name: IE + description: Interrupt enable + bit_offset: 3 + bit_size: 1 + - name: CED + description: Clock error detection + bit_offset: 5 + bit_size: 1 + - name: ARDIS + description: Auto reset disable + bit_offset: 7 + bit_size: 1 + - name: RNG_CONFIG3 + description: RNG configuration 3 + bit_offset: 8 + bit_size: 4 + enum: RNG_CONFIG3 + - name: NISTC + description: Non NIST compliant + bit_offset: 12 + bit_size: 1 + enum: NISTC + - name: RNG_CONFIG2 + description: RNG configuration 2 + bit_offset: 13 + bit_size: 3 + enum: RNG_CONFIG2 + - name: CLKDIV + description: Clock divider factor + bit_offset: 16 + bit_size: 4 + enum: CLKDIV + - name: RNG_CONFIG1 + description: RNG configuration 1 + bit_offset: 20 + bit_size: 6 + enum: RNG_CONFIG1 + - name: CONDRST + description: Conditioning soft reset + bit_offset: 30 + bit_size: 1 + - name: CONFIGLOCK + description: Config Lock + bit_offset: 31 + bit_size: 1 fieldset/HTCR: description: Health test control register fields: - - name: HTCFG - description: Health test configuration - bit_offset: 0 - bit_size: 32 - enum: HTCFG + - name: HTCFG + description: Health test configuration + bit_offset: 0 + bit_size: 32 + enum: HTCFG +fieldset/SR: + description: status register + fields: + - name: DRDY + description: Data ready + bit_offset: 0 + bit_size: 1 + - name: CECS + description: Clock error current status + bit_offset: 1 + bit_size: 1 + - name: SECS + description: Seed error current status + bit_offset: 2 + bit_size: 1 + - name: CEIS + description: Clock error interrupt status + bit_offset: 5 + bit_size: 1 + - name: SEIS + description: Seed error interrupt status + bit_offset: 6 + bit_size: 1 enum/CLKDIV: bit_size: 4 variants: - - name: NoDiv - description: Internal RNG clock after divider is similar to incoming RNG clock - value: 0 - - name: Div_2_1 - description: Divide RNG clock by 2^1 - value: 1 - - name: Div_2_2 - description: Divide RNG clock by 2^2 - value: 2 - - name: Div_2_3 - description: Divide RNG clock by 2^3 - value: 3 - - name: Div_2_4 - description: Divide RNG clock by 2^4 - value: 4 - - name: Div_2_5 - description: Divide RNG clock by 2^5 - value: 5 - - name: Div_2_6 - description: Divide RNG clock by 2^6 - value: 6 - - name: Div_2_7 - description: Divide RNG clock by 2^7 - value: 7 - - name: Div_2_8 - description: Divide RNG clock by 2^8 - value: 8 - - name: Div_2_9 - description: Divide RNG clock by 2^9 - value: 9 - - name: Div_2_10 - description: Divide RNG clock by 2^10 - value: 10 - - name: Div_2_11 - description: Divide RNG clock by 2^11 - value: 11 - - name: Div_2_12 - description: Divide RNG clock by 2^12 - value: 12 - - name: Div_2_13 - description: Divide RNG clock by 2^13 - value: 13 - - name: Div_2_14 - description: Divide RNG clock by 2^14 - value: 14 - - name: Div_2_15 - description: Divide RNG clock by 2^15 - value: 15 + - name: NoDiv + description: Internal RNG clock after divider is similar to incoming RNG clock + value: 0 + - name: Div_2_1 + description: Divide RNG clock by 2^1 + value: 1 + - name: Div_2_2 + description: Divide RNG clock by 2^2 + value: 2 + - name: Div_2_3 + description: Divide RNG clock by 2^3 + value: 3 + - name: Div_2_4 + description: Divide RNG clock by 2^4 + value: 4 + - name: Div_2_5 + description: Divide RNG clock by 2^5 + value: 5 + - name: Div_2_6 + description: Divide RNG clock by 2^6 + value: 6 + - name: Div_2_7 + description: Divide RNG clock by 2^7 + value: 7 + - name: Div_2_8 + description: Divide RNG clock by 2^8 + value: 8 + - name: Div_2_9 + description: Divide RNG clock by 2^9 + value: 9 + - name: Div_2_10 + description: Divide RNG clock by 2^10 + value: 10 + - name: Div_2_11 + description: Divide RNG clock by 2^11 + value: 11 + - name: Div_2_12 + description: Divide RNG clock by 2^12 + value: 12 + - name: Div_2_13 + description: Divide RNG clock by 2^13 + value: 13 + - name: Div_2_14 + description: Divide RNG clock by 2^14 + value: 14 + - name: Div_2_15 + description: Divide RNG clock by 2^15 + value: 15 enum/HTCFG: bit_size: 32 variants: - - name: Recommended - description: Recommended value for RNG certification (0x0000_AA74) - value: 43636 - - name: Magic - description: Magic number to be written before any write (0x1759_0ABC) - value: 391711420 + - name: Recommended + description: Recommended value for RNG certification (0x0000_AA74) + value: 43636 + - name: Magic + description: Magic number to be written before any write (0x1759_0ABC) + value: 391711420 enum/NISTC: bit_size: 1 variants: - - name: Default - description: Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used - value: 0 - - name: Custom - description: Custom values for NIST compliant RNG - value: 1 + - name: Default + description: Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used + value: 0 + - name: Custom + description: Custom values for NIST compliant RNG + value: 1 enum/RNG_CONFIG1: bit_size: 6 variants: - - name: ConfigA - description: Recommended value for config A (NIST certifiable) - value: 15 - - name: ConfigB - description: Recommended value for config B (not NIST certifiable) - value: 24 + - name: ConfigA + description: Recommended value for config A (NIST certifiable) + value: 15 + - name: ConfigB + description: Recommended value for config B (not NIST certifiable) + value: 24 enum/RNG_CONFIG2: bit_size: 3 variants: - - name: ConfigA_B - description: Recommended value for config A and B - value: 0 + - name: ConfigA_B + description: Recommended value for config A and B + value: 0 enum/RNG_CONFIG3: bit_size: 4 variants: - - name: ConfigB - description: Recommended value for config B (not NIST certifiable) - value: 0 - - name: ConfigA - description: Recommended value for config A (NIST certifiable) - value: 13 + - name: ConfigB + description: Recommended value for config B (not NIST certifiable) + value: 0 + - name: ConfigA + description: Recommended value for config A (NIST certifiable) + value: 13 diff --git a/data/registers/rtc_v1.yaml b/data/registers/rtc_v1.yaml index 50d3fff..53afc30 100644 --- a/data/registers/rtc_v1.yaml +++ b/data/registers/rtc_v1.yaml @@ -1,168 +1,167 @@ ---- block/RTC: description: Real-time clock items: - - name: CRH - description: Control Register High - byte_offset: 0 - fieldset: CRH - - name: CRL - description: Control Register Low - byte_offset: 4 - fieldset: CRL - - name: PRLH - description: Prescaler Load Register High - byte_offset: 8 - access: Write - fieldset: PRLH - - name: PRLL - description: Prescaler Load Register Low - byte_offset: 12 - access: Write - fieldset: PRLL - - name: DIVH - description: Prescaler Divider Register High - byte_offset: 16 - access: Read - fieldset: DIVH - - name: DIVL - description: Prescaler Divider Register Low - byte_offset: 20 - access: Read - fieldset: DIVL - - name: CNTH - description: Counter Register High - byte_offset: 24 - fieldset: CNTH - - name: CNTL - description: Counter Register Low - byte_offset: 28 - fieldset: CNTL - - name: ALRH - description: Alarm Register High - byte_offset: 32 - access: Write - fieldset: ALRH - - name: ALRL - description: Alarm Register Low - byte_offset: 36 - access: Write - fieldset: ALRL + - name: CRH + description: Control Register High + byte_offset: 0 + fieldset: CRH + - name: CRL + description: Control Register Low + byte_offset: 4 + fieldset: CRL + - name: PRLH + description: Prescaler Load Register High + byte_offset: 8 + access: Write + fieldset: PRLH + - name: PRLL + description: Prescaler Load Register Low + byte_offset: 12 + access: Write + fieldset: PRLL + - name: DIVH + description: Prescaler Divider Register High + byte_offset: 16 + access: Read + fieldset: DIVH + - name: DIVL + description: Prescaler Divider Register Low + byte_offset: 20 + access: Read + fieldset: DIVL + - name: CNTH + description: Counter Register High + byte_offset: 24 + fieldset: CNTH + - name: CNTL + description: Counter Register Low + byte_offset: 28 + fieldset: CNTL + - name: ALRH + description: Alarm Register High + byte_offset: 32 + access: Write + fieldset: ALRH + - name: ALRL + description: Alarm Register Low + byte_offset: 36 + access: Write + fieldset: ALRL fieldset/ALRH: description: Alarm Register High fields: - - name: ALRH - description: Alarm register high - bit_offset: 0 - bit_size: 16 + - name: ALRH + description: Alarm register high + bit_offset: 0 + bit_size: 16 fieldset/ALRL: description: Alarm Register Low fields: - - name: ALRL - description: Alarm register low - bit_offset: 0 - bit_size: 16 + - name: ALRL + description: Alarm register low + bit_offset: 0 + bit_size: 16 fieldset/CNTH: description: Counter Register High fields: - - name: CNTH - description: Counter register high - bit_offset: 0 - bit_size: 16 + - name: CNTH + description: Counter register high + bit_offset: 0 + bit_size: 16 fieldset/CNTL: description: Counter Register Low fields: - - name: CNTL - description: Counter register low - bit_offset: 0 - bit_size: 16 + - name: CNTL + description: Counter register low + bit_offset: 0 + bit_size: 16 fieldset/CRH: description: Control Register High fields: - - name: SECIE - description: Second interrupt enable - bit_offset: 0 - bit_size: 1 - - name: ALRIE - description: Alarm interrupt enable - bit_offset: 1 - bit_size: 1 - - name: OWIE - description: Overflow interrupt enable - bit_offset: 2 - bit_size: 1 + - name: SECIE + description: Second interrupt enable + bit_offset: 0 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + bit_offset: 1 + bit_size: 1 + - name: OWIE + description: Overflow interrupt enable + bit_offset: 2 + bit_size: 1 fieldset/CRL: description: Control Register Low fields: - - name: SECF - description: Second flag - bit_offset: 0 - bit_size: 1 - - name: ALRF - description: Alarm flag - bit_offset: 1 - bit_size: 1 - - name: OWF - description: Overflow flag - bit_offset: 2 - bit_size: 1 - - name: RSF - description: Registers synchronized flag - bit_offset: 3 - bit_size: 1 - - name: CNF - description: Configuration flag - bit_offset: 4 - bit_size: 1 - enum: CNF - - name: RTOFF - description: RTC operation OFF - bit_offset: 5 - bit_size: 1 - enum: RTOFF + - name: SECF + description: Second flag + bit_offset: 0 + bit_size: 1 + - name: ALRF + description: Alarm flag + bit_offset: 1 + bit_size: 1 + - name: OWF + description: Overflow flag + bit_offset: 2 + bit_size: 1 + - name: RSF + description: Registers synchronized flag + bit_offset: 3 + bit_size: 1 + - name: CNF + description: Configuration flag + bit_offset: 4 + bit_size: 1 + enum: CNF + - name: RTOFF + description: RTC operation OFF + bit_offset: 5 + bit_size: 1 + enum: RTOFF fieldset/DIVH: description: Prescaler Divider Register High fields: - - name: DIVH - description: Prescaler divider register high - bit_offset: 0 - bit_size: 4 + - name: DIVH + description: Prescaler divider register high + bit_offset: 0 + bit_size: 4 fieldset/DIVL: description: Prescaler Divider Register Low fields: - - name: DIVL - description: Prescaler divider register low - bit_offset: 0 - bit_size: 16 + - name: DIVL + description: Prescaler divider register low + bit_offset: 0 + bit_size: 16 fieldset/PRLH: description: Prescaler Load Register High fields: - - name: PRLH - description: Prescaler load register high - bit_offset: 0 - bit_size: 4 + - name: PRLH + description: Prescaler load register high + bit_offset: 0 + bit_size: 4 fieldset/PRLL: description: Prescaler Load Register Low fields: - - name: PRLL - description: Prescaler divider register low - bit_offset: 0 - bit_size: 16 + - name: PRLL + description: Prescaler divider register low + bit_offset: 0 + bit_size: 16 enum/CNF: bit_size: 1 variants: - - name: Exit - description: Exit configuration mode (start update of RTC registers) - value: 0 - - name: Enter - description: Enter configuration mode - value: 1 + - name: Exit + description: Exit configuration mode (start update of RTC registers) + value: 0 + - name: Enter + description: Enter configuration mode + value: 1 enum/RTOFF: bit_size: 1 variants: - - name: Enabled - description: Last write operation on RTC registers is still ongoing - value: 0 - - name: Disabled - description: Last write operation on RTC registers terminated - value: 1 + - name: Enabled + description: Last write operation on RTC registers is still ongoing + value: 0 + - name: Disabled + description: Last write operation on RTC registers terminated + value: 1 diff --git a/data/registers/rtc_v2f0.yaml b/data/registers/rtc_v2f0.yaml index 0ce88e7..395ba61 100644 --- a/data/registers/rtc_v2f0.yaml +++ b/data/registers/rtc_v2f0.yaml @@ -1,840 +1,839 @@ ---- block/RTC: description: Real-time clock items: - - name: TR - description: Time register - byte_offset: 0 - fieldset: TR - - name: DR - description: Date register - byte_offset: 4 - fieldset: DR - - name: CR - description: Control register - byte_offset: 8 - fieldset: CR - - name: ISR - description: Initialization and status register - byte_offset: 12 - fieldset: ISR - - name: PRER - description: Prescaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: Wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: ALRMR - description: Alarm register - array: - len: 1 - stride: 4 - byte_offset: 28 - fieldset: ALRMR - - name: WPR - description: Write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: SSR - description: Sub second register - byte_offset: 40 - access: Read - fieldset: SSR - - name: SHIFTR - description: Shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TSTR - description: Timestamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: Timestamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TSSSR - description: Timestamp sub second register - byte_offset: 56 - access: Read - fieldset: TSSSR - - name: CALR - description: Calibration register - byte_offset: 60 - fieldset: CALR - - name: TAFCR - description: Tamper and alternate function configuration register - byte_offset: 64 - fieldset: TAFCR - - name: ALRMSSR - description: Alarm sub second register - array: - len: 1 - stride: 4 - byte_offset: 68 - fieldset: ALRMSSR - - name: BKPR - description: Backup register - array: - len: 5 - stride: 4 - byte_offset: 80 - fieldset: BKPR + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMR + description: Alarm register + array: + len: 1 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAFCR + description: Tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAFCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 1 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: BKPR + description: Backup register + array: + len: 5 + stride: 4 + byte_offset: 80 + fieldset: BKPR fieldset/ALRMR: description: Alarm register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMR_MSK - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMR_MSK - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMR_PM - - name: MSK3 - description: Alarm hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMR_MSK - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMR_WDSEL - - name: MSK4 - description: Alarm date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMR_MSK + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK fieldset/ALRMSSR: description: Alarm sub second register fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 4 + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 fieldset/BKPR: description: Backup register fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/CALR: description: Calibration register fields: - - name: CALM - description: Calibration minus - bit_offset: 0 - bit_size: 9 - - name: CALW16 - description: Use a 16-second calibration cycle period - bit_offset: 13 - bit_size: 1 - enum: CALW16 - - name: CALW8 - description: Use an 8-second calibration cycle period - bit_offset: 14 - bit_size: 1 - enum: CALW8 - - name: CALP - description: Increase frequency of RTC by 488.5 ppm - bit_offset: 15 - bit_size: 1 - enum: CALP + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP fieldset/CR: description: Control register fields: - - name: WUCKSEL - description: Wakeup clock selection - bit_offset: 0 - bit_size: 3 - enum: WUCKSEL - - name: TSEDGE - description: Timestamp event active edge - bit_offset: 3 - bit_size: 1 - enum: TSEDGE - - name: REFCKON - description: Reference clock detection enable (50 or 60 Hz) - bit_offset: 4 - bit_size: 1 - enum: REFCKON - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - - name: FMT - description: Hour format - bit_offset: 6 - bit_size: 1 - enum: FMT - - name: ALRE - description: Alarm enable - bit_offset: 8 - bit_size: 1 - array: - len: 1 - stride: 1 - - name: WUTE - description: Wakeup timer enable - bit_offset: 10 - bit_size: 1 - - name: TSE - description: Timestamp enable - bit_offset: 11 - bit_size: 1 - - name: ALRIE - description: Alarm interrupt enable - bit_offset: 12 - bit_size: 1 - array: - len: 1 - stride: 1 - - name: WUTIE - description: Wakeup timer interrupt enable - bit_offset: 14 - bit_size: 1 - - name: TSIE - description: Timestamp interrupt enable - bit_offset: 15 - bit_size: 1 - - name: ADD1H - description: Add 1 hour (summer time change) - bit_offset: 16 - bit_size: 1 - - name: SUB1H - description: Subtract 1 hour (winter time change) - bit_offset: 17 - bit_size: 1 - - name: BKP - description: Backup - bit_offset: 18 - bit_size: 1 - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - enum: COSEL - - name: POL - description: Output polarity - bit_offset: 20 - bit_size: 1 - enum: POL - - name: OSEL - description: Output selection - bit_offset: 21 - bit_size: 2 - enum: OSEL - - name: COE - description: Calibration output enable - bit_offset: 23 - bit_size: 1 + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRE + description: Alarm enable + bit_offset: 8 + bit_size: 1 + array: + len: 1 + stride: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + bit_offset: 12 + bit_size: 1 + array: + len: 1 + stride: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 fieldset/DR: description: Date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 fieldset/ISR: description: Initialization and status register fields: - - name: ALRWF - description: Alarm write flag - bit_offset: 0 - bit_size: 1 - array: - len: 1 - stride: 1 - enum: ALRWF - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - - name: RSF - description: Registers synchronization flag - bit_offset: 5 - bit_size: 1 - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - enum: INIT - - name: ALRF - description: Alarm flag - bit_offset: 8 - bit_size: 1 - array: - len: 1 - stride: 1 - - name: WUTF - description: Wakeup timer flag - bit_offset: 10 - bit_size: 1 - - name: TSF - description: Timestamp flag - bit_offset: 11 - bit_size: 1 - - name: TSOVF - description: Timestamp overflow flag - bit_offset: 12 - bit_size: 1 - - name: TAMPF - description: Tamper detection flag - bit_offset: 13 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: RECALPF - description: Recalibration pending flag - bit_offset: 16 - bit_size: 1 + - name: ALRWF + description: Alarm write flag + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 1 + enum: ALRWF + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + bit_offset: 8 + bit_size: 1 + array: + len: 1 + stride: 1 + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + - name: TAMPF + description: Tamper detection flag + bit_offset: 13 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 fieldset/PRER: description: Prescaler register fields: - - name: PREDIV_S - description: Synchronous prescaler factor - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: Asynchronous prescaler factor - bit_offset: 16 - bit_size: 7 + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 fieldset/SHIFTR: description: Shift control register fields: - - name: SUBFS - description: Subtract a fraction of a second - bit_offset: 0 - bit_size: 15 - - name: ADD1S - description: Add one second - bit_offset: 31 - bit_size: 1 + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 fieldset/SSR: description: Sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TAFCR: description: Tamper and alternate function configuration register fields: - - name: TAMPE - description: Tamper detection enable - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 5 - - name: TAMPTRG - description: Active level for tamper - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 5 - enum: TAMPTRG - - name: TAMPIE - description: Tamper interrupt enable - bit_offset: 2 - bit_size: 1 - - name: TAMPTS - description: Activate timestamp on tamper detection event - bit_offset: 7 - bit_size: 1 - - name: TAMPFREQ - description: Tamper sampling frequency - bit_offset: 8 - bit_size: 3 - enum: TAMPFREQ - - name: TAMPFLT - description: Tamper filter count - bit_offset: 11 - bit_size: 2 - enum: TAMPFLT - - name: TAMPPRCH - description: Tamper precharge duration - bit_offset: 13 - bit_size: 2 - enum: TAMPPRCH - - name: TAMPPUDIS - description: Tamper pull-up disable - bit_offset: 15 - bit_size: 1 - enum: TAMPPUDIS - - name: PC13VALUE - description: PC13 value - bit_offset: 18 - bit_size: 1 - enum: PCVALUE - - name: PC13MODE - description: PC13 mode - bit_offset: 19 - bit_size: 1 - enum: PCMODE - - name: PC14VALUE - description: PC14 value - bit_offset: 20 - bit_size: 1 - enum: PCVALUE - - name: PC14MODE - description: PC14 mode - bit_offset: 21 - bit_size: 1 - enum: PCMODE - - name: PC15VALUE - description: PC15 value - bit_offset: 22 - bit_size: 1 - enum: PCVALUE - - name: PC15MODE - description: PC15 mode - bit_offset: 23 - bit_size: 1 - enum: PCMODE + - name: TAMPE + description: Tamper detection enable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 5 + - name: TAMPTRG + description: Active level for tamper + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 5 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: PC13VALUE + description: PC13 value + bit_offset: 18 + bit_size: 1 + enum: PCVALUE + - name: PC13MODE + description: PC13 mode + bit_offset: 19 + bit_size: 1 + enum: PCMODE + - name: PC14VALUE + description: PC14 value + bit_offset: 20 + bit_size: 1 + enum: PCVALUE + - name: PC14MODE + description: PC14 mode + bit_offset: 21 + bit_size: 1 + enum: PCMODE + - name: PC15VALUE + description: PC15 value + bit_offset: 22 + bit_size: 1 + enum: PCVALUE + - name: PC15MODE + description: PC15 mode + bit_offset: 23 + bit_size: 1 + enum: PCMODE fieldset/TR: description: Time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/TSDR: description: Timestamp date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 fieldset/TSSSR: description: Timestamp sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TSTR: description: Timestamp time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/WPR: description: Write protection register fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 fieldset/WUTR: description: Wakeup timer register fields: - - name: WUT - description: Wakeup auto-reload value bits - bit_offset: 0 - bit_size: 16 + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 enum/ALRMR_MSK: bit_size: 1 variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 enum/ALRMR_PM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/ALRMR_WDSEL: bit_size: 1 variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care" - value: 1 + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 enum/ALRWF: bit_size: 1 variants: - - name: UpdateNotAllowed - description: Alarm update not allowed - value: 0 - - name: UpdateAllowed - description: Alarm update allowed - value: 1 + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 enum/AMPM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/CALP: bit_size: 1 variants: - - name: NoChange - description: No RTCCLK pulses are added - value: 0 - - name: IncreaseFreq - description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - value: 1 + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 enum/CALW16: bit_size: 1 variants: - - name: Sixteen_Second - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" - value: 1 + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 enum/CALW8: bit_size: 1 variants: - - name: Eight_Second - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 enum/COSEL: bit_size: 1 variants: - - name: CalFreq_512Hz - description: Calibration output is 512 Hz (with default prescaler setting) - value: 0 - - name: CalFreq_1Hz - description: Calibration output is 1 Hz (with default prescaler setting) - value: 1 + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 enum/FMT: bit_size: 1 variants: - - name: Twenty_Four_Hour - description: 24 hour/day format - value: 0 - - name: AM_PM - description: AM/PM hour format - value: 1 + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 enum/INIT: bit_size: 1 variants: - - name: FreeRunningMode - description: Free running mode - value: 0 - - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." - value: 1 + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 enum/OSEL: bit_size: 2 variants: - - name: Disabled - description: Output disabled - value: 0 - - name: AlarmA - description: Alarm A output enabled - value: 1 - - name: Wakeup - description: Wakeup output enabled - value: 3 + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: Wakeup + description: Wakeup output enabled + value: 3 enum/PCMODE: bit_size: 1 variants: - - name: Floating - description: PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode - value: 0 - - name: PushPull - description: PCx is forced to push-pull output if LSE is disabled - value: 1 + - name: Floating + description: PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode + value: 0 + - name: PushPull + description: PCx is forced to push-pull output if LSE is disabled + value: 1 enum/PCVALUE: bit_size: 1 variants: - - name: Low - description: "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low" - value: 0 - - name: High - description: "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high" - value: 1 + - name: Low + description: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low + value: 0 + - name: High + description: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high + value: 1 enum/POL: bit_size: 1 variants: - - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 0 - - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 1 + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 enum/REFCKON: bit_size: 1 variants: - - name: Disabled - description: RTC_REFIN detection disabled - value: 0 - - name: Enabled - description: RTC_REFIN detection enabled - value: 1 + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 enum/TAMPFLT: bit_size: 2 variants: - - name: Immediate - description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - value: 0 - - name: Samples2 - description: Tamper event is activated after 2 consecutive samples at the active level - value: 1 - - name: Samples4 - description: Tamper event is activated after 4 consecutive samples at the active level - value: 2 - - name: Samples8 - description: Tamper event is activated after 8 consecutive samples at the active level - value: 3 + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 enum/TAMPFREQ: bit_size: 3 variants: - - name: Div32768 - description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - value: 0 - - name: Div16384 - description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - value: 1 - - name: Div8192 - description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - value: 2 - - name: Div4096 - description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - value: 3 - - name: Div2048 - description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - value: 4 - - name: Div1024 - description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - value: 5 - - name: Div512 - description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - value: 6 - - name: Div256 - description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - value: 7 + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 enum/TAMPPRCH: bit_size: 2 variants: - - name: Cycles1 - description: 1 RTCCLK cycle - value: 0 - - name: Cycles2 - description: 2 RTCCLK cycles - value: 1 - - name: Cycles4 - description: 4 RTCCLK cycles - value: 2 - - name: Cycles8 - description: 8 RTCCLK cycles - value: 3 + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 enum/TAMPPUDIS: bit_size: 1 variants: - - name: Enabled - description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - value: 0 - - name: Disabled - description: Disable precharge of RTC_TAMPx pins - value: 1 + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 enum/TAMPTRG: bit_size: 1 variants: - - name: RisingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." - value: 0 - - name: FallingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" - value: 1 + - name: RisingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.' + value: 0 + - name: FallingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event' + value: 1 enum/TSEDGE: bit_size: 1 variants: - - name: RisingEdge - description: RTC_TS input rising edge generates a time-stamp event - value: 0 - - name: FallingEdge - description: RTC_TS input falling edge generates a time-stamp event - value: 1 + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 enum/WUCKSEL: bit_size: 3 variants: - - name: Div16 - description: RTC/16 clock is selected - value: 0 - - name: Div8 - description: RTC/8 clock is selected - value: 1 - - name: Div4 - description: RTC/4 clock is selected - value: 2 - - name: Div2 - description: RTC/2 clock is selected - value: 3 - - name: ClockSpare - description: ck_spre (usually 1 Hz) clock is selected - value: 4 - - name: ClockSpareWithOffset - description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - value: 6 + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 diff --git a/data/registers/rtc_v2f2.yaml b/data/registers/rtc_v2f2.yaml index 571793c..6edb8f6 100644 --- a/data/registers/rtc_v2f2.yaml +++ b/data/registers/rtc_v2f2.yaml @@ -1,591 +1,590 @@ ---- block/RTC: description: Real-time clock items: - - name: TR - description: Time register - byte_offset: 0 - fieldset: TR - - name: DR - description: Date register - byte_offset: 4 - fieldset: DR - - name: CR - description: Control register - byte_offset: 8 - fieldset: CR - - name: ISR - description: Initialization and status register - byte_offset: 12 - fieldset: ISR - - name: PRER - description: Prescaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: Wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: CALIBR - description: Calibration register - byte_offset: 24 - fieldset: CALIBR - - name: ALRMR - description: Alarm register - array: - len: 2 - stride: 4 - byte_offset: 28 - fieldset: ALRMR - - name: WPR - description: Write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: TSTR - description: Timestamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: Timestamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TAFCR - description: Tamper and alternate function configuration register - byte_offset: 64 - fieldset: TAFCR - - name: BKPR - description: Backup register - array: - len: 20 - stride: 4 - byte_offset: 80 - fieldset: BKPR + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CALIBR + description: Calibration register + byte_offset: 24 + fieldset: CALIBR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TAFCR + description: Tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAFCR + - name: BKPR + description: Backup register + array: + len: 20 + stride: 4 + byte_offset: 80 + fieldset: BKPR fieldset/ALRMR: description: Alarm register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMR_MSK - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMR_MSK - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMR_PM - - name: MSK3 - description: Alarm hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMR_MSK - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMR_WDSEL - - name: MSK4 - description: Alarm date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMR_MSK + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK fieldset/BKPR: description: Backup register fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/CALIBR: description: Calibration register fields: - - name: DC - description: Digital calibration - bit_offset: 0 - bit_size: 5 - - name: DCS - description: Digital calibration sign - bit_offset: 7 - bit_size: 1 + - name: DC + description: Digital calibration + bit_offset: 0 + bit_size: 5 + - name: DCS + description: Digital calibration sign + bit_offset: 7 + bit_size: 1 fieldset/CR: description: Control register fields: - - name: WUCKSEL - description: Wakeup clock selection - bit_offset: 0 - bit_size: 3 - enum: WUCKSEL - - name: TSEDGE - description: Timestamp event active edge - bit_offset: 3 - bit_size: 1 - enum: TSEDGE - - name: REFCKON - description: Reference clock detection enable (50 or 60 Hz) - bit_offset: 4 - bit_size: 1 - enum: REFCKON - - name: FMT - description: Hour format - bit_offset: 6 - bit_size: 1 - - name: DCE - description: Coarse digital calibration enable - bit_offset: 7 - bit_size: 1 - - name: ALRE - description: Alarm enable - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTE - description: Wakeup timer enable - bit_offset: 10 - bit_size: 1 - - name: TSE - description: Timestamp enable - bit_offset: 11 - bit_size: 1 - - name: ALRIE - description: Alarm interrupt enable - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTIE - description: Wakeup timer interrupt enable - bit_offset: 14 - bit_size: 1 - - name: TSIE - description: Timestamp interrupt enable - bit_offset: 15 - bit_size: 1 - - name: ADD1H - description: Add 1 hour (summer time change) - bit_offset: 16 - bit_size: 1 - - name: SUB1H - description: Subtract 1 hour (winter time change) - bit_offset: 17 - bit_size: 1 - - name: BKP - description: Backup - bit_offset: 18 - bit_size: 1 - - name: POL - description: Output polarity - bit_offset: 20 - bit_size: 1 - enum: POL - - name: OSEL - description: Output selection - bit_offset: 21 - bit_size: 2 - enum: OSEL - - name: COE - description: Calibration output enable - bit_offset: 23 - bit_size: 1 + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + - name: DCE + description: Coarse digital calibration enable + bit_offset: 7 + bit_size: 1 + - name: ALRE + description: Alarm enable + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 fieldset/DR: description: Date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 fieldset/ISR: description: Initialization and status register fields: - - name: ALRWF - description: Alarm write flag - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: ALRWF - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - - name: RSF - description: Registers synchronization flag - bit_offset: 5 - bit_size: 1 - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - enum: INIT - - name: ALRF - description: Alarm flag - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTF - description: Wakeup timer flag - bit_offset: 10 - bit_size: 1 - - name: TSF - description: Timestamp flag - bit_offset: 11 - bit_size: 1 - - name: TSOVF - description: Timestamp overflow flag - bit_offset: 12 - bit_size: 1 - - name: TAMPF - description: Tamper detection flag - bit_offset: 13 - bit_size: 1 - array: - len: 1 - stride: 1 + - name: ALRWF + description: Alarm write flag + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: ALRWF + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + - name: TAMPF + description: Tamper detection flag + bit_offset: 13 + bit_size: 1 + array: + len: 1 + stride: 1 fieldset/PRER: description: Prescaler register fields: - - name: PREDIV_S - description: Synchronous prescaler factor - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: Asynchronous prescaler factor - bit_offset: 16 - bit_size: 7 + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 fieldset/TAFCR: description: Tamper and alternate function configuration register fields: - - name: TAMPE - description: Tamper detection enable - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - name: TAMPTRG - description: Active level for tamper - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - enum: TAMPTRG - - name: TAMPIE - description: Tamper interrupt enable - bit_offset: 2 - bit_size: 1 - - name: TAMP1INSEL - description: Tamper 1 mapping - bit_offset: 16 - bit_size: 1 - - name: TSINSEL - description: Timestamp mapping - bit_offset: 17 - bit_size: 1 - - name: ALARMOUTTYPE - description: AFO_ALARM output type - bit_offset: 18 - bit_size: 1 + - name: TAMPE + description: Tamper detection enable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - name: TAMPTRG + description: Active level for tamper + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMP1INSEL + description: Tamper 1 mapping + bit_offset: 16 + bit_size: 1 + - name: TSINSEL + description: Timestamp mapping + bit_offset: 17 + bit_size: 1 + - name: ALARMOUTTYPE + description: AFO_ALARM output type + bit_offset: 18 + bit_size: 1 fieldset/TR: description: Time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/TSDR: description: Timestamp date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 fieldset/TSTR: description: Timestamp time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/WPR: description: Write protection register fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 fieldset/WUTR: description: Wakeup timer register fields: - - name: WUT - description: Wakeup auto-reload value bits - bit_offset: 0 - bit_size: 16 + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 enum/ALRMR_MSK: bit_size: 1 variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 enum/ALRMR_PM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/ALRMR_WDSEL: bit_size: 1 variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care" - value: 1 + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 enum/ALRWF: bit_size: 1 variants: - - name: UpdateNotAllowed - description: Alarm update not allowed - value: 0 - - name: UpdateAllowed - description: Alarm update allowed - value: 1 + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 enum/AMPM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/INIT: bit_size: 1 variants: - - name: FreeRunningMode - description: Free running mode - value: 0 - - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." - value: 1 + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 enum/OSEL: bit_size: 2 variants: - - name: Disabled - description: Output disabled - value: 0 - - name: AlarmA - description: Alarm A output enabled - value: 1 - - name: AlarmB - description: Alarm B output enabled - value: 2 - - name: Wakeup - description: Wakeup output enabled - value: 3 + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 enum/POL: bit_size: 1 variants: - - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 0 - - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 1 + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 enum/REFCKON: bit_size: 1 variants: - - name: Disabled - description: RTC_REFIN detection disabled - value: 0 - - name: Enabled - description: RTC_REFIN detection enabled - value: 1 + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 enum/TAMPTRG: bit_size: 1 variants: - - name: RisingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." - value: 0 - - name: FallingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" - value: 1 + - name: RisingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.' + value: 0 + - name: FallingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event' + value: 1 enum/TSEDGE: bit_size: 1 variants: - - name: RisingEdge - description: RTC_TS input rising edge generates a time-stamp event - value: 0 - - name: FallingEdge - description: RTC_TS input falling edge generates a time-stamp event - value: 1 + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 enum/WUCKSEL: bit_size: 3 variants: - - name: Div16 - description: RTC/16 clock is selected - value: 0 - - name: Div8 - description: RTC/8 clock is selected - value: 1 - - name: Div4 - description: RTC/4 clock is selected - value: 2 - - name: Div2 - description: RTC/2 clock is selected - value: 3 - - name: ClockSpare - description: ck_spre (usually 1 Hz) clock is selected - value: 4 - - name: ClockSpareWithOffset - description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - value: 6 + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 diff --git a/data/registers/rtc_v2f3.yaml b/data/registers/rtc_v2f3.yaml index 433f6cc..c93b79d 100644 --- a/data/registers/rtc_v2f3.yaml +++ b/data/registers/rtc_v2f3.yaml @@ -1,848 +1,847 @@ ---- block/RTC: description: Real-time clock items: - - name: TR - description: Time register - byte_offset: 0 - fieldset: TR - - name: DR - description: Date register - byte_offset: 4 - fieldset: DR - - name: CR - description: Control register - byte_offset: 8 - fieldset: CR - - name: ISR - description: Initialization and status register - byte_offset: 12 - fieldset: ISR - - name: PRER - description: Prescaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: Wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: ALRMR - description: Alarm register - array: - len: 2 - stride: 4 - byte_offset: 28 - fieldset: ALRMR - - name: WPR - description: Write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: SSR - description: Sub second register - byte_offset: 40 - access: Read - fieldset: SSR - - name: SHIFTR - description: Shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TSTR - description: Timestamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: Timestamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TSSSR - description: Timestamp sub second register - byte_offset: 56 - access: Read - fieldset: TSSSR - - name: CALR - description: Calibration register - byte_offset: 60 - fieldset: CALR - - name: TAFCR - description: Tamper and alternate function configuration register - byte_offset: 64 - fieldset: TAFCR - - name: ALRMSSR - description: Alarm sub second register - array: - len: 2 - stride: 4 - byte_offset: 68 - fieldset: ALRMSSR - - name: BKPR - description: Backup register - array: - len: 32 - stride: 4 - byte_offset: 80 - fieldset: BKPR + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAFCR + description: Tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAFCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: BKPR + description: Backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR fieldset/ALRMR: description: Alarm register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMR_MSK - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMR_MSK - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMR_PM - - name: MSK3 - description: Alarm hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMR_MSK - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMR_WDSEL - - name: MSK4 - description: Alarm date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMR_MSK + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK fieldset/ALRMSSR: description: Alarm sub second register fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 4 + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 fieldset/BKPR: description: Backup register fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/CALR: description: Calibration register fields: - - name: CALM - description: Calibration minus - bit_offset: 0 - bit_size: 9 - - name: CALW16 - description: Use a 16-second calibration cycle period - bit_offset: 13 - bit_size: 1 - enum: CALW16 - - name: CALW8 - description: Use an 8-second calibration cycle period - bit_offset: 14 - bit_size: 1 - enum: CALW8 - - name: CALP - description: Increase frequency of RTC by 488.5 ppm - bit_offset: 15 - bit_size: 1 - enum: CALP + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP fieldset/CR: description: Control register fields: - - name: WUCKSEL - description: Wakeup clock selection - bit_offset: 0 - bit_size: 3 - enum: WUCKSEL - - name: TSEDGE - description: Timestamp event active edge - bit_offset: 3 - bit_size: 1 - enum: TSEDGE - - name: REFCKON - description: Reference clock detection enable (50 or 60 Hz) - bit_offset: 4 - bit_size: 1 - enum: REFCKON - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - - name: FMT - description: Hour format - bit_offset: 6 - bit_size: 1 - enum: FMT - - name: ALRE - description: Alarm enable - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTE - description: Wakeup timer enable - bit_offset: 10 - bit_size: 1 - - name: TSE - description: Timestamp enable - bit_offset: 11 - bit_size: 1 - - name: ALRIE - description: Alarm interrupt enable - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTIE - description: Wakeup timer interrupt enable - bit_offset: 14 - bit_size: 1 - - name: TSIE - description: Timestamp interrupt enable - bit_offset: 15 - bit_size: 1 - - name: ADD1H - description: Add 1 hour (summer time change) - bit_offset: 16 - bit_size: 1 - - name: SUB1H - description: Subtract 1 hour (winter time change) - bit_offset: 17 - bit_size: 1 - - name: BKP - description: Backup - bit_offset: 18 - bit_size: 1 - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - enum: COSEL - - name: POL - description: Output polarity - bit_offset: 20 - bit_size: 1 - enum: POL - - name: OSEL - description: Output selection - bit_offset: 21 - bit_size: 2 - enum: OSEL - - name: COE - description: Calibration output enable - bit_offset: 23 - bit_size: 1 + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRE + description: Alarm enable + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 fieldset/DR: description: Date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 fieldset/ISR: description: Initialization and status register fields: - - name: ALRWF - description: Alarm write flag - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: ALRWF - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - - name: RSF - description: Registers synchronization flag - bit_offset: 5 - bit_size: 1 - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - enum: INIT - - name: ALRF - description: Alarm flag - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTF - description: Wakeup timer flag - bit_offset: 10 - bit_size: 1 - - name: TSF - description: Timestamp flag - bit_offset: 11 - bit_size: 1 - - name: TSOVF - description: Timestamp overflow flag - bit_offset: 12 - bit_size: 1 - - name: TAMPF - description: Tamper detection flag - bit_offset: 13 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: RECALPF - description: Recalibration pending flag - bit_offset: 16 - bit_size: 1 - enum: RECALPF + - name: ALRWF + description: Alarm write flag + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: ALRWF + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + - name: TAMPF + description: Tamper detection flag + bit_offset: 13 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum: RECALPF fieldset/PRER: description: Prescaler register fields: - - name: PREDIV_S - description: Synchronous prescaler factor - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: Asynchronous prescaler factor - bit_offset: 16 - bit_size: 7 + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 fieldset/SHIFTR: description: Shift control register fields: - - name: SUBFS - description: Subtract a fraction of a second - bit_offset: 0 - bit_size: 15 - - name: ADD1S - description: Add one second - bit_offset: 31 - bit_size: 1 + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 fieldset/SSR: description: Sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TAFCR: description: Tamper and alternate function configuration register fields: - - name: TAMPE - description: Tamper detection enable - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - name: TAMPTRG - description: Active level for tamper - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 3 - enum: TAMPTRG - - name: TAMPIE - description: Tamper interrupt enable - bit_offset: 2 - bit_size: 1 - - name: TAMPTS - description: Activate timestamp on tamper detection event - bit_offset: 7 - bit_size: 1 - - name: TAMPFREQ - description: Tamper sampling frequency - bit_offset: 8 - bit_size: 3 - enum: TAMPFREQ - - name: TAMPFLT - description: Tamper filter count - bit_offset: 11 - bit_size: 2 - enum: TAMPFLT - - name: TAMPPRCH - description: Tamper precharge duration - bit_offset: 13 - bit_size: 2 - enum: TAMPPRCH - - name: TAMPPUDIS - description: Tamper pull-up disable - bit_offset: 15 - bit_size: 1 - enum: TAMPPUDIS - - name: PC13VALUE - description: PC13 value - bit_offset: 18 - bit_size: 1 - enum: PCVALUE - - name: PC13MODE - description: PC13 mode - bit_offset: 19 - bit_size: 1 - enum: PCMODE - - name: PC14VALUE - description: PC14 value - bit_offset: 20 - bit_size: 1 - enum: PCVALUE - - name: PC14MODE - description: PC14 mode - bit_offset: 21 - bit_size: 1 - enum: PCMODE - - name: PC15VALUE - description: PC15 value - bit_offset: 22 - bit_size: 1 - enum: PCVALUE - - name: PC15MODE - description: PC15 mode - bit_offset: 23 - bit_size: 1 - enum: PCMODE + - name: TAMPE + description: Tamper detection enable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - name: TAMPTRG + description: Active level for tamper + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 3 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: PC13VALUE + description: PC13 value + bit_offset: 18 + bit_size: 1 + enum: PCVALUE + - name: PC13MODE + description: PC13 mode + bit_offset: 19 + bit_size: 1 + enum: PCMODE + - name: PC14VALUE + description: PC14 value + bit_offset: 20 + bit_size: 1 + enum: PCVALUE + - name: PC14MODE + description: PC14 mode + bit_offset: 21 + bit_size: 1 + enum: PCMODE + - name: PC15VALUE + description: PC15 value + bit_offset: 22 + bit_size: 1 + enum: PCVALUE + - name: PC15MODE + description: PC15 mode + bit_offset: 23 + bit_size: 1 + enum: PCMODE fieldset/TR: description: Time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/TSDR: description: Timestamp date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 fieldset/TSSSR: description: Timestamp sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TSTR: description: Timestamp time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/WPR: description: Write protection register fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 fieldset/WUTR: description: Wakeup timer register fields: - - name: WUT - description: Wakeup auto-reload value bits - bit_offset: 0 - bit_size: 16 + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 enum/ALRMR_MSK: bit_size: 1 variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 enum/ALRMR_PM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/ALRMR_WDSEL: bit_size: 1 variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care" - value: 1 + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 enum/ALRWF: bit_size: 1 variants: - - name: UpdateNotAllowed - description: Alarm update not allowed - value: 0 - - name: UpdateAllowed - description: Alarm update allowed - value: 1 + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 enum/AMPM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/CALP: bit_size: 1 variants: - - name: NoChange - description: No RTCCLK pulses are added - value: 0 - - name: IncreaseFreq - description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - value: 1 + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 enum/CALW16: bit_size: 1 variants: - - name: Sixteen_Second - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" - value: 1 + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 enum/CALW8: bit_size: 1 variants: - - name: Eight_Second - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 enum/COSEL: bit_size: 1 variants: - - name: CalFreq_512Hz - description: Calibration output is 512 Hz (with default prescaler setting) - value: 0 - - name: CalFreq_1Hz - description: Calibration output is 1 Hz (with default prescaler setting) - value: 1 + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 enum/FMT: bit_size: 1 variants: - - name: Twenty_Four_Hour - description: 24 hour/day format - value: 0 - - name: AM_PM - description: AM/PM hour format - value: 1 + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 enum/INIT: bit_size: 1 variants: - - name: FreeRunningMode - description: Free running mode - value: 0 - - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." - value: 1 + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 enum/OSEL: bit_size: 2 variants: - - name: Disabled - description: Output disabled - value: 0 - - name: AlarmA - description: Alarm A output enabled - value: 1 - - name: AlarmB - description: Alarm B output enabled - value: 2 - - name: Wakeup - description: Wakeup output enabled - value: 3 + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 enum/PCMODE: bit_size: 1 variants: - - name: Floating - description: PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode - value: 0 - - name: PushPull - description: PCx is forced to push-pull output if LSE is disabled - value: 1 + - name: Floating + description: PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode + value: 0 + - name: PushPull + description: PCx is forced to push-pull output if LSE is disabled + value: 1 enum/PCVALUE: bit_size: 1 variants: - - name: Low - description: "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low" - value: 0 - - name: High - description: "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high" - value: 1 + - name: Low + description: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low + value: 0 + - name: High + description: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high + value: 1 enum/POL: bit_size: 1 variants: - - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 0 - - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 1 + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 enum/RECALPF: bit_size: 1 variants: - - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" - value: 1 + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 enum/REFCKON: bit_size: 1 variants: - - name: Disabled - description: RTC_REFIN detection disabled - value: 0 - - name: Enabled - description: RTC_REFIN detection enabled - value: 1 + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 enum/TAMPFLT: bit_size: 2 variants: - - name: Immediate - description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - value: 0 - - name: Samples2 - description: Tamper event is activated after 2 consecutive samples at the active level - value: 1 - - name: Samples4 - description: Tamper event is activated after 4 consecutive samples at the active level - value: 2 - - name: Samples8 - description: Tamper event is activated after 8 consecutive samples at the active level - value: 3 + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 enum/TAMPFREQ: bit_size: 3 variants: - - name: Div32768 - description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - value: 0 - - name: Div16384 - description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - value: 1 - - name: Div8192 - description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - value: 2 - - name: Div4096 - description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - value: 3 - - name: Div2048 - description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - value: 4 - - name: Div1024 - description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - value: 5 - - name: Div512 - description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - value: 6 - - name: Div256 - description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - value: 7 + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 enum/TAMPPRCH: bit_size: 2 variants: - - name: Cycles1 - description: 1 RTCCLK cycle - value: 0 - - name: Cycles2 - description: 2 RTCCLK cycles - value: 1 - - name: Cycles4 - description: 4 RTCCLK cycles - value: 2 - - name: Cycles8 - description: 8 RTCCLK cycles - value: 3 + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 enum/TAMPPUDIS: bit_size: 1 variants: - - name: Enabled - description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - value: 0 - - name: Disabled - description: Disable precharge of RTC_TAMPx pins - value: 1 + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 enum/TAMPTRG: bit_size: 1 variants: - - name: RisingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." - value: 0 - - name: FallingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" - value: 1 + - name: RisingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.' + value: 0 + - name: FallingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event' + value: 1 enum/TSEDGE: bit_size: 1 variants: - - name: RisingEdge - description: RTC_TS input rising edge generates a time-stamp event - value: 0 - - name: FallingEdge - description: RTC_TS input falling edge generates a time-stamp event - value: 1 + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 enum/WUCKSEL: bit_size: 3 variants: - - name: Div16 - description: RTC/16 clock is selected - value: 0 - - name: Div8 - description: RTC/8 clock is selected - value: 1 - - name: Div4 - description: RTC/4 clock is selected - value: 2 - - name: Div2 - description: RTC/2 clock is selected - value: 3 - - name: ClockSpare - description: ck_spre (usually 1 Hz) clock is selected - value: 4 - - name: ClockSpareWithOffset - description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - value: 6 + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 diff --git a/data/registers/rtc_v2f4.yaml b/data/registers/rtc_v2f4.yaml index f3a945f..ab1a017 100644 --- a/data/registers/rtc_v2f4.yaml +++ b/data/registers/rtc_v2f4.yaml @@ -1,831 +1,830 @@ ---- block/RTC: description: Real-time clock items: - - name: TR - description: Time register - byte_offset: 0 - fieldset: TR - - name: DR - description: Date register - byte_offset: 4 - fieldset: DR - - name: CR - description: Control register - byte_offset: 8 - fieldset: CR - - name: ISR - description: Initialization and status register - byte_offset: 12 - fieldset: ISR - - name: PRER - description: Prescaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: Wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: CALIBR - description: Calibration register - byte_offset: 24 - fieldset: CALIBR - - name: ALRMR - description: Alarm register - array: - len: 2 - stride: 4 - byte_offset: 28 - fieldset: ALRMR - - name: WPR - description: Write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: SSR - description: Sub second register - byte_offset: 40 - access: Read - fieldset: SSR - - name: SHIFTR - description: Shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TSTR - description: Timestamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: Timestamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TSSSR - description: Timestamp sub second register - byte_offset: 56 - access: Read - fieldset: TSSSR - - name: CALR - description: Calibration register - byte_offset: 60 - fieldset: CALR - - name: TAFCR - description: Tamper and alternate function configuration register - byte_offset: 64 - fieldset: TAFCR - - name: ALRMSSR - description: Alarm sub second register - array: - len: 2 - stride: 4 - byte_offset: 68 - fieldset: ALRMSSR - - name: BKPR - description: Backup register - array: - len: 20 - stride: 4 - byte_offset: 80 - fieldset: BKPR + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CALIBR + description: Calibration register + byte_offset: 24 + fieldset: CALIBR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAFCR + description: Tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAFCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: BKPR + description: Backup register + array: + len: 20 + stride: 4 + byte_offset: 80 + fieldset: BKPR fieldset/ALRMR: description: Alarm register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMR_MSK - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMR_MSK - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMR_PM - - name: MSK3 - description: Alarm hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMR_MSK - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMR_WDSEL - - name: MSK4 - description: Alarm date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMR_MSK + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK fieldset/ALRMSSR: description: Alarm sub second register fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 4 + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 fieldset/BKPR: description: Backup register fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/CALIBR: description: Calibration register fields: - - name: DC - description: Digital calibration - bit_offset: 0 - bit_size: 5 - - name: DCS - description: Digital calibration sign - bit_offset: 7 - bit_size: 1 + - name: DC + description: Digital calibration + bit_offset: 0 + bit_size: 5 + - name: DCS + description: Digital calibration sign + bit_offset: 7 + bit_size: 1 fieldset/CALR: description: Calibration register fields: - - name: CALM - description: Calibration minus - bit_offset: 0 - bit_size: 9 - - name: CALW16 - description: Use a 16-second calibration cycle period - bit_offset: 13 - bit_size: 1 - enum: CALW16 - - name: CALW8 - description: Use an 8-second calibration cycle period - bit_offset: 14 - bit_size: 1 - enum: CALW8 - - name: CALP - description: Increase frequency of RTC by 488.5 ppm - bit_offset: 15 - bit_size: 1 - enum: CALP + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP fieldset/CR: description: Control register fields: - - name: WUCKSEL - description: Wakeup clock selection - bit_offset: 0 - bit_size: 3 - enum: WUCKSEL - - name: TSEDGE - description: Timestamp event active edge - bit_offset: 3 - bit_size: 1 - enum: TSEDGE - - name: REFCKON - description: Reference clock detection enable (50 or 60 Hz) - bit_offset: 4 - bit_size: 1 - enum: REFCKON - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - - name: FMT - description: Hour format - bit_offset: 6 - bit_size: 1 - enum: FMT - - name: DCE - description: Coarse digital calibration enable - bit_offset: 7 - bit_size: 1 - - name: ALRE - description: Alarm enable - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTE - description: Wakeup timer enable - bit_offset: 10 - bit_size: 1 - - name: TSE - description: Timestamp enable - bit_offset: 11 - bit_size: 1 - - name: ALRIE - description: Alarm interrupt enable - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTIE - description: Wakeup timer interrupt enable - bit_offset: 14 - bit_size: 1 - - name: TSIE - description: Timestamp interrupt enable - bit_offset: 15 - bit_size: 1 - - name: ADD1H - description: Add 1 hour (summer time change) - bit_offset: 16 - bit_size: 1 - - name: SUB1H - description: Subtract 1 hour (winter time change) - bit_offset: 17 - bit_size: 1 - - name: BKP - description: Backup - bit_offset: 18 - bit_size: 1 - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - enum: COSEL - - name: POL - description: Output polarity - bit_offset: 20 - bit_size: 1 - enum: POL - - name: OSEL - description: Output selection - bit_offset: 21 - bit_size: 2 - enum: OSEL - - name: COE - description: Calibration output enable - bit_offset: 23 - bit_size: 1 + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: DCE + description: Coarse digital calibration enable + bit_offset: 7 + bit_size: 1 + - name: ALRE + description: Alarm enable + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 fieldset/DR: description: Date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 fieldset/ISR: description: Initialization and status register fields: - - name: ALRWF - description: Alarm write flag - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: ALRWF - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - - name: RSF - description: Registers synchronization flag - bit_offset: 5 - bit_size: 1 - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - enum: INIT - - name: ALRF - description: Alarm flag - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTF - description: Wakeup timer flag - bit_offset: 10 - bit_size: 1 - - name: TSF - description: Timestamp flag - bit_offset: 11 - bit_size: 1 - - name: TSOVF - description: Timestamp overflow flag - bit_offset: 12 - bit_size: 1 - - name: TAMPF - description: Tamper detection flag - bit_offset: 13 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: RECALPF - description: Recalibration pending flag - bit_offset: 16 - bit_size: 1 - enum: RECALPF + - name: ALRWF + description: Alarm write flag + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: ALRWF + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + - name: TAMPF + description: Tamper detection flag + bit_offset: 13 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum: RECALPF fieldset/PRER: description: Prescaler register fields: - - name: PREDIV_S - description: Synchronous prescaler factor - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: Asynchronous prescaler factor - bit_offset: 16 - bit_size: 7 + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 fieldset/SHIFTR: description: Shift control register fields: - - name: SUBFS - description: Subtract a fraction of a second - bit_offset: 0 - bit_size: 15 - - name: ADD1S - description: Add one second - bit_offset: 31 - bit_size: 1 + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 fieldset/SSR: description: Sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TAFCR: description: Tamper and alternate function configuration register fields: - - name: TAMPE - description: Tamper detection enable - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - name: TAMPTRG - description: Active level for tamper - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 3 - enum: TAMPTRG - - name: TAMPIE - description: Tamper interrupt enable - bit_offset: 2 - bit_size: 1 - - name: TAMPTS - description: Activate timestamp on tamper detection event - bit_offset: 7 - bit_size: 1 - - name: TAMPFREQ - description: Tamper sampling frequency - bit_offset: 8 - bit_size: 3 - enum: TAMPFREQ - - name: TAMPFLT - description: Tamper filter count - bit_offset: 11 - bit_size: 2 - enum: TAMPFLT - - name: TAMPPRCH - description: Tamper precharge duration - bit_offset: 13 - bit_size: 2 - enum: TAMPPRCH - - name: TAMPPUDIS - description: Tamper pull-up disable - bit_offset: 15 - bit_size: 1 - enum: TAMPPUDIS - - name: TAMP1INSEL - description: Tamper 1 mapping - bit_offset: 16 - bit_size: 1 - - name: TSINSEL - description: Timestamp mapping - bit_offset: 17 - bit_size: 1 - - name: ALARMOUTTYPE - description: AFO_ALARM output type - bit_offset: 18 - bit_size: 1 + - name: TAMPE + description: Tamper detection enable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - name: TAMPTRG + description: Active level for tamper + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 3 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: TAMP1INSEL + description: Tamper 1 mapping + bit_offset: 16 + bit_size: 1 + - name: TSINSEL + description: Timestamp mapping + bit_offset: 17 + bit_size: 1 + - name: ALARMOUTTYPE + description: AFO_ALARM output type + bit_offset: 18 + bit_size: 1 fieldset/TR: description: Time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/TSDR: description: Timestamp date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 fieldset/TSSSR: description: Timestamp sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TSTR: description: Timestamp time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/WPR: description: Write protection register fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 fieldset/WUTR: description: Wakeup timer register fields: - - name: WUT - description: Wakeup auto-reload value bits - bit_offset: 0 - bit_size: 16 + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 enum/ALRMR_MSK: bit_size: 1 variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 enum/ALRMR_PM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/ALRMR_WDSEL: bit_size: 1 variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care" - value: 1 + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 enum/ALRWF: bit_size: 1 variants: - - name: UpdateNotAllowed - description: Alarm update not allowed - value: 0 - - name: UpdateAllowed - description: Alarm update allowed - value: 1 + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 enum/AMPM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/CALP: bit_size: 1 variants: - - name: NoChange - description: No RTCCLK pulses are added - value: 0 - - name: IncreaseFreq - description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - value: 1 + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 enum/CALW16: bit_size: 1 variants: - - name: Sixteen_Second - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" - value: 1 + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 enum/CALW8: bit_size: 1 variants: - - name: Eight_Second - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 enum/COSEL: bit_size: 1 variants: - - name: CalFreq_512Hz - description: Calibration output is 512 Hz (with default prescaler setting) - value: 0 - - name: CalFreq_1Hz - description: Calibration output is 1 Hz (with default prescaler setting) - value: 1 + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 enum/FMT: bit_size: 1 variants: - - name: Twenty_Four_Hour - description: 24 hour/day format - value: 0 - - name: AM_PM - description: AM/PM hour format - value: 1 + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 enum/INIT: bit_size: 1 variants: - - name: FreeRunningMode - description: Free running mode - value: 0 - - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." - value: 1 + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 enum/OSEL: bit_size: 2 variants: - - name: Disabled - description: Output disabled - value: 0 - - name: AlarmA - description: Alarm A output enabled - value: 1 - - name: AlarmB - description: Alarm B output enabled - value: 2 - - name: Wakeup - description: Wakeup output enabled - value: 3 + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 enum/POL: bit_size: 1 variants: - - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 0 - - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 1 + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 enum/RECALPF: bit_size: 1 variants: - - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" - value: 1 + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 enum/REFCKON: bit_size: 1 variants: - - name: Disabled - description: RTC_REFIN detection disabled - value: 0 - - name: Enabled - description: RTC_REFIN detection enabled - value: 1 + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 enum/TAMPFLT: bit_size: 2 variants: - - name: Immediate - description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - value: 0 - - name: Samples2 - description: Tamper event is activated after 2 consecutive samples at the active level - value: 1 - - name: Samples4 - description: Tamper event is activated after 4 consecutive samples at the active level - value: 2 - - name: Samples8 - description: Tamper event is activated after 8 consecutive samples at the active level - value: 3 + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 enum/TAMPFREQ: bit_size: 3 variants: - - name: Div32768 - description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - value: 0 - - name: Div16384 - description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - value: 1 - - name: Div8192 - description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - value: 2 - - name: Div4096 - description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - value: 3 - - name: Div2048 - description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - value: 4 - - name: Div1024 - description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - value: 5 - - name: Div512 - description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - value: 6 - - name: Div256 - description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - value: 7 + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 enum/TAMPPRCH: bit_size: 2 variants: - - name: Cycles1 - description: 1 RTCCLK cycle - value: 0 - - name: Cycles2 - description: 2 RTCCLK cycles - value: 1 - - name: Cycles4 - description: 4 RTCCLK cycles - value: 2 - - name: Cycles8 - description: 8 RTCCLK cycles - value: 3 + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 enum/TAMPPUDIS: bit_size: 1 variants: - - name: Enabled - description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - value: 0 - - name: Disabled - description: Disable precharge of RTC_TAMPx pins - value: 1 + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 enum/TAMPTRG: bit_size: 1 variants: - - name: RisingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." - value: 0 - - name: FallingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" - value: 1 + - name: RisingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.' + value: 0 + - name: FallingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event' + value: 1 enum/TSEDGE: bit_size: 1 variants: - - name: RisingEdge - description: RTC_TS input rising edge generates a time-stamp event - value: 0 - - name: FallingEdge - description: RTC_TS input falling edge generates a time-stamp event - value: 1 + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 enum/WUCKSEL: bit_size: 3 variants: - - name: Div16 - description: RTC/16 clock is selected - value: 0 - - name: Div8 - description: RTC/8 clock is selected - value: 1 - - name: Div4 - description: RTC/4 clock is selected - value: 2 - - name: Div2 - description: RTC/2 clock is selected - value: 3 - - name: ClockSpare - description: ck_spre (usually 1 Hz) clock is selected - value: 4 - - name: ClockSpareWithOffset - description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - value: 6 + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 diff --git a/data/registers/rtc_v2f7.yaml b/data/registers/rtc_v2f7.yaml index 7f33f5d..2aabd35 100644 --- a/data/registers/rtc_v2f7.yaml +++ b/data/registers/rtc_v2f7.yaml @@ -1,846 +1,845 @@ ---- block/RTC: description: Real-time clock items: - - name: TR - description: Time register - byte_offset: 0 - fieldset: TR - - name: DR - description: Date register - byte_offset: 4 - fieldset: DR - - name: CR - description: Control register - byte_offset: 8 - fieldset: CR - - name: ISR - description: Initialization and status register - byte_offset: 12 - fieldset: ISR - - name: PRER - description: Prescaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: Wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: ALRMR - description: Alarm register - array: - len: 2 - stride: 4 - byte_offset: 28 - fieldset: ALRMR - - name: WPR - description: Write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: SSR - description: Sub second register - byte_offset: 40 - access: Read - fieldset: SSR - - name: SHIFTR - description: Shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TSTR - description: Timestamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: Timestamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TSSSR - description: Timestamp sub second register - byte_offset: 56 - access: Read - fieldset: TSSSR - - name: CALR - description: Calibration register - byte_offset: 60 - fieldset: CALR - - name: TAMPCR - description: Tamper configuration register - byte_offset: 64 - fieldset: TAMPCR - - name: ALRMSSR - description: Alarm sub second register - array: - len: 2 - stride: 4 - byte_offset: 68 - fieldset: ALRMSSR - - name: OR - description: Option register - byte_offset: 76 - fieldset: OR - - name: BKPR - description: Backup register - array: - len: 32 - stride: 4 - byte_offset: 80 - fieldset: BKPR + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAMPCR + description: Tamper configuration register + byte_offset: 64 + fieldset: TAMPCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: OR + description: Option register + byte_offset: 76 + fieldset: OR + - name: BKPR + description: Backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR fieldset/ALRMR: description: Alarm register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMR_MSK - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMR_MSK - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMR_PM - - name: MSK3 - description: Alarm hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMR_MSK - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMR_WDSEL - - name: MSK4 - description: Alarm date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMR_MSK + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK fieldset/ALRMSSR: description: Alarm sub second register fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 4 + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 fieldset/BKPR: description: Backup register fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/CALR: description: Calibration register fields: - - name: CALM - description: Calibration minus - bit_offset: 0 - bit_size: 9 - - name: CALW16 - description: Use a 16-second calibration cycle period - bit_offset: 13 - bit_size: 1 - enum: CALW16 - - name: CALW8 - description: Use an 8-second calibration cycle period - bit_offset: 14 - bit_size: 1 - enum: CALW8 - - name: CALP - description: Increase frequency of RTC by 488.5 ppm - bit_offset: 15 - bit_size: 1 - enum: CALP + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP fieldset/CR: description: Control register fields: - - name: WUCKSEL - description: Wakeup clock selection - bit_offset: 0 - bit_size: 3 - enum: WUCKSEL - - name: TSEDGE - description: Timestamp event active edge - bit_offset: 3 - bit_size: 1 - enum: TSEDGE - - name: REFCKON - description: Reference clock detection enable (50 or 60 Hz) - bit_offset: 4 - bit_size: 1 - enum: REFCKON - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - - name: FMT - description: Hour format - bit_offset: 6 - bit_size: 1 - enum: FMT - - name: ALRE - description: Alarm enable - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTE - description: Wakeup timer enable - bit_offset: 10 - bit_size: 1 - - name: TSE - description: Timestamp enable - bit_offset: 11 - bit_size: 1 - - name: ALRIE - description: Alarm interrupt enable - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTIE - description: Wakeup timer interrupt enable - bit_offset: 14 - bit_size: 1 - - name: TSIE - description: Timestamp interrupt enable - bit_offset: 15 - bit_size: 1 - - name: ADD1H - description: Add 1 hour (summer time change) - bit_offset: 16 - bit_size: 1 - - name: SUB1H - description: Subtract 1 hour (winter time change) - bit_offset: 17 - bit_size: 1 - - name: BKP - description: Backup - bit_offset: 18 - bit_size: 1 - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - enum: COSEL - - name: POL - description: Output polarity - bit_offset: 20 - bit_size: 1 - enum: POL - - name: OSEL - description: Output selection - bit_offset: 21 - bit_size: 2 - enum: OSEL - - name: COE - description: Calibration output enable - bit_offset: 23 - bit_size: 1 - - name: ITSE - description: Timestamp on internal event enable - bit_offset: 24 - bit_size: 1 + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRE + description: Alarm enable + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: Timestamp on internal event enable + bit_offset: 24 + bit_size: 1 fieldset/DR: description: Date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 fieldset/ISR: description: Initialization and status register fields: - - name: ALRWF - description: Alarm write flag - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: ALRWF - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - - name: RSF - description: Registers synchronization flag - bit_offset: 5 - bit_size: 1 - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - enum: INIT - - name: ALRF - description: Alarm flag - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTF - description: Wakeup timer flag - bit_offset: 10 - bit_size: 1 - - name: TSF - description: Timestamp flag - bit_offset: 11 - bit_size: 1 - - name: TSOVF - description: Timestamp overflow flag - bit_offset: 12 - bit_size: 1 - - name: TAMPF - description: Tamper detection flag - bit_offset: 13 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: RECALPF - description: Recalibration pending flag - bit_offset: 16 - bit_size: 1 - enum: RECALPF - - name: ITSF - description: Internal time-stamp flag - bit_offset: 17 - bit_size: 1 + - name: ALRWF + description: Alarm write flag + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: ALRWF + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + - name: TAMPF + description: Tamper detection flag + bit_offset: 13 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum: RECALPF + - name: ITSF + description: Internal time-stamp flag + bit_offset: 17 + bit_size: 1 fieldset/OR: description: Option register fields: - - name: TSINSEL - description: Timestamp mapping - bit_offset: 1 - bit_size: 2 - - name: RTC_ALARM_TYPE - description: RTC_ALARM on PC13 output type - bit_offset: 3 - bit_size: 1 + - name: TSINSEL + description: Timestamp mapping + bit_offset: 1 + bit_size: 2 + - name: RTC_ALARM_TYPE + description: RTC_ALARM on PC13 output type + bit_offset: 3 + bit_size: 1 fieldset/PRER: description: Prescaler register fields: - - name: PREDIV_S - description: Synchronous prescaler factor - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: Asynchronous prescaler factor - bit_offset: 16 - bit_size: 7 + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 fieldset/SHIFTR: description: Shift control register fields: - - name: SUBFS - description: Subtract a fraction of a second - bit_offset: 0 - bit_size: 15 - - name: ADD1S - description: Add one second - bit_offset: 31 - bit_size: 1 + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 fieldset/SSR: description: Sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TAMPCR: description: Tamper configuration register fields: - - name: TAMPE - description: Tamper detection enable - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 5 - - name: TAMPTRG - description: Active level for tamper - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 5 - enum: TAMPTRG - - name: TAMPIE - description: Tamper interrupt enable - bit_offset: 2 - bit_size: 1 - - name: TAMPTS - description: Activate timestamp on tamper detection event - bit_offset: 7 - bit_size: 1 - - name: TAMPFREQ - description: Tamper sampling frequency - bit_offset: 8 - bit_size: 3 - enum: TAMPFREQ - - name: TAMPFLT - description: Tamper filter count - bit_offset: 11 - bit_size: 2 - enum: TAMPFLT - - name: TAMPPRCH - description: Tamper precharge duration - bit_offset: 13 - bit_size: 2 - enum: TAMPPRCH - - name: TAMPPUDIS - description: Tamper pull-up disable - bit_offset: 15 - bit_size: 1 - enum: TAMPPUDIS - - name: TAMPXIE - description: Tamper interrupt enable - bit_offset: 16 - bit_size: 1 - array: - len: 3 - stride: 3 - - name: TAMPXNOERASE - description: Tamper no erase - bit_offset: 17 - bit_size: 1 - array: - len: 3 - stride: 3 - - name: TAMPXMF - description: Tamper mask flag - bit_offset: 18 - bit_size: 1 - array: - len: 3 - stride: 3 + - name: TAMPE + description: Tamper detection enable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 5 + - name: TAMPTRG + description: Active level for tamper + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 5 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: TAMPXIE + description: Tamper interrupt enable + bit_offset: 16 + bit_size: 1 + array: + len: 3 + stride: 3 + - name: TAMPXNOERASE + description: Tamper no erase + bit_offset: 17 + bit_size: 1 + array: + len: 3 + stride: 3 + - name: TAMPXMF + description: Tamper mask flag + bit_offset: 18 + bit_size: 1 + array: + len: 3 + stride: 3 fieldset/TR: description: Time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/TSDR: description: Timestamp date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 fieldset/TSSSR: description: Timestamp sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TSTR: description: Timestamp time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/WPR: description: Write protection register fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 fieldset/WUTR: description: Wakeup timer register fields: - - name: WUT - description: Wakeup auto-reload value bits - bit_offset: 0 - bit_size: 16 + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 enum/ALRMR_MSK: bit_size: 1 variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 enum/ALRMR_PM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/ALRMR_WDSEL: bit_size: 1 variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care" - value: 1 + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 enum/ALRWF: bit_size: 1 variants: - - name: UpdateNotAllowed - description: Alarm update not allowed - value: 0 - - name: UpdateAllowed - description: Alarm update allowed - value: 1 + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 enum/AMPM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/CALP: bit_size: 1 variants: - - name: NoChange - description: No RTCCLK pulses are added - value: 0 - - name: IncreaseFreq - description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - value: 1 + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 enum/CALW16: bit_size: 1 variants: - - name: Sixteen_Second - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" - value: 1 + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 enum/CALW8: bit_size: 1 variants: - - name: Eight_Second - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 enum/COSEL: bit_size: 1 variants: - - name: CalFreq_512Hz - description: Calibration output is 512 Hz (with default prescaler setting) - value: 0 - - name: CalFreq_1Hz - description: Calibration output is 1 Hz (with default prescaler setting) - value: 1 + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 enum/FMT: bit_size: 1 variants: - - name: Twenty_Four_Hour - description: 24 hour/day format - value: 0 - - name: AM_PM - description: AM/PM hour format - value: 1 + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 enum/INIT: bit_size: 1 variants: - - name: FreeRunningMode - description: Free running mode - value: 0 - - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." - value: 1 + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 enum/OSEL: bit_size: 2 variants: - - name: Disabled - description: Output disabled - value: 0 - - name: AlarmA - description: Alarm A output enabled - value: 1 - - name: AlarmB - description: Alarm B output enabled - value: 2 - - name: Wakeup - description: Wakeup output enabled - value: 3 + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 enum/POL: bit_size: 1 variants: - - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 0 - - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 1 + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 enum/RECALPF: bit_size: 1 variants: - - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" - value: 1 + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 enum/REFCKON: bit_size: 1 variants: - - name: Disabled - description: RTC_REFIN detection disabled - value: 0 - - name: Enabled - description: RTC_REFIN detection enabled - value: 1 + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 enum/TAMPFLT: bit_size: 2 variants: - - name: Immediate - description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - value: 0 - - name: Samples2 - description: Tamper event is activated after 2 consecutive samples at the active level - value: 1 - - name: Samples4 - description: Tamper event is activated after 4 consecutive samples at the active level - value: 2 - - name: Samples8 - description: Tamper event is activated after 8 consecutive samples at the active level - value: 3 + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 enum/TAMPFREQ: bit_size: 3 variants: - - name: Div32768 - description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - value: 0 - - name: Div16384 - description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - value: 1 - - name: Div8192 - description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - value: 2 - - name: Div4096 - description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - value: 3 - - name: Div2048 - description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - value: 4 - - name: Div1024 - description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - value: 5 - - name: Div512 - description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - value: 6 - - name: Div256 - description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - value: 7 + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 enum/TAMPPRCH: bit_size: 2 variants: - - name: Cycles1 - description: 1 RTCCLK cycle - value: 0 - - name: Cycles2 - description: 2 RTCCLK cycles - value: 1 - - name: Cycles4 - description: 4 RTCCLK cycles - value: 2 - - name: Cycles8 - description: 8 RTCCLK cycles - value: 3 + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 enum/TAMPPUDIS: bit_size: 1 variants: - - name: Enabled - description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - value: 0 - - name: Disabled - description: Disable precharge of RTC_TAMPx pins - value: 1 + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 enum/TAMPTRG: bit_size: 1 variants: - - name: RisingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." - value: 0 - - name: FallingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" - value: 1 + - name: RisingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.' + value: 0 + - name: FallingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event' + value: 1 enum/TSEDGE: bit_size: 1 variants: - - name: RisingEdge - description: RTC_TS input rising edge generates a time-stamp event - value: 0 - - name: FallingEdge - description: RTC_TS input falling edge generates a time-stamp event - value: 1 + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 enum/WUCKSEL: bit_size: 3 variants: - - name: Div16 - description: RTC/16 clock is selected - value: 0 - - name: Div8 - description: RTC/8 clock is selected - value: 1 - - name: Div4 - description: RTC/4 clock is selected - value: 2 - - name: Div2 - description: RTC/2 clock is selected - value: 3 - - name: ClockSpare - description: ck_spre (usually 1 Hz) clock is selected - value: 4 - - name: ClockSpareWithOffset - description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - value: 6 + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 diff --git a/data/registers/rtc_v2h7.yaml b/data/registers/rtc_v2h7.yaml index cec720f..81060e3 100644 --- a/data/registers/rtc_v2h7.yaml +++ b/data/registers/rtc_v2h7.yaml @@ -1,846 +1,845 @@ ---- block/RTC: description: Real-time clock items: - - name: TR - description: Time register - byte_offset: 0 - fieldset: TR - - name: DR - description: Date register - byte_offset: 4 - fieldset: DR - - name: CR - description: Control register - byte_offset: 8 - fieldset: CR - - name: ISR - description: Initialization and status register - byte_offset: 12 - fieldset: ISR - - name: PRER - description: Prescaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: Wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: ALRMR - description: Alarm register - array: - len: 2 - stride: 4 - byte_offset: 28 - fieldset: ALRMR - - name: WPR - description: Write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: SSR - description: Sub second register - byte_offset: 40 - access: Read - fieldset: SSR - - name: SHIFTR - description: Shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TSTR - description: Timestamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: Timestamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TSSSR - description: Timestamp sub second register - byte_offset: 56 - access: Read - fieldset: TSSSR - - name: CALR - description: Calibration register - byte_offset: 60 - fieldset: CALR - - name: TAMPCR - description: Tamper configuration register - byte_offset: 64 - fieldset: TAMPCR - - name: ALRMSSR - description: Alarm sub second register - array: - len: 2 - stride: 4 - byte_offset: 68 - fieldset: ALRMSSR - - name: OR - description: Option register - byte_offset: 76 - fieldset: OR - - name: BKPR - description: Backup register - array: - len: 32 - stride: 4 - byte_offset: 80 - fieldset: BKPR + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAMPCR + description: Tamper configuration register + byte_offset: 64 + fieldset: TAMPCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: OR + description: Option register + byte_offset: 76 + fieldset: OR + - name: BKPR + description: Backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR fieldset/ALRMR: description: Alarm register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMR_MSK - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMR_MSK - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMR_PM - - name: MSK3 - description: Alarm hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMR_MSK - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMR_WDSEL - - name: MSK4 - description: Alarm date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMR_MSK + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK fieldset/ALRMSSR: description: Alarm sub second register fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 4 + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 fieldset/BKPR: description: Backup register fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/CALR: description: Calibration register fields: - - name: CALM - description: Calibration minus - bit_offset: 0 - bit_size: 9 - - name: CALW16 - description: Use a 16-second calibration cycle period - bit_offset: 13 - bit_size: 1 - enum: CALW16 - - name: CALW8 - description: Use an 8-second calibration cycle period - bit_offset: 14 - bit_size: 1 - enum: CALW8 - - name: CALP - description: Increase frequency of RTC by 488.5 ppm - bit_offset: 15 - bit_size: 1 - enum: CALP + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP fieldset/CR: description: Control register fields: - - name: WUCKSEL - description: Wakeup clock selection - bit_offset: 0 - bit_size: 3 - enum: WUCKSEL - - name: TSEDGE - description: Timestamp event active edge - bit_offset: 3 - bit_size: 1 - enum: TSEDGE - - name: REFCKON - description: Reference clock detection enable (50 or 60 Hz) - bit_offset: 4 - bit_size: 1 - enum: REFCKON - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - - name: FMT - description: Hour format - bit_offset: 6 - bit_size: 1 - enum: FMT - - name: ALRE - description: Alarm enable - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTE - description: Wakeup timer enable - bit_offset: 10 - bit_size: 1 - - name: TSE - description: Timestamp enable - bit_offset: 11 - bit_size: 1 - - name: ALRIE - description: Alarm interrupt enable - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTIE - description: Wakeup timer interrupt enable - bit_offset: 14 - bit_size: 1 - - name: TSIE - description: Timestamp interrupt enable - bit_offset: 15 - bit_size: 1 - - name: ADD1H - description: Add 1 hour (summer time change) - bit_offset: 16 - bit_size: 1 - - name: SUB1H - description: Subtract 1 hour (winter time change) - bit_offset: 17 - bit_size: 1 - - name: BKP - description: Backup - bit_offset: 18 - bit_size: 1 - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - enum: COSEL - - name: POL - description: Output polarity - bit_offset: 20 - bit_size: 1 - enum: POL - - name: OSEL - description: Output selection - bit_offset: 21 - bit_size: 2 - enum: OSEL - - name: COE - description: Calibration output enable - bit_offset: 23 - bit_size: 1 - - name: ITSE - description: Timestamp on internal event enable - bit_offset: 24 - bit_size: 1 + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRE + description: Alarm enable + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: Timestamp on internal event enable + bit_offset: 24 + bit_size: 1 fieldset/DR: description: Date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 fieldset/ISR: description: Initialization and status register fields: - - name: ALRWF - description: Alarm write flag - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: ALRWF - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - - name: RSF - description: Registers synchronization flag - bit_offset: 5 - bit_size: 1 - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - enum: INIT - - name: ALRF - description: Alarm flag - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTF - description: Wakeup timer flag - bit_offset: 10 - bit_size: 1 - - name: TSF - description: Timestamp flag - bit_offset: 11 - bit_size: 1 - - name: TSOVF - description: Timestamp overflow flag - bit_offset: 12 - bit_size: 1 - - name: TAMPF - description: Tamper detection flag - bit_offset: 13 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: RECALPF - description: Recalibration pending flag - bit_offset: 16 - bit_size: 1 - enum: RECALPF - - name: ITSF - description: Internal time-stamp flag - bit_offset: 17 - bit_size: 1 + - name: ALRWF + description: Alarm write flag + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: ALRWF + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + - name: TAMPF + description: Tamper detection flag + bit_offset: 13 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum: RECALPF + - name: ITSF + description: Internal time-stamp flag + bit_offset: 17 + bit_size: 1 fieldset/OR: description: Option register fields: - - name: RTC_ALARM_TYPE - description: RTC_ALARM output type on PC13 - bit_offset: 0 - bit_size: 1 - - name: RTC_OUT_RMP - description: RTC_OUT remap - bit_offset: 1 - bit_size: 1 + - name: RTC_ALARM_TYPE + description: RTC_ALARM output type on PC13 + bit_offset: 0 + bit_size: 1 + - name: RTC_OUT_RMP + description: RTC_OUT remap + bit_offset: 1 + bit_size: 1 fieldset/PRER: description: Prescaler register fields: - - name: PREDIV_S - description: Synchronous prescaler factor - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: Asynchronous prescaler factor - bit_offset: 16 - bit_size: 7 + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 fieldset/SHIFTR: description: Shift control register fields: - - name: SUBFS - description: Subtract a fraction of a second - bit_offset: 0 - bit_size: 15 - - name: ADD1S - description: Add one second - bit_offset: 31 - bit_size: 1 + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 fieldset/SSR: description: Sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TAMPCR: description: Tamper configuration register fields: - - name: TAMPE - description: Tamper detection enable - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 5 - - name: TAMPTRG - description: Active level for tamper - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 5 - enum: TAMPTRG - - name: TAMPIE - description: Tamper interrupt enable - bit_offset: 2 - bit_size: 1 - - name: TAMPTS - description: Activate timestamp on tamper detection event - bit_offset: 7 - bit_size: 1 - - name: TAMPFREQ - description: Tamper sampling frequency - bit_offset: 8 - bit_size: 3 - enum: TAMPFREQ - - name: TAMPFLT - description: Tamper filter count - bit_offset: 11 - bit_size: 2 - enum: TAMPFLT - - name: TAMPPRCH - description: Tamper precharge duration - bit_offset: 13 - bit_size: 2 - enum: TAMPPRCH - - name: TAMPPUDIS - description: Tamper pull-up disable - bit_offset: 15 - bit_size: 1 - enum: TAMPPUDIS - - name: TAMPXIE - description: Tamper interrupt enable - bit_offset: 16 - bit_size: 1 - array: - len: 3 - stride: 3 - - name: TAMPXNOERASE - description: Tamper no erase - bit_offset: 17 - bit_size: 1 - array: - len: 3 - stride: 3 - - name: TAMPXMF - description: Tamper mask flag - bit_offset: 18 - bit_size: 1 - array: - len: 3 - stride: 3 + - name: TAMPE + description: Tamper detection enable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 5 + - name: TAMPTRG + description: Active level for tamper + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 5 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: TAMPXIE + description: Tamper interrupt enable + bit_offset: 16 + bit_size: 1 + array: + len: 3 + stride: 3 + - name: TAMPXNOERASE + description: Tamper no erase + bit_offset: 17 + bit_size: 1 + array: + len: 3 + stride: 3 + - name: TAMPXMF + description: Tamper mask flag + bit_offset: 18 + bit_size: 1 + array: + len: 3 + stride: 3 fieldset/TR: description: Time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/TSDR: description: Timestamp date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 fieldset/TSSSR: description: Timestamp sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TSTR: description: Timestamp time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/WPR: description: Write protection register fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 fieldset/WUTR: description: Wakeup timer register fields: - - name: WUT - description: Wakeup auto-reload value bits - bit_offset: 0 - bit_size: 16 + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 enum/ALRMR_MSK: bit_size: 1 variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 enum/ALRMR_PM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/ALRMR_WDSEL: bit_size: 1 variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care" - value: 1 + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 enum/ALRWF: bit_size: 1 variants: - - name: UpdateNotAllowed - description: Alarm update not allowed - value: 0 - - name: UpdateAllowed - description: Alarm update allowed - value: 1 + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 enum/AMPM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/CALP: bit_size: 1 variants: - - name: NoChange - description: No RTCCLK pulses are added - value: 0 - - name: IncreaseFreq - description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - value: 1 + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 enum/CALW16: bit_size: 1 variants: - - name: Sixteen_Second - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" - value: 1 + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 enum/CALW8: bit_size: 1 variants: - - name: Eight_Second - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 enum/COSEL: bit_size: 1 variants: - - name: CalFreq_512Hz - description: Calibration output is 512 Hz (with default prescaler setting) - value: 0 - - name: CalFreq_1Hz - description: Calibration output is 1 Hz (with default prescaler setting) - value: 1 + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 enum/FMT: bit_size: 1 variants: - - name: Twenty_Four_Hour - description: 24 hour/day format - value: 0 - - name: AM_PM - description: AM/PM hour format - value: 1 + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 enum/INIT: bit_size: 1 variants: - - name: FreeRunningMode - description: Free running mode - value: 0 - - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." - value: 1 + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 enum/OSEL: bit_size: 2 variants: - - name: Disabled - description: Output disabled - value: 0 - - name: AlarmA - description: Alarm A output enabled - value: 1 - - name: AlarmB - description: Alarm B output enabled - value: 2 - - name: Wakeup - description: Wakeup output enabled - value: 3 + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 enum/POL: bit_size: 1 variants: - - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 0 - - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 1 + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 enum/RECALPF: bit_size: 1 variants: - - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" - value: 1 + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 enum/REFCKON: bit_size: 1 variants: - - name: Disabled - description: RTC_REFIN detection disabled - value: 0 - - name: Enabled - description: RTC_REFIN detection enabled - value: 1 + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 enum/TAMPFLT: bit_size: 2 variants: - - name: Immediate - description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - value: 0 - - name: Samples2 - description: Tamper event is activated after 2 consecutive samples at the active level - value: 1 - - name: Samples4 - description: Tamper event is activated after 4 consecutive samples at the active level - value: 2 - - name: Samples8 - description: Tamper event is activated after 8 consecutive samples at the active level - value: 3 + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 enum/TAMPFREQ: bit_size: 3 variants: - - name: Div32768 - description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - value: 0 - - name: Div16384 - description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - value: 1 - - name: Div8192 - description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - value: 2 - - name: Div4096 - description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - value: 3 - - name: Div2048 - description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - value: 4 - - name: Div1024 - description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - value: 5 - - name: Div512 - description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - value: 6 - - name: Div256 - description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - value: 7 + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 enum/TAMPPRCH: bit_size: 2 variants: - - name: Cycles1 - description: 1 RTCCLK cycle - value: 0 - - name: Cycles2 - description: 2 RTCCLK cycles - value: 1 - - name: Cycles4 - description: 4 RTCCLK cycles - value: 2 - - name: Cycles8 - description: 8 RTCCLK cycles - value: 3 + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 enum/TAMPPUDIS: bit_size: 1 variants: - - name: Enabled - description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - value: 0 - - name: Disabled - description: Disable precharge of RTC_TAMPx pins - value: 1 + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 enum/TAMPTRG: bit_size: 1 variants: - - name: RisingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." - value: 0 - - name: FallingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" - value: 1 + - name: RisingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.' + value: 0 + - name: FallingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event' + value: 1 enum/TSEDGE: bit_size: 1 variants: - - name: RisingEdge - description: RTC_TS input rising edge generates a time-stamp event - value: 0 - - name: FallingEdge - description: RTC_TS input falling edge generates a time-stamp event - value: 1 + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 enum/WUCKSEL: bit_size: 3 variants: - - name: Div16 - description: RTC/16 clock is selected - value: 0 - - name: Div8 - description: RTC/8 clock is selected - value: 1 - - name: Div4 - description: RTC/4 clock is selected - value: 2 - - name: Div2 - description: RTC/2 clock is selected - value: 3 - - name: ClockSpare - description: ck_spre (usually 1 Hz) clock is selected - value: 4 - - name: ClockSpareWithOffset - description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - value: 6 + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 diff --git a/data/registers/rtc_v2l0.yaml b/data/registers/rtc_v2l0.yaml index 75dd62e..7ad5c77 100644 --- a/data/registers/rtc_v2l0.yaml +++ b/data/registers/rtc_v2l0.yaml @@ -1,838 +1,837 @@ ---- block/RTC: description: Real-time clock items: - - name: TR - description: Time register - byte_offset: 0 - fieldset: TR - - name: DR - description: Date register - byte_offset: 4 - fieldset: DR - - name: CR - description: Control register - byte_offset: 8 - fieldset: CR - - name: ISR - description: Initialization and status register - byte_offset: 12 - fieldset: ISR - - name: PRER - description: Prescaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: Wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: ALRMR - description: Alarm register - array: - len: 2 - stride: 4 - byte_offset: 28 - fieldset: ALRMR - - name: WPR - description: Write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: SSR - description: Sub second register - byte_offset: 40 - access: Read - fieldset: SSR - - name: SHIFTR - description: Shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TSTR - description: Timestamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: Timestamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TSSSR - description: Timestamp sub second register - byte_offset: 56 - access: Read - fieldset: TSSSR - - name: CALR - description: Calibration register - byte_offset: 60 - fieldset: CALR - - name: TAMPCR - description: Tamper configuration register - byte_offset: 64 - fieldset: TAMPCR - - name: ALRMSSR - description: Alarm sub second register - array: - len: 2 - stride: 4 - byte_offset: 68 - fieldset: ALRMSSR - - name: OR - description: Option register - byte_offset: 76 - fieldset: OR - - name: BKPR - description: Backup register - array: - len: 5 - stride: 4 - byte_offset: 80 - fieldset: BKPR + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAMPCR + description: Tamper configuration register + byte_offset: 64 + fieldset: TAMPCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: OR + description: Option register + byte_offset: 76 + fieldset: OR + - name: BKPR + description: Backup register + array: + len: 5 + stride: 4 + byte_offset: 80 + fieldset: BKPR fieldset/ALRMR: description: Alarm register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMR_MSK - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMR_MSK - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMR_PM - - name: MSK3 - description: Alarm hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMR_MSK - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMR_WDSEL - - name: MSK4 - description: Alarm date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMR_MSK + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK fieldset/ALRMSSR: description: Alarm sub second register fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 4 + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 fieldset/BKPR: description: Backup register fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/CALR: description: Calibration register fields: - - name: CALM - description: Calibration minus - bit_offset: 0 - bit_size: 9 - - name: CALW16 - description: Use a 16-second calibration cycle period - bit_offset: 13 - bit_size: 1 - enum: CALW16 - - name: CALW8 - description: Use an 8-second calibration cycle period - bit_offset: 14 - bit_size: 1 - enum: CALW8 - - name: CALP - description: Increase frequency of RTC by 488.5 ppm - bit_offset: 15 - bit_size: 1 - enum: CALP + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP fieldset/CR: description: Control register fields: - - name: WUCKSEL - description: Wakeup clock selection - bit_offset: 0 - bit_size: 3 - enum: WUCKSEL - - name: TSEDGE - description: Timestamp event active edge - bit_offset: 3 - bit_size: 1 - enum: TSEDGE - - name: REFCKON - description: Reference clock detection enable (50 or 60 Hz) - bit_offset: 4 - bit_size: 1 - enum: REFCKON - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - - name: FMT - description: Hour format - bit_offset: 6 - bit_size: 1 - enum: FMT - - name: ALRE - description: Alarm enable - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTE - description: Wakeup timer enable - bit_offset: 10 - bit_size: 1 - - name: TSE - description: Timestamp enable - bit_offset: 11 - bit_size: 1 - - name: ALRIE - description: Alarm interrupt enable - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTIE - description: Wakeup timer interrupt enable - bit_offset: 14 - bit_size: 1 - - name: TSIE - description: Timestamp interrupt enable - bit_offset: 15 - bit_size: 1 - - name: ADD1H - description: Add 1 hour (summer time change) - bit_offset: 16 - bit_size: 1 - - name: SUB1H - description: Subtract 1 hour (winter time change) - bit_offset: 17 - bit_size: 1 - - name: BKP - description: Backup - bit_offset: 18 - bit_size: 1 - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - enum: COSEL - - name: POL - description: Output polarity - bit_offset: 20 - bit_size: 1 - enum: POL - - name: OSEL - description: Output selection - bit_offset: 21 - bit_size: 2 - enum: OSEL - - name: COE - description: Calibration output enable - bit_offset: 23 - bit_size: 1 + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRE + description: Alarm enable + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 fieldset/DR: description: Date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 fieldset/ISR: description: Initialization and status register fields: - - name: ALRWF - description: Alarm write flag - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: ALRWF - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - - name: RSF - description: Registers synchronization flag - bit_offset: 5 - bit_size: 1 - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - enum: INIT - - name: ALRF - description: Alarm flag - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTF - description: Wakeup timer flag - bit_offset: 10 - bit_size: 1 - - name: TSF - description: Timestamp flag - bit_offset: 11 - bit_size: 1 - - name: TSOVF - description: Timestamp overflow flag - bit_offset: 12 - bit_size: 1 - - name: TAMPF - description: Tamper detection flag - bit_offset: 13 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: RECALPF - description: Recalibration pending flag - bit_offset: 16 - bit_size: 1 - enum: RECALPF + - name: ALRWF + description: Alarm write flag + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: ALRWF + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + - name: TAMPF + description: Tamper detection flag + bit_offset: 13 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum: RECALPF fieldset/OR: description: Option register fields: - - name: RTC_ALARM_TYPE - description: RTC_ALARM on PC13 output type - bit_offset: 0 - bit_size: 1 - - name: RTC_OUT_RMP - description: RTC_ALARM on PC13 output type - bit_offset: 1 - bit_size: 1 + - name: RTC_ALARM_TYPE + description: RTC_ALARM on PC13 output type + bit_offset: 0 + bit_size: 1 + - name: RTC_OUT_RMP + description: RTC_ALARM on PC13 output type + bit_offset: 1 + bit_size: 1 fieldset/PRER: description: Prescaler register fields: - - name: PREDIV_S - description: Synchronous prescaler factor - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: Asynchronous prescaler factor - bit_offset: 16 - bit_size: 7 + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 fieldset/SHIFTR: description: Shift control register fields: - - name: SUBFS - description: Subtract a fraction of a second - bit_offset: 0 - bit_size: 15 - - name: ADD1S - description: Add one second - bit_offset: 31 - bit_size: 1 + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 fieldset/SSR: description: Sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TAMPCR: description: Tamper configuration register fields: - - name: TAMPE - description: Tamper detection enable - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 5 - - name: TAMPTRG - description: Active level for tamper - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 5 - enum: TAMPTRG - - name: TAMPIE - description: Tamper interrupt enable - bit_offset: 2 - bit_size: 1 - - name: TAMPTS - description: Activate timestamp on tamper detection event - bit_offset: 7 - bit_size: 1 - - name: TAMPFREQ - description: Tamper sampling frequency - bit_offset: 8 - bit_size: 3 - enum: TAMPFREQ - - name: TAMPFLT - description: Tamper filter count - bit_offset: 11 - bit_size: 2 - enum: TAMPFLT - - name: TAMPPRCH - description: Tamper precharge duration - bit_offset: 13 - bit_size: 2 - enum: TAMPPRCH - - name: TAMPPUDIS - description: Tamper pull-up disable - bit_offset: 15 - bit_size: 1 - enum: TAMPPUDIS - - name: TAMPXIE - description: Tamper interrupt enable - bit_offset: 16 - bit_size: 1 - array: - len: 3 - stride: 3 - - name: TAMPXNOERASE - description: Tamper no erase - bit_offset: 17 - bit_size: 1 - array: - len: 3 - stride: 3 - - name: TAMPXMF - description: Tamper mask flag - bit_offset: 18 - bit_size: 1 - array: - len: 3 - stride: 3 + - name: TAMPE + description: Tamper detection enable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 5 + - name: TAMPTRG + description: Active level for tamper + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 5 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: TAMPXIE + description: Tamper interrupt enable + bit_offset: 16 + bit_size: 1 + array: + len: 3 + stride: 3 + - name: TAMPXNOERASE + description: Tamper no erase + bit_offset: 17 + bit_size: 1 + array: + len: 3 + stride: 3 + - name: TAMPXMF + description: Tamper mask flag + bit_offset: 18 + bit_size: 1 + array: + len: 3 + stride: 3 fieldset/TR: description: Time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/TSDR: description: Timestamp date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 fieldset/TSSSR: description: Timestamp sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TSTR: description: Timestamp time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/WPR: description: Write protection register fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 fieldset/WUTR: description: Wakeup timer register fields: - - name: WUT - description: Wakeup auto-reload value bits - bit_offset: 0 - bit_size: 16 + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 enum/ALRMR_MSK: bit_size: 1 variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 enum/ALRMR_PM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/ALRMR_WDSEL: bit_size: 1 variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care" - value: 1 + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 enum/ALRWF: bit_size: 1 variants: - - name: UpdateNotAllowed - description: Alarm update not allowed - value: 0 - - name: UpdateAllowed - description: Alarm update allowed - value: 1 + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 enum/AMPM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/CALP: bit_size: 1 variants: - - name: NoChange - description: No RTCCLK pulses are added - value: 0 - - name: IncreaseFreq - description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - value: 1 + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 enum/CALW16: bit_size: 1 variants: - - name: Sixteen_Second - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" - value: 1 + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 enum/CALW8: bit_size: 1 variants: - - name: Eight_Second - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 enum/COSEL: bit_size: 1 variants: - - name: CalFreq_512Hz - description: Calibration output is 512 Hz (with default prescaler setting) - value: 0 - - name: CalFreq_1Hz - description: Calibration output is 1 Hz (with default prescaler setting) - value: 1 + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 enum/FMT: bit_size: 1 variants: - - name: Twenty_Four_Hour - description: 24 hour/day format - value: 0 - - name: AM_PM - description: AM/PM hour format - value: 1 + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 enum/INIT: bit_size: 1 variants: - - name: FreeRunningMode - description: Free running mode - value: 0 - - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." - value: 1 + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 enum/OSEL: bit_size: 2 variants: - - name: Disabled - description: Output disabled - value: 0 - - name: AlarmA - description: Alarm A output enabled - value: 1 - - name: AlarmB - description: Alarm B output enabled - value: 2 - - name: Wakeup - description: Wakeup output enabled - value: 3 + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 enum/POL: bit_size: 1 variants: - - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 0 - - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 1 + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 enum/RECALPF: bit_size: 1 variants: - - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" - value: 1 + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 enum/REFCKON: bit_size: 1 variants: - - name: Disabled - description: RTC_REFIN detection disabled - value: 0 - - name: Enabled - description: RTC_REFIN detection enabled - value: 1 + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 enum/TAMPFLT: bit_size: 2 variants: - - name: Immediate - description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - value: 0 - - name: Samples2 - description: Tamper event is activated after 2 consecutive samples at the active level - value: 1 - - name: Samples4 - description: Tamper event is activated after 4 consecutive samples at the active level - value: 2 - - name: Samples8 - description: Tamper event is activated after 8 consecutive samples at the active level - value: 3 + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 enum/TAMPFREQ: bit_size: 3 variants: - - name: Div32768 - description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - value: 0 - - name: Div16384 - description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - value: 1 - - name: Div8192 - description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - value: 2 - - name: Div4096 - description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - value: 3 - - name: Div2048 - description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - value: 4 - - name: Div1024 - description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - value: 5 - - name: Div512 - description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - value: 6 - - name: Div256 - description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - value: 7 + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 enum/TAMPPRCH: bit_size: 2 variants: - - name: Cycles1 - description: 1 RTCCLK cycle - value: 0 - - name: Cycles2 - description: 2 RTCCLK cycles - value: 1 - - name: Cycles4 - description: 4 RTCCLK cycles - value: 2 - - name: Cycles8 - description: 8 RTCCLK cycles - value: 3 + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 enum/TAMPPUDIS: bit_size: 1 variants: - - name: Enabled - description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - value: 0 - - name: Disabled - description: Disable precharge of RTC_TAMPx pins - value: 1 + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 enum/TAMPTRG: bit_size: 1 variants: - - name: RisingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." - value: 0 - - name: FallingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" - value: 1 + - name: RisingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.' + value: 0 + - name: FallingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event' + value: 1 enum/TSEDGE: bit_size: 1 variants: - - name: RisingEdge - description: RTC_TS input rising edge generates a time-stamp event - value: 0 - - name: FallingEdge - description: RTC_TS input falling edge generates a time-stamp event - value: 1 + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 enum/WUCKSEL: bit_size: 3 variants: - - name: Div16 - description: RTC/16 clock is selected - value: 0 - - name: Div8 - description: RTC/8 clock is selected - value: 1 - - name: Div4 - description: RTC/4 clock is selected - value: 2 - - name: Div2 - description: RTC/2 clock is selected - value: 3 - - name: ClockSpare - description: ck_spre (usually 1 Hz) clock is selected - value: 4 - - name: ClockSpareWithOffset - description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - value: 6 + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 diff --git a/data/registers/rtc_v2l1.yaml b/data/registers/rtc_v2l1.yaml index 2442d86..12c1ea3 100644 --- a/data/registers/rtc_v2l1.yaml +++ b/data/registers/rtc_v2l1.yaml @@ -1,825 +1,824 @@ ---- block/RTC: description: Real-time clock items: - - name: TR - description: Time register - byte_offset: 0 - fieldset: TR - - name: DR - description: Date register - byte_offset: 4 - fieldset: DR - - name: CR - description: Control register - byte_offset: 8 - fieldset: CR - - name: ISR - description: Initialization and status register - byte_offset: 12 - fieldset: ISR - - name: PRER - description: Prescaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: Wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: CALIBR - description: Calibration register - byte_offset: 24 - fieldset: CALIBR - - name: ALRMR - description: Alarm register - array: - len: 2 - stride: 4 - byte_offset: 28 - fieldset: ALRMR - - name: WPR - description: Write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: SSR - description: Sub second register - byte_offset: 40 - access: Read - fieldset: SSR - - name: SHIFTR - description: Shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TSTR - description: Timestamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: Timestamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TSSSR - description: Timestamp sub second register - byte_offset: 56 - access: Read - fieldset: TSSSR - - name: CALR - description: Calibration register - byte_offset: 60 - fieldset: CALR - - name: TAFCR - description: Tamper and alternate function configuration register - byte_offset: 64 - fieldset: TAFCR - - name: ALRMSSR - description: Alarm sub second register - array: - len: 2 - stride: 4 - byte_offset: 68 - fieldset: ALRMSSR - - name: BKPR - description: Backup register - array: - len: 32 - stride: 4 - byte_offset: 80 - fieldset: BKPR + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CALIBR + description: Calibration register + byte_offset: 24 + fieldset: CALIBR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAFCR + description: Tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAFCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: BKPR + description: Backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR fieldset/ALRMR: description: Alarm register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMR_MSK - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMR_MSK - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMR_PM - - name: MSK3 - description: Alarm hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMR_MSK - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMR_WDSEL - - name: MSK4 - description: Alarm date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMR_MSK + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK fieldset/ALRMSSR: description: Alarm sub second register fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 4 + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 fieldset/BKPR: description: Backup register fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/CALIBR: description: Calibration register fields: - - name: DC - description: Digital calibration - bit_offset: 0 - bit_size: 5 - - name: DCS - description: Digital calibration sign - bit_offset: 7 - bit_size: 1 + - name: DC + description: Digital calibration + bit_offset: 0 + bit_size: 5 + - name: DCS + description: Digital calibration sign + bit_offset: 7 + bit_size: 1 fieldset/CALR: description: Calibration register fields: - - name: CALM - description: Calibration minus - bit_offset: 0 - bit_size: 9 - - name: CALW16 - description: Use a 16-second calibration cycle period - bit_offset: 13 - bit_size: 1 - enum: CALW16 - - name: CALW8 - description: Use an 8-second calibration cycle period - bit_offset: 14 - bit_size: 1 - enum: CALW8 - - name: CALP - description: Increase frequency of RTC by 488.5 ppm - bit_offset: 15 - bit_size: 1 - enum: CALP + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP fieldset/CR: description: Control register fields: - - name: WUCKSEL - description: Wakeup clock selection - bit_offset: 0 - bit_size: 3 - enum: WUCKSEL - - name: TSEDGE - description: Timestamp event active edge - bit_offset: 3 - bit_size: 1 - enum: TSEDGE - - name: REFCKON - description: Reference clock detection enable (50 or 60 Hz) - bit_offset: 4 - bit_size: 1 - enum: REFCKON - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - - name: FMT - description: Hour format - bit_offset: 6 - bit_size: 1 - enum: FMT - - name: DCE - description: Coarse digital calibration enable - bit_offset: 7 - bit_size: 1 - - name: ALRE - description: Alarm enable - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTE - description: Wakeup timer enable - bit_offset: 10 - bit_size: 1 - - name: TSE - description: Timestamp enable - bit_offset: 11 - bit_size: 1 - - name: ALRIE - description: Alarm interrupt enable - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTIE - description: Wakeup timer interrupt enable - bit_offset: 14 - bit_size: 1 - - name: TSIE - description: Timestamp interrupt enable - bit_offset: 15 - bit_size: 1 - - name: ADD1H - description: Add 1 hour (summer time change) - bit_offset: 16 - bit_size: 1 - - name: SUB1H - description: Subtract 1 hour (winter time change) - bit_offset: 17 - bit_size: 1 - - name: BKP - description: Backup - bit_offset: 18 - bit_size: 1 - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - enum: COSEL - - name: POL - description: Output polarity - bit_offset: 20 - bit_size: 1 - enum: POL - - name: OSEL - description: Output selection - bit_offset: 21 - bit_size: 2 - enum: OSEL - - name: COE - description: Calibration output enable - bit_offset: 23 - bit_size: 1 + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: DCE + description: Coarse digital calibration enable + bit_offset: 7 + bit_size: 1 + - name: ALRE + description: Alarm enable + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 fieldset/DR: description: Date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 fieldset/ISR: description: Initialization and status register fields: - - name: ALRWF - description: Alarm write flag - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: ALRWF - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - - name: RSF - description: Registers synchronization flag - bit_offset: 5 - bit_size: 1 - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - enum: INIT - - name: ALRF - description: Alarm flag - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTF - description: Wakeup timer flag - bit_offset: 10 - bit_size: 1 - - name: TSF - description: Timestamp flag - bit_offset: 11 - bit_size: 1 - - name: TSOVF - description: Timestamp overflow flag - bit_offset: 12 - bit_size: 1 - - name: TAMPF - description: Tamper detection flag - bit_offset: 13 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: RECALPF - description: Recalibration pending flag - bit_offset: 16 - bit_size: 1 - enum: RECALPF + - name: ALRWF + description: Alarm write flag + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: ALRWF + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + - name: TAMPF + description: Tamper detection flag + bit_offset: 13 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum: RECALPF fieldset/PRER: description: Prescaler register fields: - - name: PREDIV_S - description: Synchronous prescaler factor - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: Asynchronous prescaler factor - bit_offset: 16 - bit_size: 7 + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 fieldset/SHIFTR: description: Shift control register fields: - - name: SUBFS - description: Subtract a fraction of a second - bit_offset: 0 - bit_size: 15 - - name: ADD1S - description: Add one second - bit_offset: 31 - bit_size: 1 + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 fieldset/SSR: description: Sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TAFCR: description: Tamper and alternate function configuration register fields: - - name: TAMPE - description: Tamper detection enable - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 5 - - name: TAMPTRG - description: Active level for tamper - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 5 - enum: TAMPTRG - - name: TAMPIE - description: Tamper interrupt enable - bit_offset: 2 - bit_size: 1 - - name: TAMPTS - description: Activate timestamp on tamper detection event - bit_offset: 7 - bit_size: 1 - - name: TAMPFREQ - description: Tamper sampling frequency - bit_offset: 8 - bit_size: 3 - enum: TAMPFREQ - - name: TAMPFLT - description: Tamper filter count - bit_offset: 11 - bit_size: 2 - enum: TAMPFLT - - name: TAMPPRCH - description: Tamper precharge duration - bit_offset: 13 - bit_size: 2 - enum: TAMPPRCH - - name: TAMPPUDIS - description: Tamper pull-up disable - bit_offset: 15 - bit_size: 1 - enum: TAMPPUDIS - - name: ALARMOUTTYPE - description: AFO_ALARM output type - bit_offset: 18 - bit_size: 1 + - name: TAMPE + description: Tamper detection enable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 5 + - name: TAMPTRG + description: Active level for tamper + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 5 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: ALARMOUTTYPE + description: AFO_ALARM output type + bit_offset: 18 + bit_size: 1 fieldset/TR: description: Time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/TSDR: description: Timestamp date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 fieldset/TSSSR: description: Timestamp sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TSTR: description: Timestamp time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/WPR: description: Write protection register fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 fieldset/WUTR: description: Wakeup timer register fields: - - name: WUT - description: Wakeup auto-reload value bits - bit_offset: 0 - bit_size: 16 + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 enum/ALRMR_MSK: bit_size: 1 variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 enum/ALRMR_PM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/ALRMR_WDSEL: bit_size: 1 variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care" - value: 1 + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 enum/ALRWF: bit_size: 1 variants: - - name: UpdateNotAllowed - description: Alarm update not allowed - value: 0 - - name: UpdateAllowed - description: Alarm update allowed - value: 1 + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 enum/AMPM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/CALP: bit_size: 1 variants: - - name: NoChange - description: No RTCCLK pulses are added - value: 0 - - name: IncreaseFreq - description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - value: 1 + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 enum/CALW16: bit_size: 1 variants: - - name: Sixteen_Second - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" - value: 1 + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 enum/CALW8: bit_size: 1 variants: - - name: Eight_Second - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 enum/COSEL: bit_size: 1 variants: - - name: CalFreq_512Hz - description: Calibration output is 512 Hz (with default prescaler setting) - value: 0 - - name: CalFreq_1Hz - description: Calibration output is 1 Hz (with default prescaler setting) - value: 1 + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 enum/FMT: bit_size: 1 variants: - - name: Twenty_Four_Hour - description: 24 hour/day format - value: 0 - - name: AM_PM - description: AM/PM hour format - value: 1 + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 enum/INIT: bit_size: 1 variants: - - name: FreeRunningMode - description: Free running mode - value: 0 - - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." - value: 1 + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 enum/OSEL: bit_size: 2 variants: - - name: Disabled - description: Output disabled - value: 0 - - name: AlarmA - description: Alarm A output enabled - value: 1 - - name: AlarmB - description: Alarm B output enabled - value: 2 - - name: Wakeup - description: Wakeup output enabled - value: 3 + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 enum/POL: bit_size: 1 variants: - - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 0 - - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 1 + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 enum/RECALPF: bit_size: 1 variants: - - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" - value: 1 + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 enum/REFCKON: bit_size: 1 variants: - - name: Disabled - description: RTC_REFIN detection disabled - value: 0 - - name: Enabled - description: RTC_REFIN detection enabled - value: 1 + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 enum/TAMPFLT: bit_size: 2 variants: - - name: Immediate - description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - value: 0 - - name: Samples2 - description: Tamper event is activated after 2 consecutive samples at the active level - value: 1 - - name: Samples4 - description: Tamper event is activated after 4 consecutive samples at the active level - value: 2 - - name: Samples8 - description: Tamper event is activated after 8 consecutive samples at the active level - value: 3 + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 enum/TAMPFREQ: bit_size: 3 variants: - - name: Div32768 - description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - value: 0 - - name: Div16384 - description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - value: 1 - - name: Div8192 - description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - value: 2 - - name: Div4096 - description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - value: 3 - - name: Div2048 - description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - value: 4 - - name: Div1024 - description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - value: 5 - - name: Div512 - description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - value: 6 - - name: Div256 - description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - value: 7 + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 enum/TAMPPRCH: bit_size: 2 variants: - - name: Cycles1 - description: 1 RTCCLK cycle - value: 0 - - name: Cycles2 - description: 2 RTCCLK cycles - value: 1 - - name: Cycles4 - description: 4 RTCCLK cycles - value: 2 - - name: Cycles8 - description: 8 RTCCLK cycles - value: 3 + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 enum/TAMPPUDIS: bit_size: 1 variants: - - name: Enabled - description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - value: 0 - - name: Disabled - description: Disable precharge of RTC_TAMPx pins - value: 1 + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 enum/TAMPTRG: bit_size: 1 variants: - - name: RisingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." - value: 0 - - name: FallingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" - value: 1 + - name: RisingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.' + value: 0 + - name: FallingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event' + value: 1 enum/TSEDGE: bit_size: 1 variants: - - name: RisingEdge - description: RTC_TS input rising edge generates a time-stamp event - value: 0 - - name: FallingEdge - description: RTC_TS input falling edge generates a time-stamp event - value: 1 + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 enum/WUCKSEL: bit_size: 3 variants: - - name: Div16 - description: RTC/16 clock is selected - value: 0 - - name: Div8 - description: RTC/8 clock is selected - value: 1 - - name: Div4 - description: RTC/4 clock is selected - value: 2 - - name: Div2 - description: RTC/2 clock is selected - value: 3 - - name: ClockSpare - description: ck_spre (usually 1 Hz) clock is selected - value: 4 - - name: ClockSpareWithOffset - description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - value: 6 + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 diff --git a/data/registers/rtc_v2l4.yaml b/data/registers/rtc_v2l4.yaml index 0c4d309..bca17e2 100644 --- a/data/registers/rtc_v2l4.yaml +++ b/data/registers/rtc_v2l4.yaml @@ -1,842 +1,841 @@ ---- block/RTC: description: Real-time clock items: - - name: TR - description: Time register - byte_offset: 0 - fieldset: TR - - name: DR - description: Date register - byte_offset: 4 - fieldset: DR - - name: CR - description: Control register - byte_offset: 8 - fieldset: CR - - name: ISR - description: Initialization and status register - byte_offset: 12 - fieldset: ISR - - name: PRER - description: Prescaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: Wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: ALRMR - description: Alarm register - array: - len: 2 - stride: 4 - byte_offset: 28 - fieldset: ALRMR - - name: WPR - description: Write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: SSR - description: Sub second register - byte_offset: 40 - access: Read - fieldset: SSR - - name: SHIFTR - description: Shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TSTR - description: Timestamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: Timestamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TSSSR - description: Timestamp sub second register - byte_offset: 56 - access: Read - fieldset: TSSSR - - name: CALR - description: Calibration register - byte_offset: 60 - fieldset: CALR - - name: TAMPCR - description: Tamper configuration register - byte_offset: 64 - fieldset: TAMPCR - - name: ALRMSSR - description: Alarm sub second register - array: - len: 2 - stride: 4 - byte_offset: 68 - fieldset: ALRMSSR - - name: OR - description: Option register - byte_offset: 76 - fieldset: OR - - name: BKPR - description: Backup register - array: - len: 32 - stride: 4 - byte_offset: 80 - fieldset: BKPR + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAMPCR + description: Tamper configuration register + byte_offset: 64 + fieldset: TAMPCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: OR + description: Option register + byte_offset: 76 + fieldset: OR + - name: BKPR + description: Backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR fieldset/ALRMR: description: Alarm register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMR_MSK - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMR_MSK - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMR_PM - - name: MSK3 - description: Alarm hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMR_MSK - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMR_WDSEL - - name: MSK4 - description: Alarm date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMR_MSK + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK fieldset/ALRMSSR: description: Alarm sub second register fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 4 + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 fieldset/BKPR: description: Backup register fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/CALR: description: Calibration register fields: - - name: CALM - description: Calibration minus - bit_offset: 0 - bit_size: 9 - - name: CALW16 - description: Use a 16-second calibration cycle period - bit_offset: 13 - bit_size: 1 - enum: CALW16 - - name: CALW8 - description: Use an 8-second calibration cycle period - bit_offset: 14 - bit_size: 1 - enum: CALW8 - - name: CALP - description: Increase frequency of RTC by 488.5 ppm - bit_offset: 15 - bit_size: 1 - enum: CALP + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP fieldset/CR: description: Control register fields: - - name: WUCKSEL - description: Wakeup clock selection - bit_offset: 0 - bit_size: 3 - enum: WUCKSEL - - name: TSEDGE - description: Timestamp event active edge - bit_offset: 3 - bit_size: 1 - enum: TSEDGE - - name: REFCKON - description: Reference clock detection enable (50 or 60 Hz) - bit_offset: 4 - bit_size: 1 - enum: REFCKON - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - - name: FMT - description: Hour format - bit_offset: 6 - bit_size: 1 - enum: FMT - - name: ALRE - description: Alarm enable - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTE - description: Wakeup timer enable - bit_offset: 10 - bit_size: 1 - - name: TSE - description: Timestamp enable - bit_offset: 11 - bit_size: 1 - - name: ALRIE - description: Alarm interrupt enable - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTIE - description: Wakeup timer interrupt enable - bit_offset: 14 - bit_size: 1 - - name: TSIE - description: Timestamp interrupt enable - bit_offset: 15 - bit_size: 1 - - name: ADD1H - description: Add 1 hour (summer time change) - bit_offset: 16 - bit_size: 1 - - name: SUB1H - description: Subtract 1 hour (winter time change) - bit_offset: 17 - bit_size: 1 - - name: BKP - description: Backup - bit_offset: 18 - bit_size: 1 - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - enum: COSEL - - name: POL - description: Output polarity - bit_offset: 20 - bit_size: 1 - enum: POL - - name: OSEL - description: Output selection - bit_offset: 21 - bit_size: 2 - enum: OSEL - - name: COE - description: Calibration output enable - bit_offset: 23 - bit_size: 1 - - name: ITSE - description: Timestamp on internal event enable - bit_offset: 24 - bit_size: 1 + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRE + description: Alarm enable + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: Timestamp on internal event enable + bit_offset: 24 + bit_size: 1 fieldset/DR: description: Date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 fieldset/ISR: description: Initialization and status register fields: - - name: ALRWF - description: Alarm write flag - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: ALRWF - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - - name: RSF - description: Registers synchronization flag - bit_offset: 5 - bit_size: 1 - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - enum: INIT - - name: ALRF - description: Alarm flag - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTF - description: Wakeup timer flag - bit_offset: 10 - bit_size: 1 - - name: TSF - description: Timestamp flag - bit_offset: 11 - bit_size: 1 - - name: TSOVF - description: Timestamp overflow flag - bit_offset: 12 - bit_size: 1 - - name: TAMPF - description: Tamper detection flag - bit_offset: 13 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: RECALPF - description: Recalibration pending flag - bit_offset: 16 - bit_size: 1 - enum: RECALPF + - name: ALRWF + description: Alarm write flag + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: ALRWF + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + - name: TAMPF + description: Tamper detection flag + bit_offset: 13 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum: RECALPF fieldset/OR: description: Option register fields: - - name: RTC_ALARM_TYPE - description: RTC_ALARM on PC13 output type - bit_offset: 0 - bit_size: 1 - - name: RTC_OUT_RMP - description: RTC_OUT remap - bit_offset: 1 - bit_size: 1 + - name: RTC_ALARM_TYPE + description: RTC_ALARM on PC13 output type + bit_offset: 0 + bit_size: 1 + - name: RTC_OUT_RMP + description: RTC_OUT remap + bit_offset: 1 + bit_size: 1 fieldset/PRER: description: Prescaler register fields: - - name: PREDIV_S - description: Synchronous prescaler factor - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: Asynchronous prescaler factor - bit_offset: 16 - bit_size: 7 + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 fieldset/SHIFTR: description: Shift control register fields: - - name: SUBFS - description: Subtract a fraction of a second - bit_offset: 0 - bit_size: 15 - - name: ADD1S - description: Add one second - bit_offset: 31 - bit_size: 1 + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 fieldset/SSR: description: Sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TAMPCR: description: Tamper configuration register fields: - - name: TAMPE - description: Tamper detection enable - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 5 - - name: TAMPTRG - description: Active level for tamper - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 5 - enum: TAMPTRG - - name: TAMPIE - description: Tamper interrupt enable - bit_offset: 2 - bit_size: 1 - - name: TAMPTS - description: Activate timestamp on tamper detection event - bit_offset: 7 - bit_size: 1 - - name: TAMPFREQ - description: Tamper sampling frequency - bit_offset: 8 - bit_size: 3 - enum: TAMPFREQ - - name: TAMPFLT - description: Tamper filter count - bit_offset: 11 - bit_size: 2 - enum: TAMPFLT - - name: TAMPPRCH - description: Tamper precharge duration - bit_offset: 13 - bit_size: 2 - enum: TAMPPRCH - - name: TAMPPUDIS - description: Tamper pull-up disable - bit_offset: 15 - bit_size: 1 - enum: TAMPPUDIS - - name: TAMPXIE - description: Tamper interrupt enable - bit_offset: 16 - bit_size: 1 - array: - len: 3 - stride: 3 - - name: TAMPXNOERASE - description: Tamper no erase - bit_offset: 17 - bit_size: 1 - array: - len: 3 - stride: 3 - - name: TAMPXMF - description: Tamper mask flag - bit_offset: 18 - bit_size: 1 - array: - len: 3 - stride: 3 + - name: TAMPE + description: Tamper detection enable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 5 + - name: TAMPTRG + description: Active level for tamper + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 5 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: TAMPXIE + description: Tamper interrupt enable + bit_offset: 16 + bit_size: 1 + array: + len: 3 + stride: 3 + - name: TAMPXNOERASE + description: Tamper no erase + bit_offset: 17 + bit_size: 1 + array: + len: 3 + stride: 3 + - name: TAMPXMF + description: Tamper mask flag + bit_offset: 18 + bit_size: 1 + array: + len: 3 + stride: 3 fieldset/TR: description: Time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/TSDR: description: Timestamp date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 fieldset/TSSSR: description: Timestamp sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TSTR: description: Timestamp time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/WPR: description: Write protection register fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 fieldset/WUTR: description: Wakeup timer register fields: - - name: WUT - description: Wakeup auto-reload value bits - bit_offset: 0 - bit_size: 16 + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 enum/ALRMR_MSK: bit_size: 1 variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 enum/ALRMR_PM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/ALRMR_WDSEL: bit_size: 1 variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care" - value: 1 + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 enum/ALRWF: bit_size: 1 variants: - - name: UpdateNotAllowed - description: Alarm update not allowed - value: 0 - - name: UpdateAllowed - description: Alarm update allowed - value: 1 + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 enum/AMPM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/CALP: bit_size: 1 variants: - - name: NoChange - description: No RTCCLK pulses are added - value: 0 - - name: IncreaseFreq - description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - value: 1 + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 enum/CALW16: bit_size: 1 variants: - - name: Sixteen_Second - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" - value: 1 + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 enum/CALW8: bit_size: 1 variants: - - name: Eight_Second - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 enum/COSEL: bit_size: 1 variants: - - name: CalFreq_512Hz - description: Calibration output is 512 Hz (with default prescaler setting) - value: 0 - - name: CalFreq_1Hz - description: Calibration output is 1 Hz (with default prescaler setting) - value: 1 + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 enum/FMT: bit_size: 1 variants: - - name: Twenty_Four_Hour - description: 24 hour/day format - value: 0 - - name: AM_PM - description: AM/PM hour format - value: 1 + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 enum/INIT: bit_size: 1 variants: - - name: FreeRunningMode - description: Free running mode - value: 0 - - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." - value: 1 + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 enum/OSEL: bit_size: 2 variants: - - name: Disabled - description: Output disabled - value: 0 - - name: AlarmA - description: Alarm A output enabled - value: 1 - - name: AlarmB - description: Alarm B output enabled - value: 2 - - name: Wakeup - description: Wakeup output enabled - value: 3 + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 enum/POL: bit_size: 1 variants: - - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 0 - - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 1 + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 enum/RECALPF: bit_size: 1 variants: - - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" - value: 1 + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 enum/REFCKON: bit_size: 1 variants: - - name: Disabled - description: RTC_REFIN detection disabled - value: 0 - - name: Enabled - description: RTC_REFIN detection enabled - value: 1 + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 enum/TAMPFLT: bit_size: 2 variants: - - name: Immediate - description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - value: 0 - - name: Samples2 - description: Tamper event is activated after 2 consecutive samples at the active level - value: 1 - - name: Samples4 - description: Tamper event is activated after 4 consecutive samples at the active level - value: 2 - - name: Samples8 - description: Tamper event is activated after 8 consecutive samples at the active level - value: 3 + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 enum/TAMPFREQ: bit_size: 3 variants: - - name: Div32768 - description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - value: 0 - - name: Div16384 - description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - value: 1 - - name: Div8192 - description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - value: 2 - - name: Div4096 - description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - value: 3 - - name: Div2048 - description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - value: 4 - - name: Div1024 - description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - value: 5 - - name: Div512 - description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - value: 6 - - name: Div256 - description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - value: 7 + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 enum/TAMPPRCH: bit_size: 2 variants: - - name: Cycles1 - description: 1 RTCCLK cycle - value: 0 - - name: Cycles2 - description: 2 RTCCLK cycles - value: 1 - - name: Cycles4 - description: 4 RTCCLK cycles - value: 2 - - name: Cycles8 - description: 8 RTCCLK cycles - value: 3 + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 enum/TAMPPUDIS: bit_size: 1 variants: - - name: Enabled - description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - value: 0 - - name: Disabled - description: Disable precharge of RTC_TAMPx pins - value: 1 + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 enum/TAMPTRG: bit_size: 1 variants: - - name: RisingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." - value: 0 - - name: FallingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" - value: 1 + - name: RisingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.' + value: 0 + - name: FallingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event' + value: 1 enum/TSEDGE: bit_size: 1 variants: - - name: RisingEdge - description: RTC_TS input rising edge generates a time-stamp event - value: 0 - - name: FallingEdge - description: RTC_TS input falling edge generates a time-stamp event - value: 1 + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 enum/WUCKSEL: bit_size: 3 variants: - - name: Div16 - description: RTC/16 clock is selected - value: 0 - - name: Div8 - description: RTC/8 clock is selected - value: 1 - - name: Div4 - description: RTC/4 clock is selected - value: 2 - - name: Div2 - description: RTC/2 clock is selected - value: 3 - - name: ClockSpare - description: ck_spre (usually 1 Hz) clock is selected - value: 4 - - name: ClockSpareWithOffset - description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - value: 6 + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 diff --git a/data/registers/rtc_v2wb.yaml b/data/registers/rtc_v2wb.yaml index 0a0a11f..9530fc3 100644 --- a/data/registers/rtc_v2wb.yaml +++ b/data/registers/rtc_v2wb.yaml @@ -1,846 +1,845 @@ ---- block/RTC: description: Real-time clock items: - - name: TR - description: Time register - byte_offset: 0 - fieldset: TR - - name: DR - description: Date register - byte_offset: 4 - fieldset: DR - - name: CR - description: Control register - byte_offset: 8 - fieldset: CR - - name: ISR - description: Initialization and status register - byte_offset: 12 - fieldset: ISR - - name: PRER - description: Prescaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: Wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: ALRMR - description: Alarm register - array: - len: 2 - stride: 4 - byte_offset: 28 - fieldset: ALRMR - - name: WPR - description: Write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: SSR - description: Sub second register - byte_offset: 40 - access: Read - fieldset: SSR - - name: SHIFTR - description: Shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TSTR - description: Timestamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: Timestamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TSSSR - description: Timestamp sub second register - byte_offset: 56 - access: Read - fieldset: TSSSR - - name: CALR - description: Calibration register - byte_offset: 60 - fieldset: CALR - - name: TAMPCR - description: Tamper configuration register - byte_offset: 64 - fieldset: TAMPCR - - name: ALRMSSR - description: Alarm sub second register - array: - len: 2 - stride: 4 - byte_offset: 68 - fieldset: ALRMSSR - - name: OR - description: Option register - byte_offset: 76 - fieldset: OR - - name: BKPR - description: Backup register - array: - len: 20 - stride: 4 - byte_offset: 80 - fieldset: BKPR + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAMPCR + description: Tamper configuration register + byte_offset: 64 + fieldset: TAMPCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: OR + description: Option register + byte_offset: 76 + fieldset: OR + - name: BKPR + description: Backup register + array: + len: 20 + stride: 4 + byte_offset: 80 + fieldset: BKPR fieldset/ALRMR: description: Alarm register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMR_MSK - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMR_MSK - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMR_PM - - name: MSK3 - description: Alarm hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMR_MSK - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMR_WDSEL - - name: MSK4 - description: Alarm date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMR_MSK + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK fieldset/ALRMSSR: description: Alarm sub second register fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 4 + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 fieldset/BKPR: description: Backup register fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/CALR: description: Calibration register fields: - - name: CALM - description: Calibration minus - bit_offset: 0 - bit_size: 9 - - name: CALW16 - description: Use a 16-second calibration cycle period - bit_offset: 13 - bit_size: 1 - enum: CALW16 - - name: CALW8 - description: Use an 8-second calibration cycle period - bit_offset: 14 - bit_size: 1 - enum: CALW8 - - name: CALP - description: Increase frequency of RTC by 488.5 ppm - bit_offset: 15 - bit_size: 1 - enum: CALP + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP fieldset/CR: description: Control register fields: - - name: WUCKSEL - description: Wakeup clock selection - bit_offset: 0 - bit_size: 3 - enum: WUCKSEL - - name: TSEDGE - description: Timestamp event active edge - bit_offset: 3 - bit_size: 1 - enum: TSEDGE - - name: REFCKON - description: Reference clock detection enable (50 or 60 Hz) - bit_offset: 4 - bit_size: 1 - enum: REFCKON - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - - name: FMT - description: Hour format - bit_offset: 6 - bit_size: 1 - enum: FMT - - name: ALRE - description: Alarm enable - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTE - description: Wakeup timer enable - bit_offset: 10 - bit_size: 1 - - name: TSE - description: Timestamp enable - bit_offset: 11 - bit_size: 1 - - name: ALRIE - description: Alarm interrupt enable - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTIE - description: Wakeup timer interrupt enable - bit_offset: 14 - bit_size: 1 - - name: TSIE - description: Timestamp interrupt enable - bit_offset: 15 - bit_size: 1 - - name: ADD1H - description: Add 1 hour (summer time change) - bit_offset: 16 - bit_size: 1 - - name: SUB1H - description: Subtract 1 hour (winter time change) - bit_offset: 17 - bit_size: 1 - - name: BKP - description: Backup - bit_offset: 18 - bit_size: 1 - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - enum: COSEL - - name: POL - description: Output polarity - bit_offset: 20 - bit_size: 1 - enum: POL - - name: OSEL - description: Output selection - bit_offset: 21 - bit_size: 2 - enum: OSEL - - name: COE - description: Calibration output enable - bit_offset: 23 - bit_size: 1 - - name: ITSE - description: Timestamp on internal event enable - bit_offset: 24 - bit_size: 1 + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRE + description: Alarm enable + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: Timestamp on internal event enable + bit_offset: 24 + bit_size: 1 fieldset/DR: description: Date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 fieldset/ISR: description: Initialization and status register fields: - - name: ALRWF - description: Alarm write flag - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: ALRWF - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - - name: RSF - description: Registers synchronization flag - bit_offset: 5 - bit_size: 1 - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - enum: INIT - - name: ALRF - description: Alarm flag - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTF - description: Wakeup timer flag - bit_offset: 10 - bit_size: 1 - - name: TSF - description: Timestamp flag - bit_offset: 11 - bit_size: 1 - - name: TSOVF - description: Timestamp overflow flag - bit_offset: 12 - bit_size: 1 - - name: TAMPF - description: Tamper detection flag - bit_offset: 13 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: RECALPF - description: Recalibration pending flag - bit_offset: 16 - bit_size: 1 - enum: RECALPF - - name: ITSF - description: Internal time-stamp flag - bit_offset: 17 - bit_size: 1 + - name: ALRWF + description: Alarm write flag + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: ALRWF + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + - name: TAMPF + description: Tamper detection flag + bit_offset: 13 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum: RECALPF + - name: ITSF + description: Internal time-stamp flag + bit_offset: 17 + bit_size: 1 fieldset/OR: description: Option register fields: - - name: RTC_ALARM_TYPE - description: RTC_ALARM on PC13 output type - bit_offset: 0 - bit_size: 1 - - name: RTC_OUT_RMP - description: RTC_OUT remap - bit_offset: 1 - bit_size: 1 + - name: RTC_ALARM_TYPE + description: RTC_ALARM on PC13 output type + bit_offset: 0 + bit_size: 1 + - name: RTC_OUT_RMP + description: RTC_OUT remap + bit_offset: 1 + bit_size: 1 fieldset/PRER: description: Prescaler register fields: - - name: PREDIV_S - description: Synchronous prescaler factor - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: Asynchronous prescaler factor - bit_offset: 16 - bit_size: 7 + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 fieldset/SHIFTR: description: Shift control register fields: - - name: SUBFS - description: Subtract a fraction of a second - bit_offset: 0 - bit_size: 15 - - name: ADD1S - description: Add one second - bit_offset: 31 - bit_size: 1 + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 fieldset/SSR: description: Sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TAMPCR: description: Tamper configuration register fields: - - name: TAMPE - description: Tamper detection enable - bit_offset: 0 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 5 - - name: TAMPTRG - description: Active level for tamper - bit_offset: 1 - bit_size: 1 - array: - offsets: - - 0 - - 3 - - 5 - enum: TAMPTRG - - name: TAMPIE - description: Tamper interrupt enable - bit_offset: 2 - bit_size: 1 - - name: TAMPTS - description: Activate timestamp on tamper detection event - bit_offset: 7 - bit_size: 1 - - name: TAMPFREQ - description: Tamper sampling frequency - bit_offset: 8 - bit_size: 3 - enum: TAMPFREQ - - name: TAMPFLT - description: Tamper filter count - bit_offset: 11 - bit_size: 2 - enum: TAMPFLT - - name: TAMPPRCH - description: Tamper precharge duration - bit_offset: 13 - bit_size: 2 - enum: TAMPPRCH - - name: TAMPPUDIS - description: Tamper pull-up disable - bit_offset: 15 - bit_size: 1 - enum: TAMPPUDIS - - name: TAMPXIE - description: Tamper interrupt enable - bit_offset: 16 - bit_size: 1 - array: - len: 3 - stride: 3 - - name: TAMPXNOERASE - description: Tamper no erase - bit_offset: 17 - bit_size: 1 - array: - len: 3 - stride: 3 - - name: TAMPXMF - description: Tamper mask flag - bit_offset: 18 - bit_size: 1 - array: - len: 3 - stride: 3 + - name: TAMPE + description: Tamper detection enable + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 5 + - name: TAMPTRG + description: Active level for tamper + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 3 + - 5 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: TAMPXIE + description: Tamper interrupt enable + bit_offset: 16 + bit_size: 1 + array: + len: 3 + stride: 3 + - name: TAMPXNOERASE + description: Tamper no erase + bit_offset: 17 + bit_size: 1 + array: + len: 3 + stride: 3 + - name: TAMPXMF + description: Tamper mask flag + bit_offset: 18 + bit_size: 1 + array: + len: 3 + stride: 3 fieldset/TR: description: Time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/TSDR: description: Timestamp date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 fieldset/TSSSR: description: Timestamp sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TSTR: description: Timestamp time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/WPR: description: Write protection register fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 fieldset/WUTR: description: Wakeup timer register fields: - - name: WUT - description: Wakeup auto-reload value bits - bit_offset: 0 - bit_size: 16 + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 enum/ALRMR_MSK: bit_size: 1 variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 enum/ALRMR_PM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/ALRMR_WDSEL: bit_size: 1 variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care" - value: 1 + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 enum/ALRWF: bit_size: 1 variants: - - name: UpdateNotAllowed - description: Alarm update not allowed - value: 0 - - name: UpdateAllowed - description: Alarm update allowed - value: 1 + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 enum/AMPM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/CALP: bit_size: 1 variants: - - name: NoChange - description: No RTCCLK pulses are added - value: 0 - - name: IncreaseFreq - description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - value: 1 + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 enum/CALW16: bit_size: 1 variants: - - name: Sixteen_Second - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" - value: 1 + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 enum/CALW8: bit_size: 1 variants: - - name: Eight_Second - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 enum/COSEL: bit_size: 1 variants: - - name: CalFreq_512Hz - description: Calibration output is 512 Hz (with default prescaler setting) - value: 0 - - name: CalFreq_1Hz - description: Calibration output is 1 Hz (with default prescaler setting) - value: 1 + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 enum/FMT: bit_size: 1 variants: - - name: Twenty_Four_Hour - description: 24 hour/day format - value: 0 - - name: AM_PM - description: AM/PM hour format - value: 1 + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 enum/INIT: bit_size: 1 variants: - - name: FreeRunningMode - description: Free running mode - value: 0 - - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." - value: 1 + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 enum/OSEL: bit_size: 2 variants: - - name: Disabled - description: Output disabled - value: 0 - - name: AlarmA - description: Alarm A output enabled - value: 1 - - name: AlarmB - description: Alarm B output enabled - value: 2 - - name: Wakeup - description: Wakeup output enabled - value: 3 + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 enum/POL: bit_size: 1 variants: - - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 0 - - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 1 + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 enum/RECALPF: bit_size: 1 variants: - - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" - value: 1 + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 enum/REFCKON: bit_size: 1 variants: - - name: Disabled - description: RTC_REFIN detection disabled - value: 0 - - name: Enabled - description: RTC_REFIN detection enabled - value: 1 + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 enum/TAMPFLT: bit_size: 2 variants: - - name: Immediate - description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - value: 0 - - name: Samples2 - description: Tamper event is activated after 2 consecutive samples at the active level - value: 1 - - name: Samples4 - description: Tamper event is activated after 4 consecutive samples at the active level - value: 2 - - name: Samples8 - description: Tamper event is activated after 8 consecutive samples at the active level - value: 3 + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 enum/TAMPFREQ: bit_size: 3 variants: - - name: Div32768 - description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - value: 0 - - name: Div16384 - description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - value: 1 - - name: Div8192 - description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - value: 2 - - name: Div4096 - description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - value: 3 - - name: Div2048 - description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - value: 4 - - name: Div1024 - description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - value: 5 - - name: Div512 - description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - value: 6 - - name: Div256 - description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - value: 7 + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 enum/TAMPPRCH: bit_size: 2 variants: - - name: Cycles1 - description: 1 RTCCLK cycle - value: 0 - - name: Cycles2 - description: 2 RTCCLK cycles - value: 1 - - name: Cycles4 - description: 4 RTCCLK cycles - value: 2 - - name: Cycles8 - description: 8 RTCCLK cycles - value: 3 + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 enum/TAMPPUDIS: bit_size: 1 variants: - - name: Enabled - description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - value: 0 - - name: Disabled - description: Disable precharge of RTC_TAMPx pins - value: 1 + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 enum/TAMPTRG: bit_size: 1 variants: - - name: RisingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." - value: 0 - - name: FallingEdge - description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" - value: 1 + - name: RisingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.' + value: 0 + - name: FallingEdge + description: 'If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event' + value: 1 enum/TSEDGE: bit_size: 1 variants: - - name: RisingEdge - description: RTC_TS input rising edge generates a time-stamp event - value: 0 - - name: FallingEdge - description: RTC_TS input falling edge generates a time-stamp event - value: 1 + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 enum/WUCKSEL: bit_size: 3 variants: - - name: Div16 - description: RTC/16 clock is selected - value: 0 - - name: Div8 - description: RTC/8 clock is selected - value: 1 - - name: Div4 - description: RTC/4 clock is selected - value: 2 - - name: Div2 - description: RTC/2 clock is selected - value: 3 - - name: ClockSpare - description: ck_spre (usually 1 Hz) clock is selected - value: 4 - - name: ClockSpareWithOffset - description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - value: 6 + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 diff --git a/data/registers/rtc_v3.yaml b/data/registers/rtc_v3.yaml index 78024d5..e1c1841 100644 --- a/data/registers/rtc_v3.yaml +++ b/data/registers/rtc_v3.yaml @@ -1,975 +1,974 @@ ---- block/RTC: description: Real-time clock items: - - name: TR - description: Time register - byte_offset: 0 - fieldset: TR - - name: DR - description: Date register - byte_offset: 4 - fieldset: DR - - name: SSR - description: Sub second register - byte_offset: 8 - access: Read - fieldset: SSR - - name: ICSR - description: Initialization control and status register - byte_offset: 12 - fieldset: ICSR - - name: PRER - description: Prescaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: Wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: CR - description: Control register - byte_offset: 24 - fieldset: CR - - name: WPR - description: Write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: CALR - description: Calibration register - byte_offset: 40 - fieldset: CALR - - name: SHIFTR - description: Shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TSTR - description: Timestamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: Timestamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TSSSR - description: Timestamp sub second register - byte_offset: 56 - access: Read - fieldset: TSSSR - - name: ALRMR - description: Alarm register - array: - len: 2 - stride: 8 - byte_offset: 64 - fieldset: ALRMR - - name: ALRMSSR - description: Alarm sub second register - array: - len: 2 - stride: 8 - byte_offset: 68 - fieldset: ALRMSSR - - name: SR - description: Status register - byte_offset: 80 - access: Read - fieldset: SR - - name: MISR - description: Masked interrupt status register - byte_offset: 84 - access: Read - fieldset: MISR - - name: SCR - description: Status clear register - byte_offset: 92 - access: Write - fieldset: SCR - - name: ALRBINR - description: Alarm binary mode register - array: - len: 2 - stride: 4 - byte_offset: 112 - fieldset: ALRBINR + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: SSR + description: Sub second register + byte_offset: 8 + access: Read + fieldset: SSR + - name: ICSR + description: Initialization control and status register + byte_offset: 12 + fieldset: ICSR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CR + description: Control register + byte_offset: 24 + fieldset: CR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: CALR + description: Calibration register + byte_offset: 40 + fieldset: CALR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 8 + byte_offset: 64 + fieldset: ALRMR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 8 + byte_offset: 68 + fieldset: ALRMSSR + - name: SR + description: Status register + byte_offset: 80 + access: Read + fieldset: SR + - name: MISR + description: Masked interrupt status register + byte_offset: 84 + access: Read + fieldset: MISR + - name: SCR + description: Status clear register + byte_offset: 92 + access: Write + fieldset: SCR + - name: ALRBINR + description: Alarm binary mode register + array: + len: 2 + stride: 4 + byte_offset: 112 + fieldset: ALRBINR fieldset/ALRBINR: description: RTC alarm A binary mode register fields: - - name: SS - description: Synchronous counter alarm value in Binary mode - bit_offset: 0 - bit_size: 32 + - name: SS + description: Synchronous counter alarm value in Binary mode + bit_offset: 0 + bit_size: 32 fieldset/ALRMR: description: Alarm register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm A seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMR_MSK - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm A minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMR_MSK - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMR_PM - - name: MSK3 - description: Alarm A hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMR_MSK - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMR_WDSEL - - name: MSK4 - description: Alarm A date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMR_MSK + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK fieldset/ALRMSSR: description: Alarm sub second register fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 6 - - name: SSCLR - description: Clear synchronous counter on alarm (Binary mode only) - bit_offset: 31 - bit_size: 1 - enum: ALRMSSR_SSCLR + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 6 + - name: SSCLR + description: Clear synchronous counter on alarm (Binary mode only) + bit_offset: 31 + bit_size: 1 + enum: ALRMSSR_SSCLR fieldset/CALR: description: Calibration register fields: - - name: CALM - description: Calibration minus - bit_offset: 0 - bit_size: 9 - - name: LPCAL - description: Calibration low-power mode - bit_offset: 12 - bit_size: 1 - enum: LPCAL - - name: CALW16 - description: Use a 16-second calibration cycle period - bit_offset: 13 - bit_size: 1 - enum: CALW16 - - name: CALW8 - description: Use an 8-second calibration cycle period - bit_offset: 14 - bit_size: 1 - enum: CALW8 - - name: CALP - description: Increase frequency of RTC by 488.5 ppm - bit_offset: 15 - bit_size: 1 - enum: CALP + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: LPCAL + description: Calibration low-power mode + bit_offset: 12 + bit_size: 1 + enum: LPCAL + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP fieldset/CR: description: Control register fields: - - name: WUCKSEL - description: Wakeup clock selection - bit_offset: 0 - bit_size: 3 - enum: WUCKSEL - - name: TSEDGE - description: Timestamp event active edge - bit_offset: 3 - bit_size: 1 - enum: TSEDGE - - name: REFCKON - description: RTC_REFIN reference clock detection enable (50 or 60 Hz) - bit_offset: 4 - bit_size: 1 - enum: REFCKON - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - - name: FMT - description: Hour format - bit_offset: 6 - bit_size: 1 - enum: FMT - - name: SSRUIE - description: SSR underflow interrupt enable - bit_offset: 7 - bit_size: 1 - - name: ALRE - description: Alarm enable - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTE - description: Wakeup timer enable - bit_offset: 10 - bit_size: 1 - - name: TSE - description: Timestamp enable - bit_offset: 11 - bit_size: 1 - - name: ALRAIE - description: Alarm interrupt enable - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTIE - description: Wakeup timer interrupt enable - bit_offset: 14 - bit_size: 1 - - name: TSIE - description: Timestamp interrupt enable - bit_offset: 15 - bit_size: 1 - - name: ADD1H - description: Add 1 hour (summer time change) - bit_offset: 16 - bit_size: 1 - - name: SUB1H - description: Subtract 1 hour (winter time change) - bit_offset: 17 - bit_size: 1 - - name: BKP - description: Backup - bit_offset: 18 - bit_size: 1 - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - enum: COSEL - - name: POL - description: Output polarity - bit_offset: 20 - bit_size: 1 - enum: POL - - name: OSEL - description: Output selection - bit_offset: 21 - bit_size: 2 - enum: OSEL - - name: COE - description: Calibration output enable - bit_offset: 23 - bit_size: 1 - - name: ITSE - description: Timestamp on internal event enable - bit_offset: 24 - bit_size: 1 - - name: TAMPTS - description: Activate timestamp on tamper detection event - bit_offset: 25 - bit_size: 1 - - name: TAMPOE - description: Tamper detection output enable on TAMPALRM - bit_offset: 26 - bit_size: 1 - - name: TAMPALRM_PU - description: TAMPALRM pull-up enable - bit_offset: 29 - bit_size: 1 - enum: TAMPALRM_PU - - name: TAMPALRM_TYPE - description: TAMPALRM output type - bit_offset: 30 - bit_size: 1 - enum: TAMPALRM_TYPE - - name: OUT2EN - description: RTC_OUT2 output enable - bit_offset: 31 - bit_size: 1 + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: RTC_REFIN reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: SSRUIE + description: SSR underflow interrupt enable + bit_offset: 7 + bit_size: 1 + - name: ALRE + description: Alarm enable + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRAIE + description: Alarm interrupt enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: Timestamp on internal event enable + bit_offset: 24 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 25 + bit_size: 1 + - name: TAMPOE + description: Tamper detection output enable on TAMPALRM + bit_offset: 26 + bit_size: 1 + - name: TAMPALRM_PU + description: TAMPALRM pull-up enable + bit_offset: 29 + bit_size: 1 + enum: TAMPALRM_PU + - name: TAMPALRM_TYPE + description: TAMPALRM output type + bit_offset: 30 + bit_size: 1 + enum: TAMPALRM_TYPE + - name: OUT2EN + description: RTC_OUT2 output enable + bit_offset: 31 + bit_size: 1 fieldset/DR: description: Date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 fieldset/ICSR: description: Initialization control and status register fields: - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - - name: RSF - description: Registers synchronization flag - bit_offset: 5 - bit_size: 1 - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - enum: INIT - - name: BIN - description: Binary mode - bit_offset: 8 - bit_size: 2 - enum: BIN - - name: BCDU - description: BCD update - bit_offset: 10 - bit_size: 3 - enum: BCDU - - name: RECALPF - description: Recalibration pending Flag - bit_offset: 16 - bit_size: 1 - enum: RECALPF + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: BIN + description: Binary mode + bit_offset: 8 + bit_size: 2 + enum: BIN + - name: BCDU + description: BCD update + bit_offset: 10 + bit_size: 3 + enum: BCDU + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 + enum: RECALPF fieldset/MISR: description: Masked interrupt status register fields: - - name: ALRMF - description: Alarm masked flag - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: ALRMF - - name: WUTMF - description: Wakeup timer masked flag - bit_offset: 2 - bit_size: 1 - enum: WUTMF - - name: TSMF - description: Timestamp masked flag - bit_offset: 3 - bit_size: 1 - enum: TSMF - - name: TSOVMF - description: Timestamp overflow masked flag - bit_offset: 4 - bit_size: 1 - enum: TSOVMF - - name: ITSMF - description: Internal timestamp masked flag - bit_offset: 5 - bit_size: 1 - enum: ITSMF - - name: SSRUMF - description: SSR underflow masked flag - bit_offset: 6 - bit_size: 1 - enum: SSRUMF + - name: ALRMF + description: Alarm masked flag + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: ALRMF + - name: WUTMF + description: Wakeup timer masked flag + bit_offset: 2 + bit_size: 1 + enum: WUTMF + - name: TSMF + description: Timestamp masked flag + bit_offset: 3 + bit_size: 1 + enum: TSMF + - name: TSOVMF + description: Timestamp overflow masked flag + bit_offset: 4 + bit_size: 1 + enum: TSOVMF + - name: ITSMF + description: Internal timestamp masked flag + bit_offset: 5 + bit_size: 1 + enum: ITSMF + - name: SSRUMF + description: SSR underflow masked flag + bit_offset: 6 + bit_size: 1 + enum: SSRUMF fieldset/PRER: description: Prescaler register fields: - - name: PREDIV_S - description: Synchronous prescaler factor - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: Asynchronous prescaler factor - bit_offset: 16 - bit_size: 7 + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 fieldset/SCR: description: Status clear register fields: - - name: CALRF - description: Clear alarm A flag - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: CALRF - - name: CWUTF - description: Clear wakeup timer flag - bit_offset: 2 - bit_size: 1 - enum: CALRF - - name: CTSF - description: Clear timestamp flag - bit_offset: 3 - bit_size: 1 - enum: CALRF - - name: CTSOVF - description: Clear timestamp overflow flag - bit_offset: 4 - bit_size: 1 - enum: CALRF - - name: CITSF - description: Clear internal timestamp flag - bit_offset: 5 - bit_size: 1 - enum: CALRF - - name: CSSRUF - description: Clear SSR underflow flag - bit_offset: 6 - bit_size: 1 - enum: CALRF + - name: CALRF + description: Clear alarm A flag + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: CALRF + - name: CWUTF + description: Clear wakeup timer flag + bit_offset: 2 + bit_size: 1 + enum: CALRF + - name: CTSF + description: Clear timestamp flag + bit_offset: 3 + bit_size: 1 + enum: CALRF + - name: CTSOVF + description: Clear timestamp overflow flag + bit_offset: 4 + bit_size: 1 + enum: CALRF + - name: CITSF + description: Clear internal timestamp flag + bit_offset: 5 + bit_size: 1 + enum: CALRF + - name: CSSRUF + description: Clear SSR underflow flag + bit_offset: 6 + bit_size: 1 + enum: CALRF fieldset/SHIFTR: description: Shift control register fields: - - name: SUBFS - description: Subtract a fraction of a second - bit_offset: 0 - bit_size: 15 - - name: ADD1S - description: Add one second - bit_offset: 31 - bit_size: 1 + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 fieldset/SR: description: Status register fields: - - name: ALRF - description: Alarm flag - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: ALRF - - name: WUTF - description: Wakeup timer flag - bit_offset: 2 - bit_size: 1 - enum: WUTF - - name: TSF - description: Timestamp flag - bit_offset: 3 - bit_size: 1 - enum: TSF - - name: TSOVF - description: Timestamp overflow flag - bit_offset: 4 - bit_size: 1 - enum: TSOVF - - name: ITSF - description: Internal timestamp flag - bit_offset: 5 - bit_size: 1 - enum: ITSF - - name: SSRUF - description: SSR underflow flag - bit_offset: 6 - bit_size: 1 - enum: SSRUF + - name: ALRF + description: Alarm flag + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: ALRF + - name: WUTF + description: Wakeup timer flag + bit_offset: 2 + bit_size: 1 + enum: WUTF + - name: TSF + description: Timestamp flag + bit_offset: 3 + bit_size: 1 + enum: TSF + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 4 + bit_size: 1 + enum: TSOVF + - name: ITSF + description: Internal timestamp flag + bit_offset: 5 + bit_size: 1 + enum: ITSF + - name: SSRUF + description: SSR underflow flag + bit_offset: 6 + bit_size: 1 + enum: SSRUF fieldset/SSR: description: Sub second register fields: - - name: SS - description: Synchronous binary counter - bit_offset: 0 - bit_size: 32 + - name: SS + description: Synchronous binary counter + bit_offset: 0 + bit_size: 32 fieldset/TR: description: Time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/TSDR: description: Timestamp date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 fieldset/TSSSR: description: Timestamp sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 32 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 32 fieldset/TSTR: description: Timestamp time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 fieldset/WPR: description: Write protection register fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 - enum: KEY + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 + enum: KEY fieldset/WUTR: description: Wakeup timer register fields: - - name: WUT - description: Wakeup auto-reload value bits - bit_offset: 0 - bit_size: 16 - - name: WUTOCLR - description: Wakeup auto-reload output clear value - bit_offset: 16 - bit_size: 16 + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 + - name: WUTOCLR + description: Wakeup auto-reload output clear value + bit_offset: 16 + bit_size: 16 enum/ALRF: bit_size: 1 variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - value: 1 + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 enum/ALRMF: bit_size: 1 variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - value: 1 + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 enum/ALRMR_MSK: bit_size: 1 variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 enum/ALRMR_PM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/ALRMR_WDSEL: bit_size: 1 variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care." - value: 1 + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care. + value: 1 enum/ALRMSSR_SSCLR: bit_size: 1 variants: - - name: FreeRunning - description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running" - value: 0 - - name: ALRMBINR - description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0]" - value: 1 + - name: FreeRunning + description: The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running + value: 0 + - name: ALRMBINR + description: The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0] + value: 1 enum/AMPM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/BCDU: bit_size: 3 variants: - - name: Bit7 - description: "1s increment each time SS[7:0]=0" - value: 0 - - name: Bit8 - description: "1s increment each time SS[8:0]=0" - value: 1 - - name: Bit9 - description: "1s increment each time SS[9:0]=0" - value: 2 - - name: Bit10 - description: "1s increment each time SS[10:0]=0" - value: 3 - - name: Bit11 - description: "1s increment each time SS[11:0]=0" - value: 4 - - name: Bit12 - description: "1s increment each time SS[12:0]=0" - value: 5 - - name: Bit13 - description: "1s increment each time SS[13:0]=0" - value: 6 - - name: Bit14 - description: "1s increment each time SS[14:0]=0" - value: 7 + - name: Bit7 + description: 1s increment each time SS[7:0]=0 + value: 0 + - name: Bit8 + description: 1s increment each time SS[8:0]=0 + value: 1 + - name: Bit9 + description: 1s increment each time SS[9:0]=0 + value: 2 + - name: Bit10 + description: 1s increment each time SS[10:0]=0 + value: 3 + - name: Bit11 + description: 1s increment each time SS[11:0]=0 + value: 4 + - name: Bit12 + description: 1s increment each time SS[12:0]=0 + value: 5 + - name: Bit13 + description: 1s increment each time SS[13:0]=0 + value: 6 + - name: Bit14 + description: 1s increment each time SS[14:0]=0 + value: 7 enum/BIN: bit_size: 2 variants: - - name: BCD - description: Free running BCD calendar mode (Binary mode disabled) - value: 0 - - name: Binary - description: Free running Binary mode (BCD mode disabled) - value: 1 - - name: BinBCD - description: Free running BCD calendar and Binary modes - value: 2 - - name: BinBCD2 - description: Free running BCD calendar and Binary modes - value: 3 + - name: BCD + description: Free running BCD calendar mode (Binary mode disabled) + value: 0 + - name: Binary + description: Free running Binary mode (BCD mode disabled) + value: 1 + - name: BinBCD + description: Free running BCD calendar and Binary modes + value: 2 + - name: BinBCD2 + description: Free running BCD calendar and Binary modes + value: 3 enum/CALP: bit_size: 1 variants: - - name: NoChange - description: No RTCCLK pulses are added - value: 0 - - name: IncreaseFreq - description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - value: 1 + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 enum/CALRF: bit_size: 1 variants: - - name: Clear - description: Clear interrupt flag by writing 1 - value: 1 + - name: Clear + description: Clear interrupt flag by writing 1 + value: 1 enum/CALW16: bit_size: 1 variants: - - name: SixteenSeconds - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" - value: 1 + - name: SixteenSeconds + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 enum/CALW8: bit_size: 1 variants: - - name: EightSeconds - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 + - name: EightSeconds + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 enum/COSEL: bit_size: 1 variants: - - name: CalFreq_512Hz - description: Calibration output is 512 Hz (with default prescaler setting) - value: 0 - - name: CalFreq_1Hz - description: Calibration output is 1 Hz (with default prescaler setting) - value: 1 + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 enum/FMT: bit_size: 1 variants: - - name: TwentyFourHour - description: 24 hour/day format - value: 0 - - name: AmPm - description: AM/PM hour format - value: 1 + - name: TwentyFourHour + description: 24 hour/day format + value: 0 + - name: AmPm + description: AM/PM hour format + value: 1 enum/INIT: bit_size: 1 variants: - - name: FreeRunningMode - description: Free running mode - value: 0 - - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." - value: 1 + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 enum/ITSF: bit_size: 1 variants: - - name: TimestampEvent - description: This flag is set by hardware when a timestamp on the internal event occurs - value: 1 + - name: TimestampEvent + description: This flag is set by hardware when a timestamp on the internal event occurs + value: 1 enum/ITSMF: bit_size: 1 variants: - - name: TimestampEvent - description: This flag is set by hardware when a timestamp on the internal event occurs - value: 1 + - name: TimestampEvent + description: This flag is set by hardware when a timestamp on the internal event occurs + value: 1 enum/KEY: bit_size: 8 variants: - - name: Activate - description: Activate write protection (any value that is not the keys) - value: 0 - - name: Deactivate2 - description: Key 2 - value: 83 - - name: Deactivate1 - description: Key 1 - value: 202 + - name: Activate + description: Activate write protection (any value that is not the keys) + value: 0 + - name: Deactivate2 + description: Key 2 + value: 83 + - name: Deactivate1 + description: Key 1 + value: 202 enum/LPCAL: bit_size: 1 variants: - - name: RTCCLK - description: "Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required" - value: 0 - - name: CkApre - description: "Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode" - value: 1 + - name: RTCCLK + description: Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required + value: 0 + - name: CkApre + description: Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode + value: 1 enum/OSEL: bit_size: 2 variants: - - name: Disabled - description: Output disabled - value: 0 - - name: AlarmA - description: Alarm A output enabled - value: 1 - - name: AlarmB - description: Alarm B output enabled - value: 2 - - name: Wakeup - description: Wakeup output enabled - value: 3 + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 enum/POL: bit_size: 1 variants: - - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 0 - - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 1 + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 enum/RECALPF: bit_size: 1 variants: - - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" - value: 1 + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 enum/REFCKON: bit_size: 1 variants: - - name: Disabled - description: RTC_REFIN detection disabled - value: 0 - - name: Enabled - description: RTC_REFIN detection enabled - value: 1 + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 enum/SSRUF: bit_size: 1 variants: - - name: Underflow - description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 - value: 1 + - name: Underflow + description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 + value: 1 enum/SSRUMF: bit_size: 1 variants: - - name: Underflow - description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 - value: 1 + - name: Underflow + description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 + value: 1 enum/TAMPALRM_PU: bit_size: 1 variants: - - name: NoPullUp - description: No pull-up is applied on TAMPALRM output - value: 0 - - name: PullUp - description: A pull-up is applied on TAMPALRM output - value: 1 + - name: NoPullUp + description: No pull-up is applied on TAMPALRM output + value: 0 + - name: PullUp + description: A pull-up is applied on TAMPALRM output + value: 1 enum/TAMPALRM_TYPE: bit_size: 1 variants: - - name: PushPull - description: TAMPALRM is push-pull output - value: 0 - - name: OpenDrain - description: TAMPALRM is open-drain output - value: 1 + - name: PushPull + description: TAMPALRM is push-pull output + value: 0 + - name: OpenDrain + description: TAMPALRM is open-drain output + value: 1 enum/TSEDGE: bit_size: 1 variants: - - name: RisingEdge - description: RTC_TS input rising edge generates a time-stamp event - value: 0 - - name: FallingEdge - description: RTC_TS input falling edge generates a time-stamp event - value: 1 + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 enum/TSF: bit_size: 1 variants: - - name: TimestampEvent - description: This flag is set by hardware when a time-stamp event occurs - value: 1 + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 enum/TSMF: bit_size: 1 variants: - - name: TimestampEvent - description: This flag is set by hardware when a time-stamp event occurs - value: 1 + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 enum/TSOVF: bit_size: 1 variants: - - name: Overflow - description: This flag is set by hardware when a time-stamp event occurs while TSF is already set - value: 1 + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 enum/TSOVMF: bit_size: 1 variants: - - name: Overflow - description: This flag is set by hardware when a time-stamp event occurs while TSF is already set - value: 1 + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 enum/WUCKSEL: bit_size: 3 variants: - - name: Div16 - description: RTC/16 clock is selected - value: 0 - - name: Div8 - description: RTC/8 clock is selected - value: 1 - - name: Div4 - description: RTC/4 clock is selected - value: 2 - - name: Div2 - description: RTC/2 clock is selected - value: 3 - - name: ClockSpare - description: ck_spre (usually 1 Hz) clock is selected - value: 4 - - name: ClockSpareWithOffset - description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - value: 6 + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 enum/WUTF: bit_size: 1 variants: - - name: Zero - description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 - value: 1 + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 enum/WUTMF: bit_size: 1 variants: - - name: Zero - description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 - value: 1 + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 diff --git a/data/registers/rtc_v3u5.yaml b/data/registers/rtc_v3u5.yaml index 59857e5..fe764d1 100644 --- a/data/registers/rtc_v3u5.yaml +++ b/data/registers/rtc_v3u5.yaml @@ -1,1088 +1,1087 @@ ---- block/RTC: description: Real-time clock items: - - name: TR - description: Time register - byte_offset: 0 - fieldset: TR - - name: DR - description: Date register - byte_offset: 4 - fieldset: DR - - name: SSR - description: Sub second register - byte_offset: 8 - access: Read - fieldset: SSR - - name: ICSR - description: Initialization control and status register - byte_offset: 12 - fieldset: ICSR - - name: PRER - description: Prescaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: Wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: CR - description: Control register - byte_offset: 24 - fieldset: CR - - name: PRIVCR - description: Privilege mode control register - byte_offset: 28 - fieldset: PRIVCR - - name: SECCFGR - description: Secure mode control register - byte_offset: 32 - fieldset: SECCFGR - - name: WPR - description: Write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: CALR - description: Calibration register - byte_offset: 40 - fieldset: CALR - - name: SHIFTR - description: Shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TSTR - description: Timestamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: Timestamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TSSSR - description: Timestamp sub second register - byte_offset: 56 - access: Read - fieldset: TSSSR - - name: ALRMR - description: Alarm register - array: - len: 2 - stride: 8 - byte_offset: 64 - fieldset: ALRMR - - name: ALRMSSR - description: Alarm sub second register - array: - len: 2 - stride: 8 - byte_offset: 68 - fieldset: ALRMSSR - - name: SR - description: Status register - byte_offset: 80 - access: Read - fieldset: SR - - name: MISR - description: Masked interrupt status register - byte_offset: 84 - access: Read - fieldset: MISR - - name: SMISR - description: Secure masked interrupt status register - byte_offset: 88 - access: Read - fieldset: SMISR - - name: SCR - description: Status clear register - byte_offset: 92 - access: Write - fieldset: SCR - - name: ALRBINR - description: Alarm binary mode register - array: - len: 2 - stride: 4 - byte_offset: 112 - fieldset: ALRBINR + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: SSR + description: Sub second register + byte_offset: 8 + access: Read + fieldset: SSR + - name: ICSR + description: Initialization control and status register + byte_offset: 12 + fieldset: ICSR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CR + description: Control register + byte_offset: 24 + fieldset: CR + - name: PRIVCR + description: Privilege mode control register + byte_offset: 28 + fieldset: PRIVCR + - name: SECCFGR + description: Secure mode control register + byte_offset: 32 + fieldset: SECCFGR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: CALR + description: Calibration register + byte_offset: 40 + fieldset: CALR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 8 + byte_offset: 64 + fieldset: ALRMR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 8 + byte_offset: 68 + fieldset: ALRMSSR + - name: SR + description: Status register + byte_offset: 80 + access: Read + fieldset: SR + - name: MISR + description: Masked interrupt status register + byte_offset: 84 + access: Read + fieldset: MISR + - name: SMISR + description: Secure masked interrupt status register + byte_offset: 88 + access: Read + fieldset: SMISR + - name: SCR + description: Status clear register + byte_offset: 92 + access: Write + fieldset: SCR + - name: ALRBINR + description: Alarm binary mode register + array: + len: 2 + stride: 4 + byte_offset: 112 + fieldset: ALRBINR fieldset/ALRBINR: description: RTC alarm A binary mode register fields: - - name: SS - description: Synchronous counter alarm value in Binary mode - bit_offset: 0 - bit_size: 32 + - name: SS + description: Synchronous counter alarm value in Binary mode + bit_offset: 0 + bit_size: 32 fieldset/ALRMR: description: Alarm register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm A seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMR_MSK - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm A minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMR_MSK - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMR_PM - - name: MSK3 - description: Alarm A hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMR_MSK - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMR_WDSEL - - name: MSK4 - description: Alarm A date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMR_MSK + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK fieldset/ALRMSSR: description: Alarm sub second register fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 6 - - name: SSCLR - description: Clear synchronous counter on alarm (Binary mode only) - bit_offset: 31 - bit_size: 1 - enum: ALRMSSR_SSCLR + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 6 + - name: SSCLR + description: Clear synchronous counter on alarm (Binary mode only) + bit_offset: 31 + bit_size: 1 + enum: ALRMSSR_SSCLR fieldset/CALR: description: Calibration register fields: - - name: CALM - description: Calibration minus - bit_offset: 0 - bit_size: 9 - - name: LPCAL - description: Calibration low-power mode - bit_offset: 12 - bit_size: 1 - enum: LPCAL - - name: CALW16 - description: Use a 16-second calibration cycle period - bit_offset: 13 - bit_size: 1 - enum: CALW16 - - name: CALW8 - description: Use an 8-second calibration cycle period - bit_offset: 14 - bit_size: 1 - enum: CALW8 - - name: CALP - description: Increase frequency of RTC by 488.5 ppm - bit_offset: 15 - bit_size: 1 - enum: CALP + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: LPCAL + description: Calibration low-power mode + bit_offset: 12 + bit_size: 1 + enum: LPCAL + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP fieldset/CR: description: Control register fields: - - name: WUCKSEL - description: Wakeup clock selection - bit_offset: 0 - bit_size: 3 - enum: WUCKSEL - - name: TSEDGE - description: Timestamp event active edge - bit_offset: 3 - bit_size: 1 - enum: TSEDGE - - name: REFCKON - description: RTC_REFIN reference clock detection enable (50 or 60 Hz) - bit_offset: 4 - bit_size: 1 - enum: REFCKON - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - - name: FMT - description: Hour format - bit_offset: 6 - bit_size: 1 - enum: FMT - - name: SSRUIE - description: SSR underflow interrupt enable - bit_offset: 7 - bit_size: 1 - - name: ALRE - description: Alarm enable - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTE - description: Wakeup timer enable - bit_offset: 10 - bit_size: 1 - - name: TSE - description: Timestamp enable - bit_offset: 11 - bit_size: 1 - - name: ALRAIE - description: Alarm interrupt enable - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: WUTIE - description: Wakeup timer interrupt enable - bit_offset: 14 - bit_size: 1 - - name: TSIE - description: Timestamp interrupt enable - bit_offset: 15 - bit_size: 1 - - name: ADD1H - description: Add 1 hour (summer time change) - bit_offset: 16 - bit_size: 1 - - name: SUB1H - description: Subtract 1 hour (winter time change) - bit_offset: 17 - bit_size: 1 - - name: BKP - description: Backup - bit_offset: 18 - bit_size: 1 - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - enum: COSEL - - name: POL - description: Output polarity - bit_offset: 20 - bit_size: 1 - enum: POL - - name: OSEL - description: Output selection - bit_offset: 21 - bit_size: 2 - enum: OSEL - - name: COE - description: Calibration output enable - bit_offset: 23 - bit_size: 1 - - name: ITSE - description: Timestamp on internal event enable - bit_offset: 24 - bit_size: 1 - - name: TAMPTS - description: Activate timestamp on tamper detection event - bit_offset: 25 - bit_size: 1 - - name: TAMPOE - description: Tamper detection output enable on TAMPALRM - bit_offset: 26 - bit_size: 1 - - name: ALRFCLR - description: ALRFCLR - bit_offset: 27 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: TAMPALRM_PU - description: TAMPALRM pull-up enable - bit_offset: 29 - bit_size: 1 - enum: TAMPALRM_PU - - name: TAMPALRM_TYPE - description: TAMPALRM output type - bit_offset: 30 - bit_size: 1 - enum: TAMPALRM_TYPE - - name: OUT2EN - description: RTC_OUT2 output enable - bit_offset: 31 - bit_size: 1 + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: RTC_REFIN reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: SSRUIE + description: SSR underflow interrupt enable + bit_offset: 7 + bit_size: 1 + - name: ALRE + description: Alarm enable + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRAIE + description: Alarm interrupt enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: Timestamp on internal event enable + bit_offset: 24 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 25 + bit_size: 1 + - name: TAMPOE + description: Tamper detection output enable on TAMPALRM + bit_offset: 26 + bit_size: 1 + - name: ALRFCLR + description: ALRFCLR + bit_offset: 27 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: TAMPALRM_PU + description: TAMPALRM pull-up enable + bit_offset: 29 + bit_size: 1 + enum: TAMPALRM_PU + - name: TAMPALRM_TYPE + description: TAMPALRM output type + bit_offset: 30 + bit_size: 1 + enum: TAMPALRM_TYPE + - name: OUT2EN + description: RTC_OUT2 output enable + bit_offset: 31 + bit_size: 1 fieldset/DR: description: Date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 fieldset/ICSR: description: Initialization control and status register fields: - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - - name: RSF - description: Registers synchronization flag - bit_offset: 5 - bit_size: 1 - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - enum: INIT - - name: BIN - description: Binary mode - bit_offset: 8 - bit_size: 2 - enum: BIN - - name: BCDU - description: BCD update - bit_offset: 10 - bit_size: 3 - enum: BCDU - - name: RECALPF - description: Recalibration pending Flag - bit_offset: 16 - bit_size: 1 - enum: RECALPF + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: BIN + description: Binary mode + bit_offset: 8 + bit_size: 2 + enum: BIN + - name: BCDU + description: BCD update + bit_offset: 10 + bit_size: 3 + enum: BCDU + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 + enum: RECALPF fieldset/MISR: description: Masked interrupt status register fields: - - name: ALRMF - description: Alarm masked flag - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: ALRMF - - name: WUTMF - description: Wakeup timer masked flag - bit_offset: 2 - bit_size: 1 - enum: WUTMF - - name: TSMF - description: Timestamp masked flag - bit_offset: 3 - bit_size: 1 - enum: TSMF - - name: TSOVMF - description: Timestamp overflow masked flag - bit_offset: 4 - bit_size: 1 - enum: TSOVMF - - name: ITSMF - description: Internal timestamp masked flag - bit_offset: 5 - bit_size: 1 - enum: ITSMF - - name: SSRUMF - description: SSR underflow masked flag - bit_offset: 6 - bit_size: 1 - enum: SSRUMF + - name: ALRMF + description: Alarm masked flag + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: ALRMF + - name: WUTMF + description: Wakeup timer masked flag + bit_offset: 2 + bit_size: 1 + enum: WUTMF + - name: TSMF + description: Timestamp masked flag + bit_offset: 3 + bit_size: 1 + enum: TSMF + - name: TSOVMF + description: Timestamp overflow masked flag + bit_offset: 4 + bit_size: 1 + enum: TSOVMF + - name: ITSMF + description: Internal timestamp masked flag + bit_offset: 5 + bit_size: 1 + enum: ITSMF + - name: SSRUMF + description: SSR underflow masked flag + bit_offset: 6 + bit_size: 1 + enum: SSRUMF fieldset/PRER: description: Prescaler register fields: - - name: PREDIV_S - description: Synchronous prescaler factor - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: Asynchronous prescaler factor - bit_offset: 16 - bit_size: 7 + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 fieldset/PRIVCR: description: Privilege mode control register fields: - - name: ALRAPRIV - description: ALRAPRIV - bit_offset: 0 - bit_size: 1 - - name: ALRBPRIV - description: ALRBPRIV - bit_offset: 1 - bit_size: 1 - - name: WUTPRIV - description: WUTPRIV - bit_offset: 2 - bit_size: 1 - - name: TSPRIV - description: TSPRIV - bit_offset: 3 - bit_size: 1 - - name: CALPRIV - description: CALPRIV - bit_offset: 13 - bit_size: 1 - - name: INITPRIV - description: INITPRIV - bit_offset: 14 - bit_size: 1 - - name: PRIV - description: PRIV - bit_offset: 15 - bit_size: 1 + - name: ALRAPRIV + description: ALRAPRIV + bit_offset: 0 + bit_size: 1 + - name: ALRBPRIV + description: ALRBPRIV + bit_offset: 1 + bit_size: 1 + - name: WUTPRIV + description: WUTPRIV + bit_offset: 2 + bit_size: 1 + - name: TSPRIV + description: TSPRIV + bit_offset: 3 + bit_size: 1 + - name: CALPRIV + description: CALPRIV + bit_offset: 13 + bit_size: 1 + - name: INITPRIV + description: INITPRIV + bit_offset: 14 + bit_size: 1 + - name: PRIV + description: PRIV + bit_offset: 15 + bit_size: 1 fieldset/SCR: description: Status clear register fields: - - name: CALRF - description: Clear alarm A flag - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: CALRF - - name: CWUTF - description: Clear wakeup timer flag - bit_offset: 2 - bit_size: 1 - enum: CALRF - - name: CTSF - description: Clear timestamp flag - bit_offset: 3 - bit_size: 1 - enum: CALRF - - name: CTSOVF - description: Clear timestamp overflow flag - bit_offset: 4 - bit_size: 1 - enum: CALRF - - name: CITSF - description: Clear internal timestamp flag - bit_offset: 5 - bit_size: 1 - enum: CALRF - - name: CSSRUF - description: Clear SSR underflow flag - bit_offset: 6 - bit_size: 1 - enum: CALRF + - name: CALRF + description: Clear alarm A flag + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: CALRF + - name: CWUTF + description: Clear wakeup timer flag + bit_offset: 2 + bit_size: 1 + enum: CALRF + - name: CTSF + description: Clear timestamp flag + bit_offset: 3 + bit_size: 1 + enum: CALRF + - name: CTSOVF + description: Clear timestamp overflow flag + bit_offset: 4 + bit_size: 1 + enum: CALRF + - name: CITSF + description: Clear internal timestamp flag + bit_offset: 5 + bit_size: 1 + enum: CALRF + - name: CSSRUF + description: Clear SSR underflow flag + bit_offset: 6 + bit_size: 1 + enum: CALRF fieldset/SECCFGR: description: Secure mode control register fields: - - name: ALRASEC - description: ALRASEC - bit_offset: 0 - bit_size: 1 - - name: ALRBSEC - description: ALRBSEC - bit_offset: 1 - bit_size: 1 - - name: WUTSEC - description: WUTSEC - bit_offset: 2 - bit_size: 1 - - name: TSSEC - description: TSSEC - bit_offset: 3 - bit_size: 1 - - name: CALSEC - description: CALSEC - bit_offset: 13 - bit_size: 1 - - name: INITSEC - description: INITSEC - bit_offset: 14 - bit_size: 1 - - name: SEC - description: SEC - bit_offset: 15 - bit_size: 1 + - name: ALRASEC + description: ALRASEC + bit_offset: 0 + bit_size: 1 + - name: ALRBSEC + description: ALRBSEC + bit_offset: 1 + bit_size: 1 + - name: WUTSEC + description: WUTSEC + bit_offset: 2 + bit_size: 1 + - name: TSSEC + description: TSSEC + bit_offset: 3 + bit_size: 1 + - name: CALSEC + description: CALSEC + bit_offset: 13 + bit_size: 1 + - name: INITSEC + description: INITSEC + bit_offset: 14 + bit_size: 1 + - name: SEC + description: SEC + bit_offset: 15 + bit_size: 1 fieldset/SHIFTR: description: Shift control register fields: - - name: SUBFS - description: Subtract a fraction of a second - bit_offset: 0 - bit_size: 15 - - name: ADD1S - description: Add one second - bit_offset: 31 - bit_size: 1 + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 fieldset/SMISR: description: Secure masked interrupt status register fields: - - name: ALRAMF - description: ALRAMF - bit_offset: 0 - bit_size: 1 - - name: ALRBMF - description: ALRBMF - bit_offset: 1 - bit_size: 1 - - name: WUTMF - description: WUTMF - bit_offset: 2 - bit_size: 1 - - name: TSMF - description: TSMF - bit_offset: 3 - bit_size: 1 - - name: TSOVMF - description: TSOVMF - bit_offset: 4 - bit_size: 1 - - name: ITSMF - description: ITSMF - bit_offset: 5 - bit_size: 1 - - name: SSRUMF - description: SSRUMF - bit_offset: 6 - bit_size: 1 + - name: ALRAMF + description: ALRAMF + bit_offset: 0 + bit_size: 1 + - name: ALRBMF + description: ALRBMF + bit_offset: 1 + bit_size: 1 + - name: WUTMF + description: WUTMF + bit_offset: 2 + bit_size: 1 + - name: TSMF + description: TSMF + bit_offset: 3 + bit_size: 1 + - name: TSOVMF + description: TSOVMF + bit_offset: 4 + bit_size: 1 + - name: ITSMF + description: ITSMF + bit_offset: 5 + bit_size: 1 + - name: SSRUMF + description: SSRUMF + bit_offset: 6 + bit_size: 1 fieldset/SR: description: Status register fields: - - name: ALRF - description: Alarm flag - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: ALRF - - name: WUTF - description: Wakeup timer flag - bit_offset: 2 - bit_size: 1 - enum: WUTF - - name: TSF - description: Timestamp flag - bit_offset: 3 - bit_size: 1 - enum: TSF - - name: TSOVF - description: Timestamp overflow flag - bit_offset: 4 - bit_size: 1 - enum: TSOVF - - name: ITSF - description: Internal timestamp flag - bit_offset: 5 - bit_size: 1 - enum: ITSF - - name: SSRUF - description: SSR underflow flag - bit_offset: 6 - bit_size: 1 - enum: SSRUF + - name: ALRF + description: Alarm flag + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: ALRF + - name: WUTF + description: Wakeup timer flag + bit_offset: 2 + bit_size: 1 + enum: WUTF + - name: TSF + description: Timestamp flag + bit_offset: 3 + bit_size: 1 + enum: TSF + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 4 + bit_size: 1 + enum: TSOVF + - name: ITSF + description: Internal timestamp flag + bit_offset: 5 + bit_size: 1 + enum: ITSF + - name: SSRUF + description: SSR underflow flag + bit_offset: 6 + bit_size: 1 + enum: SSRUF fieldset/SSR: description: Sub second register fields: - - name: SS - description: Synchronous binary counter - bit_offset: 0 - bit_size: 32 + - name: SS + description: Synchronous binary counter + bit_offset: 0 + bit_size: 32 fieldset/TR: description: Time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: AMPM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM fieldset/TSDR: description: Timestamp date register fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 fieldset/TSSSR: description: Timestamp sub second register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 32 + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 32 fieldset/TSTR: description: Timestamp time register fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 fieldset/WPR: description: Write protection register fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 - enum: KEY + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 + enum: KEY fieldset/WUTR: description: Wakeup timer register fields: - - name: WUT - description: Wakeup auto-reload value bits - bit_offset: 0 - bit_size: 16 - - name: WUTOCLR - description: Wakeup auto-reload output clear value - bit_offset: 16 - bit_size: 16 + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 + - name: WUTOCLR + description: Wakeup auto-reload output clear value + bit_offset: 16 + bit_size: 16 enum/ALRF: bit_size: 1 variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - value: 1 + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 enum/ALRMF: bit_size: 1 variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - value: 1 + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 enum/ALRMR_MSK: bit_size: 1 variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 enum/ALRMR_PM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/ALRMR_WDSEL: bit_size: 1 variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care." - value: 1 + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care. + value: 1 enum/ALRMSSR_SSCLR: bit_size: 1 variants: - - name: FreeRunning - description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running" - value: 0 - - name: ALRMBINR - description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0]" - value: 1 + - name: FreeRunning + description: The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running + value: 0 + - name: ALRMBINR + description: The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0] + value: 1 enum/AMPM: bit_size: 1 variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 enum/BCDU: bit_size: 3 variants: - - name: Bit7 - description: "1s increment each time SS[7:0]=0" - value: 0 - - name: Bit8 - description: "1s increment each time SS[8:0]=0" - value: 1 - - name: Bit9 - description: "1s increment each time SS[9:0]=0" - value: 2 - - name: Bit10 - description: "1s increment each time SS[10:0]=0" - value: 3 - - name: Bit11 - description: "1s increment each time SS[11:0]=0" - value: 4 - - name: Bit12 - description: "1s increment each time SS[12:0]=0" - value: 5 - - name: Bit13 - description: "1s increment each time SS[13:0]=0" - value: 6 - - name: Bit14 - description: "1s increment each time SS[14:0]=0" - value: 7 + - name: Bit7 + description: 1s increment each time SS[7:0]=0 + value: 0 + - name: Bit8 + description: 1s increment each time SS[8:0]=0 + value: 1 + - name: Bit9 + description: 1s increment each time SS[9:0]=0 + value: 2 + - name: Bit10 + description: 1s increment each time SS[10:0]=0 + value: 3 + - name: Bit11 + description: 1s increment each time SS[11:0]=0 + value: 4 + - name: Bit12 + description: 1s increment each time SS[12:0]=0 + value: 5 + - name: Bit13 + description: 1s increment each time SS[13:0]=0 + value: 6 + - name: Bit14 + description: 1s increment each time SS[14:0]=0 + value: 7 enum/BIN: bit_size: 2 variants: - - name: BCD - description: Free running BCD calendar mode (Binary mode disabled) - value: 0 - - name: Binary - description: Free running Binary mode (BCD mode disabled) - value: 1 - - name: BinBCD - description: Free running BCD calendar and Binary modes - value: 2 - - name: BinBCD2 - description: Free running BCD calendar and Binary modes - value: 3 + - name: BCD + description: Free running BCD calendar mode (Binary mode disabled) + value: 0 + - name: Binary + description: Free running Binary mode (BCD mode disabled) + value: 1 + - name: BinBCD + description: Free running BCD calendar and Binary modes + value: 2 + - name: BinBCD2 + description: Free running BCD calendar and Binary modes + value: 3 enum/CALP: bit_size: 1 variants: - - name: NoChange - description: No RTCCLK pulses are added - value: 0 - - name: IncreaseFreq - description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - value: 1 + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 enum/CALRF: bit_size: 1 variants: - - name: Clear - description: Clear interrupt flag by writing 1 - value: 1 + - name: Clear + description: Clear interrupt flag by writing 1 + value: 1 enum/CALW16: bit_size: 1 variants: - - name: SixteenSeconds - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" - value: 1 + - name: SixteenSeconds + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 enum/CALW8: bit_size: 1 variants: - - name: EightSeconds - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 + - name: EightSeconds + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 enum/COSEL: bit_size: 1 variants: - - name: CalFreq_512Hz - description: Calibration output is 512 Hz (with default prescaler setting) - value: 0 - - name: CalFreq_1Hz - description: Calibration output is 1 Hz (with default prescaler setting) - value: 1 + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 enum/FMT: bit_size: 1 variants: - - name: TwentyFourHour - description: 24 hour/day format - value: 0 - - name: AmPm - description: AM/PM hour format - value: 1 + - name: TwentyFourHour + description: 24 hour/day format + value: 0 + - name: AmPm + description: AM/PM hour format + value: 1 enum/INIT: bit_size: 1 variants: - - name: FreeRunningMode - description: Free running mode - value: 0 - - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." - value: 1 + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 enum/ITSF: bit_size: 1 variants: - - name: TimestampEvent - description: This flag is set by hardware when a timestamp on the internal event occurs - value: 1 + - name: TimestampEvent + description: This flag is set by hardware when a timestamp on the internal event occurs + value: 1 enum/ITSMF: bit_size: 1 variants: - - name: TimestampEvent - description: This flag is set by hardware when a timestamp on the internal event occurs - value: 1 + - name: TimestampEvent + description: This flag is set by hardware when a timestamp on the internal event occurs + value: 1 enum/KEY: bit_size: 8 variants: - - name: Activate - description: Activate write protection (any value that is not the keys) - value: 0 - - name: Deactivate2 - description: Key 2 - value: 83 - - name: Deactivate1 - description: Key 1 - value: 202 + - name: Activate + description: Activate write protection (any value that is not the keys) + value: 0 + - name: Deactivate2 + description: Key 2 + value: 83 + - name: Deactivate1 + description: Key 1 + value: 202 enum/LPCAL: bit_size: 1 variants: - - name: RTCCLK - description: "Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required" - value: 0 - - name: CkApre - description: "Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode" - value: 1 + - name: RTCCLK + description: Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required + value: 0 + - name: CkApre + description: Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode + value: 1 enum/OSEL: bit_size: 2 variants: - - name: Disabled - description: Output disabled - value: 0 - - name: AlarmA - description: Alarm A output enabled - value: 1 - - name: AlarmB - description: Alarm B output enabled - value: 2 - - name: Wakeup - description: Wakeup output enabled - value: 3 + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 enum/POL: bit_size: 1 variants: - - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 0 - - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 1 + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 enum/RECALPF: bit_size: 1 variants: - - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" - value: 1 + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 enum/REFCKON: bit_size: 1 variants: - - name: Disabled - description: RTC_REFIN detection disabled - value: 0 - - name: Enabled - description: RTC_REFIN detection enabled - value: 1 + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 enum/SSRUF: bit_size: 1 variants: - - name: Underflow - description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 - value: 1 + - name: Underflow + description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 + value: 1 enum/SSRUMF: bit_size: 1 variants: - - name: Underflow - description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 - value: 1 + - name: Underflow + description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 + value: 1 enum/TAMPALRM_PU: bit_size: 1 variants: - - name: NoPullUp - description: No pull-up is applied on TAMPALRM output - value: 0 - - name: PullUp - description: A pull-up is applied on TAMPALRM output - value: 1 + - name: NoPullUp + description: No pull-up is applied on TAMPALRM output + value: 0 + - name: PullUp + description: A pull-up is applied on TAMPALRM output + value: 1 enum/TAMPALRM_TYPE: bit_size: 1 variants: - - name: PushPull - description: TAMPALRM is push-pull output - value: 0 - - name: OpenDrain - description: TAMPALRM is open-drain output - value: 1 + - name: PushPull + description: TAMPALRM is push-pull output + value: 0 + - name: OpenDrain + description: TAMPALRM is open-drain output + value: 1 enum/TSEDGE: bit_size: 1 variants: - - name: RisingEdge - description: RTC_TS input rising edge generates a time-stamp event - value: 0 - - name: FallingEdge - description: RTC_TS input falling edge generates a time-stamp event - value: 1 + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 enum/TSF: bit_size: 1 variants: - - name: TimestampEvent - description: This flag is set by hardware when a time-stamp event occurs - value: 1 + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 enum/TSMF: bit_size: 1 variants: - - name: TimestampEvent - description: This flag is set by hardware when a time-stamp event occurs - value: 1 + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 enum/TSOVF: bit_size: 1 variants: - - name: Overflow - description: This flag is set by hardware when a time-stamp event occurs while TSF is already set - value: 1 + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 enum/TSOVMF: bit_size: 1 variants: - - name: Overflow - description: This flag is set by hardware when a time-stamp event occurs while TSF is already set - value: 1 + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 enum/WUCKSEL: bit_size: 3 variants: - - name: Div16 - description: RTC/16 clock is selected - value: 0 - - name: Div8 - description: RTC/8 clock is selected - value: 1 - - name: Div4 - description: RTC/4 clock is selected - value: 2 - - name: Div2 - description: RTC/2 clock is selected - value: 3 - - name: ClockSpare - description: ck_spre (usually 1 Hz) clock is selected - value: 4 - - name: ClockSpareWithOffset - description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - value: 6 + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 enum/WUTF: bit_size: 1 variants: - - name: Zero - description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 - value: 1 + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 enum/WUTMF: bit_size: 1 variants: - - name: Zero - description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 - value: 1 + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 diff --git a/data/registers/sai_v1.yaml b/data/registers/sai_v1.yaml index 7e58c5e..b289a9f 100644 --- a/data/registers/sai_v1.yaml +++ b/data/registers/sai_v1.yaml @@ -1,587 +1,586 @@ ---- block/CH: - description: "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR" + description: Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR items: - - name: CR1 - description: Configuration register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Configuration register 2 - byte_offset: 4 - fieldset: CR2 - - name: FRCR - description: This register has no meaning in AC97 and SPDIF audio protocol - byte_offset: 8 - fieldset: FRCR - - name: SLOTR - description: This register has no meaning in AC97 and SPDIF audio protocol - byte_offset: 12 - fieldset: SLOTR - - name: IM - description: Interrupt mask register 2 - byte_offset: 16 - fieldset: IM - - name: SR - description: Status register - byte_offset: 20 - access: Read - fieldset: SR - - name: CLRFR - description: Clear flag register - byte_offset: 24 - access: Write - fieldset: CLRFR - - name: DR - description: Data register - byte_offset: 28 - fieldset: DR + - name: CR1 + description: Configuration register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Configuration register 2 + byte_offset: 4 + fieldset: CR2 + - name: FRCR + description: This register has no meaning in AC97 and SPDIF audio protocol + byte_offset: 8 + fieldset: FRCR + - name: SLOTR + description: This register has no meaning in AC97 and SPDIF audio protocol + byte_offset: 12 + fieldset: SLOTR + - name: IM + description: Interrupt mask register 2 + byte_offset: 16 + fieldset: IM + - name: SR + description: Status register + byte_offset: 20 + access: Read + fieldset: SR + - name: CLRFR + description: Clear flag register + byte_offset: 24 + access: Write + fieldset: CLRFR + - name: DR + description: Data register + byte_offset: 28 + fieldset: DR block/SAI: description: Serial audio interface items: - - name: CH - description: "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR" - array: - len: 2 - stride: 32 - byte_offset: 4 - block: CH + - name: CH + description: Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + array: + len: 2 + stride: 32 + byte_offset: 4 + block: CH fieldset/CLRFR: description: Clear flag register fields: - - name: COVRUDR - description: Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. - bit_offset: 0 - bit_size: 1 - - name: CMUTEDET - description: Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. - bit_offset: 1 - bit_size: 1 - - name: CWCKCFG - description: "Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0." - bit_offset: 2 - bit_size: 1 - - name: CCNRDY - description: Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. - bit_offset: 4 - bit_size: 1 - - name: CAFSDET - description: Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. - bit_offset: 5 - bit_size: 1 - - name: CLFSDET - description: Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. - bit_offset: 6 - bit_size: 1 + - name: COVRUDR + description: Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. + bit_offset: 0 + bit_size: 1 + - name: CMUTEDET + description: Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. + bit_offset: 1 + bit_size: 1 + - name: CWCKCFG + description: Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. + bit_offset: 2 + bit_size: 1 + - name: CCNRDY + description: Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. + bit_offset: 4 + bit_size: 1 + - name: CAFSDET + description: Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. + bit_offset: 5 + bit_size: 1 + - name: CLFSDET + description: Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. + bit_offset: 6 + bit_size: 1 fieldset/CR1: description: Configuration register 1 fields: - - name: MODE - description: SAIx audio block mode immediately - bit_offset: 0 - bit_size: 2 - enum: MODE - - name: PRTCFG - description: Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. - bit_offset: 2 - bit_size: 2 - enum: PRTCFG - - name: DS - description: "Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled." - bit_offset: 5 - bit_size: 3 - enum: DS - - name: LSBFIRST - description: Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. - bit_offset: 8 - bit_size: 1 - enum: LSBFIRST - - name: CKSTR - description: Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. - bit_offset: 9 - bit_size: 1 - enum: CKSTR - - name: SYNCEN - description: "Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled." - bit_offset: 10 - bit_size: 2 - enum: SYNCEN - - name: MONO - description: "Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details." - bit_offset: 12 - bit_size: 1 - enum: MONO - - name: OUTDRIV - description: "Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration." - bit_offset: 13 - bit_size: 1 - enum: OUTDRIV - - name: SAIEN - description: "Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit." - bit_offset: 16 - bit_size: 1 - - name: DMAEN - description: "DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode." - bit_offset: 17 - bit_size: 1 - - name: NODIV - description: No fixed divider between MCLK and FS - bit_offset: 19 - bit_size: 1 - enum: NODIV - - name: MCKDIV - description: "Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:" - bit_offset: 20 - bit_size: 4 + - name: MODE + description: SAIx audio block mode immediately + bit_offset: 0 + bit_size: 2 + enum: MODE + - name: PRTCFG + description: Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. + bit_offset: 2 + bit_size: 2 + enum: PRTCFG + - name: DS + description: Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. + bit_offset: 5 + bit_size: 3 + enum: DS + - name: LSBFIRST + description: Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. + bit_offset: 8 + bit_size: 1 + enum: LSBFIRST + - name: CKSTR + description: Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. + bit_offset: 9 + bit_size: 1 + enum: CKSTR + - name: SYNCEN + description: 'Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled.' + bit_offset: 10 + bit_size: 2 + enum: SYNCEN + - name: MONO + description: 'Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details.' + bit_offset: 12 + bit_size: 1 + enum: MONO + - name: OUTDRIV + description: 'Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration.' + bit_offset: 13 + bit_size: 1 + enum: OUTDRIV + - name: SAIEN + description: 'Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit.' + bit_offset: 16 + bit_size: 1 + - name: DMAEN + description: 'DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode.' + bit_offset: 17 + bit_size: 1 + - name: NODIV + description: No fixed divider between MCLK and FS + bit_offset: 19 + bit_size: 1 + enum: NODIV + - name: MCKDIV + description: 'Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:' + bit_offset: 20 + bit_size: 4 fieldset/CR2: description: Configuration register 2 fields: - - name: FTH - description: FIFO threshold. This bit is set and cleared by software. - bit_offset: 0 - bit_size: 3 - enum: FTH - - name: FFLUSH - description: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. - bit_offset: 3 - bit_size: 1 - enum: FFLUSH - - name: TRIS - description: "Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details." - bit_offset: 4 - bit_size: 1 - - name: MUTE - description: "Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks." - bit_offset: 5 - bit_size: 1 - - name: MUTEVAL - description: "Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks." - bit_offset: 6 - bit_size: 1 - enum: MUTEVAL - - name: MUTECNT - description: "Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details." - bit_offset: 7 - bit_size: 6 - - name: CPL - description: "Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm." - bit_offset: 13 - bit_size: 1 - enum: CPL - - name: COMP - description: "Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected." - bit_offset: 14 - bit_size: 2 - enum: COMP + - name: FTH + description: FIFO threshold. This bit is set and cleared by software. + bit_offset: 0 + bit_size: 3 + enum: FTH + - name: FFLUSH + description: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. + bit_offset: 3 + bit_size: 1 + enum: FFLUSH + - name: TRIS + description: 'Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details.' + bit_offset: 4 + bit_size: 1 + - name: MUTE + description: 'Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.' + bit_offset: 5 + bit_size: 1 + - name: MUTEVAL + description: 'Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.' + bit_offset: 6 + bit_size: 1 + enum: MUTEVAL + - name: MUTECNT + description: 'Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details.' + bit_offset: 7 + bit_size: 6 + - name: CPL + description: 'Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm.' + bit_offset: 13 + bit_size: 1 + enum: CPL + - name: COMP + description: 'Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected.' + bit_offset: 14 + bit_size: 2 + enum: COMP fieldset/DR: description: Data register fields: - - name: DATA - description: Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. - bit_offset: 0 - bit_size: 32 + - name: DATA + description: Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. + bit_offset: 0 + bit_size: 32 fieldset/FRCR: description: This register has no meaning in AC97 and SPDIF audio protocol fields: - - name: FRL - description: "Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration." - bit_offset: 0 - bit_size: 8 - - name: FSALL - description: "Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled." - bit_offset: 8 - bit_size: 7 - - name: FSDEF - description: "Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled." - bit_offset: 16 - bit_size: 1 - - name: FSPOL - description: Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - bit_offset: 17 - bit_size: 1 - enum: FSPOL - - name: FSOFF - description: Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - bit_offset: 18 - bit_size: 1 - enum: FSOFF + - name: FRL + description: 'Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration.' + bit_offset: 0 + bit_size: 8 + - name: FSALL + description: Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. + bit_offset: 8 + bit_size: 7 + - name: FSDEF + description: 'Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled.' + bit_offset: 16 + bit_size: 1 + - name: FSPOL + description: Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + bit_offset: 17 + bit_size: 1 + enum: FSPOL + - name: FSOFF + description: Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + bit_offset: 18 + bit_size: 1 + enum: FSOFF fieldset/IM: description: Interrupt mask register 2 fields: - - name: OVRUDRIE - description: "Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set." - bit_offset: 0 - bit_size: 1 - - name: MUTEDETIE - description: "Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode." - bit_offset: 1 - bit_size: 1 - - name: WCKCFGIE - description: "Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes." - bit_offset: 2 - bit_size: 1 - - name: FREQIE - description: "FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode," - bit_offset: 3 - bit_size: 1 - - name: CNRDYIE - description: "Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver." - bit_offset: 4 - bit_size: 1 - - name: AFSDETIE - description: "Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master." - bit_offset: 5 - bit_size: 1 - - name: LFSDETIE - description: "Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master." - bit_offset: 6 - bit_size: 1 + - name: OVRUDRIE + description: Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. + bit_offset: 0 + bit_size: 1 + - name: MUTEDETIE + description: Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. + bit_offset: 1 + bit_size: 1 + - name: WCKCFGIE + description: 'Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes.' + bit_offset: 2 + bit_size: 1 + - name: FREQIE + description: FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, + bit_offset: 3 + bit_size: 1 + - name: CNRDYIE + description: Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. + bit_offset: 4 + bit_size: 1 + - name: AFSDETIE + description: Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + bit_offset: 5 + bit_size: 1 + - name: LFSDETIE + description: Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + bit_offset: 6 + bit_size: 1 fieldset/SLOTR: description: This register has no meaning in AC97 and SPDIF audio protocol fields: - - name: FBOFF - description: "First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode." - bit_offset: 0 - bit_size: 5 - - name: SLOTSZ - description: "Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode." - bit_offset: 6 - bit_size: 2 - enum: SLOTSZ - - name: NBSLOT - description: Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - bit_offset: 8 - bit_size: 4 - - name: SLOTEN - description: Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - bit_offset: 16 - bit_size: 16 - enum: SLOTEN + - name: FBOFF + description: First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + bit_offset: 0 + bit_size: 5 + - name: SLOTSZ + description: 'Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode.' + bit_offset: 6 + bit_size: 2 + enum: SLOTSZ + - name: NBSLOT + description: Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + bit_offset: 8 + bit_size: 4 + - name: SLOTEN + description: Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + bit_offset: 16 + bit_size: 16 + enum: SLOTEN fieldset/SR: description: Status register fields: - - name: OVRUDR - description: "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register." - bit_offset: 0 - bit_size: 1 - enum: OVRUDR - - name: MUTEDET - description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. - bit_offset: 1 - bit_size: 1 - enum: MUTEDET - - name: WCKCFG - description: "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register." - bit_offset: 2 - bit_size: 1 - enum: WCKCFG - - name: FREQ - description: "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register." - bit_offset: 3 - bit_size: 1 - enum: FREQ - - name: CNRDY - description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. - bit_offset: 4 - bit_size: 1 - enum: CNRDY - - name: AFSDET - description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. - bit_offset: 5 - bit_size: 1 - enum: AFSDET - - name: LFSDET - description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register - bit_offset: 6 - bit_size: 1 - enum: LFSDET - - name: FLVL - description: "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:" - bit_offset: 16 - bit_size: 3 - enum: FLVL + - name: OVRUDR + description: Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. + bit_offset: 0 + bit_size: 1 + enum: OVRUDR + - name: MUTEDET + description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. + bit_offset: 1 + bit_size: 1 + enum: MUTEDET + - name: WCKCFG + description: Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. + bit_offset: 2 + bit_size: 1 + enum: WCKCFG + - name: FREQ + description: 'FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register.' + bit_offset: 3 + bit_size: 1 + enum: FREQ + - name: CNRDY + description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. + bit_offset: 4 + bit_size: 1 + enum: CNRDY + - name: AFSDET + description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. + bit_offset: 5 + bit_size: 1 + enum: AFSDET + - name: LFSDET + description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register + bit_offset: 6 + bit_size: 1 + enum: LFSDET + - name: FLVL + description: 'FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:' + bit_offset: 16 + bit_size: 3 + enum: FLVL enum/AFSDET: bit_size: 1 variants: - - name: NoError - description: No error - value: 0 - - name: EarlySync - description: Frame synchronization signal is detected earlier than expected - value: 1 + - name: NoError + description: No error + value: 0 + - name: EarlySync + description: Frame synchronization signal is detected earlier than expected + value: 1 enum/CKSTR: bit_size: 1 variants: - - name: FallingEdge - description: Data strobing edge is falling edge of SCK - value: 0 - - name: RisingEdge - description: Data strobing edge is rising edge of SCK - value: 1 + - name: FallingEdge + description: Data strobing edge is falling edge of SCK + value: 0 + - name: RisingEdge + description: Data strobing edge is rising edge of SCK + value: 1 enum/CNRDY: bit_size: 1 variants: - - name: Ready - description: External AC’97 Codec is ready - value: 0 - - name: NotReady - description: External AC’97 Codec is not ready - value: 1 + - name: Ready + description: External AC’97 Codec is ready + value: 0 + - name: NotReady + description: External AC’97 Codec is not ready + value: 1 enum/COMP: bit_size: 2 variants: - - name: NoCompanding - description: No companding algorithm - value: 0 - - name: MuLaw - description: μ-Law algorithm - value: 2 - - name: ALaw - description: A-Law algorithm - value: 3 + - name: NoCompanding + description: No companding algorithm + value: 0 + - name: MuLaw + description: μ-Law algorithm + value: 2 + - name: ALaw + description: A-Law algorithm + value: 3 enum/CPL: bit_size: 1 variants: - - name: OnesComplement - description: 1’s complement representation - value: 0 - - name: TwosComplement - description: 2’s complement representation - value: 1 + - name: OnesComplement + description: 1’s complement representation + value: 0 + - name: TwosComplement + description: 2’s complement representation + value: 1 enum/DS: bit_size: 3 variants: - - name: Bit8 - description: 8 bits - value: 2 - - name: Bit10 - description: 10 bits - value: 3 - - name: Bit16 - description: 16 bits - value: 4 - - name: Bit20 - description: 20 bits - value: 5 - - name: Bit24 - description: 24 bits - value: 6 - - name: Bit32 - description: 32 bits - value: 7 + - name: Bit8 + description: 8 bits + value: 2 + - name: Bit10 + description: 10 bits + value: 3 + - name: Bit16 + description: 16 bits + value: 4 + - name: Bit20 + description: 20 bits + value: 5 + - name: Bit24 + description: 24 bits + value: 6 + - name: Bit32 + description: 32 bits + value: 7 enum/FFLUSH: bit_size: 1 variants: - - name: NoFlush - description: No FIFO flush - value: 0 - - name: Flush - description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared - value: 1 + - name: NoFlush + description: No FIFO flush + value: 0 + - name: Flush + description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared + value: 1 enum/FLVL: bit_size: 3 variants: - - name: Empty - description: FIFO empty - value: 0 - - name: Quarter1 - description: FIFO <= 1⁄4 but not empty - value: 1 - - name: Quarter2 - description: 1⁄4 < FIFO <= 1⁄2 - value: 2 - - name: Quarter3 - description: 1⁄2 < FIFO <= 3⁄4 - value: 3 - - name: Quarter4 - description: 3⁄4 < FIFO but not full - value: 4 - - name: Full - description: FIFO full - value: 5 + - name: Empty + description: FIFO empty + value: 0 + - name: Quarter1 + description: FIFO <= 1⁄4 but not empty + value: 1 + - name: Quarter2 + description: 1⁄4 < FIFO <= 1⁄2 + value: 2 + - name: Quarter3 + description: 1⁄2 < FIFO <= 3⁄4 + value: 3 + - name: Quarter4 + description: 3⁄4 < FIFO but not full + value: 4 + - name: Full + description: FIFO full + value: 5 enum/FREQ: bit_size: 1 variants: - - name: NoRequest - description: No FIFO request - value: 0 - - name: Request - description: FIFO request to read or to write the SAI_xDR - value: 1 + - name: NoRequest + description: No FIFO request + value: 0 + - name: Request + description: FIFO request to read or to write the SAI_xDR + value: 1 enum/FSOFF: bit_size: 1 variants: - - name: OnFirst - description: FS is asserted on the first bit of the slot 0 - value: 0 - - name: BeforeFirst - description: FS is asserted one bit before the first bit of the slot 0 - value: 1 + - name: OnFirst + description: FS is asserted on the first bit of the slot 0 + value: 0 + - name: BeforeFirst + description: FS is asserted one bit before the first bit of the slot 0 + value: 1 enum/FSPOL: bit_size: 1 variants: - - name: FallingEdge - description: FS is active low (falling edge) - value: 0 - - name: RisingEdge - description: FS is active high (rising edge) - value: 1 + - name: FallingEdge + description: FS is active low (falling edge) + value: 0 + - name: RisingEdge + description: FS is active high (rising edge) + value: 1 enum/FTH: bit_size: 3 variants: - - name: Empty - description: FIFO empty - value: 0 - - name: Quarter1 - description: 1⁄4 FIFO - value: 1 - - name: Quarter2 - description: 1⁄2 FIFO - value: 2 - - name: Quarter3 - description: 3⁄4 FIFO - value: 3 - - name: Full - description: FIFO full - value: 4 + - name: Empty + description: FIFO empty + value: 0 + - name: Quarter1 + description: 1⁄4 FIFO + value: 1 + - name: Quarter2 + description: 1⁄2 FIFO + value: 2 + - name: Quarter3 + description: 3⁄4 FIFO + value: 3 + - name: Full + description: FIFO full + value: 4 enum/LFSDET: bit_size: 1 variants: - - name: NoError - description: No error - value: 0 - - name: NoSync - description: Frame synchronization signal is not present at the right time - value: 1 + - name: NoError + description: No error + value: 0 + - name: NoSync + description: Frame synchronization signal is not present at the right time + value: 1 enum/LSBFIRST: bit_size: 1 variants: - - name: MsbFirst - description: Data are transferred with MSB first - value: 0 - - name: LsbFirst - description: Data are transferred with LSB first - value: 1 + - name: MsbFirst + description: Data are transferred with MSB first + value: 0 + - name: LsbFirst + description: Data are transferred with LSB first + value: 1 enum/MODE: bit_size: 2 variants: - - name: MasterTx - description: Master transmitter - value: 0 - - name: MasterRx - description: Master receiver - value: 1 - - name: SlaveTx - description: Slave transmitter - value: 2 - - name: SlaveRx - description: Slave receiver - value: 3 + - name: MasterTx + description: Master transmitter + value: 0 + - name: MasterRx + description: Master receiver + value: 1 + - name: SlaveTx + description: Slave transmitter + value: 2 + - name: SlaveRx + description: Slave receiver + value: 3 enum/MONO: bit_size: 1 variants: - - name: Stereo - description: Stereo mode - value: 0 - - name: Mono - description: Mono mode - value: 1 + - name: Stereo + description: Stereo mode + value: 0 + - name: Mono + description: Mono mode + value: 1 enum/MUTEDET: bit_size: 1 variants: - - name: NoMute - description: No MUTE detection on the SD input line - value: 0 - - name: Mute - description: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame - value: 1 + - name: NoMute + description: No MUTE detection on the SD input line + value: 0 + - name: Mute + description: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame + value: 1 enum/MUTEVAL: bit_size: 1 variants: - - name: SendZero - description: Bit value 0 is sent during the mute mode - value: 0 - - name: SendLast - description: Last values are sent during the mute mode - value: 1 + - name: SendZero + description: Bit value 0 is sent during the mute mode + value: 0 + - name: SendLast + description: Last values are sent during the mute mode + value: 1 enum/NODIV: bit_size: 1 variants: - - name: MasterClock - description: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value - value: 0 - - name: NoDiv - description: "MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL." - value: 1 + - name: MasterClock + description: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value + value: 0 + - name: NoDiv + description: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. + value: 1 enum/OUTDRIV: bit_size: 1 variants: - - name: OnStart - description: Audio block output driven when SAIEN is set - value: 0 - - name: Immediately - description: Audio block output driven immediately after the setting of this bit - value: 1 + - name: OnStart + description: Audio block output driven when SAIEN is set + value: 0 + - name: Immediately + description: Audio block output driven immediately after the setting of this bit + value: 1 enum/OVRUDR: bit_size: 1 variants: - - name: NoError - description: No overrun/underrun error - value: 0 - - name: Overrun - description: Overrun/underrun error detection - value: 1 + - name: NoError + description: No overrun/underrun error + value: 0 + - name: Overrun + description: Overrun/underrun error detection + value: 1 enum/PRTCFG: bit_size: 2 variants: - - name: Free - description: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol - value: 0 - - name: Spdif - description: SPDIF protocol - value: 1 - - name: Ac97 - description: AC’97 protocol - value: 2 + - name: Free + description: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol + value: 0 + - name: Spdif + description: SPDIF protocol + value: 1 + - name: Ac97 + description: AC’97 protocol + value: 2 enum/SLOTEN: bit_size: 16 variants: - - name: Inactive - description: Inactive slot - value: 0 - - name: Active - description: Active slot - value: 1 + - name: Inactive + description: Inactive slot + value: 0 + - name: Active + description: Active slot + value: 1 enum/SLOTSZ: bit_size: 2 variants: - - name: DataSize - description: "The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)" - value: 0 - - name: Bit16 - description: 16-bit - value: 1 - - name: Bit32 - description: 32-bit - value: 2 + - name: DataSize + description: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) + value: 0 + - name: Bit16 + description: 16-bit + value: 1 + - name: Bit32 + description: 32-bit + value: 2 enum/SYNCEN: bit_size: 2 variants: - - name: Asynchronous - description: audio sub-block in asynchronous mode - value: 0 - - name: Internal - description: "audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode" - value: 1 - - name: External - description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode - value: 2 + - name: Asynchronous + description: audio sub-block in asynchronous mode + value: 0 + - name: Internal + description: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode + value: 1 + - name: External + description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode + value: 2 enum/WCKCFG: bit_size: 1 variants: - - name: Correct - description: Clock configuration is correct - value: 0 - - name: Wrong - description: Clock configuration does not respect the rule concerning the frame length specification - value: 1 + - name: Correct + description: Clock configuration is correct + value: 0 + - name: Wrong + description: Clock configuration does not respect the rule concerning the frame length specification + value: 1 diff --git a/data/registers/sai_v2.yaml b/data/registers/sai_v2.yaml index f16c640..c78633e 100644 --- a/data/registers/sai_v2.yaml +++ b/data/registers/sai_v2.yaml @@ -1,602 +1,601 @@ ---- block/CH: - description: "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR" + description: Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR items: - - name: CR1 - description: Configuration register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Configuration register 2 - byte_offset: 4 - fieldset: CR2 - - name: FRCR - description: This register has no meaning in AC97 and SPDIF audio protocol - byte_offset: 8 - fieldset: FRCR - - name: SLOTR - description: This register has no meaning in AC97 and SPDIF audio protocol - byte_offset: 12 - fieldset: SLOTR - - name: IM - description: Interrupt mask register 2 - byte_offset: 16 - fieldset: IM - - name: SR - description: Status register - byte_offset: 20 - access: Read - fieldset: SR - - name: CLRFR - description: Clear flag register - byte_offset: 24 - access: Write - fieldset: CLRFR - - name: DR - description: Data register - byte_offset: 28 - fieldset: DR + - name: CR1 + description: Configuration register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Configuration register 2 + byte_offset: 4 + fieldset: CR2 + - name: FRCR + description: This register has no meaning in AC97 and SPDIF audio protocol + byte_offset: 8 + fieldset: FRCR + - name: SLOTR + description: This register has no meaning in AC97 and SPDIF audio protocol + byte_offset: 12 + fieldset: SLOTR + - name: IM + description: Interrupt mask register 2 + byte_offset: 16 + fieldset: IM + - name: SR + description: Status register + byte_offset: 20 + access: Read + fieldset: SR + - name: CLRFR + description: Clear flag register + byte_offset: 24 + access: Write + fieldset: CLRFR + - name: DR + description: Data register + byte_offset: 28 + fieldset: DR block/SAI: description: Serial audio interface items: - - name: GCR - description: Global configuration register - byte_offset: 0 - fieldset: GCR - - name: CH - description: "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR" - array: - len: 2 - stride: 32 - byte_offset: 4 - block: CH + - name: GCR + description: Global configuration register + byte_offset: 0 + fieldset: GCR + - name: CH + description: Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + array: + len: 2 + stride: 32 + byte_offset: 4 + block: CH fieldset/CLRFR: description: Clear flag register fields: - - name: COVRUDR - description: Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. - bit_offset: 0 - bit_size: 1 - - name: CMUTEDET - description: Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. - bit_offset: 1 - bit_size: 1 - - name: CWCKCFG - description: "Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0." - bit_offset: 2 - bit_size: 1 - - name: CCNRDY - description: Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. - bit_offset: 4 - bit_size: 1 - - name: CAFSDET - description: Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. - bit_offset: 5 - bit_size: 1 - - name: CLFSDET - description: Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. - bit_offset: 6 - bit_size: 1 + - name: COVRUDR + description: Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. + bit_offset: 0 + bit_size: 1 + - name: CMUTEDET + description: Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. + bit_offset: 1 + bit_size: 1 + - name: CWCKCFG + description: Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. + bit_offset: 2 + bit_size: 1 + - name: CCNRDY + description: Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. + bit_offset: 4 + bit_size: 1 + - name: CAFSDET + description: Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. + bit_offset: 5 + bit_size: 1 + - name: CLFSDET + description: Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. + bit_offset: 6 + bit_size: 1 fieldset/CR1: description: Configuration register 1 fields: - - name: MODE - description: SAIx audio block mode immediately - bit_offset: 0 - bit_size: 2 - enum: MODE - - name: PRTCFG - description: Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. - bit_offset: 2 - bit_size: 2 - enum: PRTCFG - - name: DS - description: "Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled." - bit_offset: 5 - bit_size: 3 - enum: DS - - name: LSBFIRST - description: Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. - bit_offset: 8 - bit_size: 1 - enum: LSBFIRST - - name: CKSTR - description: Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. - bit_offset: 9 - bit_size: 1 - enum: CKSTR - - name: SYNCEN - description: "Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled." - bit_offset: 10 - bit_size: 2 - enum: SYNCEN - - name: MONO - description: "Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details." - bit_offset: 12 - bit_size: 1 - enum: MONO - - name: OUTDRIV - description: "Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration." - bit_offset: 13 - bit_size: 1 - enum: OUTDRIV - - name: SAIEN - description: "Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit." - bit_offset: 16 - bit_size: 1 - - name: DMAEN - description: "DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode." - bit_offset: 17 - bit_size: 1 - - name: NODIV - description: No fixed divider between MCLK and FS - bit_offset: 19 - bit_size: 1 - enum: NODIV - - name: MCKDIV - description: "Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:" - bit_offset: 20 - bit_size: 4 + - name: MODE + description: SAIx audio block mode immediately + bit_offset: 0 + bit_size: 2 + enum: MODE + - name: PRTCFG + description: Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. + bit_offset: 2 + bit_size: 2 + enum: PRTCFG + - name: DS + description: Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. + bit_offset: 5 + bit_size: 3 + enum: DS + - name: LSBFIRST + description: Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. + bit_offset: 8 + bit_size: 1 + enum: LSBFIRST + - name: CKSTR + description: Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. + bit_offset: 9 + bit_size: 1 + enum: CKSTR + - name: SYNCEN + description: 'Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled.' + bit_offset: 10 + bit_size: 2 + enum: SYNCEN + - name: MONO + description: 'Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details.' + bit_offset: 12 + bit_size: 1 + enum: MONO + - name: OUTDRIV + description: 'Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration.' + bit_offset: 13 + bit_size: 1 + enum: OUTDRIV + - name: SAIEN + description: 'Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit.' + bit_offset: 16 + bit_size: 1 + - name: DMAEN + description: 'DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode.' + bit_offset: 17 + bit_size: 1 + - name: NODIV + description: No fixed divider between MCLK and FS + bit_offset: 19 + bit_size: 1 + enum: NODIV + - name: MCKDIV + description: 'Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:' + bit_offset: 20 + bit_size: 4 fieldset/CR2: description: Configuration register 2 fields: - - name: FTH - description: FIFO threshold. This bit is set and cleared by software. - bit_offset: 0 - bit_size: 3 - enum: FTH - - name: FFLUSH - description: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. - bit_offset: 3 - bit_size: 1 - enum: FFLUSH - - name: TRIS - description: "Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details." - bit_offset: 4 - bit_size: 1 - - name: MUTE - description: "Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks." - bit_offset: 5 - bit_size: 1 - - name: MUTEVAL - description: "Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks." - bit_offset: 6 - bit_size: 1 - enum: MUTEVAL - - name: MUTECNT - description: "Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details." - bit_offset: 7 - bit_size: 6 - - name: CPL - description: "Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm." - bit_offset: 13 - bit_size: 1 - enum: CPL - - name: COMP - description: "Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected." - bit_offset: 14 - bit_size: 2 - enum: COMP + - name: FTH + description: FIFO threshold. This bit is set and cleared by software. + bit_offset: 0 + bit_size: 3 + enum: FTH + - name: FFLUSH + description: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. + bit_offset: 3 + bit_size: 1 + enum: FFLUSH + - name: TRIS + description: 'Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details.' + bit_offset: 4 + bit_size: 1 + - name: MUTE + description: 'Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.' + bit_offset: 5 + bit_size: 1 + - name: MUTEVAL + description: 'Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.' + bit_offset: 6 + bit_size: 1 + enum: MUTEVAL + - name: MUTECNT + description: 'Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details.' + bit_offset: 7 + bit_size: 6 + - name: CPL + description: 'Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm.' + bit_offset: 13 + bit_size: 1 + enum: CPL + - name: COMP + description: 'Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected.' + bit_offset: 14 + bit_size: 2 + enum: COMP fieldset/DR: description: Data register fields: - - name: DATA - description: Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. - bit_offset: 0 - bit_size: 32 + - name: DATA + description: Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. + bit_offset: 0 + bit_size: 32 fieldset/FRCR: description: This register has no meaning in AC97 and SPDIF audio protocol fields: - - name: FRL - description: "Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration." - bit_offset: 0 - bit_size: 8 - - name: FSALL - description: "Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled." - bit_offset: 8 - bit_size: 7 - - name: FSDEF - description: "Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled." - bit_offset: 16 - bit_size: 1 - - name: FSPOL - description: Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - bit_offset: 17 - bit_size: 1 - enum: FSPOL - - name: FSOFF - description: Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - bit_offset: 18 - bit_size: 1 - enum: FSOFF + - name: FRL + description: 'Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration.' + bit_offset: 0 + bit_size: 8 + - name: FSALL + description: Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. + bit_offset: 8 + bit_size: 7 + - name: FSDEF + description: 'Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled.' + bit_offset: 16 + bit_size: 1 + - name: FSPOL + description: Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + bit_offset: 17 + bit_size: 1 + enum: FSPOL + - name: FSOFF + description: Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + bit_offset: 18 + bit_size: 1 + enum: FSOFF fieldset/GCR: description: Global configuration register fields: - - name: SYNCIN - description: Synchronization inputs - bit_offset: 0 - bit_size: 2 - - name: SYNCOUT - description: Synchronization outputs These bits are set and cleared by software. - bit_offset: 4 - bit_size: 2 + - name: SYNCIN + description: Synchronization inputs + bit_offset: 0 + bit_size: 2 + - name: SYNCOUT + description: Synchronization outputs These bits are set and cleared by software. + bit_offset: 4 + bit_size: 2 fieldset/IM: description: Interrupt mask register 2 fields: - - name: OVRUDRIE - description: "Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set." - bit_offset: 0 - bit_size: 1 - - name: MUTEDETIE - description: "Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode." - bit_offset: 1 - bit_size: 1 - - name: WCKCFGIE - description: "Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes." - bit_offset: 2 - bit_size: 1 - - name: FREQIE - description: "FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode," - bit_offset: 3 - bit_size: 1 - - name: CNRDYIE - description: "Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver." - bit_offset: 4 - bit_size: 1 - - name: AFSDETIE - description: "Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master." - bit_offset: 5 - bit_size: 1 - - name: LFSDETIE - description: "Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master." - bit_offset: 6 - bit_size: 1 + - name: OVRUDRIE + description: Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. + bit_offset: 0 + bit_size: 1 + - name: MUTEDETIE + description: Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. + bit_offset: 1 + bit_size: 1 + - name: WCKCFGIE + description: 'Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes.' + bit_offset: 2 + bit_size: 1 + - name: FREQIE + description: FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, + bit_offset: 3 + bit_size: 1 + - name: CNRDYIE + description: Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. + bit_offset: 4 + bit_size: 1 + - name: AFSDETIE + description: Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + bit_offset: 5 + bit_size: 1 + - name: LFSDETIE + description: Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + bit_offset: 6 + bit_size: 1 fieldset/SLOTR: description: This register has no meaning in AC97 and SPDIF audio protocol fields: - - name: FBOFF - description: "First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode." - bit_offset: 0 - bit_size: 5 - - name: SLOTSZ - description: "Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode." - bit_offset: 6 - bit_size: 2 - enum: SLOTSZ - - name: NBSLOT - description: Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - bit_offset: 8 - bit_size: 4 - - name: SLOTEN - description: Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - bit_offset: 16 - bit_size: 16 - enum: SLOTEN + - name: FBOFF + description: First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + bit_offset: 0 + bit_size: 5 + - name: SLOTSZ + description: 'Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode.' + bit_offset: 6 + bit_size: 2 + enum: SLOTSZ + - name: NBSLOT + description: Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + bit_offset: 8 + bit_size: 4 + - name: SLOTEN + description: Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + bit_offset: 16 + bit_size: 16 + enum: SLOTEN fieldset/SR: description: Status register fields: - - name: OVRUDR - description: "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register." - bit_offset: 0 - bit_size: 1 - enum: OVRUDR - - name: MUTEDET - description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. - bit_offset: 1 - bit_size: 1 - enum: MUTEDET - - name: WCKCFG - description: "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register." - bit_offset: 2 - bit_size: 1 - enum: WCKCFG - - name: FREQ - description: "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register." - bit_offset: 3 - bit_size: 1 - enum: FREQ - - name: CNRDY - description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. - bit_offset: 4 - bit_size: 1 - enum: CNRDY - - name: AFSDET - description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. - bit_offset: 5 - bit_size: 1 - enum: AFSDET - - name: LFSDET - description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register - bit_offset: 6 - bit_size: 1 - enum: LFSDET - - name: FLVL - description: "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:" - bit_offset: 16 - bit_size: 3 - enum: FLVL + - name: OVRUDR + description: Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. + bit_offset: 0 + bit_size: 1 + enum: OVRUDR + - name: MUTEDET + description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. + bit_offset: 1 + bit_size: 1 + enum: MUTEDET + - name: WCKCFG + description: Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. + bit_offset: 2 + bit_size: 1 + enum: WCKCFG + - name: FREQ + description: 'FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register.' + bit_offset: 3 + bit_size: 1 + enum: FREQ + - name: CNRDY + description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. + bit_offset: 4 + bit_size: 1 + enum: CNRDY + - name: AFSDET + description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. + bit_offset: 5 + bit_size: 1 + enum: AFSDET + - name: LFSDET + description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register + bit_offset: 6 + bit_size: 1 + enum: LFSDET + - name: FLVL + description: 'FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:' + bit_offset: 16 + bit_size: 3 + enum: FLVL enum/AFSDET: bit_size: 1 variants: - - name: NoError - description: No error - value: 0 - - name: EarlySync - description: Frame synchronization signal is detected earlier than expected - value: 1 + - name: NoError + description: No error + value: 0 + - name: EarlySync + description: Frame synchronization signal is detected earlier than expected + value: 1 enum/CKSTR: bit_size: 1 variants: - - name: FallingEdge - description: Data strobing edge is falling edge of SCK - value: 0 - - name: RisingEdge - description: Data strobing edge is rising edge of SCK - value: 1 + - name: FallingEdge + description: Data strobing edge is falling edge of SCK + value: 0 + - name: RisingEdge + description: Data strobing edge is rising edge of SCK + value: 1 enum/CNRDY: bit_size: 1 variants: - - name: Ready - description: External AC’97 Codec is ready - value: 0 - - name: NotReady - description: External AC’97 Codec is not ready - value: 1 + - name: Ready + description: External AC’97 Codec is ready + value: 0 + - name: NotReady + description: External AC’97 Codec is not ready + value: 1 enum/COMP: bit_size: 2 variants: - - name: NoCompanding - description: No companding algorithm - value: 0 - - name: MuLaw - description: μ-Law algorithm - value: 2 - - name: ALaw - description: A-Law algorithm - value: 3 + - name: NoCompanding + description: No companding algorithm + value: 0 + - name: MuLaw + description: μ-Law algorithm + value: 2 + - name: ALaw + description: A-Law algorithm + value: 3 enum/CPL: bit_size: 1 variants: - - name: OnesComplement - description: 1’s complement representation - value: 0 - - name: TwosComplement - description: 2’s complement representation - value: 1 + - name: OnesComplement + description: 1’s complement representation + value: 0 + - name: TwosComplement + description: 2’s complement representation + value: 1 enum/DS: bit_size: 3 variants: - - name: Bit8 - description: 8 bits - value: 2 - - name: Bit10 - description: 10 bits - value: 3 - - name: Bit16 - description: 16 bits - value: 4 - - name: Bit20 - description: 20 bits - value: 5 - - name: Bit24 - description: 24 bits - value: 6 - - name: Bit32 - description: 32 bits - value: 7 + - name: Bit8 + description: 8 bits + value: 2 + - name: Bit10 + description: 10 bits + value: 3 + - name: Bit16 + description: 16 bits + value: 4 + - name: Bit20 + description: 20 bits + value: 5 + - name: Bit24 + description: 24 bits + value: 6 + - name: Bit32 + description: 32 bits + value: 7 enum/FFLUSH: bit_size: 1 variants: - - name: NoFlush - description: No FIFO flush - value: 0 - - name: Flush - description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared - value: 1 + - name: NoFlush + description: No FIFO flush + value: 0 + - name: Flush + description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared + value: 1 enum/FLVL: bit_size: 3 variants: - - name: Empty - description: FIFO empty - value: 0 - - name: Quarter1 - description: FIFO <= 1⁄4 but not empty - value: 1 - - name: Quarter2 - description: 1⁄4 < FIFO <= 1⁄2 - value: 2 - - name: Quarter3 - description: 1⁄2 < FIFO <= 3⁄4 - value: 3 - - name: Quarter4 - description: 3⁄4 < FIFO but not full - value: 4 - - name: Full - description: FIFO full - value: 5 + - name: Empty + description: FIFO empty + value: 0 + - name: Quarter1 + description: FIFO <= 1⁄4 but not empty + value: 1 + - name: Quarter2 + description: 1⁄4 < FIFO <= 1⁄2 + value: 2 + - name: Quarter3 + description: 1⁄2 < FIFO <= 3⁄4 + value: 3 + - name: Quarter4 + description: 3⁄4 < FIFO but not full + value: 4 + - name: Full + description: FIFO full + value: 5 enum/FREQ: bit_size: 1 variants: - - name: NoRequest - description: No FIFO request - value: 0 - - name: Request - description: FIFO request to read or to write the SAI_xDR - value: 1 + - name: NoRequest + description: No FIFO request + value: 0 + - name: Request + description: FIFO request to read or to write the SAI_xDR + value: 1 enum/FSOFF: bit_size: 1 variants: - - name: OnFirst - description: FS is asserted on the first bit of the slot 0 - value: 0 - - name: BeforeFirst - description: FS is asserted one bit before the first bit of the slot 0 - value: 1 + - name: OnFirst + description: FS is asserted on the first bit of the slot 0 + value: 0 + - name: BeforeFirst + description: FS is asserted one bit before the first bit of the slot 0 + value: 1 enum/FSPOL: bit_size: 1 variants: - - name: FallingEdge - description: FS is active low (falling edge) - value: 0 - - name: RisingEdge - description: FS is active high (rising edge) - value: 1 + - name: FallingEdge + description: FS is active low (falling edge) + value: 0 + - name: RisingEdge + description: FS is active high (rising edge) + value: 1 enum/FTH: bit_size: 3 variants: - - name: Empty - description: FIFO empty - value: 0 - - name: Quarter1 - description: 1⁄4 FIFO - value: 1 - - name: Quarter2 - description: 1⁄2 FIFO - value: 2 - - name: Quarter3 - description: 3⁄4 FIFO - value: 3 - - name: Full - description: FIFO full - value: 4 + - name: Empty + description: FIFO empty + value: 0 + - name: Quarter1 + description: 1⁄4 FIFO + value: 1 + - name: Quarter2 + description: 1⁄2 FIFO + value: 2 + - name: Quarter3 + description: 3⁄4 FIFO + value: 3 + - name: Full + description: FIFO full + value: 4 enum/LFSDET: bit_size: 1 variants: - - name: NoError - description: No error - value: 0 - - name: NoSync - description: Frame synchronization signal is not present at the right time - value: 1 + - name: NoError + description: No error + value: 0 + - name: NoSync + description: Frame synchronization signal is not present at the right time + value: 1 enum/LSBFIRST: bit_size: 1 variants: - - name: MsbFirst - description: Data are transferred with MSB first - value: 0 - - name: LsbFirst - description: Data are transferred with LSB first - value: 1 + - name: MsbFirst + description: Data are transferred with MSB first + value: 0 + - name: LsbFirst + description: Data are transferred with LSB first + value: 1 enum/MODE: bit_size: 2 variants: - - name: MasterTx - description: Master transmitter - value: 0 - - name: MasterRx - description: Master receiver - value: 1 - - name: SlaveTx - description: Slave transmitter - value: 2 - - name: SlaveRx - description: Slave receiver - value: 3 + - name: MasterTx + description: Master transmitter + value: 0 + - name: MasterRx + description: Master receiver + value: 1 + - name: SlaveTx + description: Slave transmitter + value: 2 + - name: SlaveRx + description: Slave receiver + value: 3 enum/MONO: bit_size: 1 variants: - - name: Stereo - description: Stereo mode - value: 0 - - name: Mono - description: Mono mode - value: 1 + - name: Stereo + description: Stereo mode + value: 0 + - name: Mono + description: Mono mode + value: 1 enum/MUTEDET: bit_size: 1 variants: - - name: NoMute - description: No MUTE detection on the SD input line - value: 0 - - name: Mute - description: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame - value: 1 + - name: NoMute + description: No MUTE detection on the SD input line + value: 0 + - name: Mute + description: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame + value: 1 enum/MUTEVAL: bit_size: 1 variants: - - name: SendZero - description: Bit value 0 is sent during the mute mode - value: 0 - - name: SendLast - description: Last values are sent during the mute mode - value: 1 + - name: SendZero + description: Bit value 0 is sent during the mute mode + value: 0 + - name: SendLast + description: Last values are sent during the mute mode + value: 1 enum/NODIV: bit_size: 1 variants: - - name: MasterClock - description: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value - value: 0 - - name: NoDiv - description: "MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL." - value: 1 + - name: MasterClock + description: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value + value: 0 + - name: NoDiv + description: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. + value: 1 enum/OUTDRIV: bit_size: 1 variants: - - name: OnStart - description: Audio block output driven when SAIEN is set - value: 0 - - name: Immediately - description: Audio block output driven immediately after the setting of this bit - value: 1 + - name: OnStart + description: Audio block output driven when SAIEN is set + value: 0 + - name: Immediately + description: Audio block output driven immediately after the setting of this bit + value: 1 enum/OVRUDR: bit_size: 1 variants: - - name: NoError - description: No overrun/underrun error - value: 0 - - name: Overrun - description: Overrun/underrun error detection - value: 1 + - name: NoError + description: No overrun/underrun error + value: 0 + - name: Overrun + description: Overrun/underrun error detection + value: 1 enum/PRTCFG: bit_size: 2 variants: - - name: Free - description: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol - value: 0 - - name: Spdif - description: SPDIF protocol - value: 1 - - name: Ac97 - description: AC’97 protocol - value: 2 + - name: Free + description: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol + value: 0 + - name: Spdif + description: SPDIF protocol + value: 1 + - name: Ac97 + description: AC’97 protocol + value: 2 enum/SLOTEN: bit_size: 16 variants: - - name: Inactive - description: Inactive slot - value: 0 - - name: Active - description: Active slot - value: 1 + - name: Inactive + description: Inactive slot + value: 0 + - name: Active + description: Active slot + value: 1 enum/SLOTSZ: bit_size: 2 variants: - - name: DataSize - description: "The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)" - value: 0 - - name: Bit16 - description: 16-bit - value: 1 - - name: Bit32 - description: 32-bit - value: 2 + - name: DataSize + description: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) + value: 0 + - name: Bit16 + description: 16-bit + value: 1 + - name: Bit32 + description: 32-bit + value: 2 enum/SYNCEN: bit_size: 2 variants: - - name: Asynchronous - description: audio sub-block in asynchronous mode - value: 0 - - name: Internal - description: "audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode" - value: 1 - - name: External - description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode - value: 2 + - name: Asynchronous + description: audio sub-block in asynchronous mode + value: 0 + - name: Internal + description: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode + value: 1 + - name: External + description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode + value: 2 enum/WCKCFG: bit_size: 1 variants: - - name: Correct - description: Clock configuration is correct - value: 0 - - name: Wrong - description: Clock configuration does not respect the rule concerning the frame length specification - value: 1 + - name: Correct + description: Clock configuration is correct + value: 0 + - name: Wrong + description: Clock configuration does not respect the rule concerning the frame length specification + value: 1 diff --git a/data/registers/sai_v3.yaml b/data/registers/sai_v3.yaml index d17db2f..3caf819 100644 --- a/data/registers/sai_v3.yaml +++ b/data/registers/sai_v3.yaml @@ -1,666 +1,665 @@ ---- block/CH: - description: "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR" + description: Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR items: - - name: CR1 - description: Configuration register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Configuration register 2 - byte_offset: 4 - fieldset: CR2 - - name: FRCR - description: This register has no meaning in AC97 and SPDIF audio protocol - byte_offset: 8 - fieldset: FRCR - - name: SLOTR - description: This register has no meaning in AC97 and SPDIF audio protocol - byte_offset: 12 - fieldset: SLOTR - - name: IM - description: Interrupt mask register 2 - byte_offset: 16 - fieldset: IM - - name: SR - description: Status register - byte_offset: 20 - access: Read - fieldset: SR - - name: CLRFR - description: Clear flag register - byte_offset: 24 - access: Write - fieldset: CLRFR - - name: DR - description: Data register - byte_offset: 28 - fieldset: DR + - name: CR1 + description: Configuration register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Configuration register 2 + byte_offset: 4 + fieldset: CR2 + - name: FRCR + description: This register has no meaning in AC97 and SPDIF audio protocol + byte_offset: 8 + fieldset: FRCR + - name: SLOTR + description: This register has no meaning in AC97 and SPDIF audio protocol + byte_offset: 12 + fieldset: SLOTR + - name: IM + description: Interrupt mask register 2 + byte_offset: 16 + fieldset: IM + - name: SR + description: Status register + byte_offset: 20 + access: Read + fieldset: SR + - name: CLRFR + description: Clear flag register + byte_offset: 24 + access: Write + fieldset: CLRFR + - name: DR + description: Data register + byte_offset: 28 + fieldset: DR block/SAI: description: Serial audio interface items: - - name: GCR - description: Global configuration register - byte_offset: 0 - fieldset: GCR - - name: CH - description: "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR" - array: - len: 2 - stride: 32 - byte_offset: 4 - block: CH - - name: PDMCR - description: PDM control register - byte_offset: 68 - fieldset: PDMCR - - name: PDMDLY - description: PDM delay register - byte_offset: 72 - fieldset: PDMDLY + - name: GCR + description: Global configuration register + byte_offset: 0 + fieldset: GCR + - name: CH + description: Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + array: + len: 2 + stride: 32 + byte_offset: 4 + block: CH + - name: PDMCR + description: PDM control register + byte_offset: 68 + fieldset: PDMCR + - name: PDMDLY + description: PDM delay register + byte_offset: 72 + fieldset: PDMDLY fieldset/CLRFR: description: Clear flag register fields: - - name: COVRUDR - description: Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. - bit_offset: 0 - bit_size: 1 - - name: CMUTEDET - description: Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. - bit_offset: 1 - bit_size: 1 - - name: CWCKCFG - description: "Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0." - bit_offset: 2 - bit_size: 1 - - name: CCNRDY - description: Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. - bit_offset: 4 - bit_size: 1 - - name: CAFSDET - description: Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. - bit_offset: 5 - bit_size: 1 - - name: CLFSDET - description: Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. - bit_offset: 6 - bit_size: 1 + - name: COVRUDR + description: Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. + bit_offset: 0 + bit_size: 1 + - name: CMUTEDET + description: Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. + bit_offset: 1 + bit_size: 1 + - name: CWCKCFG + description: Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. + bit_offset: 2 + bit_size: 1 + - name: CCNRDY + description: Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. + bit_offset: 4 + bit_size: 1 + - name: CAFSDET + description: Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. + bit_offset: 5 + bit_size: 1 + - name: CLFSDET + description: Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. + bit_offset: 6 + bit_size: 1 fieldset/CR1: description: Configuration register 1 fields: - - name: MODE - description: SAIx audio block mode immediately - bit_offset: 0 - bit_size: 2 - enum: MODE - - name: PRTCFG - description: Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. - bit_offset: 2 - bit_size: 2 - enum: PRTCFG - - name: DS - description: "Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled." - bit_offset: 5 - bit_size: 3 - enum: DS - - name: LSBFIRST - description: Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. - bit_offset: 8 - bit_size: 1 - enum: LSBFIRST - - name: CKSTR - description: Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. - bit_offset: 9 - bit_size: 1 - enum: CKSTR - - name: SYNCEN - description: "Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled." - bit_offset: 10 - bit_size: 2 - enum: SYNCEN - - name: MONO - description: "Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details." - bit_offset: 12 - bit_size: 1 - enum: MONO - - name: OUTDRIV - description: "Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration." - bit_offset: 13 - bit_size: 1 - enum: OUTDRIV - - name: SAIEN - description: "Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit." - bit_offset: 16 - bit_size: 1 - - name: DMAEN - description: "DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode." - bit_offset: 17 - bit_size: 1 - - name: NODIV - description: No fixed divider between MCLK and FS - bit_offset: 19 - bit_size: 1 - enum: NODIV - - name: MCKDIV - description: "Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:" - bit_offset: 20 - bit_size: 6 - - name: OSR - description: Oversampling ratio for master clock - bit_offset: 26 - bit_size: 1 + - name: MODE + description: SAIx audio block mode immediately + bit_offset: 0 + bit_size: 2 + enum: MODE + - name: PRTCFG + description: Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. + bit_offset: 2 + bit_size: 2 + enum: PRTCFG + - name: DS + description: Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. + bit_offset: 5 + bit_size: 3 + enum: DS + - name: LSBFIRST + description: Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. + bit_offset: 8 + bit_size: 1 + enum: LSBFIRST + - name: CKSTR + description: Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. + bit_offset: 9 + bit_size: 1 + enum: CKSTR + - name: SYNCEN + description: 'Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled.' + bit_offset: 10 + bit_size: 2 + enum: SYNCEN + - name: MONO + description: 'Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details.' + bit_offset: 12 + bit_size: 1 + enum: MONO + - name: OUTDRIV + description: 'Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration.' + bit_offset: 13 + bit_size: 1 + enum: OUTDRIV + - name: SAIEN + description: 'Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit.' + bit_offset: 16 + bit_size: 1 + - name: DMAEN + description: 'DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode.' + bit_offset: 17 + bit_size: 1 + - name: NODIV + description: No fixed divider between MCLK and FS + bit_offset: 19 + bit_size: 1 + enum: NODIV + - name: MCKDIV + description: 'Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:' + bit_offset: 20 + bit_size: 6 + - name: OSR + description: Oversampling ratio for master clock + bit_offset: 26 + bit_size: 1 fieldset/CR2: description: Configuration register 2 fields: - - name: FTH - description: FIFO threshold. This bit is set and cleared by software. - bit_offset: 0 - bit_size: 3 - enum: FTH - - name: FFLUSH - description: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. - bit_offset: 3 - bit_size: 1 - - name: TRIS - description: "Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details." - bit_offset: 4 - bit_size: 1 - - name: MUTE - description: "Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks." - bit_offset: 5 - bit_size: 1 - - name: MUTEVAL - description: "Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks." - bit_offset: 6 - bit_size: 1 - enum: MUTEVAL - - name: MUTECNT - description: "Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details." - bit_offset: 7 - bit_size: 6 - - name: CPL - description: "Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm." - bit_offset: 13 - bit_size: 1 - enum: CPL - - name: COMP - description: "Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected." - bit_offset: 14 - bit_size: 2 - enum: COMP + - name: FTH + description: FIFO threshold. This bit is set and cleared by software. + bit_offset: 0 + bit_size: 3 + enum: FTH + - name: FFLUSH + description: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. + bit_offset: 3 + bit_size: 1 + - name: TRIS + description: 'Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details.' + bit_offset: 4 + bit_size: 1 + - name: MUTE + description: 'Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.' + bit_offset: 5 + bit_size: 1 + - name: MUTEVAL + description: 'Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.' + bit_offset: 6 + bit_size: 1 + enum: MUTEVAL + - name: MUTECNT + description: 'Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details.' + bit_offset: 7 + bit_size: 6 + - name: CPL + description: 'Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm.' + bit_offset: 13 + bit_size: 1 + enum: CPL + - name: COMP + description: 'Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected.' + bit_offset: 14 + bit_size: 2 + enum: COMP fieldset/DR: description: Data register fields: - - name: DATA - description: Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. - bit_offset: 0 - bit_size: 32 + - name: DATA + description: Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. + bit_offset: 0 + bit_size: 32 fieldset/FRCR: description: This register has no meaning in AC97 and SPDIF audio protocol fields: - - name: FRL - description: "Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration." - bit_offset: 0 - bit_size: 8 - - name: FSALL - description: "Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled." - bit_offset: 8 - bit_size: 7 - - name: FSDEF - description: "Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled." - bit_offset: 16 - bit_size: 1 - - name: FSPOL - description: Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - bit_offset: 17 - bit_size: 1 - enum: FSPOL - - name: FSOFF - description: Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - bit_offset: 18 - bit_size: 1 - enum: FSOFF + - name: FRL + description: 'Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration.' + bit_offset: 0 + bit_size: 8 + - name: FSALL + description: Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. + bit_offset: 8 + bit_size: 7 + - name: FSDEF + description: 'Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled.' + bit_offset: 16 + bit_size: 1 + - name: FSPOL + description: Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + bit_offset: 17 + bit_size: 1 + enum: FSPOL + - name: FSOFF + description: Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + bit_offset: 18 + bit_size: 1 + enum: FSOFF fieldset/GCR: description: Global configuration register fields: - - name: SYNCIN - description: Synchronization inputs - bit_offset: 0 - bit_size: 2 - - name: SYNCOUT - description: Synchronization outputs These bits are set and cleared by software. - bit_offset: 4 - bit_size: 2 + - name: SYNCIN + description: Synchronization inputs + bit_offset: 0 + bit_size: 2 + - name: SYNCOUT + description: Synchronization outputs These bits are set and cleared by software. + bit_offset: 4 + bit_size: 2 fieldset/IM: description: Interrupt mask register 2 fields: - - name: OVRUDRIE - description: "Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set." - bit_offset: 0 - bit_size: 1 - - name: MUTEDETIE - description: "Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode." - bit_offset: 1 - bit_size: 1 - - name: WCKCFGIE - description: "Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes." - bit_offset: 2 - bit_size: 1 - - name: FREQIE - description: "FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode," - bit_offset: 3 - bit_size: 1 - - name: CNRDYIE - description: "Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver." - bit_offset: 4 - bit_size: 1 - - name: AFSDETIE - description: "Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master." - bit_offset: 5 - bit_size: 1 - - name: LFSDETIE - description: "Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master." - bit_offset: 6 - bit_size: 1 + - name: OVRUDRIE + description: Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. + bit_offset: 0 + bit_size: 1 + - name: MUTEDETIE + description: Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. + bit_offset: 1 + bit_size: 1 + - name: WCKCFGIE + description: 'Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes.' + bit_offset: 2 + bit_size: 1 + - name: FREQIE + description: FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, + bit_offset: 3 + bit_size: 1 + - name: CNRDYIE + description: Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. + bit_offset: 4 + bit_size: 1 + - name: AFSDETIE + description: Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + bit_offset: 5 + bit_size: 1 + - name: LFSDETIE + description: Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + bit_offset: 6 + bit_size: 1 fieldset/PDMCR: description: PDM control register fields: - - name: PDMEN - description: PDM enable - bit_offset: 0 - bit_size: 1 - - name: MICNBR - description: Number of microphones - bit_offset: 4 - bit_size: 2 - - name: CKEN1 - description: Clock enable of bitstream clock number 1 - bit_offset: 8 - bit_size: 1 - - name: CKEN2 - description: Clock enable of bitstream clock number 2 - bit_offset: 9 - bit_size: 1 - - name: CKEN3 - description: Clock enable of bitstream clock number 3 - bit_offset: 10 - bit_size: 1 - - name: CKEN4 - description: Clock enable of bitstream clock number 4 - bit_offset: 11 - bit_size: 1 + - name: PDMEN + description: PDM enable + bit_offset: 0 + bit_size: 1 + - name: MICNBR + description: Number of microphones + bit_offset: 4 + bit_size: 2 + - name: CKEN1 + description: Clock enable of bitstream clock number 1 + bit_offset: 8 + bit_size: 1 + - name: CKEN2 + description: Clock enable of bitstream clock number 2 + bit_offset: 9 + bit_size: 1 + - name: CKEN3 + description: Clock enable of bitstream clock number 3 + bit_offset: 10 + bit_size: 1 + - name: CKEN4 + description: Clock enable of bitstream clock number 4 + bit_offset: 11 + bit_size: 1 fieldset/PDMDLY: description: PDM delay register fields: - - name: DLYM1L - description: Delay line adjust for first microphone of pair 1 - bit_offset: 0 - bit_size: 3 - - name: DLYM1R - description: Delay line adjust for second microphone of pair 1 - bit_offset: 4 - bit_size: 3 - - name: DLYM2L - description: Delay line for first microphone of pair 2 - bit_offset: 8 - bit_size: 3 - - name: DLYM2R - description: Delay line for second microphone of pair 2 - bit_offset: 12 - bit_size: 3 - - name: DLYM3L - description: Delay line for first microphone of pair 3 - bit_offset: 16 - bit_size: 3 - - name: DLYM3R - description: Delay line for second microphone of pair 3 - bit_offset: 20 - bit_size: 3 - - name: DLYM4L - description: Delay line for first microphone of pair 4 - bit_offset: 24 - bit_size: 3 - - name: DLYM4R - description: Delay line for second microphone of pair 4 - bit_offset: 28 - bit_size: 3 + - name: DLYM1L + description: Delay line adjust for first microphone of pair 1 + bit_offset: 0 + bit_size: 3 + - name: DLYM1R + description: Delay line adjust for second microphone of pair 1 + bit_offset: 4 + bit_size: 3 + - name: DLYM2L + description: Delay line for first microphone of pair 2 + bit_offset: 8 + bit_size: 3 + - name: DLYM2R + description: Delay line for second microphone of pair 2 + bit_offset: 12 + bit_size: 3 + - name: DLYM3L + description: Delay line for first microphone of pair 3 + bit_offset: 16 + bit_size: 3 + - name: DLYM3R + description: Delay line for second microphone of pair 3 + bit_offset: 20 + bit_size: 3 + - name: DLYM4L + description: Delay line for first microphone of pair 4 + bit_offset: 24 + bit_size: 3 + - name: DLYM4R + description: Delay line for second microphone of pair 4 + bit_offset: 28 + bit_size: 3 fieldset/SLOTR: description: This register has no meaning in AC97 and SPDIF audio protocol fields: - - name: FBOFF - description: "First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode." - bit_offset: 0 - bit_size: 5 - - name: SLOTSZ - description: "Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode." - bit_offset: 6 - bit_size: 2 - enum: SLOTSZ - - name: NBSLOT - description: Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - bit_offset: 8 - bit_size: 4 - - name: SLOTEN - description: Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - bit_offset: 16 - bit_size: 16 - enum: SLOTEN + - name: FBOFF + description: First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + bit_offset: 0 + bit_size: 5 + - name: SLOTSZ + description: 'Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode.' + bit_offset: 6 + bit_size: 2 + enum: SLOTSZ + - name: NBSLOT + description: Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + bit_offset: 8 + bit_size: 4 + - name: SLOTEN + description: Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + bit_offset: 16 + bit_size: 16 + enum: SLOTEN fieldset/SR: description: Status register fields: - - name: OVRUDR - description: "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register." - bit_offset: 0 - bit_size: 1 - enum: OVRUDR - - name: MUTEDET - description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. - bit_offset: 1 - bit_size: 1 - enum: MUTEDET - - name: WCKCFG - description: "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register." - bit_offset: 2 - bit_size: 1 - enum: WCKCFG - - name: FREQ - description: "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register." - bit_offset: 3 - bit_size: 1 - enum: FREQ - - name: CNRDY - description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. - bit_offset: 4 - bit_size: 1 - enum: CNRDY - - name: AFSDET - description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. - bit_offset: 5 - bit_size: 1 - enum: AFSDET - - name: LFSDET - description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register - bit_offset: 6 - bit_size: 1 - enum: LFSDET - - name: FLVL - description: "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:" - bit_offset: 16 - bit_size: 3 - enum: FLVL + - name: OVRUDR + description: Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. + bit_offset: 0 + bit_size: 1 + enum: OVRUDR + - name: MUTEDET + description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. + bit_offset: 1 + bit_size: 1 + enum: MUTEDET + - name: WCKCFG + description: Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. + bit_offset: 2 + bit_size: 1 + enum: WCKCFG + - name: FREQ + description: 'FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register.' + bit_offset: 3 + bit_size: 1 + enum: FREQ + - name: CNRDY + description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. + bit_offset: 4 + bit_size: 1 + enum: CNRDY + - name: AFSDET + description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. + bit_offset: 5 + bit_size: 1 + enum: AFSDET + - name: LFSDET + description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register + bit_offset: 6 + bit_size: 1 + enum: LFSDET + - name: FLVL + description: 'FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:' + bit_offset: 16 + bit_size: 3 + enum: FLVL enum/AFSDET: bit_size: 1 variants: - - name: NoError - description: No error - value: 0 - - name: EarlySync - description: Frame synchronization signal is detected earlier than expected - value: 1 + - name: NoError + description: No error + value: 0 + - name: EarlySync + description: Frame synchronization signal is detected earlier than expected + value: 1 enum/CKSTR: bit_size: 1 variants: - - name: FallingEdge - description: Data strobing edge is falling edge of SCK - value: 0 - - name: RisingEdge - description: Data strobing edge is rising edge of SCK - value: 1 + - name: FallingEdge + description: Data strobing edge is falling edge of SCK + value: 0 + - name: RisingEdge + description: Data strobing edge is rising edge of SCK + value: 1 enum/CNRDY: bit_size: 1 variants: - - name: Ready - description: External AC’97 Codec is ready - value: 0 - - name: NotReady - description: External AC’97 Codec is not ready - value: 1 + - name: Ready + description: External AC’97 Codec is ready + value: 0 + - name: NotReady + description: External AC’97 Codec is not ready + value: 1 enum/COMP: bit_size: 2 variants: - - name: NoCompanding - description: No companding algorithm - value: 0 - - name: MuLaw - description: μ-Law algorithm - value: 2 - - name: ALaw - description: A-Law algorithm - value: 3 + - name: NoCompanding + description: No companding algorithm + value: 0 + - name: MuLaw + description: μ-Law algorithm + value: 2 + - name: ALaw + description: A-Law algorithm + value: 3 enum/CPL: bit_size: 1 variants: - - name: OnesComplement - description: 1’s complement representation - value: 0 - - name: TwosComplement - description: 2’s complement representation - value: 1 + - name: OnesComplement + description: 1’s complement representation + value: 0 + - name: TwosComplement + description: 2’s complement representation + value: 1 enum/DS: bit_size: 3 variants: - - name: Bit8 - description: 8 bits - value: 2 - - name: Bit10 - description: 10 bits - value: 3 - - name: Bit16 - description: 16 bits - value: 4 - - name: Bit20 - description: 20 bits - value: 5 - - name: Bit24 - description: 24 bits - value: 6 - - name: Bit32 - description: 32 bits - value: 7 + - name: Bit8 + description: 8 bits + value: 2 + - name: Bit10 + description: 10 bits + value: 3 + - name: Bit16 + description: 16 bits + value: 4 + - name: Bit20 + description: 20 bits + value: 5 + - name: Bit24 + description: 24 bits + value: 6 + - name: Bit32 + description: 32 bits + value: 7 enum/FLVL: bit_size: 3 variants: - - name: Empty - description: FIFO empty - value: 0 - - name: Quarter1 - description: FIFO <= 1⁄4 but not empty - value: 1 - - name: Quarter2 - description: 1⁄4 < FIFO <= 1⁄2 - value: 2 - - name: Quarter3 - description: 1⁄2 < FIFO <= 3⁄4 - value: 3 - - name: Quarter4 - description: 3⁄4 < FIFO but not full - value: 4 - - name: Full - description: FIFO full - value: 5 + - name: Empty + description: FIFO empty + value: 0 + - name: Quarter1 + description: FIFO <= 1⁄4 but not empty + value: 1 + - name: Quarter2 + description: 1⁄4 < FIFO <= 1⁄2 + value: 2 + - name: Quarter3 + description: 1⁄2 < FIFO <= 3⁄4 + value: 3 + - name: Quarter4 + description: 3⁄4 < FIFO but not full + value: 4 + - name: Full + description: FIFO full + value: 5 enum/FREQ: bit_size: 1 variants: - - name: NoRequest - description: No FIFO request - value: 0 - - name: Request - description: FIFO request to read or to write the SAI_xDR - value: 1 + - name: NoRequest + description: No FIFO request + value: 0 + - name: Request + description: FIFO request to read or to write the SAI_xDR + value: 1 enum/FSOFF: bit_size: 1 variants: - - name: OnFirst - description: FS is asserted on the first bit of the slot 0 - value: 0 - - name: BeforeFirst - description: FS is asserted one bit before the first bit of the slot 0 - value: 1 + - name: OnFirst + description: FS is asserted on the first bit of the slot 0 + value: 0 + - name: BeforeFirst + description: FS is asserted one bit before the first bit of the slot 0 + value: 1 enum/FSPOL: bit_size: 1 variants: - - name: FallingEdge - description: FS is active low (falling edge) - value: 0 - - name: RisingEdge - description: FS is active high (rising edge) - value: 1 + - name: FallingEdge + description: FS is active low (falling edge) + value: 0 + - name: RisingEdge + description: FS is active high (rising edge) + value: 1 enum/FTH: bit_size: 3 variants: - - name: Empty - description: FIFO empty - value: 0 - - name: Quarter1 - description: 1⁄4 FIFO - value: 1 - - name: Quarter2 - description: 1⁄2 FIFO - value: 2 - - name: Quarter3 - description: 3⁄4 FIFO - value: 3 - - name: Full - description: FIFO full - value: 4 + - name: Empty + description: FIFO empty + value: 0 + - name: Quarter1 + description: 1⁄4 FIFO + value: 1 + - name: Quarter2 + description: 1⁄2 FIFO + value: 2 + - name: Quarter3 + description: 3⁄4 FIFO + value: 3 + - name: Full + description: FIFO full + value: 4 enum/LFSDET: bit_size: 1 variants: - - name: NoError - description: No error - value: 0 - - name: NoSync - description: Frame synchronization signal is not present at the right time - value: 1 + - name: NoError + description: No error + value: 0 + - name: NoSync + description: Frame synchronization signal is not present at the right time + value: 1 enum/LSBFIRST: bit_size: 1 variants: - - name: MsbFirst - description: Data are transferred with MSB first - value: 0 - - name: LsbFirst - description: Data are transferred with LSB first - value: 1 + - name: MsbFirst + description: Data are transferred with MSB first + value: 0 + - name: LsbFirst + description: Data are transferred with LSB first + value: 1 enum/MODE: bit_size: 2 variants: - - name: MasterTx - description: Master transmitter - value: 0 - - name: MasterRx - description: Master receiver - value: 1 - - name: SlaveTx - description: Slave transmitter - value: 2 - - name: SlaveRx - description: Slave receiver - value: 3 + - name: MasterTx + description: Master transmitter + value: 0 + - name: MasterRx + description: Master receiver + value: 1 + - name: SlaveTx + description: Slave transmitter + value: 2 + - name: SlaveRx + description: Slave receiver + value: 3 enum/MONO: bit_size: 1 variants: - - name: Stereo - description: Stereo mode - value: 0 - - name: Mono - description: Mono mode - value: 1 + - name: Stereo + description: Stereo mode + value: 0 + - name: Mono + description: Mono mode + value: 1 enum/MUTEDET: bit_size: 1 variants: - - name: NoMute - description: No MUTE detection on the SD input line - value: 0 - - name: Mute - description: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame - value: 1 + - name: NoMute + description: No MUTE detection on the SD input line + value: 0 + - name: Mute + description: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame + value: 1 enum/MUTEVAL: bit_size: 1 variants: - - name: SendZero - description: Bit value 0 is sent during the mute mode - value: 0 - - name: SendLast - description: Last values are sent during the mute mode - value: 1 + - name: SendZero + description: Bit value 0 is sent during the mute mode + value: 0 + - name: SendLast + description: Last values are sent during the mute mode + value: 1 enum/NODIV: bit_size: 1 variants: - - name: MasterClock - description: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value - value: 0 - - name: NoDiv - description: "MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL." - value: 1 + - name: MasterClock + description: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value + value: 0 + - name: NoDiv + description: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. + value: 1 enum/OUTDRIV: bit_size: 1 variants: - - name: OnStart - description: Audio block output driven when SAIEN is set - value: 0 - - name: Immediately - description: Audio block output driven immediately after the setting of this bit - value: 1 + - name: OnStart + description: Audio block output driven when SAIEN is set + value: 0 + - name: Immediately + description: Audio block output driven immediately after the setting of this bit + value: 1 enum/OVRUDR: bit_size: 1 variants: - - name: NoError - description: No overrun/underrun error - value: 0 - - name: Overrun - description: Overrun/underrun error detection - value: 1 + - name: NoError + description: No overrun/underrun error + value: 0 + - name: Overrun + description: Overrun/underrun error detection + value: 1 enum/PRTCFG: bit_size: 2 variants: - - name: Free - description: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol - value: 0 - - name: Spdif - description: SPDIF protocol - value: 1 - - name: Ac97 - description: AC’97 protocol - value: 2 + - name: Free + description: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol + value: 0 + - name: Spdif + description: SPDIF protocol + value: 1 + - name: Ac97 + description: AC’97 protocol + value: 2 enum/SLOTEN: bit_size: 16 variants: - - name: Inactive - description: Inactive slot - value: 0 - - name: Active - description: Active slot - value: 1 + - name: Inactive + description: Inactive slot + value: 0 + - name: Active + description: Active slot + value: 1 enum/SLOTSZ: bit_size: 2 variants: - - name: DataSize - description: "The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)" - value: 0 - - name: Bit16 - description: 16-bit - value: 1 - - name: Bit32 - description: 32-bit - value: 2 + - name: DataSize + description: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) + value: 0 + - name: Bit16 + description: 16-bit + value: 1 + - name: Bit32 + description: 32-bit + value: 2 enum/SYNCEN: bit_size: 2 variants: - - name: Asynchronous - description: audio sub-block in asynchronous mode - value: 0 - - name: Internal - description: "audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode" - value: 1 - - name: External - description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode - value: 2 + - name: Asynchronous + description: audio sub-block in asynchronous mode + value: 0 + - name: Internal + description: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode + value: 1 + - name: External + description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode + value: 2 enum/WCKCFG: bit_size: 1 variants: - - name: Correct - description: Clock configuration is correct - value: 0 - - name: Wrong - description: Clock configuration does not respect the rule concerning the frame length specification - value: 1 + - name: Correct + description: Clock configuration is correct + value: 0 + - name: Wrong + description: Clock configuration does not respect the rule concerning the frame length specification + value: 1 diff --git a/data/registers/sai_v4.yaml b/data/registers/sai_v4.yaml index 887eb1b..99d3c75 100644 --- a/data/registers/sai_v4.yaml +++ b/data/registers/sai_v4.yaml @@ -1,670 +1,669 @@ ---- block/CH: - description: "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR" + description: Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR items: - - name: CR1 - description: Configuration register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Configuration register 2 - byte_offset: 4 - fieldset: CR2 - - name: FRCR - description: This register has no meaning in AC97 and SPDIF audio protocol - byte_offset: 8 - fieldset: FRCR - - name: SLOTR - description: This register has no meaning in AC97 and SPDIF audio protocol - byte_offset: 12 - fieldset: SLOTR - - name: IM - description: Interrupt mask register 2 - byte_offset: 16 - fieldset: IM - - name: SR - description: Status register - byte_offset: 20 - access: Read - fieldset: SR - - name: CLRFR - description: Clear flag register - byte_offset: 24 - access: Write - fieldset: CLRFR - - name: DR - description: Data register - byte_offset: 28 - fieldset: DR + - name: CR1 + description: Configuration register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Configuration register 2 + byte_offset: 4 + fieldset: CR2 + - name: FRCR + description: This register has no meaning in AC97 and SPDIF audio protocol + byte_offset: 8 + fieldset: FRCR + - name: SLOTR + description: This register has no meaning in AC97 and SPDIF audio protocol + byte_offset: 12 + fieldset: SLOTR + - name: IM + description: Interrupt mask register 2 + byte_offset: 16 + fieldset: IM + - name: SR + description: Status register + byte_offset: 20 + access: Read + fieldset: SR + - name: CLRFR + description: Clear flag register + byte_offset: 24 + access: Write + fieldset: CLRFR + - name: DR + description: Data register + byte_offset: 28 + fieldset: DR block/SAI: description: Serial audio interface items: - - name: GCR - description: Global configuration register - byte_offset: 0 - fieldset: GCR - - name: CH - description: "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR" - array: - len: 2 - stride: 32 - byte_offset: 4 - block: CH - - name: PDMCR - description: PDM control register - byte_offset: 68 - fieldset: PDMCR - - name: PDMDLY - description: PDM delay register - byte_offset: 72 - fieldset: PDMDLY + - name: GCR + description: Global configuration register + byte_offset: 0 + fieldset: GCR + - name: CH + description: Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + array: + len: 2 + stride: 32 + byte_offset: 4 + block: CH + - name: PDMCR + description: PDM control register + byte_offset: 68 + fieldset: PDMCR + - name: PDMDLY + description: PDM delay register + byte_offset: 72 + fieldset: PDMDLY fieldset/CLRFR: description: Clear flag register fields: - - name: COVRUDR - description: Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. - bit_offset: 0 - bit_size: 1 - - name: CMUTEDET - description: Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. - bit_offset: 1 - bit_size: 1 - - name: CWCKCFG - description: "Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0." - bit_offset: 2 - bit_size: 1 - - name: CCNRDY - description: Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. - bit_offset: 4 - bit_size: 1 - - name: CAFSDET - description: Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. - bit_offset: 5 - bit_size: 1 - - name: CLFSDET - description: Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. - bit_offset: 6 - bit_size: 1 + - name: COVRUDR + description: Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. + bit_offset: 0 + bit_size: 1 + - name: CMUTEDET + description: Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. + bit_offset: 1 + bit_size: 1 + - name: CWCKCFG + description: Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. + bit_offset: 2 + bit_size: 1 + - name: CCNRDY + description: Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. + bit_offset: 4 + bit_size: 1 + - name: CAFSDET + description: Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. + bit_offset: 5 + bit_size: 1 + - name: CLFSDET + description: Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. + bit_offset: 6 + bit_size: 1 fieldset/CR1: description: Configuration register 1 fields: - - name: MODE - description: SAIx audio block mode immediately - bit_offset: 0 - bit_size: 2 - enum: MODE - - name: PRTCFG - description: Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. - bit_offset: 2 - bit_size: 2 - enum: PRTCFG - - name: DS - description: "Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled." - bit_offset: 5 - bit_size: 3 - enum: DS - - name: LSBFIRST - description: Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. - bit_offset: 8 - bit_size: 1 - enum: LSBFIRST - - name: CKSTR - description: Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. - bit_offset: 9 - bit_size: 1 - enum: CKSTR - - name: SYNCEN - description: "Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled." - bit_offset: 10 - bit_size: 2 - enum: SYNCEN - - name: MONO - description: "Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details." - bit_offset: 12 - bit_size: 1 - enum: MONO - - name: OUTDRIV - description: "Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration." - bit_offset: 13 - bit_size: 1 - enum: OUTDRIV - - name: SAIEN - description: "Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit." - bit_offset: 16 - bit_size: 1 - - name: DMAEN - description: "DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode." - bit_offset: 17 - bit_size: 1 - - name: NODIV - description: No fixed divider between MCLK and FS - bit_offset: 19 - bit_size: 1 - enum: NODIV - - name: MCKDIV - description: "Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:" - bit_offset: 20 - bit_size: 6 - - name: OSR - description: Oversampling ratio for master clock - bit_offset: 26 - bit_size: 1 - - name: MCKEN - description: Master clock generation enable - bit_offset: 27 - bit_size: 1 + - name: MODE + description: SAIx audio block mode immediately + bit_offset: 0 + bit_size: 2 + enum: MODE + - name: PRTCFG + description: Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. + bit_offset: 2 + bit_size: 2 + enum: PRTCFG + - name: DS + description: Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. + bit_offset: 5 + bit_size: 3 + enum: DS + - name: LSBFIRST + description: Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. + bit_offset: 8 + bit_size: 1 + enum: LSBFIRST + - name: CKSTR + description: Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. + bit_offset: 9 + bit_size: 1 + enum: CKSTR + - name: SYNCEN + description: 'Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled.' + bit_offset: 10 + bit_size: 2 + enum: SYNCEN + - name: MONO + description: 'Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details.' + bit_offset: 12 + bit_size: 1 + enum: MONO + - name: OUTDRIV + description: 'Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration.' + bit_offset: 13 + bit_size: 1 + enum: OUTDRIV + - name: SAIEN + description: 'Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit.' + bit_offset: 16 + bit_size: 1 + - name: DMAEN + description: 'DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode.' + bit_offset: 17 + bit_size: 1 + - name: NODIV + description: No fixed divider between MCLK and FS + bit_offset: 19 + bit_size: 1 + enum: NODIV + - name: MCKDIV + description: 'Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:' + bit_offset: 20 + bit_size: 6 + - name: OSR + description: Oversampling ratio for master clock + bit_offset: 26 + bit_size: 1 + - name: MCKEN + description: Master clock generation enable + bit_offset: 27 + bit_size: 1 fieldset/CR2: description: Configuration register 2 fields: - - name: FTH - description: FIFO threshold. This bit is set and cleared by software. - bit_offset: 0 - bit_size: 3 - enum: FTH - - name: FFLUSH - description: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. - bit_offset: 3 - bit_size: 1 - - name: TRIS - description: "Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details." - bit_offset: 4 - bit_size: 1 - - name: MUTE - description: "Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks." - bit_offset: 5 - bit_size: 1 - - name: MUTEVAL - description: "Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks." - bit_offset: 6 - bit_size: 1 - enum: MUTEVAL - - name: MUTECNT - description: "Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details." - bit_offset: 7 - bit_size: 6 - - name: CPL - description: "Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm." - bit_offset: 13 - bit_size: 1 - enum: CPL - - name: COMP - description: "Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected." - bit_offset: 14 - bit_size: 2 - enum: COMP + - name: FTH + description: FIFO threshold. This bit is set and cleared by software. + bit_offset: 0 + bit_size: 3 + enum: FTH + - name: FFLUSH + description: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. + bit_offset: 3 + bit_size: 1 + - name: TRIS + description: 'Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details.' + bit_offset: 4 + bit_size: 1 + - name: MUTE + description: 'Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.' + bit_offset: 5 + bit_size: 1 + - name: MUTEVAL + description: 'Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.' + bit_offset: 6 + bit_size: 1 + enum: MUTEVAL + - name: MUTECNT + description: 'Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details.' + bit_offset: 7 + bit_size: 6 + - name: CPL + description: 'Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm.' + bit_offset: 13 + bit_size: 1 + enum: CPL + - name: COMP + description: 'Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected.' + bit_offset: 14 + bit_size: 2 + enum: COMP fieldset/DR: description: Data register fields: - - name: DATA - description: Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. - bit_offset: 0 - bit_size: 32 + - name: DATA + description: Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. + bit_offset: 0 + bit_size: 32 fieldset/FRCR: description: This register has no meaning in AC97 and SPDIF audio protocol fields: - - name: FRL - description: "Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration." - bit_offset: 0 - bit_size: 8 - - name: FSALL - description: "Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled." - bit_offset: 8 - bit_size: 7 - - name: FSDEF - description: "Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled." - bit_offset: 16 - bit_size: 1 - - name: FSPOL - description: Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - bit_offset: 17 - bit_size: 1 - enum: FSPOL - - name: FSOFF - description: Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - bit_offset: 18 - bit_size: 1 - enum: FSOFF + - name: FRL + description: 'Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration.' + bit_offset: 0 + bit_size: 8 + - name: FSALL + description: Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. + bit_offset: 8 + bit_size: 7 + - name: FSDEF + description: 'Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled.' + bit_offset: 16 + bit_size: 1 + - name: FSPOL + description: Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + bit_offset: 17 + bit_size: 1 + enum: FSPOL + - name: FSOFF + description: Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + bit_offset: 18 + bit_size: 1 + enum: FSOFF fieldset/GCR: description: Global configuration register fields: - - name: SYNCIN - description: Synchronization inputs - bit_offset: 0 - bit_size: 2 - - name: SYNCOUT - description: Synchronization outputs These bits are set and cleared by software. - bit_offset: 4 - bit_size: 2 + - name: SYNCIN + description: Synchronization inputs + bit_offset: 0 + bit_size: 2 + - name: SYNCOUT + description: Synchronization outputs These bits are set and cleared by software. + bit_offset: 4 + bit_size: 2 fieldset/IM: description: Interrupt mask register 2 fields: - - name: OVRUDRIE - description: "Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set." - bit_offset: 0 - bit_size: 1 - - name: MUTEDETIE - description: "Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode." - bit_offset: 1 - bit_size: 1 - - name: WCKCFGIE - description: "Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes." - bit_offset: 2 - bit_size: 1 - - name: FREQIE - description: "FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode," - bit_offset: 3 - bit_size: 1 - - name: CNRDYIE - description: "Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver." - bit_offset: 4 - bit_size: 1 - - name: AFSDETIE - description: "Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master." - bit_offset: 5 - bit_size: 1 - - name: LFSDETIE - description: "Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master." - bit_offset: 6 - bit_size: 1 + - name: OVRUDRIE + description: Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. + bit_offset: 0 + bit_size: 1 + - name: MUTEDETIE + description: Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. + bit_offset: 1 + bit_size: 1 + - name: WCKCFGIE + description: 'Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes.' + bit_offset: 2 + bit_size: 1 + - name: FREQIE + description: FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, + bit_offset: 3 + bit_size: 1 + - name: CNRDYIE + description: Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. + bit_offset: 4 + bit_size: 1 + - name: AFSDETIE + description: Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + bit_offset: 5 + bit_size: 1 + - name: LFSDETIE + description: Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + bit_offset: 6 + bit_size: 1 fieldset/PDMCR: description: PDM control register fields: - - name: PDMEN - description: PDM enable - bit_offset: 0 - bit_size: 1 - - name: MICNBR - description: Number of microphones - bit_offset: 4 - bit_size: 2 - - name: CKEN1 - description: Clock enable of bitstream clock number 1 - bit_offset: 8 - bit_size: 1 - - name: CKEN2 - description: Clock enable of bitstream clock number 2 - bit_offset: 9 - bit_size: 1 - - name: CKEN3 - description: Clock enable of bitstream clock number 3 - bit_offset: 10 - bit_size: 1 - - name: CKEN4 - description: Clock enable of bitstream clock number 4 - bit_offset: 11 - bit_size: 1 + - name: PDMEN + description: PDM enable + bit_offset: 0 + bit_size: 1 + - name: MICNBR + description: Number of microphones + bit_offset: 4 + bit_size: 2 + - name: CKEN1 + description: Clock enable of bitstream clock number 1 + bit_offset: 8 + bit_size: 1 + - name: CKEN2 + description: Clock enable of bitstream clock number 2 + bit_offset: 9 + bit_size: 1 + - name: CKEN3 + description: Clock enable of bitstream clock number 3 + bit_offset: 10 + bit_size: 1 + - name: CKEN4 + description: Clock enable of bitstream clock number 4 + bit_offset: 11 + bit_size: 1 fieldset/PDMDLY: description: PDM delay register fields: - - name: DLYM1L - description: Delay line adjust for first microphone of pair 1 - bit_offset: 0 - bit_size: 3 - - name: DLYM1R - description: Delay line adjust for second microphone of pair 1 - bit_offset: 4 - bit_size: 3 - - name: DLYM2L - description: Delay line for first microphone of pair 2 - bit_offset: 8 - bit_size: 3 - - name: DLYM2R - description: Delay line for second microphone of pair 2 - bit_offset: 12 - bit_size: 3 - - name: DLYM3L - description: Delay line for first microphone of pair 3 - bit_offset: 16 - bit_size: 3 - - name: DLYM3R - description: Delay line for second microphone of pair 3 - bit_offset: 20 - bit_size: 3 - - name: DLYM4L - description: Delay line for first microphone of pair 4 - bit_offset: 24 - bit_size: 3 - - name: DLYM4R - description: Delay line for second microphone of pair 4 - bit_offset: 28 - bit_size: 3 + - name: DLYM1L + description: Delay line adjust for first microphone of pair 1 + bit_offset: 0 + bit_size: 3 + - name: DLYM1R + description: Delay line adjust for second microphone of pair 1 + bit_offset: 4 + bit_size: 3 + - name: DLYM2L + description: Delay line for first microphone of pair 2 + bit_offset: 8 + bit_size: 3 + - name: DLYM2R + description: Delay line for second microphone of pair 2 + bit_offset: 12 + bit_size: 3 + - name: DLYM3L + description: Delay line for first microphone of pair 3 + bit_offset: 16 + bit_size: 3 + - name: DLYM3R + description: Delay line for second microphone of pair 3 + bit_offset: 20 + bit_size: 3 + - name: DLYM4L + description: Delay line for first microphone of pair 4 + bit_offset: 24 + bit_size: 3 + - name: DLYM4R + description: Delay line for second microphone of pair 4 + bit_offset: 28 + bit_size: 3 fieldset/SLOTR: description: This register has no meaning in AC97 and SPDIF audio protocol fields: - - name: FBOFF - description: "First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode." - bit_offset: 0 - bit_size: 5 - - name: SLOTSZ - description: "Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode." - bit_offset: 6 - bit_size: 2 - enum: SLOTSZ - - name: NBSLOT - description: Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - bit_offset: 8 - bit_size: 4 - - name: SLOTEN - description: Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - bit_offset: 16 - bit_size: 16 - enum: SLOTEN + - name: FBOFF + description: First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + bit_offset: 0 + bit_size: 5 + - name: SLOTSZ + description: 'Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode.' + bit_offset: 6 + bit_size: 2 + enum: SLOTSZ + - name: NBSLOT + description: Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + bit_offset: 8 + bit_size: 4 + - name: SLOTEN + description: Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + bit_offset: 16 + bit_size: 16 + enum: SLOTEN fieldset/SR: description: Status register fields: - - name: OVRUDR - description: "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register." - bit_offset: 0 - bit_size: 1 - enum: OVRUDR - - name: MUTEDET - description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. - bit_offset: 1 - bit_size: 1 - enum: MUTEDET - - name: WCKCFG - description: "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register." - bit_offset: 2 - bit_size: 1 - enum: WCKCFG - - name: FREQ - description: "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register." - bit_offset: 3 - bit_size: 1 - enum: FREQ - - name: CNRDY - description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. - bit_offset: 4 - bit_size: 1 - enum: CNRDY - - name: AFSDET - description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. - bit_offset: 5 - bit_size: 1 - enum: AFSDET - - name: LFSDET - description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register - bit_offset: 6 - bit_size: 1 - enum: LFSDET - - name: FLVL - description: "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:" - bit_offset: 16 - bit_size: 3 - enum: FLVL + - name: OVRUDR + description: Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. + bit_offset: 0 + bit_size: 1 + enum: OVRUDR + - name: MUTEDET + description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. + bit_offset: 1 + bit_size: 1 + enum: MUTEDET + - name: WCKCFG + description: Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. + bit_offset: 2 + bit_size: 1 + enum: WCKCFG + - name: FREQ + description: 'FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register.' + bit_offset: 3 + bit_size: 1 + enum: FREQ + - name: CNRDY + description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. + bit_offset: 4 + bit_size: 1 + enum: CNRDY + - name: AFSDET + description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. + bit_offset: 5 + bit_size: 1 + enum: AFSDET + - name: LFSDET + description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register + bit_offset: 6 + bit_size: 1 + enum: LFSDET + - name: FLVL + description: 'FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:' + bit_offset: 16 + bit_size: 3 + enum: FLVL enum/AFSDET: bit_size: 1 variants: - - name: NoError - description: No error - value: 0 - - name: EarlySync - description: Frame synchronization signal is detected earlier than expected - value: 1 + - name: NoError + description: No error + value: 0 + - name: EarlySync + description: Frame synchronization signal is detected earlier than expected + value: 1 enum/CKSTR: bit_size: 1 variants: - - name: FallingEdge - description: Data strobing edge is falling edge of SCK - value: 0 - - name: RisingEdge - description: Data strobing edge is rising edge of SCK - value: 1 + - name: FallingEdge + description: Data strobing edge is falling edge of SCK + value: 0 + - name: RisingEdge + description: Data strobing edge is rising edge of SCK + value: 1 enum/CNRDY: bit_size: 1 variants: - - name: Ready - description: External AC’97 Codec is ready - value: 0 - - name: NotReady - description: External AC’97 Codec is not ready - value: 1 + - name: Ready + description: External AC’97 Codec is ready + value: 0 + - name: NotReady + description: External AC’97 Codec is not ready + value: 1 enum/COMP: bit_size: 2 variants: - - name: NoCompanding - description: No companding algorithm - value: 0 - - name: MuLaw - description: μ-Law algorithm - value: 2 - - name: ALaw - description: A-Law algorithm - value: 3 + - name: NoCompanding + description: No companding algorithm + value: 0 + - name: MuLaw + description: μ-Law algorithm + value: 2 + - name: ALaw + description: A-Law algorithm + value: 3 enum/CPL: bit_size: 1 variants: - - name: OnesComplement - description: 1’s complement representation - value: 0 - - name: TwosComplement - description: 2’s complement representation - value: 1 + - name: OnesComplement + description: 1’s complement representation + value: 0 + - name: TwosComplement + description: 2’s complement representation + value: 1 enum/DS: bit_size: 3 variants: - - name: Bit8 - description: 8 bits - value: 2 - - name: Bit10 - description: 10 bits - value: 3 - - name: Bit16 - description: 16 bits - value: 4 - - name: Bit20 - description: 20 bits - value: 5 - - name: Bit24 - description: 24 bits - value: 6 - - name: Bit32 - description: 32 bits - value: 7 + - name: Bit8 + description: 8 bits + value: 2 + - name: Bit10 + description: 10 bits + value: 3 + - name: Bit16 + description: 16 bits + value: 4 + - name: Bit20 + description: 20 bits + value: 5 + - name: Bit24 + description: 24 bits + value: 6 + - name: Bit32 + description: 32 bits + value: 7 enum/FLVL: bit_size: 3 variants: - - name: Empty - description: FIFO empty - value: 0 - - name: Quarter1 - description: FIFO <= 1⁄4 but not empty - value: 1 - - name: Quarter2 - description: 1⁄4 < FIFO <= 1⁄2 - value: 2 - - name: Quarter3 - description: 1⁄2 < FIFO <= 3⁄4 - value: 3 - - name: Quarter4 - description: 3⁄4 < FIFO but not full - value: 4 - - name: Full - description: FIFO full - value: 5 + - name: Empty + description: FIFO empty + value: 0 + - name: Quarter1 + description: FIFO <= 1⁄4 but not empty + value: 1 + - name: Quarter2 + description: 1⁄4 < FIFO <= 1⁄2 + value: 2 + - name: Quarter3 + description: 1⁄2 < FIFO <= 3⁄4 + value: 3 + - name: Quarter4 + description: 3⁄4 < FIFO but not full + value: 4 + - name: Full + description: FIFO full + value: 5 enum/FREQ: bit_size: 1 variants: - - name: NoRequest - description: No FIFO request - value: 0 - - name: Request - description: FIFO request to read or to write the SAI_xDR - value: 1 + - name: NoRequest + description: No FIFO request + value: 0 + - name: Request + description: FIFO request to read or to write the SAI_xDR + value: 1 enum/FSOFF: bit_size: 1 variants: - - name: OnFirst - description: FS is asserted on the first bit of the slot 0 - value: 0 - - name: BeforeFirst - description: FS is asserted one bit before the first bit of the slot 0 - value: 1 + - name: OnFirst + description: FS is asserted on the first bit of the slot 0 + value: 0 + - name: BeforeFirst + description: FS is asserted one bit before the first bit of the slot 0 + value: 1 enum/FSPOL: bit_size: 1 variants: - - name: FallingEdge - description: FS is active low (falling edge) - value: 0 - - name: RisingEdge - description: FS is active high (rising edge) - value: 1 + - name: FallingEdge + description: FS is active low (falling edge) + value: 0 + - name: RisingEdge + description: FS is active high (rising edge) + value: 1 enum/FTH: bit_size: 3 variants: - - name: Empty - description: FIFO empty - value: 0 - - name: Quarter1 - description: 1⁄4 FIFO - value: 1 - - name: Quarter2 - description: 1⁄2 FIFO - value: 2 - - name: Quarter3 - description: 3⁄4 FIFO - value: 3 - - name: Full - description: FIFO full - value: 4 + - name: Empty + description: FIFO empty + value: 0 + - name: Quarter1 + description: 1⁄4 FIFO + value: 1 + - name: Quarter2 + description: 1⁄2 FIFO + value: 2 + - name: Quarter3 + description: 3⁄4 FIFO + value: 3 + - name: Full + description: FIFO full + value: 4 enum/LFSDET: bit_size: 1 variants: - - name: NoError - description: No error - value: 0 - - name: NoSync - description: Frame synchronization signal is not present at the right time - value: 1 + - name: NoError + description: No error + value: 0 + - name: NoSync + description: Frame synchronization signal is not present at the right time + value: 1 enum/LSBFIRST: bit_size: 1 variants: - - name: MsbFirst - description: Data are transferred with MSB first - value: 0 - - name: LsbFirst - description: Data are transferred with LSB first - value: 1 + - name: MsbFirst + description: Data are transferred with MSB first + value: 0 + - name: LsbFirst + description: Data are transferred with LSB first + value: 1 enum/MODE: bit_size: 2 variants: - - name: MasterTx - description: Master transmitter - value: 0 - - name: MasterRx - description: Master receiver - value: 1 - - name: SlaveTx - description: Slave transmitter - value: 2 - - name: SlaveRx - description: Slave receiver - value: 3 + - name: MasterTx + description: Master transmitter + value: 0 + - name: MasterRx + description: Master receiver + value: 1 + - name: SlaveTx + description: Slave transmitter + value: 2 + - name: SlaveRx + description: Slave receiver + value: 3 enum/MONO: bit_size: 1 variants: - - name: Stereo - description: Stereo mode - value: 0 - - name: Mono - description: Mono mode - value: 1 + - name: Stereo + description: Stereo mode + value: 0 + - name: Mono + description: Mono mode + value: 1 enum/MUTEDET: bit_size: 1 variants: - - name: NoMute - description: No MUTE detection on the SD input line - value: 0 - - name: Mute - description: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame - value: 1 + - name: NoMute + description: No MUTE detection on the SD input line + value: 0 + - name: Mute + description: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame + value: 1 enum/MUTEVAL: bit_size: 1 variants: - - name: SendZero - description: Bit value 0 is sent during the mute mode - value: 0 - - name: SendLast - description: Last values are sent during the mute mode - value: 1 + - name: SendZero + description: Bit value 0 is sent during the mute mode + value: 0 + - name: SendLast + description: Last values are sent during the mute mode + value: 1 enum/NODIV: bit_size: 1 variants: - - name: MasterClock - description: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value - value: 0 - - name: NoDiv - description: "MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL." - value: 1 + - name: MasterClock + description: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value + value: 0 + - name: NoDiv + description: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. + value: 1 enum/OUTDRIV: bit_size: 1 variants: - - name: OnStart - description: Audio block output driven when SAIEN is set - value: 0 - - name: Immediately - description: Audio block output driven immediately after the setting of this bit - value: 1 + - name: OnStart + description: Audio block output driven when SAIEN is set + value: 0 + - name: Immediately + description: Audio block output driven immediately after the setting of this bit + value: 1 enum/OVRUDR: bit_size: 1 variants: - - name: NoError - description: No overrun/underrun error - value: 0 - - name: Overrun - description: Overrun/underrun error detection - value: 1 + - name: NoError + description: No overrun/underrun error + value: 0 + - name: Overrun + description: Overrun/underrun error detection + value: 1 enum/PRTCFG: bit_size: 2 variants: - - name: Free - description: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol - value: 0 - - name: Spdif - description: SPDIF protocol - value: 1 - - name: Ac97 - description: AC’97 protocol - value: 2 + - name: Free + description: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol + value: 0 + - name: Spdif + description: SPDIF protocol + value: 1 + - name: Ac97 + description: AC’97 protocol + value: 2 enum/SLOTEN: bit_size: 16 variants: - - name: Inactive - description: Inactive slot - value: 0 - - name: Active - description: Active slot - value: 1 + - name: Inactive + description: Inactive slot + value: 0 + - name: Active + description: Active slot + value: 1 enum/SLOTSZ: bit_size: 2 variants: - - name: DataSize - description: "The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)" - value: 0 - - name: Bit16 - description: 16-bit - value: 1 - - name: Bit32 - description: 32-bit - value: 2 + - name: DataSize + description: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) + value: 0 + - name: Bit16 + description: 16-bit + value: 1 + - name: Bit32 + description: 32-bit + value: 2 enum/SYNCEN: bit_size: 2 variants: - - name: Asynchronous - description: audio sub-block in asynchronous mode - value: 0 - - name: Internal - description: "audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode" - value: 1 - - name: External - description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode - value: 2 + - name: Asynchronous + description: audio sub-block in asynchronous mode + value: 0 + - name: Internal + description: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode + value: 1 + - name: External + description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode + value: 2 enum/WCKCFG: bit_size: 1 variants: - - name: Correct - description: Clock configuration is correct - value: 0 - - name: Wrong - description: Clock configuration does not respect the rule concerning the frame length specification - value: 1 + - name: Correct + description: Clock configuration is correct + value: 0 + - name: Wrong + description: Clock configuration does not respect the rule concerning the frame length specification + value: 1 diff --git a/data/registers/sbs_h5.yaml b/data/registers/sbs_h5.yaml index 6299993..2b9d3f5 100644 --- a/data/registers/sbs_h5.yaml +++ b/data/registers/sbs_h5.yaml @@ -1,410 +1,409 @@ ---- block/SBS: description: SBS register block items: - - name: HDPLCR - description: SBS temporal isolation control register - byte_offset: 16 - fieldset: HDPLCR - - name: HDPLSR - description: SBS temporal isolation status register - byte_offset: 20 - fieldset: HDPLSR - - name: NEXTHDPLCR - description: SBS next HDPL control register - byte_offset: 24 - fieldset: NEXTHDPLCR - - name: DBGCR - description: SBS debug control register - byte_offset: 32 - fieldset: DBGCR - - name: DBGLOCKR - description: SBS debug lock register - byte_offset: 36 - fieldset: DBGLOCKR - - name: RSSCMDR - description: SBS RSS command register - byte_offset: 52 - fieldset: RSSCMDR - - name: EPOCHSELCR - description: SBS EPOCH selection control register - byte_offset: 160 - fieldset: EPOCHSELCR - - name: SECCFGR - description: SBS security mode configuration control register - byte_offset: 192 - fieldset: SECCFGR - - name: PMCR - description: SBS product mode and configuration register - byte_offset: 256 - fieldset: PMCR - - name: FPUIMR - description: SBS FPU interrupt mask register - byte_offset: 260 - fieldset: FPUIMR - - name: MESR - description: SBS memory erase status register - byte_offset: 264 - fieldset: MESR - - name: CCCSR - description: SBS compensation cell for I/Os control and status register - byte_offset: 272 - fieldset: CCCSR - - name: CCVALR - description: SBS compensation cell for I/Os value register - byte_offset: 276 - fieldset: CCVALR - - name: CCSWCR - description: SBS compensation cell for I/Os software code register - byte_offset: 280 - fieldset: CCSWCR - - name: CFGR2 - description: SBS Class B register - byte_offset: 288 - fieldset: CFGR2 - - name: CNSLCKR - description: SBS CPU non-secure lock register - byte_offset: 324 - fieldset: CNSLCKR - - name: CSLCKR - description: SBS CPU secure lock register - byte_offset: 328 - fieldset: CSLCKR - - name: ECCNMIR - description: SBS flift ECC NMI mask register - byte_offset: 332 - fieldset: ECCNMIR + - name: HDPLCR + description: SBS temporal isolation control register + byte_offset: 16 + fieldset: HDPLCR + - name: HDPLSR + description: SBS temporal isolation status register + byte_offset: 20 + fieldset: HDPLSR + - name: NEXTHDPLCR + description: SBS next HDPL control register + byte_offset: 24 + fieldset: NEXTHDPLCR + - name: DBGCR + description: SBS debug control register + byte_offset: 32 + fieldset: DBGCR + - name: DBGLOCKR + description: SBS debug lock register + byte_offset: 36 + fieldset: DBGLOCKR + - name: RSSCMDR + description: SBS RSS command register + byte_offset: 52 + fieldset: RSSCMDR + - name: EPOCHSELCR + description: SBS EPOCH selection control register + byte_offset: 160 + fieldset: EPOCHSELCR + - name: SECCFGR + description: SBS security mode configuration control register + byte_offset: 192 + fieldset: SECCFGR + - name: PMCR + description: SBS product mode and configuration register + byte_offset: 256 + fieldset: PMCR + - name: FPUIMR + description: SBS FPU interrupt mask register + byte_offset: 260 + fieldset: FPUIMR + - name: MESR + description: SBS memory erase status register + byte_offset: 264 + fieldset: MESR + - name: CCCSR + description: SBS compensation cell for I/Os control and status register + byte_offset: 272 + fieldset: CCCSR + - name: CCVALR + description: SBS compensation cell for I/Os value register + byte_offset: 276 + fieldset: CCVALR + - name: CCSWCR + description: SBS compensation cell for I/Os software code register + byte_offset: 280 + fieldset: CCSWCR + - name: CFGR2 + description: SBS Class B register + byte_offset: 288 + fieldset: CFGR2 + - name: CNSLCKR + description: SBS CPU non-secure lock register + byte_offset: 324 + fieldset: CNSLCKR + - name: CSLCKR + description: SBS CPU secure lock register + byte_offset: 328 + fieldset: CSLCKR + - name: ECCNMIR + description: SBS flift ECC NMI mask register + byte_offset: 332 + fieldset: ECCNMIR fieldset/CCCSR: description: SBS compensation cell for I/Os control and status register fields: - - name: EN - description: "enable compensation cell for VDDIO power rail\r This bit enables the I/O compensation cell." - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 2 - - name: CS - description: "code selection for VDDIO power rail (reset value set to 1)\r This bit selects the code to be applied for the I/O compensation cell." - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 2 - enum: CS - - name: RDY - description: "VDDIO compensation cell ready flag\r This bit provides the status of the compensation cell." - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 + - name: EN + description: "enable compensation cell for VDDIO power rail\r This bit enables the I/O compensation cell." + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 2 + - name: CS + description: "code selection for VDDIO power rail (reset value set to 1)\r This bit selects the code to be applied for the I/O compensation cell." + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 2 + enum: CS + - name: RDY + description: "VDDIO compensation cell ready flag\r This bit provides the status of the compensation cell." + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 fieldset/CCSWCR: description: SBS compensation cell for I/Os software code register fields: - - name: SW_ANSRC1 - description: "NMOS compensation code for VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR." - bit_offset: 0 - bit_size: 4 - - name: SW_APSRC1 - description: "PMOS compensation code for the VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR." - bit_offset: 4 - bit_size: 4 - - name: SW_ANSRC2 - description: "NMOS compensation code for VDDIO power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR." - bit_offset: 8 - bit_size: 4 - - name: SW_APSRC2 - description: "PMOS compensation code for the VDDIO power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR." - bit_offset: 12 - bit_size: 4 + - name: SW_ANSRC1 + description: "NMOS compensation code for VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR." + bit_offset: 0 + bit_size: 4 + - name: SW_APSRC1 + description: "PMOS compensation code for the VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR." + bit_offset: 4 + bit_size: 4 + - name: SW_ANSRC2 + description: "NMOS compensation code for VDDIO power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR." + bit_offset: 8 + bit_size: 4 + - name: SW_APSRC2 + description: "PMOS compensation code for the VDDIO power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR." + bit_offset: 12 + bit_size: 4 fieldset/CCVALR: description: SBS compensation cell for I/Os value register fields: - - name: ANSRC1 - description: "compensation value for the NMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." - bit_offset: 0 - bit_size: 4 - - name: APSRC1 - description: "compensation value for the PMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." - bit_offset: 4 - bit_size: 4 - - name: ANSRC2 - description: "Compensation value for the NMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." - bit_offset: 8 - bit_size: 4 - - name: APSRC2 - description: "compensation value for the PMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." - bit_offset: 12 - bit_size: 4 + - name: ANSRC1 + description: "compensation value for the NMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." + bit_offset: 0 + bit_size: 4 + - name: APSRC1 + description: "compensation value for the PMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." + bit_offset: 4 + bit_size: 4 + - name: ANSRC2 + description: "Compensation value for the NMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." + bit_offset: 8 + bit_size: 4 + - name: APSRC2 + description: "compensation value for the PMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." + bit_offset: 12 + bit_size: 4 fieldset/CFGR2: description: SBS Class B register fields: - - name: CLL - description: "core lockup lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1/8/15/16/17 break inputs." - bit_offset: 0 - bit_size: 1 - - name: SEL - description: "SRAM ECC error lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM double ECC error signal with break input of TIM1/8/15/16/17." - bit_offset: 1 - bit_size: 1 - - name: PVDL - description: "PVD lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection with TIM1/8/15/16/17 break inputs." - bit_offset: 2 - bit_size: 1 - - name: ECCL - description: "ECC lock\r This bit is set and cleared by software. It can be used to enable and lock the Flash memory double ECC error with break input of TIM1/8/15/6/17." - bit_offset: 3 - bit_size: 1 + - name: CLL + description: "core lockup lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1/8/15/16/17 break inputs." + bit_offset: 0 + bit_size: 1 + - name: SEL + description: "SRAM ECC error lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM double ECC error signal with break input of TIM1/8/15/16/17." + bit_offset: 1 + bit_size: 1 + - name: PVDL + description: "PVD lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection with TIM1/8/15/16/17 break inputs." + bit_offset: 2 + bit_size: 1 + - name: ECCL + description: "ECC lock\r This bit is set and cleared by software. It can be used to enable and lock the Flash memory double ECC error with break input of TIM1/8/15/6/17." + bit_offset: 3 + bit_size: 1 fieldset/CNSLCKR: description: SBS CPU non-secure lock register fields: - - name: LOCKNSVTOR - description: "VTOR_NS register lock\r This bit is set by software and cleared only by a system reset." - bit_offset: 0 - bit_size: 1 - - name: LOCKNSMPU - description: "non-secure MPU register lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to non-secure MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers." - bit_offset: 1 - bit_size: 1 + - name: LOCKNSVTOR + description: "VTOR_NS register lock\r This bit is set by software and cleared only by a system reset." + bit_offset: 0 + bit_size: 1 + - name: LOCKNSMPU + description: "non-secure MPU register lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to non-secure MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers." + bit_offset: 1 + bit_size: 1 fieldset/CSLCKR: description: SBS CPU secure lock register fields: - - name: LOCKSVTAIRCR - description: "VTOR_S and AIRCR register lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register." - bit_offset: 0 - bit_size: 1 - - name: LOCKSMPU - description: "secure MPU registers lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers." - bit_offset: 1 - bit_size: 1 - - name: LOCKSAU - description: "SAU registers lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers." - bit_offset: 2 - bit_size: 1 + - name: LOCKSVTAIRCR + description: "VTOR_S and AIRCR register lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register." + bit_offset: 0 + bit_size: 1 + - name: LOCKSMPU + description: "secure MPU registers lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers." + bit_offset: 1 + bit_size: 1 + - name: LOCKSAU + description: "SAU registers lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers." + bit_offset: 2 + bit_size: 1 fieldset/DBGCR: description: SBS debug control register fields: - - name: AP_UNLOCK - description: "access port unlock\r Write 0xB4 to this bitfield to open the device access port." - bit_offset: 0 - bit_size: 8 - - name: DBG_UNLOCK - description: "debug unlock when DBG_AUTH_HDPL is reached\r Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register." - bit_offset: 8 - bit_size: 8 - - name: DBG_AUTH_HDPL - description: "authenticated debug temporal isolation level\r Writing to this bitfield defines at which HDPL the authenticated debug opens.\r Note: Writing any other values is ignored. Reading any other value means the debug never opens." - bit_offset: 16 - bit_size: 8 - enum: DBG_AUTH_HDPL - - name: DBG_AUTH_SEC - description: "control debug opening secure/non-secure\r Write 0xB4 to this bitfield to open debug for secure and non-secure.\r Writing any other values only open non-secure." - bit_offset: 24 - bit_size: 8 + - name: AP_UNLOCK + description: "access port unlock\r Write 0xB4 to this bitfield to open the device access port." + bit_offset: 0 + bit_size: 8 + - name: DBG_UNLOCK + description: "debug unlock when DBG_AUTH_HDPL is reached\r Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register." + bit_offset: 8 + bit_size: 8 + - name: DBG_AUTH_HDPL + description: "authenticated debug temporal isolation level\r Writing to this bitfield defines at which HDPL the authenticated debug opens.\r Note: Writing any other values is ignored. Reading any other value means the debug never opens." + bit_offset: 16 + bit_size: 8 + enum: DBG_AUTH_HDPL + - name: DBG_AUTH_SEC + description: "control debug opening secure/non-secure\r Write 0xB4 to this bitfield to open debug for secure and non-secure.\r Writing any other values only open non-secure." + bit_offset: 24 + bit_size: 8 fieldset/DBGLOCKR: description: SBS debug lock register fields: - - name: DBGCFG_LOCK - description: "debug configuration lock\r Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4.\r 0xC3 is the recommended value to lock the debug configuration using this bitfield.\r Other: Writes to SBS_DBGCR ignored" - bit_offset: 0 - bit_size: 8 - enum: DBGCFG_LOCK + - name: DBGCFG_LOCK + description: "debug configuration lock\r Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4.\r 0xC3 is the recommended value to lock the debug configuration using this bitfield.\r Other: Writes to SBS_DBGCR ignored" + bit_offset: 0 + bit_size: 8 + enum: DBGCFG_LOCK fieldset/ECCNMIR: description: SBS flift ECC NMI mask register fields: - - name: ECCNMI_MASK_EN - description: NMI behavior setup when a double ECC error occurs on flitf data part - bit_offset: 0 - bit_size: 1 + - name: ECCNMI_MASK_EN + description: NMI behavior setup when a double ECC error occurs on flitf data part + bit_offset: 0 + bit_size: 1 fieldset/EPOCHSELCR: description: SBS EPOCH selection control register fields: - - name: EPOCH_SEL - description: "select EPOCH value to be sent to the SAES\r 1x: EPOCH forced to zero (value used to retrieve PUF reference value at boot time)" - bit_offset: 0 - bit_size: 2 - enum: EPOCH_SEL + - name: EPOCH_SEL + description: "select EPOCH value to be sent to the SAES\r 1x: EPOCH forced to zero (value used to retrieve PUF reference value at boot time)" + bit_offset: 0 + bit_size: 2 + enum: EPOCH_SEL fieldset/FPUIMR: description: SBS FPU interrupt mask register fields: - - name: FPU_IE - description: "FPU interrupt enable\r Set and cleared by software to enable the Cortex-M33 FPU interrupts\r FPU_IE[5]: inexact interrupt enable (interrupt disabled at reset)\r FPU_IE[4]: input abnormal interrupt enable\r FPU_IE[3]: overflow interrupt enable\r FPU_IE[2]: underflow interrupt enable\r FPU_IE[1]: divide-by-zero interrupt enable\r FPU_IE[0]: invalid operation interrupt enable" - bit_offset: 0 - bit_size: 6 + - name: FPU_IE + description: "FPU interrupt enable\r Set and cleared by software to enable the Cortex-M33 FPU interrupts\r FPU_IE[5]: inexact interrupt enable (interrupt disabled at reset)\r FPU_IE[4]: input abnormal interrupt enable\r FPU_IE[3]: overflow interrupt enable\r FPU_IE[2]: underflow interrupt enable\r FPU_IE[1]: divide-by-zero interrupt enable\r FPU_IE[0]: invalid operation interrupt enable" + bit_offset: 0 + bit_size: 6 fieldset/HDPLCR: description: SBS temporal isolation control register fields: - - name: INCR_HDPL - description: "increment HDPL value\r Other: all other values allow a HDPL level increment." - bit_offset: 0 - bit_size: 8 - enum: INCR_HDPL + - name: INCR_HDPL + description: "increment HDPL value\r Other: all other values allow a HDPL level increment." + bit_offset: 0 + bit_size: 8 + enum: INCR_HDPL fieldset/HDPLSR: description: SBS temporal isolation status register fields: - - name: HDPL - description: "temporal isolation level\r This bitfield returns the current temporal isolation level." - bit_offset: 0 - bit_size: 8 - enum: HDPL + - name: HDPL + description: "temporal isolation level\r This bitfield returns the current temporal isolation level." + bit_offset: 0 + bit_size: 8 + enum: HDPL fieldset/MESR: description: SBS memory erase status register fields: - - name: MCLR - description: "erase after reset status\r This bit shows the status of the protection for SRAM2, BKPRAM, ICACHE, DCACHE, ICACHE and PKA. It is set by hardware and reset by software" - bit_offset: 0 - bit_size: 1 - - name: IPMEE - description: "end-of-erase status for ICACHE and PKA RAM\r This bit shows the status of the protection for ICACHE and PKA. It is set by hardware and reset by software." - bit_offset: 16 - bit_size: 1 + - name: MCLR + description: "erase after reset status\r This bit shows the status of the protection for SRAM2, BKPRAM, ICACHE, DCACHE, ICACHE and PKA. It is set by hardware and reset by software" + bit_offset: 0 + bit_size: 1 + - name: IPMEE + description: "end-of-erase status for ICACHE and PKA RAM\r This bit shows the status of the protection for ICACHE and PKA. It is set by hardware and reset by software." + bit_offset: 16 + bit_size: 1 fieldset/NEXTHDPLCR: description: SBS next HDPL control register fields: - - name: NEXTHDPL - description: "index to point to a higher HDPL than the current one\r Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas (OBK-HDPL = HDPL + NEXTHDPL). See for more details." - bit_offset: 0 - bit_size: 2 + - name: NEXTHDPL + description: "index to point to a higher HDPL than the current one\r Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas (OBK-HDPL = HDPL + NEXTHDPL). See for more details." + bit_offset: 0 + bit_size: 2 fieldset/PMCR: description: SBS product mode and configuration register fields: - - name: BOOSTEN - description: "booster enable\r Set this bit to reduce the total harmonic distortion of the analog switch when the processor supply is below 2.7 V. The booster can be activated to guaranty AC performance on analog switch when the supply is below 2.7 V. When the booster is activated, the analog switch performances are the same as with the full voltage range." - bit_offset: 8 - bit_size: 1 - - name: BOOSTVDDSEL - description: "booster VDD selection\r Note: Booster must not be used when VDDA < 2.7 V, but VDD > 2.7 V (add current consumption).\r When both VDD < 2.7 V and VDDA < 2.7 V, booster is needed to get full AC performances from I/O analog switches." - bit_offset: 9 - bit_size: 1 - - name: PB6_FMPLUS - description: Fast-mode Plus command on PB(6) - bit_offset: 16 - bit_size: 1 - - name: PB7_FMPLUS - description: Fast-mode Plus command on PB(7) - bit_offset: 17 - bit_size: 1 - - name: PB8_FMPLUS - description: Fast-mode Plus command on PB(8) - bit_offset: 18 - bit_size: 1 - - name: PB9_FMPLUS - description: Fast-mode Plus command on PB(9) - bit_offset: 19 - bit_size: 1 - - name: ETH_SEL_PHY - description: "Ethernet PHY interface selection\r Other: reserved" - bit_offset: 21 - bit_size: 3 - enum: ETH_SEL_PHY + - name: BOOSTEN + description: "booster enable\r Set this bit to reduce the total harmonic distortion of the analog switch when the processor supply is below 2.7 V. The booster can be activated to guaranty AC performance on analog switch when the supply is below 2.7 V. When the booster is activated, the analog switch performances are the same as with the full voltage range." + bit_offset: 8 + bit_size: 1 + - name: BOOSTVDDSEL + description: "booster VDD selection\r Note: Booster must not be used when VDDA < 2.7 V, but VDD > 2.7 V (add current consumption).\r When both VDD < 2.7 V and VDDA < 2.7 V, booster is needed to get full AC performances from I/O analog switches." + bit_offset: 9 + bit_size: 1 + - name: PB6_FMPLUS + description: Fast-mode Plus command on PB(6) + bit_offset: 16 + bit_size: 1 + - name: PB7_FMPLUS + description: Fast-mode Plus command on PB(7) + bit_offset: 17 + bit_size: 1 + - name: PB8_FMPLUS + description: Fast-mode Plus command on PB(8) + bit_offset: 18 + bit_size: 1 + - name: PB9_FMPLUS + description: Fast-mode Plus command on PB(9) + bit_offset: 19 + bit_size: 1 + - name: ETH_SEL_PHY + description: "Ethernet PHY interface selection\r Other: reserved" + bit_offset: 21 + bit_size: 3 + enum: ETH_SEL_PHY fieldset/RSSCMDR: description: SBS RSS command register fields: - - name: RSSCMD - description: "RSS command\r The application can use this bitfield to pass on a command to the RSS, executed at the next reset.\r When RSSCMD ≠ 0 and PRODUCT_STATE is in Open, then the system always boots on RSS whatever is the boot pin value." - bit_offset: 0 - bit_size: 16 + - name: RSSCMD + description: "RSS command\r The application can use this bitfield to pass on a command to the RSS, executed at the next reset.\r When RSSCMD ≠ 0 and PRODUCT_STATE is in Open, then the system always boots on RSS whatever is the boot pin value." + bit_offset: 0 + bit_size: 16 fieldset/SECCFGR: description: SBS security mode configuration control register fields: - - name: SBSSEC - description: "SBS clock control, memory-erase status register and compensation cell register security enable" - bit_offset: 0 - bit_size: 1 - enum: SEC - - name: CLASSBSEC - description: ClassB security enable - bit_offset: 1 - bit_size: 1 - enum: SEC - - name: FPUSEC - description: "FPU security enable\r Note: This bit can only be written through privilege transaction." - bit_offset: 3 - bit_size: 1 - enum: SEC - - name: SDCE_SEC_EN - description: control accessibility of SMPS_DIV_CLOCK _EN in SBS_PMCR - bit_offset: 31 - bit_size: 1 + - name: SBSSEC + description: SBS clock control, memory-erase status register and compensation cell register security enable + bit_offset: 0 + bit_size: 1 + enum: SEC + - name: CLASSBSEC + description: ClassB security enable + bit_offset: 1 + bit_size: 1 + enum: SEC + - name: FPUSEC + description: "FPU security enable\r Note: This bit can only be written through privilege transaction." + bit_offset: 3 + bit_size: 1 + enum: SEC + - name: SDCE_SEC_EN + description: control accessibility of SMPS_DIV_CLOCK _EN in SBS_PMCR + bit_offset: 31 + bit_size: 1 enum/CS: bit_size: 1 variants: - - name: Cell - description: Code from the cell (available in the SBS_CCVR) - value: 0 - - name: Software - description: Code from SBS_CCCR - value: 1 + - name: Cell + description: Code from the cell (available in the SBS_CCVR) + value: 0 + - name: Software + description: Code from SBS_CCCR + value: 1 enum/DBGCFG_LOCK: bit_size: 8 variants: - - name: B_0xB4 - description: Writes to SBS_DBGCR allowed (default) - value: 180 + - name: B_0xB4 + description: Writes to SBS_DBGCR allowed (default) + value: 180 enum/DBG_AUTH_HDPL: bit_size: 8 variants: - - name: B_0x51 - description: HDPL1 - value: 81 - - name: B_0x6F - description: HDPL3 - value: 111 - - name: B_0x8A - description: HDPL2 - value: 138 + - name: B_0x51 + description: HDPL1 + value: 81 + - name: B_0x6F + description: HDPL3 + value: 111 + - name: B_0x8A + description: HDPL2 + value: 138 enum/EPOCH_SEL: bit_size: 2 variants: - - name: B_0x0 - description: SEC_EPOCH counter input selected - value: 0 - - name: B_0x1 - description: NS_EPOCH (non-secure) input selected - value: 1 + - name: B_0x0 + description: SEC_EPOCH counter input selected + value: 0 + - name: B_0x1 + description: NS_EPOCH (non-secure) input selected + value: 1 enum/ETH_SEL_PHY: bit_size: 3 variants: - - name: B_0x0 - description: GMII or MII - value: 0 - - name: B_0x1 - description: reserved (RGMII) - value: 1 - - name: B_0x4 - description: RMII - value: 4 + - name: B_0x0 + description: GMII or MII + value: 0 + - name: B_0x1 + description: reserved (RGMII) + value: 1 + - name: B_0x4 + description: RMII + value: 4 enum/HDPL: bit_size: 8 variants: - - name: B_0x51 - description: "HDPL1, iRoT" - value: 81 - - name: B_0x6F - description: "HDPL3, application (secure/non-secure)" - value: 111 - - name: B_0x8A - description: "HDPL2, uRoT" - value: 138 - - name: B_0xB4 - description: "HDPL0, RSS" - value: 180 + - name: B_0x51 + description: HDPL1, iRoT + value: 81 + - name: B_0x6F + description: HDPL3, application (secure/non-secure) + value: 111 + - name: B_0x8A + description: HDPL2, uRoT + value: 138 + - name: B_0xB4 + description: HDPL0, RSS + value: 180 enum/INCR_HDPL: bit_size: 8 variants: - - name: B_0x6A - description: recommended value to increment HDPL level by one - value: 106 - - name: B_0xB4 - description: no increment - value: 180 + - name: B_0x6A + description: recommended value to increment HDPL level by one + value: 106 + - name: B_0xB4 + description: no increment + value: 180 enum/SEC: bit_size: 1 variants: - - name: B_0x0 - description: SBS_CFGR2 register accessible through secure or non-secure transaction - value: 0 - - name: B_0x1 - description: SBS_CFGR2 register only accessible through secure transaction - value: 1 + - name: B_0x0 + description: SBS_CFGR2 register accessible through secure or non-secure transaction + value: 0 + - name: B_0x1 + description: SBS_CFGR2 register only accessible through secure transaction + value: 1 diff --git a/data/registers/sbs_h50.yaml b/data/registers/sbs_h50.yaml index 777043e..8328357 100644 --- a/data/registers/sbs_h50.yaml +++ b/data/registers/sbs_h50.yaml @@ -1,288 +1,287 @@ ---- block/SBS: - description: "System configuration, boot and security" + description: System configuration, boot and security items: - - name: HDPLCR - description: SBS temporal isolation control register - byte_offset: 16 - fieldset: HDPLCR - - name: HDPLSR - description: SBS temporal isolation status register - byte_offset: 20 - fieldset: HDPLSR - - name: DBGCR - description: SBS debug control register - byte_offset: 32 - fieldset: DBGCR - - name: DBGLOCKR - description: SBS debug lock register - byte_offset: 36 - fieldset: DBGLOCKR - - name: PMCR - description: SBS product mode and configuration register - byte_offset: 256 - fieldset: PMCR - - name: FPUIMR - description: SBS FPU interrupt mask register - byte_offset: 260 - fieldset: FPUIMR - - name: MESR - description: SBS memory erase status register - byte_offset: 264 - fieldset: MESR - - name: CCCSR - description: SBS compensation cell for I/Os control and status register - byte_offset: 272 - fieldset: CCCSR - - name: CCVALR - description: SBS compensation cell for I/Os value register - byte_offset: 276 - fieldset: CCVALR - - name: CCSWCR - description: SBS compensation cell for I/Os software code register - byte_offset: 280 - fieldset: CCSWCR - - name: CFGR2 - description: SBS Class B register - byte_offset: 288 - fieldset: CFGR2 - - name: CNSLCKR - description: SBS CPU lock register - byte_offset: 324 - fieldset: CNSLCKR - - name: ECCNMIR - description: SBS flift ECC NMI mask register - byte_offset: 332 - fieldset: ECCNMIR + - name: HDPLCR + description: SBS temporal isolation control register + byte_offset: 16 + fieldset: HDPLCR + - name: HDPLSR + description: SBS temporal isolation status register + byte_offset: 20 + fieldset: HDPLSR + - name: DBGCR + description: SBS debug control register + byte_offset: 32 + fieldset: DBGCR + - name: DBGLOCKR + description: SBS debug lock register + byte_offset: 36 + fieldset: DBGLOCKR + - name: PMCR + description: SBS product mode and configuration register + byte_offset: 256 + fieldset: PMCR + - name: FPUIMR + description: SBS FPU interrupt mask register + byte_offset: 260 + fieldset: FPUIMR + - name: MESR + description: SBS memory erase status register + byte_offset: 264 + fieldset: MESR + - name: CCCSR + description: SBS compensation cell for I/Os control and status register + byte_offset: 272 + fieldset: CCCSR + - name: CCVALR + description: SBS compensation cell for I/Os value register + byte_offset: 276 + fieldset: CCVALR + - name: CCSWCR + description: SBS compensation cell for I/Os software code register + byte_offset: 280 + fieldset: CCSWCR + - name: CFGR2 + description: SBS Class B register + byte_offset: 288 + fieldset: CFGR2 + - name: CNSLCKR + description: SBS CPU lock register + byte_offset: 324 + fieldset: CNSLCKR + - name: ECCNMIR + description: SBS flift ECC NMI mask register + byte_offset: 332 + fieldset: ECCNMIR fieldset/CCCSR: description: SBS compensation cell for I/Os control and status register fields: - - name: EN - description: "enable compensation cell for VDDIO power rail\r This bit enables the I/O compensation cell." - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 2 - - name: CS - description: "code selection for VDDIO power rail (reset value set to 1)\r This bit selects the code to be applied for the I/O compensation cell." - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 2 - enum: CS - - name: RDY - description: "VDDIO compensation cell ready flag\r This bit provides the status of the compensation cell." - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 + - name: EN + description: "enable compensation cell for VDDIO power rail\r This bit enables the I/O compensation cell." + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 2 + - name: CS + description: "code selection for VDDIO power rail (reset value set to 1)\r This bit selects the code to be applied for the I/O compensation cell." + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 2 + enum: CS + - name: RDY + description: "VDDIO compensation cell ready flag\r This bit provides the status of the compensation cell." + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 fieldset/CCSWCR: description: SBS compensation cell for I/Os software code register fields: - - name: SW_ANSRC1 - description: "NMOS compensation code for VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR." - bit_offset: 0 - bit_size: 4 - - name: SW_APSRC1 - description: "PMOS compensation code for the VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR." - bit_offset: 4 - bit_size: 4 - - name: SW_ANSRC2 - description: "NMOS compensation code for VDDIO power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR." - bit_offset: 8 - bit_size: 4 - - name: SW_APSRC2 - description: "PMOS compensation code for the VDDIO power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR." - bit_offset: 12 - bit_size: 4 + - name: SW_ANSRC1 + description: "NMOS compensation code for VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR." + bit_offset: 0 + bit_size: 4 + - name: SW_APSRC1 + description: "PMOS compensation code for the VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR." + bit_offset: 4 + bit_size: 4 + - name: SW_ANSRC2 + description: "NMOS compensation code for VDDIO power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR." + bit_offset: 8 + bit_size: 4 + - name: SW_APSRC2 + description: "PMOS compensation code for the VDDIO power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR." + bit_offset: 12 + bit_size: 4 fieldset/CCVALR: description: SBS compensation cell for I/Os value register fields: - - name: ANSRC1 - description: "compensation value for the NMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." - bit_offset: 0 - bit_size: 4 - - name: APSRC1 - description: "compensation value for the PMOS transistor \r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." - bit_offset: 4 - bit_size: 4 - - name: ANSRC2 - description: "Compensation value for the NMOS transistor \r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." - bit_offset: 8 - bit_size: 4 - - name: APSRC2 - description: "compensation value for the PMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." - bit_offset: 12 - bit_size: 4 + - name: ANSRC1 + description: "compensation value for the NMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." + bit_offset: 0 + bit_size: 4 + - name: APSRC1 + description: "compensation value for the PMOS transistor \r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." + bit_offset: 4 + bit_size: 4 + - name: ANSRC2 + description: "Compensation value for the NMOS transistor \r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." + bit_offset: 8 + bit_size: 4 + - name: APSRC2 + description: "compensation value for the PMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." + bit_offset: 12 + bit_size: 4 fieldset/CFGR2: description: SBS Class B register fields: - - name: CLL - description: "core lockup lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1 break inputs." - bit_offset: 0 - bit_size: 1 - - name: SEL - description: "SRAM ECC error lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM double ECC error signal with break input of TIM1." - bit_offset: 1 - bit_size: 1 - - name: PVDL - description: "PVD lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection with TIM1 break inputs." - bit_offset: 2 - bit_size: 1 - - name: ECCL - description: "ECC lock\r This bit is set and cleared by software. It can be used to enable and lock the Flash memory double ECC error with break input of TIM1." - bit_offset: 3 - bit_size: 1 + - name: CLL + description: "core lockup lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1 break inputs." + bit_offset: 0 + bit_size: 1 + - name: SEL + description: "SRAM ECC error lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM double ECC error signal with break input of TIM1." + bit_offset: 1 + bit_size: 1 + - name: PVDL + description: "PVD lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection with TIM1 break inputs." + bit_offset: 2 + bit_size: 1 + - name: ECCL + description: "ECC lock\r This bit is set and cleared by software. It can be used to enable and lock the Flash memory double ECC error with break input of TIM1." + bit_offset: 3 + bit_size: 1 fieldset/CNSLCKR: description: SBS CPU lock register fields: - - name: LOCKNSVTOR - description: "VTOR_NS register lock\r This bit is set by software and cleared only by a system reset." - bit_offset: 0 - bit_size: 1 - - name: LOCKNSMPU - description: "MPU register lock \r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers." - bit_offset: 1 - bit_size: 1 + - name: LOCKNSVTOR + description: "VTOR_NS register lock\r This bit is set by software and cleared only by a system reset." + bit_offset: 0 + bit_size: 1 + - name: LOCKNSMPU + description: "MPU register lock \r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers." + bit_offset: 1 + bit_size: 1 fieldset/DBGCR: description: SBS debug control register fields: - - name: AP_UNLOCK - description: "access port unlock\r Write 0xB4 to this bitfield to open the device access port." - bit_offset: 0 - bit_size: 8 - - name: DBG_UNLOCK - description: "debug unlock when DBG_AUTH_HDPL is reached\r Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register." - bit_offset: 8 - bit_size: 8 - - name: DBG_AUTH_HDPL - description: "authenticated debug temporal isolation level\r Writing to this bitfield defines at which HDPL the authenticated debug opens.\r Note: Writing any other values is ignored. Reading any other value means the debug never opens." - bit_offset: 16 - bit_size: 8 - enum: DBG_AUTH_HDPL + - name: AP_UNLOCK + description: "access port unlock\r Write 0xB4 to this bitfield to open the device access port." + bit_offset: 0 + bit_size: 8 + - name: DBG_UNLOCK + description: "debug unlock when DBG_AUTH_HDPL is reached\r Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register." + bit_offset: 8 + bit_size: 8 + - name: DBG_AUTH_HDPL + description: "authenticated debug temporal isolation level\r Writing to this bitfield defines at which HDPL the authenticated debug opens.\r Note: Writing any other values is ignored. Reading any other value means the debug never opens." + bit_offset: 16 + bit_size: 8 + enum: DBG_AUTH_HDPL fieldset/DBGLOCKR: description: SBS debug lock register fields: - - name: DBGCFG_LOCK - description: "debug configuration lock\r Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4.\r 0xC3 is the recommended value to lock the debug configuration using this bitfield.\r Other: Writes to SBS_DBGCR ignored" - bit_offset: 0 - bit_size: 8 - enum: DBGCFG_LOCK + - name: DBGCFG_LOCK + description: "debug configuration lock\r Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4.\r 0xC3 is the recommended value to lock the debug configuration using this bitfield.\r Other: Writes to SBS_DBGCR ignored" + bit_offset: 0 + bit_size: 8 + enum: DBGCFG_LOCK fieldset/ECCNMIR: description: SBS flift ECC NMI mask register fields: - - name: ECCNMI_MASK_EN - description: NMI behavior setup when a double ECC error occurs on flitf data part - bit_offset: 0 - bit_size: 1 + - name: ECCNMI_MASK_EN + description: NMI behavior setup when a double ECC error occurs on flitf data part + bit_offset: 0 + bit_size: 1 fieldset/FPUIMR: description: SBS FPU interrupt mask register fields: - - name: FPU_IE - description: "FPU interrupt enable\r Set and cleared by software to enable the Cortex-M33 FPU interrupts\r FPU_IE[5]: inexact interrupt enable (interrupt disabled at reset)\r FPU_IE[4]: input abnormal interrupt enable\r FPU_IE[3]: overflow interrupt enable\r FPU_IE[2]: underflow interrupt enable\r FPU_IE[1]: divide-by-zero interrupt enable\r FPU_IE[0]: invalid operation interrupt enable" - bit_offset: 0 - bit_size: 6 + - name: FPU_IE + description: "FPU interrupt enable\r Set and cleared by software to enable the Cortex-M33 FPU interrupts\r FPU_IE[5]: inexact interrupt enable (interrupt disabled at reset)\r FPU_IE[4]: input abnormal interrupt enable\r FPU_IE[3]: overflow interrupt enable\r FPU_IE[2]: underflow interrupt enable\r FPU_IE[1]: divide-by-zero interrupt enable\r FPU_IE[0]: invalid operation interrupt enable" + bit_offset: 0 + bit_size: 6 fieldset/HDPLCR: description: SBS temporal isolation control register fields: - - name: INCR_HDPL - description: "increment HDPL value\r Other: all other values allow a HDPL level increment." - bit_offset: 0 - bit_size: 8 - enum: INCR_HDPL + - name: INCR_HDPL + description: "increment HDPL value\r Other: all other values allow a HDPL level increment." + bit_offset: 0 + bit_size: 8 + enum: INCR_HDPL fieldset/HDPLSR: description: SBS temporal isolation status register fields: - - name: HDPL - description: "temporal isolation level\r This bitfield returns the current temporal isolation level." - bit_offset: 0 - bit_size: 8 - enum: HDPL + - name: HDPL + description: "temporal isolation level\r This bitfield returns the current temporal isolation level." + bit_offset: 0 + bit_size: 8 + enum: HDPL fieldset/MESR: description: SBS memory erase status register fields: - - name: MCLR - description: "erase after reset status\r This bit shows the status of the protection for SRAM2, BKPRAM, ICACHE, ICACHE. It is set by hardware and reset by software" - bit_offset: 0 - bit_size: 1 - - name: IPMEE - description: "end-of-erase status for ICACHE\r This bit shows the status of the protection for ICACHE. It is set by hardware and reset by software." - bit_offset: 16 - bit_size: 1 + - name: MCLR + description: "erase after reset status\r This bit shows the status of the protection for SRAM2, BKPRAM, ICACHE, ICACHE. It is set by hardware and reset by software" + bit_offset: 0 + bit_size: 1 + - name: IPMEE + description: "end-of-erase status for ICACHE\r This bit shows the status of the protection for ICACHE. It is set by hardware and reset by software." + bit_offset: 16 + bit_size: 1 fieldset/PMCR: description: SBS product mode and configuration register fields: - - name: BOOSTEN - description: "booster enable\r Set this bit to reduce the total harmonic distortion of the analog switch when the processor supply is below 2.7 V. The booster can be activated to guaranty AC performance on analog switch when the supply is below 2.7 V. When the booster is activated, the analog switch performances are the same as with the full voltage range." - bit_offset: 8 - bit_size: 1 - - name: BOOSTVDDSEL - description: "booster VDD selection\r Note: Booster must not be used when VDDA < 2.7 V, but VDD > 2.7 V (add current consumption).\r Note: When both VDD < 2.7 V and VDDA < 2.7 V, booster is needed to get full AC performances from I/O analog switches." - bit_offset: 9 - bit_size: 1 - - name: PB6_FMPLUS - description: Fast-mode Plus command on PB(6) - bit_offset: 16 - bit_size: 1 - - name: PB7_FMPLUS - description: Fast-mode Plus command on PB(7) - bit_offset: 17 - bit_size: 1 - - name: PB8_FMPLUS - description: Fast-mode Plus command on PB(8) - bit_offset: 18 - bit_size: 1 + - name: BOOSTEN + description: "booster enable\r Set this bit to reduce the total harmonic distortion of the analog switch when the processor supply is below 2.7 V. The booster can be activated to guaranty AC performance on analog switch when the supply is below 2.7 V. When the booster is activated, the analog switch performances are the same as with the full voltage range." + bit_offset: 8 + bit_size: 1 + - name: BOOSTVDDSEL + description: "booster VDD selection\r Note: Booster must not be used when VDDA < 2.7 V, but VDD > 2.7 V (add current consumption).\r Note: When both VDD < 2.7 V and VDDA < 2.7 V, booster is needed to get full AC performances from I/O analog switches." + bit_offset: 9 + bit_size: 1 + - name: PB6_FMPLUS + description: Fast-mode Plus command on PB(6) + bit_offset: 16 + bit_size: 1 + - name: PB7_FMPLUS + description: Fast-mode Plus command on PB(7) + bit_offset: 17 + bit_size: 1 + - name: PB8_FMPLUS + description: Fast-mode Plus command on PB(8) + bit_offset: 18 + bit_size: 1 enum/CS: bit_size: 1 variants: - - name: Cell - description: Code from the cell (available in SBS_CCVR) - value: 0 - - name: Software - description: Code from SBS_CCCR - value: 1 + - name: Cell + description: Code from the cell (available in SBS_CCVR) + value: 0 + - name: Software + description: Code from SBS_CCCR + value: 1 enum/DBGCFG_LOCK: bit_size: 8 variants: - - name: B_0xB4 - description: Writes to SBS_DBGCR allowed (default) - value: 180 + - name: B_0xB4 + description: Writes to SBS_DBGCR allowed (default) + value: 180 enum/DBG_AUTH_HDPL: bit_size: 8 variants: - - name: B_0x51 - description: HDPL1 - value: 81 - - name: B_0x6F - description: HDPL3 - value: 111 - - name: B_0x8A - description: HDPL2 - value: 138 + - name: B_0x51 + description: HDPL1 + value: 81 + - name: B_0x6F + description: HDPL3 + value: 111 + - name: B_0x8A + description: HDPL2 + value: 138 enum/HDPL: bit_size: 8 variants: - - name: B_0x51 - description: "HDPL1, iRoT" - value: 81 - - name: B_0x6F - description: "HDPL3, application" - value: 111 - - name: B_0x8A - description: "HDPL2, uRoT" - value: 138 - - name: B_0xB4 - description: "HDPL0, RSS" - value: 180 + - name: B_0x51 + description: HDPL1, iRoT + value: 81 + - name: B_0x6F + description: HDPL3, application + value: 111 + - name: B_0x8A + description: HDPL2, uRoT + value: 138 + - name: B_0xB4 + description: HDPL0, RSS + value: 180 enum/INCR_HDPL: bit_size: 8 variants: - - name: B_0x6A - description: recommended value to increment HDPL level by one - value: 106 - - name: B_0xB4 - description: no increment - value: 180 + - name: B_0x6A + description: recommended value to increment HDPL level by one + value: 106 + - name: B_0xB4 + description: no increment + value: 180 diff --git a/data/registers/sdmmc_v1.yaml b/data/registers/sdmmc_v1.yaml index 8841d50..72e5810 100644 --- a/data/registers/sdmmc_v1.yaml +++ b/data/registers/sdmmc_v1.yaml @@ -1,482 +1,493 @@ ---- block/SDMMC: description: Secure digital input/output interface items: - - name: POWER - description: power control register - byte_offset: 0 - fieldset: POWER - - name: CLKCR - description: SDI clock control register - byte_offset: 4 - fieldset: CLKCR - - name: ARGR - description: argument register - byte_offset: 8 - fieldset: ARGR - - name: CMDR - description: command register - byte_offset: 12 - fieldset: CMDR - - name: RESPCMDR - description: command response register - byte_offset: 16 - access: Read - fieldset: RESPCMDR - - name: RESPR - description: response 1..4 register - array: - len: 4 - stride: 4 - byte_offset: 20 - access: Read - fieldset: RESP1R - - name: DTIMER - description: data timer register - byte_offset: 36 - fieldset: DTIMER - - name: DLENR - description: data length register - byte_offset: 40 - fieldset: DLENR - - name: DCTRL - description: data control register - byte_offset: 44 - fieldset: DCTRL - - name: DCNTR - description: data counter register - byte_offset: 48 - access: Read - fieldset: DCNTR - - name: STAR - description: status register - byte_offset: 52 - access: Read - fieldset: STAR - - name: ICR - description: interrupt clear register - byte_offset: 56 - fieldset: ICR - - name: MASKR - description: mask register - byte_offset: 60 - fieldset: MASKR - - name: FIFOCNT - description: FIFO counter register - byte_offset: 72 - access: Read - fieldset: FIFOCNT - - name: FIFOR - description: data FIFO register - byte_offset: 128 - fieldset: FIFOR + - name: POWER + description: power control register + byte_offset: 0 + fieldset: POWER + - name: CLKCR + description: SDI clock control register + byte_offset: 4 + fieldset: CLKCR + - name: ARGR + description: argument register + byte_offset: 8 + fieldset: ARGR + - name: CMDR + description: command register + byte_offset: 12 + fieldset: CMDR + - name: RESPCMDR + description: command response register + byte_offset: 16 + access: Read + fieldset: RESPCMDR + - name: RESPR + description: response 1..4 register + array: + len: 4 + stride: 4 + byte_offset: 20 + access: Read + fieldset: RESP1R + - name: DTIMER + description: data timer register + byte_offset: 36 + fieldset: DTIMER + - name: DLENR + description: data length register + byte_offset: 40 + fieldset: DLENR + - name: DCTRL + description: data control register + byte_offset: 44 + fieldset: DCTRL + - name: DCNTR + description: data counter register + byte_offset: 48 + access: Read + fieldset: DCNTR + - name: STAR + description: status register + byte_offset: 52 + access: Read + fieldset: STAR + - name: ICR + description: interrupt clear register + byte_offset: 56 + fieldset: ICR + - name: MASKR + description: mask register + byte_offset: 60 + fieldset: MASKR + - name: FIFOCNT + description: FIFO counter register + byte_offset: 72 + access: Read + fieldset: FIFOCNT + - name: FIFOR + description: data FIFO register + byte_offset: 128 + fieldset: FIFOR fieldset/ARGR: description: argument register fields: - - name: CMDARG - description: Command argument - bit_offset: 0 - bit_size: 32 + - name: CMDARG + description: Command argument + bit_offset: 0 + bit_size: 32 fieldset/CLKCR: description: SDI clock control register fields: - - name: CLKDIV - description: Clock divide factor - bit_offset: 0 - bit_size: 8 - - name: CLKEN - description: Clock enable bit - bit_offset: 8 - bit_size: 1 - - name: PWRSAV - description: Power saving configuration bit - bit_offset: 9 - bit_size: 1 - - name: BYPASS - description: Clock divider bypass enable bit - bit_offset: 10 - bit_size: 1 - - name: WIDBUS - description: Wide bus mode enable bit - bit_offset: 11 - bit_size: 2 - - name: NEGEDGE - description: SDIO_CK dephasing selection bit - bit_offset: 13 - bit_size: 1 - - name: HWFC_EN - description: HW Flow Control enable - bit_offset: 14 - bit_size: 1 + - name: CLKDIV + description: Clock divide factor + bit_offset: 0 + bit_size: 8 + - name: CLKEN + description: Clock enable bit + bit_offset: 8 + bit_size: 1 + - name: PWRSAV + description: Power saving configuration bit + bit_offset: 9 + bit_size: 1 + - name: BYPASS + description: Clock divider bypass enable bit + bit_offset: 10 + bit_size: 1 + - name: WIDBUS + description: Wide bus mode enable bit + bit_offset: 11 + bit_size: 2 + - name: NEGEDGE + description: SDIO_CK dephasing selection bit + bit_offset: 13 + bit_size: 1 + - name: HWFC_EN + description: HW Flow Control enable + bit_offset: 14 + bit_size: 1 fieldset/CMDR: description: command register fields: - - name: CMDINDEX - description: Command index - bit_offset: 0 - bit_size: 6 - - name: WAITRESP - description: Wait for response bits - bit_offset: 6 - bit_size: 2 - - name: WAITINT - description: CPSM waits for interrupt request - bit_offset: 8 - bit_size: 1 - - name: WAITPEND - description: CPSM Waits for ends of data transfer (CmdPend internal signal) - bit_offset: 9 - bit_size: 1 - - name: CPSMEN - description: Command path state machine (CPSM) Enable bit - bit_offset: 10 - bit_size: 1 - - name: SDIOSuspend - description: SD I/O suspend command - bit_offset: 11 - bit_size: 1 + - name: CMDINDEX + description: Command index + bit_offset: 0 + bit_size: 6 + - name: WAITRESP + description: Wait for response bits + bit_offset: 6 + bit_size: 2 + - name: WAITINT + description: CPSM waits for interrupt request + bit_offset: 8 + bit_size: 1 + - name: WAITPEND + description: CPSM Waits for ends of data transfer (CmdPend internal signal) + bit_offset: 9 + bit_size: 1 + - name: CPSMEN + description: Command path state machine (CPSM) Enable bit + bit_offset: 10 + bit_size: 1 + - name: SDIOSuspend + description: SD I/O suspend command + bit_offset: 11 + bit_size: 1 fieldset/DCNTR: description: data counter register fields: - - name: DATACOUNT - description: Data count value - bit_offset: 0 - bit_size: 25 + - name: DATACOUNT + description: Data count value + bit_offset: 0 + bit_size: 25 fieldset/DCTRL: description: data control register fields: - - name: DTEN - description: DTEN - bit_offset: 0 - bit_size: 1 - - name: DTDIR - description: Data transfer direction selection - bit_offset: 1 - bit_size: 1 - - name: DTMODE - description: "Data transfer mode selection 1: Stream or SDIO multibyte data transfer" - bit_offset: 2 - bit_size: 1 - - name: DMAEN - description: DMA enable bit - bit_offset: 3 - bit_size: 1 - - name: DBLOCKSIZE - description: Data block size - bit_offset: 4 - bit_size: 4 - - name: RWSTART - description: Read wait start - bit_offset: 8 - bit_size: 1 - - name: RWSTOP - description: Read wait stop - bit_offset: 9 - bit_size: 1 - - name: RWMOD - description: Read wait mode - bit_offset: 10 - bit_size: 1 - - name: SDIOEN - description: SD I/O enable functions - bit_offset: 11 - bit_size: 1 + - name: DTEN + description: DTEN + bit_offset: 0 + bit_size: 1 + - name: DTDIR + description: Data transfer direction selection + bit_offset: 1 + bit_size: 1 + - name: DTMODE + description: 'Data transfer mode selection 1: Stream or SDIO multibyte data transfer' + bit_offset: 2 + bit_size: 1 + - name: DMAEN + description: DMA enable bit + bit_offset: 3 + bit_size: 1 + - name: DBLOCKSIZE + description: Data block size + bit_offset: 4 + bit_size: 4 + - name: RWSTART + description: Read wait start + bit_offset: 8 + bit_size: 1 + - name: RWSTOP + description: Read wait stop + bit_offset: 9 + bit_size: 1 + - name: RWMOD + description: Read wait mode + bit_offset: 10 + bit_size: 1 + - name: SDIOEN + description: SD I/O enable functions + bit_offset: 11 + bit_size: 1 fieldset/DLENR: description: data length register fields: - - name: DATALENGTH - description: Data length value - bit_offset: 0 - bit_size: 25 + - name: DATALENGTH + description: Data length value + bit_offset: 0 + bit_size: 25 fieldset/DTIMER: description: data timer register fields: - - name: DATATIME - description: Data timeout period - bit_offset: 0 - bit_size: 32 + - name: DATATIME + description: Data timeout period + bit_offset: 0 + bit_size: 32 fieldset/FIFOCNT: description: FIFO counter register fields: - - name: FIFOCOUNT - description: Remaining number of words to be written to or read from the FIFO - bit_offset: 0 - bit_size: 24 + - name: FIFOCOUNT + description: Remaining number of words to be written to or read from the FIFO + bit_offset: 0 + bit_size: 24 fieldset/FIFOR: description: data FIFO register fields: - - name: FIFOData - description: Receive and transmit FIFO data - bit_offset: 0 - bit_size: 32 + - name: FIFOData + description: Receive and transmit FIFO data + bit_offset: 0 + bit_size: 32 fieldset/ICR: description: interrupt clear register fields: - - name: CCRCFAILC - description: CCRCFAIL flag clear bit - bit_offset: 0 - bit_size: 1 - - name: DCRCFAILC - description: DCRCFAIL flag clear bit - bit_offset: 1 - bit_size: 1 - - name: CTIMEOUTC - description: CTIMEOUT flag clear bit - bit_offset: 2 - bit_size: 1 - - name: DTIMEOUTC - description: DTIMEOUT flag clear bit - bit_offset: 3 - bit_size: 1 - - name: TXUNDERRC - description: TXUNDERR flag clear bit - bit_offset: 4 - bit_size: 1 - - name: RXOVERRC - description: RXOVERR flag clear bit - bit_offset: 5 - bit_size: 1 - - name: CMDRENDC - description: CMDREND flag clear bit - bit_offset: 6 - bit_size: 1 - - name: CMDSENTC - description: CMDSENT flag clear bit - bit_offset: 7 - bit_size: 1 - - name: DATAENDC - description: DATAEND flag clear bit - bit_offset: 8 - bit_size: 1 - - name: DBCKENDC - description: DBCKEND flag clear bit - bit_offset: 10 - bit_size: 1 - - name: SDIOITC - description: SDIOIT flag clear bit - bit_offset: 22 - bit_size: 1 + - name: CCRCFAILC + description: CCRCFAIL flag clear bit + bit_offset: 0 + bit_size: 1 + - name: DCRCFAILC + description: DCRCFAIL flag clear bit + bit_offset: 1 + bit_size: 1 + - name: CTIMEOUTC + description: CTIMEOUT flag clear bit + bit_offset: 2 + bit_size: 1 + - name: DTIMEOUTC + description: DTIMEOUT flag clear bit + bit_offset: 3 + bit_size: 1 + - name: TXUNDERRC + description: TXUNDERR flag clear bit + bit_offset: 4 + bit_size: 1 + - name: RXOVERRC + description: RXOVERR flag clear bit + bit_offset: 5 + bit_size: 1 + - name: CMDRENDC + description: CMDREND flag clear bit + bit_offset: 6 + bit_size: 1 + - name: CMDSENTC + description: CMDSENT flag clear bit + bit_offset: 7 + bit_size: 1 + - name: DATAENDC + description: DATAEND flag clear bit + bit_offset: 8 + bit_size: 1 + - name: STBITERRC + description: STBITERR flag clear bit + bit_offset: 9 + bit_size: 1 + - name: DBCKENDC + description: DBCKEND flag clear bit + bit_offset: 10 + bit_size: 1 + - name: SDIOITC + description: SDIOIT flag clear bit + bit_offset: 22 + bit_size: 1 fieldset/MASKR: description: mask register fields: - - name: CCRCFAILIE - description: Command CRC fail interrupt enable - bit_offset: 0 - bit_size: 1 - - name: DCRCFAILIE - description: Data CRC fail interrupt enable - bit_offset: 1 - bit_size: 1 - - name: CTIMEOUTIE - description: Command timeout interrupt enable - bit_offset: 2 - bit_size: 1 - - name: DTIMEOUTIE - description: Data timeout interrupt enable - bit_offset: 3 - bit_size: 1 - - name: TXUNDERRIE - description: Tx FIFO underrun error interrupt enable - bit_offset: 4 - bit_size: 1 - - name: RXOVERRIE - description: Rx FIFO overrun error interrupt enable - bit_offset: 5 - bit_size: 1 - - name: CMDRENDIE - description: Command response received interrupt enable - bit_offset: 6 - bit_size: 1 - - name: CMDSENTIE - description: Command sent interrupt enable - bit_offset: 7 - bit_size: 1 - - name: DATAENDIE - description: Data end interrupt enable - bit_offset: 8 - bit_size: 1 - - name: DBCKENDIE - description: Data block end interrupt enable - bit_offset: 10 - bit_size: 1 - - name: CMDACTIE - description: Command acting interrupt enable - bit_offset: 11 - bit_size: 1 - - name: TXACTIE - description: Data transmit acting interrupt enable - bit_offset: 12 - bit_size: 1 - - name: RXACTIE - description: Data receive acting interrupt enable - bit_offset: 13 - bit_size: 1 - - name: TXFIFOHEIE - description: Tx FIFO half empty interrupt enable - bit_offset: 14 - bit_size: 1 - - name: RXFIFOHFIE - description: Rx FIFO half full interrupt enable - bit_offset: 15 - bit_size: 1 - - name: TXFIFOFIE - description: Tx FIFO full interrupt enable - bit_offset: 16 - bit_size: 1 - - name: RXFIFOFIE - description: Rx FIFO full interrupt enable - bit_offset: 17 - bit_size: 1 - - name: TXFIFOEIE - description: Tx FIFO empty interrupt enable - bit_offset: 18 - bit_size: 1 - - name: RXFIFOEIE - description: Rx FIFO empty interrupt enable - bit_offset: 19 - bit_size: 1 - - name: TXDAVLIE - description: Data available in Tx FIFO interrupt enable - bit_offset: 20 - bit_size: 1 - - name: RXDAVLIE - description: Data available in Rx FIFO interrupt enable - bit_offset: 21 - bit_size: 1 - - name: SDIOITIE - description: SDIO mode interrupt received interrupt enable - bit_offset: 22 - bit_size: 1 + - name: CCRCFAILIE + description: Command CRC fail interrupt enable + bit_offset: 0 + bit_size: 1 + - name: DCRCFAILIE + description: Data CRC fail interrupt enable + bit_offset: 1 + bit_size: 1 + - name: CTIMEOUTIE + description: Command timeout interrupt enable + bit_offset: 2 + bit_size: 1 + - name: DTIMEOUTIE + description: Data timeout interrupt enable + bit_offset: 3 + bit_size: 1 + - name: TXUNDERRIE + description: Tx FIFO underrun error interrupt enable + bit_offset: 4 + bit_size: 1 + - name: RXOVERRIE + description: Rx FIFO overrun error interrupt enable + bit_offset: 5 + bit_size: 1 + - name: CMDRENDIE + description: Command response received interrupt enable + bit_offset: 6 + bit_size: 1 + - name: CMDSENTIE + description: Command sent interrupt enable + bit_offset: 7 + bit_size: 1 + - name: DATAENDIE + description: Data end interrupt enable + bit_offset: 8 + bit_size: 1 + - name: STBITERRE + description: STBITERR interrupt enable + bit_offset: 9 + bit_size: 1 + - name: DBCKENDIE + description: Data block end interrupt enable + bit_offset: 10 + bit_size: 1 + - name: CMDACTIE + description: Command acting interrupt enable + bit_offset: 11 + bit_size: 1 + - name: TXACTIE + description: Data transmit acting interrupt enable + bit_offset: 12 + bit_size: 1 + - name: RXACTIE + description: Data receive acting interrupt enable + bit_offset: 13 + bit_size: 1 + - name: TXFIFOHEIE + description: Tx FIFO half empty interrupt enable + bit_offset: 14 + bit_size: 1 + - name: RXFIFOHFIE + description: Rx FIFO half full interrupt enable + bit_offset: 15 + bit_size: 1 + - name: TXFIFOFIE + description: Tx FIFO full interrupt enable + bit_offset: 16 + bit_size: 1 + - name: RXFIFOFIE + description: Rx FIFO full interrupt enable + bit_offset: 17 + bit_size: 1 + - name: TXFIFOEIE + description: Tx FIFO empty interrupt enable + bit_offset: 18 + bit_size: 1 + - name: RXFIFOEIE + description: Rx FIFO empty interrupt enable + bit_offset: 19 + bit_size: 1 + - name: TXDAVLIE + description: Data available in Tx FIFO interrupt enable + bit_offset: 20 + bit_size: 1 + - name: RXDAVLIE + description: Data available in Rx FIFO interrupt enable + bit_offset: 21 + bit_size: 1 + - name: SDIOITIE + description: SDIO mode interrupt received interrupt enable + bit_offset: 22 + bit_size: 1 fieldset/POWER: description: power control register fields: - - name: PWRCTRL - description: PWRCTRL - bit_offset: 0 - bit_size: 2 + - name: PWRCTRL + description: PWRCTRL + bit_offset: 0 + bit_size: 2 fieldset/RESP1R: description: response 1..4 register fields: - - name: CARDSTATUS - description: see Table 132 - bit_offset: 0 - bit_size: 32 + - name: CARDSTATUS + description: see Table 132 + bit_offset: 0 + bit_size: 32 fieldset/RESP2R: description: response 1..4 register fields: - - name: CARDSTATUS - description: see Table 132 - bit_offset: 0 - bit_size: 32 + - name: CARDSTATUS + description: see Table 132 + bit_offset: 0 + bit_size: 32 fieldset/RESP3R: description: response 1..4 register fields: - - name: CARDSTATUS - description: see Table 132 - bit_offset: 0 - bit_size: 32 + - name: CARDSTATUS + description: see Table 132 + bit_offset: 0 + bit_size: 32 fieldset/RESP4R: description: response 1..4 register fields: - - name: CARDSTATUS - description: see Table 132 - bit_offset: 0 - bit_size: 32 + - name: CARDSTATUS + description: see Table 132 + bit_offset: 0 + bit_size: 32 fieldset/RESPCMDR: description: command response register fields: - - name: RESPCMD - description: Response command index - bit_offset: 0 - bit_size: 6 + - name: RESPCMD + description: Response command index + bit_offset: 0 + bit_size: 6 fieldset/STAR: description: status register fields: - - name: CCRCFAIL - description: Command response received (CRC check failed) - bit_offset: 0 - bit_size: 1 - - name: DCRCFAIL - description: Data block sent/received (CRC check failed) - bit_offset: 1 - bit_size: 1 - - name: CTIMEOUT - description: Command response timeout - bit_offset: 2 - bit_size: 1 - - name: DTIMEOUT - description: Data timeout - bit_offset: 3 - bit_size: 1 - - name: TXUNDERR - description: Transmit FIFO underrun error - bit_offset: 4 - bit_size: 1 - - name: RXOVERR - description: Received FIFO overrun error - bit_offset: 5 - bit_size: 1 - - name: CMDREND - description: Command response received (CRC check passed) - bit_offset: 6 - bit_size: 1 - - name: CMDSENT - description: Command sent (no response required) - bit_offset: 7 - bit_size: 1 - - name: DATAEND - description: "Data end (data counter, SDIDCOUNT, is zero)" - bit_offset: 8 - bit_size: 1 - - name: DBCKEND - description: Data block sent/received (CRC check passed) - bit_offset: 10 - bit_size: 1 - - name: CMDACT - description: Command transfer in progress - bit_offset: 11 - bit_size: 1 - - name: TXACT - description: Data transmit in progress - bit_offset: 12 - bit_size: 1 - - name: RXACT - description: Data receive in progress - bit_offset: 13 - bit_size: 1 - - name: TXFIFOHE - description: "Transmit FIFO half empty: at least 8 words can be written into the FIFO" - bit_offset: 14 - bit_size: 1 - - name: RXFIFOHF - description: "Receive FIFO half full: there are at least 8 words in the FIFO" - bit_offset: 15 - bit_size: 1 - - name: TXFIFOF - description: Transmit FIFO full - bit_offset: 16 - bit_size: 1 - - name: RXFIFOF - description: Receive FIFO full - bit_offset: 17 - bit_size: 1 - - name: TXFIFOE - description: Transmit FIFO empty - bit_offset: 18 - bit_size: 1 - - name: RXFIFOE - description: Receive FIFO empty - bit_offset: 19 - bit_size: 1 - - name: TXDAVL - description: Data available in transmit FIFO - bit_offset: 20 - bit_size: 1 - - name: RXDAVL - description: Data available in receive FIFO - bit_offset: 21 - bit_size: 1 - - name: SDIOIT - description: SDIO interrupt received - bit_offset: 22 - bit_size: 1 + - name: CCRCFAIL + description: Command response received (CRC check failed) + bit_offset: 0 + bit_size: 1 + - name: DCRCFAIL + description: Data block sent/received (CRC check failed) + bit_offset: 1 + bit_size: 1 + - name: CTIMEOUT + description: Command response timeout + bit_offset: 2 + bit_size: 1 + - name: DTIMEOUT + description: Data timeout + bit_offset: 3 + bit_size: 1 + - name: TXUNDERR + description: Transmit FIFO underrun error + bit_offset: 4 + bit_size: 1 + - name: RXOVERR + description: Received FIFO overrun error + bit_offset: 5 + bit_size: 1 + - name: CMDREND + description: Command response received (CRC check passed) + bit_offset: 6 + bit_size: 1 + - name: CMDSENT + description: Command sent (no response required) + bit_offset: 7 + bit_size: 1 + - name: DATAEND + description: Data end (data counter, SDIDCOUNT, is zero) + bit_offset: 8 + bit_size: 1 + - name: STBITERR + description: Start bit not detected on all data signals in wide bus mode + bit_offset: 9 + bit_size: 1 + - name: DBCKEND + description: Data block sent/received (CRC check passed) + bit_offset: 10 + bit_size: 1 + - name: CMDACT + description: Command transfer in progress + bit_offset: 11 + bit_size: 1 + - name: TXACT + description: Data transmit in progress + bit_offset: 12 + bit_size: 1 + - name: RXACT + description: Data receive in progress + bit_offset: 13 + bit_size: 1 + - name: TXFIFOHE + description: 'Transmit FIFO half empty: at least 8 words can be written into the FIFO' + bit_offset: 14 + bit_size: 1 + - name: RXFIFOHF + description: 'Receive FIFO half full: there are at least 8 words in the FIFO' + bit_offset: 15 + bit_size: 1 + - name: TXFIFOF + description: Transmit FIFO full + bit_offset: 16 + bit_size: 1 + - name: RXFIFOF + description: Receive FIFO full + bit_offset: 17 + bit_size: 1 + - name: TXFIFOE + description: Transmit FIFO empty + bit_offset: 18 + bit_size: 1 + - name: RXFIFOE + description: Receive FIFO empty + bit_offset: 19 + bit_size: 1 + - name: TXDAVL + description: Data available in transmit FIFO + bit_offset: 20 + bit_size: 1 + - name: RXDAVL + description: Data available in receive FIFO + bit_offset: 21 + bit_size: 1 + - name: SDIOIT + description: SDIO interrupt received + bit_offset: 22 + bit_size: 1 diff --git a/data/registers/sdmmc_v2.yaml b/data/registers/sdmmc_v2.yaml index cd30ff0..3210812 100644 --- a/data/registers/sdmmc_v2.yaml +++ b/data/registers/sdmmc_v2.yaml @@ -1,669 +1,668 @@ ---- block/SDMMC: description: SDMMC items: - - name: POWER - description: SDMMC power control register - byte_offset: 0 - fieldset: POWER - - name: CLKCR - description: "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width." - byte_offset: 4 - fieldset: CLKCR - - name: ARGR - description: "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message." - byte_offset: 8 - fieldset: ARGR - - name: CMDR - description: The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). - byte_offset: 12 - fieldset: CMDR - - name: RESPCMDR - description: SDMMC command response register - byte_offset: 16 - access: Read - fieldset: RESPCMDR - - name: RESPR - description: "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response." - array: - len: 4 - stride: 4 - byte_offset: 20 - access: Read - fieldset: RESP1R - - name: DTIMER - description: "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set." - byte_offset: 36 - fieldset: DTIMER - - name: DLENR - description: The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. - byte_offset: 40 - fieldset: DLENR - - name: DCTRL - description: The SDMMC_DCTRL register control the data path state machine (DPSM). - byte_offset: 44 - fieldset: DCTRL - - name: DCNTR - description: "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set." - byte_offset: 48 - access: Read - fieldset: DCNTR - - name: STAR - description: "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)" - byte_offset: 52 - access: Read - fieldset: STAR - - name: ICR - description: The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. - byte_offset: 56 - fieldset: ICR - - name: MASKR - description: The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. - byte_offset: 60 - fieldset: MASKR - - name: ACKTIMER - description: "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set." - byte_offset: 64 - fieldset: ACKTIMER - - name: IDMACTRLR - description: The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. - byte_offset: 80 - fieldset: IDMACTRLR - - name: IDMABSIZER - description: The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration. - byte_offset: 84 - fieldset: IDMABSIZER - - name: IDMABASE0R - description: The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration. - byte_offset: 88 - fieldset: IDMABASE0R - - name: IDMABASE1R - description: The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address. - byte_offset: 92 - fieldset: IDMABASE1R - - name: FIFOR - description: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. - byte_offset: 128 - fieldset: FIFOR - - name: VER - description: SDMMC IP version register - byte_offset: 1012 - access: Read - fieldset: VER - - name: ID - description: SDMMC IP identification register - byte_offset: 1016 - access: Read - fieldset: ID + - name: POWER + description: SDMMC power control register + byte_offset: 0 + fieldset: POWER + - name: CLKCR + description: The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width. + byte_offset: 4 + fieldset: CLKCR + - name: ARGR + description: The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message. + byte_offset: 8 + fieldset: ARGR + - name: CMDR + description: The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). + byte_offset: 12 + fieldset: CMDR + - name: RESPCMDR + description: SDMMC command response register + byte_offset: 16 + access: Read + fieldset: RESPCMDR + - name: RESPR + description: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. + array: + len: 4 + stride: 4 + byte_offset: 20 + access: Read + fieldset: RESP1R + - name: DTIMER + description: The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. + byte_offset: 36 + fieldset: DTIMER + - name: DLENR + description: The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. + byte_offset: 40 + fieldset: DLENR + - name: DCTRL + description: The SDMMC_DCTRL register control the data path state machine (DPSM). + byte_offset: 44 + fieldset: DCTRL + - name: DCNTR + description: The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set. + byte_offset: 48 + access: Read + fieldset: DCNTR + - name: STAR + description: 'The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)' + byte_offset: 52 + access: Read + fieldset: STAR + - name: ICR + description: The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. + byte_offset: 56 + fieldset: ICR + - name: MASKR + description: The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. + byte_offset: 60 + fieldset: MASKR + - name: ACKTIMER + description: The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set. + byte_offset: 64 + fieldset: ACKTIMER + - name: IDMACTRLR + description: The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. + byte_offset: 80 + fieldset: IDMACTRLR + - name: IDMABSIZER + description: The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration. + byte_offset: 84 + fieldset: IDMABSIZER + - name: IDMABASE0R + description: The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration. + byte_offset: 88 + fieldset: IDMABASE0R + - name: IDMABASE1R + description: The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address. + byte_offset: 92 + fieldset: IDMABASE1R + - name: FIFOR + description: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + byte_offset: 128 + fieldset: FIFOR + - name: VER + description: SDMMC IP version register + byte_offset: 1012 + access: Read + fieldset: VER + - name: ID + description: SDMMC IP identification register + byte_offset: 1016 + access: Read + fieldset: ID fieldset/ACKTIMER: - description: "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set." + description: The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set. fields: - - name: ACKTIME - description: Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods. - bit_offset: 0 - bit_size: 25 + - name: ACKTIME + description: Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods. + bit_offset: 0 + bit_size: 25 fieldset/ARGR: - description: "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message." + description: The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message. fields: - - name: CMDARG - description: "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register." - bit_offset: 0 - bit_size: 32 + - name: CMDARG + description: Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register. + bit_offset: 0 + bit_size: 32 fieldset/CLKCR: - description: "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width." + description: The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width. fields: - - name: CLKDIV - description: "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.." - bit_offset: 0 - bit_size: 10 - - name: PWRSAV - description: "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:" - bit_offset: 12 - bit_size: 1 - - name: WIDBUS - description: Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) - bit_offset: 14 - bit_size: 2 - - name: NEGEDGE - description: "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge." - bit_offset: 16 - bit_size: 1 - - name: HWFC_EN - description: "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11." - bit_offset: 17 - bit_size: 1 - - name: DDR - description: Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0) - bit_offset: 18 - bit_size: 1 - - name: BUSSPEED - description: "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)" - bit_offset: 19 - bit_size: 1 - - name: SELCLKRX - description: Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) - bit_offset: 20 - bit_size: 2 + - name: CLKDIV + description: 'Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc..' + bit_offset: 0 + bit_size: 10 + - name: PWRSAV + description: 'Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:' + bit_offset: 12 + bit_size: 1 + - name: WIDBUS + description: Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) + bit_offset: 14 + bit_size: 2 + - name: NEGEDGE + description: 'SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge.' + bit_offset: 16 + bit_size: 1 + - name: HWFC_EN + description: Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11. + bit_offset: 17 + bit_size: 1 + - name: DDR + description: Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0) + bit_offset: 18 + bit_size: 1 + - name: BUSSPEED + description: Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) + bit_offset: 19 + bit_size: 1 + - name: SELCLKRX + description: Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) + bit_offset: 20 + bit_size: 2 fieldset/CMDR: description: The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). fields: - - name: CMDINDEX - description: Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message. - bit_offset: 0 - bit_size: 6 - - name: CMDTRANS - description: "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent." - bit_offset: 6 - bit_size: 1 - - name: CMDSTOP - description: "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent." - bit_offset: 7 - bit_size: 1 - - name: WAITRESP - description: "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response." - bit_offset: 8 - bit_size: 2 - - name: WAITINT - description: "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode." - bit_offset: 10 - bit_size: 1 - - name: WAITPEND - description: "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card." - bit_offset: 11 - bit_size: 1 - - name: CPSMEN - description: "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0." - bit_offset: 12 - bit_size: 1 - - name: DTHOLD - description: "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state." - bit_offset: 13 - bit_size: 1 - - name: BOOTMODE - description: Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0) - bit_offset: 14 - bit_size: 1 - - name: BOOTEN - description: Enable boot mode procedure. - bit_offset: 15 - bit_size: 1 - - name: CMDSUSPEND - description: "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1." - bit_offset: 16 - bit_size: 1 + - name: CMDINDEX + description: Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message. + bit_offset: 0 + bit_size: 6 + - name: CMDTRANS + description: The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent. + bit_offset: 6 + bit_size: 1 + - name: CMDSTOP + description: The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent. + bit_offset: 7 + bit_size: 1 + - name: WAITRESP + description: Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response. + bit_offset: 8 + bit_size: 2 + - name: WAITINT + description: CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode. + bit_offset: 10 + bit_size: 1 + - name: WAITPEND + description: CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card. + bit_offset: 11 + bit_size: 1 + - name: CPSMEN + description: Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0. + bit_offset: 12 + bit_size: 1 + - name: DTHOLD + description: Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state. + bit_offset: 13 + bit_size: 1 + - name: BOOTMODE + description: Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0) + bit_offset: 14 + bit_size: 1 + - name: BOOTEN + description: Enable boot mode procedure. + bit_offset: 15 + bit_size: 1 + - name: CMDSUSPEND + description: The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1. + bit_offset: 16 + bit_size: 1 fieldset/DCNTR: - description: "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set." + description: The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set. fields: - - name: DATACOUNT - description: "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect." - bit_offset: 0 - bit_size: 25 + - name: DATACOUNT + description: Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect. + bit_offset: 0 + bit_size: 25 fieldset/DCTRL: description: The SDMMC_DCTRL register control the data path state machine (DPSM). fields: - - name: DTEN - description: "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards." - bit_offset: 0 - bit_size: 1 - - name: DTDIR - description: Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). - bit_offset: 1 - bit_size: 1 - - name: DTMODE - description: Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). - bit_offset: 2 - bit_size: 2 - - name: DBLOCKSIZE - description: "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)" - bit_offset: 4 - bit_size: 4 - - name: RWSTART - description: "Read wait start. If this bit is set, read wait operation starts." - bit_offset: 8 - bit_size: 1 - - name: RWSTOP - description: Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state. - bit_offset: 9 - bit_size: 1 - - name: RWMOD - description: Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). - bit_offset: 10 - bit_size: 1 - - name: SDIOEN - description: "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation." - bit_offset: 11 - bit_size: 1 - - name: BOOTACKEN - description: Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). - bit_offset: 12 - bit_size: 1 - - name: FIFORST - description: "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs." - bit_offset: 13 - bit_size: 1 + - name: DTEN + description: Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards. + bit_offset: 0 + bit_size: 1 + - name: DTDIR + description: Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). + bit_offset: 1 + bit_size: 1 + - name: DTMODE + description: Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). + bit_offset: 2 + bit_size: 2 + - name: DBLOCKSIZE + description: 'Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)' + bit_offset: 4 + bit_size: 4 + - name: RWSTART + description: Read wait start. If this bit is set, read wait operation starts. + bit_offset: 8 + bit_size: 1 + - name: RWSTOP + description: Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state. + bit_offset: 9 + bit_size: 1 + - name: RWMOD + description: Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). + bit_offset: 10 + bit_size: 1 + - name: SDIOEN + description: SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation. + bit_offset: 11 + bit_size: 1 + - name: BOOTACKEN + description: Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). + bit_offset: 12 + bit_size: 1 + - name: FIFORST + description: FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs. + bit_offset: 13 + bit_size: 1 fieldset/DLENR: description: The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. fields: - - name: DATALENGTH - description: "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0." - bit_offset: 0 - bit_size: 25 + - name: DATALENGTH + description: Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0. + bit_offset: 0 + bit_size: 25 fieldset/DTIMER: - description: "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set." + description: The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. fields: - - name: DATATIME - description: Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods. - bit_offset: 0 - bit_size: 32 + - name: DATATIME + description: Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods. + bit_offset: 0 + bit_size: 32 fieldset/FIFOR: description: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. fields: - - name: FIFODATA - description: Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words. - bit_offset: 0 - bit_size: 32 + - name: FIFODATA + description: Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words. + bit_offset: 0 + bit_size: 32 fieldset/ICR: description: The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. fields: - - name: CCRCFAILC - description: CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag. - bit_offset: 0 - bit_size: 1 - - name: DCRCFAILC - description: DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag. - bit_offset: 1 - bit_size: 1 - - name: CTIMEOUTC - description: CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag. - bit_offset: 2 - bit_size: 1 - - name: DTIMEOUTC - description: DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag. - bit_offset: 3 - bit_size: 1 - - name: TXUNDERRC - description: TXUNDERR flag clear bit Set by software to clear TXUNDERR flag. - bit_offset: 4 - bit_size: 1 - - name: RXOVERRC - description: RXOVERR flag clear bit Set by software to clear the RXOVERR flag. - bit_offset: 5 - bit_size: 1 - - name: CMDRENDC - description: CMDREND flag clear bit Set by software to clear the CMDREND flag. - bit_offset: 6 - bit_size: 1 - - name: CMDSENTC - description: CMDSENT flag clear bit Set by software to clear the CMDSENT flag. - bit_offset: 7 - bit_size: 1 - - name: DATAENDC - description: DATAEND flag clear bit Set by software to clear the DATAEND flag. - bit_offset: 8 - bit_size: 1 - - name: DHOLDC - description: DHOLD flag clear bit Set by software to clear the DHOLD flag. - bit_offset: 9 - bit_size: 1 - - name: DBCKENDC - description: DBCKEND flag clear bit Set by software to clear the DBCKEND flag. - bit_offset: 10 - bit_size: 1 - - name: DABORTC - description: DABORT flag clear bit Set by software to clear the DABORT flag. - bit_offset: 11 - bit_size: 1 - - name: BUSYD0ENDC - description: BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag. - bit_offset: 21 - bit_size: 1 - - name: SDIOITC - description: SDIOIT flag clear bit Set by software to clear the SDIOIT flag. - bit_offset: 22 - bit_size: 1 - - name: ACKFAILC - description: ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag. - bit_offset: 23 - bit_size: 1 - - name: ACKTIMEOUTC - description: ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag. - bit_offset: 24 - bit_size: 1 - - name: VSWENDC - description: VSWEND flag clear bit Set by software to clear the VSWEND flag. - bit_offset: 25 - bit_size: 1 - - name: CKSTOPC - description: CKSTOP flag clear bit Set by software to clear the CKSTOP flag. - bit_offset: 26 - bit_size: 1 - - name: IDMATEC - description: IDMA transfer error clear bit Set by software to clear the IDMATE flag. - bit_offset: 27 - bit_size: 1 - - name: IDMABTCC - description: IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag. - bit_offset: 28 - bit_size: 1 + - name: CCRCFAILC + description: CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag. + bit_offset: 0 + bit_size: 1 + - name: DCRCFAILC + description: DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag. + bit_offset: 1 + bit_size: 1 + - name: CTIMEOUTC + description: CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag. + bit_offset: 2 + bit_size: 1 + - name: DTIMEOUTC + description: DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag. + bit_offset: 3 + bit_size: 1 + - name: TXUNDERRC + description: TXUNDERR flag clear bit Set by software to clear TXUNDERR flag. + bit_offset: 4 + bit_size: 1 + - name: RXOVERRC + description: RXOVERR flag clear bit Set by software to clear the RXOVERR flag. + bit_offset: 5 + bit_size: 1 + - name: CMDRENDC + description: CMDREND flag clear bit Set by software to clear the CMDREND flag. + bit_offset: 6 + bit_size: 1 + - name: CMDSENTC + description: CMDSENT flag clear bit Set by software to clear the CMDSENT flag. + bit_offset: 7 + bit_size: 1 + - name: DATAENDC + description: DATAEND flag clear bit Set by software to clear the DATAEND flag. + bit_offset: 8 + bit_size: 1 + - name: DHOLDC + description: DHOLD flag clear bit Set by software to clear the DHOLD flag. + bit_offset: 9 + bit_size: 1 + - name: DBCKENDC + description: DBCKEND flag clear bit Set by software to clear the DBCKEND flag. + bit_offset: 10 + bit_size: 1 + - name: DABORTC + description: DABORT flag clear bit Set by software to clear the DABORT flag. + bit_offset: 11 + bit_size: 1 + - name: BUSYD0ENDC + description: BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag. + bit_offset: 21 + bit_size: 1 + - name: SDIOITC + description: SDIOIT flag clear bit Set by software to clear the SDIOIT flag. + bit_offset: 22 + bit_size: 1 + - name: ACKFAILC + description: ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag. + bit_offset: 23 + bit_size: 1 + - name: ACKTIMEOUTC + description: ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag. + bit_offset: 24 + bit_size: 1 + - name: VSWENDC + description: VSWEND flag clear bit Set by software to clear the VSWEND flag. + bit_offset: 25 + bit_size: 1 + - name: CKSTOPC + description: CKSTOP flag clear bit Set by software to clear the CKSTOP flag. + bit_offset: 26 + bit_size: 1 + - name: IDMATEC + description: IDMA transfer error clear bit Set by software to clear the IDMATE flag. + bit_offset: 27 + bit_size: 1 + - name: IDMABTCC + description: IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag. + bit_offset: 28 + bit_size: 1 fieldset/ID: description: SDMMC IP identification register fields: - - name: IP_ID - description: SDMMC IP identification. - bit_offset: 0 - bit_size: 32 + - name: IP_ID + description: SDMMC IP identification. + bit_offset: 0 + bit_size: 32 fieldset/IDMABASE0R: description: The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration. fields: - - name: IDMABASE0 - description: "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)." - bit_offset: 0 - bit_size: 32 + - name: IDMABASE0 + description: Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1). + bit_offset: 0 + bit_size: 32 fieldset/IDMABASE1R: description: The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address. fields: - - name: IDMABASE1 - description: "Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)." - bit_offset: 0 - bit_size: 32 + - name: IDMABASE1 + description: Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0). + bit_offset: 0 + bit_size: 32 fieldset/IDMABSIZER: description: The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration. fields: - - name: IDMABNDT - description: "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)." - bit_offset: 5 - bit_size: 8 + - name: IDMABNDT + description: 'Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0).' + bit_offset: 5 + bit_size: 8 fieldset/IDMACTRLR: description: The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. fields: - - name: IDMAEN - description: IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). - bit_offset: 0 - bit_size: 1 - - name: IDMABMODE - description: Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). - bit_offset: 1 - bit_size: 1 - - name: IDMABACT - description: Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware. - bit_offset: 2 - bit_size: 1 + - name: IDMAEN + description: IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). + bit_offset: 0 + bit_size: 1 + - name: IDMABMODE + description: Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). + bit_offset: 1 + bit_size: 1 + - name: IDMABACT + description: Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware. + bit_offset: 2 + bit_size: 1 fieldset/MASKR: description: The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. fields: - - name: CCRCFAILIE - description: Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure. - bit_offset: 0 - bit_size: 1 - - name: DCRCFAILIE - description: Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure. - bit_offset: 1 - bit_size: 1 - - name: CTIMEOUTIE - description: Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout. - bit_offset: 2 - bit_size: 1 - - name: DTIMEOUTIE - description: Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout. - bit_offset: 3 - bit_size: 1 - - name: TXUNDERRIE - description: Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error. - bit_offset: 4 - bit_size: 1 - - name: RXOVERRIE - description: Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error. - bit_offset: 5 - bit_size: 1 - - name: CMDRENDIE - description: Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. - bit_offset: 6 - bit_size: 1 - - name: CMDSENTIE - description: Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command. - bit_offset: 7 - bit_size: 1 - - name: DATAENDIE - description: Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end. - bit_offset: 8 - bit_size: 1 - - name: DHOLDIE - description: Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state. - bit_offset: 9 - bit_size: 1 - - name: DBCKENDIE - description: Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end. - bit_offset: 10 - bit_size: 1 - - name: DABORTIE - description: Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted. - bit_offset: 11 - bit_size: 1 - - name: TXFIFOHEIE - description: Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty. - bit_offset: 14 - bit_size: 1 - - name: RXFIFOHFIE - description: Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full. - bit_offset: 15 - bit_size: 1 - - name: RXFIFOFIE - description: Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full. - bit_offset: 17 - bit_size: 1 - - name: TXFIFOEIE - description: Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty. - bit_offset: 18 - bit_size: 1 - - name: BUSYD0ENDIE - description: BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response. - bit_offset: 21 - bit_size: 1 - - name: SDIOITIE - description: SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt. - bit_offset: 22 - bit_size: 1 - - name: ACKFAILIE - description: Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail. - bit_offset: 23 - bit_size: 1 - - name: ACKTIMEOUTIE - description: Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout. - bit_offset: 24 - bit_size: 1 - - name: VSWENDIE - description: Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion. - bit_offset: 25 - bit_size: 1 - - name: CKSTOPIE - description: Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped. - bit_offset: 26 - bit_size: 1 - - name: IDMABTCIE - description: IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer. - bit_offset: 28 - bit_size: 1 + - name: CCRCFAILIE + description: Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure. + bit_offset: 0 + bit_size: 1 + - name: DCRCFAILIE + description: Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure. + bit_offset: 1 + bit_size: 1 + - name: CTIMEOUTIE + description: Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout. + bit_offset: 2 + bit_size: 1 + - name: DTIMEOUTIE + description: Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout. + bit_offset: 3 + bit_size: 1 + - name: TXUNDERRIE + description: Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error. + bit_offset: 4 + bit_size: 1 + - name: RXOVERRIE + description: Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error. + bit_offset: 5 + bit_size: 1 + - name: CMDRENDIE + description: Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. + bit_offset: 6 + bit_size: 1 + - name: CMDSENTIE + description: Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command. + bit_offset: 7 + bit_size: 1 + - name: DATAENDIE + description: Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end. + bit_offset: 8 + bit_size: 1 + - name: DHOLDIE + description: Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state. + bit_offset: 9 + bit_size: 1 + - name: DBCKENDIE + description: Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end. + bit_offset: 10 + bit_size: 1 + - name: DABORTIE + description: Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted. + bit_offset: 11 + bit_size: 1 + - name: TXFIFOHEIE + description: Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty. + bit_offset: 14 + bit_size: 1 + - name: RXFIFOHFIE + description: Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full. + bit_offset: 15 + bit_size: 1 + - name: RXFIFOFIE + description: Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full. + bit_offset: 17 + bit_size: 1 + - name: TXFIFOEIE + description: Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty. + bit_offset: 18 + bit_size: 1 + - name: BUSYD0ENDIE + description: BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response. + bit_offset: 21 + bit_size: 1 + - name: SDIOITIE + description: SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt. + bit_offset: 22 + bit_size: 1 + - name: ACKFAILIE + description: Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail. + bit_offset: 23 + bit_size: 1 + - name: ACKTIMEOUTIE + description: Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout. + bit_offset: 24 + bit_size: 1 + - name: VSWENDIE + description: Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion. + bit_offset: 25 + bit_size: 1 + - name: CKSTOPIE + description: Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped. + bit_offset: 26 + bit_size: 1 + - name: IDMABTCIE + description: IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer. + bit_offset: 28 + bit_size: 1 fieldset/POWER: description: SDMMC power control register fields: - - name: PWRCTRL - description: "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11." - bit_offset: 0 - bit_size: 2 - - name: VSWITCH - description: "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:" - bit_offset: 2 - bit_size: 1 - - name: VSWITCHEN - description: "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:" - bit_offset: 3 - bit_size: 1 - - name: DIRPOL - description: Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00). - bit_offset: 4 - bit_size: 1 + - name: PWRCTRL + description: 'SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11.' + bit_offset: 0 + bit_size: 2 + - name: VSWITCH + description: 'Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:' + bit_offset: 2 + bit_size: 1 + - name: VSWITCHEN + description: 'Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:' + bit_offset: 3 + bit_size: 1 + - name: DIRPOL + description: Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00). + bit_offset: 4 + bit_size: 1 fieldset/RESP1R: - description: "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response." + description: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. fields: - - name: CARDSTATUS - description: see Table 432 - bit_offset: 0 - bit_size: 32 + - name: CARDSTATUS + description: see Table 432 + bit_offset: 0 + bit_size: 32 fieldset/RESP2R: - description: "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response." + description: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. fields: - - name: CARDSTATUS - description: see Table404. - bit_offset: 0 - bit_size: 32 + - name: CARDSTATUS + description: see Table404. + bit_offset: 0 + bit_size: 32 fieldset/RESP3R: - description: "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response." + description: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. fields: - - name: CARDSTATUS - description: see Table404. - bit_offset: 0 - bit_size: 32 + - name: CARDSTATUS + description: see Table404. + bit_offset: 0 + bit_size: 32 fieldset/RESP4R: - description: "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response." + description: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. fields: - - name: CARDSTATUS - description: see Table404. - bit_offset: 0 - bit_size: 32 + - name: CARDSTATUS + description: see Table404. + bit_offset: 0 + bit_size: 32 fieldset/RESPCMDR: description: SDMMC command response register fields: - - name: RESPCMD - description: Response command index - bit_offset: 0 - bit_size: 6 + - name: RESPCMD + description: Response command index + bit_offset: 0 + bit_size: 6 fieldset/STAR: - description: "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)" + description: 'The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)' fields: - - name: CCRCFAIL - description: Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - bit_offset: 0 - bit_size: 1 - - name: DCRCFAIL - description: Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - bit_offset: 1 - bit_size: 1 - - name: CTIMEOUT - description: Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods. - bit_offset: 2 - bit_size: 1 - - name: DTIMEOUT - description: Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - bit_offset: 3 - bit_size: 1 - - name: TXUNDERR - description: Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - bit_offset: 4 - bit_size: 1 - - name: RXOVERR - description: Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - bit_offset: 5 - bit_size: 1 - - name: CMDREND - description: "Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." - bit_offset: 6 - bit_size: 1 - - name: CMDSENT - description: Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - bit_offset: 7 - bit_size: 1 - - name: DATAEND - description: "Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." - bit_offset: 8 - bit_size: 1 - - name: DHOLD - description: Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - bit_offset: 9 - bit_size: 1 - - name: DBCKEND - description: Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - bit_offset: 10 - bit_size: 1 - - name: DABORT - description: Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - bit_offset: 11 - bit_size: 1 - - name: DPSMACT - description: "Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt." - bit_offset: 12 - bit_size: 1 - - name: CPSMACT - description: "Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt." - bit_offset: 13 - bit_size: 1 - - name: TXFIFOHE - description: Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full. - bit_offset: 14 - bit_size: 1 - - name: RXFIFOHF - description: Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty. - bit_offset: 15 - bit_size: 1 - - name: TXFIFOF - description: "Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty." - bit_offset: 16 - bit_size: 1 - - name: RXFIFOF - description: Receive FIFO full This bit is cleared when one FIFO location becomes empty. - bit_offset: 17 - bit_size: 1 - - name: TXFIFOE - description: Transmit FIFO empty This bit is cleared when one FIFO location becomes full. - bit_offset: 18 - bit_size: 1 - - name: RXFIFOE - description: "Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full." - bit_offset: 19 - bit_size: 1 - - name: BUSYD0 - description: "Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt." - bit_offset: 20 - bit_size: 1 - - name: BUSYD0END - description: end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - bit_offset: 21 - bit_size: 1 - - name: SDIOIT - description: SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - bit_offset: 22 - bit_size: 1 - - name: ACKFAIL - description: Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - bit_offset: 23 - bit_size: 1 - - name: ACKTIMEOUT - description: Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - bit_offset: 24 - bit_size: 1 - - name: VSWEND - description: Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - bit_offset: 25 - bit_size: 1 - - name: CKSTOP - description: SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - bit_offset: 26 - bit_size: 1 - - name: IDMATE - description: IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - bit_offset: 27 - bit_size: 1 - - name: IDMABTC - description: IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - bit_offset: 28 - bit_size: 1 + - name: CCRCFAIL + description: Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 0 + bit_size: 1 + - name: DCRCFAIL + description: Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 1 + bit_size: 1 + - name: CTIMEOUT + description: Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods. + bit_offset: 2 + bit_size: 1 + - name: DTIMEOUT + description: Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 3 + bit_size: 1 + - name: TXUNDERR + description: Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 4 + bit_size: 1 + - name: RXOVERR + description: Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 5 + bit_size: 1 + - name: CMDREND + description: Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 6 + bit_size: 1 + - name: CMDSENT + description: Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 7 + bit_size: 1 + - name: DATAEND + description: Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 8 + bit_size: 1 + - name: DHOLD + description: Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 9 + bit_size: 1 + - name: DBCKEND + description: Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 10 + bit_size: 1 + - name: DABORT + description: Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 11 + bit_size: 1 + - name: DPSMACT + description: Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. + bit_offset: 12 + bit_size: 1 + - name: CPSMACT + description: Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. + bit_offset: 13 + bit_size: 1 + - name: TXFIFOHE + description: Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full. + bit_offset: 14 + bit_size: 1 + - name: RXFIFOHF + description: Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty. + bit_offset: 15 + bit_size: 1 + - name: TXFIFOF + description: Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty. + bit_offset: 16 + bit_size: 1 + - name: RXFIFOF + description: Receive FIFO full This bit is cleared when one FIFO location becomes empty. + bit_offset: 17 + bit_size: 1 + - name: TXFIFOE + description: Transmit FIFO empty This bit is cleared when one FIFO location becomes full. + bit_offset: 18 + bit_size: 1 + - name: RXFIFOE + description: Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full. + bit_offset: 19 + bit_size: 1 + - name: BUSYD0 + description: Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt. + bit_offset: 20 + bit_size: 1 + - name: BUSYD0END + description: end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 21 + bit_size: 1 + - name: SDIOIT + description: SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 22 + bit_size: 1 + - name: ACKFAIL + description: Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 23 + bit_size: 1 + - name: ACKTIMEOUT + description: Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 24 + bit_size: 1 + - name: VSWEND + description: Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 25 + bit_size: 1 + - name: CKSTOP + description: SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 26 + bit_size: 1 + - name: IDMATE + description: IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 27 + bit_size: 1 + - name: IDMABTC + description: IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + bit_offset: 28 + bit_size: 1 fieldset/VER: description: SDMMC IP version register fields: - - name: MINREV - description: IP minor revision number. - bit_offset: 0 - bit_size: 4 - - name: MAJREV - description: IP major revision number. - bit_offset: 4 - bit_size: 4 + - name: MINREV + description: IP minor revision number. + bit_offset: 0 + bit_size: 4 + - name: MAJREV + description: IP major revision number. + bit_offset: 4 + bit_size: 4 diff --git a/data/registers/spdifrx_v1.yaml b/data/registers/spdifrx_v1.yaml index ada1268..53b6aef 100644 --- a/data/registers/spdifrx_v1.yaml +++ b/data/registers/spdifrx_v1.yaml @@ -1,238 +1,237 @@ ---- block/SPDIFRX: description: Receiver Interface items: - - name: CR - description: Control register - byte_offset: 0 - fieldset: CR - - name: IMR - description: Interrupt mask register - byte_offset: 4 - fieldset: IMR - - name: SR - description: Status register - byte_offset: 8 - access: Read - fieldset: SR - - name: IFCR - description: Interrupt Flag Clear register - byte_offset: 12 - access: Write - fieldset: IFCR - - name: DR - description: Data input register - byte_offset: 16 - access: Read - fieldset: DR - - name: CSR - description: Channel Status register - byte_offset: 20 - access: Read - fieldset: CSR - - name: DIR - description: Debug Information register - byte_offset: 24 - access: Read - fieldset: DIR + - name: CR + description: Control register + byte_offset: 0 + fieldset: CR + - name: IMR + description: Interrupt mask register + byte_offset: 4 + fieldset: IMR + - name: SR + description: Status register + byte_offset: 8 + access: Read + fieldset: SR + - name: IFCR + description: Interrupt Flag Clear register + byte_offset: 12 + access: Write + fieldset: IFCR + - name: DR + description: Data input register + byte_offset: 16 + access: Read + fieldset: DR + - name: CSR + description: Channel Status register + byte_offset: 20 + access: Read + fieldset: CSR + - name: DIR + description: Debug Information register + byte_offset: 24 + access: Read + fieldset: DIR fieldset/CR: description: Control register fields: - - name: SPDIFEN - description: Peripheral Block Enable - bit_offset: 0 - bit_size: 2 - - name: RXDMAEN - description: Receiver DMA ENable for data flow - bit_offset: 2 - bit_size: 1 - - name: RXSTEO - description: STerEO Mode - bit_offset: 3 - bit_size: 1 - - name: DRFMT - description: RX Data format - bit_offset: 4 - bit_size: 2 - - name: PMSK - description: Mask Parity error bit - bit_offset: 6 - bit_size: 1 - - name: VMSK - description: Mask of Validity bit - bit_offset: 7 - bit_size: 1 - - name: CUMSK - description: Mask of channel status and user bits - bit_offset: 8 - bit_size: 1 - - name: PTMSK - description: Mask of Preamble Type bits - bit_offset: 9 - bit_size: 1 - - name: CBDMAEN - description: Control Buffer DMA ENable for control flow - bit_offset: 10 - bit_size: 1 - - name: CHSEL - description: Channel Selection - bit_offset: 11 - bit_size: 1 - - name: NBTR - description: Maximum allowed re-tries during synchronization phase - bit_offset: 12 - bit_size: 2 - - name: WFA - description: Wait For Activity - bit_offset: 14 - bit_size: 1 - - name: INSEL - description: input selection - bit_offset: 16 - bit_size: 3 + - name: SPDIFEN + description: Peripheral Block Enable + bit_offset: 0 + bit_size: 2 + - name: RXDMAEN + description: Receiver DMA ENable for data flow + bit_offset: 2 + bit_size: 1 + - name: RXSTEO + description: STerEO Mode + bit_offset: 3 + bit_size: 1 + - name: DRFMT + description: RX Data format + bit_offset: 4 + bit_size: 2 + - name: PMSK + description: Mask Parity error bit + bit_offset: 6 + bit_size: 1 + - name: VMSK + description: Mask of Validity bit + bit_offset: 7 + bit_size: 1 + - name: CUMSK + description: Mask of channel status and user bits + bit_offset: 8 + bit_size: 1 + - name: PTMSK + description: Mask of Preamble Type bits + bit_offset: 9 + bit_size: 1 + - name: CBDMAEN + description: Control Buffer DMA ENable for control flow + bit_offset: 10 + bit_size: 1 + - name: CHSEL + description: Channel Selection + bit_offset: 11 + bit_size: 1 + - name: NBTR + description: Maximum allowed re-tries during synchronization phase + bit_offset: 12 + bit_size: 2 + - name: WFA + description: Wait For Activity + bit_offset: 14 + bit_size: 1 + - name: INSEL + description: input selection + bit_offset: 16 + bit_size: 3 fieldset/CSR: description: Channel Status register fields: - - name: USR - description: User data information - bit_offset: 0 - bit_size: 16 - - name: CS - description: Channel A status information - bit_offset: 16 - bit_size: 8 - - name: SOB - description: Start Of Block - bit_offset: 24 - bit_size: 1 + - name: USR + description: User data information + bit_offset: 0 + bit_size: 16 + - name: CS + description: Channel A status information + bit_offset: 16 + bit_size: 8 + - name: SOB + description: Start Of Block + bit_offset: 24 + bit_size: 1 fieldset/DIR: description: Debug Information register fields: - - name: THI - description: Threshold HIGH - bit_offset: 0 - bit_size: 13 - - name: TLO - description: Threshold LOW - bit_offset: 16 - bit_size: 13 + - name: THI + description: Threshold HIGH + bit_offset: 0 + bit_size: 13 + - name: TLO + description: Threshold LOW + bit_offset: 16 + bit_size: 13 fieldset/DR: description: Data input register fields: - - name: DR - description: Parity Error bit - bit_offset: 0 - bit_size: 24 - - name: PE - description: Parity Error bit - bit_offset: 24 - bit_size: 1 - - name: V - description: Validity bit - bit_offset: 25 - bit_size: 1 - - name: U - description: User bit - bit_offset: 26 - bit_size: 1 - - name: C - description: Channel Status bit - bit_offset: 27 - bit_size: 1 - - name: PT - description: Preamble Type - bit_offset: 28 - bit_size: 2 + - name: DR + description: Parity Error bit + bit_offset: 0 + bit_size: 24 + - name: PE + description: Parity Error bit + bit_offset: 24 + bit_size: 1 + - name: V + description: Validity bit + bit_offset: 25 + bit_size: 1 + - name: U + description: User bit + bit_offset: 26 + bit_size: 1 + - name: C + description: Channel Status bit + bit_offset: 27 + bit_size: 1 + - name: PT + description: Preamble Type + bit_offset: 28 + bit_size: 2 fieldset/IFCR: description: Interrupt Flag Clear register fields: - - name: PERRCF - description: Clears the Parity error flag - bit_offset: 2 - bit_size: 1 - - name: OVRCF - description: Clears the Overrun error flag - bit_offset: 3 - bit_size: 1 - - name: SBDCF - description: Clears the Synchronization Block Detected flag - bit_offset: 4 - bit_size: 1 - - name: SYNCDCF - description: Clears the Synchronization Done flag - bit_offset: 5 - bit_size: 1 + - name: PERRCF + description: Clears the Parity error flag + bit_offset: 2 + bit_size: 1 + - name: OVRCF + description: Clears the Overrun error flag + bit_offset: 3 + bit_size: 1 + - name: SBDCF + description: Clears the Synchronization Block Detected flag + bit_offset: 4 + bit_size: 1 + - name: SYNCDCF + description: Clears the Synchronization Done flag + bit_offset: 5 + bit_size: 1 fieldset/IMR: description: Interrupt mask register fields: - - name: RXNEIE - description: RXNE interrupt enable - bit_offset: 0 - bit_size: 1 - - name: CSRNEIE - description: Control Buffer Ready Interrupt Enable - bit_offset: 1 - bit_size: 1 - - name: PERRIE - description: Parity error interrupt enable - bit_offset: 2 - bit_size: 1 - - name: OVRIE - description: Overrun error Interrupt Enable - bit_offset: 3 - bit_size: 1 - - name: SBLKIE - description: Synchronization Block Detected Interrupt Enable - bit_offset: 4 - bit_size: 1 - - name: SYNCDIE - description: Synchronization Done - bit_offset: 5 - bit_size: 1 - - name: IFEIE - description: Serial Interface Error Interrupt Enable - bit_offset: 6 - bit_size: 1 + - name: RXNEIE + description: RXNE interrupt enable + bit_offset: 0 + bit_size: 1 + - name: CSRNEIE + description: Control Buffer Ready Interrupt Enable + bit_offset: 1 + bit_size: 1 + - name: PERRIE + description: Parity error interrupt enable + bit_offset: 2 + bit_size: 1 + - name: OVRIE + description: Overrun error Interrupt Enable + bit_offset: 3 + bit_size: 1 + - name: SBLKIE + description: Synchronization Block Detected Interrupt Enable + bit_offset: 4 + bit_size: 1 + - name: SYNCDIE + description: Synchronization Done + bit_offset: 5 + bit_size: 1 + - name: IFEIE + description: Serial Interface Error Interrupt Enable + bit_offset: 6 + bit_size: 1 fieldset/SR: description: Status register fields: - - name: RXNE - description: Read data register not empty - bit_offset: 0 - bit_size: 1 - - name: CSRNE - description: Control Buffer register is not empty - bit_offset: 1 - bit_size: 1 - - name: PERR - description: Parity error - bit_offset: 2 - bit_size: 1 - - name: OVR - description: Overrun error - bit_offset: 3 - bit_size: 1 - - name: SBD - description: Synchronization Block Detected - bit_offset: 4 - bit_size: 1 - - name: SYNCD - description: Synchronization Done - bit_offset: 5 - bit_size: 1 - - name: FERR - description: Framing error - bit_offset: 6 - bit_size: 1 - - name: SERR - description: Synchronization error - bit_offset: 7 - bit_size: 1 - - name: TERR - description: Time-out error - bit_offset: 8 - bit_size: 1 - - name: WIDTH - description: Duration of 5 symbols counted with SPDIF_CLK - bit_offset: 16 - bit_size: 15 + - name: RXNE + description: Read data register not empty + bit_offset: 0 + bit_size: 1 + - name: CSRNE + description: Control Buffer register is not empty + bit_offset: 1 + bit_size: 1 + - name: PERR + description: Parity error + bit_offset: 2 + bit_size: 1 + - name: OVR + description: Overrun error + bit_offset: 3 + bit_size: 1 + - name: SBD + description: Synchronization Block Detected + bit_offset: 4 + bit_size: 1 + - name: SYNCD + description: Synchronization Done + bit_offset: 5 + bit_size: 1 + - name: FERR + description: Framing error + bit_offset: 6 + bit_size: 1 + - name: SERR + description: Synchronization error + bit_offset: 7 + bit_size: 1 + - name: TERR + description: Time-out error + bit_offset: 8 + bit_size: 1 + - name: WIDTH + description: Duration of 5 symbols counted with SPDIF_CLK + bit_offset: 16 + bit_size: 15 diff --git a/data/registers/spi_f1.yaml b/data/registers/spi_f1.yaml index 324b8f1..5c2278e 100644 --- a/data/registers/spi_f1.yaml +++ b/data/registers/spi_f1.yaml @@ -1,454 +1,453 @@ ---- block/SPI: description: Serial peripheral interface items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2 - - name: SR - description: status register - byte_offset: 8 - fieldset: SR - - name: DR - description: data register - byte_offset: 12 - fieldset: DR - - name: CRCPR - description: CRC polynomial register - byte_offset: 16 - fieldset: CRCPR - - name: RXCRCR - description: RX CRC register - byte_offset: 20 - access: Read - fieldset: RXCRCR - - name: TXCRCR - description: TX CRC register - byte_offset: 24 - access: Read - fieldset: TXCRCR - - name: I2SCFGR - description: I2S configuration register - byte_offset: 28 - fieldset: I2SCFGR - - name: I2SPR - description: I2S prescaler register - byte_offset: 32 - fieldset: I2SPR + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: SR + description: status register + byte_offset: 8 + fieldset: SR + - name: DR + description: data register + byte_offset: 12 + fieldset: DR + - name: CRCPR + description: CRC polynomial register + byte_offset: 16 + fieldset: CRCPR + - name: RXCRCR + description: RX CRC register + byte_offset: 20 + access: Read + fieldset: RXCRCR + - name: TXCRCR + description: TX CRC register + byte_offset: 24 + access: Read + fieldset: TXCRCR + - name: I2SCFGR + description: I2S configuration register + byte_offset: 28 + fieldset: I2SCFGR + - name: I2SPR + description: I2S prescaler register + byte_offset: 32 + fieldset: I2SPR fieldset/CR1: description: control register 1 fields: - - name: CPHA - description: Clock phase - bit_offset: 0 - bit_size: 1 - enum: CPHA - - name: CPOL - description: Clock polarity - bit_offset: 1 - bit_size: 1 - enum: CPOL - - name: MSTR - description: Master selection - bit_offset: 2 - bit_size: 1 - enum: MSTR - - name: BR - description: Baud rate control - bit_offset: 3 - bit_size: 3 - enum: BR - - name: SPE - description: SPI enable - bit_offset: 6 - bit_size: 1 - - name: LSBFIRST - description: Frame format - bit_offset: 7 - bit_size: 1 - enum: LSBFIRST - - name: SSI - description: Internal slave select - bit_offset: 8 - bit_size: 1 - - name: SSM - description: Software slave management - bit_offset: 9 - bit_size: 1 - - name: RXONLY - description: Receive only - bit_offset: 10 - bit_size: 1 - enum: RXONLY - - name: DFF - description: Data frame format - bit_offset: 11 - bit_size: 1 - enum: DFF - - name: CRCNEXT - description: CRC transfer next - bit_offset: 12 - bit_size: 1 - enum: CRCNEXT - - name: CRCEN - description: Hardware CRC calculation enable - bit_offset: 13 - bit_size: 1 - - name: BIDIOE - description: Output enable in bidirectional mode - bit_offset: 14 - bit_size: 1 - enum: BIDIOE - - name: BIDIMODE - description: Bidirectional data mode enable - bit_offset: 15 - bit_size: 1 - enum: BIDIMODE + - name: CPHA + description: Clock phase + bit_offset: 0 + bit_size: 1 + enum: CPHA + - name: CPOL + description: Clock polarity + bit_offset: 1 + bit_size: 1 + enum: CPOL + - name: MSTR + description: Master selection + bit_offset: 2 + bit_size: 1 + enum: MSTR + - name: BR + description: Baud rate control + bit_offset: 3 + bit_size: 3 + enum: BR + - name: SPE + description: SPI enable + bit_offset: 6 + bit_size: 1 + - name: LSBFIRST + description: Frame format + bit_offset: 7 + bit_size: 1 + enum: LSBFIRST + - name: SSI + description: Internal slave select + bit_offset: 8 + bit_size: 1 + - name: SSM + description: Software slave management + bit_offset: 9 + bit_size: 1 + - name: RXONLY + description: Receive only + bit_offset: 10 + bit_size: 1 + enum: RXONLY + - name: DFF + description: Data frame format + bit_offset: 11 + bit_size: 1 + enum: DFF + - name: CRCNEXT + description: CRC transfer next + bit_offset: 12 + bit_size: 1 + enum: CRCNEXT + - name: CRCEN + description: Hardware CRC calculation enable + bit_offset: 13 + bit_size: 1 + - name: BIDIOE + description: Output enable in bidirectional mode + bit_offset: 14 + bit_size: 1 + enum: BIDIOE + - name: BIDIMODE + description: Bidirectional data mode enable + bit_offset: 15 + bit_size: 1 + enum: BIDIMODE fieldset/CR2: description: control register 2 fields: - - name: RXDMAEN - description: Rx buffer DMA enable - bit_offset: 0 - bit_size: 1 - - name: TXDMAEN - description: Tx buffer DMA enable - bit_offset: 1 - bit_size: 1 - - name: SSOE - description: SS output enable - bit_offset: 2 - bit_size: 1 - - name: ERRIE - description: Error interrupt enable - bit_offset: 5 - bit_size: 1 - - name: RXNEIE - description: RX buffer not empty interrupt enable - bit_offset: 6 - bit_size: 1 - - name: TXEIE - description: Tx buffer empty interrupt enable - bit_offset: 7 - bit_size: 1 + - name: RXDMAEN + description: Rx buffer DMA enable + bit_offset: 0 + bit_size: 1 + - name: TXDMAEN + description: Tx buffer DMA enable + bit_offset: 1 + bit_size: 1 + - name: SSOE + description: SS output enable + bit_offset: 2 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 5 + bit_size: 1 + - name: RXNEIE + description: RX buffer not empty interrupt enable + bit_offset: 6 + bit_size: 1 + - name: TXEIE + description: Tx buffer empty interrupt enable + bit_offset: 7 + bit_size: 1 fieldset/CRCPR: description: CRC polynomial register fields: - - name: CRCPOLY - description: CRC polynomial register - bit_offset: 0 - bit_size: 16 + - name: CRCPOLY + description: CRC polynomial register + bit_offset: 0 + bit_size: 16 fieldset/DR: description: data register fields: - - name: DR - description: Data register - bit_offset: 0 - bit_size: 16 + - name: DR + description: Data register + bit_offset: 0 + bit_size: 16 fieldset/I2SCFGR: description: I2S configuration register fields: - - name: CHLEN - description: Channel length (number of bits per audio channel) - bit_offset: 0 - bit_size: 1 - enum: CHLEN - - name: DATLEN - description: Data length to be transferred - bit_offset: 1 - bit_size: 2 - enum: DATLEN - - name: CKPOL - description: Steady state clock polarity - bit_offset: 3 - bit_size: 1 - enum: CKPOL - - name: I2SSTD - description: I2S standard selection - bit_offset: 4 - bit_size: 2 - enum: I2SSTD - - name: PCMSYNC - description: PCM frame synchronization - bit_offset: 7 - bit_size: 1 - enum: PCMSYNC - - name: I2SCFG - description: I2S configuration mode - bit_offset: 8 - bit_size: 2 - enum: I2SCFG - - name: I2SE - description: I2S Enable - bit_offset: 10 - bit_size: 1 - - name: I2SMOD - description: I2S mode selection - bit_offset: 11 - bit_size: 1 + - name: CHLEN + description: Channel length (number of bits per audio channel) + bit_offset: 0 + bit_size: 1 + enum: CHLEN + - name: DATLEN + description: Data length to be transferred + bit_offset: 1 + bit_size: 2 + enum: DATLEN + - name: CKPOL + description: Steady state clock polarity + bit_offset: 3 + bit_size: 1 + enum: CKPOL + - name: I2SSTD + description: I2S standard selection + bit_offset: 4 + bit_size: 2 + enum: I2SSTD + - name: PCMSYNC + description: PCM frame synchronization + bit_offset: 7 + bit_size: 1 + enum: PCMSYNC + - name: I2SCFG + description: I2S configuration mode + bit_offset: 8 + bit_size: 2 + enum: I2SCFG + - name: I2SE + description: I2S Enable + bit_offset: 10 + bit_size: 1 + - name: I2SMOD + description: I2S mode selection + bit_offset: 11 + bit_size: 1 fieldset/I2SPR: description: I2S prescaler register fields: - - name: I2SDIV - description: I2S Linear prescaler - bit_offset: 0 - bit_size: 8 - - name: ODD - description: Odd factor for the prescaler - bit_offset: 8 - bit_size: 1 - enum: ODD - - name: MCKOE - description: Master clock output enable - bit_offset: 9 - bit_size: 1 + - name: I2SDIV + description: I2S Linear prescaler + bit_offset: 0 + bit_size: 8 + - name: ODD + description: Odd factor for the prescaler + bit_offset: 8 + bit_size: 1 + enum: ODD + - name: MCKOE + description: Master clock output enable + bit_offset: 9 + bit_size: 1 fieldset/RXCRCR: description: RX CRC register fields: - - name: RxCRC - description: Rx CRC register - bit_offset: 0 - bit_size: 16 + - name: RxCRC + description: Rx CRC register + bit_offset: 0 + bit_size: 16 fieldset/SR: description: status register fields: - - name: RXNE - description: Receive buffer not empty - bit_offset: 0 - bit_size: 1 - - name: TXE - description: Transmit buffer empty - bit_offset: 1 - bit_size: 1 - - name: CHSIDE - description: Channel side - bit_offset: 2 - bit_size: 1 - enum: CHSIDE - - name: UDR - description: Underrun flag - bit_offset: 3 - bit_size: 1 - - name: CRCERR - description: CRC error flag - bit_offset: 4 - bit_size: 1 - - name: MODF - description: Mode fault - bit_offset: 5 - bit_size: 1 - - name: OVR - description: Overrun flag - bit_offset: 6 - bit_size: 1 - - name: BSY - description: Busy flag - bit_offset: 7 - bit_size: 1 + - name: RXNE + description: Receive buffer not empty + bit_offset: 0 + bit_size: 1 + - name: TXE + description: Transmit buffer empty + bit_offset: 1 + bit_size: 1 + - name: CHSIDE + description: Channel side + bit_offset: 2 + bit_size: 1 + enum: CHSIDE + - name: UDR + description: Underrun flag + bit_offset: 3 + bit_size: 1 + - name: CRCERR + description: CRC error flag + bit_offset: 4 + bit_size: 1 + - name: MODF + description: Mode fault + bit_offset: 5 + bit_size: 1 + - name: OVR + description: Overrun flag + bit_offset: 6 + bit_size: 1 + - name: BSY + description: Busy flag + bit_offset: 7 + bit_size: 1 fieldset/TXCRCR: description: TX CRC register fields: - - name: TxCRC - description: Tx CRC register - bit_offset: 0 - bit_size: 16 + - name: TxCRC + description: Tx CRC register + bit_offset: 0 + bit_size: 16 enum/BIDIMODE: bit_size: 1 variants: - - name: Unidirectional - description: 2-line unidirectional data mode selected - value: 0 - - name: Bidirectional - description: 1-line bidirectional data mode selected - value: 1 + - name: Unidirectional + description: 2-line unidirectional data mode selected + value: 0 + - name: Bidirectional + description: 1-line bidirectional data mode selected + value: 1 enum/BIDIOE: bit_size: 1 variants: - - name: OutputDisabled - description: Output disabled (receive-only mode) - value: 0 - - name: OutputEnabled - description: Output enabled (transmit-only mode) - value: 1 + - name: OutputDisabled + description: Output disabled (receive-only mode) + value: 0 + - name: OutputEnabled + description: Output enabled (transmit-only mode) + value: 1 enum/BR: bit_size: 3 variants: - - name: Div2 - description: f_PCLK / 2 - value: 0 - - name: Div4 - description: f_PCLK / 4 - value: 1 - - name: Div8 - description: f_PCLK / 8 - value: 2 - - name: Div16 - description: f_PCLK / 16 - value: 3 - - name: Div32 - description: f_PCLK / 32 - value: 4 - - name: Div64 - description: f_PCLK / 64 - value: 5 - - name: Div128 - description: f_PCLK / 128 - value: 6 - - name: Div256 - description: f_PCLK / 256 - value: 7 + - name: Div2 + description: f_PCLK / 2 + value: 0 + - name: Div4 + description: f_PCLK / 4 + value: 1 + - name: Div8 + description: f_PCLK / 8 + value: 2 + - name: Div16 + description: f_PCLK / 16 + value: 3 + - name: Div32 + description: f_PCLK / 32 + value: 4 + - name: Div64 + description: f_PCLK / 64 + value: 5 + - name: Div128 + description: f_PCLK / 128 + value: 6 + - name: Div256 + description: f_PCLK / 256 + value: 7 enum/CHLEN: bit_size: 1 variants: - - name: SixteenBit - description: 16-bit wide - value: 0 - - name: ThirtyTwoBit - description: 32-bit wide - value: 1 + - name: SixteenBit + description: 16-bit wide + value: 0 + - name: ThirtyTwoBit + description: 32-bit wide + value: 1 enum/CHSIDE: bit_size: 1 variants: - - name: Left - description: Channel left has to be transmitted or has been received - value: 0 - - name: Right - description: Channel right has to be transmitted or has been received - value: 1 + - name: Left + description: Channel left has to be transmitted or has been received + value: 0 + - name: Right + description: Channel right has to be transmitted or has been received + value: 1 enum/CKPOL: bit_size: 1 variants: - - name: IdleLow - description: I2S clock inactive state is low level - value: 0 - - name: IdleHigh - description: I2S clock inactive state is high level - value: 1 + - name: IdleLow + description: I2S clock inactive state is low level + value: 0 + - name: IdleHigh + description: I2S clock inactive state is high level + value: 1 enum/CPHA: bit_size: 1 variants: - - name: FirstEdge - description: The first clock transition is the first data capture edge - value: 0 - - name: SecondEdge - description: The second clock transition is the first data capture edge - value: 1 + - name: FirstEdge + description: The first clock transition is the first data capture edge + value: 0 + - name: SecondEdge + description: The second clock transition is the first data capture edge + value: 1 enum/CPOL: bit_size: 1 variants: - - name: IdleLow - description: CK to 0 when idle - value: 0 - - name: IdleHigh - description: CK to 1 when idle - value: 1 + - name: IdleLow + description: CK to 0 when idle + value: 0 + - name: IdleHigh + description: CK to 1 when idle + value: 1 enum/CRCNEXT: bit_size: 1 variants: - - name: TxBuffer - description: Next transmit value is from Tx buffer - value: 0 - - name: CRC - description: Next transmit value is from Tx CRC register - value: 1 + - name: TxBuffer + description: Next transmit value is from Tx buffer + value: 0 + - name: CRC + description: Next transmit value is from Tx CRC register + value: 1 enum/DATLEN: bit_size: 2 variants: - - name: SixteenBit - description: 16-bit data length - value: 0 - - name: TwentyFourBit - description: 24-bit data length - value: 1 - - name: ThirtyTwoBit - description: 32-bit data length - value: 2 + - name: SixteenBit + description: 16-bit data length + value: 0 + - name: TwentyFourBit + description: 24-bit data length + value: 1 + - name: ThirtyTwoBit + description: 32-bit data length + value: 2 enum/DFF: bit_size: 1 variants: - - name: EightBit - description: 8-bit data frame format is selected for transmission/reception - value: 0 - - name: SixteenBit - description: 16-bit data frame format is selected for transmission/reception - value: 1 + - name: EightBit + description: 8-bit data frame format is selected for transmission/reception + value: 0 + - name: SixteenBit + description: 16-bit data frame format is selected for transmission/reception + value: 1 enum/I2SCFG: bit_size: 2 variants: - - name: SlaveTx - description: Slave - transmit - value: 0 - - name: SlaveRx - description: Slave - receive - value: 1 - - name: MasterTx - description: Master - transmit - value: 2 - - name: MasterRx - description: Master - receive - value: 3 + - name: SlaveTx + description: Slave - transmit + value: 0 + - name: SlaveRx + description: Slave - receive + value: 1 + - name: MasterTx + description: Master - transmit + value: 2 + - name: MasterRx + description: Master - receive + value: 3 enum/I2SSTD: bit_size: 2 variants: - - name: Philips - description: I2S Philips standard - value: 0 - - name: MSB - description: MSB justified standard - value: 1 - - name: LSB - description: LSB justified standard - value: 2 - - name: PCM - description: PCM standard - value: 3 + - name: Philips + description: I2S Philips standard + value: 0 + - name: MSB + description: MSB justified standard + value: 1 + - name: LSB + description: LSB justified standard + value: 2 + - name: PCM + description: PCM standard + value: 3 enum/LSBFIRST: bit_size: 1 variants: - - name: MSBFirst - description: Data is transmitted/received with the MSB first - value: 0 - - name: LSBFirst - description: Data is transmitted/received with the LSB first - value: 1 + - name: MSBFirst + description: Data is transmitted/received with the MSB first + value: 0 + - name: LSBFirst + description: Data is transmitted/received with the LSB first + value: 1 enum/MSTR: bit_size: 1 variants: - - name: Slave - description: Slave configuration - value: 0 - - name: Master - description: Master configuration - value: 1 + - name: Slave + description: Slave configuration + value: 0 + - name: Master + description: Master configuration + value: 1 enum/ODD: bit_size: 1 variants: - - name: Even - description: Real divider value is I2SDIV * 2 - value: 0 - - name: Odd - description: Real divider value is (I2SDIV * 2) + 1 - value: 1 + - name: Even + description: Real divider value is I2SDIV * 2 + value: 0 + - name: Odd + description: Real divider value is (I2SDIV * 2) + 1 + value: 1 enum/PCMSYNC: bit_size: 1 variants: - - name: Short - description: Short frame synchronisation - value: 0 - - name: Long - description: Long frame synchronisation - value: 1 + - name: Short + description: Short frame synchronisation + value: 0 + - name: Long + description: Long frame synchronisation + value: 1 enum/RXONLY: bit_size: 1 variants: - - name: FullDuplex - description: Full duplex (Transmit and receive) - value: 0 - - name: OutputDisabled - description: Output disabled (Receive-only mode) - value: 1 + - name: FullDuplex + description: Full duplex (Transmit and receive) + value: 0 + - name: OutputDisabled + description: Output disabled (Receive-only mode) + value: 1 diff --git a/data/registers/spi_v1.yaml b/data/registers/spi_v1.yaml index 753a612..3e2d40d 100644 --- a/data/registers/spi_v1.yaml +++ b/data/registers/spi_v1.yaml @@ -1,472 +1,471 @@ ---- block/SPI: description: Serial peripheral interface items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2 - - name: SR - description: status register - byte_offset: 8 - fieldset: SR - - name: DR - description: data register - byte_offset: 12 - fieldset: DR - - name: CRCPR - description: CRC polynomial register - byte_offset: 16 - fieldset: CRCPR - - name: RXCRCR - description: RX CRC register - byte_offset: 20 - access: Read - fieldset: RXCRCR - - name: TXCRCR - description: TX CRC register - byte_offset: 24 - access: Read - fieldset: TXCRCR - - name: I2SCFGR - description: I2S configuration register - byte_offset: 28 - fieldset: I2SCFGR - - name: I2SPR - description: I2S prescaler register - byte_offset: 32 - fieldset: I2SPR + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: SR + description: status register + byte_offset: 8 + fieldset: SR + - name: DR + description: data register + byte_offset: 12 + fieldset: DR + - name: CRCPR + description: CRC polynomial register + byte_offset: 16 + fieldset: CRCPR + - name: RXCRCR + description: RX CRC register + byte_offset: 20 + access: Read + fieldset: RXCRCR + - name: TXCRCR + description: TX CRC register + byte_offset: 24 + access: Read + fieldset: TXCRCR + - name: I2SCFGR + description: I2S configuration register + byte_offset: 28 + fieldset: I2SCFGR + - name: I2SPR + description: I2S prescaler register + byte_offset: 32 + fieldset: I2SPR fieldset/CR1: description: control register 1 fields: - - name: CPHA - description: Clock phase - bit_offset: 0 - bit_size: 1 - enum: CPHA - - name: CPOL - description: Clock polarity - bit_offset: 1 - bit_size: 1 - enum: CPOL - - name: MSTR - description: Master selection - bit_offset: 2 - bit_size: 1 - enum: MSTR - - name: BR - description: Baud rate control - bit_offset: 3 - bit_size: 3 - enum: BR - - name: SPE - description: SPI enable - bit_offset: 6 - bit_size: 1 - - name: LSBFIRST - description: Frame format - bit_offset: 7 - bit_size: 1 - enum: LSBFIRST - - name: SSI - description: Internal slave select - bit_offset: 8 - bit_size: 1 - - name: SSM - description: Software slave management - bit_offset: 9 - bit_size: 1 - - name: RXONLY - description: Receive only - bit_offset: 10 - bit_size: 1 - enum: RXONLY - - name: DFF - description: Data frame format - bit_offset: 11 - bit_size: 1 - enum: DFF - - name: CRCNEXT - description: CRC transfer next - bit_offset: 12 - bit_size: 1 - enum: CRCNEXT - - name: CRCEN - description: Hardware CRC calculation enable - bit_offset: 13 - bit_size: 1 - - name: BIDIOE - description: Output enable in bidirectional mode - bit_offset: 14 - bit_size: 1 - enum: BIDIOE - - name: BIDIMODE - description: Bidirectional data mode enable - bit_offset: 15 - bit_size: 1 - enum: BIDIMODE + - name: CPHA + description: Clock phase + bit_offset: 0 + bit_size: 1 + enum: CPHA + - name: CPOL + description: Clock polarity + bit_offset: 1 + bit_size: 1 + enum: CPOL + - name: MSTR + description: Master selection + bit_offset: 2 + bit_size: 1 + enum: MSTR + - name: BR + description: Baud rate control + bit_offset: 3 + bit_size: 3 + enum: BR + - name: SPE + description: SPI enable + bit_offset: 6 + bit_size: 1 + - name: LSBFIRST + description: Frame format + bit_offset: 7 + bit_size: 1 + enum: LSBFIRST + - name: SSI + description: Internal slave select + bit_offset: 8 + bit_size: 1 + - name: SSM + description: Software slave management + bit_offset: 9 + bit_size: 1 + - name: RXONLY + description: Receive only + bit_offset: 10 + bit_size: 1 + enum: RXONLY + - name: DFF + description: Data frame format + bit_offset: 11 + bit_size: 1 + enum: DFF + - name: CRCNEXT + description: CRC transfer next + bit_offset: 12 + bit_size: 1 + enum: CRCNEXT + - name: CRCEN + description: Hardware CRC calculation enable + bit_offset: 13 + bit_size: 1 + - name: BIDIOE + description: Output enable in bidirectional mode + bit_offset: 14 + bit_size: 1 + enum: BIDIOE + - name: BIDIMODE + description: Bidirectional data mode enable + bit_offset: 15 + bit_size: 1 + enum: BIDIMODE fieldset/CR2: description: control register 2 fields: - - name: RXDMAEN - description: Rx buffer DMA enable - bit_offset: 0 - bit_size: 1 - - name: TXDMAEN - description: Tx buffer DMA enable - bit_offset: 1 - bit_size: 1 - - name: SSOE - description: SS output enable - bit_offset: 2 - bit_size: 1 - - name: FRF - description: Frame format - bit_offset: 4 - bit_size: 1 - enum: FRF - - name: ERRIE - description: Error interrupt enable - bit_offset: 5 - bit_size: 1 - - name: RXNEIE - description: RX buffer not empty interrupt enable - bit_offset: 6 - bit_size: 1 - - name: TXEIE - description: Tx buffer empty interrupt enable - bit_offset: 7 - bit_size: 1 + - name: RXDMAEN + description: Rx buffer DMA enable + bit_offset: 0 + bit_size: 1 + - name: TXDMAEN + description: Tx buffer DMA enable + bit_offset: 1 + bit_size: 1 + - name: SSOE + description: SS output enable + bit_offset: 2 + bit_size: 1 + - name: FRF + description: Frame format + bit_offset: 4 + bit_size: 1 + enum: FRF + - name: ERRIE + description: Error interrupt enable + bit_offset: 5 + bit_size: 1 + - name: RXNEIE + description: RX buffer not empty interrupt enable + bit_offset: 6 + bit_size: 1 + - name: TXEIE + description: Tx buffer empty interrupt enable + bit_offset: 7 + bit_size: 1 fieldset/CRCPR: description: CRC polynomial register fields: - - name: CRCPOLY - description: CRC polynomial register - bit_offset: 0 - bit_size: 16 + - name: CRCPOLY + description: CRC polynomial register + bit_offset: 0 + bit_size: 16 fieldset/DR: description: data register fields: - - name: DR - description: Data register - bit_offset: 0 - bit_size: 16 + - name: DR + description: Data register + bit_offset: 0 + bit_size: 16 fieldset/I2SCFGR: description: I2S configuration register fields: - - name: CHLEN - description: Channel length (number of bits per audio channel) - bit_offset: 0 - bit_size: 1 - enum: CHLEN - - name: DATLEN - description: Data length to be transferred - bit_offset: 1 - bit_size: 2 - enum: DATLEN - - name: CKPOL - description: Steady state clock polarity - bit_offset: 3 - bit_size: 1 - enum: CKPOL - - name: I2SSTD - description: I2S standard selection - bit_offset: 4 - bit_size: 2 - enum: I2SSTD - - name: PCMSYNC - description: PCM frame synchronization - bit_offset: 7 - bit_size: 1 - enum: PCMSYNC - - name: I2SCFG - description: I2S configuration mode - bit_offset: 8 - bit_size: 2 - enum: I2SCFG - - name: I2SE - description: I2S Enable - bit_offset: 10 - bit_size: 1 - - name: I2SMOD - description: I2S mode selection - bit_offset: 11 - bit_size: 1 + - name: CHLEN + description: Channel length (number of bits per audio channel) + bit_offset: 0 + bit_size: 1 + enum: CHLEN + - name: DATLEN + description: Data length to be transferred + bit_offset: 1 + bit_size: 2 + enum: DATLEN + - name: CKPOL + description: Steady state clock polarity + bit_offset: 3 + bit_size: 1 + enum: CKPOL + - name: I2SSTD + description: I2S standard selection + bit_offset: 4 + bit_size: 2 + enum: I2SSTD + - name: PCMSYNC + description: PCM frame synchronization + bit_offset: 7 + bit_size: 1 + enum: PCMSYNC + - name: I2SCFG + description: I2S configuration mode + bit_offset: 8 + bit_size: 2 + enum: I2SCFG + - name: I2SE + description: I2S Enable + bit_offset: 10 + bit_size: 1 + - name: I2SMOD + description: I2S mode selection + bit_offset: 11 + bit_size: 1 fieldset/I2SPR: description: I2S prescaler register fields: - - name: I2SDIV - description: I2S Linear prescaler - bit_offset: 0 - bit_size: 8 - - name: ODD - description: Odd factor for the prescaler - bit_offset: 8 - bit_size: 1 - enum: ODD - - name: MCKOE - description: Master clock output enable - bit_offset: 9 - bit_size: 1 + - name: I2SDIV + description: I2S Linear prescaler + bit_offset: 0 + bit_size: 8 + - name: ODD + description: Odd factor for the prescaler + bit_offset: 8 + bit_size: 1 + enum: ODD + - name: MCKOE + description: Master clock output enable + bit_offset: 9 + bit_size: 1 fieldset/RXCRCR: description: RX CRC register fields: - - name: RxCRC - description: Rx CRC register - bit_offset: 0 - bit_size: 16 + - name: RxCRC + description: Rx CRC register + bit_offset: 0 + bit_size: 16 fieldset/SR: description: status register fields: - - name: RXNE - description: Receive buffer not empty - bit_offset: 0 - bit_size: 1 - - name: TXE - description: Transmit buffer empty - bit_offset: 1 - bit_size: 1 - - name: CHSIDE - description: Channel side - bit_offset: 2 - bit_size: 1 - enum: CHSIDE - - name: UDR - description: Underrun flag - bit_offset: 3 - bit_size: 1 - - name: CRCERR - description: CRC error flag - bit_offset: 4 - bit_size: 1 - - name: MODF - description: Mode fault - bit_offset: 5 - bit_size: 1 - - name: OVR - description: Overrun flag - bit_offset: 6 - bit_size: 1 - - name: BSY - description: Busy flag - bit_offset: 7 - bit_size: 1 - - name: FRE - description: TI frame format error - bit_offset: 8 - bit_size: 1 + - name: RXNE + description: Receive buffer not empty + bit_offset: 0 + bit_size: 1 + - name: TXE + description: Transmit buffer empty + bit_offset: 1 + bit_size: 1 + - name: CHSIDE + description: Channel side + bit_offset: 2 + bit_size: 1 + enum: CHSIDE + - name: UDR + description: Underrun flag + bit_offset: 3 + bit_size: 1 + - name: CRCERR + description: CRC error flag + bit_offset: 4 + bit_size: 1 + - name: MODF + description: Mode fault + bit_offset: 5 + bit_size: 1 + - name: OVR + description: Overrun flag + bit_offset: 6 + bit_size: 1 + - name: BSY + description: Busy flag + bit_offset: 7 + bit_size: 1 + - name: FRE + description: TI frame format error + bit_offset: 8 + bit_size: 1 fieldset/TXCRCR: description: TX CRC register fields: - - name: TxCRC - description: Tx CRC register - bit_offset: 0 - bit_size: 16 + - name: TxCRC + description: Tx CRC register + bit_offset: 0 + bit_size: 16 enum/BIDIMODE: bit_size: 1 variants: - - name: Unidirectional - description: 2-line unidirectional data mode selected - value: 0 - - name: Bidirectional - description: 1-line bidirectional data mode selected - value: 1 + - name: Unidirectional + description: 2-line unidirectional data mode selected + value: 0 + - name: Bidirectional + description: 1-line bidirectional data mode selected + value: 1 enum/BIDIOE: bit_size: 1 variants: - - name: OutputDisabled - description: Output disabled (receive-only mode) - value: 0 - - name: OutputEnabled - description: Output enabled (transmit-only mode) - value: 1 + - name: OutputDisabled + description: Output disabled (receive-only mode) + value: 0 + - name: OutputEnabled + description: Output enabled (transmit-only mode) + value: 1 enum/BR: bit_size: 3 variants: - - name: Div2 - description: f_PCLK / 2 - value: 0 - - name: Div4 - description: f_PCLK / 4 - value: 1 - - name: Div8 - description: f_PCLK / 8 - value: 2 - - name: Div16 - description: f_PCLK / 16 - value: 3 - - name: Div32 - description: f_PCLK / 32 - value: 4 - - name: Div64 - description: f_PCLK / 64 - value: 5 - - name: Div128 - description: f_PCLK / 128 - value: 6 - - name: Div256 - description: f_PCLK / 256 - value: 7 + - name: Div2 + description: f_PCLK / 2 + value: 0 + - name: Div4 + description: f_PCLK / 4 + value: 1 + - name: Div8 + description: f_PCLK / 8 + value: 2 + - name: Div16 + description: f_PCLK / 16 + value: 3 + - name: Div32 + description: f_PCLK / 32 + value: 4 + - name: Div64 + description: f_PCLK / 64 + value: 5 + - name: Div128 + description: f_PCLK / 128 + value: 6 + - name: Div256 + description: f_PCLK / 256 + value: 7 enum/CHLEN: bit_size: 1 variants: - - name: SixteenBit - description: 16-bit wide - value: 0 - - name: ThirtyTwoBit - description: 32-bit wide - value: 1 + - name: SixteenBit + description: 16-bit wide + value: 0 + - name: ThirtyTwoBit + description: 32-bit wide + value: 1 enum/CHSIDE: bit_size: 1 variants: - - name: Left - description: Channel left has to be transmitted or has been received - value: 0 - - name: Right - description: Channel right has to be transmitted or has been received - value: 1 + - name: Left + description: Channel left has to be transmitted or has been received + value: 0 + - name: Right + description: Channel right has to be transmitted or has been received + value: 1 enum/CKPOL: bit_size: 1 variants: - - name: IdleLow - description: I2S clock inactive state is low level - value: 0 - - name: IdleHigh - description: I2S clock inactive state is high level - value: 1 + - name: IdleLow + description: I2S clock inactive state is low level + value: 0 + - name: IdleHigh + description: I2S clock inactive state is high level + value: 1 enum/CPHA: bit_size: 1 variants: - - name: FirstEdge - description: The first clock transition is the first data capture edge - value: 0 - - name: SecondEdge - description: The second clock transition is the first data capture edge - value: 1 + - name: FirstEdge + description: The first clock transition is the first data capture edge + value: 0 + - name: SecondEdge + description: The second clock transition is the first data capture edge + value: 1 enum/CPOL: bit_size: 1 variants: - - name: IdleLow - description: CK to 0 when idle - value: 0 - - name: IdleHigh - description: CK to 1 when idle - value: 1 + - name: IdleLow + description: CK to 0 when idle + value: 0 + - name: IdleHigh + description: CK to 1 when idle + value: 1 enum/CRCNEXT: bit_size: 1 variants: - - name: TxBuffer - description: Next transmit value is from Tx buffer - value: 0 - - name: CRC - description: Next transmit value is from Tx CRC register - value: 1 + - name: TxBuffer + description: Next transmit value is from Tx buffer + value: 0 + - name: CRC + description: Next transmit value is from Tx CRC register + value: 1 enum/DATLEN: bit_size: 2 variants: - - name: SixteenBit - description: 16-bit data length - value: 0 - - name: TwentyFourBit - description: 24-bit data length - value: 1 - - name: ThirtyTwoBit - description: 32-bit data length - value: 2 + - name: SixteenBit + description: 16-bit data length + value: 0 + - name: TwentyFourBit + description: 24-bit data length + value: 1 + - name: ThirtyTwoBit + description: 32-bit data length + value: 2 enum/DFF: bit_size: 1 variants: - - name: EightBit - description: 8-bit data frame format is selected for transmission/reception - value: 0 - - name: SixteenBit - description: 16-bit data frame format is selected for transmission/reception - value: 1 + - name: EightBit + description: 8-bit data frame format is selected for transmission/reception + value: 0 + - name: SixteenBit + description: 16-bit data frame format is selected for transmission/reception + value: 1 enum/FRF: bit_size: 1 variants: - - name: Motorola - description: SPI Motorola mode - value: 0 - - name: TI - description: SPI TI mode - value: 1 + - name: Motorola + description: SPI Motorola mode + value: 0 + - name: TI + description: SPI TI mode + value: 1 enum/I2SCFG: bit_size: 2 variants: - - name: SlaveTx - description: Slave - transmit - value: 0 - - name: SlaveRx - description: Slave - receive - value: 1 - - name: MasterTx - description: Master - transmit - value: 2 - - name: MasterRx - description: Master - receive - value: 3 + - name: SlaveTx + description: Slave - transmit + value: 0 + - name: SlaveRx + description: Slave - receive + value: 1 + - name: MasterTx + description: Master - transmit + value: 2 + - name: MasterRx + description: Master - receive + value: 3 enum/I2SSTD: bit_size: 2 variants: - - name: Philips - description: I2S Philips standard - value: 0 - - name: MSB - description: MSB justified standard - value: 1 - - name: LSB - description: LSB justified standard - value: 2 - - name: PCM - description: PCM standard - value: 3 + - name: Philips + description: I2S Philips standard + value: 0 + - name: MSB + description: MSB justified standard + value: 1 + - name: LSB + description: LSB justified standard + value: 2 + - name: PCM + description: PCM standard + value: 3 enum/LSBFIRST: bit_size: 1 variants: - - name: MSBFirst - description: Data is transmitted/received with the MSB first - value: 0 - - name: LSBFirst - description: Data is transmitted/received with the LSB first - value: 1 + - name: MSBFirst + description: Data is transmitted/received with the MSB first + value: 0 + - name: LSBFirst + description: Data is transmitted/received with the LSB first + value: 1 enum/MSTR: bit_size: 1 variants: - - name: Slave - description: Slave configuration - value: 0 - - name: Master - description: Master configuration - value: 1 + - name: Slave + description: Slave configuration + value: 0 + - name: Master + description: Master configuration + value: 1 enum/ODD: bit_size: 1 variants: - - name: Even - description: Real divider value is I2SDIV * 2 - value: 0 - - name: Odd - description: Real divider value is (I2SDIV * 2) + 1 - value: 1 + - name: Even + description: Real divider value is I2SDIV * 2 + value: 0 + - name: Odd + description: Real divider value is (I2SDIV * 2) + 1 + value: 1 enum/PCMSYNC: bit_size: 1 variants: - - name: Short - description: Short frame synchronisation - value: 0 - - name: Long - description: Long frame synchronisation - value: 1 + - name: Short + description: Short frame synchronisation + value: 0 + - name: Long + description: Long frame synchronisation + value: 1 enum/RXONLY: bit_size: 1 variants: - - name: FullDuplex - description: Full duplex (Transmit and receive) - value: 0 - - name: OutputDisabled - description: Output disabled (Receive-only mode) - value: 1 + - name: FullDuplex + description: Full duplex (Transmit and receive) + value: 0 + - name: OutputDisabled + description: Output disabled (Receive-only mode) + value: 1 diff --git a/data/registers/spi_v2.yaml b/data/registers/spi_v2.yaml index f0c5bc5..625e39b 100644 --- a/data/registers/spi_v2.yaml +++ b/data/registers/spi_v2.yaml @@ -1,639 +1,638 @@ ---- block/SPI: description: Serial peripheral interface items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2 - - name: SR - description: status register - byte_offset: 8 - fieldset: SR - - name: DR - description: data register - byte_offset: 12 - fieldset: DR - - name: CRCPR - description: CRC polynomial register - byte_offset: 16 - fieldset: CRCPR - - name: RXCRCR - description: RX CRC register - byte_offset: 20 - access: Read - fieldset: RXCRCR - - name: TXCRCR - description: TX CRC register - byte_offset: 24 - access: Read - fieldset: TXCRCR - - name: I2SCFGR - description: I2S configuration register - byte_offset: 28 - fieldset: I2SCFGR - - name: I2SPR - description: I2S prescaler register - byte_offset: 32 - fieldset: I2SPR + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: SR + description: status register + byte_offset: 8 + fieldset: SR + - name: DR + description: data register + byte_offset: 12 + fieldset: DR + - name: CRCPR + description: CRC polynomial register + byte_offset: 16 + fieldset: CRCPR + - name: RXCRCR + description: RX CRC register + byte_offset: 20 + access: Read + fieldset: RXCRCR + - name: TXCRCR + description: TX CRC register + byte_offset: 24 + access: Read + fieldset: TXCRCR + - name: I2SCFGR + description: I2S configuration register + byte_offset: 28 + fieldset: I2SCFGR + - name: I2SPR + description: I2S prescaler register + byte_offset: 32 + fieldset: I2SPR fieldset/CR1: description: control register 1 fields: - - name: CPHA - description: Clock phase - bit_offset: 0 - bit_size: 1 - enum: CPHA - - name: CPOL - description: Clock polarity - bit_offset: 1 - bit_size: 1 - enum: CPOL - - name: MSTR - description: Master selection - bit_offset: 2 - bit_size: 1 - enum: MSTR - - name: BR - description: Baud rate control - bit_offset: 3 - bit_size: 3 - enum: BR - - name: SPE - description: SPI enable - bit_offset: 6 - bit_size: 1 - - name: LSBFIRST - description: Frame format - bit_offset: 7 - bit_size: 1 - enum: LSBFIRST - - name: SSI - description: Internal slave select - bit_offset: 8 - bit_size: 1 - - name: SSM - description: Software slave management - bit_offset: 9 - bit_size: 1 - - name: RXONLY - description: Receive only - bit_offset: 10 - bit_size: 1 - enum: RXONLY - - name: CRCL - description: CRC length - bit_offset: 11 - bit_size: 1 - enum: CRCL - - name: CRCNEXT - description: CRC transfer next - bit_offset: 12 - bit_size: 1 - enum: CRCNEXT - - name: CRCEN - description: Hardware CRC calculation enable - bit_offset: 13 - bit_size: 1 - - name: BIDIOE - description: Output enable in bidirectional mode - bit_offset: 14 - bit_size: 1 - enum: BIDIOE - - name: BIDIMODE - description: Bidirectional data mode enable - bit_offset: 15 - bit_size: 1 - enum: BIDIMODE + - name: CPHA + description: Clock phase + bit_offset: 0 + bit_size: 1 + enum: CPHA + - name: CPOL + description: Clock polarity + bit_offset: 1 + bit_size: 1 + enum: CPOL + - name: MSTR + description: Master selection + bit_offset: 2 + bit_size: 1 + enum: MSTR + - name: BR + description: Baud rate control + bit_offset: 3 + bit_size: 3 + enum: BR + - name: SPE + description: SPI enable + bit_offset: 6 + bit_size: 1 + - name: LSBFIRST + description: Frame format + bit_offset: 7 + bit_size: 1 + enum: LSBFIRST + - name: SSI + description: Internal slave select + bit_offset: 8 + bit_size: 1 + - name: SSM + description: Software slave management + bit_offset: 9 + bit_size: 1 + - name: RXONLY + description: Receive only + bit_offset: 10 + bit_size: 1 + enum: RXONLY + - name: CRCL + description: CRC length + bit_offset: 11 + bit_size: 1 + enum: CRCL + - name: CRCNEXT + description: CRC transfer next + bit_offset: 12 + bit_size: 1 + enum: CRCNEXT + - name: CRCEN + description: Hardware CRC calculation enable + bit_offset: 13 + bit_size: 1 + - name: BIDIOE + description: Output enable in bidirectional mode + bit_offset: 14 + bit_size: 1 + enum: BIDIOE + - name: BIDIMODE + description: Bidirectional data mode enable + bit_offset: 15 + bit_size: 1 + enum: BIDIMODE fieldset/CR2: description: control register 2 fields: - - name: RXDMAEN - description: Rx buffer DMA enable - bit_offset: 0 - bit_size: 1 - - name: TXDMAEN - description: Tx buffer DMA enable - bit_offset: 1 - bit_size: 1 - - name: SSOE - description: SS output enable - bit_offset: 2 - bit_size: 1 - - name: NSSP - description: NSS pulse management - bit_offset: 3 - bit_size: 1 - - name: FRF - description: Frame format - bit_offset: 4 - bit_size: 1 - enum: FRF - - name: ERRIE - description: Error interrupt enable - bit_offset: 5 - bit_size: 1 - - name: RXNEIE - description: RX buffer not empty interrupt enable - bit_offset: 6 - bit_size: 1 - - name: TXEIE - description: Tx buffer empty interrupt enable - bit_offset: 7 - bit_size: 1 - - name: DS - description: Data size - bit_offset: 8 - bit_size: 4 - enum: DS - - name: FRXTH - description: FIFO reception threshold - bit_offset: 12 - bit_size: 1 - enum: FRXTH - - name: LDMA_RX - description: Last DMA transfer for reception - bit_offset: 13 - bit_size: 1 - enum: LDMA_RX - - name: LDMA_TX - description: Last DMA transfer for transmission - bit_offset: 14 - bit_size: 1 - enum: LDMA_TX + - name: RXDMAEN + description: Rx buffer DMA enable + bit_offset: 0 + bit_size: 1 + - name: TXDMAEN + description: Tx buffer DMA enable + bit_offset: 1 + bit_size: 1 + - name: SSOE + description: SS output enable + bit_offset: 2 + bit_size: 1 + - name: NSSP + description: NSS pulse management + bit_offset: 3 + bit_size: 1 + - name: FRF + description: Frame format + bit_offset: 4 + bit_size: 1 + enum: FRF + - name: ERRIE + description: Error interrupt enable + bit_offset: 5 + bit_size: 1 + - name: RXNEIE + description: RX buffer not empty interrupt enable + bit_offset: 6 + bit_size: 1 + - name: TXEIE + description: Tx buffer empty interrupt enable + bit_offset: 7 + bit_size: 1 + - name: DS + description: Data size + bit_offset: 8 + bit_size: 4 + enum: DS + - name: FRXTH + description: FIFO reception threshold + bit_offset: 12 + bit_size: 1 + enum: FRXTH + - name: LDMA_RX + description: Last DMA transfer for reception + bit_offset: 13 + bit_size: 1 + enum: LDMA_RX + - name: LDMA_TX + description: Last DMA transfer for transmission + bit_offset: 14 + bit_size: 1 + enum: LDMA_TX fieldset/CRCPR: description: CRC polynomial register fields: - - name: CRCPOLY - description: CRC polynomial register - bit_offset: 0 - bit_size: 16 + - name: CRCPOLY + description: CRC polynomial register + bit_offset: 0 + bit_size: 16 fieldset/DR: description: data register fields: - - name: DR - description: Data register - bit_offset: 0 - bit_size: 16 + - name: DR + description: Data register + bit_offset: 0 + bit_size: 16 fieldset/I2SCFGR: description: I2S configuration register fields: - - name: CHLEN - description: Channel length (number of bits per audio channel) - bit_offset: 0 - bit_size: 1 - enum: CHLEN - - name: DATLEN - description: Data length to be transferred - bit_offset: 1 - bit_size: 2 - enum: DATLEN - - name: CKPOL - description: Steady state clock polarity - bit_offset: 3 - bit_size: 1 - enum: CKPOL - - name: I2SSTD - description: I2S standard selection - bit_offset: 4 - bit_size: 2 - enum: ISSTD - - name: PCMSYNC - description: PCM frame synchronization - bit_offset: 7 - bit_size: 1 - enum: PCMSYNC - - name: I2SCFG - description: I2S configuration mode - bit_offset: 8 - bit_size: 2 - enum: ISCFG - - name: I2SE - description: I2S Enable - bit_offset: 10 - bit_size: 1 - enum: ISE - - name: I2SMOD - description: I2S mode selection - bit_offset: 11 - bit_size: 1 - enum: ISMOD - - name: ASTRTEN - description: Asynchronous start enable - bit_offset: 12 - bit_size: 1 + - name: CHLEN + description: Channel length (number of bits per audio channel) + bit_offset: 0 + bit_size: 1 + enum: CHLEN + - name: DATLEN + description: Data length to be transferred + bit_offset: 1 + bit_size: 2 + enum: DATLEN + - name: CKPOL + description: Steady state clock polarity + bit_offset: 3 + bit_size: 1 + enum: CKPOL + - name: I2SSTD + description: I2S standard selection + bit_offset: 4 + bit_size: 2 + enum: ISSTD + - name: PCMSYNC + description: PCM frame synchronization + bit_offset: 7 + bit_size: 1 + enum: PCMSYNC + - name: I2SCFG + description: I2S configuration mode + bit_offset: 8 + bit_size: 2 + enum: ISCFG + - name: I2SE + description: I2S Enable + bit_offset: 10 + bit_size: 1 + enum: ISE + - name: I2SMOD + description: I2S mode selection + bit_offset: 11 + bit_size: 1 + enum: ISMOD + - name: ASTRTEN + description: Asynchronous start enable + bit_offset: 12 + bit_size: 1 fieldset/I2SPR: description: I2S prescaler register fields: - - name: I2SDIV - description: I2S Linear prescaler - bit_offset: 0 - bit_size: 8 - - name: ODD - description: Odd factor for the prescaler - bit_offset: 8 - bit_size: 1 - enum: ODD - - name: MCKOE - description: Master clock output enable - bit_offset: 9 - bit_size: 1 - enum: MCKOE + - name: I2SDIV + description: I2S Linear prescaler + bit_offset: 0 + bit_size: 8 + - name: ODD + description: Odd factor for the prescaler + bit_offset: 8 + bit_size: 1 + enum: ODD + - name: MCKOE + description: Master clock output enable + bit_offset: 9 + bit_size: 1 + enum: MCKOE fieldset/RXCRCR: description: RX CRC register fields: - - name: RxCRC - description: Rx CRC register - bit_offset: 0 - bit_size: 16 + - name: RxCRC + description: Rx CRC register + bit_offset: 0 + bit_size: 16 fieldset/SR: description: status register fields: - - name: RXNE - description: Receive buffer not empty - bit_offset: 0 - bit_size: 1 - - name: TXE - description: Transmit buffer empty - bit_offset: 1 - bit_size: 1 - - name: CHSIDE - description: Channel side - bit_offset: 2 - bit_size: 1 - enum: CHSIDE - - name: UDR - description: Underrun flag - bit_offset: 3 - bit_size: 1 - - name: CRCERR - description: CRC error flag - bit_offset: 4 - bit_size: 1 - - name: MODF - description: Mode fault - bit_offset: 5 - bit_size: 1 - - name: OVR - description: Overrun flag - bit_offset: 6 - bit_size: 1 - - name: BSY - description: Busy flag - bit_offset: 7 - bit_size: 1 - - name: FRE - description: frame format error - bit_offset: 8 - bit_size: 1 - - name: FRLVL - description: FIFO reception level - bit_offset: 9 - bit_size: 2 - enum: FRLVL - - name: FTLVL - description: FIFO Transmission Level - bit_offset: 11 - bit_size: 2 - enum: FTLVL + - name: RXNE + description: Receive buffer not empty + bit_offset: 0 + bit_size: 1 + - name: TXE + description: Transmit buffer empty + bit_offset: 1 + bit_size: 1 + - name: CHSIDE + description: Channel side + bit_offset: 2 + bit_size: 1 + enum: CHSIDE + - name: UDR + description: Underrun flag + bit_offset: 3 + bit_size: 1 + - name: CRCERR + description: CRC error flag + bit_offset: 4 + bit_size: 1 + - name: MODF + description: Mode fault + bit_offset: 5 + bit_size: 1 + - name: OVR + description: Overrun flag + bit_offset: 6 + bit_size: 1 + - name: BSY + description: Busy flag + bit_offset: 7 + bit_size: 1 + - name: FRE + description: frame format error + bit_offset: 8 + bit_size: 1 + - name: FRLVL + description: FIFO reception level + bit_offset: 9 + bit_size: 2 + enum: FRLVL + - name: FTLVL + description: FIFO Transmission Level + bit_offset: 11 + bit_size: 2 + enum: FTLVL fieldset/TXCRCR: description: TX CRC register fields: - - name: TxCRC - description: Tx CRC register - bit_offset: 0 - bit_size: 16 + - name: TxCRC + description: Tx CRC register + bit_offset: 0 + bit_size: 16 enum/BIDIMODE: bit_size: 1 variants: - - name: Unidirectional - description: 2-line unidirectional data mode selected - value: 0 - - name: Bidirectional - description: 1-line bidirectional data mode selected - value: 1 + - name: Unidirectional + description: 2-line unidirectional data mode selected + value: 0 + - name: Bidirectional + description: 1-line bidirectional data mode selected + value: 1 enum/BIDIOE: bit_size: 1 variants: - - name: OutputDisabled - description: Output disabled (receive-only mode) - value: 0 - - name: OutputEnabled - description: Output enabled (transmit-only mode) - value: 1 + - name: OutputDisabled + description: Output disabled (receive-only mode) + value: 0 + - name: OutputEnabled + description: Output enabled (transmit-only mode) + value: 1 enum/BR: bit_size: 3 variants: - - name: Div2 - description: f_PCLK / 2 - value: 0 - - name: Div4 - description: f_PCLK / 4 - value: 1 - - name: Div8 - description: f_PCLK / 8 - value: 2 - - name: Div16 - description: f_PCLK / 16 - value: 3 - - name: Div32 - description: f_PCLK / 32 - value: 4 - - name: Div64 - description: f_PCLK / 64 - value: 5 - - name: Div128 - description: f_PCLK / 128 - value: 6 - - name: Div256 - description: f_PCLK / 256 - value: 7 + - name: Div2 + description: f_PCLK / 2 + value: 0 + - name: Div4 + description: f_PCLK / 4 + value: 1 + - name: Div8 + description: f_PCLK / 8 + value: 2 + - name: Div16 + description: f_PCLK / 16 + value: 3 + - name: Div32 + description: f_PCLK / 32 + value: 4 + - name: Div64 + description: f_PCLK / 64 + value: 5 + - name: Div128 + description: f_PCLK / 128 + value: 6 + - name: Div256 + description: f_PCLK / 256 + value: 7 enum/CHLEN: bit_size: 1 variants: - - name: SixteenBit - description: 16-bit wide - value: 0 - - name: ThirtyTwoBit - description: 32-bit wide - value: 1 + - name: SixteenBit + description: 16-bit wide + value: 0 + - name: ThirtyTwoBit + description: 32-bit wide + value: 1 enum/CHSIDE: bit_size: 1 variants: - - name: Left - description: Channel left has to be transmitted or has been received - value: 0 - - name: Right - description: Channel right has to be transmitted or has been received - value: 1 + - name: Left + description: Channel left has to be transmitted or has been received + value: 0 + - name: Right + description: Channel right has to be transmitted or has been received + value: 1 enum/CKPOL: bit_size: 1 variants: - - name: IdleLow - description: I2S clock inactive state is low level - value: 0 - - name: IdleHigh - description: I2S clock inactive state is high level - value: 1 + - name: IdleLow + description: I2S clock inactive state is low level + value: 0 + - name: IdleHigh + description: I2S clock inactive state is high level + value: 1 enum/CPHA: bit_size: 1 variants: - - name: FirstEdge - description: The first clock transition is the first data capture edge - value: 0 - - name: SecondEdge - description: The second clock transition is the first data capture edge - value: 1 + - name: FirstEdge + description: The first clock transition is the first data capture edge + value: 0 + - name: SecondEdge + description: The second clock transition is the first data capture edge + value: 1 enum/CPOL: bit_size: 1 variants: - - name: IdleLow - description: CK to 0 when idle - value: 0 - - name: IdleHigh - description: CK to 1 when idle - value: 1 + - name: IdleLow + description: CK to 0 when idle + value: 0 + - name: IdleHigh + description: CK to 1 when idle + value: 1 enum/CRCL: bit_size: 1 variants: - - name: EightBit - description: 8-bit CRC length - value: 0 - - name: SixteenBit - description: 16-bit CRC length - value: 1 + - name: EightBit + description: 8-bit CRC length + value: 0 + - name: SixteenBit + description: 16-bit CRC length + value: 1 enum/CRCNEXT: bit_size: 1 variants: - - name: TxBuffer - description: Next transmit value is from Tx buffer - value: 0 - - name: CRC - description: Next transmit value is from Tx CRC register - value: 1 + - name: TxBuffer + description: Next transmit value is from Tx buffer + value: 0 + - name: CRC + description: Next transmit value is from Tx CRC register + value: 1 enum/DATLEN: bit_size: 2 variants: - - name: SixteenBit - description: 16-bit data length - value: 0 - - name: TwentyFourBit - description: 24-bit data length - value: 1 - - name: ThirtyTwoBit - description: 32-bit data length - value: 2 + - name: SixteenBit + description: 16-bit data length + value: 0 + - name: TwentyFourBit + description: 24-bit data length + value: 1 + - name: ThirtyTwoBit + description: 32-bit data length + value: 2 enum/DS: bit_size: 4 variants: - - name: FourBit - description: 4-bit - value: 3 - - name: FiveBit - description: 5-bit - value: 4 - - name: SixBit - description: 6-bit - value: 5 - - name: SevenBit - description: 7-bit - value: 6 - - name: EightBit - description: 8-bit - value: 7 - - name: NineBit - description: 9-bit - value: 8 - - name: TenBit - description: 10-bit - value: 9 - - name: ElevenBit - description: 11-bit - value: 10 - - name: TwelveBit - description: 12-bit - value: 11 - - name: ThirteenBit - description: 13-bit - value: 12 - - name: FourteenBit - description: 14-bit - value: 13 - - name: FifteenBit - description: 15-bit - value: 14 - - name: SixteenBit - description: 16-bit - value: 15 + - name: FourBit + description: 4-bit + value: 3 + - name: FiveBit + description: 5-bit + value: 4 + - name: SixBit + description: 6-bit + value: 5 + - name: SevenBit + description: 7-bit + value: 6 + - name: EightBit + description: 8-bit + value: 7 + - name: NineBit + description: 9-bit + value: 8 + - name: TenBit + description: 10-bit + value: 9 + - name: ElevenBit + description: 11-bit + value: 10 + - name: TwelveBit + description: 12-bit + value: 11 + - name: ThirteenBit + description: 13-bit + value: 12 + - name: FourteenBit + description: 14-bit + value: 13 + - name: FifteenBit + description: 15-bit + value: 14 + - name: SixteenBit + description: 16-bit + value: 15 enum/FRF: bit_size: 1 variants: - - name: Motorola - description: SPI Motorola mode - value: 0 - - name: TI - description: SPI TI mode - value: 1 + - name: Motorola + description: SPI Motorola mode + value: 0 + - name: TI + description: SPI TI mode + value: 1 enum/FRLVL: bit_size: 2 variants: - - name: Empty - description: Rx FIFO Empty - value: 0 - - name: Quarter - description: Rx 1/4 FIFO - value: 1 - - name: Half - description: Rx 1/2 FIFO - value: 2 - - name: Full - description: Rx FIFO full - value: 3 + - name: Empty + description: Rx FIFO Empty + value: 0 + - name: Quarter + description: Rx 1/4 FIFO + value: 1 + - name: Half + description: Rx 1/2 FIFO + value: 2 + - name: Full + description: Rx FIFO full + value: 3 enum/FRXTH: bit_size: 1 variants: - - name: Half - description: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) - value: 0 - - name: Quarter - description: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) - value: 1 + - name: Half + description: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) + value: 0 + - name: Quarter + description: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + value: 1 enum/FTLVL: bit_size: 2 variants: - - name: Empty - description: Tx FIFO Empty - value: 0 - - name: Quarter - description: Tx 1/4 FIFO - value: 1 - - name: Half - description: Tx 1/2 FIFO - value: 2 - - name: Full - description: Tx FIFO full - value: 3 + - name: Empty + description: Tx FIFO Empty + value: 0 + - name: Quarter + description: Tx 1/4 FIFO + value: 1 + - name: Half + description: Tx 1/2 FIFO + value: 2 + - name: Full + description: Tx FIFO full + value: 3 enum/ISCFG: bit_size: 2 variants: - - name: SlaveTx - description: Slave - transmit - value: 0 - - name: SlaveRx - description: Slave - receive - value: 1 - - name: MasterTx - description: Master - transmit - value: 2 - - name: MasterRx - description: Master - receive - value: 3 + - name: SlaveTx + description: Slave - transmit + value: 0 + - name: SlaveRx + description: Slave - receive + value: 1 + - name: MasterTx + description: Master - transmit + value: 2 + - name: MasterRx + description: Master - receive + value: 3 enum/ISE: bit_size: 1 variants: - - name: Disabled - description: I2S peripheral is disabled - value: 0 - - name: Enabled - description: I2S peripheral is enabled - value: 1 + - name: Disabled + description: I2S peripheral is disabled + value: 0 + - name: Enabled + description: I2S peripheral is enabled + value: 1 enum/ISMOD: bit_size: 1 variants: - - name: SPIMode - description: SPI mode is selected - value: 0 - - name: I2SMode - description: I2S mode is selected - value: 1 + - name: SPIMode + description: SPI mode is selected + value: 0 + - name: I2SMode + description: I2S mode is selected + value: 1 enum/ISSTD: bit_size: 2 variants: - - name: Philips - description: I2S Philips standard - value: 0 - - name: MSB - description: MSB justified standard - value: 1 - - name: LSB - description: LSB justified standard - value: 2 - - name: PCM - description: PCM standard - value: 3 + - name: Philips + description: I2S Philips standard + value: 0 + - name: MSB + description: MSB justified standard + value: 1 + - name: LSB + description: LSB justified standard + value: 2 + - name: PCM + description: PCM standard + value: 3 enum/LDMA_RX: bit_size: 1 variants: - - name: Even - description: Number of data to transfer for receive is even - value: 0 - - name: Odd - description: Number of data to transfer for receive is odd - value: 1 + - name: Even + description: Number of data to transfer for receive is even + value: 0 + - name: Odd + description: Number of data to transfer for receive is odd + value: 1 enum/LDMA_TX: bit_size: 1 variants: - - name: Even - description: Number of data to transfer for transmit is even - value: 0 - - name: Odd - description: Number of data to transfer for transmit is odd - value: 1 + - name: Even + description: Number of data to transfer for transmit is even + value: 0 + - name: Odd + description: Number of data to transfer for transmit is odd + value: 1 enum/LSBFIRST: bit_size: 1 variants: - - name: MSBFirst - description: Data is transmitted/received with the MSB first - value: 0 - - name: LSBFirst - description: Data is transmitted/received with the LSB first - value: 1 + - name: MSBFirst + description: Data is transmitted/received with the MSB first + value: 0 + - name: LSBFirst + description: Data is transmitted/received with the LSB first + value: 1 enum/MCKOE: bit_size: 1 variants: - - name: Disabled - description: Master clock output is disabled - value: 0 - - name: Enabled - description: Master clock output is enabled - value: 1 + - name: Disabled + description: Master clock output is disabled + value: 0 + - name: Enabled + description: Master clock output is enabled + value: 1 enum/MSTR: bit_size: 1 variants: - - name: Slave - description: Slave configuration - value: 0 - - name: Master - description: Master configuration - value: 1 + - name: Slave + description: Slave configuration + value: 0 + - name: Master + description: Master configuration + value: 1 enum/ODD: bit_size: 1 variants: - - name: Even - description: Real divider value is I2SDIV * 2 - value: 0 - - name: Odd - description: Real divider value is (I2SDIV * 2) + 1 - value: 1 + - name: Even + description: Real divider value is I2SDIV * 2 + value: 0 + - name: Odd + description: Real divider value is (I2SDIV * 2) + 1 + value: 1 enum/PCMSYNC: bit_size: 1 variants: - - name: Short - description: Short frame synchronisation - value: 0 - - name: Long - description: Long frame synchronisation - value: 1 + - name: Short + description: Short frame synchronisation + value: 0 + - name: Long + description: Long frame synchronisation + value: 1 enum/RXONLY: bit_size: 1 variants: - - name: FullDuplex - description: Full duplex (Transmit and receive) - value: 0 - - name: OutputDisabled - description: Output disabled (Receive-only mode) - value: 1 + - name: FullDuplex + description: Full duplex (Transmit and receive) + value: 0 + - name: OutputDisabled + description: Output disabled (Receive-only mode) + value: 1 diff --git a/data/registers/spi_v3.yaml b/data/registers/spi_v3.yaml index a1336e1..b0b7ce4 100644 --- a/data/registers/spi_v3.yaml +++ b/data/registers/spi_v3.yaml @@ -1,675 +1,674 @@ ---- block/SPI: description: Serial peripheral interface items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2 - - name: CFG1 - description: configuration register 1 - byte_offset: 8 - fieldset: CFG1 - - name: CFG2 - description: configuration register 2 - byte_offset: 12 - fieldset: CFG2 - - name: IER - description: Interrupt Enable Register - byte_offset: 16 - fieldset: IER - - name: SR - description: Status Register - byte_offset: 20 - access: Read - fieldset: SR - - name: IFCR - description: Interrupt/Status Flags Clear Register - byte_offset: 24 - access: Write - fieldset: IFCR - - name: TXDR - description: Transmit Data Register - byte_offset: 32 - access: Write - fieldset: TXDR - - name: RXDR - description: Receive Data Register - byte_offset: 48 - access: Read - fieldset: RXDR - - name: CRCPOLY - description: Polynomial Register - byte_offset: 64 - fieldset: CRCPOLY - - name: TXCRC - description: Transmitter CRC Register - byte_offset: 68 - fieldset: TXCRC - - name: RXCRC - description: Receiver CRC Register - byte_offset: 72 - fieldset: RXCRC - - name: UDRDR - description: Underrun Data Register - byte_offset: 76 - fieldset: UDRDR + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CFG1 + description: configuration register 1 + byte_offset: 8 + fieldset: CFG1 + - name: CFG2 + description: configuration register 2 + byte_offset: 12 + fieldset: CFG2 + - name: IER + description: Interrupt Enable Register + byte_offset: 16 + fieldset: IER + - name: SR + description: Status Register + byte_offset: 20 + access: Read + fieldset: SR + - name: IFCR + description: Interrupt/Status Flags Clear Register + byte_offset: 24 + access: Write + fieldset: IFCR + - name: TXDR + description: Transmit Data Register + byte_offset: 32 + access: Write + fieldset: TXDR + - name: RXDR + description: Receive Data Register + byte_offset: 48 + access: Read + fieldset: RXDR + - name: CRCPOLY + description: Polynomial Register + byte_offset: 64 + fieldset: CRCPOLY + - name: TXCRC + description: Transmitter CRC Register + byte_offset: 68 + fieldset: TXCRC + - name: RXCRC + description: Receiver CRC Register + byte_offset: 72 + fieldset: RXCRC + - name: UDRDR + description: Underrun Data Register + byte_offset: 76 + fieldset: UDRDR fieldset/CFG1: description: configuration register 1 fields: - - name: DSIZE - description: Number of bits in at single SPI data frame - bit_offset: 0 - bit_size: 5 - - name: FTHLV - description: threshold level - bit_offset: 5 - bit_size: 4 - enum: FTHLV - - name: UDRCFG - description: Behavior of slave transmitter at underrun condition - bit_offset: 9 - bit_size: 2 - enum: UDRCFG - - name: UDRDET - description: Detection of underrun condition at slave transmitter - bit_offset: 11 - bit_size: 2 - enum: UDRDET - - name: RXDMAEN - description: Rx DMA stream enable - bit_offset: 14 - bit_size: 1 - - name: TXDMAEN - description: Tx DMA stream enable - bit_offset: 15 - bit_size: 1 - - name: CRCSIZE - description: Length of CRC frame to be transacted and compared - bit_offset: 16 - bit_size: 5 - - name: CRCEN - description: Hardware CRC computation enable - bit_offset: 22 - bit_size: 1 - - name: MBR - description: Master baud rate - bit_offset: 28 - bit_size: 3 - enum: MBR + - name: DSIZE + description: Number of bits in at single SPI data frame + bit_offset: 0 + bit_size: 5 + - name: FTHLV + description: threshold level + bit_offset: 5 + bit_size: 4 + enum: FTHLV + - name: UDRCFG + description: Behavior of slave transmitter at underrun condition + bit_offset: 9 + bit_size: 2 + enum: UDRCFG + - name: UDRDET + description: Detection of underrun condition at slave transmitter + bit_offset: 11 + bit_size: 2 + enum: UDRDET + - name: RXDMAEN + description: Rx DMA stream enable + bit_offset: 14 + bit_size: 1 + - name: TXDMAEN + description: Tx DMA stream enable + bit_offset: 15 + bit_size: 1 + - name: CRCSIZE + description: Length of CRC frame to be transacted and compared + bit_offset: 16 + bit_size: 5 + - name: CRCEN + description: Hardware CRC computation enable + bit_offset: 22 + bit_size: 1 + - name: MBR + description: Master baud rate + bit_offset: 28 + bit_size: 3 + enum: MBR fieldset/CFG2: description: configuration register 2 fields: - - name: MSSI - description: Master SS Idleness - bit_offset: 0 - bit_size: 4 - - name: MIDI - description: Master Inter-Data Idleness - bit_offset: 4 - bit_size: 4 - - name: IOSWP - description: Swap functionality of MISO and MOSI pins - bit_offset: 15 - bit_size: 1 - - name: COMM - description: SPI Communication Mode - bit_offset: 17 - bit_size: 2 - enum: COMM - - name: SP - description: Serial Protocol - bit_offset: 19 - bit_size: 3 - enum: SP - - name: MASTER - description: SPI Master - bit_offset: 22 - bit_size: 1 - enum: MASTER - - name: LSBFIRST - description: Data frame format - bit_offset: 23 - bit_size: 1 - enum: LSBFIRST - - name: CPHA - description: Clock phase - bit_offset: 24 - bit_size: 1 - enum: CPHA - - name: CPOL - description: Clock polarity - bit_offset: 25 - bit_size: 1 - enum: CPOL - - name: SSM - description: Software management of SS signal input - bit_offset: 26 - bit_size: 1 - - name: SSIOP - description: SS input/output polarity - bit_offset: 28 - bit_size: 1 - enum: SSIOP - - name: SSOE - description: SS output enable - bit_offset: 29 - bit_size: 1 - - name: SSOM - description: SS output management in master mode - bit_offset: 30 - bit_size: 1 - enum: SSOM - - name: AFCNTR - description: Alternate function GPIOs control - bit_offset: 31 - bit_size: 1 - enum: AFCNTR + - name: MSSI + description: Master SS Idleness + bit_offset: 0 + bit_size: 4 + - name: MIDI + description: Master Inter-Data Idleness + bit_offset: 4 + bit_size: 4 + - name: IOSWP + description: Swap functionality of MISO and MOSI pins + bit_offset: 15 + bit_size: 1 + - name: COMM + description: SPI Communication Mode + bit_offset: 17 + bit_size: 2 + enum: COMM + - name: SP + description: Serial Protocol + bit_offset: 19 + bit_size: 3 + enum: SP + - name: MASTER + description: SPI Master + bit_offset: 22 + bit_size: 1 + enum: MASTER + - name: LSBFIRST + description: Data frame format + bit_offset: 23 + bit_size: 1 + enum: LSBFIRST + - name: CPHA + description: Clock phase + bit_offset: 24 + bit_size: 1 + enum: CPHA + - name: CPOL + description: Clock polarity + bit_offset: 25 + bit_size: 1 + enum: CPOL + - name: SSM + description: Software management of SS signal input + bit_offset: 26 + bit_size: 1 + - name: SSIOP + description: SS input/output polarity + bit_offset: 28 + bit_size: 1 + enum: SSIOP + - name: SSOE + description: SS output enable + bit_offset: 29 + bit_size: 1 + - name: SSOM + description: SS output management in master mode + bit_offset: 30 + bit_size: 1 + enum: SSOM + - name: AFCNTR + description: Alternate function GPIOs control + bit_offset: 31 + bit_size: 1 + enum: AFCNTR fieldset/CR1: description: control register 1 fields: - - name: SPE - description: Serial Peripheral Enable - bit_offset: 0 - bit_size: 1 - - name: MASRX - description: Master automatic SUSP in Receive mode - bit_offset: 8 - bit_size: 1 - - name: CSTART - description: Master transfer start - bit_offset: 9 - bit_size: 1 - - name: CSUSP - description: Master SUSPend request - bit_offset: 10 - bit_size: 1 - - name: HDDIR - description: Rx/Tx direction at Half-duplex mode - bit_offset: 11 - bit_size: 1 - enum: HDDIR - - name: SSI - description: Internal SS signal input level - bit_offset: 12 - bit_size: 1 - - name: CRC33_17 - description: 32-bit CRC polynomial configuration - bit_offset: 13 - bit_size: 1 - enum: CRC_ - - name: RCRCINI - description: CRC calculation initialization pattern control for receiver - bit_offset: 14 - bit_size: 1 - enum: RCRCINI - - name: TCRCINI - description: CRC calculation initialization pattern control for transmitter - bit_offset: 15 - bit_size: 1 - enum: TCRCINI - - name: IOLOCK - description: Locking the AF configuration of associated IOs - bit_offset: 16 - bit_size: 1 + - name: SPE + description: Serial Peripheral Enable + bit_offset: 0 + bit_size: 1 + - name: MASRX + description: Master automatic SUSP in Receive mode + bit_offset: 8 + bit_size: 1 + - name: CSTART + description: Master transfer start + bit_offset: 9 + bit_size: 1 + - name: CSUSP + description: Master SUSPend request + bit_offset: 10 + bit_size: 1 + - name: HDDIR + description: Rx/Tx direction at Half-duplex mode + bit_offset: 11 + bit_size: 1 + enum: HDDIR + - name: SSI + description: Internal SS signal input level + bit_offset: 12 + bit_size: 1 + - name: CRC33_17 + description: 32-bit CRC polynomial configuration + bit_offset: 13 + bit_size: 1 + enum: CRC_ + - name: RCRCINI + description: CRC calculation initialization pattern control for receiver + bit_offset: 14 + bit_size: 1 + enum: RCRCINI + - name: TCRCINI + description: CRC calculation initialization pattern control for transmitter + bit_offset: 15 + bit_size: 1 + enum: TCRCINI + - name: IOLOCK + description: Locking the AF configuration of associated IOs + bit_offset: 16 + bit_size: 1 fieldset/CR2: description: control register 2 fields: - - name: TSIZE - description: Number of data at current transfer - bit_offset: 0 - bit_size: 16 - - name: TSER - description: Number of data transfer extension to be reload into TSIZE just when a previous - bit_offset: 16 - bit_size: 16 + - name: TSIZE + description: Number of data at current transfer + bit_offset: 0 + bit_size: 16 + - name: TSER + description: Number of data transfer extension to be reload into TSIZE just when a previous + bit_offset: 16 + bit_size: 16 fieldset/CRCPOLY: description: Polynomial Register fields: - - name: CRCPOLY - description: CRC polynomial register - bit_offset: 0 - bit_size: 32 + - name: CRCPOLY + description: CRC polynomial register + bit_offset: 0 + bit_size: 32 fieldset/IER: description: Interrupt Enable Register fields: - - name: RXPIE - description: RXP Interrupt Enable - bit_offset: 0 - bit_size: 1 - - name: TXPIE - description: TXP interrupt enable - bit_offset: 1 - bit_size: 1 - - name: DXPIE - description: DXP interrupt enabled - bit_offset: 2 - bit_size: 1 - - name: EOTIE - description: "EOT, SUSP and TXC interrupt enable" - bit_offset: 3 - bit_size: 1 - - name: TXTFIE - description: TXTFIE interrupt enable - bit_offset: 4 - bit_size: 1 - - name: UDRIE - description: UDR interrupt enable - bit_offset: 5 - bit_size: 1 - - name: OVRIE - description: OVR interrupt enable - bit_offset: 6 - bit_size: 1 - - name: CRCEIE - description: CRC Interrupt enable - bit_offset: 7 - bit_size: 1 - - name: TIFREIE - description: TIFRE interrupt enable - bit_offset: 8 - bit_size: 1 - - name: MODFIE - description: Mode Fault interrupt enable - bit_offset: 9 - bit_size: 1 - - name: TSERFIE - description: Additional number of transactions reload interrupt enable - bit_offset: 10 - bit_size: 1 + - name: RXPIE + description: RXP Interrupt Enable + bit_offset: 0 + bit_size: 1 + - name: TXPIE + description: TXP interrupt enable + bit_offset: 1 + bit_size: 1 + - name: DXPIE + description: DXP interrupt enabled + bit_offset: 2 + bit_size: 1 + - name: EOTIE + description: EOT, SUSP and TXC interrupt enable + bit_offset: 3 + bit_size: 1 + - name: TXTFIE + description: TXTFIE interrupt enable + bit_offset: 4 + bit_size: 1 + - name: UDRIE + description: UDR interrupt enable + bit_offset: 5 + bit_size: 1 + - name: OVRIE + description: OVR interrupt enable + bit_offset: 6 + bit_size: 1 + - name: CRCEIE + description: CRC Interrupt enable + bit_offset: 7 + bit_size: 1 + - name: TIFREIE + description: TIFRE interrupt enable + bit_offset: 8 + bit_size: 1 + - name: MODFIE + description: Mode Fault interrupt enable + bit_offset: 9 + bit_size: 1 + - name: TSERFIE + description: Additional number of transactions reload interrupt enable + bit_offset: 10 + bit_size: 1 fieldset/IFCR: description: Interrupt/Status Flags Clear Register fields: - - name: EOTC - description: End Of Transfer flag clear - bit_offset: 3 - bit_size: 1 - - name: TXTFC - description: Transmission Transfer Filled flag clear - bit_offset: 4 - bit_size: 1 - - name: UDRC - description: Underrun flag clear - bit_offset: 5 - bit_size: 1 - - name: OVRC - description: Overrun flag clear - bit_offset: 6 - bit_size: 1 - - name: CRCEC - description: CRC Error flag clear - bit_offset: 7 - bit_size: 1 - - name: TIFREC - description: TI frame format error flag clear - bit_offset: 8 - bit_size: 1 - - name: MODFC - description: Mode Fault flag clear - bit_offset: 9 - bit_size: 1 - - name: TSERFC - description: TSERFC flag clear - bit_offset: 10 - bit_size: 1 - - name: SUSPC - description: SUSPend flag clear - bit_offset: 11 - bit_size: 1 + - name: EOTC + description: End Of Transfer flag clear + bit_offset: 3 + bit_size: 1 + - name: TXTFC + description: Transmission Transfer Filled flag clear + bit_offset: 4 + bit_size: 1 + - name: UDRC + description: Underrun flag clear + bit_offset: 5 + bit_size: 1 + - name: OVRC + description: Overrun flag clear + bit_offset: 6 + bit_size: 1 + - name: CRCEC + description: CRC Error flag clear + bit_offset: 7 + bit_size: 1 + - name: TIFREC + description: TI frame format error flag clear + bit_offset: 8 + bit_size: 1 + - name: MODFC + description: Mode Fault flag clear + bit_offset: 9 + bit_size: 1 + - name: TSERFC + description: TSERFC flag clear + bit_offset: 10 + bit_size: 1 + - name: SUSPC + description: SUSPend flag clear + bit_offset: 11 + bit_size: 1 fieldset/RXCRC: description: Receiver CRC Register fields: - - name: RXCRC - description: CRC register for receiver - bit_offset: 0 - bit_size: 32 + - name: RXCRC + description: CRC register for receiver + bit_offset: 0 + bit_size: 32 fieldset/RXDR: description: Receive Data Register fields: - - name: RXDR - description: Receive data register - bit_offset: 0 - bit_size: 32 + - name: RXDR + description: Receive data register + bit_offset: 0 + bit_size: 32 fieldset/SR: description: Status Register fields: - - name: RXP - description: Rx-Packet available - bit_offset: 0 - bit_size: 1 - - name: TXP - description: Tx-Packet space available - bit_offset: 1 - bit_size: 1 - - name: DXP - description: Duplex Packet - bit_offset: 2 - bit_size: 1 - - name: EOT - description: End Of Transfer - bit_offset: 3 - bit_size: 1 - - name: TXTF - description: Transmission Transfer Filled - bit_offset: 4 - bit_size: 1 - - name: UDR - description: Underrun at slave transmission mode - bit_offset: 5 - bit_size: 1 - - name: OVR - description: Overrun - bit_offset: 6 - bit_size: 1 - - name: CRCE - description: CRC Error - bit_offset: 7 - bit_size: 1 - - name: TIFRE - description: TI frame format error - bit_offset: 8 - bit_size: 1 - - name: MODF - description: Mode Fault - bit_offset: 9 - bit_size: 1 - - name: TSERF - description: Additional number of SPI data to be transacted was reload - bit_offset: 10 - bit_size: 1 - - name: SUSP - description: SUSPend - bit_offset: 11 - bit_size: 1 - - name: TXC - description: TxFIFO transmission complete - bit_offset: 12 - bit_size: 1 - - name: RXPLVL - description: RxFIFO Packing LeVeL - bit_offset: 13 - bit_size: 2 - enum: RXPLVL - - name: RXWNE - description: RxFIFO Word Not Empty - bit_offset: 15 - bit_size: 1 - enum: RXWNE - - name: CTSIZE - description: Number of data frames remaining in current TSIZE session - bit_offset: 16 - bit_size: 16 + - name: RXP + description: Rx-Packet available + bit_offset: 0 + bit_size: 1 + - name: TXP + description: Tx-Packet space available + bit_offset: 1 + bit_size: 1 + - name: DXP + description: Duplex Packet + bit_offset: 2 + bit_size: 1 + - name: EOT + description: End Of Transfer + bit_offset: 3 + bit_size: 1 + - name: TXTF + description: Transmission Transfer Filled + bit_offset: 4 + bit_size: 1 + - name: UDR + description: Underrun at slave transmission mode + bit_offset: 5 + bit_size: 1 + - name: OVR + description: Overrun + bit_offset: 6 + bit_size: 1 + - name: CRCE + description: CRC Error + bit_offset: 7 + bit_size: 1 + - name: TIFRE + description: TI frame format error + bit_offset: 8 + bit_size: 1 + - name: MODF + description: Mode Fault + bit_offset: 9 + bit_size: 1 + - name: TSERF + description: Additional number of SPI data to be transacted was reload + bit_offset: 10 + bit_size: 1 + - name: SUSP + description: SUSPend + bit_offset: 11 + bit_size: 1 + - name: TXC + description: TxFIFO transmission complete + bit_offset: 12 + bit_size: 1 + - name: RXPLVL + description: RxFIFO Packing LeVeL + bit_offset: 13 + bit_size: 2 + enum: RXPLVL + - name: RXWNE + description: RxFIFO Word Not Empty + bit_offset: 15 + bit_size: 1 + enum: RXWNE + - name: CTSIZE + description: Number of data frames remaining in current TSIZE session + bit_offset: 16 + bit_size: 16 fieldset/TXCRC: description: Transmitter CRC Register fields: - - name: TXCRC - description: CRC register for transmitter - bit_offset: 0 - bit_size: 32 + - name: TXCRC + description: CRC register for transmitter + bit_offset: 0 + bit_size: 32 fieldset/TXDR: description: Transmit Data Register fields: - - name: TXDR - description: Transmit data register - bit_offset: 0 - bit_size: 32 + - name: TXDR + description: Transmit data register + bit_offset: 0 + bit_size: 32 fieldset/UDRDR: description: Underrun Data Register fields: - - name: UDRDR - description: Data at slave underrun condition - bit_offset: 0 - bit_size: 32 + - name: UDRDR + description: Data at slave underrun condition + bit_offset: 0 + bit_size: 32 enum/AFCNTR: bit_size: 1 variants: - - name: NotControlled - description: Peripheral takes no control of GPIOs while disabled - value: 0 - - name: Controlled - description: Peripheral controls GPIOs while disabled - value: 1 + - name: NotControlled + description: Peripheral takes no control of GPIOs while disabled + value: 0 + - name: Controlled + description: Peripheral controls GPIOs while disabled + value: 1 enum/COMM: bit_size: 2 variants: - - name: FullDuplex - description: Full duplex - value: 0 - - name: Transmitter - description: Simplex transmitter only - value: 1 - - name: Receiver - description: Simplex receiver only - value: 2 - - name: HalfDuplex - description: Half duplex - value: 3 + - name: FullDuplex + description: Full duplex + value: 0 + - name: Transmitter + description: Simplex transmitter only + value: 1 + - name: Receiver + description: Simplex receiver only + value: 2 + - name: HalfDuplex + description: Half duplex + value: 3 enum/CPHA: bit_size: 1 variants: - - name: FirstEdge - description: The first clock transition is the first data capture edge - value: 0 - - name: SecondEdge - description: The second clock transition is the first data capture edge - value: 1 + - name: FirstEdge + description: The first clock transition is the first data capture edge + value: 0 + - name: SecondEdge + description: The second clock transition is the first data capture edge + value: 1 enum/CPOL: bit_size: 1 variants: - - name: IdleLow - description: CK to 0 when idle - value: 0 - - name: IdleHigh - description: CK to 1 when idle - value: 1 + - name: IdleLow + description: CK to 0 when idle + value: 0 + - name: IdleHigh + description: CK to 1 when idle + value: 1 enum/CRC_: bit_size: 1 variants: - - name: Disabled - description: Full size (33/17 bit) CRC polynomial is not used - value: 0 - - name: Enabled - description: Full size (33/17 bit) CRC polynomial is used - value: 1 + - name: Disabled + description: Full size (33/17 bit) CRC polynomial is not used + value: 0 + - name: Enabled + description: Full size (33/17 bit) CRC polynomial is used + value: 1 enum/FTHLV: bit_size: 4 variants: - - name: OneFrame - description: 1 frame - value: 0 - - name: TwoFrames - description: 2 frames - value: 1 - - name: ThreeFrames - description: 3 frames - value: 2 - - name: FourFrames - description: 4 frames - value: 3 - - name: FiveFrames - description: 5 frames - value: 4 - - name: SixFrames - description: 6 frames - value: 5 - - name: SevenFrames - description: 7 frames - value: 6 - - name: EightFrames - description: 8 frames - value: 7 - - name: NineFrames - description: 9 frames - value: 8 - - name: TenFrames - description: 10 frames - value: 9 - - name: ElevenFrames - description: 11 frames - value: 10 - - name: TwelveFrames - description: 12 frames - value: 11 - - name: ThirteenFrames - description: 13 frames - value: 12 - - name: FourteenFrames - description: 14 frames - value: 13 - - name: FifteenFrames - description: 15 frames - value: 14 - - name: SixteenFrames - description: 16 frames - value: 15 + - name: OneFrame + description: 1 frame + value: 0 + - name: TwoFrames + description: 2 frames + value: 1 + - name: ThreeFrames + description: 3 frames + value: 2 + - name: FourFrames + description: 4 frames + value: 3 + - name: FiveFrames + description: 5 frames + value: 4 + - name: SixFrames + description: 6 frames + value: 5 + - name: SevenFrames + description: 7 frames + value: 6 + - name: EightFrames + description: 8 frames + value: 7 + - name: NineFrames + description: 9 frames + value: 8 + - name: TenFrames + description: 10 frames + value: 9 + - name: ElevenFrames + description: 11 frames + value: 10 + - name: TwelveFrames + description: 12 frames + value: 11 + - name: ThirteenFrames + description: 13 frames + value: 12 + - name: FourteenFrames + description: 14 frames + value: 13 + - name: FifteenFrames + description: 15 frames + value: 14 + - name: SixteenFrames + description: 16 frames + value: 15 enum/HDDIR: bit_size: 1 variants: - - name: Receiver - description: Receiver in half duplex mode - value: 0 - - name: Transmitter - description: Transmitter in half duplex mode - value: 1 + - name: Receiver + description: Receiver in half duplex mode + value: 0 + - name: Transmitter + description: Transmitter in half duplex mode + value: 1 enum/LSBFIRST: bit_size: 1 variants: - - name: MSBFirst - description: Data is transmitted/received with the MSB first - value: 0 - - name: LSBFirst - description: Data is transmitted/received with the LSB first - value: 1 + - name: MSBFirst + description: Data is transmitted/received with the MSB first + value: 0 + - name: LSBFirst + description: Data is transmitted/received with the LSB first + value: 1 enum/MASTER: bit_size: 1 variants: - - name: Slave - description: Slave configuration - value: 0 - - name: Master - description: Master configuration - value: 1 + - name: Slave + description: Slave configuration + value: 0 + - name: Master + description: Master configuration + value: 1 enum/MBR: bit_size: 3 variants: - - name: Div2 - description: f_spi_ker_ck / 2 - value: 0 - - name: Div4 - description: f_spi_ker_ck / 4 - value: 1 - - name: Div8 - description: f_spi_ker_ck / 8 - value: 2 - - name: Div16 - description: f_spi_ker_ck / 16 - value: 3 - - name: Div32 - description: f_spi_ker_ck / 32 - value: 4 - - name: Div64 - description: f_spi_ker_ck / 64 - value: 5 - - name: Div128 - description: f_spi_ker_ck / 128 - value: 6 - - name: Div256 - description: f_spi_ker_ck / 256 - value: 7 + - name: Div2 + description: f_spi_ker_ck / 2 + value: 0 + - name: Div4 + description: f_spi_ker_ck / 4 + value: 1 + - name: Div8 + description: f_spi_ker_ck / 8 + value: 2 + - name: Div16 + description: f_spi_ker_ck / 16 + value: 3 + - name: Div32 + description: f_spi_ker_ck / 32 + value: 4 + - name: Div64 + description: f_spi_ker_ck / 64 + value: 5 + - name: Div128 + description: f_spi_ker_ck / 128 + value: 6 + - name: Div256 + description: f_spi_ker_ck / 256 + value: 7 enum/RCRCINI: bit_size: 1 variants: - - name: AllZeros - description: All zeros RX CRC initialization pattern - value: 0 - - name: AllOnes - description: All ones RX CRC initialization pattern - value: 1 + - name: AllZeros + description: All zeros RX CRC initialization pattern + value: 0 + - name: AllOnes + description: All ones RX CRC initialization pattern + value: 1 enum/RXPLVL: bit_size: 2 variants: - - name: ZeroFrames - description: Zero frames beyond packing ratio available - value: 0 - - name: OneFrame - description: One frame beyond packing ratio available - value: 1 - - name: TwoFrames - description: Two frame beyond packing ratio available - value: 2 - - name: ThreeFrames - description: Three frame beyond packing ratio available - value: 3 + - name: ZeroFrames + description: Zero frames beyond packing ratio available + value: 0 + - name: OneFrame + description: One frame beyond packing ratio available + value: 1 + - name: TwoFrames + description: Two frame beyond packing ratio available + value: 2 + - name: ThreeFrames + description: Three frame beyond packing ratio available + value: 3 enum/RXWNE: bit_size: 1 variants: - - name: LessThan32 - description: Less than 32-bit data frame received - value: 0 - - name: AtLeast32 - description: At least 32-bit data frame received - value: 1 + - name: LessThan32 + description: Less than 32-bit data frame received + value: 0 + - name: AtLeast32 + description: At least 32-bit data frame received + value: 1 enum/SP: bit_size: 3 variants: - - name: Motorola - description: Motorola SPI protocol - value: 0 - - name: TI - description: TI SPI protocol - value: 1 + - name: Motorola + description: Motorola SPI protocol + value: 0 + - name: TI + description: TI SPI protocol + value: 1 enum/SSIOP: bit_size: 1 variants: - - name: ActiveLow - description: Low level is active for SS signal - value: 0 - - name: ActiveHigh - description: High level is active for SS signal - value: 1 + - name: ActiveLow + description: Low level is active for SS signal + value: 0 + - name: ActiveHigh + description: High level is active for SS signal + value: 1 enum/SSOM: bit_size: 1 variants: - - name: Asserted - description: SS is asserted until data transfer complete - value: 0 - - name: NotAsserted - description: Data frames interleaved with SS not asserted during MIDI - value: 1 + - name: Asserted + description: SS is asserted until data transfer complete + value: 0 + - name: NotAsserted + description: Data frames interleaved with SS not asserted during MIDI + value: 1 enum/TCRCINI: bit_size: 1 variants: - - name: AllZeros - description: All zeros TX CRC initialization pattern - value: 0 - - name: AllOnes - description: All ones TX CRC initialization pattern - value: 1 + - name: AllZeros + description: All zeros TX CRC initialization pattern + value: 0 + - name: AllOnes + description: All ones TX CRC initialization pattern + value: 1 enum/UDRCFG: bit_size: 2 variants: - - name: Constant - description: Slave sends a constant underrun pattern - value: 0 - - name: RepeatReceived - description: Slave repeats last received data frame from master - value: 1 - - name: RepeatTransmitted - description: Slave repeats last transmitted data frame - value: 2 + - name: Constant + description: Slave sends a constant underrun pattern + value: 0 + - name: RepeatReceived + description: Slave repeats last received data frame from master + value: 1 + - name: RepeatTransmitted + description: Slave repeats last transmitted data frame + value: 2 enum/UDRDET: bit_size: 2 variants: - - name: StartOfFrame - description: Underrun is detected at begin of data frame - value: 0 - - name: EndOfFrame - description: Underrun is detected at end of last data frame - value: 1 - - name: StartOfSlaveSelect - description: Underrun is detected at begin of active SS signal - value: 2 + - name: StartOfFrame + description: Underrun is detected at begin of data frame + value: 0 + - name: EndOfFrame + description: Underrun is detected at end of last data frame + value: 1 + - name: StartOfSlaveSelect + description: Underrun is detected at begin of active SS signal + value: 2 diff --git a/data/registers/spi_v4.yaml b/data/registers/spi_v4.yaml index 89ef354..a861501 100644 --- a/data/registers/spi_v4.yaml +++ b/data/registers/spi_v4.yaml @@ -1,674 +1,675 @@ ---- block/SPI: description: Serial peripheral interface items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2 - - name: CFG1 - description: configuration register 1 - byte_offset: 8 - fieldset: CFG1 - - name: CFG2 - description: configuration register 2 - byte_offset: 12 - fieldset: CFG2 - - name: IER - description: Interrupt Enable Register - byte_offset: 16 - fieldset: IER - - name: SR - description: Status Register - byte_offset: 20 - access: Read - fieldset: SR - - name: IFCR - description: Interrupt/Status Flags Clear Register - byte_offset: 24 - access: Write - fieldset: IFCR - - name: TXDR - description: Transmit Data Register - byte_offset: 32 - access: Write - fieldset: TXDR - - name: RXDR - description: Receive Data Register - byte_offset: 48 - access: Read - fieldset: RXDR - - name: CRCPOLY - description: Polynomial Register - byte_offset: 64 - fieldset: CRCPOLY - - name: TXCRC - description: Transmitter CRC Register - byte_offset: 68 - fieldset: TXCRC - - name: RXCRC - description: Receiver CRC Register - byte_offset: 72 - fieldset: RXCRC - - name: UDRDR - description: Underrun Data Register - byte_offset: 76 - fieldset: UDRDR + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CFG1 + description: configuration register 1 + byte_offset: 8 + fieldset: CFG1 + - name: CFG2 + description: configuration register 2 + byte_offset: 12 + fieldset: CFG2 + - name: IER + description: Interrupt Enable Register + byte_offset: 16 + fieldset: IER + - name: SR + description: Status Register + byte_offset: 20 + access: Read + fieldset: SR + - name: IFCR + description: Interrupt/Status Flags Clear Register + byte_offset: 24 + access: Write + fieldset: IFCR + - name: TXDR + description: Transmit Data Register + byte_offset: 32 + access: Write + fieldset: TXDR + - name: RXDR + description: Receive Data Register + byte_offset: 48 + access: Read + fieldset: RXDR + - name: CRCPOLY + description: Polynomial Register + byte_offset: 64 + fieldset: CRCPOLY + - name: TXCRC + description: Transmitter CRC Register + byte_offset: 68 + fieldset: TXCRC + - name: RXCRC + description: Receiver CRC Register + byte_offset: 72 + fieldset: RXCRC + - name: UDRDR + description: Underrun Data Register + byte_offset: 76 + fieldset: UDRDR fieldset/CFG1: description: configuration register 1 fields: - - name: DSIZE - description: Number of bits in at single SPI data frame - bit_offset: 0 - bit_size: 5 - - name: FTHLV - description: threshold level - bit_offset: 5 - bit_size: 4 - enum: FTHLV - - name: UDRCFG - description: Behavior of slave transmitter at underrun condition - bit_offset: 9 - bit_size: 2 - enum: UDRCFG - - name: RXDMAEN - description: Rx DMA stream enable - bit_offset: 14 - bit_size: 1 - - name: TXDMAEN - description: Tx DMA stream enable - bit_offset: 15 - bit_size: 1 - - name: CRCSIZE - description: Length of CRC frame to be transacted and compared - bit_offset: 16 - bit_size: 5 - - name: CRCEN - description: Hardware CRC computation enable - bit_offset: 22 - bit_size: 1 - - name: MBR - description: Master baud rate - bit_offset: 28 - bit_size: 3 - enum: MBR - - name: BPASS - description: bypass of the prescaler at master baud rate clock generator - bit_offset: 31 - bit_size: 1 + - name: DSIZE + description: Number of bits in at single SPI data frame + bit_offset: 0 + bit_size: 5 + - name: FTHLV + description: threshold level + bit_offset: 5 + bit_size: 4 + enum: FTHLV + - name: UDRCFG + description: Behavior of slave transmitter at underrun condition + bit_offset: 9 + bit_size: 2 + enum: UDRCFG + - name: RXDMAEN + description: Rx DMA stream enable + bit_offset: 14 + bit_size: 1 + - name: TXDMAEN + description: Tx DMA stream enable + bit_offset: 15 + bit_size: 1 + - name: CRCSIZE + description: Length of CRC frame to be transacted and compared + bit_offset: 16 + bit_size: 5 + - name: CRCEN + description: Hardware CRC computation enable + bit_offset: 22 + bit_size: 1 + - name: MBR + description: Master baud rate + bit_offset: 28 + bit_size: 3 + enum: MBR + - name: BPASS + description: bypass of the prescaler at master baud rate clock generator + bit_offset: 31 + bit_size: 1 fieldset/CFG2: description: configuration register 2 fields: - - name: MSSI - description: Master SS Idleness - bit_offset: 0 - bit_size: 4 - - name: MIDI - description: Master Inter-Data Idleness - bit_offset: 4 - bit_size: 4 - - name: RDIOM - description: "RDY signal input/output management\n Note: When DSIZE at the CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero." - bit_offset: 13 - bit_size: 1 - enum: RDIOM - - name: RDIOP - description: RDY signal input/output polarity - bit_offset: 14 - bit_size: 1 - enum: RDIOP - - name: IOSWP - description: Swap functionality of MISO and MOSI pins - bit_offset: 15 - bit_size: 1 - - name: COMM - description: SPI Communication Mode - bit_offset: 17 - bit_size: 2 - enum: COMM - - name: SP - description: Serial Protocol - bit_offset: 19 - bit_size: 3 - enum: SP - - name: MASTER - description: SPI Master - bit_offset: 22 - bit_size: 1 - enum: MASTER - - name: LSBFIRST - description: Data frame format - bit_offset: 23 - bit_size: 1 - enum: LSBFIRST - - name: CPHA - description: Clock phase - bit_offset: 24 - bit_size: 1 - enum: CPHA - - name: CPOL - description: Clock polarity - bit_offset: 25 - bit_size: 1 - enum: CPOL - - name: SSM - description: Software management of SS signal input - bit_offset: 26 - bit_size: 1 - - name: SSIOP - description: SS input/output polarity - bit_offset: 28 - bit_size: 1 - enum: SSIOP - - name: SSOE - description: SS output enable - bit_offset: 29 - bit_size: 1 - - name: SSOM - description: SS output management in master mode - bit_offset: 30 - bit_size: 1 - enum: SSOM - - name: AFCNTR - description: Alternate function GPIOs control - bit_offset: 31 - bit_size: 1 - enum: AFCNTR + - name: MSSI + description: Master SS Idleness + bit_offset: 0 + bit_size: 4 + - name: MIDI + description: Master Inter-Data Idleness + bit_offset: 4 + bit_size: 4 + - name: RDIOM + description: |- + RDY signal input/output management + Note: When DSIZE at the CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero. + bit_offset: 13 + bit_size: 1 + enum: RDIOM + - name: RDIOP + description: RDY signal input/output polarity + bit_offset: 14 + bit_size: 1 + enum: RDIOP + - name: IOSWP + description: Swap functionality of MISO and MOSI pins + bit_offset: 15 + bit_size: 1 + - name: COMM + description: SPI Communication Mode + bit_offset: 17 + bit_size: 2 + enum: COMM + - name: SP + description: Serial Protocol + bit_offset: 19 + bit_size: 3 + enum: SP + - name: MASTER + description: SPI Master + bit_offset: 22 + bit_size: 1 + enum: MASTER + - name: LSBFIRST + description: Data frame format + bit_offset: 23 + bit_size: 1 + enum: LSBFIRST + - name: CPHA + description: Clock phase + bit_offset: 24 + bit_size: 1 + enum: CPHA + - name: CPOL + description: Clock polarity + bit_offset: 25 + bit_size: 1 + enum: CPOL + - name: SSM + description: Software management of SS signal input + bit_offset: 26 + bit_size: 1 + - name: SSIOP + description: SS input/output polarity + bit_offset: 28 + bit_size: 1 + enum: SSIOP + - name: SSOE + description: SS output enable + bit_offset: 29 + bit_size: 1 + - name: SSOM + description: SS output management in master mode + bit_offset: 30 + bit_size: 1 + enum: SSOM + - name: AFCNTR + description: Alternate function GPIOs control + bit_offset: 31 + bit_size: 1 + enum: AFCNTR fieldset/CR1: description: control register 1 fields: - - name: SPE - description: Serial Peripheral Enable - bit_offset: 0 - bit_size: 1 - - name: MASRX - description: Master automatic SUSP in Receive mode - bit_offset: 8 - bit_size: 1 - - name: CSTART - description: Master transfer start - bit_offset: 9 - bit_size: 1 - - name: CSUSP - description: Master SUSPend request - bit_offset: 10 - bit_size: 1 - - name: HDDIR - description: Rx/Tx direction at Half-duplex mode - bit_offset: 11 - bit_size: 1 - enum: HDDIR - - name: SSI - description: Internal SS signal input level - bit_offset: 12 - bit_size: 1 - - name: CRC33_17 - description: 32-bit CRC polynomial configuration - bit_offset: 13 - bit_size: 1 - enum: CRC_ - - name: RCRCINI - description: CRC calculation initialization pattern control for receiver - bit_offset: 14 - bit_size: 1 - enum: RCRCINI - - name: TCRCINI - description: CRC calculation initialization pattern control for transmitter - bit_offset: 15 - bit_size: 1 - enum: TCRCINI - - name: IOLOCK - description: Locking the AF configuration of associated IOs - bit_offset: 16 - bit_size: 1 + - name: SPE + description: Serial Peripheral Enable + bit_offset: 0 + bit_size: 1 + - name: MASRX + description: Master automatic SUSP in Receive mode + bit_offset: 8 + bit_size: 1 + - name: CSTART + description: Master transfer start + bit_offset: 9 + bit_size: 1 + - name: CSUSP + description: Master SUSPend request + bit_offset: 10 + bit_size: 1 + - name: HDDIR + description: Rx/Tx direction at Half-duplex mode + bit_offset: 11 + bit_size: 1 + enum: HDDIR + - name: SSI + description: Internal SS signal input level + bit_offset: 12 + bit_size: 1 + - name: CRC33_17 + description: 32-bit CRC polynomial configuration + bit_offset: 13 + bit_size: 1 + enum: CRC_ + - name: RCRCINI + description: CRC calculation initialization pattern control for receiver + bit_offset: 14 + bit_size: 1 + enum: RCRCINI + - name: TCRCINI + description: CRC calculation initialization pattern control for transmitter + bit_offset: 15 + bit_size: 1 + enum: TCRCINI + - name: IOLOCK + description: Locking the AF configuration of associated IOs + bit_offset: 16 + bit_size: 1 fieldset/CR2: description: control register 2 fields: - - name: TSIZE - description: Number of data at current transfer - bit_offset: 0 - bit_size: 16 + - name: TSIZE + description: Number of data at current transfer + bit_offset: 0 + bit_size: 16 fieldset/CRCPOLY: description: Polynomial Register fields: - - name: CRCPOLY - description: CRC polynomial register - bit_offset: 0 - bit_size: 32 + - name: CRCPOLY + description: CRC polynomial register + bit_offset: 0 + bit_size: 32 fieldset/IER: description: Interrupt Enable Register fields: - - name: RXPIE - description: RXP Interrupt Enable - bit_offset: 0 - bit_size: 1 - - name: TXPIE - description: TXP interrupt enable - bit_offset: 1 - bit_size: 1 - - name: DXPIE - description: DXP interrupt enabled - bit_offset: 2 - bit_size: 1 - - name: EOTIE - description: "EOT, SUSP and TXC interrupt enable" - bit_offset: 3 - bit_size: 1 - - name: TXTFIE - description: TXTFIE interrupt enable - bit_offset: 4 - bit_size: 1 - - name: UDRIE - description: UDR interrupt enable - bit_offset: 5 - bit_size: 1 - - name: OVRIE - description: OVR interrupt enable - bit_offset: 6 - bit_size: 1 - - name: CRCEIE - description: CRC Interrupt enable - bit_offset: 7 - bit_size: 1 - - name: TIFREIE - description: TIFRE interrupt enable - bit_offset: 8 - bit_size: 1 - - name: MODFIE - description: Mode Fault interrupt enable - bit_offset: 9 - bit_size: 1 + - name: RXPIE + description: RXP Interrupt Enable + bit_offset: 0 + bit_size: 1 + - name: TXPIE + description: TXP interrupt enable + bit_offset: 1 + bit_size: 1 + - name: DXPIE + description: DXP interrupt enabled + bit_offset: 2 + bit_size: 1 + - name: EOTIE + description: EOT, SUSP and TXC interrupt enable + bit_offset: 3 + bit_size: 1 + - name: TXTFIE + description: TXTFIE interrupt enable + bit_offset: 4 + bit_size: 1 + - name: UDRIE + description: UDR interrupt enable + bit_offset: 5 + bit_size: 1 + - name: OVRIE + description: OVR interrupt enable + bit_offset: 6 + bit_size: 1 + - name: CRCEIE + description: CRC Interrupt enable + bit_offset: 7 + bit_size: 1 + - name: TIFREIE + description: TIFRE interrupt enable + bit_offset: 8 + bit_size: 1 + - name: MODFIE + description: Mode Fault interrupt enable + bit_offset: 9 + bit_size: 1 fieldset/IFCR: description: Interrupt/Status Flags Clear Register fields: - - name: EOTC - description: End Of Transfer flag clear - bit_offset: 3 - bit_size: 1 - - name: TXTFC - description: Transmission Transfer Filled flag clear - bit_offset: 4 - bit_size: 1 - - name: UDRC - description: Underrun flag clear - bit_offset: 5 - bit_size: 1 - - name: OVRC - description: Overrun flag clear - bit_offset: 6 - bit_size: 1 - - name: CRCEC - description: CRC Error flag clear - bit_offset: 7 - bit_size: 1 - - name: TIFREC - description: TI frame format error flag clear - bit_offset: 8 - bit_size: 1 - - name: MODFC - description: Mode Fault flag clear - bit_offset: 9 - bit_size: 1 - - name: SUSPC - description: SUSPend flag clear - bit_offset: 11 - bit_size: 1 + - name: EOTC + description: End Of Transfer flag clear + bit_offset: 3 + bit_size: 1 + - name: TXTFC + description: Transmission Transfer Filled flag clear + bit_offset: 4 + bit_size: 1 + - name: UDRC + description: Underrun flag clear + bit_offset: 5 + bit_size: 1 + - name: OVRC + description: Overrun flag clear + bit_offset: 6 + bit_size: 1 + - name: CRCEC + description: CRC Error flag clear + bit_offset: 7 + bit_size: 1 + - name: TIFREC + description: TI frame format error flag clear + bit_offset: 8 + bit_size: 1 + - name: MODFC + description: Mode Fault flag clear + bit_offset: 9 + bit_size: 1 + - name: SUSPC + description: SUSPend flag clear + bit_offset: 11 + bit_size: 1 fieldset/RXCRC: description: Receiver CRC Register fields: - - name: RXCRC - description: CRC register for receiver - bit_offset: 0 - bit_size: 32 + - name: RXCRC + description: CRC register for receiver + bit_offset: 0 + bit_size: 32 fieldset/RXDR: description: Receive Data Register fields: - - name: RXDR - description: Receive data register - bit_offset: 0 - bit_size: 32 + - name: RXDR + description: Receive data register + bit_offset: 0 + bit_size: 32 fieldset/SR: description: Status Register fields: - - name: RXP - description: Rx-Packet available - bit_offset: 0 - bit_size: 1 - - name: TXP - description: Tx-Packet space available - bit_offset: 1 - bit_size: 1 - - name: DXP - description: Duplex Packet - bit_offset: 2 - bit_size: 1 - - name: EOT - description: End Of Transfer - bit_offset: 3 - bit_size: 1 - - name: TXTF - description: Transmission Transfer Filled - bit_offset: 4 - bit_size: 1 - - name: UDR - description: Underrun at slave transmission mode - bit_offset: 5 - bit_size: 1 - - name: OVR - description: Overrun - bit_offset: 6 - bit_size: 1 - - name: CRCE - description: CRC Error - bit_offset: 7 - bit_size: 1 - - name: TIFRE - description: TI frame format error - bit_offset: 8 - bit_size: 1 - - name: MODF - description: Mode Fault - bit_offset: 9 - bit_size: 1 - - name: SUSP - description: SUSPend - bit_offset: 11 - bit_size: 1 - - name: TXC - description: TxFIFO transmission complete - bit_offset: 12 - bit_size: 1 - - name: RXPLVL - description: RxFIFO Packing LeVeL - bit_offset: 13 - bit_size: 2 - enum: RXPLVL - - name: RXWNE - description: RxFIFO Word Not Empty - bit_offset: 15 - bit_size: 1 - enum: RXWNE - - name: CTSIZE - description: Number of data frames remaining in current TSIZE session - bit_offset: 16 - bit_size: 16 + - name: RXP + description: Rx-Packet available + bit_offset: 0 + bit_size: 1 + - name: TXP + description: Tx-Packet space available + bit_offset: 1 + bit_size: 1 + - name: DXP + description: Duplex Packet + bit_offset: 2 + bit_size: 1 + - name: EOT + description: End Of Transfer + bit_offset: 3 + bit_size: 1 + - name: TXTF + description: Transmission Transfer Filled + bit_offset: 4 + bit_size: 1 + - name: UDR + description: Underrun at slave transmission mode + bit_offset: 5 + bit_size: 1 + - name: OVR + description: Overrun + bit_offset: 6 + bit_size: 1 + - name: CRCE + description: CRC Error + bit_offset: 7 + bit_size: 1 + - name: TIFRE + description: TI frame format error + bit_offset: 8 + bit_size: 1 + - name: MODF + description: Mode Fault + bit_offset: 9 + bit_size: 1 + - name: SUSP + description: SUSPend + bit_offset: 11 + bit_size: 1 + - name: TXC + description: TxFIFO transmission complete + bit_offset: 12 + bit_size: 1 + - name: RXPLVL + description: RxFIFO Packing LeVeL + bit_offset: 13 + bit_size: 2 + enum: RXPLVL + - name: RXWNE + description: RxFIFO Word Not Empty + bit_offset: 15 + bit_size: 1 + enum: RXWNE + - name: CTSIZE + description: Number of data frames remaining in current TSIZE session + bit_offset: 16 + bit_size: 16 fieldset/TXCRC: description: Transmitter CRC Register fields: - - name: TXCRC - description: CRC register for transmitter - bit_offset: 0 - bit_size: 32 + - name: TXCRC + description: CRC register for transmitter + bit_offset: 0 + bit_size: 32 fieldset/TXDR: description: Transmit Data Register fields: - - name: TXDR - description: Transmit data register - bit_offset: 0 - bit_size: 32 + - name: TXDR + description: Transmit data register + bit_offset: 0 + bit_size: 32 fieldset/UDRDR: description: Underrun Data Register fields: - - name: UDRDR - description: Data at slave underrun condition - bit_offset: 0 - bit_size: 32 + - name: UDRDR + description: Data at slave underrun condition + bit_offset: 0 + bit_size: 32 enum/AFCNTR: bit_size: 1 variants: - - name: NotControlled - description: Peripheral takes no control of GPIOs while disabled - value: 0 - - name: Controlled - description: Peripheral controls GPIOs while disabled - value: 1 + - name: NotControlled + description: Peripheral takes no control of GPIOs while disabled + value: 0 + - name: Controlled + description: Peripheral controls GPIOs while disabled + value: 1 enum/COMM: bit_size: 2 variants: - - name: FullDuplex - description: Full duplex - value: 0 - - name: Transmitter - description: Simplex transmitter only - value: 1 - - name: Receiver - description: Simplex receiver only - value: 2 - - name: HalfDuplex - description: Half duplex - value: 3 + - name: FullDuplex + description: Full duplex + value: 0 + - name: Transmitter + description: Simplex transmitter only + value: 1 + - name: Receiver + description: Simplex receiver only + value: 2 + - name: HalfDuplex + description: Half duplex + value: 3 enum/CPHA: bit_size: 1 variants: - - name: FirstEdge - description: The first clock transition is the first data capture edge - value: 0 - - name: SecondEdge - description: The second clock transition is the first data capture edge - value: 1 + - name: FirstEdge + description: The first clock transition is the first data capture edge + value: 0 + - name: SecondEdge + description: The second clock transition is the first data capture edge + value: 1 enum/CPOL: bit_size: 1 variants: - - name: IdleLow - description: CK to 0 when idle - value: 0 - - name: IdleHigh - description: CK to 1 when idle - value: 1 + - name: IdleLow + description: CK to 0 when idle + value: 0 + - name: IdleHigh + description: CK to 1 when idle + value: 1 enum/CRC_: bit_size: 1 variants: - - name: Disabled - description: Full size (33/17 bit) CRC polynomial is not used - value: 0 - - name: Enabled - description: Full size (33/17 bit) CRC polynomial is used - value: 1 + - name: Disabled + description: Full size (33/17 bit) CRC polynomial is not used + value: 0 + - name: Enabled + description: Full size (33/17 bit) CRC polynomial is used + value: 1 enum/FTHLV: bit_size: 4 variants: - - name: OneFrame - description: 1 frame - value: 0 - - name: TwoFrames - description: 2 frames - value: 1 - - name: ThreeFrames - description: 3 frames - value: 2 - - name: FourFrames - description: 4 frames - value: 3 - - name: FiveFrames - description: 5 frames - value: 4 - - name: SixFrames - description: 6 frames - value: 5 - - name: SevenFrames - description: 7 frames - value: 6 - - name: EightFrames - description: 8 frames - value: 7 - - name: NineFrames - description: 9 frames - value: 8 - - name: TenFrames - description: 10 frames - value: 9 - - name: ElevenFrames - description: 11 frames - value: 10 - - name: TwelveFrames - description: 12 frames - value: 11 - - name: ThirteenFrames - description: 13 frames - value: 12 - - name: FourteenFrames - description: 14 frames - value: 13 - - name: FifteenFrames - description: 15 frames - value: 14 - - name: SixteenFrames - description: 16 frames - value: 15 + - name: OneFrame + description: 1 frame + value: 0 + - name: TwoFrames + description: 2 frames + value: 1 + - name: ThreeFrames + description: 3 frames + value: 2 + - name: FourFrames + description: 4 frames + value: 3 + - name: FiveFrames + description: 5 frames + value: 4 + - name: SixFrames + description: 6 frames + value: 5 + - name: SevenFrames + description: 7 frames + value: 6 + - name: EightFrames + description: 8 frames + value: 7 + - name: NineFrames + description: 9 frames + value: 8 + - name: TenFrames + description: 10 frames + value: 9 + - name: ElevenFrames + description: 11 frames + value: 10 + - name: TwelveFrames + description: 12 frames + value: 11 + - name: ThirteenFrames + description: 13 frames + value: 12 + - name: FourteenFrames + description: 14 frames + value: 13 + - name: FifteenFrames + description: 15 frames + value: 14 + - name: SixteenFrames + description: 16 frames + value: 15 enum/HDDIR: bit_size: 1 variants: - - name: Receiver - description: Receiver in half duplex mode - value: 0 - - name: Transmitter - description: Transmitter in half duplex mode - value: 1 + - name: Receiver + description: Receiver in half duplex mode + value: 0 + - name: Transmitter + description: Transmitter in half duplex mode + value: 1 enum/LSBFIRST: bit_size: 1 variants: - - name: MSBFirst - description: Data is transmitted/received with the MSB first - value: 0 - - name: LSBFirst - description: Data is transmitted/received with the LSB first - value: 1 + - name: MSBFirst + description: Data is transmitted/received with the MSB first + value: 0 + - name: LSBFirst + description: Data is transmitted/received with the LSB first + value: 1 enum/MASTER: bit_size: 1 variants: - - name: Slave - description: Slave configuration - value: 0 - - name: Master - description: Master configuration - value: 1 + - name: Slave + description: Slave configuration + value: 0 + - name: Master + description: Master configuration + value: 1 enum/MBR: bit_size: 3 variants: - - name: Div2 - description: f_spi_ker_ck / 2 - value: 0 - - name: Div4 - description: f_spi_ker_ck / 4 - value: 1 - - name: Div8 - description: f_spi_ker_ck / 8 - value: 2 - - name: Div16 - description: f_spi_ker_ck / 16 - value: 3 - - name: Div32 - description: f_spi_ker_ck / 32 - value: 4 - - name: Div64 - description: f_spi_ker_ck / 64 - value: 5 - - name: Div128 - description: f_spi_ker_ck / 128 - value: 6 - - name: Div256 - description: f_spi_ker_ck / 256 - value: 7 + - name: Div2 + description: f_spi_ker_ck / 2 + value: 0 + - name: Div4 + description: f_spi_ker_ck / 4 + value: 1 + - name: Div8 + description: f_spi_ker_ck / 8 + value: 2 + - name: Div16 + description: f_spi_ker_ck / 16 + value: 3 + - name: Div32 + description: f_spi_ker_ck / 32 + value: 4 + - name: Div64 + description: f_spi_ker_ck / 64 + value: 5 + - name: Div128 + description: f_spi_ker_ck / 128 + value: 6 + - name: Div256 + description: f_spi_ker_ck / 256 + value: 7 enum/RCRCINI: bit_size: 1 variants: - - name: AllZeros - description: All zeros RX CRC initialization pattern - value: 0 - - name: AllOnes - description: All ones RX CRC initialization pattern - value: 1 + - name: AllZeros + description: All zeros RX CRC initialization pattern + value: 0 + - name: AllOnes + description: All ones RX CRC initialization pattern + value: 1 enum/RDIOM: bit_size: 1 variants: - - name: PermanentlyActive - description: RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) - value: 0 - - name: FromInput - description: RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) - value: 1 + - name: PermanentlyActive + description: RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) + value: 0 + - name: FromInput + description: RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) + value: 1 enum/RDIOP: bit_size: 1 variants: - - name: ReadyHigh - description: high level of the signal means the slave is ready for communication - value: 0 - - name: ReadyLow - description: low level of the signal means the slave is ready for communication - value: 1 + - name: ReadyHigh + description: high level of the signal means the slave is ready for communication + value: 0 + - name: ReadyLow + description: low level of the signal means the slave is ready for communication + value: 1 enum/RXPLVL: bit_size: 2 variants: - - name: ZeroFrames - description: Zero frames beyond packing ratio available - value: 0 - - name: OneFrame - description: One frame beyond packing ratio available - value: 1 - - name: TwoFrames - description: Two frame beyond packing ratio available - value: 2 - - name: ThreeFrames - description: Three frame beyond packing ratio available - value: 3 + - name: ZeroFrames + description: Zero frames beyond packing ratio available + value: 0 + - name: OneFrame + description: One frame beyond packing ratio available + value: 1 + - name: TwoFrames + description: Two frame beyond packing ratio available + value: 2 + - name: ThreeFrames + description: Three frame beyond packing ratio available + value: 3 enum/RXWNE: bit_size: 1 variants: - - name: LessThan32 - description: Less than 32-bit data frame received - value: 0 - - name: AtLeast32 - description: At least 32-bit data frame received - value: 1 + - name: LessThan32 + description: Less than 32-bit data frame received + value: 0 + - name: AtLeast32 + description: At least 32-bit data frame received + value: 1 enum/SP: bit_size: 3 variants: - - name: Motorola - description: Motorola SPI protocol - value: 0 - - name: TI - description: TI SPI protocol - value: 1 + - name: Motorola + description: Motorola SPI protocol + value: 0 + - name: TI + description: TI SPI protocol + value: 1 enum/SSIOP: bit_size: 1 variants: - - name: ActiveLow - description: Low level is active for SS signal - value: 0 - - name: ActiveHigh - description: High level is active for SS signal - value: 1 + - name: ActiveLow + description: Low level is active for SS signal + value: 0 + - name: ActiveHigh + description: High level is active for SS signal + value: 1 enum/SSOM: bit_size: 1 variants: - - name: Asserted - description: SS is asserted until data transfer complete - value: 0 - - name: NotAsserted - description: Data frames interleaved with SS not asserted during MIDI - value: 1 + - name: Asserted + description: SS is asserted until data transfer complete + value: 0 + - name: NotAsserted + description: Data frames interleaved with SS not asserted during MIDI + value: 1 enum/TCRCINI: bit_size: 1 variants: - - name: AllZeros - description: All zeros TX CRC initialization pattern - value: 0 - - name: AllOnes - description: All ones TX CRC initialization pattern - value: 1 + - name: AllZeros + description: All zeros TX CRC initialization pattern + value: 0 + - name: AllOnes + description: All ones TX CRC initialization pattern + value: 1 enum/UDRCFG: bit_size: 2 variants: - - name: Constant - description: Slave sends a constant underrun pattern - value: 0 - - name: RepeatReceived - description: Slave repeats last received data frame from master - value: 1 - - name: RepeatTransmitted - description: Slave repeats last transmitted data frame - value: 2 + - name: Constant + description: Slave sends a constant underrun pattern + value: 0 + - name: RepeatReceived + description: Slave repeats last received data frame from master + value: 1 + - name: RepeatTransmitted + description: Slave repeats last transmitted data frame + value: 2 diff --git a/data/registers/spi_v5.yaml b/data/registers/spi_v5.yaml index d5961e6..6ebe0e8 100644 --- a/data/registers/spi_v5.yaml +++ b/data/registers/spi_v5.yaml @@ -1,701 +1,709 @@ ---- block/SPI: description: Serial peripheral interface items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2 - - name: CFG1 - description: configuration register 1 - byte_offset: 8 - fieldset: CFG1 - - name: CFG2 - description: configuration register 2 - byte_offset: 12 - fieldset: CFG2 - - name: IER - description: Interrupt Enable Register - byte_offset: 16 - fieldset: IER - - name: SR - description: Status Register - byte_offset: 20 - access: Read - fieldset: SR - - name: IFCR - description: Interrupt/Status Flags Clear Register - byte_offset: 24 - access: Write - fieldset: IFCR - - name: AUTOCR - byte_offset: 28 - fieldset: AUTOCR - - name: TXDR - description: Transmit Data Register - byte_offset: 32 - access: Write - fieldset: TXDR - - name: RXDR - description: Receive Data Register - byte_offset: 48 - access: Read - fieldset: RXDR - - name: CRCPOLY - description: Polynomial Register - byte_offset: 64 - fieldset: CRCPOLY - - name: TXCRC - description: Transmitter CRC Register - byte_offset: 68 - fieldset: TXCRC - - name: RXCRC - description: Receiver CRC Register - byte_offset: 72 - fieldset: RXCRC - - name: UDRDR - description: Underrun Data Register - byte_offset: 76 - fieldset: UDRDR + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CFG1 + description: configuration register 1 + byte_offset: 8 + fieldset: CFG1 + - name: CFG2 + description: configuration register 2 + byte_offset: 12 + fieldset: CFG2 + - name: IER + description: Interrupt Enable Register + byte_offset: 16 + fieldset: IER + - name: SR + description: Status Register + byte_offset: 20 + access: Read + fieldset: SR + - name: IFCR + description: Interrupt/Status Flags Clear Register + byte_offset: 24 + access: Write + fieldset: IFCR + - name: AUTOCR + byte_offset: 28 + fieldset: AUTOCR + - name: TXDR + description: Transmit Data Register + byte_offset: 32 + access: Write + fieldset: TXDR + - name: RXDR + description: Receive Data Register + byte_offset: 48 + access: Read + fieldset: RXDR + - name: CRCPOLY + description: Polynomial Register + byte_offset: 64 + fieldset: CRCPOLY + - name: TXCRC + description: Transmitter CRC Register + byte_offset: 68 + fieldset: TXCRC + - name: RXCRC + description: Receiver CRC Register + byte_offset: 72 + fieldset: RXCRC + - name: UDRDR + description: Underrun Data Register + byte_offset: 76 + fieldset: UDRDR fieldset/AUTOCR: fields: - - name: TRIGSEL - description: "trigger selection (refer ).\n ...\n Note: these bits can be written only when SPE = 0." - bit_offset: 16 - bit_size: 4 - - name: TRIGPOL - description: "trigger polarity\n Note: This bit can be written only when SPE = 0." - bit_offset: 20 - bit_size: 1 - enum: TRIGPOL - - name: TRIGEN - description: "trigger of CSTART control enable\n Note: if user can't prevent trigger event during write, the TRIGEN has to be changed when SPI is disabled" - bit_offset: 21 - bit_size: 1 + - name: TRIGSEL + description: |- + trigger selection (refer ). + ... + Note: these bits can be written only when SPE = 0. + bit_offset: 16 + bit_size: 4 + - name: TRIGPOL + description: |- + trigger polarity + Note: This bit can be written only when SPE = 0. + bit_offset: 20 + bit_size: 1 + enum: TRIGPOL + - name: TRIGEN + description: |- + trigger of CSTART control enable + Note: if user can't prevent trigger event during write, the TRIGEN has to be changed when SPI is disabled + bit_offset: 21 + bit_size: 1 fieldset/CFG1: description: configuration register 1 fields: - - name: DSIZE - description: Number of bits in at single SPI data frame - bit_offset: 0 - bit_size: 5 - - name: FTHLV - description: threshold level - bit_offset: 5 - bit_size: 4 - enum: FTHLV - - name: UDRCFG - description: Behavior of slave transmitter at underrun condition - bit_offset: 9 - bit_size: 2 - enum: UDRCFG - - name: RXDMAEN - description: Rx DMA stream enable - bit_offset: 14 - bit_size: 1 - - name: TXDMAEN - description: Tx DMA stream enable - bit_offset: 15 - bit_size: 1 - - name: CRCSIZE - description: Length of CRC frame to be transacted and compared - bit_offset: 16 - bit_size: 5 - - name: CRCEN - description: Hardware CRC computation enable - bit_offset: 22 - bit_size: 1 - - name: MBR - description: Master baud rate - bit_offset: 28 - bit_size: 3 - enum: MBR - - name: BPASS - description: bypass of the prescaler at master baud rate clock generator - bit_offset: 31 - bit_size: 1 + - name: DSIZE + description: Number of bits in at single SPI data frame + bit_offset: 0 + bit_size: 5 + - name: FTHLV + description: threshold level + bit_offset: 5 + bit_size: 4 + enum: FTHLV + - name: UDRCFG + description: Behavior of slave transmitter at underrun condition + bit_offset: 9 + bit_size: 2 + enum: UDRCFG + - name: RXDMAEN + description: Rx DMA stream enable + bit_offset: 14 + bit_size: 1 + - name: TXDMAEN + description: Tx DMA stream enable + bit_offset: 15 + bit_size: 1 + - name: CRCSIZE + description: Length of CRC frame to be transacted and compared + bit_offset: 16 + bit_size: 5 + - name: CRCEN + description: Hardware CRC computation enable + bit_offset: 22 + bit_size: 1 + - name: MBR + description: Master baud rate + bit_offset: 28 + bit_size: 3 + enum: MBR + - name: BPASS + description: bypass of the prescaler at master baud rate clock generator + bit_offset: 31 + bit_size: 1 fieldset/CFG2: description: configuration register 2 fields: - - name: MSSI - description: Master SS Idleness - bit_offset: 0 - bit_size: 4 - - name: MIDI - description: Master Inter-Data Idleness - bit_offset: 4 - bit_size: 4 - - name: RDIOM - description: "RDY signal input/output management\n Note: When DSIZE at the CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero." - bit_offset: 13 - bit_size: 1 - enum: RDIOM - - name: RDIOP - description: RDY signal input/output polarity - bit_offset: 14 - bit_size: 1 - enum: RDIOP - - name: IOSWP - description: Swap functionality of MISO and MOSI pins - bit_offset: 15 - bit_size: 1 - - name: COMM - description: SPI Communication Mode - bit_offset: 17 - bit_size: 2 - enum: COMM - - name: SP - description: Serial Protocol - bit_offset: 19 - bit_size: 3 - enum: SP - - name: MASTER - description: SPI Master - bit_offset: 22 - bit_size: 1 - enum: MASTER - - name: LSBFIRST - description: Data frame format - bit_offset: 23 - bit_size: 1 - enum: LSBFIRST - - name: CPHA - description: Clock phase - bit_offset: 24 - bit_size: 1 - enum: CPHA - - name: CPOL - description: Clock polarity - bit_offset: 25 - bit_size: 1 - enum: CPOL - - name: SSM - description: Software management of SS signal input - bit_offset: 26 - bit_size: 1 - - name: SSIOP - description: SS input/output polarity - bit_offset: 28 - bit_size: 1 - enum: SSIOP - - name: SSOE - description: SS output enable - bit_offset: 29 - bit_size: 1 - - name: SSOM - description: SS output management in master mode - bit_offset: 30 - bit_size: 1 - enum: SSOM - - name: AFCNTR - description: Alternate function GPIOs control - bit_offset: 31 - bit_size: 1 - enum: AFCNTR + - name: MSSI + description: Master SS Idleness + bit_offset: 0 + bit_size: 4 + - name: MIDI + description: Master Inter-Data Idleness + bit_offset: 4 + bit_size: 4 + - name: RDIOM + description: |- + RDY signal input/output management + Note: When DSIZE at the CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero. + bit_offset: 13 + bit_size: 1 + enum: RDIOM + - name: RDIOP + description: RDY signal input/output polarity + bit_offset: 14 + bit_size: 1 + enum: RDIOP + - name: IOSWP + description: Swap functionality of MISO and MOSI pins + bit_offset: 15 + bit_size: 1 + - name: COMM + description: SPI Communication Mode + bit_offset: 17 + bit_size: 2 + enum: COMM + - name: SP + description: Serial Protocol + bit_offset: 19 + bit_size: 3 + enum: SP + - name: MASTER + description: SPI Master + bit_offset: 22 + bit_size: 1 + enum: MASTER + - name: LSBFIRST + description: Data frame format + bit_offset: 23 + bit_size: 1 + enum: LSBFIRST + - name: CPHA + description: Clock phase + bit_offset: 24 + bit_size: 1 + enum: CPHA + - name: CPOL + description: Clock polarity + bit_offset: 25 + bit_size: 1 + enum: CPOL + - name: SSM + description: Software management of SS signal input + bit_offset: 26 + bit_size: 1 + - name: SSIOP + description: SS input/output polarity + bit_offset: 28 + bit_size: 1 + enum: SSIOP + - name: SSOE + description: SS output enable + bit_offset: 29 + bit_size: 1 + - name: SSOM + description: SS output management in master mode + bit_offset: 30 + bit_size: 1 + enum: SSOM + - name: AFCNTR + description: Alternate function GPIOs control + bit_offset: 31 + bit_size: 1 + enum: AFCNTR fieldset/CR1: description: control register 1 fields: - - name: SPE - description: Serial Peripheral Enable - bit_offset: 0 - bit_size: 1 - - name: MASRX - description: Master automatic SUSP in Receive mode - bit_offset: 8 - bit_size: 1 - - name: CSTART - description: Master transfer start - bit_offset: 9 - bit_size: 1 - - name: CSUSP - description: Master SUSPend request - bit_offset: 10 - bit_size: 1 - - name: HDDIR - description: Rx/Tx direction at Half-duplex mode - bit_offset: 11 - bit_size: 1 - enum: HDDIR - - name: SSI - description: Internal SS signal input level - bit_offset: 12 - bit_size: 1 - - name: CRC33_17 - description: 32-bit CRC polynomial configuration - bit_offset: 13 - bit_size: 1 - enum: CRC_ - - name: RCRCINI - description: CRC calculation initialization pattern control for receiver - bit_offset: 14 - bit_size: 1 - enum: RCRCINI - - name: TCRCINI - description: CRC calculation initialization pattern control for transmitter - bit_offset: 15 - bit_size: 1 - enum: TCRCINI - - name: IOLOCK - description: Locking the AF configuration of associated IOs - bit_offset: 16 - bit_size: 1 + - name: SPE + description: Serial Peripheral Enable + bit_offset: 0 + bit_size: 1 + - name: MASRX + description: Master automatic SUSP in Receive mode + bit_offset: 8 + bit_size: 1 + - name: CSTART + description: Master transfer start + bit_offset: 9 + bit_size: 1 + - name: CSUSP + description: Master SUSPend request + bit_offset: 10 + bit_size: 1 + - name: HDDIR + description: Rx/Tx direction at Half-duplex mode + bit_offset: 11 + bit_size: 1 + enum: HDDIR + - name: SSI + description: Internal SS signal input level + bit_offset: 12 + bit_size: 1 + - name: CRC33_17 + description: 32-bit CRC polynomial configuration + bit_offset: 13 + bit_size: 1 + enum: CRC_ + - name: RCRCINI + description: CRC calculation initialization pattern control for receiver + bit_offset: 14 + bit_size: 1 + enum: RCRCINI + - name: TCRCINI + description: CRC calculation initialization pattern control for transmitter + bit_offset: 15 + bit_size: 1 + enum: TCRCINI + - name: IOLOCK + description: Locking the AF configuration of associated IOs + bit_offset: 16 + bit_size: 1 fieldset/CR2: description: control register 2 fields: - - name: TSIZE - description: Number of data at current transfer - bit_offset: 0 - bit_size: 16 + - name: TSIZE + description: Number of data at current transfer + bit_offset: 0 + bit_size: 16 fieldset/CRCPOLY: description: Polynomial Register fields: - - name: CRCPOLY - description: CRC polynomial register - bit_offset: 0 - bit_size: 32 + - name: CRCPOLY + description: CRC polynomial register + bit_offset: 0 + bit_size: 32 fieldset/IER: description: Interrupt Enable Register fields: - - name: RXPIE - description: RXP Interrupt Enable - bit_offset: 0 - bit_size: 1 - - name: TXPIE - description: TXP interrupt enable - bit_offset: 1 - bit_size: 1 - - name: DXPIE - description: DXP interrupt enabled - bit_offset: 2 - bit_size: 1 - - name: EOTIE - description: "EOT, SUSP and TXC interrupt enable" - bit_offset: 3 - bit_size: 1 - - name: TXTFIE - description: TXTFIE interrupt enable - bit_offset: 4 - bit_size: 1 - - name: UDRIE - description: UDR interrupt enable - bit_offset: 5 - bit_size: 1 - - name: OVRIE - description: OVR interrupt enable - bit_offset: 6 - bit_size: 1 - - name: CRCEIE - description: CRC Interrupt enable - bit_offset: 7 - bit_size: 1 - - name: TIFREIE - description: TIFRE interrupt enable - bit_offset: 8 - bit_size: 1 - - name: MODFIE - description: Mode Fault interrupt enable - bit_offset: 9 - bit_size: 1 + - name: RXPIE + description: RXP Interrupt Enable + bit_offset: 0 + bit_size: 1 + - name: TXPIE + description: TXP interrupt enable + bit_offset: 1 + bit_size: 1 + - name: DXPIE + description: DXP interrupt enabled + bit_offset: 2 + bit_size: 1 + - name: EOTIE + description: EOT, SUSP and TXC interrupt enable + bit_offset: 3 + bit_size: 1 + - name: TXTFIE + description: TXTFIE interrupt enable + bit_offset: 4 + bit_size: 1 + - name: UDRIE + description: UDR interrupt enable + bit_offset: 5 + bit_size: 1 + - name: OVRIE + description: OVR interrupt enable + bit_offset: 6 + bit_size: 1 + - name: CRCEIE + description: CRC Interrupt enable + bit_offset: 7 + bit_size: 1 + - name: TIFREIE + description: TIFRE interrupt enable + bit_offset: 8 + bit_size: 1 + - name: MODFIE + description: Mode Fault interrupt enable + bit_offset: 9 + bit_size: 1 fieldset/IFCR: description: Interrupt/Status Flags Clear Register fields: - - name: EOTC - description: End Of Transfer flag clear - bit_offset: 3 - bit_size: 1 - - name: TXTFC - description: Transmission Transfer Filled flag clear - bit_offset: 4 - bit_size: 1 - - name: UDRC - description: Underrun flag clear - bit_offset: 5 - bit_size: 1 - - name: OVRC - description: Overrun flag clear - bit_offset: 6 - bit_size: 1 - - name: CRCEC - description: CRC Error flag clear - bit_offset: 7 - bit_size: 1 - - name: TIFREC - description: TI frame format error flag clear - bit_offset: 8 - bit_size: 1 - - name: MODFC - description: Mode Fault flag clear - bit_offset: 9 - bit_size: 1 - - name: SUSPC - description: SUSPend flag clear - bit_offset: 11 - bit_size: 1 + - name: EOTC + description: End Of Transfer flag clear + bit_offset: 3 + bit_size: 1 + - name: TXTFC + description: Transmission Transfer Filled flag clear + bit_offset: 4 + bit_size: 1 + - name: UDRC + description: Underrun flag clear + bit_offset: 5 + bit_size: 1 + - name: OVRC + description: Overrun flag clear + bit_offset: 6 + bit_size: 1 + - name: CRCEC + description: CRC Error flag clear + bit_offset: 7 + bit_size: 1 + - name: TIFREC + description: TI frame format error flag clear + bit_offset: 8 + bit_size: 1 + - name: MODFC + description: Mode Fault flag clear + bit_offset: 9 + bit_size: 1 + - name: SUSPC + description: SUSPend flag clear + bit_offset: 11 + bit_size: 1 fieldset/RXCRC: description: Receiver CRC Register fields: - - name: RXCRC - description: CRC register for receiver - bit_offset: 0 - bit_size: 32 + - name: RXCRC + description: CRC register for receiver + bit_offset: 0 + bit_size: 32 fieldset/RXDR: description: Receive Data Register fields: - - name: RXDR - description: Receive data register - bit_offset: 0 - bit_size: 32 + - name: RXDR + description: Receive data register + bit_offset: 0 + bit_size: 32 fieldset/SR: description: Status Register fields: - - name: RXP - description: Rx-Packet available - bit_offset: 0 - bit_size: 1 - - name: TXP - description: Tx-Packet space available - bit_offset: 1 - bit_size: 1 - - name: DXP - description: Duplex Packet - bit_offset: 2 - bit_size: 1 - - name: EOT - description: End Of Transfer - bit_offset: 3 - bit_size: 1 - - name: TXTF - description: Transmission Transfer Filled - bit_offset: 4 - bit_size: 1 - - name: UDR - description: Underrun at slave transmission mode - bit_offset: 5 - bit_size: 1 - - name: OVR - description: Overrun - bit_offset: 6 - bit_size: 1 - - name: CRCE - description: CRC Error - bit_offset: 7 - bit_size: 1 - - name: TIFRE - description: TI frame format error - bit_offset: 8 - bit_size: 1 - - name: MODF - description: Mode Fault - bit_offset: 9 - bit_size: 1 - - name: SUSP - description: SUSPend - bit_offset: 11 - bit_size: 1 - - name: TXC - description: TxFIFO transmission complete - bit_offset: 12 - bit_size: 1 - - name: RXPLVL - description: RxFIFO Packing LeVeL - bit_offset: 13 - bit_size: 2 - enum: RXPLVL - - name: RXWNE - description: RxFIFO Word Not Empty - bit_offset: 15 - bit_size: 1 - enum: RXWNE - - name: CTSIZE - description: Number of data frames remaining in current TSIZE session - bit_offset: 16 - bit_size: 16 + - name: RXP + description: Rx-Packet available + bit_offset: 0 + bit_size: 1 + - name: TXP + description: Tx-Packet space available + bit_offset: 1 + bit_size: 1 + - name: DXP + description: Duplex Packet + bit_offset: 2 + bit_size: 1 + - name: EOT + description: End Of Transfer + bit_offset: 3 + bit_size: 1 + - name: TXTF + description: Transmission Transfer Filled + bit_offset: 4 + bit_size: 1 + - name: UDR + description: Underrun at slave transmission mode + bit_offset: 5 + bit_size: 1 + - name: OVR + description: Overrun + bit_offset: 6 + bit_size: 1 + - name: CRCE + description: CRC Error + bit_offset: 7 + bit_size: 1 + - name: TIFRE + description: TI frame format error + bit_offset: 8 + bit_size: 1 + - name: MODF + description: Mode Fault + bit_offset: 9 + bit_size: 1 + - name: SUSP + description: SUSPend + bit_offset: 11 + bit_size: 1 + - name: TXC + description: TxFIFO transmission complete + bit_offset: 12 + bit_size: 1 + - name: RXPLVL + description: RxFIFO Packing LeVeL + bit_offset: 13 + bit_size: 2 + enum: RXPLVL + - name: RXWNE + description: RxFIFO Word Not Empty + bit_offset: 15 + bit_size: 1 + enum: RXWNE + - name: CTSIZE + description: Number of data frames remaining in current TSIZE session + bit_offset: 16 + bit_size: 16 fieldset/TXCRC: description: Transmitter CRC Register fields: - - name: TXCRC - description: CRC register for transmitter - bit_offset: 0 - bit_size: 32 + - name: TXCRC + description: CRC register for transmitter + bit_offset: 0 + bit_size: 32 fieldset/TXDR: description: Transmit Data Register fields: - - name: TXDR - description: Transmit data register - bit_offset: 0 - bit_size: 32 + - name: TXDR + description: Transmit data register + bit_offset: 0 + bit_size: 32 fieldset/UDRDR: description: Underrun Data Register fields: - - name: UDRDR - description: Data at slave underrun condition - bit_offset: 0 - bit_size: 32 + - name: UDRDR + description: Data at slave underrun condition + bit_offset: 0 + bit_size: 32 enum/AFCNTR: bit_size: 1 variants: - - name: NotControlled - description: Peripheral takes no control of GPIOs while disabled - value: 0 - - name: Controlled - description: Peripheral controls GPIOs while disabled - value: 1 + - name: NotControlled + description: Peripheral takes no control of GPIOs while disabled + value: 0 + - name: Controlled + description: Peripheral controls GPIOs while disabled + value: 1 enum/COMM: bit_size: 2 variants: - - name: FullDuplex - description: Full duplex - value: 0 - - name: Transmitter - description: Simplex transmitter only - value: 1 - - name: Receiver - description: Simplex receiver only - value: 2 - - name: HalfDuplex - description: Half duplex - value: 3 + - name: FullDuplex + description: Full duplex + value: 0 + - name: Transmitter + description: Simplex transmitter only + value: 1 + - name: Receiver + description: Simplex receiver only + value: 2 + - name: HalfDuplex + description: Half duplex + value: 3 enum/CPHA: bit_size: 1 variants: - - name: FirstEdge - description: The first clock transition is the first data capture edge - value: 0 - - name: SecondEdge - description: The second clock transition is the first data capture edge - value: 1 + - name: FirstEdge + description: The first clock transition is the first data capture edge + value: 0 + - name: SecondEdge + description: The second clock transition is the first data capture edge + value: 1 enum/CPOL: bit_size: 1 variants: - - name: IdleLow - description: CK to 0 when idle - value: 0 - - name: IdleHigh - description: CK to 1 when idle - value: 1 + - name: IdleLow + description: CK to 0 when idle + value: 0 + - name: IdleHigh + description: CK to 1 when idle + value: 1 enum/CRC_: bit_size: 1 variants: - - name: Disabled - description: Full size (33/17 bit) CRC polynomial is not used - value: 0 - - name: Enabled - description: Full size (33/17 bit) CRC polynomial is used - value: 1 + - name: Disabled + description: Full size (33/17 bit) CRC polynomial is not used + value: 0 + - name: Enabled + description: Full size (33/17 bit) CRC polynomial is used + value: 1 enum/FTHLV: bit_size: 4 variants: - - name: OneFrame - description: 1 frame - value: 0 - - name: TwoFrames - description: 2 frames - value: 1 - - name: ThreeFrames - description: 3 frames - value: 2 - - name: FourFrames - description: 4 frames - value: 3 - - name: FiveFrames - description: 5 frames - value: 4 - - name: SixFrames - description: 6 frames - value: 5 - - name: SevenFrames - description: 7 frames - value: 6 - - name: EightFrames - description: 8 frames - value: 7 - - name: NineFrames - description: 9 frames - value: 8 - - name: TenFrames - description: 10 frames - value: 9 - - name: ElevenFrames - description: 11 frames - value: 10 - - name: TwelveFrames - description: 12 frames - value: 11 - - name: ThirteenFrames - description: 13 frames - value: 12 - - name: FourteenFrames - description: 14 frames - value: 13 - - name: FifteenFrames - description: 15 frames - value: 14 - - name: SixteenFrames - description: 16 frames - value: 15 + - name: OneFrame + description: 1 frame + value: 0 + - name: TwoFrames + description: 2 frames + value: 1 + - name: ThreeFrames + description: 3 frames + value: 2 + - name: FourFrames + description: 4 frames + value: 3 + - name: FiveFrames + description: 5 frames + value: 4 + - name: SixFrames + description: 6 frames + value: 5 + - name: SevenFrames + description: 7 frames + value: 6 + - name: EightFrames + description: 8 frames + value: 7 + - name: NineFrames + description: 9 frames + value: 8 + - name: TenFrames + description: 10 frames + value: 9 + - name: ElevenFrames + description: 11 frames + value: 10 + - name: TwelveFrames + description: 12 frames + value: 11 + - name: ThirteenFrames + description: 13 frames + value: 12 + - name: FourteenFrames + description: 14 frames + value: 13 + - name: FifteenFrames + description: 15 frames + value: 14 + - name: SixteenFrames + description: 16 frames + value: 15 enum/HDDIR: bit_size: 1 variants: - - name: Receiver - description: Receiver in half duplex mode - value: 0 - - name: Transmitter - description: Transmitter in half duplex mode - value: 1 + - name: Receiver + description: Receiver in half duplex mode + value: 0 + - name: Transmitter + description: Transmitter in half duplex mode + value: 1 enum/LSBFIRST: bit_size: 1 variants: - - name: MSBFirst - description: Data is transmitted/received with the MSB first - value: 0 - - name: LSBFirst - description: Data is transmitted/received with the LSB first - value: 1 + - name: MSBFirst + description: Data is transmitted/received with the MSB first + value: 0 + - name: LSBFirst + description: Data is transmitted/received with the LSB first + value: 1 enum/MASTER: bit_size: 1 variants: - - name: Slave - description: Slave configuration - value: 0 - - name: Master - description: Master configuration - value: 1 + - name: Slave + description: Slave configuration + value: 0 + - name: Master + description: Master configuration + value: 1 enum/MBR: bit_size: 3 variants: - - name: Div2 - description: f_spi_ker_ck / 2 - value: 0 - - name: Div4 - description: f_spi_ker_ck / 4 - value: 1 - - name: Div8 - description: f_spi_ker_ck / 8 - value: 2 - - name: Div16 - description: f_spi_ker_ck / 16 - value: 3 - - name: Div32 - description: f_spi_ker_ck / 32 - value: 4 - - name: Div64 - description: f_spi_ker_ck / 64 - value: 5 - - name: Div128 - description: f_spi_ker_ck / 128 - value: 6 - - name: Div256 - description: f_spi_ker_ck / 256 - value: 7 + - name: Div2 + description: f_spi_ker_ck / 2 + value: 0 + - name: Div4 + description: f_spi_ker_ck / 4 + value: 1 + - name: Div8 + description: f_spi_ker_ck / 8 + value: 2 + - name: Div16 + description: f_spi_ker_ck / 16 + value: 3 + - name: Div32 + description: f_spi_ker_ck / 32 + value: 4 + - name: Div64 + description: f_spi_ker_ck / 64 + value: 5 + - name: Div128 + description: f_spi_ker_ck / 128 + value: 6 + - name: Div256 + description: f_spi_ker_ck / 256 + value: 7 enum/RCRCINI: bit_size: 1 variants: - - name: AllZeros - description: All zeros RX CRC initialization pattern - value: 0 - - name: AllOnes - description: All ones RX CRC initialization pattern - value: 1 + - name: AllZeros + description: All zeros RX CRC initialization pattern + value: 0 + - name: AllOnes + description: All ones RX CRC initialization pattern + value: 1 enum/RDIOM: bit_size: 1 variants: - - name: PermanentlyActive - description: RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) - value: 0 - - name: FromInput - description: RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) - value: 1 + - name: PermanentlyActive + description: RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) + value: 0 + - name: FromInput + description: RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) + value: 1 enum/RDIOP: bit_size: 1 variants: - - name: ReadyHigh - description: high level of the signal means the slave is ready for communication - value: 0 - - name: ReadyLow - description: low level of the signal means the slave is ready for communication - value: 1 + - name: ReadyHigh + description: high level of the signal means the slave is ready for communication + value: 0 + - name: ReadyLow + description: low level of the signal means the slave is ready for communication + value: 1 enum/RXPLVL: bit_size: 2 variants: - - name: ZeroFrames - description: Zero frames beyond packing ratio available - value: 0 - - name: OneFrame - description: One frame beyond packing ratio available - value: 1 - - name: TwoFrames - description: Two frame beyond packing ratio available - value: 2 - - name: ThreeFrames - description: Three frame beyond packing ratio available - value: 3 + - name: ZeroFrames + description: Zero frames beyond packing ratio available + value: 0 + - name: OneFrame + description: One frame beyond packing ratio available + value: 1 + - name: TwoFrames + description: Two frame beyond packing ratio available + value: 2 + - name: ThreeFrames + description: Three frame beyond packing ratio available + value: 3 enum/RXWNE: bit_size: 1 variants: - - name: LessThan32 - description: Less than 32-bit data frame received - value: 0 - - name: AtLeast32 - description: At least 32-bit data frame received - value: 1 + - name: LessThan32 + description: Less than 32-bit data frame received + value: 0 + - name: AtLeast32 + description: At least 32-bit data frame received + value: 1 enum/SP: bit_size: 3 variants: - - name: Motorola - description: Motorola SPI protocol - value: 0 - - name: TI - description: TI SPI protocol - value: 1 + - name: Motorola + description: Motorola SPI protocol + value: 0 + - name: TI + description: TI SPI protocol + value: 1 enum/SSIOP: bit_size: 1 variants: - - name: ActiveLow - description: Low level is active for SS signal - value: 0 - - name: ActiveHigh - description: High level is active for SS signal - value: 1 + - name: ActiveLow + description: Low level is active for SS signal + value: 0 + - name: ActiveHigh + description: High level is active for SS signal + value: 1 enum/SSOM: bit_size: 1 variants: - - name: Asserted - description: SS is asserted until data transfer complete - value: 0 - - name: NotAsserted - description: Data frames interleaved with SS not asserted during MIDI - value: 1 + - name: Asserted + description: SS is asserted until data transfer complete + value: 0 + - name: NotAsserted + description: Data frames interleaved with SS not asserted during MIDI + value: 1 enum/TCRCINI: bit_size: 1 variants: - - name: AllZeros - description: All zeros TX CRC initialization pattern - value: 0 - - name: AllOnes - description: All ones TX CRC initialization pattern - value: 1 + - name: AllZeros + description: All zeros TX CRC initialization pattern + value: 0 + - name: AllOnes + description: All ones TX CRC initialization pattern + value: 1 enum/TRIGPOL: bit_size: 1 variants: - - name: RisingEdge - description: trigger is active on raising edge - value: 0 - - name: FallingEdge - description: trigger is active on falling edge - value: 1 + - name: RisingEdge + description: trigger is active on raising edge + value: 0 + - name: FallingEdge + description: trigger is active on falling edge + value: 1 enum/UDRCFG: bit_size: 2 variants: - - name: Constant - description: Slave sends a constant underrun pattern - value: 0 - - name: RepeatReceived - description: Slave repeats last received data frame from master - value: 1 - - name: RepeatTransmitted - description: Slave repeats last transmitted data frame - value: 2 + - name: Constant + description: Slave sends a constant underrun pattern + value: 0 + - name: RepeatReceived + description: Slave repeats last received data frame from master + value: 1 + - name: RepeatTransmitted + description: Slave repeats last transmitted data frame + value: 2 diff --git a/data/registers/syscfg_c0.yaml b/data/registers/syscfg_c0.yaml index b52448b..a7ec916 100644 --- a/data/registers/syscfg_c0.yaml +++ b/data/registers/syscfg_c0.yaml @@ -1,522 +1,521 @@ ---- block/SYSCFG: description: register block items: - - name: CFGR1 - description: configuration register 1 - byte_offset: 0 - fieldset: CFGR1 - - name: CFGR2 - description: configuration register 2 - byte_offset: 24 - fieldset: CFGR2 - - name: CFGR3 - description: configuration register 3 - byte_offset: 60 - fieldset: CFGR3 - - name: ITLINE0 - description: interrupt line 0 status register - byte_offset: 128 - access: Read - fieldset: ITLINE0 - - name: ITLINE2 - description: interrupt line 2 status register - byte_offset: 136 - access: Read - fieldset: ITLINE2 - - name: ITLINE3 - description: interrupt line 3 status register - byte_offset: 140 - access: Read - fieldset: ITLINE3 - - name: ITLINE4 - description: interrupt line 4 status register - byte_offset: 144 - access: Read - fieldset: ITLINE4 - - name: ITLINE5 - description: interrupt line 5 status register - byte_offset: 148 - access: Read - fieldset: ITLINE5 - - name: ITLINE6 - description: interrupt line 6 status register - byte_offset: 152 - access: Read - fieldset: ITLINE6 - - name: ITLINE7 - description: interrupt line 7 status register - byte_offset: 156 - access: Read - fieldset: ITLINE7 - - name: ITLINE9 - description: interrupt line 9 status register - byte_offset: 164 - access: Read - fieldset: ITLINE9 - - name: ITLINE10 - description: interrupt line 10 status register - byte_offset: 168 - access: Read - fieldset: ITLINE10 - - name: ITLINE11 - description: interrupt line 11 status register - byte_offset: 172 - access: Read - fieldset: ITLINE11 - - name: ITLINE12 - description: interrupt line 12 status register - byte_offset: 176 - access: Read - fieldset: ITLINE12 - - name: ITLINE13 - description: interrupt line 13 status register - byte_offset: 180 - access: Read - fieldset: ITLINE13 - - name: ITLINE14 - description: interrupt line 14 status register - byte_offset: 184 - access: Read - fieldset: ITLINE14 - - name: ITLINE16 - description: interrupt line 16 status register - byte_offset: 192 - access: Read - fieldset: ITLINE16 - - name: ITLINE19 - description: interrupt line 19 status register - byte_offset: 204 - access: Read - fieldset: ITLINE19 - - name: ITLINE21 - description: interrupt line 21 status register - byte_offset: 212 - access: Read - fieldset: ITLINE21 - - name: ITLINE22 - description: interrupt line 22 status register - byte_offset: 216 - access: Read - fieldset: ITLINE22 - - name: ITLINE23 - description: interrupt line 23 status register - byte_offset: 220 - access: Read - fieldset: ITLINE23 - - name: ITLINE25 - description: interrupt line 25 status register - byte_offset: 228 - access: Read - fieldset: ITLINE25 - - name: ITLINE27 - description: interrupt line 27 status register - byte_offset: 236 - access: Read - fieldset: ITLINE27 - - name: ITLINE28 - description: interrupt line 28 status register - byte_offset: 240 - access: Read - fieldset: ITLINE28 + - name: CFGR1 + description: configuration register 1 + byte_offset: 0 + fieldset: CFGR1 + - name: CFGR2 + description: configuration register 2 + byte_offset: 24 + fieldset: CFGR2 + - name: CFGR3 + description: configuration register 3 + byte_offset: 60 + fieldset: CFGR3 + - name: ITLINE0 + description: interrupt line 0 status register + byte_offset: 128 + access: Read + fieldset: ITLINE0 + - name: ITLINE2 + description: interrupt line 2 status register + byte_offset: 136 + access: Read + fieldset: ITLINE2 + - name: ITLINE3 + description: interrupt line 3 status register + byte_offset: 140 + access: Read + fieldset: ITLINE3 + - name: ITLINE4 + description: interrupt line 4 status register + byte_offset: 144 + access: Read + fieldset: ITLINE4 + - name: ITLINE5 + description: interrupt line 5 status register + byte_offset: 148 + access: Read + fieldset: ITLINE5 + - name: ITLINE6 + description: interrupt line 6 status register + byte_offset: 152 + access: Read + fieldset: ITLINE6 + - name: ITLINE7 + description: interrupt line 7 status register + byte_offset: 156 + access: Read + fieldset: ITLINE7 + - name: ITLINE9 + description: interrupt line 9 status register + byte_offset: 164 + access: Read + fieldset: ITLINE9 + - name: ITLINE10 + description: interrupt line 10 status register + byte_offset: 168 + access: Read + fieldset: ITLINE10 + - name: ITLINE11 + description: interrupt line 11 status register + byte_offset: 172 + access: Read + fieldset: ITLINE11 + - name: ITLINE12 + description: interrupt line 12 status register + byte_offset: 176 + access: Read + fieldset: ITLINE12 + - name: ITLINE13 + description: interrupt line 13 status register + byte_offset: 180 + access: Read + fieldset: ITLINE13 + - name: ITLINE14 + description: interrupt line 14 status register + byte_offset: 184 + access: Read + fieldset: ITLINE14 + - name: ITLINE16 + description: interrupt line 16 status register + byte_offset: 192 + access: Read + fieldset: ITLINE16 + - name: ITLINE19 + description: interrupt line 19 status register + byte_offset: 204 + access: Read + fieldset: ITLINE19 + - name: ITLINE21 + description: interrupt line 21 status register + byte_offset: 212 + access: Read + fieldset: ITLINE21 + - name: ITLINE22 + description: interrupt line 22 status register + byte_offset: 216 + access: Read + fieldset: ITLINE22 + - name: ITLINE23 + description: interrupt line 23 status register + byte_offset: 220 + access: Read + fieldset: ITLINE23 + - name: ITLINE25 + description: interrupt line 25 status register + byte_offset: 228 + access: Read + fieldset: ITLINE25 + - name: ITLINE27 + description: interrupt line 27 status register + byte_offset: 236 + access: Read + fieldset: ITLINE27 + - name: ITLINE28 + description: interrupt line 28 status register + byte_offset: 240 + access: Read + fieldset: ITLINE28 fieldset/CFGR1: description: configuration register 1 fields: - - name: MEM_MODE - description: Memory mapping selection bits. This bitfield controlled by software selects the memory internally mapped at the address 0x0000_0000. Its reset value is determined by the boot mode configuration. Refer to Reference Manual section 2.5 for more details. - bit_offset: 0 - bit_size: 2 - enum: MEM_MODE - - name: PA11_RMP - description: "PA11 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port." - bit_offset: 3 - bit_size: 1 - - name: PA12_RMP - description: "PA12 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port." - bit_offset: 4 - bit_size: 1 - - name: IR_POL - description: IR output polarity selection - bit_offset: 5 - bit_size: 1 - - name: IR_MOD - description: "IR Modulation Envelope signal selection\r This bitfield selects the signal for IR modulation envelope:" - bit_offset: 6 - bit_size: 2 - enum: IR_MOD - - name: I2C_PB6_FMP - description: "Fast Mode Plus (FM+) enable for PB6\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." - bit_offset: 16 - bit_size: 1 - - name: I2C_PB7_FMP - description: "Fast Mode Plus (FM+) enable for PB7\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." - bit_offset: 17 - bit_size: 1 - - name: I2C_PB8_FMP - description: "Fast Mode Plus (FM+) enable for PB8\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." - bit_offset: 18 - bit_size: 1 - - name: I2C_PB9_FMP - description: "Fast Mode Plus (FM+) enable for PB9\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." - bit_offset: 19 - bit_size: 1 - - name: I2C1_FMP - description: "Fast Mode Plus (FM+) enable for I2C1\r This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports configured as I2C1 through GPIOx_AFR registers.\r With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C1 can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the speed control is ignored." - bit_offset: 20 - bit_size: 1 - - name: I2C_PA9_FMP - description: "Fast Mode Plus (FM+) enable for PA9\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." - bit_offset: 22 - bit_size: 1 - - name: I2C_PA10_FMP - description: "Fast Mode Plus (FM+) enable for PA10\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." - bit_offset: 23 - bit_size: 1 - - name: I2C_PC14_FMP - description: "Fast Mode Plus (FM+) enable for PC14\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PC14 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." - bit_offset: 24 - bit_size: 1 + - name: MEM_MODE + description: Memory mapping selection bits. This bitfield controlled by software selects the memory internally mapped at the address 0x0000_0000. Its reset value is determined by the boot mode configuration. Refer to Reference Manual section 2.5 for more details. + bit_offset: 0 + bit_size: 2 + enum: MEM_MODE + - name: PA11_RMP + description: "PA11 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port." + bit_offset: 3 + bit_size: 1 + - name: PA12_RMP + description: "PA12 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port." + bit_offset: 4 + bit_size: 1 + - name: IR_POL + description: IR output polarity selection + bit_offset: 5 + bit_size: 1 + - name: IR_MOD + description: "IR Modulation Envelope signal selection\r This bitfield selects the signal for IR modulation envelope:" + bit_offset: 6 + bit_size: 2 + enum: IR_MOD + - name: I2C_PB6_FMP + description: "Fast Mode Plus (FM+) enable for PB6\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." + bit_offset: 16 + bit_size: 1 + - name: I2C_PB7_FMP + description: "Fast Mode Plus (FM+) enable for PB7\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." + bit_offset: 17 + bit_size: 1 + - name: I2C_PB8_FMP + description: "Fast Mode Plus (FM+) enable for PB8\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." + bit_offset: 18 + bit_size: 1 + - name: I2C_PB9_FMP + description: "Fast Mode Plus (FM+) enable for PB9\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." + bit_offset: 19 + bit_size: 1 + - name: I2C1_FMP + description: "Fast Mode Plus (FM+) enable for I2C1\r This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports configured as I2C1 through GPIOx_AFR registers.\r With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C1 can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the speed control is ignored." + bit_offset: 20 + bit_size: 1 + - name: I2C_PA9_FMP + description: "Fast Mode Plus (FM+) enable for PA9\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." + bit_offset: 22 + bit_size: 1 + - name: I2C_PA10_FMP + description: "Fast Mode Plus (FM+) enable for PA10\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." + bit_offset: 23 + bit_size: 1 + - name: I2C_PC14_FMP + description: "Fast Mode Plus (FM+) enable for PC14\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PC14 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." + bit_offset: 24 + bit_size: 1 fieldset/CFGR2: description: configuration register 2 fields: - - name: LOCKUP_LOCK - description: "Cortex�-M0+ LOCKUP enable\r This bit is set by software and cleared by system reset. When set, it enables the connection of Cortex�-M0+ LOCKUP (HardFault) output to the TIM1/16/17 Break input." - bit_offset: 0 - bit_size: 1 + - name: LOCKUP_LOCK + description: "Cortex�-M0+ LOCKUP enable\r This bit is set by software and cleared by system reset. When set, it enables the connection of Cortex�-M0+ LOCKUP (HardFault) output to the TIM1/16/17 Break input." + bit_offset: 0 + bit_size: 1 fieldset/CFGR3: description: configuration register 3 fields: - - name: PINMUX0 - description: "Pin GPIO multiplexer 0\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved\r Pin F2 of WLCSP14 package GPIO assignment\r 1x: Reserved" - bit_offset: 0 - bit_size: 2 - enum: PINMUX0 - - name: PINMUX1 - description: "Pin GPIO multiplexer 1\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved" - bit_offset: 2 - bit_size: 2 - enum: PINMUX1 - - name: PINMUX2 - description: "Pin GPIO multiplexer 2\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved\r 1x: Reserved" - bit_offset: 4 - bit_size: 2 - enum: PINMUX2 - - name: PINMUX3 - description: "Pin GPIO multiplexer 3\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved" - bit_offset: 6 - bit_size: 2 - enum: PINMUX3 - - name: PINMUX4 - description: "Pin GPIO multiplexer 4\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved\r 1x: Reserved" - bit_offset: 8 - bit_size: 2 - enum: PINMUX4 - - name: PINMUX5 - description: "Pin GPIO multiplexer 5\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved" - bit_offset: 10 - bit_size: 2 - enum: PINMUX5 + - name: PINMUX0 + description: "Pin GPIO multiplexer 0\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved\r Pin F2 of WLCSP14 package GPIO assignment\r 1x: Reserved" + bit_offset: 0 + bit_size: 2 + enum: PINMUX0 + - name: PINMUX1 + description: "Pin GPIO multiplexer 1\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved" + bit_offset: 2 + bit_size: 2 + enum: PINMUX1 + - name: PINMUX2 + description: "Pin GPIO multiplexer 2\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved\r 1x: Reserved" + bit_offset: 4 + bit_size: 2 + enum: PINMUX2 + - name: PINMUX3 + description: "Pin GPIO multiplexer 3\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved" + bit_offset: 6 + bit_size: 2 + enum: PINMUX3 + - name: PINMUX4 + description: "Pin GPIO multiplexer 4\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved\r 1x: Reserved" + bit_offset: 8 + bit_size: 2 + enum: PINMUX4 + - name: PINMUX5 + description: "Pin GPIO multiplexer 5\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved" + bit_offset: 10 + bit_size: 2 + enum: PINMUX5 fieldset/ITLINE0: description: interrupt line 0 status register fields: - - name: WWDG - description: Window watchdog interrupt pending flag - bit_offset: 0 - bit_size: 1 + - name: WWDG + description: Window watchdog interrupt pending flag + bit_offset: 0 + bit_size: 1 fieldset/ITLINE10: description: interrupt line 10 status register fields: - - name: DMA1_CH2 - description: DMA1 channel 2 interrupt request pending - bit_offset: 0 - bit_size: 1 - - name: DMA1_CH3 - description: DMA1 channel 3 interrupt request pending - bit_offset: 1 - bit_size: 1 + - name: DMA1_CH2 + description: DMA1 channel 2 interrupt request pending + bit_offset: 0 + bit_size: 1 + - name: DMA1_CH3 + description: DMA1 channel 3 interrupt request pending + bit_offset: 1 + bit_size: 1 fieldset/ITLINE11: description: interrupt line 11 status register fields: - - name: DMAMUX - description: DMAMUX interrupt request pending - bit_offset: 0 - bit_size: 1 + - name: DMAMUX + description: DMAMUX interrupt request pending + bit_offset: 0 + bit_size: 1 fieldset/ITLINE12: description: interrupt line 12 status register fields: - - name: ADC - description: ADC interrupt request pending - bit_offset: 0 - bit_size: 1 + - name: ADC + description: ADC interrupt request pending + bit_offset: 0 + bit_size: 1 fieldset/ITLINE13: description: interrupt line 13 status register fields: - - name: TIM1_CCU - description: Timer 1 commutation interrupt request pending - bit_offset: 0 - bit_size: 1 - - name: TIM1_TRG - description: Timer 1 trigger interrupt request pending - bit_offset: 1 - bit_size: 1 - - name: TIM1_UPD - description: Timer 1 update interrupt request pending - bit_offset: 2 - bit_size: 1 - - name: TIM1_BRK - description: Timer 1 break interrupt request pending - bit_offset: 3 - bit_size: 1 + - name: TIM1_CCU + description: Timer 1 commutation interrupt request pending + bit_offset: 0 + bit_size: 1 + - name: TIM1_TRG + description: Timer 1 trigger interrupt request pending + bit_offset: 1 + bit_size: 1 + - name: TIM1_UPD + description: Timer 1 update interrupt request pending + bit_offset: 2 + bit_size: 1 + - name: TIM1_BRK + description: Timer 1 break interrupt request pending + bit_offset: 3 + bit_size: 1 fieldset/ITLINE14: description: interrupt line 14 status register fields: - - name: TIM1_CC - description: Timer 1 capture compare interrupt request pending - bit_offset: 0 - bit_size: 1 + - name: TIM1_CC + description: Timer 1 capture compare interrupt request pending + bit_offset: 0 + bit_size: 1 fieldset/ITLINE16: description: interrupt line 16 status register fields: - - name: TIM3 - description: Timer 3 interrupt request pending - bit_offset: 0 - bit_size: 1 + - name: TIM3 + description: Timer 3 interrupt request pending + bit_offset: 0 + bit_size: 1 fieldset/ITLINE19: description: interrupt line 19 status register fields: - - name: TIM14 - description: Timer 14 interrupt request pending - bit_offset: 0 - bit_size: 1 + - name: TIM14 + description: Timer 14 interrupt request pending + bit_offset: 0 + bit_size: 1 fieldset/ITLINE2: description: interrupt line 2 status register fields: - - name: RTC - description: RTC interrupt request pending (EXTI line 19) - bit_offset: 1 - bit_size: 1 + - name: RTC + description: RTC interrupt request pending (EXTI line 19) + bit_offset: 1 + bit_size: 1 fieldset/ITLINE21: description: interrupt line 21 status register fields: - - name: TIM16 - description: Timer 16 interrupt request pending - bit_offset: 0 - bit_size: 1 + - name: TIM16 + description: Timer 16 interrupt request pending + bit_offset: 0 + bit_size: 1 fieldset/ITLINE22: description: interrupt line 22 status register fields: - - name: TIM17 - description: Timer 17 interrupt request pending - bit_offset: 0 - bit_size: 1 + - name: TIM17 + description: Timer 17 interrupt request pending + bit_offset: 0 + bit_size: 1 fieldset/ITLINE23: description: interrupt line 23 status register fields: - - name: I2C1 - description: "I2C1 interrupt request pending, combined with EXTI line 23" - bit_offset: 0 - bit_size: 1 + - name: I2C1 + description: I2C1 interrupt request pending, combined with EXTI line 23 + bit_offset: 0 + bit_size: 1 fieldset/ITLINE25: description: interrupt line 25 status register fields: - - name: SPI1 - description: SPI1 interrupt request pending - bit_offset: 0 - bit_size: 1 + - name: SPI1 + description: SPI1 interrupt request pending + bit_offset: 0 + bit_size: 1 fieldset/ITLINE27: description: interrupt line 27 status register fields: - - name: USART1 - description: "USART1 interrupt request pending, combined with EXTI line 25" - bit_offset: 0 - bit_size: 1 + - name: USART1 + description: USART1 interrupt request pending, combined with EXTI line 25 + bit_offset: 0 + bit_size: 1 fieldset/ITLINE28: description: interrupt line 28 status register fields: - - name: USART2 - description: USART2 interrupt request pending (EXTI line 26) - bit_offset: 0 - bit_size: 1 + - name: USART2 + description: USART2 interrupt request pending (EXTI line 26) + bit_offset: 0 + bit_size: 1 fieldset/ITLINE3: description: interrupt line 3 status register fields: - - name: FLASH_ITF - description: Flash interface interrupt request pending - bit_offset: 1 - bit_size: 1 + - name: FLASH_ITF + description: Flash interface interrupt request pending + bit_offset: 1 + bit_size: 1 fieldset/ITLINE4: description: interrupt line 4 status register fields: - - name: RCC - description: Reset and clock control interrupt request pending - bit_offset: 0 - bit_size: 1 + - name: RCC + description: Reset and clock control interrupt request pending + bit_offset: 0 + bit_size: 1 fieldset/ITLINE5: description: interrupt line 5 status register fields: - - name: EXTI - description: EXTI - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 + - name: EXTI + description: EXTI + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 fieldset/ITLINE6: description: interrupt line 6 status register fields: - - name: EXTI - description: EXTI - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 + - name: EXTI + description: EXTI + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 fieldset/ITLINE7: description: interrupt line 7 status register fields: - - name: EXTI - description: EXTI - bit_offset: 0 - bit_size: 1 - array: - len: 12 - stride: 1 + - name: EXTI + description: EXTI + bit_offset: 0 + bit_size: 1 + array: + len: 12 + stride: 1 fieldset/ITLINE9: description: interrupt line 9 status register fields: - - name: DMA1_CH1 - description: DMA1 channel 1interrupt request pending - bit_offset: 0 - bit_size: 1 + - name: DMA1_CH1 + description: DMA1 channel 1interrupt request pending + bit_offset: 0 + bit_size: 1 enum/IR_MOD: bit_size: 2 variants: - - name: TIM16 - description: TIM16 - value: 0 - - name: USART1 - description: USART1 - value: 1 - - name: USART2 - description: USART2 - value: 2 + - name: TIM16 + description: TIM16 + value: 0 + - name: USART1 + description: USART1 + value: 1 + - name: USART2 + description: USART2 + value: 2 enum/MEM_MODE: bit_size: 2 variants: - - name: MAIN_FLASH - description: Main Flash memory mapped at address 0 - value: 0 - - name: SYSTEM_FLASH - description: System Flash memory mapped at address 0 - value: 1 - - name: MAIN_FLASH_ALT - description: Main Flash memory mapped at address 0 (alternate encoding) - value: 2 - - name: SRAM - description: Embedded SRAM mapped at address 0 - value: 3 + - name: MAIN_FLASH + description: Main Flash memory mapped at address 0 + value: 0 + - name: SYSTEM_FLASH + description: System Flash memory mapped at address 0 + value: 1 + - name: MAIN_FLASH_ALT + description: Main Flash memory mapped at address 0 (alternate encoding) + value: 2 + - name: SRAM + description: Embedded SRAM mapped at address 0 + value: 3 enum/PINMUX0: bit_size: 2 variants: - - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1 - description: PB7 - value: 0 - - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_F2 - description: PA1 - value: 0 - - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1 - description: PC14 - value: 1 - - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_F2 - description: PA2 - value: 1 + - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1 + description: PB7 + value: 0 + - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_F2 + description: PA1 + value: 0 + - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1 + description: PC14 + value: 1 + - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_F2 + description: PA2 + value: 1 enum/PINMUX1: bit_size: 2 variants: - - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4 - description: PF2 - value: 0 - - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G3 - description: PF2 - value: 0 - - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4 - description: PA0 - value: 1 - - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G3 - description: PA0 - value: 1 - - name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4 - description: PA1 - value: 2 - - name: B_0x3_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4 - description: PA2 - value: 3 + - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4 + description: PF2 + value: 0 + - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G3 + description: PF2 + value: 0 + - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4 + description: PA0 + value: 1 + - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G3 + description: PA0 + value: 1 + - name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4 + description: PA1 + value: 2 + - name: B_0x3_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4 + description: PA2 + value: 3 enum/PINMUX2: bit_size: 2 variants: - - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5 - description: PA8 - value: 0 - - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J1 - description: PA8 - value: 0 - - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5 - description: PA11 - value: 1 - - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J1 - description: PA11 - value: 1 + - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5 + description: PA8 + value: 0 + - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J1 + description: PA8 + value: 0 + - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5 + description: PA11 + value: 1 + - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J1 + description: PA11 + value: 1 enum/PINMUX3: bit_size: 2 variants: - - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8 - description: PA14 - value: 0 - - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_H2 - description: PA5 - value: 0 - - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8 - description: PB6 - value: 1 - - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_H2 - description: PA6 - value: 1 - - name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8 - description: PC15 - value: 2 + - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8 + description: PA14 + value: 0 + - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_H2 + description: PA5 + value: 0 + - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8 + description: PB6 + value: 1 + - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_H2 + description: PA6 + value: 1 + - name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8 + description: PC15 + value: 2 enum/PINMUX4: bit_size: 2 variants: - - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2 - description: PA7 - value: 0 - - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G1 - description: PA7 - value: 0 - - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2 - description: PA12 - value: 1 - - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G1 - description: PA12 - value: 1 + - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2 + description: PA7 + value: 0 + - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G1 + description: PA7 + value: 0 + - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2 + description: PA12 + value: 1 + - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G1 + description: PA12 + value: 1 enum/PINMUX5: bit_size: 2 variants: - - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1 - description: PA3 - value: 0 - - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J3 - description: PA3 - value: 0 - - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1 - description: PA4 - value: 1 - - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J3 - description: PA4 - value: 1 - - name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1 - description: PA5 - value: 2 - - name: B_0x3_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1 - description: PA6 - value: 3 + - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1 + description: PA3 + value: 0 + - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J3 + description: PA3 + value: 0 + - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1 + description: PA4 + value: 1 + - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J3 + description: PA4 + value: 1 + - name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1 + description: PA5 + value: 2 + - name: B_0x3_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1 + description: PA6 + value: 3 diff --git a/data/registers/syscfg_f0.yaml b/data/registers/syscfg_f0.yaml index 91caf2e..de839ae 100644 --- a/data/registers/syscfg_f0.yaml +++ b/data/registers/syscfg_f0.yaml @@ -1,440 +1,439 @@ ---- block/SYSCFG: description: System configuration controller items: - - name: CFGR1 - description: configuration register 1 - byte_offset: 0 - fieldset: CFGR1 - - name: EXTICR - description: external interrupt configuration register 1 - array: - len: 4 - stride: 4 - byte_offset: 8 - fieldset: EXTICR - - name: CFGR2 - description: configuration register 2 - byte_offset: 24 - fieldset: CFGR2 + - name: CFGR1 + description: configuration register 1 + byte_offset: 0 + fieldset: CFGR1 + - name: EXTICR + description: external interrupt configuration register 1 + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: CFGR2 + description: configuration register 2 + byte_offset: 24 + fieldset: CFGR2 fieldset/CFGR1: description: configuration register 1 fields: - - name: MEM_MODE - description: Memory mapping selection bits - bit_offset: 0 - bit_size: 2 - enum: MEM_MODE - - name: PA11_PA12_RMP - description: PA11 and PA12 remapping bit for small packages (28 and 20 pins) - bit_offset: 4 - bit_size: 1 - enum: PA11_PA12_RMP - - name: IR_MOD - description: IR Modulation Envelope signal selection - bit_offset: 6 - bit_size: 2 - enum: IR_MOD - - name: ADC_DMA_RMP - description: ADC DMA remapping bit - bit_offset: 8 - bit_size: 1 - enum: ADC_DMA_RMP - - name: USART1_TX_DMA_RMP - description: USART1_TX DMA remapping bit - bit_offset: 9 - bit_size: 1 - enum: USART1_TX_DMA_RMP - - name: USART1_RX_DMA_RMP - description: USART1_RX DMA request remapping bit - bit_offset: 10 - bit_size: 1 - enum: USART1_RX_DMA_RMP - - name: TIM16_DMA_RMP - description: TIM16 DMA request remapping bit - bit_offset: 11 - bit_size: 1 - enum: TIM16_DMA_RMP - - name: TIM17_DMA_RMP - description: TIM17 DMA request remapping bit - bit_offset: 12 - bit_size: 1 - enum: TIM17_DMA_RMP - - name: TIM16_DMA_RMP2 - description: TIM16 alternate DMA request remapping bit - bit_offset: 13 - bit_size: 1 - enum: TIM16_DMA_RMP2 - - name: TIM17_DMA_RMP2 - description: TIM17 alternate DMA request remapping bit - bit_offset: 14 - bit_size: 1 - enum: TIM17_DMA_RMP2 - - name: I2C_PB6_FMP - description: Fast Mode Plus (FM plus) driving capability activation bits. - bit_offset: 16 - bit_size: 1 - enum: I2C_PB6_FMP - - name: I2C_PB7_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. - bit_offset: 17 - bit_size: 1 - enum: I2C_PB7_FMP - - name: I2C_PB8_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. - bit_offset: 18 - bit_size: 1 - enum: I2C_PB8_FMP - - name: I2C_PB9_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. - bit_offset: 19 - bit_size: 1 - enum: I2C_PB9_FMP - - name: I2C1_FMP - description: FM+ driving capability activation for I2C1 - bit_offset: 20 - bit_size: 1 - enum: I2C1_FMP - - name: I2C2_FMP - description: FM+ driving capability activation for I2C2 - bit_offset: 21 - bit_size: 1 - enum: I2C2_FMP - - name: I2C_PA9_FMP - description: Fast Mode Plus (FM+) driving capability activation bits - bit_offset: 22 - bit_size: 1 - enum: I2C_PA9_FMP - - name: I2C_PA10_FMP - description: Fast Mode Plus (FM+) driving capability activation bits - bit_offset: 23 - bit_size: 1 - enum: I2C_PA10_FMP - - name: SPI2_DMA_RMP - description: SPI2 DMA request remapping bit - bit_offset: 24 - bit_size: 1 - enum: SPI2_DMA_RMP - - name: USART2_DMA_RMP - description: USART2 DMA request remapping bit - bit_offset: 25 - bit_size: 1 - enum: USART2_DMA_RMP - - name: USART3_DMA_RMP - description: USART3 DMA request remapping bit - bit_offset: 26 - bit_size: 1 - enum: USART3_DMA_RMP - - name: I2C1_DMA_RMP - description: I2C1 DMA request remapping bit - bit_offset: 27 - bit_size: 1 - enum: I2C1_DMA_RMP - - name: TIM1_DMA_RMP - description: TIM1 DMA request remapping bit - bit_offset: 28 - bit_size: 1 - enum: TIM1_DMA_RMP - - name: TIM2_DMA_RMP - description: TIM2 DMA request remapping bit - bit_offset: 29 - bit_size: 1 - enum: TIM2_DMA_RMP - - name: TIM3_DMA_RMP - description: TIM3 DMA request remapping bit - bit_offset: 30 - bit_size: 1 - enum: TIM3_DMA_RMP + - name: MEM_MODE + description: Memory mapping selection bits + bit_offset: 0 + bit_size: 2 + enum: MEM_MODE + - name: PA11_PA12_RMP + description: PA11 and PA12 remapping bit for small packages (28 and 20 pins) + bit_offset: 4 + bit_size: 1 + enum: PA11_PA12_RMP + - name: IR_MOD + description: IR Modulation Envelope signal selection + bit_offset: 6 + bit_size: 2 + enum: IR_MOD + - name: ADC_DMA_RMP + description: ADC DMA remapping bit + bit_offset: 8 + bit_size: 1 + enum: ADC_DMA_RMP + - name: USART1_TX_DMA_RMP + description: USART1_TX DMA remapping bit + bit_offset: 9 + bit_size: 1 + enum: USART1_TX_DMA_RMP + - name: USART1_RX_DMA_RMP + description: USART1_RX DMA request remapping bit + bit_offset: 10 + bit_size: 1 + enum: USART1_RX_DMA_RMP + - name: TIM16_DMA_RMP + description: TIM16 DMA request remapping bit + bit_offset: 11 + bit_size: 1 + enum: TIM16_DMA_RMP + - name: TIM17_DMA_RMP + description: TIM17 DMA request remapping bit + bit_offset: 12 + bit_size: 1 + enum: TIM17_DMA_RMP + - name: TIM16_DMA_RMP2 + description: TIM16 alternate DMA request remapping bit + bit_offset: 13 + bit_size: 1 + enum: TIM16_DMA_RMP2 + - name: TIM17_DMA_RMP2 + description: TIM17 alternate DMA request remapping bit + bit_offset: 14 + bit_size: 1 + enum: TIM17_DMA_RMP2 + - name: I2C_PB6_FMP + description: Fast Mode Plus (FM plus) driving capability activation bits. + bit_offset: 16 + bit_size: 1 + enum: I2C_PB6_FMP + - name: I2C_PB7_FMP + description: Fast Mode Plus (FM+) driving capability activation bits. + bit_offset: 17 + bit_size: 1 + enum: I2C_PB7_FMP + - name: I2C_PB8_FMP + description: Fast Mode Plus (FM+) driving capability activation bits. + bit_offset: 18 + bit_size: 1 + enum: I2C_PB8_FMP + - name: I2C_PB9_FMP + description: Fast Mode Plus (FM+) driving capability activation bits. + bit_offset: 19 + bit_size: 1 + enum: I2C_PB9_FMP + - name: I2C1_FMP + description: FM+ driving capability activation for I2C1 + bit_offset: 20 + bit_size: 1 + enum: I2C1_FMP + - name: I2C2_FMP + description: FM+ driving capability activation for I2C2 + bit_offset: 21 + bit_size: 1 + enum: I2C2_FMP + - name: I2C_PA9_FMP + description: Fast Mode Plus (FM+) driving capability activation bits + bit_offset: 22 + bit_size: 1 + enum: I2C_PA9_FMP + - name: I2C_PA10_FMP + description: Fast Mode Plus (FM+) driving capability activation bits + bit_offset: 23 + bit_size: 1 + enum: I2C_PA10_FMP + - name: SPI2_DMA_RMP + description: SPI2 DMA request remapping bit + bit_offset: 24 + bit_size: 1 + enum: SPI2_DMA_RMP + - name: USART2_DMA_RMP + description: USART2 DMA request remapping bit + bit_offset: 25 + bit_size: 1 + enum: USART2_DMA_RMP + - name: USART3_DMA_RMP + description: USART3 DMA request remapping bit + bit_offset: 26 + bit_size: 1 + enum: USART3_DMA_RMP + - name: I2C1_DMA_RMP + description: I2C1 DMA request remapping bit + bit_offset: 27 + bit_size: 1 + enum: I2C1_DMA_RMP + - name: TIM1_DMA_RMP + description: TIM1 DMA request remapping bit + bit_offset: 28 + bit_size: 1 + enum: TIM1_DMA_RMP + - name: TIM2_DMA_RMP + description: TIM2 DMA request remapping bit + bit_offset: 29 + bit_size: 1 + enum: TIM2_DMA_RMP + - name: TIM3_DMA_RMP + description: TIM3 DMA request remapping bit + bit_offset: 30 + bit_size: 1 + enum: TIM3_DMA_RMP fieldset/CFGR2: description: configuration register 2 fields: - - name: LOCKUP_LOCK - description: Cortex-M0 LOCKUP bit enable bit - bit_offset: 0 - bit_size: 1 - enum: LOCKUP_LOCK - - name: SRAM_PARITY_LOCK - description: SRAM parity lock bit - bit_offset: 1 - bit_size: 1 - enum: SRAM_PARITY_LOCK - - name: PVD_LOCK - description: PVD lock enable bit - bit_offset: 2 - bit_size: 1 - enum: PVD_LOCK - - name: SRAM_PEF - description: SRAM parity flag - bit_offset: 8 - bit_size: 1 + - name: LOCKUP_LOCK + description: Cortex-M0 LOCKUP bit enable bit + bit_offset: 0 + bit_size: 1 + enum: LOCKUP_LOCK + - name: SRAM_PARITY_LOCK + description: SRAM parity lock bit + bit_offset: 1 + bit_size: 1 + enum: SRAM_PARITY_LOCK + - name: PVD_LOCK + description: PVD lock enable bit + bit_offset: 2 + bit_size: 1 + enum: PVD_LOCK + - name: SRAM_PEF + description: SRAM parity flag + bit_offset: 8 + bit_size: 1 fieldset/EXTICR: description: external interrupt configuration register 1 fields: - - name: EXTI - description: EXTI configuration bits - bit_offset: 0 - bit_size: 4 - array: - len: 4 - stride: 4 + - name: EXTI + description: EXTI configuration bits + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 enum/ADC_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: ADC DMA request mapped on DMA channel 1 - value: 0 - - name: Remapped - description: ADC DMA request mapped on DMA channel 2 - value: 1 + - name: NotRemapped + description: ADC DMA request mapped on DMA channel 1 + value: 0 + - name: Remapped + description: ADC DMA request mapped on DMA channel 2 + value: 1 enum/I2C1_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively - value: 0 - - name: Remapped - description: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively - value: 1 + - name: NotRemapped + description: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively + value: 0 + - name: Remapped + description: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively + value: 1 enum/I2C1_FMP: bit_size: 1 variants: - - name: Standard - description: FM+ mode is controlled by I2C_Pxx_FMP bits only - value: 0 - - name: FMP - description: FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers - value: 1 + - name: Standard + description: FM+ mode is controlled by I2C_Pxx_FMP bits only + value: 0 + - name: FMP + description: FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers + value: 1 enum/I2C2_FMP: bit_size: 1 variants: - - name: Standard - description: FM+ mode is controlled by I2C_Pxx_FMP bits only - value: 0 - - name: FMP - description: FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers - value: 1 + - name: Standard + description: FM+ mode is controlled by I2C_Pxx_FMP bits only + value: 0 + - name: FMP + description: FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers + value: 1 enum/I2C_PA10_FMP: bit_size: 1 variants: - - name: Standard - description: PA10 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PA10 and the Speed control is bypassed - value: 1 + - name: Standard + description: PA10 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PA10 and the Speed control is bypassed + value: 1 enum/I2C_PA9_FMP: bit_size: 1 variants: - - name: Standard - description: PA9 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PA9 and the Speed control is bypassed - value: 1 + - name: Standard + description: PA9 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PA9 and the Speed control is bypassed + value: 1 enum/I2C_PB6_FMP: bit_size: 1 variants: - - name: Standard - description: PB6 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB6 and the Speed control is bypassed - value: 1 + - name: Standard + description: PB6 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB6 and the Speed control is bypassed + value: 1 enum/I2C_PB7_FMP: bit_size: 1 variants: - - name: Standard - description: PB7 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB7 and the Speed control is bypassed - value: 1 + - name: Standard + description: PB7 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB7 and the Speed control is bypassed + value: 1 enum/I2C_PB8_FMP: bit_size: 1 variants: - - name: Standard - description: PB8 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB8 and the Speed control is bypassed - value: 1 + - name: Standard + description: PB8 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB8 and the Speed control is bypassed + value: 1 enum/I2C_PB9_FMP: bit_size: 1 variants: - - name: Standard - description: PB9 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB9 and the Speed control is bypassed - value: 1 + - name: Standard + description: PB9 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB9 and the Speed control is bypassed + value: 1 enum/IR_MOD: bit_size: 2 variants: - - name: TIM16 - description: TIM16 selected - value: 0 - - name: USART1 - description: USART1 selected - value: 1 - - name: USART4 - description: USART4 selected - value: 2 + - name: TIM16 + description: TIM16 selected + value: 0 + - name: USART1 + description: USART1 selected + value: 1 + - name: USART4 + description: USART4 selected + value: 2 enum/LOCKUP_LOCK: bit_size: 1 variants: - - name: Disconnected - description: Cortex-M0 LOCKUP output disconnected from TIM1/15/16/17 Break input - value: 0 - - name: Connected - description: Cortex-M0 LOCKUP output connected to TIM1/15/16/17 Break input - value: 1 + - name: Disconnected + description: Cortex-M0 LOCKUP output disconnected from TIM1/15/16/17 Break input + value: 0 + - name: Connected + description: Cortex-M0 LOCKUP output connected to TIM1/15/16/17 Break input + value: 1 enum/MEM_MODE: bit_size: 2 variants: - - name: MainFlash - description: Main Flash memory mapped at 0x0000_0000 - value: 0 - - name: SystemFlash - description: System Flash memory mapped at 0x0000_0000 - value: 1 - - name: MainFlash2 - description: Main Flash memory mapped at 0x0000_0000 - value: 2 - - name: SRAM - description: Embedded SRAM mapped at 0x0000_0000 - value: 3 + - name: MainFlash + description: Main Flash memory mapped at 0x0000_0000 + value: 0 + - name: SystemFlash + description: System Flash memory mapped at 0x0000_0000 + value: 1 + - name: MainFlash2 + description: Main Flash memory mapped at 0x0000_0000 + value: 2 + - name: SRAM + description: Embedded SRAM mapped at 0x0000_0000 + value: 3 enum/PA11_PA12_RMP: bit_size: 1 variants: - - name: NotRemapped - description: Pin pair PA9/PA10 mapped on the pins - value: 0 - - name: Remapped - description: Pin pair PA11/PA12 mapped instead of PA9/PA10 - value: 1 + - name: NotRemapped + description: Pin pair PA9/PA10 mapped on the pins + value: 0 + - name: Remapped + description: Pin pair PA11/PA12 mapped instead of PA9/PA10 + value: 1 enum/PVD_LOCK: bit_size: 1 variants: - - name: Disconnected - description: PVD interrupt disconnected from TIM1/15/16/17 Break input - value: 0 - - name: Connected - description: PVD interrupt connected to TIM1/15/16/17 Break input - value: 1 + - name: Disconnected + description: PVD interrupt disconnected from TIM1/15/16/17 Break input + value: 0 + - name: Connected + description: PVD interrupt connected to TIM1/15/16/17 Break input + value: 1 enum/SPI2_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively - value: 0 - - name: Remapped - description: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively - value: 1 + - name: NotRemapped + description: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively + value: 0 + - name: Remapped + description: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively + value: 1 enum/SRAM_PARITY_LOCK: bit_size: 1 variants: - - name: Disconnected - description: SRAM parity error disconnected from TIM1/15/16/17 Break input - value: 0 - - name: Connected - description: SRAM parity error connected to TIM1/15/16/17 Break input - value: 1 + - name: Disconnected + description: SRAM parity error disconnected from TIM1/15/16/17 Break input + value: 0 + - name: Connected + description: SRAM parity error connected to TIM1/15/16/17 Break input + value: 1 enum/TIM16_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 3 - value: 0 - - name: Remapped - description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 4 - value: 1 + - name: NotRemapped + description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 3 + value: 0 + - name: Remapped + description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 4 + value: 1 enum/TIM16_DMA_RMP2: bit_size: 1 variants: - - name: NotAlternateRemapped - description: TIM16 DMA request mapped according to TIM16_DMA_RMP bit - value: 0 - - name: AlternateRemapped - description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 6 - value: 1 + - name: NotAlternateRemapped + description: TIM16 DMA request mapped according to TIM16_DMA_RMP bit + value: 0 + - name: AlternateRemapped + description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 6 + value: 1 enum/TIM17_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 1 - value: 0 - - name: Remapped - description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 2 - value: 1 + - name: NotRemapped + description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 1 + value: 0 + - name: Remapped + description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 2 + value: 1 enum/TIM17_DMA_RMP2: bit_size: 1 variants: - - name: NotAlternateRemapped - description: TIM17 DMA request mapped according to TIM16_DMA_RMP bit - value: 0 - - name: AlternateRemapped - description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 7 - value: 1 + - name: NotAlternateRemapped + description: TIM17 DMA request mapped according to TIM16_DMA_RMP bit + value: 0 + - name: AlternateRemapped + description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 7 + value: 1 enum/TIM1_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: "TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively" - value: 0 - - name: Remapped - description: "TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6" - value: 1 + - name: NotRemapped + description: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively + value: 0 + - name: Remapped + description: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 + value: 1 enum/TIM2_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively - value: 0 - - name: Remapped - description: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 - value: 1 + - name: NotRemapped + description: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively + value: 0 + - name: Remapped + description: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 + value: 1 enum/TIM3_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 - value: 0 - - name: Remapped - description: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 - value: 1 + - name: NotRemapped + description: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 + value: 0 + - name: Remapped + description: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 + value: 1 enum/USART1_RX_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: USART1_RX DMA request mapped on DMA channel 3 - value: 0 - - name: Remapped - description: USART1_RX DMA request mapped on DMA channel 5 - value: 1 + - name: NotRemapped + description: USART1_RX DMA request mapped on DMA channel 3 + value: 0 + - name: Remapped + description: USART1_RX DMA request mapped on DMA channel 5 + value: 1 enum/USART1_TX_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: USART1_TX DMA request mapped on DMA channel 2 - value: 0 - - name: Remapped - description: USART1_TX DMA request mapped on DMA channel 4 - value: 1 + - name: NotRemapped + description: USART1_TX DMA request mapped on DMA channel 2 + value: 0 + - name: Remapped + description: USART1_TX DMA request mapped on DMA channel 4 + value: 1 enum/USART2_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively - value: 0 - - name: Remapped - description: USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively - value: 1 + - name: NotRemapped + description: USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively + value: 0 + - name: Remapped + description: USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively + value: 1 enum/USART3_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively (or simply disabled on STM32F0x0) - value: 0 - - name: Remapped - description: USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively - value: 1 + - name: NotRemapped + description: USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively (or simply disabled on STM32F0x0) + value: 0 + - name: Remapped + description: USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively + value: 1 diff --git a/data/registers/syscfg_f2.yaml b/data/registers/syscfg_f2.yaml index 31160f9..afbe46e 100644 --- a/data/registers/syscfg_f2.yaml +++ b/data/registers/syscfg_f2.yaml @@ -1,75 +1,74 @@ ---- block/SYSCFG: description: System configuration controller items: - - name: MEMRMP - description: memory remap register - byte_offset: 0 - fieldset: MEMRMP - - name: PMC - description: peripheral mode configuration register - byte_offset: 4 - fieldset: PMC - - name: EXTICR - description: external interrupt configuration register 1 - array: - len: 4 - stride: 4 - byte_offset: 8 - fieldset: EXTICR - - name: CMPCR - description: Compensation cell control register - byte_offset: 32 - access: Read - fieldset: CMPCR + - name: MEMRMP + description: memory remap register + byte_offset: 0 + fieldset: MEMRMP + - name: PMC + description: peripheral mode configuration register + byte_offset: 4 + fieldset: PMC + - name: EXTICR + description: external interrupt configuration register 1 + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: CMPCR + description: Compensation cell control register + byte_offset: 32 + access: Read + fieldset: CMPCR fieldset/CMPCR: description: Compensation cell control register fields: - - name: CMP_PD - description: Compensation cell power-down - bit_offset: 0 - bit_size: 1 - - name: READY - description: Compensation cell ready flag - bit_offset: 8 - bit_size: 1 + - name: CMP_PD + description: Compensation cell power-down + bit_offset: 0 + bit_size: 1 + - name: READY + description: Compensation cell ready flag + bit_offset: 8 + bit_size: 1 fieldset/EXTICR: description: external interrupt configuration register 1 fields: - - name: EXTI - description: EXTI x configuration (x = 0 to 3) - bit_offset: 0 - bit_size: 4 - array: - len: 4 - stride: 4 + - name: EXTI + description: EXTI x configuration (x = 0 to 3) + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 fieldset/MEMRMP: description: memory remap register fields: - - name: MEM_MODE - description: Memory mapping selection - bit_offset: 0 - bit_size: 2 - enum: MEM_MODE + - name: MEM_MODE + description: Memory mapping selection + bit_offset: 0 + bit_size: 2 + enum: MEM_MODE fieldset/PMC: description: peripheral mode configuration register fields: - - name: MII_RMII_SEL - description: Ethernet PHY interface selection - bit_offset: 23 - bit_size: 1 + - name: MII_RMII_SEL + description: Ethernet PHY interface selection + bit_offset: 23 + bit_size: 1 enum/MEM_MODE: bit_size: 2 variants: - - name: MainFlash - description: Main Flash memory mapped at 0x0000_0000 - value: 0 - - name: SystemFlash - description: System Flash memory mapped at 0x0000_0000 - value: 1 - - name: FSMC - description: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000_0000 - value: 2 - - name: SRAM - description: Embedded SRAM mapped at 0x0000_0000 - value: 3 + - name: MainFlash + description: Main Flash memory mapped at 0x0000_0000 + value: 0 + - name: SystemFlash + description: System Flash memory mapped at 0x0000_0000 + value: 1 + - name: FSMC + description: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000_0000 + value: 2 + - name: SRAM + description: Embedded SRAM mapped at 0x0000_0000 + value: 3 diff --git a/data/registers/syscfg_f3.yaml b/data/registers/syscfg_f3.yaml index a683666..aab97fa 100644 --- a/data/registers/syscfg_f3.yaml +++ b/data/registers/syscfg_f3.yaml @@ -1,934 +1,933 @@ ---- block/SYSCFG: description: System configuration controller items: - - name: CFGR1 - description: configuration register 1 - byte_offset: 0 - fieldset: CFGR1 - - name: RCR - description: CCM SRAM protection register - byte_offset: 4 - fieldset: RCR - - name: EXTICR - description: external interrupt configuration register - array: - len: 4 - stride: 4 - byte_offset: 8 - fieldset: EXTICR - - name: CFGR2 - description: configuration register 2 - byte_offset: 24 - fieldset: CFGR2 - - name: CFGR4 - description: configuration register 4 - byte_offset: 72 - fieldset: CFGR4 - - name: CFGR3 - description: configuration register 3 - byte_offset: 80 - fieldset: CFGR3 + - name: CFGR1 + description: configuration register 1 + byte_offset: 0 + fieldset: CFGR1 + - name: RCR + description: CCM SRAM protection register + byte_offset: 4 + fieldset: RCR + - name: EXTICR + description: external interrupt configuration register + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: CFGR2 + description: configuration register 2 + byte_offset: 24 + fieldset: CFGR2 + - name: CFGR4 + description: configuration register 4 + byte_offset: 72 + fieldset: CFGR4 + - name: CFGR3 + description: configuration register 3 + byte_offset: 80 + fieldset: CFGR3 fieldset/CFGR1: description: configuration register 1 fields: - - name: MEM_MODE - description: Memory mapping selection bits - bit_offset: 0 - bit_size: 2 - enum: MEM_MODE - - name: USB_IT_RMP - description: USB interrupt remap - bit_offset: 5 - bit_size: 1 - enum: USB_IT_RMP - - name: TIM1_ITR3_RMP - description: Timer 1 ITR3 selection - bit_offset: 6 - bit_size: 1 - enum: TIM1_ITR3_RMP - - name: DAC1_TRIG_RMP - description: DAC trigger remap (when TSEL = 001) - bit_offset: 7 - bit_size: 1 - enum: DAC1_TRIG_RMP - - name: DAC_TRIG_RMP - description: DAC trigger remap (when TSEL = 001) - bit_offset: 7 - bit_size: 1 - enum: DAC_TRIG_RMP - - name: ADC2_DMA_RMP - description: ADC24 DMA remapping bit - bit_offset: 8 - bit_size: 1 - enum: ADC2_DMA_RMP - - name: TIM16_DMA_RMP - description: TIM16 DMA request remapping bit - bit_offset: 11 - bit_size: 1 - enum: TIM16_DMA_RMP - - name: TIM17_DMA_RMP - description: TIM17 DMA request remapping bit - bit_offset: 12 - bit_size: 1 - enum: TIM17_DMA_RMP - - name: TIM6_DAC1_CH1_DMA_RMP - description: TIM6 and DAC1 DMA request remapping bit - bit_offset: 13 - bit_size: 1 - enum: TIM6_DAC1_CH1_DMA_RMP - - name: TIM6_DAC1_DMA_RMP - description: TIM6 and DAC1 DMA request remapping bit - bit_offset: 13 - bit_size: 1 - enum: TIM6_DAC1_DMA_RMP - - name: TIM6_DAC1_OUT1_DMA_RMP - description: TIM6 and DAC1 DMA request remapping bit - bit_offset: 13 - bit_size: 1 - enum: TIM6_DAC1_OUT1_DMA_RMP - - name: TIM7_DAC1_CH2_DMA_RMP - description: TIM7 and DAC2 DMA request remapping bit - bit_offset: 14 - bit_size: 1 - enum: TIM7_DAC1_CH2_DMA_RMP - - name: TIM7_DAC1_OUT2_DMA_RMP - description: TIM7 and DAC2 DMA request remapping bit - bit_offset: 14 - bit_size: 1 - enum: TIM7_DAC1_OUT2_DMA_RMP - - name: DAC2_CH1_DMA_RMP - description: DAC2 channel1 DMA remap - bit_offset: 15 - bit_size: 1 - enum: DAC2_CH1_DMA_RMP - - name: TIM18_DAC2_OUT1_DMA_RMP - description: TIM18 and DAC2_OUT1 DMA request remapping bit - bit_offset: 15 - bit_size: 1 - enum: TIM18_DAC2_OUT1_DMA_RMP - - name: I2C_PB6_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. - bit_offset: 16 - bit_size: 1 - enum: I2C_PB6_FMP - - name: I2C_PB7_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. - bit_offset: 17 - bit_size: 1 - enum: I2C_PB7_FMP - - name: I2C_PB8_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. - bit_offset: 18 - bit_size: 1 - enum: I2C_PB8_FMP - - name: I2C_PB9_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. - bit_offset: 19 - bit_size: 1 - enum: I2C_PB9_FMP - - name: I2C1_FMP - description: I2C1 Fast Mode Plus - bit_offset: 20 - bit_size: 1 - enum: I2C1_FMP - - name: I2C2_FMP - description: I2C2 Fast Mode Plus - bit_offset: 21 - bit_size: 1 - enum: I2C2_FMP - - name: ENCODER_MODE - description: Encoder mode - bit_offset: 22 - bit_size: 2 - enum: ENCODER_MODE - - name: I2C3_FMP - description: I2C3 Fast Mode Plus - bit_offset: 24 - bit_size: 1 - enum: I2C3_FMP - - name: VBAT_MON - description: VBAT monitoring enable - bit_offset: 24 - bit_size: 1 - enum: VBAT_MON - - name: FPU_IE0 - description: Invalid operation interrupt enable - bit_offset: 26 - bit_size: 1 - enum: FPU_IE0 - - name: FPU_IE1 - description: Devide-by-zero interrupt enable - bit_offset: 27 - bit_size: 1 - enum: FPU_IE1 - - name: FPU_IE2 - description: Underflow interrupt enable - bit_offset: 28 - bit_size: 1 - enum: FPU_IE2 - - name: FPU_IE3 - description: Overflow interrupt enable - bit_offset: 29 - bit_size: 1 - enum: FPU_IE3 - - name: FPU_IE4 - description: Input denormal interrupt enable - bit_offset: 30 - bit_size: 1 - enum: FPU_IE4 - - name: FPU_IE5 - description: Inexact interrupt enable - bit_offset: 31 - bit_size: 1 - enum: FPU_IE5 + - name: MEM_MODE + description: Memory mapping selection bits + bit_offset: 0 + bit_size: 2 + enum: MEM_MODE + - name: USB_IT_RMP + description: USB interrupt remap + bit_offset: 5 + bit_size: 1 + enum: USB_IT_RMP + - name: TIM1_ITR3_RMP + description: Timer 1 ITR3 selection + bit_offset: 6 + bit_size: 1 + enum: TIM1_ITR3_RMP + - name: DAC1_TRIG_RMP + description: DAC trigger remap (when TSEL = 001) + bit_offset: 7 + bit_size: 1 + enum: DAC1_TRIG_RMP + - name: DAC_TRIG_RMP + description: DAC trigger remap (when TSEL = 001) + bit_offset: 7 + bit_size: 1 + enum: DAC_TRIG_RMP + - name: ADC2_DMA_RMP + description: ADC24 DMA remapping bit + bit_offset: 8 + bit_size: 1 + enum: ADC2_DMA_RMP + - name: TIM16_DMA_RMP + description: TIM16 DMA request remapping bit + bit_offset: 11 + bit_size: 1 + enum: TIM16_DMA_RMP + - name: TIM17_DMA_RMP + description: TIM17 DMA request remapping bit + bit_offset: 12 + bit_size: 1 + enum: TIM17_DMA_RMP + - name: TIM6_DAC1_CH1_DMA_RMP + description: TIM6 and DAC1 DMA request remapping bit + bit_offset: 13 + bit_size: 1 + enum: TIM6_DAC1_CH1_DMA_RMP + - name: TIM6_DAC1_DMA_RMP + description: TIM6 and DAC1 DMA request remapping bit + bit_offset: 13 + bit_size: 1 + enum: TIM6_DAC1_DMA_RMP + - name: TIM6_DAC1_OUT1_DMA_RMP + description: TIM6 and DAC1 DMA request remapping bit + bit_offset: 13 + bit_size: 1 + enum: TIM6_DAC1_OUT1_DMA_RMP + - name: TIM7_DAC1_CH2_DMA_RMP + description: TIM7 and DAC2 DMA request remapping bit + bit_offset: 14 + bit_size: 1 + enum: TIM7_DAC1_CH2_DMA_RMP + - name: TIM7_DAC1_OUT2_DMA_RMP + description: TIM7 and DAC2 DMA request remapping bit + bit_offset: 14 + bit_size: 1 + enum: TIM7_DAC1_OUT2_DMA_RMP + - name: DAC2_CH1_DMA_RMP + description: DAC2 channel1 DMA remap + bit_offset: 15 + bit_size: 1 + enum: DAC2_CH1_DMA_RMP + - name: TIM18_DAC2_OUT1_DMA_RMP + description: TIM18 and DAC2_OUT1 DMA request remapping bit + bit_offset: 15 + bit_size: 1 + enum: TIM18_DAC2_OUT1_DMA_RMP + - name: I2C_PB6_FMP + description: Fast Mode Plus (FM+) driving capability activation bits. + bit_offset: 16 + bit_size: 1 + enum: I2C_PB6_FMP + - name: I2C_PB7_FMP + description: Fast Mode Plus (FM+) driving capability activation bits. + bit_offset: 17 + bit_size: 1 + enum: I2C_PB7_FMP + - name: I2C_PB8_FMP + description: Fast Mode Plus (FM+) driving capability activation bits. + bit_offset: 18 + bit_size: 1 + enum: I2C_PB8_FMP + - name: I2C_PB9_FMP + description: Fast Mode Plus (FM+) driving capability activation bits. + bit_offset: 19 + bit_size: 1 + enum: I2C_PB9_FMP + - name: I2C1_FMP + description: I2C1 Fast Mode Plus + bit_offset: 20 + bit_size: 1 + enum: I2C1_FMP + - name: I2C2_FMP + description: I2C2 Fast Mode Plus + bit_offset: 21 + bit_size: 1 + enum: I2C2_FMP + - name: ENCODER_MODE + description: Encoder mode + bit_offset: 22 + bit_size: 2 + enum: ENCODER_MODE + - name: I2C3_FMP + description: I2C3 Fast Mode Plus + bit_offset: 24 + bit_size: 1 + enum: I2C3_FMP + - name: VBAT_MON + description: VBAT monitoring enable + bit_offset: 24 + bit_size: 1 + enum: VBAT_MON + - name: FPU_IE0 + description: Invalid operation interrupt enable + bit_offset: 26 + bit_size: 1 + enum: FPU_IE0 + - name: FPU_IE1 + description: Devide-by-zero interrupt enable + bit_offset: 27 + bit_size: 1 + enum: FPU_IE1 + - name: FPU_IE2 + description: Underflow interrupt enable + bit_offset: 28 + bit_size: 1 + enum: FPU_IE2 + - name: FPU_IE3 + description: Overflow interrupt enable + bit_offset: 29 + bit_size: 1 + enum: FPU_IE3 + - name: FPU_IE4 + description: Input denormal interrupt enable + bit_offset: 30 + bit_size: 1 + enum: FPU_IE4 + - name: FPU_IE5 + description: Inexact interrupt enable + bit_offset: 31 + bit_size: 1 + enum: FPU_IE5 fieldset/CFGR2: description: configuration register 2 fields: - - name: LOCKUP_LOCK - description: Cortex-M0 LOCKUP bit enable bit - bit_offset: 0 - bit_size: 1 - enum: LOCKUP_LOCK - - name: SRAM_PARITY_LOCK - description: SRAM parity lock bit - bit_offset: 1 - bit_size: 1 - enum: SRAM_PARITY_LOCK - - name: PVD_LOCK - description: PVD lock enable bit - bit_offset: 2 - bit_size: 1 - enum: PVD_LOCK - - name: BYP_ADDR_PAR - description: Bypass address bit 29 in parity calculation - bit_offset: 4 - bit_size: 1 - enum: BYP_ADDR_PAR - - name: SRAM_PEF - description: SRAM parity flag - bit_offset: 8 - bit_size: 1 + - name: LOCKUP_LOCK + description: Cortex-M0 LOCKUP bit enable bit + bit_offset: 0 + bit_size: 1 + enum: LOCKUP_LOCK + - name: SRAM_PARITY_LOCK + description: SRAM parity lock bit + bit_offset: 1 + bit_size: 1 + enum: SRAM_PARITY_LOCK + - name: PVD_LOCK + description: PVD lock enable bit + bit_offset: 2 + bit_size: 1 + enum: PVD_LOCK + - name: BYP_ADDR_PAR + description: Bypass address bit 29 in parity calculation + bit_offset: 4 + bit_size: 1 + enum: BYP_ADDR_PAR + - name: SRAM_PEF + description: SRAM parity flag + bit_offset: 8 + bit_size: 1 fieldset/CFGR3: description: configuration register 3 fields: - - name: SPI1_RX_DMA_RMP - description: SPI1_RX DMA remapping bit - bit_offset: 0 - bit_size: 2 - enum: SPI1_RX_DMA_RMP - - name: SPI1_TX_DMA_RMP - description: SPI1_TX DMA remapping bit - bit_offset: 2 - bit_size: 2 - enum: SPI1_TX_DMA_RMP - - name: I2C1_RX_DMA_RMP - description: I2C1_RX DMA remapping bit - bit_offset: 4 - bit_size: 2 - enum: I2C1_RX_DMA_RMP - - name: I2C1_TX_DMA_RMP - description: I2C1_TX DMA remapping bit - bit_offset: 6 - bit_size: 2 - enum: I2C1_TX_DMA_RMP - - name: ADC2_DMA_RMP - description: ADC2 DMA remapping bit - bit_offset: 8 - bit_size: 2 - enum: ADC2_DMA_RMP - - name: DAC1_TRIG3_RMP - description: DAC1_CH1 / DAC1_CH2 Trigger remap - bit_offset: 16 - bit_size: 1 - enum: DAC1_TRIG3_RMP - - name: DAC1_TRIG5_RMP - description: DAC1_CH1 / DAC1_CH2 Trigger remap - bit_offset: 17 - bit_size: 1 - enum: DAC1_TRIG5_RMP + - name: SPI1_RX_DMA_RMP + description: SPI1_RX DMA remapping bit + bit_offset: 0 + bit_size: 2 + enum: SPI1_RX_DMA_RMP + - name: SPI1_TX_DMA_RMP + description: SPI1_TX DMA remapping bit + bit_offset: 2 + bit_size: 2 + enum: SPI1_TX_DMA_RMP + - name: I2C1_RX_DMA_RMP + description: I2C1_RX DMA remapping bit + bit_offset: 4 + bit_size: 2 + enum: I2C1_RX_DMA_RMP + - name: I2C1_TX_DMA_RMP + description: I2C1_TX DMA remapping bit + bit_offset: 6 + bit_size: 2 + enum: I2C1_TX_DMA_RMP + - name: ADC2_DMA_RMP + description: ADC2 DMA remapping bit + bit_offset: 8 + bit_size: 2 + enum: ADC2_DMA_RMP + - name: DAC1_TRIG3_RMP + description: DAC1_CH1 / DAC1_CH2 Trigger remap + bit_offset: 16 + bit_size: 1 + enum: DAC1_TRIG3_RMP + - name: DAC1_TRIG5_RMP + description: DAC1_CH1 / DAC1_CH2 Trigger remap + bit_offset: 17 + bit_size: 1 + enum: DAC1_TRIG5_RMP fieldset/CFGR4: description: configuration register 4 fields: - - name: ADC12_EXT2_RMP - description: Controls the Input trigger of ADC12 regular channel EXT2 - bit_offset: 0 - bit_size: 1 - enum: ADC12_EXT2_RMP - - name: ADC12_EXT3_RMP - description: Controls the Input trigger of ADC12 regular channel EXT3 - bit_offset: 1 - bit_size: 1 - enum: ADC12_EXT3_RMP - - name: ADC12_EXT5_RMP - description: Controls the Input trigger of ADC12 regular channel EXT5 - bit_offset: 2 - bit_size: 1 - enum: ADC12_EXT5_RMP - - name: ADC12_EXT13_RMP - description: Controls the Input trigger of ADC12 regular channel EXT13 - bit_offset: 3 - bit_size: 1 - enum: ADC12_EXT13_RMP - - name: ADC12_EXT15_RMP - description: Controls the Input trigger of ADC12 regular channel EXT15 - bit_offset: 4 - bit_size: 1 - enum: ADC12_EXT15_RMP - - name: ADC12_JEXT3_RMP - description: Controls the Input trigger of ADC12 injected channel JEXT3 - bit_offset: 5 - bit_size: 1 - enum: ADC12_JEXT3_RMP - - name: ADC12_JEXT6_RMP - description: Controls the Input trigger of ADC12 injected channel JEXT6 - bit_offset: 6 - bit_size: 1 - enum: ADC12_JEXT6_RMP - - name: ADC12_JEXT13_RMP - description: Controls the Input trigger of ADC12 injected channel JEXT13 - bit_offset: 7 - bit_size: 1 - enum: ADC12_JEXT13_RMP - - name: ADC34_EXT5_RMP - description: Controls the Input trigger of ADC34 regular channel EXT5 - bit_offset: 8 - bit_size: 1 - enum: ADC34_EXT5_RMP - - name: ADC34_EXT6_RMP - description: Controls the Input trigger of ADC34 regular channel EXT6 - bit_offset: 9 - bit_size: 1 - enum: ADC34_EXT6_RMP - - name: ADC34_EXT15_RMP - description: Controls the Input trigger of ADC34 regular channel EXT15 - bit_offset: 10 - bit_size: 1 - enum: ADC34_EXT15_RMP - - name: ADC34_JEXT5_RMP - description: Controls the Input trigger of ADC34 injected channel JEXT5 - bit_offset: 11 - bit_size: 1 - enum: ADC34_JEXT5_RMP - - name: ADC34_JEXT11_RMP - description: Controls the Input trigger of ADC34 injected channel JEXT11 - bit_offset: 12 - bit_size: 1 - enum: ADC34_JEXT11_RMP - - name: ADC34_JEXT14_RMP - description: Controls the Input trigger of ADC34 injected channel JEXT14 - bit_offset: 13 - bit_size: 1 - enum: ADC34_JEXT14_RMP + - name: ADC12_EXT2_RMP + description: Controls the Input trigger of ADC12 regular channel EXT2 + bit_offset: 0 + bit_size: 1 + enum: ADC12_EXT2_RMP + - name: ADC12_EXT3_RMP + description: Controls the Input trigger of ADC12 regular channel EXT3 + bit_offset: 1 + bit_size: 1 + enum: ADC12_EXT3_RMP + - name: ADC12_EXT5_RMP + description: Controls the Input trigger of ADC12 regular channel EXT5 + bit_offset: 2 + bit_size: 1 + enum: ADC12_EXT5_RMP + - name: ADC12_EXT13_RMP + description: Controls the Input trigger of ADC12 regular channel EXT13 + bit_offset: 3 + bit_size: 1 + enum: ADC12_EXT13_RMP + - name: ADC12_EXT15_RMP + description: Controls the Input trigger of ADC12 regular channel EXT15 + bit_offset: 4 + bit_size: 1 + enum: ADC12_EXT15_RMP + - name: ADC12_JEXT3_RMP + description: Controls the Input trigger of ADC12 injected channel JEXT3 + bit_offset: 5 + bit_size: 1 + enum: ADC12_JEXT3_RMP + - name: ADC12_JEXT6_RMP + description: Controls the Input trigger of ADC12 injected channel JEXT6 + bit_offset: 6 + bit_size: 1 + enum: ADC12_JEXT6_RMP + - name: ADC12_JEXT13_RMP + description: Controls the Input trigger of ADC12 injected channel JEXT13 + bit_offset: 7 + bit_size: 1 + enum: ADC12_JEXT13_RMP + - name: ADC34_EXT5_RMP + description: Controls the Input trigger of ADC34 regular channel EXT5 + bit_offset: 8 + bit_size: 1 + enum: ADC34_EXT5_RMP + - name: ADC34_EXT6_RMP + description: Controls the Input trigger of ADC34 regular channel EXT6 + bit_offset: 9 + bit_size: 1 + enum: ADC34_EXT6_RMP + - name: ADC34_EXT15_RMP + description: Controls the Input trigger of ADC34 regular channel EXT15 + bit_offset: 10 + bit_size: 1 + enum: ADC34_EXT15_RMP + - name: ADC34_JEXT5_RMP + description: Controls the Input trigger of ADC34 injected channel JEXT5 + bit_offset: 11 + bit_size: 1 + enum: ADC34_JEXT5_RMP + - name: ADC34_JEXT11_RMP + description: Controls the Input trigger of ADC34 injected channel JEXT11 + bit_offset: 12 + bit_size: 1 + enum: ADC34_JEXT11_RMP + - name: ADC34_JEXT14_RMP + description: Controls the Input trigger of ADC34 injected channel JEXT14 + bit_offset: 13 + bit_size: 1 + enum: ADC34_JEXT14_RMP fieldset/EXTICR: description: external interrupt configuration register fields: - - name: EXTI - description: EXTI x configuration - bit_offset: 0 - bit_size: 4 - array: - len: 4 - stride: 4 + - name: EXTI + description: EXTI x configuration + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 fieldset/RCR: description: CCM SRAM protection register fields: - - name: PAGE0_WP - description: CCM SRAM page write protection bit - bit_offset: 0 - bit_size: 1 - enum: PAGE0_WP - - name: PAGE1_WP - description: CCM SRAM page write protection bit - bit_offset: 1 - bit_size: 1 - enum: PAGE0_WP - - name: PAGE2_WP - description: CCM SRAM page write protection bit - bit_offset: 2 - bit_size: 1 - enum: PAGE0_WP - - name: PAGE3_WP - description: CCM SRAM page write protection bit - bit_offset: 3 - bit_size: 1 - enum: PAGE0_WP - - name: PAGE4_WP - description: CCM SRAM page write protection bit - bit_offset: 4 - bit_size: 1 - enum: PAGE0_WP - - name: PAGE5_WP - description: CCM SRAM page write protection bit - bit_offset: 5 - bit_size: 1 - enum: PAGE0_WP - - name: PAGE6_WP - description: CCM SRAM page write protection bit - bit_offset: 6 - bit_size: 1 - enum: PAGE0_WP - - name: PAGE7_WP - description: CCM SRAM page write protection bit - bit_offset: 7 - bit_size: 1 - enum: PAGE0_WP - - name: PAGE8_WP - description: CCM SRAM page write protection bit - bit_offset: 8 - bit_size: 1 - enum: PAGE0_WP - - name: PAGE9_WP - description: CCM SRAM page write protection bit - bit_offset: 9 - bit_size: 1 - enum: PAGE0_WP - - name: PAGE10_WP - description: CCM SRAM page write protection bit - bit_offset: 10 - bit_size: 1 - enum: PAGE0_WP - - name: PAGE11_WP - description: CCM SRAM page write protection bit - bit_offset: 11 - bit_size: 1 - enum: PAGE0_WP - - name: PAGE12_WP - description: CCM SRAM page write protection bit - bit_offset: 12 - bit_size: 1 - enum: PAGE0_WP - - name: PAGE13_WP - description: CCM SRAM page write protection bit - bit_offset: 13 - bit_size: 1 - enum: PAGE0_WP - - name: PAGE14_WP - description: CCM SRAM page write protection bit - bit_offset: 14 - bit_size: 1 - enum: PAGE0_WP - - name: PAGE15_WP - description: CCM SRAM page write protection bit - bit_offset: 15 - bit_size: 1 - enum: PAGE0_WP + - name: PAGE0_WP + description: CCM SRAM page write protection bit + bit_offset: 0 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE1_WP + description: CCM SRAM page write protection bit + bit_offset: 1 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE2_WP + description: CCM SRAM page write protection bit + bit_offset: 2 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE3_WP + description: CCM SRAM page write protection bit + bit_offset: 3 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE4_WP + description: CCM SRAM page write protection bit + bit_offset: 4 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE5_WP + description: CCM SRAM page write protection bit + bit_offset: 5 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE6_WP + description: CCM SRAM page write protection bit + bit_offset: 6 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE7_WP + description: CCM SRAM page write protection bit + bit_offset: 7 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE8_WP + description: CCM SRAM page write protection bit + bit_offset: 8 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE9_WP + description: CCM SRAM page write protection bit + bit_offset: 9 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE10_WP + description: CCM SRAM page write protection bit + bit_offset: 10 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE11_WP + description: CCM SRAM page write protection bit + bit_offset: 11 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE12_WP + description: CCM SRAM page write protection bit + bit_offset: 12 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE13_WP + description: CCM SRAM page write protection bit + bit_offset: 13 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE14_WP + description: CCM SRAM page write protection bit + bit_offset: 14 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE15_WP + description: CCM SRAM page write protection bit + bit_offset: 15 + bit_size: 1 + enum: PAGE0_WP enum/ADC12_EXT13_RMP: bit_size: 1 variants: - - name: Tim6 - description: Trigger source is TIM6_TRGO - value: 0 - - name: Tim20 - description: Trigger source is TIM20_CC2 - value: 1 + - name: Tim6 + description: Trigger source is TIM6_TRGO + value: 0 + - name: Tim20 + description: Trigger source is TIM20_CC2 + value: 1 enum/ADC12_EXT15_RMP: bit_size: 1 variants: - - name: Tim3 - description: Trigger source is TIM3_CC4 - value: 0 - - name: Tim20 - description: Trigger source is TIM20_CC3 - value: 1 + - name: Tim3 + description: Trigger source is TIM3_CC4 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_CC3 + value: 1 enum/ADC12_EXT2_RMP: bit_size: 1 variants: - - name: Tim1 - description: Trigger source is TIM3_CC3 - value: 0 - - name: Tim20 - description: rigger source is TIM20_TRGO - value: 1 + - name: Tim1 + description: Trigger source is TIM3_CC3 + value: 0 + - name: Tim20 + description: rigger source is TIM20_TRGO + value: 1 enum/ADC12_EXT3_RMP: bit_size: 1 variants: - - name: Tim2 - description: Trigger source is TIM2_CC2 - value: 0 - - name: Tim20 - description: rigger source is TIM20_TRGO2 - value: 1 + - name: Tim2 + description: Trigger source is TIM2_CC2 + value: 0 + - name: Tim20 + description: rigger source is TIM20_TRGO2 + value: 1 enum/ADC12_EXT5_RMP: bit_size: 1 variants: - - name: Tim4 - description: Trigger source is TIM4_CC4 - value: 0 - - name: Tim20 - description: Trigger source is TIM20_CC1 - value: 1 + - name: Tim4 + description: Trigger source is TIM4_CC4 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_CC1 + value: 1 enum/ADC12_JEXT13_RMP: bit_size: 1 variants: - - name: Tim3 - description: Trigger source is TIM3_CC1 - value: 0 - - name: Tim20 - description: Trigger source is TIM20_CC4 - value: 1 + - name: Tim3 + description: Trigger source is TIM3_CC1 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_CC4 + value: 1 enum/ADC12_JEXT3_RMP: bit_size: 1 variants: - - name: Tim2 - description: Trigger source is TIM2_CC1 - value: 0 - - name: Tim20 - description: Trigger source is TIM20_TRGO - value: 1 + - name: Tim2 + description: Trigger source is TIM2_CC1 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_TRGO + value: 1 enum/ADC12_JEXT6_RMP: bit_size: 1 variants: - - name: Exti15 - description: Trigger source is EXTI line 15 - value: 0 - - name: Tim20 - description: Trigger source is TIM20_TRGO2 - value: 1 + - name: Exti15 + description: Trigger source is EXTI line 15 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_TRGO2 + value: 1 enum/ADC2_DMA_RMP: bit_size: 1 variants: - - name: MapDma2 - description: ADC2 mapped on DMA2 - value: 0 - - name: MapDma1Ch2 - description: ADC2 mapped on DMA1 channel 2 - value: 2 - - name: MapDma1Ch4 - description: ADC2 mapped on DMA1 channel 4 - value: 3 + - name: MapDma2 + description: ADC2 mapped on DMA2 + value: 0 + - name: MapDma1Ch2 + description: ADC2 mapped on DMA1 channel 2 + value: 2 + - name: MapDma1Ch4 + description: ADC2 mapped on DMA1 channel 4 + value: 3 enum/ADC34_EXT15_RMP: bit_size: 1 variants: - - name: Tim2 - description: Trigger source is TIM2_CC1 - value: 0 - - name: Tim20 - description: Trigger source is TIM20_CC1 - value: 1 + - name: Tim2 + description: Trigger source is TIM2_CC1 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_CC1 + value: 1 enum/ADC34_EXT5_RMP: bit_size: 1 variants: - - name: Exti2 - description: Trigger source is EXTI line 2 when reset at 0 - value: 0 - - name: Tim20 - description: Trigger source is TIM20_TRGO - value: 1 + - name: Exti2 + description: Trigger source is EXTI line 2 when reset at 0 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_TRGO + value: 1 enum/ADC34_EXT6_RMP: bit_size: 1 variants: - - name: Tim4 - description: Trigger source is TIM4_CC1 - value: 0 - - name: Tim20 - description: Trigger source is TIM20_TRGO2 - value: 1 + - name: Tim4 + description: Trigger source is TIM4_CC1 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_TRGO2 + value: 1 enum/ADC34_JEXT11_RMP: bit_size: 1 variants: - - name: Tim1 - description: Trigger source is TIM1_CC3 - value: 0 - - name: Tim20 - description: Trigger source is TIM20_TRGO2 - value: 1 + - name: Tim1 + description: Trigger source is TIM1_CC3 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_TRGO2 + value: 1 enum/ADC34_JEXT14_RMP: bit_size: 1 variants: - - name: Tim7 - description: Trigger source is TIM7_TRGO - value: 0 - - name: Tim20 - description: Trigger source is TIM20_CC2 - value: 1 + - name: Tim7 + description: Trigger source is TIM7_TRGO + value: 0 + - name: Tim20 + description: Trigger source is TIM20_CC2 + value: 1 enum/ADC34_JEXT5_RMP: bit_size: 1 variants: - - name: Tim4 - description: Trigger source is TIM4_CC3 - value: 0 - - name: Tim20 - description: Trigger source is TIM20_TRGO - value: 1 + - name: Tim4 + description: Trigger source is TIM4_CC3 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_TRGO + value: 1 enum/BYP_ADDR_PAR: bit_size: 1 variants: - - name: NoBypass - description: The ramload operation is performed taking into consideration bit 29 of the address when the parity is calculated - value: 0 - - name: Bypass - description: The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated - value: 1 + - name: NoBypass + description: The ramload operation is performed taking into consideration bit 29 of the address when the parity is calculated + value: 0 + - name: Bypass + description: The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated + value: 1 enum/DAC1_TRIG3_RMP: bit_size: 1 variants: - - name: Tim15 - description: DAC trigger is TIM15_TRGO - value: 0 - - name: HrTim1 - description: DAC trigger is HRTIM1_DAC1_TRIG1 - value: 1 + - name: Tim15 + description: DAC trigger is TIM15_TRGO + value: 0 + - name: HrTim1 + description: DAC trigger is HRTIM1_DAC1_TRIG1 + value: 1 enum/DAC1_TRIG5_RMP: bit_size: 1 variants: - - name: NotRemapped - description: Not remapped - value: 0 - - name: Remapped - description: DAC trigger is HRTIM1_DAC1_TRIG2 - value: 1 + - name: NotRemapped + description: Not remapped + value: 0 + - name: Remapped + description: DAC trigger is HRTIM1_DAC1_TRIG2 + value: 1 enum/DAC1_TRIG_RMP: bit_size: 1 variants: - - name: NotRemapped - description: DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices - value: 0 - - name: Remapped - description: DAC trigger is TIM3_TRGO - value: 1 + - name: NotRemapped + description: DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices + value: 0 + - name: Remapped + description: DAC trigger is TIM3_TRGO + value: 1 enum/DAC2_CH1_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: Not remapped - value: 0 - - name: Remapped - description: DAC2_CH1 DMA requests mapped on DMA1 channel 5 - value: 1 + - name: NotRemapped + description: Not remapped + value: 0 + - name: Remapped + description: DAC2_CH1 DMA requests mapped on DMA1 channel 5 + value: 1 enum/DAC_TRIG_RMP: bit_size: 1 variants: - - name: NotRemapped - description: Not remapped - value: 0 - - name: Remapped - description: DAC trigger is TIM3_TRGO - value: 1 + - name: NotRemapped + description: Not remapped + value: 0 + - name: Remapped + description: DAC trigger is TIM3_TRGO + value: 1 enum/ENCODER_MODE: bit_size: 2 variants: - - name: NoRedirection - description: No redirection - value: 0 - - name: MapTim2Tim15 - description: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively - value: 1 - - name: MapTim3Tim15 - description: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively - value: 2 + - name: NoRedirection + description: No redirection + value: 0 + - name: MapTim2Tim15 + description: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively + value: 1 + - name: MapTim3Tim15 + description: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively + value: 2 enum/FPU_IE0: bit_size: 1 variants: - - name: Disabled - description: Invalid operation interrupt disable - value: 0 - - name: Enabled - description: Invalid operation interrupt enable - value: 1 + - name: Disabled + description: Invalid operation interrupt disable + value: 0 + - name: Enabled + description: Invalid operation interrupt enable + value: 1 enum/FPU_IE1: bit_size: 1 variants: - - name: Disabled - description: Devide-by-zero interrupt disable - value: 0 - - name: Enabled - description: Devide-by-zero interrupt enable - value: 1 + - name: Disabled + description: Devide-by-zero interrupt disable + value: 0 + - name: Enabled + description: Devide-by-zero interrupt enable + value: 1 enum/FPU_IE2: bit_size: 1 variants: - - name: Disabled - description: Underflow interrupt disable - value: 0 - - name: Enabled - description: Underflow interrupt enable - value: 1 + - name: Disabled + description: Underflow interrupt disable + value: 0 + - name: Enabled + description: Underflow interrupt enable + value: 1 enum/FPU_IE3: bit_size: 1 variants: - - name: Disabled - description: Overflow interrupt disable - value: 0 - - name: Enabled - description: Overflow interrupt enable - value: 1 + - name: Disabled + description: Overflow interrupt disable + value: 0 + - name: Enabled + description: Overflow interrupt enable + value: 1 enum/FPU_IE4: bit_size: 1 variants: - - name: Disabled - description: Input denormal interrupt disable - value: 0 - - name: Enabled - description: Input denormal interrupt enable - value: 1 + - name: Disabled + description: Input denormal interrupt disable + value: 0 + - name: Enabled + description: Input denormal interrupt enable + value: 1 enum/FPU_IE5: bit_size: 1 variants: - - name: Disabled - description: Inexact interrupt disable - value: 0 - - name: Enabled - description: Inexact interrupt enable - value: 1 + - name: Disabled + description: Inexact interrupt disable + value: 0 + - name: Enabled + description: Inexact interrupt enable + value: 1 enum/I2C1_FMP: bit_size: 1 variants: - - name: Standard - description: FM+ mode is controlled by I2C_Pxx_FMP bits only - value: 0 - - name: FMP - description: FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits - value: 1 + - name: Standard + description: FM+ mode is controlled by I2C_Pxx_FMP bits only + value: 0 + - name: FMP + description: FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits + value: 1 enum/I2C1_RX_DMA_RMP: bit_size: 2 variants: - - name: MapDma1Ch7 - description: I2C1_RX mapped on DMA1 CH7 - value: 0 - - name: MapDma1Ch3 - description: I2C1_RX mapped on DMA1 CH3 - value: 1 - - name: MapDma1Ch5 - description: I2C1_RX mapped on DMA1 CH5 - value: 2 + - name: MapDma1Ch7 + description: I2C1_RX mapped on DMA1 CH7 + value: 0 + - name: MapDma1Ch3 + description: I2C1_RX mapped on DMA1 CH3 + value: 1 + - name: MapDma1Ch5 + description: I2C1_RX mapped on DMA1 CH5 + value: 2 enum/I2C1_TX_DMA_RMP: bit_size: 2 variants: - - name: MapDma1Ch6 - description: I2C1_TX mapped on DMA1 CH6 - value: 0 - - name: MapDma1Ch2 - description: I2C1_TX mapped on DMA1 CH2 - value: 1 - - name: MapDma1Ch4 - description: I2C1_TX mapped on DMA1 CH4 - value: 2 + - name: MapDma1Ch6 + description: I2C1_TX mapped on DMA1 CH6 + value: 0 + - name: MapDma1Ch2 + description: I2C1_TX mapped on DMA1 CH2 + value: 1 + - name: MapDma1Ch4 + description: I2C1_TX mapped on DMA1 CH4 + value: 2 enum/I2C2_FMP: bit_size: 1 variants: - - name: Standard - description: FM+ mode is controlled by I2C_Pxx_FMP bits only - value: 0 - - name: FMP - description: FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits - value: 1 + - name: Standard + description: FM+ mode is controlled by I2C_Pxx_FMP bits only + value: 0 + - name: FMP + description: FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits + value: 1 enum/I2C3_FMP: bit_size: 1 variants: - - name: Standard - description: FM+ mode is controlled by I2C_Pxx_FMP bits only - value: 0 - - name: FMP - description: FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits - value: 1 + - name: Standard + description: FM+ mode is controlled by I2C_Pxx_FMP bits only + value: 0 + - name: FMP + description: FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits + value: 1 enum/I2C_PB6_FMP: bit_size: 1 variants: - - name: Standard - description: PB6 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB6 and the Speed control is bypassed - value: 1 + - name: Standard + description: PB6 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB6 and the Speed control is bypassed + value: 1 enum/I2C_PB7_FMP: bit_size: 1 variants: - - name: Standard - description: PB7 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB7 and the Speed control is bypassed - value: 1 + - name: Standard + description: PB7 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB7 and the Speed control is bypassed + value: 1 enum/I2C_PB8_FMP: bit_size: 1 variants: - - name: Standard - description: PB8 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB8 and the Speed control is bypassed - value: 1 + - name: Standard + description: PB8 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB8 and the Speed control is bypassed + value: 1 enum/I2C_PB9_FMP: bit_size: 1 variants: - - name: Standard - description: PB9 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB9 and the Speed control is bypassed - value: 1 + - name: Standard + description: PB9 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB9 and the Speed control is bypassed + value: 1 enum/LOCKUP_LOCK: bit_size: 1 variants: - - name: Disconnected - description: Cortex-M4 LOCKUP output disconnected from TIM1/15/16/17 Break inputs and HRTIM1 SYSFLT. - value: 0 - - name: Connected - description: Cortex-M4 LOCKUP output connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs - value: 1 + - name: Disconnected + description: Cortex-M4 LOCKUP output disconnected from TIM1/15/16/17 Break inputs and HRTIM1 SYSFLT. + value: 0 + - name: Connected + description: Cortex-M4 LOCKUP output connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs + value: 1 enum/MEM_MODE: bit_size: 2 variants: - - name: MainFlash - description: Main Flash memory mapped at 0x0000_0000 - value: 0 - - name: SystemFlash - description: System Flash memory mapped at 0x0000_0000 - value: 1 - - name: MainFlash2 - description: Main Flash memory mapped at 0x0000_0000 - value: 2 - - name: SRAM - description: Embedded SRAM mapped at 0x0000_0000 - value: 3 + - name: MainFlash + description: Main Flash memory mapped at 0x0000_0000 + value: 0 + - name: SystemFlash + description: System Flash memory mapped at 0x0000_0000 + value: 1 + - name: MainFlash2 + description: Main Flash memory mapped at 0x0000_0000 + value: 2 + - name: SRAM + description: Embedded SRAM mapped at 0x0000_0000 + value: 3 enum/PAGE0_WP: bit_size: 1 variants: - - name: Disabled - description: Write protection of pagex is disabled - value: 0 - - name: Enabled - description: Write protection of pagex is enabled - value: 1 + - name: Disabled + description: Write protection of pagex is disabled + value: 0 + - name: Enabled + description: Write protection of pagex is enabled + value: 1 enum/PVD_LOCK: bit_size: 1 variants: - - name: Disconnected - description: PVD interrupt disconnected from TIM15/16/17 Break input - value: 0 - - name: Connected - description: PVD interrupt connected to TIM15/16/17 Break input - value: 1 + - name: Disconnected + description: PVD interrupt disconnected from TIM15/16/17 Break input + value: 0 + - name: Connected + description: PVD interrupt connected to TIM15/16/17 Break input + value: 1 enum/SPI1_RX_DMA_RMP: bit_size: 2 variants: - - name: MapDma1Ch3 - description: SPI1_RX mapped on DMA1 CH2 - value: 0 - - name: MapDma1Ch5 - description: SPI1_RX mapped on DMA1 CH4 - value: 1 - - name: MapDma1Ch7 - description: SPI1_RX mapped on DMA1 CH6 - value: 2 + - name: MapDma1Ch3 + description: SPI1_RX mapped on DMA1 CH2 + value: 0 + - name: MapDma1Ch5 + description: SPI1_RX mapped on DMA1 CH4 + value: 1 + - name: MapDma1Ch7 + description: SPI1_RX mapped on DMA1 CH6 + value: 2 enum/SPI1_TX_DMA_RMP: bit_size: 2 variants: - - name: MapDma1Ch3 - description: SPI1_TX mapped on DMA1 CH3 - value: 0 - - name: MapDma1Ch5 - description: SPI1_TX mapped on DMA1 CH5 - value: 1 - - name: MapDma1Ch7 - description: SPI1_TX mapped on DMA1 CH7 - value: 2 + - name: MapDma1Ch3 + description: SPI1_TX mapped on DMA1 CH3 + value: 0 + - name: MapDma1Ch5 + description: SPI1_TX mapped on DMA1 CH5 + value: 1 + - name: MapDma1Ch7 + description: SPI1_TX mapped on DMA1 CH7 + value: 2 enum/SRAM_PARITY_LOCK: bit_size: 1 variants: - - name: Disconnected - description: SRAM parity error signal disconnected from TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs - value: 0 - - name: Connected - description: SRAM parity error signal connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs - value: 1 + - name: Disconnected + description: SRAM parity error signal disconnected from TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs + value: 0 + - name: Connected + description: SRAM parity error signal connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs + value: 1 enum/TIM16_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 - value: 0 - - name: Remapped - description: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 - value: 1 + - name: NotRemapped + description: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 + value: 0 + - name: Remapped + description: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 + value: 1 enum/TIM17_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 - value: 0 - - name: Remapped - description: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 - value: 1 + - name: NotRemapped + description: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 + value: 0 + - name: Remapped + description: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 + value: 1 enum/TIM18_DAC2_OUT1_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5 - value: 0 - - name: Remapped - description: TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5 - value: 1 + - name: NotRemapped + description: TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5 + value: 0 + - name: Remapped + description: TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5 + value: 1 enum/TIM1_ITR3_RMP: bit_size: 1 variants: - - name: NotRemapped - description: Not remapped - value: 0 - - name: Remapped - description: TIM1_ITR3 = TIM17_OC - value: 1 + - name: NotRemapped + description: Not remapped + value: 0 + - name: Remapped + description: TIM1_ITR3 = TIM17_OC + value: 1 enum/TIM6_DAC1_CH1_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 - value: 0 - - name: Remapped - description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 - value: 1 + - name: NotRemapped + description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 + value: 0 + - name: Remapped + description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 + value: 1 enum/TIM6_DAC1_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 - value: 0 - - name: Remapped - description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 - value: 1 + - name: NotRemapped + description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 + value: 0 + - name: Remapped + description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 + value: 1 enum/TIM6_DAC1_OUT1_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3 - value: 0 - - name: Remapped - description: TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3 - value: 1 + - name: NotRemapped + description: TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3 + value: 0 + - name: Remapped + description: TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3 + value: 1 enum/TIM7_DAC1_CH2_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: Not remapped - value: 0 - - name: Remapped - description: TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4 - value: 1 + - name: NotRemapped + description: Not remapped + value: 0 + - name: Remapped + description: TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4 + value: 1 enum/TIM7_DAC1_OUT2_DMA_RMP: bit_size: 1 variants: - - name: NotRemapped - description: TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4 - value: 0 - - name: Remapped - description: TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4 - value: 1 + - name: NotRemapped + description: TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4 + value: 0 + - name: Remapped + description: TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4 + value: 1 enum/USB_IT_RMP: bit_size: 1 variants: - - name: NotRemapped - description: "USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively" - value: 0 - - name: Remapped - description: "USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively" - value: 1 + - name: NotRemapped + description: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively + value: 0 + - name: Remapped + description: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively + value: 1 enum/VBAT_MON: bit_size: 1 variants: - - name: Disable - description: Disable the power switch to not deliver VBAT voltage on ADC channel 18 input - value: 0 - - name: Enable - description: Enable the power switch to deliver VBAT voltage on ADC channel 18 input - value: 1 + - name: Disable + description: Disable the power switch to not deliver VBAT voltage on ADC channel 18 input + value: 0 + - name: Enable + description: Enable the power switch to deliver VBAT voltage on ADC channel 18 input + value: 1 diff --git a/data/registers/syscfg_f4.yaml b/data/registers/syscfg_f4.yaml index 41f1661..f08fe7a 100644 --- a/data/registers/syscfg_f4.yaml +++ b/data/registers/syscfg_f4.yaml @@ -1,79 +1,78 @@ ---- block/SYSCFG: description: System configuration controller items: - - name: MEMRM - description: memory remap register - byte_offset: 0 - fieldset: MEMRM - - name: PMC - description: peripheral mode configuration register - byte_offset: 4 - fieldset: PMC - - name: EXTICR - description: external interrupt configuration register - array: - len: 4 - stride: 4 - byte_offset: 8 - fieldset: EXTICR - - name: CMPCR - description: Compensation cell control register - byte_offset: 32 - access: Read - fieldset: CMPCR + - name: MEMRM + description: memory remap register + byte_offset: 0 + fieldset: MEMRM + - name: PMC + description: peripheral mode configuration register + byte_offset: 4 + fieldset: PMC + - name: EXTICR + description: external interrupt configuration register + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: CMPCR + description: Compensation cell control register + byte_offset: 32 + access: Read + fieldset: CMPCR fieldset/CMPCR: description: Compensation cell control register fields: - - name: CMP_PD - description: Compensation cell power-down - bit_offset: 0 - bit_size: 1 - - name: READY - description: READY - bit_offset: 8 - bit_size: 1 + - name: CMP_PD + description: Compensation cell power-down + bit_offset: 0 + bit_size: 1 + - name: READY + description: READY + bit_offset: 8 + bit_size: 1 fieldset/EXTICR: description: external interrupt configuration register fields: - - name: EXTI - description: EXTI x configuration - bit_offset: 0 - bit_size: 4 - array: - len: 4 - stride: 4 + - name: EXTI + description: EXTI x configuration + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 fieldset/MEMRM: description: memory remap register fields: - - name: MEM_MODE - description: Memory mapping selection - bit_offset: 0 - bit_size: 3 - - name: FB_MODE - description: Flash bank mode selection - bit_offset: 8 - bit_size: 1 - - name: SWP_FMC - description: FMC memory mapping swap - bit_offset: 10 - bit_size: 2 + - name: MEM_MODE + description: Memory mapping selection + bit_offset: 0 + bit_size: 3 + - name: FB_MODE + description: Flash bank mode selection + bit_offset: 8 + bit_size: 1 + - name: SWP_FMC + description: FMC memory mapping swap + bit_offset: 10 + bit_size: 2 fieldset/PMC: description: peripheral mode configuration register fields: - - name: ADC1DC2 - description: ADC1DC2 - bit_offset: 16 - bit_size: 1 - - name: ADC2DC2 - description: ADC2DC2 - bit_offset: 17 - bit_size: 1 - - name: ADC3DC2 - description: ADC3DC2 - bit_offset: 18 - bit_size: 1 - - name: MII_RMII_SEL - description: Ethernet PHY interface selection - bit_offset: 23 - bit_size: 1 + - name: ADC1DC2 + description: ADC1DC2 + bit_offset: 16 + bit_size: 1 + - name: ADC2DC2 + description: ADC2DC2 + bit_offset: 17 + bit_size: 1 + - name: ADC3DC2 + description: ADC3DC2 + bit_offset: 18 + bit_size: 1 + - name: MII_RMII_SEL + description: Ethernet PHY interface selection + bit_offset: 23 + bit_size: 1 diff --git a/data/registers/syscfg_f7.yaml b/data/registers/syscfg_f7.yaml index f5a2242..a39ccfe 100644 --- a/data/registers/syscfg_f7.yaml +++ b/data/registers/syscfg_f7.yaml @@ -1,111 +1,110 @@ ---- block/SYSCFG: description: System configuration controller items: - - name: MEMRMP - description: memory remap register - byte_offset: 0 - fieldset: MEMRMP - - name: PMC - description: peripheral mode configuration register - byte_offset: 4 - fieldset: PMC - - name: EXTICR - description: external interrupt configuration register 1 - array: - len: 4 - stride: 4 - byte_offset: 8 - fieldset: EXTICR - - name: CMPCR - description: Compensation cell control register - byte_offset: 32 - access: Read - fieldset: CMPCR + - name: MEMRMP + description: memory remap register + byte_offset: 0 + fieldset: MEMRMP + - name: PMC + description: peripheral mode configuration register + byte_offset: 4 + fieldset: PMC + - name: EXTICR + description: external interrupt configuration register 1 + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: CMPCR + description: Compensation cell control register + byte_offset: 32 + access: Read + fieldset: CMPCR fieldset/CMPCR: description: Compensation cell control register fields: - - name: CMP_PD - description: Compensation cell power-down - bit_offset: 0 - bit_size: 1 - - name: READY - description: READY - bit_offset: 8 - bit_size: 1 + - name: CMP_PD + description: Compensation cell power-down + bit_offset: 0 + bit_size: 1 + - name: READY + description: READY + bit_offset: 8 + bit_size: 1 fieldset/EXTICR: description: external interrupt configuration register 1 fields: - - name: EXTI - description: EXTI x configuration (x = 0 to 3) - bit_offset: 0 - bit_size: 4 - array: - len: 4 - stride: 4 + - name: EXTI + description: EXTI x configuration (x = 0 to 3) + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 fieldset/MEMRMP: description: memory remap register fields: - - name: MEM_BOOT - description: Memory boot mapping - bit_offset: 0 - bit_size: 1 - - name: FB_MODE - description: Flash bank mode selection - bit_offset: 8 - bit_size: 1 - - name: SWP_FMC - description: FMC memory mapping swap - bit_offset: 10 - bit_size: 2 + - name: MEM_BOOT + description: Memory boot mapping + bit_offset: 0 + bit_size: 1 + - name: FB_MODE + description: Flash bank mode selection + bit_offset: 8 + bit_size: 1 + - name: SWP_FMC + description: FMC memory mapping swap + bit_offset: 10 + bit_size: 2 fieldset/PMC: description: peripheral mode configuration register fields: - - name: I2C1_FMP - description: I2C1_FMP I2C1 Fast Mode + Enable - bit_offset: 0 - bit_size: 1 - - name: I2C2_FMP - description: I2C2_FMP I2C2 Fast Mode + Enable - bit_offset: 1 - bit_size: 1 - - name: I2C3_FMP - description: I2C3_FMP I2C3 Fast Mode + Enable - bit_offset: 2 - bit_size: 1 - - name: I2C4_FMP - description: I2C4 Fast Mode + Enable - bit_offset: 3 - bit_size: 1 - - name: PB6_FMP - description: PB6_FMP Fast Mode - bit_offset: 4 - bit_size: 1 - - name: PB7_FMP - description: PB7_FMP Fast Mode + Enable - bit_offset: 5 - bit_size: 1 - - name: PB8_FMP - description: PB8_FMP Fast Mode + Enable - bit_offset: 6 - bit_size: 1 - - name: PB9_FMP - description: Fast Mode + Enable - bit_offset: 7 - bit_size: 1 - - name: ADC1DC2 - description: ADC3DC2 - bit_offset: 16 - bit_size: 1 - - name: ADC2DC2 - description: ADC2DC2 - bit_offset: 17 - bit_size: 1 - - name: ADC3DC2 - description: ADC3DC2 - bit_offset: 18 - bit_size: 1 - - name: MII_RMII_SEL - description: Ethernet PHY interface selection - bit_offset: 23 - bit_size: 1 + - name: I2C1_FMP + description: I2C1_FMP I2C1 Fast Mode + Enable + bit_offset: 0 + bit_size: 1 + - name: I2C2_FMP + description: I2C2_FMP I2C2 Fast Mode + Enable + bit_offset: 1 + bit_size: 1 + - name: I2C3_FMP + description: I2C3_FMP I2C3 Fast Mode + Enable + bit_offset: 2 + bit_size: 1 + - name: I2C4_FMP + description: I2C4 Fast Mode + Enable + bit_offset: 3 + bit_size: 1 + - name: PB6_FMP + description: PB6_FMP Fast Mode + bit_offset: 4 + bit_size: 1 + - name: PB7_FMP + description: PB7_FMP Fast Mode + Enable + bit_offset: 5 + bit_size: 1 + - name: PB8_FMP + description: PB8_FMP Fast Mode + Enable + bit_offset: 6 + bit_size: 1 + - name: PB9_FMP + description: Fast Mode + Enable + bit_offset: 7 + bit_size: 1 + - name: ADC1DC2 + description: ADC3DC2 + bit_offset: 16 + bit_size: 1 + - name: ADC2DC2 + description: ADC2DC2 + bit_offset: 17 + bit_size: 1 + - name: ADC3DC2 + description: ADC3DC2 + bit_offset: 18 + bit_size: 1 + - name: MII_RMII_SEL + description: Ethernet PHY interface selection + bit_offset: 23 + bit_size: 1 diff --git a/data/registers/syscfg_g0.yaml b/data/registers/syscfg_g0.yaml index 3cf81eb..448223c 100644 --- a/data/registers/syscfg_g0.yaml +++ b/data/registers/syscfg_g0.yaml @@ -1,684 +1,683 @@ ---- block/SYSCFG: description: System configuration controller items: - - name: CFGR1 - description: configuration register 1 - byte_offset: 0 - fieldset: CFGR1 - - name: CFGR2 - description: configuration register 1 - byte_offset: 24 - fieldset: CFGR2 - - name: VREFBUF_CSR - description: VREFBUF control and status register - byte_offset: 48 - fieldset: VREFBUF_CSR - - name: VREFBUF_CCR - description: VREFBUF calibration control register - byte_offset: 52 - fieldset: VREFBUF_CCR - - name: ITLINE0 - description: interrupt line 0 status register - byte_offset: 128 - access: Read - fieldset: ITLINE0 - - name: ITLINE1 - description: interrupt line 1 status register - byte_offset: 132 - access: Read - fieldset: ITLINE1 - - name: ITLINE2 - description: interrupt line 2 status register - byte_offset: 136 - access: Read - fieldset: ITLINE2 - - name: ITLINE3 - description: interrupt line 3 status register - byte_offset: 140 - access: Read - fieldset: ITLINE3 - - name: ITLINE4 - description: interrupt line 4 status register - byte_offset: 144 - access: Read - fieldset: ITLINE4 - - name: ITLINE5 - description: interrupt line 5 status register - byte_offset: 148 - access: Read - fieldset: ITLINE5 - - name: ITLINE6 - description: interrupt line 6 status register - byte_offset: 152 - access: Read - fieldset: ITLINE6 - - name: ITLINE7 - description: interrupt line 7 status register - byte_offset: 156 - access: Read - fieldset: ITLINE7 - - name: ITLINE8 - description: interrupt line 8 status register - byte_offset: 160 - access: Read - fieldset: ITLINE8 - - name: ITLINE9 - description: interrupt line 9 status register - byte_offset: 164 - access: Read - fieldset: ITLINE9 - - name: ITLINE10 - description: interrupt line 10 status register - byte_offset: 168 - access: Read - fieldset: ITLINE10 - - name: ITLINE11 - description: interrupt line 11 status register - byte_offset: 172 - access: Read - fieldset: ITLINE11 - - name: ITLINE12 - description: interrupt line 12 status register - byte_offset: 176 - access: Read - fieldset: ITLINE12 - - name: ITLINE13 - description: interrupt line 13 status register - byte_offset: 180 - access: Read - fieldset: ITLINE13 - - name: ITLINE14 - description: interrupt line 14 status register - byte_offset: 184 - access: Read - fieldset: ITLINE14 - - name: ITLINE15 - description: interrupt line 15 status register - byte_offset: 188 - access: Read - fieldset: ITLINE15 - - name: ITLINE16 - description: interrupt line 16 status register - byte_offset: 192 - access: Read - fieldset: ITLINE16 - - name: ITLINE17 - description: interrupt line 17 status register - byte_offset: 196 - access: Read - fieldset: ITLINE17 - - name: ITLINE18 - description: interrupt line 18 status register - byte_offset: 200 - access: Read - fieldset: ITLINE18 - - name: ITLINE19 - description: interrupt line 19 status register - byte_offset: 204 - access: Read - fieldset: ITLINE19 - - name: ITLINE20 - description: interrupt line 20 status register - byte_offset: 208 - access: Read - fieldset: ITLINE20 - - name: ITLINE21 - description: interrupt line 21 status register - byte_offset: 212 - access: Read - fieldset: ITLINE21 - - name: ITLINE22 - description: interrupt line 22 status register - byte_offset: 216 - access: Read - fieldset: ITLINE22 - - name: ITLINE23 - description: interrupt line 23 status register - byte_offset: 220 - access: Read - fieldset: ITLINE23 - - name: ITLINE24 - description: interrupt line 24 status register - byte_offset: 224 - access: Read - fieldset: ITLINE24 - - name: ITLINE25 - description: interrupt line 25 status register - byte_offset: 228 - access: Read - fieldset: ITLINE25 - - name: ITLINE26 - description: interrupt line 26 status register - byte_offset: 232 - access: Read - fieldset: ITLINE26 - - name: ITLINE27 - description: interrupt line 27 status register - byte_offset: 236 - access: Read - fieldset: ITLINE27 - - name: ITLINE28 - description: interrupt line 28 status register - byte_offset: 240 - access: Read - fieldset: ITLINE28 - - name: ITLINE29 - description: interrupt line 29 status register - byte_offset: 244 - access: Read - fieldset: ITLINE29 - - name: ITLINE30 - description: interrupt line 30 status register - byte_offset: 248 - access: Read - fieldset: ITLINE30 - - name: ITLINE31 - description: interrupt line 31 status register - byte_offset: 252 - access: Read - fieldset: ITLINE31 + - name: CFGR1 + description: configuration register 1 + byte_offset: 0 + fieldset: CFGR1 + - name: CFGR2 + description: configuration register 1 + byte_offset: 24 + fieldset: CFGR2 + - name: VREFBUF_CSR + description: VREFBUF control and status register + byte_offset: 48 + fieldset: VREFBUF_CSR + - name: VREFBUF_CCR + description: VREFBUF calibration control register + byte_offset: 52 + fieldset: VREFBUF_CCR + - name: ITLINE0 + description: interrupt line 0 status register + byte_offset: 128 + access: Read + fieldset: ITLINE0 + - name: ITLINE1 + description: interrupt line 1 status register + byte_offset: 132 + access: Read + fieldset: ITLINE1 + - name: ITLINE2 + description: interrupt line 2 status register + byte_offset: 136 + access: Read + fieldset: ITLINE2 + - name: ITLINE3 + description: interrupt line 3 status register + byte_offset: 140 + access: Read + fieldset: ITLINE3 + - name: ITLINE4 + description: interrupt line 4 status register + byte_offset: 144 + access: Read + fieldset: ITLINE4 + - name: ITLINE5 + description: interrupt line 5 status register + byte_offset: 148 + access: Read + fieldset: ITLINE5 + - name: ITLINE6 + description: interrupt line 6 status register + byte_offset: 152 + access: Read + fieldset: ITLINE6 + - name: ITLINE7 + description: interrupt line 7 status register + byte_offset: 156 + access: Read + fieldset: ITLINE7 + - name: ITLINE8 + description: interrupt line 8 status register + byte_offset: 160 + access: Read + fieldset: ITLINE8 + - name: ITLINE9 + description: interrupt line 9 status register + byte_offset: 164 + access: Read + fieldset: ITLINE9 + - name: ITLINE10 + description: interrupt line 10 status register + byte_offset: 168 + access: Read + fieldset: ITLINE10 + - name: ITLINE11 + description: interrupt line 11 status register + byte_offset: 172 + access: Read + fieldset: ITLINE11 + - name: ITLINE12 + description: interrupt line 12 status register + byte_offset: 176 + access: Read + fieldset: ITLINE12 + - name: ITLINE13 + description: interrupt line 13 status register + byte_offset: 180 + access: Read + fieldset: ITLINE13 + - name: ITLINE14 + description: interrupt line 14 status register + byte_offset: 184 + access: Read + fieldset: ITLINE14 + - name: ITLINE15 + description: interrupt line 15 status register + byte_offset: 188 + access: Read + fieldset: ITLINE15 + - name: ITLINE16 + description: interrupt line 16 status register + byte_offset: 192 + access: Read + fieldset: ITLINE16 + - name: ITLINE17 + description: interrupt line 17 status register + byte_offset: 196 + access: Read + fieldset: ITLINE17 + - name: ITLINE18 + description: interrupt line 18 status register + byte_offset: 200 + access: Read + fieldset: ITLINE18 + - name: ITLINE19 + description: interrupt line 19 status register + byte_offset: 204 + access: Read + fieldset: ITLINE19 + - name: ITLINE20 + description: interrupt line 20 status register + byte_offset: 208 + access: Read + fieldset: ITLINE20 + - name: ITLINE21 + description: interrupt line 21 status register + byte_offset: 212 + access: Read + fieldset: ITLINE21 + - name: ITLINE22 + description: interrupt line 22 status register + byte_offset: 216 + access: Read + fieldset: ITLINE22 + - name: ITLINE23 + description: interrupt line 23 status register + byte_offset: 220 + access: Read + fieldset: ITLINE23 + - name: ITLINE24 + description: interrupt line 24 status register + byte_offset: 224 + access: Read + fieldset: ITLINE24 + - name: ITLINE25 + description: interrupt line 25 status register + byte_offset: 228 + access: Read + fieldset: ITLINE25 + - name: ITLINE26 + description: interrupt line 26 status register + byte_offset: 232 + access: Read + fieldset: ITLINE26 + - name: ITLINE27 + description: interrupt line 27 status register + byte_offset: 236 + access: Read + fieldset: ITLINE27 + - name: ITLINE28 + description: interrupt line 28 status register + byte_offset: 240 + access: Read + fieldset: ITLINE28 + - name: ITLINE29 + description: interrupt line 29 status register + byte_offset: 244 + access: Read + fieldset: ITLINE29 + - name: ITLINE30 + description: interrupt line 30 status register + byte_offset: 248 + access: Read + fieldset: ITLINE30 + - name: ITLINE31 + description: interrupt line 31 status register + byte_offset: 252 + access: Read + fieldset: ITLINE31 fieldset/CFGR1: description: configuration register 1 fields: - - name: MEM_MODE - description: Memory mapping selection bits. This bitfield controlled by software selects the memory internally mapped at the address 0x0000_0000. Its reset value is determined by the boot mode configuration. Refer to Reference Manual section 2.5 for more details. - bit_offset: 0 - bit_size: 2 - enum: MEM_MODE - - name: PA11_RMP - description: "PA11 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port." - bit_offset: 3 - bit_size: 1 - - name: PA12_RMP - description: "PA12 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port." - bit_offset: 4 - bit_size: 1 - - name: IR_POL - description: IR output polarity selection - bit_offset: 5 - bit_size: 1 - - name: IR_MOD - description: IR Modulation Envelope signal selection. - bit_offset: 6 - bit_size: 2 - - name: BOOSTEN - description: I/O analog switch voltage booster enable - bit_offset: 8 - bit_size: 1 - - name: UCPD1_STROBE - description: Strobe signal bit for UCPD1 - bit_offset: 9 - bit_size: 1 - - name: UCPD2_STROBE - description: Strobe signal bit for UCPD2 - bit_offset: 10 - bit_size: 1 - - name: I2C_PBx_FMP - description: Fast Mode Plus (FM+) driving capability activation bits - bit_offset: 16 - bit_size: 4 - - name: I2C1_FMP - description: FM+ driving capability activation for I2C1 - bit_offset: 20 - bit_size: 1 - - name: I2C2_FMP - description: FM+ driving capability activation for I2C2 - bit_offset: 21 - bit_size: 1 - - name: I2C_PAx_FMP - description: Fast Mode Plus (FM+) driving capability activation bits - bit_offset: 22 - bit_size: 2 + - name: MEM_MODE + description: Memory mapping selection bits. This bitfield controlled by software selects the memory internally mapped at the address 0x0000_0000. Its reset value is determined by the boot mode configuration. Refer to Reference Manual section 2.5 for more details. + bit_offset: 0 + bit_size: 2 + enum: MEM_MODE + - name: PA11_RMP + description: "PA11 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port." + bit_offset: 3 + bit_size: 1 + - name: PA12_RMP + description: "PA12 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port." + bit_offset: 4 + bit_size: 1 + - name: IR_POL + description: IR output polarity selection + bit_offset: 5 + bit_size: 1 + - name: IR_MOD + description: IR Modulation Envelope signal selection. + bit_offset: 6 + bit_size: 2 + - name: BOOSTEN + description: I/O analog switch voltage booster enable + bit_offset: 8 + bit_size: 1 + - name: UCPD1_STROBE + description: Strobe signal bit for UCPD1 + bit_offset: 9 + bit_size: 1 + - name: UCPD2_STROBE + description: Strobe signal bit for UCPD2 + bit_offset: 10 + bit_size: 1 + - name: I2C_PBx_FMP + description: Fast Mode Plus (FM+) driving capability activation bits + bit_offset: 16 + bit_size: 4 + - name: I2C1_FMP + description: FM+ driving capability activation for I2C1 + bit_offset: 20 + bit_size: 1 + - name: I2C2_FMP + description: FM+ driving capability activation for I2C2 + bit_offset: 21 + bit_size: 1 + - name: I2C_PAx_FMP + description: Fast Mode Plus (FM+) driving capability activation bits + bit_offset: 22 + bit_size: 2 fieldset/CFGR2: description: configuration register 1 fields: - - name: LOCKUP_LOCK - description: Cortex-M0+ LOCKUP bit enable bit - bit_offset: 0 - bit_size: 1 - - name: SRAM_PARITY_LOCK - description: SRAM parity lock bit - bit_offset: 1 - bit_size: 1 - - name: PVD_LOCK - description: PVD lock enable bit - bit_offset: 2 - bit_size: 1 - - name: ECC_LOCK - description: ECC error lock bit - bit_offset: 3 - bit_size: 1 - - name: SRAM_PEF - description: SRAM parity error flag - bit_offset: 8 - bit_size: 1 - - name: PA1_CDEN - description: PA1_CDEN - bit_offset: 16 - bit_size: 1 - - name: PA3_CDEN - description: PA3_CDEN - bit_offset: 17 - bit_size: 1 - - name: PA5_CDEN - description: PA5_CDEN - bit_offset: 18 - bit_size: 1 - - name: PA6_CDEN - description: PA6_CDEN - bit_offset: 19 - bit_size: 1 - - name: PA13_CDEN - description: PA13_CDEN - bit_offset: 20 - bit_size: 1 - - name: PB0_CDEN - description: PB0_CDEN - bit_offset: 21 - bit_size: 1 - - name: PB1_CDEN - description: PB1_CDEN - bit_offset: 22 - bit_size: 1 - - name: PB2_CDEN - description: PB2_CDEN - bit_offset: 23 - bit_size: 1 + - name: LOCKUP_LOCK + description: Cortex-M0+ LOCKUP bit enable bit + bit_offset: 0 + bit_size: 1 + - name: SRAM_PARITY_LOCK + description: SRAM parity lock bit + bit_offset: 1 + bit_size: 1 + - name: PVD_LOCK + description: PVD lock enable bit + bit_offset: 2 + bit_size: 1 + - name: ECC_LOCK + description: ECC error lock bit + bit_offset: 3 + bit_size: 1 + - name: SRAM_PEF + description: SRAM parity error flag + bit_offset: 8 + bit_size: 1 + - name: PA1_CDEN + description: PA1_CDEN + bit_offset: 16 + bit_size: 1 + - name: PA3_CDEN + description: PA3_CDEN + bit_offset: 17 + bit_size: 1 + - name: PA5_CDEN + description: PA5_CDEN + bit_offset: 18 + bit_size: 1 + - name: PA6_CDEN + description: PA6_CDEN + bit_offset: 19 + bit_size: 1 + - name: PA13_CDEN + description: PA13_CDEN + bit_offset: 20 + bit_size: 1 + - name: PB0_CDEN + description: PB0_CDEN + bit_offset: 21 + bit_size: 1 + - name: PB1_CDEN + description: PB1_CDEN + bit_offset: 22 + bit_size: 1 + - name: PB2_CDEN + description: PB2_CDEN + bit_offset: 23 + bit_size: 1 fieldset/ITLINE0: description: interrupt line 0 status register fields: - - name: WWDG - description: Window watchdog interrupt pending flag - bit_offset: 0 - bit_size: 1 + - name: WWDG + description: Window watchdog interrupt pending flag + bit_offset: 0 + bit_size: 1 fieldset/ITLINE1: description: interrupt line 1 status register fields: - - name: PVDOUT - description: PVD supply monitoring interrupt request pending (EXTI line 16). - bit_offset: 0 - bit_size: 1 + - name: PVDOUT + description: PVD supply monitoring interrupt request pending (EXTI line 16). + bit_offset: 0 + bit_size: 1 fieldset/ITLINE10: description: interrupt line 10 status register fields: - - name: DMA1_CH2 - description: DMA1_CH1 - bit_offset: 0 - bit_size: 1 - - name: DMA1_CH3 - description: DMA1_CH3 - bit_offset: 1 - bit_size: 1 + - name: DMA1_CH2 + description: DMA1_CH1 + bit_offset: 0 + bit_size: 1 + - name: DMA1_CH3 + description: DMA1_CH3 + bit_offset: 1 + bit_size: 1 fieldset/ITLINE11: description: interrupt line 11 status register fields: - - name: DMAMUX - description: DMAMUX - bit_offset: 0 - bit_size: 1 - - name: DMA1_CH4 - description: DMA1_CH4 - bit_offset: 1 - bit_size: 1 - - name: DMA1_CH5 - description: DMA1_CH5 - bit_offset: 2 - bit_size: 1 - - name: DMA1_CH6 - description: DMA1_CH6 - bit_offset: 3 - bit_size: 1 - - name: DMA1_CH7 - description: DMA1_CH7 - bit_offset: 4 - bit_size: 1 + - name: DMAMUX + description: DMAMUX + bit_offset: 0 + bit_size: 1 + - name: DMA1_CH4 + description: DMA1_CH4 + bit_offset: 1 + bit_size: 1 + - name: DMA1_CH5 + description: DMA1_CH5 + bit_offset: 2 + bit_size: 1 + - name: DMA1_CH6 + description: DMA1_CH6 + bit_offset: 3 + bit_size: 1 + - name: DMA1_CH7 + description: DMA1_CH7 + bit_offset: 4 + bit_size: 1 fieldset/ITLINE12: description: interrupt line 12 status register fields: - - name: ADC - description: ADC - bit_offset: 0 - bit_size: 1 - - name: COMP1 - description: COMP1 - bit_offset: 1 - bit_size: 1 - - name: COMP2 - description: COMP2 - bit_offset: 2 - bit_size: 1 + - name: ADC + description: ADC + bit_offset: 0 + bit_size: 1 + - name: COMP1 + description: COMP1 + bit_offset: 1 + bit_size: 1 + - name: COMP2 + description: COMP2 + bit_offset: 2 + bit_size: 1 fieldset/ITLINE13: description: interrupt line 13 status register fields: - - name: TIM1_CCU - description: TIM1_CCU - bit_offset: 0 - bit_size: 1 - - name: TIM1_TRG - description: TIM1_TRG - bit_offset: 1 - bit_size: 1 - - name: TIM1_UPD - description: TIM1_UPD - bit_offset: 2 - bit_size: 1 - - name: TIM1_BRK - description: TIM1_BRK - bit_offset: 3 - bit_size: 1 + - name: TIM1_CCU + description: TIM1_CCU + bit_offset: 0 + bit_size: 1 + - name: TIM1_TRG + description: TIM1_TRG + bit_offset: 1 + bit_size: 1 + - name: TIM1_UPD + description: TIM1_UPD + bit_offset: 2 + bit_size: 1 + - name: TIM1_BRK + description: TIM1_BRK + bit_offset: 3 + bit_size: 1 fieldset/ITLINE14: description: interrupt line 14 status register fields: - - name: TIM1_CC - description: TIM1_CC - bit_offset: 0 - bit_size: 1 + - name: TIM1_CC + description: TIM1_CC + bit_offset: 0 + bit_size: 1 fieldset/ITLINE15: description: interrupt line 15 status register fields: - - name: TIM2 - description: TIM2 - bit_offset: 0 - bit_size: 1 + - name: TIM2 + description: TIM2 + bit_offset: 0 + bit_size: 1 fieldset/ITLINE16: description: interrupt line 16 status register fields: - - name: TIM3 - description: TIM3 - bit_offset: 0 - bit_size: 1 + - name: TIM3 + description: TIM3 + bit_offset: 0 + bit_size: 1 fieldset/ITLINE17: description: interrupt line 17 status register fields: - - name: TIM6 - description: TIM6 - bit_offset: 0 - bit_size: 1 - - name: DAC - description: DAC - bit_offset: 1 - bit_size: 1 - - name: LPTIM1 - description: LPTIM1 - bit_offset: 2 - bit_size: 1 + - name: TIM6 + description: TIM6 + bit_offset: 0 + bit_size: 1 + - name: DAC + description: DAC + bit_offset: 1 + bit_size: 1 + - name: LPTIM1 + description: LPTIM1 + bit_offset: 2 + bit_size: 1 fieldset/ITLINE18: description: interrupt line 18 status register fields: - - name: TIM7 - description: TIM7 - bit_offset: 0 - bit_size: 1 - - name: LPTIM2 - description: LPTIM2 - bit_offset: 1 - bit_size: 1 + - name: TIM7 + description: TIM7 + bit_offset: 0 + bit_size: 1 + - name: LPTIM2 + description: LPTIM2 + bit_offset: 1 + bit_size: 1 fieldset/ITLINE19: description: interrupt line 19 status register fields: - - name: TIM14 - description: TIM14 - bit_offset: 0 - bit_size: 1 + - name: TIM14 + description: TIM14 + bit_offset: 0 + bit_size: 1 fieldset/ITLINE2: description: interrupt line 2 status register fields: - - name: TAMP - description: TAMP - bit_offset: 0 - bit_size: 1 - - name: RTC - description: RTC - bit_offset: 1 - bit_size: 1 + - name: TAMP + description: TAMP + bit_offset: 0 + bit_size: 1 + - name: RTC + description: RTC + bit_offset: 1 + bit_size: 1 fieldset/ITLINE20: description: interrupt line 20 status register fields: - - name: TIM15 - description: TIM15 - bit_offset: 0 - bit_size: 1 + - name: TIM15 + description: TIM15 + bit_offset: 0 + bit_size: 1 fieldset/ITLINE21: description: interrupt line 21 status register fields: - - name: TIM16 - description: TIM16 - bit_offset: 0 - bit_size: 1 + - name: TIM16 + description: TIM16 + bit_offset: 0 + bit_size: 1 fieldset/ITLINE22: description: interrupt line 22 status register fields: - - name: TIM17 - description: TIM17 - bit_offset: 0 - bit_size: 1 + - name: TIM17 + description: TIM17 + bit_offset: 0 + bit_size: 1 fieldset/ITLINE23: description: interrupt line 23 status register fields: - - name: I2C1 - description: I2C1 - bit_offset: 0 - bit_size: 1 + - name: I2C1 + description: I2C1 + bit_offset: 0 + bit_size: 1 fieldset/ITLINE24: description: interrupt line 24 status register fields: - - name: I2C2 - description: I2C2 - bit_offset: 0 - bit_size: 1 + - name: I2C2 + description: I2C2 + bit_offset: 0 + bit_size: 1 fieldset/ITLINE25: description: interrupt line 25 status register fields: - - name: SPI1 - description: SPI1 - bit_offset: 0 - bit_size: 1 + - name: SPI1 + description: SPI1 + bit_offset: 0 + bit_size: 1 fieldset/ITLINE26: description: interrupt line 26 status register fields: - - name: SPI2 - description: SPI2 - bit_offset: 0 - bit_size: 1 + - name: SPI2 + description: SPI2 + bit_offset: 0 + bit_size: 1 fieldset/ITLINE27: description: interrupt line 27 status register fields: - - name: USART1 - description: USART1 - bit_offset: 0 - bit_size: 1 + - name: USART1 + description: USART1 + bit_offset: 0 + bit_size: 1 fieldset/ITLINE28: description: interrupt line 28 status register fields: - - name: USART2 - description: USART2 - bit_offset: 0 - bit_size: 1 + - name: USART2 + description: USART2 + bit_offset: 0 + bit_size: 1 fieldset/ITLINE29: description: interrupt line 29 status register fields: - - name: USART3 - bit_offset: 0 - bit_size: 1 - - name: USART4 - bit_offset: 1 - bit_size: 1 - - name: USART5 - bit_offset: 3 - bit_size: 1 - - name: USART6 - bit_offset: 4 - bit_size: 1 + - name: USART3 + bit_offset: 0 + bit_size: 1 + - name: USART4 + bit_offset: 1 + bit_size: 1 + - name: USART5 + bit_offset: 3 + bit_size: 1 + - name: USART6 + bit_offset: 4 + bit_size: 1 fieldset/ITLINE3: description: interrupt line 3 status register fields: - - name: FLASH_ITF - description: FLASH_ITF - bit_offset: 0 - bit_size: 1 - - name: FLASH_ECC - description: FLASH_ECC - bit_offset: 1 - bit_size: 1 + - name: FLASH_ITF + description: FLASH_ITF + bit_offset: 0 + bit_size: 1 + - name: FLASH_ECC + description: FLASH_ECC + bit_offset: 1 + bit_size: 1 fieldset/ITLINE30: description: interrupt line 30 status register fields: - - name: CEC - description: CEC - bit_offset: 0 - bit_size: 1 + - name: CEC + description: CEC + bit_offset: 0 + bit_size: 1 fieldset/ITLINE31: description: interrupt line 31 status register fields: - - name: RNG - description: RNG - bit_offset: 0 - bit_size: 1 - - name: AES - description: AES - bit_offset: 1 - bit_size: 1 + - name: RNG + description: RNG + bit_offset: 0 + bit_size: 1 + - name: AES + description: AES + bit_offset: 1 + bit_size: 1 fieldset/ITLINE4: description: interrupt line 4 status register fields: - - name: RCC - description: RCC - bit_offset: 0 - bit_size: 1 + - name: RCC + description: RCC + bit_offset: 0 + bit_size: 1 fieldset/ITLINE5: description: interrupt line 5 status register fields: - - name: EXTI0 - description: EXTI0 - bit_offset: 0 - bit_size: 1 - - name: EXTI1 - description: EXTI1 - bit_offset: 1 - bit_size: 1 + - name: EXTI0 + description: EXTI0 + bit_offset: 0 + bit_size: 1 + - name: EXTI1 + description: EXTI1 + bit_offset: 1 + bit_size: 1 fieldset/ITLINE6: description: interrupt line 6 status register fields: - - name: EXTI2 - description: EXTI2 - bit_offset: 0 - bit_size: 1 - - name: EXTI3 - description: EXTI3 - bit_offset: 1 - bit_size: 1 + - name: EXTI2 + description: EXTI2 + bit_offset: 0 + bit_size: 1 + - name: EXTI3 + description: EXTI3 + bit_offset: 1 + bit_size: 1 fieldset/ITLINE7: description: interrupt line 7 status register fields: - - name: EXTI4 - description: EXTI4 - bit_offset: 0 - bit_size: 1 - - name: EXTI5 - description: EXTI5 - bit_offset: 1 - bit_size: 1 - - name: EXTI6 - description: EXTI6 - bit_offset: 2 - bit_size: 1 - - name: EXTI7 - description: EXTI7 - bit_offset: 3 - bit_size: 1 - - name: EXTI8 - description: EXTI8 - bit_offset: 4 - bit_size: 1 - - name: EXTI9 - description: EXTI9 - bit_offset: 5 - bit_size: 1 - - name: EXTI10 - description: EXTI10 - bit_offset: 6 - bit_size: 1 - - name: EXTI11 - description: EXTI11 - bit_offset: 7 - bit_size: 1 - - name: EXTI12 - description: EXTI12 - bit_offset: 8 - bit_size: 1 - - name: EXTI13 - description: EXTI13 - bit_offset: 9 - bit_size: 1 - - name: EXTI14 - description: EXTI14 - bit_offset: 10 - bit_size: 1 - - name: EXTI15 - description: EXTI15 - bit_offset: 11 - bit_size: 1 + - name: EXTI4 + description: EXTI4 + bit_offset: 0 + bit_size: 1 + - name: EXTI5 + description: EXTI5 + bit_offset: 1 + bit_size: 1 + - name: EXTI6 + description: EXTI6 + bit_offset: 2 + bit_size: 1 + - name: EXTI7 + description: EXTI7 + bit_offset: 3 + bit_size: 1 + - name: EXTI8 + description: EXTI8 + bit_offset: 4 + bit_size: 1 + - name: EXTI9 + description: EXTI9 + bit_offset: 5 + bit_size: 1 + - name: EXTI10 + description: EXTI10 + bit_offset: 6 + bit_size: 1 + - name: EXTI11 + description: EXTI11 + bit_offset: 7 + bit_size: 1 + - name: EXTI12 + description: EXTI12 + bit_offset: 8 + bit_size: 1 + - name: EXTI13 + description: EXTI13 + bit_offset: 9 + bit_size: 1 + - name: EXTI14 + description: EXTI14 + bit_offset: 10 + bit_size: 1 + - name: EXTI15 + description: EXTI15 + bit_offset: 11 + bit_size: 1 fieldset/ITLINE8: description: interrupt line 8 status register fields: - - name: UCPD1 - description: UCPD1 - bit_offset: 0 - bit_size: 1 - - name: UCPD2 - description: UCPD2 - bit_offset: 1 - bit_size: 1 - - name: USB - description: USB - bit_offset: 2 - bit_size: 1 + - name: UCPD1 + description: UCPD1 + bit_offset: 0 + bit_size: 1 + - name: UCPD2 + description: UCPD2 + bit_offset: 1 + bit_size: 1 + - name: USB + description: USB + bit_offset: 2 + bit_size: 1 fieldset/ITLINE9: description: interrupt line 9 status register fields: - - name: DMA1_CH1 - description: DMA1_CH1 - bit_offset: 0 - bit_size: 1 + - name: DMA1_CH1 + description: DMA1_CH1 + bit_offset: 0 + bit_size: 1 fieldset/VREFBUF_CCR: description: VREFBUF calibration control register fields: - - name: TRIM - description: Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage. - bit_offset: 0 - bit_size: 6 + - name: TRIM + description: Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage. + bit_offset: 0 + bit_size: 6 fieldset/VREFBUF_CSR: description: VREFBUF control and status register fields: - - name: ENVR - description: Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode. - bit_offset: 0 - bit_size: 1 - - name: HIZ - description: "High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration." - bit_offset: 1 - bit_size: 1 - - name: VRR - description: Voltage reference buffer ready - bit_offset: 3 - bit_size: 1 - - name: VRS - description: "Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved" - bit_offset: 4 - bit_size: 3 + - name: ENVR + description: Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode. + bit_offset: 0 + bit_size: 1 + - name: HIZ + description: 'High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration.' + bit_offset: 1 + bit_size: 1 + - name: VRR + description: Voltage reference buffer ready + bit_offset: 3 + bit_size: 1 + - name: VRS + description: 'Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved' + bit_offset: 4 + bit_size: 3 enum/MEM_MODE: bit_size: 2 variants: - - name: MAIN_FLASH - description: Main Flash memory mapped at address 0 - value: 0 - - name: SYSTEM_FLASH - description: System Flash memory mapped at address 0 - value: 1 - - name: MAIN_FLASH_ALT - description: Main Flash memory mapped at address 0 (alternate encoding) - value: 2 - - name: SRAM - description: Embedded SRAM mapped at address 0 - value: 3 + - name: MAIN_FLASH + description: Main Flash memory mapped at address 0 + value: 0 + - name: SYSTEM_FLASH + description: System Flash memory mapped at address 0 + value: 1 + - name: MAIN_FLASH_ALT + description: Main Flash memory mapped at address 0 (alternate encoding) + value: 2 + - name: SRAM + description: Embedded SRAM mapped at address 0 + value: 3 diff --git a/data/registers/syscfg_g4.yaml b/data/registers/syscfg_g4.yaml index 56094e8..0aca795 100644 --- a/data/registers/syscfg_g4.yaml +++ b/data/registers/syscfg_g4.yaml @@ -1,155 +1,154 @@ ---- block/SYSCFG: description: System configuration controller items: - - name: MEMRMP - description: Remap Memory register - byte_offset: 0 - fieldset: MEMRMP - - name: CFGR1 - description: peripheral mode configuration register - byte_offset: 4 - fieldset: CFGR1 - - name: EXTICR - description: external interrupt configuration register 1 - array: - len: 4 - stride: 4 - byte_offset: 8 - fieldset: EXTICR - - name: SCSR - description: CCM SRAM control and status register - byte_offset: 24 - fieldset: SCSR - - name: CFGR2 - description: configuration register 2 - byte_offset: 28 - fieldset: CFGR2 - - name: SWPR - description: SRAM Write protection register 1 - byte_offset: 32 - fieldset: SWPR - - name: SKR - description: SRAM2 Key Register - byte_offset: 36 - access: Write - fieldset: SKR + - name: MEMRMP + description: Remap Memory register + byte_offset: 0 + fieldset: MEMRMP + - name: CFGR1 + description: peripheral mode configuration register + byte_offset: 4 + fieldset: CFGR1 + - name: EXTICR + description: external interrupt configuration register 1 + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: SCSR + description: CCM SRAM control and status register + byte_offset: 24 + fieldset: SCSR + - name: CFGR2 + description: configuration register 2 + byte_offset: 28 + fieldset: CFGR2 + - name: SWPR + description: SRAM Write protection register 1 + byte_offset: 32 + fieldset: SWPR + - name: SKR + description: SRAM2 Key Register + byte_offset: 36 + access: Write + fieldset: SKR fieldset/CFGR1: description: peripheral mode configuration register fields: - - name: BOOSTEN - description: BOOSTEN - bit_offset: 8 - bit_size: 1 - - name: ANASWVDD - description: GPIO analog switch control voltage selection - bit_offset: 9 - bit_size: 1 - - name: I2C_PB6_FMP - description: FM+ drive capability on PB6 - bit_offset: 16 - bit_size: 1 - - name: I2C_PB7_FMP - description: FM+ drive capability on PB6 - bit_offset: 17 - bit_size: 1 - - name: I2C_PB8_FMP - description: FM+ drive capability on PB6 - bit_offset: 18 - bit_size: 1 - - name: I2C_PB9_FMP - description: FM+ drive capability on PB6 - bit_offset: 19 - bit_size: 1 - - name: I2C1_FMP - description: I2C1 FM+ drive capability enable - bit_offset: 20 - bit_size: 1 - - name: I2C2_FMP - description: I2C1 FM+ drive capability enable - bit_offset: 21 - bit_size: 1 - - name: I2C3_FMP - description: I2C1 FM+ drive capability enable - bit_offset: 22 - bit_size: 1 - - name: I2C4_FMP - description: I2C1 FM+ drive capability enable - bit_offset: 23 - bit_size: 1 - - name: FPU_IE - description: FPU Interrupts Enable - bit_offset: 26 - bit_size: 6 + - name: BOOSTEN + description: BOOSTEN + bit_offset: 8 + bit_size: 1 + - name: ANASWVDD + description: GPIO analog switch control voltage selection + bit_offset: 9 + bit_size: 1 + - name: I2C_PB6_FMP + description: FM+ drive capability on PB6 + bit_offset: 16 + bit_size: 1 + - name: I2C_PB7_FMP + description: FM+ drive capability on PB6 + bit_offset: 17 + bit_size: 1 + - name: I2C_PB8_FMP + description: FM+ drive capability on PB6 + bit_offset: 18 + bit_size: 1 + - name: I2C_PB9_FMP + description: FM+ drive capability on PB6 + bit_offset: 19 + bit_size: 1 + - name: I2C1_FMP + description: I2C1 FM+ drive capability enable + bit_offset: 20 + bit_size: 1 + - name: I2C2_FMP + description: I2C1 FM+ drive capability enable + bit_offset: 21 + bit_size: 1 + - name: I2C3_FMP + description: I2C1 FM+ drive capability enable + bit_offset: 22 + bit_size: 1 + - name: I2C4_FMP + description: I2C1 FM+ drive capability enable + bit_offset: 23 + bit_size: 1 + - name: FPU_IE + description: FPU Interrupts Enable + bit_offset: 26 + bit_size: 6 fieldset/CFGR2: description: configuration register 2 fields: - - name: CLL - description: Core Lockup Lock - bit_offset: 0 - bit_size: 1 - - name: SPL - description: SRAM Parity Lock - bit_offset: 1 - bit_size: 1 - - name: PVDL - description: PVD Lock - bit_offset: 2 - bit_size: 1 - - name: ECCL - description: ECC Lock - bit_offset: 3 - bit_size: 1 - - name: SPF - description: SRAM Parity Flag - bit_offset: 8 - bit_size: 1 + - name: CLL + description: Core Lockup Lock + bit_offset: 0 + bit_size: 1 + - name: SPL + description: SRAM Parity Lock + bit_offset: 1 + bit_size: 1 + - name: PVDL + description: PVD Lock + bit_offset: 2 + bit_size: 1 + - name: ECCL + description: ECC Lock + bit_offset: 3 + bit_size: 1 + - name: SPF + description: SRAM Parity Flag + bit_offset: 8 + bit_size: 1 fieldset/EXTICR: description: external interrupt configuration register fields: - - name: EXTI - description: EXTI x configuration - bit_offset: 0 - bit_size: 4 - array: - len: 4 - stride: 4 + - name: EXTI + description: EXTI x configuration + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 fieldset/MEMRMP: description: Remap Memory register fields: - - name: MEM_MODE - description: Memory mapping selection - bit_offset: 0 - bit_size: 3 - - name: FB_mode - description: User Flash Bank mode - bit_offset: 8 - bit_size: 1 + - name: MEM_MODE + description: Memory mapping selection + bit_offset: 0 + bit_size: 3 + - name: FB_mode + description: User Flash Bank mode + bit_offset: 8 + bit_size: 1 fieldset/SCSR: description: CCM SRAM control and status register fields: - - name: CCMER - description: CCM SRAM Erase - bit_offset: 0 - bit_size: 1 - - name: CCMBSY - description: CCM SRAM busy by erase operation - bit_offset: 1 - bit_size: 1 + - name: CCMER + description: CCM SRAM Erase + bit_offset: 0 + bit_size: 1 + - name: CCMBSY + description: CCM SRAM busy by erase operation + bit_offset: 1 + bit_size: 1 fieldset/SKR: description: SRAM2 Key Register fields: - - name: KEY - description: SRAM2 Key for software erase - bit_offset: 0 - bit_size: 8 + - name: KEY + description: SRAM2 Key for software erase + bit_offset: 0 + bit_size: 8 fieldset/SWPR: description: SRAM Write protection register fields: - - name: Page_WP - description: Write protection - bit_offset: 0 - bit_size: 1 - array: - len: 32 - stride: 1 + - name: Page_WP + description: Write protection + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 diff --git a/data/registers/syscfg_h7.yaml b/data/registers/syscfg_h7.yaml index 2afe710..1f000ab 100644 --- a/data/registers/syscfg_h7.yaml +++ b/data/registers/syscfg_h7.yaml @@ -1,410 +1,398 @@ ---- block/SYSCFG: description: System configuration controller items: - - name: PMCR - description: peripheral mode configuration register - byte_offset: 4 - fieldset: PMCR - - name: EXTICR - description: external interrupt configuration register - array: - len: 4 - stride: 4 - byte_offset: 8 - fieldset: EXTICR - - name: CCCSR - description: compensation cell control/status register - byte_offset: 32 - fieldset: CCCSR - - name: CCVR - description: SYSCFG compensation cell value register - byte_offset: 36 - access: Read - fieldset: CCVR - - name: CCCR - description: SYSCFG compensation cell code register - byte_offset: 40 - fieldset: CCCR - - name: PWRCR - description: SYSCFG power control register - byte_offset: 44 - fieldset: PWRCR - - name: PKGR - description: SYSCFG package register - byte_offset: 292 - access: Read - fieldset: PKGR - - name: UR0 - description: SYSCFG user register 0 - byte_offset: 768 - access: Read - fieldset: UR0 - - name: UR2 - description: SYSCFG user register 2 - byte_offset: 776 - fieldset: UR2 - - name: UR3 - description: SYSCFG user register 3 - byte_offset: 780 - fieldset: UR3 - - name: UR4 - description: SYSCFG user register 4 - byte_offset: 784 - access: Read - fieldset: UR4 - - name: UR5 - description: SYSCFG user register 5 - byte_offset: 788 - access: Read - fieldset: UR5 - - name: UR6 - description: SYSCFG user register 6 - byte_offset: 792 - access: Read - fieldset: UR6 - - name: UR7 - description: SYSCFG user register 7 - byte_offset: 796 - access: Read - fieldset: UR7 - - name: UR8 - description: SYSCFG user register 8 - byte_offset: 800 - access: Read - fieldset: UR8 - - name: UR9 - description: SYSCFG user register 9 - byte_offset: 804 - access: Read - fieldset: UR9 - - name: UR10 - description: SYSCFG user register 10 - byte_offset: 808 - access: Read - fieldset: UR10 - - name: UR11 - description: SYSCFG user register 11 - byte_offset: 812 - access: Read - fieldset: UR11 - - name: UR12 - description: SYSCFG user register 12 - byte_offset: 816 - access: Read - fieldset: UR12 - - name: UR13 - description: SYSCFG user register 13 - byte_offset: 820 - access: Read - fieldset: UR13 - - name: UR14 - description: SYSCFG user register 14 - byte_offset: 824 - fieldset: UR14 - - name: UR15 - description: SYSCFG user register 15 - byte_offset: 828 - access: Read - fieldset: UR15 - - name: UR16 - description: SYSCFG user register 16 - byte_offset: 832 - access: Read - fieldset: UR16 - - name: UR17 - description: SYSCFG user register 17 - byte_offset: 836 - access: Read - fieldset: UR17 + - name: PMCR + description: peripheral mode configuration register + byte_offset: 4 + fieldset: PMCR + - name: EXTICR + description: external interrupt configuration register + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: CCCSR + description: compensation cell control/status register + byte_offset: 32 + fieldset: CCCSR + - name: CCVR + description: SYSCFG compensation cell value register + byte_offset: 36 + access: Read + fieldset: CCVR + - name: CCCR + description: SYSCFG compensation cell code register + byte_offset: 40 + fieldset: CCCR + - name: PKGR + description: SYSCFG package register + byte_offset: 292 + access: Read + fieldset: PKGR + - name: UR0 + description: SYSCFG user register 0 + byte_offset: 768 + access: Read + fieldset: UR0 + - name: UR2 + description: SYSCFG user register 2 + byte_offset: 776 + fieldset: UR2 + - name: UR3 + description: SYSCFG user register 3 + byte_offset: 780 + fieldset: UR3 + - name: UR4 + description: SYSCFG user register 4 + byte_offset: 784 + access: Read + fieldset: UR4 + - name: UR5 + description: SYSCFG user register 5 + byte_offset: 788 + access: Read + fieldset: UR5 + - name: UR6 + description: SYSCFG user register 6 + byte_offset: 792 + access: Read + fieldset: UR6 + - name: UR7 + description: SYSCFG user register 7 + byte_offset: 796 + access: Read + fieldset: UR7 + - name: UR8 + description: SYSCFG user register 8 + byte_offset: 800 + access: Read + fieldset: UR8 + - name: UR9 + description: SYSCFG user register 9 + byte_offset: 804 + access: Read + fieldset: UR9 + - name: UR10 + description: SYSCFG user register 10 + byte_offset: 808 + access: Read + fieldset: UR10 + - name: UR11 + description: SYSCFG user register 11 + byte_offset: 812 + access: Read + fieldset: UR11 + - name: UR12 + description: SYSCFG user register 12 + byte_offset: 816 + access: Read + fieldset: UR12 + - name: UR13 + description: SYSCFG user register 13 + byte_offset: 820 + access: Read + fieldset: UR13 + - name: UR14 + description: SYSCFG user register 14 + byte_offset: 824 + fieldset: UR14 + - name: UR15 + description: SYSCFG user register 15 + byte_offset: 828 + access: Read + fieldset: UR15 + - name: UR16 + description: SYSCFG user register 16 + byte_offset: 832 + access: Read + fieldset: UR16 + - name: UR17 + description: SYSCFG user register 17 + byte_offset: 836 + access: Read + fieldset: UR17 fieldset/CCCR: description: SYSCFG compensation cell code register fields: - - name: NCC - description: NMOS compensation code - bit_offset: 0 - bit_size: 4 - - name: PCC - description: PMOS compensation code - bit_offset: 4 - bit_size: 4 + - name: NCC + description: NMOS compensation code + bit_offset: 0 + bit_size: 4 + - name: PCC + description: PMOS compensation code + bit_offset: 4 + bit_size: 4 fieldset/CCCSR: description: compensation cell control/status register fields: - - name: EN - description: enable - bit_offset: 0 - bit_size: 1 - - name: CS - description: Code selection - bit_offset: 1 - bit_size: 1 - - name: READY - description: Compensation cell ready flag - bit_offset: 8 - bit_size: 1 - - name: HSLV - description: High-speed at low-voltage - bit_offset: 16 - bit_size: 1 + - name: EN + description: enable + bit_offset: 0 + bit_size: 1 + - name: CS + description: Code selection + bit_offset: 1 + bit_size: 1 + - name: READY + description: Compensation cell ready flag + bit_offset: 8 + bit_size: 1 + - name: HSLV + description: High-speed at low-voltage + bit_offset: 16 + bit_size: 1 fieldset/CCVR: description: SYSCFG compensation cell value register fields: - - name: NCV - description: NMOS compensation value - bit_offset: 0 - bit_size: 4 - - name: PCV - description: PMOS compensation value - bit_offset: 4 - bit_size: 4 + - name: NCV + description: NMOS compensation value + bit_offset: 0 + bit_size: 4 + - name: PCV + description: PMOS compensation value + bit_offset: 4 + bit_size: 4 fieldset/EXTICR: description: external interrupt configuration register 2 fields: - - name: EXTI - description: EXTI x configuration (x = 4 to 7) - bit_offset: 0 - bit_size: 4 - array: - len: 4 - stride: 4 + - name: EXTI + description: EXTI x configuration (x = 4 to 7) + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 fieldset/PKGR: description: SYSCFG package register fields: - - name: PKG - description: Package - bit_offset: 0 - bit_size: 4 + - name: PKG + description: Package + bit_offset: 0 + bit_size: 4 fieldset/PMCR: description: peripheral mode configuration register fields: - - name: I2C1FMP - description: I2C1 Fm+ - bit_offset: 0 - bit_size: 1 - - name: I2C2FMP - description: I2C2 Fm+ - bit_offset: 1 - bit_size: 1 - - name: I2C3FMP - description: I2C3 Fm+ - bit_offset: 2 - bit_size: 1 - - name: I2C4FMP - description: I2C4 Fm+ - bit_offset: 3 - bit_size: 1 - - name: PB6FMP - description: PB(6) Fm+ - bit_offset: 4 - bit_size: 1 - - name: PB7FMP - description: PB(7) Fast Mode Plus - bit_offset: 5 - bit_size: 1 - - name: PB8FMP - description: PB(8) Fast Mode Plus - bit_offset: 6 - bit_size: 1 - - name: PB9FMP - description: PB(9) Fm+ - bit_offset: 7 - bit_size: 1 - - name: BOOSTE - description: Booster Enable - bit_offset: 8 - bit_size: 1 - - name: BOOSTVDDSEL - description: Analog switch supply voltage selection - bit_offset: 9 - bit_size: 1 - - name: EPIS - description: Ethernet PHY Interface Selection - bit_offset: 21 - bit_size: 3 - - name: PA0SO - description: PA0 Switch Open - bit_offset: 24 - bit_size: 1 - - name: PA1SO - description: PA1 Switch Open - bit_offset: 25 - bit_size: 1 - - name: PC2SO - description: PC2 Switch Open - bit_offset: 26 - bit_size: 1 - - name: PC3SO - description: PC3 Switch Open - bit_offset: 27 - bit_size: 1 -fieldset/PWRCR: - description: SYSCFG power control register - fields: - - name: ODEN - description: Overdrive enable - bit_offset: 0 - bit_size: 4 + - name: I2C1FMP + description: I2C1 Fm+ + bit_offset: 0 + bit_size: 1 + - name: I2C2FMP + description: I2C2 Fm+ + bit_offset: 1 + bit_size: 1 + - name: I2C3FMP + description: I2C3 Fm+ + bit_offset: 2 + bit_size: 1 + - name: I2C4FMP + description: I2C4 Fm+ + bit_offset: 3 + bit_size: 1 + - name: PB6FMP + description: PB(6) Fm+ + bit_offset: 4 + bit_size: 1 + - name: PB7FMP + description: PB(7) Fast Mode Plus + bit_offset: 5 + bit_size: 1 + - name: PB8FMP + description: PB(8) Fast Mode Plus + bit_offset: 6 + bit_size: 1 + - name: PB9FMP + description: PB(9) Fm+ + bit_offset: 7 + bit_size: 1 + - name: BOOSTE + description: Booster Enable + bit_offset: 8 + bit_size: 1 + - name: BOOSTVDDSEL + description: Analog switch supply voltage selection + bit_offset: 9 + bit_size: 1 + - name: EPIS + description: Ethernet PHY Interface Selection + bit_offset: 21 + bit_size: 3 + - name: PA0SO + description: PA0 Switch Open + bit_offset: 24 + bit_size: 1 + - name: PA1SO + description: PA1 Switch Open + bit_offset: 25 + bit_size: 1 + - name: PC2SO + description: PC2 Switch Open + bit_offset: 26 + bit_size: 1 + - name: PC3SO + description: PC3 Switch Open + bit_offset: 27 + bit_size: 1 fieldset/UR0: description: SYSCFG user register 0 fields: - - name: BKS - description: Bank Swap - bit_offset: 0 - bit_size: 1 - - name: RDP - description: Readout protection - bit_offset: 16 - bit_size: 8 + - name: BKS + description: Bank Swap + bit_offset: 0 + bit_size: 1 + - name: RDP + description: Readout protection + bit_offset: 16 + bit_size: 8 fieldset/UR10: description: SYSCFG user register 10 fields: - - name: PA_END_2 - description: Protected area end address for bank 2 - bit_offset: 0 - bit_size: 12 - - name: SA_BEG_2 - description: Secured area start address for bank 2 - bit_offset: 16 - bit_size: 12 + - name: PA_END_2 + description: Protected area end address for bank 2 + bit_offset: 0 + bit_size: 12 + - name: SA_BEG_2 + description: Secured area start address for bank 2 + bit_offset: 16 + bit_size: 12 fieldset/UR11: description: SYSCFG user register 11 fields: - - name: SA_END_2 - description: Secured area end address for bank 2 - bit_offset: 0 - bit_size: 12 - - name: IWDG1M - description: Independent Watchdog 1 mode - bit_offset: 16 - bit_size: 1 + - name: SA_END_2 + description: Secured area end address for bank 2 + bit_offset: 0 + bit_size: 12 + - name: IWDG1M + description: Independent Watchdog 1 mode + bit_offset: 16 + bit_size: 1 fieldset/UR12: description: SYSCFG user register 12 fields: - - name: SECURE - description: Secure mode - bit_offset: 16 - bit_size: 1 + - name: SECURE + description: Secure mode + bit_offset: 16 + bit_size: 1 fieldset/UR13: description: SYSCFG user register 13 fields: - - name: SDRS - description: Secured DTCM RAM Size - bit_offset: 0 - bit_size: 2 - - name: D1SBRST - description: D1 Standby reset - bit_offset: 16 - bit_size: 1 + - name: SDRS + description: Secured DTCM RAM Size + bit_offset: 0 + bit_size: 2 + - name: D1SBRST + description: D1 Standby reset + bit_offset: 16 + bit_size: 1 fieldset/UR14: description: SYSCFG user register 14 fields: - - name: D1STPRST - description: D1 Stop Reset - bit_offset: 0 - bit_size: 1 + - name: D1STPRST + description: D1 Stop Reset + bit_offset: 0 + bit_size: 1 fieldset/UR15: description: SYSCFG user register 15 fields: - - name: FZIWDGSTB - description: Freeze independent watchdog in Standby mode - bit_offset: 16 - bit_size: 1 + - name: FZIWDGSTB + description: Freeze independent watchdog in Standby mode + bit_offset: 16 + bit_size: 1 fieldset/UR16: description: SYSCFG user register 16 fields: - - name: FZIWDGSTP - description: Freeze independent watchdog in Stop mode - bit_offset: 0 - bit_size: 1 - - name: PKP - description: Private key programmed - bit_offset: 16 - bit_size: 1 + - name: FZIWDGSTP + description: Freeze independent watchdog in Stop mode + bit_offset: 0 + bit_size: 1 + - name: PKP + description: Private key programmed + bit_offset: 16 + bit_size: 1 fieldset/UR17: description: SYSCFG user register 17 fields: - - name: IO_HSLV - description: I/O high speed / low voltage - bit_offset: 0 - bit_size: 1 + - name: IO_HSLV + description: I/O high speed / low voltage + bit_offset: 0 + bit_size: 1 fieldset/UR2: description: SYSCFG user register 2 fields: - - name: BORH - description: BOR_LVL Brownout Reset Threshold Level - bit_offset: 0 - bit_size: 2 - - name: BOOT_ADD0 - description: Boot Address 0 - bit_offset: 16 - bit_size: 16 + - name: BORH + description: BOR_LVL Brownout Reset Threshold Level + bit_offset: 0 + bit_size: 2 + - name: BOOT_ADD0 + description: Boot Address 0 + bit_offset: 16 + bit_size: 16 fieldset/UR3: description: SYSCFG user register 3 fields: - - name: BOOT_ADD1 - description: Boot Address 1 - bit_offset: 16 - bit_size: 16 + - name: BOOT_ADD1 + description: Boot Address 1 + bit_offset: 16 + bit_size: 16 fieldset/UR4: description: SYSCFG user register 4 fields: - - name: MEPAD_1 - description: Mass Erase Protected Area Disabled for bank 1 - bit_offset: 16 - bit_size: 1 + - name: MEPAD_1 + description: Mass Erase Protected Area Disabled for bank 1 + bit_offset: 16 + bit_size: 1 fieldset/UR5: description: SYSCFG user register 5 fields: - - name: MESAD_1 - description: Mass erase secured area disabled for bank 1 - bit_offset: 0 - bit_size: 1 - - name: WRPN_1 - description: Write protection for flash bank 1 - bit_offset: 16 - bit_size: 8 + - name: MESAD_1 + description: Mass erase secured area disabled for bank 1 + bit_offset: 0 + bit_size: 1 + - name: WRPN_1 + description: Write protection for flash bank 1 + bit_offset: 16 + bit_size: 8 fieldset/UR6: description: SYSCFG user register 6 fields: - - name: PA_BEG_1 - description: Protected area start address for bank 1 - bit_offset: 0 - bit_size: 12 - - name: PA_END_1 - description: Protected area end address for bank 1 - bit_offset: 16 - bit_size: 12 + - name: PA_BEG_1 + description: Protected area start address for bank 1 + bit_offset: 0 + bit_size: 12 + - name: PA_END_1 + description: Protected area end address for bank 1 + bit_offset: 16 + bit_size: 12 fieldset/UR7: description: SYSCFG user register 7 fields: - - name: SA_BEG_1 - description: Secured area start address for bank 1 - bit_offset: 0 - bit_size: 12 - - name: SA_END_1 - description: Secured area end address for bank 1 - bit_offset: 16 - bit_size: 12 + - name: SA_BEG_1 + description: Secured area start address for bank 1 + bit_offset: 0 + bit_size: 12 + - name: SA_END_1 + description: Secured area end address for bank 1 + bit_offset: 16 + bit_size: 12 fieldset/UR8: description: SYSCFG user register 8 fields: - - name: MEPAD_2 - description: Mass erase protected area disabled for bank 2 - bit_offset: 0 - bit_size: 1 - - name: MESAD_2 - description: Mass erase secured area disabled for bank 2 - bit_offset: 16 - bit_size: 1 + - name: MEPAD_2 + description: Mass erase protected area disabled for bank 2 + bit_offset: 0 + bit_size: 1 + - name: MESAD_2 + description: Mass erase secured area disabled for bank 2 + bit_offset: 16 + bit_size: 1 fieldset/UR9: description: SYSCFG user register 9 fields: - - name: WRPN_2 - description: Write protection for flash bank 2 - bit_offset: 0 - bit_size: 8 - - name: PA_BEG_2 - description: Protected area start address for bank 2 - bit_offset: 16 - bit_size: 12 + - name: WRPN_2 + description: Write protection for flash bank 2 + bit_offset: 0 + bit_size: 8 + - name: PA_BEG_2 + description: Protected area start address for bank 2 + bit_offset: 16 + bit_size: 12 diff --git a/data/registers/syscfg_h7od.yaml b/data/registers/syscfg_h7od.yaml new file mode 100644 index 0000000..24f8b08 --- /dev/null +++ b/data/registers/syscfg_h7od.yaml @@ -0,0 +1,409 @@ +block/SYSCFG: + description: System configuration controller + items: + - name: PMCR + description: peripheral mode configuration register + byte_offset: 4 + fieldset: PMCR + - name: EXTICR + description: external interrupt configuration register + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: CCCSR + description: compensation cell control/status register + byte_offset: 32 + fieldset: CCCSR + - name: CCVR + description: SYSCFG compensation cell value register + byte_offset: 36 + access: Read + fieldset: CCVR + - name: CCCR + description: SYSCFG compensation cell code register + byte_offset: 40 + fieldset: CCCR + - name: PWRCR + description: SYSCFG power control register + byte_offset: 44 + fieldset: PWRCR + - name: PKGR + description: SYSCFG package register + byte_offset: 292 + access: Read + fieldset: PKGR + - name: UR0 + description: SYSCFG user register 0 + byte_offset: 768 + access: Read + fieldset: UR0 + - name: UR2 + description: SYSCFG user register 2 + byte_offset: 776 + fieldset: UR2 + - name: UR3 + description: SYSCFG user register 3 + byte_offset: 780 + fieldset: UR3 + - name: UR4 + description: SYSCFG user register 4 + byte_offset: 784 + access: Read + fieldset: UR4 + - name: UR5 + description: SYSCFG user register 5 + byte_offset: 788 + access: Read + fieldset: UR5 + - name: UR6 + description: SYSCFG user register 6 + byte_offset: 792 + access: Read + fieldset: UR6 + - name: UR7 + description: SYSCFG user register 7 + byte_offset: 796 + access: Read + fieldset: UR7 + - name: UR8 + description: SYSCFG user register 8 + byte_offset: 800 + access: Read + fieldset: UR8 + - name: UR9 + description: SYSCFG user register 9 + byte_offset: 804 + access: Read + fieldset: UR9 + - name: UR10 + description: SYSCFG user register 10 + byte_offset: 808 + access: Read + fieldset: UR10 + - name: UR11 + description: SYSCFG user register 11 + byte_offset: 812 + access: Read + fieldset: UR11 + - name: UR12 + description: SYSCFG user register 12 + byte_offset: 816 + access: Read + fieldset: UR12 + - name: UR13 + description: SYSCFG user register 13 + byte_offset: 820 + access: Read + fieldset: UR13 + - name: UR14 + description: SYSCFG user register 14 + byte_offset: 824 + fieldset: UR14 + - name: UR15 + description: SYSCFG user register 15 + byte_offset: 828 + access: Read + fieldset: UR15 + - name: UR16 + description: SYSCFG user register 16 + byte_offset: 832 + access: Read + fieldset: UR16 + - name: UR17 + description: SYSCFG user register 17 + byte_offset: 836 + access: Read + fieldset: UR17 +fieldset/CCCR: + description: SYSCFG compensation cell code register + fields: + - name: NCC + description: NMOS compensation code + bit_offset: 0 + bit_size: 4 + - name: PCC + description: PMOS compensation code + bit_offset: 4 + bit_size: 4 +fieldset/CCCSR: + description: compensation cell control/status register + fields: + - name: EN + description: enable + bit_offset: 0 + bit_size: 1 + - name: CS + description: Code selection + bit_offset: 1 + bit_size: 1 + - name: READY + description: Compensation cell ready flag + bit_offset: 8 + bit_size: 1 + - name: HSLV + description: High-speed at low-voltage + bit_offset: 16 + bit_size: 1 +fieldset/CCVR: + description: SYSCFG compensation cell value register + fields: + - name: NCV + description: NMOS compensation value + bit_offset: 0 + bit_size: 4 + - name: PCV + description: PMOS compensation value + bit_offset: 4 + bit_size: 4 +fieldset/EXTICR: + description: external interrupt configuration register 2 + fields: + - name: EXTI + description: EXTI x configuration (x = 4 to 7) + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 +fieldset/PKGR: + description: SYSCFG package register + fields: + - name: PKG + description: Package + bit_offset: 0 + bit_size: 4 +fieldset/PMCR: + description: peripheral mode configuration register + fields: + - name: I2C1FMP + description: I2C1 Fm+ + bit_offset: 0 + bit_size: 1 + - name: I2C2FMP + description: I2C2 Fm+ + bit_offset: 1 + bit_size: 1 + - name: I2C3FMP + description: I2C3 Fm+ + bit_offset: 2 + bit_size: 1 + - name: I2C4FMP + description: I2C4 Fm+ + bit_offset: 3 + bit_size: 1 + - name: PB6FMP + description: PB(6) Fm+ + bit_offset: 4 + bit_size: 1 + - name: PB7FMP + description: PB(7) Fast Mode Plus + bit_offset: 5 + bit_size: 1 + - name: PB8FMP + description: PB(8) Fast Mode Plus + bit_offset: 6 + bit_size: 1 + - name: PB9FMP + description: PB(9) Fm+ + bit_offset: 7 + bit_size: 1 + - name: BOOSTE + description: Booster Enable + bit_offset: 8 + bit_size: 1 + - name: BOOSTVDDSEL + description: Analog switch supply voltage selection + bit_offset: 9 + bit_size: 1 + - name: EPIS + description: Ethernet PHY Interface Selection + bit_offset: 21 + bit_size: 3 + - name: PA0SO + description: PA0 Switch Open + bit_offset: 24 + bit_size: 1 + - name: PA1SO + description: PA1 Switch Open + bit_offset: 25 + bit_size: 1 + - name: PC2SO + description: PC2 Switch Open + bit_offset: 26 + bit_size: 1 + - name: PC3SO + description: PC3 Switch Open + bit_offset: 27 + bit_size: 1 +fieldset/PWRCR: + description: SYSCFG power control register + fields: + - name: ODEN + description: Overdrive enable + bit_offset: 0 + bit_size: 4 +fieldset/UR0: + description: SYSCFG user register 0 + fields: + - name: BKS + description: Bank Swap + bit_offset: 0 + bit_size: 1 + - name: RDP + description: Readout protection + bit_offset: 16 + bit_size: 8 +fieldset/UR10: + description: SYSCFG user register 10 + fields: + - name: PA_END_2 + description: Protected area end address for bank 2 + bit_offset: 0 + bit_size: 12 + - name: SA_BEG_2 + description: Secured area start address for bank 2 + bit_offset: 16 + bit_size: 12 +fieldset/UR11: + description: SYSCFG user register 11 + fields: + - name: SA_END_2 + description: Secured area end address for bank 2 + bit_offset: 0 + bit_size: 12 + - name: IWDG1M + description: Independent Watchdog 1 mode + bit_offset: 16 + bit_size: 1 +fieldset/UR12: + description: SYSCFG user register 12 + fields: + - name: SECURE + description: Secure mode + bit_offset: 16 + bit_size: 1 +fieldset/UR13: + description: SYSCFG user register 13 + fields: + - name: SDRS + description: Secured DTCM RAM Size + bit_offset: 0 + bit_size: 2 + - name: D1SBRST + description: D1 Standby reset + bit_offset: 16 + bit_size: 1 +fieldset/UR14: + description: SYSCFG user register 14 + fields: + - name: D1STPRST + description: D1 Stop Reset + bit_offset: 0 + bit_size: 1 +fieldset/UR15: + description: SYSCFG user register 15 + fields: + - name: FZIWDGSTB + description: Freeze independent watchdog in Standby mode + bit_offset: 16 + bit_size: 1 +fieldset/UR16: + description: SYSCFG user register 16 + fields: + - name: FZIWDGSTP + description: Freeze independent watchdog in Stop mode + bit_offset: 0 + bit_size: 1 + - name: PKP + description: Private key programmed + bit_offset: 16 + bit_size: 1 +fieldset/UR17: + description: SYSCFG user register 17 + fields: + - name: IO_HSLV + description: I/O high speed / low voltage + bit_offset: 0 + bit_size: 1 +fieldset/UR2: + description: SYSCFG user register 2 + fields: + - name: BORH + description: BOR_LVL Brownout Reset Threshold Level + bit_offset: 0 + bit_size: 2 + - name: BOOT_ADD0 + description: Boot Address 0 + bit_offset: 16 + bit_size: 16 +fieldset/UR3: + description: SYSCFG user register 3 + fields: + - name: BOOT_ADD1 + description: Boot Address 1 + bit_offset: 16 + bit_size: 16 +fieldset/UR4: + description: SYSCFG user register 4 + fields: + - name: MEPAD_1 + description: Mass Erase Protected Area Disabled for bank 1 + bit_offset: 16 + bit_size: 1 +fieldset/UR5: + description: SYSCFG user register 5 + fields: + - name: MESAD_1 + description: Mass erase secured area disabled for bank 1 + bit_offset: 0 + bit_size: 1 + - name: WRPN_1 + description: Write protection for flash bank 1 + bit_offset: 16 + bit_size: 8 +fieldset/UR6: + description: SYSCFG user register 6 + fields: + - name: PA_BEG_1 + description: Protected area start address for bank 1 + bit_offset: 0 + bit_size: 12 + - name: PA_END_1 + description: Protected area end address for bank 1 + bit_offset: 16 + bit_size: 12 +fieldset/UR7: + description: SYSCFG user register 7 + fields: + - name: SA_BEG_1 + description: Secured area start address for bank 1 + bit_offset: 0 + bit_size: 12 + - name: SA_END_1 + description: Secured area end address for bank 1 + bit_offset: 16 + bit_size: 12 +fieldset/UR8: + description: SYSCFG user register 8 + fields: + - name: MEPAD_2 + description: Mass erase protected area disabled for bank 2 + bit_offset: 0 + bit_size: 1 + - name: MESAD_2 + description: Mass erase secured area disabled for bank 2 + bit_offset: 16 + bit_size: 1 +fieldset/UR9: + description: SYSCFG user register 9 + fields: + - name: WRPN_2 + description: Write protection for flash bank 2 + bit_offset: 0 + bit_size: 8 + - name: PA_BEG_2 + description: Protected area start address for bank 2 + bit_offset: 16 + bit_size: 12 diff --git a/data/registers/syscfg_l0.yaml b/data/registers/syscfg_l0.yaml index df80345..ce9db68 100644 --- a/data/registers/syscfg_l0.yaml +++ b/data/registers/syscfg_l0.yaml @@ -1,118 +1,117 @@ ---- block/SYSCFG: description: System configuration controller items: - - name: CFGR1 - description: configuration register 1 - byte_offset: 0 - fieldset: CFGR1 - - name: CFGR2 - description: CFGR2 - byte_offset: 4 - fieldset: CFGR2 - - name: EXTICR - description: external interrupt configuration register - array: - len: 4 - stride: 4 - byte_offset: 8 - fieldset: EXTICR - - name: CFGR3 - description: CFGR3 - byte_offset: 32 - fieldset: CFGR3 + - name: CFGR1 + description: configuration register 1 + byte_offset: 0 + fieldset: CFGR1 + - name: CFGR2 + description: CFGR2 + byte_offset: 4 + fieldset: CFGR2 + - name: EXTICR + description: external interrupt configuration register + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: CFGR3 + description: CFGR3 + byte_offset: 32 + fieldset: CFGR3 fieldset/CFGR1: description: configuration register 1 fields: - - name: MEM_MODE - description: Memory mapping selection bits - bit_offset: 0 - bit_size: 2 - - name: UFB - description: User bank swapping - bit_offset: 3 - bit_size: 1 - - name: BOOT_MODE - description: Boot mode selected by the boot pins status bits - bit_offset: 8 - bit_size: 2 + - name: MEM_MODE + description: Memory mapping selection bits + bit_offset: 0 + bit_size: 2 + - name: UFB + description: User bank swapping + bit_offset: 3 + bit_size: 1 + - name: BOOT_MODE + description: Boot mode selected by the boot pins status bits + bit_offset: 8 + bit_size: 2 fieldset/CFGR2: description: CFGR2 fields: - - name: FWDIS - description: Firewall disable bit - bit_offset: 0 - bit_size: 1 - - name: I2C_PB6_FMP - description: Fm+ drive capability on PB6 enable bit - bit_offset: 8 - bit_size: 1 - - name: I2C_PB7_FMP - description: Fm+ drive capability on PB7 enable bit - bit_offset: 9 - bit_size: 1 - - name: I2C_PB8_FMP - description: Fm+ drive capability on PB8 enable bit - bit_offset: 10 - bit_size: 1 - - name: I2C_PB9_FMP - description: Fm+ drive capability on PB9 enable bit - bit_offset: 11 - bit_size: 1 - - name: I2C1_FMP - description: I2C1 Fm+ drive capability enable bit - bit_offset: 12 - bit_size: 1 - - name: I2C2_FMP - description: I2C2 Fm+ drive capability enable bit - bit_offset: 13 - bit_size: 1 - - name: I2C3_FMP - description: I2C3 Fm+ drive capability enable bit - bit_offset: 14 - bit_size: 1 + - name: FWDIS + description: Firewall disable bit + bit_offset: 0 + bit_size: 1 + - name: I2C_PB6_FMP + description: Fm+ drive capability on PB6 enable bit + bit_offset: 8 + bit_size: 1 + - name: I2C_PB7_FMP + description: Fm+ drive capability on PB7 enable bit + bit_offset: 9 + bit_size: 1 + - name: I2C_PB8_FMP + description: Fm+ drive capability on PB8 enable bit + bit_offset: 10 + bit_size: 1 + - name: I2C_PB9_FMP + description: Fm+ drive capability on PB9 enable bit + bit_offset: 11 + bit_size: 1 + - name: I2C1_FMP + description: I2C1 Fm+ drive capability enable bit + bit_offset: 12 + bit_size: 1 + - name: I2C2_FMP + description: I2C2 Fm+ drive capability enable bit + bit_offset: 13 + bit_size: 1 + - name: I2C3_FMP + description: I2C3 Fm+ drive capability enable bit + bit_offset: 14 + bit_size: 1 fieldset/CFGR3: description: CFGR3 fields: - - name: EN_VREFINT - description: VREFINT enable and scaler control for COMP2 enable bit - bit_offset: 0 - bit_size: 1 - - name: SEL_VREF_OUT - description: VREFINT_ADC connection bit - bit_offset: 4 - bit_size: 2 - - name: ENBUF_VREFINT_ADC - description: VREFINT reference for ADC enable bit - bit_offset: 8 - bit_size: 1 - - name: ENBUF_SENSOR_ADC - description: Temperature sensor reference for ADC enable bit - bit_offset: 9 - bit_size: 1 - - name: ENBUF_VREFINT_COMP2 - description: VREFINT reference for COMP2 scaler enable bit - bit_offset: 12 - bit_size: 1 - - name: ENREF_HSI48 - description: VREFINT reference for HSI48 oscillator enable bit - bit_offset: 13 - bit_size: 1 - - name: VREFINT_RDYF - description: VREFINT ready flag - bit_offset: 30 - bit_size: 1 - - name: REF_LOCK - description: SYSCFG_CFGR3 lock bit - bit_offset: 31 - bit_size: 1 + - name: EN_VREFINT + description: VREFINT enable and scaler control for COMP2 enable bit + bit_offset: 0 + bit_size: 1 + - name: SEL_VREF_OUT + description: VREFINT_ADC connection bit + bit_offset: 4 + bit_size: 2 + - name: ENBUF_VREFINT_ADC + description: VREFINT reference for ADC enable bit + bit_offset: 8 + bit_size: 1 + - name: ENBUF_SENSOR_ADC + description: Temperature sensor reference for ADC enable bit + bit_offset: 9 + bit_size: 1 + - name: ENBUF_VREFINT_COMP2 + description: VREFINT reference for COMP2 scaler enable bit + bit_offset: 12 + bit_size: 1 + - name: ENREF_HSI48 + description: VREFINT reference for HSI48 oscillator enable bit + bit_offset: 13 + bit_size: 1 + - name: VREFINT_RDYF + description: VREFINT ready flag + bit_offset: 30 + bit_size: 1 + - name: REF_LOCK + description: SYSCFG_CFGR3 lock bit + bit_offset: 31 + bit_size: 1 fieldset/EXTICR: description: external interrupt configuration register 1-4 fields: - - name: EXTI - description: EXTI configuration bits - bit_offset: 0 - bit_size: 4 - array: - len: 4 - stride: 4 + - name: EXTI + description: EXTI configuration bits + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 diff --git a/data/registers/syscfg_l1.yaml b/data/registers/syscfg_l1.yaml index b1dd048..ce9760d 100644 --- a/data/registers/syscfg_l1.yaml +++ b/data/registers/syscfg_l1.yaml @@ -1,51 +1,50 @@ ---- block/SYSCFG: description: System configuration controller items: - - name: MEMRMP - description: memory remap register - byte_offset: 0 - fieldset: MEMRMP - - name: PMC - description: peripheral mode configuration register - byte_offset: 4 - fieldset: PMC - - name: EXTICR - description: external interrupt configuration register 1 - array: - len: 4 - stride: 4 - byte_offset: 8 - fieldset: EXTICR + - name: MEMRMP + description: memory remap register + byte_offset: 0 + fieldset: MEMRMP + - name: PMC + description: peripheral mode configuration register + byte_offset: 4 + fieldset: PMC + - name: EXTICR + description: external interrupt configuration register 1 + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR fieldset/EXTICR: description: external interrupt configuration register 3 fields: - - name: EXTI - description: EXTI x configuration (x = 8 to 11) - bit_offset: 0 - bit_size: 4 - array: - len: 4 - stride: 4 + - name: EXTI + description: EXTI x configuration (x = 8 to 11) + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 fieldset/MEMRMP: description: memory remap register fields: - - name: MEM_MODE - description: MEM_MODE - bit_offset: 0 - bit_size: 2 - - name: BOOT_MODE - description: BOOT_MODE - bit_offset: 8 - bit_size: 2 + - name: MEM_MODE + description: MEM_MODE + bit_offset: 0 + bit_size: 2 + - name: BOOT_MODE + description: BOOT_MODE + bit_offset: 8 + bit_size: 2 fieldset/PMC: description: peripheral mode configuration register fields: - - name: USB_PU - description: USB pull-up - bit_offset: 0 - bit_size: 1 - - name: LCD_CAPA - description: USB pull-up enable on DP line - bit_offset: 1 - bit_size: 5 + - name: USB_PU + description: USB pull-up + bit_offset: 0 + bit_size: 1 + - name: LCD_CAPA + description: USB pull-up enable on DP line + bit_offset: 1 + bit_size: 5 diff --git a/data/registers/syscfg_l4.yaml b/data/registers/syscfg_l4.yaml index c9e4ae1..eaa36b6 100644 --- a/data/registers/syscfg_l4.yaml +++ b/data/registers/syscfg_l4.yaml @@ -1,156 +1,155 @@ ---- block/SYSCFG: description: System configuration controller items: - - name: MEMRMP - description: memory remap register - byte_offset: 0 - fieldset: MEMRMP - - name: CFGR1 - description: configuration register 1 - byte_offset: 4 - fieldset: CFGR1 - - name: EXTICR - description: external interrupt configuration register 1 - array: - len: 4 - stride: 4 - byte_offset: 8 - fieldset: EXTICR - - name: SCSR - description: SCSR - byte_offset: 24 - fieldset: SCSR - - name: CFGR2 - description: CFGR2 - byte_offset: 28 - fieldset: CFGR2 - - name: SWPR - description: SWPR - byte_offset: 32 - access: Write - fieldset: SWPR - - name: SKR - description: SKR - byte_offset: 36 - access: Write - fieldset: SKR + - name: MEMRMP + description: memory remap register + byte_offset: 0 + fieldset: MEMRMP + - name: CFGR1 + description: configuration register 1 + byte_offset: 4 + fieldset: CFGR1 + - name: EXTICR + description: external interrupt configuration register 1 + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: SCSR + description: SCSR + byte_offset: 24 + fieldset: SCSR + - name: CFGR2 + description: CFGR2 + byte_offset: 28 + fieldset: CFGR2 + - name: SWPR + description: SWPR + byte_offset: 32 + access: Write + fieldset: SWPR + - name: SKR + description: SKR + byte_offset: 36 + access: Write + fieldset: SKR fieldset/CFGR1: description: configuration register 1 fields: - - name: FWDIS - description: Firewall disable - bit_offset: 0 - bit_size: 1 - - name: BOOSTEN - description: I/O analog switch voltage booster enable - bit_offset: 8 - bit_size: 1 - - name: I2C_PB6_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB6 - bit_offset: 16 - bit_size: 1 - - name: I2C_PB7_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB7 - bit_offset: 17 - bit_size: 1 - - name: I2C_PB8_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB8 - bit_offset: 18 - bit_size: 1 - - name: I2C_PB9_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB9 - bit_offset: 19 - bit_size: 1 - - name: I2C1_FMP - description: I2C1 Fast-mode Plus driving capability activation - bit_offset: 20 - bit_size: 1 - - name: I2C2_FMP - description: I2C2 Fast-mode Plus driving capability activation - bit_offset: 21 - bit_size: 1 - - name: I2C3_FMP - description: I2C3 Fast-mode Plus driving capability activation - bit_offset: 22 - bit_size: 1 - - name: FPU_IE - description: Floating Point Unit interrupts enable bits - bit_offset: 26 - bit_size: 6 + - name: FWDIS + description: Firewall disable + bit_offset: 0 + bit_size: 1 + - name: BOOSTEN + description: I/O analog switch voltage booster enable + bit_offset: 8 + bit_size: 1 + - name: I2C_PB6_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB6 + bit_offset: 16 + bit_size: 1 + - name: I2C_PB7_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB7 + bit_offset: 17 + bit_size: 1 + - name: I2C_PB8_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB8 + bit_offset: 18 + bit_size: 1 + - name: I2C_PB9_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB9 + bit_offset: 19 + bit_size: 1 + - name: I2C1_FMP + description: I2C1 Fast-mode Plus driving capability activation + bit_offset: 20 + bit_size: 1 + - name: I2C2_FMP + description: I2C2 Fast-mode Plus driving capability activation + bit_offset: 21 + bit_size: 1 + - name: I2C3_FMP + description: I2C3 Fast-mode Plus driving capability activation + bit_offset: 22 + bit_size: 1 + - name: FPU_IE + description: Floating Point Unit interrupts enable bits + bit_offset: 26 + bit_size: 6 fieldset/CFGR2: description: CFGR2 fields: - - name: CLL - description: Cortex LOCKUP (Hardfault) output enable bit - bit_offset: 0 - bit_size: 1 - - name: SPL - description: SRAM2 parity lock bit - bit_offset: 1 - bit_size: 1 - - name: PVDL - description: PVD lock enable bit - bit_offset: 2 - bit_size: 1 - - name: ECCL - description: ECC Lock - bit_offset: 3 - bit_size: 1 - - name: SPF - description: SRAM2 parity error flag - bit_offset: 8 - bit_size: 1 + - name: CLL + description: Cortex LOCKUP (Hardfault) output enable bit + bit_offset: 0 + bit_size: 1 + - name: SPL + description: SRAM2 parity lock bit + bit_offset: 1 + bit_size: 1 + - name: PVDL + description: PVD lock enable bit + bit_offset: 2 + bit_size: 1 + - name: ECCL + description: ECC Lock + bit_offset: 3 + bit_size: 1 + - name: SPF + description: SRAM2 parity error flag + bit_offset: 8 + bit_size: 1 fieldset/EXTICR: description: external interrupt configuration register 4 fields: - - name: EXTI - description: EXTI12 configuration bits - bit_offset: 0 - bit_size: 4 - array: - len: 4 - stride: 4 + - name: EXTI + description: EXTI12 configuration bits + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 fieldset/MEMRMP: description: memory remap register fields: - - name: MEM_MODE - description: Memory mapping selection - bit_offset: 0 - bit_size: 3 - - name: QFS - description: QUADSPI memory mapping swap - bit_offset: 3 - bit_size: 1 - - name: FB_MODE - description: Flash Bank mode selection - bit_offset: 8 - bit_size: 1 + - name: MEM_MODE + description: Memory mapping selection + bit_offset: 0 + bit_size: 3 + - name: QFS + description: QUADSPI memory mapping swap + bit_offset: 3 + bit_size: 1 + - name: FB_MODE + description: Flash Bank mode selection + bit_offset: 8 + bit_size: 1 fieldset/SCSR: description: SCSR fields: - - name: SRAM2ER - description: SRAM2 Erase - bit_offset: 0 - bit_size: 1 - - name: SRAM2BSY - description: SRAM2 busy by erase operation - bit_offset: 1 - bit_size: 1 + - name: SRAM2ER + description: SRAM2 Erase + bit_offset: 0 + bit_size: 1 + - name: SRAM2BSY + description: SRAM2 busy by erase operation + bit_offset: 1 + bit_size: 1 fieldset/SKR: description: SKR fields: - - name: KEY - description: SRAM2 write protection key for software erase - bit_offset: 0 - bit_size: 8 + - name: KEY + description: SRAM2 write protection key for software erase + bit_offset: 0 + bit_size: 8 fieldset/SWPR: description: SWPR fields: - - name: PWP - description: SRAWM2 write protection. - bit_offset: 0 - bit_size: 1 - array: - len: 32 - stride: 1 + - name: PWP + description: SRAWM2 write protection. + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 diff --git a/data/registers/syscfg_l5.yaml b/data/registers/syscfg_l5.yaml index 9692d9b..bfceaa1 100644 --- a/data/registers/syscfg_l5.yaml +++ b/data/registers/syscfg_l5.yaml @@ -1,456 +1,455 @@ ---- block/SYSCFG: description: System configuration controller items: - - name: SECCFGR - description: SYSCFG secure configuration register - byte_offset: 0 - fieldset: SECCFGR - - name: CFGR1 - description: configuration register 1 - byte_offset: 4 - fieldset: CFGR1 - - name: FPUIMR - description: FPU interrupt mask register - byte_offset: 8 - fieldset: FPUIMR - - name: CNSLCKR - description: SYSCFG CPU non-secure lock register - byte_offset: 12 - fieldset: CNSLCKR - - name: CSLOCKR - description: SYSCFG CPU secure lock register - byte_offset: 16 - fieldset: CSLOCKR - - name: CFGR2 - description: CFGR2 - byte_offset: 20 - fieldset: CFGR2 - - name: SCSR - description: SCSR - byte_offset: 24 - fieldset: SCSR - - name: SKR - description: SKR - byte_offset: 28 - access: Write - fieldset: SKR - - name: SWPR - description: SWPR - byte_offset: 32 - access: Write - fieldset: SWPR - - name: SWPR2 - description: SWPR2 - byte_offset: 36 - access: Write - fieldset: SWPR2 - - name: RSSCMDR - description: RSSCMDR - byte_offset: 44 - fieldset: RSSCMDR + - name: SECCFGR + description: SYSCFG secure configuration register + byte_offset: 0 + fieldset: SECCFGR + - name: CFGR1 + description: configuration register 1 + byte_offset: 4 + fieldset: CFGR1 + - name: FPUIMR + description: FPU interrupt mask register + byte_offset: 8 + fieldset: FPUIMR + - name: CNSLCKR + description: SYSCFG CPU non-secure lock register + byte_offset: 12 + fieldset: CNSLCKR + - name: CSLOCKR + description: SYSCFG CPU secure lock register + byte_offset: 16 + fieldset: CSLOCKR + - name: CFGR2 + description: CFGR2 + byte_offset: 20 + fieldset: CFGR2 + - name: SCSR + description: SCSR + byte_offset: 24 + fieldset: SCSR + - name: SKR + description: SKR + byte_offset: 28 + access: Write + fieldset: SKR + - name: SWPR + description: SWPR + byte_offset: 32 + access: Write + fieldset: SWPR + - name: SWPR2 + description: SWPR2 + byte_offset: 36 + access: Write + fieldset: SWPR2 + - name: RSSCMDR + description: RSSCMDR + byte_offset: 44 + fieldset: RSSCMDR fieldset/CFGR1: description: configuration register 1 fields: - - name: BOOSTEN - description: I/O analog switch voltage booster enable - bit_offset: 8 - bit_size: 1 - - name: ANASWVDD - description: GPIO analog switch control voltage selection - bit_offset: 9 - bit_size: 1 - - name: I2C_PB6_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB6 - bit_offset: 16 - bit_size: 1 - - name: I2C_PB7_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB7 - bit_offset: 17 - bit_size: 1 - - name: I2C_PB8_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB8 - bit_offset: 18 - bit_size: 1 - - name: I2C_PB9_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB9 - bit_offset: 19 - bit_size: 1 - - name: I2C1_FMP - description: I2C1 Fast-mode Plus driving capability activation - bit_offset: 20 - bit_size: 1 - - name: I2C2_FMP - description: I2C2 Fast-mode Plus driving capability activation - bit_offset: 21 - bit_size: 1 - - name: I2C3_FMP - description: I2C3 Fast-mode Plus driving capability activation - bit_offset: 22 - bit_size: 1 - - name: I2C4_FMP - description: I2C4_FMP - bit_offset: 23 - bit_size: 1 + - name: BOOSTEN + description: I/O analog switch voltage booster enable + bit_offset: 8 + bit_size: 1 + - name: ANASWVDD + description: GPIO analog switch control voltage selection + bit_offset: 9 + bit_size: 1 + - name: I2C_PB6_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB6 + bit_offset: 16 + bit_size: 1 + - name: I2C_PB7_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB7 + bit_offset: 17 + bit_size: 1 + - name: I2C_PB8_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB8 + bit_offset: 18 + bit_size: 1 + - name: I2C_PB9_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB9 + bit_offset: 19 + bit_size: 1 + - name: I2C1_FMP + description: I2C1 Fast-mode Plus driving capability activation + bit_offset: 20 + bit_size: 1 + - name: I2C2_FMP + description: I2C2 Fast-mode Plus driving capability activation + bit_offset: 21 + bit_size: 1 + - name: I2C3_FMP + description: I2C3 Fast-mode Plus driving capability activation + bit_offset: 22 + bit_size: 1 + - name: I2C4_FMP + description: I2C4_FMP + bit_offset: 23 + bit_size: 1 fieldset/CFGR2: description: CFGR2 fields: - - name: CLL - description: LOCKUP (hardfault) output enable bit - bit_offset: 0 - bit_size: 1 - - name: SPL - description: SRAM2 parity lock bit - bit_offset: 1 - bit_size: 1 - - name: PVDL - description: PVD lock enable bit - bit_offset: 2 - bit_size: 1 - - name: ECCL - description: ECC Lock - bit_offset: 3 - bit_size: 1 - - name: SPF - description: SRAM2 parity error flag - bit_offset: 8 - bit_size: 1 + - name: CLL + description: LOCKUP (hardfault) output enable bit + bit_offset: 0 + bit_size: 1 + - name: SPL + description: SRAM2 parity lock bit + bit_offset: 1 + bit_size: 1 + - name: PVDL + description: PVD lock enable bit + bit_offset: 2 + bit_size: 1 + - name: ECCL + description: ECC Lock + bit_offset: 3 + bit_size: 1 + - name: SPF + description: SRAM2 parity error flag + bit_offset: 8 + bit_size: 1 fieldset/CNSLCKR: description: SYSCFG CPU non-secure lock register fields: - - name: LOCKNSVTOR - description: VTOR_NS register lock - bit_offset: 0 - bit_size: 1 - - name: LOCKNSMPU - description: Non-secure MPU registers lock - bit_offset: 1 - bit_size: 1 + - name: LOCKNSVTOR + description: VTOR_NS register lock + bit_offset: 0 + bit_size: 1 + - name: LOCKNSMPU + description: Non-secure MPU registers lock + bit_offset: 1 + bit_size: 1 fieldset/CSLOCKR: description: SYSCFG CPU secure lock register fields: - - name: LOCKSVTAIRCR - description: LOCKSVTAIRCR - bit_offset: 0 - bit_size: 1 - - name: LOCKSMPU - description: LOCKSMPU - bit_offset: 1 - bit_size: 1 - - name: LOCKSAU - description: LOCKSAU - bit_offset: 2 - bit_size: 1 + - name: LOCKSVTAIRCR + description: LOCKSVTAIRCR + bit_offset: 0 + bit_size: 1 + - name: LOCKSMPU + description: LOCKSMPU + bit_offset: 1 + bit_size: 1 + - name: LOCKSAU + description: LOCKSAU + bit_offset: 2 + bit_size: 1 fieldset/FPUIMR: description: FPU interrupt mask register fields: - - name: FPU_IE - description: Floating point unit interrupts enable bits - bit_offset: 0 - bit_size: 6 + - name: FPU_IE + description: Floating point unit interrupts enable bits + bit_offset: 0 + bit_size: 6 fieldset/RSSCMDR: description: RSSCMDR fields: - - name: RSSCMD - description: RSS commands - bit_offset: 0 - bit_size: 8 + - name: RSSCMD + description: RSS commands + bit_offset: 0 + bit_size: 8 fieldset/SCSR: description: SCSR fields: - - name: SRAM2ER - description: SRAM2 Erase - bit_offset: 0 - bit_size: 1 - - name: SRAM2BSY - description: SRAM2 busy by erase operation - bit_offset: 1 - bit_size: 1 + - name: SRAM2ER + description: SRAM2 Erase + bit_offset: 0 + bit_size: 1 + - name: SRAM2BSY + description: SRAM2 busy by erase operation + bit_offset: 1 + bit_size: 1 fieldset/SECCFGR: description: SYSCFG secure configuration register fields: - - name: SYSCFGSEC - description: SYSCFG clock control security - bit_offset: 0 - bit_size: 1 - - name: CLASSBSEC - description: ClassB security - bit_offset: 1 - bit_size: 1 - - name: SRAM2SEC - description: SRAM2 security - bit_offset: 2 - bit_size: 1 - - name: FPUSEC - description: FPUSEC - bit_offset: 3 - bit_size: 1 + - name: SYSCFGSEC + description: SYSCFG clock control security + bit_offset: 0 + bit_size: 1 + - name: CLASSBSEC + description: ClassB security + bit_offset: 1 + bit_size: 1 + - name: SRAM2SEC + description: SRAM2 security + bit_offset: 2 + bit_size: 1 + - name: FPUSEC + description: FPUSEC + bit_offset: 3 + bit_size: 1 fieldset/SKR: description: SKR fields: - - name: KEY - description: SRAM2 write protection key for software erase - bit_offset: 0 - bit_size: 8 + - name: KEY + description: SRAM2 write protection key for software erase + bit_offset: 0 + bit_size: 8 fieldset/SWPR: description: SWPR fields: - - name: P0WP - description: P0WP - bit_offset: 0 - bit_size: 1 - - name: P1WP - description: P1WP - bit_offset: 1 - bit_size: 1 - - name: P2WP - description: P2WP - bit_offset: 2 - bit_size: 1 - - name: P3WP - description: P3WP - bit_offset: 3 - bit_size: 1 - - name: P4WP - description: P4WP - bit_offset: 4 - bit_size: 1 - - name: P5WP - description: P5WP - bit_offset: 5 - bit_size: 1 - - name: P6WP - description: P6WP - bit_offset: 6 - bit_size: 1 - - name: P7WP - description: P7WP - bit_offset: 7 - bit_size: 1 - - name: P8WP - description: P8WP - bit_offset: 8 - bit_size: 1 - - name: P9WP - description: P9WP - bit_offset: 9 - bit_size: 1 - - name: P10WP - description: P10WP - bit_offset: 10 - bit_size: 1 - - name: P11WP - description: P11WP - bit_offset: 11 - bit_size: 1 - - name: P12WP - description: P12WP - bit_offset: 12 - bit_size: 1 - - name: P13WP - description: P13WP - bit_offset: 13 - bit_size: 1 - - name: P14WP - description: P14WP - bit_offset: 14 - bit_size: 1 - - name: P15WP - description: P15WP - bit_offset: 15 - bit_size: 1 - - name: P16WP - description: P16WP - bit_offset: 16 - bit_size: 1 - - name: P17WP - description: P17WP - bit_offset: 17 - bit_size: 1 - - name: P18WP - description: P18WP - bit_offset: 18 - bit_size: 1 - - name: P19WP - description: P19WP - bit_offset: 19 - bit_size: 1 - - name: P20WP - description: P20WP - bit_offset: 20 - bit_size: 1 - - name: P21WP - description: P21WP - bit_offset: 21 - bit_size: 1 - - name: P22WP - description: P22WP - bit_offset: 22 - bit_size: 1 - - name: P23WP - description: P23WP - bit_offset: 23 - bit_size: 1 - - name: P24WP - description: P24WP - bit_offset: 24 - bit_size: 1 - - name: P25WP - description: P25WP - bit_offset: 25 - bit_size: 1 - - name: P26WP - description: P26WP - bit_offset: 26 - bit_size: 1 - - name: P27WP - description: P27WP - bit_offset: 27 - bit_size: 1 - - name: P28WP - description: P28WP - bit_offset: 28 - bit_size: 1 - - name: P29WP - description: P29WP - bit_offset: 29 - bit_size: 1 - - name: P30WP - description: P30WP - bit_offset: 30 - bit_size: 1 - - name: P31WP - description: SRAM2 page 31 write protection - bit_offset: 31 - bit_size: 1 + - name: P0WP + description: P0WP + bit_offset: 0 + bit_size: 1 + - name: P1WP + description: P1WP + bit_offset: 1 + bit_size: 1 + - name: P2WP + description: P2WP + bit_offset: 2 + bit_size: 1 + - name: P3WP + description: P3WP + bit_offset: 3 + bit_size: 1 + - name: P4WP + description: P4WP + bit_offset: 4 + bit_size: 1 + - name: P5WP + description: P5WP + bit_offset: 5 + bit_size: 1 + - name: P6WP + description: P6WP + bit_offset: 6 + bit_size: 1 + - name: P7WP + description: P7WP + bit_offset: 7 + bit_size: 1 + - name: P8WP + description: P8WP + bit_offset: 8 + bit_size: 1 + - name: P9WP + description: P9WP + bit_offset: 9 + bit_size: 1 + - name: P10WP + description: P10WP + bit_offset: 10 + bit_size: 1 + - name: P11WP + description: P11WP + bit_offset: 11 + bit_size: 1 + - name: P12WP + description: P12WP + bit_offset: 12 + bit_size: 1 + - name: P13WP + description: P13WP + bit_offset: 13 + bit_size: 1 + - name: P14WP + description: P14WP + bit_offset: 14 + bit_size: 1 + - name: P15WP + description: P15WP + bit_offset: 15 + bit_size: 1 + - name: P16WP + description: P16WP + bit_offset: 16 + bit_size: 1 + - name: P17WP + description: P17WP + bit_offset: 17 + bit_size: 1 + - name: P18WP + description: P18WP + bit_offset: 18 + bit_size: 1 + - name: P19WP + description: P19WP + bit_offset: 19 + bit_size: 1 + - name: P20WP + description: P20WP + bit_offset: 20 + bit_size: 1 + - name: P21WP + description: P21WP + bit_offset: 21 + bit_size: 1 + - name: P22WP + description: P22WP + bit_offset: 22 + bit_size: 1 + - name: P23WP + description: P23WP + bit_offset: 23 + bit_size: 1 + - name: P24WP + description: P24WP + bit_offset: 24 + bit_size: 1 + - name: P25WP + description: P25WP + bit_offset: 25 + bit_size: 1 + - name: P26WP + description: P26WP + bit_offset: 26 + bit_size: 1 + - name: P27WP + description: P27WP + bit_offset: 27 + bit_size: 1 + - name: P28WP + description: P28WP + bit_offset: 28 + bit_size: 1 + - name: P29WP + description: P29WP + bit_offset: 29 + bit_size: 1 + - name: P30WP + description: P30WP + bit_offset: 30 + bit_size: 1 + - name: P31WP + description: SRAM2 page 31 write protection + bit_offset: 31 + bit_size: 1 fieldset/SWPR2: description: SWPR2 fields: - - name: P32WP - description: P32WP - bit_offset: 0 - bit_size: 1 - - name: P33WP - description: P33WP - bit_offset: 1 - bit_size: 1 - - name: P34WP - description: P34WP - bit_offset: 2 - bit_size: 1 - - name: P35WP - description: P35WP - bit_offset: 3 - bit_size: 1 - - name: P36WP - description: P36WP - bit_offset: 4 - bit_size: 1 - - name: P37WP - description: P37WP - bit_offset: 5 - bit_size: 1 - - name: P38WP - description: P38WP - bit_offset: 6 - bit_size: 1 - - name: P39WP - description: P39WP - bit_offset: 7 - bit_size: 1 - - name: P40WP - description: P40WP - bit_offset: 8 - bit_size: 1 - - name: P41WP - description: P41WP - bit_offset: 9 - bit_size: 1 - - name: P42WP - description: P42WP - bit_offset: 10 - bit_size: 1 - - name: P43WP - description: P43WP - bit_offset: 11 - bit_size: 1 - - name: P44WP - description: P44WP - bit_offset: 12 - bit_size: 1 - - name: P45WP - description: P45WP - bit_offset: 13 - bit_size: 1 - - name: P46WP - description: P46WP - bit_offset: 14 - bit_size: 1 - - name: P47WP - description: P47WP - bit_offset: 15 - bit_size: 1 - - name: P48WP - description: P48WP - bit_offset: 16 - bit_size: 1 - - name: P49WP - description: P49WP - bit_offset: 17 - bit_size: 1 - - name: P50WP - description: P50WP - bit_offset: 18 - bit_size: 1 - - name: P51WP - description: P51WP - bit_offset: 19 - bit_size: 1 - - name: P52WP - description: P52WP - bit_offset: 20 - bit_size: 1 - - name: P53WP - description: P53WP - bit_offset: 21 - bit_size: 1 - - name: P54WP - description: P54WP - bit_offset: 22 - bit_size: 1 - - name: P55WP - description: P55WP - bit_offset: 23 - bit_size: 1 - - name: P56WP - description: P56WP - bit_offset: 24 - bit_size: 1 - - name: P57WP - description: P57WP - bit_offset: 25 - bit_size: 1 - - name: P58WP - description: P58WP - bit_offset: 26 - bit_size: 1 - - name: P59WP - description: P59WP - bit_offset: 27 - bit_size: 1 - - name: P60WP - description: P60WP - bit_offset: 28 - bit_size: 1 - - name: P61WP - description: P61WP - bit_offset: 29 - bit_size: 1 - - name: P62WP - description: P62WP - bit_offset: 30 - bit_size: 1 - - name: P63WP - description: P63WP - bit_offset: 31 - bit_size: 1 + - name: P32WP + description: P32WP + bit_offset: 0 + bit_size: 1 + - name: P33WP + description: P33WP + bit_offset: 1 + bit_size: 1 + - name: P34WP + description: P34WP + bit_offset: 2 + bit_size: 1 + - name: P35WP + description: P35WP + bit_offset: 3 + bit_size: 1 + - name: P36WP + description: P36WP + bit_offset: 4 + bit_size: 1 + - name: P37WP + description: P37WP + bit_offset: 5 + bit_size: 1 + - name: P38WP + description: P38WP + bit_offset: 6 + bit_size: 1 + - name: P39WP + description: P39WP + bit_offset: 7 + bit_size: 1 + - name: P40WP + description: P40WP + bit_offset: 8 + bit_size: 1 + - name: P41WP + description: P41WP + bit_offset: 9 + bit_size: 1 + - name: P42WP + description: P42WP + bit_offset: 10 + bit_size: 1 + - name: P43WP + description: P43WP + bit_offset: 11 + bit_size: 1 + - name: P44WP + description: P44WP + bit_offset: 12 + bit_size: 1 + - name: P45WP + description: P45WP + bit_offset: 13 + bit_size: 1 + - name: P46WP + description: P46WP + bit_offset: 14 + bit_size: 1 + - name: P47WP + description: P47WP + bit_offset: 15 + bit_size: 1 + - name: P48WP + description: P48WP + bit_offset: 16 + bit_size: 1 + - name: P49WP + description: P49WP + bit_offset: 17 + bit_size: 1 + - name: P50WP + description: P50WP + bit_offset: 18 + bit_size: 1 + - name: P51WP + description: P51WP + bit_offset: 19 + bit_size: 1 + - name: P52WP + description: P52WP + bit_offset: 20 + bit_size: 1 + - name: P53WP + description: P53WP + bit_offset: 21 + bit_size: 1 + - name: P54WP + description: P54WP + bit_offset: 22 + bit_size: 1 + - name: P55WP + description: P55WP + bit_offset: 23 + bit_size: 1 + - name: P56WP + description: P56WP + bit_offset: 24 + bit_size: 1 + - name: P57WP + description: P57WP + bit_offset: 25 + bit_size: 1 + - name: P58WP + description: P58WP + bit_offset: 26 + bit_size: 1 + - name: P59WP + description: P59WP + bit_offset: 27 + bit_size: 1 + - name: P60WP + description: P60WP + bit_offset: 28 + bit_size: 1 + - name: P61WP + description: P61WP + bit_offset: 29 + bit_size: 1 + - name: P62WP + description: P62WP + bit_offset: 30 + bit_size: 1 + - name: P63WP + description: P63WP + bit_offset: 31 + bit_size: 1 diff --git a/data/registers/syscfg_u5.yaml b/data/registers/syscfg_u5.yaml index a3402e9..c5cdf3e 100644 --- a/data/registers/syscfg_u5.yaml +++ b/data/registers/syscfg_u5.yaml @@ -1,241 +1,240 @@ ---- block/SYSCFG: description: System configuration controller items: - - name: SECCFGR - description: "SYSCFG secure configuration\r register" - byte_offset: 0 - fieldset: SECCFGR - - name: CFGR1 - description: configuration register 1 - byte_offset: 4 - fieldset: CFGR1 - - name: FPUIMR - description: FPU interrupt mask register - byte_offset: 8 - fieldset: FPUIMR - - name: CNSLCKR - description: "SYSCFG CPU non-secure lock\r register" - byte_offset: 12 - fieldset: CNSLCKR - - name: CSLOCKR - description: "SYSCFG CPU secure lock\r register" - byte_offset: 16 - fieldset: CSLOCKR - - name: CFGR2 - description: configuration register 2 - byte_offset: 20 - fieldset: CFGR2 - - name: MESR - description: memory erase status register - byte_offset: 24 - fieldset: MESR - - name: CCCSR - description: compensation cell control/status register - byte_offset: 28 - fieldset: CCCSR - - name: CCVR - description: compensation cell value register - byte_offset: 32 - access: Read - fieldset: CCVR - - name: CCCR - description: compensation cell code register - byte_offset: 36 - fieldset: CCCR - - name: RSSCMDR - description: RSS command register - byte_offset: 44 - fieldset: RSSCMDR - - name: UCPDR - description: USB Type C and Power Delivery register - byte_offset: 112 - fieldset: UCPDR + - name: SECCFGR + description: "SYSCFG secure configuration\r register" + byte_offset: 0 + fieldset: SECCFGR + - name: CFGR1 + description: configuration register 1 + byte_offset: 4 + fieldset: CFGR1 + - name: FPUIMR + description: FPU interrupt mask register + byte_offset: 8 + fieldset: FPUIMR + - name: CNSLCKR + description: "SYSCFG CPU non-secure lock\r register" + byte_offset: 12 + fieldset: CNSLCKR + - name: CSLOCKR + description: "SYSCFG CPU secure lock\r register" + byte_offset: 16 + fieldset: CSLOCKR + - name: CFGR2 + description: configuration register 2 + byte_offset: 20 + fieldset: CFGR2 + - name: MESR + description: memory erase status register + byte_offset: 24 + fieldset: MESR + - name: CCCSR + description: compensation cell control/status register + byte_offset: 28 + fieldset: CCCSR + - name: CCVR + description: compensation cell value register + byte_offset: 32 + access: Read + fieldset: CCVR + - name: CCCR + description: compensation cell code register + byte_offset: 36 + fieldset: CCCR + - name: RSSCMDR + description: RSS command register + byte_offset: 44 + fieldset: RSSCMDR + - name: UCPDR + description: USB Type C and Power Delivery register + byte_offset: 112 + fieldset: UCPDR fieldset/CCCR: description: compensation cell code register fields: - - name: NCC1 - description: NCC1 - bit_offset: 0 - bit_size: 4 - - name: PCC1 - description: PCC1 - bit_offset: 4 - bit_size: 4 - - name: NCC2 - description: NCC2 - bit_offset: 8 - bit_size: 4 - - name: PCC2 - description: PCC2 - bit_offset: 12 - bit_size: 4 + - name: NCC1 + description: NCC1 + bit_offset: 0 + bit_size: 4 + - name: PCC1 + description: PCC1 + bit_offset: 4 + bit_size: 4 + - name: NCC2 + description: NCC2 + bit_offset: 8 + bit_size: 4 + - name: PCC2 + description: PCC2 + bit_offset: 12 + bit_size: 4 fieldset/CCCSR: description: compensation cell control/status register fields: - - name: EN1 - description: EN1 - bit_offset: 0 - bit_size: 1 - - name: CS1 - description: CS1 - bit_offset: 1 - bit_size: 1 - - name: EN2 - description: EN2 - bit_offset: 2 - bit_size: 1 - - name: CS2 - description: CS2 - bit_offset: 3 - bit_size: 1 - - name: RDY1 - description: RDY1 - bit_offset: 8 - bit_size: 1 - - name: RDY2 - description: RDY2 - bit_offset: 9 - bit_size: 1 + - name: EN1 + description: EN1 + bit_offset: 0 + bit_size: 1 + - name: CS1 + description: CS1 + bit_offset: 1 + bit_size: 1 + - name: EN2 + description: EN2 + bit_offset: 2 + bit_size: 1 + - name: CS2 + description: CS2 + bit_offset: 3 + bit_size: 1 + - name: RDY1 + description: RDY1 + bit_offset: 8 + bit_size: 1 + - name: RDY2 + description: RDY2 + bit_offset: 9 + bit_size: 1 fieldset/CCVR: description: compensation cell value register fields: - - name: NCV1 - description: NCV1 - bit_offset: 0 - bit_size: 4 - - name: PCV1 - description: PCV1 - bit_offset: 4 - bit_size: 4 - - name: NCV2 - description: NCV2 - bit_offset: 8 - bit_size: 4 - - name: PCV2 - description: PCV2 - bit_offset: 12 - bit_size: 4 + - name: NCV1 + description: NCV1 + bit_offset: 0 + bit_size: 4 + - name: PCV1 + description: PCV1 + bit_offset: 4 + bit_size: 4 + - name: NCV2 + description: NCV2 + bit_offset: 8 + bit_size: 4 + - name: PCV2 + description: PCV2 + bit_offset: 12 + bit_size: 4 fieldset/CFGR1: description: configuration register 1 fields: - - name: BOOSTEN - description: "I/O analog switch voltage booster\r enable" - bit_offset: 8 - bit_size: 1 - - name: ANASWVDD - description: "GPIO analog switch control voltage\r selection" - bit_offset: 9 - bit_size: 1 - - name: PB6_FMP - description: PB6_FMP - bit_offset: 16 - bit_size: 1 - - name: PB7_FMP - description: PB7_FMP - bit_offset: 17 - bit_size: 1 - - name: PB8_FMP - description: PB8_FMP - bit_offset: 18 - bit_size: 1 - - name: PB9_FMP - description: PB9_FMP - bit_offset: 19 - bit_size: 1 + - name: BOOSTEN + description: "I/O analog switch voltage booster\r enable" + bit_offset: 8 + bit_size: 1 + - name: ANASWVDD + description: "GPIO analog switch control voltage\r selection" + bit_offset: 9 + bit_size: 1 + - name: PB6_FMP + description: PB6_FMP + bit_offset: 16 + bit_size: 1 + - name: PB7_FMP + description: PB7_FMP + bit_offset: 17 + bit_size: 1 + - name: PB8_FMP + description: PB8_FMP + bit_offset: 18 + bit_size: 1 + - name: PB9_FMP + description: PB9_FMP + bit_offset: 19 + bit_size: 1 fieldset/CFGR2: description: configuration register 2 fields: - - name: CLL - description: "LOCKUP (hardfault) output enable\r bit" - bit_offset: 0 - bit_size: 1 - - name: SPL - description: SRAM ECC lock bit - bit_offset: 1 - bit_size: 1 - - name: PVDL - description: PVD lock enable bit - bit_offset: 2 - bit_size: 1 - - name: ECCL - description: ECC Lock - bit_offset: 3 - bit_size: 1 + - name: CLL + description: "LOCKUP (hardfault) output enable\r bit" + bit_offset: 0 + bit_size: 1 + - name: SPL + description: SRAM ECC lock bit + bit_offset: 1 + bit_size: 1 + - name: PVDL + description: PVD lock enable bit + bit_offset: 2 + bit_size: 1 + - name: ECCL + description: ECC Lock + bit_offset: 3 + bit_size: 1 fieldset/CNSLCKR: description: "SYSCFG CPU non-secure lock\r register" fields: - - name: LOCKNSVTOR - description: VTOR_NS register lock - bit_offset: 0 - bit_size: 1 - - name: LOCKNSMPU - description: "Non-secure MPU registers\r lock" - bit_offset: 1 - bit_size: 1 + - name: LOCKNSVTOR + description: VTOR_NS register lock + bit_offset: 0 + bit_size: 1 + - name: LOCKNSMPU + description: "Non-secure MPU registers\r lock" + bit_offset: 1 + bit_size: 1 fieldset/CSLOCKR: description: "SYSCFG CPU secure lock\r register" fields: - - name: LOCKSVTAIRCR - description: LOCKSVTAIRCR - bit_offset: 0 - bit_size: 1 - - name: LOCKSMPU - description: LOCKSMPU - bit_offset: 1 - bit_size: 1 - - name: LOCKSAU - description: LOCKSAU - bit_offset: 2 - bit_size: 1 + - name: LOCKSVTAIRCR + description: LOCKSVTAIRCR + bit_offset: 0 + bit_size: 1 + - name: LOCKSMPU + description: LOCKSMPU + bit_offset: 1 + bit_size: 1 + - name: LOCKSAU + description: LOCKSAU + bit_offset: 2 + bit_size: 1 fieldset/FPUIMR: description: FPU interrupt mask register fields: - - name: FPU_IE - description: "Floating point unit interrupts enable\r bits" - bit_offset: 0 - bit_size: 6 + - name: FPU_IE + description: "Floating point unit interrupts enable\r bits" + bit_offset: 0 + bit_size: 6 fieldset/MESR: description: memory erase status register fields: - - name: MCLR - description: MCLR - bit_offset: 0 - bit_size: 1 - - name: IPMEE - description: IPMEE - bit_offset: 16 - bit_size: 1 + - name: MCLR + description: MCLR + bit_offset: 0 + bit_size: 1 + - name: IPMEE + description: IPMEE + bit_offset: 16 + bit_size: 1 fieldset/RSSCMDR: description: RSS command register fields: - - name: RSSCMD - description: RSS commands - bit_offset: 0 - bit_size: 16 + - name: RSSCMD + description: RSS commands + bit_offset: 0 + bit_size: 16 fieldset/SECCFGR: description: "SYSCFG secure configuration\r register" fields: - - name: SYSCFGSEC - description: "SYSCFG clock control\r security" - bit_offset: 0 - bit_size: 1 - - name: CLASSBSEC - description: CLASSBSEC - bit_offset: 1 - bit_size: 1 - - name: FPUSEC - description: FPUSEC - bit_offset: 3 - bit_size: 1 + - name: SYSCFGSEC + description: "SYSCFG clock control\r security" + bit_offset: 0 + bit_size: 1 + - name: CLASSBSEC + description: CLASSBSEC + bit_offset: 1 + bit_size: 1 + - name: FPUSEC + description: FPUSEC + bit_offset: 3 + bit_size: 1 fieldset/UCPDR: description: USB Type C and Power Delivery register fields: - - name: CC1ENRXFILTER - description: CC1ENRXFILTER - bit_offset: 0 - bit_size: 1 - - name: CC2ENRXFILTER - description: CC2ENRXFILTER - bit_offset: 1 - bit_size: 1 + - name: CC1ENRXFILTER + description: CC1ENRXFILTER + bit_offset: 0 + bit_size: 1 + - name: CC2ENRXFILTER + description: CC2ENRXFILTER + bit_offset: 1 + bit_size: 1 diff --git a/data/registers/syscfg_wb.yaml b/data/registers/syscfg_wb.yaml index 788fa92..bf05209 100644 --- a/data/registers/syscfg_wb.yaml +++ b/data/registers/syscfg_wb.yaml @@ -1,397 +1,396 @@ ---- block/SYSCFG: description: System configuration controller items: - - name: MEMRMP - description: memory remap register - byte_offset: 0 - fieldset: MEMRMP - - name: CFGR1 - description: configuration register 1 - byte_offset: 4 - fieldset: CFGR1 - - name: EXTICR - description: external interrupt configuration register 1 - array: - len: 4 - stride: 4 - byte_offset: 8 - fieldset: EXTICR - - name: SCSR - description: SCSR - byte_offset: 24 - fieldset: SCSR - - name: CFGR2 - description: CFGR2 - byte_offset: 28 - fieldset: CFGR2 - - name: SWPR - description: SRAM2 write protection register - byte_offset: 32 - access: Write - fieldset: SWPR - - name: SKR - description: SKR - byte_offset: 36 - access: Write - fieldset: SKR - - name: SWPR2 - description: SRAM2 write protection register 2 - byte_offset: 40 - access: Write - fieldset: SWPR2 - - name: IMR1 - description: CPU1 interrupt mask register 1 - byte_offset: 256 - fieldset: IMR1 - - name: IMR2 - description: CPU1 interrupt mask register 2 - byte_offset: 260 - fieldset: IMR2 - - name: C2IMR1 - description: CPU2 interrupt mask register 1 - byte_offset: 264 - fieldset: C2IMR1 - - name: C2IMR2 - description: CPU2 interrupt mask register 1 - byte_offset: 268 - fieldset: C2IMR2 - - name: SIPCR - description: secure IP control register - byte_offset: 272 - fieldset: SIPCR + - name: MEMRMP + description: memory remap register + byte_offset: 0 + fieldset: MEMRMP + - name: CFGR1 + description: configuration register 1 + byte_offset: 4 + fieldset: CFGR1 + - name: EXTICR + description: external interrupt configuration register 1 + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: SCSR + description: SCSR + byte_offset: 24 + fieldset: SCSR + - name: CFGR2 + description: CFGR2 + byte_offset: 28 + fieldset: CFGR2 + - name: SWPR + description: SRAM2 write protection register + byte_offset: 32 + access: Write + fieldset: SWPR + - name: SKR + description: SKR + byte_offset: 36 + access: Write + fieldset: SKR + - name: SWPR2 + description: SRAM2 write protection register 2 + byte_offset: 40 + access: Write + fieldset: SWPR2 + - name: IMR1 + description: CPU1 interrupt mask register 1 + byte_offset: 256 + fieldset: IMR1 + - name: IMR2 + description: CPU1 interrupt mask register 2 + byte_offset: 260 + fieldset: IMR2 + - name: C2IMR1 + description: CPU2 interrupt mask register 1 + byte_offset: 264 + fieldset: C2IMR1 + - name: C2IMR2 + description: CPU2 interrupt mask register 1 + byte_offset: 268 + fieldset: C2IMR2 + - name: SIPCR + description: secure IP control register + byte_offset: 272 + fieldset: SIPCR fieldset/C2IMR1: description: CPU2 interrupt mask register 1 fields: - - name: RTCSTAMP - description: Peripheral RTCSTAMP interrupt mask to CPU2 - bit_offset: 0 - bit_size: 1 - - name: RTCWKUP - description: Peripheral RTCWKUP interrupt mask to CPU2 - bit_offset: 3 - bit_size: 1 - - name: RTCALARM - description: Peripheral RTCALARM interrupt mask to CPU2 - bit_offset: 4 - bit_size: 1 - - name: RCC - description: Peripheral RCC interrupt mask to CPU2 - bit_offset: 5 - bit_size: 1 - - name: FLASH - description: Peripheral FLASH interrupt mask to CPU2 - bit_offset: 6 - bit_size: 1 - - name: PKA - description: Peripheral PKA interrupt mask to CPU2 - bit_offset: 8 - bit_size: 1 - - name: RNG - description: Peripheral RNG interrupt mask to CPU2 - bit_offset: 9 - bit_size: 1 - - name: AES1 - description: Peripheral AES1 interrupt mask to CPU2 - bit_offset: 10 - bit_size: 1 - - name: COMP - description: Peripheral COMP interrupt mask to CPU2 - bit_offset: 11 - bit_size: 1 - - name: ADC - description: Peripheral ADC interrupt mask to CPU2 - bit_offset: 12 - bit_size: 1 + - name: RTCSTAMP + description: Peripheral RTCSTAMP interrupt mask to CPU2 + bit_offset: 0 + bit_size: 1 + - name: RTCWKUP + description: Peripheral RTCWKUP interrupt mask to CPU2 + bit_offset: 3 + bit_size: 1 + - name: RTCALARM + description: Peripheral RTCALARM interrupt mask to CPU2 + bit_offset: 4 + bit_size: 1 + - name: RCC + description: Peripheral RCC interrupt mask to CPU2 + bit_offset: 5 + bit_size: 1 + - name: FLASH + description: Peripheral FLASH interrupt mask to CPU2 + bit_offset: 6 + bit_size: 1 + - name: PKA + description: Peripheral PKA interrupt mask to CPU2 + bit_offset: 8 + bit_size: 1 + - name: RNG + description: Peripheral RNG interrupt mask to CPU2 + bit_offset: 9 + bit_size: 1 + - name: AES1 + description: Peripheral AES1 interrupt mask to CPU2 + bit_offset: 10 + bit_size: 1 + - name: COMP + description: Peripheral COMP interrupt mask to CPU2 + bit_offset: 11 + bit_size: 1 + - name: ADC + description: Peripheral ADC interrupt mask to CPU2 + bit_offset: 12 + bit_size: 1 fieldset/C2IMR2: description: CPU2 interrupt mask register 1 fields: - - name: DMA1_CH1_IM - description: Peripheral DMA1 CH1 interrupt mask to CPU2 - bit_offset: 0 - bit_size: 1 - - name: DMA1_CH2_IM - description: Peripheral DMA1 CH2 interrupt mask to CPU2 - bit_offset: 1 - bit_size: 1 - - name: DMA1_CH3_IM - description: Peripheral DMA1 CH3 interrupt mask to CPU2 - bit_offset: 2 - bit_size: 1 - - name: DMA1_CH4_IM - description: Peripheral DMA1 CH4 interrupt mask to CPU2 - bit_offset: 3 - bit_size: 1 - - name: DMA1_CH5_IM - description: Peripheral DMA1 CH5 interrupt mask to CPU2 - bit_offset: 4 - bit_size: 1 - - name: DMA1_CH6_IM - description: Peripheral DMA1 CH6 interrupt mask to CPU2 - bit_offset: 5 - bit_size: 1 - - name: DMA1_CH7_IM - description: Peripheral DMA1 CH7 interrupt mask to CPU2 - bit_offset: 6 - bit_size: 1 - - name: DMA2_CH1_IM - description: Peripheral DMA2 CH1 interrupt mask to CPU1 - bit_offset: 8 - bit_size: 1 - - name: DMA2_CH2_IM - description: Peripheral DMA2 CH2 interrupt mask to CPU1 - bit_offset: 9 - bit_size: 1 - - name: DMA2_CH3_IM - description: Peripheral DMA2 CH3 interrupt mask to CPU1 - bit_offset: 10 - bit_size: 1 - - name: DMA2_CH4_IM - description: Peripheral DMA2 CH4 interrupt mask to CPU1 - bit_offset: 11 - bit_size: 1 - - name: DMA2_CH5_IM - description: Peripheral DMA2 CH5 interrupt mask to CPU1 - bit_offset: 12 - bit_size: 1 - - name: DMA2_CH6_IM - description: Peripheral DMA2 CH6 interrupt mask to CPU1 - bit_offset: 13 - bit_size: 1 - - name: DMA2_CH7_IM - description: Peripheral DMA2 CH7 interrupt mask to CPU1 - bit_offset: 14 - bit_size: 1 - - name: DMAM_UX1_IM - description: Peripheral DMAM UX1 interrupt mask to CPU1 - bit_offset: 15 - bit_size: 1 - - name: PVM1IM - description: Peripheral PVM1IM interrupt mask to CPU1 - bit_offset: 16 - bit_size: 1 - - name: PVM3IM - description: Peripheral PVM3IM interrupt mask to CPU1 - bit_offset: 18 - bit_size: 1 - - name: PVDIM - description: Peripheral PVDIM interrupt mask to CPU1 - bit_offset: 20 - bit_size: 1 - - name: TSCIM - description: Peripheral TSCIM interrupt mask to CPU1 - bit_offset: 21 - bit_size: 1 - - name: LCDIM - description: Peripheral LCDIM interrupt mask to CPU1 - bit_offset: 22 - bit_size: 1 + - name: DMA1_CH1_IM + description: Peripheral DMA1 CH1 interrupt mask to CPU2 + bit_offset: 0 + bit_size: 1 + - name: DMA1_CH2_IM + description: Peripheral DMA1 CH2 interrupt mask to CPU2 + bit_offset: 1 + bit_size: 1 + - name: DMA1_CH3_IM + description: Peripheral DMA1 CH3 interrupt mask to CPU2 + bit_offset: 2 + bit_size: 1 + - name: DMA1_CH4_IM + description: Peripheral DMA1 CH4 interrupt mask to CPU2 + bit_offset: 3 + bit_size: 1 + - name: DMA1_CH5_IM + description: Peripheral DMA1 CH5 interrupt mask to CPU2 + bit_offset: 4 + bit_size: 1 + - name: DMA1_CH6_IM + description: Peripheral DMA1 CH6 interrupt mask to CPU2 + bit_offset: 5 + bit_size: 1 + - name: DMA1_CH7_IM + description: Peripheral DMA1 CH7 interrupt mask to CPU2 + bit_offset: 6 + bit_size: 1 + - name: DMA2_CH1_IM + description: Peripheral DMA2 CH1 interrupt mask to CPU1 + bit_offset: 8 + bit_size: 1 + - name: DMA2_CH2_IM + description: Peripheral DMA2 CH2 interrupt mask to CPU1 + bit_offset: 9 + bit_size: 1 + - name: DMA2_CH3_IM + description: Peripheral DMA2 CH3 interrupt mask to CPU1 + bit_offset: 10 + bit_size: 1 + - name: DMA2_CH4_IM + description: Peripheral DMA2 CH4 interrupt mask to CPU1 + bit_offset: 11 + bit_size: 1 + - name: DMA2_CH5_IM + description: Peripheral DMA2 CH5 interrupt mask to CPU1 + bit_offset: 12 + bit_size: 1 + - name: DMA2_CH6_IM + description: Peripheral DMA2 CH6 interrupt mask to CPU1 + bit_offset: 13 + bit_size: 1 + - name: DMA2_CH7_IM + description: Peripheral DMA2 CH7 interrupt mask to CPU1 + bit_offset: 14 + bit_size: 1 + - name: DMAM_UX1_IM + description: Peripheral DMAM UX1 interrupt mask to CPU1 + bit_offset: 15 + bit_size: 1 + - name: PVM1IM + description: Peripheral PVM1IM interrupt mask to CPU1 + bit_offset: 16 + bit_size: 1 + - name: PVM3IM + description: Peripheral PVM3IM interrupt mask to CPU1 + bit_offset: 18 + bit_size: 1 + - name: PVDIM + description: Peripheral PVDIM interrupt mask to CPU1 + bit_offset: 20 + bit_size: 1 + - name: TSCIM + description: Peripheral TSCIM interrupt mask to CPU1 + bit_offset: 21 + bit_size: 1 + - name: LCDIM + description: Peripheral LCDIM interrupt mask to CPU1 + bit_offset: 22 + bit_size: 1 fieldset/CFGR1: description: configuration register 1 fields: - - name: BOOSTEN - description: I/O analog switch voltage booster enable - bit_offset: 8 - bit_size: 1 - - name: I2C_PB6_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB6 - bit_offset: 16 - bit_size: 1 - - name: I2C_PB7_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB7 - bit_offset: 17 - bit_size: 1 - - name: I2C_PB8_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB8 - bit_offset: 18 - bit_size: 1 - - name: I2C_PB9_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB9 - bit_offset: 19 - bit_size: 1 - - name: I2C1_FMP - description: I2C1 Fast-mode Plus driving capability activation - bit_offset: 20 - bit_size: 1 - - name: I2C3_FMP - description: I2C3 Fast-mode Plus driving capability activation - bit_offset: 22 - bit_size: 1 - - name: FPU_IE - description: Floating Point Unit interrupts enable bits - bit_offset: 26 - bit_size: 6 + - name: BOOSTEN + description: I/O analog switch voltage booster enable + bit_offset: 8 + bit_size: 1 + - name: I2C_PB6_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB6 + bit_offset: 16 + bit_size: 1 + - name: I2C_PB7_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB7 + bit_offset: 17 + bit_size: 1 + - name: I2C_PB8_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB8 + bit_offset: 18 + bit_size: 1 + - name: I2C_PB9_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB9 + bit_offset: 19 + bit_size: 1 + - name: I2C1_FMP + description: I2C1 Fast-mode Plus driving capability activation + bit_offset: 20 + bit_size: 1 + - name: I2C3_FMP + description: I2C3 Fast-mode Plus driving capability activation + bit_offset: 22 + bit_size: 1 + - name: FPU_IE + description: Floating Point Unit interrupts enable bits + bit_offset: 26 + bit_size: 6 fieldset/CFGR2: description: CFGR2 fields: - - name: CLL - description: Cortex-M4 LOCKUP (Hardfault) output enable bit - bit_offset: 0 - bit_size: 1 - - name: SPL - description: SRAM2 parity lock bit - bit_offset: 1 - bit_size: 1 - - name: PVDL - description: PVD lock enable bit - bit_offset: 2 - bit_size: 1 - - name: ECCL - description: ECC Lock - bit_offset: 3 - bit_size: 1 - - name: SPF - description: SRAM2 parity error flag - bit_offset: 8 - bit_size: 1 + - name: CLL + description: Cortex-M4 LOCKUP (Hardfault) output enable bit + bit_offset: 0 + bit_size: 1 + - name: SPL + description: SRAM2 parity lock bit + bit_offset: 1 + bit_size: 1 + - name: PVDL + description: PVD lock enable bit + bit_offset: 2 + bit_size: 1 + - name: ECCL + description: ECC Lock + bit_offset: 3 + bit_size: 1 + - name: SPF + description: SRAM2 parity error flag + bit_offset: 8 + bit_size: 1 fieldset/EXTICR: description: external interrupt configuration register 1 fields: - - name: EXTI - description: EXTI 0 configuration bits - bit_offset: 0 - bit_size: 3 - array: - len: 4 - stride: 4 + - name: EXTI + description: EXTI 0 configuration bits + bit_offset: 0 + bit_size: 3 + array: + len: 4 + stride: 4 fieldset/IMR1: description: CPU1 interrupt mask register 1 fields: - - name: TIM1IM - description: Peripheral TIM1 interrupt mask to CPU1 - bit_offset: 13 - bit_size: 1 - - name: TIM16IM - description: Peripheral TIM16 interrupt mask to CPU1 - bit_offset: 14 - bit_size: 1 - - name: TIM17IM - description: Peripheral TIM17 interrupt mask to CPU1 - bit_offset: 15 - bit_size: 1 - - name: EXIT5IM - description: Peripheral EXIT5 interrupt mask to CPU1 - bit_offset: 21 - bit_size: 1 - - name: EXIT6IM - description: Peripheral EXIT6 interrupt mask to CPU1 - bit_offset: 22 - bit_size: 1 - - name: EXIT7IM - description: Peripheral EXIT7 interrupt mask to CPU1 - bit_offset: 23 - bit_size: 1 - - name: EXIT8IM - description: Peripheral EXIT8 interrupt mask to CPU1 - bit_offset: 24 - bit_size: 1 - - name: EXIT9IM - description: Peripheral EXIT9 interrupt mask to CPU1 - bit_offset: 25 - bit_size: 1 - - name: EXIT10IM - description: Peripheral EXIT10 interrupt mask to CPU1 - bit_offset: 26 - bit_size: 1 - - name: EXIT11IM - description: Peripheral EXIT11 interrupt mask to CPU1 - bit_offset: 27 - bit_size: 1 - - name: EXIT12IM - description: Peripheral EXIT12 interrupt mask to CPU1 - bit_offset: 28 - bit_size: 1 - - name: EXIT13IM - description: Peripheral EXIT13 interrupt mask to CPU1 - bit_offset: 29 - bit_size: 1 - - name: EXIT14IM - description: Peripheral EXIT14 interrupt mask to CPU1 - bit_offset: 30 - bit_size: 1 - - name: EXIT15IM - description: Peripheral EXIT15 interrupt mask to CPU1 - bit_offset: 31 - bit_size: 1 + - name: TIM1IM + description: Peripheral TIM1 interrupt mask to CPU1 + bit_offset: 13 + bit_size: 1 + - name: TIM16IM + description: Peripheral TIM16 interrupt mask to CPU1 + bit_offset: 14 + bit_size: 1 + - name: TIM17IM + description: Peripheral TIM17 interrupt mask to CPU1 + bit_offset: 15 + bit_size: 1 + - name: EXIT5IM + description: Peripheral EXIT5 interrupt mask to CPU1 + bit_offset: 21 + bit_size: 1 + - name: EXIT6IM + description: Peripheral EXIT6 interrupt mask to CPU1 + bit_offset: 22 + bit_size: 1 + - name: EXIT7IM + description: Peripheral EXIT7 interrupt mask to CPU1 + bit_offset: 23 + bit_size: 1 + - name: EXIT8IM + description: Peripheral EXIT8 interrupt mask to CPU1 + bit_offset: 24 + bit_size: 1 + - name: EXIT9IM + description: Peripheral EXIT9 interrupt mask to CPU1 + bit_offset: 25 + bit_size: 1 + - name: EXIT10IM + description: Peripheral EXIT10 interrupt mask to CPU1 + bit_offset: 26 + bit_size: 1 + - name: EXIT11IM + description: Peripheral EXIT11 interrupt mask to CPU1 + bit_offset: 27 + bit_size: 1 + - name: EXIT12IM + description: Peripheral EXIT12 interrupt mask to CPU1 + bit_offset: 28 + bit_size: 1 + - name: EXIT13IM + description: Peripheral EXIT13 interrupt mask to CPU1 + bit_offset: 29 + bit_size: 1 + - name: EXIT14IM + description: Peripheral EXIT14 interrupt mask to CPU1 + bit_offset: 30 + bit_size: 1 + - name: EXIT15IM + description: Peripheral EXIT15 interrupt mask to CPU1 + bit_offset: 31 + bit_size: 1 fieldset/IMR2: description: CPU1 interrupt mask register 2 fields: - - name: PVM1IM - description: Peripheral PVM1 interrupt mask to CPU1 - bit_offset: 16 - bit_size: 1 - - name: PVM3IM - description: Peripheral PVM3 interrupt mask to CPU1 - bit_offset: 18 - bit_size: 1 - - name: PVDIM - description: Peripheral PVD interrupt mask to CPU1 - bit_offset: 20 - bit_size: 1 + - name: PVM1IM + description: Peripheral PVM1 interrupt mask to CPU1 + bit_offset: 16 + bit_size: 1 + - name: PVM3IM + description: Peripheral PVM3 interrupt mask to CPU1 + bit_offset: 18 + bit_size: 1 + - name: PVDIM + description: Peripheral PVD interrupt mask to CPU1 + bit_offset: 20 + bit_size: 1 fieldset/MEMRMP: description: memory remap register fields: - - name: MEM_MODE - description: Memory mapping selection - bit_offset: 0 - bit_size: 3 + - name: MEM_MODE + description: Memory mapping selection + bit_offset: 0 + bit_size: 3 fieldset/SCSR: description: SCSR fields: - - name: SRAM2ER - description: SRAM2 Erase - bit_offset: 0 - bit_size: 1 - - name: SRAM2BSY - description: SRAM2 busy by erase operation - bit_offset: 1 - bit_size: 1 - - name: C2RFD - description: CPU2 SRAM fetch (execution) disable. - bit_offset: 31 - bit_size: 1 + - name: SRAM2ER + description: SRAM2 Erase + bit_offset: 0 + bit_size: 1 + - name: SRAM2BSY + description: SRAM2 busy by erase operation + bit_offset: 1 + bit_size: 1 + - name: C2RFD + description: CPU2 SRAM fetch (execution) disable. + bit_offset: 31 + bit_size: 1 fieldset/SIPCR: description: secure IP control register fields: - - name: SAES - description: "Enable AES1 KEY[7:0] security." - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: SPKA - description: Enable PKA security - bit_offset: 2 - bit_size: 1 - - name: SRNG - description: Enable True RNG security - bit_offset: 3 - bit_size: 1 + - name: SAES + description: Enable AES1 KEY[7:0] security. + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: SPKA + description: Enable PKA security + bit_offset: 2 + bit_size: 1 + - name: SRNG + description: Enable True RNG security + bit_offset: 3 + bit_size: 1 fieldset/SKR: description: SKR fields: - - name: KEY - description: SRAM2 write protection key for software erase - bit_offset: 0 - bit_size: 8 + - name: KEY + description: SRAM2 write protection key for software erase + bit_offset: 0 + bit_size: 8 fieldset/SWPR: description: SRAM2 write protection register fields: - - name: PWP - description: P0WP - bit_offset: 0 - bit_size: 1 - array: - len: 32 - stride: 1 + - name: PWP + description: P0WP + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 fieldset/SWPR2: description: SRAM2 write protection register 2 fields: - - name: PWP - description: P32WP - bit_offset: 0 - bit_size: 1 - array: - len: 32 - stride: 1 + - name: PWP + description: P32WP + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 diff --git a/data/registers/syscfg_wba.yaml b/data/registers/syscfg_wba.yaml new file mode 100644 index 0000000..9c46714 --- /dev/null +++ b/data/registers/syscfg_wba.yaml @@ -0,0 +1,196 @@ +block/SYSCFG: + description: System configuration controller + items: + - name: SECCFGR + description: secure configuration register + byte_offset: 0 + fieldset: SECCFGR + - name: CFGR1 + description: configuration register 1 + byte_offset: 4 + fieldset: CFGR1 + - name: FPUIMR + description: FPU interrupt mask register + byte_offset: 8 + fieldset: FPUIMR + - name: CNSLCKR + description: CPU non-secure lock register + byte_offset: 12 + fieldset: CNSLCKR + - name: CSLOCKR + description: CPU secure lock register + byte_offset: 16 + fieldset: CSLOCKR + - name: CFGR2 + description: configuration register 2 + byte_offset: 20 + fieldset: CFGR2 + - name: MESR + description: memory erase status register + byte_offset: 24 + fieldset: MESR + - name: CCCSR + description: compensation cell control/status register + byte_offset: 28 + fieldset: CCCSR + - name: CCVR + description: compensation cell value register + byte_offset: 32 + fieldset: CCVR + - name: CCCR + description: compensation cell code register + byte_offset: 36 + fieldset: CCCR + - name: RSSCMDR + description: RSS command register + byte_offset: 44 + fieldset: RSSCMDR +fieldset/CCCR: + description: compensation cell code register + fields: + - name: NCC1 + description: "NMOS compensation code of the I/Os supplied by VDD\r These bits are written by software to define an I/Os compensation cell code for NMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is set." + bit_offset: 0 + bit_size: 4 + - name: PCC1 + description: "PMOS compensation code of the I/Os supplied by VDD\r These bits are written by software to define an I/Os compensation cell code for PMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is set." + bit_offset: 4 + bit_size: 4 +fieldset/CCCSR: + description: compensation cell control/status register + fields: + - name: EN1 + description: "VDD I/Os compensation cell enable\r This bit enables the compensation cell of the I/Os supplied by VDD." + bit_offset: 0 + bit_size: 1 + - name: CS1 + description: "VDD I/Os code selection\r This bit selects the code to be applied for the compensation cell of the I/Os supplied by VDD." + bit_offset: 1 + bit_size: 1 + - name: RDY1 + description: "VDD I/Os compensation cell ready flag\r This bit provides the compensation cell status of the I/Os supplied by VDD.\r Note: The HSI16 clock is required for the compensation cell to work properly. The compensation cell ready bit (RDY1) is not set if the HSI16 clock is not enabled (HSION)." + bit_offset: 8 + bit_size: 1 +fieldset/CCVR: + description: compensation cell value register + fields: + - name: NCV1 + description: "NMOS compensation value of the I/Os supplied by VDD\r This value is provided by the cell and can be used by the CPU to compute an I/Os compensation cell code for NMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is reset." + bit_offset: 0 + bit_size: 4 + - name: PCV1 + description: "PMOS compensation value of the I/Os supplied by VDD\r This value is provided by the cell and can be used by the CPU to compute an I/Os compensation cell code for PMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is reset." + bit_offset: 4 + bit_size: 4 +fieldset/CFGR1: + description: configuration register 1 + fields: + - name: BOOSTEN + description: "I/O analog switch voltage booster enable\r Access can be protected by GTZC_TZSC ADC4SEC.\r Note: Refer to Table�121 for setting." + bit_offset: 8 + bit_size: 1 + - name: ANASWVDD + description: "GPIO analog switch control voltage selection\r Access can be protected by GTZC_TZSC ADC4SEC.\r Note: Refer to Table�121 for setting." + bit_offset: 9 + bit_size: 1 + - name: PA6_FMP + description: "Fast-mode Plus drive capability activation on PA6\r This bit can be read and written only with secure access if PA6 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA6 when PA6 is not used by I2C peripheral. This can be used to dive a LED for instance.\r Access can be protected by GPIOA SEC6." + bit_offset: 16 + bit_size: 1 + - name: PA7_FMP + description: "Fast-mode Plus drive capability activation on PA7\r This bit can be read and written only with secure access if PA7 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA7 when PA7 is not used by I2C peripheral. This can be used to dive a LED for instance.\r Access can be protected by GPIOA SEC7." + bit_offset: 17 + bit_size: 1 + - name: PA15_FMP + description: "Fast-mode Plus drive capability activation on PA15\r This bit can be read and written only with secure access if PA15 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA15 when PA15 is not used by I2C peripheral. This can be used to dive a LED for instance.\r Access can be protected by GPIOA SEC15." + bit_offset: 18 + bit_size: 1 + - name: PB3_FMP + description: "Fast-mode Plus drive capability activation on PB3\r This bit can be read and written only with secure access if PB3 is secure in GPIOB. This bit enables the Fast-mode Plus drive mode for PB3 when PB3 is not used by I2C peripheral. This can be used to dive a LED for instance.\r Access can be protected by GPIOB SEC3." + bit_offset: 19 + bit_size: 1 +fieldset/CFGR2: + description: configuration register 2 + fields: + - name: CLL + description: "Cortex-M33 LOCKUP (hardfault) output enable\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of Cortex-M33 LOCKUP (hardfault) output to TIM1/16/17 break input." + bit_offset: 0 + bit_size: 1 + - name: SPL + description: "SRAM2 parity lock bit\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/16/17 break inputs." + bit_offset: 1 + bit_size: 1 + - name: PVDL + description: "PVD lock enable bit\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/16/17 break input, as well as the PVDE and PVDLS[2:0] in the PWR register." + bit_offset: 2 + bit_size: 1 + - name: ECCL + description: "ECC lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Flash ECC double error signal connection to TIM1/16/17 break input." + bit_offset: 3 + bit_size: 1 +fieldset/CNSLCKR: + description: CPU non-secure lock register + fields: + - name: LOCKNSVTOR + description: "VTOR_NS register lock\r This bit is set by software and cleared only by a system reset." + bit_offset: 0 + bit_size: 1 + - name: LOCKNSMPU + description: "Non-secure MPU registers lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to non-secure MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers." + bit_offset: 1 + bit_size: 1 +fieldset/CSLOCKR: + description: CPU secure lock register + fields: + - name: LOCKSVTAIRCR + description: "VTOR_S register and AIRCR register bits lock\r This bit is set by software and cleared only by a system reset. When set, it disables write access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register." + bit_offset: 0 + bit_size: 1 + - name: LOCKSMPU + description: "Secure MPU registers lock\r This bit is set by software and cleared only by a system reset. When set, it disables write access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers." + bit_offset: 1 + bit_size: 1 + - name: LOCKSAU + description: "SAU registers lock\r This bit is set by software and cleared only by a system reset. When set, it disables write access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers." + bit_offset: 2 + bit_size: 1 +fieldset/FPUIMR: + description: FPU interrupt mask register + fields: + - name: FPU_IE + description: "Floating point unit interrupts enable bits\r FPU_IE[5]: Inexact interrupt enable (interrupt disable at reset)\r FPU_IE[4]: Input abnormal interrupt enable\r FPU_IE[3]: Overflow interrupt enable\r FPU_IE[2]: Underflow interrupt enable\r FPU_IE[1]: Divide-by-zero interrupt enable\r FPU_IE[0]: Invalid operation Interrupt enable" + bit_offset: 0 + bit_size: 6 +fieldset/MESR: + description: memory erase status register + fields: + - name: MCLR + description: "Device memories erase status\r This bit is set by hardware when SRAM2, ICACHE, PKA SRAM erase is completed after power-on reset or tamper detection (refer to Section�75: Tamper and backup registers (TAMP) for more details). This bit is not reset by system reset and is cleared by software by writing 1 to it." + bit_offset: 0 + bit_size: 1 + - name: IPMEE + description: "ICACHE and PKA SRAM erase status\r This bit is set by hardware when ICACHE and PKA SRAM erase is completed after potential tamper detection (refer to Section�75: Tamper and backup registers (TAMP) for more details). This bit is cleared by software by writing 1 to it." + bit_offset: 16 + bit_size: 1 +fieldset/RSSCMDR: + description: RSS command register + fields: + - name: RSSCMD + description: "RSS commands\r This field defines a command to be executed by the RSS." + bit_offset: 0 + bit_size: 16 +fieldset/SECCFGR: + description: secure configuration register + fields: + - name: SYSCFGSEC + description: clock control, memory erase status and compensation cell registers security + bit_offset: 0 + bit_size: 1 + - name: CLASSBSEC + description: Class B security + bit_offset: 1 + bit_size: 1 + - name: FPUSEC + description: FPU security + bit_offset: 3 + bit_size: 1 diff --git a/data/registers/syscfg_wl5.yaml b/data/registers/syscfg_wl5.yaml index a104742..0b19615 100644 --- a/data/registers/syscfg_wl5.yaml +++ b/data/registers/syscfg_wl5.yaml @@ -1,418 +1,417 @@ ---- block/SYSCFG: description: System configuration controller items: - - name: MEMRMP - description: memory remap register - byte_offset: 0 - fieldset: MEMRMP - - name: CFGR1 - description: configuration register 1 - byte_offset: 4 - fieldset: CFGR1 - - name: EXTICR - description: external interrupt configuration register 1 - array: - len: 4 - stride: 4 - byte_offset: 8 - fieldset: EXTICR - - name: SCSR - description: SCSR - byte_offset: 24 - fieldset: SCSR - - name: CFGR2 - description: CFGR2 - byte_offset: 28 - fieldset: CFGR2 - - name: SWPR - description: SWPR - byte_offset: 32 - fieldset: SWPR - - name: SKR - description: SKR - byte_offset: 36 - access: Write - fieldset: SKR - - name: IMR1 - description: SYSCFG CPU1 interrupt mask register 1 - byte_offset: 256 - fieldset: IMR1 - - name: IMR2 - description: SYSCFG CPU1 interrupt mask register 2 - byte_offset: 260 - fieldset: IMR2 - - name: C2IMR1 - description: SYSCFG CPU2 interrupt mask register 1 - byte_offset: 264 - fieldset: C2IMR1 - - name: C2IMR2 - description: SYSCFG CPU2 interrupt mask register 2 - byte_offset: 268 - fieldset: C2IMR2 - - name: RFDCR - description: radio debug control register - byte_offset: 520 - fieldset: RFDCR + - name: MEMRMP + description: memory remap register + byte_offset: 0 + fieldset: MEMRMP + - name: CFGR1 + description: configuration register 1 + byte_offset: 4 + fieldset: CFGR1 + - name: EXTICR + description: external interrupt configuration register 1 + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: SCSR + description: SCSR + byte_offset: 24 + fieldset: SCSR + - name: CFGR2 + description: CFGR2 + byte_offset: 28 + fieldset: CFGR2 + - name: SWPR + description: SWPR + byte_offset: 32 + fieldset: SWPR + - name: SKR + description: SKR + byte_offset: 36 + access: Write + fieldset: SKR + - name: IMR1 + description: SYSCFG CPU1 interrupt mask register 1 + byte_offset: 256 + fieldset: IMR1 + - name: IMR2 + description: SYSCFG CPU1 interrupt mask register 2 + byte_offset: 260 + fieldset: IMR2 + - name: C2IMR1 + description: SYSCFG CPU2 interrupt mask register 1 + byte_offset: 264 + fieldset: C2IMR1 + - name: C2IMR2 + description: SYSCFG CPU2 interrupt mask register 2 + byte_offset: 268 + fieldset: C2IMR2 + - name: RFDCR + description: radio debug control register + byte_offset: 520 + fieldset: RFDCR fieldset/C2IMR1: description: SYSCFG CPU2 interrupt mask register 1 fields: - - name: RTCSTAMPTAMPLSECSSIM - description: RTCSTAMPTAMPLSECSSIM - bit_offset: 0 - bit_size: 1 - - name: RTCALARMIM - description: RTCALARMIM - bit_offset: 1 - bit_size: 1 - - name: RTCSSRUIM - description: RTCSSRUIM - bit_offset: 2 - bit_size: 1 - - name: RTCWKUPIM - description: RTCWKUPIM - bit_offset: 3 - bit_size: 1 - - name: RCCIM - description: RCCIM - bit_offset: 5 - bit_size: 1 - - name: FLASHIM - description: FLASHIM - bit_offset: 6 - bit_size: 1 - - name: PKAIM - description: PKAIM - bit_offset: 8 - bit_size: 1 - - name: AESIM - description: AESIM - bit_offset: 10 - bit_size: 1 - - name: COMPIM - description: COMPIM - bit_offset: 11 - bit_size: 1 - - name: ADCIM - description: ADCIM - bit_offset: 12 - bit_size: 1 - - name: DACIM - description: DACIM - bit_offset: 13 - bit_size: 1 - - name: EXTI0IM - description: EXTI0IM - bit_offset: 16 - bit_size: 1 - - name: EXTI1IM - description: EXTI1IM - bit_offset: 17 - bit_size: 1 - - name: EXTI2IM - description: EXTI2IM - bit_offset: 18 - bit_size: 1 - - name: EXTI3IM - description: EXTI3IM - bit_offset: 19 - bit_size: 1 - - name: EXTI4IM - description: EXTI4IM - bit_offset: 20 - bit_size: 1 - - name: EXTI5IM - description: EXTI5IM - bit_offset: 21 - bit_size: 1 - - name: EXTI6IM - description: EXTI6IM - bit_offset: 22 - bit_size: 1 - - name: EXTI7IM - description: EXTI7IM - bit_offset: 23 - bit_size: 1 - - name: EXTI8IM - description: EXTI8IM - bit_offset: 24 - bit_size: 1 - - name: EXTI9IM - description: EXTI9IM - bit_offset: 25 - bit_size: 1 - - name: EXTI10IM - description: EXTI10IM - bit_offset: 26 - bit_size: 1 - - name: EXTI11IM - description: EXTI11IM - bit_offset: 27 - bit_size: 1 - - name: EXTI12IM - description: EXTI12IM - bit_offset: 28 - bit_size: 1 - - name: EXTI13IM - description: EXTI13IM - bit_offset: 29 - bit_size: 1 - - name: EXTI14IM - description: EXTI14IM - bit_offset: 30 - bit_size: 1 - - name: EXTI15IM - description: EXTI15IM - bit_offset: 31 - bit_size: 1 + - name: RTCSTAMPTAMPLSECSSIM + description: RTCSTAMPTAMPLSECSSIM + bit_offset: 0 + bit_size: 1 + - name: RTCALARMIM + description: RTCALARMIM + bit_offset: 1 + bit_size: 1 + - name: RTCSSRUIM + description: RTCSSRUIM + bit_offset: 2 + bit_size: 1 + - name: RTCWKUPIM + description: RTCWKUPIM + bit_offset: 3 + bit_size: 1 + - name: RCCIM + description: RCCIM + bit_offset: 5 + bit_size: 1 + - name: FLASHIM + description: FLASHIM + bit_offset: 6 + bit_size: 1 + - name: PKAIM + description: PKAIM + bit_offset: 8 + bit_size: 1 + - name: AESIM + description: AESIM + bit_offset: 10 + bit_size: 1 + - name: COMPIM + description: COMPIM + bit_offset: 11 + bit_size: 1 + - name: ADCIM + description: ADCIM + bit_offset: 12 + bit_size: 1 + - name: DACIM + description: DACIM + bit_offset: 13 + bit_size: 1 + - name: EXTI0IM + description: EXTI0IM + bit_offset: 16 + bit_size: 1 + - name: EXTI1IM + description: EXTI1IM + bit_offset: 17 + bit_size: 1 + - name: EXTI2IM + description: EXTI2IM + bit_offset: 18 + bit_size: 1 + - name: EXTI3IM + description: EXTI3IM + bit_offset: 19 + bit_size: 1 + - name: EXTI4IM + description: EXTI4IM + bit_offset: 20 + bit_size: 1 + - name: EXTI5IM + description: EXTI5IM + bit_offset: 21 + bit_size: 1 + - name: EXTI6IM + description: EXTI6IM + bit_offset: 22 + bit_size: 1 + - name: EXTI7IM + description: EXTI7IM + bit_offset: 23 + bit_size: 1 + - name: EXTI8IM + description: EXTI8IM + bit_offset: 24 + bit_size: 1 + - name: EXTI9IM + description: EXTI9IM + bit_offset: 25 + bit_size: 1 + - name: EXTI10IM + description: EXTI10IM + bit_offset: 26 + bit_size: 1 + - name: EXTI11IM + description: EXTI11IM + bit_offset: 27 + bit_size: 1 + - name: EXTI12IM + description: EXTI12IM + bit_offset: 28 + bit_size: 1 + - name: EXTI13IM + description: EXTI13IM + bit_offset: 29 + bit_size: 1 + - name: EXTI14IM + description: EXTI14IM + bit_offset: 30 + bit_size: 1 + - name: EXTI15IM + description: EXTI15IM + bit_offset: 31 + bit_size: 1 fieldset/C2IMR2: description: SYSCFG CPU2 interrupt mask register 2 fields: - - name: DMA1CH1IM - description: DMA1CH1IM - bit_offset: 0 - bit_size: 1 - - name: DMA1CH2IM - description: DMA1CH2IM - bit_offset: 1 - bit_size: 1 - - name: DMA1CH3IM - description: DMA1CH3IM - bit_offset: 2 - bit_size: 1 - - name: DMA1CH4IM - description: DMA1CH4IM - bit_offset: 3 - bit_size: 1 - - name: DMA1CH5IM - description: DMA1CH5IM - bit_offset: 4 - bit_size: 1 - - name: DMA1CH6IM - description: DMA1CH6IM - bit_offset: 5 - bit_size: 1 - - name: DMA1CH7IM - description: DMA1CH7IM - bit_offset: 6 - bit_size: 1 - - name: DMA2CH1IM - description: DMA2CH1IM - bit_offset: 8 - bit_size: 1 - - name: DMA2CH2IM - description: DMA2CH2IM - bit_offset: 9 - bit_size: 1 - - name: DMA2CH3IM - description: DMA2CH3IM - bit_offset: 10 - bit_size: 1 - - name: DMA2CH4IM - description: DMA2CH4IM - bit_offset: 11 - bit_size: 1 - - name: DMA2CH5IM - description: DMA2CH5IM - bit_offset: 12 - bit_size: 1 - - name: DMA2CH6IM - description: DMA2CH6IM - bit_offset: 13 - bit_size: 1 - - name: DMA2CH7IM - description: DMA2CH7IM - bit_offset: 14 - bit_size: 1 - - name: DMAMUX1IM - description: DMAMUX1IM - bit_offset: 15 - bit_size: 1 - - name: PVM3IM - description: PVM3IM - bit_offset: 18 - bit_size: 1 - - name: PVDIM - description: PVDIM - bit_offset: 20 - bit_size: 1 + - name: DMA1CH1IM + description: DMA1CH1IM + bit_offset: 0 + bit_size: 1 + - name: DMA1CH2IM + description: DMA1CH2IM + bit_offset: 1 + bit_size: 1 + - name: DMA1CH3IM + description: DMA1CH3IM + bit_offset: 2 + bit_size: 1 + - name: DMA1CH4IM + description: DMA1CH4IM + bit_offset: 3 + bit_size: 1 + - name: DMA1CH5IM + description: DMA1CH5IM + bit_offset: 4 + bit_size: 1 + - name: DMA1CH6IM + description: DMA1CH6IM + bit_offset: 5 + bit_size: 1 + - name: DMA1CH7IM + description: DMA1CH7IM + bit_offset: 6 + bit_size: 1 + - name: DMA2CH1IM + description: DMA2CH1IM + bit_offset: 8 + bit_size: 1 + - name: DMA2CH2IM + description: DMA2CH2IM + bit_offset: 9 + bit_size: 1 + - name: DMA2CH3IM + description: DMA2CH3IM + bit_offset: 10 + bit_size: 1 + - name: DMA2CH4IM + description: DMA2CH4IM + bit_offset: 11 + bit_size: 1 + - name: DMA2CH5IM + description: DMA2CH5IM + bit_offset: 12 + bit_size: 1 + - name: DMA2CH6IM + description: DMA2CH6IM + bit_offset: 13 + bit_size: 1 + - name: DMA2CH7IM + description: DMA2CH7IM + bit_offset: 14 + bit_size: 1 + - name: DMAMUX1IM + description: DMAMUX1IM + bit_offset: 15 + bit_size: 1 + - name: PVM3IM + description: PVM3IM + bit_offset: 18 + bit_size: 1 + - name: PVDIM + description: PVDIM + bit_offset: 20 + bit_size: 1 fieldset/CFGR1: description: configuration register 1 fields: - - name: BOOSTEN - description: I/O analog switch voltage booster enable - bit_offset: 8 - bit_size: 1 - - name: I2C_PB6_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB6 - bit_offset: 16 - bit_size: 1 - - name: I2C_PB7_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB7 - bit_offset: 17 - bit_size: 1 - - name: I2C_PB8_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB8 - bit_offset: 18 - bit_size: 1 - - name: I2C_PB9_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB9 - bit_offset: 19 - bit_size: 1 - - name: I2C1_FMP - description: I2C1 Fast-mode Plus driving capability activation - bit_offset: 20 - bit_size: 1 - - name: I2C2_FMP - description: I2C2 Fast-mode Plus driving capability activation - bit_offset: 21 - bit_size: 1 - - name: I2C3_FMP - description: I2C3 Fast-mode Plus driving capability activation - bit_offset: 22 - bit_size: 1 + - name: BOOSTEN + description: I/O analog switch voltage booster enable + bit_offset: 8 + bit_size: 1 + - name: I2C_PB6_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB6 + bit_offset: 16 + bit_size: 1 + - name: I2C_PB7_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB7 + bit_offset: 17 + bit_size: 1 + - name: I2C_PB8_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB8 + bit_offset: 18 + bit_size: 1 + - name: I2C_PB9_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB9 + bit_offset: 19 + bit_size: 1 + - name: I2C1_FMP + description: I2C1 Fast-mode Plus driving capability activation + bit_offset: 20 + bit_size: 1 + - name: I2C2_FMP + description: I2C2 Fast-mode Plus driving capability activation + bit_offset: 21 + bit_size: 1 + - name: I2C3_FMP + description: I2C3 Fast-mode Plus driving capability activation + bit_offset: 22 + bit_size: 1 fieldset/CFGR2: description: CFGR2 fields: - - name: CLL - description: CPU1 LOCKUP (Hardfault) output enable bit - bit_offset: 0 - bit_size: 1 - - name: SPL - description: SRAM2 parity lock bit - bit_offset: 1 - bit_size: 1 - - name: PVDL - description: PVD lock enable bit - bit_offset: 2 - bit_size: 1 - - name: ECCL - description: ECC Lock - bit_offset: 3 - bit_size: 1 - - name: SPF - description: SRAM2 parity error flag - bit_offset: 8 - bit_size: 1 + - name: CLL + description: CPU1 LOCKUP (Hardfault) output enable bit + bit_offset: 0 + bit_size: 1 + - name: SPL + description: SRAM2 parity lock bit + bit_offset: 1 + bit_size: 1 + - name: PVDL + description: PVD lock enable bit + bit_offset: 2 + bit_size: 1 + - name: ECCL + description: ECC Lock + bit_offset: 3 + bit_size: 1 + - name: SPF + description: SRAM2 parity error flag + bit_offset: 8 + bit_size: 1 fieldset/EXTICR: description: external interrupt configuration register 4 fields: - - name: EXTI - description: EXTI12 configuration bits - bit_offset: 0 - bit_size: 3 - array: - len: 4 - stride: 4 + - name: EXTI + description: EXTI12 configuration bits + bit_offset: 0 + bit_size: 3 + array: + len: 4 + stride: 4 fieldset/IMR1: description: SYSCFG CPU1 interrupt mask register 1 fields: - - name: RTCSTAMPTAMPLSECSSIM - description: RTCSTAMPTAMPLSECSSIM - bit_offset: 0 - bit_size: 1 - - name: RTCSSRUIM - description: RTCSSRUIM - bit_offset: 2 - bit_size: 1 - - name: EXTI5IM - description: EXTI5IM - bit_offset: 21 - bit_size: 1 - - name: EXTI6IM - description: EXTI6IM - bit_offset: 22 - bit_size: 1 - - name: EXTI7IM - description: EXTI7IM - bit_offset: 23 - bit_size: 1 - - name: EXTI8IM - description: EXTI8IM - bit_offset: 24 - bit_size: 1 - - name: EXTI9IM - description: EXTI9IM - bit_offset: 25 - bit_size: 1 - - name: EXTI10IM - description: EXTI10IM - bit_offset: 26 - bit_size: 1 - - name: EXTI11IM - description: EXTI11IM - bit_offset: 27 - bit_size: 1 - - name: EXTI12IM - description: EXTI12IM - bit_offset: 28 - bit_size: 1 - - name: EXTI13IM - description: EXTI13IM - bit_offset: 29 - bit_size: 1 - - name: EXTI14IM - description: EXTI14IM - bit_offset: 30 - bit_size: 1 - - name: EXTI15IM - description: EXTI15IM - bit_offset: 31 - bit_size: 1 + - name: RTCSTAMPTAMPLSECSSIM + description: RTCSTAMPTAMPLSECSSIM + bit_offset: 0 + bit_size: 1 + - name: RTCSSRUIM + description: RTCSSRUIM + bit_offset: 2 + bit_size: 1 + - name: EXTI5IM + description: EXTI5IM + bit_offset: 21 + bit_size: 1 + - name: EXTI6IM + description: EXTI6IM + bit_offset: 22 + bit_size: 1 + - name: EXTI7IM + description: EXTI7IM + bit_offset: 23 + bit_size: 1 + - name: EXTI8IM + description: EXTI8IM + bit_offset: 24 + bit_size: 1 + - name: EXTI9IM + description: EXTI9IM + bit_offset: 25 + bit_size: 1 + - name: EXTI10IM + description: EXTI10IM + bit_offset: 26 + bit_size: 1 + - name: EXTI11IM + description: EXTI11IM + bit_offset: 27 + bit_size: 1 + - name: EXTI12IM + description: EXTI12IM + bit_offset: 28 + bit_size: 1 + - name: EXTI13IM + description: EXTI13IM + bit_offset: 29 + bit_size: 1 + - name: EXTI14IM + description: EXTI14IM + bit_offset: 30 + bit_size: 1 + - name: EXTI15IM + description: EXTI15IM + bit_offset: 31 + bit_size: 1 fieldset/IMR2: description: SYSCFG CPU1 interrupt mask register 2 fields: - - name: PVM3IM - description: PVM3IM - bit_offset: 18 - bit_size: 1 - - name: PVDIM - description: PVDIM - bit_offset: 20 - bit_size: 1 + - name: PVM3IM + description: PVM3IM + bit_offset: 18 + bit_size: 1 + - name: PVDIM + description: PVDIM + bit_offset: 20 + bit_size: 1 fieldset/MEMRMP: description: memory remap register fields: - - name: MEM_MODE - description: Memory mapping selection - bit_offset: 0 - bit_size: 3 + - name: MEM_MODE + description: Memory mapping selection + bit_offset: 0 + bit_size: 3 fieldset/RFDCR: description: radio debug control register fields: - - name: RFTBSEL - description: radio debug test bus selection - bit_offset: 0 - bit_size: 1 + - name: RFTBSEL + description: radio debug test bus selection + bit_offset: 0 + bit_size: 1 fieldset/SCSR: description: SCSR fields: - - name: SRAM2ER - description: SRAM2 erase - bit_offset: 0 - bit_size: 1 - - name: SRAMBSY - description: "SRAM1, SRAM2 and PKA SRAM busy by erase operation" - bit_offset: 1 - bit_size: 1 - - name: PKASRAMBSY - description: PKA SRAM busy by erase operation - bit_offset: 8 - bit_size: 1 + - name: SRAM2ER + description: SRAM2 erase + bit_offset: 0 + bit_size: 1 + - name: SRAMBSY + description: SRAM1, SRAM2 and PKA SRAM busy by erase operation + bit_offset: 1 + bit_size: 1 + - name: PKASRAMBSY + description: PKA SRAM busy by erase operation + bit_offset: 8 + bit_size: 1 fieldset/SKR: description: SKR fields: - - name: KEY - description: SRAM2 write protection key for software erase - bit_offset: 0 - bit_size: 8 + - name: KEY + description: SRAM2 write protection key for software erase + bit_offset: 0 + bit_size: 8 fieldset/SWPR: description: SWPR fields: - - name: PWP - description: SRAM2 1Kbyte page 0 write protection - bit_offset: 0 - bit_size: 1 - array: - len: 32 - stride: 1 + - name: PWP + description: SRAM2 1Kbyte page 0 write protection + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 diff --git a/data/registers/syscfg_wle.yaml b/data/registers/syscfg_wle.yaml index a6d6bf6..6289122 100644 --- a/data/registers/syscfg_wle.yaml +++ b/data/registers/syscfg_wle.yaml @@ -1,154 +1,153 @@ ---- block/SYSCFG: description: System configuration controller items: - - name: MEMRMP - description: memory remap register - byte_offset: 0 - fieldset: MEMRMP - - name: CFGR1 - description: configuration register 1 - byte_offset: 4 - fieldset: CFGR1 - - name: EXTICR - description: external interrupt configuration register 1 - array: - len: 4 - stride: 4 - byte_offset: 8 - fieldset: EXTICR - - name: SCSR - description: SCSR - byte_offset: 24 - fieldset: SCSR - - name: CFGR2 - description: CFGR2 - byte_offset: 28 - fieldset: CFGR2 - - name: SWPR - description: SWPR - byte_offset: 32 - fieldset: SWPR - - name: SKR - description: SKR - byte_offset: 36 - access: Write - fieldset: SKR - - name: RFDCR - description: radio debug control register - byte_offset: 520 - fieldset: RFDCR + - name: MEMRMP + description: memory remap register + byte_offset: 0 + fieldset: MEMRMP + - name: CFGR1 + description: configuration register 1 + byte_offset: 4 + fieldset: CFGR1 + - name: EXTICR + description: external interrupt configuration register 1 + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: SCSR + description: SCSR + byte_offset: 24 + fieldset: SCSR + - name: CFGR2 + description: CFGR2 + byte_offset: 28 + fieldset: CFGR2 + - name: SWPR + description: SWPR + byte_offset: 32 + fieldset: SWPR + - name: SKR + description: SKR + byte_offset: 36 + access: Write + fieldset: SKR + - name: RFDCR + description: radio debug control register + byte_offset: 520 + fieldset: RFDCR fieldset/CFGR1: description: configuration register 1 fields: - - name: BOOSTEN - description: I/O analog switch voltage booster enable - bit_offset: 8 - bit_size: 1 - - name: I2C_PB6_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB6 - bit_offset: 16 - bit_size: 1 - - name: I2C_PB7_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB7 - bit_offset: 17 - bit_size: 1 - - name: I2C_PB8_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB8 - bit_offset: 18 - bit_size: 1 - - name: I2C_PB9_FMP - description: Fast-mode Plus (Fm+) driving capability activation on PB9 - bit_offset: 19 - bit_size: 1 - - name: I2C1_FMP - description: I2C1 Fast-mode Plus driving capability activation - bit_offset: 20 - bit_size: 1 - - name: I2C2_FMP - description: I2C2 Fast-mode Plus driving capability activation - bit_offset: 21 - bit_size: 1 - - name: I2C3_FMP - description: I2C3 Fast-mode Plus driving capability activation - bit_offset: 22 - bit_size: 1 + - name: BOOSTEN + description: I/O analog switch voltage booster enable + bit_offset: 8 + bit_size: 1 + - name: I2C_PB6_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB6 + bit_offset: 16 + bit_size: 1 + - name: I2C_PB7_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB7 + bit_offset: 17 + bit_size: 1 + - name: I2C_PB8_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB8 + bit_offset: 18 + bit_size: 1 + - name: I2C_PB9_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB9 + bit_offset: 19 + bit_size: 1 + - name: I2C1_FMP + description: I2C1 Fast-mode Plus driving capability activation + bit_offset: 20 + bit_size: 1 + - name: I2C2_FMP + description: I2C2 Fast-mode Plus driving capability activation + bit_offset: 21 + bit_size: 1 + - name: I2C3_FMP + description: I2C3 Fast-mode Plus driving capability activation + bit_offset: 22 + bit_size: 1 fieldset/CFGR2: description: CFGR2 fields: - - name: CLL - description: CPU1 LOCKUP (Hardfault) output enable bit - bit_offset: 0 - bit_size: 1 - - name: SPL - description: SRAM2 parity lock bit - bit_offset: 1 - bit_size: 1 - - name: PVDL - description: PVD lock enable bit - bit_offset: 2 - bit_size: 1 - - name: ECCL - description: ECC Lock - bit_offset: 3 - bit_size: 1 - - name: SPF - description: SRAM2 parity error flag - bit_offset: 8 - bit_size: 1 + - name: CLL + description: CPU1 LOCKUP (Hardfault) output enable bit + bit_offset: 0 + bit_size: 1 + - name: SPL + description: SRAM2 parity lock bit + bit_offset: 1 + bit_size: 1 + - name: PVDL + description: PVD lock enable bit + bit_offset: 2 + bit_size: 1 + - name: ECCL + description: ECC Lock + bit_offset: 3 + bit_size: 1 + - name: SPF + description: SRAM2 parity error flag + bit_offset: 8 + bit_size: 1 fieldset/EXTICR: description: external interrupt configuration register 4 fields: - - name: EXTI - description: EXTI12 configuration bits - bit_offset: 0 - bit_size: 3 - array: - len: 4 - stride: 4 + - name: EXTI + description: EXTI12 configuration bits + bit_offset: 0 + bit_size: 3 + array: + len: 4 + stride: 4 fieldset/MEMRMP: description: memory remap register fields: - - name: MEM_MODE - description: Memory mapping selection - bit_offset: 0 - bit_size: 3 + - name: MEM_MODE + description: Memory mapping selection + bit_offset: 0 + bit_size: 3 fieldset/RFDCR: description: radio debug control register fields: - - name: RFTBSEL - description: radio debug test bus selection - bit_offset: 0 - bit_size: 1 + - name: RFTBSEL + description: radio debug test bus selection + bit_offset: 0 + bit_size: 1 fieldset/SCSR: description: SCSR fields: - - name: SRAM2ER - description: SRAM2 erase - bit_offset: 0 - bit_size: 1 - - name: SRAMBSY - description: "SRAM1, SRAM2 and PKA SRAM busy by erase operation" - bit_offset: 1 - bit_size: 1 - - name: PKASRAMBSY - description: PKA SRAM busy by erase operation - bit_offset: 8 - bit_size: 1 + - name: SRAM2ER + description: SRAM2 erase + bit_offset: 0 + bit_size: 1 + - name: SRAMBSY + description: SRAM1, SRAM2 and PKA SRAM busy by erase operation + bit_offset: 1 + bit_size: 1 + - name: PKASRAMBSY + description: PKA SRAM busy by erase operation + bit_offset: 8 + bit_size: 1 fieldset/SKR: description: SKR fields: - - name: KEY - description: SRAM2 write protection key for software erase - bit_offset: 0 - bit_size: 8 + - name: KEY + description: SRAM2 write protection key for software erase + bit_offset: 0 + bit_size: 8 fieldset/SWPR: description: SWPR fields: - - name: PWP - description: SRAM2 1Kbyte page 0 write protection - bit_offset: 0 - bit_size: 1 - array: - len: 32 - stride: 1 + - name: PWP + description: SRAM2 1Kbyte page 0 write protection + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index 595175f..e013ed1 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -1,1026 +1,1025 @@ ---- block/TIM_ADV: extends: TIM_GP16 description: Advanced-timers items: - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2_ADV - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - fieldset: DIER_ADV - - name: SR - description: status register - byte_offset: 16 - fieldset: SR_ADV - - name: EGR - description: event generation register - byte_offset: 20 - access: Write - fieldset: EGR_ADV - - name: CCER - description: capture/compare enable register - byte_offset: 32 - fieldset: CCER_ADV - - name: RCR - description: repetition counter register - byte_offset: 48 - fieldset: RCR - - name: BDTR - description: break and dead-time register - byte_offset: 68 - fieldset: BDTR + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_ADV + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_ADV + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_ADV + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_ADV + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_ADV + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR block/TIM_BASIC: description: Basic timer items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1_BASIC - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2_BASIC - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - fieldset: DIER_BASIC - - name: SR - description: status register - byte_offset: 16 - fieldset: SR_BASIC - - name: EGR - description: event generation register - byte_offset: 20 - access: Write - fieldset: EGR_BASIC - - name: CNT - description: counter - byte_offset: 36 - fieldset: CNT_16 - - name: PSC - description: prescaler - byte_offset: 40 - fieldset: PSC - - name: ARR - description: auto-reload register - byte_offset: 44 - fieldset: ARR_16 + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1_BASIC + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_BASIC + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_BASIC + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_BASIC + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_BASIC + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT_16 + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC + - name: ARR + description: auto-reload register + byte_offset: 44 + fieldset: ARR_16 block/TIM_GP16: extends: TIM_BASIC description: General purpose 16-bit timer items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1_GP - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2_GP - - name: SMCR - description: slave mode control register - byte_offset: 8 - fieldset: SMCR - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - fieldset: DIER_GP - - name: SR - description: status register - byte_offset: 16 - fieldset: SR_GP - - name: EGR - description: event generation register - byte_offset: 20 - access: Write - fieldset: EGR_GP - - name: CCMR_Input - description: capture/compare mode register 1 (input mode) - array: - len: 2 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Input - - name: CCMR_Output - description: capture/compare mode register 1 (output mode) - array: - len: 2 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Output - - name: CCER - description: capture/compare enable register - byte_offset: 32 - fieldset: CCER_GP - - name: PSC - description: prescaler - byte_offset: 40 - fieldset: PSC - - name: CCR - description: capture/compare register - array: - len: 4 - stride: 4 - byte_offset: 52 - fieldset: CCR_16 - - name: DCR - description: DMA control register - byte_offset: 72 - fieldset: DCR - - name: DMAR - description: DMA address for full transfer - byte_offset: 76 - fieldset: DMAR + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1_GP + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_GP + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_GP + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_GP + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_GP + - name: CCMR_Input + description: capture/compare mode register 1 (input mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input + - name: CCMR_Output + description: capture/compare mode register 1 (output mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_GP + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC + - name: CCR + description: capture/compare register + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_16 + - name: DCR + description: DMA control register + byte_offset: 72 + fieldset: DCR + - name: DMAR + description: DMA address for full transfer + byte_offset: 76 + fieldset: DMAR block/TIM_GP32: extends: TIM_GP16 description: General purpose 32-bit timer items: - - name: CNT - description: counter - byte_offset: 36 - fieldset: CNT_32 - - name: ARR - description: auto-reload register - byte_offset: 44 - fieldset: ARR_32 - - name: CCR - description: capture/compare register - array: - len: 4 - stride: 4 - byte_offset: 52 - fieldset: CCR_32 + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT_32 + - name: ARR + description: auto-reload register + byte_offset: 44 + fieldset: ARR_32 + - name: CCR + description: capture/compare register + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_32 fieldset/ARR_16: description: auto-reload register fields: - - name: ARR - description: Auto-reload value - bit_offset: 0 - bit_size: 16 + - name: ARR + description: Auto-reload value + bit_offset: 0 + bit_size: 16 fieldset/ARR_32: description: auto-reload register fields: - - name: ARR - description: Auto-reload value - bit_offset: 0 - bit_size: 32 + - name: ARR + description: Auto-reload value + bit_offset: 0 + bit_size: 32 fieldset/BDTR: description: break and dead-time register fields: - - name: DTG - description: Dead-time generator setup - bit_offset: 0 - bit_size: 8 - - name: LOCK - description: Lock configuration - bit_offset: 8 - bit_size: 2 - - name: OSSI - description: Off-state selection for Idle mode - bit_offset: 10 - bit_size: 1 - enum: OSSI - - name: OSSR - description: Off-state selection for Run mode - bit_offset: 11 - bit_size: 1 - enum: OSSR - - name: BKE - description: Break enable - bit_offset: 12 - bit_size: 1 - - name: BKP - description: Break polarity - bit_offset: 13 - bit_size: 1 - - name: AOE - description: Automatic output enable - bit_offset: 14 - bit_size: 1 - - name: MOE - description: Main output enable - bit_offset: 15 - bit_size: 1 + - name: DTG + description: Dead-time generator setup + bit_offset: 0 + bit_size: 8 + - name: LOCK + description: Lock configuration + bit_offset: 8 + bit_size: 2 + - name: OSSI + description: Off-state selection for Idle mode + bit_offset: 10 + bit_size: 1 + enum: OSSI + - name: OSSR + description: Off-state selection for Run mode + bit_offset: 11 + bit_size: 1 + enum: OSSR + - name: BKE + description: Break enable + bit_offset: 12 + bit_size: 1 + - name: BKP + description: Break polarity + bit_offset: 13 + bit_size: 1 + - name: AOE + description: Automatic output enable + bit_offset: 14 + bit_size: 1 + - name: MOE + description: Main output enable + bit_offset: 15 + bit_size: 1 fieldset/CCER_ADV: extends: CCER_GP description: capture/compare enable register fields: - - name: CCNE - description: Capture/Compare 1 complementary output enable - bit_offset: 2 - bit_size: 1 - array: - len: 4 - stride: 4 + - name: CCNE + description: Capture/Compare 1 complementary output enable + bit_offset: 2 + bit_size: 1 + array: + len: 4 + stride: 4 fieldset/CCER_GP: description: capture/compare enable register fields: - - name: CCE - description: Capture/Compare 1 output enable - bit_offset: 0 - bit_size: 1 - array: - len: 4 - stride: 4 - - name: CCP - description: Capture/Compare 1 output Polarity - bit_offset: 1 - bit_size: 1 - array: - len: 4 - stride: 4 - - name: CCNP - description: Capture/Compare 1 output Polarity - bit_offset: 3 - bit_size: 1 - array: - len: 4 - stride: 4 + - name: CCE + description: Capture/Compare 1 output enable + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 4 + - name: CCP + description: Capture/Compare 1 output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 4 + - name: CCNP + description: Capture/Compare 1 output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 4 + stride: 4 fieldset/CCMR_Input: description: capture/compare mode register 1 (input mode) fields: - - name: CCS - description: Capture/Compare 1 selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Input_CCS - - name: ICPSC - description: Input capture 1 prescaler - bit_offset: 2 - bit_size: 2 - array: - len: 2 - stride: 8 - - name: ICF - description: Input capture 1 filter - bit_offset: 4 - bit_size: 4 - array: - len: 2 - stride: 8 - enum: ICF + - name: CCS + description: Capture/Compare 1 selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture 1 prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 8 + - name: ICF + description: Input capture 1 filter + bit_offset: 4 + bit_size: 4 + array: + len: 2 + stride: 8 + enum: ICF fieldset/CCMR_Output: description: capture/compare mode register 2 (output mode) fields: - - name: CCS - description: Capture/Compare 3 selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Output_CCS - - name: OCFE - description: Output compare 3 fast enable - bit_offset: 2 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCPE - description: Output compare 3 preload enable - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 8 - enum: OCPE - - name: OCM - description: Output compare 3 mode - bit_offset: 4 - bit_size: 3 - array: - len: 2 - stride: 8 - enum: OCM - - name: OCCE - description: Output compare 3 clear enable - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 8 + - name: CCS + description: Capture/Compare 3 selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare 3 fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCPE + description: Output compare 3 preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 8 + enum: OCPE + - name: OCM + description: Output compare 3 mode + bit_offset: 4 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: OCM + - name: OCCE + description: Output compare 3 clear enable + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 8 fieldset/CCR_16: description: capture/compare register 1 fields: - - name: CCR - description: Capture/Compare 1 value - bit_offset: 0 - bit_size: 16 + - name: CCR + description: Capture/Compare 1 value + bit_offset: 0 + bit_size: 16 fieldset/CCR_32: description: capture/compare register 1 fields: - - name: CCR - description: Capture/Compare 1 value - bit_offset: 0 - bit_size: 32 + - name: CCR + description: Capture/Compare 1 value + bit_offset: 0 + bit_size: 32 fieldset/CNT_16: description: counter fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 16 + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 16 fieldset/CNT_32: description: counter fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 32 + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 32 fieldset/CR1_BASIC: description: control register 1 fields: - - name: CEN - description: Counter enable - bit_offset: 0 - bit_size: 1 - - name: UDIS - description: Update disable - bit_offset: 1 - bit_size: 1 - - name: URS - description: Update request source - bit_offset: 2 - bit_size: 1 - enum: URS - - name: OPM - description: One-pulse mode - bit_offset: 3 - bit_size: 1 - enum: OPM - - name: ARPE - description: Auto-reload preload enable - bit_offset: 7 - bit_size: 1 - enum: ARPE + - name: CEN + description: Counter enable + bit_offset: 0 + bit_size: 1 + - name: UDIS + description: Update disable + bit_offset: 1 + bit_size: 1 + - name: URS + description: Update request source + bit_offset: 2 + bit_size: 1 + enum: URS + - name: OPM + description: One-pulse mode + bit_offset: 3 + bit_size: 1 + enum: OPM + - name: ARPE + description: Auto-reload preload enable + bit_offset: 7 + bit_size: 1 + enum: ARPE fieldset/CR1_GP: extends: CR1_BASIC description: control register 1 fields: - - name: DIR - description: Direction - bit_offset: 4 - bit_size: 1 - enum: DIR - - name: CMS - description: Center-aligned mode selection - bit_offset: 5 - bit_size: 2 - enum: CMS - - name: CKD - description: Clock division - bit_offset: 8 - bit_size: 2 - enum: CKD + - name: DIR + description: Direction + bit_offset: 4 + bit_size: 1 + enum: DIR + - name: CMS + description: Center-aligned mode selection + bit_offset: 5 + bit_size: 2 + enum: CMS + - name: CKD + description: Clock division + bit_offset: 8 + bit_size: 2 + enum: CKD fieldset/CR2_ADV: extends: CR2_GP description: control register 2 fields: - - name: CCPC - description: Capture/compare preloaded control - bit_offset: 0 - bit_size: 1 - - name: CCUS - description: Capture/compare control update selection - bit_offset: 2 - bit_size: 1 - - name: OIS - description: Output Idle state 1 - bit_offset: 8 - bit_size: 1 - array: - len: 4 - stride: 2 - - name: OIS1N - description: Output Idle state 1 - bit_offset: 9 - bit_size: 1 - - name: OIS2N - description: Output Idle state 2 - bit_offset: 11 - bit_size: 1 - - name: OIS3N - description: Output Idle state 3 - bit_offset: 13 - bit_size: 1 + - name: CCPC + description: Capture/compare preloaded control + bit_offset: 0 + bit_size: 1 + - name: CCUS + description: Capture/compare control update selection + bit_offset: 2 + bit_size: 1 + - name: OIS + description: Output Idle state 1 + bit_offset: 8 + bit_size: 1 + array: + len: 4 + stride: 2 + - name: OIS1N + description: Output Idle state 1 + bit_offset: 9 + bit_size: 1 + - name: OIS2N + description: Output Idle state 2 + bit_offset: 11 + bit_size: 1 + - name: OIS3N + description: Output Idle state 3 + bit_offset: 13 + bit_size: 1 fieldset/CR2_BASIC: description: control register 2 fields: - - name: MMS - description: Master mode selection - bit_offset: 4 - bit_size: 3 - enum: MMS + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS fieldset/CR2_GP: extends: CR2_BASIC description: control register 2 fields: - - name: CCDS - description: Capture/compare DMA selection - bit_offset: 3 - bit_size: 1 - enum: CCDS - - name: TI1S - description: TI1 selection - bit_offset: 7 - bit_size: 1 - enum: TIS + - name: CCDS + description: Capture/compare DMA selection + bit_offset: 3 + bit_size: 1 + enum: CCDS + - name: TI1S + description: TI1 selection + bit_offset: 7 + bit_size: 1 + enum: TIS fieldset/DCR: description: DMA control register fields: - - name: DBA - description: DMA base address - bit_offset: 0 - bit_size: 5 - - name: DBL - description: DMA burst length - bit_offset: 8 - bit_size: 5 + - name: DBA + description: DMA base address + bit_offset: 0 + bit_size: 5 + - name: DBL + description: DMA burst length + bit_offset: 8 + bit_size: 5 fieldset/DIER_ADV: extends: DIER_GP description: DMA/Interrupt enable register fields: - - name: COMIE - description: COM interrupt enable - bit_offset: 5 - bit_size: 1 - - name: BIE - description: Break interrupt enable - bit_offset: 7 - bit_size: 1 - - name: COMDE - description: COM DMA request enable - bit_offset: 13 - bit_size: 1 + - name: COMIE + description: COM interrupt enable + bit_offset: 5 + bit_size: 1 + - name: BIE + description: Break interrupt enable + bit_offset: 7 + bit_size: 1 + - name: COMDE + description: COM DMA request enable + bit_offset: 13 + bit_size: 1 fieldset/DIER_BASIC: description: DMA/Interrupt enable register fields: - - name: UIE - description: Update interrupt enable - bit_offset: 0 - bit_size: 1 - - name: UDE - description: Update DMA request enable - bit_offset: 8 - bit_size: 1 + - name: UIE + description: Update interrupt enable + bit_offset: 0 + bit_size: 1 + - name: UDE + description: Update DMA request enable + bit_offset: 8 + bit_size: 1 fieldset/DIER_GP: extends: DIER_BASIC description: DMA/Interrupt enable register fields: - - name: CCIE - description: Capture/Compare 1 interrupt enable - bit_offset: 1 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: TIE - description: Trigger interrupt enable - bit_offset: 6 - bit_size: 1 - - name: CCDE - description: Capture/Compare 1 DMA request enable - bit_offset: 9 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: TDE - description: Trigger DMA request enable - bit_offset: 14 - bit_size: 1 + - name: CCIE + description: Capture/Compare 1 interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: TIE + description: Trigger interrupt enable + bit_offset: 6 + bit_size: 1 + - name: CCDE + description: Capture/Compare 1 DMA request enable + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: TDE + description: Trigger DMA request enable + bit_offset: 14 + bit_size: 1 fieldset/DMAR: description: DMA address for full transfer fields: - - name: DMAB - description: DMA register for burst accesses - bit_offset: 0 - bit_size: 16 + - name: DMAB + description: DMA register for burst accesses + bit_offset: 0 + bit_size: 16 fieldset/EGR_ADV: extends: EGR_GP description: event generation register fields: - - name: COMG - description: Capture/Compare control update generation - bit_offset: 5 - bit_size: 1 - - name: BG - description: Break generation - bit_offset: 7 - bit_size: 1 + - name: COMG + description: Capture/Compare control update generation + bit_offset: 5 + bit_size: 1 + - name: BG + description: Break generation + bit_offset: 7 + bit_size: 1 fieldset/EGR_BASIC: description: event generation register fields: - - name: UG - description: Update generation - bit_offset: 0 - bit_size: 1 + - name: UG + description: Update generation + bit_offset: 0 + bit_size: 1 fieldset/EGR_GP: extends: EGR_BASIC description: event generation register fields: - - name: CCG - description: Capture/compare 1 generation - bit_offset: 1 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: COMG - description: Capture/Compare control update generation - bit_offset: 5 - bit_size: 1 - - name: TG - description: Trigger generation - bit_offset: 6 - bit_size: 1 - - name: BG - description: Break generation - bit_offset: 7 - bit_size: 1 + - name: CCG + description: Capture/compare 1 generation + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: COMG + description: Capture/Compare control update generation + bit_offset: 5 + bit_size: 1 + - name: TG + description: Trigger generation + bit_offset: 6 + bit_size: 1 + - name: BG + description: Break generation + bit_offset: 7 + bit_size: 1 fieldset/PSC: description: prescaler fields: - - name: PSC - description: Prescaler value - bit_offset: 0 - bit_size: 16 + - name: PSC + description: Prescaler value + bit_offset: 0 + bit_size: 16 fieldset/RCR: description: repetition counter register fields: - - name: REP - description: Repetition counter value - bit_offset: 0 - bit_size: 8 + - name: REP + description: Repetition counter value + bit_offset: 0 + bit_size: 8 fieldset/SMCR: description: slave mode control register fields: - - name: SMS - description: Slave mode selection - bit_offset: 0 - bit_size: 3 - enum: SMS - - name: TS - description: Trigger selection - bit_offset: 4 - bit_size: 3 - enum: TS - - name: MSM - description: Master/Slave mode - bit_offset: 7 - bit_size: 1 - enum: MSM - - name: ETF - description: External trigger filter - bit_offset: 8 - bit_size: 4 - enum: ETF - - name: ETPS - description: External trigger prescaler - bit_offset: 12 - bit_size: 2 - enum: ETPS - - name: ECE - description: External clock enable - bit_offset: 14 - bit_size: 1 - enum: ECE - - name: ETP - description: External trigger polarity - bit_offset: 15 - bit_size: 1 - enum: ETP + - name: SMS + description: Slave mode selection + bit_offset: 0 + bit_size: 3 + enum: SMS + - name: TS + description: Trigger selection + bit_offset: 4 + bit_size: 3 + enum: TS + - name: MSM + description: Master/Slave mode + bit_offset: 7 + bit_size: 1 + enum: MSM + - name: ETF + description: External trigger filter + bit_offset: 8 + bit_size: 4 + enum: ETF + - name: ETPS + description: External trigger prescaler + bit_offset: 12 + bit_size: 2 + enum: ETPS + - name: ECE + description: External clock enable + bit_offset: 14 + bit_size: 1 + enum: ECE + - name: ETP + description: External trigger polarity + bit_offset: 15 + bit_size: 1 + enum: ETP fieldset/SR_ADV: extends: SR_GP description: status register fields: - - name: COMIF - description: COM interrupt flag - bit_offset: 5 - bit_size: 1 - - name: BIF - description: Break interrupt flag - bit_offset: 7 - bit_size: 1 + - name: COMIF + description: COM interrupt flag + bit_offset: 5 + bit_size: 1 + - name: BIF + description: Break interrupt flag + bit_offset: 7 + bit_size: 1 fieldset/SR_BASIC: description: status register fields: - - name: UIF - description: Update interrupt flag - bit_offset: 0 - bit_size: 1 + - name: UIF + description: Update interrupt flag + bit_offset: 0 + bit_size: 1 fieldset/SR_GP: extends: SR_BASIC description: status register fields: - - name: CCIF - description: Capture/compare 1 interrupt flag - bit_offset: 1 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: COMIF - description: COM interrupt flag - bit_offset: 5 - bit_size: 1 - - name: TIF - description: Trigger interrupt flag - bit_offset: 6 - bit_size: 1 - - name: BIF - description: Break interrupt flag - bit_offset: 7 - bit_size: 1 - - name: CCOF - description: Capture/Compare 1 overcapture flag - bit_offset: 9 - bit_size: 1 - array: - len: 4 - stride: 1 + - name: CCIF + description: Capture/compare 1 interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: COMIF + description: COM interrupt flag + bit_offset: 5 + bit_size: 1 + - name: TIF + description: Trigger interrupt flag + bit_offset: 6 + bit_size: 1 + - name: BIF + description: Break interrupt flag + bit_offset: 7 + bit_size: 1 + - name: CCOF + description: Capture/Compare 1 overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 1 enum/ARPE: bit_size: 1 variants: - - name: Disabled - description: TIMx_APRR register is not buffered - value: 0 - - name: Enabled - description: TIMx_APRR register is buffered - value: 1 + - name: Disabled + description: TIMx_APRR register is not buffered + value: 0 + - name: Enabled + description: TIMx_APRR register is buffered + value: 1 enum/CCDS: bit_size: 1 variants: - - name: OnCompare - description: CCx DMA request sent when CCx event occurs - value: 0 - - name: OnUpdate - description: CCx DMA request sent when update event occurs - value: 1 + - name: OnCompare + description: CCx DMA request sent when CCx event occurs + value: 0 + - name: OnUpdate + description: CCx DMA request sent when update event occurs + value: 1 enum/CCMR_Input_CCS: bit_size: 2 variants: - - name: TI4 - description: "CCx channel is configured as input, normal mapping: ICx mapped to TIx" - value: 1 - - name: TI3 - description: "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)" - value: 2 - - name: TRC - description: "CCx channel is configured as input, ICx is mapped on TRC" - value: 3 + - name: TI4 + description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' + value: 1 + - name: TI3 + description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) + value: 2 + - name: TRC + description: CCx channel is configured as input, ICx is mapped on TRC + value: 3 enum/CCMR_Output_CCS: bit_size: 2 variants: - - name: Output - description: CCx channel is configured as output - value: 0 + - name: Output + description: CCx channel is configured as output + value: 0 enum/CKD: bit_size: 2 variants: - - name: Div1 - description: t_DTS = t_CK_INT - value: 0 - - name: Div2 - description: t_DTS = 2 × t_CK_INT - value: 1 - - name: Div4 - description: t_DTS = 4 × t_CK_INT - value: 2 + - name: Div1 + description: t_DTS = t_CK_INT + value: 0 + - name: Div2 + description: t_DTS = 2 × t_CK_INT + value: 1 + - name: Div4 + description: t_DTS = 4 × t_CK_INT + value: 2 enum/CMS: bit_size: 2 variants: - - name: EdgeAligned - description: The counter counts up or down depending on the direction bit - value: 0 - - name: CenterAligned1 - description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. - value: 1 - - name: CenterAligned2 - description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. - value: 2 - - name: CenterAligned3 - description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. - value: 3 + - name: EdgeAligned + description: The counter counts up or down depending on the direction bit + value: 0 + - name: CenterAligned1 + description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. + value: 1 + - name: CenterAligned2 + description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. + value: 2 + - name: CenterAligned3 + description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. + value: 3 enum/DIR: bit_size: 1 variants: - - name: Up - description: Counter used as upcounter - value: 0 - - name: Down - description: Counter used as downcounter - value: 1 + - name: Up + description: Counter used as upcounter + value: 0 + - name: Down + description: Counter used as downcounter + value: 1 enum/ECE: bit_size: 1 variants: - - name: Disabled - description: External clock mode 2 disabled - value: 0 - - name: Enabled - description: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. - value: 1 + - name: Disabled + description: External clock mode 2 disabled + value: 0 + - name: Enabled + description: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. + value: 1 enum/ETF: bit_size: 4 variants: - - name: NoFilter - description: "No filter, sampling is done at fDTS" - value: 0 - - name: FCK_INT_N2 - description: "fSAMPLING=fCK_INT, N=2" - value: 1 - - name: FCK_INT_N4 - description: "fSAMPLING=fCK_INT, N=4" - value: 2 - - name: FCK_INT_N8 - description: "fSAMPLING=fCK_INT, N=8" - value: 3 - - name: FDTS_Div2_N6 - description: "fSAMPLING=fDTS/2, N=6" - value: 4 - - name: FDTS_Div2_N8 - description: "fSAMPLING=fDTS/2, N=8" - value: 5 - - name: FDTS_Div4_N6 - description: "fSAMPLING=fDTS/4, N=6" - value: 6 - - name: FDTS_Div4_N8 - description: "fSAMPLING=fDTS/4, N=8" - value: 7 - - name: FDTS_Div8_N6 - description: "fSAMPLING=fDTS/8, N=6" - value: 8 - - name: FDTS_Div8_N8 - description: "fSAMPLING=fDTS/8, N=8" - value: 9 - - name: FDTS_Div16_N5 - description: "fSAMPLING=fDTS/16, N=5" - value: 10 - - name: FDTS_Div16_N6 - description: "fSAMPLING=fDTS/16, N=6" - value: 11 - - name: FDTS_Div16_N8 - description: "fSAMPLING=fDTS/16, N=8" - value: 12 - - name: FDTS_Div32_N5 - description: "fSAMPLING=fDTS/32, N=5" - value: 13 - - name: FDTS_Div32_N6 - description: "fSAMPLING=fDTS/32, N=6" - value: 14 - - name: FDTS_Div32_N8 - description: "fSAMPLING=fDTS/32, N=8" - value: 15 + - name: NoFilter + description: No filter, sampling is done at fDTS + value: 0 + - name: FCK_INT_N2 + description: fSAMPLING=fCK_INT, N=2 + value: 1 + - name: FCK_INT_N4 + description: fSAMPLING=fCK_INT, N=4 + value: 2 + - name: FCK_INT_N8 + description: fSAMPLING=fCK_INT, N=8 + value: 3 + - name: FDTS_Div2_N6 + description: fSAMPLING=fDTS/2, N=6 + value: 4 + - name: FDTS_Div2_N8 + description: fSAMPLING=fDTS/2, N=8 + value: 5 + - name: FDTS_Div4_N6 + description: fSAMPLING=fDTS/4, N=6 + value: 6 + - name: FDTS_Div4_N8 + description: fSAMPLING=fDTS/4, N=8 + value: 7 + - name: FDTS_Div8_N6 + description: fSAMPLING=fDTS/8, N=6 + value: 8 + - name: FDTS_Div8_N8 + description: fSAMPLING=fDTS/8, N=8 + value: 9 + - name: FDTS_Div16_N5 + description: fSAMPLING=fDTS/16, N=5 + value: 10 + - name: FDTS_Div16_N6 + description: fSAMPLING=fDTS/16, N=6 + value: 11 + - name: FDTS_Div16_N8 + description: fSAMPLING=fDTS/16, N=8 + value: 12 + - name: FDTS_Div32_N5 + description: fSAMPLING=fDTS/32, N=5 + value: 13 + - name: FDTS_Div32_N6 + description: fSAMPLING=fDTS/32, N=6 + value: 14 + - name: FDTS_Div32_N8 + description: fSAMPLING=fDTS/32, N=8 + value: 15 enum/ETP: bit_size: 1 variants: - - name: NotInverted - description: "ETR is noninverted, active at high level or rising edge" - value: 0 - - name: Inverted - description: "ETR is inverted, active at low level or falling edge" - value: 1 + - name: NotInverted + description: ETR is noninverted, active at high level or rising edge + value: 0 + - name: Inverted + description: ETR is inverted, active at low level or falling edge + value: 1 enum/ETPS: bit_size: 2 variants: - - name: Div1 - description: Prescaler OFF - value: 0 - - name: Div2 - description: ETRP frequency divided by 2 - value: 1 - - name: Div4 - description: ETRP frequency divided by 4 - value: 2 - - name: Div8 - description: ETRP frequency divided by 8 - value: 3 + - name: Div1 + description: Prescaler OFF + value: 0 + - name: Div2 + description: ETRP frequency divided by 2 + value: 1 + - name: Div4 + description: ETRP frequency divided by 4 + value: 2 + - name: Div8 + description: ETRP frequency divided by 8 + value: 3 enum/ICF: bit_size: 4 variants: - - name: NoFilter - description: "No filter, sampling is done at fDTS" - value: 0 - - name: FCK_INT_N2 - description: "fSAMPLING=fCK_INT, N=2" - value: 1 - - name: FCK_INT_N4 - description: "fSAMPLING=fCK_INT, N=4" - value: 2 - - name: FCK_INT_N8 - description: "fSAMPLING=fCK_INT, N=8" - value: 3 - - name: FDTS_Div2_N6 - description: "fSAMPLING=fDTS/2, N=6" - value: 4 - - name: FDTS_Div2_N8 - description: "fSAMPLING=fDTS/2, N=8" - value: 5 - - name: FDTS_Div4_N6 - description: "fSAMPLING=fDTS/4, N=6" - value: 6 - - name: FDTS_Div4_N8 - description: "fSAMPLING=fDTS/4, N=8" - value: 7 - - name: FDTS_Div8_N6 - description: "fSAMPLING=fDTS/8, N=6" - value: 8 - - name: FDTS_Div8_N8 - description: "fSAMPLING=fDTS/8, N=8" - value: 9 - - name: FDTS_Div16_N5 - description: "fSAMPLING=fDTS/16, N=5" - value: 10 - - name: FDTS_Div16_N6 - description: "fSAMPLING=fDTS/16, N=6" - value: 11 - - name: FDTS_Div16_N8 - description: "fSAMPLING=fDTS/16, N=8" - value: 12 - - name: FDTS_Div32_N5 - description: "fSAMPLING=fDTS/32, N=5" - value: 13 - - name: FDTS_Div32_N6 - description: "fSAMPLING=fDTS/32, N=6" - value: 14 - - name: FDTS_Div32_N8 - description: "fSAMPLING=fDTS/32, N=8" - value: 15 + - name: NoFilter + description: No filter, sampling is done at fDTS + value: 0 + - name: FCK_INT_N2 + description: fSAMPLING=fCK_INT, N=2 + value: 1 + - name: FCK_INT_N4 + description: fSAMPLING=fCK_INT, N=4 + value: 2 + - name: FCK_INT_N8 + description: fSAMPLING=fCK_INT, N=8 + value: 3 + - name: FDTS_Div2_N6 + description: fSAMPLING=fDTS/2, N=6 + value: 4 + - name: FDTS_Div2_N8 + description: fSAMPLING=fDTS/2, N=8 + value: 5 + - name: FDTS_Div4_N6 + description: fSAMPLING=fDTS/4, N=6 + value: 6 + - name: FDTS_Div4_N8 + description: fSAMPLING=fDTS/4, N=8 + value: 7 + - name: FDTS_Div8_N6 + description: fSAMPLING=fDTS/8, N=6 + value: 8 + - name: FDTS_Div8_N8 + description: fSAMPLING=fDTS/8, N=8 + value: 9 + - name: FDTS_Div16_N5 + description: fSAMPLING=fDTS/16, N=5 + value: 10 + - name: FDTS_Div16_N6 + description: fSAMPLING=fDTS/16, N=6 + value: 11 + - name: FDTS_Div16_N8 + description: fSAMPLING=fDTS/16, N=8 + value: 12 + - name: FDTS_Div32_N5 + description: fSAMPLING=fDTS/32, N=5 + value: 13 + - name: FDTS_Div32_N6 + description: fSAMPLING=fDTS/32, N=6 + value: 14 + - name: FDTS_Div32_N8 + description: fSAMPLING=fDTS/32, N=8 + value: 15 enum/MMS: bit_size: 3 variants: - - name: Reset - description: The UG bit from the TIMx_EGR register is used as trigger output - value: 0 - - name: Enable - description: "The counter enable signal, CNT_EN, is used as trigger output" - value: 1 - - name: Update - description: The update event is selected as trigger output - value: 2 - - name: ComparePulse - description: "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred" - value: 3 - - name: CompareOC1 - description: OC1REF signal is used as trigger output - value: 4 - - name: CompareOC2 - description: OC2REF signal is used as trigger output - value: 5 - - name: CompareOC3 - description: OC3REF signal is used as trigger output - value: 6 - - name: CompareOC4 - description: OC4REF signal is used as trigger output - value: 7 + - name: Reset + description: The UG bit from the TIMx_EGR register is used as trigger output + value: 0 + - name: Enable + description: The counter enable signal, CNT_EN, is used as trigger output + value: 1 + - name: Update + description: The update event is selected as trigger output + value: 2 + - name: ComparePulse + description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + value: 3 + - name: CompareOC1 + description: OC1REF signal is used as trigger output + value: 4 + - name: CompareOC2 + description: OC2REF signal is used as trigger output + value: 5 + - name: CompareOC3 + description: OC3REF signal is used as trigger output + value: 6 + - name: CompareOC4 + description: OC4REF signal is used as trigger output + value: 7 enum/MSM: bit_size: 1 variants: - - name: NoSync - description: No action - value: 0 - - name: Sync - description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. - value: 1 + - name: NoSync + description: No action + value: 0 + - name: Sync + description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + value: 1 enum/OCM: bit_size: 3 variants: - - name: Frozen - description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs - value: 0 - - name: ActiveOnMatch - description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register - value: 1 - - name: InactiveOnMatch - description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register - value: 2 - - name: Toggle - description: OCyREF toggles when TIMx_CNT=TIMx_CCRy - value: 3 - - name: ForceInactive - description: OCyREF is forced low - value: 4 - - name: ForceActive - description: OCyREF is forced high - value: 5 - - name: PwmMode1 - description: "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active" - value: 6 - - name: PwmMode2 - description: Inversely to PwmMode1 - value: 7 + - name: Frozen + description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + value: 0 + - name: ActiveOnMatch + description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + value: 1 + - name: InactiveOnMatch + description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + value: 2 + - name: Toggle + description: OCyREF toggles when TIMx_CNT=TIMx_CCRy + value: 3 + - name: ForceInactive + description: OCyREF is forced low + value: 4 + - name: ForceActive + description: OCyREF is forced high + value: 5 + - name: PwmMode1 + description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active + value: 6 + - name: PwmMode2 + description: Inversely to PwmMode1 + value: 7 enum/OCPE: bit_size: 1 variants: - - name: Disabled - description: Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately - value: 0 - - name: Enabled - description: Preload register on CCR2 enabled. Preload value is loaded into active register on each update event - value: 1 + - name: Disabled + description: Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately + value: 0 + - name: Enabled + description: Preload register on CCR2 enabled. Preload value is loaded into active register on each update event + value: 1 enum/OPM: bit_size: 1 variants: - - name: Disabled - description: Counter is not stopped at update event - value: 0 - - name: Enabled - description: Counter stops counting at the next update event (clearing the CEN bit) - value: 1 + - name: Disabled + description: Counter is not stopped at update event + value: 0 + - name: Enabled + description: Counter stops counting at the next update event (clearing the CEN bit) + value: 1 enum/OSSI: bit_size: 1 variants: - - name: Disabled - description: "When inactive, OC/OCN outputs are disabled" - value: 0 - - name: IdleLevel - description: "When inactive, OC/OCN outputs are forced to idle level" - value: 1 + - name: Disabled + description: When inactive, OC/OCN outputs are disabled + value: 0 + - name: IdleLevel + description: When inactive, OC/OCN outputs are forced to idle level + value: 1 enum/OSSR: bit_size: 1 variants: - - name: Disabled - description: "When inactive, OC/OCN outputs are disabled" - value: 0 - - name: IdleLevel - description: "When inactive, OC/OCN outputs are enabled with their inactive level" - value: 1 + - name: Disabled + description: When inactive, OC/OCN outputs are disabled + value: 0 + - name: IdleLevel + description: When inactive, OC/OCN outputs are enabled with their inactive level + value: 1 enum/SMS: bit_size: 3 variants: - - name: Disabled - description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. - value: 0 - - name: Encoder_Mode_1 - description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. - value: 1 - - name: Encoder_Mode_2 - description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. - value: 2 - - name: Encoder_Mode_3 - description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. - value: 3 - - name: Reset_Mode - description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. - value: 4 - - name: Gated_Mode - description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. - value: 5 - - name: Trigger_Mode - description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. - value: 6 - - name: Ext_Clock_Mode - description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. - value: 7 + - name: Disabled + description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. + value: 0 + - name: Encoder_Mode_1 + description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + value: 1 + - name: Encoder_Mode_2 + description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + value: 2 + - name: Encoder_Mode_3 + description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + value: 3 + - name: Reset_Mode + description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + value: 4 + - name: Gated_Mode + description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + value: 5 + - name: Trigger_Mode + description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + value: 6 + - name: Ext_Clock_Mode + description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + value: 7 enum/TIS: bit_size: 1 variants: - - name: Normal - description: The TIMx_CH1 pin is connected to TI1 input - value: 0 - - name: XOR - description: "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input" - value: 1 + - name: Normal + description: The TIMx_CH1 pin is connected to TI1 input + value: 0 + - name: XOR + description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + value: 1 enum/TS: bit_size: 3 variants: - - name: ITR0 - description: Internal Trigger 0 (ITR0) - value: 0 - - name: ITR1 - description: Internal Trigger 1 (ITR1) - value: 1 - - name: ITR2 - description: Internal Trigger 2 (ITR2) - value: 2 - - name: ITR3 - description: Internal Trigger 3 (ITR3) - value: 3 - - name: TI1F_ED - description: TI1 Edge Detector (TI1F_ED) - value: 4 - - name: TI1FP1 - description: Filtered Timer Input 1 (TI1FP1) - value: 5 - - name: TI2FP2 - description: Filtered Timer Input 2 (TI2FP2) - value: 6 - - name: ETRF - description: External Trigger input (ETRF) - value: 7 + - name: ITR0 + description: Internal Trigger 0 (ITR0) + value: 0 + - name: ITR1 + description: Internal Trigger 1 (ITR1) + value: 1 + - name: ITR2 + description: Internal Trigger 2 (ITR2) + value: 2 + - name: ITR3 + description: Internal Trigger 3 (ITR3) + value: 3 + - name: TI1F_ED + description: TI1 Edge Detector (TI1F_ED) + value: 4 + - name: TI1FP1 + description: Filtered Timer Input 1 (TI1FP1) + value: 5 + - name: TI2FP2 + description: Filtered Timer Input 2 (TI2FP2) + value: 6 + - name: ETRF + description: External Trigger input (ETRF) + value: 7 enum/URS: bit_size: 1 variants: - - name: AnyEvent - description: "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request" - value: 0 - - name: CounterOnly - description: Only counter overflow/underflow generates an update interrupt or DMA request - value: 1 + - name: AnyEvent + description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + value: 0 + - name: CounterOnly + description: Only counter overflow/underflow generates an update interrupt or DMA request + value: 1 diff --git a/data/registers/ucpd_v1.yaml b/data/registers/ucpd_v1.yaml new file mode 100644 index 0000000..512539c --- /dev/null +++ b/data/registers/ucpd_v1.yaml @@ -0,0 +1,626 @@ +block/UCPD: + description: USB Power Delivery interface + items: + - name: CFGR1 + description: configuration register 1 + byte_offset: 0 + fieldset: CFGR1 + - name: CFGR2 + description: configuration register 2 + byte_offset: 4 + fieldset: CFGR2 + - name: CFGR3 + description: configuration register 3 + byte_offset: 8 + fieldset: CFGR3 + - name: CR + description: control register + byte_offset: 12 + fieldset: CR + - name: IMR + description: interrupt mask register + byte_offset: 16 + fieldset: IMR + - name: SR + description: status register + byte_offset: 20 + fieldset: SR + - name: ICR + description: interrupt clear register + byte_offset: 24 + fieldset: ICR + - name: TX_ORDSETR + description: Tx ordered set type register + byte_offset: 28 + fieldset: TX_ORDSETR + - name: TX_PAYSZR + description: Tx payload size register + byte_offset: 32 + fieldset: TX_PAYSZR + - name: TXDR + description: Tx data register + byte_offset: 36 + fieldset: TXDR + - name: RX_ORDSETR + byte_offset: 40 + fieldset: RX_ORDSETR + - name: RX_PAYSZR + byte_offset: 44 + fieldset: RX_PAYSZR + - name: RXDR + byte_offset: 48 + fieldset: RXDR + - name: RX_ORDEXTR1 + description: Rx ordered set extension register 1 + byte_offset: 52 + fieldset: RX_ORDEXTR1 + - name: RX_ORDEXTR2 + description: Rx ordered set extension register 2 + byte_offset: 56 + fieldset: RX_ORDEXTR2 + - name: IPVER + description: UCPD IP ID register + byte_offset: 1012 + access: Read + fieldset: IPVER + - name: IPID + description: UCPD IP ID register + byte_offset: 1016 + access: Read + fieldset: IPID + - name: MID + description: UCPD IP ID register + byte_offset: 1020 + access: Read + fieldset: MID +fieldset/CFGR1: + description: configuration register 1 + fields: + - name: HBITCLKDIV + description: "Division ratio for producing half-bit clock\r The bitfield determines the division ratio (the bitfield value plus one) of a clk divider producing half-bit clock (hbit_clk)." + bit_offset: 0 + bit_size: 6 + - name: IFRGAP + description: "Division ratio for producing inter-frame gap timer clock\r The bitfield determines the division ratio (the bitfield value minus one) of a clk divider producing inter-frame gap timer clock (tInterFrameGap).\r The division ratio 15 is to apply for Tx clock at the USB PD 2.0 specification nominal value. The division ratios below 15 are to apply for Tx clock below nominal, and the division ratios above 15 for Tx clock above nominal." + bit_offset: 6 + bit_size: 5 + - name: TRANSWIN + description: "Transition window duration\r The bitfield determines the division ratio (the bitfield value minus one) of a hbit_clk divider producing tTransitionWindow interval.\r Set a value that produces an interval of 12 to 20 us, taking into account the clk frequency and the HBITCLKDIV[5:0] bitfield setting." + bit_offset: 11 + bit_size: 5 + - name: PSC_USBPDCLK + description: "Pre-scaler division ratio for generating clk\r The bitfield determines the division ratio of a kernel clock pre-scaler producing peripheral clock (clk).\r It is recommended to use the pre-scaler so as to set the clk frequency in the range from 6 to 9 MHz." + bit_offset: 17 + bit_size: 3 + enum: PSC_USBPDCLK + - name: RXORDSETEN + description: "Receiver ordered set enable\r The bitfield determines the types of ordered sets that the receiver must detect. When set/cleared, each bit enables/disables a specific function:\r 0bxxxxxxxx1: SOP detect enabled\r 0bxxxxxxx1x: SOP' detect enabled\r 0bxxxxxx1xx: SOP'' detect enabled\r 0bxxxxx1xxx: Hard Reset detect enabled\r 0bxxxx1xxxx: Cable Detect reset enabled\r 0bxxx1xxxxx: SOP'_Debug enabled\r 0bxx1xxxxxx: SOP''_Debug enabled\r 0bx1xxxxxxx: SOP extension#1 enabled\r 0b1xxxxxxxx: SOP extension#2 enabled" + bit_offset: 20 + bit_size: 9 + - name: TXDMAEN + description: "Transmission DMA mode enable\r When set, the bit enables DMA mode for transmission." + bit_offset: 29 + bit_size: 1 + - name: RXDMAEN + description: "Reception DMA mode enable\r When set, the bit enables DMA mode for reception." + bit_offset: 30 + bit_size: 1 + - name: UCPDEN + description: "peripheral enable\r General enable of the peripheral.\r Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state." + bit_offset: 31 + bit_size: 1 +fieldset/CFGR2: + description: configuration register 2 + fields: + - name: RXFILTDIS + description: "BMC decoder Rx pre-filter enable\r The sampling clock is that of the receiver (that is, after pre-scaler)." + bit_offset: 0 + bit_size: 1 + - name: RXFILT2N3 + description: "BMC decoder Rx pre-filter sampling method\r Number of consistent consecutive samples before confirming a new value." + bit_offset: 1 + bit_size: 1 + - name: FORCECLK + description: Force ClkReq clock request + bit_offset: 2 + bit_size: 1 + - name: WUPEN + description: "Wakeup from Stop mode enable\r Setting the bit enables the ASYNC_INT signal." + bit_offset: 3 + bit_size: 1 +fieldset/CFGR3: + description: configuration register 3 + fields: + - name: TRIM_CC1_RD + description: SW trim value for Rd resistor on the CC1 line + bit_offset: 0 + bit_size: 4 + - name: TRIM_CC1_RP + description: SW trim value for Rp current sources on the CC1 line + bit_offset: 9 + bit_size: 4 + - name: TRIM_CC2_RD + description: SW trim value for Rd resistor on the CC2 line + bit_offset: 16 + bit_size: 4 + - name: TRIM_CC2_RP + description: SW trim value for Rp current sources on the CC2 line + bit_offset: 25 + bit_size: 4 +fieldset/CR: + description: control register + fields: + - name: TXMODE + description: "Type of Tx packet\r Writing the bitfield triggers the action as follows, depending on the value:\r Others: invalid\r From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the \"tBISTContMode\" delay), disable the peripheral (UCPDEN = 0)." + bit_offset: 0 + bit_size: 2 + enum: TXMODE + - name: TXSEND + description: "Command to send a Tx packet\r The bit is cleared by hardware as soon as the packet transmission begins or is discarded." + bit_offset: 2 + bit_size: 1 + - name: TXHRST + description: "Command to send a Tx Hard Reset\r The bit is cleared by hardware as soon as the message transmission begins or is discarded." + bit_offset: 3 + bit_size: 1 + - name: RXMODE + description: "Receiver mode\r Determines the mode of the receiver.\r When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message." + bit_offset: 4 + bit_size: 1 + - name: PHYRXEN + description: "USB Power Delivery receiver enable\r Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver selected via the PHYCCSEL bit is enabled when the bit is set." + bit_offset: 5 + bit_size: 1 + - name: PHYCCSEL + description: "CC1/CC2 line selector for USB Power Delivery signaling\r The selection depends on the cable orientation as discovered at attach." + bit_offset: 6 + bit_size: 1 + enum: PHYCCSEL + - name: ANASUBMODE + description: "Analog PHY sub-mode\r Refer to TYPEC_VSTATE_CCx for the effect of this bitfield." + bit_offset: 7 + bit_size: 2 + - name: ANAMODE + description: "Analog PHY operating mode\r The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE[1:0]." + bit_offset: 9 + bit_size: 1 + enum: ANAMODE + - name: CCENABLE + description: "CC line enable\r This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE[1:0] setting.\r A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source." + bit_offset: 10 + bit_size: 2 + enum: CCENABLE + - name: CC1VCONNEN + description: VCONN switch enable for CC1 + bit_offset: 13 + bit_size: 1 + - name: CC2VCONNEN + description: VCONN switch enable for CC2 + bit_offset: 14 + bit_size: 1 + - name: DBATTEN + description: "Dead battery function enable\r The bit takes effect upon setting the USBPDstrobe bit of the SYS_CONFIG register.\r Dead battery function only operates if the external circuit is appropriately configured." + bit_offset: 15 + bit_size: 1 + - name: FRSRXEN + description: "FRS event detection enable\r Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through the PHYCCSEL bit. 0: Disable\r Clear the bit when the device is attached to an FRS-incapable source/sink." + bit_offset: 16 + bit_size: 1 + - name: FRSTX + description: "FRS Tx signaling enable.\r Setting the bit enables FRS Tx signaling.\r The bit is cleared by hardware after a delay respecting the USB Power Delivery specification Revision 3.0." + bit_offset: 17 + bit_size: 1 + - name: RDCH + description: "Rdch condition drive\r The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to \"USB Type-C ECN for Source VCONN Discharge\". The CCENABLE[1:0] bitfield must be set accordingly, too." + bit_offset: 18 + bit_size: 1 + - name: CC1TCDIS + description: "CC1 Type-C detector disable\r The bit disables the Type-C detector on the CC1 line.\r When enabled, the Type-C detector for CC1 is configured through ANAMODE and ANASUBMODE[1:0]." + bit_offset: 20 + bit_size: 1 + - name: CC2TCDIS + description: "CC2 Type-C detector disable\r The bit disables the Type-C detector on the CC2 line.\r When enabled, the Type-C detector for CC2 is configured through ANAMODE and ANASUBMODE[1:0]." + bit_offset: 21 + bit_size: 1 +fieldset/ICR: + description: interrupt clear register + fields: + - name: TXMSGDISCCF + description: "Tx message discard flag (TXMSGDISC) clear\r Setting the bit clears the TXMSGDISC flag in the SR register." + bit_offset: 1 + bit_size: 1 + - name: TXMSGSENTCF + description: "Tx message send flag (TXMSGSENT) clear\r Setting the bit clears the TXMSGSENT flag in the SR register." + bit_offset: 2 + bit_size: 1 + - name: TXMSGABTCF + description: "Tx message abort flag (TXMSGABT) clear\r Setting the bit clears the TXMSGABT flag in the SR register." + bit_offset: 3 + bit_size: 1 + - name: HRSTDISCCF + description: "Hard reset discard flag (HRSTDISC) clear\r Setting the bit clears the HRSTDISC flag in the SR register." + bit_offset: 4 + bit_size: 1 + - name: HRSTSENTCF + description: "Hard reset send flag (HRSTSENT) clear\r Setting the bit clears the HRSTSENT flag in the SR register." + bit_offset: 5 + bit_size: 1 + - name: TXUNDCF + description: "Tx underflow flag (TXUND) clear\r Setting the bit clears the TXUND flag in the SR register." + bit_offset: 6 + bit_size: 1 + - name: RXORDDETCF + description: "Rx ordered set detect flag (RXORDDET) clear\r Setting the bit clears the RXORDDET flag in the SR register." + bit_offset: 9 + bit_size: 1 + - name: RXHRSTDETCF + description: "Rx Hard Reset detect flag (RXHRSTDET) clear\r Setting the bit clears the RXHRSTDET flag in the SR register." + bit_offset: 10 + bit_size: 1 + - name: RXOVRCF + description: "Rx overflow flag (RXOVR) clear\r Setting the bit clears the RXOVR flag in the SR register." + bit_offset: 11 + bit_size: 1 + - name: RXMSGENDCF + description: "Rx message received flag (RXMSGEND) clear\r Setting the bit clears the RXMSGEND flag in the SR register." + bit_offset: 12 + bit_size: 1 + - name: TYPECEVT1CF + description: "Type-C CC1 event flag (TYPECEVT1) clear\r Setting the bit clears the TYPECEVT1 flag in the SR register" + bit_offset: 14 + bit_size: 1 + - name: TYPECEVT2CF + description: "Type-C CC2 line event flag (TYPECEVT2) clear\r Setting the bit clears the TYPECEVT2 flag in the SR register" + bit_offset: 15 + bit_size: 1 + - name: FRSEVTCF + description: "FRS event flag (FRSEVT) clear\r Setting the bit clears the FRSEVT flag in the SR register." + bit_offset: 20 + bit_size: 1 +fieldset/IMR: + description: interrupt mask register + fields: + - name: TXISIE + description: TXIS interrupt enable + bit_offset: 0 + bit_size: 1 + - name: TXMSGDISCIE + description: TXMSGDISC interrupt enable + bit_offset: 1 + bit_size: 1 + - name: TXMSGSENTIE + description: TXMSGSENT interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TXMSGABTIE + description: TXMSGABT interrupt enable + bit_offset: 3 + bit_size: 1 + - name: HRSTDISCIE + description: HRSTDISC interrupt enable + bit_offset: 4 + bit_size: 1 + - name: HRSTSENTIE + description: HRSTSENT interrupt enable + bit_offset: 5 + bit_size: 1 + - name: TXUNDIE + description: TXUND interrupt enable + bit_offset: 6 + bit_size: 1 + - name: RXNEIE + description: RXNE interrupt enable + bit_offset: 8 + bit_size: 1 + - name: RXORDDETIE + description: RXORDDET interrupt enable + bit_offset: 9 + bit_size: 1 + - name: RXHRSTDETIE + description: RXHRSTDET interrupt enable + bit_offset: 10 + bit_size: 1 + - name: RXOVRIE + description: RXOVR interrupt enable + bit_offset: 11 + bit_size: 1 + - name: RXMSGENDIE + description: RXMSGEND interrupt enable + bit_offset: 12 + bit_size: 1 + - name: TYPECEVT1IE + description: TYPECEVT1 interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TYPECEVT2IE + description: TYPECEVT2 interrupt enable + bit_offset: 15 + bit_size: 1 + - name: FRSEVTIE + description: FRSEVT interrupt enable + bit_offset: 20 + bit_size: 1 +fieldset/IPID: + description: UCPD IP ID register + fields: + - name: IPID + description: IPID + bit_offset: 0 + bit_size: 32 +fieldset/IPVER: + description: UCPD IP ID register + fields: + - name: IPVER + description: IPVER + bit_offset: 0 + bit_size: 32 +fieldset/MID: + description: UCPD IP ID register + fields: + - name: IPID + description: IPID + bit_offset: 0 + bit_size: 32 +fieldset/RXDR: + fields: + - name: RXDATA + description: Data byte received + bit_offset: 0 + bit_size: 8 +fieldset/RX_ORDEXTR1: + description: Rx ordered set extension register 1 + fields: + - name: RXSOPX1 + description: "Ordered set 1 received\r The bitfield contains a full 20-bit sequence received, consisting of four K‑codes, each of five bits. The bit 0 (bit 0 of K‑code1) is receive first, the bit 19 (bit 4 of K‑code4) last." + bit_offset: 0 + bit_size: 20 +fieldset/RX_ORDEXTR2: + description: Rx ordered set extension register 2 + fields: + - name: RXSOPX2 + description: "Ordered set 2 received\r The bitfield contains a full 20-bit sequence received, consisting of four K‑codes, each of five bits. The bit 0 (bit 0 of K‑code1) is receive first, the bit 19 (bit 4 of K‑code4) last." + bit_offset: 0 + bit_size: 20 +fieldset/RX_ORDSETR: + fields: + - name: RXORDSET + description: Rx ordered set code detected + bit_offset: 0 + bit_size: 3 + enum: RXORDSET + - name: RXSOP3OF4 + description: The bit indicates the number of correct K‑codes. For debug purposes only. + bit_offset: 3 + bit_size: 1 + - name: RXSOPKINVALID + description: "The bitfield is for debug purposes only.\r Others: Invalid" + bit_offset: 4 + bit_size: 3 + enum: RXSOPKINVALID +fieldset/RX_PAYSZR: + fields: + - name: RXPAYSZ + description: "Rx payload size received\r This bitfield contains the number of bytes of a payload (including header but excluding CRC) received: each time a new data byte is received in the RXDR register, the bitfield value increments and the RXMSGEND flag is set (and an interrupt generated if enabled).\r The bitfield may return a spurious value when a byte reception is ongoing (the RXMSGEND flag is low)." + bit_offset: 0 + bit_size: 10 +fieldset/SR: + description: status register + fields: + - name: TXIS + description: "Transmit interrupt status\r The flag indicates that the TXDR register is empty and new data write is required (as the amount of data sent has not reached the payload size defined in the TXPAYSZ bitfield). The flag is cleared with the data write into the TXDR register." + bit_offset: 0 + bit_size: 1 + - name: TXMSGDISC + description: "Message transmission discarded\r The flag indicates that a message transmission was dropped. The flag is cleared by setting the TXMSGDISCCF bit.\r Transmission of a message can be dropped if there is a concurrent receive in progress or at excessive noise on the line. After a Tx message is discarded, the flag is only raised when the CC line becomes idle." + bit_offset: 1 + bit_size: 1 + - name: TXMSGSENT + description: "Message transmission completed\r The flag indicates the completion of packet transmission. It is cleared by setting the TXMSGSENTCF bit.\r In the event of a message transmission interrupted by a Hard Reset, the flag is not raised." + bit_offset: 2 + bit_size: 1 + - name: TXMSGABT + description: "Transmit message abort\r The flag indicates that a Tx message is aborted due to a subsequent Hard Reset message send request taking priority during transmit. It is cleared by setting the TXMSGABTCF bit." + bit_offset: 3 + bit_size: 1 + - name: HRSTDISC + description: "Hard Reset discarded\r The flag indicates that the Hard Reset message is discarded. The flag is cleared by setting the HRSTDISCCF bit." + bit_offset: 4 + bit_size: 1 + - name: HRSTSENT + description: "Hard Reset message sent\r The flag indicates that the Hard Reset message is sent. The flag is cleared by setting the HRSTSENTCF bit." + bit_offset: 5 + bit_size: 1 + - name: TXUND + description: "Tx data underrun detection\r The flag indicates that the Tx data register (TXDR) was not written in time for a transmit message to execute normally. It is cleared by setting the TXUNDCF bit." + bit_offset: 6 + bit_size: 1 + - name: RXNE + description: "Receive data register not empty detection\r The flag indicates that the RXDR register is not empty. It is automatically cleared upon reading RXDR." + bit_offset: 8 + bit_size: 1 + - name: RXORDDET + description: "Rx ordered set (4 K-codes) detection\r The flag indicates the detection of an ordered set. The relevant information is stored in the RXORDSET[2:0] bitfield of the RX_ORDSET register. It is cleared by setting the RXORDDETCF bit." + bit_offset: 9 + bit_size: 1 + - name: RXHRSTDET + description: "Rx Hard Reset receipt detection\r The flag indicates the receipt of valid Hard Reset message. It is cleared by setting the RXHRSTDETCF bit." + bit_offset: 10 + bit_size: 1 + - name: RXOVR + description: "Rx data overflow detection\r The flag indicates Rx data buffer overflow. It is cleared by setting the RXOVRCF bit.\r The buffer overflow can occur if the received data are not read fast enough." + bit_offset: 11 + bit_size: 1 + - name: RXMSGEND + description: "Rx message received\r The flag indicates whether a message (except Hard Reset message) has been received, regardless the CRC value. The flag is cleared by setting the RXMSGENDCF bit.\r The RXERR flag set when the RXMSGEND flag goes high indicates errors in the last-received message." + bit_offset: 12 + bit_size: 1 + - name: RXERR + description: "Receive message error\r The flag indicates errors of the last Rx message declared (via RXMSGEND), such as incorrect CRC or truncated message (a line becoming static before EOP is met). It is asserted whenever the RXMSGEND flag is set." + bit_offset: 13 + bit_size: 1 + - name: TYPECEVT1 + description: "Type-C voltage level event on CC1 line\r The flag indicates a change of the TYPEC_VSTATE_CC1[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit." + bit_offset: 14 + bit_size: 1 + - name: TYPECEVT2 + description: "Type-C voltage level event on CC2 line\r The flag indicates a change of the TYPEC_VSTATE_CC2[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit." + bit_offset: 15 + bit_size: 1 + - name: TYPEC_VSTATE_CC1 + description: "The status bitfield indicates the voltage level on the CC1 line in its steady state.\r The voltage variation on the CC1 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value." + bit_offset: 16 + bit_size: 2 + enum: TYPEC_VSTATE_CC + - name: TYPEC_VSTATE_CC2 + description: "CC2 line voltage level\r The status bitfield indicates the voltage level on the CC2 line in its steady state.\r The voltage variation on the CC2 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value." + bit_offset: 18 + bit_size: 2 + enum: TYPEC_VSTATE_CC + - name: FRSEVT + description: "FRS detection event\r The flag is cleared by setting the FRSEVTCF bit." + bit_offset: 20 + bit_size: 1 +fieldset/TXDR: + description: Tx data register + fields: + - name: TXDATA + description: Data byte to transmit + bit_offset: 0 + bit_size: 8 +fieldset/TX_ORDSETR: + description: Tx ordered set type register + fields: + - name: TXORDSET + description: "Ordered set to transmit\r The bitfield determines a full 20-bit sequence to transmit, consisting of four K-codes, each of five bits, defining the packet to transmit. The bit 0 (bit 0 of K-code1) is the first, the bit 19 (bit 4 of K‑code4) the last." + bit_offset: 0 + bit_size: 20 +fieldset/TX_PAYSZR: + description: Tx payload size register + fields: + - name: TXPAYSZ + description: "Payload size yet to transmit\r The bitfield is modified by software and by hardware. It contains the number of bytes of a payload (including header but excluding CRC) yet to transmit: each time a data byte is written into the TXDR register, the bitfield value decrements and the TXIS bit is set, except when the bitfield value reaches zero. The enumerated values are standard payload sizes before the start of transmission." + bit_offset: 0 + bit_size: 10 +enum/ANAMODE: + bit_size: 1 + variants: + - name: Source + description: Source + value: 0 + - name: Sink + description: Sink + value: 1 +enum/CCENABLE: + bit_size: 2 + variants: + - name: Disabled + description: Disable both PHYs + value: 0 + - name: Cc1 + description: Enable CC1 PHY + value: 1 + - name: Cc2 + description: Enable CC2 PHY + value: 2 + - name: Both + description: Enable CC1 and CC2 PHY + value: 3 +enum/PHYCCSEL: + bit_size: 1 + variants: + - name: Cc1 + description: Use CC1 IO for Power Delivery communication + value: 0 + - name: Cc2 + description: Use CC2 IO for Power Delivery communication + value: 1 +enum/PSC_USBPDCLK: + bit_size: 3 + variants: + - name: Div1 + description: 1 (bypass) + value: 0 + - name: Div2 + description: '2' + value: 1 + - name: Div4 + description: '4' + value: 2 + - name: Div8 + description: '8' + value: 3 + - name: Div16 + description: '16' + value: 4 +enum/RXORDSET: + bit_size: 3 + variants: + - name: Sop + description: SOP code detected in receiver + value: 0 + - name: SopPrime + description: SOP' code detected in receiver + value: 1 + - name: SopDoublePrime + description: SOP'' code detected in receiver + value: 2 + - name: SopPrimeDebug + description: SOP'_Debug detected in receiver + value: 3 + - name: SopDoublePrimeDebug + description: SOP''_Debug detected in receiver + value: 4 + - name: CableReset + description: Cable Reset detected in receiver + value: 5 + - name: Ext1 + description: SOP extension#1 detected in receiver + value: 6 + - name: Ext2 + description: SOP extension#2 detected in receiver + value: 7 +enum/RXSOPKINVALID: + bit_size: 3 + variants: + - name: None + description: No K‑code corrupted + value: 0 + - name: First + description: First K‑code corrupted + value: 1 + - name: Second + description: Second K‑code corrupted + value: 2 + - name: Third + description: Third K‑code corrupted + value: 3 + - name: Fourth + description: Fourth K‑code corrupted + value: 4 +enum/TXMODE: + bit_size: 2 + variants: + - name: Packet + description: Transmission of Tx packet previously defined in other registers + value: 0 + - name: CableReset + description: Cable Reset sequence + value: 1 + - name: Bist + description: BIST test sequence (BIST Carrier Mode 2) + value: 2 +enum/TYPEC_VSTATE_CC: + bit_size: 2 + variants: + - name: Lowest + description: Lowest + value: 0 + - name: Low + description: Low + value: 1 + - name: High + description: High + value: 2 + - name: Highest + description: Highest + value: 3 diff --git a/data/registers/uid_v1.yaml b/data/registers/uid_v1.yaml index 77e9e86..e4185a1 100644 --- a/data/registers/uid_v1.yaml +++ b/data/registers/uid_v1.yaml @@ -1,11 +1,10 @@ ---- block/UID: description: Device Factory programmed 96-bit unique device identifier items: - - name: UID - description: Factory programmed 96-bit unique device identifier word 0 - array: - len: 3 - stride: 4 - byte_offset: 0 - access: Read + - name: UID + description: Factory programmed 96-bit unique device identifier word 0 + array: + len: 3 + stride: 4 + byte_offset: 0 + access: Read diff --git a/data/registers/usart_v1.yaml b/data/registers/usart_v1.yaml index 5887ffe..64bcf56 100644 --- a/data/registers/usart_v1.yaml +++ b/data/registers/usart_v1.yaml @@ -1,365 +1,364 @@ ---- block/UART: description: Universal asynchronous receiver transmitter items: - - name: SR - description: Status register - byte_offset: 0 - fieldset: SR - - name: DR - description: Data register - byte_offset: 4 - fieldset: DR - - name: BRR - description: Baud rate register - byte_offset: 8 - fieldset: BRR - - name: CR1 - description: Control register 1 - byte_offset: 12 - fieldset: CR1 - - name: CR2 - description: Control register 2 - byte_offset: 16 - fieldset: CR2 - - name: CR3 - description: Control register 3 - byte_offset: 20 - fieldset: CR3 + - name: SR + description: Status register + byte_offset: 0 + fieldset: SR + - name: DR + description: Data register + byte_offset: 4 + fieldset: DR + - name: BRR + description: Baud rate register + byte_offset: 8 + fieldset: BRR + - name: CR1 + description: Control register 1 + byte_offset: 12 + fieldset: CR1 + - name: CR2 + description: Control register 2 + byte_offset: 16 + fieldset: CR2 + - name: CR3 + description: Control register 3 + byte_offset: 20 + fieldset: CR3 block/USART: extends: UART description: Universal synchronous asynchronous receiver transmitter items: - - name: CR2 - description: Control register 2 - byte_offset: 16 - fieldset: CR2_USART - - name: CR3 - description: Control register 3 - byte_offset: 20 - fieldset: CR3_USART - - name: GTPR - description: Guard time and prescaler register - byte_offset: 24 - fieldset: GTPR + - name: CR2 + description: Control register 2 + byte_offset: 16 + fieldset: CR2_USART + - name: CR3 + description: Control register 3 + byte_offset: 20 + fieldset: CR3_USART + - name: GTPR + description: Guard time and prescaler register + byte_offset: 24 + fieldset: GTPR fieldset/BRR: description: Baud rate register fields: - - name: BRR - description: USARTDIV - bit_offset: 0 - bit_size: 16 + - name: BRR + description: USARTDIV + bit_offset: 0 + bit_size: 16 fieldset/CR1: description: Control register 1 fields: - - name: SBK - description: Send break - bit_offset: 0 - bit_size: 1 - - name: RWU - description: Receiver wakeup - bit_offset: 1 - bit_size: 1 - enum: RWU - - name: RE - description: Receiver enable - bit_offset: 2 - bit_size: 1 - - name: TE - description: Transmitter enable - bit_offset: 3 - bit_size: 1 - - name: IDLEIE - description: IDLE interrupt enable - bit_offset: 4 - bit_size: 1 - - name: RXNEIE - description: RXNE interrupt enable - bit_offset: 5 - bit_size: 1 - - name: TCIE - description: Transmission complete interrupt enable - bit_offset: 6 - bit_size: 1 - - name: TXEIE - description: TXE interrupt enable - bit_offset: 7 - bit_size: 1 - - name: PEIE - description: PE interrupt enable - bit_offset: 8 - bit_size: 1 - - name: PS - description: Parity selection - bit_offset: 9 - bit_size: 1 - enum: PS - - name: PCE - description: Parity control enable - bit_offset: 10 - bit_size: 1 - - name: WAKE - description: Receiver wakeup method - bit_offset: 11 - bit_size: 1 - enum: WAKE - - name: M0 - description: Word length - bit_offset: 12 - bit_size: 1 - enum: M0 - - name: UE - description: USART enable - bit_offset: 13 - bit_size: 1 + - name: SBK + description: Send break + bit_offset: 0 + bit_size: 1 + - name: RWU + description: Receiver wakeup + bit_offset: 1 + bit_size: 1 + enum: RWU + - name: RE + description: Receiver enable + bit_offset: 2 + bit_size: 1 + - name: TE + description: Transmitter enable + bit_offset: 3 + bit_size: 1 + - name: IDLEIE + description: IDLE interrupt enable + bit_offset: 4 + bit_size: 1 + - name: RXNEIE + description: RXNE interrupt enable + bit_offset: 5 + bit_size: 1 + - name: TCIE + description: Transmission complete interrupt enable + bit_offset: 6 + bit_size: 1 + - name: TXEIE + description: TXE interrupt enable + bit_offset: 7 + bit_size: 1 + - name: PEIE + description: PE interrupt enable + bit_offset: 8 + bit_size: 1 + - name: PS + description: Parity selection + bit_offset: 9 + bit_size: 1 + enum: PS + - name: PCE + description: Parity control enable + bit_offset: 10 + bit_size: 1 + - name: WAKE + description: Receiver wakeup method + bit_offset: 11 + bit_size: 1 + enum: WAKE + - name: M0 + description: Word length + bit_offset: 12 + bit_size: 1 + enum: M0 + - name: UE + description: USART enable + bit_offset: 13 + bit_size: 1 fieldset/CR2: description: Control register 2 fields: - - name: ADD - description: Address of the USART node - bit_offset: 0 - bit_size: 4 - - name: LBDL - description: Line break detection length - bit_offset: 5 - bit_size: 1 - enum: LBDL - - name: LBDIE - description: LIN break detection interrupt enable - bit_offset: 6 - bit_size: 1 - - name: STOP - description: STOP bits - bit_offset: 12 - bit_size: 2 - enum: STOP - - name: LINEN - description: LIN mode enable - bit_offset: 14 - bit_size: 1 + - name: ADD + description: Address of the USART node + bit_offset: 0 + bit_size: 4 + - name: LBDL + description: Line break detection length + bit_offset: 5 + bit_size: 1 + enum: LBDL + - name: LBDIE + description: LIN break detection interrupt enable + bit_offset: 6 + bit_size: 1 + - name: STOP + description: STOP bits + bit_offset: 12 + bit_size: 2 + enum: STOP + - name: LINEN + description: LIN mode enable + bit_offset: 14 + bit_size: 1 fieldset/CR2_USART: extends: CR2 description: Control register 2 fields: - - name: LBCL - description: Last bit clock pulse - bit_offset: 8 - bit_size: 1 - - name: CPHA - description: Clock phase - bit_offset: 9 - bit_size: 1 - enum: CPHA - - name: CPOL - description: Clock polarity - bit_offset: 10 - bit_size: 1 - enum: CPOL - - name: CLKEN - description: Clock enable - bit_offset: 11 - bit_size: 1 + - name: LBCL + description: Last bit clock pulse + bit_offset: 8 + bit_size: 1 + - name: CPHA + description: Clock phase + bit_offset: 9 + bit_size: 1 + enum: CPHA + - name: CPOL + description: Clock polarity + bit_offset: 10 + bit_size: 1 + enum: CPOL + - name: CLKEN + description: Clock enable + bit_offset: 11 + bit_size: 1 fieldset/CR3: description: Control register 3 fields: - - name: EIE - description: Error interrupt enable - bit_offset: 0 - bit_size: 1 - - name: IREN - description: IrDA mode enable - bit_offset: 1 - bit_size: 1 - - name: IRLP - description: IrDA low-power - bit_offset: 2 - bit_size: 1 - enum: IRLP - - name: HDSEL - description: Half-duplex selection - bit_offset: 3 - bit_size: 1 - - name: DMAR - description: DMA enable receiver - bit_offset: 6 - bit_size: 1 - - name: DMAT - description: DMA enable transmitter - bit_offset: 7 - bit_size: 1 + - name: EIE + description: Error interrupt enable + bit_offset: 0 + bit_size: 1 + - name: IREN + description: IrDA mode enable + bit_offset: 1 + bit_size: 1 + - name: IRLP + description: IrDA low-power + bit_offset: 2 + bit_size: 1 + enum: IRLP + - name: HDSEL + description: Half-duplex selection + bit_offset: 3 + bit_size: 1 + - name: DMAR + description: DMA enable receiver + bit_offset: 6 + bit_size: 1 + - name: DMAT + description: DMA enable transmitter + bit_offset: 7 + bit_size: 1 fieldset/CR3_USART: extends: CR3 description: Control register 3 fields: - - name: NACK - description: Smartcard NACK enable - bit_offset: 4 - bit_size: 1 - - name: SCEN - description: Smartcard mode enable - bit_offset: 5 - bit_size: 1 - - name: RTSE - description: RTS enable - bit_offset: 8 - bit_size: 1 - - name: CTSE - description: CTS enable - bit_offset: 9 - bit_size: 1 - - name: CTSIE - description: CTS interrupt enable - bit_offset: 10 - bit_size: 1 + - name: NACK + description: Smartcard NACK enable + bit_offset: 4 + bit_size: 1 + - name: SCEN + description: Smartcard mode enable + bit_offset: 5 + bit_size: 1 + - name: RTSE + description: RTS enable + bit_offset: 8 + bit_size: 1 + - name: CTSE + description: CTS enable + bit_offset: 9 + bit_size: 1 + - name: CTSIE + description: CTS interrupt enable + bit_offset: 10 + bit_size: 1 fieldset/DR: description: Data register fields: - - name: DR - description: Data value - bit_offset: 0 - bit_size: 9 + - name: DR + description: Data value + bit_offset: 0 + bit_size: 9 fieldset/GTPR: description: Guard time and prescaler register fields: - - name: PSC - description: Prescaler value - bit_offset: 0 - bit_size: 8 - - name: GT - description: Guard time value - bit_offset: 8 - bit_size: 8 + - name: PSC + description: Prescaler value + bit_offset: 0 + bit_size: 8 + - name: GT + description: Guard time value + bit_offset: 8 + bit_size: 8 fieldset/SR: description: Status register fields: - - name: PE - description: Parity error - bit_offset: 0 - bit_size: 1 - - name: FE - description: Framing error - bit_offset: 1 - bit_size: 1 - - name: NE - description: Noise error flag - bit_offset: 2 - bit_size: 1 - - name: ORE - description: Overrun error - bit_offset: 3 - bit_size: 1 - - name: IDLE - description: Idle line detected - bit_offset: 4 - bit_size: 1 - - name: RXNE - description: Read data register not empty - bit_offset: 5 - bit_size: 1 - - name: TC - description: Transmission complete - bit_offset: 6 - bit_size: 1 - - name: TXE - description: Transmit data register empty - bit_offset: 7 - bit_size: 1 - - name: LBD - description: LIN break detection flag - bit_offset: 8 - bit_size: 1 + - name: PE + description: Parity error + bit_offset: 0 + bit_size: 1 + - name: FE + description: Framing error + bit_offset: 1 + bit_size: 1 + - name: NE + description: Noise error flag + bit_offset: 2 + bit_size: 1 + - name: ORE + description: Overrun error + bit_offset: 3 + bit_size: 1 + - name: IDLE + description: Idle line detected + bit_offset: 4 + bit_size: 1 + - name: RXNE + description: Read data register not empty + bit_offset: 5 + bit_size: 1 + - name: TC + description: Transmission complete + bit_offset: 6 + bit_size: 1 + - name: TXE + description: Transmit data register empty + bit_offset: 7 + bit_size: 1 + - name: LBD + description: LIN break detection flag + bit_offset: 8 + bit_size: 1 fieldset/SR_USART: extends: SR description: Status register fields: - - name: CTS - description: CTS flag - bit_offset: 9 - bit_size: 1 + - name: CTS + description: CTS flag + bit_offset: 9 + bit_size: 1 enum/CPHA: bit_size: 1 variants: - - name: First - description: The first clock transition is the first data capture edge - value: 0 - - name: Second - description: The second clock transition is the first data capture edge - value: 1 + - name: First + description: The first clock transition is the first data capture edge + value: 0 + - name: Second + description: The second clock transition is the first data capture edge + value: 1 enum/CPOL: bit_size: 1 variants: - - name: Low - description: Steady low value on CK pin outside transmission window - value: 0 - - name: High - description: Steady high value on CK pin outside transmission window - value: 1 + - name: Low + description: Steady low value on CK pin outside transmission window + value: 0 + - name: High + description: Steady high value on CK pin outside transmission window + value: 1 enum/IRLP: bit_size: 1 variants: - - name: Normal - description: Normal mode - value: 0 - - name: LowPower - description: Low-power mode - value: 1 + - name: Normal + description: Normal mode + value: 0 + - name: LowPower + description: Low-power mode + value: 1 enum/LBDL: bit_size: 1 variants: - - name: Bit10 - description: 10-bit break detection - value: 0 - - name: Bit11 - description: 11-bit break detection - value: 1 + - name: Bit10 + description: 10-bit break detection + value: 0 + - name: Bit11 + description: 11-bit break detection + value: 1 enum/M0: bit_size: 1 variants: - - name: Bit8 - description: "1 start bit, 8 data bits, n stop bits" - value: 0 - - name: Bit9 - description: "1 start bit, 9 data bits, n stop bits" - value: 1 + - name: Bit8 + description: 1 start bit, 8 data bits, n stop bits + value: 0 + - name: Bit9 + description: 1 start bit, 9 data bits, n stop bits + value: 1 enum/PS: bit_size: 1 variants: - - name: Even - description: Even parity - value: 0 - - name: Odd - description: Odd parity - value: 1 + - name: Even + description: Even parity + value: 0 + - name: Odd + description: Odd parity + value: 1 enum/RWU: bit_size: 1 variants: - - name: Active - description: Receiver in active mode - value: 0 - - name: Mute - description: Receiver in mute mode - value: 1 + - name: Active + description: Receiver in active mode + value: 0 + - name: Mute + description: Receiver in mute mode + value: 1 enum/STOP: bit_size: 2 variants: - - name: Stop1 - description: 1 stop bit - value: 0 - - name: Stop0p5 - description: 0.5 stop bits - value: 1 - - name: Stop2 - description: 2 stop bits - value: 2 - - name: Stop1p5 - description: 1.5 stop bits - value: 3 + - name: Stop1 + description: 1 stop bit + value: 0 + - name: Stop0p5 + description: 0.5 stop bits + value: 1 + - name: Stop2 + description: 2 stop bits + value: 2 + - name: Stop1p5 + description: 1.5 stop bits + value: 3 enum/WAKE: bit_size: 1 variants: - - name: IdleLine - description: USART wakeup on idle line - value: 0 - - name: AddressMark - description: USART wakeup on address mark - value: 1 + - name: IdleLine + description: USART wakeup on idle line + value: 0 + - name: AddressMark + description: USART wakeup on address mark + value: 1 diff --git a/data/registers/usart_v2.yaml b/data/registers/usart_v2.yaml index 99f8949..c8c04e6 100644 --- a/data/registers/usart_v2.yaml +++ b/data/registers/usart_v2.yaml @@ -1,383 +1,382 @@ ---- block/UART: description: Universal asynchronous receiver transmitter items: - - name: SR - description: Status register - byte_offset: 0 - fieldset: SR - - name: DR - description: Data register - byte_offset: 4 - fieldset: DR - - name: BRR - description: Baud rate register - byte_offset: 8 - fieldset: BRR - - name: CR1 - description: Control register 1 - byte_offset: 12 - fieldset: CR1 - - name: CR2 - description: Control register 2 - byte_offset: 16 - fieldset: CR2 - - name: CR3 - description: Control register 3 - byte_offset: 20 - fieldset: CR3 + - name: SR + description: Status register + byte_offset: 0 + fieldset: SR + - name: DR + description: Data register + byte_offset: 4 + fieldset: DR + - name: BRR + description: Baud rate register + byte_offset: 8 + fieldset: BRR + - name: CR1 + description: Control register 1 + byte_offset: 12 + fieldset: CR1 + - name: CR2 + description: Control register 2 + byte_offset: 16 + fieldset: CR2 + - name: CR3 + description: Control register 3 + byte_offset: 20 + fieldset: CR3 block/USART: extends: UART description: Universal synchronous asynchronous receiver transmitter items: - - name: CR2 - description: Control register 2 - byte_offset: 16 - fieldset: CR2_USART - - name: CR3 - description: Control register 3 - byte_offset: 20 - fieldset: CR3_USART - - name: GTPR - description: Guard time and prescaler register - byte_offset: 24 - fieldset: GTPR + - name: CR2 + description: Control register 2 + byte_offset: 16 + fieldset: CR2_USART + - name: CR3 + description: Control register 3 + byte_offset: 20 + fieldset: CR3_USART + - name: GTPR + description: Guard time and prescaler register + byte_offset: 24 + fieldset: GTPR fieldset/BRR: description: Baud rate register fields: - - name: BRR - description: USARTDIV - bit_offset: 0 - bit_size: 16 + - name: BRR + description: USARTDIV + bit_offset: 0 + bit_size: 16 fieldset/CR1: description: Control register 1 fields: - - name: SBK - description: Send break - bit_offset: 0 - bit_size: 1 - - name: RWU - description: Receiver wakeup - bit_offset: 1 - bit_size: 1 - enum: RWU - - name: RE - description: Receiver enable - bit_offset: 2 - bit_size: 1 - - name: TE - description: Transmitter enable - bit_offset: 3 - bit_size: 1 - - name: IDLEIE - description: IDLE interrupt enable - bit_offset: 4 - bit_size: 1 - - name: RXNEIE - description: RXNE interrupt enable - bit_offset: 5 - bit_size: 1 - - name: TCIE - description: Transmission complete interrupt enable - bit_offset: 6 - bit_size: 1 - - name: TXEIE - description: TXE interrupt enable - bit_offset: 7 - bit_size: 1 - - name: PEIE - description: PE interrupt enable - bit_offset: 8 - bit_size: 1 - - name: PS - description: Parity selection - bit_offset: 9 - bit_size: 1 - enum: PS - - name: PCE - description: Parity control enable - bit_offset: 10 - bit_size: 1 - - name: WAKE - description: Receiver wakeup method - bit_offset: 11 - bit_size: 1 - enum: WAKE - - name: M0 - description: Word length - bit_offset: 12 - bit_size: 1 - enum: M0 - - name: UE - description: USART enable - bit_offset: 13 - bit_size: 1 - - name: OVER8 - description: Oversampling mode - bit_offset: 15 - bit_size: 1 - enum: OVER8 + - name: SBK + description: Send break + bit_offset: 0 + bit_size: 1 + - name: RWU + description: Receiver wakeup + bit_offset: 1 + bit_size: 1 + enum: RWU + - name: RE + description: Receiver enable + bit_offset: 2 + bit_size: 1 + - name: TE + description: Transmitter enable + bit_offset: 3 + bit_size: 1 + - name: IDLEIE + description: IDLE interrupt enable + bit_offset: 4 + bit_size: 1 + - name: RXNEIE + description: RXNE interrupt enable + bit_offset: 5 + bit_size: 1 + - name: TCIE + description: Transmission complete interrupt enable + bit_offset: 6 + bit_size: 1 + - name: TXEIE + description: TXE interrupt enable + bit_offset: 7 + bit_size: 1 + - name: PEIE + description: PE interrupt enable + bit_offset: 8 + bit_size: 1 + - name: PS + description: Parity selection + bit_offset: 9 + bit_size: 1 + enum: PS + - name: PCE + description: Parity control enable + bit_offset: 10 + bit_size: 1 + - name: WAKE + description: Receiver wakeup method + bit_offset: 11 + bit_size: 1 + enum: WAKE + - name: M0 + description: Word length + bit_offset: 12 + bit_size: 1 + enum: M0 + - name: UE + description: USART enable + bit_offset: 13 + bit_size: 1 + - name: OVER8 + description: Oversampling mode + bit_offset: 15 + bit_size: 1 + enum: OVER8 fieldset/CR2: description: Control register 2 fields: - - name: ADD - description: Address of the USART node - bit_offset: 0 - bit_size: 4 - - name: LBDL - description: Line break detection length - bit_offset: 5 - bit_size: 1 - enum: LBDL - - name: LBDIE - description: LIN break detection interrupt enable - bit_offset: 6 - bit_size: 1 - - name: STOP - description: STOP bits - bit_offset: 12 - bit_size: 2 - enum: STOP - - name: LINEN - description: LIN mode enable - bit_offset: 14 - bit_size: 1 + - name: ADD + description: Address of the USART node + bit_offset: 0 + bit_size: 4 + - name: LBDL + description: Line break detection length + bit_offset: 5 + bit_size: 1 + enum: LBDL + - name: LBDIE + description: LIN break detection interrupt enable + bit_offset: 6 + bit_size: 1 + - name: STOP + description: STOP bits + bit_offset: 12 + bit_size: 2 + enum: STOP + - name: LINEN + description: LIN mode enable + bit_offset: 14 + bit_size: 1 fieldset/CR2_USART: extends: CR2 description: Control register 2 fields: - - name: LBCL - description: Last bit clock pulse - bit_offset: 8 - bit_size: 1 - - name: CPHA - description: Clock phase - bit_offset: 9 - bit_size: 1 - enum: CPHA - - name: CPOL - description: Clock polarity - bit_offset: 10 - bit_size: 1 - enum: CPOL - - name: CLKEN - description: Clock enable - bit_offset: 11 - bit_size: 1 + - name: LBCL + description: Last bit clock pulse + bit_offset: 8 + bit_size: 1 + - name: CPHA + description: Clock phase + bit_offset: 9 + bit_size: 1 + enum: CPHA + - name: CPOL + description: Clock polarity + bit_offset: 10 + bit_size: 1 + enum: CPOL + - name: CLKEN + description: Clock enable + bit_offset: 11 + bit_size: 1 fieldset/CR3: description: Control register 3 fields: - - name: EIE - description: Error interrupt enable - bit_offset: 0 - bit_size: 1 - - name: IREN - description: IrDA mode enable - bit_offset: 1 - bit_size: 1 - - name: IRLP - description: IrDA low-power - bit_offset: 2 - bit_size: 1 - enum: IRLP - - name: HDSEL - description: Half-duplex selection - bit_offset: 3 - bit_size: 1 - - name: DMAR - description: DMA enable receiver - bit_offset: 6 - bit_size: 1 - - name: DMAT - description: DMA enable transmitter - bit_offset: 7 - bit_size: 1 + - name: EIE + description: Error interrupt enable + bit_offset: 0 + bit_size: 1 + - name: IREN + description: IrDA mode enable + bit_offset: 1 + bit_size: 1 + - name: IRLP + description: IrDA low-power + bit_offset: 2 + bit_size: 1 + enum: IRLP + - name: HDSEL + description: Half-duplex selection + bit_offset: 3 + bit_size: 1 + - name: DMAR + description: DMA enable receiver + bit_offset: 6 + bit_size: 1 + - name: DMAT + description: DMA enable transmitter + bit_offset: 7 + bit_size: 1 fieldset/CR3_USART: extends: CR3 description: Control register 3 fields: - - name: NACK - description: Smartcard NACK enable - bit_offset: 4 - bit_size: 1 - - name: SCEN - description: Smartcard mode enable - bit_offset: 5 - bit_size: 1 - - name: RTSE - description: RTS enable - bit_offset: 8 - bit_size: 1 - - name: CTSE - description: CTS enable - bit_offset: 9 - bit_size: 1 - - name: CTSIE - description: CTS interrupt enable - bit_offset: 10 - bit_size: 1 - - name: ONEBIT - description: One sample bit method enable - bit_offset: 11 - bit_size: 1 + - name: NACK + description: Smartcard NACK enable + bit_offset: 4 + bit_size: 1 + - name: SCEN + description: Smartcard mode enable + bit_offset: 5 + bit_size: 1 + - name: RTSE + description: RTS enable + bit_offset: 8 + bit_size: 1 + - name: CTSE + description: CTS enable + bit_offset: 9 + bit_size: 1 + - name: CTSIE + description: CTS interrupt enable + bit_offset: 10 + bit_size: 1 + - name: ONEBIT + description: One sample bit method enable + bit_offset: 11 + bit_size: 1 fieldset/DR: description: Data register fields: - - name: DR - description: Data value - bit_offset: 0 - bit_size: 9 + - name: DR + description: Data value + bit_offset: 0 + bit_size: 9 fieldset/GTPR: description: Guard time and prescaler register fields: - - name: PSC - description: Prescaler value - bit_offset: 0 - bit_size: 8 - - name: GT - description: Guard time value - bit_offset: 8 - bit_size: 8 + - name: PSC + description: Prescaler value + bit_offset: 0 + bit_size: 8 + - name: GT + description: Guard time value + bit_offset: 8 + bit_size: 8 fieldset/SR: description: Status register fields: - - name: PE - description: Parity error - bit_offset: 0 - bit_size: 1 - - name: FE - description: Framing error - bit_offset: 1 - bit_size: 1 - - name: NE - description: Noise error flag - bit_offset: 2 - bit_size: 1 - - name: ORE - description: Overrun error - bit_offset: 3 - bit_size: 1 - - name: IDLE - description: Idle line detected - bit_offset: 4 - bit_size: 1 - - name: RXNE - description: Read data register not empty - bit_offset: 5 - bit_size: 1 - - name: TC - description: Transmission complete - bit_offset: 6 - bit_size: 1 - - name: TXE - description: Transmit data register empty - bit_offset: 7 - bit_size: 1 - - name: LBD - description: LIN break detection flag - bit_offset: 8 - bit_size: 1 + - name: PE + description: Parity error + bit_offset: 0 + bit_size: 1 + - name: FE + description: Framing error + bit_offset: 1 + bit_size: 1 + - name: NE + description: Noise error flag + bit_offset: 2 + bit_size: 1 + - name: ORE + description: Overrun error + bit_offset: 3 + bit_size: 1 + - name: IDLE + description: Idle line detected + bit_offset: 4 + bit_size: 1 + - name: RXNE + description: Read data register not empty + bit_offset: 5 + bit_size: 1 + - name: TC + description: Transmission complete + bit_offset: 6 + bit_size: 1 + - name: TXE + description: Transmit data register empty + bit_offset: 7 + bit_size: 1 + - name: LBD + description: LIN break detection flag + bit_offset: 8 + bit_size: 1 fieldset/SR_USART: extends: SR description: Status register fields: - - name: CTS - description: CTS flag - bit_offset: 9 - bit_size: 1 + - name: CTS + description: CTS flag + bit_offset: 9 + bit_size: 1 enum/CPHA: bit_size: 1 variants: - - name: First - description: The first clock transition is the first data capture edge - value: 0 - - name: Second - description: The second clock transition is the first data capture edge - value: 1 + - name: First + description: The first clock transition is the first data capture edge + value: 0 + - name: Second + description: The second clock transition is the first data capture edge + value: 1 enum/CPOL: bit_size: 1 variants: - - name: Low - description: Steady low value on CK pin outside transmission window - value: 0 - - name: High - description: Steady high value on CK pin outside transmission window - value: 1 + - name: Low + description: Steady low value on CK pin outside transmission window + value: 0 + - name: High + description: Steady high value on CK pin outside transmission window + value: 1 enum/IRLP: bit_size: 1 variants: - - name: Normal - description: Normal mode - value: 0 - - name: LowPower - description: Low-power mode - value: 1 + - name: Normal + description: Normal mode + value: 0 + - name: LowPower + description: Low-power mode + value: 1 enum/LBDL: bit_size: 1 variants: - - name: Bit10 - description: 10-bit break detection - value: 0 - - name: Bit11 - description: 11-bit break detection - value: 1 + - name: Bit10 + description: 10-bit break detection + value: 0 + - name: Bit11 + description: 11-bit break detection + value: 1 enum/M0: bit_size: 1 variants: - - name: Bit8 - description: "1 start bit, 8 data bits, n stop bits" - value: 0 - - name: Bit9 - description: "1 start bit, 9 data bits, n stop bits" - value: 1 + - name: Bit8 + description: 1 start bit, 8 data bits, n stop bits + value: 0 + - name: Bit9 + description: 1 start bit, 9 data bits, n stop bits + value: 1 enum/OVER8: bit_size: 1 variants: - - name: Oversampling16 - description: Oversampling by 16 - value: 0 - - name: Oversampling8 - description: Oversampling by 8 - value: 1 + - name: Oversampling16 + description: Oversampling by 16 + value: 0 + - name: Oversampling8 + description: Oversampling by 8 + value: 1 enum/PS: bit_size: 1 variants: - - name: Even - description: Even parity - value: 0 - - name: Odd - description: Odd parity - value: 1 + - name: Even + description: Even parity + value: 0 + - name: Odd + description: Odd parity + value: 1 enum/RWU: bit_size: 1 variants: - - name: Active - description: Receiver in active mode - value: 0 - - name: Mute - description: Receiver in mute mode - value: 1 + - name: Active + description: Receiver in active mode + value: 0 + - name: Mute + description: Receiver in mute mode + value: 1 enum/STOP: bit_size: 2 variants: - - name: Stop1 - description: 1 stop bit - value: 0 - - name: Stop0p5 - description: 0.5 stop bits - value: 1 - - name: Stop2 - description: 2 stop bits - value: 2 - - name: Stop1p5 - description: 1.5 stop bits - value: 3 + - name: Stop1 + description: 1 stop bit + value: 0 + - name: Stop0p5 + description: 0.5 stop bits + value: 1 + - name: Stop2 + description: 2 stop bits + value: 2 + - name: Stop1p5 + description: 1.5 stop bits + value: 3 enum/WAKE: bit_size: 1 variants: - - name: IdleLine - description: USART wakeup on idle line - value: 0 - - name: AddressMark - description: USART wakeup on address mark - value: 1 + - name: IdleLine + description: USART wakeup on idle line + value: 0 + - name: AddressMark + description: USART wakeup on address mark + value: 1 diff --git a/data/registers/usart_v3.yaml b/data/registers/usart_v3.yaml index b4a97c4..131db12 100644 --- a/data/registers/usart_v3.yaml +++ b/data/registers/usart_v3.yaml @@ -1,714 +1,713 @@ ---- block/LPUART: description: Low-power Universal synchronous asynchronous receiver transmitter items: - - name: CR1 - description: Control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Control register 2 - byte_offset: 4 - fieldset: CR2 - - name: CR3 - description: Control register 3 - byte_offset: 8 - fieldset: CR3 - - name: BRR - description: Baud rate register - byte_offset: 12 - fieldset: BRR - - name: RQR - description: Request register - byte_offset: 24 - access: Write - fieldset: RQR - - name: ISR - description: Interrupt & status register - byte_offset: 28 - access: Read - fieldset: ISR - - name: ICR - description: Interrupt flag clear register - byte_offset: 32 - access: Write - fieldset: ICR - - name: RDR - description: Receive data register - byte_offset: 36 - access: Read - fieldset: DR - - name: TDR - description: Transmit data register - byte_offset: 40 - access: Write - fieldset: DR + - name: CR1 + description: Control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: Control register 3 + byte_offset: 8 + fieldset: CR3 + - name: BRR + description: Baud rate register + byte_offset: 12 + fieldset: BRR + - name: RQR + description: Request register + byte_offset: 24 + access: Write + fieldset: RQR + - name: ISR + description: Interrupt & status register + byte_offset: 28 + access: Read + fieldset: ISR + - name: ICR + description: Interrupt flag clear register + byte_offset: 32 + access: Write + fieldset: ICR + - name: RDR + description: Receive data register + byte_offset: 36 + access: Read + fieldset: DR + - name: TDR + description: Transmit data register + byte_offset: 40 + access: Write + fieldset: DR block/USART: description: Universal synchronous asynchronous receiver transmitter items: - - name: CR1 - description: Control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Control register 2 - byte_offset: 4 - fieldset: CR2 - - name: CR3 - description: Control register 3 - byte_offset: 8 - fieldset: CR3 - - name: BRR - description: Baud rate register - byte_offset: 12 - fieldset: BRR - - name: GTPR - description: Guard time and prescaler register - byte_offset: 16 - fieldset: GTPR - - name: RTOR - description: Receiver timeout register - byte_offset: 20 - fieldset: RTOR - - name: RQR - description: Request register - byte_offset: 24 - access: Write - fieldset: RQR - - name: ISR - description: Interrupt & status register - byte_offset: 28 - access: Read - fieldset: ISR - - name: ICR - description: Interrupt flag clear register - byte_offset: 32 - access: Write - fieldset: ICR - - name: RDR - description: Receive data register - byte_offset: 36 - access: Read - fieldset: DR - - name: TDR - description: Transmit data register - byte_offset: 40 - access: Write - fieldset: DR + - name: CR1 + description: Control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: Control register 3 + byte_offset: 8 + fieldset: CR3 + - name: BRR + description: Baud rate register + byte_offset: 12 + fieldset: BRR + - name: GTPR + description: Guard time and prescaler register + byte_offset: 16 + fieldset: GTPR + - name: RTOR + description: Receiver timeout register + byte_offset: 20 + fieldset: RTOR + - name: RQR + description: Request register + byte_offset: 24 + access: Write + fieldset: RQR + - name: ISR + description: Interrupt & status register + byte_offset: 28 + access: Read + fieldset: ISR + - name: ICR + description: Interrupt flag clear register + byte_offset: 32 + access: Write + fieldset: ICR + - name: RDR + description: Receive data register + byte_offset: 36 + access: Read + fieldset: DR + - name: TDR + description: Transmit data register + byte_offset: 40 + access: Write + fieldset: DR fieldset/BRR: description: Baud rate register fields: - - name: BRR - description: USARTDIV - bit_offset: 0 - bit_size: 16 + - name: BRR + description: USARTDIV + bit_offset: 0 + bit_size: 16 fieldset/CR1: description: Control register 1 fields: - - name: UE - description: USART enable - bit_offset: 0 - bit_size: 1 - - name: UESM - description: USART enable in Stop mode - bit_offset: 1 - bit_size: 1 - - name: RE - description: Receiver enable - bit_offset: 2 - bit_size: 1 - - name: TE - description: Transmitter enable - bit_offset: 3 - bit_size: 1 - - name: IDLEIE - description: IDLE interrupt enable - bit_offset: 4 - bit_size: 1 - - name: RXNEIE - description: RXNE interrupt enable - bit_offset: 5 - bit_size: 1 - - name: TCIE - description: Transmission complete interrupt enable - bit_offset: 6 - bit_size: 1 - - name: TXEIE - description: TXE interrupt enable - bit_offset: 7 - bit_size: 1 - - name: PEIE - description: PE interrupt enable - bit_offset: 8 - bit_size: 1 - - name: PS - description: Parity selection - bit_offset: 9 - bit_size: 1 - enum: PS - - name: PCE - description: Parity control enable - bit_offset: 10 - bit_size: 1 - - name: WAKE - description: Receiver wakeup method - bit_offset: 11 - bit_size: 1 - enum: WAKE - - name: M0 - description: Word length - bit_offset: 12 - bit_size: 1 - enum: M0 - - name: MME - description: Mute mode enable - bit_offset: 13 - bit_size: 1 - - name: CMIE - description: Character match interrupt enable - bit_offset: 14 - bit_size: 1 - - name: OVER8 - description: Oversampling mode - bit_offset: 15 - bit_size: 1 - enum: OVER8 - - name: DEDT - description: Driver Enable deassertion time - bit_offset: 16 - bit_size: 5 - - name: DEAT - description: Driver Enable assertion time - bit_offset: 21 - bit_size: 5 - - name: RTOIE - description: Receiver timeout interrupt enable - bit_offset: 26 - bit_size: 1 - - name: EOBIE - description: End of Block interrupt enable - bit_offset: 27 - bit_size: 1 - - name: M1 - description: Word length - bit_offset: 28 - bit_size: 1 - enum: M1 + - name: UE + description: USART enable + bit_offset: 0 + bit_size: 1 + - name: UESM + description: USART enable in Stop mode + bit_offset: 1 + bit_size: 1 + - name: RE + description: Receiver enable + bit_offset: 2 + bit_size: 1 + - name: TE + description: Transmitter enable + bit_offset: 3 + bit_size: 1 + - name: IDLEIE + description: IDLE interrupt enable + bit_offset: 4 + bit_size: 1 + - name: RXNEIE + description: RXNE interrupt enable + bit_offset: 5 + bit_size: 1 + - name: TCIE + description: Transmission complete interrupt enable + bit_offset: 6 + bit_size: 1 + - name: TXEIE + description: TXE interrupt enable + bit_offset: 7 + bit_size: 1 + - name: PEIE + description: PE interrupt enable + bit_offset: 8 + bit_size: 1 + - name: PS + description: Parity selection + bit_offset: 9 + bit_size: 1 + enum: PS + - name: PCE + description: Parity control enable + bit_offset: 10 + bit_size: 1 + - name: WAKE + description: Receiver wakeup method + bit_offset: 11 + bit_size: 1 + enum: WAKE + - name: M0 + description: Word length + bit_offset: 12 + bit_size: 1 + enum: M0 + - name: MME + description: Mute mode enable + bit_offset: 13 + bit_size: 1 + - name: CMIE + description: Character match interrupt enable + bit_offset: 14 + bit_size: 1 + - name: OVER8 + description: Oversampling mode + bit_offset: 15 + bit_size: 1 + enum: OVER8 + - name: DEDT + description: Driver Enable deassertion time + bit_offset: 16 + bit_size: 5 + - name: DEAT + description: Driver Enable assertion time + bit_offset: 21 + bit_size: 5 + - name: RTOIE + description: Receiver timeout interrupt enable + bit_offset: 26 + bit_size: 1 + - name: EOBIE + description: End of Block interrupt enable + bit_offset: 27 + bit_size: 1 + - name: M1 + description: Word length + bit_offset: 28 + bit_size: 1 + enum: M1 fieldset/CR2: description: Control register 2 fields: - - name: ADDM - description: 7-bit Address Detection/4-bit Address Detection - bit_offset: 4 - bit_size: 1 - enum: ADDM - - name: LBDL - description: Line break detection length - bit_offset: 5 - bit_size: 1 - enum: LBDL - - name: LBDIE - description: LIN break detection interrupt enable - bit_offset: 6 - bit_size: 1 - - name: LBCL - description: Last bit clock pulse - bit_offset: 8 - bit_size: 1 - - name: CPHA - description: Clock phase - bit_offset: 9 - bit_size: 1 - enum: CPHA - - name: CPOL - description: Clock polarity - bit_offset: 10 - bit_size: 1 - enum: CPOL - - name: CLKEN - description: Clock enable - bit_offset: 11 - bit_size: 1 - - name: STOP - description: STOP bits - bit_offset: 12 - bit_size: 2 - enum: STOP - - name: LINEN - description: LIN mode enable - bit_offset: 14 - bit_size: 1 - - name: SWAP - description: Swap TX/RX pins - bit_offset: 15 - bit_size: 1 - - name: RXINV - description: RX pin active level inversion - bit_offset: 16 - bit_size: 1 - - name: TXINV - description: TX pin active level inversion - bit_offset: 17 - bit_size: 1 - - name: DATAINV - description: Binary data inversion - bit_offset: 18 - bit_size: 1 - - name: MSBFIRST - description: Most significant bit first - bit_offset: 19 - bit_size: 1 - enum: MSBFIRST - - name: ABREN - description: Auto baud rate enable - bit_offset: 20 - bit_size: 1 - - name: ABRMOD - description: Auto baud rate mode - bit_offset: 21 - bit_size: 2 - enum: ABRMOD - - name: RTOEN - description: Receiver timeout enable - bit_offset: 23 - bit_size: 1 - - name: ADD - description: Address of the USART node - bit_offset: 24 - bit_size: 8 + - name: ADDM + description: 7-bit Address Detection/4-bit Address Detection + bit_offset: 4 + bit_size: 1 + enum: ADDM + - name: LBDL + description: Line break detection length + bit_offset: 5 + bit_size: 1 + enum: LBDL + - name: LBDIE + description: LIN break detection interrupt enable + bit_offset: 6 + bit_size: 1 + - name: LBCL + description: Last bit clock pulse + bit_offset: 8 + bit_size: 1 + - name: CPHA + description: Clock phase + bit_offset: 9 + bit_size: 1 + enum: CPHA + - name: CPOL + description: Clock polarity + bit_offset: 10 + bit_size: 1 + enum: CPOL + - name: CLKEN + description: Clock enable + bit_offset: 11 + bit_size: 1 + - name: STOP + description: STOP bits + bit_offset: 12 + bit_size: 2 + enum: STOP + - name: LINEN + description: LIN mode enable + bit_offset: 14 + bit_size: 1 + - name: SWAP + description: Swap TX/RX pins + bit_offset: 15 + bit_size: 1 + - name: RXINV + description: RX pin active level inversion + bit_offset: 16 + bit_size: 1 + - name: TXINV + description: TX pin active level inversion + bit_offset: 17 + bit_size: 1 + - name: DATAINV + description: Binary data inversion + bit_offset: 18 + bit_size: 1 + - name: MSBFIRST + description: Most significant bit first + bit_offset: 19 + bit_size: 1 + enum: MSBFIRST + - name: ABREN + description: Auto baud rate enable + bit_offset: 20 + bit_size: 1 + - name: ABRMOD + description: Auto baud rate mode + bit_offset: 21 + bit_size: 2 + enum: ABRMOD + - name: RTOEN + description: Receiver timeout enable + bit_offset: 23 + bit_size: 1 + - name: ADD + description: Address of the USART node + bit_offset: 24 + bit_size: 8 fieldset/CR3: description: Control register 3 fields: - - name: EIE - description: Error interrupt enable - bit_offset: 0 - bit_size: 1 - - name: IREN - description: IrDA mode enable - bit_offset: 1 - bit_size: 1 - - name: IRLP - description: IrDA low-power - bit_offset: 2 - bit_size: 1 - enum: IRLP - - name: HDSEL - description: Half-duplex selection - bit_offset: 3 - bit_size: 1 - - name: NACK - description: Smartcard NACK enable - bit_offset: 4 - bit_size: 1 - - name: SCEN - description: Smartcard mode enable - bit_offset: 5 - bit_size: 1 - - name: DMAR - description: DMA enable receiver - bit_offset: 6 - bit_size: 1 - - name: DMAT - description: DMA enable transmitter - bit_offset: 7 - bit_size: 1 - - name: RTSE - description: RTS enable - bit_offset: 8 - bit_size: 1 - - name: CTSE - description: CTS enable - bit_offset: 9 - bit_size: 1 - - name: CTSIE - description: CTS interrupt enable - bit_offset: 10 - bit_size: 1 - - name: ONEBIT - description: One sample bit method enable - bit_offset: 11 - bit_size: 1 - - name: OVRDIS - description: Overrun Disable - bit_offset: 12 - bit_size: 1 - - name: DDRE - description: DMA Disable on Reception Error - bit_offset: 13 - bit_size: 1 - - name: DEM - description: Driver enable mode - bit_offset: 14 - bit_size: 1 - - name: DEP - description: Driver enable polarity selection - bit_offset: 15 - bit_size: 1 - enum: DEP - - name: SCARCNT - description: Smartcard auto-retry count - bit_offset: 17 - bit_size: 3 - - name: WUS - description: Wakeup from Stop mode interrupt flag selection - bit_offset: 20 - bit_size: 2 - enum: WUS - - name: WUFIE - description: Wakeup from Stop mode interrupt enable - bit_offset: 22 - bit_size: 1 + - name: EIE + description: Error interrupt enable + bit_offset: 0 + bit_size: 1 + - name: IREN + description: IrDA mode enable + bit_offset: 1 + bit_size: 1 + - name: IRLP + description: IrDA low-power + bit_offset: 2 + bit_size: 1 + enum: IRLP + - name: HDSEL + description: Half-duplex selection + bit_offset: 3 + bit_size: 1 + - name: NACK + description: Smartcard NACK enable + bit_offset: 4 + bit_size: 1 + - name: SCEN + description: Smartcard mode enable + bit_offset: 5 + bit_size: 1 + - name: DMAR + description: DMA enable receiver + bit_offset: 6 + bit_size: 1 + - name: DMAT + description: DMA enable transmitter + bit_offset: 7 + bit_size: 1 + - name: RTSE + description: RTS enable + bit_offset: 8 + bit_size: 1 + - name: CTSE + description: CTS enable + bit_offset: 9 + bit_size: 1 + - name: CTSIE + description: CTS interrupt enable + bit_offset: 10 + bit_size: 1 + - name: ONEBIT + description: One sample bit method enable + bit_offset: 11 + bit_size: 1 + - name: OVRDIS + description: Overrun Disable + bit_offset: 12 + bit_size: 1 + - name: DDRE + description: DMA Disable on Reception Error + bit_offset: 13 + bit_size: 1 + - name: DEM + description: Driver enable mode + bit_offset: 14 + bit_size: 1 + - name: DEP + description: Driver enable polarity selection + bit_offset: 15 + bit_size: 1 + enum: DEP + - name: SCARCNT + description: Smartcard auto-retry count + bit_offset: 17 + bit_size: 3 + - name: WUS + description: Wakeup from Stop mode interrupt flag selection + bit_offset: 20 + bit_size: 2 + enum: WUS + - name: WUFIE + description: Wakeup from Stop mode interrupt enable + bit_offset: 22 + bit_size: 1 fieldset/DR: description: Data register fields: - - name: DR - description: Data value - bit_offset: 0 - bit_size: 9 + - name: DR + description: Data value + bit_offset: 0 + bit_size: 9 fieldset/GTPR: description: Guard time and prescaler register fields: - - name: PSC - description: Prescaler value - bit_offset: 0 - bit_size: 8 - - name: GT - description: Guard time value - bit_offset: 8 - bit_size: 8 + - name: PSC + description: Prescaler value + bit_offset: 0 + bit_size: 8 + - name: GT + description: Guard time value + bit_offset: 8 + bit_size: 8 fieldset/ICR: description: Interrupt flag clear register fields: - - name: PE - description: Parity error clear flag - bit_offset: 0 - bit_size: 1 - - name: FE - description: Framing error clear flag - bit_offset: 1 - bit_size: 1 - - name: NE - description: Noise error clear flag - bit_offset: 2 - bit_size: 1 - - name: ORE - description: Overrun error clear flag - bit_offset: 3 - bit_size: 1 - - name: IDLE - description: Idle line detected clear flag - bit_offset: 4 - bit_size: 1 - - name: TC - description: Transmission complete clear flag - bit_offset: 6 - bit_size: 1 - - name: LBD - description: LIN break detection clear flag - bit_offset: 8 - bit_size: 1 - - name: CTS - description: CTS clear flag - bit_offset: 9 - bit_size: 1 - - name: RTOF - description: Receiver timeout clear flag - bit_offset: 11 - bit_size: 1 - - name: EOBF - description: End of block clear flag - bit_offset: 12 - bit_size: 1 - - name: CMF - description: Character match clear flag - bit_offset: 17 - bit_size: 1 - - name: WUF - description: Wakeup from Stop mode clear flag - bit_offset: 20 - bit_size: 1 + - name: PE + description: Parity error clear flag + bit_offset: 0 + bit_size: 1 + - name: FE + description: Framing error clear flag + bit_offset: 1 + bit_size: 1 + - name: NE + description: Noise error clear flag + bit_offset: 2 + bit_size: 1 + - name: ORE + description: Overrun error clear flag + bit_offset: 3 + bit_size: 1 + - name: IDLE + description: Idle line detected clear flag + bit_offset: 4 + bit_size: 1 + - name: TC + description: Transmission complete clear flag + bit_offset: 6 + bit_size: 1 + - name: LBD + description: LIN break detection clear flag + bit_offset: 8 + bit_size: 1 + - name: CTS + description: CTS clear flag + bit_offset: 9 + bit_size: 1 + - name: RTOF + description: Receiver timeout clear flag + bit_offset: 11 + bit_size: 1 + - name: EOBF + description: End of block clear flag + bit_offset: 12 + bit_size: 1 + - name: CMF + description: Character match clear flag + bit_offset: 17 + bit_size: 1 + - name: WUF + description: Wakeup from Stop mode clear flag + bit_offset: 20 + bit_size: 1 fieldset/ISR: description: Interrupt & status register fields: - - name: PE - description: Parity error - bit_offset: 0 - bit_size: 1 - - name: FE - description: Framing error - bit_offset: 1 - bit_size: 1 - - name: NE - description: Noise error flag - bit_offset: 2 - bit_size: 1 - - name: ORE - description: Overrun error - bit_offset: 3 - bit_size: 1 - - name: IDLE - description: Idle line detected - bit_offset: 4 - bit_size: 1 - - name: RXNE - description: Read data register not empty - bit_offset: 5 - bit_size: 1 - - name: TC - description: Transmission complete - bit_offset: 6 - bit_size: 1 - - name: TXE - description: Transmit data register empty - bit_offset: 7 - bit_size: 1 - - name: LBD - description: LIN break detection flag - bit_offset: 8 - bit_size: 1 - - name: CTSIF - description: CTS interrupt flag - bit_offset: 9 - bit_size: 1 - - name: CTS - description: CTS flag - bit_offset: 10 - bit_size: 1 - - name: RTOF - description: Receiver timeout - bit_offset: 11 - bit_size: 1 - - name: EOBF - description: End of block flag - bit_offset: 12 - bit_size: 1 - - name: ABRE - description: Auto baud rate error - bit_offset: 14 - bit_size: 1 - - name: ABRF - description: Auto baud rate flag - bit_offset: 15 - bit_size: 1 - - name: BUSY - description: Busy flag - bit_offset: 16 - bit_size: 1 - - name: CMF - description: character match flag - bit_offset: 17 - bit_size: 1 - - name: SBKF - description: Send break flag - bit_offset: 18 - bit_size: 1 - - name: RWU - description: Receiver wakeup from Mute mode - bit_offset: 19 - bit_size: 1 - enum: RWU - - name: WUF - description: Wakeup from Stop mode flag - bit_offset: 20 - bit_size: 1 - - name: TEACK - description: Transmit enable acknowledge flag - bit_offset: 21 - bit_size: 1 - - name: REACK - description: Receive enable acknowledge flag - bit_offset: 22 - bit_size: 1 + - name: PE + description: Parity error + bit_offset: 0 + bit_size: 1 + - name: FE + description: Framing error + bit_offset: 1 + bit_size: 1 + - name: NE + description: Noise error flag + bit_offset: 2 + bit_size: 1 + - name: ORE + description: Overrun error + bit_offset: 3 + bit_size: 1 + - name: IDLE + description: Idle line detected + bit_offset: 4 + bit_size: 1 + - name: RXNE + description: Read data register not empty + bit_offset: 5 + bit_size: 1 + - name: TC + description: Transmission complete + bit_offset: 6 + bit_size: 1 + - name: TXE + description: Transmit data register empty + bit_offset: 7 + bit_size: 1 + - name: LBD + description: LIN break detection flag + bit_offset: 8 + bit_size: 1 + - name: CTSIF + description: CTS interrupt flag + bit_offset: 9 + bit_size: 1 + - name: CTS + description: CTS flag + bit_offset: 10 + bit_size: 1 + - name: RTOF + description: Receiver timeout + bit_offset: 11 + bit_size: 1 + - name: EOBF + description: End of block flag + bit_offset: 12 + bit_size: 1 + - name: ABRE + description: Auto baud rate error + bit_offset: 14 + bit_size: 1 + - name: ABRF + description: Auto baud rate flag + bit_offset: 15 + bit_size: 1 + - name: BUSY + description: Busy flag + bit_offset: 16 + bit_size: 1 + - name: CMF + description: character match flag + bit_offset: 17 + bit_size: 1 + - name: SBKF + description: Send break flag + bit_offset: 18 + bit_size: 1 + - name: RWU + description: Receiver wakeup from Mute mode + bit_offset: 19 + bit_size: 1 + enum: RWU + - name: WUF + description: Wakeup from Stop mode flag + bit_offset: 20 + bit_size: 1 + - name: TEACK + description: Transmit enable acknowledge flag + bit_offset: 21 + bit_size: 1 + - name: REACK + description: Receive enable acknowledge flag + bit_offset: 22 + bit_size: 1 fieldset/RQR: description: Request register fields: - - name: ABRRQ - description: Auto baud rate request. Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame. - bit_offset: 0 - bit_size: 1 - - name: SBKRQ - description: "Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available" - bit_offset: 1 - bit_size: 1 - - name: MMRQ - description: Mute mode request. Puts the USART in mute mode and sets the RWU flag. - bit_offset: 2 - bit_size: 1 - - name: RXFRQ - description: "Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition" - bit_offset: 3 - bit_size: 1 - - name: TXFRQ - description: Transmit data flush request. Sets the TXE flags. This allows to discard the transmit data. - bit_offset: 4 - bit_size: 1 + - name: ABRRQ + description: Auto baud rate request. Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame. + bit_offset: 0 + bit_size: 1 + - name: SBKRQ + description: Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available + bit_offset: 1 + bit_size: 1 + - name: MMRQ + description: Mute mode request. Puts the USART in mute mode and sets the RWU flag. + bit_offset: 2 + bit_size: 1 + - name: RXFRQ + description: Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition + bit_offset: 3 + bit_size: 1 + - name: TXFRQ + description: Transmit data flush request. Sets the TXE flags. This allows to discard the transmit data. + bit_offset: 4 + bit_size: 1 fieldset/RTOR: description: Receiver timeout register fields: - - name: RTO - description: Receiver timeout value - bit_offset: 0 - bit_size: 24 - - name: BLEN - description: Block Length - bit_offset: 24 - bit_size: 8 + - name: RTO + description: Receiver timeout value + bit_offset: 0 + bit_size: 24 + - name: BLEN + description: Block Length + bit_offset: 24 + bit_size: 8 enum/ABRMOD: bit_size: 2 variants: - - name: Start - description: Measurement of the start bit is used to detect the baud rate - value: 0 - - name: Edge - description: Falling edge to falling edge measurement - value: 1 - - name: Frame7F - description: "0x7F frame detection" - value: 2 - - name: Frame55 - description: "0x55 frame detection" - value: 3 + - name: Start + description: Measurement of the start bit is used to detect the baud rate + value: 0 + - name: Edge + description: Falling edge to falling edge measurement + value: 1 + - name: Frame7F + description: 0x7F frame detection + value: 2 + - name: Frame55 + description: 0x55 frame detection + value: 3 enum/ADDM: bit_size: 1 variants: - - name: Bit4 - description: 4-bit address detection - value: 0 - - name: Bit7 - description: 7-bit address detection - value: 1 + - name: Bit4 + description: 4-bit address detection + value: 0 + - name: Bit7 + description: 7-bit address detection + value: 1 enum/CPHA: bit_size: 1 variants: - - name: First - description: The first clock transition is the first data capture edge - value: 0 - - name: Second - description: The second clock transition is the first data capture edge - value: 1 + - name: First + description: The first clock transition is the first data capture edge + value: 0 + - name: Second + description: The second clock transition is the first data capture edge + value: 1 enum/CPOL: bit_size: 1 variants: - - name: Low - description: Steady low value on CK pin outside transmission window - value: 0 - - name: High - description: Steady high value on CK pin outside transmission window - value: 1 + - name: Low + description: Steady low value on CK pin outside transmission window + value: 0 + - name: High + description: Steady high value on CK pin outside transmission window + value: 1 enum/DEP: bit_size: 1 variants: - - name: High - description: DE signal is active high - value: 0 - - name: Low - description: DE signal is active low - value: 1 + - name: High + description: DE signal is active high + value: 0 + - name: Low + description: DE signal is active low + value: 1 enum/IRLP: bit_size: 1 variants: - - name: Normal - description: Normal mode - value: 0 - - name: LowPower - description: Low-power mode - value: 1 + - name: Normal + description: Normal mode + value: 0 + - name: LowPower + description: Low-power mode + value: 1 enum/LBDL: bit_size: 1 variants: - - name: Bit10 - description: 10-bit break detection - value: 0 - - name: Bit11 - description: 11-bit break detection - value: 1 + - name: Bit10 + description: 10-bit break detection + value: 0 + - name: Bit11 + description: 11-bit break detection + value: 1 enum/M0: bit_size: 1 variants: - - name: Bit8 - description: "1 start bit, 8 data bits, n stop bits" - value: 0 - - name: Bit9 - description: "1 start bit, 9 data bits, n stop bits" - value: 1 + - name: Bit8 + description: 1 start bit, 8 data bits, n stop bits + value: 0 + - name: Bit9 + description: 1 start bit, 9 data bits, n stop bits + value: 1 enum/M1: bit_size: 1 variants: - - name: M0 - description: Use M0 to set the data bits - value: 0 - - name: Bit7 - description: "1 start bit, 7 data bits, n stop bits" - value: 1 + - name: M0 + description: Use M0 to set the data bits + value: 0 + - name: Bit7 + description: 1 start bit, 7 data bits, n stop bits + value: 1 enum/MSBFIRST: bit_size: 1 variants: - - name: LSB - description: "data is transmitted/received with data bit 0 first, following the start bit" - value: 0 - - name: MSB - description: "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit" - value: 1 + - name: LSB + description: data is transmitted/received with data bit 0 first, following the start bit + value: 0 + - name: MSB + description: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit + value: 1 enum/OVER8: bit_size: 1 variants: - - name: Oversampling16 - description: Oversampling by 16 - value: 0 - - name: Oversampling8 - description: Oversampling by 8 - value: 1 + - name: Oversampling16 + description: Oversampling by 16 + value: 0 + - name: Oversampling8 + description: Oversampling by 8 + value: 1 enum/PS: bit_size: 1 variants: - - name: Even - description: Even parity - value: 0 - - name: Odd - description: Odd parity - value: 1 + - name: Even + description: Even parity + value: 0 + - name: Odd + description: Odd parity + value: 1 enum/RWU: bit_size: 1 variants: - - name: Active - description: Receiver in active mode - value: 0 - - name: Mute - description: Receiver in mute mode - value: 1 + - name: Active + description: Receiver in active mode + value: 0 + - name: Mute + description: Receiver in mute mode + value: 1 enum/STOP: bit_size: 2 variants: - - name: Stop1 - description: 1 stop bit - value: 0 - - name: Stop0p5 - description: 0.5 stop bits - value: 1 - - name: Stop2 - description: 2 stop bits - value: 2 - - name: Stop1p5 - description: 1.5 stop bits - value: 3 + - name: Stop1 + description: 1 stop bit + value: 0 + - name: Stop0p5 + description: 0.5 stop bits + value: 1 + - name: Stop2 + description: 2 stop bits + value: 2 + - name: Stop1p5 + description: 1.5 stop bits + value: 3 enum/WAKE: bit_size: 1 variants: - - name: IdleLine - description: USART wakeup on idle line - value: 0 - - name: AddressMark - description: USART wakeup on address mark - value: 1 + - name: IdleLine + description: USART wakeup on idle line + value: 0 + - name: AddressMark + description: USART wakeup on address mark + value: 1 enum/WUS: bit_size: 2 variants: - - name: Address - description: WUF active on address match - value: 0 - - name: Start - description: WuF active on Start bit detection - value: 2 - - name: RXNE - description: WUF active on RXNE - value: 3 + - name: Address + description: WUF active on address match + value: 0 + - name: Start + description: WuF active on Start bit detection + value: 2 + - name: RXNE + description: WUF active on RXNE + value: 3 diff --git a/data/registers/usart_v4.yaml b/data/registers/usart_v4.yaml index 6f1351b..f0fdb08 100644 --- a/data/registers/usart_v4.yaml +++ b/data/registers/usart_v4.yaml @@ -1,813 +1,812 @@ ---- block/LPUART: description: Low-power Universal synchronous asynchronous receiver transmitter items: - - name: CR1 - description: Control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Control register 2 - byte_offset: 4 - fieldset: CR2 - - name: CR3 - description: Control register 3 - byte_offset: 8 - fieldset: CR3 - - name: BRR - description: Baud rate register - byte_offset: 12 - fieldset: BRR - - name: RQR - description: Request register - byte_offset: 24 - access: Write - fieldset: RQR - - name: ISR - description: Interrupt & status register - byte_offset: 28 - access: Read - fieldset: ISR - - name: ICR - description: Interrupt flag clear register - byte_offset: 32 - access: Write - fieldset: ICR - - name: RDR - description: Receive data register - byte_offset: 36 - access: Read - fieldset: DR - - name: TDR - description: Transmit data register - byte_offset: 40 - access: Write - fieldset: DR - - name: PRESC - description: Prescaler register - byte_offset: 44 - fieldset: PRESC + - name: CR1 + description: Control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: Control register 3 + byte_offset: 8 + fieldset: CR3 + - name: BRR + description: Baud rate register + byte_offset: 12 + fieldset: BRR + - name: RQR + description: Request register + byte_offset: 24 + access: Write + fieldset: RQR + - name: ISR + description: Interrupt & status register + byte_offset: 28 + access: Read + fieldset: ISR + - name: ICR + description: Interrupt flag clear register + byte_offset: 32 + access: Write + fieldset: ICR + - name: RDR + description: Receive data register + byte_offset: 36 + access: Read + fieldset: DR + - name: TDR + description: Transmit data register + byte_offset: 40 + access: Write + fieldset: DR + - name: PRESC + description: Prescaler register + byte_offset: 44 + fieldset: PRESC block/USART: description: Universal synchronous asynchronous receiver transmitter items: - - name: CR1 - description: Control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Control register 2 - byte_offset: 4 - fieldset: CR2 - - name: CR3 - description: Control register 3 - byte_offset: 8 - fieldset: CR3 - - name: BRR - description: Baud rate register - byte_offset: 12 - fieldset: BRR - - name: GTPR - description: Guard time and prescaler register - byte_offset: 16 - fieldset: GTPR - - name: RTOR - description: Receiver timeout register - byte_offset: 20 - fieldset: RTOR - - name: RQR - description: Request register - byte_offset: 24 - access: Write - fieldset: RQR - - name: ISR - description: Interrupt & status register - byte_offset: 28 - access: Read - fieldset: ISR - - name: ICR - description: Interrupt flag clear register - byte_offset: 32 - access: Write - fieldset: ICR - - name: RDR - description: Receive data register - byte_offset: 36 - access: Read - fieldset: DR - - name: TDR - description: Transmit data register - byte_offset: 40 - access: Write - fieldset: DR - - name: PRESC - description: Prescaler register - byte_offset: 44 - fieldset: PRESC + - name: CR1 + description: Control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: Control register 3 + byte_offset: 8 + fieldset: CR3 + - name: BRR + description: Baud rate register + byte_offset: 12 + fieldset: BRR + - name: GTPR + description: Guard time and prescaler register + byte_offset: 16 + fieldset: GTPR + - name: RTOR + description: Receiver timeout register + byte_offset: 20 + fieldset: RTOR + - name: RQR + description: Request register + byte_offset: 24 + access: Write + fieldset: RQR + - name: ISR + description: Interrupt & status register + byte_offset: 28 + access: Read + fieldset: ISR + - name: ICR + description: Interrupt flag clear register + byte_offset: 32 + access: Write + fieldset: ICR + - name: RDR + description: Receive data register + byte_offset: 36 + access: Read + fieldset: DR + - name: TDR + description: Transmit data register + byte_offset: 40 + access: Write + fieldset: DR + - name: PRESC + description: Prescaler register + byte_offset: 44 + fieldset: PRESC fieldset/BRR: description: Baud rate register fields: - - name: BRR - description: USARTDIV - bit_offset: 0 - bit_size: 16 + - name: BRR + description: USARTDIV + bit_offset: 0 + bit_size: 16 fieldset/CR1: description: Control register 1 fields: - - name: UE - description: USART enable - bit_offset: 0 - bit_size: 1 - - name: UESM - description: USART enable in Stop mode - bit_offset: 1 - bit_size: 1 - - name: RE - description: Receiver enable - bit_offset: 2 - bit_size: 1 - - name: TE - description: Transmitter enable - bit_offset: 3 - bit_size: 1 - - name: IDLEIE - description: IDLE interrupt enable - bit_offset: 4 - bit_size: 1 - - name: RXNEIE - description: RXNE interrupt enable - bit_offset: 5 - bit_size: 1 - - name: TCIE - description: Transmission complete interrupt enable - bit_offset: 6 - bit_size: 1 - - name: TXEIE - description: TXE interrupt enable - bit_offset: 7 - bit_size: 1 - - name: PEIE - description: PE interrupt enable - bit_offset: 8 - bit_size: 1 - - name: PS - description: Parity selection - bit_offset: 9 - bit_size: 1 - enum: PS - - name: PCE - description: Parity control enable - bit_offset: 10 - bit_size: 1 - - name: WAKE - description: Receiver wakeup method - bit_offset: 11 - bit_size: 1 - enum: WAKE - - name: M0 - description: Word length - bit_offset: 12 - bit_size: 1 - enum: M0 - - name: MME - description: Mute mode enable - bit_offset: 13 - bit_size: 1 - - name: CMIE - description: Character match interrupt enable - bit_offset: 14 - bit_size: 1 - - name: OVER8 - description: Oversampling mode - bit_offset: 15 - bit_size: 1 - enum: OVER8 - - name: DEDT - description: Driver Enable deassertion time - bit_offset: 16 - bit_size: 5 - - name: DEAT - description: Driver Enable assertion time - bit_offset: 21 - bit_size: 5 - - name: RTOIE - description: Receiver timeout interrupt enable - bit_offset: 26 - bit_size: 1 - - name: EOBIE - description: End of Block interrupt enable - bit_offset: 27 - bit_size: 1 - - name: M1 - description: Word length - bit_offset: 28 - bit_size: 1 - enum: M1 - - name: FIFOEN - description: FIFO mode enable - bit_offset: 29 - bit_size: 1 - - name: TXFEIE - description: TXFIFO empty interrupt enable - bit_offset: 30 - bit_size: 1 - - name: RXFFIE - description: RXFIFO Full interrupt enable - bit_offset: 31 - bit_size: 1 + - name: UE + description: USART enable + bit_offset: 0 + bit_size: 1 + - name: UESM + description: USART enable in Stop mode + bit_offset: 1 + bit_size: 1 + - name: RE + description: Receiver enable + bit_offset: 2 + bit_size: 1 + - name: TE + description: Transmitter enable + bit_offset: 3 + bit_size: 1 + - name: IDLEIE + description: IDLE interrupt enable + bit_offset: 4 + bit_size: 1 + - name: RXNEIE + description: RXNE interrupt enable + bit_offset: 5 + bit_size: 1 + - name: TCIE + description: Transmission complete interrupt enable + bit_offset: 6 + bit_size: 1 + - name: TXEIE + description: TXE interrupt enable + bit_offset: 7 + bit_size: 1 + - name: PEIE + description: PE interrupt enable + bit_offset: 8 + bit_size: 1 + - name: PS + description: Parity selection + bit_offset: 9 + bit_size: 1 + enum: PS + - name: PCE + description: Parity control enable + bit_offset: 10 + bit_size: 1 + - name: WAKE + description: Receiver wakeup method + bit_offset: 11 + bit_size: 1 + enum: WAKE + - name: M0 + description: Word length + bit_offset: 12 + bit_size: 1 + enum: M0 + - name: MME + description: Mute mode enable + bit_offset: 13 + bit_size: 1 + - name: CMIE + description: Character match interrupt enable + bit_offset: 14 + bit_size: 1 + - name: OVER8 + description: Oversampling mode + bit_offset: 15 + bit_size: 1 + enum: OVER8 + - name: DEDT + description: Driver Enable deassertion time + bit_offset: 16 + bit_size: 5 + - name: DEAT + description: Driver Enable assertion time + bit_offset: 21 + bit_size: 5 + - name: RTOIE + description: Receiver timeout interrupt enable + bit_offset: 26 + bit_size: 1 + - name: EOBIE + description: End of Block interrupt enable + bit_offset: 27 + bit_size: 1 + - name: M1 + description: Word length + bit_offset: 28 + bit_size: 1 + enum: M1 + - name: FIFOEN + description: FIFO mode enable + bit_offset: 29 + bit_size: 1 + - name: TXFEIE + description: TXFIFO empty interrupt enable + bit_offset: 30 + bit_size: 1 + - name: RXFFIE + description: RXFIFO Full interrupt enable + bit_offset: 31 + bit_size: 1 fieldset/CR2: description: Control register 2 fields: - - name: ADDM - description: 7-bit Address Detection/4-bit Address Detection - bit_offset: 4 - bit_size: 1 - enum: ADDM - - name: LBDL - description: Line break detection length - bit_offset: 5 - bit_size: 1 - enum: LBDL - - name: LBDIE - description: LIN break detection interrupt enable - bit_offset: 6 - bit_size: 1 - - name: LBCL - description: Last bit clock pulse - bit_offset: 8 - bit_size: 1 - - name: CPHA - description: Clock phase - bit_offset: 9 - bit_size: 1 - enum: CPHA - - name: CPOL - description: Clock polarity - bit_offset: 10 - bit_size: 1 - enum: CPOL - - name: CLKEN - description: Clock enable - bit_offset: 11 - bit_size: 1 - - name: STOP - description: STOP bits - bit_offset: 12 - bit_size: 2 - enum: STOP - - name: LINEN - description: LIN mode enable - bit_offset: 14 - bit_size: 1 - - name: SWAP - description: Swap TX/RX pins - bit_offset: 15 - bit_size: 1 - - name: RXINV - description: RX pin active level inversion - bit_offset: 16 - bit_size: 1 - - name: TXINV - description: TX pin active level inversion - bit_offset: 17 - bit_size: 1 - - name: DATAINV - description: Binary data inversion - bit_offset: 18 - bit_size: 1 - - name: MSBFIRST - description: Most significant bit first - bit_offset: 19 - bit_size: 1 - enum: MSBFIRST - - name: ABREN - description: Auto baud rate enable - bit_offset: 20 - bit_size: 1 - - name: ABRMOD - description: Auto baud rate mode - bit_offset: 21 - bit_size: 2 - enum: ABRMOD - - name: RTOEN - description: Receiver timeout enable - bit_offset: 23 - bit_size: 1 - - name: ADD - description: Address of the USART node - bit_offset: 24 - bit_size: 8 + - name: ADDM + description: 7-bit Address Detection/4-bit Address Detection + bit_offset: 4 + bit_size: 1 + enum: ADDM + - name: LBDL + description: Line break detection length + bit_offset: 5 + bit_size: 1 + enum: LBDL + - name: LBDIE + description: LIN break detection interrupt enable + bit_offset: 6 + bit_size: 1 + - name: LBCL + description: Last bit clock pulse + bit_offset: 8 + bit_size: 1 + - name: CPHA + description: Clock phase + bit_offset: 9 + bit_size: 1 + enum: CPHA + - name: CPOL + description: Clock polarity + bit_offset: 10 + bit_size: 1 + enum: CPOL + - name: CLKEN + description: Clock enable + bit_offset: 11 + bit_size: 1 + - name: STOP + description: STOP bits + bit_offset: 12 + bit_size: 2 + enum: STOP + - name: LINEN + description: LIN mode enable + bit_offset: 14 + bit_size: 1 + - name: SWAP + description: Swap TX/RX pins + bit_offset: 15 + bit_size: 1 + - name: RXINV + description: RX pin active level inversion + bit_offset: 16 + bit_size: 1 + - name: TXINV + description: TX pin active level inversion + bit_offset: 17 + bit_size: 1 + - name: DATAINV + description: Binary data inversion + bit_offset: 18 + bit_size: 1 + - name: MSBFIRST + description: Most significant bit first + bit_offset: 19 + bit_size: 1 + enum: MSBFIRST + - name: ABREN + description: Auto baud rate enable + bit_offset: 20 + bit_size: 1 + - name: ABRMOD + description: Auto baud rate mode + bit_offset: 21 + bit_size: 2 + enum: ABRMOD + - name: RTOEN + description: Receiver timeout enable + bit_offset: 23 + bit_size: 1 + - name: ADD + description: Address of the USART node + bit_offset: 24 + bit_size: 8 fieldset/CR3: description: Control register 3 fields: - - name: EIE - description: Error interrupt enable - bit_offset: 0 - bit_size: 1 - - name: IREN - description: IrDA mode enable - bit_offset: 1 - bit_size: 1 - - name: IRLP - description: IrDA low-power - bit_offset: 2 - bit_size: 1 - enum: IRLP - - name: HDSEL - description: Half-duplex selection - bit_offset: 3 - bit_size: 1 - - name: NACK - description: Smartcard NACK enable - bit_offset: 4 - bit_size: 1 - - name: SCEN - description: Smartcard mode enable - bit_offset: 5 - bit_size: 1 - - name: DMAR - description: DMA enable receiver - bit_offset: 6 - bit_size: 1 - - name: DMAT - description: DMA enable transmitter - bit_offset: 7 - bit_size: 1 - - name: RTSE - description: RTS enable - bit_offset: 8 - bit_size: 1 - - name: CTSE - description: CTS enable - bit_offset: 9 - bit_size: 1 - - name: CTSIE - description: CTS interrupt enable - bit_offset: 10 - bit_size: 1 - - name: ONEBIT - description: One sample bit method enable - bit_offset: 11 - bit_size: 1 - - name: OVRDIS - description: Overrun Disable - bit_offset: 12 - bit_size: 1 - - name: DDRE - description: DMA Disable on Reception Error - bit_offset: 13 - bit_size: 1 - - name: DEM - description: Driver enable mode - bit_offset: 14 - bit_size: 1 - - name: DEP - description: Driver enable polarity selection - bit_offset: 15 - bit_size: 1 - enum: DEP - - name: SCARCNT - description: Smartcard auto-retry count - bit_offset: 17 - bit_size: 3 - - name: WUS - description: Wakeup from Stop mode interrupt flag selection - bit_offset: 20 - bit_size: 2 - enum: WUS - - name: WUFIE - description: Wakeup from Stop mode interrupt enable - bit_offset: 22 - bit_size: 1 - - name: TXFTIE - description: TXFIFO threshold interrupt enable - bit_offset: 23 - bit_size: 1 - - name: RXFTCFG - description: Receive FIFO threshold configuration - bit_offset: 25 - bit_size: 3 - - name: RXFTIE - description: RXFIFO threshold interrupt enable - bit_offset: 28 - bit_size: 1 - - name: TXFTCFG - description: TXFIFO threshold configuration - bit_offset: 29 - bit_size: 3 + - name: EIE + description: Error interrupt enable + bit_offset: 0 + bit_size: 1 + - name: IREN + description: IrDA mode enable + bit_offset: 1 + bit_size: 1 + - name: IRLP + description: IrDA low-power + bit_offset: 2 + bit_size: 1 + enum: IRLP + - name: HDSEL + description: Half-duplex selection + bit_offset: 3 + bit_size: 1 + - name: NACK + description: Smartcard NACK enable + bit_offset: 4 + bit_size: 1 + - name: SCEN + description: Smartcard mode enable + bit_offset: 5 + bit_size: 1 + - name: DMAR + description: DMA enable receiver + bit_offset: 6 + bit_size: 1 + - name: DMAT + description: DMA enable transmitter + bit_offset: 7 + bit_size: 1 + - name: RTSE + description: RTS enable + bit_offset: 8 + bit_size: 1 + - name: CTSE + description: CTS enable + bit_offset: 9 + bit_size: 1 + - name: CTSIE + description: CTS interrupt enable + bit_offset: 10 + bit_size: 1 + - name: ONEBIT + description: One sample bit method enable + bit_offset: 11 + bit_size: 1 + - name: OVRDIS + description: Overrun Disable + bit_offset: 12 + bit_size: 1 + - name: DDRE + description: DMA Disable on Reception Error + bit_offset: 13 + bit_size: 1 + - name: DEM + description: Driver enable mode + bit_offset: 14 + bit_size: 1 + - name: DEP + description: Driver enable polarity selection + bit_offset: 15 + bit_size: 1 + enum: DEP + - name: SCARCNT + description: Smartcard auto-retry count + bit_offset: 17 + bit_size: 3 + - name: WUS + description: Wakeup from Stop mode interrupt flag selection + bit_offset: 20 + bit_size: 2 + enum: WUS + - name: WUFIE + description: Wakeup from Stop mode interrupt enable + bit_offset: 22 + bit_size: 1 + - name: TXFTIE + description: TXFIFO threshold interrupt enable + bit_offset: 23 + bit_size: 1 + - name: RXFTCFG + description: Receive FIFO threshold configuration + bit_offset: 25 + bit_size: 3 + - name: RXFTIE + description: RXFIFO threshold interrupt enable + bit_offset: 28 + bit_size: 1 + - name: TXFTCFG + description: TXFIFO threshold configuration + bit_offset: 29 + bit_size: 3 fieldset/DR: description: Data register fields: - - name: DR - description: Data value - bit_offset: 0 - bit_size: 9 + - name: DR + description: Data value + bit_offset: 0 + bit_size: 9 fieldset/GTPR: description: Guard time and prescaler register fields: - - name: PSC - description: Prescaler value - bit_offset: 0 - bit_size: 8 - - name: GT - description: Guard time value - bit_offset: 8 - bit_size: 8 + - name: PSC + description: Prescaler value + bit_offset: 0 + bit_size: 8 + - name: GT + description: Guard time value + bit_offset: 8 + bit_size: 8 fieldset/ICR: description: Interrupt flag clear register fields: - - name: PE - description: Parity error clear flag - bit_offset: 0 - bit_size: 1 - - name: FE - description: Framing error clear flag - bit_offset: 1 - bit_size: 1 - - name: NE - description: Noise error clear flag - bit_offset: 2 - bit_size: 1 - - name: ORE - description: Overrun error clear flag - bit_offset: 3 - bit_size: 1 - - name: IDLE - description: Idle line detected clear flag - bit_offset: 4 - bit_size: 1 - - name: TC - description: Transmission complete clear flag - bit_offset: 6 - bit_size: 1 - - name: LBD - description: LIN break detection clear flag - bit_offset: 8 - bit_size: 1 - - name: CTS - description: CTS clear flag - bit_offset: 9 - bit_size: 1 - - name: RTOF - description: Receiver timeout clear flag - bit_offset: 11 - bit_size: 1 - - name: EOBF - description: End of block clear flag - bit_offset: 12 - bit_size: 1 - - name: CMF - description: Character match clear flag - bit_offset: 17 - bit_size: 1 - - name: WUF - description: Wakeup from Stop mode clear flag - bit_offset: 20 - bit_size: 1 + - name: PE + description: Parity error clear flag + bit_offset: 0 + bit_size: 1 + - name: FE + description: Framing error clear flag + bit_offset: 1 + bit_size: 1 + - name: NE + description: Noise error clear flag + bit_offset: 2 + bit_size: 1 + - name: ORE + description: Overrun error clear flag + bit_offset: 3 + bit_size: 1 + - name: IDLE + description: Idle line detected clear flag + bit_offset: 4 + bit_size: 1 + - name: TC + description: Transmission complete clear flag + bit_offset: 6 + bit_size: 1 + - name: LBD + description: LIN break detection clear flag + bit_offset: 8 + bit_size: 1 + - name: CTS + description: CTS clear flag + bit_offset: 9 + bit_size: 1 + - name: RTOF + description: Receiver timeout clear flag + bit_offset: 11 + bit_size: 1 + - name: EOBF + description: End of block clear flag + bit_offset: 12 + bit_size: 1 + - name: CMF + description: Character match clear flag + bit_offset: 17 + bit_size: 1 + - name: WUF + description: Wakeup from Stop mode clear flag + bit_offset: 20 + bit_size: 1 fieldset/ISR: description: Interrupt & status register fields: - - name: PE - description: Parity error - bit_offset: 0 - bit_size: 1 - - name: FE - description: Framing error - bit_offset: 1 - bit_size: 1 - - name: NE - description: Noise error flag - bit_offset: 2 - bit_size: 1 - - name: ORE - description: Overrun error - bit_offset: 3 - bit_size: 1 - - name: IDLE - description: Idle line detected - bit_offset: 4 - bit_size: 1 - - name: RXNE - description: Read data register not empty - bit_offset: 5 - bit_size: 1 - - name: TC - description: Transmission complete - bit_offset: 6 - bit_size: 1 - - name: TXE - description: Transmit data register empty - bit_offset: 7 - bit_size: 1 - - name: LBD - description: LIN break detection flag - bit_offset: 8 - bit_size: 1 - - name: CTSIF - description: CTS interrupt flag - bit_offset: 9 - bit_size: 1 - - name: CTS - description: CTS flag - bit_offset: 10 - bit_size: 1 - - name: RTOF - description: Receiver timeout - bit_offset: 11 - bit_size: 1 - - name: EOBF - description: End of block flag - bit_offset: 12 - bit_size: 1 - - name: ABRE - description: Auto baud rate error - bit_offset: 14 - bit_size: 1 - - name: ABRF - description: Auto baud rate flag - bit_offset: 15 - bit_size: 1 - - name: BUSY - description: Busy flag - bit_offset: 16 - bit_size: 1 - - name: CMF - description: character match flag - bit_offset: 17 - bit_size: 1 - - name: SBKF - description: Send break flag - bit_offset: 18 - bit_size: 1 - - name: RWU - description: Receiver wakeup from Mute mode - bit_offset: 19 - bit_size: 1 - enum: RWU - - name: WUF - description: Wakeup from Stop mode flag - bit_offset: 20 - bit_size: 1 - - name: TEACK - description: Transmit enable acknowledge flag - bit_offset: 21 - bit_size: 1 - - name: REACK - description: Receive enable acknowledge flag - bit_offset: 22 - bit_size: 1 - - name: TXFE - description: TXFIFO Empty - bit_offset: 23 - bit_size: 1 - - name: RXFF - description: RXFIFO Full - bit_offset: 24 - bit_size: 1 - - name: RXFT - description: RXFIFO threshold flag - bit_offset: 26 - bit_size: 1 - - name: TXFT - description: TXFIFO threshold flag - bit_offset: 27 - bit_size: 1 + - name: PE + description: Parity error + bit_offset: 0 + bit_size: 1 + - name: FE + description: Framing error + bit_offset: 1 + bit_size: 1 + - name: NE + description: Noise error flag + bit_offset: 2 + bit_size: 1 + - name: ORE + description: Overrun error + bit_offset: 3 + bit_size: 1 + - name: IDLE + description: Idle line detected + bit_offset: 4 + bit_size: 1 + - name: RXNE + description: Read data register not empty + bit_offset: 5 + bit_size: 1 + - name: TC + description: Transmission complete + bit_offset: 6 + bit_size: 1 + - name: TXE + description: Transmit data register empty + bit_offset: 7 + bit_size: 1 + - name: LBD + description: LIN break detection flag + bit_offset: 8 + bit_size: 1 + - name: CTSIF + description: CTS interrupt flag + bit_offset: 9 + bit_size: 1 + - name: CTS + description: CTS flag + bit_offset: 10 + bit_size: 1 + - name: RTOF + description: Receiver timeout + bit_offset: 11 + bit_size: 1 + - name: EOBF + description: End of block flag + bit_offset: 12 + bit_size: 1 + - name: ABRE + description: Auto baud rate error + bit_offset: 14 + bit_size: 1 + - name: ABRF + description: Auto baud rate flag + bit_offset: 15 + bit_size: 1 + - name: BUSY + description: Busy flag + bit_offset: 16 + bit_size: 1 + - name: CMF + description: character match flag + bit_offset: 17 + bit_size: 1 + - name: SBKF + description: Send break flag + bit_offset: 18 + bit_size: 1 + - name: RWU + description: Receiver wakeup from Mute mode + bit_offset: 19 + bit_size: 1 + enum: RWU + - name: WUF + description: Wakeup from Stop mode flag + bit_offset: 20 + bit_size: 1 + - name: TEACK + description: Transmit enable acknowledge flag + bit_offset: 21 + bit_size: 1 + - name: REACK + description: Receive enable acknowledge flag + bit_offset: 22 + bit_size: 1 + - name: TXFE + description: TXFIFO Empty + bit_offset: 23 + bit_size: 1 + - name: RXFF + description: RXFIFO Full + bit_offset: 24 + bit_size: 1 + - name: RXFT + description: RXFIFO threshold flag + bit_offset: 26 + bit_size: 1 + - name: TXFT + description: TXFIFO threshold flag + bit_offset: 27 + bit_size: 1 fieldset/PRESC: description: Prescaler register fields: - - name: PRESCALER - description: Clock prescaler - bit_offset: 0 - bit_size: 4 - enum: PRESC + - name: PRESCALER + description: Clock prescaler + bit_offset: 0 + bit_size: 4 + enum: PRESC fieldset/RQR: description: Request register fields: - - name: ABRRQ - description: Auto baud rate request. Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame. - bit_offset: 0 - bit_size: 1 - - name: SBKRQ - description: "Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available" - bit_offset: 1 - bit_size: 1 - - name: MMRQ - description: Mute mode request. Puts the USART in mute mode and sets the RWU flag. - bit_offset: 2 - bit_size: 1 - - name: RXFRQ - description: "Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition" - bit_offset: 3 - bit_size: 1 - - name: TXFRQ - description: Transmit data flush request. Sets the TXE flags. This allows to discard the transmit data. - bit_offset: 4 - bit_size: 1 + - name: ABRRQ + description: Auto baud rate request. Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame. + bit_offset: 0 + bit_size: 1 + - name: SBKRQ + description: Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available + bit_offset: 1 + bit_size: 1 + - name: MMRQ + description: Mute mode request. Puts the USART in mute mode and sets the RWU flag. + bit_offset: 2 + bit_size: 1 + - name: RXFRQ + description: Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition + bit_offset: 3 + bit_size: 1 + - name: TXFRQ + description: Transmit data flush request. Sets the TXE flags. This allows to discard the transmit data. + bit_offset: 4 + bit_size: 1 fieldset/RTOR: description: Receiver timeout register fields: - - name: RTO - description: Receiver timeout value - bit_offset: 0 - bit_size: 24 - - name: BLEN - description: Block Length - bit_offset: 24 - bit_size: 8 + - name: RTO + description: Receiver timeout value + bit_offset: 0 + bit_size: 24 + - name: BLEN + description: Block Length + bit_offset: 24 + bit_size: 8 enum/ABRMOD: bit_size: 2 variants: - - name: Start - description: Measurement of the start bit is used to detect the baud rate - value: 0 - - name: Edge - description: Falling edge to falling edge measurement - value: 1 - - name: Frame7F - description: "0x7F frame detection" - value: 2 - - name: Frame55 - description: "0x55 frame detection" - value: 3 + - name: Start + description: Measurement of the start bit is used to detect the baud rate + value: 0 + - name: Edge + description: Falling edge to falling edge measurement + value: 1 + - name: Frame7F + description: 0x7F frame detection + value: 2 + - name: Frame55 + description: 0x55 frame detection + value: 3 enum/ADDM: bit_size: 1 variants: - - name: Bit4 - description: 4-bit address detection - value: 0 - - name: Bit7 - description: 7-bit address detection - value: 1 + - name: Bit4 + description: 4-bit address detection + value: 0 + - name: Bit7 + description: 7-bit address detection + value: 1 enum/CPHA: bit_size: 1 variants: - - name: First - description: The first clock transition is the first data capture edge - value: 0 - - name: Second - description: The second clock transition is the first data capture edge - value: 1 + - name: First + description: The first clock transition is the first data capture edge + value: 0 + - name: Second + description: The second clock transition is the first data capture edge + value: 1 enum/CPOL: bit_size: 1 variants: - - name: Low - description: Steady low value on CK pin outside transmission window - value: 0 - - name: High - description: Steady high value on CK pin outside transmission window - value: 1 + - name: Low + description: Steady low value on CK pin outside transmission window + value: 0 + - name: High + description: Steady high value on CK pin outside transmission window + value: 1 enum/DEP: bit_size: 1 variants: - - name: High - description: DE signal is active high - value: 0 - - name: Low - description: DE signal is active low - value: 1 + - name: High + description: DE signal is active high + value: 0 + - name: Low + description: DE signal is active low + value: 1 enum/IRLP: bit_size: 1 variants: - - name: Normal - description: Normal mode - value: 0 - - name: LowPower - description: Low-power mode - value: 1 + - name: Normal + description: Normal mode + value: 0 + - name: LowPower + description: Low-power mode + value: 1 enum/LBDL: bit_size: 1 variants: - - name: Bit10 - description: 10-bit break detection - value: 0 - - name: Bit11 - description: 11-bit break detection - value: 1 + - name: Bit10 + description: 10-bit break detection + value: 0 + - name: Bit11 + description: 11-bit break detection + value: 1 enum/M0: bit_size: 1 variants: - - name: Bit8 - description: "1 start bit, 8 data bits, n stop bits" - value: 0 - - name: Bit9 - description: "1 start bit, 9 data bits, n stop bits" - value: 1 + - name: Bit8 + description: 1 start bit, 8 data bits, n stop bits + value: 0 + - name: Bit9 + description: 1 start bit, 9 data bits, n stop bits + value: 1 enum/M1: bit_size: 1 variants: - - name: M0 - description: Use M0 to set the data bits - value: 0 - - name: Bit7 - description: "1 start bit, 7 data bits, n stop bits" - value: 1 + - name: M0 + description: Use M0 to set the data bits + value: 0 + - name: Bit7 + description: 1 start bit, 7 data bits, n stop bits + value: 1 enum/MSBFIRST: bit_size: 1 variants: - - name: LSB - description: "data is transmitted/received with data bit 0 first, following the start bit" - value: 0 - - name: MSB - description: "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit" - value: 1 + - name: LSB + description: data is transmitted/received with data bit 0 first, following the start bit + value: 0 + - name: MSB + description: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit + value: 1 enum/OVER8: bit_size: 1 variants: - - name: Oversampling16 - description: Oversampling by 16 - value: 0 - - name: Oversampling8 - description: Oversampling by 8 - value: 1 + - name: Oversampling16 + description: Oversampling by 16 + value: 0 + - name: Oversampling8 + description: Oversampling by 8 + value: 1 enum/PRESC: bit_size: 4 variants: - - name: Div1 - description: input clock not divided - value: 0 - - name: Div2 - description: input clock divided by 2 - value: 1 - - name: Div4 - description: input clock divided by 4 - value: 2 - - name: Div6 - description: input clock divided by 6 - value: 3 - - name: Div8 - description: input clock divided by 8 - value: 4 - - name: Div10 - description: input clock divided by 10 - value: 5 - - name: Div12 - description: input clock divided by 12 - value: 6 - - name: Div16 - description: input clock divided by 16 - value: 7 - - name: Div32 - description: input clock divided by 32 - value: 8 - - name: Div64 - description: input clock divided by 64 - value: 9 - - name: Div128 - description: input clock divided by 128 - value: 10 - - name: Div256 - description: input clock divided by 256 - value: 11 + - name: Div1 + description: input clock not divided + value: 0 + - name: Div2 + description: input clock divided by 2 + value: 1 + - name: Div4 + description: input clock divided by 4 + value: 2 + - name: Div6 + description: input clock divided by 6 + value: 3 + - name: Div8 + description: input clock divided by 8 + value: 4 + - name: Div10 + description: input clock divided by 10 + value: 5 + - name: Div12 + description: input clock divided by 12 + value: 6 + - name: Div16 + description: input clock divided by 16 + value: 7 + - name: Div32 + description: input clock divided by 32 + value: 8 + - name: Div64 + description: input clock divided by 64 + value: 9 + - name: Div128 + description: input clock divided by 128 + value: 10 + - name: Div256 + description: input clock divided by 256 + value: 11 enum/PS: bit_size: 1 variants: - - name: Even - description: Even parity - value: 0 - - name: Odd - description: Odd parity - value: 1 + - name: Even + description: Even parity + value: 0 + - name: Odd + description: Odd parity + value: 1 enum/RWU: bit_size: 1 variants: - - name: Active - description: Receiver in active mode - value: 0 - - name: Mute - description: Receiver in mute mode - value: 1 + - name: Active + description: Receiver in active mode + value: 0 + - name: Mute + description: Receiver in mute mode + value: 1 enum/STOP: bit_size: 2 variants: - - name: Stop1 - description: 1 stop bit - value: 0 - - name: Stop0p5 - description: 0.5 stop bits - value: 1 - - name: Stop2 - description: 2 stop bits - value: 2 - - name: Stop1p5 - description: 1.5 stop bits - value: 3 + - name: Stop1 + description: 1 stop bit + value: 0 + - name: Stop0p5 + description: 0.5 stop bits + value: 1 + - name: Stop2 + description: 2 stop bits + value: 2 + - name: Stop1p5 + description: 1.5 stop bits + value: 3 enum/WAKE: bit_size: 1 variants: - - name: IdleLine - description: USART wakeup on idle line - value: 0 - - name: AddressMark - description: USART wakeup on address mark - value: 1 + - name: IdleLine + description: USART wakeup on idle line + value: 0 + - name: AddressMark + description: USART wakeup on address mark + value: 1 enum/WUS: bit_size: 2 variants: - - name: Address - description: WUF active on address match - value: 0 - - name: Start - description: WuF active on Start bit detection - value: 2 - - name: RXNE - description: WUF active on RXNE - value: 3 + - name: Address + description: WUF active on address match + value: 0 + - name: Start + description: WuF active on Start bit detection + value: 2 + - name: RXNE + description: WUF active on RXNE + value: 3 diff --git a/data/registers/usb_v1.yaml b/data/registers/usb_v1.yaml index e885e7d..8192041 100644 --- a/data/registers/usb_v1.yaml +++ b/data/registers/usb_v1.yaml @@ -1,257 +1,256 @@ ---- block/USB: description: Universal serial bus full-speed device interface items: - - name: EPR - description: endpoint register - array: - len: 8 - stride: 4 - byte_offset: 0 - fieldset: EPR - - name: CNTR - description: control register - byte_offset: 64 - fieldset: CNTR - - name: ISTR - description: interrupt status register - byte_offset: 68 - fieldset: ISTR - - name: FNR - description: frame number register - byte_offset: 72 - access: Read - fieldset: FNR - - name: DADDR - description: device address - byte_offset: 76 - fieldset: DADDR - - name: BTABLE - description: Buffer table address - byte_offset: 80 - fieldset: BTABLE + - name: EPR + description: endpoint register + array: + len: 8 + stride: 4 + byte_offset: 0 + fieldset: EPR + - name: CNTR + description: control register + byte_offset: 64 + fieldset: CNTR + - name: ISTR + description: interrupt status register + byte_offset: 68 + fieldset: ISTR + - name: FNR + description: frame number register + byte_offset: 72 + access: Read + fieldset: FNR + - name: DADDR + description: device address + byte_offset: 76 + fieldset: DADDR + - name: BTABLE + description: Buffer table address + byte_offset: 80 + fieldset: BTABLE fieldset/BTABLE: description: Buffer table address fields: - - name: BTABLE - description: BTABLE - bit_offset: 3 - bit_size: 13 + - name: BTABLE + description: BTABLE + bit_offset: 3 + bit_size: 13 fieldset/CNTR: description: control register fields: - - name: FRES - description: "Force a reset of the USB peripheral, exactly like a RESET signaling on the USB" - bit_offset: 0 - bit_size: 1 - - name: PDWN - description: Enter power down mode - bit_offset: 1 - bit_size: 1 - - name: LPMODE - description: Enter low-power mode - bit_offset: 2 - bit_size: 1 - - name: FSUSP - description: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected - bit_offset: 3 - bit_size: 1 - - name: RESUME - description: Resume request - bit_offset: 4 - bit_size: 1 - - name: ESOFM - description: "ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 8 - bit_size: 1 - - name: SOFM - description: "SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 9 - bit_size: 1 - - name: RESETM - description: "RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 10 - bit_size: 1 - - name: SUSPM - description: "SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 11 - bit_size: 1 - - name: WKUPM - description: "WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 12 - bit_size: 1 - - name: ERRM - description: "ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 13 - bit_size: 1 - - name: PMAOVRM - description: "PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 14 - bit_size: 1 - - name: CTRM - description: "CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 15 - bit_size: 1 + - name: FRES + description: Force a reset of the USB peripheral, exactly like a RESET signaling on the USB + bit_offset: 0 + bit_size: 1 + - name: PDWN + description: Enter power down mode + bit_offset: 1 + bit_size: 1 + - name: LPMODE + description: Enter low-power mode + bit_offset: 2 + bit_size: 1 + - name: FSUSP + description: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected + bit_offset: 3 + bit_size: 1 + - name: RESUME + description: Resume request + bit_offset: 4 + bit_size: 1 + - name: ESOFM + description: ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 8 + bit_size: 1 + - name: SOFM + description: SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 9 + bit_size: 1 + - name: RESETM + description: RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 10 + bit_size: 1 + - name: SUSPM + description: SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 11 + bit_size: 1 + - name: WKUPM + description: WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 12 + bit_size: 1 + - name: ERRM + description: ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 13 + bit_size: 1 + - name: PMAOVRM + description: PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 14 + bit_size: 1 + - name: CTRM + description: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 15 + bit_size: 1 fieldset/DADDR: description: device address fields: - - name: ADD - description: device address - bit_offset: 0 - bit_size: 7 - - name: EF - description: USB device enabled - bit_offset: 7 - bit_size: 1 + - name: ADD + description: device address + bit_offset: 0 + bit_size: 7 + - name: EF + description: USB device enabled + bit_offset: 7 + bit_size: 1 fieldset/EPR: description: endpoint register fields: - - name: EA - description: EA - bit_offset: 0 - bit_size: 4 - - name: STAT_TX - description: STAT_TX - bit_offset: 4 - bit_size: 2 - enum: STAT - - name: DTOG_TX - description: DTOG_TX - bit_offset: 6 - bit_size: 1 - - name: CTR_TX - description: CTR_TX - bit_offset: 7 - bit_size: 1 - - name: EP_KIND - description: EP_KIND - bit_offset: 8 - bit_size: 1 - - name: EP_TYPE - description: EPTYPE - bit_offset: 9 - bit_size: 2 - enum: EP_TYPE - - name: SETUP - description: SETUP - bit_offset: 11 - bit_size: 1 - - name: STAT_RX - description: STAT_RX - bit_offset: 12 - bit_size: 2 - enum: STAT - - name: DTOG_RX - description: DTOG_RX - bit_offset: 14 - bit_size: 1 - - name: CTR_RX - description: CTR_RX - bit_offset: 15 - bit_size: 1 + - name: EA + description: EA + bit_offset: 0 + bit_size: 4 + - name: STAT_TX + description: STAT_TX + bit_offset: 4 + bit_size: 2 + enum: STAT + - name: DTOG_TX + description: DTOG_TX + bit_offset: 6 + bit_size: 1 + - name: CTR_TX + description: CTR_TX + bit_offset: 7 + bit_size: 1 + - name: EP_KIND + description: EP_KIND + bit_offset: 8 + bit_size: 1 + - name: EP_TYPE + description: EPTYPE + bit_offset: 9 + bit_size: 2 + enum: EP_TYPE + - name: SETUP + description: SETUP + bit_offset: 11 + bit_size: 1 + - name: STAT_RX + description: STAT_RX + bit_offset: 12 + bit_size: 2 + enum: STAT + - name: DTOG_RX + description: DTOG_RX + bit_offset: 14 + bit_size: 1 + - name: CTR_RX + description: CTR_RX + bit_offset: 15 + bit_size: 1 fieldset/FNR: description: frame number register fields: - - name: FN - description: FN - bit_offset: 0 - bit_size: 11 - - name: LSOF - description: LSOF - bit_offset: 11 - bit_size: 2 - - name: LCK - description: the frame timer remains in this state until an USB reset or USB suspend event occurs - bit_offset: 13 - bit_size: 1 - - name: RXDM - description: received data minus upstream port data line - bit_offset: 14 - bit_size: 1 - - name: RXDP - description: received data plus upstream port data line - bit_offset: 15 - bit_size: 1 + - name: FN + description: FN + bit_offset: 0 + bit_size: 11 + - name: LSOF + description: LSOF + bit_offset: 11 + bit_size: 2 + - name: LCK + description: the frame timer remains in this state until an USB reset or USB suspend event occurs + bit_offset: 13 + bit_size: 1 + - name: RXDM + description: received data minus upstream port data line + bit_offset: 14 + bit_size: 1 + - name: RXDP + description: received data plus upstream port data line + bit_offset: 15 + bit_size: 1 fieldset/ISTR: description: interrupt status register fields: - - name: EP_ID - description: EP_ID - bit_offset: 0 - bit_size: 4 - - name: DIR - description: DIR - bit_offset: 4 - bit_size: 1 - enum: DIR - - name: ESOF - description: an SOF packet is expected but not received - bit_offset: 8 - bit_size: 1 - - name: SOF - description: beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus - bit_offset: 9 - bit_size: 1 - - name: RESET - description: peripheral detects an active USB RESET signal at its inputs - bit_offset: 10 - bit_size: 1 - - name: SUSP - description: "no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus" - bit_offset: 11 - bit_size: 1 - - name: WKUP - description: activity is detected that wakes up the USB peripheral - bit_offset: 12 - bit_size: 1 - - name: ERR - description: "One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred" - bit_offset: 13 - bit_size: 1 - - name: PMAOVR - description: microcontroller has not been able to respond in time to an USB memory request - bit_offset: 14 - bit_size: 1 - - name: CTR - description: endpoint has successfully completed a transaction - bit_offset: 15 - bit_size: 1 + - name: EP_ID + description: EP_ID + bit_offset: 0 + bit_size: 4 + - name: DIR + description: DIR + bit_offset: 4 + bit_size: 1 + enum: DIR + - name: ESOF + description: an SOF packet is expected but not received + bit_offset: 8 + bit_size: 1 + - name: SOF + description: beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus + bit_offset: 9 + bit_size: 1 + - name: RESET + description: peripheral detects an active USB RESET signal at its inputs + bit_offset: 10 + bit_size: 1 + - name: SUSP + description: no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus + bit_offset: 11 + bit_size: 1 + - name: WKUP + description: activity is detected that wakes up the USB peripheral + bit_offset: 12 + bit_size: 1 + - name: ERR + description: One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred + bit_offset: 13 + bit_size: 1 + - name: PMAOVR + description: microcontroller has not been able to respond in time to an USB memory request + bit_offset: 14 + bit_size: 1 + - name: CTR + description: endpoint has successfully completed a transaction + bit_offset: 15 + bit_size: 1 enum/DIR: bit_size: 1 variants: - - name: To - description: data transmitted by the USB peripheral to the host PC - value: 0 - - name: From - description: data received by the USB peripheral from the host PC - value: 1 + - name: To + description: data transmitted by the USB peripheral to the host PC + value: 0 + - name: From + description: data received by the USB peripheral from the host PC + value: 1 enum/EP_TYPE: bit_size: 2 variants: - - name: Bulk - description: Bulk endpoint - value: 0 - - name: Control - description: Control endpoint - value: 1 - - name: Iso - description: Iso endpoint - value: 2 - - name: Interrupt - description: Interrupt endpoint - value: 3 + - name: Bulk + description: Bulk endpoint + value: 0 + - name: Control + description: Control endpoint + value: 1 + - name: Iso + description: Iso endpoint + value: 2 + - name: Interrupt + description: Interrupt endpoint + value: 3 enum/STAT: bit_size: 2 variants: - - name: Disabled - description: all requests addressed to this endpoint are ignored - value: 0 - - name: Stall - description: the endpoint is stalled and all requests result in a STALL handshake - value: 1 - - name: Nak - description: the endpoint is naked and all requests result in a NAK handshake - value: 2 - - name: Valid - description: "this endpoint is enabled, requests are ACKed" - value: 3 + - name: Disabled + description: all requests addressed to this endpoint are ignored + value: 0 + - name: Stall + description: the endpoint is stalled and all requests result in a STALL handshake + value: 1 + - name: Nak + description: the endpoint is naked and all requests result in a NAK handshake + value: 2 + - name: Valid + description: this endpoint is enabled, requests are ACKed + value: 3 diff --git a/data/registers/usb_v2.yaml b/data/registers/usb_v2.yaml index 70c6954..f3b6457 100644 --- a/data/registers/usb_v2.yaml +++ b/data/registers/usb_v2.yaml @@ -1,302 +1,301 @@ ---- block/USB: description: Universal serial bus full-speed device interface items: - - name: EPR - description: endpoint register - array: - len: 8 - stride: 4 - byte_offset: 0 - fieldset: EPR - - name: CNTR - description: control register - byte_offset: 64 - fieldset: CNTR - - name: ISTR - description: interrupt status register - byte_offset: 68 - fieldset: ISTR - - name: FNR - description: frame number register - byte_offset: 72 - access: Read - fieldset: FNR - - name: DADDR - description: device address - byte_offset: 76 - fieldset: DADDR - - name: BTABLE - description: Buffer table address - byte_offset: 80 - fieldset: BTABLE - - name: LPMCSR - description: LPM control and status register - byte_offset: 84 - fieldset: LPMCSR + - name: EPR + description: endpoint register + array: + len: 8 + stride: 4 + byte_offset: 0 + fieldset: EPR + - name: CNTR + description: control register + byte_offset: 64 + fieldset: CNTR + - name: ISTR + description: interrupt status register + byte_offset: 68 + fieldset: ISTR + - name: FNR + description: frame number register + byte_offset: 72 + access: Read + fieldset: FNR + - name: DADDR + description: device address + byte_offset: 76 + fieldset: DADDR + - name: BTABLE + description: Buffer table address + byte_offset: 80 + fieldset: BTABLE + - name: LPMCSR + description: LPM control and status register + byte_offset: 84 + fieldset: LPMCSR fieldset/BTABLE: description: Buffer table address fields: - - name: BTABLE - description: BTABLE - bit_offset: 3 - bit_size: 13 + - name: BTABLE + description: BTABLE + bit_offset: 3 + bit_size: 13 fieldset/CNTR: description: control register fields: - - name: FRES - description: "Force a reset of the USB peripheral, exactly like a RESET signaling on the USB" - bit_offset: 0 - bit_size: 1 - - name: PDWN - description: Enter power down mode - bit_offset: 1 - bit_size: 1 - - name: LPMODE - description: Enter low-power mode - bit_offset: 2 - bit_size: 1 - - name: FSUSP - description: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected - bit_offset: 3 - bit_size: 1 - - name: RESUME - description: Resume request - bit_offset: 4 - bit_size: 1 - - name: L1RESUME - description: LPM L1 request request - bit_offset: 5 - bit_size: 1 - - name: L1REQM - description: "L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 7 - bit_size: 1 - - name: ESOFM - description: "ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 8 - bit_size: 1 - - name: SOFM - description: "SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 9 - bit_size: 1 - - name: RESETM - description: "RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 10 - bit_size: 1 - - name: SUSPM - description: "SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 11 - bit_size: 1 - - name: WKUPM - description: "WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 12 - bit_size: 1 - - name: ERRM - description: "ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 13 - bit_size: 1 - - name: PMAOVRM - description: "PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 14 - bit_size: 1 - - name: CTRM - description: "CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 15 - bit_size: 1 + - name: FRES + description: Force a reset of the USB peripheral, exactly like a RESET signaling on the USB + bit_offset: 0 + bit_size: 1 + - name: PDWN + description: Enter power down mode + bit_offset: 1 + bit_size: 1 + - name: LPMODE + description: Enter low-power mode + bit_offset: 2 + bit_size: 1 + - name: FSUSP + description: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected + bit_offset: 3 + bit_size: 1 + - name: RESUME + description: Resume request + bit_offset: 4 + bit_size: 1 + - name: L1RESUME + description: LPM L1 request request + bit_offset: 5 + bit_size: 1 + - name: L1REQM + description: L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 7 + bit_size: 1 + - name: ESOFM + description: ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 8 + bit_size: 1 + - name: SOFM + description: SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 9 + bit_size: 1 + - name: RESETM + description: RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 10 + bit_size: 1 + - name: SUSPM + description: SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 11 + bit_size: 1 + - name: WKUPM + description: WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 12 + bit_size: 1 + - name: ERRM + description: ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 13 + bit_size: 1 + - name: PMAOVRM + description: PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 14 + bit_size: 1 + - name: CTRM + description: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 15 + bit_size: 1 fieldset/DADDR: description: device address fields: - - name: ADD - description: device address - bit_offset: 0 - bit_size: 7 - - name: EF - description: USB device enabled - bit_offset: 7 - bit_size: 1 + - name: ADD + description: device address + bit_offset: 0 + bit_size: 7 + - name: EF + description: USB device enabled + bit_offset: 7 + bit_size: 1 fieldset/EPR: description: endpoint register fields: - - name: EA - description: EA - bit_offset: 0 - bit_size: 4 - - name: STAT_TX - description: STAT_TX - bit_offset: 4 - bit_size: 2 - enum: STAT - - name: DTOG_TX - description: DTOG_TX - bit_offset: 6 - bit_size: 1 - - name: CTR_TX - description: CTR_TX - bit_offset: 7 - bit_size: 1 - - name: EP_KIND - description: EP_KIND - bit_offset: 8 - bit_size: 1 - - name: EP_TYPE - description: EPTYPE - bit_offset: 9 - bit_size: 2 - enum: EP_TYPE - - name: SETUP - description: SETUP - bit_offset: 11 - bit_size: 1 - - name: STAT_RX - description: STAT_RX - bit_offset: 12 - bit_size: 2 - enum: STAT - - name: DTOG_RX - description: DTOG_RX - bit_offset: 14 - bit_size: 1 - - name: CTR_RX - description: CTR_RX - bit_offset: 15 - bit_size: 1 + - name: EA + description: EA + bit_offset: 0 + bit_size: 4 + - name: STAT_TX + description: STAT_TX + bit_offset: 4 + bit_size: 2 + enum: STAT + - name: DTOG_TX + description: DTOG_TX + bit_offset: 6 + bit_size: 1 + - name: CTR_TX + description: CTR_TX + bit_offset: 7 + bit_size: 1 + - name: EP_KIND + description: EP_KIND + bit_offset: 8 + bit_size: 1 + - name: EP_TYPE + description: EPTYPE + bit_offset: 9 + bit_size: 2 + enum: EP_TYPE + - name: SETUP + description: SETUP + bit_offset: 11 + bit_size: 1 + - name: STAT_RX + description: STAT_RX + bit_offset: 12 + bit_size: 2 + enum: STAT + - name: DTOG_RX + description: DTOG_RX + bit_offset: 14 + bit_size: 1 + - name: CTR_RX + description: CTR_RX + bit_offset: 15 + bit_size: 1 fieldset/FNR: description: frame number register fields: - - name: FN - description: FN - bit_offset: 0 - bit_size: 11 - - name: LSOF - description: LSOF - bit_offset: 11 - bit_size: 2 - - name: LCK - description: the frame timer remains in this state until an USB reset or USB suspend event occurs - bit_offset: 13 - bit_size: 1 - - name: RXDM - description: received data minus upstream port data line - bit_offset: 14 - bit_size: 1 - - name: RXDP - description: received data plus upstream port data line - bit_offset: 15 - bit_size: 1 + - name: FN + description: FN + bit_offset: 0 + bit_size: 11 + - name: LSOF + description: LSOF + bit_offset: 11 + bit_size: 2 + - name: LCK + description: the frame timer remains in this state until an USB reset or USB suspend event occurs + bit_offset: 13 + bit_size: 1 + - name: RXDM + description: received data minus upstream port data line + bit_offset: 14 + bit_size: 1 + - name: RXDP + description: received data plus upstream port data line + bit_offset: 15 + bit_size: 1 fieldset/ISTR: description: interrupt status register fields: - - name: EP_ID - description: EP_ID - bit_offset: 0 - bit_size: 4 - - name: DIR - description: DIR - bit_offset: 4 - bit_size: 1 - enum: DIR - - name: L1REQ - description: LPM command to enter the L1 state is successfully received and acknowledged - bit_offset: 7 - bit_size: 1 - - name: ESOF - description: an SOF packet is expected but not received - bit_offset: 8 - bit_size: 1 - - name: SOF - description: beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus - bit_offset: 9 - bit_size: 1 - - name: RESET - description: peripheral detects an active USB RESET signal at its inputs - bit_offset: 10 - bit_size: 1 - - name: SUSP - description: "no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus" - bit_offset: 11 - bit_size: 1 - - name: WKUP - description: activity is detected that wakes up the USB peripheral - bit_offset: 12 - bit_size: 1 - - name: ERR - description: "One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred" - bit_offset: 13 - bit_size: 1 - - name: PMAOVR - description: microcontroller has not been able to respond in time to an USB memory request - bit_offset: 14 - bit_size: 1 - - name: CTR - description: endpoint has successfully completed a transaction - bit_offset: 15 - bit_size: 1 + - name: EP_ID + description: EP_ID + bit_offset: 0 + bit_size: 4 + - name: DIR + description: DIR + bit_offset: 4 + bit_size: 1 + enum: DIR + - name: L1REQ + description: LPM command to enter the L1 state is successfully received and acknowledged + bit_offset: 7 + bit_size: 1 + - name: ESOF + description: an SOF packet is expected but not received + bit_offset: 8 + bit_size: 1 + - name: SOF + description: beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus + bit_offset: 9 + bit_size: 1 + - name: RESET + description: peripheral detects an active USB RESET signal at its inputs + bit_offset: 10 + bit_size: 1 + - name: SUSP + description: no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus + bit_offset: 11 + bit_size: 1 + - name: WKUP + description: activity is detected that wakes up the USB peripheral + bit_offset: 12 + bit_size: 1 + - name: ERR + description: One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred + bit_offset: 13 + bit_size: 1 + - name: PMAOVR + description: microcontroller has not been able to respond in time to an USB memory request + bit_offset: 14 + bit_size: 1 + - name: CTR + description: endpoint has successfully completed a transaction + bit_offset: 15 + bit_size: 1 fieldset/LPMCSR: description: LPM control and status register fields: - - name: LPMEN - description: enable the LPM support within the USB device - bit_offset: 0 - bit_size: 1 - - name: LPMACK - description: LPMACK - bit_offset: 1 - bit_size: 1 - enum: LPMACK - - name: REMWAKE - description: REMWAKE - bit_offset: 3 - bit_size: 1 - - name: BESL - description: BESL - bit_offset: 4 - bit_size: 4 + - name: LPMEN + description: enable the LPM support within the USB device + bit_offset: 0 + bit_size: 1 + - name: LPMACK + description: LPMACK + bit_offset: 1 + bit_size: 1 + enum: LPMACK + - name: REMWAKE + description: REMWAKE + bit_offset: 3 + bit_size: 1 + - name: BESL + description: BESL + bit_offset: 4 + bit_size: 4 enum/DIR: bit_size: 1 variants: - - name: To - description: data transmitted by the USB peripheral to the host PC - value: 0 - - name: From - description: data received by the USB peripheral from the host PC - value: 1 + - name: To + description: data transmitted by the USB peripheral to the host PC + value: 0 + - name: From + description: data received by the USB peripheral from the host PC + value: 1 enum/EP_TYPE: bit_size: 2 variants: - - name: Bulk - description: Bulk endpoint - value: 0 - - name: Control - description: Control endpoint - value: 1 - - name: Iso - description: Iso endpoint - value: 2 - - name: Interrupt - description: Interrupt endpoint - value: 3 + - name: Bulk + description: Bulk endpoint + value: 0 + - name: Control + description: Control endpoint + value: 1 + - name: Iso + description: Iso endpoint + value: 2 + - name: Interrupt + description: Interrupt endpoint + value: 3 enum/LPMACK: bit_size: 1 variants: - - name: Nyet - description: the valid LPM Token will be NYET - value: 0 - - name: Ack - description: the valid LPM Token will be ACK - value: 1 + - name: Nyet + description: the valid LPM Token will be NYET + value: 0 + - name: Ack + description: the valid LPM Token will be ACK + value: 1 enum/STAT: bit_size: 2 variants: - - name: Disabled - description: all requests addressed to this endpoint are ignored - value: 0 - - name: Stall - description: the endpoint is stalled and all requests result in a STALL handshake - value: 1 - - name: Nak - description: the endpoint is naked and all requests result in a NAK handshake - value: 2 - - name: Valid - description: "this endpoint is enabled, requests are ACKed" - value: 3 + - name: Disabled + description: all requests addressed to this endpoint are ignored + value: 0 + - name: Stall + description: the endpoint is stalled and all requests result in a STALL handshake + value: 1 + - name: Nak + description: the endpoint is naked and all requests result in a NAK handshake + value: 2 + - name: Valid + description: this endpoint is enabled, requests are ACKed + value: 3 diff --git a/data/registers/usb_v3.yaml b/data/registers/usb_v3.yaml index 21900e9..6af4763 100644 --- a/data/registers/usb_v3.yaml +++ b/data/registers/usb_v3.yaml @@ -1,355 +1,354 @@ ---- block/USB: description: Universal serial bus full-speed device interface items: - - name: EPR - description: endpoint register - array: - len: 8 - stride: 4 - byte_offset: 0 - fieldset: EPR - - name: CNTR - description: control register - byte_offset: 64 - fieldset: CNTR - - name: ISTR - description: interrupt status register - byte_offset: 68 - fieldset: ISTR - - name: FNR - description: frame number register - byte_offset: 72 - access: Read - fieldset: FNR - - name: DADDR - description: device address - byte_offset: 76 - fieldset: DADDR - - name: BTABLE - description: Buffer table address - byte_offset: 80 - fieldset: BTABLE - - name: LPMCSR - description: LPM control and status register - byte_offset: 84 - fieldset: LPMCSR - - name: BCDR - description: Battery Charging Detector - byte_offset: 88 - fieldset: BCDR + - name: EPR + description: endpoint register + array: + len: 8 + stride: 4 + byte_offset: 0 + fieldset: EPR + - name: CNTR + description: control register + byte_offset: 64 + fieldset: CNTR + - name: ISTR + description: interrupt status register + byte_offset: 68 + fieldset: ISTR + - name: FNR + description: frame number register + byte_offset: 72 + access: Read + fieldset: FNR + - name: DADDR + description: device address + byte_offset: 76 + fieldset: DADDR + - name: BTABLE + description: Buffer table address + byte_offset: 80 + fieldset: BTABLE + - name: LPMCSR + description: LPM control and status register + byte_offset: 84 + fieldset: LPMCSR + - name: BCDR + description: Battery Charging Detector + byte_offset: 88 + fieldset: BCDR fieldset/BCDR: description: Battery Charging Detector fields: - - name: BCDEN - description: Battery charging detector mode enable - bit_offset: 0 - bit_size: 1 - - name: DCDEN - description: Data contact detection mode enable - bit_offset: 1 - bit_size: 1 - - name: PDEN - description: Primary detection mode enable - bit_offset: 2 - bit_size: 1 - - name: SDEN - description: Secondary detection mode enable - bit_offset: 3 - bit_size: 1 - - name: DCDET - description: Data contact detection status - bit_offset: 4 - bit_size: 1 - - name: PDET - description: Primary detection status - bit_offset: 5 - bit_size: 1 - - name: SDET - description: Secondary detection status - bit_offset: 6 - bit_size: 1 - enum: SDET - - name: PS2DET - description: DM pull-up detection status - bit_offset: 7 - bit_size: 1 - - name: DPPU - description: DP pull-up control - bit_offset: 15 - bit_size: 1 + - name: BCDEN + description: Battery charging detector mode enable + bit_offset: 0 + bit_size: 1 + - name: DCDEN + description: Data contact detection mode enable + bit_offset: 1 + bit_size: 1 + - name: PDEN + description: Primary detection mode enable + bit_offset: 2 + bit_size: 1 + - name: SDEN + description: Secondary detection mode enable + bit_offset: 3 + bit_size: 1 + - name: DCDET + description: Data contact detection status + bit_offset: 4 + bit_size: 1 + - name: PDET + description: Primary detection status + bit_offset: 5 + bit_size: 1 + - name: SDET + description: Secondary detection status + bit_offset: 6 + bit_size: 1 + enum: SDET + - name: PS2DET + description: DM pull-up detection status + bit_offset: 7 + bit_size: 1 + - name: DPPU + description: DP pull-up control + bit_offset: 15 + bit_size: 1 fieldset/BTABLE: description: Buffer table address fields: - - name: BTABLE - description: BTABLE - bit_offset: 3 - bit_size: 13 + - name: BTABLE + description: BTABLE + bit_offset: 3 + bit_size: 13 fieldset/CNTR: description: control register fields: - - name: FRES - description: "Force a reset of the USB peripheral, exactly like a RESET signaling on the USB" - bit_offset: 0 - bit_size: 1 - - name: PDWN - description: Enter power down mode - bit_offset: 1 - bit_size: 1 - - name: LPMODE - description: Enter low-power mode - bit_offset: 2 - bit_size: 1 - - name: FSUSP - description: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected - bit_offset: 3 - bit_size: 1 - - name: RESUME - description: Resume request - bit_offset: 4 - bit_size: 1 - - name: L1RESUME - description: LPM L1 request request - bit_offset: 5 - bit_size: 1 - - name: L1REQM - description: "L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 7 - bit_size: 1 - - name: ESOFM - description: "ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 8 - bit_size: 1 - - name: SOFM - description: "SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 9 - bit_size: 1 - - name: RESETM - description: "RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 10 - bit_size: 1 - - name: SUSPM - description: "SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 11 - bit_size: 1 - - name: WKUPM - description: "WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 12 - bit_size: 1 - - name: ERRM - description: "ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 13 - bit_size: 1 - - name: PMAOVRM - description: "PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 14 - bit_size: 1 - - name: CTRM - description: "CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 15 - bit_size: 1 + - name: FRES + description: Force a reset of the USB peripheral, exactly like a RESET signaling on the USB + bit_offset: 0 + bit_size: 1 + - name: PDWN + description: Enter power down mode + bit_offset: 1 + bit_size: 1 + - name: LPMODE + description: Enter low-power mode + bit_offset: 2 + bit_size: 1 + - name: FSUSP + description: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected + bit_offset: 3 + bit_size: 1 + - name: RESUME + description: Resume request + bit_offset: 4 + bit_size: 1 + - name: L1RESUME + description: LPM L1 request request + bit_offset: 5 + bit_size: 1 + - name: L1REQM + description: L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 7 + bit_size: 1 + - name: ESOFM + description: ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 8 + bit_size: 1 + - name: SOFM + description: SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 9 + bit_size: 1 + - name: RESETM + description: RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 10 + bit_size: 1 + - name: SUSPM + description: SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 11 + bit_size: 1 + - name: WKUPM + description: WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 12 + bit_size: 1 + - name: ERRM + description: ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 13 + bit_size: 1 + - name: PMAOVRM + description: PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 14 + bit_size: 1 + - name: CTRM + description: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 15 + bit_size: 1 fieldset/DADDR: description: device address fields: - - name: ADD - description: device address - bit_offset: 0 - bit_size: 7 - - name: EF - description: USB device enabled - bit_offset: 7 - bit_size: 1 + - name: ADD + description: device address + bit_offset: 0 + bit_size: 7 + - name: EF + description: USB device enabled + bit_offset: 7 + bit_size: 1 fieldset/EPR: description: endpoint register fields: - - name: EA - description: EA - bit_offset: 0 - bit_size: 4 - - name: STAT_TX - description: STAT_TX - bit_offset: 4 - bit_size: 2 - enum: STAT - - name: DTOG_TX - description: DTOG_TX - bit_offset: 6 - bit_size: 1 - - name: CTR_TX - description: CTR_TX - bit_offset: 7 - bit_size: 1 - - name: EP_KIND - description: EP_KIND - bit_offset: 8 - bit_size: 1 - - name: EP_TYPE - description: EPTYPE - bit_offset: 9 - bit_size: 2 - enum: EP_TYPE - - name: SETUP - description: SETUP - bit_offset: 11 - bit_size: 1 - - name: STAT_RX - description: STAT_RX - bit_offset: 12 - bit_size: 2 - enum: STAT - - name: DTOG_RX - description: DTOG_RX - bit_offset: 14 - bit_size: 1 - - name: CTR_RX - description: CTR_RX - bit_offset: 15 - bit_size: 1 + - name: EA + description: EA + bit_offset: 0 + bit_size: 4 + - name: STAT_TX + description: STAT_TX + bit_offset: 4 + bit_size: 2 + enum: STAT + - name: DTOG_TX + description: DTOG_TX + bit_offset: 6 + bit_size: 1 + - name: CTR_TX + description: CTR_TX + bit_offset: 7 + bit_size: 1 + - name: EP_KIND + description: EP_KIND + bit_offset: 8 + bit_size: 1 + - name: EP_TYPE + description: EPTYPE + bit_offset: 9 + bit_size: 2 + enum: EP_TYPE + - name: SETUP + description: SETUP + bit_offset: 11 + bit_size: 1 + - name: STAT_RX + description: STAT_RX + bit_offset: 12 + bit_size: 2 + enum: STAT + - name: DTOG_RX + description: DTOG_RX + bit_offset: 14 + bit_size: 1 + - name: CTR_RX + description: CTR_RX + bit_offset: 15 + bit_size: 1 fieldset/FNR: description: frame number register fields: - - name: FN - description: FN - bit_offset: 0 - bit_size: 11 - - name: LSOF - description: LSOF - bit_offset: 11 - bit_size: 2 - - name: LCK - description: the frame timer remains in this state until an USB reset or USB suspend event occurs - bit_offset: 13 - bit_size: 1 - - name: RXDM - description: received data minus upstream port data line - bit_offset: 14 - bit_size: 1 - - name: RXDP - description: received data plus upstream port data line - bit_offset: 15 - bit_size: 1 + - name: FN + description: FN + bit_offset: 0 + bit_size: 11 + - name: LSOF + description: LSOF + bit_offset: 11 + bit_size: 2 + - name: LCK + description: the frame timer remains in this state until an USB reset or USB suspend event occurs + bit_offset: 13 + bit_size: 1 + - name: RXDM + description: received data minus upstream port data line + bit_offset: 14 + bit_size: 1 + - name: RXDP + description: received data plus upstream port data line + bit_offset: 15 + bit_size: 1 fieldset/ISTR: description: interrupt status register fields: - - name: EP_ID - description: EP_ID - bit_offset: 0 - bit_size: 4 - - name: DIR - description: DIR - bit_offset: 4 - bit_size: 1 - enum: DIR - - name: L1REQ - description: LPM command to enter the L1 state is successfully received and acknowledged - bit_offset: 7 - bit_size: 1 - - name: ESOF - description: an SOF packet is expected but not received - bit_offset: 8 - bit_size: 1 - - name: SOF - description: beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus - bit_offset: 9 - bit_size: 1 - - name: RESET - description: peripheral detects an active USB RESET signal at its inputs - bit_offset: 10 - bit_size: 1 - - name: SUSP - description: "no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus" - bit_offset: 11 - bit_size: 1 - - name: WKUP - description: activity is detected that wakes up the USB peripheral - bit_offset: 12 - bit_size: 1 - - name: ERR - description: "One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred" - bit_offset: 13 - bit_size: 1 - - name: PMAOVR - description: microcontroller has not been able to respond in time to an USB memory request - bit_offset: 14 - bit_size: 1 - - name: CTR - description: endpoint has successfully completed a transaction - bit_offset: 15 - bit_size: 1 + - name: EP_ID + description: EP_ID + bit_offset: 0 + bit_size: 4 + - name: DIR + description: DIR + bit_offset: 4 + bit_size: 1 + enum: DIR + - name: L1REQ + description: LPM command to enter the L1 state is successfully received and acknowledged + bit_offset: 7 + bit_size: 1 + - name: ESOF + description: an SOF packet is expected but not received + bit_offset: 8 + bit_size: 1 + - name: SOF + description: beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus + bit_offset: 9 + bit_size: 1 + - name: RESET + description: peripheral detects an active USB RESET signal at its inputs + bit_offset: 10 + bit_size: 1 + - name: SUSP + description: no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus + bit_offset: 11 + bit_size: 1 + - name: WKUP + description: activity is detected that wakes up the USB peripheral + bit_offset: 12 + bit_size: 1 + - name: ERR + description: One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred + bit_offset: 13 + bit_size: 1 + - name: PMAOVR + description: microcontroller has not been able to respond in time to an USB memory request + bit_offset: 14 + bit_size: 1 + - name: CTR + description: endpoint has successfully completed a transaction + bit_offset: 15 + bit_size: 1 fieldset/LPMCSR: description: LPM control and status register fields: - - name: LPMEN - description: enable the LPM support within the USB device - bit_offset: 0 - bit_size: 1 - - name: LPMACK - description: LPMACK - bit_offset: 1 - bit_size: 1 - enum: LPMACK - - name: REMWAKE - description: REMWAKE - bit_offset: 3 - bit_size: 1 - - name: BESL - description: BESL - bit_offset: 4 - bit_size: 4 + - name: LPMEN + description: enable the LPM support within the USB device + bit_offset: 0 + bit_size: 1 + - name: LPMACK + description: LPMACK + bit_offset: 1 + bit_size: 1 + enum: LPMACK + - name: REMWAKE + description: REMWAKE + bit_offset: 3 + bit_size: 1 + - name: BESL + description: BESL + bit_offset: 4 + bit_size: 4 enum/DIR: bit_size: 1 variants: - - name: To - description: data transmitted by the USB peripheral to the host PC - value: 0 - - name: From - description: data received by the USB peripheral from the host PC - value: 1 + - name: To + description: data transmitted by the USB peripheral to the host PC + value: 0 + - name: From + description: data received by the USB peripheral from the host PC + value: 1 enum/EP_TYPE: bit_size: 2 variants: - - name: Bulk - description: Bulk endpoint - value: 0 - - name: Control - description: Control endpoint - value: 1 - - name: Iso - description: Iso endpoint - value: 2 - - name: Interrupt - description: Interrupt endpoint - value: 3 + - name: Bulk + description: Bulk endpoint + value: 0 + - name: Control + description: Control endpoint + value: 1 + - name: Iso + description: Iso endpoint + value: 2 + - name: Interrupt + description: Interrupt endpoint + value: 3 enum/LPMACK: bit_size: 1 variants: - - name: Nyet - description: the valid LPM Token will be NYET - value: 0 - - name: Ack - description: the valid LPM Token will be ACK - value: 1 + - name: Nyet + description: the valid LPM Token will be NYET + value: 0 + - name: Ack + description: the valid LPM Token will be ACK + value: 1 enum/SDET: bit_size: 1 variants: - - name: CDP - description: CDP detected - value: 0 - - name: DCP - description: DCP detected - value: 1 + - name: CDP + description: CDP detected + value: 0 + - name: DCP + description: DCP detected + value: 1 enum/STAT: bit_size: 2 variants: - - name: Disabled - description: all requests addressed to this endpoint are ignored - value: 0 - - name: Stall - description: the endpoint is stalled and all requests result in a STALL handshake - value: 1 - - name: Nak - description: the endpoint is naked and all requests result in a NAK handshake - value: 2 - - name: Valid - description: "this endpoint is enabled, requests are ACKed" - value: 3 + - name: Disabled + description: all requests addressed to this endpoint are ignored + value: 0 + - name: Stall + description: the endpoint is stalled and all requests result in a STALL handshake + value: 1 + - name: Nak + description: the endpoint is naked and all requests result in a NAK handshake + value: 2 + - name: Valid + description: this endpoint is enabled, requests are ACKed + value: 3 diff --git a/data/registers/usb_v4.yaml b/data/registers/usb_v4.yaml index da2a5ce..56f2809 100644 --- a/data/registers/usb_v4.yaml +++ b/data/registers/usb_v4.yaml @@ -1,384 +1,383 @@ ---- block/USB: description: Universal serial bus full-speed host/device interface items: - - name: EPR - description: endpoint/channel - array: - len: 8 - stride: 4 - byte_offset: 0 - fieldset: EPR - - name: CNTR - description: control register - byte_offset: 64 - fieldset: CNTR - - name: ISTR - description: interrupt status register - byte_offset: 68 - fieldset: ISTR - - name: FNR - description: frame number register - byte_offset: 72 - access: Read - fieldset: FNR - - name: DADDR - description: device address - byte_offset: 76 - fieldset: DADDR - - name: LPMCSR - description: LPM control and status register - byte_offset: 84 - fieldset: LPMCSR - - name: BCDR - description: Battery charging detector - byte_offset: 88 - fieldset: BCDR + - name: EPR + description: endpoint/channel + array: + len: 8 + stride: 4 + byte_offset: 0 + fieldset: EPR + - name: CNTR + description: control register + byte_offset: 64 + fieldset: CNTR + - name: ISTR + description: interrupt status register + byte_offset: 68 + fieldset: ISTR + - name: FNR + description: frame number register + byte_offset: 72 + access: Read + fieldset: FNR + - name: DADDR + description: device address + byte_offset: 76 + fieldset: DADDR + - name: LPMCSR + description: LPM control and status register + byte_offset: 84 + fieldset: LPMCSR + - name: BCDR + description: Battery charging detector + byte_offset: 88 + fieldset: BCDR fieldset/BCDR: description: Battery charging detector fields: - - name: BCDEN - description: "Battery charging detector (BCD) enable Device mode This bit is set by the software to enable the BCD support within the USB device. When enabled, the USB PHY is fully controlled by BCD and cannot be used for normal communication. Once the BCD discovery is finished, the BCD should be placed in OFF mode by clearing this bit to '0 in order to allow the normal USB operation." - bit_offset: 0 - bit_size: 1 - - name: DCDEN - description: "Data contact detection (DCD) mode enable Device mode This bit is set by the software to put the BCD into DCD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly." - bit_offset: 1 - bit_size: 1 - - name: PDEN - description: "Primary detection (PD) mode enable Device mode This bit is set by the software to put the BCD into PD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly." - bit_offset: 2 - bit_size: 1 - - name: SDEN - description: "Secondary detection (SD) mode enable Device mode This bit is set by the software to put the BCD into SD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly." - bit_offset: 3 - bit_size: 1 - - name: DCDET - description: Data contact detection (DCD) status Device mode This bit gives the result of DCD. - bit_offset: 4 - bit_size: 1 - - name: PDET - description: Primary detection (PD) status Device mode This bit gives the result of PD. - bit_offset: 5 - bit_size: 1 - - name: SDET - description: Secondary detection (SD) status Device mode This bit gives the result of SD. - bit_offset: 6 - bit_size: 1 - enum: SDET - - name: PS2DET - description: "DM pull-up detection status Device mode This bit is active only during PD and gives the result of comparison between DM voltage level and VLGC threshold. In normal situation, the DM level should be below this threshold. If it is above, it means that the DM is externally pulled high. This can be caused by connection to a PS2 port (which pulls-up both DP and DM lines) or to some proprietary charger not following the BCD specification." - bit_offset: 7 - bit_size: 1 - - name: DPPU - description: "DP pull-up / DPDM pull-down Device mode This bit is set by software to enable the embedded pull-up on DP line. Clearing it to '0 can be used to signal disconnect to the host when needed by the user software. Host mode This bit is set by software to enable the embedded pull-down on DP and DM lines." - bit_offset: 15 - bit_size: 1 + - name: BCDEN + description: Battery charging detector (BCD) enable Device mode This bit is set by the software to enable the BCD support within the USB device. When enabled, the USB PHY is fully controlled by BCD and cannot be used for normal communication. Once the BCD discovery is finished, the BCD should be placed in OFF mode by clearing this bit to '0 in order to allow the normal USB operation. + bit_offset: 0 + bit_size: 1 + - name: DCDEN + description: Data contact detection (DCD) mode enable Device mode This bit is set by the software to put the BCD into DCD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. + bit_offset: 1 + bit_size: 1 + - name: PDEN + description: Primary detection (PD) mode enable Device mode This bit is set by the software to put the BCD into PD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. + bit_offset: 2 + bit_size: 1 + - name: SDEN + description: Secondary detection (SD) mode enable Device mode This bit is set by the software to put the BCD into SD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. + bit_offset: 3 + bit_size: 1 + - name: DCDET + description: Data contact detection (DCD) status Device mode This bit gives the result of DCD. + bit_offset: 4 + bit_size: 1 + - name: PDET + description: Primary detection (PD) status Device mode This bit gives the result of PD. + bit_offset: 5 + bit_size: 1 + - name: SDET + description: Secondary detection (SD) status Device mode This bit gives the result of SD. + bit_offset: 6 + bit_size: 1 + enum: SDET + - name: PS2DET + description: DM pull-up detection status Device mode This bit is active only during PD and gives the result of comparison between DM voltage level and VLGC threshold. In normal situation, the DM level should be below this threshold. If it is above, it means that the DM is externally pulled high. This can be caused by connection to a PS2 port (which pulls-up both DP and DM lines) or to some proprietary charger not following the BCD specification. + bit_offset: 7 + bit_size: 1 + - name: DPPU + description: DP pull-up / DPDM pull-down Device mode This bit is set by software to enable the embedded pull-up on DP line. Clearing it to '0 can be used to signal disconnect to the host when needed by the user software. Host mode This bit is set by software to enable the embedded pull-down on DP and DM lines. + bit_offset: 15 + bit_size: 1 fieldset/CNTR: description: control register fields: - - name: FRES - description: "Force a reset of the USB peripheral, exactly like a RESET signaling on the USB" - bit_offset: 0 - bit_size: 1 - - name: PDWN - description: "Power down This bit is used to completely switch off all USB-related analog parts if it is required to completely disable the USB peripheral for any reason. When this bit is set, the USB peripheral is disconnected from the transceivers and it cannot be used." - bit_offset: 1 - bit_size: 1 - - name: LPMODE - description: "Suspend state effective This bit is set by hardware as soon as the suspend state entered through the SUSPEN control gets internally effective. In this state USB activity is suspended, USB clock is gated, transceiver is set in low power mode by disabling the differential receiver. Only asynchronous wakeup logic and single ended receiver is kept alive to detect remote wakeup or resume events. Software must poll this bit to confirm it to be set before any STOP mode entry. This bit is cleared by hardware simultaneously to the WAKEUP flag being set." - bit_offset: 2 - bit_size: 1 - - name: FSUSP - description: "Suspend state enable Device mode Software can set this bit when the SUSP interrupt is received, which is issued when no traffic is received by the USB peripheral for 3 ms. Software can also set this bit when the L1REQ interrupt is received with positive acknowledge sent. As soon as the suspend state is propagated internally all device activity is stopped, USB clock is gated, USB transceiver is set into low power mode and the SUSPRDY bit is set by hardware. In the case that device application wants to purse more aggressive power saving by stopping the USB clock source and by moving the microcontroller to stop mode, as in the case of bus powered device application, it must first wait few cycles to see the SUSPRDY=1 acknowledge the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. Host mode Software can set this bit when Host application has nothing scheduled for the next frames and wants to enter long term power saving. When set, it stops immediately SOF generation and any other host activity, gates the USB clock and sets the transceiver in low power mode. If any USB transaction is on-going at the time SUSPEN is set, suspend is entered at the end of the current transaction. As soon as suspend state is propagated internally and gets effective the SUSPRDY bit is set. In the case that host application wants to purse more aggressive power saving by stopping the USB clock source and by moving the micro-controller to STOP mode, it must first wait few cycles to see SUSPRDY=1 acknowledge to the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set." - bit_offset: 3 - bit_size: 1 - - name: RESUME - description: "L2 Remote Wakeup / Resume driver Device mode The microcontroller can set this bit to send remote wake-up signaling to the Host. It must be activated, according to USB specifications, for no less than 1ms and no more than 15ms after which the Host PC is ready to drive the resume sequence up to its end. Host mode Software sets this bit to send resume signaling to the device. Software clears this bit to send end of resume to device and restart SOF generation. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt." - bit_offset: 4 - bit_size: 1 - - name: L1RESUME - description: "L1 Remote Wakeup / Resume driver Device mode Software sets this bit to send a LPM L1 50us remote wakeup signaling to the host. After the signaling ends, this bit is cleared by hardware. Host mode Software sets this bit to send L1 resume signaling to device. Resume duration and next SOF generation is automatically driven to set the restart of USB activity timely aligned with the programmed BESL value. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt. This bit is cleared by hardware at the end of resume." - bit_offset: 5 - bit_size: 1 - - name: L1REQM - description: LPM L1 state request interrupt mask - bit_offset: 7 - bit_size: 1 - - name: ESOFM - description: Expected start of frame interrupt mask - bit_offset: 8 - bit_size: 1 - - name: SOFM - description: Start of frame interrupt mask - bit_offset: 9 - bit_size: 1 - - name: RESETM - description: reset interrupt mask - bit_offset: 10 - bit_size: 1 - - name: SUSPM - description: Suspend mode interrupt mask - bit_offset: 11 - bit_size: 1 - - name: WKUPM - description: Wakeup interrupt mask - bit_offset: 12 - bit_size: 1 - - name: ERRM - description: Error interrupt mask - bit_offset: 13 - bit_size: 1 - - name: PMAOVRM - description: Packet memory area over / underrun interrupt mask - bit_offset: 14 - bit_size: 1 - - name: CTRM - description: "CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" - bit_offset: 15 - bit_size: 1 - - name: THR512M - description: 512 byte threshold interrupt mask - bit_offset: 16 - bit_size: 1 - - name: HOST - description: HOST mode HOST bit selects betweens Host or Device USB mode of operation. It must be set before enabling the USB peripheral by the function enable bit. - bit_offset: 31 - bit_size: 1 + - name: FRES + description: Force a reset of the USB peripheral, exactly like a RESET signaling on the USB + bit_offset: 0 + bit_size: 1 + - name: PDWN + description: Power down This bit is used to completely switch off all USB-related analog parts if it is required to completely disable the USB peripheral for any reason. When this bit is set, the USB peripheral is disconnected from the transceivers and it cannot be used. + bit_offset: 1 + bit_size: 1 + - name: LPMODE + description: Suspend state effective This bit is set by hardware as soon as the suspend state entered through the SUSPEN control gets internally effective. In this state USB activity is suspended, USB clock is gated, transceiver is set in low power mode by disabling the differential receiver. Only asynchronous wakeup logic and single ended receiver is kept alive to detect remote wakeup or resume events. Software must poll this bit to confirm it to be set before any STOP mode entry. This bit is cleared by hardware simultaneously to the WAKEUP flag being set. + bit_offset: 2 + bit_size: 1 + - name: FSUSP + description: Suspend state enable Device mode Software can set this bit when the SUSP interrupt is received, which is issued when no traffic is received by the USB peripheral for 3 ms. Software can also set this bit when the L1REQ interrupt is received with positive acknowledge sent. As soon as the suspend state is propagated internally all device activity is stopped, USB clock is gated, USB transceiver is set into low power mode and the SUSPRDY bit is set by hardware. In the case that device application wants to purse more aggressive power saving by stopping the USB clock source and by moving the microcontroller to stop mode, as in the case of bus powered device application, it must first wait few cycles to see the SUSPRDY=1 acknowledge the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. Host mode Software can set this bit when Host application has nothing scheduled for the next frames and wants to enter long term power saving. When set, it stops immediately SOF generation and any other host activity, gates the USB clock and sets the transceiver in low power mode. If any USB transaction is on-going at the time SUSPEN is set, suspend is entered at the end of the current transaction. As soon as suspend state is propagated internally and gets effective the SUSPRDY bit is set. In the case that host application wants to purse more aggressive power saving by stopping the USB clock source and by moving the micro-controller to STOP mode, it must first wait few cycles to see SUSPRDY=1 acknowledge to the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. + bit_offset: 3 + bit_size: 1 + - name: RESUME + description: L2 Remote Wakeup / Resume driver Device mode The microcontroller can set this bit to send remote wake-up signaling to the Host. It must be activated, according to USB specifications, for no less than 1ms and no more than 15ms after which the Host PC is ready to drive the resume sequence up to its end. Host mode Software sets this bit to send resume signaling to the device. Software clears this bit to send end of resume to device and restart SOF generation. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt. + bit_offset: 4 + bit_size: 1 + - name: L1RESUME + description: L1 Remote Wakeup / Resume driver Device mode Software sets this bit to send a LPM L1 50us remote wakeup signaling to the host. After the signaling ends, this bit is cleared by hardware. Host mode Software sets this bit to send L1 resume signaling to device. Resume duration and next SOF generation is automatically driven to set the restart of USB activity timely aligned with the programmed BESL value. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt. This bit is cleared by hardware at the end of resume. + bit_offset: 5 + bit_size: 1 + - name: L1REQM + description: LPM L1 state request interrupt mask + bit_offset: 7 + bit_size: 1 + - name: ESOFM + description: Expected start of frame interrupt mask + bit_offset: 8 + bit_size: 1 + - name: SOFM + description: Start of frame interrupt mask + bit_offset: 9 + bit_size: 1 + - name: RESETM + description: reset interrupt mask + bit_offset: 10 + bit_size: 1 + - name: SUSPM + description: Suspend mode interrupt mask + bit_offset: 11 + bit_size: 1 + - name: WKUPM + description: Wakeup interrupt mask + bit_offset: 12 + bit_size: 1 + - name: ERRM + description: Error interrupt mask + bit_offset: 13 + bit_size: 1 + - name: PMAOVRM + description: Packet memory area over / underrun interrupt mask + bit_offset: 14 + bit_size: 1 + - name: CTRM + description: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + bit_offset: 15 + bit_size: 1 + - name: THR512M + description: 512 byte threshold interrupt mask + bit_offset: 16 + bit_size: 1 + - name: HOST + description: HOST mode HOST bit selects betweens Host or Device USB mode of operation. It must be set before enabling the USB peripheral by the function enable bit. + bit_offset: 31 + bit_size: 1 fieldset/DADDR: description: device address fields: - - name: ADD - description: Device address Device mode These bits contain the USB function address assigned by the host PC during the enumeration process. Both this field and the endpoint/channel Address (EA) field in the associated USB_EPnR register must match with the information contained in a USB token in order to handle a transaction to the required endpoint. Host mode These bits contain the address transmitted with the LPM transaction - bit_offset: 0 - bit_size: 7 - - name: EF - description: "Enable function This bit is set by the software to enable the USB device. The address of this device is contained in the following ADD[6:0] bits. If this bit is at '0 no transactions are handled, irrespective of the settings of USB_EPnR registers." - bit_offset: 7 - bit_size: 1 + - name: ADD + description: Device address Device mode These bits contain the USB function address assigned by the host PC during the enumeration process. Both this field and the endpoint/channel Address (EA) field in the associated USB_EPnR register must match with the information contained in a USB token in order to handle a transaction to the required endpoint. Host mode These bits contain the address transmitted with the LPM transaction + bit_offset: 0 + bit_size: 7 + - name: EF + description: Enable function This bit is set by the software to enable the USB device. The address of this device is contained in the following ADD[6:0] bits. If this bit is at '0 no transactions are handled, irrespective of the settings of USB_EPnR registers. + bit_offset: 7 + bit_size: 1 fieldset/EPR: description: endpoint/channel 0 register fields: - - name: EA - description: endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. - bit_offset: 0 - bit_size: 4 - - name: STAT_TX - description: "Status bits, for transmission transfers Device mode These bits contain the information about the endpoint status, listed in . These bits can be toggled by the software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STTX bits to NAK, when a correct transfer has occurred (VTTX=1) corresponding to a IN or SETUP (control only) transaction addressed to this channel/endpoint. It then waits for the software to prepare the next set of data to be transmitted. Double-buffered bulk endpoints implement a special transaction flow control, which controls the status based on buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can only be VALID or DISABLED. Therefore, the hardware cannot change the status of the channel/endpoint/channel after a successful transaction. If the software sets the STTX bits to STALL or NAK for an Isochronous channel/endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode Same as STRX behaviour but for IN transactions (TBC)" - bit_offset: 4 - bit_size: 2 - enum: STAT - - name: DTOG_TX - description: "Data Toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint. If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to ) If the endpoint/channel is Isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (Refer to ). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for Isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGTX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can only be toggled by writing 1." - bit_offset: 6 - bit_size: 1 - - name: CTR_TX - description: "Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written. Host mode Same of VTRX behaviour but for USB OUT and SETUP transactions." - bit_offset: 7 - bit_size: 1 - - name: EP_KIND - description: "endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the EP_TYPE bits. summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Double-buffered endpoints. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required." - bit_offset: 8 - bit_size: 1 - - name: EP_TYPE - description: "USB type of transaction These bits configure the behavior of this endpoint/channel as described in endpoint/channel type encoding on page 2001. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral will not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet will be accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of Isochronous channels/endpoints is explained in transfers" - bit_offset: 9 - bit_size: 2 - enum: EP_TYPE - - name: SETUP - description: "Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated." - bit_offset: 11 - bit_size: 1 - - name: STAT_RX - description: "Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Reception status encoding on page 2000.These bits can be toggled by software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STRX bits to NAK when a correct transfer has occurred (VTRX=1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledge a new transaction Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STRX bits to 'STALL or 'NAK for an Isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STRX table of states: -\tDISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the Host execution list. If the aborted transaction was already under execution it will be regularly terminated on the USB but the relative VTRX interrupt is not generated. -\tVALID An Host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the Host Frame Schedure to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel will be re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application should not retry transmission but reset the USB and re-enumerate." - bit_offset: 12 - bit_size: 2 - enum: STAT - - name: DTOG_RX - description: "Data Toggle, for reception transfers If the endpoint/channel is not Isochronous, this bit contains the expected value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device) or acknowledged by device (in host). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to ). If the endpoint/channel is Isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Isochronous transfers). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGRX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1." - bit_offset: 14 - bit_size: 1 - - name: CTR_RX - description: "USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the VTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STRX field of this register. One naked transaction keeps pending and is automatically retried by the Host at the next frame, or the Host can immediately retry by resetting STRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STRX field of this register. Host application should consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STRX field of this register. Host application should read received data from USBRAM and re-arm the channel by writing VALID to the STRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STRX field of this register. Host application should read received data from USBRAM and toggle the DTOGTX bit of this register. This bit is read/write but only '0 can be written, writing 1 has no effect." - bit_offset: 15 - bit_size: 1 - - name: DEVADDR - description: Host mode Device address assigned to the endpoint during the enumeration process. - bit_offset: 16 - bit_size: 7 - - name: NAK - description: Host mode This bit is set by the hardware when a device responds with a NAK. Software can be use this bit to monitoring the number of NAKs received from a device. - bit_offset: 23 - bit_size: 1 - - name: LS_EP - description: Low speed endpoint Host with HUB only Host mode This bit is set by the software to send an LS transaction to the corresponding endpoint. - bit_offset: 24 - bit_size: 1 - - name: ERR_TX - description: "Transmit error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated." - bit_offset: 25 - bit_size: 1 - - name: ERR_RX - description: "Receive error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated." - bit_offset: 26 - bit_size: 1 + - name: EA + description: endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + bit_offset: 0 + bit_size: 4 + - name: STAT_TX + description: Status bits, for transmission transfers Device mode These bits contain the information about the endpoint status, listed in . These bits can be toggled by the software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STTX bits to NAK, when a correct transfer has occurred (VTTX=1) corresponding to a IN or SETUP (control only) transaction addressed to this channel/endpoint. It then waits for the software to prepare the next set of data to be transmitted. Double-buffered bulk endpoints implement a special transaction flow control, which controls the status based on buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can only be VALID or DISABLED. Therefore, the hardware cannot change the status of the channel/endpoint/channel after a successful transaction. If the software sets the STTX bits to STALL or NAK for an Isochronous channel/endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode Same as STRX behaviour but for IN transactions (TBC) + bit_offset: 4 + bit_size: 2 + enum: STAT + - name: DTOG_TX + description: Data Toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint. If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to ) If the endpoint/channel is Isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (Refer to ). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for Isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGTX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can only be toggled by writing 1. + bit_offset: 6 + bit_size: 1 + - name: CTR_TX + description: Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written. Host mode Same of VTRX behaviour but for USB OUT and SETUP transactions. + bit_offset: 7 + bit_size: 1 + - name: EP_KIND + description: 'endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the EP_TYPE bits. summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Double-buffered endpoints. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required.' + bit_offset: 8 + bit_size: 1 + - name: EP_TYPE + description: USB type of transaction These bits configure the behavior of this endpoint/channel as described in endpoint/channel type encoding on page 2001. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral will not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet will be accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of Isochronous channels/endpoints is explained in transfers + bit_offset: 9 + bit_size: 2 + enum: EP_TYPE + - name: SETUP + description: Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + bit_offset: 11 + bit_size: 1 + - name: STAT_RX + description: "Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Reception status encoding on page 2000.These bits can be toggled by software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STRX bits to NAK when a correct transfer has occurred (VTRX=1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledge a new transaction Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STRX bits to 'STALL or 'NAK for an Isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STRX table of states: -\tDISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the Host execution list. If the aborted transaction was already under execution it will be regularly terminated on the USB but the relative VTRX interrupt is not generated. -\tVALID An Host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the Host Frame Schedure to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel will be re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application should not retry transmission but reset the USB and re-enumerate." + bit_offset: 12 + bit_size: 2 + enum: STAT + - name: DTOG_RX + description: Data Toggle, for reception transfers If the endpoint/channel is not Isochronous, this bit contains the expected value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device) or acknowledged by device (in host). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to ). If the endpoint/channel is Isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Isochronous transfers). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGRX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + bit_offset: 14 + bit_size: 1 + - name: CTR_RX + description: USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the VTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STRX field of this register. One naked transaction keeps pending and is automatically retried by the Host at the next frame, or the Host can immediately retry by resetting STRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STRX field of this register. Host application should consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STRX field of this register. Host application should read received data from USBRAM and re-arm the channel by writing VALID to the STRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STRX field of this register. Host application should read received data from USBRAM and toggle the DTOGTX bit of this register. This bit is read/write but only '0 can be written, writing 1 has no effect. + bit_offset: 15 + bit_size: 1 + - name: DEVADDR + description: Host mode Device address assigned to the endpoint during the enumeration process. + bit_offset: 16 + bit_size: 7 + - name: NAK + description: Host mode This bit is set by the hardware when a device responds with a NAK. Software can be use this bit to monitoring the number of NAKs received from a device. + bit_offset: 23 + bit_size: 1 + - name: LS_EP + description: Low speed endpoint Host with HUB only Host mode This bit is set by the software to send an LS transaction to the corresponding endpoint. + bit_offset: 24 + bit_size: 1 + - name: ERR_TX + description: Transmit error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. + bit_offset: 25 + bit_size: 1 + - name: ERR_RX + description: Receive error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. + bit_offset: 26 + bit_size: 1 fieldset/FNR: description: frame number register fields: - - name: FN - description: Frame number This bit field contains the 11-bits frame number contained in the last received SOF packet. The frame number is incremented for every frame sent by the host and it is useful for Isochronous transfers. This bit field is updated on the generation of an SOF interrupt. - bit_offset: 0 - bit_size: 11 - - name: LSOF - description: "Lost SOF Device mode These bits are written by the hardware when an ESOF interrupt is generated, counting the number of consecutive SOF packets lost. At the reception of an SOF packet, these bits are cleared." - bit_offset: 11 - bit_size: 2 - - name: LCK - description: "Locked Device mode This bit is set by the hardware when at least two consecutive SOF packets have been received after the end of an USB reset condition or after the end of an USB resume sequence. Once locked, the frame timer remains in this state until an USB reset or USB suspend event occurs." - bit_offset: 13 - bit_size: 1 - - name: RXDM - description: Receive data - line status This bit can be used to observe the status of received data minus upstream port data line. It can be used during end-of-suspend routines to help determining the wakeup event. - bit_offset: 14 - bit_size: 1 - - name: RXDP - description: Receive data + line status This bit can be used to observe the status of received data plus upstream port data line. It can be used during end-of-suspend routines to help determining the wakeup event. - bit_offset: 15 - bit_size: 1 + - name: FN + description: Frame number This bit field contains the 11-bits frame number contained in the last received SOF packet. The frame number is incremented for every frame sent by the host and it is useful for Isochronous transfers. This bit field is updated on the generation of an SOF interrupt. + bit_offset: 0 + bit_size: 11 + - name: LSOF + description: Lost SOF Device mode These bits are written by the hardware when an ESOF interrupt is generated, counting the number of consecutive SOF packets lost. At the reception of an SOF packet, these bits are cleared. + bit_offset: 11 + bit_size: 2 + - name: LCK + description: Locked Device mode This bit is set by the hardware when at least two consecutive SOF packets have been received after the end of an USB reset condition or after the end of an USB resume sequence. Once locked, the frame timer remains in this state until an USB reset or USB suspend event occurs. + bit_offset: 13 + bit_size: 1 + - name: RXDM + description: Receive data - line status This bit can be used to observe the status of received data minus upstream port data line. It can be used during end-of-suspend routines to help determining the wakeup event. + bit_offset: 14 + bit_size: 1 + - name: RXDP + description: Receive data + line status This bit can be used to observe the status of received data plus upstream port data line. It can be used during end-of-suspend routines to help determining the wakeup event. + bit_offset: 15 + bit_size: 1 fieldset/ISTR: description: interrupt status register fields: - - name: EP_ID - description: "Device Endpoint / Host channel identification number These bits are written by the hardware according to the host channel or device endpoint number, which generated the interrupt request. If several endpoint/channel transactions are pending, the hardware writes the identification number related to the endpoint/channel having the highest priority defined in the following way: Two levels are defined, in order of priority: Isochronous and double-buffered bulk channels/endpoints are considered first and then the others are examined. If more than one endpoint/channel from the same set is requesting an interrupt, the IDN bits in USB_ISTR register are assigned according to the lowest requesting register, CHEP0R having the highest priority followed by CHEP1R and so on. The application software can assign a register to each endpoint/channel according to this priority scheme, so as to order the concurring endpoint/channel requests in a suitable way. These bits are read only." - bit_offset: 0 - bit_size: 4 - - name: DIR - description: "Direction of transaction This bit is written by the hardware according to the direction of the successful transaction, which generated the interrupt request. If DIR bit=0, VTTX bit is set in the USB_EPnR register related to the interrupting endpoint. The interrupting transaction is of IN type (data transmitted by the USB peripheral to the host PC). If DIR bit=1, VTRX bit or both VTTX/VTRX are set in the USB_EPnR register related to the interrupting endpoint. The interrupting transaction is of OUT type (data received by the USB peripheral from the host PC) or two pending transactions are waiting to be processed. This information can be used by the application software to access the USB_EPnR bits related to the triggering transaction since it represents the direction having the interrupt pending. This bit is read-only." - bit_offset: 4 - bit_size: 1 - enum: DIR - - name: L1REQ - description: "LPM L1 state request This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. This bit is read/write but only '0 can be written and writing '1 has no effect." - bit_offset: 7 - bit_size: 1 - - name: ESOF - description: "Expected start of frame This bit is set by the hardware when an SOF packet is expected but not received. The host sends an SOF packet each 1 ms, but if the device does not receive it properly, the Suspend Timer issues this interrupt. If three consecutive ESOF interrupts are generated (i.e. three SOF packets are lost) without any traffic occurring in between, a SUSP interrupt is generated. This bit is set even when the missing SOF packets occur while the Suspend Timer is not yet locked. This bit is read/write but only '0 can be written and writing '1 has no effect." - bit_offset: 8 - bit_size: 1 - - name: SOF - description: "Start of frame This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus. The interrupt service routine may monitor the SOF events to have a 1 ms synchronization event to the USB host and to safely read the USB_FNR register which is updated at the SOF packet reception (this could be useful for isochronous applications). This bit is read/write but only '0 can be written and writing '1 has no effect." - bit_offset: 9 - bit_size: 1 - - name: RESET - description: reset request Device mode This bit is set by hardware when an USB reset is released by the host and the bus returns to idle. USB reset state is internally detected after the sampling of 60 consecutive SE0 cycles. Host mode This bit is set by hardware when device connection or device disconnection is detected. Device connection is signaled after J state is sampled for 22cycles consecutively from unconnected state. Device disconnection is signaled after SE0 state is sampled for 22cycles consecutively from connected state. - bit_offset: 10 - bit_size: 1 - - name: SUSP - description: "Suspend mode request This bit is set by the hardware when no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus. The suspend condition check is enabled immediately after any USB reset and it is disabled by the hardware when the suspend mode is active (SUSPEN=1) until the end of resume sequence. This bit is read/write but only '0 can be written and writing '1 has no effect." - bit_offset: 11 - bit_size: 1 - - name: WKUP - description: "Wakeup This bit is set to 1 by the hardware when, during suspend mode, activity is detected that wakes up the USB peripheral. This event asynchronously clears the LP_MODE bit in the CTLR register and activates the USB_WAKEUP line, which can be used to notify the rest of the device (e.g. wakeup unit) about the start of the resume process. This bit is read/write but only '0 can be written and writing '1 has no effect." - bit_offset: 12 - bit_size: 1 - - name: ERR - description: "Error This flag is set whenever one of the errors listed below has occurred: NANS:\tNo ANSwer. The timeout for a host response has expired. CRC:\tCyclic Redundancy Check error. One of the received CRCs, either in the token or in the data, was wrong. BST:\tBit Stuffing error. A bit stuffing error was detected anywhere in the PID, data, and/or CRC. FVIO:\tFraming format Violation. A non-standard frame was received (EOP not in the right place, wrong token sequence, etc.). The USB software can usually ignore errors, since the USB peripheral and the PC host manage retransmission in case of errors in a fully transparent way. This interrupt can be useful during the software development phase, or to monitor the quality of transmission over the USB bus, to flag possible problems to the user (e.g. loose connector, too noisy environment, broken conductor in the USB cable and so on). This bit is read/write but only '0 can be written and writing '1 has no effect." - bit_offset: 13 - bit_size: 1 - - name: PMAOVR - description: "Packet memory area over / underrun This bit is set if the microcontroller has not been able to respond in time to an USB memory request. The USB peripheral handles this event in the following way: During reception an ACK handshake packet is not sent, during transmission a bit-stuff error is forced on the transmitted stream; in both cases the host will retry the transaction. The PMAOVR interrupt should never occur during normal operations. Since the failed transaction is retried by the host, the application software has the chance to speed-up device operations during this interrupt handling, to be ready for the next transaction retry; however this does not happen during Isochronous transfers (no isochronous transaction is anyway retried) leading to a loss of data in this case. This bit is read/write but only '0 can be written and writing '1 has no effect." - bit_offset: 14 - bit_size: 1 - - name: CTR - description: Correct transfer This bit is set by the hardware to indicate that an endpoint/channel has successfully completed a transaction; using DIR and EP_ID bits software can determine which endpoint/channel requested the interrupt. This bit is read-only. - bit_offset: 15 - bit_size: 1 - - name: THR512 - description: "512 byte threshold interrupt This bit is set to 1 by the hardware when 512 bytes have been transmitted or received during isochronous transfers. This bit is read/write but only 0 can be written and writing 1 has no effect. Note that no information is available to indicate the associated channel/endpoint, however in practice only one ISO endpoint/channel with such large packets can be supported, so that channel." - bit_offset: 16 - bit_size: 1 - - name: DCON_STAT - description: "Device connection status Host mode: This bit contains information about device connection status. It is set by hardware when a LS/FS device is attached to the host while it is reset when the device is disconnected." - bit_offset: 29 - bit_size: 1 - - name: LS_DCON - description: "Low Speed device connected Host mode: This bit is set by hardware when an LS device connection is detected. Device connection is signaled after LS J-state is sampled for 22 consecutive cycles of the USB clock (48 MHz) from the unconnected state." - bit_offset: 30 - bit_size: 1 + - name: EP_ID + description: 'Device Endpoint / Host channel identification number These bits are written by the hardware according to the host channel or device endpoint number, which generated the interrupt request. If several endpoint/channel transactions are pending, the hardware writes the identification number related to the endpoint/channel having the highest priority defined in the following way: Two levels are defined, in order of priority: Isochronous and double-buffered bulk channels/endpoints are considered first and then the others are examined. If more than one endpoint/channel from the same set is requesting an interrupt, the IDN bits in USB_ISTR register are assigned according to the lowest requesting register, CHEP0R having the highest priority followed by CHEP1R and so on. The application software can assign a register to each endpoint/channel according to this priority scheme, so as to order the concurring endpoint/channel requests in a suitable way. These bits are read only.' + bit_offset: 0 + bit_size: 4 + - name: DIR + description: Direction of transaction This bit is written by the hardware according to the direction of the successful transaction, which generated the interrupt request. If DIR bit=0, VTTX bit is set in the USB_EPnR register related to the interrupting endpoint. The interrupting transaction is of IN type (data transmitted by the USB peripheral to the host PC). If DIR bit=1, VTRX bit or both VTTX/VTRX are set in the USB_EPnR register related to the interrupting endpoint. The interrupting transaction is of OUT type (data received by the USB peripheral from the host PC) or two pending transactions are waiting to be processed. This information can be used by the application software to access the USB_EPnR bits related to the triggering transaction since it represents the direction having the interrupt pending. This bit is read-only. + bit_offset: 4 + bit_size: 1 + enum: DIR + - name: L1REQ + description: LPM L1 state request This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. This bit is read/write but only '0 can be written and writing '1 has no effect. + bit_offset: 7 + bit_size: 1 + - name: ESOF + description: Expected start of frame This bit is set by the hardware when an SOF packet is expected but not received. The host sends an SOF packet each 1 ms, but if the device does not receive it properly, the Suspend Timer issues this interrupt. If three consecutive ESOF interrupts are generated (i.e. three SOF packets are lost) without any traffic occurring in between, a SUSP interrupt is generated. This bit is set even when the missing SOF packets occur while the Suspend Timer is not yet locked. This bit is read/write but only '0 can be written and writing '1 has no effect. + bit_offset: 8 + bit_size: 1 + - name: SOF + description: Start of frame This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus. The interrupt service routine may monitor the SOF events to have a 1 ms synchronization event to the USB host and to safely read the USB_FNR register which is updated at the SOF packet reception (this could be useful for isochronous applications). This bit is read/write but only '0 can be written and writing '1 has no effect. + bit_offset: 9 + bit_size: 1 + - name: RESET + description: reset request Device mode This bit is set by hardware when an USB reset is released by the host and the bus returns to idle. USB reset state is internally detected after the sampling of 60 consecutive SE0 cycles. Host mode This bit is set by hardware when device connection or device disconnection is detected. Device connection is signaled after J state is sampled for 22cycles consecutively from unconnected state. Device disconnection is signaled after SE0 state is sampled for 22cycles consecutively from connected state. + bit_offset: 10 + bit_size: 1 + - name: SUSP + description: Suspend mode request This bit is set by the hardware when no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus. The suspend condition check is enabled immediately after any USB reset and it is disabled by the hardware when the suspend mode is active (SUSPEN=1) until the end of resume sequence. This bit is read/write but only '0 can be written and writing '1 has no effect. + bit_offset: 11 + bit_size: 1 + - name: WKUP + description: Wakeup This bit is set to 1 by the hardware when, during suspend mode, activity is detected that wakes up the USB peripheral. This event asynchronously clears the LP_MODE bit in the CTLR register and activates the USB_WAKEUP line, which can be used to notify the rest of the device (e.g. wakeup unit) about the start of the resume process. This bit is read/write but only '0 can be written and writing '1 has no effect. + bit_offset: 12 + bit_size: 1 + - name: ERR + description: "Error This flag is set whenever one of the errors listed below has occurred: NANS:\tNo ANSwer. The timeout for a host response has expired. CRC:\tCyclic Redundancy Check error. One of the received CRCs, either in the token or in the data, was wrong. BST:\tBit Stuffing error. A bit stuffing error was detected anywhere in the PID, data, and/or CRC. FVIO:\tFraming format Violation. A non-standard frame was received (EOP not in the right place, wrong token sequence, etc.). The USB software can usually ignore errors, since the USB peripheral and the PC host manage retransmission in case of errors in a fully transparent way. This interrupt can be useful during the software development phase, or to monitor the quality of transmission over the USB bus, to flag possible problems to the user (e.g. loose connector, too noisy environment, broken conductor in the USB cable and so on). This bit is read/write but only '0 can be written and writing '1 has no effect." + bit_offset: 13 + bit_size: 1 + - name: PMAOVR + description: 'Packet memory area over / underrun This bit is set if the microcontroller has not been able to respond in time to an USB memory request. The USB peripheral handles this event in the following way: During reception an ACK handshake packet is not sent, during transmission a bit-stuff error is forced on the transmitted stream; in both cases the host will retry the transaction. The PMAOVR interrupt should never occur during normal operations. Since the failed transaction is retried by the host, the application software has the chance to speed-up device operations during this interrupt handling, to be ready for the next transaction retry; however this does not happen during Isochronous transfers (no isochronous transaction is anyway retried) leading to a loss of data in this case. This bit is read/write but only ''0 can be written and writing ''1 has no effect.' + bit_offset: 14 + bit_size: 1 + - name: CTR + description: Correct transfer This bit is set by the hardware to indicate that an endpoint/channel has successfully completed a transaction; using DIR and EP_ID bits software can determine which endpoint/channel requested the interrupt. This bit is read-only. + bit_offset: 15 + bit_size: 1 + - name: THR512 + description: 512 byte threshold interrupt This bit is set to 1 by the hardware when 512 bytes have been transmitted or received during isochronous transfers. This bit is read/write but only 0 can be written and writing 1 has no effect. Note that no information is available to indicate the associated channel/endpoint, however in practice only one ISO endpoint/channel with such large packets can be supported, so that channel. + bit_offset: 16 + bit_size: 1 + - name: DCON_STAT + description: 'Device connection status Host mode: This bit contains information about device connection status. It is set by hardware when a LS/FS device is attached to the host while it is reset when the device is disconnected.' + bit_offset: 29 + bit_size: 1 + - name: LS_DCON + description: 'Low Speed device connected Host mode: This bit is set by hardware when an LS device connection is detected. Device connection is signaled after LS J-state is sampled for 22 consecutive cycles of the USB clock (48 MHz) from the unconnected state.' + bit_offset: 30 + bit_size: 1 fieldset/LPMCSR: description: LPM control and status register fields: - - name: LPMEN - description: "LPM support enable Device mode This bit is set by the software to enable the LPM support within the USB device. If this bit is at '0 no LPM transactions are handled. Host mode Software sets this bit to transmit an LPM transaction to device. This bit is cleared by hardware, simultaneous with L1REQ flag set, when device answer is received" - bit_offset: 0 - bit_size: 1 - - name: LPMACK - description: "LPM Token acknowledge enable The NYET/ACK will be returned only on a successful LPM transaction: No errors in both the EXT token and the LPM token (else ERROR) A valid bLinkState = 0001B (L1) is received (else STALL) This bit contains the device answer to the LPM transaction. It mast be evaluated following the L1REQ interrupt." - bit_offset: 1 - bit_size: 1 - enum: LPMACK - - name: REMWAKE - description: bRemoteWake value Device mode This bit contains the bRemoteWake value received with last ACKed LPM Token Host mode This bit contains the bRemoteWake value transmitted with the LPM transaction - bit_offset: 3 - bit_size: 1 - - name: BESL - description: BESL value Device mode These bits contain the BESL value received with last ACKed LPM Token Host mode These bits contain the BESL value transmitted with the LPM transaction - bit_offset: 4 - bit_size: 4 + - name: LPMEN + description: LPM support enable Device mode This bit is set by the software to enable the LPM support within the USB device. If this bit is at '0 no LPM transactions are handled. Host mode Software sets this bit to transmit an LPM transaction to device. This bit is cleared by hardware, simultaneous with L1REQ flag set, when device answer is received + bit_offset: 0 + bit_size: 1 + - name: LPMACK + description: 'LPM Token acknowledge enable The NYET/ACK will be returned only on a successful LPM transaction: No errors in both the EXT token and the LPM token (else ERROR) A valid bLinkState = 0001B (L1) is received (else STALL) This bit contains the device answer to the LPM transaction. It mast be evaluated following the L1REQ interrupt.' + bit_offset: 1 + bit_size: 1 + enum: LPMACK + - name: REMWAKE + description: bRemoteWake value Device mode This bit contains the bRemoteWake value received with last ACKed LPM Token Host mode This bit contains the bRemoteWake value transmitted with the LPM transaction + bit_offset: 3 + bit_size: 1 + - name: BESL + description: BESL value Device mode These bits contain the BESL value received with last ACKed LPM Token Host mode These bits contain the BESL value transmitted with the LPM transaction + bit_offset: 4 + bit_size: 4 enum/DIR: bit_size: 1 variants: - - name: To - description: data transmitted by the USB peripheral to the host PC - value: 0 - - name: From - description: data received by the USB peripheral from the host PC - value: 1 + - name: To + description: data transmitted by the USB peripheral to the host PC + value: 0 + - name: From + description: data received by the USB peripheral from the host PC + value: 1 enum/EP_TYPE: bit_size: 2 variants: - - name: Bulk - description: Bulk endpoint - value: 0 - - name: Control - description: Control endpoint - value: 1 - - name: Iso - description: Iso endpoint - value: 2 - - name: Interrupt - description: Interrupt endpoint - value: 3 + - name: Bulk + description: Bulk endpoint + value: 0 + - name: Control + description: Control endpoint + value: 1 + - name: Iso + description: Iso endpoint + value: 2 + - name: Interrupt + description: Interrupt endpoint + value: 3 enum/LPMACK: bit_size: 1 variants: - - name: Nyet - description: The valid LPM Token will be NYET / NYET answer - value: 0 - - name: Ack - description: The valid LPM Token will be ACK / ACK answer - value: 1 + - name: Nyet + description: The valid LPM Token will be NYET / NYET answer + value: 0 + - name: Ack + description: The valid LPM Token will be ACK / ACK answer + value: 1 enum/SDET: bit_size: 1 variants: - - name: CDP - description: CDP detected - value: 0 - - name: DCP - description: DCP detected - value: 1 + - name: CDP + description: CDP detected + value: 0 + - name: DCP + description: DCP detected + value: 1 enum/STAT: bit_size: 2 variants: - - name: Disabled - description: all requests addressed to this endpoint are ignored - value: 0 - - name: Stall - description: the endpoint is stalled and all requests result in a STALL handshake - value: 1 - - name: Nak - description: the endpoint is naked and all requests result in a NAK handshake - value: 2 - - name: Valid - description: "this endpoint is enabled, requests are ACKed" - value: 3 + - name: Disabled + description: all requests addressed to this endpoint are ignored + value: 0 + - name: Stall + description: the endpoint is stalled and all requests result in a STALL handshake + value: 1 + - name: Nak + description: the endpoint is naked and all requests result in a NAK handshake + value: 2 + - name: Valid + description: this endpoint is enabled, requests are ACKed + value: 3 diff --git a/data/registers/usbram_16x1_512.yaml b/data/registers/usbram_16x1_512.yaml index 335220b..af0b98b 100644 --- a/data/registers/usbram_16x1_512.yaml +++ b/data/registers/usbram_16x1_512.yaml @@ -1,11 +1,10 @@ ---- block/USBRAM: description: USB Endpoint memory items: - - name: MEM - description: USB Endpoint memory - array: - len: 256 - stride: 4 - byte_offset: 0 - bit_size: 16 + - name: MEM + description: USB Endpoint memory + array: + len: 256 + stride: 4 + byte_offset: 0 + bit_size: 16 diff --git a/data/registers/usbram_16x2_1024.yaml b/data/registers/usbram_16x2_1024.yaml index 9941e63..4b9df7b 100644 --- a/data/registers/usbram_16x2_1024.yaml +++ b/data/registers/usbram_16x2_1024.yaml @@ -1,11 +1,10 @@ ---- block/USBRAM: description: USB Endpoint memory items: - - name: MEM - description: USB Endpoint memory - array: - len: 512 - stride: 2 - byte_offset: 0 - bit_size: 16 + - name: MEM + description: USB Endpoint memory + array: + len: 512 + stride: 2 + byte_offset: 0 + bit_size: 16 diff --git a/data/registers/usbram_16x2_512.yaml b/data/registers/usbram_16x2_512.yaml index 67051cd..b93c920 100644 --- a/data/registers/usbram_16x2_512.yaml +++ b/data/registers/usbram_16x2_512.yaml @@ -1,11 +1,10 @@ ---- block/USBRAM: description: USB Endpoint memory items: - - name: MEM - description: USB Endpoint memory - array: - len: 256 - stride: 2 - byte_offset: 0 - bit_size: 16 + - name: MEM + description: USB Endpoint memory + array: + len: 256 + stride: 2 + byte_offset: 0 + bit_size: 16 diff --git a/data/registers/usbram_32_2048.yaml b/data/registers/usbram_32_2048.yaml index 7d5a384..c5a9f10 100644 --- a/data/registers/usbram_32_2048.yaml +++ b/data/registers/usbram_32_2048.yaml @@ -1,10 +1,9 @@ ---- block/USBRAM: description: USB Endpoint memory items: - - name: MEM - description: USB Endpoint memory - array: - len: 512 - stride: 4 - byte_offset: 0 + - name: MEM + description: USB Endpoint memory + array: + len: 512 + stride: 4 + byte_offset: 0 diff --git a/data/registers/vrefintcal_v1.yaml b/data/registers/vrefintcal_v1.yaml index 3b27b74..a40c0dd 100644 --- a/data/registers/vrefintcal_v1.yaml +++ b/data/registers/vrefintcal_v1.yaml @@ -1,16 +1,15 @@ ---- block/VREFINTCAL: description: VREFINT Factory Calibration items: - - name: DATA - description: Factory calibration - byte_offset: 0 - access: Read - fieldset: DATA + - name: DATA + description: Factory calibration + byte_offset: 0 + access: Read + fieldset: DATA fieldset/DATA: description: Factory calibration data fields: - - name: VALUE - description: Calibration value - bit_offset: 0 - bit_size: 16 + - name: VALUE + description: Calibration value + bit_offset: 0 + bit_size: 16 diff --git a/data/registers/wwdg_v1.yaml b/data/registers/wwdg_v1.yaml index b1d77c2..e776979 100644 --- a/data/registers/wwdg_v1.yaml +++ b/data/registers/wwdg_v1.yaml @@ -1,75 +1,74 @@ ---- block/WWDG: description: Window watchdog items: - - name: CR - description: Control register - byte_offset: 0 - fieldset: CR - - name: CFR - description: Configuration register - byte_offset: 4 - fieldset: CFR - - name: SR - description: Status register - byte_offset: 8 - fieldset: SR + - name: CR + description: Control register + byte_offset: 0 + fieldset: CR + - name: CFR + description: Configuration register + byte_offset: 4 + fieldset: CFR + - name: SR + description: Status register + byte_offset: 8 + fieldset: SR fieldset/CFR: description: Configuration register fields: - - name: W - description: 7-bit window value - bit_offset: 0 - bit_size: 7 - - name: WDGTB - description: Timer base - bit_offset: 7 - bit_size: 2 - enum: WDGTB - - name: EWI - description: Early wakeup interrupt - bit_offset: 9 - bit_size: 1 + - name: W + description: 7-bit window value + bit_offset: 0 + bit_size: 7 + - name: WDGTB + description: Timer base + bit_offset: 7 + bit_size: 2 + enum: WDGTB + - name: EWI + description: Early wakeup interrupt + bit_offset: 9 + bit_size: 1 fieldset/CR: description: Control register fields: - - name: T - description: 7-bit counter (MSB to LSB) - bit_offset: 0 - bit_size: 7 - - name: WDGA - description: Activation bit - bit_offset: 7 - bit_size: 1 - enum: WDGA + - name: T + description: 7-bit counter (MSB to LSB) + bit_offset: 0 + bit_size: 7 + - name: WDGA + description: Activation bit + bit_offset: 7 + bit_size: 1 + enum: WDGA fieldset/SR: description: Status register fields: - - name: EWIF - description: Early wakeup interrupt flag - bit_offset: 0 - bit_size: 1 + - name: EWIF + description: Early wakeup interrupt flag + bit_offset: 0 + bit_size: 1 enum/WDGA: bit_size: 1 variants: - - name: Disabled - description: Watchdog disabled - value: 0 - - name: Enabled - description: Watchdog enabled - value: 1 + - name: Disabled + description: Watchdog disabled + value: 0 + - name: Enabled + description: Watchdog enabled + value: 1 enum/WDGTB: bit_size: 2 variants: - - name: Div1 - description: Counter clock (PCLK1 div 4096) div 1 - value: 0 - - name: Div2 - description: Counter clock (PCLK1 div 4096) div 2 - value: 1 - - name: Div4 - description: Counter clock (PCLK1 div 4096) div 4 - value: 2 - - name: Div8 - description: Counter clock (PCLK1 div 4096) div 8 - value: 3 + - name: Div1 + description: Counter clock (PCLK1 div 4096) div 1 + value: 0 + - name: Div2 + description: Counter clock (PCLK1 div 4096) div 2 + value: 1 + - name: Div4 + description: Counter clock (PCLK1 div 4096) div 4 + value: 2 + - name: Div8 + description: Counter clock (PCLK1 div 4096) div 8 + value: 3 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index b40ee33..2a72e85 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -142,9 +142,21 @@ impl PeriMatcher { ("STM32H7.*:RNG:.*", ("rng", "v1", "RNG")), ("STM32G0.*:RNG:.*", ("rng", "v1", "RNG")), ("STM32G4.*:RNG:.*", ("rng", "v1", "RNG")), + ("STM32F7.*:AES:.*", ("aes", "f7", "AES")), + ("STM32F4.*:AES:.*", ("aes", "v1", "AES")), + ("STM32G0.*:AES:.*", ("aes", "v2", "AES")), + ("STM32G4.*:AES:.*", ("aes", "v2", "AES")), + ("STM32L0.*:AES:.*", ("aes", "v1", "AES")), + ("STM32L1.*:AES:.*", ("aes", "v1", "AES")), + ("STM32L4.*:AES:.*", ("aes", "v1", "AES")), + ("STM32L5.*:AES:.*", ("aes", "v2", "AES")), + ("STM32U5.*:AES:.*", ("aes", "u5", "AES")), + ("STM32WL5.*:AES:.*", ("aes", "v2", "AES")), + ("STM32WLE.*:AES:.*", ("aes", "v2", "AES")), (".*:SPI:spi2_v1_4", ("spi", "f1", "SPI")), (".*:SPI:spi2s1_v2_1", ("spi", "v1", "SPI")), (".*:SPI:spi2s1_v2_2", ("spi", "v1", "SPI")), + (".*:SPI:spi2s1_v2_3", ("spi", "v1", "SPI")), (".*:SPI:spi2s1_v2_4", ("spi", "v1", "SPI")), (".*:SPI:spi2s1_v3_0", ("spi", "v2", "SPI")), (".*:SPI:spi2s1_v3_2", ("spi", "v2", "SPI")), @@ -170,6 +182,7 @@ impl PeriMatcher { (".*:DAC:F3_dacif_v1_1", ("dac", "v1", "DAC")), (".*:ADC:aditf_v2_5F1", ("adc", "f1", "ADC")), (".*:ADC:aditf5_v1_1", ("adc", "f3", "ADC")), + (".*:ADC:aditf_v2_5", ("adc", "f3_v2", "ADC")), (".*:ADC:aditf4_v1_1", ("adc", "v1", "ADC")), (".*:ADC:aditf2_v1_1", ("adc", "v2", "ADC")), (".*:ADC:aditf5_v2_0", ("adc", "v3", "ADC")), @@ -178,10 +191,14 @@ impl PeriMatcher { (".*:ADC:aditf5_v3_1", ("adc", "v4", "ADC")), ("STM32G0.*:ADC:.*", ("adc", "g0", "ADC")), ("STM32G0.*:ADC_COMMON:.*", ("adccommon", "v3", "ADC_COMMON")), + ("STM32G4.*:ADC:.*", ("adc", "v4", "ADC")), + ("STM32G4.*:ADC_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")), (".*:ADC_COMMON:aditf2_v1_1", ("adccommon", "v2", "ADC_COMMON")), (".*:ADC_COMMON:aditf5_v2_0", ("adccommon", "v3", "ADC_COMMON")), (".*:ADC_COMMON:aditf5_v2_2", ("adccommon", "v3", "ADC_COMMON")), (".*:ADC_COMMON:aditf4_v3_0_WL", ("adccommon", "v3", "ADC_COMMON")), + (".*:ADC_COMMON:aditf5_v1_1", ("adccommon", "f3", "ADC_COMMON")), + (".*:ADC3_COMMON:aditf5_v1_1", ("adccommon", "f3", "ADC_COMMON")), ("STM32H7.*:ADC_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")), ("STM32H7.*:ADC3_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")), (".*:DCMI:.*", ("dcmi", "v1", "DCMI")), @@ -197,11 +214,18 @@ impl PeriMatcher { ("STM32L5.*:SYSCFG:.*", ("syscfg", "l5", "SYSCFG")), ("STM32G0.*:SYSCFG:.*", ("syscfg", "g0", "SYSCFG")), ("STM32G4.*:SYSCFG:.*", ("syscfg", "g4", "SYSCFG")), + ( + "STM32H7(45|47|55|57|42|43|53|50).*:SYSCFG:.*", + ("syscfg", "h7od", "SYSCFG"), + ), ("STM32H7.*:SYSCFG:.*", ("syscfg", "h7", "SYSCFG")), ("STM32U5.*:SYSCFG:.*", ("syscfg", "u5", "SYSCFG")), + ("STM32WBA.*:SYSCFG:.*", ("syscfg", "wba", "SYSCFG")), ("STM32WB.*:SYSCFG:.*", ("syscfg", "wb", "SYSCFG")), ("STM32WL5.*:SYSCFG:.*", ("syscfg", "wl5", "SYSCFG")), + ("STM32WL5.*:ADC:.*", ("adc", "g0", "ADC")), ("STM32WLE.*:SYSCFG:.*", ("syscfg", "wle", "SYSCFG")), + ("STM32WLE.*:ADC:.*", ("adc", "g0", "ADC")), ("STM32H50.*:SBS:.*", ("sbs", "h50", "SBS")), ("STM32H5.*:SBS:.*", ("sbs", "h5", "SBS")), (".*:IWDG:iwdg1_v1_1", ("iwdg", "v1", "IWDG")), @@ -226,6 +250,7 @@ impl PeriMatcher { ("STM32L0.*:RTC:rtc2_.*", ("rtc", "v2l0", "RTC")), ("STM32L1.*:RTC:rtc2_.*", ("rtc", "v2l1", "RTC")), ("STM32L4.*:RTC:rtc2_.*", ("rtc", "v2l4", "RTC")), + ("STM32WBA.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")), ("STM32WB.*:RTC:rtc2_.*", ("rtc", "v2wb", "RTC")), ("STM32U5.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")), // Cube says v2, but it's v3 with security stuff (".*:RTC:rtc3_v1_0", ("rtc", "v3", "RTC")), @@ -262,6 +287,7 @@ impl PeriMatcher { ("STM32F10[123].*:RCC:.*", ("rcc", "f1", "RCC")), ("STM32F10[57].*:RCC:.*", ("rcc", "f1cl", "RCC")), ("STM32F2.*:RCC:.*", ("rcc", "f2", "RCC")), + ("STM32F37.*:RCC:.*", ("rcc", "f3_v2", "RCC")), ("STM32F3.*:RCC:.*", ("rcc", "f3", "RCC")), ("STM32F410.*:RCC:.*", ("rcc", "f410", "RCC")), ("STM32F4.*:RCC:.*", ("rcc", "f4", "RCC")), @@ -277,12 +303,14 @@ impl PeriMatcher { ("STM32U5.*:RCC:.*", ("rcc", "u5", "RCC")), ("STM32H50.*:RCC:.*", ("rcc", "h50", "RCC")), ("STM32H5.*:RCC:.*", ("rcc", "h5", "RCC")), + ("STM32WBA.*:RCC:.*", ("rcc", "wba", "RCC")), ("STM32WB.*:RCC:.*", ("rcc", "wb", "RCC")), ("STM32WL5.*:RCC:.*", ("rcc", "wl5", "RCC")), ("STM32WLE.*:RCC:.*", ("rcc", "wle", "RCC")), ("STM32F1.*:SPI[1234]:.*", ("spi", "f1", "SPI")), ("STM32F3.*:SPI[1234]:.*", ("spi", "v2", "SPI")), ("STM32F1.*:AFIO:.*", ("afio", "f1", "AFIO")), + ("STM32WBA.*:EXTI:.*", ("exti", "l5", "EXTI")), ("STM32L5.*:EXTI:.*", ("exti", "l5", "EXTI")), ("STM32C0.*:EXTI:.*", ("exti", "c0", "EXTI")), ("STM32G0.*:EXTI:.*", ("exti", "g0", "EXTI")), @@ -300,23 +328,33 @@ impl PeriMatcher { ("STM32G4.*:CRS:.*", ("crs", "v1", "CRS")), ("STM32U5.*:CRS:.*", ("crs", "v1", "CRS")), (".*SDMMC:sdmmc2_v1_0", ("sdmmc", "v2", "SDMMC")), + (".*SDMMC:sdmmc2_v2_1", ("sdmmc", "v2", "SDMMC")), ("STM32C0.*:PWR:.*", ("pwr", "c0", "PWR")), ("STM32G0.*:PWR:.*", ("pwr", "g0", "PWR")), ("STM32G4.*:PWR:.*", ("pwr", "g4", "PWR")), - ("STM32H7(42|43|53|50).*:PWR:.*", ("pwr", "h7", "PWR")), - ("STM32H7.*:PWR:.*", ("pwr", "h7smps", "PWR")), + ("STM32H7(45|47|55|57).*:PWR:.*", ("pwr", "h7rm0399", "PWR")), + ("STM32H7(42|43|53|50).*:PWR:.*", ("pwr", "h7rm0433", "PWR")), + ("STM32H7(23|25|33|35|30).*:PWR:.*", ("pwr", "h7rm0468", "PWR")), + ("STM32H7(A3|B0|B3).*:PWR:.*", ("pwr", "h7rm0455", "PWR")), + ("STM32F0.0.*:PWR:.*", ("pwr", "f0x0", "PWR")), + ("STM32F0.*:PWR:.*", ("pwr", "f0", "PWR")), + ("STM32F1.*:PWR:.*", ("pwr", "f1", "PWR")), ("STM32F2.*:PWR:.*", ("pwr", "f2", "PWR")), ("STM32F3.*:PWR:.*", ("pwr", "f3", "PWR")), ("STM32F4.*:PWR:.*", ("pwr", "f4", "PWR")), ("STM32F7.*:PWR:.*", ("pwr", "f7", "PWR")), + ("STM32L0.*:PWR:.*", ("pwr", "l0", "PWR")), ("STM32L1.*:PWR:.*", ("pwr", "l1", "PWR")), ("STM32L4.*:PWR:.*", ("pwr", "l4", "PWR")), ("STM32L5.*:PWR:.*", ("pwr", "l5", "PWR")), ("STM32U5.*:PWR:.*", ("pwr", "u5", "PWR")), ("STM32WL.*:PWR:.*", ("pwr", "wl5", "PWR")), - ("STM32WB.*:PWR:.*", ("pwr", "wb55", "PWR")), + ("STM32WBA.*:PWR:.*", ("pwr", "wba", "PWR")), + ("STM32WB55.*:PWR:.*", ("pwr", "wb55", "PWR")), + ("STM32WB.*:PWR:.*", ("pwr", "wb", "PWR")), ("STM32H50.*:PWR:.*", ("pwr", "h50", "PWR")), ("STM32H5.*:PWR:.*", ("pwr", "h5", "PWR")), + ("STM32H7(A3|B3|B0).*:FLASH:.*", ("flash", "h7ab", "FLASH")), ("STM32H7.*:FLASH:.*", ("flash", "h7", "FLASH")), ("STM32F0.*:FLASH:.*", ("flash", "f0", "FLASH")), ("STM32F1.*:FLASH:.*", ("flash", "f1", "FLASH")), @@ -324,11 +362,12 @@ impl PeriMatcher { ("STM32F3.*:FLASH:.*", ("flash", "f3", "FLASH")), ("STM32F4.*:FLASH:.*", ("flash", "f4", "FLASH")), ("STM32F7.*:FLASH:.*", ("flash", "f7", "FLASH")), - ("STM32L0[0-9]2.*:FLASH:.*", ("flash", "l0", "FLASH")), + ("STM32L0.*:FLASH:.*", ("flash", "l0", "FLASH")), ("STM32L1.*:FLASH:.*", ("flash", "l1", "FLASH")), ("STM32L4.*:FLASH:.*", ("flash", "l4", "FLASH")), ("STM32L5.*:FLASH:.*", ("flash", "l5", "FLASH")), ("STM32U5.*:FLASH:.*", ("flash", "u5", "FLASH")), + ("STM32WBA.*:FLASH:.*", ("flash", "wba", "FLASH")), ("STM32WB.*:FLASH:.*", ("flash", "wb", "FLASH")), ("STM32WL.*:FLASH:.*", ("flash", "wl", "FLASH")), ("STM32C0.*:FLASH:.*", ("flash", "c0", "FLASH")), @@ -340,6 +379,7 @@ impl PeriMatcher { ("STM32F[24].*:ETH:.*", ("eth", "v1b", "ETH")), ("STM32F7.*:ETH:.*", ("eth", "v1c", "ETH")), (".*ETH:ethermac110_v3_0", ("eth", "v2", "ETH")), + (".*ETH:ethermac110_v3_0_1", ("eth", "v2", "ETH")), ("STM32F4[23][79].*:FMC:.*", ("fmc", "v1x3", "FMC")), ("STM32F446.*:FMC:.*", ("fmc", "v2x1", "FMC")), ("STM32F469.*:FMC:.*", ("fmc", "v2x1", "FMC")), @@ -384,6 +424,7 @@ impl PeriMatcher { ("STM32L1.*:DBGMCU:.*", ("dbgmcu", "l1", "DBGMCU")), ("STM32L4.*:DBGMCU:.*", ("dbgmcu", "l4", "DBGMCU")), ("STM32U5.*:DBGMCU:.*", ("dbgmcu", "u5", "DBGMCU")), + ("STM32WBA.*:DBGMCU:.*", ("dbgmcu", "wba", "DBGMCU")), ("STM32WB.*:DBGMCU:.*", ("dbgmcu", "wb", "DBGMCU")), ("STM32WL.*:DBGMCU:.*", ("dbgmcu", "wl", "DBGMCU")), ("STM32F1.*:GPIO.*", ("gpio", "v1", "GPIO")), @@ -416,6 +457,7 @@ impl PeriMatcher { (".*:LCD:lcdc1_v1.2.*", ("lcd", "v2", "LCD")), (".*:LCD:lcdc1_v1.3.*", ("lcd", "v2", "LCD")), (".*:UID:.*", ("uid", "v1", "UID")), + (".*:UCPD:.*", ("ucpd", "v1", "UCPD")), ]; Self { @@ -524,11 +566,11 @@ pub fn parse_groups() -> Result<(HashMap, Vec), anyhow: static NOPELIST: &[&str] = &[ // Not supported, not planned unless someone wants to do it. "STM32MP", - // Not supported yet, planned. - "STM32WBA", // Does not exist in ST website. No datasheet, no RM. "STM32GBK", "STM32L485", + "STM32U5F", + "STM32U5G", // STM32WxM modules. These are based on a chip that's supported on its own, // not sure why we want a separate target for it. "STM32WL5M", @@ -743,7 +785,7 @@ fn process_core( if ["L5", "U5"].contains(&&chip_name[5..7]) { want_nvic_name = "NVIC2" } - if ["H56", "H57"].contains(&&chip_name[5..8]) { + if ["H56", "H57", "WBA"].contains(&&chip_name[5..8]) { want_nvic_name = "NVIC2" } @@ -824,7 +866,7 @@ fn process_core( entry.insert(format!("ADC_COMMON:{}", ip.version.strip_suffix("_Cube").unwrap())); } } - if pname.starts_with("ADC3") && chip_name.starts_with("STM32H7") { + if pname.starts_with("ADC3") && (chip_name.starts_with("STM32H7") || chip_name.starts_with("STM32F3")) { if let Entry::Vacant(entry) = peri_kinds.entry("ADC3_COMMON".to_string()) { entry.insert(format!("ADC3_COMMON:{}", ip.version.strip_suffix("_Cube").unwrap())); } diff --git a/stm32-data-gen/src/dma.rs b/stm32-data-gen/src/dma.rs index 083eaf5..116edc7 100644 --- a/stm32-data-gen/src/dma.rs +++ b/stm32-data-gen/src/dma.rs @@ -298,6 +298,7 @@ impl DmaChannels { ("H5_GPDMA.yaml", "GPDMA1", "STM32H5_dma3_Cube", 8, 2), ("H5_GPDMA.yaml", "GPDMA2", "Instance2_STM32H5_dma3_Cube", 8, 2), ("U5_GPDMA1.yaml", "GPDMA1", "STM32U5_dma3_Cube", 16, 4), + ("WBA_GPDMA1.yaml", "GPDMA1", "STM32WBA_dma3_Cube", 8, 0), ] { let mut chip_dma = ChipDma { peripherals: HashMap::new(), diff --git a/stm32-data-gen/src/header.rs b/stm32-data-gen/src/header.rs index 1427d72..158be9a 100644 --- a/stm32-data-gen/src/header.rs +++ b/stm32-data-gen/src/header.rs @@ -165,6 +165,7 @@ impl Defines { "ADC_COMMON", &["ADC_COMMON", "ADC1_COMMON", "ADC12_COMMON", "ADC123_COMMON"], ), + ("ADC3_COMMON", &["ADC3_COMMON", "ADC4_COMMON", "ADC34_COMMON"]), ("CAN", &["CAN_BASE", "CAN1_BASE"]), ("FMC", &["FMC_BASE", "FMC_R_BASE"]), ("FSMC", &["FSMC_R_BASE"]), diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs index d4e17c6..7316c3d 100644 --- a/stm32-data-gen/src/rcc.rs +++ b/stm32-data-gen/src/rcc.rs @@ -26,6 +26,8 @@ impl PeripheralToClock { }; for field in &body.fields { if let Some(peri) = field.name.strip_suffix("EN") { + let peri = if peri == "RTCAPB" { "RTC" } else { peri }; + // Timers are a bit special, they may have a x2 freq let peri_clock = { if regex!(r"^TIM\d+$").is_match(peri) { @@ -79,6 +81,9 @@ impl PeripheralToClock { const PERI_OVERRIDE: &[(&str, &[&str])] = &[("DCMI", &["DCMI_PSSI"]), ("PSSI", &["DCMI_PSSI"])]; let clocks = self.0.get(rcc_block)?; + if peri_name.starts_with("ADC") && !peri_name.contains("COMMON") { + return self.match_adc_peri_clock(clocks, peri_name); + } if let Some(res) = clocks.get(peri_name) { Some(res) } else if let Some(peri_name) = peri_name.strip_suffix('1') { @@ -94,4 +99,42 @@ impl PeripheralToClock { None } } + + fn match_adc_peri_clock<'a>( + &'a self, + clocks: &'a HashMap, + peri_name: &str, + ) -> Option<&stm32_data_serde::chip::core::peripheral::Rcc> { + // Direct match + if clocks.contains_key(peri_name) { + return clocks.get(peri_name); + } + + // Paired match based on odd/even + if let Some(digit_char) = peri_name.chars().last() { + if let Some(digit) = digit_char.to_digit(10) { + let paired = if digit % 2 == 1 { + format!("ADC{}{}", digit, digit + 1) + } else { + format!("ADC{}{}", digit - 1, digit) + }; + + if clocks.contains_key(paired.as_str()) { + return clocks.get(paired.as_str()); + } + } + } + + // If adc is 3, 4, or 5, check for ADC345 + if (peri_name == "ADC3" || peri_name == "ADC4" || peri_name == "ADC5") && clocks.contains_key("ADC345") { + return clocks.get("ADC345"); + } + + // Look for bare ADC clock register + if clocks.contains_key("ADC") { + return clocks.get("ADC"); + } + + None + } } diff --git a/stm32-metapac-gen/res/Cargo.toml b/stm32-metapac-gen/res/Cargo.toml index c9aa767..67062de 100644 --- a/stm32-metapac-gen/res/Cargo.toml +++ b/stm32-metapac-gen/res/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "stm32-metapac" -version = "13.0.0" +version = "14.0.0" edition = "2021" license = "MIT OR Apache-2.0" repository = "https://github.com/embassy-rs/stm32-data" diff --git a/stm32-metapac-gen/res/build.rs b/stm32-metapac-gen/res/build.rs index 080375c..e1b88aa 100644 --- a/stm32-metapac-gen/res/build.rs +++ b/stm32-metapac-gen/res/build.rs @@ -13,6 +13,7 @@ fn main() { .to_ascii_lowercase() .replace('_', "-"); + #[cfg(feature = "rt")] println!( "cargo:rustc-link-search={}/src/chips/{}", crate_dir.display(),