384 lines
8.5 KiB
YAML
384 lines
8.5 KiB
YAML
block/ADC:
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description: Analog-to-digital converter
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items:
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- name: ISR
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description: interrupt and status register
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byte_offset: 0
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fieldset: ISR
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- name: IER
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description: interrupt enable register
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byte_offset: 4
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fieldset: IER
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- name: CR
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description: control register
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byte_offset: 8
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fieldset: CR
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- name: CFGR1
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description: configuration register 1
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byte_offset: 12
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fieldset: CFGR1
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- name: CFGR2
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description: configuration register 2
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byte_offset: 16
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fieldset: CFGR2
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- name: SMPR
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description: sampling time register
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byte_offset: 20
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fieldset: SMPR
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- name: TR
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description: watchdog threshold register
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byte_offset: 32
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fieldset: TR
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- name: CHSELR
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description: channel selection register
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byte_offset: 40
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fieldset: CHSELR
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- name: DR
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description: data register
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byte_offset: 64
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access: Read
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fieldset: DR
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- name: CCR
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description: common configuration register
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byte_offset: 776
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fieldset: CCR
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fieldset/CCR:
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description: common configuration register
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fields:
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- name: VREFEN
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description: Temperature sensor and VREFINT enable
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bit_offset: 22
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bit_size: 1
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- name: TSEN
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description: Temperature sensor enable
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bit_offset: 23
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bit_size: 1
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- name: VBATEN
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description: VBAT enable
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bit_offset: 24
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bit_size: 1
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fieldset/CFGR1:
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description: configuration register 1
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fields:
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- name: DMAEN
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description: Direct memory access enable
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bit_offset: 0
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bit_size: 1
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- name: DMACFG
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description: Direct memery access configuration
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bit_offset: 1
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bit_size: 1
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enum: DMACFG
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- name: SCANDIR
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description: Scan sequence direction
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bit_offset: 2
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bit_size: 1
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enum: SCANDIR
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- name: RES
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description: Data resolution
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bit_offset: 3
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bit_size: 2
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enum: RES
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- name: ALIGN
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description: Data alignment
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bit_offset: 5
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bit_size: 1
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enum: ALIGN
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- name: EXTSEL
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description: External trigger selection
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bit_offset: 6
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bit_size: 3
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enum: EXTSEL
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- name: EXTEN
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description: External trigger enable and polarity selection
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bit_offset: 10
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bit_size: 2
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enum: EXTEN
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- name: OVRMOD
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description: Overrun management mode
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bit_offset: 12
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bit_size: 1
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enum: OVRMOD
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- name: CONT
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description: Single / continuous conversion mode
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bit_offset: 13
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bit_size: 1
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- name: WAIT
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description: Wait conversion mode
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bit_offset: 14
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bit_size: 1
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- name: AUTOFF
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description: Auto-off mode
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bit_offset: 15
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bit_size: 1
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- name: DISCEN
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description: Discontinuous mode
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bit_offset: 16
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bit_size: 1
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- name: AWDSGL
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description: Enable the watchdog on a single channel or on all channels
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bit_offset: 22
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bit_size: 1
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enum: AWDSGL
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- name: AWDEN
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description: Analog watchdog enable
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bit_offset: 23
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bit_size: 1
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- name: AWDCH
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description: Analog watchdog channel selection
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bit_offset: 26
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bit_size: 5
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fieldset/CFGR2:
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description: configuration register 2
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fields:
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- name: CKMODE
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description: ADC clock mode
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bit_offset: 30
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bit_size: 2
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enum: CKMODE
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fieldset/CHSELR:
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description: channel selection register
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fields:
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- name: CHSEL x
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description: Channel-x selection
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bit_offset: 0
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bit_size: 1
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array:
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len: 19
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stride: 1
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fieldset/CR:
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description: control register
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fields:
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- name: ADEN
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description: ADC enable command
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bit_offset: 0
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bit_size: 1
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- name: ADDIS
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description: ADC disable command
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bit_offset: 1
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bit_size: 1
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- name: ADSTART
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description: ADC start conversion command
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bit_offset: 2
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bit_size: 1
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- name: ADSTP
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description: ADC stop conversion command
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bit_offset: 4
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bit_size: 1
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- name: ADCAL
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description: ADC calibration
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bit_offset: 31
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bit_size: 1
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fieldset/DR:
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description: data register
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fields:
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- name: DATA
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description: Converted data
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bit_offset: 0
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bit_size: 16
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fieldset/IER:
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description: interrupt enable register
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fields:
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- name: ADRDYIE
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description: ADC ready interrupt enable
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bit_offset: 0
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bit_size: 1
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- name: EOSMPIE
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description: End of sampling flag interrupt enable
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bit_offset: 1
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bit_size: 1
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- name: EOCIE
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description: End of conversion interrupt enable
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bit_offset: 2
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bit_size: 1
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- name: EOSEQIE
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description: End of conversion sequence interrupt enable
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bit_offset: 3
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bit_size: 1
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- name: OVRIE
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description: Overrun interrupt enable
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bit_offset: 4
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bit_size: 1
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- name: AWDIE
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description: Analog watchdog interrupt enable
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bit_offset: 7
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bit_size: 1
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fieldset/ISR:
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description: interrupt and status register
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fields:
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- name: ADRDY
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description: ADC ready
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bit_offset: 0
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bit_size: 1
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- name: EOSMP
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description: End of sampling flag
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bit_offset: 1
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bit_size: 1
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- name: EOC
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description: End of conversion flag
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bit_offset: 2
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bit_size: 1
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- name: EOSEQ
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description: End of sequence flag
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bit_offset: 3
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bit_size: 1
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- name: OVR
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description: ADC overrun
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bit_offset: 4
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bit_size: 1
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- name: AWD
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description: Analog watchdog flag
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bit_offset: 7
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bit_size: 1
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fieldset/SMPR:
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description: sampling time register
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fields:
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- name: SMP
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description: Sampling time selection
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bit_offset: 0
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bit_size: 3
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enum: SAMPLE_TIME
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fieldset/TR:
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description: watchdog threshold register
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fields:
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- name: LT
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description: Analog watchdog lower threshold
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bit_offset: 0
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bit_size: 12
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- name: HT
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description: Analog watchdog higher threshold
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bit_offset: 16
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bit_size: 12
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enum/ALIGN:
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bit_size: 1
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variants:
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- name: Right
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description: Right alignment
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value: 0
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- name: Left
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description: Left alignment
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value: 1
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enum/AWDSGL:
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bit_size: 1
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variants:
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- name: AllChannels
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description: Analog watchdog enabled on all channels
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value: 0
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- name: SingleChannel
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description: Analog watchdog enabled on a single channel
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value: 1
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enum/CKMODE:
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bit_size: 2
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variants:
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- name: ADCCLK
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description: Asynchronous clock mode
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value: 0
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- name: PCLK_Div2
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description: Synchronous clock mode (PCLK/2)
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value: 1
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- name: PCLK_Div4
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description: Sychronous clock mode (PCLK/4)
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value: 2
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enum/DMACFG:
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bit_size: 1
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variants:
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- name: OneShot
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description: DMA one shot mode
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value: 0
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- name: Circular
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description: DMA circular mode
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value: 1
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enum/EXTEN:
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bit_size: 2
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variants:
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- name: Disabled
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description: Trigger detection disabled
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value: 0
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- name: RisingEdge
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description: Trigger detection on the rising edge
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value: 1
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- name: FallingEdge
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description: Trigger detection on the falling edge
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value: 2
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- name: BothEdges
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description: Trigger detection on both the rising and falling edges
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value: 3
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enum/EXTSEL:
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bit_size: 3
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variants:
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- name: TIM1_TRGO
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description: Timer 1 TRGO Event
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value: 0
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- name: TIM1_CC4
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description: Timer 1 CC4 event
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value: 1
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- name: TIM2_TRGO
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description: Timer 2 TRGO event
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value: 2
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- name: TIM3_TRGO
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description: Timer 3 TRGO event
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value: 3
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- name: TIM15_TRGO
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description: Timer 15 TRGO event
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value: 4
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enum/OVRMOD:
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bit_size: 1
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variants:
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- name: Preserved
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description: ADC_DR register is preserved with the old data when an overrun is detected
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value: 0
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- name: Overwritten
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description: ADC_DR register is overwritten with the last conversion result when an overrun is detected
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value: 1
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enum/RES:
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bit_size: 2
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variants:
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- name: TwelveBit
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description: 12-bit (14 ADCCLK cycles)
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value: 0
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- name: TenBit
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description: 10-bit (13 ADCCLK cycles)
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value: 1
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- name: EightBit
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description: 8-bit (11 ADCCLK cycles)
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value: 2
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- name: SixBit
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description: 6-bit (9 ADCCLK cycles)
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value: 3
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enum/SAMPLE_TIME:
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bit_size: 3
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variants:
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- name: Cycles1_5
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description: 1.5 cycles
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value: 0
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- name: Cycles7_5
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description: 7.5 cycles
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value: 1
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- name: Cycles13_5
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description: 13.5 cycles
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value: 2
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- name: Cycles28_5
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description: 28.5 cycles
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value: 3
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- name: Cycles41_5
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description: 41.5 cycles
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value: 4
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- name: Cycles55_5
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description: 55.5 cycles
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value: 5
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- name: Cycles71_5
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description: 71.5 cycles
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value: 6
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- name: Cycles239_5
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description: 239.5 cycles
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value: 7
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enum/SCANDIR:
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bit_size: 1
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variants:
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- name: Upward
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description: Upward scan (from CHSEL0 to CHSEL18)
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value: 0
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- name: Backward
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description: Backward scan (from CHSEL18 to CHSEL0)
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value: 1
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