Merge branch 'master' into lptim-basic
This commit is contained in:
xoviat
commit
1b39301d8c
33
.github/ci/build.sh
vendored
33
.github/ci/build.sh
vendored
@ -2,7 +2,7 @@
|
||||
## on push branch~=gh-readonly-queue/main/.*
|
||||
## on pull_request
|
||||
|
||||
set -euo pipefail
|
||||
set -euxo pipefail
|
||||
|
||||
export RUSTUP_HOME=/ci/cache/rustup
|
||||
export CARGO_HOME=/ci/cache/cargo
|
||||
@ -13,4 +13,35 @@ hashtime save /ci/cache/filetime.json
|
||||
|
||||
cargo fmt -- --check
|
||||
|
||||
# clone stm32-data-generated at the merge base
|
||||
# so the diff will show this PR's effect
|
||||
git remote add upstream https://github.com/embassy-rs/stm32-data
|
||||
git fetch --depth 1 upstream main
|
||||
git clone --depth 1 --branch stm32-data-$(git merge-base HEAD upstream/main) https://github.com/embassy-rs/stm32-data-generated/ build
|
||||
|
||||
./d ci
|
||||
|
||||
# upload diff
|
||||
(
|
||||
cd build
|
||||
git add .
|
||||
git diff --staged --color data | aha --black > /ci/artifacts/diff.html
|
||||
)
|
||||
|
||||
# upload generated data to a fake git repo at
|
||||
# https://ci.embassy.dev/jobs/$ID/artifacts/generated.git
|
||||
# this allows testing the corresponding embassy-stm32 PR before merging the stm32-data one.
|
||||
(
|
||||
cd build
|
||||
rm -rf .git
|
||||
git init
|
||||
git add .
|
||||
git commit -m 'generated'
|
||||
git gc # makes cloning faster
|
||||
git update-server-info # generate .git/info/refs
|
||||
mv .git /ci/artifacts/generated.git
|
||||
)
|
||||
|
||||
cat > /ci/comment.md <<EOF
|
||||
diff: https://ci.embassy.dev/jobs/$(jq -r .id < /ci/job.json)/artifacts/diff.html
|
||||
EOF
|
||||
|
||||
2
.github/ci/generated.sh
vendored
2
.github/ci/generated.sh
vendored
@ -12,7 +12,7 @@ export CARGO_TARGET_DIR=/ci/cache/target
|
||||
hashtime restore /ci/cache/filetime.json || true
|
||||
hashtime save /ci/cache/filetime.json
|
||||
|
||||
git clone https://github.com/embassy-rs/stm32-data-generated/ build
|
||||
git clone --depth 1 https://github.com/embassy-rs/stm32-data-generated/ build
|
||||
./d ci
|
||||
|
||||
COMMIT=$(git rev-parse HEAD)
|
||||
|
||||
@ -97,7 +97,7 @@ are only interested in one. It's easier than it looks, and doing all families at
|
||||
- Cleanup the register yamls (see below).
|
||||
- Minimize the diff between each pair of versions. For example between `lpuart_v1.yaml` and `lpuart_v2.yaml`. If one is missing enums or descriptions, copy it from another.
|
||||
- Make sure the block
|
||||
- Add entries to [`perimap`](https://github.com/embassy-rs/stm32-data/blob/main/stm32data/__main__.py#L84), see below.
|
||||
- Add entries to [`perimap`](https://github.com/embassy-rs/stm32-data/blob/main/stm32-data-gen/src/chips.rs#L109), see below.
|
||||
- Regen, check `data/chips/*.yaml` has the right `block: lpuart_vX/LPUART` fields
|
||||
|
||||
Please separate manual changes and changes resulting from regen in separate commits. It helps tremendously with review and rebasing/merging.
|
||||
|
||||
2
d
2
d
@ -11,7 +11,7 @@ case "$CMD" in
|
||||
rm -rf ./sources/
|
||||
git clone https://github.com/embassy-rs/stm32-data-sources.git ./sources/
|
||||
cd ./sources/
|
||||
git checkout ca89656b
|
||||
git checkout a2062c088cf299bd3dc5128eeaa96e07fff2087c
|
||||
;;
|
||||
install-chiptool)
|
||||
cargo install --git https://github.com/embassy-rs/chiptool
|
||||
|
||||
2
d.ps1
2
d.ps1
@ -12,7 +12,7 @@ Switch ($CMD)
|
||||
rm -r -Force ./sources/ -ErrorAction SilentlyContinue
|
||||
git clone https://github.com/embassy-rs/stm32-data-sources.git ./sources/
|
||||
cd ./sources/
|
||||
git checkout ca89656b
|
||||
git checkout a2062c088cf299bd3dc5128eeaa96e07fff2087c
|
||||
cd ..
|
||||
}
|
||||
"install-chiptool" {
|
||||
|
||||
50
data/dmamux/WBA_GPDMA1.yaml
Normal file
50
data/dmamux/WBA_GPDMA1.yaml
Normal file
@ -0,0 +1,50 @@
|
||||
ADC4: 0
|
||||
SPI1_RX: 1
|
||||
SPI1_TX: 2
|
||||
SPI3_RX: 3
|
||||
SPI3_TX: 4
|
||||
I2C1_RX: 5
|
||||
I2C1_TX: 6
|
||||
I2C1_EVC: 7
|
||||
I2C3_RX: 8
|
||||
I2C3_TX: 9
|
||||
I2C3_EVC: 10
|
||||
USART1_RX: 11
|
||||
USART1_TX: 12
|
||||
USART2_RX: 13
|
||||
USART2_TX: 14
|
||||
LPUART1_RX: 15
|
||||
LPUART1_TX: 16
|
||||
TIM1_CC1: 19
|
||||
TIM1_CC2: 20
|
||||
TIM1_CC3: 21
|
||||
TIM1_CC4: 22
|
||||
TIM1_UPD: 23
|
||||
TIM1_TRG: 24
|
||||
TIM1_COM: 25
|
||||
TIM2_CC1: 26
|
||||
TIM2_CC2: 27
|
||||
TIM2_CC3: 28
|
||||
TIM2_CC4: 29
|
||||
TIM2_UPD: 30
|
||||
TIM3_CC1: 31
|
||||
TIM3_CC2: 32
|
||||
TIM3_CC3: 33
|
||||
TIM3_CC4: 34
|
||||
TIM3_UPD: 35
|
||||
TIM3_TRG: 36
|
||||
TIM16_CC1: 37
|
||||
TIM16_UPD: 38
|
||||
TIM17_CC1: 39
|
||||
TIM17_UPD: 40
|
||||
AES_IN: 41
|
||||
AES_OUT: 42
|
||||
HASH_IN: 43
|
||||
SAES_IN: 44
|
||||
SAES_OUT: 45
|
||||
LPTIM1_IC1: 46
|
||||
LPTIM1_IC2: 47
|
||||
LPTIM1_UE: 48
|
||||
LPTIM2_IC1: 49
|
||||
LPTIM2_IC2: 50
|
||||
LPTIM2_UE: 51
|
||||
8
data/extra/family/STM32F3.yaml
Normal file
8
data/extra/family/STM32F3.yaml
Normal file
@ -0,0 +1,8 @@
|
||||
---
|
||||
peripherals:
|
||||
- name: VREFINTCAL
|
||||
address: 0x1FFFF7BA
|
||||
registers:
|
||||
kind: vrefintcal
|
||||
version: v1
|
||||
block: VREFINTCAL
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/ADC:
|
||||
description: Analog-to-digital converter
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/ADC:
|
||||
description: Analog-to-Digital Converter
|
||||
items:
|
||||
@ -65,26 +64,26 @@ block/ADC:
|
||||
fieldset: JSQR
|
||||
- name: OFR
|
||||
description: offset register X
|
||||
byte_offset: 96
|
||||
fieldset: OFR
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 96
|
||||
fieldset: OFR
|
||||
- name: JDR
|
||||
description: injected data register X
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 128
|
||||
access: Read
|
||||
fieldset: JDR
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
- name: AWDCR
|
||||
description: "Analog Watchdog X Configuration\r Register"
|
||||
byte_offset: 160
|
||||
fieldset: AWDCR
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 160
|
||||
fieldset: AWDCR
|
||||
- name: DIFSEL
|
||||
description: "Differential Mode Selection Register\r 2"
|
||||
byte_offset: 176
|
||||
@ -472,10 +471,10 @@ fieldset/SMPR1:
|
||||
description: Channel x sampling time selection
|
||||
bit_offset: 3
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
array:
|
||||
len: 9
|
||||
stride: 3
|
||||
enum: SAMPLE_TIME
|
||||
fieldset/SMPR2:
|
||||
description: sample time register 2
|
||||
fields:
|
||||
@ -483,10 +482,10 @@ fieldset/SMPR2:
|
||||
description: Channel x sampling time selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
array:
|
||||
len: 9
|
||||
stride: 3
|
||||
enum: SAMPLE_TIME
|
||||
fieldset/SQR1:
|
||||
description: regular sequence register 1
|
||||
fields:
|
||||
@ -727,10 +726,10 @@ enum/JQM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Mode0
|
||||
description: "JSQR Mode 0: Queue maintains the last written configuration into JSQR"
|
||||
description: 'JSQR Mode 0: Queue maintains the last written configuration into JSQR'
|
||||
value: 0
|
||||
- name: Mode1
|
||||
description: "JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence"
|
||||
description: 'JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence'
|
||||
value: 1
|
||||
enum/RES:
|
||||
bit_size: 2
|
||||
|
||||
610
data/registers/adc_f3_v2.yaml
Normal file
610
data/registers/adc_f3_v2.yaml
Normal file
@ -0,0 +1,610 @@
|
||||
block/ADC:
|
||||
description: Analog-to-Digital Converter
|
||||
items:
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 0
|
||||
fieldset: SR
|
||||
- name: CR1
|
||||
description: control register 1
|
||||
byte_offset: 4
|
||||
fieldset: CR1
|
||||
- name: CR2
|
||||
description: control register 2
|
||||
byte_offset: 8
|
||||
fieldset: CR2
|
||||
- name: SMPR1
|
||||
description: sample time register 1
|
||||
byte_offset: 12
|
||||
fieldset: SMPR1
|
||||
- name: SMPR2
|
||||
description: sample time register 2
|
||||
byte_offset: 16
|
||||
fieldset: SMPR2
|
||||
- name: JOFR1
|
||||
description: injected channel data offset register 1
|
||||
byte_offset: 20
|
||||
fieldset: JOFR1
|
||||
- name: JOFR2
|
||||
description: injected channel data offset register 2
|
||||
byte_offset: 24
|
||||
fieldset: JOFR2
|
||||
- name: JOFR3
|
||||
description: injected channel data offset register 3
|
||||
byte_offset: 28
|
||||
fieldset: JOFR3
|
||||
- name: JOFR4
|
||||
description: injected channel data offset register 4
|
||||
byte_offset: 32
|
||||
fieldset: JOFR4
|
||||
- name: HTR
|
||||
description: watchdog higher threshold register
|
||||
byte_offset: 36
|
||||
fieldset: HTR
|
||||
- name: LTR
|
||||
description: watchdog lower threshold register
|
||||
byte_offset: 40
|
||||
fieldset: LTR
|
||||
- name: SQR1
|
||||
description: regular sequence register 1
|
||||
byte_offset: 44
|
||||
fieldset: SQR1
|
||||
- name: SQR2
|
||||
description: regular sequence register 2
|
||||
byte_offset: 48
|
||||
fieldset: SQR2
|
||||
- name: SQR3
|
||||
description: regular sequence register 3
|
||||
byte_offset: 52
|
||||
fieldset: SQR3
|
||||
- name: JSQR
|
||||
description: injected sequence register
|
||||
byte_offset: 56
|
||||
fieldset: JSQR
|
||||
- name: JDR1
|
||||
description: injected data register 1
|
||||
byte_offset: 60
|
||||
access: Read
|
||||
fieldset: JDR1
|
||||
- name: JDR2
|
||||
description: injected data register 2
|
||||
byte_offset: 64
|
||||
access: Read
|
||||
fieldset: JDR2
|
||||
- name: JDR3
|
||||
description: injected data register 3
|
||||
byte_offset: 68
|
||||
access: Read
|
||||
fieldset: JDR3
|
||||
- name: JDR4
|
||||
description: injected data register 4
|
||||
byte_offset: 72
|
||||
access: Read
|
||||
fieldset: JDR4
|
||||
- name: DR
|
||||
description: regular data register
|
||||
byte_offset: 76
|
||||
access: Read
|
||||
fieldset: DR
|
||||
fieldset/CR1:
|
||||
description: control register 1
|
||||
fields:
|
||||
- name: AWDCH
|
||||
description: analog watchdog channel select bits
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: EOCIE
|
||||
description: interrupt enable for EOC
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: AWDIE
|
||||
description: analog watchdog interrupt enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: JEOCIE
|
||||
description: interrupt enable for injected channels
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: SCAN
|
||||
description: scan mode
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: AWDSGL
|
||||
description: enable the watchdog on a single channel in scan mode
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: JAUTO
|
||||
description: automatic injected group conversion
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DISCEN
|
||||
description: discontinuous mode on regular channels
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: JDISCEN
|
||||
description: discontinuous mode on injected channels
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DISCNUM
|
||||
description: discontinuous mode channel count
|
||||
bit_offset: 13
|
||||
bit_size: 3
|
||||
enum: DISCNUM
|
||||
- name: JAWDEN
|
||||
description: analog watchdog enable on injected channels
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: AWDEN
|
||||
description: analog watchdog enable on regular channels
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/CR2:
|
||||
description: control register 2
|
||||
fields:
|
||||
- name: ADON
|
||||
description: A/D converter ON / OFF
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: CONT
|
||||
description: continuous conversion
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: CAL
|
||||
description: A/D calibration
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: RSTCAL
|
||||
description: reset calibration
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DMA
|
||||
description: DMA disable selection (for single ADC mode)
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ALIGN
|
||||
description: data alignment
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: JEXTSEL
|
||||
description: external event select for injected group
|
||||
bit_offset: 12
|
||||
bit_size: 3
|
||||
enum: JEXTSEL
|
||||
- name: JEXTTRIG
|
||||
description: external trigger conversion mode for injected channels
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: EXTSEL
|
||||
description: external event select for regular group
|
||||
bit_offset: 17
|
||||
bit_size: 3
|
||||
enum: EXTSEL
|
||||
- name: EXTTRIG
|
||||
description: external trigger conversion mode for regular channels
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: JSWSTART
|
||||
description: start conversion of injected channels
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: SWSTART
|
||||
description: start conversion of regular channels
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TSVREFE
|
||||
description: temperature sensor and VREFINT enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/DR:
|
||||
description: regular data register
|
||||
fields:
|
||||
- name: DATA
|
||||
description: Regular data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/HTR:
|
||||
description: watchdog higher threshold register
|
||||
fields:
|
||||
- name: HT
|
||||
description: Analog watchdog high threshold
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/JDR1:
|
||||
description: injected data register 1
|
||||
fields:
|
||||
- name: JDATA1
|
||||
description: Injected data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/JDR2:
|
||||
description: injected data register 2
|
||||
fields:
|
||||
- name: JDATA2
|
||||
description: Injected data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/JDR3:
|
||||
description: injected data register 3
|
||||
fields:
|
||||
- name: JDATA3
|
||||
description: Injected data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/JDR4:
|
||||
description: injected data register 4
|
||||
fields:
|
||||
- name: JDATA4
|
||||
description: Injected data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/JOFR1:
|
||||
description: injected channel data offset register 1
|
||||
fields:
|
||||
- name: JOFFSET1
|
||||
description: data offset for injected channel 1
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/JOFR2:
|
||||
description: injected channel data offset register 2
|
||||
fields:
|
||||
- name: JOFFSET2
|
||||
description: data offset for injected channel 2
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/JOFR3:
|
||||
description: injected channel data offset register 3
|
||||
fields:
|
||||
- name: JOFFSET3
|
||||
description: data offset for injected channel 3
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/JOFR4:
|
||||
description: injected channel data offset register 4
|
||||
fields:
|
||||
- name: JOFFSET4
|
||||
description: data offset for injected channel 4
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/JSQR:
|
||||
description: injected sequence register
|
||||
fields:
|
||||
- name: JSQ1
|
||||
description: 1st conversion in injected sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: JSQ2
|
||||
description: 2nd conversion in injected sequence
|
||||
bit_offset: 5
|
||||
bit_size: 5
|
||||
- name: JSQ3
|
||||
description: 3rd conversion in injected sequence
|
||||
bit_offset: 10
|
||||
bit_size: 5
|
||||
- name: JSQ4
|
||||
description: 4th conversion in injected sequence
|
||||
bit_offset: 15
|
||||
bit_size: 5
|
||||
- name: JL
|
||||
description: injected sequence length
|
||||
bit_offset: 20
|
||||
bit_size: 2
|
||||
fieldset/LTR:
|
||||
description: watchdog lower threshold register
|
||||
fields:
|
||||
- name: LT
|
||||
description: Analog watchdog low threshold
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/SMPR1:
|
||||
description: sample time register 1
|
||||
fields:
|
||||
- name: SMP10
|
||||
description: channel 10 sampling time selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP11
|
||||
description: channel 11 sampling time selection
|
||||
bit_offset: 3
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP12
|
||||
description: channel 12 sampling time selection
|
||||
bit_offset: 6
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP13
|
||||
description: channel 13 sampling time selection
|
||||
bit_offset: 9
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP14
|
||||
description: channel 14 sampling time selection
|
||||
bit_offset: 12
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP15
|
||||
description: channel 15 sampling time selection
|
||||
bit_offset: 15
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP16
|
||||
description: channel 16 sampling time selection
|
||||
bit_offset: 18
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP17
|
||||
description: channel 17 sampling time selection
|
||||
bit_offset: 21
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP18
|
||||
description: channel 18 sampling time selection
|
||||
bit_offset: 24
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
fieldset/SMPR2:
|
||||
description: sample time register 2
|
||||
fields:
|
||||
- name: SMP0
|
||||
description: channel 0 sampling time selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP1
|
||||
description: channel 1 sampling time selection
|
||||
bit_offset: 3
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP2
|
||||
description: channel 2 sampling time selection
|
||||
bit_offset: 6
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP3
|
||||
description: channel 3 sampling time selection
|
||||
bit_offset: 9
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP4
|
||||
description: channel 4 sampling time selection
|
||||
bit_offset: 12
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP5
|
||||
description: channel 5 sampling time selection
|
||||
bit_offset: 15
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP6
|
||||
description: channel 6 sampling time selection
|
||||
bit_offset: 18
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP7
|
||||
description: channel 7 sampling time selection
|
||||
bit_offset: 21
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP8
|
||||
description: channel 8 sampling time selection
|
||||
bit_offset: 24
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMP9
|
||||
description: channel 9 sampling time selection
|
||||
bit_offset: 27
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
fieldset/SQR1:
|
||||
description: regular sequence register 1
|
||||
fields:
|
||||
- name: SQ13
|
||||
description: 13th conversion in regular sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: SQ14
|
||||
description: 14th conversion in regular sequence
|
||||
bit_offset: 5
|
||||
bit_size: 5
|
||||
- name: SQ15
|
||||
description: 15th conversion in regular sequence
|
||||
bit_offset: 10
|
||||
bit_size: 5
|
||||
- name: SQ16
|
||||
description: 16th conversion in regular sequence
|
||||
bit_offset: 15
|
||||
bit_size: 5
|
||||
- name: L
|
||||
description: regular channel sequence length
|
||||
bit_offset: 20
|
||||
bit_size: 4
|
||||
fieldset/SQR2:
|
||||
description: regular sequence register 2
|
||||
fields:
|
||||
- name: SQ7
|
||||
description: 7th conversion in regular sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: SQ8
|
||||
description: 8th conversion in regular sequence
|
||||
bit_offset: 5
|
||||
bit_size: 5
|
||||
- name: SQ9
|
||||
description: 9th conversion in regular sequence
|
||||
bit_offset: 10
|
||||
bit_size: 5
|
||||
- name: SQ10
|
||||
description: 10th conversion in regular sequence
|
||||
bit_offset: 15
|
||||
bit_size: 5
|
||||
- name: SQ11
|
||||
description: 11th conversion in regular sequence
|
||||
bit_offset: 20
|
||||
bit_size: 5
|
||||
- name: SQ12
|
||||
description: 12th conversion in regular sequence
|
||||
bit_offset: 25
|
||||
bit_size: 5
|
||||
fieldset/SQR3:
|
||||
description: regular sequence register 3
|
||||
fields:
|
||||
- name: SQ1
|
||||
description: 1st conversion in regular sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: SQ2
|
||||
description: 2nd conversion in regular sequence
|
||||
bit_offset: 5
|
||||
bit_size: 5
|
||||
- name: SQ3
|
||||
description: 3rd conversion in regular sequence
|
||||
bit_offset: 10
|
||||
bit_size: 5
|
||||
- name: SQ4
|
||||
description: 4th conversion in regular sequence
|
||||
bit_offset: 15
|
||||
bit_size: 5
|
||||
- name: SQ5
|
||||
description: 5th conversion in regular sequence
|
||||
bit_offset: 20
|
||||
bit_size: 5
|
||||
- name: SQ6
|
||||
description: 6th conversion in regular sequence
|
||||
bit_offset: 25
|
||||
bit_size: 5
|
||||
fieldset/SR:
|
||||
description: status register
|
||||
fields:
|
||||
- name: AWD
|
||||
description: analog watchdog flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOC
|
||||
description: end of conversion
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: JEOC
|
||||
description: injected channel end of conversion
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: JSTRT
|
||||
description: injected channel start flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: STRT
|
||||
description: regular channel start flag
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: OVR
|
||||
description: overrun
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum/DISCNUM:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: DISCNUM_1
|
||||
description: 1 conversions are discontinued and the conversion is carried out on one channel
|
||||
value: 0
|
||||
- name: DISCNUM_2
|
||||
description: 2 conversion is discontinued and the conversions are carried out on 2 channels
|
||||
value: 1
|
||||
- name: DISCNUM_3
|
||||
description: 3 conversions are discontinued and the conversions are carried out on 3 channels
|
||||
value: 2
|
||||
- name: DISCNUM_4
|
||||
description: 4 conversions are discontinued and the conversions are carried out on 4 channels
|
||||
value: 3
|
||||
- name: DISCNUM_5
|
||||
description: 5 conversions are discontinued and the conversions are carried out on 5 channels
|
||||
value: 4
|
||||
- name: DISCNUM_6
|
||||
description: 6 conversions are discontinued and the conversions are carried out on 6 channels
|
||||
value: 5
|
||||
- name: DISCNUM_7
|
||||
description: 7 conversions are discontinued and the conversions are carried out on 7 channels
|
||||
value: 6
|
||||
- name: DISCNUM_8
|
||||
description: 8 conversions are discontinued and the conversions are carried out on 8 channels
|
||||
value: 7
|
||||
enum/EXTSEL:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: TIM19_TRGO
|
||||
description: Timer 19 TRGO event
|
||||
value: 0
|
||||
- name: TIM19_CC3
|
||||
description: Timer 19 CC3 event
|
||||
value: 1
|
||||
- name: TIM19_CC4
|
||||
description: Timer 19 CC4 event
|
||||
value: 2
|
||||
- name: TIM2_CC2
|
||||
description: Timer 2 CC2 event
|
||||
value: 3
|
||||
- name: TIM3_TRGO
|
||||
description: Timer 3 TRGO event
|
||||
value: 4
|
||||
- name: TIM4_CC4
|
||||
description: Timer 4 CC4 event
|
||||
value: 5
|
||||
- name: EXTI_LINE11
|
||||
description: External interrupt line 11
|
||||
value: 6
|
||||
- name: SWSTART
|
||||
description: SWSTART bit
|
||||
value: 7
|
||||
enum/JEXTSEL:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: TIM19_CC1
|
||||
description: Timer 19 CC1 event
|
||||
value: 0
|
||||
- name: TIM19_CC2
|
||||
description: Timer 19 CC2 event
|
||||
value: 1
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 2
|
||||
- name: TIM2_CC1
|
||||
description: Timer 2 CC1 event
|
||||
value: 3
|
||||
- name: TIM3_CC4
|
||||
description: Timer 3 CC4 event
|
||||
value: 4
|
||||
- name: TIM4_TRGO
|
||||
description: Timer 4 TRGO event
|
||||
value: 5
|
||||
- name: EXTI_LINE15
|
||||
description: External interrupt line 15
|
||||
value: 6
|
||||
- name: JSWSTART
|
||||
description: JSWSTART bit
|
||||
value: 7
|
||||
enum/SAMPLE_TIME:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Cycles1_5
|
||||
description: 1.5 ADC clock cycles
|
||||
value: 0
|
||||
- name: Cycles7_5
|
||||
description: 7.5 ADC clock cycles
|
||||
value: 1
|
||||
- name: Cycles13_5
|
||||
description: 13.5 ADC clock cycles
|
||||
value: 2
|
||||
- name: Cycles28_5
|
||||
description: 28.5 ADC clock cycles
|
||||
value: 3
|
||||
- name: Cycles41_5
|
||||
description: 41.5 ADC clock cycles
|
||||
value: 4
|
||||
- name: Cycles55_5
|
||||
description: 55.5 ADC clock cycles
|
||||
value: 5
|
||||
- name: Cycles71_5
|
||||
description: 71.5 ADC clock cycles
|
||||
value: 6
|
||||
- name: Cycles239_5
|
||||
description: 239.5 ADC clock cycles
|
||||
value: 7
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/ADC:
|
||||
description: Analog to Digital Converter
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/ADC:
|
||||
description: Analog-to-digital converter
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/ADC:
|
||||
description: Analog-to-digital converter
|
||||
items:
|
||||
@ -77,22 +76,18 @@ fieldset/CR1:
|
||||
description: Interrupt enable for EOC
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: EOCIE
|
||||
- name: AWDIE
|
||||
description: Analog watchdog interrupt enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
enum: AWDIE
|
||||
- name: JEOCIE
|
||||
description: Interrupt enable for injected channels
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: JEOCIE
|
||||
- name: SCAN
|
||||
description: Scan mode
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: SCAN
|
||||
- name: AWDSGL
|
||||
description: Enable the watchdog on a single channel in scan mode
|
||||
bit_offset: 9
|
||||
@ -102,17 +97,14 @@ fieldset/CR1:
|
||||
description: Automatic injected group conversion
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: JAUTO
|
||||
- name: DISCEN
|
||||
description: Discontinuous mode on regular channels
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
enum: DISCEN
|
||||
- name: JDISCEN
|
||||
description: Discontinuous mode on injected channels
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
enum: JDISCEN
|
||||
- name: DISCNUM
|
||||
description: Discontinuous mode channel count
|
||||
bit_offset: 13
|
||||
@ -121,12 +113,10 @@ fieldset/CR1:
|
||||
description: Analog watchdog enable on injected channels
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
enum: JAWDEN
|
||||
- name: AWDEN
|
||||
description: Analog watchdog enable on regular channels
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
enum: AWDEN
|
||||
- name: RES
|
||||
description: Resolution
|
||||
bit_offset: 24
|
||||
@ -136,7 +126,6 @@ fieldset/CR1:
|
||||
description: Overrun interrupt enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
enum: OVRIE
|
||||
fieldset/CR2:
|
||||
description: control register 2
|
||||
fields:
|
||||
@ -144,7 +133,6 @@ fieldset/CR2:
|
||||
description: A/D Converter ON / OFF
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
enum: ADON
|
||||
- name: CONT
|
||||
description: Continuous conversion
|
||||
bit_offset: 1
|
||||
@ -154,7 +142,6 @@ fieldset/CR2:
|
||||
description: Direct memory access mode (for single ADC mode)
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: DMA
|
||||
- name: DDS
|
||||
description: DMA disable selection (for single ADC mode)
|
||||
bit_offset: 9
|
||||
@ -346,15 +333,6 @@ fieldset/SR:
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: OVR
|
||||
enum/ADON:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Disable ADC conversion and go to power down mode
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Enable ADC
|
||||
value: 1
|
||||
enum/ALIGN:
|
||||
bit_size: 1
|
||||
variants:
|
||||
@ -373,24 +351,6 @@ enum/AWD:
|
||||
- name: Event
|
||||
description: Analog watchdog event occurred
|
||||
value: 1
|
||||
enum/AWDEN:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Analog watchdog disabled on regular channels
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Analog watchdog enabled on regular channels
|
||||
value: 1
|
||||
enum/AWDIE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Analogue watchdog interrupt disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Analogue watchdog interrupt enabled
|
||||
value: 1
|
||||
enum/AWDSGL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
@ -418,24 +378,6 @@ enum/DDS:
|
||||
- name: Continuous
|
||||
description: DMA requests are issued as long as data are converted and DMA=1
|
||||
value: 1
|
||||
enum/DISCEN:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Discontinuous mode on regular channels disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Discontinuous mode on regular channels enabled
|
||||
value: 1
|
||||
enum/DMA:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: DMA mode disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: DMA mode enabled
|
||||
value: 1
|
||||
enum/EOC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
@ -445,15 +387,6 @@ enum/EOC:
|
||||
- name: Complete
|
||||
description: Conversion complete
|
||||
value: 1
|
||||
enum/EOCIE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: EOC interrupt disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: EOC interrupt enabled
|
||||
value: 1
|
||||
enum/EOCS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
@ -502,33 +435,6 @@ enum/EXTSEL:
|
||||
- name: TIM2TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 6
|
||||
enum/JAUTO:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Automatic injected group conversion disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Automatic injected group conversion enabled
|
||||
value: 1
|
||||
enum/JAWDEN:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Analog watchdog disabled on injected channels
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Analog watchdog enabled on injected channels
|
||||
value: 1
|
||||
enum/JDISCEN:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Discontinuous mode on injected channels disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Discontinuous mode on injected channels enabled
|
||||
value: 1
|
||||
enum/JEOC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
@ -538,15 +444,6 @@ enum/JEOC:
|
||||
- name: Complete
|
||||
description: Conversion complete
|
||||
value: 1
|
||||
enum/JEOCIE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: JEOC interrupt disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: JEOC interrupt enabled
|
||||
value: 1
|
||||
enum/JEXTEN:
|
||||
bit_size: 2
|
||||
variants:
|
||||
@ -625,15 +522,6 @@ enum/OVR:
|
||||
- name: Overrun
|
||||
description: Overrun occurred
|
||||
value: 1
|
||||
enum/OVRIE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Overrun interrupt disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Overrun interrupt enabled
|
||||
value: 1
|
||||
enum/RES:
|
||||
bit_size: 2
|
||||
variants:
|
||||
@ -676,15 +564,6 @@ enum/SAMPLE_TIME:
|
||||
- name: Cycles480
|
||||
description: 480 cycles
|
||||
value: 7
|
||||
enum/SCAN:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Scan mode disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Scan mode enabled
|
||||
value: 1
|
||||
enum/SMPR_SMPx_x:
|
||||
bit_size: 32
|
||||
variants:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/ADC:
|
||||
description: Analog-to-Digital Converter
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/ADC:
|
||||
description: Analog to Digital Converter
|
||||
items:
|
||||
@ -569,7 +568,7 @@ fieldset/PCSEL:
|
||||
description: channel preselection register
|
||||
fields:
|
||||
- name: PCSEL
|
||||
description: "Channel x (VINP[i]) pre selection"
|
||||
description: Channel x (VINP[i]) pre selection
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
@ -860,10 +859,10 @@ enum/JQM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Mode0
|
||||
description: "JSQR Mode 0: Queue maintains the last written configuration into JSQR"
|
||||
description: 'JSQR Mode 0: Queue maintains the last written configuration into JSQR'
|
||||
value: 0
|
||||
- name: Mode1
|
||||
description: "JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence"
|
||||
description: 'JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence'
|
||||
value: 1
|
||||
enum/OVRMOD:
|
||||
bit_size: 1
|
||||
|
||||
284
data/registers/adccommon_f3.yaml
Normal file
284
data/registers/adccommon_f3.yaml
Normal file
@ -0,0 +1,284 @@
|
||||
block/ADC_COMMON:
|
||||
description: ADC common registers
|
||||
items:
|
||||
- name: CSR
|
||||
description: ADC Common status register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: CSR
|
||||
- name: CCR
|
||||
description: ADC common control register
|
||||
byte_offset: 8
|
||||
fieldset: CCR
|
||||
- name: CDR
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
byte_offset: 12
|
||||
access: Read
|
||||
fieldset: CDR
|
||||
fieldset/CCR:
|
||||
description: ADC common control register
|
||||
fields:
|
||||
- name: DUAL
|
||||
description: Dual ADC mode selection
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
enum: DUAL
|
||||
- name: DELAY
|
||||
description: Delay between 2 sampling phases
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
- name: DMACFG
|
||||
description: DMA configuration (for multi-ADC mode)
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
enum: DMACFG
|
||||
- name: MDMA
|
||||
description: Direct memory access mode for multi ADC mode
|
||||
bit_offset: 14
|
||||
bit_size: 2
|
||||
enum: MDMA
|
||||
- name: CKMODE
|
||||
description: ADC clock mode
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: CKMODE
|
||||
- name: VREFEN
|
||||
description: VREFINT enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TSEN
|
||||
description: Temperature sensor enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: VBATEN
|
||||
description: VBAT enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/CDR:
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
fields:
|
||||
- name: RDATA_MST
|
||||
description: Regular data of the master ADC
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: RDATA_SLV
|
||||
description: Regular data of the master ADC
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/CSR:
|
||||
fields:
|
||||
- name: ADRDY_MST
|
||||
description: Master ADC ready
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMP_MST
|
||||
description: End of sampling phase flag of the master ADC
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: EOC_MST
|
||||
description: End of regular conversion of the master ADC
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: EOS_MST
|
||||
description: End of regular sequence flag of the master ADC
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: OVR_MST
|
||||
description: Overrun flag of the master ADC
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: OVR
|
||||
- name: JEOC_MST
|
||||
description: End of injected conversion of the master ADC
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: JEOS
|
||||
description: End of injected sequence flag of the master ADC
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: AWD1_MST
|
||||
description: Analog watchdog 1 flag of the master ADC
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: AWD
|
||||
- name: AWD2_MST
|
||||
description: Analog watchdog 2 flag of the master ADC
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: AWD
|
||||
- name: AWD3_MST
|
||||
description: Analog watchdog 3 flag of the master ADC
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: AWD
|
||||
- name: JQOVF_MST
|
||||
description: Injected context queue overflow flag of the master ADC
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: JQOVF
|
||||
- name: ADRDY_SLV
|
||||
description: Slave ADC ready
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOSMP_SLV
|
||||
description: End of sampling phase flag of the slave ADC
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: EOC_SLV
|
||||
description: End of regular conversion of the slave ADC
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: EOS_SLV
|
||||
description: End of regular sequence flag of the slave ADC
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: OVR_SLV
|
||||
description: Overrun flag of the slave ADC
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
enum: OVR
|
||||
- name: JEOC_SLV
|
||||
description: End of injected conversion of the slave ADC
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: JEOS_SLV
|
||||
description: End of injected sequence flag of the slave ADC
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
enum: ENDED
|
||||
- name: AWD1_SLV
|
||||
description: Analog watchdog 1 flag of the slave ADC
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
enum: AWD
|
||||
- name: AWD2_SLV
|
||||
description: Analog watchdog 2 flag of the slave ADC
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
enum: AWD
|
||||
- name: AWD3_SLV
|
||||
description: Analog watchdog 3 flag of the slave ADC
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
enum: AWD
|
||||
- name: JQOVF_SLV
|
||||
description: Injected context queue overflow flag of the slave ADC
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
enum: JQOVF
|
||||
enum/AWD:
|
||||
description: Analog watchdog flag
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoEvent
|
||||
description: No analog watchdog event occurred
|
||||
value: 0
|
||||
- name: Event
|
||||
description: Analog watchdog event occurred
|
||||
value: 1
|
||||
enum/CKMODE:
|
||||
description: ADC clock mode
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Asynchronous
|
||||
description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous mode
|
||||
value: 0
|
||||
- name: SyncDiv1
|
||||
description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck.
|
||||
value: 1
|
||||
- name: SyncDiv2
|
||||
description: Use AHB clock rcc_hclk3 divided by 2.
|
||||
value: 2
|
||||
- name: SyncDiv4
|
||||
description: Use AHB clock rcc_hclk3 divided by 4.
|
||||
value: 3
|
||||
enum/DMACFG:
|
||||
description: DMA configuration (for multi-ADC mode)
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: OneShot
|
||||
description: DMA one shot mode selected
|
||||
value: 0
|
||||
- name: Circulator
|
||||
description: DMA circular mode selected
|
||||
value: 1
|
||||
enum/DUAL:
|
||||
description: Dual ADC mode selection
|
||||
bit_size: 5
|
||||
variants:
|
||||
- name: Independent
|
||||
description: Independent mode
|
||||
value: 0
|
||||
- name: DualRJ
|
||||
description: Dual, combined regular simultaneous + injected simultaneous mode
|
||||
value: 1
|
||||
- name: DualRA
|
||||
description: Dual, combined regular simultaneous + alternate trigger mode
|
||||
value: 2
|
||||
- name: DualIJ
|
||||
description: Dual, combined injected simultaneous + fast interleaved mode
|
||||
value: 3
|
||||
- name: DualJ
|
||||
description: Dual, injected simultaneous mode only
|
||||
value: 5
|
||||
- name: DualR
|
||||
description: Dual, regular simultaneous mode only
|
||||
value: 6
|
||||
- name: DualI
|
||||
description: dual, interleaved mode only
|
||||
value: 7
|
||||
- name: DualA
|
||||
description: Dual, alternate trigger mode only
|
||||
value: 9
|
||||
enum/ENDED:
|
||||
description: End of operation
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotEnded
|
||||
description: Operation is not ended
|
||||
value: 0
|
||||
- name: Ended
|
||||
description: Operation is ended
|
||||
value: 1
|
||||
enum/JQOVF:
|
||||
description: Injected context queue overflow flag
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoOverflow
|
||||
description: No injected context queue overflow
|
||||
value: 0
|
||||
- name: Overflow
|
||||
description: Injected context queue overflow
|
||||
value: 1
|
||||
enum/MDMA:
|
||||
description: Direct memory access mode for multi ADC mode
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: MDMA mode disabled
|
||||
value: 0
|
||||
- name: Bits12_10
|
||||
description: MDMA mode enabled for 12 and 10-bit resolution
|
||||
value: 2
|
||||
- name: Bit8_6
|
||||
description: MDMA mode enabled for 8 and 6-bit resolution
|
||||
value: 3
|
||||
enum/OVR:
|
||||
description: Overrun flag
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoOverrun
|
||||
description: No overrun occurred
|
||||
value: 0
|
||||
- name: Overrun
|
||||
description: Overrun occurred
|
||||
value: 1
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/ADC_COMMON:
|
||||
description: ADC common registers
|
||||
items:
|
||||
@ -47,12 +46,10 @@ fieldset/CCR:
|
||||
description: VBAT enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
enum: VBATE
|
||||
- name: TSVREFE
|
||||
description: Temperature sensor and VREFINT enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
enum: TSVREFE
|
||||
fieldset/CDR:
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
fields:
|
||||
@ -145,7 +142,7 @@ enum/DDS:
|
||||
description: No new DMA request is issued after the last transfer
|
||||
value: 0
|
||||
- name: Continuous
|
||||
description: "DMA requests are issued as long as data are converted and DMA=01, 10 or 11"
|
||||
description: DMA requests are issued as long as data are converted and DMA=01, 10 or 11
|
||||
value: 1
|
||||
enum/DMA:
|
||||
bit_size: 2
|
||||
@ -193,43 +190,43 @@ enum/MULTI:
|
||||
bit_size: 5
|
||||
variants:
|
||||
- name: Independent
|
||||
description: "All the ADCs independent: independent mode"
|
||||
description: 'All the ADCs independent: independent mode'
|
||||
value: 0
|
||||
- name: DualRJ
|
||||
description: "Dual ADC1 and ADC2, combined regular and injected simultaneous mode"
|
||||
description: Dual ADC1 and ADC2, combined regular and injected simultaneous mode
|
||||
value: 1
|
||||
- name: DualRA
|
||||
description: "Dual ADC1 and ADC2, combined regular and alternate trigger mode"
|
||||
description: Dual ADC1 and ADC2, combined regular and alternate trigger mode
|
||||
value: 2
|
||||
- name: DualJ
|
||||
description: "Dual ADC1 and ADC2, injected simultaneous mode only"
|
||||
description: Dual ADC1 and ADC2, injected simultaneous mode only
|
||||
value: 5
|
||||
- name: DualR
|
||||
description: "Dual ADC1 and ADC2, regular simultaneous mode only"
|
||||
description: Dual ADC1 and ADC2, regular simultaneous mode only
|
||||
value: 6
|
||||
- name: DualI
|
||||
description: "Dual ADC1 and ADC2, interleaved mode only"
|
||||
description: Dual ADC1 and ADC2, interleaved mode only
|
||||
value: 7
|
||||
- name: DualA
|
||||
description: "Dual ADC1 and ADC2, alternate trigger mode only"
|
||||
description: Dual ADC1 and ADC2, alternate trigger mode only
|
||||
value: 9
|
||||
- name: TripleRJ
|
||||
description: "Triple ADC, regular and injected simultaneous mode"
|
||||
description: Triple ADC, regular and injected simultaneous mode
|
||||
value: 17
|
||||
- name: TripleRA
|
||||
description: "Triple ADC, regular and alternate trigger mode"
|
||||
description: Triple ADC, regular and alternate trigger mode
|
||||
value: 18
|
||||
- name: TripleJ
|
||||
description: "Triple ADC, injected simultaneous mode only"
|
||||
description: Triple ADC, injected simultaneous mode only
|
||||
value: 21
|
||||
- name: TripleR
|
||||
description: "Triple ADC, regular simultaneous mode only"
|
||||
description: Triple ADC, regular simultaneous mode only
|
||||
value: 22
|
||||
- name: TripleI
|
||||
description: "Triple ADC, interleaved mode only"
|
||||
description: Triple ADC, interleaved mode only
|
||||
value: 23
|
||||
- name: TripleA
|
||||
description: "Triple ADC, alternate trigger mode only"
|
||||
description: Triple ADC, alternate trigger mode only
|
||||
value: 24
|
||||
enum/OVR:
|
||||
bit_size: 1
|
||||
@ -249,21 +246,3 @@ enum/STRT:
|
||||
- name: Started
|
||||
description: Regular channel conversion has started
|
||||
value: 1
|
||||
enum/TSVREFE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Temperature sensor and V_REFINT channel disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Temperature sensor and V_REFINT channel enabled
|
||||
value: 1
|
||||
enum/VBATE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: V_BAT channel disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: V_BAT channel enabled
|
||||
value: 1
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/ADC_COMMON:
|
||||
description: Analog-to-Digital Converter
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/ADC_COMMON:
|
||||
description: Analog-to-Digital Converter
|
||||
items:
|
||||
@ -228,7 +227,7 @@ enum/DAMDF:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: NoPack
|
||||
description: "Without data packing, CDR/CDR2 not used"
|
||||
description: Without data packing, CDR/CDR2 not used
|
||||
value: 0
|
||||
- name: Format32to10
|
||||
description: CDR formatted for 32-bit down to 10-bit resolution
|
||||
@ -243,25 +242,25 @@ enum/DUAL:
|
||||
description: Independent mode
|
||||
value: 0
|
||||
- name: DualRJ
|
||||
description: "Dual, combined regular simultaneous + injected simultaneous mode"
|
||||
description: Dual, combined regular simultaneous + injected simultaneous mode
|
||||
value: 1
|
||||
- name: DualRA
|
||||
description: "Dual, combined regular simultaneous + alternate trigger mode"
|
||||
description: Dual, combined regular simultaneous + alternate trigger mode
|
||||
value: 2
|
||||
- name: DualIJ
|
||||
description: "Dual, combined interleaved mode + injected simultaneous mode"
|
||||
description: Dual, combined interleaved mode + injected simultaneous mode
|
||||
value: 3
|
||||
- name: DualJ
|
||||
description: "Dual, injected simultaneous mode only"
|
||||
description: Dual, injected simultaneous mode only
|
||||
value: 5
|
||||
- name: DualR
|
||||
description: "Dual, regular simultaneous mode only"
|
||||
description: Dual, regular simultaneous mode only
|
||||
value: 6
|
||||
- name: DualI
|
||||
description: "Dual, interleaved mode only"
|
||||
description: Dual, interleaved mode only
|
||||
value: 7
|
||||
- name: DualA
|
||||
description: "Dual, alternate trigger mode only"
|
||||
description: Dual, alternate trigger mode only
|
||||
value: 9
|
||||
enum/EOC_MST:
|
||||
bit_size: 1
|
||||
|
||||
204
data/registers/aes_f7.yaml
Normal file
204
data/registers/aes_f7.yaml
Normal file
@ -0,0 +1,204 @@
|
||||
block/AES:
|
||||
description: Advanced encryption standard hardware accelerator
|
||||
items:
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 4
|
||||
fieldset: SR
|
||||
- name: DINR
|
||||
description: Data input register
|
||||
byte_offset: 8
|
||||
fieldset: DINR
|
||||
- name: DOUTR
|
||||
description: Data output register
|
||||
byte_offset: 12
|
||||
fieldset: DOUTR
|
||||
- name: KEYR
|
||||
description: Key register
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 4
|
||||
- 8
|
||||
- 12
|
||||
- 32
|
||||
- 36
|
||||
- 40
|
||||
- 44
|
||||
byte_offset: 16
|
||||
fieldset: KEYR
|
||||
- name: IVR
|
||||
description: Initialization vector register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 32
|
||||
fieldset: IVR
|
||||
- name: SUSPR
|
||||
description: Suspend register
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
byte_offset: 64
|
||||
fieldset: SUSPR
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: AES enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DATATYPE
|
||||
description: Data type selection
|
||||
bit_offset: 1
|
||||
bit_size: 2
|
||||
enum: DATATYPE
|
||||
- name: MODE
|
||||
description: Operating mode
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
enum: MODE
|
||||
- name: CHMOD10
|
||||
description: Chaining mode bit1 bit0
|
||||
bit_offset: 5
|
||||
bit_size: 2
|
||||
- name: CCFC
|
||||
description: Computation Complete Flag Clear
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: ERRC
|
||||
description: Error clear
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: CCFIE
|
||||
description: CCF flag interrupt enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DMAINEN
|
||||
description: Enable DMA management of data input phase
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DMAOUTEN
|
||||
description: Enable DMA management of data output phase
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: GCMPH
|
||||
description: GCM or CCM phase selection
|
||||
bit_offset: 13
|
||||
bit_size: 2
|
||||
enum: GCMPH
|
||||
- name: CHMOD2
|
||||
description: Chaining mode bit2
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: KEYSIZE
|
||||
description: Key size selection
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/DINR:
|
||||
description: Data input register
|
||||
fields:
|
||||
- name: DIN
|
||||
description: Input data word
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/DOUTR:
|
||||
description: Data output register
|
||||
fields:
|
||||
- name: DOUT
|
||||
description: Output data word
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/IVR:
|
||||
description: Initialization vector register
|
||||
fields:
|
||||
- name: IVI
|
||||
description: Initialization vector input
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/KEYR:
|
||||
description: Key register
|
||||
fields:
|
||||
- name: KEY
|
||||
description: Cryptographic key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: CCF
|
||||
description: Computation complete flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: Read error flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WRERR
|
||||
description: Write error flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: BUSY
|
||||
description: Busy flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
fieldset/SUSPR:
|
||||
description: Suspend register
|
||||
fields:
|
||||
- name: SUSP
|
||||
description: AES suspend
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
enum/DATATYPE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: None
|
||||
description: Word
|
||||
value: 0
|
||||
- name: HalfWord
|
||||
description: Half-word (16-bit)
|
||||
value: 1
|
||||
- name: Byte
|
||||
description: Byte (8-bit)
|
||||
value: 2
|
||||
- name: Bit
|
||||
description: Bit
|
||||
value: 3
|
||||
enum/GCMPH:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Init phase
|
||||
description: Init phase
|
||||
value: 0
|
||||
- name: Header phase
|
||||
description: Header phase
|
||||
value: 1
|
||||
- name: Payload phase
|
||||
description: Payload phase
|
||||
value: 2
|
||||
- name: Final phase
|
||||
description: Final phase
|
||||
value: 3
|
||||
enum/MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Mode1
|
||||
description: Encryption
|
||||
value: 0
|
||||
- name: Mode2
|
||||
description: Key derivation (or key preparation for ECB/CBC decryption)
|
||||
value: 1
|
||||
- name: Mode3
|
||||
description: Decryption
|
||||
value: 2
|
||||
- name: Mode4
|
||||
description: Key derivation then single decryption
|
||||
value: 3
|
||||
258
data/registers/aes_u5.yaml
Normal file
258
data/registers/aes_u5.yaml
Normal file
@ -0,0 +1,258 @@
|
||||
block/AES:
|
||||
description: Advanced encryption standard hardware accelerator
|
||||
items:
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 4
|
||||
fieldset: SR
|
||||
- name: DINR
|
||||
description: Data input register
|
||||
byte_offset: 8
|
||||
fieldset: DINR
|
||||
- name: DOUTR
|
||||
description: Data output register
|
||||
byte_offset: 12
|
||||
fieldset: DOUTR
|
||||
- name: KEYR
|
||||
description: Key register
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 4
|
||||
- 8
|
||||
- 12
|
||||
- 32
|
||||
- 36
|
||||
- 40
|
||||
- 44
|
||||
byte_offset: 16
|
||||
fieldset: KEYR
|
||||
- name: IVR
|
||||
description: Initialization vector register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 32
|
||||
fieldset: IVR
|
||||
- name: SUSPR
|
||||
description: Suspend register
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
byte_offset: 64
|
||||
fieldset: SUSPR
|
||||
- name: IER
|
||||
description: interrupt enable register
|
||||
byte_offset: 768
|
||||
fieldset: IER
|
||||
- name: ISR
|
||||
description: interrupt status register
|
||||
byte_offset: 772
|
||||
fieldset: ISR
|
||||
- name: ICR
|
||||
description: interrupt clear register
|
||||
byte_offset: 776
|
||||
fieldset: ICR
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: AES enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DATATYPE
|
||||
description: Data type selection
|
||||
bit_offset: 1
|
||||
bit_size: 2
|
||||
enum: DATATYPE
|
||||
- name: MODE
|
||||
description: Operating mode
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
enum: MODE
|
||||
- name: CHMOD10
|
||||
description: Chaining mode bit1 bit0
|
||||
bit_offset: 5
|
||||
bit_size: 2
|
||||
- name: DMAINEN
|
||||
description: Enable DMA management of data input phase
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DMAOUTEN
|
||||
description: Enable DMA management of data output phase
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: GCMPH
|
||||
description: GCM or CCM phase selection
|
||||
bit_offset: 13
|
||||
bit_size: 2
|
||||
enum: GCMPH
|
||||
- name: CHMOD2
|
||||
description: Chaining mode bit2
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: KEYSIZE
|
||||
description: Key size selection
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: NPBLB
|
||||
description: Number of padding bytes in last block of payload
|
||||
bit_offset: 20
|
||||
bit_size: 4
|
||||
- name: KMOD
|
||||
description: Key mode selection
|
||||
bit_offset: 24
|
||||
bit_size: 2
|
||||
- name: IPRST
|
||||
description: AES peripheral software reset
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/DINR:
|
||||
description: Data input register
|
||||
fields:
|
||||
- name: DIN
|
||||
description: Input data word
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/DOUTR:
|
||||
description: Data output register
|
||||
fields:
|
||||
- name: DOUT
|
||||
description: Output data word
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/ICR:
|
||||
description: Interrupt clear register
|
||||
fields:
|
||||
- name: CCF
|
||||
description: Computation complete flag clear
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RWEIF
|
||||
description: Read or write error interrupt flag clear
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: KEIF
|
||||
description: Key error interrupt flag clear
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
fieldset/IER:
|
||||
description: Interrupt enable register
|
||||
fields:
|
||||
- name: CCFIE
|
||||
description: Computation complete flag interrupt enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RWEIE
|
||||
description: Read or write error interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: KEIE
|
||||
description: Key error interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
fieldset/ISR:
|
||||
description: Interrupt status register
|
||||
fields:
|
||||
- name: CCF
|
||||
description: Computation complete flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RWEIF
|
||||
description: Read or write error interrupt flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: KEIF
|
||||
description: Key error interrupt flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
fieldset/IVR:
|
||||
description: Initialization vector register
|
||||
fields:
|
||||
- name: IVI
|
||||
description: Initialization vector input
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/KEYR:
|
||||
description: Key register
|
||||
fields:
|
||||
- name: KEY
|
||||
description: Cryptographic key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: CCF
|
||||
description: Computation complete flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: Read error flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WRERR
|
||||
description: Write error flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: BUSY
|
||||
description: Busy flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: KEYVALID
|
||||
description: Key valid flag
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
fieldset/SUSPR:
|
||||
description: Suspend register
|
||||
fields:
|
||||
- name: SUSP
|
||||
description: AES suspend
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
enum/DATATYPE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: None
|
||||
description: Word
|
||||
value: 0
|
||||
- name: HalfWord
|
||||
description: Half-word (16-bit)
|
||||
value: 1
|
||||
- name: Byte
|
||||
description: Byte (8-bit)
|
||||
value: 2
|
||||
- name: Bit
|
||||
description: Bit
|
||||
value: 3
|
||||
enum/GCMPH:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Init phase
|
||||
description: Init phase
|
||||
value: 0
|
||||
- name: Header phase
|
||||
description: Header phase
|
||||
value: 1
|
||||
- name: Payload phase
|
||||
description: Payload phase
|
||||
value: 2
|
||||
- name: Final phase
|
||||
description: Final phase
|
||||
value: 3
|
||||
enum/MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Mode1
|
||||
description: Encryption
|
||||
value: 0
|
||||
- name: Mode2
|
||||
description: Key derivation (or key preparation for ECB/CBC decryption)
|
||||
value: 1
|
||||
- name: Mode3
|
||||
description: Decryption
|
||||
value: 2
|
||||
151
data/registers/aes_v1.yaml
Normal file
151
data/registers/aes_v1.yaml
Normal file
@ -0,0 +1,151 @@
|
||||
block/AES:
|
||||
description: Advanced encryption standard hardware accelerator
|
||||
items:
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 4
|
||||
fieldset: SR
|
||||
- name: DINR
|
||||
description: Data input register
|
||||
byte_offset: 8
|
||||
fieldset: DINR
|
||||
- name: DOUTR
|
||||
description: Data output register
|
||||
byte_offset: 12
|
||||
fieldset: DOUTR
|
||||
- name: KEYR
|
||||
description: Key register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 16
|
||||
fieldset: KEYR
|
||||
- name: IVR
|
||||
description: Initialization vector register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 32
|
||||
fieldset: IVR
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: AES enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DATATYPE
|
||||
description: Data type selection
|
||||
bit_offset: 1
|
||||
bit_size: 2
|
||||
enum: DATATYPE
|
||||
- name: MODE
|
||||
description: Operating mode
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
enum: MODE
|
||||
- name: CHMOD10
|
||||
description: Chaining mode bit1 bit0
|
||||
bit_offset: 5
|
||||
bit_size: 2
|
||||
- name: CCFC
|
||||
description: Computation Complete Flag Clear
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: ERRC
|
||||
description: Error clear
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: CCFIE
|
||||
description: CCF flag interrupt enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DMAINEN
|
||||
description: Enable DMA management of data input phase
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DMAOUTEN
|
||||
description: Enable DMA management of data output phase
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
fieldset/DINR:
|
||||
description: Data input register
|
||||
fields:
|
||||
- name: DIN
|
||||
description: Input data word
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/DOUTR:
|
||||
description: Data output register
|
||||
fields:
|
||||
- name: DOUT
|
||||
description: Output data word
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/IVR:
|
||||
description: Initialization vector register
|
||||
fields:
|
||||
- name: IVI
|
||||
description: Initialization vector input
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/KEYR:
|
||||
description: Key register
|
||||
fields:
|
||||
- name: KEY
|
||||
description: Cryptographic key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: CCF
|
||||
description: Computation complete flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: Read error flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WRERR
|
||||
description: Write error flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum/DATATYPE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: None
|
||||
description: Word
|
||||
value: 0
|
||||
- name: HalfWord
|
||||
description: Half-word (16-bit)
|
||||
value: 1
|
||||
- name: Byte
|
||||
description: Byte (8-bit)
|
||||
value: 2
|
||||
- name: Bit
|
||||
description: Bit
|
||||
value: 3
|
||||
enum/MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Mode1
|
||||
description: Encryption
|
||||
value: 0
|
||||
- name: Mode2
|
||||
description: Key derivation (or key preparation for ECB/CBC decryption)
|
||||
value: 1
|
||||
- name: Mode3
|
||||
description: Decryption
|
||||
value: 2
|
||||
- name: Mode4
|
||||
description: Key derivation then single decryption
|
||||
value: 3
|
||||
208
data/registers/aes_v2.yaml
Normal file
208
data/registers/aes_v2.yaml
Normal file
@ -0,0 +1,208 @@
|
||||
block/AES:
|
||||
description: Advanced encryption standard hardware accelerator
|
||||
items:
|
||||
- name: CR
|
||||
description: Control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 4
|
||||
fieldset: SR
|
||||
- name: DINR
|
||||
description: Data input register
|
||||
byte_offset: 8
|
||||
fieldset: DINR
|
||||
- name: DOUTR
|
||||
description: Data output register
|
||||
byte_offset: 12
|
||||
fieldset: DOUTR
|
||||
- name: KEYR
|
||||
description: Key register
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 4
|
||||
- 8
|
||||
- 12
|
||||
- 32
|
||||
- 36
|
||||
- 40
|
||||
- 44
|
||||
byte_offset: 16
|
||||
fieldset: KEYR
|
||||
- name: IVR
|
||||
description: Initialization vector register
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 32
|
||||
fieldset: IVR
|
||||
- name: SUSPR
|
||||
description: Suspend register
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
byte_offset: 64
|
||||
fieldset: SUSPR
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: AES enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DATATYPE
|
||||
description: Data type selection
|
||||
bit_offset: 1
|
||||
bit_size: 2
|
||||
enum: DATATYPE
|
||||
- name: MODE
|
||||
description: Operating mode
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
enum: MODE
|
||||
- name: CHMOD10
|
||||
description: Chaining mode bit1 bit0
|
||||
bit_offset: 5
|
||||
bit_size: 2
|
||||
- name: CCFC
|
||||
description: Computation Complete Flag Clear
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: ERRC
|
||||
description: Error clear
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: CCFIE
|
||||
description: CCF flag interrupt enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DMAINEN
|
||||
description: Enable DMA management of data input phase
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DMAOUTEN
|
||||
description: Enable DMA management of data output phase
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: GCMPH
|
||||
description: GCM or CCM phase selection
|
||||
bit_offset: 13
|
||||
bit_size: 2
|
||||
enum: GCMPH
|
||||
- name: CHMOD2
|
||||
description: Chaining mode bit2
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: KEYSIZE
|
||||
description: Key size selection
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: NPBLB
|
||||
description: Number of padding bytes in last block of payload
|
||||
bit_offset: 20
|
||||
bit_size: 4
|
||||
fieldset/DINR:
|
||||
description: Data input register
|
||||
fields:
|
||||
- name: DIN
|
||||
description: Input data word
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/DOUTR:
|
||||
description: Data output register
|
||||
fields:
|
||||
- name: DOUT
|
||||
description: Output data word
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/IVR:
|
||||
description: Initialization vector register
|
||||
fields:
|
||||
- name: IVI
|
||||
description: Initialization vector input
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/KEYR:
|
||||
description: Key register
|
||||
fields:
|
||||
- name: KEY
|
||||
description: Cryptographic key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: CCF
|
||||
description: Computation complete flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: Read error flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WRERR
|
||||
description: Write error flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: BUSY
|
||||
description: Busy flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
fieldset/SUSPR:
|
||||
description: Suspend register
|
||||
fields:
|
||||
- name: SUSP
|
||||
description: AES suspend
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
enum/DATATYPE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: None
|
||||
description: Word
|
||||
value: 0
|
||||
- name: HalfWord
|
||||
description: Half-word (16-bit)
|
||||
value: 1
|
||||
- name: Byte
|
||||
description: Byte (8-bit)
|
||||
value: 2
|
||||
- name: Bit
|
||||
description: Bit
|
||||
value: 3
|
||||
enum/GCMPH:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Init phase
|
||||
description: Init phase
|
||||
value: 0
|
||||
- name: Header phase
|
||||
description: Header phase
|
||||
value: 1
|
||||
- name: Payload phase
|
||||
description: Payload phase
|
||||
value: 2
|
||||
- name: Final phase
|
||||
description: Final phase
|
||||
value: 3
|
||||
enum/MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Mode1
|
||||
description: Encryption
|
||||
value: 0
|
||||
- name: Mode2
|
||||
description: Key derivation (or key preparation for ECB/CBC decryption)
|
||||
value: 1
|
||||
- name: Mode3
|
||||
description: Decryption
|
||||
value: 2
|
||||
- name: Mode4
|
||||
description: Key derivation then single decryption
|
||||
value: 3
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/AFIO:
|
||||
description: Alternate function I/O
|
||||
items:
|
||||
|
||||
@ -1,6 +1,5 @@
|
||||
---
|
||||
block/CH:
|
||||
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
|
||||
description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
|
||||
items:
|
||||
- name: CR
|
||||
description: DMA channel configuration register (DMA_CCR)
|
||||
@ -30,7 +29,7 @@ block/DMA:
|
||||
access: Write
|
||||
fieldset: ISR
|
||||
- name: CH
|
||||
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
|
||||
description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
|
||||
array:
|
||||
len: 8
|
||||
stride: 20
|
||||
|
||||
@ -1,6 +1,5 @@
|
||||
---
|
||||
block/CH:
|
||||
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
|
||||
description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
|
||||
items:
|
||||
- name: CR
|
||||
description: DMA channel configuration register (DMA_CCR)
|
||||
@ -30,7 +29,7 @@ block/DMA:
|
||||
access: Write
|
||||
fieldset: ISR
|
||||
- name: CH
|
||||
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
|
||||
description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
|
||||
array:
|
||||
len: 8
|
||||
stride: 20
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/BKP:
|
||||
description: Backup registers
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/CAN:
|
||||
description: Controller area network
|
||||
items:
|
||||
@ -643,10 +642,10 @@ enum/FMPIE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: "No interrupt generated when state of FMP[1:0] bits are not 00b"
|
||||
description: No interrupt generated when state of FMP[1:0] bits are not 00b
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "Interrupt generated when state of FMP[1:0] bits are not 00b"
|
||||
description: Interrupt generated when state of FMP[1:0] bits are not 00b
|
||||
value: 1
|
||||
enum/FOVIE:
|
||||
bit_size: 1
|
||||
@ -697,10 +696,10 @@ enum/LECIE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: "ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection"
|
||||
description: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection"
|
||||
description: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection
|
||||
value: 1
|
||||
enum/RIR_IDE:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FDCAN:
|
||||
description: FDCAN
|
||||
items:
|
||||
@ -13,15 +12,15 @@ block/FDCAN:
|
||||
access: Read
|
||||
fieldset: ENDN
|
||||
- name: DBTP
|
||||
description: "This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point."
|
||||
description: This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.
|
||||
byte_offset: 12
|
||||
fieldset: DBTP
|
||||
- name: TEST
|
||||
description: "Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus."
|
||||
description: Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus.
|
||||
byte_offset: 16
|
||||
fieldset: TEST
|
||||
- name: RWD
|
||||
description: "The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock."
|
||||
description: The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock.
|
||||
byte_offset: 20
|
||||
fieldset: RWD
|
||||
- name: CCCR
|
||||
@ -70,7 +69,7 @@ block/FDCAN:
|
||||
byte_offset: 84
|
||||
fieldset: IE
|
||||
- name: ILS
|
||||
description: "The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]."
|
||||
description: The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1].
|
||||
byte_offset: 88
|
||||
fieldset: ILS
|
||||
- name: ILE
|
||||
@ -78,7 +77,7 @@ block/FDCAN:
|
||||
byte_offset: 92
|
||||
fieldset: ILE
|
||||
- name: RXGFC
|
||||
description: "Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path."
|
||||
description: 'Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path.'
|
||||
byte_offset: 128
|
||||
fieldset: RXGFC
|
||||
- name: XIDAM
|
||||
@ -92,21 +91,21 @@ block/FDCAN:
|
||||
fieldset: HPMS
|
||||
- name: RXFS
|
||||
description: FDCAN Rx FIFO X Status Register
|
||||
byte_offset: 144
|
||||
fieldset: RXFS
|
||||
access: Read
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 8
|
||||
byte_offset: 144
|
||||
access: Read
|
||||
fieldset: RXFS
|
||||
- name: RXFA
|
||||
description: CAN Rx FIFO 0 Acknowledge Register
|
||||
byte_offset: 148
|
||||
fieldset: RXFA
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 8
|
||||
byte_offset: 148
|
||||
fieldset: RXFA
|
||||
- name: TXBC
|
||||
description: FDCAN Tx Buffer Configuration Register
|
||||
byte_offset: 192
|
||||
@ -254,7 +253,7 @@ fieldset/CREL:
|
||||
bit_offset: 28
|
||||
bit_size: 4
|
||||
fieldset/DBTP:
|
||||
description: "This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point."
|
||||
description: This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.
|
||||
fields:
|
||||
- name: DSJW
|
||||
description: DSJW
|
||||
@ -348,7 +347,6 @@ fieldset/IE:
|
||||
offsets:
|
||||
- 0
|
||||
- 3
|
||||
|
||||
- name: HPME
|
||||
description: High-priority message enable
|
||||
bit_offset: 6
|
||||
@ -433,7 +431,7 @@ fieldset/ILE:
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
fieldset/ILS:
|
||||
description: "The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]."
|
||||
description: The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1].
|
||||
fields:
|
||||
- name: RXFIFO
|
||||
description: RX FIFO bit grouping the following interruption
|
||||
@ -628,7 +626,7 @@ fieldset/PSR:
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
fieldset/RWD:
|
||||
description: "The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock."
|
||||
description: The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock.
|
||||
fields:
|
||||
- name: WDC
|
||||
description: WDC
|
||||
@ -669,7 +667,7 @@ fieldset/RXFS:
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
fieldset/RXGFC:
|
||||
description: "Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path."
|
||||
description: 'Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path.'
|
||||
fields:
|
||||
- name: RRFE
|
||||
description: RRFE
|
||||
@ -715,7 +713,7 @@ fieldset/TDCR:
|
||||
bit_offset: 8
|
||||
bit_size: 7
|
||||
fieldset/TEST:
|
||||
description: "Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus."
|
||||
description: Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus.
|
||||
fields:
|
||||
- name: LBCK
|
||||
description: LBCK
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/CRC:
|
||||
description: Cyclic Redundancy Check calculation unit
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/CRC:
|
||||
description: Cyclic Redundancy Check calculation unit
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/CRC:
|
||||
description: Cyclic Redundancy Check calculation unit
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/CRS:
|
||||
description: Clock recovery system
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DAC:
|
||||
description: Digital-to-analog converter
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DAC:
|
||||
description: Digital-to-analog converter
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DAC:
|
||||
description: Digital-to-analog converter
|
||||
items:
|
||||
@ -330,7 +329,6 @@ enum/TSEL1:
|
||||
- name: LPTIM3_OUT
|
||||
description: Low-power timer 3 OUT event
|
||||
value: 14
|
||||
|
||||
enum/TSEL2:
|
||||
bit_size: 4
|
||||
variants:
|
||||
@ -379,7 +377,6 @@ enum/TSEL2:
|
||||
- name: LPTIM3_OUT
|
||||
description: Low-power timer 3 OUT event
|
||||
value: 14
|
||||
|
||||
enum/WAVE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: MCU debug component
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: MCU debug component
|
||||
items:
|
||||
@ -285,32 +284,32 @@ fieldset/CIDR0:
|
||||
description: Debug MCU CoreSight component identity register 0
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: "component identification bits [7:0]"
|
||||
description: component identification bits [7:0]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/CIDR1:
|
||||
description: Debug MCU CoreSight component identity register 1
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: "component identification bits [11:8]"
|
||||
description: component identification bits [11:8]
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: CLASS
|
||||
description: "component identification bits [15:12] - component class"
|
||||
description: component identification bits [15:12] - component class
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/CIDR2:
|
||||
description: Debug MCU CoreSight component identity register 2
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: "component identification bits [23:16]"
|
||||
description: component identification bits [23:16]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/CIDR3:
|
||||
description: Debug MCU CoreSight component identity register 3
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: "component identification bits [31:24]"
|
||||
description: component identification bits [31:24]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/CR:
|
||||
@ -376,25 +375,25 @@ fieldset/PIDR0:
|
||||
description: Debug MCU CoreSight peripheral identity register 0
|
||||
fields:
|
||||
- name: PARTNUM
|
||||
description: "part number bits [7:0]"
|
||||
description: part number bits [7:0]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/PIDR1:
|
||||
description: Debug MCU CoreSight peripheral identity register 1
|
||||
fields:
|
||||
- name: PARTNUM
|
||||
description: "part number bits [11:8]"
|
||||
description: part number bits [11:8]
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: JEP106ID
|
||||
description: "JEP106 identity code bits [3:0]"
|
||||
description: JEP106 identity code bits [3:0]
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/PIDR2:
|
||||
description: Debug MCU CoreSight peripheral identity register 2
|
||||
fields:
|
||||
- name: JEP106ID
|
||||
description: "JEP106 identity code bits [6:4]"
|
||||
description: JEP106 identity code bits [6:4]
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
- name: JEDEC
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
339
data/registers/dbgmcu_wba.yaml
Normal file
339
data/registers/dbgmcu_wba.yaml
Normal file
@ -0,0 +1,339 @@
|
||||
block/DBGMCU:
|
||||
description: Microcontroller debug unit
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: identity code register
|
||||
byte_offset: 0
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: status and configuration register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1LFZR
|
||||
description: APB1L peripheral freeze register
|
||||
byte_offset: 8
|
||||
fieldset: APB1LFZR
|
||||
- name: APB1HFZR
|
||||
description: APB1H peripheral freeze register
|
||||
byte_offset: 12
|
||||
fieldset: APB1HFZR
|
||||
- name: APB2FZR
|
||||
description: APB2 peripheral freeze register
|
||||
byte_offset: 16
|
||||
fieldset: APB2FZR
|
||||
- name: APB7FZR
|
||||
description: APB7 peripheral freeze register
|
||||
byte_offset: 36
|
||||
fieldset: APB7FZR
|
||||
- name: AHB1FZR
|
||||
description: AHB1 peripheral freeze register
|
||||
byte_offset: 40
|
||||
fieldset: AHB1FZR
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 252
|
||||
fieldset: SR
|
||||
- name: DBG_AUTH_HOST
|
||||
description: debug host authentication register
|
||||
byte_offset: 256
|
||||
fieldset: DBG_AUTH_HOST
|
||||
- name: DBG_AUTH_DEVICE
|
||||
description: debug device authentication register
|
||||
byte_offset: 260
|
||||
fieldset: DBG_AUTH_DEVICE
|
||||
- name: PNCR
|
||||
description: part number codification register
|
||||
byte_offset: 2012
|
||||
fieldset: PNCR
|
||||
- name: PIDR4
|
||||
description: CoreSight peripheral identity register 4
|
||||
byte_offset: 4048
|
||||
fieldset: PIDR4
|
||||
- name: PIDR0
|
||||
description: CoreSight peripheral identity register 0
|
||||
byte_offset: 4064
|
||||
fieldset: PIDR0
|
||||
- name: PIDR1
|
||||
description: CoreSight peripheral identity register 1
|
||||
byte_offset: 4068
|
||||
fieldset: PIDR1
|
||||
- name: PIDR2
|
||||
description: CoreSight peripheral identity register 2
|
||||
byte_offset: 4072
|
||||
fieldset: PIDR2
|
||||
- name: PIDR3
|
||||
description: CoreSight peripheral identity register 3
|
||||
byte_offset: 4076
|
||||
fieldset: PIDR3
|
||||
- name: CIDR0
|
||||
description: CoreSight component identity register 0
|
||||
byte_offset: 4080
|
||||
fieldset: CIDR0
|
||||
- name: CIDR1
|
||||
description: CoreSight peripheral identity register 1
|
||||
byte_offset: 4084
|
||||
fieldset: CIDR1
|
||||
- name: CIDR2
|
||||
description: CoreSight component identity register 2
|
||||
byte_offset: 4088
|
||||
fieldset: CIDR2
|
||||
- name: CIDR3
|
||||
description: CoreSight component identity register 3
|
||||
byte_offset: 4092
|
||||
fieldset: CIDR3
|
||||
fieldset/AHB1FZR:
|
||||
description: AHB1 peripheral freeze register
|
||||
fields:
|
||||
- name: DBG_GPDMA1_CH0_STOP
|
||||
description: "GPDMA 1 channel 0 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC0."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA1_CH1_STOP
|
||||
description: "GPDMA 1 channel 1 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC1."
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA1_CH2_STOP
|
||||
description: "GPDMA 1 channel 2 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC2."
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA1_CH3_STOP
|
||||
description: "GPDMA 1 channel 3 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC3."
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA1_CH4_STOP
|
||||
description: "GPDMA 1 channel 4 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC4."
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA1_CH5_STOP
|
||||
description: "GPDMA 1 channel 5 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC5."
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA1_CH6_STOP
|
||||
description: "GPDMA 1 channel 6 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC6."
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: DBG_GPDMA1_CH7_STOP
|
||||
description: "GPDMA 1 channel 7 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC7."
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
fieldset/APB1HFZR:
|
||||
description: APB1H peripheral freeze register
|
||||
fields:
|
||||
- name: DBG_LPTIM2_STOP
|
||||
description: "LPTIM2 stop in CPU debug\r Write access can be protected by GTZC_TZSC.LPTIM2SEC."
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/APB1LFZR:
|
||||
description: APB1L peripheral freeze register
|
||||
fields:
|
||||
- name: DBG_TIM2_STOP
|
||||
description: "TIM2 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM2SEC."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_TIM3_STOP
|
||||
description: "TIM3 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM3SEC."
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_WWDG_STOP
|
||||
description: "WWDG stop in CPU debug\r Write access can be protected by GTZC_TZSC.WWDGSEC"
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DBG_IWDG_STOP
|
||||
description: "IWDG stop in CPU debug\r Write access can be protected by GTZC_TZSC.IWDGSEC."
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DBG_I2C1_STOP
|
||||
description: "I2C1 SMBUS timeout stop in CPU debug\r Write access can be protected by GTZC_TZSC.I2C1SEC."
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: APB2 peripheral freeze register
|
||||
fields:
|
||||
- name: DBG_TIM1_STOP
|
||||
description: "TIM1 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM1SEC."
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DBG_TIM16_STOP
|
||||
description: "TIM16 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM16SEC."
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: DBG_TIM17_STOP
|
||||
description: "TIM17 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM17SEC."
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/APB7FZR:
|
||||
description: APB7 peripheral freeze register
|
||||
fields:
|
||||
- name: DBG_I2C3_STOP
|
||||
description: "I2C3 stop in CPU debug\r Access can be protected by GTZC_TZSC.I2C3SEC."
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DBG_LPTIM1_STOP
|
||||
description: "LPTIM1 stop in CPU debug\r Access can be protected by GTZC_TZSC.LPTIM1SEC."
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: DBG_RTC_STOP
|
||||
description: "RTC stop in CPU debug\r Access can be protected by GTZC_TZSC.TIM17SEC.\r Can only be accessed secure when one or more features in the RTC or TAMP is/are secure."
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
fieldset/CIDR0:
|
||||
description: CoreSight component identity register 0
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: Component ID bits [7:0]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/CIDR1:
|
||||
description: CoreSight peripheral identity register 1
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: Component ID bits [11:8]
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: CLASS
|
||||
description: Component ID bits [15:12] - component class
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/CIDR2:
|
||||
description: CoreSight component identity register 2
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: Component ID bits [23:16]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/CIDR3:
|
||||
description: CoreSight component identity register 3
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: Component ID bits [31:24]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/CR:
|
||||
description: status and configuration register
|
||||
fields:
|
||||
- name: DBG_STOP
|
||||
description: "Allows debug in Stop mode\r Write access can be protected by PWR_SECCFGR.LPMSEC.\r The CPU debug and clocks remain active and the HSI16 oscillators is used as system clock during Stop debug mode, allowing CPU debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state."
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: "Allows debug in Standby mode\r Write access can be protected by PWR_SECCFGR.LPMSEC.\r The CPU debug and clocks remain active and the HSI16 oscillator is used as system clock, the supply and SRAM memory content is maintained during Standby debug mode, allowing CPU debug capability. On exit from Standby mode, a standby reset is performed."
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: LPMS
|
||||
description: "Device low power mode selected\r 10x: Standby mode\r others reserved"
|
||||
bit_offset: 16
|
||||
bit_size: 3
|
||||
- name: STOPF
|
||||
description: Device Stop flag
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: SBF
|
||||
description: Device Standby flag
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: CS
|
||||
description: CPU Sleep
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: CDS
|
||||
description: CPU DeepSleep
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
fieldset/DBG_AUTH_DEVICE:
|
||||
description: debug device authentication register
|
||||
fields:
|
||||
- name: AUTH_ID
|
||||
description: "Device specific ID\r Device specific ID used for RDP regression."
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/DBG_AUTH_HOST:
|
||||
description: debug host authentication register
|
||||
fields:
|
||||
- name: AUTH_KEY
|
||||
description: "Device authentication key\r The device specific 64-bit authentication key (OEMn key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory."
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/IDCODE:
|
||||
description: identity code register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision ID
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/PIDR0:
|
||||
description: CoreSight peripheral identity register 0
|
||||
fields:
|
||||
- name: PARTNUM
|
||||
description: Part number bits [7:0]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/PIDR1:
|
||||
description: CoreSight peripheral identity register 1
|
||||
fields:
|
||||
- name: PARTNUM
|
||||
description: Part number bits [11:8]
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: JEP106ID
|
||||
description: JEP106 identity code bits [3:0]
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/PIDR2:
|
||||
description: CoreSight peripheral identity register 2
|
||||
fields:
|
||||
- name: JEP106ID
|
||||
description: JEP106 identity code bits [6:4]
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
- name: JEDEC
|
||||
description: JEDEC assigned value
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: REVISION
|
||||
description: Component revision number
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/PIDR3:
|
||||
description: CoreSight peripheral identity register 3
|
||||
fields:
|
||||
- name: CMOD
|
||||
description: Customer modified
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: REVAND
|
||||
description: Metal fix version
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/PIDR4:
|
||||
description: CoreSight peripheral identity register 4
|
||||
fields:
|
||||
- name: JEP106CON
|
||||
description: JEP106 continuation code
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: F4KCOUNT
|
||||
description: Register file size
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/PNCR:
|
||||
description: part number codification register
|
||||
fields:
|
||||
- name: CODIFICATION
|
||||
description: Part number codification
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: status register
|
||||
fields:
|
||||
- name: AP_PRESENT
|
||||
description: "Bit n identifies whether access port APn is present in device \r Bit n<>=<3D>0: APn absent \r Bit n<>=<3D>1: APn present"
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: AP_ENABLED
|
||||
description: "Bit n identifies whether access port APn is open (can be accessed via the debug port) or locked (debug access to the APn is blocked, except for access) \r Bit n<>=<3D>0: APn locked (except for access to DBGMCU)\r Bit n<>=<3D>1: APn enabled"
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Microcontroller Debug Unit
|
||||
items:
|
||||
@ -16,7 +15,7 @@ block/DBGMCU:
|
||||
byte_offset: 60
|
||||
fieldset: APB1FZR1
|
||||
- name: C2APB1FZR1
|
||||
description: "CPU2 APB1 Peripheral Freeze Register 1 [dual core device"
|
||||
description: CPU2 APB1 Peripheral Freeze Register 1 [dual core device
|
||||
byte_offset: 64
|
||||
fieldset: C2APB1FZR1
|
||||
- name: APB1FZR2
|
||||
@ -24,7 +23,7 @@ block/DBGMCU:
|
||||
byte_offset: 68
|
||||
fieldset: APB1FZR2
|
||||
- name: C2APB1FZR2
|
||||
description: "CPU2 APB1 Peripheral Freeze Register 2 [dual core device"
|
||||
description: CPU2 APB1 Peripheral Freeze Register 2 [dual core device
|
||||
byte_offset: 72
|
||||
fieldset: C2APB1FZR2
|
||||
- name: APB2FZR
|
||||
@ -32,7 +31,7 @@ block/DBGMCU:
|
||||
byte_offset: 76
|
||||
fieldset: APB2FZR
|
||||
- name: C2APB2FZR
|
||||
description: "CPU2 APB2 Peripheral Freeze Register [dual core device"
|
||||
description: CPU2 APB2 Peripheral Freeze Register [dual core device
|
||||
byte_offset: 80
|
||||
fieldset: C2APB2FZR
|
||||
fieldset/APB1FZR1:
|
||||
@ -97,7 +96,7 @@ fieldset/APB2FZR:
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/C2APB1FZR1:
|
||||
description: "CPU2 APB1 Peripheral Freeze Register 1 [dual core device"
|
||||
description: CPU2 APB1 Peripheral Freeze Register 1 [dual core device
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: TIM2
|
||||
@ -128,7 +127,7 @@ fieldset/C2APB1FZR1:
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/C2APB1FZR2:
|
||||
description: "CPU2 APB1 Peripheral Freeze Register 2 [dual core device"
|
||||
description: CPU2 APB1 Peripheral Freeze Register 2 [dual core device
|
||||
fields:
|
||||
- name: LPTIM2
|
||||
description: LPTIM2
|
||||
@ -139,7 +138,7 @@ fieldset/C2APB1FZR2:
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/C2APB2FZR:
|
||||
description: "CPU2 APB2 Peripheral Freeze Register [dual core device"
|
||||
description: CPU2 APB2 Peripheral Freeze Register [dual core device
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DCMI:
|
||||
description: Digital camera interface
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DMA2D:
|
||||
description: DMA2D controller
|
||||
items:
|
||||
@ -460,10 +459,10 @@ enum/BGPFCCR_AM:
|
||||
description: No modification of alpha channel
|
||||
value: 0
|
||||
- name: Replace
|
||||
description: "Replace with value in ALPHA[7:0]"
|
||||
description: Replace with value in ALPHA[7:0]
|
||||
value: 1
|
||||
- name: Multiply
|
||||
description: "Multiply with value in ALPHA[7:0]"
|
||||
description: Multiply with value in ALPHA[7:0]
|
||||
value: 2
|
||||
enum/BGPFCCR_CCM:
|
||||
bit_size: 1
|
||||
@ -601,10 +600,10 @@ enum/FGPFCCR_AM:
|
||||
description: No modification of alpha channel
|
||||
value: 0
|
||||
- name: Replace
|
||||
description: "Replace with value in ALPHA[7:0]"
|
||||
description: Replace with value in ALPHA[7:0]
|
||||
value: 1
|
||||
- name: Multiply
|
||||
description: "Multiply with value in ALPHA[7:0]"
|
||||
description: Multiply with value in ALPHA[7:0]
|
||||
value: 2
|
||||
enum/FGPFCCR_CCM:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DMA2D:
|
||||
description: DMA2D
|
||||
items:
|
||||
@ -99,77 +98,77 @@ fieldset/BGCMAR:
|
||||
description: DMA2D background CLUT memory address register
|
||||
fields:
|
||||
- name: MA
|
||||
description: "Memory address Address of the data used for the CLUT address dedicated to the background image. This register can only be written when no transfer is on going. Once the CLUT transfer has started, this register is read-only. If the background CLUT format is 32-bit, the address must be 32-bit aligned."
|
||||
description: Memory address Address of the data used for the CLUT address dedicated to the background image. This register can only be written when no transfer is on going. Once the CLUT transfer has started, this register is read-only. If the background CLUT format is 32-bit, the address must be 32-bit aligned.
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/BGCOLR:
|
||||
description: DMA2D background color register
|
||||
fields:
|
||||
- name: BLUE
|
||||
description: "Blue Value These bits define the blue value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Blue Value These bits define the blue value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: GREEN
|
||||
description: "Green Value These bits define the green value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Green Value These bits define the green value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: RED
|
||||
description: "Red Value These bits define the red value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Red Value These bits define the red value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
fieldset/BGMAR:
|
||||
description: DMA2D background memory address register
|
||||
fields:
|
||||
- name: MA
|
||||
description: "Memory address Address of the data used for the background image. This register can only be written when data transfers are disabled. Once a data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned."
|
||||
description: Memory address Address of the data used for the background image. This register can only be written when data transfers are disabled. Once a data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned.
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/BGOR:
|
||||
description: DMA2D background offset register
|
||||
fields:
|
||||
- name: LO
|
||||
description: "Line offset Line offset used for the background image (expressed in pixel). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even."
|
||||
description: Line offset Line offset used for the background image (expressed in pixel). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even.
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/BGPFCCR:
|
||||
description: DMA2D background PFC control register
|
||||
fields:
|
||||
- name: CM
|
||||
description: "Color mode These bits define the color format of the foreground image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless"
|
||||
description: 'Color mode These bits define the color format of the foreground image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless'
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
enum: BGPFCCR_CM
|
||||
- name: CCM
|
||||
description: "CLUT Color mode These bits define the color format of the CLUT. This register can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only."
|
||||
description: CLUT Color mode These bits define the color format of the CLUT. This register can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only.
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: BGPFCCR_CCM
|
||||
- name: START
|
||||
description: "Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already on going (data transfer or automatic BackGround CLUT transfer)."
|
||||
description: 'Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already on going (data transfer or automatic BackGround CLUT transfer).'
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: BGPFCCR_START
|
||||
- name: CS
|
||||
description: "CLUT size These bits define the size of the CLUT used for the BG. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1."
|
||||
description: CLUT size These bits define the size of the CLUT used for the BG. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1.
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: AM
|
||||
description: "Alpha mode These bits define which alpha channel value to be used for the background image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless"
|
||||
description: 'Alpha mode These bits define which alpha channel value to be used for the background image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless'
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: BGPFCCR_AM
|
||||
- name: AI
|
||||
description: "Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only."
|
||||
description: Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only.
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
enum: BGPFCCR_AI
|
||||
- name: RBS
|
||||
description: "Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only."
|
||||
description: Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only.
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
enum: BGPFCCR_RBS
|
||||
- name: ALPHA
|
||||
description: "Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: 'Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.'
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
fieldset/CR:
|
||||
@ -229,81 +228,81 @@ fieldset/FGCMAR:
|
||||
description: DMA2D foreground CLUT memory address register
|
||||
fields:
|
||||
- name: MA
|
||||
description: "Memory Address Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only. If the foreground CLUT format is 32-bit, the address must be 32-bit aligned."
|
||||
description: Memory Address Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only. If the foreground CLUT format is 32-bit, the address must be 32-bit aligned.
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/FGCOLR:
|
||||
description: DMA2D foreground color register
|
||||
fields:
|
||||
- name: BLUE
|
||||
description: "Blue Value These bits defines the blue value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only."
|
||||
description: Blue Value These bits defines the blue value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only.
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: GREEN
|
||||
description: "Green Value These bits defines the green value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only."
|
||||
description: Green Value These bits defines the green value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only.
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: RED
|
||||
description: "Red Value These bits defines the red value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Red Value These bits defines the red value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
fieldset/FGMAR:
|
||||
description: DMA2D foreground memory address register
|
||||
fields:
|
||||
- name: MA
|
||||
description: "Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned."
|
||||
description: Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned.
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/FGOR:
|
||||
description: DMA2D foreground offset register
|
||||
fields:
|
||||
- name: LO
|
||||
description: "Line offset Line offset used for the foreground expressed in pixel. This value is used to generate the address. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once a data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even."
|
||||
description: Line offset Line offset used for the foreground expressed in pixel. This value is used to generate the address. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once a data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even.
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/FGPFCCR:
|
||||
description: DMA2D foreground PFC control register
|
||||
fields:
|
||||
- name: CM
|
||||
description: "Color mode These bits defines the color format of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless"
|
||||
description: 'Color mode These bits defines the color format of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless'
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
enum: FGPFCCR_CM
|
||||
- name: CCM
|
||||
description: "CLUT color mode This bit defines the color format of the CLUT. It can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only."
|
||||
description: CLUT color mode This bit defines the color format of the CLUT. It can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only.
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: FGPFCCR_CCM
|
||||
- name: START
|
||||
description: "Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already ongoing (data transfer or automatic background CLUT transfer)."
|
||||
description: 'Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already ongoing (data transfer or automatic background CLUT transfer).'
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: FGPFCCR_START
|
||||
- name: CS
|
||||
description: "CLUT size These bits define the size of the CLUT used for the foreground image. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1."
|
||||
description: CLUT size These bits define the size of the CLUT used for the foreground image. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1.
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: AM
|
||||
description: "Alpha mode These bits select the alpha channel value to be used for the foreground image. They can only be written data the transfer are disabled. Once the transfer has started, they become read-only. other configurations are meaningless"
|
||||
description: Alpha mode These bits select the alpha channel value to be used for the foreground image. They can only be written data the transfer are disabled. Once the transfer has started, they become read-only. other configurations are meaningless
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: FGPFCCR_AM
|
||||
- name: CSS
|
||||
description: "Chroma Sub-Sampling These bits define the chroma sub-sampling mode for YCbCr color mode. Once the transfer has started, these bits are read-only. others: meaningless"
|
||||
description: 'Chroma Sub-Sampling These bits define the chroma sub-sampling mode for YCbCr color mode. Once the transfer has started, these bits are read-only. others: meaningless'
|
||||
bit_offset: 18
|
||||
bit_size: 2
|
||||
- name: AI
|
||||
description: "Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only."
|
||||
description: Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only.
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
enum: FGPFCCR_AI
|
||||
- name: RBS
|
||||
description: "Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only."
|
||||
description: Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only.
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
enum: FGPFCCR_RBS
|
||||
- name: ALPHA
|
||||
description: "Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits. These bits can only be written when data transfers are disabled. Once a transfer has started, they become read-only."
|
||||
description: Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits. These bits can only be written when data transfers are disabled. Once a transfer has started, they become read-only.
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
fieldset/IFCR:
|
||||
@ -363,65 +362,65 @@ fieldset/ISR:
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: CEIF
|
||||
description: "Configuration error interrupt flag This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed."
|
||||
description: Configuration error interrupt flag This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed.
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/LWR:
|
||||
description: DMA2D line watermark register
|
||||
fields:
|
||||
- name: LW
|
||||
description: "Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/NLR:
|
||||
description: DMA2D number of line register
|
||||
fields:
|
||||
- name: NL
|
||||
description: "Number of lines Number of lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Number of lines Number of lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: PL
|
||||
description: "Pixel per lines Number of pixels per lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. If any of the input image format is 4-bit per pixel, pixel per lines must be even."
|
||||
description: Pixel per lines Number of pixels per lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. If any of the input image format is 4-bit per pixel, pixel per lines must be even.
|
||||
bit_offset: 16
|
||||
bit_size: 14
|
||||
fieldset/OCOLR:
|
||||
description: DMA2D output color register
|
||||
fields:
|
||||
- name: BLUE
|
||||
description: "Blue Value These bits define the blue value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Blue Value These bits define the blue value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: GREEN
|
||||
description: "Green Value These bits define the green value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Green Value These bits define the green value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: RED
|
||||
description: "Red Value These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Red Value These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: ALPHA
|
||||
description: "Alpha Channel Value These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Alpha Channel Value These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
fieldset/OMAR:
|
||||
description: DMA2D output memory address register
|
||||
fields:
|
||||
- name: MA
|
||||
description: "Memory Address Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned."
|
||||
description: Memory Address Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned.
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OOR:
|
||||
description: DMA2D output offset register
|
||||
fields:
|
||||
- name: LO
|
||||
description: "Line Offset Line offset used for the output (expressed in pixels). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Line Offset Line offset used for the output (expressed in pixels). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/OPFCCR:
|
||||
description: DMA2D output PFC control register
|
||||
fields:
|
||||
- name: CM
|
||||
description: "Color mode These bits define the color format of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless"
|
||||
description: 'Color mode These bits define the color format of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless'
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: OPFCCR_CM
|
||||
@ -431,12 +430,12 @@ fieldset/OPFCCR:
|
||||
bit_size: 1
|
||||
enum: SB
|
||||
- name: AI
|
||||
description: "Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only."
|
||||
description: Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only.
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
enum: OPFCCR_AI
|
||||
- name: RBS
|
||||
description: "Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only."
|
||||
description: Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only.
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
enum: OPFCCR_RBS
|
||||
@ -462,10 +461,10 @@ enum/BGPFCCR_AM:
|
||||
description: No modification of alpha channel
|
||||
value: 0
|
||||
- name: Replace
|
||||
description: "Replace with value in ALPHA[7:0]"
|
||||
description: Replace with value in ALPHA[7:0]
|
||||
value: 1
|
||||
- name: Multiply
|
||||
description: "Multiply with value in ALPHA[7:0]"
|
||||
description: Multiply with value in ALPHA[7:0]
|
||||
value: 2
|
||||
enum/BGPFCCR_CCM:
|
||||
bit_size: 1
|
||||
@ -621,10 +620,10 @@ enum/FGPFCCR_AM:
|
||||
description: No modification of alpha channel
|
||||
value: 0
|
||||
- name: Replace
|
||||
description: "Replace with value in ALPHA[7:0]"
|
||||
description: Replace with value in ALPHA[7:0]
|
||||
value: 1
|
||||
- name: Multiply
|
||||
description: "Multiply with value in ALPHA[7:0]"
|
||||
description: Multiply with value in ALPHA[7:0]
|
||||
value: 2
|
||||
enum/FGPFCCR_CCM:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DMA:
|
||||
description: DMA controller
|
||||
items:
|
||||
@ -19,14 +18,14 @@ block/DMA:
|
||||
access: Write
|
||||
fieldset: IXR
|
||||
- name: ST
|
||||
description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"
|
||||
description: 'Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers'
|
||||
array:
|
||||
len: 8
|
||||
stride: 24
|
||||
byte_offset: 16
|
||||
block: ST
|
||||
block/ST:
|
||||
description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"
|
||||
description: 'Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers'
|
||||
items:
|
||||
- name: CR
|
||||
description: stream x configuration register
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DMA:
|
||||
description: DMA controller
|
||||
items:
|
||||
@ -19,14 +18,14 @@ block/DMA:
|
||||
access: Write
|
||||
fieldset: IXR
|
||||
- name: ST
|
||||
description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"
|
||||
description: 'Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers'
|
||||
array:
|
||||
len: 8
|
||||
stride: 24
|
||||
byte_offset: 16
|
||||
block: ST
|
||||
block/ST:
|
||||
description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"
|
||||
description: 'Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers'
|
||||
items:
|
||||
- name: CR
|
||||
description: stream x configuration register
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DMAMUX:
|
||||
description: DMAMUX
|
||||
items:
|
||||
@ -56,12 +55,12 @@ fieldset/CCR:
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: SPOL
|
||||
description: "Synchronization event type selector Defines the synchronization event on the selected synchronization input:"
|
||||
description: 'Synchronization event type selector Defines the synchronization event on the selected synchronization input:'
|
||||
bit_offset: 17
|
||||
bit_size: 2
|
||||
enum: POL
|
||||
- name: NBREQ
|
||||
description: "Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset."
|
||||
description: 'Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.'
|
||||
bit_offset: 19
|
||||
bit_size: 5
|
||||
- name: SYNC_ID
|
||||
@ -99,14 +98,14 @@ fieldset/RGCR:
|
||||
bit_size: 2
|
||||
enum: POL
|
||||
- name: GNBREQ
|
||||
description: "Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset."
|
||||
description: 'Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.'
|
||||
bit_offset: 19
|
||||
bit_size: 5
|
||||
fieldset/RGSR:
|
||||
description: DMAMux - DMA request generator status register
|
||||
fields:
|
||||
- name: OF
|
||||
description: "Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register."
|
||||
description: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
@ -116,7 +115,7 @@ enum/POL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: NoEdge
|
||||
description: "No event, i.e. no synchronization nor detection"
|
||||
description: No event, i.e. no synchronization nor detection
|
||||
value: 0
|
||||
- name: RisingEdge
|
||||
description: Rising edge
|
||||
|
||||
@ -1,21 +1,20 @@
|
||||
---
|
||||
block/ETH:
|
||||
description: Ethernet Peripheral
|
||||
items:
|
||||
- name: ETHERNET_MAC
|
||||
description: "Ethernet: media access control (MAC)"
|
||||
description: 'Ethernet: media access control (MAC)'
|
||||
byte_offset: 0
|
||||
block: ETHERNET_MAC
|
||||
- name: ETHERNET_PTP
|
||||
description: "Ethernet: Precision Time Protocol (PTP)"
|
||||
description: 'Ethernet: Precision Time Protocol (PTP)'
|
||||
byte_offset: 1792
|
||||
block: ETHERNET_PTP
|
||||
- name: ETHERNET_DMA
|
||||
description: "Ethernet: DMA mode register (DMA)"
|
||||
description: 'Ethernet: DMA mode register (DMA)'
|
||||
byte_offset: 4096
|
||||
block: ETHERNET_DMA
|
||||
block/ETHERNET_DMA:
|
||||
description: "Ethernet: DMA controller operation"
|
||||
description: 'Ethernet: DMA controller operation'
|
||||
items:
|
||||
- name: DMABMR
|
||||
description: Ethernet DMA bus mode register
|
||||
@ -74,7 +73,7 @@ block/ETHERNET_DMA:
|
||||
access: Read
|
||||
fieldset: DMACHRBAR
|
||||
block/ETHERNET_MAC:
|
||||
description: "Ethernet: media access control (MAC)"
|
||||
description: 'Ethernet: media access control (MAC)'
|
||||
items:
|
||||
- name: MACCR
|
||||
description: Ethernet MAC configuration register
|
||||
@ -212,7 +211,7 @@ block/ETHERNET_MAC:
|
||||
access: Read
|
||||
fieldset: MMCRGUFCR
|
||||
block/ETHERNET_PTP:
|
||||
description: "Ethernet: Precision time protocol"
|
||||
description: 'Ethernet: Precision time protocol'
|
||||
items:
|
||||
- name: PTPTSCR
|
||||
description: Ethernet PTP time stamp control register
|
||||
@ -618,7 +617,7 @@ fieldset/MACA0LR:
|
||||
description: Ethernet MAC address 0 low register
|
||||
fields:
|
||||
- name: MACA0L
|
||||
description: "0"
|
||||
description: '0'
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/MACA1HR:
|
||||
@ -1332,7 +1331,7 @@ fieldset/PTPTTHR:
|
||||
description: Ethernet PTP target time high register
|
||||
fields:
|
||||
- name: TTSH
|
||||
description: "0"
|
||||
description: '0'
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PTPTTLR:
|
||||
@ -1373,16 +1372,16 @@ enum/BL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: BL10
|
||||
description: "For retransmission n, wait up to 2^min(n, 10) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 10) time slots
|
||||
value: 0
|
||||
- name: BL8
|
||||
description: "For retransmission n, wait up to 2^min(n, 8) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 8) time slots
|
||||
value: 1
|
||||
- name: BL4
|
||||
description: "For retransmission n, wait up to 2^min(n, 4) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 4) time slots
|
||||
value: 2
|
||||
- name: BL1
|
||||
description: "For retransmission n, wait up to 2^min(n, 1) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 1) time slots
|
||||
value: 3
|
||||
enum/CR:
|
||||
bit_size: 3
|
||||
@ -1430,7 +1429,7 @@ enum/DA:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: RoundRobin
|
||||
description: "Round-robin with Rx:Tx priority given by PM"
|
||||
description: Round-robin with Rx:Tx priority given by PM
|
||||
value: 0
|
||||
- name: RxPriority
|
||||
description: Rx has priority over Tx
|
||||
@ -1493,10 +1492,10 @@ enum/FCB:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: DisableBackPressure
|
||||
description: "In half duplex only, deasserts back pressure"
|
||||
description: In half duplex only, deasserts back pressure
|
||||
value: 0
|
||||
- name: PauseOrBackPressure
|
||||
description: "In full duplex, initiate a Pause control frame. In half duplex, assert back pressure"
|
||||
description: In full duplex, initiate a Pause control frame. In half duplex, assert back pressure
|
||||
value: 1
|
||||
enum/FEF:
|
||||
bit_size: 1
|
||||
@ -1562,10 +1561,10 @@ enum/HPF:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: HashOnly
|
||||
description: "If HM or HU is set, only frames that match the Hash filter are passed"
|
||||
description: If HM or HU is set, only frames that match the Hash filter are passed
|
||||
value: 0
|
||||
- name: HashOrPerfect
|
||||
description: "If HM or HU is set, frames that match either the perfect filter or the hash filter are passed"
|
||||
description: If HM or HU is set, frames that match either the perfect filter or the hash filter are passed
|
||||
value: 1
|
||||
enum/HU:
|
||||
bit_size: 1
|
||||
@ -1616,10 +1615,10 @@ enum/JD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enabled
|
||||
description: "Jabber enabled, transmit frames up to 2048 bytes"
|
||||
description: Jabber enabled, transmit frames up to 2048 bytes
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: "Jabber disabled, transmit frames up to 16384 bytes"
|
||||
description: Jabber disabled, transmit frames up to 16384 bytes
|
||||
value: 1
|
||||
enum/LM:
|
||||
bit_size: 1
|
||||
@ -1769,16 +1768,16 @@ enum/PriorityRxOverTx:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: OneToOne
|
||||
description: "RxDMA priority over TxDMA is 1:1"
|
||||
description: RxDMA priority over TxDMA is 1:1
|
||||
value: 0
|
||||
- name: TwoToOne
|
||||
description: "RxDMA priority over TxDMA is 2:1"
|
||||
description: RxDMA priority over TxDMA is 2:1
|
||||
value: 1
|
||||
- name: ThreeToOne
|
||||
description: "RxDMA priority over TxDMA is 3:1"
|
||||
description: RxDMA priority over TxDMA is 3:1
|
||||
value: 2
|
||||
- name: FourToOne
|
||||
description: "RxDMA priority over TxDMA is 4:1"
|
||||
description: RxDMA priority over TxDMA is 4:1
|
||||
value: 3
|
||||
enum/RA:
|
||||
bit_size: 1
|
||||
@ -1883,25 +1882,25 @@ enum/RPS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Stopped
|
||||
description: "Stopped, reset or Stop Receive command issued"
|
||||
description: Stopped, reset or Stop Receive command issued
|
||||
value: 0
|
||||
- name: RunningFetching
|
||||
description: "Running, fetching receive transfer descriptor"
|
||||
description: Running, fetching receive transfer descriptor
|
||||
value: 1
|
||||
- name: RunningWaiting
|
||||
description: "Running, waiting for receive packet"
|
||||
description: Running, waiting for receive packet
|
||||
value: 3
|
||||
- name: Suspended
|
||||
description: "Suspended, receive descriptor unavailable"
|
||||
description: Suspended, receive descriptor unavailable
|
||||
value: 4
|
||||
- name: RunningWriting
|
||||
description: "Running, writing data to host memory buffer"
|
||||
description: Running, writing data to host memory buffer
|
||||
value: 7
|
||||
enum/RSF:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: CutThrough
|
||||
description: "Rx FIFO operates in cut-through mode, subject to RTC bits"
|
||||
description: Rx FIFO operates in cut-through mode, subject to RTC bits
|
||||
value: 0
|
||||
- name: StoreForward
|
||||
description: Frames are read from Rx FIFO after complete frame has been written
|
||||
@ -1952,10 +1951,10 @@ enum/TFCE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: "In full duplex, flow control is disabled. In half duplex, back pressure is disabled"
|
||||
description: In full duplex, flow control is disabled. In half duplex, back pressure is disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "In full duplex, flow control is enabled. In half duplex, back pressure is enabled"
|
||||
description: In full duplex, flow control is enabled. In half duplex, back pressure is enabled
|
||||
value: 1
|
||||
enum/TGFM:
|
||||
bit_size: 1
|
||||
@ -1994,22 +1993,22 @@ enum/TPS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Stopped
|
||||
description: "Stopped, Reset or Stop Transmit command issued"
|
||||
description: Stopped, Reset or Stop Transmit command issued
|
||||
value: 0
|
||||
- name: RunningFetching
|
||||
description: "Running, fetching transmit transfer descriptor"
|
||||
description: Running, fetching transmit transfer descriptor
|
||||
value: 1
|
||||
- name: RunningWaiting
|
||||
description: "Running, waiting for status"
|
||||
description: Running, waiting for status
|
||||
value: 2
|
||||
- name: RunningReading
|
||||
description: "Running, reading data from host memory buffer"
|
||||
description: Running, reading data from host memory buffer
|
||||
value: 3
|
||||
- name: Suspended
|
||||
description: "Suspended, transmit descriptor unavailable or transmit buffer underflow"
|
||||
description: Suspended, transmit descriptor unavailable or transmit buffer underflow
|
||||
value: 6
|
||||
- name: Running
|
||||
description: "Running, closing transmit descriptor"
|
||||
description: Running, closing transmit descriptor
|
||||
value: 7
|
||||
enum/TSF:
|
||||
bit_size: 1
|
||||
@ -2063,7 +2062,7 @@ enum/UPFD:
|
||||
description: MAC detects only a Pause frame with the multicast address specified in the 802.3x standard
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "MAC additionally detects Pause frames with the station's unicast address"
|
||||
description: MAC additionally detects Pause frames with the station's unicast address
|
||||
value: 1
|
||||
enum/USP:
|
||||
bit_size: 1
|
||||
@ -2072,7 +2071,7 @@ enum/USP:
|
||||
description: PBL value used for both Rx and Tx DMA
|
||||
value: 0
|
||||
- name: Separate
|
||||
description: "RxDMA uses RDP value, TxDMA uses PBL value"
|
||||
description: RxDMA uses RDP value, TxDMA uses PBL value
|
||||
value: 1
|
||||
enum/VLANTC:
|
||||
bit_size: 1
|
||||
@ -2087,10 +2086,10 @@ enum/WD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enabled
|
||||
description: "Watchdog enabled, receive frames limited to 2048 bytes"
|
||||
description: Watchdog enabled, receive frames limited to 2048 bytes
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: "Watchdog disabled, receive frames may be up to to 16384 bytes"
|
||||
description: Watchdog disabled, receive frames may be up to to 16384 bytes
|
||||
value: 1
|
||||
enum/WFE:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,21 +1,20 @@
|
||||
---
|
||||
block/ETH:
|
||||
description: Ethernet Peripheral
|
||||
items:
|
||||
- name: ETHERNET_MAC
|
||||
description: "Ethernet: media access control (MAC)"
|
||||
description: 'Ethernet: media access control (MAC)'
|
||||
byte_offset: 0
|
||||
block: ETHERNET_MAC
|
||||
- name: ETHERNET_PTP
|
||||
description: "Ethernet: Precision Time Protocol (PTP)"
|
||||
description: 'Ethernet: Precision Time Protocol (PTP)'
|
||||
byte_offset: 1792
|
||||
block: ETHERNET_PTP
|
||||
- name: ETHERNET_DMA
|
||||
description: "Ethernet: DMA mode register (DMA)"
|
||||
description: 'Ethernet: DMA mode register (DMA)'
|
||||
byte_offset: 4096
|
||||
block: ETHERNET_DMA
|
||||
block/ETHERNET_DMA:
|
||||
description: "Ethernet: DMA controller operation"
|
||||
description: 'Ethernet: DMA controller operation'
|
||||
items:
|
||||
- name: DMABMR
|
||||
description: Ethernet DMA bus mode register
|
||||
@ -78,7 +77,7 @@ block/ETHERNET_DMA:
|
||||
access: Read
|
||||
fieldset: DMACHRBAR
|
||||
block/ETHERNET_MAC:
|
||||
description: "Ethernet: media access control (MAC)"
|
||||
description: 'Ethernet: media access control (MAC)'
|
||||
items:
|
||||
- name: MACCR
|
||||
description: Ethernet MAC configuration register
|
||||
@ -216,7 +215,7 @@ block/ETHERNET_MAC:
|
||||
access: Read
|
||||
fieldset: MMCRGUFCR
|
||||
block/ETHERNET_PTP:
|
||||
description: "Ethernet: Precision time protocol"
|
||||
description: 'Ethernet: Precision time protocol'
|
||||
items:
|
||||
- name: PTPTSCR
|
||||
description: Ethernet PTP time stamp control register
|
||||
@ -639,7 +638,7 @@ fieldset/MACA0LR:
|
||||
description: Ethernet MAC address 0 low register
|
||||
fields:
|
||||
- name: MACA0L
|
||||
description: "0"
|
||||
description: '0'
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/MACA1HR:
|
||||
@ -1368,7 +1367,7 @@ fieldset/PTPTTHR:
|
||||
description: Ethernet PTP target time high register
|
||||
fields:
|
||||
- name: TTSH
|
||||
description: "0"
|
||||
description: '0'
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PTPTTLR:
|
||||
@ -1409,16 +1408,16 @@ enum/BL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: BL10
|
||||
description: "For retransmission n, wait up to 2^min(n, 10) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 10) time slots
|
||||
value: 0
|
||||
- name: BL8
|
||||
description: "For retransmission n, wait up to 2^min(n, 8) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 8) time slots
|
||||
value: 1
|
||||
- name: BL4
|
||||
description: "For retransmission n, wait up to 2^min(n, 4) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 4) time slots
|
||||
value: 2
|
||||
- name: BL1
|
||||
description: "For retransmission n, wait up to 2^min(n, 1) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 1) time slots
|
||||
value: 3
|
||||
enum/CR:
|
||||
bit_size: 3
|
||||
@ -1475,7 +1474,7 @@ enum/DA:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: RoundRobin
|
||||
description: "Round-robin with Rx:Tx priority given by PM"
|
||||
description: Round-robin with Rx:Tx priority given by PM
|
||||
value: 0
|
||||
- name: RxPriority
|
||||
description: Rx has priority over Tx
|
||||
@ -1532,7 +1531,7 @@ enum/EDFE:
|
||||
description: Normal descriptor format
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "Enhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload"
|
||||
description: Enhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload
|
||||
value: 1
|
||||
enum/FB:
|
||||
bit_size: 1
|
||||
@ -1547,10 +1546,10 @@ enum/FCB:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: DisableBackPressure
|
||||
description: "In half duplex only, deasserts back pressure"
|
||||
description: In half duplex only, deasserts back pressure
|
||||
value: 0
|
||||
- name: PauseOrBackPressure
|
||||
description: "In full duplex, initiate a Pause control frame. In half duplex, assert back pressure"
|
||||
description: In full duplex, initiate a Pause control frame. In half duplex, assert back pressure
|
||||
value: 1
|
||||
enum/FEF:
|
||||
bit_size: 1
|
||||
@ -1616,10 +1615,10 @@ enum/HPF:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: HashOnly
|
||||
description: "If HM or HU is set, only frames that match the Hash filter are passed"
|
||||
description: If HM or HU is set, only frames that match the Hash filter are passed
|
||||
value: 0
|
||||
- name: HashOrPerfect
|
||||
description: "If HM or HU is set, frames that match either the perfect filter or the hash filter are passed"
|
||||
description: If HM or HU is set, frames that match either the perfect filter or the hash filter are passed
|
||||
value: 1
|
||||
enum/HU:
|
||||
bit_size: 1
|
||||
@ -1670,10 +1669,10 @@ enum/JD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enabled
|
||||
description: "Jabber enabled, transmit frames up to 2048 bytes"
|
||||
description: Jabber enabled, transmit frames up to 2048 bytes
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: "Jabber disabled, transmit frames up to 16384 bytes"
|
||||
description: Jabber disabled, transmit frames up to 16384 bytes
|
||||
value: 1
|
||||
enum/LM:
|
||||
bit_size: 1
|
||||
@ -1709,7 +1708,7 @@ enum/MB:
|
||||
description: Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below
|
||||
value: 0
|
||||
- name: Mixed
|
||||
description: "If FB is low, start all bursts greater than 16 with INCR (undefined burst)"
|
||||
description: If FB is low, start all bursts greater than 16 with INCR (undefined burst)
|
||||
value: 1
|
||||
enum/MB_progress:
|
||||
bit_size: 1
|
||||
@ -1730,10 +1729,10 @@ enum/MCFHP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: AlmostHalf
|
||||
description: "When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0"
|
||||
description: When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0
|
||||
value: 0
|
||||
- name: AlmostFull
|
||||
description: "When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0"
|
||||
description: When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0
|
||||
value: 1
|
||||
enum/MCP:
|
||||
bit_size: 1
|
||||
@ -1847,16 +1846,16 @@ enum/PriorityRxOverTx:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: OneToOne
|
||||
description: "RxDMA priority over TxDMA is 1:1"
|
||||
description: RxDMA priority over TxDMA is 1:1
|
||||
value: 0
|
||||
- name: TwoToOne
|
||||
description: "RxDMA priority over TxDMA is 2:1"
|
||||
description: RxDMA priority over TxDMA is 2:1
|
||||
value: 1
|
||||
- name: ThreeToOne
|
||||
description: "RxDMA priority over TxDMA is 3:1"
|
||||
description: RxDMA priority over TxDMA is 3:1
|
||||
value: 2
|
||||
- name: FourToOne
|
||||
description: "RxDMA priority over TxDMA is 4:1"
|
||||
description: RxDMA priority over TxDMA is 4:1
|
||||
value: 3
|
||||
enum/RA:
|
||||
bit_size: 1
|
||||
@ -1961,25 +1960,25 @@ enum/RPS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Stopped
|
||||
description: "Stopped, reset or Stop Receive command issued"
|
||||
description: Stopped, reset or Stop Receive command issued
|
||||
value: 0
|
||||
- name: RunningFetching
|
||||
description: "Running, fetching receive transfer descriptor"
|
||||
description: Running, fetching receive transfer descriptor
|
||||
value: 1
|
||||
- name: RunningWaiting
|
||||
description: "Running, waiting for receive packet"
|
||||
description: Running, waiting for receive packet
|
||||
value: 3
|
||||
- name: Suspended
|
||||
description: "Suspended, receive descriptor unavailable"
|
||||
description: Suspended, receive descriptor unavailable
|
||||
value: 4
|
||||
- name: RunningWriting
|
||||
description: "Running, writing data to host memory buffer"
|
||||
description: Running, writing data to host memory buffer
|
||||
value: 7
|
||||
enum/RSF:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: CutThrough
|
||||
description: "Rx FIFO operates in cut-through mode, subject to RTC bits"
|
||||
description: Rx FIFO operates in cut-through mode, subject to RTC bits
|
||||
value: 0
|
||||
- name: StoreForward
|
||||
description: Frames are read from Rx FIFO after complete frame has been written
|
||||
@ -2030,10 +2029,10 @@ enum/TFCE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: "In full duplex, flow control is disabled. In half duplex, back pressure is disabled"
|
||||
description: In full duplex, flow control is disabled. In half duplex, back pressure is disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "In full duplex, flow control is enabled. In half duplex, back pressure is enabled"
|
||||
description: In full duplex, flow control is enabled. In half duplex, back pressure is enabled
|
||||
value: 1
|
||||
enum/TGFM:
|
||||
bit_size: 1
|
||||
@ -2072,22 +2071,22 @@ enum/TPS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Stopped
|
||||
description: "Stopped, Reset or Stop Transmit command issued"
|
||||
description: Stopped, Reset or Stop Transmit command issued
|
||||
value: 0
|
||||
- name: RunningFetching
|
||||
description: "Running, fetching transmit transfer descriptor"
|
||||
description: Running, fetching transmit transfer descriptor
|
||||
value: 1
|
||||
- name: RunningWaiting
|
||||
description: "Running, waiting for status"
|
||||
description: Running, waiting for status
|
||||
value: 2
|
||||
- name: RunningReading
|
||||
description: "Running, reading data from host memory buffer"
|
||||
description: Running, reading data from host memory buffer
|
||||
value: 3
|
||||
- name: Suspended
|
||||
description: "Suspended, transmit descriptor unavailable or transmit buffer underflow"
|
||||
description: Suspended, transmit descriptor unavailable or transmit buffer underflow
|
||||
value: 6
|
||||
- name: Running
|
||||
description: "Running, closing transmit descriptor"
|
||||
description: Running, closing transmit descriptor
|
||||
value: 7
|
||||
enum/TSF:
|
||||
bit_size: 1
|
||||
@ -2141,7 +2140,7 @@ enum/UPFD:
|
||||
description: MAC detects only a Pause frame with the multicast address specified in the 802.3x standard
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "MAC additionally detects Pause frames with the station's unicast address"
|
||||
description: MAC additionally detects Pause frames with the station's unicast address
|
||||
value: 1
|
||||
enum/USP:
|
||||
bit_size: 1
|
||||
@ -2150,7 +2149,7 @@ enum/USP:
|
||||
description: PBL value used for both Rx and Tx DMA
|
||||
value: 0
|
||||
- name: Separate
|
||||
description: "RxDMA uses RDP value, TxDMA uses PBL value"
|
||||
description: RxDMA uses RDP value, TxDMA uses PBL value
|
||||
value: 1
|
||||
enum/VLANTC:
|
||||
bit_size: 1
|
||||
@ -2165,10 +2164,10 @@ enum/WD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enabled
|
||||
description: "Watchdog enabled, receive frames limited to 2048 bytes"
|
||||
description: Watchdog enabled, receive frames limited to 2048 bytes
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: "Watchdog disabled, receive frames may be up to to 16384 bytes"
|
||||
description: Watchdog disabled, receive frames may be up to to 16384 bytes
|
||||
value: 1
|
||||
enum/WFE:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,21 +1,20 @@
|
||||
---
|
||||
block/ETH:
|
||||
description: Ethernet Peripheral
|
||||
items:
|
||||
- name: ETHERNET_MAC
|
||||
description: "Ethernet: media access control (MAC)"
|
||||
description: 'Ethernet: media access control (MAC)'
|
||||
byte_offset: 0
|
||||
block: ETHERNET_MAC
|
||||
- name: ETHERNET_PTP
|
||||
description: "Ethernet: Precision Time Protocol (PTP)"
|
||||
description: 'Ethernet: Precision Time Protocol (PTP)'
|
||||
byte_offset: 1792
|
||||
block: ETHERNET_PTP
|
||||
- name: ETHERNET_DMA
|
||||
description: "Ethernet: DMA mode register (DMA)"
|
||||
description: 'Ethernet: DMA mode register (DMA)'
|
||||
byte_offset: 4096
|
||||
block: ETHERNET_DMA
|
||||
block/ETHERNET_DMA:
|
||||
description: "Ethernet: DMA controller operation"
|
||||
description: 'Ethernet: DMA controller operation'
|
||||
items:
|
||||
- name: DMABMR
|
||||
description: Ethernet DMA bus mode register
|
||||
@ -78,7 +77,7 @@ block/ETHERNET_DMA:
|
||||
access: Read
|
||||
fieldset: DMACHRBAR
|
||||
block/ETHERNET_MAC:
|
||||
description: "Ethernet: media access control (MAC)"
|
||||
description: 'Ethernet: media access control (MAC)'
|
||||
items:
|
||||
- name: MACCR
|
||||
description: Ethernet MAC configuration register
|
||||
@ -216,7 +215,7 @@ block/ETHERNET_MAC:
|
||||
access: Read
|
||||
fieldset: MMCRGUFCR
|
||||
block/ETHERNET_PTP:
|
||||
description: "Ethernet: Precision time protocol"
|
||||
description: 'Ethernet: Precision time protocol'
|
||||
items:
|
||||
- name: PTPTSCR
|
||||
description: Ethernet PTP time stamp control register
|
||||
@ -639,7 +638,7 @@ fieldset/MACA0LR:
|
||||
description: Ethernet MAC address 0 low register
|
||||
fields:
|
||||
- name: MACA0L
|
||||
description: "0"
|
||||
description: '0'
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/MACA1HR:
|
||||
@ -1368,7 +1367,7 @@ fieldset/PTPTTHR:
|
||||
description: Ethernet PTP target time high register
|
||||
fields:
|
||||
- name: TTSH
|
||||
description: "0"
|
||||
description: '0'
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PTPTTLR:
|
||||
@ -1409,16 +1408,16 @@ enum/BL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: BL10
|
||||
description: "For retransmission n, wait up to 2^min(n, 10) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 10) time slots
|
||||
value: 0
|
||||
- name: BL8
|
||||
description: "For retransmission n, wait up to 2^min(n, 8) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 8) time slots
|
||||
value: 1
|
||||
- name: BL4
|
||||
description: "For retransmission n, wait up to 2^min(n, 4) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 4) time slots
|
||||
value: 2
|
||||
- name: BL1
|
||||
description: "For retransmission n, wait up to 2^min(n, 1) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 1) time slots
|
||||
value: 3
|
||||
enum/CR:
|
||||
bit_size: 3
|
||||
@ -1475,7 +1474,7 @@ enum/DA:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: RoundRobin
|
||||
description: "Round-robin with Rx:Tx priority given by PM"
|
||||
description: Round-robin with Rx:Tx priority given by PM
|
||||
value: 0
|
||||
- name: RxPriority
|
||||
description: Rx has priority over Tx
|
||||
@ -1532,7 +1531,7 @@ enum/EDFE:
|
||||
description: Normal descriptor format
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "Enhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload"
|
||||
description: Enhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload
|
||||
value: 1
|
||||
enum/FB:
|
||||
bit_size: 1
|
||||
@ -1547,10 +1546,10 @@ enum/FCB:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: DisableBackPressure
|
||||
description: "In half duplex only, deasserts back pressure"
|
||||
description: In half duplex only, deasserts back pressure
|
||||
value: 0
|
||||
- name: PauseOrBackPressure
|
||||
description: "In full duplex, initiate a Pause control frame. In half duplex, assert back pressure"
|
||||
description: In full duplex, initiate a Pause control frame. In half duplex, assert back pressure
|
||||
value: 1
|
||||
enum/FEF:
|
||||
bit_size: 1
|
||||
@ -1616,10 +1615,10 @@ enum/HPF:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: HashOnly
|
||||
description: "If HM or HU is set, only frames that match the Hash filter are passed"
|
||||
description: If HM or HU is set, only frames that match the Hash filter are passed
|
||||
value: 0
|
||||
- name: HashOrPerfect
|
||||
description: "If HM or HU is set, frames that match either the perfect filter or the hash filter are passed"
|
||||
description: If HM or HU is set, frames that match either the perfect filter or the hash filter are passed
|
||||
value: 1
|
||||
enum/HU:
|
||||
bit_size: 1
|
||||
@ -1670,10 +1669,10 @@ enum/JD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enabled
|
||||
description: "Jabber enabled, transmit frames up to 2048 bytes"
|
||||
description: Jabber enabled, transmit frames up to 2048 bytes
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: "Jabber disabled, transmit frames up to 16384 bytes"
|
||||
description: Jabber disabled, transmit frames up to 16384 bytes
|
||||
value: 1
|
||||
enum/LM:
|
||||
bit_size: 1
|
||||
@ -1709,7 +1708,7 @@ enum/MB:
|
||||
description: Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below
|
||||
value: 0
|
||||
- name: Mixed
|
||||
description: "If FB is low, start all bursts greater than 16 with INCR (undefined burst)"
|
||||
description: If FB is low, start all bursts greater than 16 with INCR (undefined burst)
|
||||
value: 1
|
||||
enum/MB_progress:
|
||||
bit_size: 1
|
||||
@ -1730,10 +1729,10 @@ enum/MCFHP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: AlmostHalf
|
||||
description: "When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0"
|
||||
description: When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0
|
||||
value: 0
|
||||
- name: AlmostFull
|
||||
description: "When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0"
|
||||
description: When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0
|
||||
value: 1
|
||||
enum/MCP:
|
||||
bit_size: 1
|
||||
@ -1847,16 +1846,16 @@ enum/PriorityRxOverTx:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: OneToOne
|
||||
description: "RxDMA priority over TxDMA is 1:1"
|
||||
description: RxDMA priority over TxDMA is 1:1
|
||||
value: 0
|
||||
- name: TwoToOne
|
||||
description: "RxDMA priority over TxDMA is 2:1"
|
||||
description: RxDMA priority over TxDMA is 2:1
|
||||
value: 1
|
||||
- name: ThreeToOne
|
||||
description: "RxDMA priority over TxDMA is 3:1"
|
||||
description: RxDMA priority over TxDMA is 3:1
|
||||
value: 2
|
||||
- name: FourToOne
|
||||
description: "RxDMA priority over TxDMA is 4:1"
|
||||
description: RxDMA priority over TxDMA is 4:1
|
||||
value: 3
|
||||
enum/RA:
|
||||
bit_size: 1
|
||||
@ -1961,25 +1960,25 @@ enum/RPS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Stopped
|
||||
description: "Stopped, reset or Stop Receive command issued"
|
||||
description: Stopped, reset or Stop Receive command issued
|
||||
value: 0
|
||||
- name: RunningFetching
|
||||
description: "Running, fetching receive transfer descriptor"
|
||||
description: Running, fetching receive transfer descriptor
|
||||
value: 1
|
||||
- name: RunningWaiting
|
||||
description: "Running, waiting for receive packet"
|
||||
description: Running, waiting for receive packet
|
||||
value: 3
|
||||
- name: Suspended
|
||||
description: "Suspended, receive descriptor unavailable"
|
||||
description: Suspended, receive descriptor unavailable
|
||||
value: 4
|
||||
- name: RunningWriting
|
||||
description: "Running, writing data to host memory buffer"
|
||||
description: Running, writing data to host memory buffer
|
||||
value: 7
|
||||
enum/RSF:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: CutThrough
|
||||
description: "Rx FIFO operates in cut-through mode, subject to RTC bits"
|
||||
description: Rx FIFO operates in cut-through mode, subject to RTC bits
|
||||
value: 0
|
||||
- name: StoreForward
|
||||
description: Frames are read from Rx FIFO after complete frame has been written
|
||||
@ -2030,10 +2029,10 @@ enum/TFCE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: "In full duplex, flow control is disabled. In half duplex, back pressure is disabled"
|
||||
description: In full duplex, flow control is disabled. In half duplex, back pressure is disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "In full duplex, flow control is enabled. In half duplex, back pressure is enabled"
|
||||
description: In full duplex, flow control is enabled. In half duplex, back pressure is enabled
|
||||
value: 1
|
||||
enum/TGFM:
|
||||
bit_size: 1
|
||||
@ -2072,22 +2071,22 @@ enum/TPS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Stopped
|
||||
description: "Stopped, Reset or Stop Transmit command issued"
|
||||
description: Stopped, Reset or Stop Transmit command issued
|
||||
value: 0
|
||||
- name: RunningFetching
|
||||
description: "Running, fetching transmit transfer descriptor"
|
||||
description: Running, fetching transmit transfer descriptor
|
||||
value: 1
|
||||
- name: RunningWaiting
|
||||
description: "Running, waiting for status"
|
||||
description: Running, waiting for status
|
||||
value: 2
|
||||
- name: RunningReading
|
||||
description: "Running, reading data from host memory buffer"
|
||||
description: Running, reading data from host memory buffer
|
||||
value: 3
|
||||
- name: Suspended
|
||||
description: "Suspended, transmit descriptor unavailable or transmit buffer underflow"
|
||||
description: Suspended, transmit descriptor unavailable or transmit buffer underflow
|
||||
value: 6
|
||||
- name: Running
|
||||
description: "Running, closing transmit descriptor"
|
||||
description: Running, closing transmit descriptor
|
||||
value: 7
|
||||
enum/TSF:
|
||||
bit_size: 1
|
||||
@ -2141,7 +2140,7 @@ enum/UPFD:
|
||||
description: MAC detects only a Pause frame with the multicast address specified in the 802.3x standard
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "MAC additionally detects Pause frames with the station's unicast address"
|
||||
description: MAC additionally detects Pause frames with the station's unicast address
|
||||
value: 1
|
||||
enum/USP:
|
||||
bit_size: 1
|
||||
@ -2150,7 +2149,7 @@ enum/USP:
|
||||
description: PBL value used for both Rx and Tx DMA
|
||||
value: 0
|
||||
- name: Separate
|
||||
description: "RxDMA uses RDP value, TxDMA uses PBL value"
|
||||
description: RxDMA uses RDP value, TxDMA uses PBL value
|
||||
value: 1
|
||||
enum/VLANTC:
|
||||
bit_size: 1
|
||||
@ -2165,10 +2164,10 @@ enum/WD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enabled
|
||||
description: "Watchdog enabled, receive frames limited to 2048 bytes"
|
||||
description: Watchdog enabled, receive frames limited to 2048 bytes
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: "Watchdog disabled, receive frames may be up to to 16384 bytes"
|
||||
description: Watchdog disabled, receive frames may be up to to 16384 bytes
|
||||
value: 1
|
||||
enum/WFE:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,21 +1,20 @@
|
||||
---
|
||||
block/ETH:
|
||||
description: Ethernet Peripheral
|
||||
items:
|
||||
- name: ETHERNET_MAC
|
||||
description: "Ethernet: media access control (MAC)"
|
||||
description: 'Ethernet: media access control (MAC)'
|
||||
byte_offset: 0
|
||||
block: ETHERNET_MAC
|
||||
- name: ETHERNET_MTL
|
||||
description: "Ethernet: MTL mode register (MTL)"
|
||||
description: 'Ethernet: MTL mode register (MTL)'
|
||||
byte_offset: 3072
|
||||
block: ETHERNET_MTL
|
||||
- name: ETHERNET_DMA
|
||||
description: "Ethernet: DMA mode register (DMA)"
|
||||
description: 'Ethernet: DMA mode register (DMA)'
|
||||
byte_offset: 4096
|
||||
block: ETHERNET_DMA
|
||||
block/ETHERNET_DMA:
|
||||
description: "Ethernet: DMA mode register (DMA)"
|
||||
description: 'Ethernet: DMA mode register (DMA)'
|
||||
items:
|
||||
- name: DMAMR
|
||||
description: DMA mode register
|
||||
@ -109,7 +108,7 @@ block/ETHERNET_DMA:
|
||||
access: Read
|
||||
fieldset: DMACMFCR
|
||||
block/ETHERNET_MAC:
|
||||
description: "Ethernet: media access control (MAC)"
|
||||
description: 'Ethernet: media access control (MAC)'
|
||||
items:
|
||||
- name: MACCR
|
||||
description: Operating mode configuration register
|
||||
@ -497,7 +496,7 @@ block/ETHERNET_MAC:
|
||||
byte_offset: 3024
|
||||
fieldset: MACLMIR
|
||||
block/ETHERNET_MTL:
|
||||
description: "Ethernet: MTL mode register (MTL)"
|
||||
description: 'Ethernet: MTL mode register (MTL)'
|
||||
items:
|
||||
- name: MTLOMR
|
||||
description: Operating mode Register
|
||||
@ -882,7 +881,7 @@ fieldset/MACA0HR:
|
||||
description: Address 0 high register
|
||||
fields:
|
||||
- name: ADDRHI
|
||||
description: "MAC Address0[47:32]"
|
||||
description: MAC Address0[47:32]
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: AE
|
||||
@ -893,14 +892,14 @@ fieldset/MACA0LR:
|
||||
description: Address 0 low register
|
||||
fields:
|
||||
- name: ADDRLO
|
||||
description: "MAC Address 0 [31:0]"
|
||||
description: MAC Address 0 [31:0]
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/MACA1HR:
|
||||
description: Address 1 high register
|
||||
fields:
|
||||
- name: ADDRHI
|
||||
description: "MAC Address1 [47:32]"
|
||||
description: MAC Address1 [47:32]
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: MBC
|
||||
@ -919,14 +918,14 @@ fieldset/MACA1LR:
|
||||
description: Address 1 low register
|
||||
fields:
|
||||
- name: ADDRLO
|
||||
description: "MAC Address 1 [31:0]"
|
||||
description: MAC Address 1 [31:0]
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/MACA2HR:
|
||||
description: Address 2 high register
|
||||
fields:
|
||||
- name: ADDRHI
|
||||
description: "MAC Address2 [47:32]"
|
||||
description: MAC Address2 [47:32]
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: MBC
|
||||
@ -945,14 +944,14 @@ fieldset/MACA2LR:
|
||||
description: Address 2 low register
|
||||
fields:
|
||||
- name: ADDRLO
|
||||
description: "MAC Address 2 [31:0]"
|
||||
description: MAC Address 2 [31:0]
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/MACA3HR:
|
||||
description: Address 3 high register
|
||||
fields:
|
||||
- name: ADDRHI
|
||||
description: "MAC Address3 [47:32]"
|
||||
description: MAC Address3 [47:32]
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: MBC
|
||||
@ -971,7 +970,7 @@ fieldset/MACA3LR:
|
||||
description: Address 3 low register
|
||||
fields:
|
||||
- name: ADDRLO
|
||||
description: "MAC Address 3 [31:0]"
|
||||
description: MAC Address 3 [31:0]
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/MACACR:
|
||||
@ -1791,7 +1790,7 @@ fieldset/MACPPSCR:
|
||||
description: PPS control register
|
||||
fields:
|
||||
- name: PPSCTRL
|
||||
description: "Flexible PPS Output (ptp_pps_o[0]) Control or PPSCTRL PPS Output Frequency Control if PPSEN0 is cleared"
|
||||
description: Flexible PPS Output (ptp_pps_o[0]) Control or PPSCTRL PPS Output Frequency Control if PPSEN0 is cleared
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: PPSEN0
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
@ -69,7 +68,7 @@ fieldset/EXTICR:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
@ -69,7 +68,7 @@ fieldset/EXTICR:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: Extended interrupt and event controller
|
||||
items:
|
||||
@ -87,7 +86,7 @@ fieldset/EXTI:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: Extended interrupt and event controller
|
||||
items:
|
||||
@ -76,7 +75,7 @@ fieldset/EXTI:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
@ -45,7 +44,7 @@ block/EXTI:
|
||||
byte_offset: 136
|
||||
fieldset: LINES
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
@ -87,7 +86,7 @@ fieldset/EXTICR:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
@ -87,7 +86,7 @@ fieldset/EXTICR:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
@ -45,7 +44,7 @@ block/EXTI:
|
||||
byte_offset: 20
|
||||
fieldset: LINES
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/CPU:
|
||||
description: CPU-specific registers
|
||||
items:
|
||||
@ -55,7 +54,7 @@ block/EXTI:
|
||||
byte_offset: 128
|
||||
block: CPU
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
@ -45,7 +44,7 @@ block/EXTI:
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
@ -270,19 +269,19 @@ enum/nBOOT0:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: "When BOOT_SEL is cleared, select the device boot mode"
|
||||
description: When BOOT_SEL is cleared, select the device boot mode
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "When BOOT_SEL is cleared, select the device boot mode"
|
||||
description: When BOOT_SEL is cleared, select the device boot mode
|
||||
value: 1
|
||||
enum/nBOOT1:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: "Together with BOOT0, select the device boot mode"
|
||||
description: Together with BOOT0, select the device boot mode
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "Together with BOOT0, select the device boot mode"
|
||||
description: Together with BOOT0, select the device boot mode
|
||||
value: 1
|
||||
enum/nRST_STDBY:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: FLASH
|
||||
items:
|
||||
@ -184,11 +183,11 @@ enum/LATENCY:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: WS0
|
||||
description: "Zero wait state, if 0 < SYSCLK≤ 24 MHz"
|
||||
description: Zero wait state, if 0 < SYSCLK≤ 24 MHz
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: "One wait state, if 24 MHz < SYSCLK ≤ 48 MHz"
|
||||
description: One wait state, if 24 MHz < SYSCLK ≤ 48 MHz
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: "Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz"
|
||||
description: Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz
|
||||
value: 2
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: FLASH
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
@ -208,13 +207,13 @@ enum/LATENCY:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: WS0
|
||||
description: "0 wait states, if 0 < HCLK <= 24 MHz"
|
||||
description: 0 wait states, if 0 < HCLK <= 24 MHz
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: "1 wait state, if 24 < HCLK <= 48 MHz"
|
||||
description: 1 wait state, if 24 < HCLK <= 48 MHz
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: "2 wait states, if 48 < HCLK <= 72 MHz"
|
||||
description: 2 wait states, if 48 < HCLK <= 72 MHz
|
||||
value: 2
|
||||
enum/RDPRT:
|
||||
bit_size: 2
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: FLASH
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: FLASH
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: FLASH address block description
|
||||
items:
|
||||
@ -281,7 +280,7 @@ fieldset/BOOTR:
|
||||
description: FLASH secure boot register
|
||||
fields:
|
||||
- name: SECBOOT_LOCK
|
||||
description: "A field locking the values of UBE, SWAP_ BANK, and SECBOOTADD setting."
|
||||
description: A field locking the values of UBE, SWAP_ BANK, and SECBOOTADD setting.
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
enum: BOOTR_SECBOOT_LOCK
|
||||
@ -421,7 +420,7 @@ fieldset/NSBOOTR:
|
||||
description: FLASH non-secure boot register
|
||||
fields:
|
||||
- name: NSBOOT_LOCK
|
||||
description: "A field locking the values of SWAP_ BANK, and NSBOOTADD settings."
|
||||
description: A field locking the values of SWAP_ BANK, and NSBOOTADD settings.
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
enum: NSBOOTR_NSBOOT_LOCK
|
||||
@ -711,7 +710,7 @@ fieldset/OPTSR:
|
||||
bit_size: 1
|
||||
enum: OPTSR_NRST_STDBY
|
||||
- name: PRODUCT_STATE
|
||||
description: "Life state code (based on Hamming 8,4). More information in Section<6F>7.6.11: Product state transitions."
|
||||
description: 'Life state code (based on Hamming 8,4). More information in Section<6F>7.6.11: Product state transitions.'
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: IO_VDD_HSLV
|
||||
@ -819,7 +818,7 @@ fieldset/SECBOOTR:
|
||||
description: FLASH secure boot register
|
||||
fields:
|
||||
- name: SECBOOT_LOCK
|
||||
description: "A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings."
|
||||
description: A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings.
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
enum: SECBOOTR_SECBOOT_LOCK
|
||||
@ -1042,7 +1041,7 @@ enum/BOOTR_SECBOOT_LOCK:
|
||||
description: The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled).
|
||||
value: 180
|
||||
- name: B_0xC3
|
||||
description: "The BOOT_UBE, SWAP_ BANK and SECBOOTADD can still be modified following their individual rules."
|
||||
description: The BOOT_UBE, SWAP_ BANK and SECBOOTADD can still be modified following their individual rules.
|
||||
value: 195
|
||||
enum/CODE_OP:
|
||||
bit_size: 3
|
||||
@ -1129,10 +1128,10 @@ enum/OPTSR_BOR_LEV:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: B_0x1
|
||||
description: "BOR Level 2, the threshold level is medium (around 2.4 V)"
|
||||
description: BOR Level 2, the threshold level is medium (around 2.4 V)
|
||||
value: 1
|
||||
- name: B_0x2
|
||||
description: "BOR Level 3, the threshold level is high (around 2.7 V)"
|
||||
description: BOR Level 3, the threshold level is high (around 2.7 V)
|
||||
value: 2
|
||||
enum/OPTSR_IO_VDDIO_HSLV:
|
||||
bit_size: 1
|
||||
@ -1258,7 +1257,7 @@ enum/SECBOOTR_SECBOOT_LOCK:
|
||||
description: The BOOT_UBE and SECBOOTADD are frozen. SWAP_ BANK can only be modified with TZEN set to 0xC3 (disabled).
|
||||
value: 180
|
||||
- name: B_0xC3
|
||||
description: "The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules."
|
||||
description: The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules.
|
||||
value: 195
|
||||
enum/SECCR_BKSEL:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: FLASH address block description
|
||||
items:
|
||||
@ -165,7 +164,7 @@ fieldset/ECCCORR:
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ECCCIE
|
||||
description: "ECC single correction error interrupt enable bit When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation."
|
||||
description: ECC single correction error interrupt enable bit When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation.
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: ECCC
|
||||
@ -239,7 +238,7 @@ fieldset/NSBOOTR:
|
||||
description: FLASH non-secure unique boot entry register
|
||||
fields:
|
||||
- name: NSBOOT_LOCK
|
||||
description: "A field locking the values of SWAP_BANK, and NSBOOTADD settings."
|
||||
description: A field locking the values of SWAP_BANK, and NSBOOTADD settings.
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
enum: NSBOOTR_NSBOOT_LOCK
|
||||
@ -469,7 +468,7 @@ fieldset/OPTSR:
|
||||
bit_size: 1
|
||||
enum: OPTSR_NRST_STDBY
|
||||
- name: PRODUCT_STATE
|
||||
description: "Life state code (based on Hamming 8,4). More information in ."
|
||||
description: Life state code (based on Hamming 8,4). More information in .
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: IO_VDD_HSLV
|
||||
@ -658,16 +657,16 @@ enum/OPTSR_BOR_LEV:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "BOR OFF, POR/PDR reset threshold level is applied"
|
||||
description: BOR OFF, POR/PDR reset threshold level is applied
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "BOR Level 1, the threshold level is low (around 2.1 V)"
|
||||
description: BOR Level 1, the threshold level is low (around 2.1 V)
|
||||
value: 1
|
||||
- name: B_0x2
|
||||
description: "BOR Level 2, the threshold level is medium (around 2.4 V)"
|
||||
description: BOR Level 2, the threshold level is medium (around 2.4 V)
|
||||
value: 2
|
||||
- name: B_0x3
|
||||
description: "BOR Level 3, the threshold level is high (around 2.7 V)"
|
||||
description: BOR Level 3, the threshold level is high (around 2.7 V)
|
||||
value: 3
|
||||
enum/OPTSR_IO_VDDIO_HSLV:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,6 +1,5 @@
|
||||
---
|
||||
block/BANK:
|
||||
description: "Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R"
|
||||
description: Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R
|
||||
items:
|
||||
- name: KEYR
|
||||
description: FLASH key register for bank 1
|
||||
@ -70,7 +69,7 @@ block/FLASH:
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: BANK
|
||||
description: "Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R"
|
||||
description: Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R
|
||||
array:
|
||||
len: 2
|
||||
stride: 256
|
||||
@ -190,6 +189,10 @@ fieldset/CCR:
|
||||
description: Bank 1 CRCEND1 flag clear bit
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: CLR_CRCRDERR
|
||||
description: Bank 1 CRC read error clear bit
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: FLASH control register for bank 1
|
||||
fields:
|
||||
@ -273,6 +276,10 @@ fieldset/CR:
|
||||
description: Bank 1 end of CRC calculation interrupt enable bit
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: CRCRDERRIE
|
||||
description: Bank 1 CRC read error interrupt enable bit
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
fieldset/CRCCR:
|
||||
description: FLASH CRC control register for bank 1
|
||||
fields:
|
||||
@ -621,6 +628,10 @@ fieldset/SR:
|
||||
description: Bank 1 CRC-complete flag
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: CRCRDERR
|
||||
description: Bank 1 CRC read error flag
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
fieldset/WPSN_CURR:
|
||||
description: FLASH write sector protection for bank 1
|
||||
fields:
|
||||
|
||||
648
data/registers/flash_h7ab.yaml
Normal file
648
data/registers/flash_h7ab.yaml
Normal file
@ -0,0 +1,648 @@
|
||||
block/BANK:
|
||||
description: Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R
|
||||
items:
|
||||
- name: KEYR
|
||||
description: FLASH key register for bank 1
|
||||
byte_offset: 0
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: CR
|
||||
description: FLASH control register for bank 1
|
||||
byte_offset: 8
|
||||
fieldset: CR
|
||||
- name: SR
|
||||
description: FLASH status register for bank 1
|
||||
byte_offset: 12
|
||||
fieldset: SR
|
||||
- name: CCR
|
||||
description: FLASH clear control register for bank 1
|
||||
byte_offset: 16
|
||||
fieldset: CCR
|
||||
- name: PRAR_CUR
|
||||
description: FLASH protection address for bank 1
|
||||
byte_offset: 36
|
||||
access: Read
|
||||
fieldset: PRAR_CUR
|
||||
- name: PRAR_PRG
|
||||
description: FLASH protection address for bank 1
|
||||
byte_offset: 40
|
||||
fieldset: PRAR_PRG
|
||||
- name: SCAR_CUR
|
||||
description: FLASH secure address for bank 1
|
||||
byte_offset: 44
|
||||
fieldset: SCAR_CUR
|
||||
- name: SCAR_PRG
|
||||
description: FLASH secure address for bank 1
|
||||
byte_offset: 48
|
||||
fieldset: SCAR_PRG
|
||||
- name: WPSN_CURR
|
||||
description: FLASH write sector protection for bank 1
|
||||
byte_offset: 52
|
||||
access: Read
|
||||
fieldset: WPSN_CURR
|
||||
- name: WPSN_PRGR
|
||||
description: FLASH write sector protection for bank 1
|
||||
byte_offset: 56
|
||||
fieldset: WPSN_PRGR
|
||||
- name: CRCCR
|
||||
description: FLASH CRC control register for bank 1
|
||||
byte_offset: 76
|
||||
fieldset: CRCCR
|
||||
- name: CRCSADDR
|
||||
description: FLASH CRC start address register for bank 1
|
||||
byte_offset: 80
|
||||
fieldset: CRCSADDR
|
||||
- name: CRCEADDR
|
||||
description: FLASH CRC end address register for bank 1
|
||||
byte_offset: 84
|
||||
fieldset: CRCEADDR
|
||||
- name: FAR
|
||||
description: FLASH ECC fail address for bank 1
|
||||
byte_offset: 92
|
||||
access: Read
|
||||
fieldset: FAR
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
- name: ACR
|
||||
description: Access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: BANK
|
||||
description: Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R
|
||||
array:
|
||||
len: 2
|
||||
stride: 256
|
||||
byte_offset: 4
|
||||
block: BANK
|
||||
- name: OPTKEYR
|
||||
description: FLASH option key register
|
||||
byte_offset: 8
|
||||
fieldset: OPTKEYR
|
||||
- name: OPTCR
|
||||
description: FLASH option control register
|
||||
byte_offset: 24
|
||||
fieldset: OPTCR
|
||||
- name: OPTSR_CUR
|
||||
description: FLASH option status register
|
||||
byte_offset: 28
|
||||
fieldset: OPTSR_CUR
|
||||
- name: OPTSR_PRG
|
||||
description: FLASH option status register
|
||||
byte_offset: 32
|
||||
fieldset: OPTSR_PRG
|
||||
- name: OPTCCR
|
||||
description: FLASH option clear control register
|
||||
byte_offset: 36
|
||||
access: Write
|
||||
fieldset: OPTCCR
|
||||
- name: BOOT_CURR
|
||||
description: FLASH register with boot address
|
||||
byte_offset: 64
|
||||
access: Read
|
||||
fieldset: BOOT_CURR
|
||||
- name: BOOT_PRGR
|
||||
description: FLASH register with boot address
|
||||
byte_offset: 68
|
||||
fieldset: BOOT_PRGR
|
||||
- name: CRCDATAR
|
||||
description: FLASH CRC data register
|
||||
byte_offset: 92
|
||||
fieldset: CRCDATAR
|
||||
fieldset/ACR:
|
||||
description: Access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: Read latency
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
- name: WRHIGHFREQ
|
||||
description: Flash signal delay
|
||||
bit_offset: 4
|
||||
bit_size: 2
|
||||
fieldset/BOOT_CURR:
|
||||
description: FLASH register with boot address
|
||||
fields:
|
||||
- name: BOOT_ADD0
|
||||
description: Boot address 0
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: BOOT_ADD1
|
||||
description: Boot address 1
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/BOOT_PRGR:
|
||||
description: FLASH register with boot address
|
||||
fields:
|
||||
- name: BOOT_ADD0
|
||||
description: Boot address 0
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: BOOT_ADD1
|
||||
description: Boot address 1
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/CCR:
|
||||
description: FLASH clear control register for bank 1
|
||||
fields:
|
||||
- name: CLR_EOP
|
||||
description: Bank 1 EOP1 flag clear bit
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: CLR_WRPERR
|
||||
description: Bank 1 WRPERR1 flag clear bit
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: CLR_PGSERR
|
||||
description: Bank 1 PGSERR1 flag clear bi
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: CLR_STRBERR
|
||||
description: Bank 1 STRBERR1 flag clear bit
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: CLR_INCERR
|
||||
description: Bank 1 INCERR1 flag clear bit
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: CLR_OPERR
|
||||
description: Bank 1 OPERR1 flag clear bit
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: CLR_RDPERR
|
||||
description: Bank 1 RDPERR1 flag clear bit
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: CLR_RDSERR
|
||||
description: Bank 1 RDSERR1 flag clear bit
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: CLR_SNECCERR
|
||||
description: Bank 1 SNECCERR1 flag clear bit
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: CLR_DBECCERR
|
||||
description: Bank 1 DBECCERR1 flag clear bit
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: CLR_CRCEND
|
||||
description: Bank 1 CRCEND1 flag clear bit
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: CLR_CRCRDERR
|
||||
description: Bank 1 CRC read error clear bit
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: FLASH control register for bank 1
|
||||
fields:
|
||||
- name: LOCK
|
||||
description: Bank 1 configuration lock bit
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PG
|
||||
description: Bank 1 program enable bit
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: SER
|
||||
description: Bank 1 sector erase request
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: BER
|
||||
description: Bank 1 erase request
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: FW
|
||||
description: Bank 1 write forcing control bit
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: START
|
||||
description: Bank 1 bank or sector erase start control bit
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SSN
|
||||
description: Bank 1 sector erase selection number
|
||||
bit_offset: 6
|
||||
bit_size: 7
|
||||
- name: CRC_EN
|
||||
description: Bank 1 CRC control bit
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: Bank 1 end-of-program interrupt control bit
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: WRPERRIE
|
||||
description: Bank 1 write protection error interrupt enable bit
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: PGSERRIE
|
||||
description: Bank 1 programming sequence error interrupt enable bit
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: STRBERRIE
|
||||
description: Bank 1 strobe error interrupt enable bit
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: INCERRIE
|
||||
description: Bank 1 inconsistency error interrupt enable bit
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: OPERRIE
|
||||
description: Bank 1 write/erase error interrupt enable bit
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: RDPERRIE
|
||||
description: Bank 1 read protection error interrupt enable bit
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: RDSERRIE
|
||||
description: Bank 1 secure error interrupt enable bit
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: SNECCERRIE
|
||||
description: Bank 1 ECC single correction error interrupt enable bit
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: DBECCERRIE
|
||||
description: Bank 1 ECC double detection error interrupt enable bit
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: CRCENDIE
|
||||
description: Bank 1 end of CRC calculation interrupt enable bit
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: CRCRDERRIE
|
||||
description: Bank 1 CRC read error interrupt enable bit
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
fieldset/CRCCR:
|
||||
description: FLASH CRC control register for bank 1
|
||||
fields:
|
||||
- name: CRC_SECT
|
||||
description: Bank 1 CRC sector number
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
- name: ALL_BANK
|
||||
description: Bank 1 CRC select bit
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: CRC_BY_SECT
|
||||
description: Bank 1 CRC sector mode select bit
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ADD_SECT
|
||||
description: Bank 1 CRC sector select bit
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: CLEAN_SECT
|
||||
description: Bank 1 CRC sector list clear bit
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: START_CRC
|
||||
description: Bank 1 CRC start bit
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: CLEAN_CRC
|
||||
description: Bank 1 CRC clear bit
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: CRC_BURST
|
||||
description: Bank 1 CRC burst size
|
||||
bit_offset: 20
|
||||
bit_size: 2
|
||||
fieldset/CRCDATAR:
|
||||
description: FLASH CRC data register
|
||||
fields:
|
||||
- name: CRC_DATA
|
||||
description: CRC result
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/CRCEADDR:
|
||||
description: FLASH CRC end address register for bank 1
|
||||
fields:
|
||||
- name: CRC_END_ADDR
|
||||
description: CRC end address on bank 1
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/CRCSADDR:
|
||||
description: FLASH CRC start address register for bank 1
|
||||
fields:
|
||||
- name: CRC_START_ADDR
|
||||
description: CRC start address on bank 1
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/FAR:
|
||||
description: FLASH ECC fail address for bank 1
|
||||
fields:
|
||||
- name: FAIL_ECC_ADDR
|
||||
description: Bank 1 ECC error address
|
||||
bit_offset: 0
|
||||
bit_size: 15
|
||||
fieldset/KEYR:
|
||||
description: FLASH key register for bank 1
|
||||
fields:
|
||||
- name: KEYR
|
||||
description: Bank 1 access configuration unlock key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTCCR:
|
||||
description: FLASH option clear control register
|
||||
fields:
|
||||
- name: CLR_OPTCHANGEERR
|
||||
description: OPTCHANGEERR reset bit
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
fieldset/OPTCR:
|
||||
description: FLASH option control register
|
||||
fields:
|
||||
- name: OPTLOCK
|
||||
description: FLASH_OPTCR lock option configuration bit
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPTSTART
|
||||
description: Option byte start change option configuration bit
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Flash mass erase enable bit
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PG_OTP
|
||||
description: OTP program control bit
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: OPTCHANGEERRIE
|
||||
description: Option byte change error interrupt enable bit
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: SWAP_BANK
|
||||
description: Bank swapping configuration bit
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/OPTKEYR:
|
||||
description: FLASH option key register
|
||||
fields:
|
||||
- name: OPTKEYR
|
||||
description: Unlock key option bytes
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTSR_CUR:
|
||||
description: FLASH option status register
|
||||
fields:
|
||||
- name: OPT_BUSY
|
||||
description: Option byte change ongoing flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: BOR_LEV
|
||||
description: Brownout level option status bit
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
- name: IWDG1_HW
|
||||
description: IWDG1 control option status bit
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: nRST_STOP_D1
|
||||
description: D1 DStop entry reset option status bit
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: nRST_STBY_D1
|
||||
description: D1 DStandby entry reset option status bit
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: RDP
|
||||
description: Readout protection level option status byte
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: FZ_IWDG_STOP
|
||||
description: IWDG Stop mode freeze option status bit
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: FZ_IWDG_SDBY
|
||||
description: IWDG Standby mode freeze option status bit
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: ST_RAM_SIZE
|
||||
description: DTCM RAM size option status
|
||||
bit_offset: 19
|
||||
bit_size: 2
|
||||
- name: SECURITY
|
||||
description: Security enable option status bit
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: RSS1
|
||||
description: User option bit 1
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: PERSO_OK
|
||||
description: Device personalization status bit
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: IO_HSLV
|
||||
description: I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V)
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: OPTCHANGEERR
|
||||
description: Option byte change error flag
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: SWAP_BANK_OPT
|
||||
description: Bank swapping option status bit
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/OPTSR_PRG:
|
||||
description: FLASH option status register
|
||||
fields:
|
||||
- name: BOR_LEV
|
||||
description: BOR reset level option configuration bits
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
- name: IWDG1_HW
|
||||
description: IWDG1 option configuration bit
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: nRST_STOP_D1
|
||||
description: Option byte erase after D1 DStop option configuration bit
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: nRST_STBY_D1
|
||||
description: Option byte erase after D1 DStandby option configuration bit
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: RDP
|
||||
description: Readout protection level option configuration byte
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: FZ_IWDG_STOP
|
||||
description: IWDG Stop mode freeze option configuration bit
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: FZ_IWDG_SDBY
|
||||
description: IWDG Standby mode freeze option configuration bit
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: ST_RAM_SIZE
|
||||
description: DTCM size select option configuration bits
|
||||
bit_offset: 19
|
||||
bit_size: 2
|
||||
- name: SECURITY
|
||||
description: Security option configuration bit
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: RSS1
|
||||
description: User option configuration bit 1
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: RSS2
|
||||
description: User option configuration bit 2
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: IO_HSLV
|
||||
description: I/O high-speed at low-voltage (PRODUCT_BELOW_25V)
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: SWAP_BANK_OPT
|
||||
description: Bank swapping option configuration bit
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/PRAR_CUR:
|
||||
description: FLASH protection address for bank 1
|
||||
fields:
|
||||
- name: PROT_AREA_START
|
||||
description: Bank 1 lowest PCROP protected address
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: PROT_AREA_END
|
||||
description: Bank 1 highest PCROP protected address
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
- name: DMEP
|
||||
description: Bank 1 PCROP protected erase enable option status bit
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/PRAR_PRG:
|
||||
description: FLASH protection address for bank 1
|
||||
fields:
|
||||
- name: PROT_AREA_START
|
||||
description: Bank 1 lowest PCROP protected address configuration
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: PROT_AREA_END
|
||||
description: Bank 1 highest PCROP protected address configuration
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
- name: DMEP
|
||||
description: Bank 1 PCROP protected erase enable option configuration bit
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SCAR_CUR:
|
||||
description: FLASH secure address for bank 1
|
||||
fields:
|
||||
- name: SEC_AREA_START
|
||||
description: Bank 1 lowest secure protected address
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: SEC_AREA_END
|
||||
description: Bank 1 highest secure protected address
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
- name: DMES
|
||||
description: Bank 1 secure protected erase enable option status bit
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SCAR_PRG:
|
||||
description: FLASH secure address for bank 1
|
||||
fields:
|
||||
- name: SEC_AREA_START
|
||||
description: Bank 1 lowest secure protected address configuration
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: SEC_AREA_END
|
||||
description: Bank 1 highest secure protected address configuration
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
- name: DMES
|
||||
description: Bank 1 secure protected erase enable option configuration bit
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SR:
|
||||
description: FLASH status register for bank 1
|
||||
fields:
|
||||
- name: BSY
|
||||
description: Bank 1 ongoing program flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: WBNE
|
||||
description: Bank 1 write buffer not empty flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: QW
|
||||
description: Bank 1 wait queue flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: CRC_BUSY
|
||||
description: Bank 1 CRC busy flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: Bank 1 end-of-program flag
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Bank 1 write protection error flag
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: Bank 1 programming sequence error flag
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: STRBERR
|
||||
description: Bank 1 strobe error flag
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: INCERR
|
||||
description: Bank 1 inconsistency error flag
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Bank 1 write/erase error flag
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: RDPERR
|
||||
description: Bank 1 read protection error flag
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: RDSERR
|
||||
description: Bank 1 secure error flag
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: SNECCERR1
|
||||
description: Bank 1 single correction error flag
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: DBECCERR
|
||||
description: Bank 1 ECC double detection error flag
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: CRCEND
|
||||
description: Bank 1 CRC-complete flag
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: CRCRDERR
|
||||
description: Bank 1 CRC read error flag
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
fieldset/WPSN_CURR:
|
||||
description: FLASH write sector protection for bank 1
|
||||
fields:
|
||||
- name: WRPSn
|
||||
description: Bank 1 sector write protection option status byte
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/WPSN_PRGR:
|
||||
description: FLASH write sector protection for bank 1
|
||||
fields:
|
||||
- name: WRPSn
|
||||
description: Bank 1 sector write protection configuration byte
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
@ -129,7 +128,7 @@ fieldset/PECR:
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: FIX
|
||||
description: "Fixed time data write for Byte, Half Word and Word programming"
|
||||
description: Fixed time data write for Byte, Half Word and Word programming
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ERASE
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
@ -139,7 +138,7 @@ fieldset/PECR:
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: FTDW
|
||||
description: "Fixed time data write for Byte, Half Word and Word programming"
|
||||
description: Fixed time data write for Byte, Half Word and Word programming
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ERASE
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
@ -476,7 +475,7 @@ fieldset/OPTR:
|
||||
bit_size: 1
|
||||
enum: nRST_SHDW
|
||||
- name: SRAM1345_RST
|
||||
description: "SRAM1, SRAM3 and SRAM4 erase upon system reset"
|
||||
description: SRAM1, SRAM3 and SRAM4 erase upon system reset
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: IWDG_SW
|
||||
@ -3143,7 +3142,7 @@ enum/RDP:
|
||||
bit_size: 8
|
||||
variants:
|
||||
- name: B_0x55
|
||||
description: "Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1)"
|
||||
description: Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1)
|
||||
value: 85
|
||||
- name: B_0xAA
|
||||
description: Level 0 (readout protection not active)
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
|
||||
643
data/registers/flash_wba.yaml
Normal file
643
data/registers/flash_wba.yaml
Normal file
@ -0,0 +1,643 @@
|
||||
block/FLASH:
|
||||
description: Embedded memory
|
||||
items:
|
||||
- name: ACR
|
||||
description: access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: NSKEYR
|
||||
description: key register
|
||||
byte_offset: 8
|
||||
fieldset: NSKEYR
|
||||
- name: SECKEYR
|
||||
description: secure key register
|
||||
byte_offset: 12
|
||||
fieldset: SECKEYR
|
||||
- name: OPTKEYR
|
||||
description: option key register
|
||||
byte_offset: 16
|
||||
fieldset: OPTKEYR
|
||||
- name: PDKEYR
|
||||
description: power-down key register
|
||||
byte_offset: 24
|
||||
fieldset: PDKEYR
|
||||
- name: NSSR
|
||||
description: status register
|
||||
byte_offset: 32
|
||||
fieldset: NSSR
|
||||
- name: SECSR
|
||||
description: secure status register
|
||||
byte_offset: 36
|
||||
fieldset: SECSR
|
||||
- name: NSCR1
|
||||
description: control register
|
||||
byte_offset: 40
|
||||
fieldset: NSCR1
|
||||
- name: SECCR1
|
||||
description: secure control register
|
||||
byte_offset: 44
|
||||
fieldset: SECCR1
|
||||
- name: ECCR
|
||||
description: ECC register
|
||||
byte_offset: 48
|
||||
fieldset: ECCR
|
||||
- name: OPSR
|
||||
description: operation status register
|
||||
byte_offset: 52
|
||||
fieldset: OPSR
|
||||
- name: NSCR2
|
||||
description: control 2 register
|
||||
byte_offset: 56
|
||||
fieldset: NSCR2
|
||||
- name: SECCR2
|
||||
description: secure control 2 register
|
||||
byte_offset: 60
|
||||
fieldset: SECCR2
|
||||
- name: OPTR
|
||||
description: option register
|
||||
byte_offset: 64
|
||||
fieldset: OPTR
|
||||
- name: NSBOOTADD0R
|
||||
description: boot address 0 register
|
||||
byte_offset: 68
|
||||
fieldset: NSBOOTADD0R
|
||||
- name: NSBOOTADD1R
|
||||
description: boot address 1 register
|
||||
byte_offset: 72
|
||||
fieldset: NSBOOTADD1R
|
||||
- name: SECBOOTADD0R
|
||||
description: secure boot address 0 register
|
||||
byte_offset: 76
|
||||
fieldset: SECBOOTADD0R
|
||||
- name: SECWMR1
|
||||
description: secure watermark register 1
|
||||
byte_offset: 80
|
||||
fieldset: SECWMR1
|
||||
- name: SECWMR2
|
||||
description: secure watermark register 2
|
||||
byte_offset: 84
|
||||
fieldset: SECWMR2
|
||||
- name: WRPAR
|
||||
description: WRP area A address register
|
||||
byte_offset: 88
|
||||
fieldset: WRPAR
|
||||
- name: WRPBR
|
||||
description: WRP area B address register
|
||||
byte_offset: 92
|
||||
fieldset: WRPBR
|
||||
- name: OEM1KEYR1
|
||||
description: OEM1 key register 1
|
||||
byte_offset: 112
|
||||
- name: OEM1KEYR2
|
||||
description: OEM1 key register 2
|
||||
byte_offset: 116
|
||||
- name: OEM2KEYR1
|
||||
description: OEM2 key register 1
|
||||
byte_offset: 120
|
||||
- name: OEM2KEYR2
|
||||
description: OEM2 key register 2
|
||||
byte_offset: 124
|
||||
- name: SECBBR
|
||||
description: secure block based register 1
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 128
|
||||
fieldset: BBR
|
||||
- name: SECHDPCR
|
||||
description: secure HDP control register
|
||||
byte_offset: 192
|
||||
fieldset: SECHDPCR
|
||||
- name: PRIFCFGR
|
||||
description: privilege configuration register
|
||||
byte_offset: 196
|
||||
fieldset: PRIFCFGR
|
||||
- name: PRIVBBR
|
||||
description: privilege block based register 1
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 208
|
||||
fieldset: BBR
|
||||
fieldset/ACR:
|
||||
description: access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: "Latency\r These bits represent the ratio between the AHB hclk1 clock period and the memory access time.\r Access to the bit can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r ...\r Note: Before entering Stop 1 mode software must set wait state latency to at least 1."
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: PRFTEN
|
||||
description: "Prefetch enable\r This bit enables the prefetch buffer in the embedded memory.\r This bit can be protected against unprivileged access by NSPRIV."
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: LPM
|
||||
description: "Low-power read mode\r This bit puts the memory in low-power read mode.\r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r This bit can’t be written when a program or erase operation is busy (BSY = 1) or when the write buffer is not empty (WDW = 1). Changing this bit while a program or erase operation is busy (BSY = 1) is rejected."
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: PDREQ
|
||||
description: "power-down mode request\r This bit requests to enter power-down mode. When enters power-down mode, this bit is cleared by hardware and the PDKEYR is locked.\r This bit is write-protected with PDKEYR. \r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: SLEEP_PD
|
||||
description: "memory power-down mode during Sleep mode\r This bit determines whether the memory is in power-down mode or Idle mode when the device is in Sleep mode.\r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r The must not be put in power-down while a program or an erase operation is ongoing."
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
fieldset/BBR:
|
||||
description: block based register
|
||||
fields:
|
||||
- name: BLOCK
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 32
|
||||
stride: 1
|
||||
fieldset/ECCR:
|
||||
description: ECC register
|
||||
fields:
|
||||
- name: ADDR_ECC
|
||||
description: "ECC fail address\r This field indicates which address is concerned by the ECC error correction or by the double ECC error detection. The address is given relative to base address, from offset 0x0<78>0000 to 0xF<78>FFF0.\r Note that bit 19 is reserved on STM32WBAxEx devices."
|
||||
bit_offset: 0
|
||||
bit_size: 20
|
||||
- name: SYSF_ECC
|
||||
description: "System memory ECC fail\r This bit indicates that the ECC error correction or double ECC error detection is located in the system memory."
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: ECCIE
|
||||
description: "ECC correction interrupt enable\r This bit enables the interrupt generation when the ECCC bit in the ECCR register is set."
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ECCC
|
||||
description: "ECC correction\r This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1."
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: ECCD
|
||||
description: "ECC detection\r This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1."
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/NSBOOTADD0R:
|
||||
description: boot address 0 register
|
||||
fields:
|
||||
- name: NSBOOTADD0
|
||||
description: "Non-secure boot base address 0\r This address is only used when TZEN = 0.\r The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state.\r Examples:\r NSBOOTADD0[24:0] = 0x0100000: Boot from memory (0x0800 0000)\r NSBOOTADD0[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000)\r NSBOOTADD0[24:0] = 0x0400200: Boot from SRAM2 on S-Bus (0x2001 0000)"
|
||||
bit_offset: 7
|
||||
bit_size: 25
|
||||
fieldset/NSBOOTADD1R:
|
||||
description: boot address 1 register
|
||||
fields:
|
||||
- name: NSBOOTADD1
|
||||
description: "Non-secure boot address 1\r This address is only used when TZEN = 0.\r The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. \r Examples:\r NSBOOTADD1[24:0] = 0x0100000: Boot from memory (0x0800 0000)\r NSBOOTADD1[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000)\r NSBOOTADD1[24:0] = 0x0400200: Boot from SRAM2 (0x2001 0000)"
|
||||
bit_offset: 7
|
||||
bit_size: 25
|
||||
fieldset/NSCR1:
|
||||
description: control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Non-secure programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Non-secure page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: "Non-secure mass erase\r This bit triggers the non-secure mass erase (all user pages) when set."
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PNB
|
||||
description: "Non-secure page number selection\r These bits select the page to erase.\r ...\r Note that bit 9 is reserved on STM32WBA5xEx devices."
|
||||
bit_offset: 3
|
||||
bit_size: 7
|
||||
- name: BWR
|
||||
description: "Non-secure burst write programming mode\r When set, this bit selects the burst write programming mode."
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: STRT
|
||||
description: "Non-secure operation start \r This bit triggers a non-secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR bit in NSSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in NSSR."
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: "Options modification start\r This bit triggers an option bytes erase and program operation when set. This bit is write-protected with OPTLOCK.. This bit is set only by software, and is cleared when the BSY bit is cleared in NSSR."
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: "Non-secure end of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in the NSSR is set to 1."
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: "Non-secure error interrupt enable\r This bit enables the interrupt generation when the OPERR bit in the NSSR is set to 1."
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: "Force the option byte loading\r When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. This bit is write-protected with OPTLOCK.\r Note: The LSE oscillator must be disabled, LSEON = 0 and LSERDY = 0, before starting OBL_LAUNCH."
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: "Option lock\r This bit is set only. When set, the NSCR1.OPTSRT and OBL_LAUNCH bits concerning user options write access is locked. This bit is cleared by hardware after detecting the unlock sequence in OPTKEYR. The NSCR1.LOCK bit must be cleared before doing the OPTKEYR unlock sequence.\r In case of an unsuccessful unlock operation, this bit remains set until the next reset."
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: "Non-secure lock\r This bit is set only.\r When set, the NSCR1 register write access is locked. This bit is cleared by hardware after detecting the unlock sequence in NSKEYR.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset."
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/NSCR2:
|
||||
description: control 2 register
|
||||
fields:
|
||||
- name: PS
|
||||
description: Program suspend request
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: ES
|
||||
description: Erase suspend request
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
fieldset/NSKEYR:
|
||||
description: key register
|
||||
fields:
|
||||
- name: NSKEY
|
||||
description: "memory non-secure key\r The following values must be written consecutively to unlock the NSCR1 register, allowing the memory non-secure programming/erasing operations:\r KEY1: 0x4567<36>0123\r KEY2: 0xCDEF<45>89AB"
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/NSSR:
|
||||
description: status register
|
||||
fields:
|
||||
- name: EOP
|
||||
description: "Non-secure end of operation\r This bit is set by hardware when one or more memory non-secure operation (program/erase) has been completed successfully. This bit is set only if the non-secure end of operation interrupts are enabled (EOPIE = 1 in NSCR1). This bit is cleared by writing<6E>1."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: "Non-secure operation error\r This bit is set by hardware when a memory non-secure operation (program/erase) completes unsuccessfully. This bit is set only if non-secure error interrupts are enabled (NSERRIE = 1). This bit is cleared by writing 1."
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PROGERR
|
||||
description: "Non-secure programming error\r This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1."
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: "Non-secure write protection error\r This bit is set by hardware when a non-secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: "Non-secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1."
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: "Non-secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1."
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: "Non-secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: OPTWERR
|
||||
description: "Option write error \r This bit is set by hardware when the options bytes are written with an invalid configuration or when modifying options in RDP level 2.. It is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: "Non-secure busy\r This indicates that a memory secure or non-secure operation is in progress. This bit is set at the beginning of a operation and reset when the operation finishes or when an error occurs."
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: WDW
|
||||
description: "Non-secure wait data to write\r This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory."
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: OEM1LOCK
|
||||
description: "OEM1 key RDP lock\r This bit indicates that the OEM1 key read during the OBL is not virgin. When set, the OEM1 key RDP lock mechanism is active."
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: OEM2LOCK
|
||||
description: "OEM2 key RDP lock\r This bit indicates that the OEM2 key read during the OBL is not virgin. When set, the OEM2 key RDP lock mechanism is active."
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: PD
|
||||
description: "in power-down mode\r This bit indicates that the memory is in power-down state. It is reset when is in normal mode or being awaken."
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
fieldset/OPSR:
|
||||
description: operation status register
|
||||
fields:
|
||||
- name: ADDR_OP
|
||||
description: "Interrupted operation address\r This field indicates which address in the memory was accessed when reset occurred. The address is given relative to the base address, from offset 0x0<78>0000 to 0xF<78>FFF0.\r Note that bit 19 is reserved on STM32WBAxEx devices."
|
||||
bit_offset: 0
|
||||
bit_size: 20
|
||||
- name: SYSF_OP
|
||||
description: "Operation in system memory interrupted\r This bit indicates that the reset occurred during an operation in the system memory."
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: CODE_OP
|
||||
description: "memory operation code\r This field indicates which memory operation has been interrupted by a system reset:"
|
||||
bit_offset: 29
|
||||
bit_size: 3
|
||||
enum: CODE_OP
|
||||
fieldset/OPTKEYR:
|
||||
description: option key register
|
||||
fields:
|
||||
- name: OPTKEY
|
||||
description: "Option byte key\r The LOCK bit in the NSCR1 must be cleared before doing the unlock sequence for OPTLOCK bit. The following values must be written consecutively to unlock the NSCR1.OPTSTRT and OBL_LAUNCH register bits concerning user option operations:\r KEY1: 0x0819<31>2A3B\r KEY2: 0x4C5D<35>6E7F"
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTR:
|
||||
description: option register
|
||||
fields:
|
||||
- name: RDP
|
||||
description: "Readout protection level\r Others: Level 1 (memories readout protection active)\r Note: Refer to Section<6F>7.6.2: Readout protection (RDP) for more details."
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
enum: RDP
|
||||
- name: BOR_LEV
|
||||
description: "BOR reset level\r These bits contain the V<sub>DD</sub> supply level threshold that activates/releases the reset."
|
||||
bit_offset: 8
|
||||
bit_size: 3
|
||||
enum: BOR_LEV
|
||||
- name: NRST_STOP
|
||||
description: Reset generation in Stop mode
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: NRST_STDBY
|
||||
description: Reset generation in Standby mode
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: SRAM1_RST
|
||||
description: SRAM1 erase upon system reset
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: IWDG_SW
|
||||
description: Independent watchdog enable selection
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: IWDG_STOP
|
||||
description: Independent watchdog counter freeze in Stop mode
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: IWDG_STDBY
|
||||
description: Independent watchdog counter freeze in Standby mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: WWDG_SW
|
||||
description: Window watchdog selection
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: SRAM2_PE
|
||||
description: SRAM2 parity check enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: SRAM2_RST
|
||||
description: SRAM2 erase when system reset
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: NSWBOOT0
|
||||
description: Software BOOT0
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: NBOOT0
|
||||
description: NBOOT0 option bit
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: TZEN
|
||||
description: Global TrustZone security enable
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/PDKEYR:
|
||||
description: power-down key register
|
||||
fields:
|
||||
- name: PDKEY1
|
||||
description: "power-down key\r The following values must be written consecutively to unlock the PDREQ bit in ACR:\r PDKEY_1: 0x0415<31>2637\r PDKEY_2: 0xFAFB<46>FCFD"
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PRIFCFGR:
|
||||
description: privilege configuration register
|
||||
fields:
|
||||
- name: SPRIV
|
||||
description: "Privileged protection for secure registers\r This bit is secure write protected. It can only be written by a secure privileged access when TrustZone is enabled (TZEN<45>=<3D>1)."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: NSPRIV
|
||||
description: Privileged protection for non-secure registers
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
fieldset/SECBOOTADD0R:
|
||||
description: secure boot address 0 register
|
||||
fields:
|
||||
- name: BOOT_LOCK
|
||||
description: "Boot lock\r This lock is only used when TZEN = 0.\r When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP regression level 1 to level 0."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SECBOOTADD0
|
||||
description: "Secure boot base address 0\r This address is only used when TZEN = 1.\r The secure boot memory address can be programmed to any address in the valid address range (see Table<6C>28: Boot space versus RDP protection) with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. \r Examples:\r SECBOOTADD0[24:0] = 0x018 0000: Boot from secure user memory (0x0C00 0000)\r SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS system memory (0x0FF8 0000)\r SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000)"
|
||||
bit_offset: 7
|
||||
bit_size: 25
|
||||
fieldset/SECCR1:
|
||||
description: secure control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Secure programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Secure page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: "Secure mass erase\r This bit triggers the secure mass erase (all user pages) when set."
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PNB
|
||||
description: "Secure page number selection\r These bits select the page to erase:\r ...\r Note that bit 9 is reserved on STM32WBA5xEx devices."
|
||||
bit_offset: 3
|
||||
bit_size: 7
|
||||
- name: BWR
|
||||
description: "Secure burst write programming mode\r When set, this bit selects the burst write programming mode."
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: STRT
|
||||
description: "Secure start \r This bit triggers a secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR in the SECSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in SECSR."
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: "Secure End of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in SECSR is set to 1."
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: "Secure error interrupt enable\r This bit enables the interrupt generation when the OPERR bit in SECSR is set to 1."
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: INV
|
||||
description: "memory security state invert\r This bit inverts the memory security state."
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: "Secure lock\r This bit is set only. When set, the SECCR1 register is locked. It is cleared by hardware after detecting the unlock sequence in SECKEYR register.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset."
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SECCR2:
|
||||
description: secure control 2 register
|
||||
fields:
|
||||
- name: PS
|
||||
description: Program suspend request
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: ES
|
||||
description: Erase suspend request
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
fieldset/SECHDPCR:
|
||||
description: secure HDP control register
|
||||
fields:
|
||||
- name: HDP_ACCDIS
|
||||
description: "Secure HDP area access disable \r When set, this bit is only cleared by a system reset."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
fieldset/SECKEYR:
|
||||
description: secure key register
|
||||
fields:
|
||||
- name: SECKEY
|
||||
description: "memory secure key\r The following values must be written consecutively to unlock the SECCR1 register, allowing the memory secure programming/erasing operations:\r KEY1: 0x4567<36>0123\r KEY2: 0xCDEF<45>89AB"
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SECSR:
|
||||
description: secure status register
|
||||
fields:
|
||||
- name: EOP
|
||||
description: "Secure end of operation\r This bit is set by hardware when one or more memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in SECCR1). This bit is cleared by writing<6E>1."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: "Secure operation error\r This bit is set by hardware when a memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1."
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PROGERR
|
||||
description: "Secure programming error\r This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1."
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: "Secure write protection error\r This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: "Secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1."
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: "Secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1."
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: "Secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: "Secure busy\r This bit indicates that a memory secure or non-secure operation is in progress. This is set on the beginning of a operation and reset when the operation finishes or when an error occurs."
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: WDW
|
||||
description: "Secure wait data to write\r This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory."
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
fieldset/SECWMR1:
|
||||
description: secure watermark register 1
|
||||
fields:
|
||||
- name: SECWM_PSTRT
|
||||
description: "Start page of secure area\r This field contains the first page of the secure area."
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: SECWM_PEND
|
||||
description: "End page of secure area\r This field contains the last page of the secure area."
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
fieldset/SECWMR2:
|
||||
description: secure watermark register 2
|
||||
fields:
|
||||
- name: HDP_PEND
|
||||
description: "End page of secure hide protection area\r This field contains the last page of the secure HDP area."
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
- name: HDPEN
|
||||
description: Secure Hide protection area enable
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/WRPAR:
|
||||
description: WRP area A address register
|
||||
fields:
|
||||
- name: WRPA_PSTRT
|
||||
description: "WPR area A start page\r This field contains the first page of the WPR area A.\r Note that bit 6 is reserved on STM32WBAxEx devices."
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: WRPA_PEND
|
||||
description: "WPR area A end page\r This field contains the last page of the WPR area A.\r Note that bit 22 is reserved on STM32WBAxEx devices."
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
- name: UNLOCK
|
||||
description: WPR area A unlock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/WRPBR:
|
||||
description: WRP area B address register
|
||||
fields:
|
||||
- name: WRPB_PSTRT
|
||||
description: "WRP area B start page\r This field contains the first page of the WRP area B.\r Note that bit 6 is reserved on STM32WBAxEx devices."
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: WRPB_PEND
|
||||
description: "WRP area B end page\r This field contains the last page of the WRP area B.\r Note that bit 22 is reserved on STM32WBAxEx devices."
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
- name: UNLOCK
|
||||
description: WPR area B unlock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
enum/BOR_LEV:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Level0
|
||||
description: BOR level 0 (reset level threshold around 1.7<EFBFBD>V)
|
||||
value: 0
|
||||
- name: Level1
|
||||
description: BOR level 1 (reset level threshold around 2.0<EFBFBD>V)
|
||||
value: 1
|
||||
- name: Level2
|
||||
description: BOR level 2 (reset level threshold around 2.2<EFBFBD>V)
|
||||
value: 2
|
||||
- name: Level3
|
||||
description: BOR level 3 (reset level threshold around 2.5<EFBFBD>V)
|
||||
value: 3
|
||||
- name: Level4
|
||||
description: BOR level 4 (reset level threshold around 2.8<EFBFBD>V)
|
||||
value: 4
|
||||
enum/CODE_OP:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: No operation interrupted by previous reset
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: Single write operation interrupted
|
||||
value: 1
|
||||
- name: B_0x2
|
||||
description: Burst write operation interrupted
|
||||
value: 2
|
||||
- name: B_0x3
|
||||
description: Page erase operation interrupted
|
||||
value: 3
|
||||
- name: B_0x4
|
||||
description: Reserved
|
||||
value: 4
|
||||
- name: B_0x5
|
||||
description: Mass erase operation interrupted
|
||||
value: 5
|
||||
- name: B_0x6
|
||||
description: Option change operation interrupted
|
||||
value: 6
|
||||
- name: B_0x7
|
||||
description: Reserved
|
||||
value: 7
|
||||
enum/RDP:
|
||||
bit_size: 8
|
||||
variants:
|
||||
- name: B_0x55
|
||||
description: Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1)
|
||||
value: 85
|
||||
- name: B_0xAA
|
||||
description: Level 0 (readout protection not active)
|
||||
value: 170
|
||||
- name: B_0xCC
|
||||
description: Level 2 (chip readout protection active)
|
||||
value: 204
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FMAC:
|
||||
description: Filter math accelerator
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FMC:
|
||||
description: Flexible memory controller
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FMC:
|
||||
description: Flexible memory controller
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FMC:
|
||||
description: Flexible memory controller
|
||||
items:
|
||||
@ -212,7 +211,7 @@ fieldset/BCR1:
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: BMAP
|
||||
description: "FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register."
|
||||
description: 'FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register.'
|
||||
bit_offset: 24
|
||||
bit_size: 2
|
||||
- name: FMCEN
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FSMC:
|
||||
description: Flexible static memory controller
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FSMC:
|
||||
description: Flexible static memory controller
|
||||
items:
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user