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Merge branch 'master' into lptim-basic

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This commit is contained in:
xoviat 2023-09-27 21:09:34 -05:00
commit 1b39301d8c
248 changed files with 125888 additions and 118062 deletions
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33
.github/ci/build.sh vendored
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@ -2,7 +2,7 @@
## on push branch~=gh-readonly-queue/main/.* ## on push branch~=gh-readonly-queue/main/.*
## on pull_request ## on pull_request
set -euo pipefail set -euxo pipefail
export RUSTUP_HOME=/ci/cache/rustup export RUSTUP_HOME=/ci/cache/rustup
export CARGO_HOME=/ci/cache/cargo export CARGO_HOME=/ci/cache/cargo
@ -13,4 +13,35 @@ hashtime save /ci/cache/filetime.json
cargo fmt -- --check cargo fmt -- --check
# clone stm32-data-generated at the merge base
# so the diff will show this PR's effect
git remote add upstream https://github.com/embassy-rs/stm32-data
git fetch --depth 1 upstream main
git clone --depth 1 --branch stm32-data-$(git merge-base HEAD upstream/main) https://github.com/embassy-rs/stm32-data-generated/ build
./d ci ./d ci
# upload diff
(
cd build
git add .
git diff --staged --color data | aha --black > /ci/artifacts/diff.html
)
# upload generated data to a fake git repo at
# https://ci.embassy.dev/jobs/$ID/artifacts/generated.git
# this allows testing the corresponding embassy-stm32 PR before merging the stm32-data one.
(
cd build
rm -rf .git
git init
git add .
git commit -m 'generated'
git gc # makes cloning faster
git update-server-info # generate .git/info/refs
mv .git /ci/artifacts/generated.git
)
cat > /ci/comment.md <<EOF
diff: https://ci.embassy.dev/jobs/$(jq -r .id < /ci/job.json)/artifacts/diff.html
EOF

2
.github/ci/generated.sh vendored
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@ -12,7 +12,7 @@ export CARGO_TARGET_DIR=/ci/cache/target
hashtime restore /ci/cache/filetime.json || true hashtime restore /ci/cache/filetime.json || true
hashtime save /ci/cache/filetime.json hashtime save /ci/cache/filetime.json
git clone https://github.com/embassy-rs/stm32-data-generated/ build git clone --depth 1 https://github.com/embassy-rs/stm32-data-generated/ build
./d ci ./d ci
COMMIT=$(git rev-parse HEAD) COMMIT=$(git rev-parse HEAD)

2
README.md
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@ -97,7 +97,7 @@ are only interested in one. It's easier than it looks, and doing all families at
- Cleanup the register yamls (see below). - Cleanup the register yamls (see below).
- Minimize the diff between each pair of versions. For example between `lpuart_v1.yaml` and `lpuart_v2.yaml`. If one is missing enums or descriptions, copy it from another. - Minimize the diff between each pair of versions. For example between `lpuart_v1.yaml` and `lpuart_v2.yaml`. If one is missing enums or descriptions, copy it from another.
- Make sure the block - Make sure the block
- Add entries to [`perimap`](https://github.com/embassy-rs/stm32-data/blob/main/stm32data/__main__.py#L84), see below. - Add entries to [`perimap`](https://github.com/embassy-rs/stm32-data/blob/main/stm32-data-gen/src/chips.rs#L109), see below.
- Regen, check `data/chips/*.yaml` has the right `block: lpuart_vX/LPUART` fields - Regen, check `data/chips/*.yaml` has the right `block: lpuart_vX/LPUART` fields
Please separate manual changes and changes resulting from regen in separate commits. It helps tremendously with review and rebasing/merging. Please separate manual changes and changes resulting from regen in separate commits. It helps tremendously with review and rebasing/merging.

2
d
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@ -11,7 +11,7 @@ case "$CMD" in
rm -rf ./sources/ rm -rf ./sources/
git clone https://github.com/embassy-rs/stm32-data-sources.git ./sources/ git clone https://github.com/embassy-rs/stm32-data-sources.git ./sources/
cd ./sources/ cd ./sources/
git checkout ca89656b git checkout a2062c088cf299bd3dc5128eeaa96e07fff2087c
;; ;;
install-chiptool) install-chiptool)
cargo install --git https://github.com/embassy-rs/chiptool cargo install --git https://github.com/embassy-rs/chiptool

2
d.ps1
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@ -12,7 +12,7 @@ Switch ($CMD)
rm -r -Force ./sources/ -ErrorAction SilentlyContinue rm -r -Force ./sources/ -ErrorAction SilentlyContinue
git clone https://github.com/embassy-rs/stm32-data-sources.git ./sources/ git clone https://github.com/embassy-rs/stm32-data-sources.git ./sources/
cd ./sources/ cd ./sources/
git checkout ca89656b git checkout a2062c088cf299bd3dc5128eeaa96e07fff2087c
cd .. cd ..
} }
"install-chiptool" { "install-chiptool" {

50
data/dmamux/WBA_GPDMA1.yaml Normal file
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@ -0,0 +1,50 @@
ADC4: 0
SPI1_RX: 1
SPI1_TX: 2
SPI3_RX: 3
SPI3_TX: 4
I2C1_RX: 5
I2C1_TX: 6
I2C1_EVC: 7
I2C3_RX: 8
I2C3_TX: 9
I2C3_EVC: 10
USART1_RX: 11
USART1_TX: 12
USART2_RX: 13
USART2_TX: 14
LPUART1_RX: 15
LPUART1_TX: 16
TIM1_CC1: 19
TIM1_CC2: 20
TIM1_CC3: 21
TIM1_CC4: 22
TIM1_UPD: 23
TIM1_TRG: 24
TIM1_COM: 25
TIM2_CC1: 26
TIM2_CC2: 27
TIM2_CC3: 28
TIM2_CC4: 29
TIM2_UPD: 30
TIM3_CC1: 31
TIM3_CC2: 32
TIM3_CC3: 33
TIM3_CC4: 34
TIM3_UPD: 35
TIM3_TRG: 36
TIM16_CC1: 37
TIM16_UPD: 38
TIM17_CC1: 39
TIM17_UPD: 40
AES_IN: 41
AES_OUT: 42
HASH_IN: 43
SAES_IN: 44
SAES_OUT: 45
LPTIM1_IC1: 46
LPTIM1_IC2: 47
LPTIM1_UE: 48
LPTIM2_IC1: 49
LPTIM2_IC2: 50
LPTIM2_UE: 51

8
data/extra/family/STM32F3.yaml Normal file
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@ -0,0 +1,8 @@
---
peripherals:
- name: VREFINTCAL
address: 0x1FFFF7BA
registers:
kind: vrefintcal
version: v1
block: VREFINTCAL

691
data/registers/adc_f1.yaml
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@ -1,400 +1,399 @@
---
block/ADC: block/ADC:
description: Analog-to-digital converter description: Analog-to-digital converter
items: items:
- name: SR - name: SR
description: status register description: status register
byte_offset: 0 byte_offset: 0
fieldset: SR fieldset: SR
- name: CR1 - name: CR1
description: control register 1 description: control register 1
byte_offset: 4 byte_offset: 4
fieldset: CR1 fieldset: CR1
- name: CR2 - name: CR2
description: control register 2 description: control register 2
byte_offset: 8 byte_offset: 8
fieldset: CR2 fieldset: CR2
- name: SMPR1 - name: SMPR1
description: sample time register 1 description: sample time register 1
byte_offset: 12 byte_offset: 12
fieldset: SMPR1 fieldset: SMPR1
- name: SMPR2 - name: SMPR2
description: sample time register 2 description: sample time register 2
byte_offset: 16 byte_offset: 16
fieldset: SMPR2 fieldset: SMPR2
- name: JOFR - name: JOFR
description: injected channel data offset register x description: injected channel data offset register x
array: array:
len: 4 len: 4
stride: 4 stride: 4
byte_offset: 20 byte_offset: 20
fieldset: JOFR fieldset: JOFR
- name: HTR - name: HTR
description: watchdog higher threshold register description: watchdog higher threshold register
byte_offset: 36 byte_offset: 36
fieldset: HTR fieldset: HTR
- name: LTR - name: LTR
description: watchdog lower threshold register description: watchdog lower threshold register
byte_offset: 40 byte_offset: 40
fieldset: LTR fieldset: LTR
- name: SQR1 - name: SQR1
description: regular sequence register 1 description: regular sequence register 1
byte_offset: 44 byte_offset: 44
fieldset: SQR1 fieldset: SQR1
- name: SQR2 - name: SQR2
description: regular sequence register 2 description: regular sequence register 2
byte_offset: 48 byte_offset: 48
fieldset: SQR2 fieldset: SQR2
- name: SQR3 - name: SQR3
description: regular sequence register 3 description: regular sequence register 3
byte_offset: 52 byte_offset: 52
fieldset: SQR3 fieldset: SQR3
- name: JSQR - name: JSQR
description: injected sequence register description: injected sequence register
byte_offset: 56 byte_offset: 56
fieldset: JSQR fieldset: JSQR
- name: JDR - name: JDR
description: injected data register x description: injected data register x
array: array:
len: 4 len: 4
stride: 4 stride: 4
byte_offset: 60 byte_offset: 60
access: Read access: Read
fieldset: JDR fieldset: JDR
- name: DR - name: DR
description: regular data register description: regular data register
byte_offset: 76 byte_offset: 76
access: Read access: Read
fieldset: DR fieldset: DR
fieldset/CR1: fieldset/CR1:
description: control register 1 description: control register 1
fields: fields:
- name: AWDCH - name: AWDCH
description: Analog watchdog channel select bits description: Analog watchdog channel select bits
bit_offset: 0 bit_offset: 0
bit_size: 5 bit_size: 5
- name: EOCIE - name: EOCIE
description: Interrupt enable for EOC description: Interrupt enable for EOC
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: AWDIE - name: AWDIE
description: Analog watchdog interrupt enable description: Analog watchdog interrupt enable
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: JEOCIE - name: JEOCIE
description: Interrupt enable for injected channels description: Interrupt enable for injected channels
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: SCAN - name: SCAN
description: Scan mode description: Scan mode
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: AWDSGL - name: AWDSGL
description: Enable the watchdog on a single channel in scan mode description: Enable the watchdog on a single channel in scan mode
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: JAUTO - name: JAUTO
description: Automatic injected group conversion description: Automatic injected group conversion
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: DISCEN - name: DISCEN
description: Discontinuous mode on regular channels description: Discontinuous mode on regular channels
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: JDISCEN - name: JDISCEN
description: Discontinuous mode on injected channels description: Discontinuous mode on injected channels
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: DISCNUM - name: DISCNUM
description: Discontinuous mode channel count description: Discontinuous mode channel count
bit_offset: 13 bit_offset: 13
bit_size: 3 bit_size: 3
- name: DUALMOD - name: DUALMOD
description: Dual mode selection description: Dual mode selection
bit_offset: 16 bit_offset: 16
bit_size: 4 bit_size: 4
enum: DUALMOD enum: DUALMOD
- name: JAWDEN - name: JAWDEN
description: Analog watchdog enable on injected channels description: Analog watchdog enable on injected channels
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: AWDEN - name: AWDEN
description: Analog watchdog enable on regular channels description: Analog watchdog enable on regular channels
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
fieldset/CR2: fieldset/CR2:
description: control register 2 description: control register 2
fields: fields:
- name: ADON - name: ADON
description: A/D Converter ON / OFF description: A/D Converter ON / OFF
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: CONT - name: CONT
description: Continuous conversion description: Continuous conversion
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: CAL - name: CAL
description: A/D Calibration description: A/D Calibration
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: RSTCAL - name: RSTCAL
description: Reset calibration description: Reset calibration
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: DMA - name: DMA
description: Direct memory access mode (for single ADC mode) description: Direct memory access mode (for single ADC mode)
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: ALIGN - name: ALIGN
description: Data alignment description: Data alignment
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: JEXTSEL - name: JEXTSEL
description: External event select for injected group description: External event select for injected group
bit_offset: 12 bit_offset: 12
bit_size: 3 bit_size: 3
enum: EXTSEL enum: EXTSEL
- name: JEXTTRIG - name: JEXTTRIG
description: External trigger conversion mode for injected channels description: External trigger conversion mode for injected channels
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: EXTSEL - name: EXTSEL
description: External event select for regular group description: External event select for regular group
bit_offset: 17 bit_offset: 17
bit_size: 3 bit_size: 3
enum: EXTSEL enum: EXTSEL
- name: EXTTRIG - name: EXTTRIG
description: External trigger conversion mode for regular channels description: External trigger conversion mode for regular channels
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
- name: JSWSTART - name: JSWSTART
description: Start conversion of injected channels description: Start conversion of injected channels
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: SWSTART - name: SWSTART
description: Start conversion of regular channels description: Start conversion of regular channels
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: TSVREFE - name: TSVREFE
description: Temperature sensor and VREFINT enable description: Temperature sensor and VREFINT enable
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
fieldset/DR: fieldset/DR:
description: regular data register description: regular data register
fields: fields:
- name: DATA - name: DATA
description: Regular data description: Regular data
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
- name: ADC2DATA - name: ADC2DATA
description: ADC2 data description: ADC2 data
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16
fieldset/HTR: fieldset/HTR:
description: watchdog higher threshold register description: watchdog higher threshold register
fields: fields:
- name: HT - name: HT
description: Analog watchdog higher threshold description: Analog watchdog higher threshold
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
fieldset/JDR: fieldset/JDR:
description: injected data register x description: injected data register x
fields: fields:
- name: JDATA - name: JDATA
description: Injected data description: Injected data
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
fieldset/JOFR: fieldset/JOFR:
description: injected channel data offset register x description: injected channel data offset register x
fields: fields:
- name: JOFFSET - name: JOFFSET
description: Data offset for injected channel x description: Data offset for injected channel x
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
fieldset/JSQR: fieldset/JSQR:
description: injected sequence register description: injected sequence register
fields: fields:
- name: JSQ - name: JSQ
description: 1st conversion in injected sequence description: 1st conversion in injected sequence
bit_offset: 0 bit_offset: 0
bit_size: 5 bit_size: 5
array: array:
len: 4 len: 4
stride: 5 stride: 5
- name: JL - name: JL
description: Injected sequence length description: Injected sequence length
bit_offset: 20 bit_offset: 20
bit_size: 2 bit_size: 2
fieldset/LTR: fieldset/LTR:
description: watchdog lower threshold register description: watchdog lower threshold register
fields: fields:
- name: LT - name: LT
description: Analog watchdog lower threshold description: Analog watchdog lower threshold
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
fieldset/SMPR1: fieldset/SMPR1:
description: sample time register 1 description: sample time register 1
fields: fields:
- name: SMP - name: SMP
description: Channel x sample time selection description: Channel x sample time selection
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
array: array:
len: 8 len: 8
stride: 3 stride: 3
enum: SAMPLE_TIME enum: SAMPLE_TIME
fieldset/SMPR2: fieldset/SMPR2:
description: sample time register 2 description: sample time register 2
fields: fields:
- name: SMP - name: SMP
description: Channel 0 sampling time selection description: Channel 0 sampling time selection
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
array: array:
len: 10 len: 10
stride: 3 stride: 3
enum: SAMPLE_TIME enum: SAMPLE_TIME
fieldset/SQR1: fieldset/SQR1:
description: regular sequence register 1 description: regular sequence register 1
fields: fields:
- name: SQ - name: SQ
description: 13th to 16th conversion in regular sequence description: 13th to 16th conversion in regular sequence
bit_offset: 0 bit_offset: 0
bit_size: 5 bit_size: 5
array: array:
len: 4 len: 4
stride: 5 stride: 5
- name: L - name: L
description: Regular channel sequence length description: Regular channel sequence length
bit_offset: 20 bit_offset: 20
bit_size: 4 bit_size: 4
fieldset/SQR2: fieldset/SQR2:
description: regular sequence register 2 description: regular sequence register 2
fields: fields:
- name: SQ - name: SQ
description: 7th to 12th conversion in regular sequence description: 7th to 12th conversion in regular sequence
bit_offset: 0 bit_offset: 0
bit_size: 5 bit_size: 5
array: array:
len: 6 len: 6
stride: 5 stride: 5
fieldset/SQR3: fieldset/SQR3:
description: regular sequence register 3 description: regular sequence register 3
fields: fields:
- name: SQ - name: SQ
description: 1st to 6th conversion in regular sequence description: 1st to 6th conversion in regular sequence
bit_offset: 0 bit_offset: 0
bit_size: 5 bit_size: 5
array: array:
len: 6 len: 6
stride: 5 stride: 5
fieldset/SR: fieldset/SR:
description: status register description: status register
fields: fields:
- name: AWD - name: AWD
description: Analog watchdog flag description: Analog watchdog flag
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: EOC - name: EOC
description: Regular channel end of conversion description: Regular channel end of conversion
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: JEOC - name: JEOC
description: Injected channel end of conversion description: Injected channel end of conversion
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: JSTRT - name: JSTRT
description: Injected channel start flag description: Injected channel start flag
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: STRT - name: STRT
description: Regular channel start flag description: Regular channel start flag
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum/DUALMOD: enum/DUALMOD:
bit_size: 4 bit_size: 4
variants: variants:
- name: Independent - name: Independent
description: Independent mode. description: Independent mode.
value: 0 value: 0
- name: RegularInjected - name: RegularInjected
description: Combined regular simultaneous + injected simultaneous mode description: Combined regular simultaneous + injected simultaneous mode
value: 1 value: 1
- name: RegularAlternateTrigger - name: RegularAlternateTrigger
description: Combined regular simultaneous + alternate trigger mode description: Combined regular simultaneous + alternate trigger mode
value: 2 value: 2
- name: InjectedFastInterleaved - name: InjectedFastInterleaved
description: Combined injected simultaneous + fast interleaved mode description: Combined injected simultaneous + fast interleaved mode
value: 3 value: 3
- name: InjectedSlowInterleaved - name: InjectedSlowInterleaved
description: Combined injected simultaneous + slow Interleaved mode description: Combined injected simultaneous + slow Interleaved mode
value: 4 value: 4
- name: Injected - name: Injected
description: Injected simultaneous mode only description: Injected simultaneous mode only
value: 5 value: 5
- name: Regular - name: Regular
description: Regular simultaneous mode only description: Regular simultaneous mode only
value: 6 value: 6
- name: FastInterleaved - name: FastInterleaved
description: Fast interleaved mode only description: Fast interleaved mode only
value: 7 value: 7
- name: SlowInterleaved - name: SlowInterleaved
description: Slow interleaved mode only description: Slow interleaved mode only
value: 8 value: 8
- name: AlternateTrigger - name: AlternateTrigger
description: Alternate trigger mode only description: Alternate trigger mode only
value: 9 value: 9
enum/EXTSEL: enum/EXTSEL:
bit_size: 3 bit_size: 3
variants: variants:
- name: TIM1TRGO - name: TIM1TRGO
description: Timer 1 TRGO event description: Timer 1 TRGO event
value: 0 value: 0
- name: TIM1CC4 - name: TIM1CC4
description: Timer 1 CC4 event description: Timer 1 CC4 event
value: 1 value: 1
- name: TIM2TRGO - name: TIM2TRGO
description: Timer 2 TRGO event description: Timer 2 TRGO event
value: 2 value: 2
- name: TIM2CC1 - name: TIM2CC1
description: Timer 2 CC1 event description: Timer 2 CC1 event
value: 3 value: 3
- name: TIM3CC4 - name: TIM3CC4
description: Timer 3 CC4 event description: Timer 3 CC4 event
value: 4 value: 4
- name: TIM4TRGO - name: TIM4TRGO
description: Timer 4 TRGO event description: Timer 4 TRGO event
value: 5 value: 5
- name: TIM8CC4 - name: TIM8CC4
description: EXTI line 15/Timer 8 CC4 event description: EXTI line 15/Timer 8 CC4 event
value: 6 value: 6
- name: SWSTART - name: SWSTART
description: SWSTART description: SWSTART
value: 7 value: 7
enum/SAMPLE_TIME: enum/SAMPLE_TIME:
bit_size: 3 bit_size: 3
variants: variants:
- name: Cycles1_5 - name: Cycles1_5
description: 1.5 cycles description: 1.5 cycles
value: 0 value: 0
- name: Cycles7_5 - name: Cycles7_5
description: 7.5 cycles description: 7.5 cycles
value: 1 value: 1
- name: Cycles13_5 - name: Cycles13_5
description: 13.5 cycles description: 13.5 cycles
value: 2 value: 2
- name: Cycles28_5 - name: Cycles28_5
description: 28.5 cycles description: 28.5 cycles
value: 3 value: 3
- name: Cycles41_5 - name: Cycles41_5
description: 41.5 cycles description: 41.5 cycles
value: 4 value: 4
- name: Cycles55_5 - name: Cycles55_5
description: 55.5 cycles description: 55.5 cycles
value: 5 value: 5
- name: Cycles71_5 - name: Cycles71_5
description: 71.5 cycles description: 71.5 cycles
value: 6 value: 6
- name: Cycles239_5 - name: Cycles239_5
description: 239.5 cycles description: 239.5 cycles
value: 7 value: 7

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data/registers/adc_f3.yaml
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610
data/registers/adc_f3_v2.yaml Normal file
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@ -0,0 +1,610 @@
block/ADC:
description: Analog-to-Digital Converter
items:
- name: SR
description: status register
byte_offset: 0
fieldset: SR
- name: CR1
description: control register 1
byte_offset: 4
fieldset: CR1
- name: CR2
description: control register 2
byte_offset: 8
fieldset: CR2
- name: SMPR1
description: sample time register 1
byte_offset: 12
fieldset: SMPR1
- name: SMPR2
description: sample time register 2
byte_offset: 16
fieldset: SMPR2
- name: JOFR1
description: injected channel data offset register 1
byte_offset: 20
fieldset: JOFR1
- name: JOFR2
description: injected channel data offset register 2
byte_offset: 24
fieldset: JOFR2
- name: JOFR3
description: injected channel data offset register 3
byte_offset: 28
fieldset: JOFR3
- name: JOFR4
description: injected channel data offset register 4
byte_offset: 32
fieldset: JOFR4
- name: HTR
description: watchdog higher threshold register
byte_offset: 36
fieldset: HTR
- name: LTR
description: watchdog lower threshold register
byte_offset: 40
fieldset: LTR
- name: SQR1
description: regular sequence register 1
byte_offset: 44
fieldset: SQR1
- name: SQR2
description: regular sequence register 2
byte_offset: 48
fieldset: SQR2
- name: SQR3
description: regular sequence register 3
byte_offset: 52
fieldset: SQR3
- name: JSQR
description: injected sequence register
byte_offset: 56
fieldset: JSQR
- name: JDR1
description: injected data register 1
byte_offset: 60
access: Read
fieldset: JDR1
- name: JDR2
description: injected data register 2
byte_offset: 64
access: Read
fieldset: JDR2
- name: JDR3
description: injected data register 3
byte_offset: 68
access: Read
fieldset: JDR3
- name: JDR4
description: injected data register 4
byte_offset: 72
access: Read
fieldset: JDR4
- name: DR
description: regular data register
byte_offset: 76
access: Read
fieldset: DR
fieldset/CR1:
description: control register 1
fields:
- name: AWDCH
description: analog watchdog channel select bits
bit_offset: 0
bit_size: 5
- name: EOCIE
description: interrupt enable for EOC
bit_offset: 5
bit_size: 1
- name: AWDIE
description: analog watchdog interrupt enable
bit_offset: 6
bit_size: 1
- name: JEOCIE
description: interrupt enable for injected channels
bit_offset: 7
bit_size: 1
- name: SCAN
description: scan mode
bit_offset: 8
bit_size: 1
- name: AWDSGL
description: enable the watchdog on a single channel in scan mode
bit_offset: 9
bit_size: 1
- name: JAUTO
description: automatic injected group conversion
bit_offset: 10
bit_size: 1
- name: DISCEN
description: discontinuous mode on regular channels
bit_offset: 11
bit_size: 1
- name: JDISCEN
description: discontinuous mode on injected channels
bit_offset: 12
bit_size: 1
- name: DISCNUM
description: discontinuous mode channel count
bit_offset: 13
bit_size: 3
enum: DISCNUM
- name: JAWDEN
description: analog watchdog enable on injected channels
bit_offset: 22
bit_size: 1
- name: AWDEN
description: analog watchdog enable on regular channels
bit_offset: 23
bit_size: 1
fieldset/CR2:
description: control register 2
fields:
- name: ADON
description: A/D converter ON / OFF
bit_offset: 0
bit_size: 1
- name: CONT
description: continuous conversion
bit_offset: 1
bit_size: 1
- name: CAL
description: A/D calibration
bit_offset: 2
bit_size: 1
- name: RSTCAL
description: reset calibration
bit_offset: 3
bit_size: 1
- name: DMA
description: DMA disable selection (for single ADC mode)
bit_offset: 8
bit_size: 1
- name: ALIGN
description: data alignment
bit_offset: 11
bit_size: 1
- name: JEXTSEL
description: external event select for injected group
bit_offset: 12
bit_size: 3
enum: JEXTSEL
- name: JEXTTRIG
description: external trigger conversion mode for injected channels
bit_offset: 15
bit_size: 1
- name: EXTSEL
description: external event select for regular group
bit_offset: 17
bit_size: 3
enum: EXTSEL
- name: EXTTRIG
description: external trigger conversion mode for regular channels
bit_offset: 20
bit_size: 1
- name: JSWSTART
description: start conversion of injected channels
bit_offset: 21
bit_size: 1
- name: SWSTART
description: start conversion of regular channels
bit_offset: 22
bit_size: 1
- name: TSVREFE
description: temperature sensor and VREFINT enable
bit_offset: 23
bit_size: 1
fieldset/DR:
description: regular data register
fields:
- name: DATA
description: Regular data
bit_offset: 0
bit_size: 16
fieldset/HTR:
description: watchdog higher threshold register
fields:
- name: HT
description: Analog watchdog high threshold
bit_offset: 0
bit_size: 12
fieldset/JDR1:
description: injected data register 1
fields:
- name: JDATA1
description: Injected data
bit_offset: 0
bit_size: 16
fieldset/JDR2:
description: injected data register 2
fields:
- name: JDATA2
description: Injected data
bit_offset: 0
bit_size: 16
fieldset/JDR3:
description: injected data register 3
fields:
- name: JDATA3
description: Injected data
bit_offset: 0
bit_size: 16
fieldset/JDR4:
description: injected data register 4
fields:
- name: JDATA4
description: Injected data
bit_offset: 0
bit_size: 16
fieldset/JOFR1:
description: injected channel data offset register 1
fields:
- name: JOFFSET1
description: data offset for injected channel 1
bit_offset: 0
bit_size: 12
fieldset/JOFR2:
description: injected channel data offset register 2
fields:
- name: JOFFSET2
description: data offset for injected channel 2
bit_offset: 0
bit_size: 12
fieldset/JOFR3:
description: injected channel data offset register 3
fields:
- name: JOFFSET3
description: data offset for injected channel 3
bit_offset: 0
bit_size: 12
fieldset/JOFR4:
description: injected channel data offset register 4
fields:
- name: JOFFSET4
description: data offset for injected channel 4
bit_offset: 0
bit_size: 12
fieldset/JSQR:
description: injected sequence register
fields:
- name: JSQ1
description: 1st conversion in injected sequence
bit_offset: 0
bit_size: 5
- name: JSQ2
description: 2nd conversion in injected sequence
bit_offset: 5
bit_size: 5
- name: JSQ3
description: 3rd conversion in injected sequence
bit_offset: 10
bit_size: 5
- name: JSQ4
description: 4th conversion in injected sequence
bit_offset: 15
bit_size: 5
- name: JL
description: injected sequence length
bit_offset: 20
bit_size: 2
fieldset/LTR:
description: watchdog lower threshold register
fields:
- name: LT
description: Analog watchdog low threshold
bit_offset: 0
bit_size: 12
fieldset/SMPR1:
description: sample time register 1
fields:
- name: SMP10
description: channel 10 sampling time selection
bit_offset: 0
bit_size: 3
enum: SAMPLE_TIME
- name: SMP11
description: channel 11 sampling time selection
bit_offset: 3
bit_size: 3
enum: SAMPLE_TIME
- name: SMP12
description: channel 12 sampling time selection
bit_offset: 6
bit_size: 3
enum: SAMPLE_TIME
- name: SMP13
description: channel 13 sampling time selection
bit_offset: 9
bit_size: 3
enum: SAMPLE_TIME
- name: SMP14
description: channel 14 sampling time selection
bit_offset: 12
bit_size: 3
enum: SAMPLE_TIME
- name: SMP15
description: channel 15 sampling time selection
bit_offset: 15
bit_size: 3
enum: SAMPLE_TIME
- name: SMP16
description: channel 16 sampling time selection
bit_offset: 18
bit_size: 3
enum: SAMPLE_TIME
- name: SMP17
description: channel 17 sampling time selection
bit_offset: 21
bit_size: 3
enum: SAMPLE_TIME
- name: SMP18
description: channel 18 sampling time selection
bit_offset: 24
bit_size: 3
enum: SAMPLE_TIME
fieldset/SMPR2:
description: sample time register 2
fields:
- name: SMP0
description: channel 0 sampling time selection
bit_offset: 0
bit_size: 3
enum: SAMPLE_TIME
- name: SMP1
description: channel 1 sampling time selection
bit_offset: 3
bit_size: 3
enum: SAMPLE_TIME
- name: SMP2
description: channel 2 sampling time selection
bit_offset: 6
bit_size: 3
enum: SAMPLE_TIME
- name: SMP3
description: channel 3 sampling time selection
bit_offset: 9
bit_size: 3
enum: SAMPLE_TIME
- name: SMP4
description: channel 4 sampling time selection
bit_offset: 12
bit_size: 3
enum: SAMPLE_TIME
- name: SMP5
description: channel 5 sampling time selection
bit_offset: 15
bit_size: 3
enum: SAMPLE_TIME
- name: SMP6
description: channel 6 sampling time selection
bit_offset: 18
bit_size: 3
enum: SAMPLE_TIME
- name: SMP7
description: channel 7 sampling time selection
bit_offset: 21
bit_size: 3
enum: SAMPLE_TIME
- name: SMP8
description: channel 8 sampling time selection
bit_offset: 24
bit_size: 3
enum: SAMPLE_TIME
- name: SMP9
description: channel 9 sampling time selection
bit_offset: 27
bit_size: 3
enum: SAMPLE_TIME
fieldset/SQR1:
description: regular sequence register 1
fields:
- name: SQ13
description: 13th conversion in regular sequence
bit_offset: 0
bit_size: 5
- name: SQ14
description: 14th conversion in regular sequence
bit_offset: 5
bit_size: 5
- name: SQ15
description: 15th conversion in regular sequence
bit_offset: 10
bit_size: 5
- name: SQ16
description: 16th conversion in regular sequence
bit_offset: 15
bit_size: 5
- name: L
description: regular channel sequence length
bit_offset: 20
bit_size: 4
fieldset/SQR2:
description: regular sequence register 2
fields:
- name: SQ7
description: 7th conversion in regular sequence
bit_offset: 0
bit_size: 5
- name: SQ8
description: 8th conversion in regular sequence
bit_offset: 5
bit_size: 5
- name: SQ9
description: 9th conversion in regular sequence
bit_offset: 10
bit_size: 5
- name: SQ10
description: 10th conversion in regular sequence
bit_offset: 15
bit_size: 5
- name: SQ11
description: 11th conversion in regular sequence
bit_offset: 20
bit_size: 5
- name: SQ12
description: 12th conversion in regular sequence
bit_offset: 25
bit_size: 5
fieldset/SQR3:
description: regular sequence register 3
fields:
- name: SQ1
description: 1st conversion in regular sequence
bit_offset: 0
bit_size: 5
- name: SQ2
description: 2nd conversion in regular sequence
bit_offset: 5
bit_size: 5
- name: SQ3
description: 3rd conversion in regular sequence
bit_offset: 10
bit_size: 5
- name: SQ4
description: 4th conversion in regular sequence
bit_offset: 15
bit_size: 5
- name: SQ5
description: 5th conversion in regular sequence
bit_offset: 20
bit_size: 5
- name: SQ6
description: 6th conversion in regular sequence
bit_offset: 25
bit_size: 5
fieldset/SR:
description: status register
fields:
- name: AWD
description: analog watchdog flag
bit_offset: 0
bit_size: 1
- name: EOC
description: end of conversion
bit_offset: 1
bit_size: 1
- name: JEOC
description: injected channel end of conversion
bit_offset: 2
bit_size: 1
- name: JSTRT
description: injected channel start flag
bit_offset: 3
bit_size: 1
- name: STRT
description: regular channel start flag
bit_offset: 4
bit_size: 1
- name: OVR
description: overrun
bit_offset: 5
bit_size: 1
enum/DISCNUM:
bit_size: 3
variants:
- name: DISCNUM_1
description: 1 conversions are discontinued and the conversion is carried out on one channel
value: 0
- name: DISCNUM_2
description: 2 conversion is discontinued and the conversions are carried out on 2 channels
value: 1
- name: DISCNUM_3
description: 3 conversions are discontinued and the conversions are carried out on 3 channels
value: 2
- name: DISCNUM_4
description: 4 conversions are discontinued and the conversions are carried out on 4 channels
value: 3
- name: DISCNUM_5
description: 5 conversions are discontinued and the conversions are carried out on 5 channels
value: 4
- name: DISCNUM_6
description: 6 conversions are discontinued and the conversions are carried out on 6 channels
value: 5
- name: DISCNUM_7
description: 7 conversions are discontinued and the conversions are carried out on 7 channels
value: 6
- name: DISCNUM_8
description: 8 conversions are discontinued and the conversions are carried out on 8 channels
value: 7
enum/EXTSEL:
bit_size: 3
variants:
- name: TIM19_TRGO
description: Timer 19 TRGO event
value: 0
- name: TIM19_CC3
description: Timer 19 CC3 event
value: 1
- name: TIM19_CC4
description: Timer 19 CC4 event
value: 2
- name: TIM2_CC2
description: Timer 2 CC2 event
value: 3
- name: TIM3_TRGO
description: Timer 3 TRGO event
value: 4
- name: TIM4_CC4
description: Timer 4 CC4 event
value: 5
- name: EXTI_LINE11
description: External interrupt line 11
value: 6
- name: SWSTART
description: SWSTART bit
value: 7
enum/JEXTSEL:
bit_size: 3
variants:
- name: TIM19_CC1
description: Timer 19 CC1 event
value: 0
- name: TIM19_CC2
description: Timer 19 CC2 event
value: 1
- name: TIM2_TRGO
description: Timer 2 TRGO event
value: 2
- name: TIM2_CC1
description: Timer 2 CC1 event
value: 3
- name: TIM3_CC4
description: Timer 3 CC4 event
value: 4
- name: TIM4_TRGO
description: Timer 4 TRGO event
value: 5
- name: EXTI_LINE15
description: External interrupt line 15
value: 6
- name: JSWSTART
description: JSWSTART bit
value: 7
enum/SAMPLE_TIME:
bit_size: 3
variants:
- name: Cycles1_5
description: 1.5 ADC clock cycles
value: 0
- name: Cycles7_5
description: 7.5 ADC clock cycles
value: 1
- name: Cycles13_5
description: 13.5 ADC clock cycles
value: 2
- name: Cycles28_5
description: 28.5 ADC clock cycles
value: 3
- name: Cycles41_5
description: 41.5 ADC clock cycles
value: 4
- name: Cycles55_5
description: 55.5 ADC clock cycles
value: 5
- name: Cycles71_5
description: 71.5 ADC clock cycles
value: 6
- name: Cycles239_5
description: 239.5 ADC clock cycles
value: 7

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data/registers/adc_g0.yaml
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data/registers/adc_v1.yaml
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@ -1,384 +1,383 @@
---
block/ADC: block/ADC:
description: Analog-to-digital converter description: Analog-to-digital converter
items: items:
- name: ISR - name: ISR
description: interrupt and status register description: interrupt and status register
byte_offset: 0 byte_offset: 0
fieldset: ISR fieldset: ISR
- name: IER - name: IER
description: interrupt enable register description: interrupt enable register
byte_offset: 4 byte_offset: 4
fieldset: IER fieldset: IER
- name: CR - name: CR
description: control register description: control register
byte_offset: 8 byte_offset: 8
fieldset: CR fieldset: CR
- name: CFGR1 - name: CFGR1
description: configuration register 1 description: configuration register 1
byte_offset: 12 byte_offset: 12
fieldset: CFGR1 fieldset: CFGR1
- name: CFGR2 - name: CFGR2
description: configuration register 2 description: configuration register 2
byte_offset: 16 byte_offset: 16
fieldset: CFGR2 fieldset: CFGR2
- name: SMPR - name: SMPR
description: sampling time register description: sampling time register
byte_offset: 20 byte_offset: 20
fieldset: SMPR fieldset: SMPR
- name: TR - name: TR
description: watchdog threshold register description: watchdog threshold register
byte_offset: 32 byte_offset: 32
fieldset: TR fieldset: TR
- name: CHSELR - name: CHSELR
description: channel selection register description: channel selection register
byte_offset: 40 byte_offset: 40
fieldset: CHSELR fieldset: CHSELR
- name: DR - name: DR
description: data register description: data register
byte_offset: 64 byte_offset: 64
access: Read access: Read
fieldset: DR fieldset: DR
- name: CCR - name: CCR
description: common configuration register description: common configuration register
byte_offset: 776 byte_offset: 776
fieldset: CCR fieldset: CCR
fieldset/CCR: fieldset/CCR:
description: common configuration register description: common configuration register
fields: fields:
- name: VREFEN - name: VREFEN
description: Temperature sensor and VREFINT enable description: Temperature sensor and VREFINT enable
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: TSEN - name: TSEN
description: Temperature sensor enable description: Temperature sensor enable
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: VBATEN - name: VBATEN
description: VBAT enable description: VBAT enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
fieldset/CFGR1: fieldset/CFGR1:
description: configuration register 1 description: configuration register 1
fields: fields:
- name: DMAEN - name: DMAEN
description: Direct memory access enable description: Direct memory access enable
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DMACFG - name: DMACFG
description: Direct memery access configuration description: Direct memery access configuration
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
enum: DMACFG enum: DMACFG
- name: SCANDIR - name: SCANDIR
description: Scan sequence direction description: Scan sequence direction
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum: SCANDIR enum: SCANDIR
- name: RES - name: RES
description: Data resolution description: Data resolution
bit_offset: 3 bit_offset: 3
bit_size: 2 bit_size: 2
enum: RES enum: RES
- name: ALIGN - name: ALIGN
description: Data alignment description: Data alignment
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum: ALIGN enum: ALIGN
- name: EXTSEL - name: EXTSEL
description: External trigger selection description: External trigger selection
bit_offset: 6 bit_offset: 6
bit_size: 3 bit_size: 3
enum: EXTSEL enum: EXTSEL
- name: EXTEN - name: EXTEN
description: External trigger enable and polarity selection description: External trigger enable and polarity selection
bit_offset: 10 bit_offset: 10
bit_size: 2 bit_size: 2
enum: EXTEN enum: EXTEN
- name: OVRMOD - name: OVRMOD
description: Overrun management mode description: Overrun management mode
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
enum: OVRMOD enum: OVRMOD
- name: CONT - name: CONT
description: Single / continuous conversion mode description: Single / continuous conversion mode
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: WAIT - name: WAIT
description: Wait conversion mode description: Wait conversion mode
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: AUTOFF - name: AUTOFF
description: Auto-off mode description: Auto-off mode
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: DISCEN - name: DISCEN
description: Discontinuous mode description: Discontinuous mode
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: AWDSGL - name: AWDSGL
description: Enable the watchdog on a single channel or on all channels description: Enable the watchdog on a single channel or on all channels
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
enum: AWDSGL enum: AWDSGL
- name: AWDEN - name: AWDEN
description: Analog watchdog enable description: Analog watchdog enable
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: AWDCH - name: AWDCH
description: Analog watchdog channel selection description: Analog watchdog channel selection
bit_offset: 26 bit_offset: 26
bit_size: 5 bit_size: 5
fieldset/CFGR2: fieldset/CFGR2:
description: configuration register 2 description: configuration register 2
fields: fields:
- name: CKMODE - name: CKMODE
description: ADC clock mode description: ADC clock mode
bit_offset: 30 bit_offset: 30
bit_size: 2 bit_size: 2
enum: CKMODE enum: CKMODE
fieldset/CHSELR: fieldset/CHSELR:
description: channel selection register description: channel selection register
fields: fields:
- name: CHSEL x - name: CHSEL x
description: Channel-x selection description: Channel-x selection
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 19 len: 19
stride: 1 stride: 1
fieldset/CR: fieldset/CR:
description: control register description: control register
fields: fields:
- name: ADEN - name: ADEN
description: ADC enable command description: ADC enable command
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: ADDIS - name: ADDIS
description: ADC disable command description: ADC disable command
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: ADSTART - name: ADSTART
description: ADC start conversion command description: ADC start conversion command
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: ADSTP - name: ADSTP
description: ADC stop conversion command description: ADC stop conversion command
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: ADCAL - name: ADCAL
description: ADC calibration description: ADC calibration
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/DR: fieldset/DR:
description: data register description: data register
fields: fields:
- name: DATA - name: DATA
description: Converted data description: Converted data
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
fieldset/IER: fieldset/IER:
description: interrupt enable register description: interrupt enable register
fields: fields:
- name: ADRDYIE - name: ADRDYIE
description: ADC ready interrupt enable description: ADC ready interrupt enable
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: EOSMPIE - name: EOSMPIE
description: End of sampling flag interrupt enable description: End of sampling flag interrupt enable
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: EOCIE - name: EOCIE
description: End of conversion interrupt enable description: End of conversion interrupt enable
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: EOSEQIE - name: EOSEQIE
description: End of conversion sequence interrupt enable description: End of conversion sequence interrupt enable
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: OVRIE - name: OVRIE
description: Overrun interrupt enable description: Overrun interrupt enable
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: AWDIE - name: AWDIE
description: Analog watchdog interrupt enable description: Analog watchdog interrupt enable
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
fieldset/ISR: fieldset/ISR:
description: interrupt and status register description: interrupt and status register
fields: fields:
- name: ADRDY - name: ADRDY
description: ADC ready description: ADC ready
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: EOSMP - name: EOSMP
description: End of sampling flag description: End of sampling flag
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: EOC - name: EOC
description: End of conversion flag description: End of conversion flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: EOSEQ - name: EOSEQ
description: End of sequence flag description: End of sequence flag
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: OVR - name: OVR
description: ADC overrun description: ADC overrun
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: AWD - name: AWD
description: Analog watchdog flag description: Analog watchdog flag
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
fieldset/SMPR: fieldset/SMPR:
description: sampling time register description: sampling time register
fields: fields:
- name: SMP - name: SMP
description: Sampling time selection description: Sampling time selection
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
enum: SAMPLE_TIME enum: SAMPLE_TIME
fieldset/TR: fieldset/TR:
description: watchdog threshold register description: watchdog threshold register
fields: fields:
- name: LT - name: LT
description: Analog watchdog lower threshold description: Analog watchdog lower threshold
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
- name: HT - name: HT
description: Analog watchdog higher threshold description: Analog watchdog higher threshold
bit_offset: 16 bit_offset: 16
bit_size: 12 bit_size: 12
enum/ALIGN: enum/ALIGN:
bit_size: 1 bit_size: 1
variants: variants:
- name: Right - name: Right
description: Right alignment description: Right alignment
value: 0 value: 0
- name: Left - name: Left
description: Left alignment description: Left alignment
value: 1 value: 1
enum/AWDSGL: enum/AWDSGL:
bit_size: 1 bit_size: 1
variants: variants:
- name: AllChannels - name: AllChannels
description: Analog watchdog enabled on all channels description: Analog watchdog enabled on all channels
value: 0 value: 0
- name: SingleChannel - name: SingleChannel
description: Analog watchdog enabled on a single channel description: Analog watchdog enabled on a single channel
value: 1 value: 1
enum/CKMODE: enum/CKMODE:
bit_size: 2 bit_size: 2
variants: variants:
- name: ADCCLK - name: ADCCLK
description: Asynchronous clock mode description: Asynchronous clock mode
value: 0 value: 0
- name: PCLK_Div2 - name: PCLK_Div2
description: Synchronous clock mode (PCLK/2) description: Synchronous clock mode (PCLK/2)
value: 1 value: 1
- name: PCLK_Div4 - name: PCLK_Div4
description: Sychronous clock mode (PCLK/4) description: Sychronous clock mode (PCLK/4)
value: 2 value: 2
enum/DMACFG: enum/DMACFG:
bit_size: 1 bit_size: 1
variants: variants:
- name: OneShot - name: OneShot
description: DMA one shot mode description: DMA one shot mode
value: 0 value: 0
- name: Circular - name: Circular
description: DMA circular mode description: DMA circular mode
value: 1 value: 1
enum/EXTEN: enum/EXTEN:
bit_size: 2 bit_size: 2
variants: variants:
- name: Disabled - name: Disabled
description: Trigger detection disabled description: Trigger detection disabled
value: 0 value: 0
- name: RisingEdge - name: RisingEdge
description: Trigger detection on the rising edge description: Trigger detection on the rising edge
value: 1 value: 1
- name: FallingEdge - name: FallingEdge
description: Trigger detection on the falling edge description: Trigger detection on the falling edge
value: 2 value: 2
- name: BothEdges - name: BothEdges
description: Trigger detection on both the rising and falling edges description: Trigger detection on both the rising and falling edges
value: 3 value: 3
enum/EXTSEL: enum/EXTSEL:
bit_size: 3 bit_size: 3
variants: variants:
- name: TIM1_TRGO - name: TIM1_TRGO
description: Timer 1 TRGO Event description: Timer 1 TRGO Event
value: 0 value: 0
- name: TIM1_CC4 - name: TIM1_CC4
description: Timer 1 CC4 event description: Timer 1 CC4 event
value: 1 value: 1
- name: TIM2_TRGO - name: TIM2_TRGO
description: Timer 2 TRGO event description: Timer 2 TRGO event
value: 2 value: 2
- name: TIM3_TRGO - name: TIM3_TRGO
description: Timer 3 TRGO event description: Timer 3 TRGO event
value: 3 value: 3
- name: TIM15_TRGO - name: TIM15_TRGO
description: Timer 15 TRGO event description: Timer 15 TRGO event
value: 4 value: 4
enum/OVRMOD: enum/OVRMOD:
bit_size: 1 bit_size: 1
variants: variants:
- name: Preserved - name: Preserved
description: ADC_DR register is preserved with the old data when an overrun is detected description: ADC_DR register is preserved with the old data when an overrun is detected
value: 0 value: 0
- name: Overwritten - name: Overwritten
description: ADC_DR register is overwritten with the last conversion result when an overrun is detected description: ADC_DR register is overwritten with the last conversion result when an overrun is detected
value: 1 value: 1
enum/RES: enum/RES:
bit_size: 2 bit_size: 2
variants: variants:
- name: TwelveBit - name: TwelveBit
description: 12-bit (14 ADCCLK cycles) description: 12-bit (14 ADCCLK cycles)
value: 0 value: 0
- name: TenBit - name: TenBit
description: 10-bit (13 ADCCLK cycles) description: 10-bit (13 ADCCLK cycles)
value: 1 value: 1
- name: EightBit - name: EightBit
description: 8-bit (11 ADCCLK cycles) description: 8-bit (11 ADCCLK cycles)
value: 2 value: 2
- name: SixBit - name: SixBit
description: 6-bit (9 ADCCLK cycles) description: 6-bit (9 ADCCLK cycles)
value: 3 value: 3
enum/SAMPLE_TIME: enum/SAMPLE_TIME:
bit_size: 3 bit_size: 3
variants: variants:
- name: Cycles1_5 - name: Cycles1_5
description: 1.5 cycles description: 1.5 cycles
value: 0 value: 0
- name: Cycles7_5 - name: Cycles7_5
description: 7.5 cycles description: 7.5 cycles
value: 1 value: 1
- name: Cycles13_5 - name: Cycles13_5
description: 13.5 cycles description: 13.5 cycles
value: 2 value: 2
- name: Cycles28_5 - name: Cycles28_5
description: 28.5 cycles description: 28.5 cycles
value: 3 value: 3
- name: Cycles41_5 - name: Cycles41_5
description: 41.5 cycles description: 41.5 cycles
value: 4 value: 4
- name: Cycles55_5 - name: Cycles55_5
description: 55.5 cycles description: 55.5 cycles
value: 5 value: 5
- name: Cycles71_5 - name: Cycles71_5
description: 71.5 cycles description: 71.5 cycles
value: 6 value: 6
- name: Cycles239_5 - name: Cycles239_5
description: 239.5 cycles description: 239.5 cycles
value: 7 value: 7
enum/SCANDIR: enum/SCANDIR:
bit_size: 1 bit_size: 1
variants: variants:
- name: Upward - name: Upward
description: Upward scan (from CHSEL0 to CHSEL18) description: Upward scan (from CHSEL0 to CHSEL18)
value: 0 value: 0
- name: Backward - name: Backward
description: Backward scan (from CHSEL18 to CHSEL0) description: Backward scan (from CHSEL18 to CHSEL0)
value: 1 value: 1

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data/registers/adc_v2.yaml
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---
block/ADC: block/ADC:
description: Analog-to-Digital Converter description: Analog-to-Digital Converter
items: items:
- name: ISR - name: ISR
description: interrupt and status register description: interrupt and status register
byte_offset: 0 byte_offset: 0
fieldset: ISR fieldset: ISR
- name: IER - name: IER
description: interrupt enable register description: interrupt enable register
byte_offset: 4 byte_offset: 4
fieldset: IER fieldset: IER
- name: CR - name: CR
description: control register description: control register
byte_offset: 8 byte_offset: 8
fieldset: CR fieldset: CR
- name: CFGR - name: CFGR
description: configuration register description: configuration register
byte_offset: 12 byte_offset: 12
fieldset: CFGR fieldset: CFGR
- name: CFGR2 - name: CFGR2
description: configuration register description: configuration register
byte_offset: 16 byte_offset: 16
fieldset: CFGR2 fieldset: CFGR2
- name: SMPR - name: SMPR
description: sample time register 1 description: sample time register 1
array: array:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 20 byte_offset: 20
fieldset: SMPR fieldset: SMPR
- name: TR - name: TR
description: watchdog threshold register 1 description: watchdog threshold register 1
array: array:
len: 3 len: 3
stride: 4 stride: 4
byte_offset: 32 byte_offset: 32
fieldset: TR fieldset: TR
- name: SQR1 - name: SQR1
description: regular sequence register 1 description: regular sequence register 1
byte_offset: 48 byte_offset: 48
fieldset: SQR1 fieldset: SQR1
- name: SQR2 - name: SQR2
description: regular sequence register 2 description: regular sequence register 2
byte_offset: 52 byte_offset: 52
fieldset: SQR2 fieldset: SQR2
- name: SQR3 - name: SQR3
description: regular sequence register 3 description: regular sequence register 3
byte_offset: 56 byte_offset: 56
fieldset: SQR3 fieldset: SQR3
- name: SQR4 - name: SQR4
description: regular sequence register 4 description: regular sequence register 4
byte_offset: 60 byte_offset: 60
fieldset: SQR4 fieldset: SQR4
- name: DR - name: DR
description: regular Data Register description: regular Data Register
byte_offset: 64 byte_offset: 64
access: Read access: Read
fieldset: DR fieldset: DR
- name: JSQR - name: JSQR
description: injected sequence register description: injected sequence register
byte_offset: 76 byte_offset: 76
fieldset: JSQR fieldset: JSQR
- name: OFR - name: OFR
description: offset register 1 description: offset register 1
array: array:
len: 4 len: 4
stride: 4 stride: 4
byte_offset: 96 byte_offset: 96
fieldset: OFR fieldset: OFR
- name: JDR - name: JDR
description: injected data registers description: injected data registers
array: array:
len: 4 len: 4
stride: 4 stride: 4
byte_offset: 128 byte_offset: 128
access: Read access: Read
fieldset: JDR fieldset: JDR
- name: AWD2CR - name: AWD2CR
description: Analog Watchdog 2 Configuration Register description: Analog Watchdog 2 Configuration Register
byte_offset: 160 byte_offset: 160
fieldset: AWD2CR fieldset: AWD2CR
- name: AWD3CR - name: AWD3CR
description: Analog Watchdog 3 Configuration Register description: Analog Watchdog 3 Configuration Register
byte_offset: 164 byte_offset: 164
fieldset: AWD3CR fieldset: AWD3CR
- name: DIFSEL - name: DIFSEL
description: Differential Mode Selection Register 2 description: Differential Mode Selection Register 2
byte_offset: 176 byte_offset: 176
fieldset: DIFSEL fieldset: DIFSEL
- name: CALFACT - name: CALFACT
description: Calibration Factors description: Calibration Factors
byte_offset: 180 byte_offset: 180
fieldset: CALFACT fieldset: CALFACT
fieldset/AWD2CR: fieldset/AWD2CR:
description: Analog Watchdog 2 Configuration Register description: Analog Watchdog 2 Configuration Register
fields: fields:
- name: AWD2CH - name: AWD2CH
description: AWD2CH description: AWD2CH
bit_offset: 1 bit_offset: 1
bit_size: 18 bit_size: 18
fieldset/AWD3CR: fieldset/AWD3CR:
description: Analog Watchdog 3 Configuration Register description: Analog Watchdog 3 Configuration Register
fields: fields:
- name: AWD3CH - name: AWD3CH
description: AWD3CH description: AWD3CH
bit_offset: 1 bit_offset: 1
bit_size: 18 bit_size: 18
fieldset/CALFACT: fieldset/CALFACT:
description: Calibration Factors description: Calibration Factors
fields: fields:
- name: CALFACT_S - name: CALFACT_S
description: CALFACT_S description: CALFACT_S
bit_offset: 0 bit_offset: 0
bit_size: 7 bit_size: 7
- name: CALFACT_D - name: CALFACT_D
description: CALFACT_D description: CALFACT_D
bit_offset: 16 bit_offset: 16
bit_size: 7 bit_size: 7
fieldset/CFGR: fieldset/CFGR:
description: configuration register description: configuration register
fields: fields:
- name: DMAEN - name: DMAEN
description: DMAEN description: DMAEN
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DMACFG - name: DMACFG
description: DMACFG description: DMACFG
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: RES - name: RES
description: RES description: RES
bit_offset: 3 bit_offset: 3
bit_size: 2 bit_size: 2
enum: RES enum: RES
- name: ALIGN - name: ALIGN
description: ALIGN description: ALIGN
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: EXTSEL - name: EXTSEL
description: EXTSEL description: EXTSEL
bit_offset: 6 bit_offset: 6
bit_size: 4 bit_size: 4
- name: EXTEN - name: EXTEN
description: EXTEN description: EXTEN
bit_offset: 10 bit_offset: 10
bit_size: 2 bit_size: 2
- name: OVRMOD - name: OVRMOD
description: OVRMOD description: OVRMOD
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: CONT - name: CONT
description: CONT description: CONT
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: AUTDLY - name: AUTDLY
description: AUTDLY description: AUTDLY
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: AUTOFF - name: AUTOFF
description: AUTOFF description: AUTOFF
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: DISCEN - name: DISCEN
description: DISCEN description: DISCEN
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: DISCNUM - name: DISCNUM
description: DISCNUM description: DISCNUM
bit_offset: 17 bit_offset: 17
bit_size: 3 bit_size: 3
- name: JDISCEN - name: JDISCEN
description: JDISCEN description: JDISCEN
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
- name: JQM - name: JQM
description: JQM description: JQM
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: AWD1SGL - name: AWD1SGL
description: AWD1SGL description: AWD1SGL
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: AWD1EN - name: AWD1EN
description: AWD1EN description: AWD1EN
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: JAWD1EN - name: JAWD1EN
description: JAWD1EN description: JAWD1EN
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: JAUTO - name: JAUTO
description: JAUTO description: JAUTO
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: AWDCH1CH - name: AWDCH1CH
description: AWDCH1CH description: AWDCH1CH
bit_offset: 26 bit_offset: 26
bit_size: 5 bit_size: 5
fieldset/CFGR2: fieldset/CFGR2:
description: configuration register description: configuration register
fields: fields:
- name: ROVSE - name: ROVSE
description: DMAEN description: DMAEN
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: JOVSE - name: JOVSE
description: DMACFG description: DMACFG
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: OVSR - name: OVSR
description: RES description: RES
bit_offset: 2 bit_offset: 2
bit_size: 3 bit_size: 3
- name: OVSS - name: OVSS
description: ALIGN description: ALIGN
bit_offset: 5 bit_offset: 5
bit_size: 4 bit_size: 4
- name: TOVS - name: TOVS
description: EXTSEL description: EXTSEL
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: ROVSM - name: ROVSM
description: EXTEN description: EXTEN
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: control register description: control register
fields: fields:
- name: ADEN - name: ADEN
description: ADEN description: ADEN
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: ADDIS - name: ADDIS
description: ADDIS description: ADDIS
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: ADSTART - name: ADSTART
description: ADSTART description: ADSTART
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: JADSTART - name: JADSTART
description: JADSTART description: JADSTART
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: ADSTP - name: ADSTP
description: ADSTP description: ADSTP
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: JADSTP - name: JADSTP
description: JADSTP description: JADSTP
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: ADVREGEN - name: ADVREGEN
description: ADVREGEN description: ADVREGEN
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
- name: DEEPPWD - name: DEEPPWD
description: DEEPPWD description: DEEPPWD
bit_offset: 29 bit_offset: 29
bit_size: 1 bit_size: 1
- name: ADCALDIF - name: ADCALDIF
description: ADCALDIF description: ADCALDIF
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
- name: ADCAL - name: ADCAL
description: ADCAL description: ADCAL
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/DIFSEL: fieldset/DIFSEL:
description: Differential Mode Selection Register 2 description: Differential Mode Selection Register 2
fields: fields:
- name: DIFSEL_1_15 - name: DIFSEL_1_15
description: Differential mode for channels 15 to 1 description: Differential mode for channels 15 to 1
bit_offset: 1 bit_offset: 1
bit_size: 15 bit_size: 15
- name: DIFSEL_16_18 - name: DIFSEL_16_18
description: Differential mode for channels 18 to 16 description: Differential mode for channels 18 to 16
bit_offset: 16 bit_offset: 16
bit_size: 3 bit_size: 3
fieldset/DR: fieldset/DR:
description: regular Data Register description: regular Data Register
fields: fields:
- name: regularDATA - name: regularDATA
description: regularDATA description: regularDATA
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
fieldset/IER: fieldset/IER:
description: interrupt enable register description: interrupt enable register
fields: fields:
- name: ADRDYIE - name: ADRDYIE
description: ADRDYIE description: ADRDYIE
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: EOSMPIE - name: EOSMPIE
description: EOSMPIE description: EOSMPIE
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: EOCIE - name: EOCIE
description: EOCIE description: EOCIE
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: EOSIE - name: EOSIE
description: EOSIE description: EOSIE
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: OVRIE - name: OVRIE
description: OVRIE description: OVRIE
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: JEOCIE - name: JEOCIE
description: JEOCIE description: JEOCIE
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: JEOSIE - name: JEOSIE
description: JEOSIE description: JEOSIE
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: AWD1IE - name: AWD1IE
description: AWD1IE description: AWD1IE
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: AWD2IE - name: AWD2IE
description: AWD2IE description: AWD2IE
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: AWD3IE - name: AWD3IE
description: AWD3IE description: AWD3IE
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: JQOVFIE - name: JQOVFIE
description: JQOVFIE description: JQOVFIE
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
fieldset/ISR: fieldset/ISR:
description: interrupt and status register description: interrupt and status register
fields: fields:
- name: ADRDY - name: ADRDY
description: ADRDY description: ADRDY
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: EOSMP - name: EOSMP
description: EOSMP description: EOSMP
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: EOC - name: EOC
description: EOC description: EOC
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: EOS - name: EOS
description: EOS description: EOS
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: OVR - name: OVR
description: OVR description: OVR
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: JEOC - name: JEOC
description: JEOC description: JEOC
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: JEOS - name: JEOS
description: JEOS description: JEOS
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: AWD - name: AWD
description: AWD1 description: AWD1
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
array: array:
len: 3 len: 3
stride: 1 stride: 1
- name: JQOVF - name: JQOVF
description: JQOVF description: JQOVF
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
fieldset/JDR: fieldset/JDR:
description: injected data register 1 description: injected data register 1
fields: fields:
- name: JDATA - name: JDATA
description: JDATA1 description: JDATA1
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
fieldset/JSQR: fieldset/JSQR:
description: injected sequence register description: injected sequence register
fields: fields:
- name: JL - name: JL
description: JL description: JL
bit_offset: 0 bit_offset: 0
bit_size: 2 bit_size: 2
- name: JEXTSEL - name: JEXTSEL
description: JEXTSEL description: JEXTSEL
bit_offset: 2 bit_offset: 2
bit_size: 4 bit_size: 4
- name: JEXTEN - name: JEXTEN
description: JEXTEN description: JEXTEN
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
- name: JSQ - name: JSQ
description: JSQ1 description: JSQ1
bit_offset: 8 bit_offset: 8
bit_size: 5 bit_size: 5
array: array:
len: 4 len: 4
stride: 6 stride: 6
fieldset/OFR: fieldset/OFR:
description: offset register description: offset register
fields: fields:
- name: OFFSET - name: OFFSET
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
- name: OFFSET_CH - name: OFFSET_CH
bit_offset: 26 bit_offset: 26
bit_size: 5 bit_size: 5
- name: OFFSET_EN - name: OFFSET_EN
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/SMPR: fieldset/SMPR:
description: sample time register 1 description: sample time register 1
fields: fields:
- name: SMP - name: SMP
description: Channel 0 sampling time selection description: Channel 0 sampling time selection
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
array: array:
len: 10 len: 10
stride: 3 stride: 3
enum: SAMPLE_TIME enum: SAMPLE_TIME
fieldset/SQR1: fieldset/SQR1:
description: regular sequence register 1 description: regular sequence register 1
fields: fields:
- name: L - name: L
description: Regular channel sequence length description: Regular channel sequence length
bit_offset: 0 bit_offset: 0
bit_size: 4 bit_size: 4
- name: SQ - name: SQ
description: SQ1 description: SQ1
bit_offset: 6 bit_offset: 6
bit_size: 5 bit_size: 5
array: array:
len: 4 len: 4
stride: 6 stride: 6
fieldset/SQR2: fieldset/SQR2:
description: regular sequence register 2 description: regular sequence register 2
fields: fields:
- name: SQ - name: SQ
description: SQ5 description: SQ5
bit_offset: 0 bit_offset: 0
bit_size: 5 bit_size: 5
array: array:
len: 5 len: 5
stride: 6 stride: 6
fieldset/SQR3: fieldset/SQR3:
description: regular sequence register 3 description: regular sequence register 3
fields: fields:
- name: SQ - name: SQ
description: SQ10 description: SQ10
bit_offset: 0 bit_offset: 0
bit_size: 5 bit_size: 5
array: array:
len: 5 len: 5
stride: 6 stride: 6
fieldset/SQR4: fieldset/SQR4:
description: regular sequence register 4 description: regular sequence register 4
fields: fields:
- name: SQ - name: SQ
description: SQ15 description: SQ15
bit_offset: 0 bit_offset: 0
bit_size: 5 bit_size: 5
array: array:
len: 2 len: 2
stride: 6 stride: 6
fieldset/TR: fieldset/TR:
description: watchdog threshold register description: watchdog threshold register
fields: fields:
- name: LT - name: LT
description: LT1 description: LT1
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
- name: HT - name: HT
description: HT1 description: HT1
bit_offset: 16 bit_offset: 16
bit_size: 12 bit_size: 12
enum/RES: enum/RES:
bit_size: 2 bit_size: 2
variants: variants:
- name: TwelveBit - name: TwelveBit
description: 12-bit resolution description: 12-bit resolution
value: 0 value: 0
- name: TenBit - name: TenBit
description: 10-bit resolution description: 10-bit resolution
value: 1 value: 1
- name: EightBit - name: EightBit
description: 8-bit resolution description: 8-bit resolution
value: 2 value: 2
- name: SixBit - name: SixBit
description: 6-bit resolution description: 6-bit resolution
value: 3 value: 3
enum/SAMPLE_TIME: enum/SAMPLE_TIME:
bit_size: 3 bit_size: 3
variants: variants:
- name: Cycles2_5 - name: Cycles2_5
description: 2.5 ADC cycles description: 2.5 ADC cycles
value: 0 value: 0
- name: Cycles6_5 - name: Cycles6_5
description: 6.5 ADC cycles description: 6.5 ADC cycles
value: 1 value: 1
- name: Cycles12_5 - name: Cycles12_5
description: 12.5 ADC cycles description: 12.5 ADC cycles
value: 2 value: 2
- name: Cycles24_5 - name: Cycles24_5
description: 24.5 ADC cycles description: 24.5 ADC cycles
value: 3 value: 3
- name: Cycles47_5 - name: Cycles47_5
description: 47.5 ADC cycles description: 47.5 ADC cycles
value: 4 value: 4
- name: Cycles92_5 - name: Cycles92_5
description: 92.5 ADC cycles description: 92.5 ADC cycles
value: 5 value: 5
- name: Cycles247_5 - name: Cycles247_5
description: 247.5 ADC cycles description: 247.5 ADC cycles
value: 6 value: 6
- name: Cycles640_5 - name: Cycles640_5
description: 640.5 ADC cycles description: 640.5 ADC cycles
value: 7 value: 7

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data/registers/adc_v4.yaml
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block/ADC_COMMON:
description: ADC common registers
items:
- name: CSR
description: ADC Common status register
byte_offset: 0
access: Read
fieldset: CSR
- name: CCR
description: ADC common control register
byte_offset: 8
fieldset: CCR
- name: CDR
description: ADC common regular data register for dual and triple modes
byte_offset: 12
access: Read
fieldset: CDR
fieldset/CCR:
description: ADC common control register
fields:
- name: DUAL
description: Dual ADC mode selection
bit_offset: 0
bit_size: 5
enum: DUAL
- name: DELAY
description: Delay between 2 sampling phases
bit_offset: 8
bit_size: 4
- name: DMACFG
description: DMA configuration (for multi-ADC mode)
bit_offset: 13
bit_size: 1
enum: DMACFG
- name: MDMA
description: Direct memory access mode for multi ADC mode
bit_offset: 14
bit_size: 2
enum: MDMA
- name: CKMODE
description: ADC clock mode
bit_offset: 16
bit_size: 2
enum: CKMODE
- name: VREFEN
description: VREFINT enable
bit_offset: 22
bit_size: 1
- name: TSEN
description: Temperature sensor enable
bit_offset: 23
bit_size: 1
- name: VBATEN
description: VBAT enable
bit_offset: 24
bit_size: 1
fieldset/CDR:
description: ADC common regular data register for dual and triple modes
fields:
- name: RDATA_MST
description: Regular data of the master ADC
bit_offset: 0
bit_size: 16
- name: RDATA_SLV
description: Regular data of the master ADC
bit_offset: 16
bit_size: 16
fieldset/CSR:
fields:
- name: ADRDY_MST
description: Master ADC ready
bit_offset: 0
bit_size: 1
- name: EOSMP_MST
description: End of sampling phase flag of the master ADC
bit_offset: 1
bit_size: 1
enum: ENDED
- name: EOC_MST
description: End of regular conversion of the master ADC
bit_offset: 2
bit_size: 1
enum: ENDED
- name: EOS_MST
description: End of regular sequence flag of the master ADC
bit_offset: 3
bit_size: 1
enum: ENDED
- name: OVR_MST
description: Overrun flag of the master ADC
bit_offset: 4
bit_size: 1
enum: OVR
- name: JEOC_MST
description: End of injected conversion of the master ADC
bit_offset: 5
bit_size: 1
enum: ENDED
- name: JEOS
description: End of injected sequence flag of the master ADC
bit_offset: 6
bit_size: 1
enum: ENDED
- name: AWD1_MST
description: Analog watchdog 1 flag of the master ADC
bit_offset: 7
bit_size: 1
enum: AWD
- name: AWD2_MST
description: Analog watchdog 2 flag of the master ADC
bit_offset: 8
bit_size: 1
enum: AWD
- name: AWD3_MST
description: Analog watchdog 3 flag of the master ADC
bit_offset: 9
bit_size: 1
enum: AWD
- name: JQOVF_MST
description: Injected context queue overflow flag of the master ADC
bit_offset: 10
bit_size: 1
enum: JQOVF
- name: ADRDY_SLV
description: Slave ADC ready
bit_offset: 16
bit_size: 1
- name: EOSMP_SLV
description: End of sampling phase flag of the slave ADC
bit_offset: 17
bit_size: 1
enum: ENDED
- name: EOC_SLV
description: End of regular conversion of the slave ADC
bit_offset: 18
bit_size: 1
enum: ENDED
- name: EOS_SLV
description: End of regular sequence flag of the slave ADC
bit_offset: 19
bit_size: 1
enum: ENDED
- name: OVR_SLV
description: Overrun flag of the slave ADC
bit_offset: 20
bit_size: 1
enum: OVR
- name: JEOC_SLV
description: End of injected conversion of the slave ADC
bit_offset: 21
bit_size: 1
enum: ENDED
- name: JEOS_SLV
description: End of injected sequence flag of the slave ADC
bit_offset: 22
bit_size: 1
enum: ENDED
- name: AWD1_SLV
description: Analog watchdog 1 flag of the slave ADC
bit_offset: 23
bit_size: 1
enum: AWD
- name: AWD2_SLV
description: Analog watchdog 2 flag of the slave ADC
bit_offset: 24
bit_size: 1
enum: AWD
- name: AWD3_SLV
description: Analog watchdog 3 flag of the slave ADC
bit_offset: 25
bit_size: 1
enum: AWD
- name: JQOVF_SLV
description: Injected context queue overflow flag of the slave ADC
bit_offset: 26
bit_size: 1
enum: JQOVF
enum/AWD:
description: Analog watchdog flag
bit_size: 1
variants:
- name: NoEvent
description: No analog watchdog event occurred
value: 0
- name: Event
description: Analog watchdog event occurred
value: 1
enum/CKMODE:
description: ADC clock mode
bit_size: 2
variants:
- name: Asynchronous
description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous mode
value: 0
- name: SyncDiv1
description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck.
value: 1
- name: SyncDiv2
description: Use AHB clock rcc_hclk3 divided by 2.
value: 2
- name: SyncDiv4
description: Use AHB clock rcc_hclk3 divided by 4.
value: 3
enum/DMACFG:
description: DMA configuration (for multi-ADC mode)
bit_size: 1
variants:
- name: OneShot
description: DMA one shot mode selected
value: 0
- name: Circulator
description: DMA circular mode selected
value: 1
enum/DUAL:
description: Dual ADC mode selection
bit_size: 5
variants:
- name: Independent
description: Independent mode
value: 0
- name: DualRJ
description: Dual, combined regular simultaneous + injected simultaneous mode
value: 1
- name: DualRA
description: Dual, combined regular simultaneous + alternate trigger mode
value: 2
- name: DualIJ
description: Dual, combined injected simultaneous + fast interleaved mode
value: 3
- name: DualJ
description: Dual, injected simultaneous mode only
value: 5
- name: DualR
description: Dual, regular simultaneous mode only
value: 6
- name: DualI
description: dual, interleaved mode only
value: 7
- name: DualA
description: Dual, alternate trigger mode only
value: 9
enum/ENDED:
description: End of operation
bit_size: 1
variants:
- name: NotEnded
description: Operation is not ended
value: 0
- name: Ended
description: Operation is ended
value: 1
enum/JQOVF:
description: Injected context queue overflow flag
bit_size: 1
variants:
- name: NoOverflow
description: No injected context queue overflow
value: 0
- name: Overflow
description: Injected context queue overflow
value: 1
enum/MDMA:
description: Direct memory access mode for multi ADC mode
bit_size: 2
variants:
- name: Disabled
description: MDMA mode disabled
value: 0
- name: Bits12_10
description: MDMA mode enabled for 12 and 10-bit resolution
value: 2
- name: Bit8_6
description: MDMA mode enabled for 8 and 6-bit resolution
value: 3
enum/OVR:
description: Overrun flag
bit_size: 1
variants:
- name: NoOverrun
description: No overrun occurred
value: 0
- name: Overrun
description: Overrun occurred
value: 1

433
data/registers/adccommon_v2.yaml
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@ -1,269 +1,248 @@
---
block/ADC_COMMON: block/ADC_COMMON:
description: ADC common registers description: ADC common registers
items: items:
- name: CSR - name: CSR
description: ADC Common status register description: ADC Common status register
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: CSR fieldset: CSR
- name: CCR - name: CCR
description: ADC common control register description: ADC common control register
byte_offset: 4 byte_offset: 4
fieldset: CCR fieldset: CCR
- name: CDR - name: CDR
description: ADC common regular data register for dual and triple modes description: ADC common regular data register for dual and triple modes
byte_offset: 8 byte_offset: 8
access: Read access: Read
fieldset: CDR fieldset: CDR
fieldset/CCR: fieldset/CCR:
description: ADC common control register description: ADC common control register
fields: fields:
- name: MULTI - name: MULTI
description: Multi ADC mode selection description: Multi ADC mode selection
bit_offset: 0 bit_offset: 0
bit_size: 5 bit_size: 5
enum: MULTI enum: MULTI
- name: DELAY - name: DELAY
description: Delay between 2 sampling phases description: Delay between 2 sampling phases
bit_offset: 8 bit_offset: 8
bit_size: 4 bit_size: 4
- name: DDS - name: DDS
description: DMA disable selection for multi-ADC mode description: DMA disable selection for multi-ADC mode
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
enum: DDS enum: DDS
- name: DMA - name: DMA
description: Direct memory access mode for multi ADC mode description: Direct memory access mode for multi ADC mode
bit_offset: 14 bit_offset: 14
bit_size: 2 bit_size: 2
enum: DMA enum: DMA
- name: ADCPRE - name: ADCPRE
description: ADC prescaler description: ADC prescaler
bit_offset: 16 bit_offset: 16
bit_size: 2 bit_size: 2
enum: ADCPRE enum: ADCPRE
- name: VBATE - name: VBATE
description: VBAT enable description: VBAT enable
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
enum: VBATE - name: TSVREFE
- name: TSVREFE description: Temperature sensor and VREFINT enable
description: Temperature sensor and VREFINT enable bit_offset: 23
bit_offset: 23 bit_size: 1
bit_size: 1
enum: TSVREFE
fieldset/CDR: fieldset/CDR:
description: ADC common regular data register for dual and triple modes description: ADC common regular data register for dual and triple modes
fields: fields:
- name: DATA - name: DATA
description: 1st data item of a pair of regular conversions description: 1st data item of a pair of regular conversions
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
array: array:
len: 2 len: 2
stride: 16 stride: 16
fieldset/CSR: fieldset/CSR:
description: ADC common status register description: ADC common status register
fields: fields:
- name: AWD - name: AWD
description: Analog watchdog flag of ADC 1 description: Analog watchdog flag of ADC 1
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 3 len: 3
stride: 8 stride: 8
enum: AWD enum: AWD
- name: EOC - name: EOC
description: End of conversion of ADC 1 description: End of conversion of ADC 1
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
array: array:
len: 3 len: 3
stride: 8 stride: 8
enum: EOC enum: EOC
- name: JEOC - name: JEOC
description: Injected channel end of conversion of ADC 1 description: Injected channel end of conversion of ADC 1
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
array: array:
len: 3 len: 3
stride: 8 stride: 8
enum: JEOC enum: JEOC
- name: JSTRT - name: JSTRT
description: Injected channel Start flag of ADC 1 description: Injected channel Start flag of ADC 1
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
array: array:
len: 3 len: 3
stride: 8 stride: 8
enum: JSTRT enum: JSTRT
- name: STRT - name: STRT
description: Regular channel Start flag of ADC 1 description: Regular channel Start flag of ADC 1
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
array: array:
len: 3 len: 3
stride: 8 stride: 8
enum: STRT enum: STRT
- name: OVR - name: OVR
description: Overrun flag of ADC 1 description: Overrun flag of ADC 1
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
array: array:
len: 3 len: 3
stride: 8 stride: 8
enum: OVR enum: OVR
enum/ADCPRE: enum/ADCPRE:
bit_size: 2 bit_size: 2
variants: variants:
- name: Div2 - name: Div2
description: PCLK2 divided by 2 description: PCLK2 divided by 2
value: 0 value: 0
- name: Div4 - name: Div4
description: PCLK2 divided by 4 description: PCLK2 divided by 4
value: 1 value: 1
- name: Div6 - name: Div6
description: PCLK2 divided by 6 description: PCLK2 divided by 6
value: 2 value: 2
- name: Div8 - name: Div8
description: PCLK2 divided by 8 description: PCLK2 divided by 8
value: 3 value: 3
enum/AWD: enum/AWD:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoEvent - name: NoEvent
description: No analog watchdog event occurred description: No analog watchdog event occurred
value: 0 value: 0
- name: Event - name: Event
description: Analog watchdog event occurred description: Analog watchdog event occurred
value: 1 value: 1
enum/DDS: enum/DDS:
bit_size: 1 bit_size: 1
variants: variants:
- name: Single - name: Single
description: No new DMA request is issued after the last transfer description: No new DMA request is issued after the last transfer
value: 0 value: 0
- name: Continuous - name: Continuous
description: "DMA requests are issued as long as data are converted and DMA=01, 10 or 11" description: DMA requests are issued as long as data are converted and DMA=01, 10 or 11
value: 1 value: 1
enum/DMA: enum/DMA:
bit_size: 2 bit_size: 2
variants: variants:
- name: Disabled - name: Disabled
description: DMA mode disabled description: DMA mode disabled
value: 0 value: 0
- name: Mode1 - name: Mode1
description: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3) description: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)
value: 1 value: 1
- name: Mode2 - name: Mode2
description: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2) description: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
value: 2 value: 2
- name: Mode3 - name: Mode3
description: DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2) description: DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
value: 3 value: 3
enum/EOC: enum/EOC:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotComplete - name: NotComplete
description: Conversion is not complete description: Conversion is not complete
value: 0 value: 0
- name: Complete - name: Complete
description: Conversion complete description: Conversion complete
value: 1 value: 1
enum/JEOC: enum/JEOC:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotComplete - name: NotComplete
description: Conversion is not complete description: Conversion is not complete
value: 0 value: 0
- name: Complete - name: Complete
description: Conversion complete description: Conversion complete
value: 1 value: 1
enum/JSTRT: enum/JSTRT:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotStarted - name: NotStarted
description: No injected channel conversion started description: No injected channel conversion started
value: 0 value: 0
- name: Started - name: Started
description: Injected channel conversion has started description: Injected channel conversion has started
value: 1 value: 1
enum/MULTI: enum/MULTI:
bit_size: 5 bit_size: 5
variants: variants:
- name: Independent - name: Independent
description: "All the ADCs independent: independent mode" description: 'All the ADCs independent: independent mode'
value: 0 value: 0
- name: DualRJ - name: DualRJ
description: "Dual ADC1 and ADC2, combined regular and injected simultaneous mode" description: Dual ADC1 and ADC2, combined regular and injected simultaneous mode
value: 1 value: 1
- name: DualRA - name: DualRA
description: "Dual ADC1 and ADC2, combined regular and alternate trigger mode" description: Dual ADC1 and ADC2, combined regular and alternate trigger mode
value: 2 value: 2
- name: DualJ - name: DualJ
description: "Dual ADC1 and ADC2, injected simultaneous mode only" description: Dual ADC1 and ADC2, injected simultaneous mode only
value: 5 value: 5
- name: DualR - name: DualR
description: "Dual ADC1 and ADC2, regular simultaneous mode only" description: Dual ADC1 and ADC2, regular simultaneous mode only
value: 6 value: 6
- name: DualI - name: DualI
description: "Dual ADC1 and ADC2, interleaved mode only" description: Dual ADC1 and ADC2, interleaved mode only
value: 7 value: 7
- name: DualA - name: DualA
description: "Dual ADC1 and ADC2, alternate trigger mode only" description: Dual ADC1 and ADC2, alternate trigger mode only
value: 9 value: 9
- name: TripleRJ - name: TripleRJ
description: "Triple ADC, regular and injected simultaneous mode" description: Triple ADC, regular and injected simultaneous mode
value: 17 value: 17
- name: TripleRA - name: TripleRA
description: "Triple ADC, regular and alternate trigger mode" description: Triple ADC, regular and alternate trigger mode
value: 18 value: 18
- name: TripleJ - name: TripleJ
description: "Triple ADC, injected simultaneous mode only" description: Triple ADC, injected simultaneous mode only
value: 21 value: 21
- name: TripleR - name: TripleR
description: "Triple ADC, regular simultaneous mode only" description: Triple ADC, regular simultaneous mode only
value: 22 value: 22
- name: TripleI - name: TripleI
description: "Triple ADC, interleaved mode only" description: Triple ADC, interleaved mode only
value: 23 value: 23
- name: TripleA - name: TripleA
description: "Triple ADC, alternate trigger mode only" description: Triple ADC, alternate trigger mode only
value: 24 value: 24
enum/OVR: enum/OVR:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoOverrun - name: NoOverrun
description: No overrun occurred description: No overrun occurred
value: 0 value: 0
- name: Overrun - name: Overrun
description: Overrun occurred description: Overrun occurred
value: 1 value: 1
enum/STRT: enum/STRT:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotStarted - name: NotStarted
description: No regular channel conversion started description: No regular channel conversion started
value: 0 value: 0
- name: Started - name: Started
description: Regular channel conversion has started description: Regular channel conversion has started
value: 1 value: 1
enum/TSVREFE:
bit_size: 1
variants:
- name: Disabled
description: Temperature sensor and V_REFINT channel disabled
value: 0
- name: Enabled
description: Temperature sensor and V_REFINT channel enabled
value: 1
enum/VBATE:
bit_size: 1
variants:
- name: Disabled
description: V_BAT channel disabled
value: 0
- name: Enabled
description: V_BAT channel enabled
value: 1

285
data/registers/adccommon_v3.yaml
View File

@ -1,155 +1,154 @@
---
block/ADC_COMMON: block/ADC_COMMON:
description: Analog-to-Digital Converter description: Analog-to-Digital Converter
items: items:
- name: CSR - name: CSR
description: ADC Common status register description: ADC Common status register
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: CSR fieldset: CSR
- name: CCR - name: CCR
description: ADC common control register description: ADC common control register
byte_offset: 8 byte_offset: 8
fieldset: CCR fieldset: CCR
- name: CDR - name: CDR
description: ADC common regular data register for dual and triple modes description: ADC common regular data register for dual and triple modes
byte_offset: 12 byte_offset: 12
access: Read access: Read
fieldset: CDR fieldset: CDR
fieldset/CCR: fieldset/CCR:
description: ADC common control register description: ADC common control register
fields: fields:
- name: MULT - name: MULT
description: Multi ADC mode selection description: Multi ADC mode selection
bit_offset: 0 bit_offset: 0
bit_size: 5 bit_size: 5
- name: DELAY - name: DELAY
description: Delay between 2 sampling phases description: Delay between 2 sampling phases
bit_offset: 8 bit_offset: 8
bit_size: 4 bit_size: 4
- name: DMACFG - name: DMACFG
description: DMA configuration (for multi-ADC mode) description: DMA configuration (for multi-ADC mode)
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: MDMA - name: MDMA
description: Direct memory access mode for multi ADC mode description: Direct memory access mode for multi ADC mode
bit_offset: 14 bit_offset: 14
bit_size: 2 bit_size: 2
- name: CKMODE - name: CKMODE
description: ADC clock mode description: ADC clock mode
bit_offset: 16 bit_offset: 16
bit_size: 2 bit_size: 2
- name: VREFEN - name: VREFEN
description: VREFINT enable description: VREFINT enable
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: CH18SEL - name: CH18SEL
description: CH18 selection (Vbat) description: CH18 selection (Vbat)
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: CH17SEL - name: CH17SEL
description: CH17 selection (temperature) description: CH17 selection (temperature)
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
fieldset/CDR: fieldset/CDR:
description: ADC common regular data register for dual and triple modes description: ADC common regular data register for dual and triple modes
fields: fields:
- name: RDATA_MST - name: RDATA_MST
description: Regular data of the master ADC description: Regular data of the master ADC
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
- name: RDATA_SLV - name: RDATA_SLV
description: Regular data of the slave ADC description: Regular data of the slave ADC
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16
fieldset/CSR: fieldset/CSR:
description: ADC Common status register description: ADC Common status register
fields: fields:
- name: ADDRDY_MST - name: ADDRDY_MST
description: ADDRDY_MST description: ADDRDY_MST
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: EOSMP_MST - name: EOSMP_MST
description: EOSMP_MST description: EOSMP_MST
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: EOC_MST - name: EOC_MST
description: EOC_MST description: EOC_MST
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: EOS_MST - name: EOS_MST
description: EOS_MST description: EOS_MST
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: OVR_MST - name: OVR_MST
description: OVR_MST description: OVR_MST
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: JEOC_MST - name: JEOC_MST
description: JEOC_MST description: JEOC_MST
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: JEOS_MST - name: JEOS_MST
description: JEOS_MST description: JEOS_MST
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: AWD1_MST - name: AWD1_MST
description: AWD1_MST description: AWD1_MST
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: AWD2_MST - name: AWD2_MST
description: AWD2_MST description: AWD2_MST
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: AWD3_MST - name: AWD3_MST
description: AWD3_MST description: AWD3_MST
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: JQOVF_MST - name: JQOVF_MST
description: JQOVF_MST description: JQOVF_MST
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: ADRDY_SLV - name: ADRDY_SLV
description: ADRDY_SLV description: ADRDY_SLV
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: EOSMP_SLV - name: EOSMP_SLV
description: EOSMP_SLV description: EOSMP_SLV
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: EOC_SLV - name: EOC_SLV
description: End of regular conversion of the slave ADC description: End of regular conversion of the slave ADC
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
- name: EOS_SLV - name: EOS_SLV
description: End of regular sequence flag of the slave ADC description: End of regular sequence flag of the slave ADC
bit_offset: 19 bit_offset: 19
bit_size: 1 bit_size: 1
- name: OVR_SLV - name: OVR_SLV
description: Overrun flag of the slave ADC description: Overrun flag of the slave ADC
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
- name: JEOC_SLV - name: JEOC_SLV
description: End of injected conversion flag of the slave ADC description: End of injected conversion flag of the slave ADC
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: JEOS_SLV - name: JEOS_SLV
description: End of injected sequence flag of the slave ADC description: End of injected sequence flag of the slave ADC
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: AWD1_SLV - name: AWD1_SLV
description: Analog watchdog 1 flag of the slave ADC description: Analog watchdog 1 flag of the slave ADC
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: AWD2_SLV - name: AWD2_SLV
description: Analog watchdog 2 flag of the slave ADC description: Analog watchdog 2 flag of the slave ADC
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: AWD3_SLV - name: AWD3_SLV
description: Analog watchdog 3 flag of the slave ADC description: Analog watchdog 3 flag of the slave ADC
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: JQOVF_SLV - name: JQOVF_SLV
description: Injected Context Queue Overflow flag of the slave ADC description: Injected Context Queue Overflow flag of the slave ADC
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1

625
data/registers/adccommon_v4.yaml
View File

@ -1,367 +1,366 @@
---
block/ADC_COMMON: block/ADC_COMMON:
description: Analog-to-Digital Converter description: Analog-to-Digital Converter
items: items:
- name: CSR - name: CSR
description: ADC Common status register description: ADC Common status register
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: CSR fieldset: CSR
- name: CCR - name: CCR
description: ADC common control register description: ADC common control register
byte_offset: 8 byte_offset: 8
fieldset: CCR fieldset: CCR
- name: CDR - name: CDR
description: ADC common regular data register for dual and triple modes description: ADC common regular data register for dual and triple modes
byte_offset: 12 byte_offset: 12
access: Read access: Read
fieldset: CDR fieldset: CDR
- name: CDR2 - name: CDR2
description: ADC x common regular data register for 32-bit dual mode description: ADC x common regular data register for 32-bit dual mode
byte_offset: 16 byte_offset: 16
access: Read access: Read
fieldset: CDR2 fieldset: CDR2
fieldset/CCR: fieldset/CCR:
description: ADC common control register description: ADC common control register
fields: fields:
- name: DUAL - name: DUAL
description: Dual ADC mode selection description: Dual ADC mode selection
bit_offset: 0 bit_offset: 0
bit_size: 5 bit_size: 5
enum: DUAL enum: DUAL
- name: DELAY - name: DELAY
description: Delay between 2 sampling phases description: Delay between 2 sampling phases
bit_offset: 8 bit_offset: 8
bit_size: 4 bit_size: 4
- name: DAMDF - name: DAMDF
description: Dual ADC Mode Data Format description: Dual ADC Mode Data Format
bit_offset: 14 bit_offset: 14
bit_size: 2 bit_size: 2
enum: DAMDF enum: DAMDF
- name: CKMODE - name: CKMODE
description: ADC clock mode description: ADC clock mode
bit_offset: 16 bit_offset: 16
bit_size: 2 bit_size: 2
enum: CKMODE enum: CKMODE
- name: PRESC - name: PRESC
description: ADC prescaler description: ADC prescaler
bit_offset: 18 bit_offset: 18
bit_size: 4 bit_size: 4
enum: PRESC enum: PRESC
- name: VREFEN - name: VREFEN
description: VREFINT enable description: VREFINT enable
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: VSENSEEN - name: VSENSEEN
description: Temperature sensor enable description: Temperature sensor enable
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: VBATEN - name: VBATEN
description: VBAT enable description: VBAT enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
fieldset/CDR: fieldset/CDR:
description: ADC common regular data register for dual and triple modes description: ADC common regular data register for dual and triple modes
fields: fields:
- name: RDATA_MST - name: RDATA_MST
description: Regular data of the master ADC description: Regular data of the master ADC
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
- name: RDATA_SLV - name: RDATA_SLV
description: Regular data of the slave ADC description: Regular data of the slave ADC
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16
fieldset/CDR2: fieldset/CDR2:
description: ADC x common regular data register for 32-bit dual mode description: ADC x common regular data register for 32-bit dual mode
fields: fields:
- name: RDATA_ALT - name: RDATA_ALT
description: Regular data of the master/slave alternated ADCs description: Regular data of the master/slave alternated ADCs
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/CSR: fieldset/CSR:
description: ADC Common status register description: ADC Common status register
fields: fields:
- name: ADRDY_MST - name: ADRDY_MST
description: Master ADC ready description: Master ADC ready
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum: ADRDY_MST enum: ADRDY_MST
- name: EOSMP_MST - name: EOSMP_MST
description: End of Sampling phase flag of the master ADC description: End of Sampling phase flag of the master ADC
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
enum: EOSMP_MST enum: EOSMP_MST
- name: EOC_MST - name: EOC_MST
description: End of regular conversion of the master ADC description: End of regular conversion of the master ADC
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum: EOC_MST enum: EOC_MST
- name: EOS_MST - name: EOS_MST
description: End of regular sequence flag of the master ADC description: End of regular sequence flag of the master ADC
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
enum: EOS_MST enum: EOS_MST
- name: OVR_MST - name: OVR_MST
description: Overrun flag of the master ADC description: Overrun flag of the master ADC
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum: OVR_MST enum: OVR_MST
- name: JEOC_MST - name: JEOC_MST
description: End of injected conversion flag of the master ADC description: End of injected conversion flag of the master ADC
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum: JEOC_MST enum: JEOC_MST
- name: JEOS_MST - name: JEOS_MST
description: End of injected sequence flag of the master ADC description: End of injected sequence flag of the master ADC
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum: JEOS_MST enum: JEOS_MST
- name: AWD1_MST - name: AWD1_MST
description: Analog watchdog 1 flag of the master ADC description: Analog watchdog 1 flag of the master ADC
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
enum: AWD1_MST enum: AWD1_MST
- name: AWD2_MST - name: AWD2_MST
description: Analog watchdog 2 flag of the master ADC description: Analog watchdog 2 flag of the master ADC
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
enum: AWD1_MST enum: AWD1_MST
- name: AWD3_MST - name: AWD3_MST
description: Analog watchdog 3 flag of the master ADC description: Analog watchdog 3 flag of the master ADC
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
enum: AWD1_MST enum: AWD1_MST
- name: JQOVF_MST - name: JQOVF_MST
description: Injected Context Queue Overflow flag of the master ADC description: Injected Context Queue Overflow flag of the master ADC
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
enum: JQOVF_MST enum: JQOVF_MST
- name: ADRDY_SLV - name: ADRDY_SLV
description: Slave ADC ready description: Slave ADC ready
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum: ADRDY_MST enum: ADRDY_MST
- name: EOSMP_SLV - name: EOSMP_SLV
description: End of Sampling phase flag of the slave ADC description: End of Sampling phase flag of the slave ADC
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
enum: EOSMP_MST enum: EOSMP_MST
- name: EOC_SLV - name: EOC_SLV
description: End of regular conversion of the slave ADC description: End of regular conversion of the slave ADC
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
enum: EOC_MST enum: EOC_MST
- name: EOS_SLV - name: EOS_SLV
description: End of regular sequence flag of the slave ADC description: End of regular sequence flag of the slave ADC
bit_offset: 19 bit_offset: 19
bit_size: 1 bit_size: 1
enum: EOS_MST enum: EOS_MST
- name: OVR_SLV - name: OVR_SLV
description: Overrun flag of the slave ADC description: Overrun flag of the slave ADC
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
enum: OVR_MST enum: OVR_MST
- name: JEOC_SLV - name: JEOC_SLV
description: End of injected conversion flag of the slave ADC description: End of injected conversion flag of the slave ADC
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
enum: JEOC_MST enum: JEOC_MST
- name: JEOS_SLV - name: JEOS_SLV
description: End of injected sequence flag of the slave ADC description: End of injected sequence flag of the slave ADC
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
enum: JEOS_MST enum: JEOS_MST
- name: AWD1_SLV - name: AWD1_SLV
description: Analog watchdog 1 flag of the slave ADC description: Analog watchdog 1 flag of the slave ADC
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
enum: AWD1_MST enum: AWD1_MST
- name: AWD2_SLV - name: AWD2_SLV
description: Analog watchdog 2 flag of the slave ADC description: Analog watchdog 2 flag of the slave ADC
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
enum: AWD1_MST enum: AWD1_MST
- name: AWD3_SLV - name: AWD3_SLV
description: Analog watchdog 3 flag of the slave ADC description: Analog watchdog 3 flag of the slave ADC
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
enum: AWD1_MST enum: AWD1_MST
- name: JQOVF_SLV - name: JQOVF_SLV
description: Injected Context Queue Overflow flag of the slave ADC description: Injected Context Queue Overflow flag of the slave ADC
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
enum: JQOVF_MST enum: JQOVF_MST
enum/ADRDY_MST: enum/ADRDY_MST:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotReady - name: NotReady
description: ADC is not ready to start conversion description: ADC is not ready to start conversion
value: 0 value: 0
- name: Ready - name: Ready
description: ADC is ready to start conversion description: ADC is ready to start conversion
value: 1 value: 1
enum/AWD1_MST: enum/AWD1_MST:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoEvent - name: NoEvent
description: No analog watchdog event occurred description: No analog watchdog event occurred
value: 0 value: 0
- name: Event - name: Event
description: Analog watchdog event occurred description: Analog watchdog event occurred
value: 1 value: 1
enum/CKMODE: enum/CKMODE:
bit_size: 2 bit_size: 2
variants: variants:
- name: Asynchronous - name: Asynchronous
description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
value: 0 value: 0
- name: SyncDiv1 - name: SyncDiv1
description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
value: 1 value: 1
- name: SyncDiv2 - name: SyncDiv2
description: Use AHB clock rcc_hclk3 divided by 2 description: Use AHB clock rcc_hclk3 divided by 2
value: 2 value: 2
- name: SyncDiv4 - name: SyncDiv4
description: Use AHB clock rcc_hclk3 divided by 4 description: Use AHB clock rcc_hclk3 divided by 4
value: 3 value: 3
enum/DAMDF: enum/DAMDF:
bit_size: 2 bit_size: 2
variants: variants:
- name: NoPack - name: NoPack
description: "Without data packing, CDR/CDR2 not used" description: Without data packing, CDR/CDR2 not used
value: 0 value: 0
- name: Format32to10 - name: Format32to10
description: CDR formatted for 32-bit down to 10-bit resolution description: CDR formatted for 32-bit down to 10-bit resolution
value: 2 value: 2
- name: Format8 - name: Format8
description: CDR formatted for 8-bit resolution description: CDR formatted for 8-bit resolution
value: 3 value: 3
enum/DUAL: enum/DUAL:
bit_size: 5 bit_size: 5
variants: variants:
- name: Independent - name: Independent
description: Independent mode description: Independent mode
value: 0 value: 0
- name: DualRJ - name: DualRJ
description: "Dual, combined regular simultaneous + injected simultaneous mode" description: Dual, combined regular simultaneous + injected simultaneous mode
value: 1 value: 1
- name: DualRA - name: DualRA
description: "Dual, combined regular simultaneous + alternate trigger mode" description: Dual, combined regular simultaneous + alternate trigger mode
value: 2 value: 2
- name: DualIJ - name: DualIJ
description: "Dual, combined interleaved mode + injected simultaneous mode" description: Dual, combined interleaved mode + injected simultaneous mode
value: 3 value: 3
- name: DualJ - name: DualJ
description: "Dual, injected simultaneous mode only" description: Dual, injected simultaneous mode only
value: 5 value: 5
- name: DualR - name: DualR
description: "Dual, regular simultaneous mode only" description: Dual, regular simultaneous mode only
value: 6 value: 6
- name: DualI - name: DualI
description: "Dual, interleaved mode only" description: Dual, interleaved mode only
value: 7 value: 7
- name: DualA - name: DualA
description: "Dual, alternate trigger mode only" description: Dual, alternate trigger mode only
value: 9 value: 9
enum/EOC_MST: enum/EOC_MST:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotComplete - name: NotComplete
description: Regular conversion is not complete description: Regular conversion is not complete
value: 0 value: 0
- name: Complete - name: Complete
description: Regular conversion complete description: Regular conversion complete
value: 1 value: 1
enum/EOSMP_MST: enum/EOSMP_MST:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotEnded - name: NotEnded
description: End of sampling phase no yet reached description: End of sampling phase no yet reached
value: 0 value: 0
- name: Ended - name: Ended
description: End of sampling phase reached description: End of sampling phase reached
value: 1 value: 1
enum/EOS_MST: enum/EOS_MST:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotComplete - name: NotComplete
description: Regular sequence is not complete description: Regular sequence is not complete
value: 0 value: 0
- name: Complete - name: Complete
description: Regular sequence complete description: Regular sequence complete
value: 1 value: 1
enum/JEOC_MST: enum/JEOC_MST:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotComplete - name: NotComplete
description: Injected conversion is not complete description: Injected conversion is not complete
value: 0 value: 0
- name: Complete - name: Complete
description: Injected conversion complete description: Injected conversion complete
value: 1 value: 1
enum/JEOS_MST: enum/JEOS_MST:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotComplete - name: NotComplete
description: Injected sequence is not complete description: Injected sequence is not complete
value: 0 value: 0
- name: Complete - name: Complete
description: Injected sequence complete description: Injected sequence complete
value: 1 value: 1
enum/JQOVF_MST: enum/JQOVF_MST:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoOverflow - name: NoOverflow
description: No injected context queue overflow has occurred description: No injected context queue overflow has occurred
value: 0 value: 0
- name: Overflow - name: Overflow
description: Injected context queue overflow has occurred description: Injected context queue overflow has occurred
value: 1 value: 1
enum/OVR_MST: enum/OVR_MST:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoOverrun - name: NoOverrun
description: No overrun occurred description: No overrun occurred
value: 0 value: 0
- name: Overrun - name: Overrun
description: Overrun occurred description: Overrun occurred
value: 1 value: 1
enum/PRESC: enum/PRESC:
bit_size: 4 bit_size: 4
variants: variants:
- name: Div1 - name: Div1
description: adc_ker_ck_input not divided description: adc_ker_ck_input not divided
value: 0 value: 0
- name: Div2 - name: Div2
description: adc_ker_ck_input divided by 2 description: adc_ker_ck_input divided by 2
value: 1 value: 1
- name: Div4 - name: Div4
description: adc_ker_ck_input divided by 4 description: adc_ker_ck_input divided by 4
value: 2 value: 2
- name: Div6 - name: Div6
description: adc_ker_ck_input divided by 6 description: adc_ker_ck_input divided by 6
value: 3 value: 3
- name: Div8 - name: Div8
description: adc_ker_ck_input divided by 8 description: adc_ker_ck_input divided by 8
value: 4 value: 4
- name: Div10 - name: Div10
description: adc_ker_ck_input divided by 10 description: adc_ker_ck_input divided by 10
value: 5 value: 5
- name: Div12 - name: Div12
description: adc_ker_ck_input divided by 12 description: adc_ker_ck_input divided by 12
value: 6 value: 6
- name: Div16 - name: Div16
description: adc_ker_ck_input divided by 16 description: adc_ker_ck_input divided by 16
value: 7 value: 7
- name: Div32 - name: Div32
description: adc_ker_ck_input divided by 32 description: adc_ker_ck_input divided by 32
value: 8 value: 8
- name: Div64 - name: Div64
description: adc_ker_ck_input divided by 64 description: adc_ker_ck_input divided by 64
value: 9 value: 9
- name: Div128 - name: Div128
description: adc_ker_ck_input divided by 128 description: adc_ker_ck_input divided by 128
value: 10 value: 10
- name: Div256 - name: Div256
description: adc_ker_ck_input divided by 256 description: adc_ker_ck_input divided by 256
value: 11 value: 11

204
data/registers/aes_f7.yaml Normal file
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block/AES:
description: Advanced encryption standard hardware accelerator
items:
- name: CR
description: Control register
byte_offset: 0
fieldset: CR
- name: SR
description: Status register
byte_offset: 4
fieldset: SR
- name: DINR
description: Data input register
byte_offset: 8
fieldset: DINR
- name: DOUTR
description: Data output register
byte_offset: 12
fieldset: DOUTR
- name: KEYR
description: Key register
array:
offsets:
- 0
- 4
- 8
- 12
- 32
- 36
- 40
- 44
byte_offset: 16
fieldset: KEYR
- name: IVR
description: Initialization vector register
array:
len: 4
stride: 4
byte_offset: 32
fieldset: IVR
- name: SUSPR
description: Suspend register
array:
len: 8
stride: 4
byte_offset: 64
fieldset: SUSPR
fieldset/CR:
description: Control register
fields:
- name: EN
description: AES enable
bit_offset: 0
bit_size: 1
- name: DATATYPE
description: Data type selection
bit_offset: 1
bit_size: 2
enum: DATATYPE
- name: MODE
description: Operating mode
bit_offset: 3
bit_size: 2
enum: MODE
- name: CHMOD10
description: Chaining mode bit1 bit0
bit_offset: 5
bit_size: 2
- name: CCFC
description: Computation Complete Flag Clear
bit_offset: 7
bit_size: 1
- name: ERRC
description: Error clear
bit_offset: 8
bit_size: 1
- name: CCFIE
description: CCF flag interrupt enable
bit_offset: 9
bit_size: 1
- name: ERRIE
description: Error interrupt enable
bit_offset: 10
bit_size: 1
- name: DMAINEN
description: Enable DMA management of data input phase
bit_offset: 11
bit_size: 1
- name: DMAOUTEN
description: Enable DMA management of data output phase
bit_offset: 12
bit_size: 1
- name: GCMPH
description: GCM or CCM phase selection
bit_offset: 13
bit_size: 2
enum: GCMPH
- name: CHMOD2
description: Chaining mode bit2
bit_offset: 16
bit_size: 1
- name: KEYSIZE
description: Key size selection
bit_offset: 18
bit_size: 1
fieldset/DINR:
description: Data input register
fields:
- name: DIN
description: Input data word
bit_offset: 0
bit_size: 32
fieldset/DOUTR:
description: Data output register
fields:
- name: DOUT
description: Output data word
bit_offset: 0
bit_size: 32
fieldset/IVR:
description: Initialization vector register
fields:
- name: IVI
description: Initialization vector input
bit_offset: 0
bit_size: 32
fieldset/KEYR:
description: Key register
fields:
- name: KEY
description: Cryptographic key
bit_offset: 0
bit_size: 32
fieldset/SR:
description: Status register
fields:
- name: CCF
description: Computation complete flag
bit_offset: 0
bit_size: 1
- name: RDERR
description: Read error flag
bit_offset: 1
bit_size: 1
- name: WRERR
description: Write error flag
bit_offset: 2
bit_size: 1
- name: BUSY
description: Busy flag
bit_offset: 3
bit_size: 1
fieldset/SUSPR:
description: Suspend register
fields:
- name: SUSP
description: AES suspend
bit_offset: 0
bit_size: 32
enum/DATATYPE:
bit_size: 2
variants:
- name: None
description: Word
value: 0
- name: HalfWord
description: Half-word (16-bit)
value: 1
- name: Byte
description: Byte (8-bit)
value: 2
- name: Bit
description: Bit
value: 3
enum/GCMPH:
bit_size: 2
variants:
- name: Init phase
description: Init phase
value: 0
- name: Header phase
description: Header phase
value: 1
- name: Payload phase
description: Payload phase
value: 2
- name: Final phase
description: Final phase
value: 3
enum/MODE:
bit_size: 2
variants:
- name: Mode1
description: Encryption
value: 0
- name: Mode2
description: Key derivation (or key preparation for ECB/CBC decryption)
value: 1
- name: Mode3
description: Decryption
value: 2
- name: Mode4
description: Key derivation then single decryption
value: 3

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block/AES:
description: Advanced encryption standard hardware accelerator
items:
- name: CR
description: Control register
byte_offset: 0
fieldset: CR
- name: SR
description: Status register
byte_offset: 4
fieldset: SR
- name: DINR
description: Data input register
byte_offset: 8
fieldset: DINR
- name: DOUTR
description: Data output register
byte_offset: 12
fieldset: DOUTR
- name: KEYR
description: Key register
array:
offsets:
- 0
- 4
- 8
- 12
- 32
- 36
- 40
- 44
byte_offset: 16
fieldset: KEYR
- name: IVR
description: Initialization vector register
array:
len: 4
stride: 4
byte_offset: 32
fieldset: IVR
- name: SUSPR
description: Suspend register
array:
len: 8
stride: 4
byte_offset: 64
fieldset: SUSPR
- name: IER
description: interrupt enable register
byte_offset: 768
fieldset: IER
- name: ISR
description: interrupt status register
byte_offset: 772
fieldset: ISR
- name: ICR
description: interrupt clear register
byte_offset: 776
fieldset: ICR
fieldset/CR:
description: Control register
fields:
- name: EN
description: AES enable
bit_offset: 0
bit_size: 1
- name: DATATYPE
description: Data type selection
bit_offset: 1
bit_size: 2
enum: DATATYPE
- name: MODE
description: Operating mode
bit_offset: 3
bit_size: 2
enum: MODE
- name: CHMOD10
description: Chaining mode bit1 bit0
bit_offset: 5
bit_size: 2
- name: DMAINEN
description: Enable DMA management of data input phase
bit_offset: 11
bit_size: 1
- name: DMAOUTEN
description: Enable DMA management of data output phase
bit_offset: 12
bit_size: 1
- name: GCMPH
description: GCM or CCM phase selection
bit_offset: 13
bit_size: 2
enum: GCMPH
- name: CHMOD2
description: Chaining mode bit2
bit_offset: 16
bit_size: 1
- name: KEYSIZE
description: Key size selection
bit_offset: 18
bit_size: 1
- name: NPBLB
description: Number of padding bytes in last block of payload
bit_offset: 20
bit_size: 4
- name: KMOD
description: Key mode selection
bit_offset: 24
bit_size: 2
- name: IPRST
description: AES peripheral software reset
bit_offset: 31
bit_size: 1
fieldset/DINR:
description: Data input register
fields:
- name: DIN
description: Input data word
bit_offset: 0
bit_size: 32
fieldset/DOUTR:
description: Data output register
fields:
- name: DOUT
description: Output data word
bit_offset: 0
bit_size: 32
fieldset/ICR:
description: Interrupt clear register
fields:
- name: CCF
description: Computation complete flag clear
bit_offset: 0
bit_size: 1
- name: RWEIF
description: Read or write error interrupt flag clear
bit_offset: 1
bit_size: 1
- name: KEIF
description: Key error interrupt flag clear
bit_offset: 2
bit_size: 1
fieldset/IER:
description: Interrupt enable register
fields:
- name: CCFIE
description: Computation complete flag interrupt enable
bit_offset: 0
bit_size: 1
- name: RWEIE
description: Read or write error interrupt enable
bit_offset: 1
bit_size: 1
- name: KEIE
description: Key error interrupt enable
bit_offset: 2
bit_size: 1
fieldset/ISR:
description: Interrupt status register
fields:
- name: CCF
description: Computation complete flag
bit_offset: 0
bit_size: 1
- name: RWEIF
description: Read or write error interrupt flag
bit_offset: 1
bit_size: 1
- name: KEIF
description: Key error interrupt flag
bit_offset: 2
bit_size: 1
fieldset/IVR:
description: Initialization vector register
fields:
- name: IVI
description: Initialization vector input
bit_offset: 0
bit_size: 32
fieldset/KEYR:
description: Key register
fields:
- name: KEY
description: Cryptographic key
bit_offset: 0
bit_size: 32
fieldset/SR:
description: Status register
fields:
- name: CCF
description: Computation complete flag
bit_offset: 0
bit_size: 1
- name: RDERR
description: Read error flag
bit_offset: 1
bit_size: 1
- name: WRERR
description: Write error flag
bit_offset: 2
bit_size: 1
- name: BUSY
description: Busy flag
bit_offset: 3
bit_size: 1
- name: KEYVALID
description: Key valid flag
bit_offset: 7
bit_size: 1
fieldset/SUSPR:
description: Suspend register
fields:
- name: SUSP
description: AES suspend
bit_offset: 0
bit_size: 32
enum/DATATYPE:
bit_size: 2
variants:
- name: None
description: Word
value: 0
- name: HalfWord
description: Half-word (16-bit)
value: 1
- name: Byte
description: Byte (8-bit)
value: 2
- name: Bit
description: Bit
value: 3
enum/GCMPH:
bit_size: 2
variants:
- name: Init phase
description: Init phase
value: 0
- name: Header phase
description: Header phase
value: 1
- name: Payload phase
description: Payload phase
value: 2
- name: Final phase
description: Final phase
value: 3
enum/MODE:
bit_size: 2
variants:
- name: Mode1
description: Encryption
value: 0
- name: Mode2
description: Key derivation (or key preparation for ECB/CBC decryption)
value: 1
- name: Mode3
description: Decryption
value: 2

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block/AES:
description: Advanced encryption standard hardware accelerator
items:
- name: CR
description: Control register
byte_offset: 0
fieldset: CR
- name: SR
description: Status register
byte_offset: 4
fieldset: SR
- name: DINR
description: Data input register
byte_offset: 8
fieldset: DINR
- name: DOUTR
description: Data output register
byte_offset: 12
fieldset: DOUTR
- name: KEYR
description: Key register
array:
len: 4
stride: 4
byte_offset: 16
fieldset: KEYR
- name: IVR
description: Initialization vector register
array:
len: 4
stride: 4
byte_offset: 32
fieldset: IVR
fieldset/CR:
description: Control register
fields:
- name: EN
description: AES enable
bit_offset: 0
bit_size: 1
- name: DATATYPE
description: Data type selection
bit_offset: 1
bit_size: 2
enum: DATATYPE
- name: MODE
description: Operating mode
bit_offset: 3
bit_size: 2
enum: MODE
- name: CHMOD10
description: Chaining mode bit1 bit0
bit_offset: 5
bit_size: 2
- name: CCFC
description: Computation Complete Flag Clear
bit_offset: 7
bit_size: 1
- name: ERRC
description: Error clear
bit_offset: 8
bit_size: 1
- name: CCFIE
description: CCF flag interrupt enable
bit_offset: 9
bit_size: 1
- name: ERRIE
description: Error interrupt enable
bit_offset: 10
bit_size: 1
- name: DMAINEN
description: Enable DMA management of data input phase
bit_offset: 11
bit_size: 1
- name: DMAOUTEN
description: Enable DMA management of data output phase
bit_offset: 12
bit_size: 1
fieldset/DINR:
description: Data input register
fields:
- name: DIN
description: Input data word
bit_offset: 0
bit_size: 32
fieldset/DOUTR:
description: Data output register
fields:
- name: DOUT
description: Output data word
bit_offset: 0
bit_size: 32
fieldset/IVR:
description: Initialization vector register
fields:
- name: IVI
description: Initialization vector input
bit_offset: 0
bit_size: 32
fieldset/KEYR:
description: Key register
fields:
- name: KEY
description: Cryptographic key
bit_offset: 0
bit_size: 32
fieldset/SR:
description: Status register
fields:
- name: CCF
description: Computation complete flag
bit_offset: 0
bit_size: 1
- name: RDERR
description: Read error flag
bit_offset: 1
bit_size: 1
- name: WRERR
description: Write error flag
bit_offset: 2
bit_size: 1
enum/DATATYPE:
bit_size: 2
variants:
- name: None
description: Word
value: 0
- name: HalfWord
description: Half-word (16-bit)
value: 1
- name: Byte
description: Byte (8-bit)
value: 2
- name: Bit
description: Bit
value: 3
enum/MODE:
bit_size: 2
variants:
- name: Mode1
description: Encryption
value: 0
- name: Mode2
description: Key derivation (or key preparation for ECB/CBC decryption)
value: 1
- name: Mode3
description: Decryption
value: 2
- name: Mode4
description: Key derivation then single decryption
value: 3

208
data/registers/aes_v2.yaml Normal file
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@ -0,0 +1,208 @@
block/AES:
description: Advanced encryption standard hardware accelerator
items:
- name: CR
description: Control register
byte_offset: 0
fieldset: CR
- name: SR
description: Status register
byte_offset: 4
fieldset: SR
- name: DINR
description: Data input register
byte_offset: 8
fieldset: DINR
- name: DOUTR
description: Data output register
byte_offset: 12
fieldset: DOUTR
- name: KEYR
description: Key register
array:
offsets:
- 0
- 4
- 8
- 12
- 32
- 36
- 40
- 44
byte_offset: 16
fieldset: KEYR
- name: IVR
description: Initialization vector register
array:
len: 4
stride: 4
byte_offset: 32
fieldset: IVR
- name: SUSPR
description: Suspend register
array:
len: 8
stride: 4
byte_offset: 64
fieldset: SUSPR
fieldset/CR:
description: Control register
fields:
- name: EN
description: AES enable
bit_offset: 0
bit_size: 1
- name: DATATYPE
description: Data type selection
bit_offset: 1
bit_size: 2
enum: DATATYPE
- name: MODE
description: Operating mode
bit_offset: 3
bit_size: 2
enum: MODE
- name: CHMOD10
description: Chaining mode bit1 bit0
bit_offset: 5
bit_size: 2
- name: CCFC
description: Computation Complete Flag Clear
bit_offset: 7
bit_size: 1
- name: ERRC
description: Error clear
bit_offset: 8
bit_size: 1
- name: CCFIE
description: CCF flag interrupt enable
bit_offset: 9
bit_size: 1
- name: ERRIE
description: Error interrupt enable
bit_offset: 10
bit_size: 1
- name: DMAINEN
description: Enable DMA management of data input phase
bit_offset: 11
bit_size: 1
- name: DMAOUTEN
description: Enable DMA management of data output phase
bit_offset: 12
bit_size: 1
- name: GCMPH
description: GCM or CCM phase selection
bit_offset: 13
bit_size: 2
enum: GCMPH
- name: CHMOD2
description: Chaining mode bit2
bit_offset: 16
bit_size: 1
- name: KEYSIZE
description: Key size selection
bit_offset: 18
bit_size: 1
- name: NPBLB
description: Number of padding bytes in last block of payload
bit_offset: 20
bit_size: 4
fieldset/DINR:
description: Data input register
fields:
- name: DIN
description: Input data word
bit_offset: 0
bit_size: 32
fieldset/DOUTR:
description: Data output register
fields:
- name: DOUT
description: Output data word
bit_offset: 0
bit_size: 32
fieldset/IVR:
description: Initialization vector register
fields:
- name: IVI
description: Initialization vector input
bit_offset: 0
bit_size: 32
fieldset/KEYR:
description: Key register
fields:
- name: KEY
description: Cryptographic key
bit_offset: 0
bit_size: 32
fieldset/SR:
description: Status register
fields:
- name: CCF
description: Computation complete flag
bit_offset: 0
bit_size: 1
- name: RDERR
description: Read error flag
bit_offset: 1
bit_size: 1
- name: WRERR
description: Write error flag
bit_offset: 2
bit_size: 1
- name: BUSY
description: Busy flag
bit_offset: 3
bit_size: 1
fieldset/SUSPR:
description: Suspend register
fields:
- name: SUSP
description: AES suspend
bit_offset: 0
bit_size: 32
enum/DATATYPE:
bit_size: 2
variants:
- name: None
description: Word
value: 0
- name: HalfWord
description: Half-word (16-bit)
value: 1
- name: Byte
description: Byte (8-bit)
value: 2
- name: Bit
description: Bit
value: 3
enum/GCMPH:
bit_size: 2
variants:
- name: Init phase
description: Init phase
value: 0
- name: Header phase
description: Header phase
value: 1
- name: Payload phase
description: Payload phase
value: 2
- name: Final phase
description: Final phase
value: 3
enum/MODE:
bit_size: 2
variants:
- name: Mode1
description: Encryption
value: 0
- name: Mode2
description: Key derivation (or key preparation for ECB/CBC decryption)
value: 1
- name: Mode3
description: Decryption
value: 2
- name: Mode4
description: Key derivation then single decryption
value: 3

373
data/registers/afio_f1.yaml
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@ -1,202 +1,201 @@
---
block/AFIO: block/AFIO:
description: Alternate function I/O description: Alternate function I/O
items: items:
- name: EVCR - name: EVCR
description: Event Control Register (AFIO_EVCR) description: Event Control Register (AFIO_EVCR)
byte_offset: 0 byte_offset: 0
fieldset: EVCR fieldset: EVCR
- name: MAPR - name: MAPR
description: AF remap and debug I/O configuration register (AFIO_MAPR) description: AF remap and debug I/O configuration register (AFIO_MAPR)
byte_offset: 4 byte_offset: 4
fieldset: MAPR fieldset: MAPR
- name: EXTICR - name: EXTICR
description: External interrupt configuration register 1 (AFIO_EXTICR1) description: External interrupt configuration register 1 (AFIO_EXTICR1)
array: array:
len: 4 len: 4
stride: 4 stride: 4
byte_offset: 8 byte_offset: 8
fieldset: EXTICR fieldset: EXTICR
- name: MAPR2 - name: MAPR2
description: AF remap and debug I/O configuration register description: AF remap and debug I/O configuration register
byte_offset: 28 byte_offset: 28
fieldset: MAPR2 fieldset: MAPR2
fieldset/EVCR: fieldset/EVCR:
description: Event Control Register (AFIO_EVCR) description: Event Control Register (AFIO_EVCR)
fields: fields:
- name: PIN - name: PIN
description: Pin selection description: Pin selection
bit_offset: 0 bit_offset: 0
bit_size: 4 bit_size: 4
- name: PORT - name: PORT
description: Port selection description: Port selection
bit_offset: 4 bit_offset: 4
bit_size: 3 bit_size: 3
- name: EVOE - name: EVOE
description: Event Output Enable description: Event Output Enable
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
fieldset/EXTICR: fieldset/EXTICR:
description: External interrupt configuration register 3 (AFIO_EXTICR3) description: External interrupt configuration register 3 (AFIO_EXTICR3)
fields: fields:
- name: EXTI - name: EXTI
description: EXTI12 configuration description: EXTI12 configuration
bit_offset: 0 bit_offset: 0
bit_size: 4 bit_size: 4
array: array:
len: 4 len: 4
stride: 4 stride: 4
fieldset/MAPR: fieldset/MAPR:
description: AF remap and debug I/O configuration register (AFIO_MAPR) description: AF remap and debug I/O configuration register (AFIO_MAPR)
fields: fields:
- name: SPI1_REMAP - name: SPI1_REMAP
description: SPI1 remapping description: SPI1 remapping
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: I2C1_REMAP - name: I2C1_REMAP
description: I2C1 remapping description: I2C1 remapping
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: USART1_REMAP - name: USART1_REMAP
description: USART1 remapping description: USART1 remapping
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: USART2_REMAP - name: USART2_REMAP
description: USART2 remapping description: USART2 remapping
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: USART3_REMAP - name: USART3_REMAP
description: USART3 remapping description: USART3 remapping
bit_offset: 4 bit_offset: 4
bit_size: 2 bit_size: 2
- name: TIM1_REMAP - name: TIM1_REMAP
description: TIM1 remapping description: TIM1 remapping
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
- name: TIM2_REMAP - name: TIM2_REMAP
description: TIM2 remapping description: TIM2 remapping
bit_offset: 8 bit_offset: 8
bit_size: 2 bit_size: 2
- name: TIM3_REMAP - name: TIM3_REMAP
description: TIM3 remapping description: TIM3 remapping
bit_offset: 10 bit_offset: 10
bit_size: 2 bit_size: 2
- name: TIM4_REMAP - name: TIM4_REMAP
description: TIM4 remapping description: TIM4 remapping
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: CAN1_REMAP - name: CAN1_REMAP
description: CAN1 remapping description: CAN1 remapping
bit_offset: 13 bit_offset: 13
bit_size: 2 bit_size: 2
- name: PD01_REMAP - name: PD01_REMAP
description: Port D0/Port D1 mapping on OSCIN/OSCOUT description: Port D0/Port D1 mapping on OSCIN/OSCOUT
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: TIM5CH4_IREMAP - name: TIM5CH4_IREMAP
description: Set and cleared by software description: Set and cleared by software
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: ADC1_ETRGINJ_REMAP - name: ADC1_ETRGINJ_REMAP
description: ADC 1 External trigger injected conversion remapping description: ADC 1 External trigger injected conversion remapping
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: ADC1_ETRGREG_REMAP - name: ADC1_ETRGREG_REMAP
description: ADC 1 external trigger regular conversion remapping description: ADC 1 external trigger regular conversion remapping
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
- name: ADC2_ETRGINJ_REMAP - name: ADC2_ETRGINJ_REMAP
description: ADC 2 external trigger injected conversion remapping description: ADC 2 external trigger injected conversion remapping
bit_offset: 19 bit_offset: 19
bit_size: 1 bit_size: 1
- name: ADC2_ETRGREG_REMAP - name: ADC2_ETRGREG_REMAP
description: ADC 2 external trigger regular conversion remapping description: ADC 2 external trigger regular conversion remapping
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
- name: ETH_REMAP - name: ETH_REMAP
description: Ethernet MAC I/O remapping description: Ethernet MAC I/O remapping
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: CAN2_REMAP - name: CAN2_REMAP
description: CAN2 I/O remapping description: CAN2 I/O remapping
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: MII_RMII_SEL - name: MII_RMII_SEL
description: MII or RMII selection description: MII or RMII selection
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: SWJ_CFG - name: SWJ_CFG
description: Serial wire JTAG configuration description: Serial wire JTAG configuration
bit_offset: 24 bit_offset: 24
bit_size: 3 bit_size: 3
- name: SPI3_REMAP - name: SPI3_REMAP
description: SPI3/I2S3 remapping description: SPI3/I2S3 remapping
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
- name: TIM2ITR1_IREMAP - name: TIM2ITR1_IREMAP
description: TIM2 internal trigger 1 remapping description: TIM2 internal trigger 1 remapping
bit_offset: 29 bit_offset: 29
bit_size: 1 bit_size: 1
- name: PTP_PPS_REMAP - name: PTP_PPS_REMAP
description: Ethernet PTP PPS remapping description: Ethernet PTP PPS remapping
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
fieldset/MAPR2: fieldset/MAPR2:
description: AF remap and debug I/O configuration register description: AF remap and debug I/O configuration register
fields: fields:
- name: TIM15_REMAP - name: TIM15_REMAP
description: TIM15 remapping description: TIM15 remapping
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TIM16_REMAP - name: TIM16_REMAP
description: TIM16 remapping description: TIM16 remapping
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: TIM17_REMAP - name: TIM17_REMAP
description: TIM17 remapping description: TIM17 remapping
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: CEC_REMAP - name: CEC_REMAP
description: CEC remapping description: CEC remapping
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: TIM1_DMA_REMAP - name: TIM1_DMA_REMAP
description: TIM1 DMA remapping description: TIM1 DMA remapping
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: TIM9_REMAP - name: TIM9_REMAP
description: TIM9 remapping description: TIM9 remapping
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: TIM10_REMAP - name: TIM10_REMAP
description: TIM10 remapping description: TIM10 remapping
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: TIM11_REMAP - name: TIM11_REMAP
description: TIM11 remapping description: TIM11 remapping
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: TIM13_REMAP - name: TIM13_REMAP
description: TIM13 remapping description: TIM13 remapping
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: TIM14_REMAP - name: TIM14_REMAP
description: TIM14 remapping description: TIM14 remapping
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: FSMC_NADV - name: FSMC_NADV
description: NADV connect/disconnect description: NADV connect/disconnect
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: TIM67_DAC_DMA_REMAP - name: TIM67_DAC_DMA_REMAP
description: TIM67_DAC DMA remapping description: TIM67_DAC DMA remapping
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: TIM12_REMAP - name: TIM12_REMAP
description: TIM12 remapping description: TIM12 remapping
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: MISC_REMAP - name: MISC_REMAP
description: Miscellaneous features remapping description: Miscellaneous features remapping
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1

331
data/registers/bdma_v1.yaml
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@ -1,198 +1,197 @@
---
block/CH: block/CH:
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers" description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
items: items:
- name: CR - name: CR
description: DMA channel configuration register (DMA_CCR) description: DMA channel configuration register (DMA_CCR)
byte_offset: 0 byte_offset: 0
fieldset: CR fieldset: CR
- name: NDTR - name: NDTR
description: DMA channel 1 number of data register description: DMA channel 1 number of data register
byte_offset: 4 byte_offset: 4
fieldset: NDTR fieldset: NDTR
- name: PAR - name: PAR
description: DMA channel 1 peripheral address register description: DMA channel 1 peripheral address register
byte_offset: 8 byte_offset: 8
- name: MAR - name: MAR
description: DMA channel 1 memory address register description: DMA channel 1 memory address register
byte_offset: 12 byte_offset: 12
block/DMA: block/DMA:
description: DMA controller description: DMA controller
items: items:
- name: ISR - name: ISR
description: DMA interrupt status register (DMA_ISR) description: DMA interrupt status register (DMA_ISR)
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: ISR fieldset: ISR
- name: IFCR - name: IFCR
description: DMA interrupt flag clear register (DMA_IFCR) description: DMA interrupt flag clear register (DMA_IFCR)
byte_offset: 4 byte_offset: 4
access: Write access: Write
fieldset: ISR fieldset: ISR
- name: CH - name: CH
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers" description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
array: array:
len: 8 len: 8
stride: 20 stride: 20
byte_offset: 8 byte_offset: 8
block: CH block: CH
fieldset/CR: fieldset/CR:
description: DMA channel configuration register (DMA_CCR) description: DMA channel configuration register (DMA_CCR)
fields: fields:
- name: EN - name: EN
description: Channel enable description: Channel enable
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TCIE - name: TCIE
description: Transfer complete interrupt enable description: Transfer complete interrupt enable
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: HTIE - name: HTIE
description: Half Transfer interrupt enable description: Half Transfer interrupt enable
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TEIE - name: TEIE
description: Transfer error interrupt enable description: Transfer error interrupt enable
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: DIR - name: DIR
description: Data transfer direction description: Data transfer direction
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum: DIR enum: DIR
- name: CIRC - name: CIRC
description: Circular mode description: Circular mode
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum: CIRC enum: CIRC
- name: PINC - name: PINC
description: Peripheral increment mode description: Peripheral increment mode
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum: INC enum: INC
- name: MINC - name: MINC
description: Memory increment mode description: Memory increment mode
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
enum: INC enum: INC
- name: PSIZE - name: PSIZE
description: Peripheral size description: Peripheral size
bit_offset: 8 bit_offset: 8
bit_size: 2 bit_size: 2
enum: SIZE enum: SIZE
- name: MSIZE - name: MSIZE
description: Memory size description: Memory size
bit_offset: 10 bit_offset: 10
bit_size: 2 bit_size: 2
enum: SIZE enum: SIZE
- name: PL - name: PL
description: Channel Priority level description: Channel Priority level
bit_offset: 12 bit_offset: 12
bit_size: 2 bit_size: 2
enum: PL enum: PL
- name: MEM2MEM - name: MEM2MEM
description: Memory to memory mode description: Memory to memory mode
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
enum: MEMMEM enum: MEMMEM
fieldset/ISR: fieldset/ISR:
description: DMA interrupt status register (DMA_ISR) description: DMA interrupt status register (DMA_ISR)
fields: fields:
- name: GIF - name: GIF
description: Channel 1 Global interrupt flag description: Channel 1 Global interrupt flag
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 8 len: 8
stride: 4 stride: 4
- name: TCIF - name: TCIF
description: Channel 1 Transfer Complete flag description: Channel 1 Transfer Complete flag
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
array: array:
len: 8 len: 8
stride: 4 stride: 4
- name: HTIF - name: HTIF
description: Channel 1 Half Transfer Complete flag description: Channel 1 Half Transfer Complete flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
array: array:
len: 8 len: 8
stride: 4 stride: 4
- name: TEIF - name: TEIF
description: Channel 1 Transfer Error flag description: Channel 1 Transfer Error flag
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
array: array:
len: 8 len: 8
stride: 4 stride: 4
fieldset/NDTR: fieldset/NDTR:
description: DMA channel 1 number of data register description: DMA channel 1 number of data register
fields: fields:
- name: NDT - name: NDT
description: Number of data to transfer description: Number of data to transfer
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
enum/CIRC: enum/CIRC:
bit_size: 1 bit_size: 1
variants: variants:
- name: Disabled - name: Disabled
description: Circular buffer disabled description: Circular buffer disabled
value: 0 value: 0
- name: Enabled - name: Enabled
description: Circular buffer enabled description: Circular buffer enabled
value: 1 value: 1
enum/DIR: enum/DIR:
bit_size: 1 bit_size: 1
variants: variants:
- name: FromPeripheral - name: FromPeripheral
description: Read from peripheral description: Read from peripheral
value: 0 value: 0
- name: FromMemory - name: FromMemory
description: Read from memory description: Read from memory
value: 1 value: 1
enum/INC: enum/INC:
bit_size: 1 bit_size: 1
variants: variants:
- name: Disabled - name: Disabled
description: Increment mode disabled description: Increment mode disabled
value: 0 value: 0
- name: Enabled - name: Enabled
description: Increment mode enabled description: Increment mode enabled
value: 1 value: 1
enum/MEMMEM: enum/MEMMEM:
bit_size: 1 bit_size: 1
variants: variants:
- name: Disabled - name: Disabled
description: Memory to memory mode disabled description: Memory to memory mode disabled
value: 0 value: 0
- name: Enabled - name: Enabled
description: Memory to memory mode enabled description: Memory to memory mode enabled
value: 1 value: 1
enum/PL: enum/PL:
bit_size: 2 bit_size: 2
variants: variants:
- name: Low - name: Low
description: Low priority description: Low priority
value: 0 value: 0
- name: Medium - name: Medium
description: Medium priority description: Medium priority
value: 1 value: 1
- name: High - name: High
description: High priority description: High priority
value: 2 value: 2
- name: VeryHigh - name: VeryHigh
description: Very high priority description: Very high priority
value: 3 value: 3
enum/SIZE: enum/SIZE:
bit_size: 2 bit_size: 2
variants: variants:
- name: Bits8 - name: Bits8
description: 8-bit size description: 8-bit size
value: 0 value: 0
- name: Bits16 - name: Bits16
description: 16-bit size description: 16-bit size
value: 1 value: 1
- name: Bits32 - name: Bits32
description: 32-bit size description: 32-bit size
value: 2 value: 2

353
data/registers/bdma_v2.yaml
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@ -1,212 +1,211 @@
---
block/CH: block/CH:
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers" description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
items: items:
- name: CR - name: CR
description: DMA channel configuration register (DMA_CCR) description: DMA channel configuration register (DMA_CCR)
byte_offset: 0 byte_offset: 0
fieldset: CR fieldset: CR
- name: NDTR - name: NDTR
description: DMA channel 1 number of data register description: DMA channel 1 number of data register
byte_offset: 4 byte_offset: 4
fieldset: NDTR fieldset: NDTR
- name: PAR - name: PAR
description: DMA channel 1 peripheral address register description: DMA channel 1 peripheral address register
byte_offset: 8 byte_offset: 8
- name: MAR - name: MAR
description: DMA channel 1 memory address register description: DMA channel 1 memory address register
byte_offset: 12 byte_offset: 12
block/DMA: block/DMA:
description: DMA controller description: DMA controller
items: items:
- name: ISR - name: ISR
description: DMA interrupt status register (DMA_ISR) description: DMA interrupt status register (DMA_ISR)
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: ISR fieldset: ISR
- name: IFCR - name: IFCR
description: DMA interrupt flag clear register (DMA_IFCR) description: DMA interrupt flag clear register (DMA_IFCR)
byte_offset: 4 byte_offset: 4
access: Write access: Write
fieldset: ISR fieldset: ISR
- name: CH - name: CH
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers" description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
array: array:
len: 8 len: 8
stride: 20 stride: 20
byte_offset: 8 byte_offset: 8
block: CH block: CH
- name: CSELR - name: CSELR
description: channel selection register description: channel selection register
byte_offset: 168 byte_offset: 168
fieldset: CSELR fieldset: CSELR
fieldset/CR: fieldset/CR:
description: DMA channel configuration register (DMA_CCR) description: DMA channel configuration register (DMA_CCR)
fields: fields:
- name: EN - name: EN
description: Channel enable description: Channel enable
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TCIE - name: TCIE
description: Transfer complete interrupt enable description: Transfer complete interrupt enable
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: HTIE - name: HTIE
description: Half Transfer interrupt enable description: Half Transfer interrupt enable
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TEIE - name: TEIE
description: Transfer error interrupt enable description: Transfer error interrupt enable
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: DIR - name: DIR
description: Data transfer direction description: Data transfer direction
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum: DIR enum: DIR
- name: CIRC - name: CIRC
description: Circular mode description: Circular mode
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum: CIRC enum: CIRC
- name: PINC - name: PINC
description: Peripheral increment mode description: Peripheral increment mode
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum: INC enum: INC
- name: MINC - name: MINC
description: Memory increment mode description: Memory increment mode
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
enum: INC enum: INC
- name: PSIZE - name: PSIZE
description: Peripheral size description: Peripheral size
bit_offset: 8 bit_offset: 8
bit_size: 2 bit_size: 2
enum: SIZE enum: SIZE
- name: MSIZE - name: MSIZE
description: Memory size description: Memory size
bit_offset: 10 bit_offset: 10
bit_size: 2 bit_size: 2
enum: SIZE enum: SIZE
- name: PL - name: PL
description: Channel Priority level description: Channel Priority level
bit_offset: 12 bit_offset: 12
bit_size: 2 bit_size: 2
enum: PL enum: PL
- name: MEM2MEM - name: MEM2MEM
description: Memory to memory mode description: Memory to memory mode
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
enum: MEMMEM enum: MEMMEM
fieldset/CSELR: fieldset/CSELR:
description: channel selection register description: channel selection register
fields: fields:
- name: CS - name: CS
description: DMA channel selection description: DMA channel selection
bit_offset: 0 bit_offset: 0
bit_size: 4 bit_size: 4
array: array:
len: 8 len: 8
stride: 4 stride: 4
fieldset/ISR: fieldset/ISR:
description: DMA interrupt status register (DMA_ISR) description: DMA interrupt status register (DMA_ISR)
fields: fields:
- name: GIF - name: GIF
description: Channel 1 Global interrupt flag description: Channel 1 Global interrupt flag
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 8 len: 8
stride: 4 stride: 4
- name: TCIF - name: TCIF
description: Channel 1 Transfer Complete flag description: Channel 1 Transfer Complete flag
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
array: array:
len: 8 len: 8
stride: 4 stride: 4
- name: HTIF - name: HTIF
description: Channel 1 Half Transfer Complete flag description: Channel 1 Half Transfer Complete flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
array: array:
len: 8 len: 8
stride: 4 stride: 4
- name: TEIF - name: TEIF
description: Channel 1 Transfer Error flag description: Channel 1 Transfer Error flag
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
array: array:
len: 8 len: 8
stride: 4 stride: 4
fieldset/NDTR: fieldset/NDTR:
description: DMA channel 1 number of data register description: DMA channel 1 number of data register
fields: fields:
- name: NDT - name: NDT
description: Number of data to transfer description: Number of data to transfer
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
enum/CIRC: enum/CIRC:
bit_size: 1 bit_size: 1
variants: variants:
- name: Disabled - name: Disabled
description: Circular buffer disabled description: Circular buffer disabled
value: 0 value: 0
- name: Enabled - name: Enabled
description: Circular buffer enabled description: Circular buffer enabled
value: 1 value: 1
enum/DIR: enum/DIR:
bit_size: 1 bit_size: 1
variants: variants:
- name: FromPeripheral - name: FromPeripheral
description: Read from peripheral description: Read from peripheral
value: 0 value: 0
- name: FromMemory - name: FromMemory
description: Read from memory description: Read from memory
value: 1 value: 1
enum/INC: enum/INC:
bit_size: 1 bit_size: 1
variants: variants:
- name: Disabled - name: Disabled
description: Increment mode disabled description: Increment mode disabled
value: 0 value: 0
- name: Enabled - name: Enabled
description: Increment mode enabled description: Increment mode enabled
value: 1 value: 1
enum/MEMMEM: enum/MEMMEM:
bit_size: 1 bit_size: 1
variants: variants:
- name: Disabled - name: Disabled
description: Memory to memory mode disabled description: Memory to memory mode disabled
value: 0 value: 0
- name: Enabled - name: Enabled
description: Memory to memory mode enabled description: Memory to memory mode enabled
value: 1 value: 1
enum/PL: enum/PL:
bit_size: 2 bit_size: 2
variants: variants:
- name: Low - name: Low
description: Low priority description: Low priority
value: 0 value: 0
- name: Medium - name: Medium
description: Medium priority description: Medium priority
value: 1 value: 1
- name: High - name: High
description: High priority description: High priority
value: 2 value: 2
- name: VeryHigh - name: VeryHigh
description: Very high priority description: Very high priority
value: 3 value: 3
enum/SIZE: enum/SIZE:
bit_size: 2 bit_size: 2
variants: variants:
- name: Bits8 - name: Bits8
description: 8-bit size description: 8-bit size
value: 0 value: 0
- name: Bits16 - name: Bits16
description: 16-bit size description: 16-bit size
value: 1 value: 1
- name: Bits32 - name: Bits32
description: 32-bit size description: 32-bit size
value: 2 value: 2

245
data/registers/bkp_v1.yaml
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@ -1,144 +1,143 @@
---
block/BKP: block/BKP:
description: Backup registers description: Backup registers
items: items:
- name: DR - name: DR
description: Data register description: Data register
array: array:
offsets: offsets:
- 0 - 0
- 4 - 4
- 8 - 8
- 12 - 12
- 16 - 16
- 20 - 20
- 24 - 24
- 28 - 28
- 32 - 32
- 36 - 36
- 60 - 60
- 64 - 64
- 68 - 68
- 72 - 72
- 76 - 76
- 80 - 80
- 84 - 84
- 88 - 88
- 92 - 92
- 96 - 96
- 100 - 100
- 104 - 104
- 108 - 108
- 112 - 112
- 116 - 116
- 120 - 120
- 124 - 124
- 128 - 128
- 132 - 132
- 136 - 136
- 140 - 140
- 144 - 144
- 148 - 148
- 152 - 152
- 156 - 156
- 160 - 160
- 164 - 164
- 168 - 168
- 172 - 172
- 176 - 176
- 180 - 180
- 184 - 184
byte_offset: 0 byte_offset: 0
fieldset: DR fieldset: DR
- name: RTCCR - name: RTCCR
description: RTC clock calibration register description: RTC clock calibration register
byte_offset: 40 byte_offset: 40
fieldset: RTCCR fieldset: RTCCR
- name: CR - name: CR
description: Control register description: Control register
byte_offset: 44 byte_offset: 44
fieldset: CR fieldset: CR
- name: CSR - name: CSR
description: Control/status register description: Control/status register
byte_offset: 48 byte_offset: 48
fieldset: CSR fieldset: CSR
fieldset/CR: fieldset/CR:
description: Control register description: Control register
fields: fields:
- name: TPE - name: TPE
description: Tamper pin enable description: Tamper pin enable
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TPAL - name: TPAL
description: Tamper pin active level description: Tamper pin active level
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
enum: TPAL enum: TPAL
fieldset/CSR: fieldset/CSR:
description: Control/status register description: Control/status register
fields: fields:
- name: CTE - name: CTE
description: Clear Tamper event description: Clear Tamper event
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: CTI - name: CTI
description: Clear Tamper Interrupt description: Clear Tamper Interrupt
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: TPIE - name: TPIE
description: Tamper Pin interrupt enable description: Tamper Pin interrupt enable
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TEF - name: TEF
description: Tamper Event Flag description: Tamper Event Flag
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: TIF - name: TIF
description: Tamper Interrupt Flag description: Tamper Interrupt Flag
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
fieldset/DR: fieldset/DR:
description: Data register description: Data register
fields: fields:
- name: D - name: D
description: Backup data description: Backup data
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
fieldset/RTCCR: fieldset/RTCCR:
description: RTC clock calibration register description: RTC clock calibration register
fields: fields:
- name: CAL - name: CAL
description: Calibration value description: Calibration value
bit_offset: 0 bit_offset: 0
bit_size: 7 bit_size: 7
- name: CCO - name: CCO
description: Calibration Clock Output description: Calibration Clock Output
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: ASOE - name: ASOE
description: Alarm or second output enable description: Alarm or second output enable
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: ASOS - name: ASOS
description: Alarm or second output selection description: Alarm or second output selection
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
enum: ASOS enum: ASOS
enum/ASOS: enum/ASOS:
bit_size: 1 bit_size: 1
variants: variants:
- name: Alarm - name: Alarm
description: RTC Alarm pulse output selected description: RTC Alarm pulse output selected
value: 0 value: 0
- name: Second - name: Second
description: RTC Second pulse output selected description: RTC Second pulse output selected
value: 1 value: 1
enum/TPAL: enum/TPAL:
bit_size: 1 bit_size: 1
variants: variants:
- name: High - name: High
description: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) description: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set)
value: 0 value: 0
- name: Low - name: Low
description: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) description: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set)
value: 1 value: 1

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data/registers/can_bxcan.yaml
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data/registers/can_fdcan.yaml
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29
data/registers/crc_v1.yaml
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@ -1,21 +1,20 @@
---
block/CRC: block/CRC:
description: Cyclic Redundancy Check calculation unit description: Cyclic Redundancy Check calculation unit
items: items:
- name: DR - name: DR
description: Data register description: Data register
byte_offset: 0 byte_offset: 0
- name: IDR - name: IDR
description: Independent Data register description: Independent Data register
byte_offset: 4 byte_offset: 4
- name: CR - name: CR
description: Control register description: Control register
byte_offset: 8 byte_offset: 8
fieldset: CR fieldset: CR
fieldset/CR: fieldset/CR:
description: Control register description: Control register
fields: fields:
- name: RESET - name: RESET
description: RESET bit description: RESET bit
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1

141
data/registers/crc_v2.yaml
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@ -1,86 +1,85 @@
---
block/CRC: block/CRC:
description: Cyclic Redundancy Check calculation unit description: Cyclic Redundancy Check calculation unit
items: items:
- name: DR - name: DR
description: Data register description: Data register
byte_offset: 0 byte_offset: 0
- name: DR16 - name: DR16
description: Data register - half-word sized description: Data register - half-word sized
byte_offset: 0 byte_offset: 0
bit_size: 16 bit_size: 16
- name: DR8 - name: DR8
description: Data register - byte sized description: Data register - byte sized
byte_offset: 0 byte_offset: 0
bit_size: 8 bit_size: 8
- name: IDR - name: IDR
description: Independent Data register description: Independent Data register
byte_offset: 4 byte_offset: 4
- name: CR - name: CR
description: Control register description: Control register
byte_offset: 8 byte_offset: 8
fieldset: CR fieldset: CR
- name: INIT - name: INIT
description: Initial CRC value description: Initial CRC value
byte_offset: 16 byte_offset: 16
fieldset/CR: fieldset/CR:
description: Control register description: Control register
fields: fields:
- name: RESET - name: RESET
description: RESET bit description: RESET bit
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: POLYSIZE - name: POLYSIZE
description: Polynomial size description: Polynomial size
bit_offset: 3 bit_offset: 3
bit_size: 2 bit_size: 2
enum: POLYSIZE enum: POLYSIZE
- name: REV_IN - name: REV_IN
description: Reverse input data description: Reverse input data
bit_offset: 5 bit_offset: 5
bit_size: 2 bit_size: 2
enum: REV_IN enum: REV_IN
- name: REV_OUT - name: REV_OUT
description: Reverse output data description: Reverse output data
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
enum: REV_OUT enum: REV_OUT
enum/POLYSIZE: enum/POLYSIZE:
bit_size: 2 bit_size: 2
variants: variants:
- name: Polysize32 - name: Polysize32
description: 32-bit polynomial description: 32-bit polynomial
value: 0 value: 0
- name: Polysize16 - name: Polysize16
description: 16-bit polynomial description: 16-bit polynomial
value: 1 value: 1
- name: Polysize8 - name: Polysize8
description: 8-bit polynomial description: 8-bit polynomial
value: 2 value: 2
- name: Polysize7 - name: Polysize7
description: 7-bit polynomial description: 7-bit polynomial
value: 3 value: 3
enum/REV_IN: enum/REV_IN:
bit_size: 2 bit_size: 2
variants: variants:
- name: Normal - name: Normal
description: Bit order not affected description: Bit order not affected
value: 0 value: 0
- name: Byte - name: Byte
description: Bit reversal done by byte description: Bit reversal done by byte
value: 1 value: 1
- name: HalfWord - name: HalfWord
description: Bit reversal done by half-word description: Bit reversal done by half-word
value: 2 value: 2
- name: Word - name: Word
description: Bit reversal done by word description: Bit reversal done by word
value: 3 value: 3
enum/REV_OUT: enum/REV_OUT:
bit_size: 1 bit_size: 1
variants: variants:
- name: Normal - name: Normal
description: Bit order not affected description: Bit order not affected
value: 0 value: 0
- name: Reversed - name: Reversed
description: Bit reversed output description: Bit reversed output
value: 1 value: 1

147
data/registers/crc_v3.yaml
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@ -1,89 +1,88 @@
---
block/CRC: block/CRC:
description: Cyclic Redundancy Check calculation unit description: Cyclic Redundancy Check calculation unit
items: items:
- name: DR - name: DR
description: Data register description: Data register
byte_offset: 0 byte_offset: 0
- name: DR16 - name: DR16
description: Data register - half-word sized description: Data register - half-word sized
byte_offset: 0 byte_offset: 0
bit_size: 16 bit_size: 16
- name: DR8 - name: DR8
description: Data register - byte sized description: Data register - byte sized
byte_offset: 0 byte_offset: 0
bit_size: 8 bit_size: 8
- name: IDR - name: IDR
description: Independent Data register description: Independent Data register
byte_offset: 4 byte_offset: 4
- name: CR - name: CR
description: Control register description: Control register
byte_offset: 8 byte_offset: 8
fieldset: CR fieldset: CR
- name: INIT - name: INIT
description: Initial CRC value description: Initial CRC value
byte_offset: 16 byte_offset: 16
- name: POL - name: POL
description: CRC polynomial description: CRC polynomial
byte_offset: 20 byte_offset: 20
fieldset/CR: fieldset/CR:
description: Control register description: Control register
fields: fields:
- name: RESET - name: RESET
description: RESET bit description: RESET bit
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: POLYSIZE - name: POLYSIZE
description: Polynomial size description: Polynomial size
bit_offset: 3 bit_offset: 3
bit_size: 2 bit_size: 2
enum: POLYSIZE enum: POLYSIZE
- name: REV_IN - name: REV_IN
description: Reverse input data description: Reverse input data
bit_offset: 5 bit_offset: 5
bit_size: 2 bit_size: 2
enum: REV_IN enum: REV_IN
- name: REV_OUT - name: REV_OUT
description: Reverse output data description: Reverse output data
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
enum: REV_OUT enum: REV_OUT
enum/POLYSIZE: enum/POLYSIZE:
bit_size: 2 bit_size: 2
variants: variants:
- name: Polysize32 - name: Polysize32
description: 32-bit polynomial description: 32-bit polynomial
value: 0 value: 0
- name: Polysize16 - name: Polysize16
description: 16-bit polynomial description: 16-bit polynomial
value: 1 value: 1
- name: Polysize8 - name: Polysize8
description: 8-bit polynomial description: 8-bit polynomial
value: 2 value: 2
- name: Polysize7 - name: Polysize7
description: 7-bit polynomial description: 7-bit polynomial
value: 3 value: 3
enum/REV_IN: enum/REV_IN:
bit_size: 2 bit_size: 2
variants: variants:
- name: Normal - name: Normal
description: Bit order not affected description: Bit order not affected
value: 0 value: 0
- name: Byte - name: Byte
description: Bit reversal done by byte description: Bit reversal done by byte
value: 1 value: 1
- name: HalfWord - name: HalfWord
description: Bit reversal done by half-word description: Bit reversal done by half-word
value: 2 value: 2
- name: Word - name: Word
description: Bit reversal done by word description: Bit reversal done by word
value: 3 value: 3
enum/REV_OUT: enum/REV_OUT:
bit_size: 1 bit_size: 1
variants: variants:
- name: Normal - name: Normal
description: Bit order not affected description: Bit order not affected
value: 0 value: 0
- name: Reversed - name: Reversed
description: Bit reversed output description: Bit reversed output
value: 1 value: 1

263
data/registers/crs_v1.yaml
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@ -1,150 +1,149 @@
---
block/CRS: block/CRS:
description: Clock recovery system description: Clock recovery system
items: items:
- name: CR - name: CR
description: control register description: control register
byte_offset: 0 byte_offset: 0
fieldset: CR fieldset: CR
- name: CFGR - name: CFGR
description: configuration register description: configuration register
byte_offset: 4 byte_offset: 4
fieldset: CFGR fieldset: CFGR
- name: ISR - name: ISR
description: interrupt and status register description: interrupt and status register
byte_offset: 8 byte_offset: 8
access: Read access: Read
fieldset: ISR fieldset: ISR
- name: ICR - name: ICR
description: interrupt flag clear register description: interrupt flag clear register
byte_offset: 12 byte_offset: 12
fieldset: ICR fieldset: ICR
fieldset/CFGR: fieldset/CFGR:
description: configuration register description: configuration register
fields: fields:
- name: RELOAD - name: RELOAD
description: Counter reload value description: Counter reload value
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
- name: FELIM - name: FELIM
description: Frequency error limit description: Frequency error limit
bit_offset: 16 bit_offset: 16
bit_size: 8 bit_size: 8
- name: SYNCDIV - name: SYNCDIV
description: SYNC divider description: SYNC divider
bit_offset: 24 bit_offset: 24
bit_size: 3 bit_size: 3
- name: SYNCSRC - name: SYNCSRC
description: SYNC signal source selection description: SYNC signal source selection
bit_offset: 28 bit_offset: 28
bit_size: 2 bit_size: 2
enum: SYNCSRC enum: SYNCSRC
- name: SYNCPOL - name: SYNCPOL
description: SYNC polarity selection description: SYNC polarity selection
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: control register description: control register
fields: fields:
- name: SYNCOKIE - name: SYNCOKIE
description: SYNC event OK interrupt enable description: SYNC event OK interrupt enable
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: SYNCWARNIE - name: SYNCWARNIE
description: SYNC warning interrupt enable description: SYNC warning interrupt enable
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: ERRIE - name: ERRIE
description: Synchronization or trimming error interrupt enable description: Synchronization or trimming error interrupt enable
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: ESYNCIE - name: ESYNCIE
description: Expected SYNC interrupt enable description: Expected SYNC interrupt enable
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: CEN - name: CEN
description: Frequency error counter enable description: Frequency error counter enable
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: AUTOTRIMEN - name: AUTOTRIMEN
description: Automatic trimming enable description: Automatic trimming enable
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: SWSYNC - name: SWSYNC
description: Generate software SYNC event description: Generate software SYNC event
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: TRIM - name: TRIM
description: HSI48 oscillator smooth trimming description: HSI48 oscillator smooth trimming
bit_offset: 8 bit_offset: 8
bit_size: 6 bit_size: 6
fieldset/ICR: fieldset/ICR:
description: interrupt flag clear register description: interrupt flag clear register
fields: fields:
- name: SYNCOKC - name: SYNCOKC
description: SYNC event OK clear flag description: SYNC event OK clear flag
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: SYNCWARNC - name: SYNCWARNC
description: SYNC warning clear flag description: SYNC warning clear flag
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: ERRC - name: ERRC
description: Error clear flag description: Error clear flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: ESYNCC - name: ESYNCC
description: Expected SYNC clear flag description: Expected SYNC clear flag
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
fieldset/ISR: fieldset/ISR:
description: interrupt and status register description: interrupt and status register
fields: fields:
- name: SYNCOKF - name: SYNCOKF
description: SYNC event OK flag description: SYNC event OK flag
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: SYNCWARNF - name: SYNCWARNF
description: SYNC warning flag description: SYNC warning flag
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: ERRF - name: ERRF
description: Error flag description: Error flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: ESYNCF - name: ESYNCF
description: Expected SYNC flag description: Expected SYNC flag
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: SYNCERR - name: SYNCERR
description: SYNC error description: SYNC error
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: SYNCMISS - name: SYNCMISS
description: SYNC missed description: SYNC missed
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: TRIMOVF - name: TRIMOVF
description: Trimming overflow or underflow description: Trimming overflow or underflow
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: FEDIR - name: FEDIR
description: Frequency error direction description: Frequency error direction
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: FECAP - name: FECAP
description: Frequency error capture description: Frequency error capture
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16
enum/SYNCSRC: enum/SYNCSRC:
bit_size: 2 bit_size: 2
variants: variants:
- name: GPIO - name: GPIO
description: GPIO selected as SYNC signal source description: GPIO selected as SYNC signal source
value: 0 value: 0
- name: LSE - name: LSE
description: LSE selected as SYNC signal source description: LSE selected as SYNC signal source
value: 1 value: 1
- name: USB - name: USB
description: USB SOF selected as SYNC signal source description: USB SOF selected as SYNC signal source
value: 2 value: 2

439
data/registers/dac_v1.yaml
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@ -1,262 +1,261 @@
---
block/DAC: block/DAC:
description: Digital-to-analog converter description: Digital-to-analog converter
items: items:
- name: CR - name: CR
description: control register description: control register
byte_offset: 0 byte_offset: 0
fieldset: CR fieldset: CR
- name: SWTRIGR - name: SWTRIGR
description: software trigger register description: software trigger register
byte_offset: 4 byte_offset: 4
access: Write access: Write
fieldset: SWTRIGR fieldset: SWTRIGR
- name: DHR12R - name: DHR12R
description: channel 12-bit right-aligned data holding register description: channel 12-bit right-aligned data holding register
array: array:
len: 2 len: 2
stride: 12 stride: 12
byte_offset: 8 byte_offset: 8
fieldset: DHR12R fieldset: DHR12R
- name: DHR12L - name: DHR12L
description: channel 12-bit left-aligned data holding register description: channel 12-bit left-aligned data holding register
array: array:
len: 2 len: 2
stride: 12 stride: 12
byte_offset: 12 byte_offset: 12
fieldset: DHR12L fieldset: DHR12L
- name: DHR8R - name: DHR8R
description: channel 8-bit right-aligned data holding register description: channel 8-bit right-aligned data holding register
array: array:
len: 2 len: 2
stride: 12 stride: 12
byte_offset: 16 byte_offset: 16
fieldset: DHR8R fieldset: DHR8R
- name: DHR12RD - name: DHR12RD
description: Dual DAC 12-bit right-aligned data holding register description: Dual DAC 12-bit right-aligned data holding register
byte_offset: 32 byte_offset: 32
fieldset: DHR12RD fieldset: DHR12RD
- name: DHR12LD - name: DHR12LD
description: DUAL DAC 12-bit left aligned data holding register description: DUAL DAC 12-bit left aligned data holding register
byte_offset: 36 byte_offset: 36
fieldset: DHR12LD fieldset: DHR12LD
- name: DHR8RD - name: DHR8RD
description: DUAL DAC 8-bit right aligned data holding register description: DUAL DAC 8-bit right aligned data holding register
byte_offset: 40 byte_offset: 40
fieldset: DHR8RD fieldset: DHR8RD
- name: DOR - name: DOR
description: channel data output register description: channel data output register
array: array:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 44 byte_offset: 44
access: Read access: Read
fieldset: DOR fieldset: DOR
- name: SR - name: SR
description: status register description: status register
byte_offset: 52 byte_offset: 52
fieldset: SR fieldset: SR
fieldset/CR: fieldset/CR:
description: control register description: control register
fields: fields:
- name: EN - name: EN
description: DAC channel enable description: DAC channel enable
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: BOFF - name: BOFF
description: DAC channel output buffer disable description: DAC channel output buffer disable
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: TEN - name: TEN
description: DAC channel trigger enable description: DAC channel trigger enable
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: TSEL1 - name: TSEL1
description: DAC channel 1 trigger selection description: DAC channel 1 trigger selection
bit_offset: 3 bit_offset: 3
bit_size: 3 bit_size: 3
enum: TSEL1 enum: TSEL1
- name: WAVE - name: WAVE
description: DAC channel noise/triangle wave generation enable description: DAC channel noise/triangle wave generation enable
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
array: array:
len: 2 len: 2
stride: 16 stride: 16
enum: WAVE enum: WAVE
- name: MAMP - name: MAMP
description: DAC channel mask/amplitude selector description: DAC channel mask/amplitude selector
bit_offset: 8 bit_offset: 8
bit_size: 4 bit_size: 4
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: DMAEN - name: DMAEN
description: DAC channel DMA enable description: DAC channel DMA enable
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: DMAUDRIE - name: DMAUDRIE
description: DAC channel DMA Underrun Interrupt enable description: DAC channel DMA Underrun Interrupt enable
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: TSEL2 - name: TSEL2
description: DAC channel 2 trigger selection description: DAC channel 2 trigger selection
bit_offset: 19 bit_offset: 19
bit_size: 3 bit_size: 3
enum: TSEL2 enum: TSEL2
fieldset/DHR12L: fieldset/DHR12L:
description: channel 12-bit left-aligned data holding register description: channel 12-bit left-aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 12-bit left-aligned data description: DAC channel 12-bit left-aligned data
bit_offset: 4 bit_offset: 4
bit_size: 12 bit_size: 12
fieldset/DHR12LD: fieldset/DHR12LD:
description: DUAL DAC 12-bit left aligned data holding register description: DUAL DAC 12-bit left aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 12-bit left-aligned data description: DAC channel 12-bit left-aligned data
bit_offset: 4 bit_offset: 4
bit_size: 12 bit_size: 12
array: array:
len: 2 len: 2
stride: 16 stride: 16
fieldset/DHR12R: fieldset/DHR12R:
description: channel 12-bit right-aligned data holding register description: channel 12-bit right-aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 12-bit right-aligned data description: DAC channel 12-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
fieldset/DHR12RD: fieldset/DHR12RD:
description: Dual DAC 12-bit right-aligned data holding register description: Dual DAC 12-bit right-aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 12-bit right-aligned data description: DAC channel 12-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
array: array:
len: 2 len: 2
stride: 16 stride: 16
fieldset/DHR8R: fieldset/DHR8R:
description: channel 8-bit right-aligned data holding register description: channel 8-bit right-aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 8-bit right-aligned data description: DAC channel 8-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
fieldset/DHR8RD: fieldset/DHR8RD:
description: DUAL DAC 8-bit right aligned data holding register description: DUAL DAC 8-bit right aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 8-bit right-aligned data description: DAC channel 8-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
array: array:
len: 2 len: 2
stride: 8 stride: 8
fieldset/DOR: fieldset/DOR:
description: channel data output register description: channel data output register
fields: fields:
- name: DOR - name: DOR
description: DAC channel data output description: DAC channel data output
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
fieldset/SR: fieldset/SR:
description: status register description: status register
fields: fields:
- name: DMAUDR - name: DMAUDR
description: DAC channel DMA underrun flag description: DAC channel DMA underrun flag
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
fieldset/SWTRIGR: fieldset/SWTRIGR:
description: software trigger register description: software trigger register
fields: fields:
- name: SWTRIG - name: SWTRIG
description: DAC channel software trigger description: DAC channel software trigger
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum/TSEL1: enum/TSEL1:
bit_size: 3 bit_size: 3
variants: variants:
- name: TIM6_TRGO - name: TIM6_TRGO
description: Timer 6 TRGO event description: Timer 6 TRGO event
value: 0 value: 0
- name: TIM3_TRGO - name: TIM3_TRGO
description: Timer 3 TRGO event description: Timer 3 TRGO event
value: 1 value: 1
- name: TIM7_TRGO - name: TIM7_TRGO
description: Timer 7 TRGO event description: Timer 7 TRGO event
value: 2 value: 2
- name: TIM15_TRGO - name: TIM15_TRGO
description: Timer 15 TRGO event description: Timer 15 TRGO event
value: 3 value: 3
- name: TIM2_TRGO - name: TIM2_TRGO
description: Timer 2 TRGO event description: Timer 2 TRGO event
value: 4 value: 4
- name: EXTI9 - name: EXTI9
description: EXTI line9 description: EXTI line9
value: 6 value: 6
- name: SOFTWARE - name: SOFTWARE
description: Software trigger description: Software trigger
value: 7 value: 7
enum/TSEL2: enum/TSEL2:
bit_size: 3 bit_size: 3
variants: variants:
- name: TIM6_TRGO - name: TIM6_TRGO
description: Timer 6 TRGO event description: Timer 6 TRGO event
value: 0 value: 0
- name: TIM8_TRGO - name: TIM8_TRGO
description: Timer 8 TRGO event description: Timer 8 TRGO event
value: 1 value: 1
- name: TIM7_TRGO - name: TIM7_TRGO
description: Timer 7 TRGO event description: Timer 7 TRGO event
value: 2 value: 2
- name: TIM5_TRGO - name: TIM5_TRGO
description: Timer 5 TRGO event description: Timer 5 TRGO event
value: 3 value: 3
- name: TIM2_TRGO - name: TIM2_TRGO
description: Timer 2 TRGO event description: Timer 2 TRGO event
value: 4 value: 4
- name: TIM4_TRGO - name: TIM4_TRGO
description: Timer 4 TRGO event description: Timer 4 TRGO event
value: 5 value: 5
- name: EXTI9 - name: EXTI9
description: EXTI line9 description: EXTI line9
value: 6 value: 6
- name: SOFTWARE - name: SOFTWARE
description: Software trigger description: Software trigger
value: 7 value: 7
enum/WAVE: enum/WAVE:
bit_size: 2 bit_size: 2
variants: variants:
- name: Disabled - name: Disabled
description: Wave generation disabled description: Wave generation disabled
value: 0 value: 0
- name: Noise - name: Noise
description: Noise wave generation enabled description: Noise wave generation enabled
value: 1 value: 1
- name: Triangle - name: Triangle
description: Triangle wave generation enabled description: Triangle wave generation enabled
value: 2 value: 2

579
data/registers/dac_v2.yaml
View File

@ -1,347 +1,346 @@
---
block/DAC: block/DAC:
description: Digital-to-analog converter description: Digital-to-analog converter
items: items:
- name: CR - name: CR
description: control register description: control register
byte_offset: 0 byte_offset: 0
fieldset: CR fieldset: CR
- name: SWTRIGR - name: SWTRIGR
description: software trigger register description: software trigger register
byte_offset: 4 byte_offset: 4
access: Write access: Write
fieldset: SWTRIGR fieldset: SWTRIGR
- name: DHR12R - name: DHR12R
description: channel 12-bit right-aligned data holding register description: channel 12-bit right-aligned data holding register
array: array:
len: 2 len: 2
stride: 12 stride: 12
byte_offset: 8 byte_offset: 8
fieldset: DHR12R fieldset: DHR12R
- name: DHR12L - name: DHR12L
description: channel 12-bit left-aligned data holding register description: channel 12-bit left-aligned data holding register
array: array:
len: 2 len: 2
stride: 12 stride: 12
byte_offset: 12 byte_offset: 12
fieldset: DHR12L fieldset: DHR12L
- name: DHR8R - name: DHR8R
description: channel 8-bit right-aligned data holding register description: channel 8-bit right-aligned data holding register
array: array:
len: 2 len: 2
stride: 12 stride: 12
byte_offset: 16 byte_offset: 16
fieldset: DHR8R fieldset: DHR8R
- name: DHR12RD - name: DHR12RD
description: Dual DAC 12-bit right-aligned data holding register description: Dual DAC 12-bit right-aligned data holding register
byte_offset: 32 byte_offset: 32
fieldset: DHR12RD fieldset: DHR12RD
- name: DHR12LD - name: DHR12LD
description: DUAL DAC 12-bit left aligned data holding register description: DUAL DAC 12-bit left aligned data holding register
byte_offset: 36 byte_offset: 36
fieldset: DHR12LD fieldset: DHR12LD
- name: DHR8RD - name: DHR8RD
description: DUAL DAC 8-bit right aligned data holding register description: DUAL DAC 8-bit right aligned data holding register
byte_offset: 40 byte_offset: 40
fieldset: DHR8RD fieldset: DHR8RD
- name: DOR - name: DOR
description: channel data output register description: channel data output register
array: array:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 44 byte_offset: 44
access: Read access: Read
fieldset: DOR fieldset: DOR
- name: SR - name: SR
description: status register description: status register
byte_offset: 52 byte_offset: 52
fieldset: SR fieldset: SR
- name: CCR - name: CCR
description: calibration control register description: calibration control register
byte_offset: 56 byte_offset: 56
fieldset: CCR fieldset: CCR
- name: MCR - name: MCR
description: mode control register description: mode control register
byte_offset: 60 byte_offset: 60
fieldset: MCR fieldset: MCR
- name: SHSR1 - name: SHSR1
description: Sample and Hold sample time register description: Sample and Hold sample time register
array: array:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 64 byte_offset: 64
fieldset: SHSR fieldset: SHSR
- name: SHHR - name: SHHR
description: Sample and Hold hold time register description: Sample and Hold hold time register
byte_offset: 72 byte_offset: 72
fieldset: SHHR fieldset: SHHR
- name: SHRR - name: SHRR
description: Sample and Hold refresh time register description: Sample and Hold refresh time register
byte_offset: 76 byte_offset: 76
fieldset: SHRR fieldset: SHRR
fieldset/CCR: fieldset/CCR:
description: calibration control register description: calibration control register
fields: fields:
- name: OTRIM1 - name: OTRIM1
description: DAC Channel 1 offset trimming value description: DAC Channel 1 offset trimming value
bit_offset: 0 bit_offset: 0
bit_size: 5 bit_size: 5
- name: OTRIM2 - name: OTRIM2
description: DAC Channel 2 offset trimming value description: DAC Channel 2 offset trimming value
bit_offset: 16 bit_offset: 16
bit_size: 5 bit_size: 5
fieldset/CR: fieldset/CR:
description: control register description: control register
fields: fields:
- name: EN - name: EN
description: DAC channel enable description: DAC channel enable
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: TEN - name: TEN
description: DAC channel trigger enable description: DAC channel trigger enable
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: TSEL1 - name: TSEL1
description: DAC channel 1 trigger selection description: DAC channel 1 trigger selection
bit_offset: 3 bit_offset: 3
bit_size: 3 bit_size: 3
enum: TSEL1 enum: TSEL1
- name: WAVE - name: WAVE
description: DAC channel noise/triangle wave generation enable description: DAC channel noise/triangle wave generation enable
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
array: array:
len: 2 len: 2
stride: 16 stride: 16
enum: WAVE enum: WAVE
- name: MAMP - name: MAMP
description: DAC channel mask/amplitude selector description: DAC channel mask/amplitude selector
bit_offset: 8 bit_offset: 8
bit_size: 4 bit_size: 4
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: DMAEN - name: DMAEN
description: DAC channel DMA enable description: DAC channel DMA enable
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: DMAUDRIE - name: DMAUDRIE
description: DAC channel DMA Underrun Interrupt enable description: DAC channel DMA Underrun Interrupt enable
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: CEN - name: CEN
description: DAC channel calibration enable description: DAC channel calibration enable
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: TSEL2 - name: TSEL2
description: DAC channel 2 trigger selection description: DAC channel 2 trigger selection
bit_offset: 19 bit_offset: 19
bit_size: 3 bit_size: 3
enum: TSEL2 enum: TSEL2
fieldset/DHR12L: fieldset/DHR12L:
description: channel 12-bit left-aligned data holding register description: channel 12-bit left-aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 12-bit left-aligned data description: DAC channel 12-bit left-aligned data
bit_offset: 4 bit_offset: 4
bit_size: 12 bit_size: 12
fieldset/DHR12LD: fieldset/DHR12LD:
description: DUAL DAC 12-bit left aligned data holding register description: DUAL DAC 12-bit left aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 12-bit left-aligned data description: DAC channel 12-bit left-aligned data
bit_offset: 4 bit_offset: 4
bit_size: 12 bit_size: 12
array: array:
len: 2 len: 2
stride: 16 stride: 16
fieldset/DHR12R: fieldset/DHR12R:
description: channel 12-bit right-aligned data holding register description: channel 12-bit right-aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 12-bit right-aligned data description: DAC channel 12-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
fieldset/DHR12RD: fieldset/DHR12RD:
description: Dual DAC 12-bit right-aligned data holding register description: Dual DAC 12-bit right-aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 12-bit right-aligned data description: DAC channel 12-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
array: array:
len: 2 len: 2
stride: 16 stride: 16
fieldset/DHR8R: fieldset/DHR8R:
description: channel 8-bit right-aligned data holding register description: channel 8-bit right-aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 8-bit right-aligned data description: DAC channel 8-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
fieldset/DHR8RD: fieldset/DHR8RD:
description: DUAL DAC 8-bit right aligned data holding register description: DUAL DAC 8-bit right aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 8-bit right-aligned data description: DAC channel 8-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
array: array:
len: 2 len: 2
stride: 8 stride: 8
fieldset/DOR: fieldset/DOR:
description: channel data output register description: channel data output register
fields: fields:
- name: DOR - name: DOR
description: DAC channel data output description: DAC channel data output
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
fieldset/MCR: fieldset/MCR:
description: mode control register description: mode control register
fields: fields:
- name: MODE - name: MODE
description: DAC channel mode description: DAC channel mode
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
array: array:
len: 2 len: 2
stride: 16 stride: 16
fieldset/SHHR: fieldset/SHHR:
description: Sample and Hold hold time register description: Sample and Hold hold time register
fields: fields:
- name: THOLD - name: THOLD
description: DAC channel hold Time description: DAC channel hold Time
bit_offset: 0 bit_offset: 0
bit_size: 10 bit_size: 10
array: array:
len: 2 len: 2
stride: 16 stride: 16
fieldset/SHRR: fieldset/SHRR:
description: Sample and Hold refresh time register description: Sample and Hold refresh time register
fields: fields:
- name: TREFRESH - name: TREFRESH
description: DAC channel refresh Time description: DAC channel refresh Time
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
array: array:
len: 2 len: 2
stride: 16 stride: 16
fieldset/SHSR: fieldset/SHSR:
description: Sample and Hold sample time register description: Sample and Hold sample time register
fields: fields:
- name: TSAMPLE - name: TSAMPLE
description: DAC channel sample Time description: DAC channel sample Time
bit_offset: 0 bit_offset: 0
bit_size: 10 bit_size: 10
fieldset/SR: fieldset/SR:
description: status register description: status register
fields: fields:
- name: DMAUDR - name: DMAUDR
description: DAC channel DMA underrun flag description: DAC channel DMA underrun flag
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: CAL_FLAG - name: CAL_FLAG
description: DAC channel calibration offset status description: DAC channel calibration offset status
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: BWST - name: BWST
description: DAC channel busy writing sample time flag description: DAC channel busy writing sample time flag
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
fieldset/SWTRIGR: fieldset/SWTRIGR:
description: software trigger register description: software trigger register
fields: fields:
- name: SWTRIG - name: SWTRIG
description: DAC channel software trigger description: DAC channel software trigger
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum/TSEL1: enum/TSEL1:
bit_size: 3 bit_size: 3
variants: variants:
- name: TIM6_TRGO - name: TIM6_TRGO
description: Timer 6 TRGO event description: Timer 6 TRGO event
value: 0 value: 0
- name: TIM3_TRGO - name: TIM3_TRGO
description: Timer 3 TRGO event description: Timer 3 TRGO event
value: 1 value: 1
- name: TIM7_TRGO - name: TIM7_TRGO
description: Timer 7 TRGO event description: Timer 7 TRGO event
value: 2 value: 2
- name: TIM15_TRGO - name: TIM15_TRGO
description: Timer 15 TRGO event description: Timer 15 TRGO event
value: 3 value: 3
- name: TIM2_TRGO - name: TIM2_TRGO
description: Timer 2 TRGO event description: Timer 2 TRGO event
value: 4 value: 4
- name: EXTI9 - name: EXTI9
description: EXTI line9 description: EXTI line9
value: 6 value: 6
- name: SOFTWARE - name: SOFTWARE
description: Software trigger description: Software trigger
value: 7 value: 7
enum/TSEL2: enum/TSEL2:
bit_size: 3 bit_size: 3
variants: variants:
- name: TIM6_TRGO - name: TIM6_TRGO
description: Timer 6 TRGO event description: Timer 6 TRGO event
value: 0 value: 0
- name: TIM8_TRGO - name: TIM8_TRGO
description: Timer 8 TRGO event description: Timer 8 TRGO event
value: 1 value: 1
- name: TIM7_TRGO - name: TIM7_TRGO
description: Timer 7 TRGO event description: Timer 7 TRGO event
value: 2 value: 2
- name: TIM5_TRGO - name: TIM5_TRGO
description: Timer 5 TRGO event description: Timer 5 TRGO event
value: 3 value: 3
- name: TIM2_TRGO - name: TIM2_TRGO
description: Timer 2 TRGO event description: Timer 2 TRGO event
value: 4 value: 4
- name: TIM4_TRGO - name: TIM4_TRGO
description: Timer 4 TRGO event description: Timer 4 TRGO event
value: 5 value: 5
- name: EXTI9 - name: EXTI9
description: EXTI line9 description: EXTI line9
value: 6 value: 6
- name: SOFTWARE - name: SOFTWARE
description: Software trigger description: Software trigger
value: 7 value: 7
enum/WAVE: enum/WAVE:
bit_size: 2 bit_size: 2
variants: variants:
- name: Disabled - name: Disabled
description: Wave generation disabled description: Wave generation disabled
value: 0 value: 0
- name: Noise - name: Noise
description: Noise wave generation enabled description: Noise wave generation enabled
value: 1 value: 1
- name: Triangle - name: Triangle
description: Triangle wave generation enabled description: Triangle wave generation enabled
value: 2 value: 2

671
data/registers/dac_v3.yaml
View File

@ -1,394 +1,391 @@
---
block/DAC: block/DAC:
description: Digital-to-analog converter description: Digital-to-analog converter
items: items:
- name: CR - name: CR
description: control register description: control register
byte_offset: 0 byte_offset: 0
fieldset: CR fieldset: CR
- name: SWTRIGR - name: SWTRIGR
description: software trigger register description: software trigger register
byte_offset: 4 byte_offset: 4
access: Write access: Write
fieldset: SWTRIGR fieldset: SWTRIGR
- name: DHR12R - name: DHR12R
description: channel 12-bit right-aligned data holding register description: channel 12-bit right-aligned data holding register
array: array:
len: 2 len: 2
stride: 12 stride: 12
byte_offset: 8 byte_offset: 8
fieldset: DHR12R fieldset: DHR12R
- name: DHR12L - name: DHR12L
description: channel 12-bit left-aligned data holding register description: channel 12-bit left-aligned data holding register
array: array:
len: 2 len: 2
stride: 12 stride: 12
byte_offset: 12 byte_offset: 12
fieldset: DHR12L fieldset: DHR12L
- name: DHR8R - name: DHR8R
description: channel 8-bit right-aligned data holding register description: channel 8-bit right-aligned data holding register
array: array:
len: 2 len: 2
stride: 12 stride: 12
byte_offset: 16 byte_offset: 16
fieldset: DHR8R fieldset: DHR8R
- name: DHR12RD - name: DHR12RD
description: Dual DAC 12-bit right-aligned data holding register description: Dual DAC 12-bit right-aligned data holding register
byte_offset: 32 byte_offset: 32
fieldset: DHR12RD fieldset: DHR12RD
- name: DHR12LD - name: DHR12LD
description: DUAL DAC 12-bit left aligned data holding register description: DUAL DAC 12-bit left aligned data holding register
byte_offset: 36 byte_offset: 36
fieldset: DHR12LD fieldset: DHR12LD
- name: DHR8RD - name: DHR8RD
description: DUAL DAC 8-bit right aligned data holding register description: DUAL DAC 8-bit right aligned data holding register
byte_offset: 40 byte_offset: 40
fieldset: DHR8RD fieldset: DHR8RD
- name: DOR - name: DOR
description: channel data output register description: channel data output register
array: array:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 44 byte_offset: 44
access: Read access: Read
fieldset: DOR fieldset: DOR
- name: SR - name: SR
description: status register description: status register
byte_offset: 52 byte_offset: 52
fieldset: SR fieldset: SR
- name: CCR - name: CCR
description: calibration control register description: calibration control register
byte_offset: 56 byte_offset: 56
fieldset: CCR fieldset: CCR
- name: MCR - name: MCR
description: mode control register description: mode control register
byte_offset: 60 byte_offset: 60
fieldset: MCR fieldset: MCR
- name: SHSR1 - name: SHSR1
description: Sample and Hold sample time register description: Sample and Hold sample time register
array: array:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 64 byte_offset: 64
fieldset: SHSR fieldset: SHSR
- name: SHHR - name: SHHR
description: Sample and Hold hold time register description: Sample and Hold hold time register
byte_offset: 72 byte_offset: 72
fieldset: SHHR fieldset: SHHR
- name: SHRR - name: SHRR
description: Sample and Hold refresh time register description: Sample and Hold refresh time register
byte_offset: 76 byte_offset: 76
fieldset: SHRR fieldset: SHRR
fieldset/CCR: fieldset/CCR:
description: calibration control register description: calibration control register
fields: fields:
- name: OTRIM1 - name: OTRIM1
description: DAC Channel 1 offset trimming value description: DAC Channel 1 offset trimming value
bit_offset: 0 bit_offset: 0
bit_size: 5 bit_size: 5
- name: OTRIM2 - name: OTRIM2
description: DAC Channel 2 offset trimming value description: DAC Channel 2 offset trimming value
bit_offset: 16 bit_offset: 16
bit_size: 5 bit_size: 5
fieldset/CR: fieldset/CR:
description: control register description: control register
fields: fields:
- name: EN - name: EN
description: DAC channel enable description: DAC channel enable
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: TEN - name: TEN
description: DAC channel trigger enable description: DAC channel trigger enable
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: TSEL1 - name: TSEL1
description: DAC channel 1 trigger selection description: DAC channel 1 trigger selection
bit_offset: 2 bit_offset: 2
bit_size: 4 bit_size: 4
enum: TSEL1 enum: TSEL1
- name: WAVE - name: WAVE
description: DAC channel noise/triangle wave generation enable description: DAC channel noise/triangle wave generation enable
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
array: array:
len: 2 len: 2
stride: 16 stride: 16
enum: WAVE enum: WAVE
- name: MAMP - name: MAMP
description: DAC channel mask/amplitude selector description: DAC channel mask/amplitude selector
bit_offset: 8 bit_offset: 8
bit_size: 4 bit_size: 4
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: DMAEN - name: DMAEN
description: DAC channel DMA enable description: DAC channel DMA enable
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: DMAUDRIE - name: DMAUDRIE
description: DAC channel DMA Underrun Interrupt enable description: DAC channel DMA Underrun Interrupt enable
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: CEN - name: CEN
description: DAC channel calibration enable description: DAC channel calibration enable
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: TSEL2 - name: TSEL2
description: DAC channel 2 trigger selection description: DAC channel 2 trigger selection
bit_offset: 18 bit_offset: 18
bit_size: 4 bit_size: 4
enum: TSEL2 enum: TSEL2
fieldset/DHR12L: fieldset/DHR12L:
description: channel 12-bit left-aligned data holding register description: channel 12-bit left-aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 12-bit left-aligned data description: DAC channel 12-bit left-aligned data
bit_offset: 4 bit_offset: 4
bit_size: 12 bit_size: 12
fieldset/DHR12LD: fieldset/DHR12LD:
description: DUAL DAC 12-bit left aligned data holding register description: DUAL DAC 12-bit left aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 12-bit left-aligned data description: DAC channel 12-bit left-aligned data
bit_offset: 4 bit_offset: 4
bit_size: 12 bit_size: 12
array: array:
len: 2 len: 2
stride: 16 stride: 16
fieldset/DHR12R: fieldset/DHR12R:
description: channel 12-bit right-aligned data holding register description: channel 12-bit right-aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 12-bit right-aligned data description: DAC channel 12-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
fieldset/DHR12RD: fieldset/DHR12RD:
description: Dual DAC 12-bit right-aligned data holding register description: Dual DAC 12-bit right-aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 12-bit right-aligned data description: DAC channel 12-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
array: array:
len: 2 len: 2
stride: 16 stride: 16
fieldset/DHR8R: fieldset/DHR8R:
description: channel 8-bit right-aligned data holding register description: channel 8-bit right-aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 8-bit right-aligned data description: DAC channel 8-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
fieldset/DHR8RD: fieldset/DHR8RD:
description: DUAL DAC 8-bit right aligned data holding register description: DUAL DAC 8-bit right aligned data holding register
fields: fields:
- name: DHR - name: DHR
description: DAC channel 8-bit right-aligned data description: DAC channel 8-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
array: array:
len: 2 len: 2
stride: 8 stride: 8
fieldset/DOR: fieldset/DOR:
description: channel data output register description: channel data output register
fields: fields:
- name: DOR - name: DOR
description: DAC channel data output description: DAC channel data output
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
fieldset/MCR: fieldset/MCR:
description: mode control register description: mode control register
fields: fields:
- name: MODE - name: MODE
description: DAC channel mode description: DAC channel mode
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
array: array:
len: 2 len: 2
stride: 16 stride: 16
fieldset/SHHR: fieldset/SHHR:
description: Sample and Hold hold time register description: Sample and Hold hold time register
fields: fields:
- name: THOLD - name: THOLD
description: DAC channel hold Time description: DAC channel hold Time
bit_offset: 0 bit_offset: 0
bit_size: 10 bit_size: 10
array: array:
len: 2 len: 2
stride: 16 stride: 16
fieldset/SHRR: fieldset/SHRR:
description: Sample and Hold refresh time register description: Sample and Hold refresh time register
fields: fields:
- name: TREFRESH - name: TREFRESH
description: DAC channel refresh Time description: DAC channel refresh Time
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
array: array:
len: 2 len: 2
stride: 16 stride: 16
fieldset/SHSR: fieldset/SHSR:
description: Sample and Hold sample time register description: Sample and Hold sample time register
fields: fields:
- name: TSAMPLE - name: TSAMPLE
description: DAC channel sample Time description: DAC channel sample Time
bit_offset: 0 bit_offset: 0
bit_size: 10 bit_size: 10
fieldset/SR: fieldset/SR:
description: status register description: status register
fields: fields:
- name: DMAUDR - name: DMAUDR
description: DAC channel DMA underrun flag description: DAC channel DMA underrun flag
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: CAL_FLAG - name: CAL_FLAG
description: DAC channel calibration offset status description: DAC channel calibration offset status
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: BWST - name: BWST
description: DAC channel busy writing sample time flag description: DAC channel busy writing sample time flag
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
fieldset/SWTRIGR: fieldset/SWTRIGR:
description: software trigger register description: software trigger register
fields: fields:
- name: SWTRIG - name: SWTRIG
description: DAC channel software trigger description: DAC channel software trigger
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum/TSEL1: enum/TSEL1:
bit_size: 4 bit_size: 4
variants: variants:
- name: SOFTWARE - name: SOFTWARE
description: Software trigger description: Software trigger
value: 0 value: 0
- name: TIM1_TRGO - name: TIM1_TRGO
description: Timer 1 TRGO event description: Timer 1 TRGO event
value: 1 value: 1
- name: TIM2_TRGO - name: TIM2_TRGO
description: Timer 2 TRGO event description: Timer 2 TRGO event
value: 2 value: 2
- name: TIM4_TRGO - name: TIM4_TRGO
description: Timer 4 TRGO event description: Timer 4 TRGO event
value: 3 value: 3
- name: TIM5_TRGO - name: TIM5_TRGO
description: Timer 5 TRGO event description: Timer 5 TRGO event
value: 4 value: 4
- name: TIM6_TRGO - name: TIM6_TRGO
description: Timer 6 TRGO event description: Timer 6 TRGO event
value: 5 value: 5
- name: TIM7_TRGO - name: TIM7_TRGO
description: Timer 7 TRGO event description: Timer 7 TRGO event
value: 6 value: 6
- name: TIM8_TRGO - name: TIM8_TRGO
description: Timer 8 TRGO event description: Timer 8 TRGO event
value: 7 value: 7
- name: TIM15_TRGO - name: TIM15_TRGO
description: Timer 15 TRGO event description: Timer 15 TRGO event
value: 8 value: 8
- name: HRTIM1_DACTRG1 - name: HRTIM1_DACTRG1
description: High resolution timer 1 DACTRG1 event description: High resolution timer 1 DACTRG1 event
value: 9 value: 9
- name: HRTIM1_DACTRG2 - name: HRTIM1_DACTRG2
description: High resolution timer 1 DACTRG2 event description: High resolution timer 1 DACTRG2 event
value: 10 value: 10
- name: LPTIM1_OUT - name: LPTIM1_OUT
description: Low-power timer 1 OUT event description: Low-power timer 1 OUT event
value: 11 value: 11
- name: LPTIM2_OUT - name: LPTIM2_OUT
description: Low-power timer 2 OUT event description: Low-power timer 2 OUT event
value: 12 value: 12
- name: EXTI9 - name: EXTI9
description: EXTI line9 description: EXTI line9
value: 13 value: 13
- name: LPTIM3_OUT - name: LPTIM3_OUT
description: Low-power timer 3 OUT event description: Low-power timer 3 OUT event
value: 14 value: 14
enum/TSEL2: enum/TSEL2:
bit_size: 4 bit_size: 4
variants: variants:
- name: SOFTWARE - name: SOFTWARE
description: Software trigger description: Software trigger
value: 0 value: 0
- name: TIM1_TRGO - name: TIM1_TRGO
description: Timer 1 TRGO event description: Timer 1 TRGO event
value: 1 value: 1
- name: TIM2_TRGO - name: TIM2_TRGO
description: Timer 2 TRGO event description: Timer 2 TRGO event
value: 2 value: 2
- name: TIM4_TRGO - name: TIM4_TRGO
description: Timer 4 TRGO event description: Timer 4 TRGO event
value: 3 value: 3
- name: TIM5_TRGO - name: TIM5_TRGO
description: Timer 5 TRGO event description: Timer 5 TRGO event
value: 4 value: 4
- name: TIM6_TRGO - name: TIM6_TRGO
description: Timer 6 TRGO event description: Timer 6 TRGO event
value: 5 value: 5
- name: TIM7_TRGO - name: TIM7_TRGO
description: Timer 7 TRGO event description: Timer 7 TRGO event
value: 6 value: 6
- name: TIM8_TRGO - name: TIM8_TRGO
description: Timer 8 TRGO event description: Timer 8 TRGO event
value: 7 value: 7
- name: TIM15_TRGO - name: TIM15_TRGO
description: Timer 15 TRGO event description: Timer 15 TRGO event
value: 8 value: 8
- name: HRTIM1_DACTRG1 - name: HRTIM1_DACTRG1
description: High resolution timer 1 DACTRG1 event description: High resolution timer 1 DACTRG1 event
value: 9 value: 9
- name: HRTIM1_DACTRG2 - name: HRTIM1_DACTRG2
description: High resolution timer 1 DACTRG2 event description: High resolution timer 1 DACTRG2 event
value: 10 value: 10
- name: LPTIM1_OUT - name: LPTIM1_OUT
description: Low-power timer 1 OUT event description: Low-power timer 1 OUT event
value: 11 value: 11
- name: LPTIM2_OUT - name: LPTIM2_OUT
description: Low-power timer 2 OUT event description: Low-power timer 2 OUT event
value: 12 value: 12
- name: EXTI9 - name: EXTI9
description: EXTI line9 description: EXTI line9
value: 13 value: 13
- name: LPTIM3_OUT - name: LPTIM3_OUT
description: Low-power timer 3 OUT event description: Low-power timer 3 OUT event
value: 14 value: 14
enum/WAVE: enum/WAVE:
bit_size: 2 bit_size: 2
variants: variants:
- name: Disabled - name: Disabled
description: Wave generation disabled description: Wave generation disabled
value: 0 value: 0
- name: Noise - name: Noise
description: Noise wave generation enabled description: Noise wave generation enabled
value: 1 value: 1
- name: Triangle - name: Triangle
description: Triangle wave generation enabled description: Triangle wave generation enabled
value: 2 value: 2

139
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@ -1,85 +1,84 @@
---
block/DBGMCU: block/DBGMCU:
description: Debug support description: Debug support
items: items:
- name: IDCODE - name: IDCODE
description: MCU Device ID Code Register description: MCU Device ID Code Register
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IDCODE fieldset: IDCODE
- name: CR - name: CR
description: Debug MCU Configuration Register description: Debug MCU Configuration Register
byte_offset: 4 byte_offset: 4
fieldset: CR fieldset: CR
- name: APB1FZR - name: APB1FZR
description: DBG APB freeze register 1 description: DBG APB freeze register 1
byte_offset: 8 byte_offset: 8
fieldset: APB1FZR fieldset: APB1FZR
- name: APB2FZR - name: APB2FZR
description: DBG APB freeze register 2 description: DBG APB freeze register 2
byte_offset: 12 byte_offset: 12
fieldset: APB2FZR fieldset: APB2FZR
fieldset/APB1FZR: fieldset/APB1FZR:
description: DBG APB freeze register 1 description: DBG APB freeze register 1
fields: fields:
- name: TIM3 - name: TIM3
description: TIM3 counter stopped when core is halted description: TIM3 counter stopped when core is halted
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: RTC - name: RTC
description: Debug RTC stopped when Core is halted description: Debug RTC stopped when Core is halted
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: WWDG - name: WWDG
description: Debug Window Wachdog stopped when Core is halted description: Debug Window Wachdog stopped when Core is halted
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: IWDG - name: IWDG
description: Debug Independent Wachdog stopped when Core is halted description: Debug Independent Wachdog stopped when Core is halted
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: I2C1 - name: I2C1
description: I2C1 SMBUS timeout mode stopped when core is halted description: I2C1 SMBUS timeout mode stopped when core is halted
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
fieldset/APB2FZR: fieldset/APB2FZR:
description: DBG APB freeze register 2 description: DBG APB freeze register 2
fields: fields:
- name: TIM1 - name: TIM1
description: TIM1 description: TIM1
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: TIM14 - name: TIM14
description: TIM14 description: TIM14
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: TIM16 - name: TIM16
description: TIM16 description: TIM16
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: TIM17 - name: TIM17
description: TIM17 description: TIM17
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Debug MCU Configuration Register description: Debug MCU Configuration Register
fields: fields:
- name: DBG_STOP - name: DBG_STOP
description: Debug Stop Mode description: Debug Stop Mode
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_STANDBY - name: DBG_STANDBY
description: Debug Standby Mode description: Debug Standby Mode
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
fieldset/IDCODE: fieldset/IDCODE:
description: MCU Device ID Code Register description: MCU Device ID Code Register
fields: fields:
- name: DEV_ID - name: DEV_ID
description: Device Identifier description: Device Identifier
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
- name: REV_ID - name: REV_ID
description: Revision Identifier description: Revision Identifier
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16

187
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@ -1,109 +1,108 @@
---
block/DBGMCU: block/DBGMCU:
description: Debug support description: Debug support
items: items:
- name: IDCODE - name: IDCODE
description: MCU Device ID Code Register description: MCU Device ID Code Register
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IDCODE fieldset: IDCODE
- name: CR - name: CR
description: Debug MCU Configuration Register description: Debug MCU Configuration Register
byte_offset: 4 byte_offset: 4
fieldset: CR fieldset: CR
- name: APB1_FZ - name: APB1_FZ
description: Debug MCU APB1 freeze register description: Debug MCU APB1 freeze register
byte_offset: 8 byte_offset: 8
fieldset: APB1_FZ fieldset: APB1_FZ
- name: APB2_FZ - name: APB2_FZ
description: Debug MCU APB2 freeze register description: Debug MCU APB2 freeze register
byte_offset: 12 byte_offset: 12
fieldset: APB2_FZ fieldset: APB2_FZ
fieldset/APB1_FZ: fieldset/APB1_FZ:
description: Debug MCU APB1 freeze register description: Debug MCU APB1 freeze register
fields: fields:
- name: TIM2 - name: TIM2
description: TIM2 counter stopped when core is halted description: TIM2 counter stopped when core is halted
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TIM3 - name: TIM3
description: TIM3 counter stopped when core is halted description: TIM3 counter stopped when core is halted
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: TIM6 - name: TIM6
description: TIM6 counter stopped when core is halted description: TIM6 counter stopped when core is halted
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: TIM7 - name: TIM7
description: TIM7 counter stopped when core is halted description: TIM7 counter stopped when core is halted
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: TIM14 - name: TIM14
description: TIM14 counter stopped when core is halted description: TIM14 counter stopped when core is halted
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: RTC - name: RTC
description: Debug RTC stopped when core is halted description: Debug RTC stopped when core is halted
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: WWDG - name: WWDG
description: Debug window watchdog stopped when core is halted description: Debug window watchdog stopped when core is halted
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: IWDG - name: IWDG
description: Debug independent watchdog stopped when core is halted description: Debug independent watchdog stopped when core is halted
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: DBG_I2C1_SMBUS_TIMEOUT - name: DBG_I2C1_SMBUS_TIMEOUT
description: SMBUS timeout mode stopped when core is halted description: SMBUS timeout mode stopped when core is halted
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: CAN - name: CAN
description: CAN stopped when core is halted description: CAN stopped when core is halted
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
fieldset/APB2_FZ: fieldset/APB2_FZ:
description: Debug MCU APB2 freeze register description: Debug MCU APB2 freeze register
fields: fields:
- name: TIM1 - name: TIM1
description: TIM1 counter stopped when core is halted description: TIM1 counter stopped when core is halted
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: TIM15 - name: TIM15
description: TIM15 counter stopped when core is halted description: TIM15 counter stopped when core is halted
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: TIM16 - name: TIM16
description: TIM16 counter stopped when core is halted description: TIM16 counter stopped when core is halted
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: TIM17 - name: TIM17
description: TIM17 counter stopped when core is halted description: TIM17 counter stopped when core is halted
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Debug MCU Configuration Register description: Debug MCU Configuration Register
fields: fields:
- name: DBG_STOP - name: DBG_STOP
description: Debug Stop Mode description: Debug Stop Mode
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_STANDBY - name: DBG_STANDBY
description: Debug Standby Mode description: Debug Standby Mode
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
fieldset/IDCODE: fieldset/IDCODE:
description: MCU Device ID Code Register description: MCU Device ID Code Register
fields: fields:
- name: DEV_ID - name: DEV_ID
description: Device Identifier description: Device Identifier
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
- name: DIV_ID - name: DIV_ID
description: Division Identifier description: Division Identifier
bit_offset: 12 bit_offset: 12
bit_size: 4 bit_size: 4
- name: REV_ID - name: REV_ID
description: Revision Identifier description: Revision Identifier
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16

235
data/registers/dbgmcu_f1.yaml
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@ -1,127 +1,126 @@
---
block/DBGMCU: block/DBGMCU:
description: Debug support description: Debug support
items: items:
- name: IDCODE - name: IDCODE
description: DBGMCU_IDCODE description: DBGMCU_IDCODE
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IDCODE fieldset: IDCODE
- name: CR - name: CR
description: DBGMCU_CR description: DBGMCU_CR
byte_offset: 4 byte_offset: 4
fieldset: CR fieldset: CR
fieldset/CR: fieldset/CR:
description: DBGMCU_CR description: DBGMCU_CR
fields: fields:
- name: DBG_SLEEP - name: DBG_SLEEP
description: DBG_SLEEP description: DBG_SLEEP
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DBG_STOP - name: DBG_STOP
description: DBG_STOP description: DBG_STOP
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_STANDBY - name: DBG_STANDBY
description: DBG_STANDBY description: DBG_STANDBY
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TRACE_IOEN - name: TRACE_IOEN
description: TRACE_IOEN description: TRACE_IOEN
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: TRACE_MODE - name: TRACE_MODE
description: TRACE_MODE description: TRACE_MODE
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
- name: IWDG - name: IWDG
description: IWDG description: IWDG
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: WWDG - name: WWDG
description: WWDG description: WWDG
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: TIM1 - name: TIM1
description: TIM1 description: TIM1
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: TIM2 - name: TIM2
description: TIM2 description: TIM2
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: TIM3 - name: TIM3
description: TIM3 description: TIM3
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: TIM4 - name: TIM4
description: TIM4 description: TIM4
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: CAN1 - name: CAN1
description: CAN1 description: CAN1
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: DBG_I2C1_SMBUS_TIMEOUT - name: DBG_I2C1_SMBUS_TIMEOUT
description: DBG_I2C1_SMBUS_TIMEOUT description: DBG_I2C1_SMBUS_TIMEOUT
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: DBG_I2C2_SMBUS_TIMEOUT - name: DBG_I2C2_SMBUS_TIMEOUT
description: DBG_I2C2_SMBUS_TIMEOUT description: DBG_I2C2_SMBUS_TIMEOUT
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: TIM8 - name: TIM8
description: TIM8 description: TIM8
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: TIM5 - name: TIM5
description: TIM5 description: TIM5
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
- name: TIM6 - name: TIM6
description: TIM6 description: TIM6
bit_offset: 19 bit_offset: 19
bit_size: 1 bit_size: 1
- name: TIM7 - name: TIM7
description: TIM7 description: TIM7
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
- name: CAN2 - name: CAN2
description: CAN2 description: CAN2
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: TIM15 - name: TIM15
description: TIM15 description: TIM15
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: TIM16 - name: TIM16
description: TIM16 description: TIM16
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: TIM17 - name: TIM17
description: TIM17 description: TIM17
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: TIM12 - name: TIM12
description: TIM12 description: TIM12
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: TIM13 - name: TIM13
description: TIM13 description: TIM13
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
- name: TIM14 - name: TIM14
description: TIM14 description: TIM14
bit_offset: 27 bit_offset: 27
bit_size: 1 bit_size: 1
fieldset/IDCODE: fieldset/IDCODE:
description: DBGMCU_IDCODE description: DBGMCU_IDCODE
fields: fields:
- name: DEV_ID - name: DEV_ID
description: DEV_ID description: DEV_ID
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
- name: REV_ID - name: REV_ID
description: REV_ID description: REV_ID
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16

267
data/registers/dbgmcu_f2.yaml
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@ -1,149 +1,148 @@
---
block/DBGMCU: block/DBGMCU:
description: Debug support description: Debug support
items: items:
- name: IDCODE - name: IDCODE
description: IDCODE description: IDCODE
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IDCODE fieldset: IDCODE
- name: CR - name: CR
description: Control Register description: Control Register
byte_offset: 4 byte_offset: 4
fieldset: CR fieldset: CR
- name: APB1_FZ - name: APB1_FZ
description: Debug MCU APB1 Freeze registe description: Debug MCU APB1 Freeze registe
byte_offset: 8 byte_offset: 8
fieldset: APB1_FZ fieldset: APB1_FZ
- name: APB2_FZ - name: APB2_FZ
description: Debug MCU APB2 Freeze registe description: Debug MCU APB2 Freeze registe
byte_offset: 12 byte_offset: 12
fieldset: APB2_FZ fieldset: APB2_FZ
fieldset/APB1_FZ: fieldset/APB1_FZ:
description: Debug MCU APB1 Freeze registe description: Debug MCU APB1 Freeze registe
fields: fields:
- name: TIM2 - name: TIM2
description: TIM2 description: TIM2
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TIM3 - name: TIM3
description: TIM3 description: TIM3
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: TIM4 - name: TIM4
description: TIM4 description: TIM4
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TIM5 - name: TIM5
description: TIM5 description: TIM5
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: TIM6 - name: TIM6
description: TIM6 description: TIM6
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: TIM7 - name: TIM7
description: TIM7 description: TIM7
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: TIM12 - name: TIM12
description: TIM12 description: TIM12
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: TIM13 - name: TIM13
description: TIM13 description: TIM13
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: TIM14 - name: TIM14
description: TIM14 description: TIM14
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: RTC - name: RTC
description: RTC description: RTC
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: WWDG - name: WWDG
description: WWDG description: WWDG
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: IWDG - name: IWDG
description: IWDEG description: IWDEG
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: I2C1_SMBUS_TIMEOUT - name: I2C1_SMBUS_TIMEOUT
description: I2C1_SMBUS_TIMEOUT description: I2C1_SMBUS_TIMEOUT
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: I2C2_SMBUS_TIMEOUT - name: I2C2_SMBUS_TIMEOUT
description: I2C2_SMBUS_TIMEOUT description: I2C2_SMBUS_TIMEOUT
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: I2C3_SMBUS_TIMEOUT - name: I2C3_SMBUS_TIMEOUT
description: I2C3_SMBUS_TIMEOUT description: I2C3_SMBUS_TIMEOUT
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: CAN1 - name: CAN1
description: CAN1 description: CAN1
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: CAN2 - name: CAN2
description: CAN2 description: CAN2
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
fieldset/APB2_FZ: fieldset/APB2_FZ:
description: Debug MCU APB2 Freeze registe description: Debug MCU APB2 Freeze registe
fields: fields:
- name: TIM1 - name: TIM1
description: TIM1 counter stopped when core is halted description: TIM1 counter stopped when core is halted
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TIM8 - name: TIM8
description: TIM8 counter stopped when core is halted description: TIM8 counter stopped when core is halted
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: TIM9 - name: TIM9
description: TIM9 counter stopped when core is halted description: TIM9 counter stopped when core is halted
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: TIM10 - name: TIM10
description: TIM10 counter stopped when core is halted description: TIM10 counter stopped when core is halted
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: TIM11 - name: TIM11
description: TIM11 counter stopped when core is halted description: TIM11 counter stopped when core is halted
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Control Register description: Control Register
fields: fields:
- name: DBG_SLEEP - name: DBG_SLEEP
description: DBG_SLEEP description: DBG_SLEEP
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DBG_STOP - name: DBG_STOP
description: DBG_STOP description: DBG_STOP
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_STANDBY - name: DBG_STANDBY
description: DBG_STANDBY description: DBG_STANDBY
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TRACE_IOEN - name: TRACE_IOEN
description: TRACE_IOEN description: TRACE_IOEN
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: TRACE_MODE - name: TRACE_MODE
description: TRACE_MODE description: TRACE_MODE
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
fieldset/IDCODE: fieldset/IDCODE:
description: IDCODE description: IDCODE
fields: fields:
- name: DEV_ID - name: DEV_ID
description: DEV_ID description: DEV_ID
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
- name: REV_ID - name: REV_ID
description: REV_ID description: REV_ID
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16

251
data/registers/dbgmcu_f3.yaml
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@ -1,141 +1,140 @@
---
block/DBGMCU: block/DBGMCU:
description: Debug support description: Debug support
items: items:
- name: IDCODE - name: IDCODE
description: MCU Device ID Code Register description: MCU Device ID Code Register
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IDCODE fieldset: IDCODE
- name: CR - name: CR
description: Debug MCU Configuration Register description: Debug MCU Configuration Register
byte_offset: 4 byte_offset: 4
fieldset: CR fieldset: CR
- name: APB1FZR - name: APB1FZR
description: APB Low Freeze Register description: APB Low Freeze Register
byte_offset: 8 byte_offset: 8
fieldset: APB1FZR fieldset: APB1FZR
- name: APB2FZR - name: APB2FZR
description: APB High Freeze Register description: APB High Freeze Register
byte_offset: 12 byte_offset: 12
fieldset: APB2FZR fieldset: APB2FZR
fieldset/APB1FZR: fieldset/APB1FZR:
description: APB Low Freeze Register description: APB Low Freeze Register
fields: fields:
- name: TIM2 - name: TIM2
description: Debug Timer 2 stopped when Core is halted description: Debug Timer 2 stopped when Core is halted
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TIM3 - name: TIM3
description: Debug Timer 3 stopped when Core is halted description: Debug Timer 3 stopped when Core is halted
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: TIM4 - name: TIM4
description: Debug Timer 4 stopped when Core is halted description: Debug Timer 4 stopped when Core is halted
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TIM5 - name: TIM5
description: Debug Timer 5 stopped when Core is halted description: Debug Timer 5 stopped when Core is halted
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: TIM6 - name: TIM6
description: Debug Timer 6 stopped when Core is halted description: Debug Timer 6 stopped when Core is halted
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: TIM7 - name: TIM7
description: Debug Timer 7 stopped when Core is halted description: Debug Timer 7 stopped when Core is halted
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: TIM12 - name: TIM12
description: Debug Timer 12 stopped when Core is halted description: Debug Timer 12 stopped when Core is halted
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: TIM13 - name: TIM13
description: Debug Timer 13 stopped when Core is halted description: Debug Timer 13 stopped when Core is halted
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: TIM14 - name: TIM14
description: Debug Timer 14 stopped when Core is halted description: Debug Timer 14 stopped when Core is halted
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: TIM18 - name: TIM18
description: Debug Timer 18 stopped when Core is halted description: Debug Timer 18 stopped when Core is halted
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: RTC - name: RTC
description: Debug RTC stopped when Core is halted description: Debug RTC stopped when Core is halted
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: WWDG - name: WWDG
description: Debug Window Wachdog stopped when Core is halted description: Debug Window Wachdog stopped when Core is halted
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: IWDG - name: IWDG
description: Debug Independent Wachdog stopped when Core is halted description: Debug Independent Wachdog stopped when Core is halted
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: I2C1_SMBUS_TIMEOUT - name: I2C1_SMBUS_TIMEOUT
description: SMBUS timeout mode stopped when Core is halted description: SMBUS timeout mode stopped when Core is halted
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: I2C2_SMBUS_TIMEOUT - name: I2C2_SMBUS_TIMEOUT
description: SMBUS timeout mode stopped when Core is halted description: SMBUS timeout mode stopped when Core is halted
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: CAN - name: CAN
description: Debug CAN stopped when core is halted description: Debug CAN stopped when core is halted
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
fieldset/APB2FZR: fieldset/APB2FZR:
description: APB High Freeze Register description: APB High Freeze Register
fields: fields:
- name: TIM15 - name: TIM15
description: Debug Timer 15 stopped when Core is halted description: Debug Timer 15 stopped when Core is halted
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TIM16 - name: TIM16
description: Debug Timer 16 stopped when Core is halted description: Debug Timer 16 stopped when Core is halted
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: TIM17 - name: TIM17
description: Debug Timer 17 stopped when Core is halted description: Debug Timer 17 stopped when Core is halted
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: TIM19 - name: TIM19
description: Debug Timer 19 stopped when Core is halted description: Debug Timer 19 stopped when Core is halted
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Debug MCU Configuration Register description: Debug MCU Configuration Register
fields: fields:
- name: DBG_SLEEP - name: DBG_SLEEP
description: Debug Sleep mode description: Debug Sleep mode
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DBG_STOP - name: DBG_STOP
description: Debug Stop Mode description: Debug Stop Mode
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_STANDBY - name: DBG_STANDBY
description: Debug Standby Mode description: Debug Standby Mode
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TRACE_IOEN - name: TRACE_IOEN
description: Trace pin assignment control description: Trace pin assignment control
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: TRACE_MODE - name: TRACE_MODE
description: Trace pin assignment control description: Trace pin assignment control
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
fieldset/IDCODE: fieldset/IDCODE:
description: MCU Device ID Code Register description: MCU Device ID Code Register
fields: fields:
- name: DEV_ID - name: DEV_ID
description: Device Identifier description: Device Identifier
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
- name: REV_ID - name: REV_ID
description: Revision Identifier description: Revision Identifier
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16

275
data/registers/dbgmcu_f4.yaml
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@ -1,153 +1,152 @@
---
block/DBGMCU: block/DBGMCU:
description: Debug support description: Debug support
items: items:
- name: IDCODE - name: IDCODE
description: IDCODE description: IDCODE
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IDCODE fieldset: IDCODE
- name: CR - name: CR
description: Control Register description: Control Register
byte_offset: 4 byte_offset: 4
fieldset: CR fieldset: CR
- name: APB1FZR - name: APB1FZR
description: Debug MCU APB1 Freeze registe description: Debug MCU APB1 Freeze registe
byte_offset: 8 byte_offset: 8
fieldset: APB1FZR fieldset: APB1FZR
- name: APB2FZR - name: APB2FZR
description: Debug MCU APB2 Freeze registe description: Debug MCU APB2 Freeze registe
byte_offset: 12 byte_offset: 12
fieldset: APB2FZR fieldset: APB2FZR
fieldset/APB1FZR: fieldset/APB1FZR:
description: Debug MCU APB1 Freeze registe description: Debug MCU APB1 Freeze registe
fields: fields:
- name: TIM2 - name: TIM2
description: TIM2 description: TIM2
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TIM3 - name: TIM3
description: TIM3 description: TIM3
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: TIM4 - name: TIM4
description: TIM4 description: TIM4
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TIM5 - name: TIM5
description: TIM5 description: TIM5
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: TIM6 - name: TIM6
description: TIM6 description: TIM6
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: TIM7 - name: TIM7
description: TIM7 description: TIM7
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: TIM12 - name: TIM12
description: TIM12 description: TIM12
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: TIM13 - name: TIM13
description: TIM13 description: TIM13
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: TIM14 - name: TIM14
description: TIM14 description: TIM14
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: RTC - name: RTC
description: RTC stopped when Core is halted description: RTC stopped when Core is halted
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: WWDG - name: WWDG
description: WWDG description: WWDG
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: IWDG - name: IWDG
description: IWDEG description: IWDEG
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: I2C1_SMBUS_TIMEOUT - name: I2C1_SMBUS_TIMEOUT
description: I2C1_SMBUS_TIMEOUT description: I2C1_SMBUS_TIMEOUT
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: I2C2_SMBUS_TIMEOUT - name: I2C2_SMBUS_TIMEOUT
description: I2C2_SMBUS_TIMEOUT description: I2C2_SMBUS_TIMEOUT
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: I2C3_SMBUS_TIMEOUT - name: I2C3_SMBUS_TIMEOUT
description: I2C3SMBUS_TIMEOUT description: I2C3SMBUS_TIMEOUT
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: I2CFMP_SMBUS_TIMEOUT - name: I2CFMP_SMBUS_TIMEOUT
description: SMBUS timeout mode stopped when Core is halted description: SMBUS timeout mode stopped when Core is halted
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: CAN1 - name: CAN1
description: CAN1 description: CAN1
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: CAN2 - name: CAN2
description: CAN2 description: CAN2
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
fieldset/APB2FZR: fieldset/APB2FZR:
description: Debug MCU APB2 Freeze registe description: Debug MCU APB2 Freeze registe
fields: fields:
- name: TIM1 - name: TIM1
description: TIM1 counter stopped when core is halted description: TIM1 counter stopped when core is halted
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TIM8 - name: TIM8
description: TIM8 counter stopped when core is halted description: TIM8 counter stopped when core is halted
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: TIM9 - name: TIM9
description: TIM9 counter stopped when core is halted description: TIM9 counter stopped when core is halted
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: TIM10 - name: TIM10
description: TIM10 counter stopped when core is halted description: TIM10 counter stopped when core is halted
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: TIM11 - name: TIM11
description: TIM11 counter stopped when core is halted description: TIM11 counter stopped when core is halted
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Control Register description: Control Register
fields: fields:
- name: DBG_SLEEP - name: DBG_SLEEP
description: DBG_SLEEP description: DBG_SLEEP
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DBG_STOP - name: DBG_STOP
description: DBG_STOP description: DBG_STOP
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_STANDBY - name: DBG_STANDBY
description: DBG_STANDBY description: DBG_STANDBY
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TRACE_IOEN - name: TRACE_IOEN
description: TRACE_IOEN description: TRACE_IOEN
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: TRACE_MODE - name: TRACE_MODE
description: TRACE_MODE description: TRACE_MODE
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
fieldset/IDCODE: fieldset/IDCODE:
description: IDCODE description: IDCODE
fields: fields:
- name: DEV_ID - name: DEV_ID
description: DEV_ID description: DEV_ID
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
- name: REV_ID - name: REV_ID
description: REV_ID description: REV_ID
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16

291
data/registers/dbgmcu_f7.yaml
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@ -1,161 +1,160 @@
---
block/DBGMCU: block/DBGMCU:
description: Debug support description: Debug support
items: items:
- name: IDCODE - name: IDCODE
description: IDCODE description: IDCODE
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IDCODE fieldset: IDCODE
- name: CR - name: CR
description: Control Register description: Control Register
byte_offset: 4 byte_offset: 4
fieldset: CR fieldset: CR
- name: APB1FZR - name: APB1FZR
description: Debug MCU APB1 Freeze register description: Debug MCU APB1 Freeze register
byte_offset: 8 byte_offset: 8
fieldset: APB1FZR fieldset: APB1FZR
- name: APB2FZR - name: APB2FZR
description: Debug MCU APB2 Freeze register description: Debug MCU APB2 Freeze register
byte_offset: 12 byte_offset: 12
fieldset: APB2FZR fieldset: APB2FZR
fieldset/APB1FZR: fieldset/APB1FZR:
description: Debug MCU APB1 Freeze register description: Debug MCU APB1 Freeze register
fields: fields:
- name: TIM2 - name: TIM2
description: TIM2 description: TIM2
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TIM3 - name: TIM3
description: TIM3 description: TIM3
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: TIM4 - name: TIM4
description: TIM4 description: TIM4
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TIM5 - name: TIM5
description: TIM5 description: TIM5
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: TIM6 - name: TIM6
description: TIM6 description: TIM6
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: TIM7 - name: TIM7
description: TIM7 description: TIM7
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: TIM12 - name: TIM12
description: TIM12 description: TIM12
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: TIM13 - name: TIM13
description: TIM13 description: TIM13
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: TIM14 - name: TIM14
description: TIM14 description: TIM14
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: LPTIM1 - name: LPTIM1
description: LPTIM1 description: LPTIM1
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: RTC - name: RTC
description: RTC description: RTC
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: WWDG - name: WWDG
description: WWDG description: WWDG
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: IWDG - name: IWDG
description: IWDG description: IWDG
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: CAN3 - name: CAN3
description: CAN3 description: CAN3
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: DBG_I2C1_SMBUS_TIMEOUT - name: DBG_I2C1_SMBUS_TIMEOUT
description: DBG_I2C1_SMBUS_TIMEOUT description: DBG_I2C1_SMBUS_TIMEOUT
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: DBG_I2C2_SMBUS_TIMEOUT - name: DBG_I2C2_SMBUS_TIMEOUT
description: DBG_I2C2_SMBUS_TIMEOUT description: DBG_I2C2_SMBUS_TIMEOUT
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: DBG_I2C3_SMBUS_TIMEOUT - name: DBG_I2C3_SMBUS_TIMEOUT
description: DBG_I2C3_SMBUS_TIMEOUT description: DBG_I2C3_SMBUS_TIMEOUT
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: DBG_I2C4_SMBUS_TIMEOUT - name: DBG_I2C4_SMBUS_TIMEOUT
description: DBG_I2C4SMBUS_TIMEOUT description: DBG_I2C4SMBUS_TIMEOUT
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: CAN1 - name: CAN1
description: CAN1 description: CAN1
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: CAN2 - name: CAN2
description: CAN2 description: CAN2
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
fieldset/APB2FZR: fieldset/APB2FZR:
description: Debug MCU APB2 Freeze register description: Debug MCU APB2 Freeze register
fields: fields:
- name: TIM1 - name: TIM1
description: TIM1 counter stopped when core is halted description: TIM1 counter stopped when core is halted
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TIM8 - name: TIM8
description: TIM8 counter stopped when core is halted description: TIM8 counter stopped when core is halted
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: TIM9 - name: TIM9
description: TIM9 counter stopped when core is halted description: TIM9 counter stopped when core is halted
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: TIM10 - name: TIM10
description: TIM10 counter stopped when core is halted description: TIM10 counter stopped when core is halted
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: TIM11 - name: TIM11
description: TIM11 counter stopped when core is halted description: TIM11 counter stopped when core is halted
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Control Register description: Control Register
fields: fields:
- name: DBG_SLEEP - name: DBG_SLEEP
description: DBG_SLEEP description: DBG_SLEEP
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DBG_STOP - name: DBG_STOP
description: DBG_STOP description: DBG_STOP
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_STANDBY - name: DBG_STANDBY
description: DBG_STANDBY description: DBG_STANDBY
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TRACE_IOEN - name: TRACE_IOEN
description: TRACE_IOEN description: TRACE_IOEN
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: TRACE_MODE - name: TRACE_MODE
description: TRACE_MODE description: TRACE_MODE
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
fieldset/IDCODE: fieldset/IDCODE:
description: IDCODE description: IDCODE
fields: fields:
- name: DEV_ID - name: DEV_ID
description: DEV_ID description: DEV_ID
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
- name: REV_ID - name: REV_ID
description: REV_ID description: REV_ID
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16

187
data/registers/dbgmcu_g0.yaml
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@ -1,109 +1,108 @@
---
block/DBGMCU: block/DBGMCU:
description: Debug support description: Debug support
items: items:
- name: IDCODE - name: IDCODE
description: MCU Device ID Code Register description: MCU Device ID Code Register
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IDCODE fieldset: IDCODE
- name: CR - name: CR
description: Debug MCU Configuration Register description: Debug MCU Configuration Register
byte_offset: 4 byte_offset: 4
fieldset: CR fieldset: CR
- name: APB1FZR - name: APB1FZR
description: DBG APB freeze register 1 description: DBG APB freeze register 1
byte_offset: 8 byte_offset: 8
fieldset: APB1FZR fieldset: APB1FZR
- name: APB2FZR - name: APB2FZR
description: DBG APB freeze register 2 description: DBG APB freeze register 2
byte_offset: 12 byte_offset: 12
fieldset: APB2FZR fieldset: APB2FZR
fieldset/APB1FZR: fieldset/APB1FZR:
description: DBG APB freeze register 1 description: DBG APB freeze register 1
fields: fields:
- name: TIM2 - name: TIM2
description: Debug Timer 2 stopped when Core is halted description: Debug Timer 2 stopped when Core is halted
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TIM3 - name: TIM3
description: TIM3 counter stopped when core is halted description: TIM3 counter stopped when core is halted
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: TIM6 - name: TIM6
description: Debug Timer 6 stopped when Core is halted description: Debug Timer 6 stopped when Core is halted
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: TIM7 - name: TIM7
description: TIM7 counter stopped when core is halted description: TIM7 counter stopped when core is halted
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: RTC - name: RTC
description: Debug RTC stopped when Core is halted description: Debug RTC stopped when Core is halted
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: WWDG - name: WWDG
description: Debug Window Wachdog stopped when Core is halted description: Debug Window Wachdog stopped when Core is halted
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: IWDG - name: IWDG
description: Debug Independent Wachdog stopped when Core is halted description: Debug Independent Wachdog stopped when Core is halted
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: I2C1 - name: I2C1
description: I2C1 SMBUS timeout mode stopped when core is halted description: I2C1 SMBUS timeout mode stopped when core is halted
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: LPTIM2 - name: LPTIM2
description: Clocking of LPTIMER2 counter when the core is halted description: Clocking of LPTIMER2 counter when the core is halted
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
- name: LPTIM1 - name: LPTIM1
description: Clocking of LPTIMER1 counter when the core is halted description: Clocking of LPTIMER1 counter when the core is halted
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/APB2FZR: fieldset/APB2FZR:
description: DBG APB freeze register 2 description: DBG APB freeze register 2
fields: fields:
- name: TIM1 - name: TIM1
description: TIM1 description: TIM1
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: TIM14 - name: TIM14
description: TIM14 description: TIM14
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: TIM15 - name: TIM15
description: TIM15 description: TIM15
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: TIM16 - name: TIM16
description: TIM16 description: TIM16
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: TIM17 - name: TIM17
description: TIM17 description: TIM17
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Debug MCU Configuration Register description: Debug MCU Configuration Register
fields: fields:
- name: DBG_STOP - name: DBG_STOP
description: Debug Stop Mode description: Debug Stop Mode
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_STANDBY - name: DBG_STANDBY
description: Debug Standby Mode description: Debug Standby Mode
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
fieldset/IDCODE: fieldset/IDCODE:
description: MCU Device ID Code Register description: MCU Device ID Code Register
fields: fields:
- name: DEV_ID - name: DEV_ID
description: Device Identifier description: Device Identifier
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
- name: REV_ID - name: REV_ID
description: Revision Identifier description: Revision Identifier
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16

291
data/registers/dbgmcu_g4.yaml
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@ -1,164 +1,163 @@
---
block/DBGMCU: block/DBGMCU:
description: Debug support description: Debug support
items: items:
- name: IDCODE - name: IDCODE
description: MCU Device ID Code Register description: MCU Device ID Code Register
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IDCODE fieldset: IDCODE
- name: CR - name: CR
description: Debug MCU Configuration Register description: Debug MCU Configuration Register
byte_offset: 4 byte_offset: 4
fieldset: CR fieldset: CR
- name: APB1LFZR - name: APB1LFZR
description: APB Low Freeze Register 1 description: APB Low Freeze Register 1
byte_offset: 8 byte_offset: 8
fieldset: APB1LFZR fieldset: APB1LFZR
- name: APB1HFZR - name: APB1HFZR
description: APB Low Freeze Register 2 description: APB Low Freeze Register 2
byte_offset: 12 byte_offset: 12
fieldset: APB1HFZR fieldset: APB1HFZR
- name: APB2FZR - name: APB2FZR
description: APB High Freeze Register description: APB High Freeze Register
byte_offset: 16 byte_offset: 16
fieldset: APB2FZR fieldset: APB2FZR
fieldset/APB1HFZR: fieldset/APB1HFZR:
description: APB Low Freeze Register 2 description: APB Low Freeze Register 2
fields: fields:
- name: I2C4 - name: I2C4
description: I2C4 description: I2C4
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
fieldset/APB1LFZR: fieldset/APB1LFZR:
description: APB Low Freeze Register 1 description: APB Low Freeze Register 1
fields: fields:
- name: TIM2 - name: TIM2
description: Debug Timer 2 stopped when Core is halted description: Debug Timer 2 stopped when Core is halted
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TIM3 - name: TIM3
description: TIM3 counter stopped when core is halted description: TIM3 counter stopped when core is halted
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: TIM4 - name: TIM4
description: TIM4 counter stopped when core is halted description: TIM4 counter stopped when core is halted
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TIM5 - name: TIM5
description: TIM5 counter stopped when core is halted description: TIM5 counter stopped when core is halted
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: TIM6 - name: TIM6
description: Debug Timer 6 stopped when Core is halted description: Debug Timer 6 stopped when Core is halted
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: TIM7 - name: TIM7
description: TIM7 counter stopped when core is halted description: TIM7 counter stopped when core is halted
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: RTC - name: RTC
description: Debug RTC stopped when Core is halted description: Debug RTC stopped when Core is halted
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: WWDG - name: WWDG
description: Debug Window Wachdog stopped when Core is halted description: Debug Window Wachdog stopped when Core is halted
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: IWDG - name: IWDG
description: Debug Independent Wachdog stopped when Core is halted description: Debug Independent Wachdog stopped when Core is halted
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: I2C1 - name: I2C1
description: I2C1 SMBUS timeout mode stopped when core is halted description: I2C1 SMBUS timeout mode stopped when core is halted
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: I2C2 - name: I2C2
description: I2C2 SMBUS timeout mode stopped when core is halted description: I2C2 SMBUS timeout mode stopped when core is halted
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: I2C3 - name: I2C3
description: I2C3 SMBUS timeout mode stopped when core is halted description: I2C3 SMBUS timeout mode stopped when core is halted
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
- name: LPTIMER - name: LPTIMER
description: LPTIM1 counter stopped when core is halted description: LPTIM1 counter stopped when core is halted
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/APB2FZR: fieldset/APB2FZR:
description: APB High Freeze Register description: APB High Freeze Register
fields: fields:
- name: TIM1 - name: TIM1
description: TIM1 counter stopped when core is halted description: TIM1 counter stopped when core is halted
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: TIM8 - name: TIM8
description: TIM8 counter stopped when core is halted description: TIM8 counter stopped when core is halted
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: TIM15 - name: TIM15
description: TIM15 counter stopped when core is halted description: TIM15 counter stopped when core is halted
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: TIM16 - name: TIM16
description: TIM16 counter stopped when core is halted description: TIM16 counter stopped when core is halted
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: TIM17 - name: TIM17
description: TIM17 counter stopped when core is halted description: TIM17 counter stopped when core is halted
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
- name: TIM20 - name: TIM20
description: TIM20counter stopped when core is halted description: TIM20counter stopped when core is halted
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
- name: HRTIM0 - name: HRTIM0
description: HRTIM0 description: HRTIM0
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
- name: HRTIM1 - name: HRTIM1
description: HRTIM0 description: HRTIM0
bit_offset: 27 bit_offset: 27
bit_size: 1 bit_size: 1
- name: HRTIM2 - name: HRTIM2
description: HRTIM0 description: HRTIM0
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
- name: HRTIM3 - name: HRTIM3
description: HRTIM0 description: HRTIM0
bit_offset: 29 bit_offset: 29
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Debug MCU Configuration Register description: Debug MCU Configuration Register
fields: fields:
- name: DBG_SLEEP - name: DBG_SLEEP
description: Debug Sleep Mode description: Debug Sleep Mode
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DBG_STOP - name: DBG_STOP
description: Debug Stop Mode description: Debug Stop Mode
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_STANDBY - name: DBG_STANDBY
description: Debug Standby Mode description: Debug Standby Mode
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TRACE_IOEN - name: TRACE_IOEN
description: Trace pin assignment control description: Trace pin assignment control
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: TRACE_MODE - name: TRACE_MODE
description: Trace pin assignment control description: Trace pin assignment control
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
fieldset/IDCODE: fieldset/IDCODE:
description: MCU Device ID Code Register description: MCU Device ID Code Register
fields: fields:
- name: DEV_ID - name: DEV_ID
description: Device Identifier description: Device Identifier
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
- name: REV_ID - name: REV_ID
description: Revision Identifier description: Revision Identifier
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16

339
data/registers/dbgmcu_h7.yaml
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@ -1,191 +1,190 @@
---
block/DBGMCU: block/DBGMCU:
description: Debug support description: Debug support
items: items:
- name: IDC - name: IDC
description: Identity code description: Identity code
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IDC fieldset: IDC
- name: CR - name: CR
description: Configuration register description: Configuration register
byte_offset: 4 byte_offset: 4
fieldset: CR fieldset: CR
- name: APB3FZR1 - name: APB3FZR1
description: APB3 peripheral freeze register description: APB3 peripheral freeze register
byte_offset: 52 byte_offset: 52
fieldset: APB3FZR1 fieldset: APB3FZR1
- name: APB1LFZR1 - name: APB1LFZR1
description: APB1L peripheral freeze register description: APB1L peripheral freeze register
byte_offset: 60 byte_offset: 60
fieldset: APB1LFZR1 fieldset: APB1LFZR1
- name: APB2FZR1 - name: APB2FZR1
description: APB2 peripheral freeze register description: APB2 peripheral freeze register
byte_offset: 76 byte_offset: 76
fieldset: APB2FZR1 fieldset: APB2FZR1
- name: APB4FZR1 - name: APB4FZR1
description: APB4 peripheral freeze register description: APB4 peripheral freeze register
byte_offset: 84 byte_offset: 84
fieldset: APB4FZR1 fieldset: APB4FZR1
fieldset/APB1LFZR1: fieldset/APB1LFZR1:
description: APB1L peripheral freeze register description: APB1L peripheral freeze register
fields: fields:
- name: TIM2 - name: TIM2
description: TIM2 stop in debug mode description: TIM2 stop in debug mode
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TIM3 - name: TIM3
description: TIM3 stop in debug mode description: TIM3 stop in debug mode
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: TIM4 - name: TIM4
description: TIM4 stop in debug mode description: TIM4 stop in debug mode
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TIM5 - name: TIM5
description: TIM5 stop in debug mode description: TIM5 stop in debug mode
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: TIM6 - name: TIM6
description: TIM6 stop in debug mode description: TIM6 stop in debug mode
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: TIM7 - name: TIM7
description: TIM7 stop in debug mode description: TIM7 stop in debug mode
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: TIM12 - name: TIM12
description: TIM12 stop in debug mode description: TIM12 stop in debug mode
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: TIM13 - name: TIM13
description: TIM13 stop in debug mode description: TIM13 stop in debug mode
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: TIM14 - name: TIM14
description: TIM14 stop in debug mode description: TIM14 stop in debug mode
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: LPTIM1 - name: LPTIM1
description: LPTIM1 stop in debug mode description: LPTIM1 stop in debug mode
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: I2C1 - name: I2C1
description: I2C1 SMBUS timeout stop in debug mode description: I2C1 SMBUS timeout stop in debug mode
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: I2C2 - name: I2C2
description: I2C2 SMBUS timeout stop in debug mode description: I2C2 SMBUS timeout stop in debug mode
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: I2C3 - name: I2C3
description: I2C3 SMBUS timeout stop in debug mode description: I2C3 SMBUS timeout stop in debug mode
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
fieldset/APB2FZR1: fieldset/APB2FZR1:
description: APB2 peripheral freeze register description: APB2 peripheral freeze register
fields: fields:
- name: TIM1 - name: TIM1
description: TIM1 stop in debug mode description: TIM1 stop in debug mode
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TIM8 - name: TIM8
description: TIM8 stop in debug mode description: TIM8 stop in debug mode
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: TIM15 - name: TIM15
description: TIM15 stop in debug mode description: TIM15 stop in debug mode
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: TIM16 - name: TIM16
description: TIM16 stop in debug mode description: TIM16 stop in debug mode
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: TIM17 - name: TIM17
description: TIM17 stop in debug mode description: TIM17 stop in debug mode
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
- name: HRTIM - name: HRTIM
description: HRTIM stop in debug mode description: HRTIM stop in debug mode
bit_offset: 29 bit_offset: 29
bit_size: 1 bit_size: 1
fieldset/APB3FZR1: fieldset/APB3FZR1:
description: APB3 peripheral freeze register description: APB3 peripheral freeze register
fields: fields:
- name: WWDG1 - name: WWDG1
description: WWDG1 stop in debug mode description: WWDG1 stop in debug mode
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
fieldset/APB4FZR1: fieldset/APB4FZR1:
description: APB4 peripheral freeze register description: APB4 peripheral freeze register
fields: fields:
- name: I2C4 - name: I2C4
description: I2C4 SMBUS timeout stop in debug mode description: I2C4 SMBUS timeout stop in debug mode
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: LPTIM2 - name: LPTIM2
description: LPTIM2 stop in debug mode description: LPTIM2 stop in debug mode
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: LPTIM3 - name: LPTIM3
description: LPTIM3 stop in debug mode description: LPTIM3 stop in debug mode
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: LPTIM4 - name: LPTIM4
description: LPTIM4 stop in debug mode description: LPTIM4 stop in debug mode
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: LPTIM5 - name: LPTIM5
description: LPTIM5 stop in debug mode description: LPTIM5 stop in debug mode
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: RTC - name: RTC
description: RTC stop in debug mode description: RTC stop in debug mode
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: IWDG1 - name: IWDG1
description: Independent watchdog for D1 stop in debug mode description: Independent watchdog for D1 stop in debug mode
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Configuration register description: Configuration register
fields: fields:
- name: DBGSLEEP_D1 - name: DBGSLEEP_D1
description: Allow debug in D1 Sleep mode description: Allow debug in D1 Sleep mode
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DBGSTOP_D1 - name: DBGSTOP_D1
description: Allow debug in D1 Stop mode description: Allow debug in D1 Stop mode
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBGSTBY_D1 - name: DBGSTBY_D1
description: Allow debug in D1 Standby mode description: Allow debug in D1 Standby mode
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TRACECLKEN - name: TRACECLKEN
description: Trace clock enable enable description: Trace clock enable enable
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
- name: D1DBGCKEN - name: D1DBGCKEN
description: D1 debug clock enable enable description: D1 debug clock enable enable
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: D3DBGCKEN - name: D3DBGCKEN
description: D3 debug clock enable enable description: D3 debug clock enable enable
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: TRGOEN - name: TRGOEN
description: External trigger output enable description: External trigger output enable
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
fieldset/IDC: fieldset/IDC:
description: Identity code description: Identity code
fields: fields:
- name: DEV_ID - name: DEV_ID
description: Device ID description: Device ID
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
- name: REV_ID - name: REV_ID
description: Revision ID description: Revision ID
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16

155
data/registers/dbgmcu_l0.yaml
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@ -1,93 +1,92 @@
---
block/DBGMCU: block/DBGMCU:
description: Debug support description: Debug support
items: items:
- name: IDCODE - name: IDCODE
description: MCU Device ID Code Register description: MCU Device ID Code Register
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IDCODE fieldset: IDCODE
- name: CR - name: CR
description: Debug MCU Configuration Register description: Debug MCU Configuration Register
byte_offset: 4 byte_offset: 4
fieldset: CR fieldset: CR
- name: APB1FZR - name: APB1FZR
description: APB Low Freeze Register description: APB Low Freeze Register
byte_offset: 8 byte_offset: 8
fieldset: APB1FZR fieldset: APB1FZR
- name: APB2FZR - name: APB2FZR
description: APB High Freeze Register description: APB High Freeze Register
byte_offset: 12 byte_offset: 12
fieldset: APB2FZR fieldset: APB2FZR
fieldset/APB1FZR: fieldset/APB1FZR:
description: APB Low Freeze Register description: APB Low Freeze Register
fields: fields:
- name: TIM2 - name: TIM2
description: Debug Timer 2 stopped when Core is halted description: Debug Timer 2 stopped when Core is halted
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TIM6 - name: TIM6
description: Debug Timer 6 stopped when Core is halted description: Debug Timer 6 stopped when Core is halted
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: RTC - name: RTC
description: Debug RTC stopped when Core is halted description: Debug RTC stopped when Core is halted
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: WWDG - name: WWDG
description: Debug Window Wachdog stopped when Core is halted description: Debug Window Wachdog stopped when Core is halted
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: IWDG - name: IWDG
description: Debug Independent Wachdog stopped when Core is halted description: Debug Independent Wachdog stopped when Core is halted
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: I2C1 - name: I2C1
description: I2C1 SMBUS timeout mode stopped when core is halted description: I2C1 SMBUS timeout mode stopped when core is halted
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: I2C2 - name: I2C2
description: I2C2 SMBUS timeout mode stopped when core is halted description: I2C2 SMBUS timeout mode stopped when core is halted
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: LPTIM - name: LPTIM
description: LPTIM1 counter stopped when core is halted description: LPTIM1 counter stopped when core is halted
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/APB2FZR: fieldset/APB2FZR:
description: APB High Freeze Register description: APB High Freeze Register
fields: fields:
- name: TIM21 - name: TIM21
description: Debug Timer 21 stopped when Core is halted description: Debug Timer 21 stopped when Core is halted
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TIM22 - name: TIM22
description: Debug Timer 22 stopped when Core is halted description: Debug Timer 22 stopped when Core is halted
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Debug MCU Configuration Register description: Debug MCU Configuration Register
fields: fields:
- name: DBG_SLEEP - name: DBG_SLEEP
description: Debug Sleep Mode description: Debug Sleep Mode
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DBG_STOP - name: DBG_STOP
description: Debug Stop Mode description: Debug Stop Mode
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_STANDBY - name: DBG_STANDBY
description: Debug Standby Mode description: Debug Standby Mode
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
fieldset/IDCODE: fieldset/IDCODE:
description: MCU Device ID Code Register description: MCU Device ID Code Register
fields: fields:
- name: DEV_ID - name: DEV_ID
description: Device Identifier description: Device Identifier
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
- name: REV_ID - name: REV_ID
description: Revision Identifier description: Revision Identifier
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16

203
data/registers/dbgmcu_l1.yaml
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@ -1,117 +1,116 @@
---
block/DBGMCU: block/DBGMCU:
description: debug support description: debug support
items: items:
- name: IDCODE - name: IDCODE
description: DBGMCU_IDCODE description: DBGMCU_IDCODE
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IDCODE fieldset: IDCODE
- name: CR - name: CR
description: Debug MCU configuration register description: Debug MCU configuration register
byte_offset: 4 byte_offset: 4
fieldset: CR fieldset: CR
- name: APB1_FZ - name: APB1_FZ
description: Debug MCU APB1 freeze register1 description: Debug MCU APB1 freeze register1
byte_offset: 8 byte_offset: 8
fieldset: APB1_FZ fieldset: APB1_FZ
- name: APB2_FZ - name: APB2_FZ
description: Debug MCU APB1 freeze register 2 description: Debug MCU APB1 freeze register 2
byte_offset: 12 byte_offset: 12
fieldset: APB2_FZ fieldset: APB2_FZ
fieldset/APB1_FZ: fieldset/APB1_FZ:
description: Debug MCU APB1 freeze register1 description: Debug MCU APB1 freeze register1
fields: fields:
- name: DBG_TIM2_STOP - name: DBG_TIM2_STOP
description: TIM2 counter stopped when core is halted description: TIM2 counter stopped when core is halted
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DBG_TIM3_STOP - name: DBG_TIM3_STOP
description: TIM3 counter stopped when core is halted description: TIM3 counter stopped when core is halted
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_TIM4_STOP - name: DBG_TIM4_STOP
description: TIM4 counter stopped when core is halted description: TIM4 counter stopped when core is halted
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: DBG_TIM5_STOP - name: DBG_TIM5_STOP
description: TIM5 counter stopped when core is halted description: TIM5 counter stopped when core is halted
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: DBG_TIM6_STOP - name: DBG_TIM6_STOP
description: TIM6 counter stopped when core is halted description: TIM6 counter stopped when core is halted
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: DBG_TIM7_STOP - name: DBG_TIM7_STOP
description: TIM7 counter stopped when core is halted description: TIM7 counter stopped when core is halted
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: DBG_RTC_STOP - name: DBG_RTC_STOP
description: Debug RTC stopped when core is halted description: Debug RTC stopped when core is halted
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: DBG_WWDG_STOP - name: DBG_WWDG_STOP
description: Debug window watchdog stopped when core is halted description: Debug window watchdog stopped when core is halted
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: DBG_IWDG_STOP - name: DBG_IWDG_STOP
description: Debug independent watchdog stopped when core is halted description: Debug independent watchdog stopped when core is halted
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: DBG_I2C1_SMBUS_TIMEOUT - name: DBG_I2C1_SMBUS_TIMEOUT
description: SMBUS timeout mode stopped when core is halted description: SMBUS timeout mode stopped when core is halted
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: DBG_I2C2_SMBUS_TIMEOUT - name: DBG_I2C2_SMBUS_TIMEOUT
description: SMBUS timeout mode stopped when core is halted description: SMBUS timeout mode stopped when core is halted
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
fieldset/APB2_FZ: fieldset/APB2_FZ:
description: Debug MCU APB1 freeze register 2 description: Debug MCU APB1 freeze register 2
fields: fields:
- name: DBG_TIM9_STOP - name: DBG_TIM9_STOP
description: TIM counter stopped when core is halted description: TIM counter stopped when core is halted
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: DBG_TIM10_STOP - name: DBG_TIM10_STOP
description: TIM counter stopped when core is halted description: TIM counter stopped when core is halted
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: DBG_TIM11_STOP - name: DBG_TIM11_STOP
description: TIM counter stopped when core is halted description: TIM counter stopped when core is halted
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Debug MCU configuration register description: Debug MCU configuration register
fields: fields:
- name: DBG_SLEEP - name: DBG_SLEEP
description: Debug Sleep mode description: Debug Sleep mode
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DBG_STOP - name: DBG_STOP
description: Debug Stop mode description: Debug Stop mode
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_STANDBY - name: DBG_STANDBY
description: Debug Standby mode description: Debug Standby mode
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TRACE_IOEN - name: TRACE_IOEN
description: Trace pin assignment control description: Trace pin assignment control
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: TRACE_MODE - name: TRACE_MODE
description: Trace pin assignment control description: Trace pin assignment control
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
fieldset/IDCODE: fieldset/IDCODE:
description: DBGMCU_IDCODE description: DBGMCU_IDCODE
fields: fields:
- name: DEV_ID - name: DEV_ID
description: Device identifier description: Device identifier
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
- name: REV_ID - name: REV_ID
description: Revision identifie description: Revision identifie
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16

259
data/registers/dbgmcu_l4.yaml
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@ -1,148 +1,147 @@
---
block/DBGMCU: block/DBGMCU:
description: MCU debug component description: MCU debug component
items: items:
- name: IDCODE - name: IDCODE
description: DBGMCU_IDCODE description: DBGMCU_IDCODE
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IDCODE fieldset: IDCODE
- name: CR - name: CR
description: Debug MCU configuration register description: Debug MCU configuration register
byte_offset: 4 byte_offset: 4
fieldset: CR fieldset: CR
- name: APB1FZR1 - name: APB1FZR1
description: Debug MCU APB1 freeze register1 description: Debug MCU APB1 freeze register1
byte_offset: 8 byte_offset: 8
fieldset: APB1FZR1 fieldset: APB1FZR1
- name: APB1FZR2 - name: APB1FZR2
description: Debug MCU APB1 freeze register 2 description: Debug MCU APB1 freeze register 2
byte_offset: 12 byte_offset: 12
fieldset: APB1FZR2 fieldset: APB1FZR2
- name: APB2FZR - name: APB2FZR
description: Debug MCU APB2 freeze register description: Debug MCU APB2 freeze register
byte_offset: 16 byte_offset: 16
fieldset: APB2FZR fieldset: APB2FZR
fieldset/APB1FZR1: fieldset/APB1FZR1:
description: Debug MCU APB1 freeze register1 description: Debug MCU APB1 freeze register1
fields: fields:
- name: TIM2 - name: TIM2
description: TIM2 counter stopped when core is halted description: TIM2 counter stopped when core is halted
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TIM3 - name: TIM3
description: TIM3 counter stopped when core is halted description: TIM3 counter stopped when core is halted
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: TIM4 - name: TIM4
description: TIM4 counter stopped when core is halted description: TIM4 counter stopped when core is halted
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TIM5 - name: TIM5
description: TIM5 counter stopped when core is halted description: TIM5 counter stopped when core is halted
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: TIM6 - name: TIM6
description: TIM6 counter stopped when core is halted description: TIM6 counter stopped when core is halted
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: TIM7 - name: TIM7
description: TIM7 counter stopped when core is halted description: TIM7 counter stopped when core is halted
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: RTC - name: RTC
description: RTC counter stopped when core is halted description: RTC counter stopped when core is halted
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: WWDG - name: WWDG
description: Window watchdog counter stopped when core is halted description: Window watchdog counter stopped when core is halted
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: IWDG - name: IWDG
description: Independent watchdog counter stopped when core is halted description: Independent watchdog counter stopped when core is halted
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: I2C1 - name: I2C1
description: I2C1 SMBUS timeout counter stopped when core is halted description: I2C1 SMBUS timeout counter stopped when core is halted
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: I2C2 - name: I2C2
description: I2C2 SMBUS timeout counter stopped when core is halted description: I2C2 SMBUS timeout counter stopped when core is halted
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: I2C3 - name: I2C3
description: I2C3 SMBUS timeout counter stopped when core is halted description: I2C3 SMBUS timeout counter stopped when core is halted
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: CAN - name: CAN
description: bxCAN stopped when core is halted description: bxCAN stopped when core is halted
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: LPTIM1 - name: LPTIM1
description: LPTIM1 counter stopped when core is halted description: LPTIM1 counter stopped when core is halted
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/APB1FZR2: fieldset/APB1FZR2:
description: Debug MCU APB1 freeze register 2 description: Debug MCU APB1 freeze register 2
fields: fields:
- name: LPTIM2 - name: LPTIM2
description: LPTIM2 counter stopped when core is halted description: LPTIM2 counter stopped when core is halted
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
fieldset/APB2FZR: fieldset/APB2FZR:
description: Debug MCU APB2 freeze register description: Debug MCU APB2 freeze register
fields: fields:
- name: TIM1 - name: TIM1
description: TIM1 counter stopped when core is halted description: TIM1 counter stopped when core is halted
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: TIM8 - name: TIM8
description: TIM8 counter stopped when core is halted description: TIM8 counter stopped when core is halted
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: TIM15 - name: TIM15
description: TIM15 counter stopped when core is halted description: TIM15 counter stopped when core is halted
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: TIM16 - name: TIM16
description: TIM16 counter stopped when core is halted description: TIM16 counter stopped when core is halted
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: TIM17 - name: TIM17
description: TIM17 counter stopped when core is halted description: TIM17 counter stopped when core is halted
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Debug MCU configuration register description: Debug MCU configuration register
fields: fields:
- name: DBG_SLEEP - name: DBG_SLEEP
description: Debug Sleep mode description: Debug Sleep mode
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DBG_STOP - name: DBG_STOP
description: Debug Stop mode description: Debug Stop mode
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_STANDBY - name: DBG_STANDBY
description: Debug Standby mode description: Debug Standby mode
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TRACE_IOEN - name: TRACE_IOEN
description: Trace pin assignment control description: Trace pin assignment control
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: TRACE_MODE - name: TRACE_MODE
description: Trace pin assignment control description: Trace pin assignment control
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
fieldset/IDCODE: fieldset/IDCODE:
description: DBGMCU_IDCODE description: DBGMCU_IDCODE
fields: fields:
- name: DEV_ID - name: DEV_ID
description: Device identifier description: Device identifier
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
- name: REV_ID - name: REV_ID
description: Revision identifie description: Revision identifie
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16

731
data/registers/dbgmcu_u5.yaml
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@ -1,429 +1,428 @@
---
block/DBGMCU: block/DBGMCU:
description: MCU debug component description: MCU debug component
items: items:
- name: IDCODE - name: IDCODE
description: DBGMCU_IDCODE description: DBGMCU_IDCODE
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IDCODE fieldset: IDCODE
- name: CR - name: CR
description: "Debug MCU configuration\r register" description: "Debug MCU configuration\r register"
byte_offset: 4 byte_offset: 4
fieldset: CR fieldset: CR
- name: APB1LFZR - name: APB1LFZR
description: "Debug MCU APB1L peripheral freeze\r register" description: "Debug MCU APB1L peripheral freeze\r register"
byte_offset: 8 byte_offset: 8
fieldset: APB1LFZR fieldset: APB1LFZR
- name: APB1HFZR - name: APB1HFZR
description: Debug MCU APB1H peripheral freeze register description: Debug MCU APB1H peripheral freeze register
byte_offset: 12 byte_offset: 12
fieldset: APB1HFZR fieldset: APB1HFZR
- name: APB2FZR - name: APB2FZR
description: Debug MCU APB2 peripheral freeze register description: Debug MCU APB2 peripheral freeze register
byte_offset: 16 byte_offset: 16
fieldset: APB2FZR fieldset: APB2FZR
- name: APB3FZR - name: APB3FZR
description: Debug MCU APB3 peripheral freeze register description: Debug MCU APB3 peripheral freeze register
byte_offset: 20 byte_offset: 20
fieldset: APB3FZR fieldset: APB3FZR
- name: AHB1FZR - name: AHB1FZR
description: Debug MCU AHB1 peripheral freeze register description: Debug MCU AHB1 peripheral freeze register
byte_offset: 32 byte_offset: 32
fieldset: AHB1FZR fieldset: AHB1FZR
- name: AHB3FZR - name: AHB3FZR
description: Debug MCU AHB3 peripheral freeze register description: Debug MCU AHB3 peripheral freeze register
byte_offset: 40 byte_offset: 40
fieldset: AHB3FZR fieldset: AHB3FZR
- name: DBGMCU_SR - name: DBGMCU_SR
description: DBGMCU status register description: DBGMCU status register
byte_offset: 252 byte_offset: 252
access: Read access: Read
fieldset: DBGMCU_SR fieldset: DBGMCU_SR
- name: DBGMCU_DBG_AUTH_HOST - name: DBGMCU_DBG_AUTH_HOST
description: DBGMCU debug host authentication register description: DBGMCU debug host authentication register
byte_offset: 256 byte_offset: 256
access: Read access: Read
fieldset: DBGMCU_DBG_AUTH_HOST fieldset: DBGMCU_DBG_AUTH_HOST
- name: DBGMCU_DBG_AUTH_DEVICE - name: DBGMCU_DBG_AUTH_DEVICE
description: DBGMCU debug device authentication register description: DBGMCU debug device authentication register
byte_offset: 260 byte_offset: 260
access: Read access: Read
fieldset: DBGMCU_DBG_AUTH_DEVICE fieldset: DBGMCU_DBG_AUTH_DEVICE
- name: PIDR4 - name: PIDR4
description: Debug MCU CoreSight peripheral identity register 4 description: Debug MCU CoreSight peripheral identity register 4
byte_offset: 4048 byte_offset: 4048
access: Read access: Read
fieldset: PIDR4 fieldset: PIDR4
- name: PIDR0 - name: PIDR0
description: Debug MCU CoreSight peripheral identity register 0 description: Debug MCU CoreSight peripheral identity register 0
byte_offset: 4064 byte_offset: 4064
access: Read access: Read
fieldset: PIDR0 fieldset: PIDR0
- name: PIDR1 - name: PIDR1
description: Debug MCU CoreSight peripheral identity register 1 description: Debug MCU CoreSight peripheral identity register 1
byte_offset: 4068 byte_offset: 4068
access: Read access: Read
fieldset: PIDR1 fieldset: PIDR1
- name: PIDR2 - name: PIDR2
description: Debug MCU CoreSight peripheral identity register 2 description: Debug MCU CoreSight peripheral identity register 2
byte_offset: 4072 byte_offset: 4072
access: Read access: Read
fieldset: PIDR2 fieldset: PIDR2
- name: PIDR3 - name: PIDR3
description: Debug MCU CoreSight peripheral identity register 3 description: Debug MCU CoreSight peripheral identity register 3
byte_offset: 4076 byte_offset: 4076
access: Read access: Read
fieldset: PIDR3 fieldset: PIDR3
- name: CIDR0 - name: CIDR0
description: Debug MCU CoreSight component identity register 0 description: Debug MCU CoreSight component identity register 0
byte_offset: 4080 byte_offset: 4080
access: Read access: Read
fieldset: CIDR0 fieldset: CIDR0
- name: CIDR1 - name: CIDR1
description: Debug MCU CoreSight component identity register 1 description: Debug MCU CoreSight component identity register 1
byte_offset: 4084 byte_offset: 4084
access: Read access: Read
fieldset: CIDR1 fieldset: CIDR1
- name: CIDR2 - name: CIDR2
description: Debug MCU CoreSight component identity register 2 description: Debug MCU CoreSight component identity register 2
byte_offset: 4088 byte_offset: 4088
access: Read access: Read
fieldset: CIDR2 fieldset: CIDR2
- name: CIDR3 - name: CIDR3
description: Debug MCU CoreSight component identity register 3 description: Debug MCU CoreSight component identity register 3
byte_offset: 4092 byte_offset: 4092
access: Read access: Read
fieldset: CIDR3 fieldset: CIDR3
fieldset/AHB1FZR: fieldset/AHB1FZR:
description: Debug MCU AHB1 peripheral freeze register description: Debug MCU AHB1 peripheral freeze register
fields: fields:
- name: DBG_GPDMA0_STOP - name: DBG_GPDMA0_STOP
description: GPDMA channel 0 stop in debug description: GPDMA channel 0 stop in debug
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DBG_GPDMA1_STOP - name: DBG_GPDMA1_STOP
description: GPDMA channel 1 stop in debug description: GPDMA channel 1 stop in debug
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_GPDMA2_STOP - name: DBG_GPDMA2_STOP
description: GPDMA channel 2 stop in debug description: GPDMA channel 2 stop in debug
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: DBG_GPDMA3_STOP - name: DBG_GPDMA3_STOP
description: GPDMA channel 3 stop in debug description: GPDMA channel 3 stop in debug
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: DBG_GPDMA4_STOP - name: DBG_GPDMA4_STOP
description: GPDMA channel 4 stop in debug description: GPDMA channel 4 stop in debug
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: DBG_GPDMA5_STOP - name: DBG_GPDMA5_STOP
description: GPDMA channel 5 stop in debug description: GPDMA channel 5 stop in debug
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: DBG_GPDMA6_STOP - name: DBG_GPDMA6_STOP
description: GPDMA channel 6 stop in debug description: GPDMA channel 6 stop in debug
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: DBG_GPDMA7_STOP - name: DBG_GPDMA7_STOP
description: GPDMA channel 7 stop in debug description: GPDMA channel 7 stop in debug
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: DBG_GPDMA8_STOP - name: DBG_GPDMA8_STOP
description: GPDMA channel 8 stop in debug description: GPDMA channel 8 stop in debug
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: DBG_GPDMA9_STOP - name: DBG_GPDMA9_STOP
description: GPDMA channel 9 stop in debug description: GPDMA channel 9 stop in debug
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: DBG_GPDMA10_STOP - name: DBG_GPDMA10_STOP
description: GPDMA channel 10 stop in debug description: GPDMA channel 10 stop in debug
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: DBG_GPDMA11_STOP - name: DBG_GPDMA11_STOP
description: GPDMA channel 11 stop in debug description: GPDMA channel 11 stop in debug
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: DBG_GPDMA12_STOP - name: DBG_GPDMA12_STOP
description: GPDMA channel 12 stop in debug description: GPDMA channel 12 stop in debug
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: DBG_GPDMA13_STOP - name: DBG_GPDMA13_STOP
description: GPDMA channel 13 stop in debug description: GPDMA channel 13 stop in debug
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: DBG_GPDMA14_STOP - name: DBG_GPDMA14_STOP
description: GPDMA channel 14 stop in debug description: GPDMA channel 14 stop in debug
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: DBG_GPDMA15_STOP - name: DBG_GPDMA15_STOP
description: GPDMA channel 15 stop in debug description: GPDMA channel 15 stop in debug
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
fieldset/AHB3FZR: fieldset/AHB3FZR:
description: Debug MCU AHB3 peripheral freeze register description: Debug MCU AHB3 peripheral freeze register
fields: fields:
- name: DBG_LPDMA0_STOP - name: DBG_LPDMA0_STOP
description: LPDMA channel 0 stop in debug description: LPDMA channel 0 stop in debug
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DBG_LPDMA1_STOP - name: DBG_LPDMA1_STOP
description: LPDMA channel 1 stop in debug description: LPDMA channel 1 stop in debug
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_LPDMA2_STOP - name: DBG_LPDMA2_STOP
description: LPDMA channel 2 stop in debug description: LPDMA channel 2 stop in debug
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: DBG_LPDMA3_STOP - name: DBG_LPDMA3_STOP
description: LPDMA channel 3 stop in debug description: LPDMA channel 3 stop in debug
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
fieldset/APB1HFZR: fieldset/APB1HFZR:
description: Debug MCU APB1H peripheral freeze register description: Debug MCU APB1H peripheral freeze register
fields: fields:
- name: DBG_I2C4_STOP - name: DBG_I2C4_STOP
description: I2C4 stop in debug description: I2C4 stop in debug
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_LPTIM2_STOP - name: DBG_LPTIM2_STOP
description: LPTIM2 stop in debug description: LPTIM2 stop in debug
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
fieldset/APB1LFZR: fieldset/APB1LFZR:
description: "Debug MCU APB1L peripheral freeze\r register" description: "Debug MCU APB1L peripheral freeze\r register"
fields: fields:
- name: DBG_TIM2_STOP - name: DBG_TIM2_STOP
description: TIM2 stop in debug description: TIM2 stop in debug
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DBG_TIM3_STOP - name: DBG_TIM3_STOP
description: TIM3 stop in debug description: TIM3 stop in debug
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_TIM4_STOP - name: DBG_TIM4_STOP
description: TIM4 stop in debug description: TIM4 stop in debug
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: DBG_TIM5_STOP - name: DBG_TIM5_STOP
description: TIM5 stop in debug description: TIM5 stop in debug
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: DBG_TIM6_STOP - name: DBG_TIM6_STOP
description: TIM6 stop in debug description: TIM6 stop in debug
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: DBG_TIM7_STOP - name: DBG_TIM7_STOP
description: TIM7 stop in debug description: TIM7 stop in debug
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: DBG_WWDG_STOP - name: DBG_WWDG_STOP
description: Window watchdog counter stop in debug description: Window watchdog counter stop in debug
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: DBG_IWDG_STOP - name: DBG_IWDG_STOP
description: Independent watchdog counter stop in debug description: Independent watchdog counter stop in debug
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: DBG_I2C1_STOP - name: DBG_I2C1_STOP
description: I2C1 SMBUS timeout stop in debug description: I2C1 SMBUS timeout stop in debug
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: DBG_I2C2_STOP - name: DBG_I2C2_STOP
description: I2C2 SMBUS timeout stop in debug description: I2C2 SMBUS timeout stop in debug
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
fieldset/APB2FZR: fieldset/APB2FZR:
description: Debug MCU APB2 peripheral freeze register description: Debug MCU APB2 peripheral freeze register
fields: fields:
- name: DBG_TIM1_STOP - name: DBG_TIM1_STOP
description: "TIM1 counter stopped when core is\r halted" description: "TIM1 counter stopped when core is\r halted"
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: DBG_TIM8_STOP - name: DBG_TIM8_STOP
description: TIM8 stop in debug description: TIM8 stop in debug
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: DBG_TIM15_STOP - name: DBG_TIM15_STOP
description: "TIM15 counter stopped when core is\r halted" description: "TIM15 counter stopped when core is\r halted"
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: DBG_TIM16_STOP - name: DBG_TIM16_STOP
description: "TIM16 counter stopped when core is\r halted" description: "TIM16 counter stopped when core is\r halted"
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: DBG_TIM17_STOP - name: DBG_TIM17_STOP
description: DBG_TIM17_STOP description: DBG_TIM17_STOP
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/APB3FZR: fieldset/APB3FZR:
description: Debug MCU APB3 peripheral freeze register description: Debug MCU APB3 peripheral freeze register
fields: fields:
- name: DBG_I2C3_STOP - name: DBG_I2C3_STOP
description: I2C3 stop in debug description: I2C3 stop in debug
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: DBG_LPTIM1_STOP - name: DBG_LPTIM1_STOP
description: LPTIM1 stop in debug description: LPTIM1 stop in debug
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: DBG_LPTIM3_STOP - name: DBG_LPTIM3_STOP
description: LPTIM3 stop in debug description: LPTIM3 stop in debug
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
- name: DBG_LPTIM4_STOP - name: DBG_LPTIM4_STOP
description: LPTIM4 stop in debug description: LPTIM4 stop in debug
bit_offset: 19 bit_offset: 19
bit_size: 1 bit_size: 1
- name: DBG_RTC_STOP - name: DBG_RTC_STOP
description: RTC stop in debug description: RTC stop in debug
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
fieldset/CIDR0: fieldset/CIDR0:
description: Debug MCU CoreSight component identity register 0 description: Debug MCU CoreSight component identity register 0
fields: fields:
- name: PREAMBLE - name: PREAMBLE
description: "component identification bits [7:0]" description: component identification bits [7:0]
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
fieldset/CIDR1: fieldset/CIDR1:
description: Debug MCU CoreSight component identity register 1 description: Debug MCU CoreSight component identity register 1
fields: fields:
- name: PREAMBLE - name: PREAMBLE
description: "component identification bits [11:8]" description: component identification bits [11:8]
bit_offset: 0 bit_offset: 0
bit_size: 4 bit_size: 4
- name: CLASS - name: CLASS
description: "component identification bits [15:12] - component class" description: component identification bits [15:12] - component class
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
fieldset/CIDR2: fieldset/CIDR2:
description: Debug MCU CoreSight component identity register 2 description: Debug MCU CoreSight component identity register 2
fields: fields:
- name: PREAMBLE - name: PREAMBLE
description: "component identification bits [23:16]" description: component identification bits [23:16]
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
fieldset/CIDR3: fieldset/CIDR3:
description: Debug MCU CoreSight component identity register 3 description: Debug MCU CoreSight component identity register 3
fields: fields:
- name: PREAMBLE - name: PREAMBLE
description: "component identification bits [31:24]" description: component identification bits [31:24]
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
fieldset/CR: fieldset/CR:
description: "Debug MCU configuration\r register" description: "Debug MCU configuration\r register"
fields: fields:
- name: DBG_STOP - name: DBG_STOP
description: Debug Stop mode description: Debug Stop mode
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_STANDBY - name: DBG_STANDBY
description: Debug Standby mode description: Debug Standby mode
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TRACE_IOEN - name: TRACE_IOEN
description: "Trace pin assignment\r control" description: "Trace pin assignment\r control"
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: TRACE_EN - name: TRACE_EN
description: "trace port and clock\r enable" description: "trace port and clock\r enable"
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: TRACE_MODE - name: TRACE_MODE
description: "Trace pin assignment\r control" description: "Trace pin assignment\r control"
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
fieldset/DBGMCU_DBG_AUTH_DEVICE: fieldset/DBGMCU_DBG_AUTH_DEVICE:
description: DBGMCU debug device authentication register description: DBGMCU debug device authentication register
fields: fields:
- name: AUTH_ID - name: AUTH_ID
description: "Device specific ID\r \tDevice specific ID used for RDP regression." description: "Device specific ID\r \tDevice specific ID used for RDP regression."
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/DBGMCU_DBG_AUTH_HOST: fieldset/DBGMCU_DBG_AUTH_HOST:
description: DBGMCU debug host authentication register description: DBGMCU debug host authentication register
fields: fields:
- name: AUTH_KEY - name: AUTH_KEY
description: "Device authentication key\r \tThe device specific 64-bit authentication key (OEM key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory." description: "Device authentication key\r \tThe device specific 64-bit authentication key (OEM key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory."
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/DBGMCU_SR: fieldset/DBGMCU_SR:
description: DBGMCU status register description: DBGMCU status register
fields: fields:
- name: AP_PRESENT - name: AP_PRESENT
description: "Bit n identifies whether access port AP n is present in device\r \tBit n = 0: APn absent\r \tBit n = 1: APn present" description: "Bit n identifies whether access port AP n is present in device\r \tBit n = 0: APn absent\r \tBit n = 1: APn present"
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: AP_LOCKED - name: AP_LOCKED
description: "DECLARATION TO BE CONFIRMED by PRODUCT OWNER! Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked)\r \tBit n = 0: APn locked\r \tBit n = 1: APn enabled" description: "DECLARATION TO BE CONFIRMED by PRODUCT OWNER! Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked)\r \tBit n = 0: APn locked\r \tBit n = 1: APn enabled"
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
fieldset/IDCODE: fieldset/IDCODE:
description: DBGMCU_IDCODE description: DBGMCU_IDCODE
fields: fields:
- name: DEV_ID - name: DEV_ID
description: Device dentification description: Device dentification
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
- name: REV_ID - name: REV_ID
description: Revision description: Revision
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16
fieldset/PIDR0: fieldset/PIDR0:
description: Debug MCU CoreSight peripheral identity register 0 description: Debug MCU CoreSight peripheral identity register 0
fields: fields:
- name: PARTNUM - name: PARTNUM
description: "part number bits [7:0]" description: part number bits [7:0]
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
fieldset/PIDR1: fieldset/PIDR1:
description: Debug MCU CoreSight peripheral identity register 1 description: Debug MCU CoreSight peripheral identity register 1
fields: fields:
- name: PARTNUM - name: PARTNUM
description: "part number bits [11:8]" description: part number bits [11:8]
bit_offset: 0 bit_offset: 0
bit_size: 4 bit_size: 4
- name: JEP106ID - name: JEP106ID
description: "JEP106 identity code bits [3:0]" description: JEP106 identity code bits [3:0]
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
fieldset/PIDR2: fieldset/PIDR2:
description: Debug MCU CoreSight peripheral identity register 2 description: Debug MCU CoreSight peripheral identity register 2
fields: fields:
- name: JEP106ID - name: JEP106ID
description: "JEP106 identity code bits [6:4]" description: JEP106 identity code bits [6:4]
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
- name: JEDEC - name: JEDEC
description: JEDEC assigned value description: JEDEC assigned value
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: REVISION - name: REVISION
description: component revision number description: component revision number
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
fieldset/PIDR3: fieldset/PIDR3:
description: Debug MCU CoreSight peripheral identity register 3 description: Debug MCU CoreSight peripheral identity register 3
fields: fields:
- name: CMOD - name: CMOD
description: customer modified description: customer modified
bit_offset: 0 bit_offset: 0
bit_size: 4 bit_size: 4
- name: REVAND - name: REVAND
description: metal fix version description: metal fix version
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
fieldset/PIDR4: fieldset/PIDR4:
description: Debug MCU CoreSight peripheral identity register 4 description: Debug MCU CoreSight peripheral identity register 4
fields: fields:
- name: JEP106CON - name: JEP106CON
description: JEP106 continuation code description: JEP106 continuation code
bit_offset: 0 bit_offset: 0
bit_size: 4 bit_size: 4
- name: KCOUNT_4 - name: KCOUNT_4
description: register file size description: register file size
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4

291
data/registers/dbgmcu_wb.yaml
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@ -1,173 +1,172 @@
---
block/DBGMCU: block/DBGMCU:
description: Debug support description: Debug support
items: items:
- name: IDCODE - name: IDCODE
description: MCU Device ID Code Register description: MCU Device ID Code Register
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IDCODE fieldset: IDCODE
- name: CR - name: CR
description: Debug MCU Configuration Register description: Debug MCU Configuration Register
byte_offset: 4 byte_offset: 4
fieldset: CR fieldset: CR
- name: APB1FZR1 - name: APB1FZR1
description: APB1 Low Freeze Register CPU1 description: APB1 Low Freeze Register CPU1
byte_offset: 60 byte_offset: 60
fieldset: APB1FZR1 fieldset: APB1FZR1
- name: C2AP_B1FZR1 - name: C2AP_B1FZR1
description: APB1 Low Freeze Register CPU2 description: APB1 Low Freeze Register CPU2
byte_offset: 64 byte_offset: 64
fieldset: C2AP_B1FZR1 fieldset: C2AP_B1FZR1
- name: APB1FZR2 - name: APB1FZR2
description: APB1 High Freeze Register CPU1 description: APB1 High Freeze Register CPU1
byte_offset: 68 byte_offset: 68
fieldset: APB1FZR2 fieldset: APB1FZR2
- name: C2APB1FZR2 - name: C2APB1FZR2
description: APB1 High Freeze Register CPU2 description: APB1 High Freeze Register CPU2
byte_offset: 72 byte_offset: 72
fieldset: C2APB1FZR2 fieldset: C2APB1FZR2
- name: C2APB2FZR - name: C2APB2FZR
description: APB2 Freeze Register CPU2 description: APB2 Freeze Register CPU2
byte_offset: 72 byte_offset: 72
fieldset: C2APB2FZR fieldset: C2APB2FZR
- name: APB2FZR - name: APB2FZR
description: APB2 Freeze Register CPU1 description: APB2 Freeze Register CPU1
byte_offset: 76 byte_offset: 76
fieldset: APB2FZR fieldset: APB2FZR
fieldset/APB1FZR1: fieldset/APB1FZR1:
description: APB1 Low Freeze Register CPU1 description: APB1 Low Freeze Register CPU1
fields: fields:
- name: TIM2 - name: TIM2
description: Debug Timer 2 stopped when Core is halted description: Debug Timer 2 stopped when Core is halted
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: RTC - name: RTC
description: RTC counter stopped when core is halted description: RTC counter stopped when core is halted
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: WWDG - name: WWDG
description: WWDG counter stopped when core is halted description: WWDG counter stopped when core is halted
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: IWDG - name: IWDG
description: IWDG counter stopped when core is halted description: IWDG counter stopped when core is halted
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: I2C1 - name: I2C1
description: Debug I2C1 SMBUS timeout stopped when Core is halted description: Debug I2C1 SMBUS timeout stopped when Core is halted
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: I2C3 - name: I2C3
description: Debug I2C3 SMBUS timeout stopped when core is halted description: Debug I2C3 SMBUS timeout stopped when core is halted
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: LPTIM1 - name: LPTIM1
description: Debug LPTIM1 stopped when Core is halted description: Debug LPTIM1 stopped when Core is halted
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/APB1FZR2: fieldset/APB1FZR2:
description: APB1 High Freeze Register CPU1 description: APB1 High Freeze Register CPU1
fields: fields:
- name: LPTIM2 - name: LPTIM2
description: LPTIM2 counter stopped when core is halted description: LPTIM2 counter stopped when core is halted
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
fieldset/APB2FZR: fieldset/APB2FZR:
description: APB2 Freeze Register CPU1 description: APB2 Freeze Register CPU1
fields: fields:
- name: TIM1 - name: TIM1
description: TIM1 counter stopped when core is halted description: TIM1 counter stopped when core is halted
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: TIM16 - name: TIM16
description: TIM16 counter stopped when core is halted description: TIM16 counter stopped when core is halted
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: TIM17 - name: TIM17
description: TIM17 counter stopped when core is halted description: TIM17 counter stopped when core is halted
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/C2APB1FZR2: fieldset/C2APB1FZR2:
description: APB1 High Freeze Register CPU2 description: APB1 High Freeze Register CPU2
fields: fields:
- name: LPTIM2 - name: LPTIM2
description: LPTIM2 counter stopped when core is halted description: LPTIM2 counter stopped when core is halted
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
fieldset/C2APB2FZR: fieldset/C2APB2FZR:
description: APB2 Freeze Register CPU2 description: APB2 Freeze Register CPU2
fields: fields:
- name: TIM1 - name: TIM1
description: TIM1 counter stopped when core is halted description: TIM1 counter stopped when core is halted
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: TIM16 - name: TIM16
description: TIM16 counter stopped when core is halted description: TIM16 counter stopped when core is halted
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: TIM17 - name: TIM17
description: TIM17 counter stopped when core is halted description: TIM17 counter stopped when core is halted
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/C2AP_B1FZR1: fieldset/C2AP_B1FZR1:
description: APB1 Low Freeze Register CPU2 description: APB1 Low Freeze Register CPU2
fields: fields:
- name: LPTIM2 - name: LPTIM2
description: LPTIM2 counter stopped when core is halted description: LPTIM2 counter stopped when core is halted
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: RTC - name: RTC
description: RTC counter stopped when core is halted description: RTC counter stopped when core is halted
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: IWDG - name: IWDG
description: IWDG stopped when core is halted description: IWDG stopped when core is halted
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: I2C1 - name: I2C1
description: I2C1 SMBUS timeout stopped when core is halted description: I2C1 SMBUS timeout stopped when core is halted
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: I2C3 - name: I2C3
description: I2C3 SMBUS timeout stopped when core is halted description: I2C3 SMBUS timeout stopped when core is halted
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: LPTIM1 - name: LPTIM1
description: LPTIM1 counter stopped when core is halted description: LPTIM1 counter stopped when core is halted
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Debug MCU Configuration Register description: Debug MCU Configuration Register
fields: fields:
- name: DBG_SLEEP - name: DBG_SLEEP
description: Debug Sleep Mode description: Debug Sleep Mode
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DBG_STOP - name: DBG_STOP
description: Debug Stop Mode description: Debug Stop Mode
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_STANDBY - name: DBG_STANDBY
description: Debug Standby Mode description: Debug Standby Mode
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TRACE_IOEN - name: TRACE_IOEN
description: Trace port and clock enable description: Trace port and clock enable
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: TRGOEN - name: TRGOEN
description: External trigger output enable description: External trigger output enable
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
fieldset/IDCODE: fieldset/IDCODE:
description: MCU Device ID Code Register description: MCU Device ID Code Register
fields: fields:
- name: DEV_ID - name: DEV_ID
description: Device Identifier description: Device Identifier
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
- name: REV_ID - name: REV_ID
description: Revision Identifier description: Revision Identifier
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16

339
data/registers/dbgmcu_wba.yaml Normal file
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@ -0,0 +1,339 @@
block/DBGMCU:
description: Microcontroller debug unit
items:
- name: IDCODE
description: identity code register
byte_offset: 0
fieldset: IDCODE
- name: CR
description: status and configuration register
byte_offset: 4
fieldset: CR
- name: APB1LFZR
description: APB1L peripheral freeze register
byte_offset: 8
fieldset: APB1LFZR
- name: APB1HFZR
description: APB1H peripheral freeze register
byte_offset: 12
fieldset: APB1HFZR
- name: APB2FZR
description: APB2 peripheral freeze register
byte_offset: 16
fieldset: APB2FZR
- name: APB7FZR
description: APB7 peripheral freeze register
byte_offset: 36
fieldset: APB7FZR
- name: AHB1FZR
description: AHB1 peripheral freeze register
byte_offset: 40
fieldset: AHB1FZR
- name: SR
description: status register
byte_offset: 252
fieldset: SR
- name: DBG_AUTH_HOST
description: debug host authentication register
byte_offset: 256
fieldset: DBG_AUTH_HOST
- name: DBG_AUTH_DEVICE
description: debug device authentication register
byte_offset: 260
fieldset: DBG_AUTH_DEVICE
- name: PNCR
description: part number codification register
byte_offset: 2012
fieldset: PNCR
- name: PIDR4
description: CoreSight peripheral identity register 4
byte_offset: 4048
fieldset: PIDR4
- name: PIDR0
description: CoreSight peripheral identity register 0
byte_offset: 4064
fieldset: PIDR0
- name: PIDR1
description: CoreSight peripheral identity register 1
byte_offset: 4068
fieldset: PIDR1
- name: PIDR2
description: CoreSight peripheral identity register 2
byte_offset: 4072
fieldset: PIDR2
- name: PIDR3
description: CoreSight peripheral identity register 3
byte_offset: 4076
fieldset: PIDR3
- name: CIDR0
description: CoreSight component identity register 0
byte_offset: 4080
fieldset: CIDR0
- name: CIDR1
description: CoreSight peripheral identity register 1
byte_offset: 4084
fieldset: CIDR1
- name: CIDR2
description: CoreSight component identity register 2
byte_offset: 4088
fieldset: CIDR2
- name: CIDR3
description: CoreSight component identity register 3
byte_offset: 4092
fieldset: CIDR3
fieldset/AHB1FZR:
description: AHB1 peripheral freeze register
fields:
- name: DBG_GPDMA1_CH0_STOP
description: "GPDMA 1 channel 0 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC0."
bit_offset: 0
bit_size: 1
- name: DBG_GPDMA1_CH1_STOP
description: "GPDMA 1 channel 1 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC1."
bit_offset: 1
bit_size: 1
- name: DBG_GPDMA1_CH2_STOP
description: "GPDMA 1 channel 2 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC2."
bit_offset: 2
bit_size: 1
- name: DBG_GPDMA1_CH3_STOP
description: "GPDMA 1 channel 3 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC3."
bit_offset: 3
bit_size: 1
- name: DBG_GPDMA1_CH4_STOP
description: "GPDMA 1 channel 4 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC4."
bit_offset: 4
bit_size: 1
- name: DBG_GPDMA1_CH5_STOP
description: "GPDMA 1 channel 5 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC5."
bit_offset: 5
bit_size: 1
- name: DBG_GPDMA1_CH6_STOP
description: "GPDMA 1 channel 6 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC6."
bit_offset: 6
bit_size: 1
- name: DBG_GPDMA1_CH7_STOP
description: "GPDMA 1 channel 7 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC7."
bit_offset: 7
bit_size: 1
fieldset/APB1HFZR:
description: APB1H peripheral freeze register
fields:
- name: DBG_LPTIM2_STOP
description: "LPTIM2 stop in CPU debug\r Write access can be protected by GTZC_TZSC.LPTIM2SEC."
bit_offset: 5
bit_size: 1
fieldset/APB1LFZR:
description: APB1L peripheral freeze register
fields:
- name: DBG_TIM2_STOP
description: "TIM2 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM2SEC."
bit_offset: 0
bit_size: 1
- name: DBG_TIM3_STOP
description: "TIM3 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM3SEC."
bit_offset: 1
bit_size: 1
- name: DBG_WWDG_STOP
description: "WWDG stop in CPU debug\r Write access can be protected by GTZC_TZSC.WWDGSEC"
bit_offset: 11
bit_size: 1
- name: DBG_IWDG_STOP
description: "IWDG stop in CPU debug\r Write access can be protected by GTZC_TZSC.IWDGSEC."
bit_offset: 12
bit_size: 1
- name: DBG_I2C1_STOP
description: "I2C1 SMBUS timeout stop in CPU debug\r Write access can be protected by GTZC_TZSC.I2C1SEC."
bit_offset: 21
bit_size: 1
fieldset/APB2FZR:
description: APB2 peripheral freeze register
fields:
- name: DBG_TIM1_STOP
description: "TIM1 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM1SEC."
bit_offset: 11
bit_size: 1
- name: DBG_TIM16_STOP
description: "TIM16 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM16SEC."
bit_offset: 17
bit_size: 1
- name: DBG_TIM17_STOP
description: "TIM17 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM17SEC."
bit_offset: 18
bit_size: 1
fieldset/APB7FZR:
description: APB7 peripheral freeze register
fields:
- name: DBG_I2C3_STOP
description: "I2C3 stop in CPU debug\r Access can be protected by GTZC_TZSC.I2C3SEC."
bit_offset: 10
bit_size: 1
- name: DBG_LPTIM1_STOP
description: "LPTIM1 stop in CPU debug\r Access can be protected by GTZC_TZSC.LPTIM1SEC."
bit_offset: 17
bit_size: 1
- name: DBG_RTC_STOP
description: "RTC stop in CPU debug\r Access can be protected by GTZC_TZSC.TIM17SEC.\r Can only be accessed secure when one or more features in the RTC or TAMP is/are secure."
bit_offset: 30
bit_size: 1
fieldset/CIDR0:
description: CoreSight component identity register 0
fields:
- name: PREAMBLE
description: Component ID bits [7:0]
bit_offset: 0
bit_size: 8
fieldset/CIDR1:
description: CoreSight peripheral identity register 1
fields:
- name: PREAMBLE
description: Component ID bits [11:8]
bit_offset: 0
bit_size: 4
- name: CLASS
description: Component ID bits [15:12] - component class
bit_offset: 4
bit_size: 4
fieldset/CIDR2:
description: CoreSight component identity register 2
fields:
- name: PREAMBLE
description: Component ID bits [23:16]
bit_offset: 0
bit_size: 8
fieldset/CIDR3:
description: CoreSight component identity register 3
fields:
- name: PREAMBLE
description: Component ID bits [31:24]
bit_offset: 0
bit_size: 8
fieldset/CR:
description: status and configuration register
fields:
- name: DBG_STOP
description: "Allows debug in Stop mode\r Write access can be protected by PWR_SECCFGR.LPMSEC.\r The CPU debug and clocks remain active and the HSI16 oscillators is used as system clock during Stop debug mode, allowing CPU debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state."
bit_offset: 1
bit_size: 1
- name: DBG_STANDBY
description: "Allows debug in Standby mode\r Write access can be protected by PWR_SECCFGR.LPMSEC.\r The CPU debug and clocks remain active and the HSI16 oscillator is used as system clock, the supply and SRAM memory content is maintained during Standby debug mode, allowing CPU debug capability. On exit from Standby mode, a standby reset is performed."
bit_offset: 2
bit_size: 1
- name: LPMS
description: "Device low power mode selected\r 10x: Standby mode\r others reserved"
bit_offset: 16
bit_size: 3
- name: STOPF
description: Device Stop flag
bit_offset: 19
bit_size: 1
- name: SBF
description: Device Standby flag
bit_offset: 20
bit_size: 1
- name: CS
description: CPU Sleep
bit_offset: 24
bit_size: 1
- name: CDS
description: CPU DeepSleep
bit_offset: 25
bit_size: 1
fieldset/DBG_AUTH_DEVICE:
description: debug device authentication register
fields:
- name: AUTH_ID
description: "Device specific ID\r Device specific ID used for RDP regression."
bit_offset: 0
bit_size: 32
fieldset/DBG_AUTH_HOST:
description: debug host authentication register
fields:
- name: AUTH_KEY
description: "Device authentication key\r The device specific 64-bit authentication key (OEMn key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory."
bit_offset: 0
bit_size: 32
fieldset/IDCODE:
description: identity code register
fields:
- name: DEV_ID
description: Device ID
bit_offset: 0
bit_size: 12
- name: REV_ID
description: Revision ID
bit_offset: 16
bit_size: 16
fieldset/PIDR0:
description: CoreSight peripheral identity register 0
fields:
- name: PARTNUM
description: Part number bits [7:0]
bit_offset: 0
bit_size: 8
fieldset/PIDR1:
description: CoreSight peripheral identity register 1
fields:
- name: PARTNUM
description: Part number bits [11:8]
bit_offset: 0
bit_size: 4
- name: JEP106ID
description: JEP106 identity code bits [3:0]
bit_offset: 4
bit_size: 4
fieldset/PIDR2:
description: CoreSight peripheral identity register 2
fields:
- name: JEP106ID
description: JEP106 identity code bits [6:4]
bit_offset: 0
bit_size: 3
- name: JEDEC
description: JEDEC assigned value
bit_offset: 3
bit_size: 1
- name: REVISION
description: Component revision number
bit_offset: 4
bit_size: 4
fieldset/PIDR3:
description: CoreSight peripheral identity register 3
fields:
- name: CMOD
description: Customer modified
bit_offset: 0
bit_size: 4
- name: REVAND
description: Metal fix version
bit_offset: 4
bit_size: 4
fieldset/PIDR4:
description: CoreSight peripheral identity register 4
fields:
- name: JEP106CON
description: JEP106 continuation code
bit_offset: 0
bit_size: 4
- name: F4KCOUNT
description: Register file size
bit_offset: 4
bit_size: 4
fieldset/PNCR:
description: part number codification register
fields:
- name: CODIFICATION
description: Part number codification
bit_offset: 0
bit_size: 32
fieldset/SR:
description: status register
fields:
- name: AP_PRESENT
description: "Bit n identifies whether access port APn is present in device \r Bit n<>=<3D>0: APn absent \r Bit n<>=<3D>1: APn present"
bit_offset: 0
bit_size: 16
- name: AP_ENABLED
description: "Bit n identifies whether access port APn is open (can be accessed via the debug port) or locked (debug access to the APn is blocked, except for access) \r Bit n<>=<3D>0: APn locked (except for access to DBGMCU)\r Bit n<>=<3D>1: APn enabled"
bit_offset: 16
bit_size: 16

313
data/registers/dbgmcu_wl.yaml
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@ -1,181 +1,180 @@
---
block/DBGMCU: block/DBGMCU:
description: Microcontroller Debug Unit description: Microcontroller Debug Unit
items: items:
- name: IDCODER - name: IDCODER
description: Identity Code Register description: Identity Code Register
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IDCODER fieldset: IDCODER
- name: CR - name: CR
description: Configuration Register description: Configuration Register
byte_offset: 4 byte_offset: 4
fieldset: CR fieldset: CR
- name: APB1FZR1 - name: APB1FZR1
description: CPU1 APB1 Peripheral Freeze Register 1 description: CPU1 APB1 Peripheral Freeze Register 1
byte_offset: 60 byte_offset: 60
fieldset: APB1FZR1 fieldset: APB1FZR1
- name: C2APB1FZR1 - name: C2APB1FZR1
description: "CPU2 APB1 Peripheral Freeze Register 1 [dual core device" description: CPU2 APB1 Peripheral Freeze Register 1 [dual core device
byte_offset: 64 byte_offset: 64
fieldset: C2APB1FZR1 fieldset: C2APB1FZR1
- name: APB1FZR2 - name: APB1FZR2
description: CPU1 APB1 Peripheral Freeze Register 2 description: CPU1 APB1 Peripheral Freeze Register 2
byte_offset: 68 byte_offset: 68
fieldset: APB1FZR2 fieldset: APB1FZR2
- name: C2APB1FZR2 - name: C2APB1FZR2
description: "CPU2 APB1 Peripheral Freeze Register 2 [dual core device" description: CPU2 APB1 Peripheral Freeze Register 2 [dual core device
byte_offset: 72 byte_offset: 72
fieldset: C2APB1FZR2 fieldset: C2APB1FZR2
- name: APB2FZR - name: APB2FZR
description: CPU1 APB2 Peripheral Freeze Register description: CPU1 APB2 Peripheral Freeze Register
byte_offset: 76 byte_offset: 76
fieldset: APB2FZR fieldset: APB2FZR
- name: C2APB2FZR - name: C2APB2FZR
description: "CPU2 APB2 Peripheral Freeze Register [dual core device" description: CPU2 APB2 Peripheral Freeze Register [dual core device
byte_offset: 80 byte_offset: 80
fieldset: C2APB2FZR fieldset: C2APB2FZR
fieldset/APB1FZR1: fieldset/APB1FZR1:
description: CPU1 APB1 Peripheral Freeze Register 1 description: CPU1 APB1 Peripheral Freeze Register 1
fields: fields:
- name: TIM2 - name: TIM2
description: TIM2 stop in CPU1 debug description: TIM2 stop in CPU1 debug
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: RTC - name: RTC
description: RTC stop in CPU1 debug description: RTC stop in CPU1 debug
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: WWDG - name: WWDG
description: WWDG stop in CPU1 debug description: WWDG stop in CPU1 debug
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: IWDG - name: IWDG
description: IWDG stop in CPU1 debug description: IWDG stop in CPU1 debug
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: I2C1 - name: I2C1
description: I2C1 SMBUS timeout stop in CPU1 debug description: I2C1 SMBUS timeout stop in CPU1 debug
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: I2C2 - name: I2C2
description: I2C2 SMBUS timeout stop in CPU1 debug description: I2C2 SMBUS timeout stop in CPU1 debug
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: I2C3 - name: I2C3
description: I2C3 SMBUS timeout stop in CPU1 debug description: I2C3 SMBUS timeout stop in CPU1 debug
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: LPTIM1 - name: LPTIM1
description: LPTIM1 stop in CPU1 debug description: LPTIM1 stop in CPU1 debug
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/APB1FZR2: fieldset/APB1FZR2:
description: CPU1 APB1 Peripheral Freeze Register 2 description: CPU1 APB1 Peripheral Freeze Register 2
fields: fields:
- name: LPTIM2 - name: LPTIM2
description: LPTIM2 description: LPTIM2
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: LPTIM3 - name: LPTIM3
description: LPTIM3 description: LPTIM3
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
fieldset/APB2FZR: fieldset/APB2FZR:
description: CPU1 APB2 Peripheral Freeze Register description: CPU1 APB2 Peripheral Freeze Register
fields: fields:
- name: TIM1 - name: TIM1
description: TIM1 description: TIM1
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: TIM16 - name: TIM16
description: TIM16 description: TIM16
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: TIM17 - name: TIM17
description: TIM17 description: TIM17
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/C2APB1FZR1: fieldset/C2APB1FZR1:
description: "CPU2 APB1 Peripheral Freeze Register 1 [dual core device" description: CPU2 APB1 Peripheral Freeze Register 1 [dual core device
fields: fields:
- name: TIM2 - name: TIM2
description: TIM2 description: TIM2
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: RTC - name: RTC
description: RTC description: RTC
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: IWDG - name: IWDG
description: IWDG description: IWDG
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: I2C1 - name: I2C1
description: I2C1 description: I2C1
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: I2C2 - name: I2C2
description: I2C2 description: I2C2
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: I2C3 - name: I2C3
description: I2C3 description: I2C3
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: LPTIM1 - name: LPTIM1
description: LPTIM1 description: LPTIM1
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/C2APB1FZR2: fieldset/C2APB1FZR2:
description: "CPU2 APB1 Peripheral Freeze Register 2 [dual core device" description: CPU2 APB1 Peripheral Freeze Register 2 [dual core device
fields: fields:
- name: LPTIM2 - name: LPTIM2
description: LPTIM2 description: LPTIM2
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: LPTIM3 - name: LPTIM3
description: LPTIM3 description: LPTIM3
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
fieldset/C2APB2FZR: fieldset/C2APB2FZR:
description: "CPU2 APB2 Peripheral Freeze Register [dual core device" description: CPU2 APB2 Peripheral Freeze Register [dual core device
fields: fields:
- name: TIM1 - name: TIM1
description: TIM1 description: TIM1
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: TIM16 - name: TIM16
description: TIM16 description: TIM16
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: TIM17 - name: TIM17
description: TIM17 description: TIM17
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Configuration Register description: Configuration Register
fields: fields:
- name: DBG_SLEEP - name: DBG_SLEEP
description: Allow debug in SLEEP mode description: Allow debug in SLEEP mode
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DBG_STOP - name: DBG_STOP
description: Allow debug in STOP mode description: Allow debug in STOP mode
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DBG_STANDBY - name: DBG_STANDBY
description: Allow debug in STANDBY mode description: Allow debug in STANDBY mode
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
fieldset/IDCODER: fieldset/IDCODER:
description: Identity Code Register description: Identity Code Register
fields: fields:
- name: DEV_ID - name: DEV_ID
description: Device ID description: Device ID
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
- name: REV_ID - name: REV_ID
description: Revision description: Revision
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16

499
data/registers/dcmi_v1.yaml
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@ -1,286 +1,285 @@
---
block/DCMI: block/DCMI:
description: Digital camera interface description: Digital camera interface
items: items:
- name: CR - name: CR
description: control register 1 description: control register 1
byte_offset: 0 byte_offset: 0
fieldset: CR fieldset: CR
- name: SR - name: SR
description: status register description: status register
byte_offset: 4 byte_offset: 4
access: Read access: Read
fieldset: SR fieldset: SR
- name: RIS - name: RIS
description: raw interrupt status register description: raw interrupt status register
byte_offset: 8 byte_offset: 8
access: Read access: Read
fieldset: RIS fieldset: RIS
- name: IER - name: IER
description: interrupt enable register description: interrupt enable register
byte_offset: 12 byte_offset: 12
fieldset: IER fieldset: IER
- name: MIS - name: MIS
description: masked interrupt status register description: masked interrupt status register
byte_offset: 16 byte_offset: 16
access: Read access: Read
fieldset: MIS fieldset: MIS
- name: ICR - name: ICR
description: interrupt clear register description: interrupt clear register
byte_offset: 20 byte_offset: 20
access: Write access: Write
fieldset: ICR fieldset: ICR
- name: ESCR - name: ESCR
description: embedded synchronization code register description: embedded synchronization code register
byte_offset: 24 byte_offset: 24
fieldset: ESCR fieldset: ESCR
- name: ESUR - name: ESUR
description: embedded synchronization unmask register description: embedded synchronization unmask register
byte_offset: 28 byte_offset: 28
fieldset: ESUR fieldset: ESUR
- name: CWSTRT - name: CWSTRT
description: crop window start description: crop window start
byte_offset: 32 byte_offset: 32
fieldset: CWSTRT fieldset: CWSTRT
- name: CWSIZE - name: CWSIZE
description: crop window size description: crop window size
byte_offset: 36 byte_offset: 36
fieldset: CWSIZE fieldset: CWSIZE
- name: DR - name: DR
description: data register description: data register
byte_offset: 40 byte_offset: 40
access: Read access: Read
fieldset: DR fieldset: DR
fieldset/CR: fieldset/CR:
description: control register 1 description: control register 1
fields: fields:
- name: CAPTURE - name: CAPTURE
description: Capture enable description: Capture enable
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: CM - name: CM
description: Capture mode description: Capture mode
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: CROP - name: CROP
description: Crop feature description: Crop feature
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: JPEG - name: JPEG
description: JPEG format description: JPEG format
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: ESS - name: ESS
description: Embedded synchronization select description: Embedded synchronization select
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: PCKPOL - name: PCKPOL
description: Pixel clock polarity description: Pixel clock polarity
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: HSPOL - name: HSPOL
description: Horizontal synchronization polarity description: Horizontal synchronization polarity
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: VSPOL - name: VSPOL
description: Vertical synchronization polarity description: Vertical synchronization polarity
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: FCRC - name: FCRC
description: Frame capture rate control description: Frame capture rate control
bit_offset: 8 bit_offset: 8
bit_size: 2 bit_size: 2
- name: EDM - name: EDM
description: Extended data mode description: Extended data mode
bit_offset: 10 bit_offset: 10
bit_size: 2 bit_size: 2
- name: ENABLE - name: ENABLE
description: DCMI enable description: DCMI enable
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
fieldset/CWSIZE: fieldset/CWSIZE:
description: crop window size description: crop window size
fields: fields:
- name: CAPCNT - name: CAPCNT
description: Capture count description: Capture count
bit_offset: 0 bit_offset: 0
bit_size: 14 bit_size: 14
- name: VLINE - name: VLINE
description: Vertical line count description: Vertical line count
bit_offset: 16 bit_offset: 16
bit_size: 14 bit_size: 14
fieldset/CWSTRT: fieldset/CWSTRT:
description: crop window start description: crop window start
fields: fields:
- name: HOFFCNT - name: HOFFCNT
description: Horizontal offset count description: Horizontal offset count
bit_offset: 0 bit_offset: 0
bit_size: 14 bit_size: 14
- name: VST - name: VST
description: Vertical start line count description: Vertical start line count
bit_offset: 16 bit_offset: 16
bit_size: 13 bit_size: 13
fieldset/DR: fieldset/DR:
description: data register description: data register
fields: fields:
- name: Byte0 - name: Byte0
description: Data byte 0 description: Data byte 0
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: Byte1 - name: Byte1
description: Data byte 1 description: Data byte 1
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
- name: Byte2 - name: Byte2
description: Data byte 2 description: Data byte 2
bit_offset: 16 bit_offset: 16
bit_size: 8 bit_size: 8
- name: Byte3 - name: Byte3
description: Data byte 3 description: Data byte 3
bit_offset: 24 bit_offset: 24
bit_size: 8 bit_size: 8
fieldset/ESCR: fieldset/ESCR:
description: embedded synchronization code register description: embedded synchronization code register
fields: fields:
- name: FSC - name: FSC
description: Frame start delimiter code description: Frame start delimiter code
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: LSC - name: LSC
description: Line start delimiter code description: Line start delimiter code
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
- name: LEC - name: LEC
description: Line end delimiter code description: Line end delimiter code
bit_offset: 16 bit_offset: 16
bit_size: 8 bit_size: 8
- name: FEC - name: FEC
description: Frame end delimiter code description: Frame end delimiter code
bit_offset: 24 bit_offset: 24
bit_size: 8 bit_size: 8
fieldset/ESUR: fieldset/ESUR:
description: embedded synchronization unmask register description: embedded synchronization unmask register
fields: fields:
- name: FSU - name: FSU
description: Frame start delimiter unmask description: Frame start delimiter unmask
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: LSU - name: LSU
description: Line start delimiter unmask description: Line start delimiter unmask
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
- name: LEU - name: LEU
description: Line end delimiter unmask description: Line end delimiter unmask
bit_offset: 16 bit_offset: 16
bit_size: 8 bit_size: 8
- name: FEU - name: FEU
description: Frame end delimiter unmask description: Frame end delimiter unmask
bit_offset: 24 bit_offset: 24
bit_size: 8 bit_size: 8
fieldset/ICR: fieldset/ICR:
description: interrupt clear register description: interrupt clear register
fields: fields:
- name: FRAME_ISC - name: FRAME_ISC
description: Capture complete interrupt status clear description: Capture complete interrupt status clear
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: OVR_ISC - name: OVR_ISC
description: Overrun interrupt status clear description: Overrun interrupt status clear
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: ERR_ISC - name: ERR_ISC
description: Synchronization error interrupt status clear description: Synchronization error interrupt status clear
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: VSYNC_ISC - name: VSYNC_ISC
description: Vertical synch interrupt status clear description: Vertical synch interrupt status clear
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: LINE_ISC - name: LINE_ISC
description: line interrupt status clear description: line interrupt status clear
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
fieldset/IER: fieldset/IER:
description: interrupt enable register description: interrupt enable register
fields: fields:
- name: FRAME_IE - name: FRAME_IE
description: Capture complete interrupt enable description: Capture complete interrupt enable
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: OVR_IE - name: OVR_IE
description: Overrun interrupt enable description: Overrun interrupt enable
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: ERR_IE - name: ERR_IE
description: Synchronization error interrupt enable description: Synchronization error interrupt enable
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: VSYNC_IE - name: VSYNC_IE
description: VSYNC interrupt enable description: VSYNC interrupt enable
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: LINE_IE - name: LINE_IE
description: Line interrupt enable description: Line interrupt enable
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
fieldset/MIS: fieldset/MIS:
description: masked interrupt status register description: masked interrupt status register
fields: fields:
- name: FRAME_MIS - name: FRAME_MIS
description: Capture complete masked interrupt status description: Capture complete masked interrupt status
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: OVR_MIS - name: OVR_MIS
description: Overrun masked interrupt status description: Overrun masked interrupt status
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: ERR_MIS - name: ERR_MIS
description: Synchronization error masked interrupt status description: Synchronization error masked interrupt status
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: VSYNC_MIS - name: VSYNC_MIS
description: VSYNC masked interrupt status description: VSYNC masked interrupt status
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: LINE_MIS - name: LINE_MIS
description: Line masked interrupt status description: Line masked interrupt status
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
fieldset/RIS: fieldset/RIS:
description: raw interrupt status register description: raw interrupt status register
fields: fields:
- name: FRAME_RIS - name: FRAME_RIS
description: Capture complete raw interrupt status description: Capture complete raw interrupt status
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: OVR_RIS - name: OVR_RIS
description: Overrun raw interrupt status description: Overrun raw interrupt status
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: ERR_RIS - name: ERR_RIS
description: Synchronization error raw interrupt status description: Synchronization error raw interrupt status
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: VSYNC_RIS - name: VSYNC_RIS
description: VSYNC raw interrupt status description: VSYNC raw interrupt status
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: LINE_RIS - name: LINE_RIS
description: Line raw interrupt status description: Line raw interrupt status
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
fieldset/SR: fieldset/SR:
description: status register description: status register
fields: fields:
- name: HSYNC - name: HSYNC
description: HSYNC description: HSYNC
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: VSYNC - name: VSYNC
description: VSYNC description: VSYNC
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: FNE - name: FNE
description: FIFO not empty description: FIFO not empty
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1

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data/registers/dma2d_v1.yaml
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@ -1,378 +1,377 @@
---
block/DMA: block/DMA:
description: DMA controller description: DMA controller
items: items:
- name: ISR - name: ISR
description: low interrupt status register description: low interrupt status register
array: array:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IXR fieldset: IXR
- name: IFCR - name: IFCR
description: low interrupt flag clear register description: low interrupt flag clear register
array: array:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 8 byte_offset: 8
access: Write access: Write
fieldset: IXR fieldset: IXR
- name: ST - name: ST
description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers" description: 'Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers'
array: array:
len: 8 len: 8
stride: 24 stride: 24
byte_offset: 16 byte_offset: 16
block: ST block: ST
block/ST: block/ST:
description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers" description: 'Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers'
items: items:
- name: CR - name: CR
description: stream x configuration register description: stream x configuration register
byte_offset: 0 byte_offset: 0
fieldset: CR fieldset: CR
- name: NDTR - name: NDTR
description: stream x number of data register description: stream x number of data register
byte_offset: 4 byte_offset: 4
fieldset: NDTR fieldset: NDTR
- name: PAR - name: PAR
description: stream x peripheral address register description: stream x peripheral address register
byte_offset: 8 byte_offset: 8
- name: M0AR - name: M0AR
description: stream x memory 0 address register description: stream x memory 0 address register
byte_offset: 12 byte_offset: 12
- name: M1AR - name: M1AR
description: stream x memory 1 address register description: stream x memory 1 address register
byte_offset: 16 byte_offset: 16
- name: FCR - name: FCR
description: stream x FIFO control register description: stream x FIFO control register
byte_offset: 20 byte_offset: 20
fieldset: FCR fieldset: FCR
fieldset/CR: fieldset/CR:
description: stream x configuration register description: stream x configuration register
fields: fields:
- name: EN - name: EN
description: Stream enable / flag stream ready when read low description: Stream enable / flag stream ready when read low
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DMEIE - name: DMEIE
description: Direct mode error interrupt enable description: Direct mode error interrupt enable
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: TEIE - name: TEIE
description: Transfer error interrupt enable description: Transfer error interrupt enable
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: HTIE - name: HTIE
description: Half transfer interrupt enable description: Half transfer interrupt enable
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: TCIE - name: TCIE
description: Transfer complete interrupt enable description: Transfer complete interrupt enable
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: PFCTRL - name: PFCTRL
description: Peripheral flow controller description: Peripheral flow controller
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum: PFCTRL enum: PFCTRL
- name: DIR - name: DIR
description: Data transfer direction description: Data transfer direction
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
enum: DIR enum: DIR
- name: CIRC - name: CIRC
description: Circular mode description: Circular mode
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
enum: CIRC enum: CIRC
- name: PINC - name: PINC
description: Peripheral increment mode description: Peripheral increment mode
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
enum: INC enum: INC
- name: MINC - name: MINC
description: Memory increment mode description: Memory increment mode
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
enum: INC enum: INC
- name: PSIZE - name: PSIZE
description: Peripheral data size description: Peripheral data size
bit_offset: 11 bit_offset: 11
bit_size: 2 bit_size: 2
enum: SIZE enum: SIZE
- name: MSIZE - name: MSIZE
description: Memory data size description: Memory data size
bit_offset: 13 bit_offset: 13
bit_size: 2 bit_size: 2
enum: SIZE enum: SIZE
- name: PINCOS - name: PINCOS
description: Peripheral increment offset size description: Peripheral increment offset size
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
enum: PINCOS enum: PINCOS
- name: PL - name: PL
description: Priority level description: Priority level
bit_offset: 16 bit_offset: 16
bit_size: 2 bit_size: 2
enum: PL enum: PL
- name: DBM - name: DBM
description: Double buffer mode description: Double buffer mode
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
enum: DBM enum: DBM
- name: CT - name: CT
description: Current target (only in double buffer mode) description: Current target (only in double buffer mode)
bit_offset: 19 bit_offset: 19
bit_size: 1 bit_size: 1
enum: CT enum: CT
- name: TRBUFF - name: TRBUFF
description: Enable bufferable transfers description: Enable bufferable transfers
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
- name: PBURST - name: PBURST
description: Peripheral burst transfer configuration description: Peripheral burst transfer configuration
bit_offset: 21 bit_offset: 21
bit_size: 2 bit_size: 2
enum: BURST enum: BURST
- name: MBURST - name: MBURST
description: Memory burst transfer configuration description: Memory burst transfer configuration
bit_offset: 23 bit_offset: 23
bit_size: 2 bit_size: 2
enum: BURST enum: BURST
fieldset/FCR: fieldset/FCR:
description: stream x FIFO control register description: stream x FIFO control register
fields: fields:
- name: FTH - name: FTH
description: FIFO threshold selection description: FIFO threshold selection
bit_offset: 0 bit_offset: 0
bit_size: 2 bit_size: 2
enum: FTH enum: FTH
- name: DMDIS - name: DMDIS
description: Direct mode disable description: Direct mode disable
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum: DMDIS enum: DMDIS
- name: FS - name: FS
description: FIFO status description: FIFO status
bit_offset: 3 bit_offset: 3
bit_size: 3 bit_size: 3
enum: FS enum: FS
- name: FEIE - name: FEIE
description: FIFO error interrupt enable description: FIFO error interrupt enable
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
fieldset/IXR: fieldset/IXR:
description: interrupt register description: interrupt register
fields: fields:
- name: FEIF - name: FEIF
description: Stream x FIFO error interrupt flag (x=3..0) description: Stream x FIFO error interrupt flag (x=3..0)
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
offsets: offsets:
- 0 - 0
- 6 - 6
- 16 - 16
- 22 - 22
- name: DMEIF - name: DMEIF
description: Stream x direct mode error interrupt flag (x=3..0) description: Stream x direct mode error interrupt flag (x=3..0)
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
array: array:
offsets: offsets:
- 0 - 0
- 6 - 6
- 16 - 16
- 22 - 22
- name: TEIF - name: TEIF
description: Stream x transfer error interrupt flag (x=3..0) description: Stream x transfer error interrupt flag (x=3..0)
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
array: array:
offsets: offsets:
- 0 - 0
- 6 - 6
- 16 - 16
- 22 - 22
- name: HTIF - name: HTIF
description: Stream x half transfer interrupt flag (x=3..0) description: Stream x half transfer interrupt flag (x=3..0)
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
array: array:
offsets: offsets:
- 0 - 0
- 6 - 6
- 16 - 16
- 22 - 22
- name: TCIF - name: TCIF
description: Stream x transfer complete interrupt flag (x = 3..0) description: Stream x transfer complete interrupt flag (x = 3..0)
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
array: array:
offsets: offsets:
- 0 - 0
- 6 - 6
- 16 - 16
- 22 - 22
fieldset/NDTR: fieldset/NDTR:
description: stream x number of data register description: stream x number of data register
fields: fields:
- name: NDT - name: NDT
description: Number of data items to transfer description: Number of data items to transfer
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
enum/BURST: enum/BURST:
bit_size: 2 bit_size: 2
variants: variants:
- name: Single - name: Single
description: Single transfer description: Single transfer
value: 0 value: 0
- name: INCR4 - name: INCR4
description: Incremental burst of 4 beats description: Incremental burst of 4 beats
value: 1 value: 1
- name: INCR8 - name: INCR8
description: Incremental burst of 8 beats description: Incremental burst of 8 beats
value: 2 value: 2
- name: INCR16 - name: INCR16
description: Incremental burst of 16 beats description: Incremental burst of 16 beats
value: 3 value: 3
enum/CIRC: enum/CIRC:
bit_size: 1 bit_size: 1
variants: variants:
- name: Disabled - name: Disabled
description: Circular mode disabled description: Circular mode disabled
value: 0 value: 0
- name: Enabled - name: Enabled
description: Circular mode enabled description: Circular mode enabled
value: 1 value: 1
enum/CT: enum/CT:
bit_size: 1 bit_size: 1
variants: variants:
- name: Memory0 - name: Memory0
description: The current target memory is Memory 0 description: The current target memory is Memory 0
value: 0 value: 0
- name: Memory1 - name: Memory1
description: The current target memory is Memory 1 description: The current target memory is Memory 1
value: 1 value: 1
enum/DBM: enum/DBM:
bit_size: 1 bit_size: 1
variants: variants:
- name: Disabled - name: Disabled
description: No buffer switching at the end of transfer description: No buffer switching at the end of transfer
value: 0 value: 0
- name: Enabled - name: Enabled
description: Memory target switched at the end of the DMA transfer description: Memory target switched at the end of the DMA transfer
value: 1 value: 1
enum/DIR: enum/DIR:
bit_size: 2 bit_size: 2
variants: variants:
- name: PeripheralToMemory - name: PeripheralToMemory
description: Peripheral-to-memory description: Peripheral-to-memory
value: 0 value: 0
- name: MemoryToPeripheral - name: MemoryToPeripheral
description: Memory-to-peripheral description: Memory-to-peripheral
value: 1 value: 1
- name: MemoryToMemory - name: MemoryToMemory
description: Memory-to-memory description: Memory-to-memory
value: 2 value: 2
enum/DMDIS: enum/DMDIS:
bit_size: 1 bit_size: 1
variants: variants:
- name: Enabled - name: Enabled
description: Direct mode is enabled description: Direct mode is enabled
value: 0 value: 0
- name: Disabled - name: Disabled
description: Direct mode is disabled description: Direct mode is disabled
value: 1 value: 1
enum/FS: enum/FS:
bit_size: 3 bit_size: 3
variants: variants:
- name: Quarter1 - name: Quarter1
description: 0 < fifo_level < 1/4 description: 0 < fifo_level < 1/4
value: 0 value: 0
- name: Quarter2 - name: Quarter2
description: 1/4 <= fifo_level < 1/2 description: 1/4 <= fifo_level < 1/2
value: 1 value: 1
- name: Quarter3 - name: Quarter3
description: 1/2 <= fifo_level < 3/4 description: 1/2 <= fifo_level < 3/4
value: 2 value: 2
- name: Quarter4 - name: Quarter4
description: 3/4 <= fifo_level < full description: 3/4 <= fifo_level < full
value: 3 value: 3
- name: Empty - name: Empty
description: FIFO is empty description: FIFO is empty
value: 4 value: 4
- name: Full - name: Full
description: FIFO is full description: FIFO is full
value: 5 value: 5
enum/FTH: enum/FTH:
bit_size: 2 bit_size: 2
variants: variants:
- name: Quarter - name: Quarter
description: 1/4 full FIFO description: 1/4 full FIFO
value: 0 value: 0
- name: Half - name: Half
description: 1/2 full FIFO description: 1/2 full FIFO
value: 1 value: 1
- name: ThreeQuarters - name: ThreeQuarters
description: 3/4 full FIFO description: 3/4 full FIFO
value: 2 value: 2
- name: Full - name: Full
description: Full FIFO description: Full FIFO
value: 3 value: 3
enum/INC: enum/INC:
bit_size: 1 bit_size: 1
variants: variants:
- name: Fixed - name: Fixed
description: Address pointer is fixed description: Address pointer is fixed
value: 0 value: 0
- name: Incremented - name: Incremented
description: Address pointer is incremented after each data transfer description: Address pointer is incremented after each data transfer
value: 1 value: 1
enum/PFCTRL: enum/PFCTRL:
bit_size: 1 bit_size: 1
variants: variants:
- name: DMA - name: DMA
description: The DMA is the flow controller description: The DMA is the flow controller
value: 0 value: 0
- name: Peripheral - name: Peripheral
description: The peripheral is the flow controller description: The peripheral is the flow controller
value: 1 value: 1
enum/PINCOS: enum/PINCOS:
bit_size: 1 bit_size: 1
variants: variants:
- name: PSIZE - name: PSIZE
description: The offset size for the peripheral address calculation is linked to the PSIZE description: The offset size for the peripheral address calculation is linked to the PSIZE
value: 0 value: 0
- name: Fixed4 - name: Fixed4
description: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment) description: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)
value: 1 value: 1
enum/PL: enum/PL:
bit_size: 2 bit_size: 2
variants: variants:
- name: Low - name: Low
description: Low description: Low
value: 0 value: 0
- name: Medium - name: Medium
description: Medium description: Medium
value: 1 value: 1
- name: High - name: High
description: High description: High
value: 2 value: 2
- name: VeryHigh - name: VeryHigh
description: Very high description: Very high
value: 3 value: 3
enum/SIZE: enum/SIZE:
bit_size: 2 bit_size: 2
variants: variants:
- name: Bits8 - name: Bits8
description: Byte (8-bit) description: Byte (8-bit)
value: 0 value: 0
- name: Bits16 - name: Bits16
description: Half-word (16-bit) description: Half-word (16-bit)
value: 1 value: 1
- name: Bits32 - name: Bits32
description: Word (32-bit) description: Word (32-bit)
value: 2 value: 2

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data/registers/dma_v2.yaml
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@ -1,378 +1,377 @@
---
block/DMA: block/DMA:
description: DMA controller description: DMA controller
items: items:
- name: ISR - name: ISR
description: low interrupt status register description: low interrupt status register
array: array:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 0 byte_offset: 0
access: Read access: Read
fieldset: IXR fieldset: IXR
- name: IFCR - name: IFCR
description: low interrupt flag clear register description: low interrupt flag clear register
array: array:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 8 byte_offset: 8
access: Write access: Write
fieldset: IXR fieldset: IXR
- name: ST - name: ST
description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers" description: 'Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers'
array: array:
len: 8 len: 8
stride: 24 stride: 24
byte_offset: 16 byte_offset: 16
block: ST block: ST
block/ST: block/ST:
description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers" description: 'Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers'
items: items:
- name: CR - name: CR
description: stream x configuration register description: stream x configuration register
byte_offset: 0 byte_offset: 0
fieldset: CR fieldset: CR
- name: NDTR - name: NDTR
description: stream x number of data register description: stream x number of data register
byte_offset: 4 byte_offset: 4
fieldset: NDTR fieldset: NDTR
- name: PAR - name: PAR
description: stream x peripheral address register description: stream x peripheral address register
byte_offset: 8 byte_offset: 8
- name: M0AR - name: M0AR
description: stream x memory 0 address register description: stream x memory 0 address register
byte_offset: 12 byte_offset: 12
- name: M1AR - name: M1AR
description: stream x memory 1 address register description: stream x memory 1 address register
byte_offset: 16 byte_offset: 16
- name: FCR - name: FCR
description: stream x FIFO control register description: stream x FIFO control register
byte_offset: 20 byte_offset: 20
fieldset: FCR fieldset: FCR
fieldset/CR: fieldset/CR:
description: stream x configuration register description: stream x configuration register
fields: fields:
- name: EN - name: EN
description: Stream enable / flag stream ready when read low description: Stream enable / flag stream ready when read low
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: DMEIE - name: DMEIE
description: Direct mode error interrupt enable description: Direct mode error interrupt enable
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: TEIE - name: TEIE
description: Transfer error interrupt enable description: Transfer error interrupt enable
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: HTIE - name: HTIE
description: Half transfer interrupt enable description: Half transfer interrupt enable
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: TCIE - name: TCIE
description: Transfer complete interrupt enable description: Transfer complete interrupt enable
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: PFCTRL - name: PFCTRL
description: Peripheral flow controller description: Peripheral flow controller
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum: PFCTRL enum: PFCTRL
- name: DIR - name: DIR
description: Data transfer direction description: Data transfer direction
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
enum: DIR enum: DIR
- name: CIRC - name: CIRC
description: Circular mode description: Circular mode
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
enum: CIRC enum: CIRC
- name: PINC - name: PINC
description: Peripheral increment mode description: Peripheral increment mode
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
enum: INC enum: INC
- name: MINC - name: MINC
description: Memory increment mode description: Memory increment mode
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
enum: INC enum: INC
- name: PSIZE - name: PSIZE
description: Peripheral data size description: Peripheral data size
bit_offset: 11 bit_offset: 11
bit_size: 2 bit_size: 2
enum: SIZE enum: SIZE
- name: MSIZE - name: MSIZE
description: Memory data size description: Memory data size
bit_offset: 13 bit_offset: 13
bit_size: 2 bit_size: 2
enum: SIZE enum: SIZE
- name: PINCOS - name: PINCOS
description: Peripheral increment offset size description: Peripheral increment offset size
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
enum: PINCOS enum: PINCOS
- name: PL - name: PL
description: Priority level description: Priority level
bit_offset: 16 bit_offset: 16
bit_size: 2 bit_size: 2
enum: PL enum: PL
- name: DBM - name: DBM
description: Double buffer mode description: Double buffer mode
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
enum: DBM enum: DBM
- name: CT - name: CT
description: Current target (only in double buffer mode) description: Current target (only in double buffer mode)
bit_offset: 19 bit_offset: 19
bit_size: 1 bit_size: 1
enum: CT enum: CT
- name: PBURST - name: PBURST
description: Peripheral burst transfer configuration description: Peripheral burst transfer configuration
bit_offset: 21 bit_offset: 21
bit_size: 2 bit_size: 2
enum: BURST enum: BURST
- name: MBURST - name: MBURST
description: Memory burst transfer configuration description: Memory burst transfer configuration
bit_offset: 23 bit_offset: 23
bit_size: 2 bit_size: 2
enum: BURST enum: BURST
- name: CHSEL - name: CHSEL
description: Channel selection description: Channel selection
bit_offset: 25 bit_offset: 25
bit_size: 4 bit_size: 4
fieldset/FCR: fieldset/FCR:
description: stream x FIFO control register description: stream x FIFO control register
fields: fields:
- name: FTH - name: FTH
description: FIFO threshold selection description: FIFO threshold selection
bit_offset: 0 bit_offset: 0
bit_size: 2 bit_size: 2
enum: FTH enum: FTH
- name: DMDIS - name: DMDIS
description: Direct mode disable description: Direct mode disable
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum: DMDIS enum: DMDIS
- name: FS - name: FS
description: FIFO status description: FIFO status
bit_offset: 3 bit_offset: 3
bit_size: 3 bit_size: 3
enum: FS enum: FS
- name: FEIE - name: FEIE
description: FIFO error interrupt enable description: FIFO error interrupt enable
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
fieldset/IXR: fieldset/IXR:
description: interrupt register description: interrupt register
fields: fields:
- name: FEIF - name: FEIF
description: Stream x FIFO error interrupt flag (x=3..0) description: Stream x FIFO error interrupt flag (x=3..0)
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
offsets: offsets:
- 0 - 0
- 6 - 6
- 16 - 16
- 22 - 22
- name: DMEIF - name: DMEIF
description: Stream x direct mode error interrupt flag (x=3..0) description: Stream x direct mode error interrupt flag (x=3..0)
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
array: array:
offsets: offsets:
- 0 - 0
- 6 - 6
- 16 - 16
- 22 - 22
- name: TEIF - name: TEIF
description: Stream x transfer error interrupt flag (x=3..0) description: Stream x transfer error interrupt flag (x=3..0)
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
array: array:
offsets: offsets:
- 0 - 0
- 6 - 6
- 16 - 16
- 22 - 22
- name: HTIF - name: HTIF
description: Stream x half transfer interrupt flag (x=3..0) description: Stream x half transfer interrupt flag (x=3..0)
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
array: array:
offsets: offsets:
- 0 - 0
- 6 - 6
- 16 - 16
- 22 - 22
- name: TCIF - name: TCIF
description: Stream x transfer complete interrupt flag (x = 3..0) description: Stream x transfer complete interrupt flag (x = 3..0)
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
array: array:
offsets: offsets:
- 0 - 0
- 6 - 6
- 16 - 16
- 22 - 22
fieldset/NDTR: fieldset/NDTR:
description: stream x number of data register description: stream x number of data register
fields: fields:
- name: NDT - name: NDT
description: Number of data items to transfer description: Number of data items to transfer
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
enum/BURST: enum/BURST:
bit_size: 2 bit_size: 2
variants: variants:
- name: Single - name: Single
description: Single transfer description: Single transfer
value: 0 value: 0
- name: INCR4 - name: INCR4
description: Incremental burst of 4 beats description: Incremental burst of 4 beats
value: 1 value: 1
- name: INCR8 - name: INCR8
description: Incremental burst of 8 beats description: Incremental burst of 8 beats
value: 2 value: 2
- name: INCR16 - name: INCR16
description: Incremental burst of 16 beats description: Incremental burst of 16 beats
value: 3 value: 3
enum/CIRC: enum/CIRC:
bit_size: 1 bit_size: 1
variants: variants:
- name: Disabled - name: Disabled
description: Circular mode disabled description: Circular mode disabled
value: 0 value: 0
- name: Enabled - name: Enabled
description: Circular mode enabled description: Circular mode enabled
value: 1 value: 1
enum/CT: enum/CT:
bit_size: 1 bit_size: 1
variants: variants:
- name: Memory0 - name: Memory0
description: The current target memory is Memory 0 description: The current target memory is Memory 0
value: 0 value: 0
- name: Memory1 - name: Memory1
description: The current target memory is Memory 1 description: The current target memory is Memory 1
value: 1 value: 1
enum/DBM: enum/DBM:
bit_size: 1 bit_size: 1
variants: variants:
- name: Disabled - name: Disabled
description: No buffer switching at the end of transfer description: No buffer switching at the end of transfer
value: 0 value: 0
- name: Enabled - name: Enabled
description: Memory target switched at the end of the DMA transfer description: Memory target switched at the end of the DMA transfer
value: 1 value: 1
enum/DIR: enum/DIR:
bit_size: 2 bit_size: 2
variants: variants:
- name: PeripheralToMemory - name: PeripheralToMemory
description: Peripheral-to-memory description: Peripheral-to-memory
value: 0 value: 0
- name: MemoryToPeripheral - name: MemoryToPeripheral
description: Memory-to-peripheral description: Memory-to-peripheral
value: 1 value: 1
- name: MemoryToMemory - name: MemoryToMemory
description: Memory-to-memory description: Memory-to-memory
value: 2 value: 2
enum/DMDIS: enum/DMDIS:
bit_size: 1 bit_size: 1
variants: variants:
- name: Enabled - name: Enabled
description: Direct mode is enabled description: Direct mode is enabled
value: 0 value: 0
- name: Disabled - name: Disabled
description: Direct mode is disabled description: Direct mode is disabled
value: 1 value: 1
enum/FS: enum/FS:
bit_size: 3 bit_size: 3
variants: variants:
- name: Quarter1 - name: Quarter1
description: 0 < fifo_level < 1/4 description: 0 < fifo_level < 1/4
value: 0 value: 0
- name: Quarter2 - name: Quarter2
description: 1/4 <= fifo_level < 1/2 description: 1/4 <= fifo_level < 1/2
value: 1 value: 1
- name: Quarter3 - name: Quarter3
description: 1/2 <= fifo_level < 3/4 description: 1/2 <= fifo_level < 3/4
value: 2 value: 2
- name: Quarter4 - name: Quarter4
description: 3/4 <= fifo_level < full description: 3/4 <= fifo_level < full
value: 3 value: 3
- name: Empty - name: Empty
description: FIFO is empty description: FIFO is empty
value: 4 value: 4
- name: Full - name: Full
description: FIFO is full description: FIFO is full
value: 5 value: 5
enum/FTH: enum/FTH:
bit_size: 2 bit_size: 2
variants: variants:
- name: Quarter - name: Quarter
description: 1/4 full FIFO description: 1/4 full FIFO
value: 0 value: 0
- name: Half - name: Half
description: 1/2 full FIFO description: 1/2 full FIFO
value: 1 value: 1
- name: ThreeQuarters - name: ThreeQuarters
description: 3/4 full FIFO description: 3/4 full FIFO
value: 2 value: 2
- name: Full - name: Full
description: Full FIFO description: Full FIFO
value: 3 value: 3
enum/INC: enum/INC:
bit_size: 1 bit_size: 1
variants: variants:
- name: Fixed - name: Fixed
description: Address pointer is fixed description: Address pointer is fixed
value: 0 value: 0
- name: Incremented - name: Incremented
description: Address pointer is incremented after each data transfer description: Address pointer is incremented after each data transfer
value: 1 value: 1
enum/PFCTRL: enum/PFCTRL:
bit_size: 1 bit_size: 1
variants: variants:
- name: DMA - name: DMA
description: The DMA is the flow controller description: The DMA is the flow controller
value: 0 value: 0
- name: Peripheral - name: Peripheral
description: The peripheral is the flow controller description: The peripheral is the flow controller
value: 1 value: 1
enum/PINCOS: enum/PINCOS:
bit_size: 1 bit_size: 1
variants: variants:
- name: PSIZE - name: PSIZE
description: The offset size for the peripheral address calculation is linked to the PSIZE description: The offset size for the peripheral address calculation is linked to the PSIZE
value: 0 value: 0
- name: Fixed4 - name: Fixed4
description: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment) description: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)
value: 1 value: 1
enum/PL: enum/PL:
bit_size: 2 bit_size: 2
variants: variants:
- name: Low - name: Low
description: Low description: Low
value: 0 value: 0
- name: Medium - name: Medium
description: Medium description: Medium
value: 1 value: 1
- name: High - name: High
description: High description: High
value: 2 value: 2
- name: VeryHigh - name: VeryHigh
description: Very high description: Very high
value: 3 value: 3
enum/SIZE: enum/SIZE:
bit_size: 2 bit_size: 2
variants: variants:
- name: Bits8 - name: Bits8
description: Byte (8-bit) description: Byte (8-bit)
value: 0 value: 0
- name: Bits16 - name: Bits16
description: Half-word (16-bit) description: Half-word (16-bit)
value: 1 value: 1
- name: Bits32 - name: Bits32
description: Word (32-bit) description: Word (32-bit)
value: 2 value: 2

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---
block/DMAMUX: block/DMAMUX:
description: DMAMUX description: DMAMUX
items: items:
- name: CCR - name: CCR
description: DMAMux - DMA request line multiplexer channel x control register description: DMAMux - DMA request line multiplexer channel x control register
array: array:
len: 16 len: 16
stride: 4 stride: 4
byte_offset: 0 byte_offset: 0
fieldset: CCR fieldset: CCR
- name: CSR - name: CSR
description: DMAMUX request line multiplexer interrupt channel status register description: DMAMUX request line multiplexer interrupt channel status register
byte_offset: 128 byte_offset: 128
access: Read access: Read
fieldset: CSR fieldset: CSR
- name: CFR - name: CFR
description: DMAMUX request line multiplexer interrupt clear flag register description: DMAMUX request line multiplexer interrupt clear flag register
byte_offset: 132 byte_offset: 132
access: Write access: Write
fieldset: CSR fieldset: CSR
- name: RGCR - name: RGCR
description: DMAMux - DMA request generator channel x control register description: DMAMux - DMA request generator channel x control register
array: array:
len: 8 len: 8
stride: 4 stride: 4
byte_offset: 256 byte_offset: 256
fieldset: RGCR fieldset: RGCR
- name: RGSR - name: RGSR
description: DMAMux - DMA request generator status register description: DMAMux - DMA request generator status register
byte_offset: 320 byte_offset: 320
access: Read access: Read
fieldset: RGSR fieldset: RGSR
- name: RGCFR - name: RGCFR
description: DMAMux - DMA request generator clear flag register description: DMAMux - DMA request generator clear flag register
byte_offset: 324 byte_offset: 324
access: Write access: Write
fieldset: RGSR fieldset: RGSR
fieldset/CCR: fieldset/CCR:
description: DMAMux - DMA request line multiplexer channel x control register description: DMAMux - DMA request line multiplexer channel x control register
fields: fields:
- name: DMAREQ_ID - name: DMAREQ_ID
description: Input DMA request line selected description: Input DMA request line selected
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: SOIE - name: SOIE
description: Interrupt enable at synchronization event overrun description: Interrupt enable at synchronization event overrun
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: EGE - name: EGE
description: Event generation enable/disable description: Event generation enable/disable
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: SE - name: SE
description: Synchronous operating mode enable/disable description: Synchronous operating mode enable/disable
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: SPOL - name: SPOL
description: "Synchronization event type selector Defines the synchronization event on the selected synchronization input:" description: 'Synchronization event type selector Defines the synchronization event on the selected synchronization input:'
bit_offset: 17 bit_offset: 17
bit_size: 2 bit_size: 2
enum: POL enum: POL
- name: NBREQ - name: NBREQ
description: "Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." description: 'Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.'
bit_offset: 19 bit_offset: 19
bit_size: 5 bit_size: 5
- name: SYNC_ID - name: SYNC_ID
description: Synchronization input selected description: Synchronization input selected
bit_offset: 24 bit_offset: 24
bit_size: 5 bit_size: 5
fieldset/CSR: fieldset/CSR:
description: DMAMUX request line multiplexer interrupt channel status register description: DMAMUX request line multiplexer interrupt channel status register
fields: fields:
- name: SOF - name: SOF
description: Synchronization overrun event flag description: Synchronization overrun event flag
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 16 len: 16
stride: 1 stride: 1
fieldset/RGCR: fieldset/RGCR:
description: DMAMux - DMA request generator channel x control register description: DMAMux - DMA request generator channel x control register
fields: fields:
- name: SIG_ID - name: SIG_ID
description: DMA request trigger input selected description: DMA request trigger input selected
bit_offset: 0 bit_offset: 0
bit_size: 5 bit_size: 5
- name: OIE - name: OIE
description: Interrupt enable at trigger event overrun description: Interrupt enable at trigger event overrun
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: GE - name: GE
description: DMA request generator channel enable/disable description: DMA request generator channel enable/disable
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: GPOL - name: GPOL
description: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input description: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bit_offset: 17 bit_offset: 17
bit_size: 2 bit_size: 2
enum: POL enum: POL
- name: GNBREQ - name: GNBREQ
description: "Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset." description: 'Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.'
bit_offset: 19 bit_offset: 19
bit_size: 5 bit_size: 5
fieldset/RGSR: fieldset/RGSR:
description: DMAMux - DMA request generator status register description: DMAMux - DMA request generator status register
fields: fields:
- name: OF - name: OF
description: "Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register." description: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 8 len: 8
stride: 1 stride: 1
enum/POL: enum/POL:
bit_size: 2 bit_size: 2
variants: variants:
- name: NoEdge - name: NoEdge
description: "No event, i.e. no synchronization nor detection" description: No event, i.e. no synchronization nor detection
value: 0 value: 0
- name: RisingEdge - name: RisingEdge
description: Rising edge description: Rising edge
value: 1 value: 1
- name: FallingEdge - name: FallingEdge
description: Falling edge description: Falling edge
value: 2 value: 2
- name: BothEdges - name: BothEdges
description: Rising and falling edges description: Rising and falling edges
value: 3 value: 3

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data/registers/exti_c0.yaml
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@ -1,80 +1,79 @@
---
block/EXTI: block/EXTI:
description: External interrupt/event controller description: External interrupt/event controller
items: items:
- name: RTSR - name: RTSR
description: Rising Trigger selection register description: Rising Trigger selection register
array: array:
len: 1 len: 1
stride: 40 stride: 40
byte_offset: 0 byte_offset: 0
fieldset: LINES fieldset: LINES
- name: FTSR - name: FTSR
description: Falling Trigger selection register description: Falling Trigger selection register
array: array:
len: 1 len: 1
stride: 40 stride: 40
byte_offset: 4 byte_offset: 4
fieldset: LINES fieldset: LINES
- name: SWIER - name: SWIER
description: Software interrupt event register description: Software interrupt event register
array: array:
len: 1 len: 1
stride: 40 stride: 40
byte_offset: 8 byte_offset: 8
fieldset: LINES fieldset: LINES
- name: RPR - name: RPR
description: Rising pending register description: Rising pending register
array: array:
len: 1 len: 1
stride: 40 stride: 40
byte_offset: 12 byte_offset: 12
fieldset: LINES fieldset: LINES
- name: FPR - name: FPR
description: Falling pending register description: Falling pending register
array: array:
len: 1 len: 1
stride: 40 stride: 40
byte_offset: 16 byte_offset: 16
fieldset: LINES fieldset: LINES
- name: EXTICR - name: EXTICR
description: Configuration register description: Configuration register
array: array:
len: 4 len: 4
stride: 4 stride: 4
byte_offset: 96 byte_offset: 96
fieldset: EXTICR fieldset: EXTICR
- name: IMR - name: IMR
description: Interrupt mask register description: Interrupt mask register
array: array:
len: 1 len: 1
stride: 16 stride: 16
byte_offset: 128 byte_offset: 128
fieldset: LINES fieldset: LINES
- name: EMR - name: EMR
description: Event mask register description: Event mask register
array: array:
len: 1 len: 1
stride: 16 stride: 16
byte_offset: 132 byte_offset: 132
fieldset: LINES fieldset: LINES
fieldset/EXTICR: fieldset/EXTICR:
description: external interrupt configuration register 1 description: external interrupt configuration register 1
fields: fields:
- name: EXTI - name: EXTI
description: EXTI configuration bits description: EXTI configuration bits
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
array: array:
len: 4 len: 4
stride: 8 stride: 8
fieldset/LINES: fieldset/LINES:
description: "EXTI lines register, 1 bit per line" description: EXTI lines register, 1 bit per line
fields: fields:
- name: LINE - name: LINE
description: EXTI line description: EXTI line
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1

143
data/registers/exti_g0.yaml
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@ -1,80 +1,79 @@
---
block/EXTI: block/EXTI:
description: External interrupt/event controller description: External interrupt/event controller
items: items:
- name: RTSR - name: RTSR
description: Rising Trigger selection register description: Rising Trigger selection register
array: array:
len: 2 len: 2
stride: 40 stride: 40
byte_offset: 0 byte_offset: 0
fieldset: LINES fieldset: LINES
- name: FTSR - name: FTSR
description: Falling Trigger selection register description: Falling Trigger selection register
array: array:
len: 2 len: 2
stride: 40 stride: 40
byte_offset: 4 byte_offset: 4
fieldset: LINES fieldset: LINES
- name: SWIER - name: SWIER
description: Software interrupt event register description: Software interrupt event register
array: array:
len: 2 len: 2
stride: 40 stride: 40
byte_offset: 8 byte_offset: 8
fieldset: LINES fieldset: LINES
- name: RPR - name: RPR
description: Rising pending register description: Rising pending register
array: array:
len: 2 len: 2
stride: 40 stride: 40
byte_offset: 12 byte_offset: 12
fieldset: LINES fieldset: LINES
- name: FPR - name: FPR
description: Falling pending register description: Falling pending register
array: array:
len: 2 len: 2
stride: 40 stride: 40
byte_offset: 16 byte_offset: 16
fieldset: LINES fieldset: LINES
- name: EXTICR - name: EXTICR
description: Configuration register description: Configuration register
array: array:
len: 4 len: 4
stride: 4 stride: 4
byte_offset: 96 byte_offset: 96
fieldset: EXTICR fieldset: EXTICR
- name: IMR - name: IMR
description: Interrupt mask register description: Interrupt mask register
array: array:
len: 2 len: 2
stride: 16 stride: 16
byte_offset: 128 byte_offset: 128
fieldset: LINES fieldset: LINES
- name: EMR - name: EMR
description: Event mask register description: Event mask register
array: array:
len: 2 len: 2
stride: 16 stride: 16
byte_offset: 132 byte_offset: 132
fieldset: LINES fieldset: LINES
fieldset/EXTICR: fieldset/EXTICR:
description: external interrupt configuration register 1 description: external interrupt configuration register 1
fields: fields:
- name: EXTI - name: EXTI
description: EXTI configuration bits description: EXTI configuration bits
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
array: array:
len: 4 len: 4
stride: 8 stride: 8
fieldset/LINES: fieldset/LINES:
description: "EXTI lines register, 1 bit per line" description: EXTI lines register, 1 bit per line
fields: fields:
- name: LINE - name: LINE
description: EXTI line description: EXTI line
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1

243
data/registers/exti_h5.yaml
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@ -1,145 +1,144 @@
---
block/EXTI: block/EXTI:
description: Extended interrupt and event controller description: Extended interrupt and event controller
items: items:
- name: RTSR - name: RTSR
description: rising trigger selection register description: rising trigger selection register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 0 byte_offset: 0
fieldset: LINES fieldset: LINES
- name: FTSR - name: FTSR
description: falling trigger selection register description: falling trigger selection register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 4 byte_offset: 4
fieldset: LINES fieldset: LINES
- name: SWIER - name: SWIER
description: software interrupt event register description: software interrupt event register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 8 byte_offset: 8
fieldset: LINES fieldset: LINES
- name: RPR - name: RPR
description: rising edge pending register description: rising edge pending register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 12 byte_offset: 12
fieldset: LINES fieldset: LINES
- name: FPR - name: FPR
description: falling edge pending register description: falling edge pending register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 16 byte_offset: 16
fieldset: LINES fieldset: LINES
- name: SECCFGR - name: SECCFGR
description: security configuration register description: security configuration register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 20 byte_offset: 20
fieldset: SEC fieldset: SEC
- name: PRIVCFGR - name: PRIVCFGR
description: privilege configuration register description: privilege configuration register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 24 byte_offset: 24
fieldset: PRIV fieldset: PRIV
- name: EXTICR - name: EXTICR
description: external interrupt selection register description: external interrupt selection register
array: array:
len: 4 len: 4
stride: 4 stride: 4
byte_offset: 96 byte_offset: 96
fieldset: EXTI fieldset: EXTI
- name: LOCKR - name: LOCKR
description: lock register description: lock register
byte_offset: 112 byte_offset: 112
fieldset: LOCKR fieldset: LOCKR
- name: IMR - name: IMR
description: CPU wakeup with interrupt mask register description: CPU wakeup with interrupt mask register
array: array:
len: 2 len: 2
stride: 16 stride: 16
byte_offset: 128 byte_offset: 128
fieldset: LINES fieldset: LINES
- name: EMR - name: EMR
description: CPU wakeup with event mask register description: CPU wakeup with event mask register
array: array:
len: 2 len: 2
stride: 16 stride: 16
byte_offset: 132 byte_offset: 132
fieldset: LINES fieldset: LINES
fieldset/EXTI: fieldset/EXTI:
description: EXTI external interrupt selection register description: EXTI external interrupt selection register
fields: fields:
- name: EXTI - name: EXTI
description: "EXTI12 GPIO port selection\r These bits are written by software to select the source input for EXTI12 external interrupt.\r When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded.\r Others: reserved" description: "EXTI12 GPIO port selection\r These bits are written by software to select the source input for EXTI12 external interrupt.\r When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded.\r Others: reserved"
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
array: array:
len: 4 len: 4
stride: 8 stride: 8
fieldset/LINES: fieldset/LINES:
description: "EXTI lines register, 1 bit per line" description: EXTI lines register, 1 bit per line
fields: fields:
- name: LINE - name: LINE
description: EXTI line description: EXTI line
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1
fieldset/LOCKR: fieldset/LOCKR:
description: lock register description: lock register
fields: fields:
- name: LOCK - name: LOCK
description: "Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock \r This bit is written once after reset." description: "Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock \r This bit is written once after reset."
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
fieldset/PRIV: fieldset/PRIV:
description: privilege configuration register description: privilege configuration register
fields: fields:
- name: PRIV - name: PRIV
description: "Security enable on event input x\r When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access.\r When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded." description: "Security enable on event input x\r When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access.\r When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded."
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1
enum: PRIV enum: PRIV
fieldset/SEC: fieldset/SEC:
description: security configuration register description: security configuration register
fields: fields:
- name: SEC - name: SEC
description: "Security enable on event input x\r When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded." description: "Security enable on event input x\r When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded."
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1
enum: SEC enum: SEC
enum/PRIV: enum/PRIV:
bit_size: 1 bit_size: 1
variants: variants:
- name: Unprivileged - name: Unprivileged
description: Event privilege disabled (unprivileged) description: Event privilege disabled (unprivileged)
value: 0 value: 0
- name: Privileged - name: Privileged
description: Event privilege enabled (privileged) description: Event privilege enabled (privileged)
value: 1 value: 1
enum/SEC: enum/SEC:
bit_size: 1 bit_size: 1
variants: variants:
- name: NonSecure - name: NonSecure
description: Event security disabled (non-secure) description: Event security disabled (non-secure)
value: 0 value: 0
- name: Secure - name: Secure
description: Event security enabled (secure) description: Event security enabled (secure)
value: 1 value: 1

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data/registers/exti_h50.yaml
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@ -1,107 +1,106 @@
---
block/EXTI: block/EXTI:
description: Extended interrupt and event controller description: Extended interrupt and event controller
items: items:
- name: RTSR - name: RTSR
description: rising trigger selection register description: rising trigger selection register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 0 byte_offset: 0
fieldset: LINES fieldset: LINES
- name: FTSR - name: FTSR
description: falling trigger selection register description: falling trigger selection register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 4 byte_offset: 4
fieldset: LINES fieldset: LINES
- name: SWIER - name: SWIER
description: software interrupt event register description: software interrupt event register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 8 byte_offset: 8
fieldset: LINES fieldset: LINES
- name: RPR - name: RPR
description: rising edge pending register description: rising edge pending register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 12 byte_offset: 12
fieldset: LINES fieldset: LINES
- name: FPR - name: FPR
description: falling edge pending register description: falling edge pending register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 16 byte_offset: 16
fieldset: LINES fieldset: LINES
- name: PRIVCFGR - name: PRIVCFGR
description: privilege configuration register description: privilege configuration register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 24 byte_offset: 24
fieldset: PRIV fieldset: PRIV
- name: EXTICR - name: EXTICR
description: external interrupt selection register description: external interrupt selection register
array: array:
len: 4 len: 4
stride: 4 stride: 4
byte_offset: 96 byte_offset: 96
fieldset: EXTI fieldset: EXTI
- name: IMR - name: IMR
description: CPU wakeup with interrupt mask register description: CPU wakeup with interrupt mask register
array: array:
len: 2 len: 2
stride: 16 stride: 16
byte_offset: 128 byte_offset: 128
fieldset: LINES fieldset: LINES
- name: EMR - name: EMR
description: CPU wakeup with event mask register description: CPU wakeup with event mask register
array: array:
len: 2 len: 2
stride: 16 stride: 16
byte_offset: 132 byte_offset: 132
fieldset: LINES fieldset: LINES
fieldset/EXTI: fieldset/EXTI:
description: EXTI external interrupt selection register description: EXTI external interrupt selection register
fields: fields:
- name: EXTI - name: EXTI
description: "EXTI12 GPIO port selection\r These bits are written by software to select the source input for EXTI12 external interrupt.\r When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded.\r Others: reserved" description: "EXTI12 GPIO port selection\r These bits are written by software to select the source input for EXTI12 external interrupt.\r When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded.\r Others: reserved"
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
array: array:
len: 4 len: 4
stride: 8 stride: 8
fieldset/LINES: fieldset/LINES:
description: "EXTI lines register, 1 bit per line" description: EXTI lines register, 1 bit per line
fields: fields:
- name: LINE - name: LINE
description: EXTI line description: EXTI line
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1
fieldset/PRIV: fieldset/PRIV:
description: privilege configuration register description: privilege configuration register
fields: fields:
- name: PRIV - name: PRIV
description: "Security enable on event input x\r When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access.\r When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded." description: "Security enable on event input x\r When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access.\r When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded."
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1
enum: PRIV enum: PRIV
enum/PRIV: enum/PRIV:
bit_size: 1 bit_size: 1
variants: variants:
- name: Unprivileged - name: Unprivileged
description: Event privilege disabled (unprivileged) description: Event privilege disabled (unprivileged)
value: 0 value: 0
- name: Privileged - name: Privileged
description: Event privilege enabled (privileged) description: Event privilege enabled (privileged)
value: 1 value: 1

101
data/registers/exti_h7.yaml
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@ -1,56 +1,55 @@
---
block/EXTI: block/EXTI:
description: External interrupt/event controller description: External interrupt/event controller
items: items:
- name: RTSR - name: RTSR
description: Rising Trigger selection register description: Rising Trigger selection register
array: array:
len: 1 len: 1
stride: 0 stride: 0
byte_offset: 0 byte_offset: 0
fieldset: LINES fieldset: LINES
- name: FTSR - name: FTSR
description: Falling Trigger selection register description: Falling Trigger selection register
array: array:
len: 1 len: 1
stride: 0 stride: 0
byte_offset: 4 byte_offset: 4
fieldset: LINES fieldset: LINES
- name: SWIER - name: SWIER
description: Software interrupt event register description: Software interrupt event register
array: array:
len: 1 len: 1
stride: 0 stride: 0
byte_offset: 8 byte_offset: 8
fieldset: LINES fieldset: LINES
- name: IMR - name: IMR
description: Interrupt mask register description: Interrupt mask register
array: array:
len: 1 len: 1
stride: 0 stride: 0
byte_offset: 128 byte_offset: 128
fieldset: LINES fieldset: LINES
- name: EMR - name: EMR
description: Event mask register description: Event mask register
array: array:
len: 1 len: 1
stride: 0 stride: 0
byte_offset: 132 byte_offset: 132
fieldset: LINES fieldset: LINES
- name: PR - name: PR
description: Pending register description: Pending register
array: array:
len: 1 len: 1
stride: 0 stride: 0
byte_offset: 136 byte_offset: 136
fieldset: LINES fieldset: LINES
fieldset/LINES: fieldset/LINES:
description: "EXTI lines register, 1 bit per line" description: EXTI lines register, 1 bit per line
fields: fields:
- name: LINE - name: LINE
description: EXTI line description: EXTI line
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1

215
data/registers/exti_l5.yaml
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@ -1,125 +1,124 @@
---
block/EXTI: block/EXTI:
description: External interrupt/event controller description: External interrupt/event controller
items: items:
- name: RTSR - name: RTSR
description: Rising Trigger selection register description: Rising Trigger selection register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 0 byte_offset: 0
fieldset: LINES fieldset: LINES
- name: FTSR - name: FTSR
description: Falling Trigger selection register description: Falling Trigger selection register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 4 byte_offset: 4
fieldset: LINES fieldset: LINES
- name: SWIER - name: SWIER
description: Software interrupt event register description: Software interrupt event register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 8 byte_offset: 8
fieldset: LINES fieldset: LINES
- name: RPR - name: RPR
description: Rising pending register description: Rising pending register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 12 byte_offset: 12
fieldset: LINES fieldset: LINES
- name: FPR - name: FPR
description: Falling pending register description: Falling pending register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 16 byte_offset: 16
fieldset: LINES fieldset: LINES
- name: SECCFGR - name: SECCFGR
description: Security configuration register description: Security configuration register
array: array:
len: 2 len: 2
stride: 36 stride: 36
byte_offset: 20 byte_offset: 20
fieldset: SECCFGR fieldset: SECCFGR
- name: PRIVCFGR - name: PRIVCFGR
description: Privilege configuration register description: Privilege configuration register
array: array:
len: 2 len: 2
stride: 28 stride: 28
byte_offset: 24 byte_offset: 24
fieldset: PRIVCFGR fieldset: PRIVCFGR
- name: EXTICR - name: EXTICR
description: Configuration register description: Configuration register
array: array:
len: 4 len: 4
stride: 4 stride: 4
byte_offset: 96 byte_offset: 96
fieldset: EXTICR fieldset: EXTICR
- name: LOCKRG - name: LOCKRG
description: EXTI lock register description: EXTI lock register
byte_offset: 112 byte_offset: 112
fieldset: LOCKRG fieldset: LOCKRG
- name: IMR - name: IMR
description: Interrupt mask register description: Interrupt mask register
array: array:
len: 2 len: 2
stride: 16 stride: 16
byte_offset: 128 byte_offset: 128
fieldset: LINES fieldset: LINES
- name: EMR - name: EMR
description: Event mask register description: Event mask register
array: array:
len: 2 len: 2
stride: 16 stride: 16
byte_offset: 132 byte_offset: 132
fieldset: LINES fieldset: LINES
fieldset/EXTICR: fieldset/EXTICR:
description: external interrupt configuration register 1 description: external interrupt configuration register 1
fields: fields:
- name: EXTI - name: EXTI
description: EXTI configuration bits description: EXTI configuration bits
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
array: array:
len: 4 len: 4
stride: 8 stride: 8
fieldset/LINES: fieldset/LINES:
description: "EXTI lines register, 1 bit per line" description: EXTI lines register, 1 bit per line
fields: fields:
- name: LINE - name: LINE
description: EXTI line description: EXTI line
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1
fieldset/LOCKRG: fieldset/LOCKRG:
description: EXTI lock register description: EXTI lock register
fields: fields:
- name: LOCK - name: LOCK
description: LOCK description: LOCK
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
fieldset/PRIVCFGR: fieldset/PRIVCFGR:
description: Privilege configuration register description: Privilege configuration register
fields: fields:
- name: PRIV - name: PRIV
description: Security enable on event input x description: Security enable on event input x
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1
fieldset/SECCFGR: fieldset/SECCFGR:
description: Security configuration register description: Security configuration register
fields: fields:
- name: SEC - name: SEC
description: Security enable on event input x description: Security enable on event input x
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1

215
data/registers/exti_u5.yaml
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@ -1,125 +1,124 @@
---
block/EXTI: block/EXTI:
description: External interrupt/event controller description: External interrupt/event controller
items: items:
- name: RTSR - name: RTSR
description: Rising Trigger selection register description: Rising Trigger selection register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 0 byte_offset: 0
fieldset: LINES fieldset: LINES
- name: FTSR - name: FTSR
description: Falling Trigger selection register description: Falling Trigger selection register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 4 byte_offset: 4
fieldset: LINES fieldset: LINES
- name: SWIER - name: SWIER
description: Software interrupt event register description: Software interrupt event register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 8 byte_offset: 8
fieldset: LINES fieldset: LINES
- name: RPR - name: RPR
description: Rising pending register description: Rising pending register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 12 byte_offset: 12
fieldset: LINES fieldset: LINES
- name: FPR - name: FPR
description: Falling pending register description: Falling pending register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 16 byte_offset: 16
fieldset: LINES fieldset: LINES
- name: SECCFGR - name: SECCFGR
description: Security configuration register description: Security configuration register
array: array:
len: 2 len: 2
stride: 36 stride: 36
byte_offset: 20 byte_offset: 20
fieldset: SECCFGR fieldset: SECCFGR
- name: PRIVCFGR - name: PRIVCFGR
description: Privilege configuration register description: Privilege configuration register
array: array:
len: 2 len: 2
stride: 28 stride: 28
byte_offset: 24 byte_offset: 24
fieldset: PRIVCFGR fieldset: PRIVCFGR
- name: EXTICR - name: EXTICR
description: Configuration register description: Configuration register
array: array:
len: 4 len: 4
stride: 4 stride: 4
byte_offset: 96 byte_offset: 96
fieldset: EXTICR fieldset: EXTICR
- name: LOCKRG - name: LOCKRG
description: EXTI lock register description: EXTI lock register
byte_offset: 112 byte_offset: 112
fieldset: LOCKRG fieldset: LOCKRG
- name: IMR - name: IMR
description: Interrupt mask register description: Interrupt mask register
array: array:
len: 2 len: 2
stride: 16 stride: 16
byte_offset: 128 byte_offset: 128
fieldset: LINES fieldset: LINES
- name: EMR - name: EMR
description: Event mask register description: Event mask register
array: array:
len: 2 len: 2
stride: 16 stride: 16
byte_offset: 132 byte_offset: 132
fieldset: LINES fieldset: LINES
fieldset/EXTICR: fieldset/EXTICR:
description: external interrupt configuration register 1 description: external interrupt configuration register 1
fields: fields:
- name: EXTI - name: EXTI
description: EXTI configuration bits description: EXTI configuration bits
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
array: array:
len: 4 len: 4
stride: 8 stride: 8
fieldset/LINES: fieldset/LINES:
description: "EXTI lines register, 1 bit per line" description: EXTI lines register, 1 bit per line
fields: fields:
- name: LINE - name: LINE
description: EXTI line description: EXTI line
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1
fieldset/LOCKRG: fieldset/LOCKRG:
description: EXTI lock register description: EXTI lock register
fields: fields:
- name: LOCK - name: LOCK
description: LOCK description: LOCK
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
fieldset/PRIVCFGR: fieldset/PRIVCFGR:
description: Privilege configuration register description: Privilege configuration register
fields: fields:
- name: PRIV - name: PRIV
description: Security enable on event input x description: Security enable on event input x
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1
fieldset/SECCFGR: fieldset/SECCFGR:
description: Security configuration register description: Security configuration register
fields: fields:
- name: SEC - name: SEC
description: Security enable on event input x description: Security enable on event input x
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1

101
data/registers/exti_v1.yaml
View File

@ -1,56 +1,55 @@
---
block/EXTI: block/EXTI:
description: External interrupt/event controller description: External interrupt/event controller
items: items:
- name: IMR - name: IMR
description: Interrupt mask register description: Interrupt mask register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 0 byte_offset: 0
fieldset: LINES fieldset: LINES
- name: EMR - name: EMR
description: Interrupt mask register description: Interrupt mask register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 4 byte_offset: 4
fieldset: LINES fieldset: LINES
- name: RTSR - name: RTSR
description: Rising Trigger selection register description: Rising Trigger selection register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 8 byte_offset: 8
fieldset: LINES fieldset: LINES
- name: FTSR - name: FTSR
description: Falling Trigger selection register description: Falling Trigger selection register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 12 byte_offset: 12
fieldset: LINES fieldset: LINES
- name: SWIER - name: SWIER
description: Software interrupt event register description: Software interrupt event register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 16 byte_offset: 16
fieldset: LINES fieldset: LINES
- name: PR - name: PR
description: Pending register description: Pending register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 20 byte_offset: 20
fieldset: LINES fieldset: LINES
fieldset/LINES: fieldset/LINES:
description: "EXTI lines register, 1 bit per line" description: EXTI lines register, 1 bit per line
fields: fields:
- name: LINE - name: LINE
description: EXTI line description: EXTI line
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1

115
data/registers/exti_w.yaml
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@ -1,66 +1,65 @@
---
block/CPU: block/CPU:
description: CPU-specific registers description: CPU-specific registers
items: items:
- name: IMR - name: IMR
description: CPU x interrupt mask register description: CPU x interrupt mask register
array: array:
len: 2 len: 2
stride: 16 stride: 16
byte_offset: 0 byte_offset: 0
fieldset: LINES fieldset: LINES
- name: EMR - name: EMR
description: CPU x event mask register description: CPU x event mask register
array: array:
len: 2 len: 2
stride: 16 stride: 16
byte_offset: 4 byte_offset: 4
fieldset: LINES fieldset: LINES
block/EXTI: block/EXTI:
description: External interrupt/event controller description: External interrupt/event controller
items: items:
- name: RTSR - name: RTSR
description: rising trigger selection register description: rising trigger selection register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 0 byte_offset: 0
fieldset: LINES fieldset: LINES
- name: FTSR - name: FTSR
description: falling trigger selection register description: falling trigger selection register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 4 byte_offset: 4
fieldset: LINES fieldset: LINES
- name: SWIER - name: SWIER
description: software interrupt event register description: software interrupt event register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 8 byte_offset: 8
fieldset: LINES fieldset: LINES
- name: PR - name: PR
description: EXTI pending register description: EXTI pending register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 12 byte_offset: 12
fieldset: LINES fieldset: LINES
- name: CPU - name: CPU
description: CPU specific registers description: CPU specific registers
array: array:
len: 2 len: 2
stride: 64 stride: 64
byte_offset: 128 byte_offset: 128
block: CPU block: CPU
fieldset/LINES: fieldset/LINES:
description: "EXTI lines register, 1 bit per line" description: EXTI lines register, 1 bit per line
fields: fields:
- name: LINE - name: LINE
description: EXTI line description: EXTI line
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1

101
data/registers/exti_wle.yaml
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@ -1,56 +1,55 @@
---
block/EXTI: block/EXTI:
description: External interrupt/event controller description: External interrupt/event controller
items: items:
- name: RTSR - name: RTSR
description: Rising Trigger selection register description: Rising Trigger selection register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 0 byte_offset: 0
fieldset: LINES fieldset: LINES
- name: FTSR - name: FTSR
description: Falling Trigger selection register description: Falling Trigger selection register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 4 byte_offset: 4
fieldset: LINES fieldset: LINES
- name: SWIER - name: SWIER
description: Software interrupt event register description: Software interrupt event register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 8 byte_offset: 8
fieldset: LINES fieldset: LINES
- name: PR - name: PR
description: Pending register description: Pending register
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 12 byte_offset: 12
fieldset: LINES fieldset: LINES
- name: IMR - name: IMR
description: Interrupt mask register description: Interrupt mask register
array: array:
len: 2 len: 2
stride: 16 stride: 16
byte_offset: 128 byte_offset: 128
fieldset: LINES fieldset: LINES
- name: EMR - name: EMR
description: Event mask register description: Event mask register
array: array:
len: 2 len: 2
stride: 16 stride: 16
byte_offset: 132 byte_offset: 132
fieldset: LINES fieldset: LINES
fieldset/LINES: fieldset/LINES:
description: "EXTI lines register, 1 bit per line" description: EXTI lines register, 1 bit per line
fields: fields:
- name: LINE - name: LINE
description: EXTI line description: EXTI line
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1

733
data/registers/flash_c0.yaml
View File

@ -1,424 +1,423 @@
---
block/FLASH: block/FLASH:
description: Flash description: Flash
items: items:
- name: ACR - name: ACR
description: Access control register description: Access control register
byte_offset: 0 byte_offset: 0
fieldset: ACR fieldset: ACR
- name: KEYR - name: KEYR
description: Flash key register description: Flash key register
byte_offset: 8 byte_offset: 8
access: Write access: Write
fieldset: KEYR fieldset: KEYR
- name: OPTKEYR - name: OPTKEYR
description: Option byte key register description: Option byte key register
byte_offset: 12 byte_offset: 12
access: Write access: Write
fieldset: OPTKEYR fieldset: OPTKEYR
- name: SR - name: SR
description: Status register description: Status register
byte_offset: 16 byte_offset: 16
fieldset: SR fieldset: SR
- name: CR - name: CR
description: Flash control register description: Flash control register
byte_offset: 20 byte_offset: 20
fieldset: CR fieldset: CR
- name: OPTR - name: OPTR
description: Flash option register description: Flash option register
byte_offset: 32 byte_offset: 32
fieldset: OPTR fieldset: OPTR
- name: PCROP1ASR - name: PCROP1ASR
description: Flash PCROP zone A Start address register description: Flash PCROP zone A Start address register
byte_offset: 36 byte_offset: 36
access: Read access: Read
fieldset: PCROP1ASR fieldset: PCROP1ASR
- name: PCROP1AER - name: PCROP1AER
description: Flash PCROP zone A End address register description: Flash PCROP zone A End address register
byte_offset: 40 byte_offset: 40
access: Read access: Read
fieldset: PCROP1AER fieldset: PCROP1AER
- name: WRP1AR - name: WRP1AR
description: Flash WRP area A address register description: Flash WRP area A address register
byte_offset: 44 byte_offset: 44
access: Read access: Read
fieldset: WRP1AR fieldset: WRP1AR
- name: WRP1BR - name: WRP1BR
description: Flash WRP area B address register description: Flash WRP area B address register
byte_offset: 48 byte_offset: 48
access: Read access: Read
fieldset: WRP1BR fieldset: WRP1BR
- name: PCROP1BSR - name: PCROP1BSR
description: Flash PCROP zone B Start address register description: Flash PCROP zone B Start address register
byte_offset: 52 byte_offset: 52
access: Read access: Read
fieldset: PCROP1BSR fieldset: PCROP1BSR
- name: PCROP1BER - name: PCROP1BER
description: Flash PCROP zone B End address register description: Flash PCROP zone B End address register
byte_offset: 56 byte_offset: 56
access: Read access: Read
fieldset: PCROP1BER fieldset: PCROP1BER
- name: SECR - name: SECR
description: Flash Security register description: Flash Security register
byte_offset: 128 byte_offset: 128
access: Read access: Read
fieldset: SECR fieldset: SECR
fieldset/ACR: fieldset/ACR:
description: Access control register description: Access control register
fields: fields:
- name: LATENCY - name: LATENCY
description: Latency description: Latency
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
enum: LATENCY enum: LATENCY
- name: PRFTEN - name: PRFTEN
description: Prefetch enable description: Prefetch enable
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: ICEN - name: ICEN
description: Instruction cache enable description: Instruction cache enable
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: ICRST - name: ICRST
description: Instruction cache reset description: Instruction cache reset
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: EMPTY - name: EMPTY
description: Flash User area empty description: Flash User area empty
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: DBG_SWEN - name: DBG_SWEN
description: Debug access software enable description: Debug access software enable
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Flash control register description: Flash control register
fields: fields:
- name: PG - name: PG
description: Programming description: Programming
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: PER - name: PER
description: Page erase description: Page erase
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: MER - name: MER
description: Mass erase description: Mass erase
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: PNB - name: PNB
description: Page number description: Page number
bit_offset: 3 bit_offset: 3
bit_size: 4 bit_size: 4
- name: STRT - name: STRT
description: Start description: Start
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: OPTSTRT - name: OPTSTRT
description: Options modification start description: Options modification start
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: FSTPG - name: FSTPG
description: Fast programming description: Fast programming
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
- name: EOPIE - name: EOPIE
description: End of operation interrupt enable description: End of operation interrupt enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: ERRIE - name: ERRIE
description: Error interrupt enable description: Error interrupt enable
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: RDERRIE - name: RDERRIE
description: PCROP read error interrupt enable description: PCROP read error interrupt enable
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
- name: OBL_LAUNCH - name: OBL_LAUNCH
description: Force the option byte loading description: Force the option byte loading
bit_offset: 27 bit_offset: 27
bit_size: 1 bit_size: 1
- name: SEC_PROT - name: SEC_PROT
description: Securable memory area protection enable description: Securable memory area protection enable
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
- name: OPTLOCK - name: OPTLOCK
description: Options Lock description: Options Lock
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
- name: LOCK - name: LOCK
description: FLASH_CR Lock description: FLASH_CR Lock
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/KEYR: fieldset/KEYR:
description: Flash key register description: Flash key register
fields: fields:
- name: KEYR - name: KEYR
description: KEYR description: KEYR
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/OPTKEYR: fieldset/OPTKEYR:
description: Option byte key register description: Option byte key register
fields: fields:
- name: OPTKEYR - name: OPTKEYR
description: Option byte key description: Option byte key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/OPTR: fieldset/OPTR:
description: Flash option register description: Flash option register
fields: fields:
- name: RDP - name: RDP
description: Read protection level description: Read protection level
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
enum: RDP enum: RDP
- name: BOREN - name: BOREN
description: BOR reset Level description: BOR reset Level
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: BORF_LEV - name: BORF_LEV
description: These bits contain the VDD supply level threshold that activates the reset description: These bits contain the VDD supply level threshold that activates the reset
bit_offset: 9 bit_offset: 9
bit_size: 2 bit_size: 2
enum: BORF_LEV enum: BORF_LEV
- name: BORR_LEV - name: BORR_LEV
description: These bits contain the VDD supply level threshold that releases the reset. description: These bits contain the VDD supply level threshold that releases the reset.
bit_offset: 11 bit_offset: 11
bit_size: 2 bit_size: 2
enum: BORR_LEV enum: BORR_LEV
- name: nRST_STOP - name: nRST_STOP
description: nRST_STOP description: nRST_STOP
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: nRST_STDBY - name: nRST_STDBY
description: nRST_STDBY description: nRST_STDBY
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: nRSTS_HDW - name: nRSTS_HDW
description: nRSTS_HDW description: nRSTS_HDW
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: IDWG_SW - name: IDWG_SW
description: Independent watchdog selection description: Independent watchdog selection
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: IWDG_STOP - name: IWDG_STOP
description: Independent watchdog counter freeze in Stop mode description: Independent watchdog counter freeze in Stop mode
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: IWDG_STDBY - name: IWDG_STDBY
description: Independent watchdog counter freeze in Standby mode description: Independent watchdog counter freeze in Standby mode
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
- name: WWDG_SW - name: WWDG_SW
description: Window watchdog selection description: Window watchdog selection
bit_offset: 19 bit_offset: 19
bit_size: 1 bit_size: 1
- name: RAM_PARITY_CHECK - name: RAM_PARITY_CHECK
description: SRAM parity check control description: SRAM parity check control
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: nBOOT_SEL - name: nBOOT_SEL
description: nBOOT_SEL description: nBOOT_SEL
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: nBOOT1 - name: nBOOT1
description: Boot configuration description: Boot configuration
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: nBOOT0 - name: nBOOT0
description: nBOOT0 option bit description: nBOOT0 option bit
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
- name: NRST_MODE - name: NRST_MODE
description: NRST_MODE description: NRST_MODE
bit_offset: 27 bit_offset: 27
bit_size: 2 bit_size: 2
enum: NRST_MODE enum: NRST_MODE
- name: IRHEN - name: IRHEN
description: Internal reset holder enable bit description: Internal reset holder enable bit
bit_offset: 29 bit_offset: 29
bit_size: 1 bit_size: 1
fieldset/PCROP1AER: fieldset/PCROP1AER:
description: Flash PCROP zone A End address register description: Flash PCROP zone A End address register
fields: fields:
- name: PCROP1A_END - name: PCROP1A_END
description: PCROP1A area end offset description: PCROP1A area end offset
bit_offset: 0 bit_offset: 0
bit_size: 6 bit_size: 6
- name: PCROP_RDP - name: PCROP_RDP
description: PCROP area preserved when RDP level decreased description: PCROP area preserved when RDP level decreased
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/PCROP1ASR: fieldset/PCROP1ASR:
description: Flash PCROP zone A Start address register description: Flash PCROP zone A Start address register
fields: fields:
- name: PCROP1A_STRT - name: PCROP1A_STRT
description: PCROP1A area start offset description: PCROP1A area start offset
bit_offset: 0 bit_offset: 0
bit_size: 6 bit_size: 6
fieldset/PCROP1BER: fieldset/PCROP1BER:
description: Flash PCROP zone B End address register description: Flash PCROP zone B End address register
fields: fields:
- name: PCROP1B_END - name: PCROP1B_END
description: PCROP1B area end offset description: PCROP1B area end offset
bit_offset: 0 bit_offset: 0
bit_size: 6 bit_size: 6
fieldset/PCROP1BSR: fieldset/PCROP1BSR:
description: Flash PCROP zone B Start address register description: Flash PCROP zone B Start address register
fields: fields:
- name: PCROP1B_STRT - name: PCROP1B_STRT
description: PCROP1B area start offset description: PCROP1B area start offset
bit_offset: 0 bit_offset: 0
bit_size: 6 bit_size: 6
fieldset/SECR: fieldset/SECR:
description: Flash Security register description: Flash Security register
fields: fields:
- name: SEC_SIZE - name: SEC_SIZE
description: Securable memory area size description: Securable memory area size
bit_offset: 0 bit_offset: 0
bit_size: 5 bit_size: 5
- name: BOOT_LOCK - name: BOOT_LOCK
description: used to force boot from user area description: used to force boot from user area
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
fieldset/SR: fieldset/SR:
description: Status register description: Status register
fields: fields:
- name: EOP - name: EOP
description: End of operation description: End of operation
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: OPERR - name: OPERR
description: Operation error description: Operation error
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: PROGERR - name: PROGERR
description: Programming error description: Programming error
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: WRPERR - name: WRPERR
description: Write protected error description: Write protected error
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: PGAERR - name: PGAERR
description: Programming alignment error description: Programming alignment error
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: SIZERR - name: SIZERR
description: Size error description: Size error
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: PGSERR - name: PGSERR
description: Programming sequence error description: Programming sequence error
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: MISERR - name: MISERR
description: Fast programming data miss error description: Fast programming data miss error
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: FASTERR - name: FASTERR
description: Fast programming error description: Fast programming error
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: RDERR - name: RDERR
description: PCROP read error description: PCROP read error
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: OPTVERR - name: OPTVERR
description: Option and Engineering bits loading validity error description: Option and Engineering bits loading validity error
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: BSY - name: BSY
description: Busy description: Busy
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: CFGBSY - name: CFGBSY
description: Programming or erase configuration busy. description: Programming or erase configuration busy.
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/WRP1AR: fieldset/WRP1AR:
description: Flash WRP area A address register description: Flash WRP area A address register
fields: fields:
- name: WRP1A_STRT - name: WRP1A_STRT
description: WRP area A start offset description: WRP area A start offset
bit_offset: 0 bit_offset: 0
bit_size: 6 bit_size: 6
- name: WRP1A_END - name: WRP1A_END
description: WRP area A end offset description: WRP area A end offset
bit_offset: 16 bit_offset: 16
bit_size: 6 bit_size: 6
fieldset/WRP1BR: fieldset/WRP1BR:
description: Flash WRP area B address register description: Flash WRP area B address register
fields: fields:
- name: WRP1B_STRT - name: WRP1B_STRT
description: WRP area B start offset description: WRP area B start offset
bit_offset: 0 bit_offset: 0
bit_size: 6 bit_size: 6
- name: WRP1B_END - name: WRP1B_END
description: WRP area B end offset description: WRP area B end offset
bit_offset: 16 bit_offset: 16
bit_size: 6 bit_size: 6
enum/BORF_LEV: enum/BORF_LEV:
bit_size: 2 bit_size: 2
variants: variants:
- name: FALLING_0 - name: FALLING_0
description: BOR falling level 1 with threshold around 2.0V description: BOR falling level 1 with threshold around 2.0V
value: 0 value: 0
- name: FALLING_1 - name: FALLING_1
description: BOR falling level 2 with threshold around 2.2V description: BOR falling level 2 with threshold around 2.2V
value: 1 value: 1
- name: FALLING_2 - name: FALLING_2
description: BOR falling level 3 with threshold around 2.5V description: BOR falling level 3 with threshold around 2.5V
value: 2 value: 2
- name: FALLING_3 - name: FALLING_3
description: BOR falling level 4 with threshold around 2.8V description: BOR falling level 4 with threshold around 2.8V
value: 3 value: 3
enum/BORR_LEV: enum/BORR_LEV:
bit_size: 2 bit_size: 2
variants: variants:
- name: RISING_0 - name: RISING_0
description: BOR rising level 1 with threshold around 2.1V description: BOR rising level 1 with threshold around 2.1V
value: 0 value: 0
- name: RISING_1 - name: RISING_1
description: BOR rising level 2 with threshold around 2.3V description: BOR rising level 2 with threshold around 2.3V
value: 1 value: 1
- name: RISING_2 - name: RISING_2
description: BOR rising level 3 with threshold around 2.6V description: BOR rising level 3 with threshold around 2.6V
value: 2 value: 2
- name: RISING_3 - name: RISING_3
description: BOR rising level 4 with threshold around 2.9V description: BOR rising level 4 with threshold around 2.9V
value: 3 value: 3
enum/LATENCY: enum/LATENCY:
bit_size: 3 bit_size: 3
variants: variants:
- name: WS0 - name: WS0
description: Zero wait states description: Zero wait states
value: 0 value: 0
- name: WS1 - name: WS1
description: One wait state description: One wait state
value: 1 value: 1
enum/NRST_MODE: enum/NRST_MODE:
bit_size: 2 bit_size: 2
variants: variants:
- name: INPUT_ONLY - name: INPUT_ONLY
description: Reset pin is in reset input mode only description: Reset pin is in reset input mode only
value: 1 value: 1
- name: GPIO - name: GPIO
description: Reset pin is in GPIO mode only description: Reset pin is in GPIO mode only
value: 2 value: 2
- name: INPUT_OUTPUT - name: INPUT_OUTPUT
description: Reset pin is in resety input and output mode description: Reset pin is in resety input and output mode
value: 3 value: 3
enum/RDP: enum/RDP:
bit_size: 8 bit_size: 8
variants: variants:
- name: LEVEL_0 - name: LEVEL_0
description: Read protection not active description: Read protection not active
value: 170 value: 170
- name: LEVEL_1 - name: LEVEL_1
description: Memories read protection active description: Memories read protection active
value: 187 value: 187
- name: LEVEL_2 - name: LEVEL_2
description: Chip read protection active description: Chip read protection active
value: 204 value: 204

493
data/registers/flash_f0.yaml
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@ -1,304 +1,303 @@
---
block/FLASH: block/FLASH:
description: Flash description: Flash
items: items:
- name: ACR - name: ACR
description: Flash access control register description: Flash access control register
byte_offset: 0 byte_offset: 0
fieldset: ACR fieldset: ACR
- name: KEYR - name: KEYR
description: Flash key register description: Flash key register
byte_offset: 4 byte_offset: 4
access: Write access: Write
fieldset: KEYR fieldset: KEYR
- name: OPTKEYR - name: OPTKEYR
description: Flash option key register description: Flash option key register
byte_offset: 8 byte_offset: 8
access: Write access: Write
fieldset: OPTKEYR fieldset: OPTKEYR
- name: SR - name: SR
description: Flash status register description: Flash status register
byte_offset: 12 byte_offset: 12
fieldset: SR fieldset: SR
- name: CR - name: CR
description: Flash control register description: Flash control register
byte_offset: 16 byte_offset: 16
fieldset: CR fieldset: CR
- name: AR - name: AR
description: Flash address register description: Flash address register
byte_offset: 20 byte_offset: 20
access: Write access: Write
fieldset: AR fieldset: AR
- name: OBR - name: OBR
description: Option byte register description: Option byte register
byte_offset: 28 byte_offset: 28
access: Read access: Read
fieldset: OBR fieldset: OBR
- name: WRPR - name: WRPR
description: Write protection register description: Write protection register
byte_offset: 32 byte_offset: 32
access: Read access: Read
fieldset: WRPR fieldset: WRPR
fieldset/ACR: fieldset/ACR:
description: Flash access control register description: Flash access control register
fields: fields:
- name: LATENCY - name: LATENCY
description: LATENCY description: LATENCY
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
enum: LATENCY enum: LATENCY
- name: PRFTBE - name: PRFTBE
description: Prefetch buffer enable description: Prefetch buffer enable
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: PRFTBS - name: PRFTBS
description: Prefetch buffer status description: Prefetch buffer status
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
fieldset/AR: fieldset/AR:
description: Flash address register description: Flash address register
fields: fields:
- name: FAR - name: FAR
description: Flash address description: Flash address
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/CR: fieldset/CR:
description: Flash control register description: Flash control register
fields: fields:
- name: PG - name: PG
description: Programming description: Programming
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: PER - name: PER
description: Page erase description: Page erase
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: MER - name: MER
description: Mass erase description: Mass erase
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: OPTPG - name: OPTPG
description: Option byte programming description: Option byte programming
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: OPTER - name: OPTER
description: Option byte erase description: Option byte erase
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: STRT - name: STRT
description: Start description: Start
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: LOCK - name: LOCK
description: Lock description: Lock
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: OPTWRE - name: OPTWRE
description: Option bytes write enable description: Option bytes write enable
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: ERRIE - name: ERRIE
description: Error interrupt enable description: Error interrupt enable
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: EOPIE - name: EOPIE
description: End of operation interrupt enable description: End of operation interrupt enable
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: FORCE_OPTLOAD - name: FORCE_OPTLOAD
description: Force option byte loading description: Force option byte loading
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
fieldset/KEYR: fieldset/KEYR:
description: Flash key register description: Flash key register
fields: fields:
- name: FKEYR - name: FKEYR
description: Flash Key description: Flash Key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/OBR: fieldset/OBR:
description: Option byte register description: Option byte register
fields: fields:
- name: OPTERR - name: OPTERR
description: Option byte error description: Option byte error
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: RDPRT - name: RDPRT
description: Read protection level status description: Read protection level status
bit_offset: 1 bit_offset: 1
bit_size: 2 bit_size: 2
enum: RDPRT enum: RDPRT
- name: WDG_SW - name: WDG_SW
description: WDG_SW description: WDG_SW
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
enum: WDG_SW enum: WDG_SW
- name: nRST_STOP - name: nRST_STOP
description: nRST_STOP description: nRST_STOP
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
enum: nRST_STOP enum: nRST_STOP
- name: nRST_STDBY - name: nRST_STDBY
description: nRST_STDBY description: nRST_STDBY
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
enum: nRST_STDBY enum: nRST_STDBY
- name: nBOOT0 - name: nBOOT0
description: nBOOT0 description: nBOOT0
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
enum: nBOOT0 enum: nBOOT0
- name: nBOOT1 - name: nBOOT1
description: BOOT1 description: BOOT1
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
enum: nBOOT1 enum: nBOOT1
- name: VDDA_MONITOR - name: VDDA_MONITOR
description: VDDA_MONITOR description: VDDA_MONITOR
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
enum: VDDA_MONITOR enum: VDDA_MONITOR
- name: RAM_PARITY_CHECK - name: RAM_PARITY_CHECK
description: RAM_PARITY_CHECK description: RAM_PARITY_CHECK
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
enum: RAM_PARITY_CHECK enum: RAM_PARITY_CHECK
- name: BOOT_SEL - name: BOOT_SEL
description: BOOT_SEL description: BOOT_SEL
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
enum: BOOT_SEL enum: BOOT_SEL
- name: Data0 - name: Data0
description: Data0 description: Data0
bit_offset: 16 bit_offset: 16
bit_size: 8 bit_size: 8
- name: Data1 - name: Data1
description: Data1 description: Data1
bit_offset: 24 bit_offset: 24
bit_size: 8 bit_size: 8
fieldset/OPTKEYR: fieldset/OPTKEYR:
description: Flash option key register description: Flash option key register
fields: fields:
- name: OPTKEYR - name: OPTKEYR
description: Option byte key description: Option byte key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/SR: fieldset/SR:
description: Flash status register description: Flash status register
fields: fields:
- name: BSY - name: BSY
description: Busy description: Busy
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: PGERR - name: PGERR
description: Programming error description: Programming error
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: WRPRT - name: WRPRT
description: Write protection error description: Write protection error
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: EOP - name: EOP
description: End of operation description: End of operation
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
fieldset/WRPR: fieldset/WRPR:
description: Write protection register description: Write protection register
fields: fields:
- name: WRP - name: WRP
description: Write protect description: Write protect
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
enum/BOOT_SEL: enum/BOOT_SEL:
bit_size: 1 bit_size: 1
variants: variants:
- name: nBOOT0 - name: nBOOT0
description: BOOT0 signal is defined by nBOOT0 option bit description: BOOT0 signal is defined by nBOOT0 option bit
value: 0 value: 0
- name: BOOT0 - name: BOOT0
description: BOOT0 signal is defined by BOOT0 pin value (legacy mode) description: BOOT0 signal is defined by BOOT0 pin value (legacy mode)
value: 1 value: 1
enum/LATENCY: enum/LATENCY:
bit_size: 3 bit_size: 3
variants: variants:
- name: WS0 - name: WS0
description: 0 wait states description: 0 wait states
value: 0 value: 0
- name: WS1 - name: WS1
description: 1 wait state description: 1 wait state
value: 1 value: 1
enum/RAM_PARITY_CHECK: enum/RAM_PARITY_CHECK:
bit_size: 1 bit_size: 1
variants: variants:
- name: Enabled - name: Enabled
description: RAM parity check enabled description: RAM parity check enabled
value: 0 value: 0
- name: Disabled - name: Disabled
description: RAM parity check disabled description: RAM parity check disabled
value: 1 value: 1
enum/RDPRT: enum/RDPRT:
bit_size: 2 bit_size: 2
variants: variants:
- name: Level0 - name: Level0
description: Level 0 description: Level 0
value: 0 value: 0
- name: Level1 - name: Level1
description: Level 1 description: Level 1
value: 1 value: 1
- name: Level2 - name: Level2
description: Level 2 description: Level 2
value: 3 value: 3
enum/VDDA_MONITOR: enum/VDDA_MONITOR:
bit_size: 1 bit_size: 1
variants: variants:
- name: Disabled - name: Disabled
description: VDDA power supply supervisor disabled description: VDDA power supply supervisor disabled
value: 0 value: 0
- name: Enabled - name: Enabled
description: VDDA power supply supervisor enabled description: VDDA power supply supervisor enabled
value: 1 value: 1
enum/WDG_SW: enum/WDG_SW:
bit_size: 1 bit_size: 1
variants: variants:
- name: Hardware - name: Hardware
description: Hardware watchdog description: Hardware watchdog
value: 0 value: 0
- name: Software - name: Software
description: Software watchdog description: Software watchdog
value: 1 value: 1
enum/nBOOT0: enum/nBOOT0:
bit_size: 1 bit_size: 1
variants: variants:
- name: Disabled - name: Disabled
description: "When BOOT_SEL is cleared, select the device boot mode" description: When BOOT_SEL is cleared, select the device boot mode
value: 0 value: 0
- name: Enabled - name: Enabled
description: "When BOOT_SEL is cleared, select the device boot mode" description: When BOOT_SEL is cleared, select the device boot mode
value: 1 value: 1
enum/nBOOT1: enum/nBOOT1:
bit_size: 1 bit_size: 1
variants: variants:
- name: Disabled - name: Disabled
description: "Together with BOOT0, select the device boot mode" description: Together with BOOT0, select the device boot mode
value: 0 value: 0
- name: Enabled - name: Enabled
description: "Together with BOOT0, select the device boot mode" description: Together with BOOT0, select the device boot mode
value: 1 value: 1
enum/nRST_STDBY: enum/nRST_STDBY:
bit_size: 1 bit_size: 1
variants: variants:
- name: Reset - name: Reset
description: Reset generated when entering Standby mode description: Reset generated when entering Standby mode
value: 0 value: 0
- name: NoReset - name: NoReset
description: No reset generated description: No reset generated
value: 1 value: 1
enum/nRST_STOP: enum/nRST_STOP:
bit_size: 1 bit_size: 1
variants: variants:
- name: Reset - name: Reset
description: Reset generated when entering Stop mode description: Reset generated when entering Stop mode
value: 0 value: 0
- name: NoReset - name: NoReset
description: No reset generated description: No reset generated
value: 1 value: 1

327
data/registers/flash_f1.yaml
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@ -1,194 +1,193 @@
---
block/FLASH: block/FLASH:
description: FLASH description: FLASH
items: items:
- name: ACR - name: ACR
description: Flash access control register description: Flash access control register
byte_offset: 0 byte_offset: 0
fieldset: ACR fieldset: ACR
- name: KEYR - name: KEYR
description: Flash key register description: Flash key register
byte_offset: 4 byte_offset: 4
access: Write access: Write
fieldset: KEYR fieldset: KEYR
- name: OPTKEYR - name: OPTKEYR
description: Flash option key register description: Flash option key register
byte_offset: 8 byte_offset: 8
access: Write access: Write
fieldset: OPTKEYR fieldset: OPTKEYR
- name: SR - name: SR
description: Status register description: Status register
byte_offset: 12 byte_offset: 12
fieldset: SR fieldset: SR
- name: CR - name: CR
description: Control register description: Control register
byte_offset: 16 byte_offset: 16
fieldset: CR fieldset: CR
- name: AR - name: AR
description: Flash address register description: Flash address register
byte_offset: 20 byte_offset: 20
access: Write access: Write
fieldset: AR fieldset: AR
- name: OBR - name: OBR
description: Option byte register description: Option byte register
byte_offset: 28 byte_offset: 28
access: Read access: Read
fieldset: OBR fieldset: OBR
- name: WRPR - name: WRPR
description: Write protection register description: Write protection register
byte_offset: 32 byte_offset: 32
access: Read access: Read
fieldset: WRPR fieldset: WRPR
fieldset/ACR: fieldset/ACR:
description: Flash access control register description: Flash access control register
fields: fields:
- name: LATENCY - name: LATENCY
description: Latency description: Latency
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
enum: LATENCY enum: LATENCY
- name: HLFCYA - name: HLFCYA
description: Flash half cycle access enable description: Flash half cycle access enable
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: PRFTBE - name: PRFTBE
description: Prefetch buffer enable description: Prefetch buffer enable
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: PRFTBS - name: PRFTBS
description: Prefetch buffer status description: Prefetch buffer status
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
fieldset/AR: fieldset/AR:
description: Flash address register description: Flash address register
fields: fields:
- name: FAR - name: FAR
description: Flash Address description: Flash Address
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/CR: fieldset/CR:
description: Control register description: Control register
fields: fields:
- name: PG - name: PG
description: Programming description: Programming
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: PER - name: PER
description: Page Erase description: Page Erase
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: MER - name: MER
description: Mass Erase description: Mass Erase
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: OPTPG - name: OPTPG
description: Option byte programming description: Option byte programming
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: OPTER - name: OPTER
description: Option byte erase description: Option byte erase
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: STRT - name: STRT
description: Start description: Start
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: LOCK - name: LOCK
description: Lock description: Lock
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: OPTWRE - name: OPTWRE
description: Option bytes write enable description: Option bytes write enable
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: ERRIE - name: ERRIE
description: Error interrupt enable description: Error interrupt enable
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: EOPIE - name: EOPIE
description: End of operation interrupt enable description: End of operation interrupt enable
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
fieldset/KEYR: fieldset/KEYR:
description: Flash key register description: Flash key register
fields: fields:
- name: KEY - name: KEY
description: FPEC key description: FPEC key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/OBR: fieldset/OBR:
description: Option byte register description: Option byte register
fields: fields:
- name: OPTERR - name: OPTERR
description: Option byte error description: Option byte error
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: RDPRT - name: RDPRT
description: Read protection description: Read protection
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: WDG_SW - name: WDG_SW
description: WDG_SW description: WDG_SW
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: nRST_STOP - name: nRST_STOP
description: nRST_STOP description: nRST_STOP
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: nRST_STDBY - name: nRST_STDBY
description: nRST_STDBY description: nRST_STDBY
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: Data0 - name: Data0
description: Data0 description: Data0
bit_offset: 10 bit_offset: 10
bit_size: 8 bit_size: 8
- name: Data1 - name: Data1
description: Data1 description: Data1
bit_offset: 18 bit_offset: 18
bit_size: 8 bit_size: 8
fieldset/OPTKEYR: fieldset/OPTKEYR:
description: Flash option key register description: Flash option key register
fields: fields:
- name: OPTKEY - name: OPTKEY
description: Option byte key description: Option byte key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/SR: fieldset/SR:
description: Status register description: Status register
fields: fields:
- name: BSY - name: BSY
description: Busy description: Busy
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: PGERR - name: PGERR
description: Programming error description: Programming error
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: WRPRTERR - name: WRPRTERR
description: Write protection error description: Write protection error
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: EOP - name: EOP
description: End of operation description: End of operation
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
fieldset/WRPR: fieldset/WRPR:
description: Write protection register description: Write protection register
fields: fields:
- name: WRP - name: WRP
description: Write protect description: Write protect
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
enum/LATENCY: enum/LATENCY:
bit_size: 3 bit_size: 3
variants: variants:
- name: WS0 - name: WS0
description: "Zero wait state, if 0 < SYSCLK≤ 24 MHz" description: Zero wait state, if 0 < SYSCLK≤ 24 MHz
value: 0 value: 0
- name: WS1 - name: WS1
description: "One wait state, if 24 MHz < SYSCLK ≤ 48 MHz" description: One wait state, if 24 MHz < SYSCLK ≤ 48 MHz
value: 1 value: 1
- name: WS2 - name: WS2
description: "Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz" description: Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz
value: 2 value: 2

385
data/registers/flash_f2.yaml
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@ -1,220 +1,219 @@
---
block/FLASH: block/FLASH:
description: FLASH description: FLASH
items: items:
- name: ACR - name: ACR
description: Flash access control register description: Flash access control register
byte_offset: 0 byte_offset: 0
fieldset: ACR fieldset: ACR
- name: KEYR - name: KEYR
description: Flash key register description: Flash key register
byte_offset: 4 byte_offset: 4
access: Write access: Write
fieldset: KEYR fieldset: KEYR
- name: OPTKEYR - name: OPTKEYR
description: Flash option key register description: Flash option key register
byte_offset: 8 byte_offset: 8
access: Write access: Write
fieldset: OPTKEYR fieldset: OPTKEYR
- name: SR - name: SR
description: Status register description: Status register
byte_offset: 12 byte_offset: 12
fieldset: SR fieldset: SR
- name: CR - name: CR
description: Control register description: Control register
byte_offset: 16 byte_offset: 16
fieldset: CR fieldset: CR
- name: OPTCR - name: OPTCR
description: Flash option control register description: Flash option control register
byte_offset: 20 byte_offset: 20
fieldset: OPTCR fieldset: OPTCR
fieldset/ACR: fieldset/ACR:
description: Flash access control register description: Flash access control register
fields: fields:
- name: LATENCY - name: LATENCY
description: Latency description: Latency
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
enum: LATENCY enum: LATENCY
- name: PRFTEN - name: PRFTEN
description: Prefetch enable description: Prefetch enable
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: ICEN - name: ICEN
description: Instruction cache enable description: Instruction cache enable
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: DCEN - name: DCEN
description: Data cache enable description: Data cache enable
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: ICRST - name: ICRST
description: Instruction cache reset description: Instruction cache reset
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: DCRST - name: DCRST
description: Data cache reset description: Data cache reset
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Control register description: Control register
fields: fields:
- name: PG - name: PG
description: Programming description: Programming
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: SER - name: SER
description: Sector Erase description: Sector Erase
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: MER - name: MER
description: Mass Erase description: Mass Erase
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: SNB - name: SNB
description: Sector number description: Sector number
bit_offset: 3 bit_offset: 3
bit_size: 4 bit_size: 4
- name: PSIZE - name: PSIZE
description: Program size description: Program size
bit_offset: 8 bit_offset: 8
bit_size: 2 bit_size: 2
enum: PSIZE enum: PSIZE
- name: STRT - name: STRT
description: Start description: Start
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: EOPIE - name: EOPIE
description: End of operation interrupt enable description: End of operation interrupt enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: ERRIE - name: ERRIE
description: Error interrupt enable description: Error interrupt enable
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: LOCK - name: LOCK
description: Lock description: Lock
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/KEYR: fieldset/KEYR:
description: Flash key register description: Flash key register
fields: fields:
- name: KEY - name: KEY
description: FPEC key description: FPEC key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/OPTCR: fieldset/OPTCR:
description: Flash option control register description: Flash option control register
fields: fields:
- name: OPTLOCK - name: OPTLOCK
description: Option lock description: Option lock
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: OPTSTRT - name: OPTSTRT
description: Option start description: Option start
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: BOR_LEV - name: BOR_LEV
description: BOR reset Level description: BOR reset Level
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
- name: WDG_SW - name: WDG_SW
description: WDG_SW User option bytes description: WDG_SW User option bytes
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: nRST_STOP - name: nRST_STOP
description: nRST_STOP User option bytes description: nRST_STOP User option bytes
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: nRST_STDBY - name: nRST_STDBY
description: nRST_STDBY User option bytes description: nRST_STDBY User option bytes
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: RDP - name: RDP
description: Read protect description: Read protect
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
- name: nWRP - name: nWRP
description: Not write protect description: Not write protect
bit_offset: 16 bit_offset: 16
bit_size: 12 bit_size: 12
fieldset/OPTKEYR: fieldset/OPTKEYR:
description: Flash option key register description: Flash option key register
fields: fields:
- name: OPTKEY - name: OPTKEY
description: Option byte key description: Option byte key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/SR: fieldset/SR:
description: Status register description: Status register
fields: fields:
- name: EOP - name: EOP
description: End of operation description: End of operation
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: OPERR - name: OPERR
description: Operation error description: Operation error
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: WRPERR - name: WRPERR
description: Write protection error description: Write protection error
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: PGAERR - name: PGAERR
description: Programming alignment error description: Programming alignment error
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: PGPERR - name: PGPERR
description: Programming parallelism error description: Programming parallelism error
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: PGSERR - name: PGSERR
description: Programming sequence error description: Programming sequence error
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: BSY - name: BSY
description: Busy description: Busy
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum/LATENCY: enum/LATENCY:
bit_size: 3 bit_size: 3
variants: variants:
- name: WS0 - name: WS0
description: 0 wait states description: 0 wait states
value: 0 value: 0
- name: WS1 - name: WS1
description: 1 wait states description: 1 wait states
value: 1 value: 1
- name: WS2 - name: WS2
description: 2 wait states description: 2 wait states
value: 2 value: 2
- name: WS3 - name: WS3
description: 3 wait states description: 3 wait states
value: 3 value: 3
- name: WS4 - name: WS4
description: 4 wait states description: 4 wait states
value: 4 value: 4
- name: WS5 - name: WS5
description: 5 wait states description: 5 wait states
value: 5 value: 5
- name: WS6 - name: WS6
description: 6 wait states description: 6 wait states
value: 6 value: 6
- name: WS7 - name: WS7
description: 7 wait states description: 7 wait states
value: 7 value: 7
enum/PSIZE: enum/PSIZE:
bit_size: 2 bit_size: 2
variants: variants:
- name: PSIZE8 - name: PSIZE8
description: Program x8 description: Program x8
value: 0 value: 0
- name: PSIZE16 - name: PSIZE16
description: Program x16 description: Program x16
value: 1 value: 1
- name: PSIZE32 - name: PSIZE32
description: Program x32 description: Program x32
value: 2 value: 2
- name: PSIZE64 - name: PSIZE64
description: Program x64 description: Program x64
value: 3 value: 3

429
data/registers/flash_f3.yaml
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@ -1,257 +1,256 @@
---
block/FLASH: block/FLASH:
description: Flash description: Flash
items: items:
- name: ACR - name: ACR
description: Flash access control register description: Flash access control register
byte_offset: 0 byte_offset: 0
fieldset: ACR fieldset: ACR
- name: KEYR - name: KEYR
description: Flash key register description: Flash key register
byte_offset: 4 byte_offset: 4
access: Write access: Write
fieldset: KEYR fieldset: KEYR
- name: OPTKEYR - name: OPTKEYR
description: Flash option key register description: Flash option key register
byte_offset: 8 byte_offset: 8
access: Write access: Write
fieldset: OPTKEYR fieldset: OPTKEYR
- name: SR - name: SR
description: Flash status register description: Flash status register
byte_offset: 12 byte_offset: 12
fieldset: SR fieldset: SR
- name: CR - name: CR
description: Flash control register description: Flash control register
byte_offset: 16 byte_offset: 16
fieldset: CR fieldset: CR
- name: AR - name: AR
description: Flash address register description: Flash address register
byte_offset: 20 byte_offset: 20
access: Write access: Write
fieldset: AR fieldset: AR
- name: OBR - name: OBR
description: Option byte register description: Option byte register
byte_offset: 28 byte_offset: 28
access: Read access: Read
fieldset: OBR fieldset: OBR
- name: WRPR - name: WRPR
description: Write protection register description: Write protection register
byte_offset: 32 byte_offset: 32
access: Read access: Read
fieldset: WRPR fieldset: WRPR
fieldset/ACR: fieldset/ACR:
description: Flash access control register description: Flash access control register
fields: fields:
- name: LATENCY - name: LATENCY
description: LATENCY description: LATENCY
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
enum: LATENCY enum: LATENCY
- name: HLFCYA - name: HLFCYA
description: Flash half cycle access enable description: Flash half cycle access enable
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: PRFTBE - name: PRFTBE
description: PRFTBE description: PRFTBE
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: PRFTBS - name: PRFTBS
description: PRFTBS description: PRFTBS
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
fieldset/AR: fieldset/AR:
description: Flash address register description: Flash address register
fields: fields:
- name: FAR - name: FAR
description: Flash address description: Flash address
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/CR: fieldset/CR:
description: Flash control register description: Flash control register
fields: fields:
- name: PG - name: PG
description: Programming description: Programming
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: PER - name: PER
description: Page erase description: Page erase
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: MER - name: MER
description: Mass erase description: Mass erase
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: OPTPG - name: OPTPG
description: Option byte programming description: Option byte programming
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: OPTER - name: OPTER
description: Option byte erase description: Option byte erase
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: STRT - name: STRT
description: Start description: Start
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: LOCK - name: LOCK
description: Lock description: Lock
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: OPTWRE - name: OPTWRE
description: Option bytes write enable description: Option bytes write enable
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: ERRIE - name: ERRIE
description: Error interrupt enable description: Error interrupt enable
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: EOPIE - name: EOPIE
description: End of operation interrupt enable description: End of operation interrupt enable
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: OBL_LAUNCH - name: OBL_LAUNCH
description: Force option byte loading description: Force option byte loading
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
fieldset/KEYR: fieldset/KEYR:
description: Flash key register description: Flash key register
fields: fields:
- name: FKEYR - name: FKEYR
description: Flash Key description: Flash Key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/OBR: fieldset/OBR:
description: Option byte register description: Option byte register
fields: fields:
- name: OPTERR - name: OPTERR
description: Option byte error description: Option byte error
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: RDPRT - name: RDPRT
description: Read protection Level status description: Read protection Level status
bit_offset: 1 bit_offset: 1
bit_size: 2 bit_size: 2
enum: RDPRT enum: RDPRT
- name: WDG_SW - name: WDG_SW
description: WDG_SW description: WDG_SW
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
enum: WDG_SW enum: WDG_SW
- name: nRST_STOP - name: nRST_STOP
description: nRST_STOP description: nRST_STOP
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
enum: nRST_STOP enum: nRST_STOP
- name: nRST_STDBY - name: nRST_STDBY
description: nRST_STDBY description: nRST_STDBY
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
enum: nRST_STDBY enum: nRST_STDBY
- name: nBOOT1 - name: nBOOT1
description: BOOT1 description: BOOT1
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: VDDA_MONITOR - name: VDDA_MONITOR
description: VDDA_MONITOR description: VDDA_MONITOR
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: SRAM_PARITY_CHECK - name: SRAM_PARITY_CHECK
description: SRAM_PARITY_CHECK description: SRAM_PARITY_CHECK
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: SDADC12_VDD_MONITOR - name: SDADC12_VDD_MONITOR
description: SDADC12_VDD_MONITOR description: SDADC12_VDD_MONITOR
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: Data0 - name: Data0
description: Data0 description: Data0
bit_offset: 16 bit_offset: 16
bit_size: 8 bit_size: 8
- name: Data1 - name: Data1
description: Data1 description: Data1
bit_offset: 24 bit_offset: 24
bit_size: 8 bit_size: 8
fieldset/OPTKEYR: fieldset/OPTKEYR:
description: Flash option key register description: Flash option key register
fields: fields:
- name: OPTKEYR - name: OPTKEYR
description: Option byte key description: Option byte key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/SR: fieldset/SR:
description: Flash status register description: Flash status register
fields: fields:
- name: BSY - name: BSY
description: Busy description: Busy
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: PGERR - name: PGERR
description: Programming error description: Programming error
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: WRPRTERR - name: WRPRTERR
description: Write protection error description: Write protection error
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: EOP - name: EOP
description: End of operation description: End of operation
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
fieldset/WRPR: fieldset/WRPR:
description: Write protection register description: Write protection register
fields: fields:
- name: WRP - name: WRP
description: Write protect description: Write protect
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
enum/LATENCY: enum/LATENCY:
bit_size: 3 bit_size: 3
variants: variants:
- name: WS0 - name: WS0
description: "0 wait states, if 0 < HCLK <= 24 MHz" description: 0 wait states, if 0 < HCLK <= 24 MHz
value: 0 value: 0
- name: WS1 - name: WS1
description: "1 wait state, if 24 < HCLK <= 48 MHz" description: 1 wait state, if 24 < HCLK <= 48 MHz
value: 1 value: 1
- name: WS2 - name: WS2
description: "2 wait states, if 48 < HCLK <= 72 MHz" description: 2 wait states, if 48 < HCLK <= 72 MHz
value: 2 value: 2
enum/RDPRT: enum/RDPRT:
bit_size: 2 bit_size: 2
variants: variants:
- name: Level0 - name: Level0
description: Level 0 description: Level 0
value: 0 value: 0
- name: Level1 - name: Level1
description: Level 1 description: Level 1
value: 1 value: 1
- name: Level2 - name: Level2
description: Level 2 description: Level 2
value: 3 value: 3
enum/WDG_SW: enum/WDG_SW:
bit_size: 1 bit_size: 1
variants: variants:
- name: Hardware - name: Hardware
description: Hardware watchdog description: Hardware watchdog
value: 0 value: 0
- name: Software - name: Software
description: Software watchdog description: Software watchdog
value: 1 value: 1
enum/nRST_STDBY: enum/nRST_STDBY:
bit_size: 1 bit_size: 1
variants: variants:
- name: Reset - name: Reset
description: Reset generated when entering Standby mode description: Reset generated when entering Standby mode
value: 0 value: 0
- name: NoReset - name: NoReset
description: No reset generated description: No reset generated
value: 1 value: 1
enum/nRST_STOP: enum/nRST_STOP:
bit_size: 1 bit_size: 1
variants: variants:
- name: Reset - name: Reset
description: Reset generated when entering Stop mode description: Reset generated when entering Stop mode
value: 0 value: 0
- name: NoReset - name: NoReset
description: No reset generated description: No reset generated
value: 1 value: 1

449
data/registers/flash_f4.yaml
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@ -1,252 +1,251 @@
---
block/FLASH: block/FLASH:
description: FLASH description: FLASH
items: items:
- name: ACR - name: ACR
description: Flash access control register description: Flash access control register
byte_offset: 0 byte_offset: 0
fieldset: ACR fieldset: ACR
- name: KEYR - name: KEYR
description: Flash key register description: Flash key register
byte_offset: 4 byte_offset: 4
access: Write access: Write
fieldset: KEYR fieldset: KEYR
- name: OPTKEYR - name: OPTKEYR
description: Flash option key register description: Flash option key register
byte_offset: 8 byte_offset: 8
access: Write access: Write
fieldset: OPTKEYR fieldset: OPTKEYR
- name: SR - name: SR
description: Status register description: Status register
byte_offset: 12 byte_offset: 12
fieldset: SR fieldset: SR
- name: CR - name: CR
description: Control register description: Control register
byte_offset: 16 byte_offset: 16
fieldset: CR fieldset: CR
- name: OPTCR - name: OPTCR
description: Flash option control register description: Flash option control register
byte_offset: 20 byte_offset: 20
fieldset: OPTCR fieldset: OPTCR
fieldset/ACR: fieldset/ACR:
description: Flash access control register description: Flash access control register
fields: fields:
- name: LATENCY - name: LATENCY
description: Latency description: Latency
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
enum: LATENCY enum: LATENCY
- name: PRFTEN - name: PRFTEN
description: Prefetch enable description: Prefetch enable
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: ICEN - name: ICEN
description: Instruction cache enable description: Instruction cache enable
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: DCEN - name: DCEN
description: Data cache enable description: Data cache enable
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: ICRST - name: ICRST
description: Instruction cache reset description: Instruction cache reset
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: DCRST - name: DCRST
description: Data cache reset description: Data cache reset
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Control register description: Control register
fields: fields:
- name: PG - name: PG
description: Programming description: Programming
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: SER - name: SER
description: Sector Erase description: Sector Erase
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: MER - name: MER
description: Mass Erase description: Mass Erase
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: SNB - name: SNB
description: Sector number description: Sector number
bit_offset: 3 bit_offset: 3
bit_size: 5 bit_size: 5
- name: PSIZE - name: PSIZE
description: Program size description: Program size
bit_offset: 8 bit_offset: 8
bit_size: 2 bit_size: 2
enum: PSIZE enum: PSIZE
- name: STRT - name: STRT
description: Start description: Start
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: EOPIE - name: EOPIE
description: End of operation interrupt enable description: End of operation interrupt enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: ERRIE - name: ERRIE
description: Error interrupt enable description: Error interrupt enable
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: LOCK - name: LOCK
description: Lock description: Lock
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/KEYR: fieldset/KEYR:
description: Flash key register description: Flash key register
fields: fields:
- name: KEY - name: KEY
description: FPEC key description: FPEC key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/OPTCR: fieldset/OPTCR:
description: Flash option control register description: Flash option control register
fields: fields:
- name: OPTLOCK - name: OPTLOCK
description: Option lock description: Option lock
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: OPTSTRT - name: OPTSTRT
description: Option start description: Option start
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: BOR_LEV - name: BOR_LEV
description: BOR reset Level description: BOR reset Level
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
- name: WDG_SW - name: WDG_SW
description: WDG_SW User option bytes description: WDG_SW User option bytes
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: nRST_STOP - name: nRST_STOP
description: nRST_STOP User option bytes description: nRST_STOP User option bytes
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: nRST_STDBY - name: nRST_STDBY
description: nRST_STDBY User option bytes description: nRST_STDBY User option bytes
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: RDP - name: RDP
description: Read protect description: Read protect
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
- name: nWRP - name: nWRP
description: Not write protect description: Not write protect
bit_offset: 16 bit_offset: 16
bit_size: 12 bit_size: 12
- name: DB1M - name: DB1M
description: Dual-bank enable on 1 Mbyte Flash memory devices description: Dual-bank enable on 1 Mbyte Flash memory devices
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
- name: SPRMOD - name: SPRMOD
description: Selection of protection mode for nWPRi bits description: Selection of protection mode for nWPRi bits
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/OPTKEYR: fieldset/OPTKEYR:
description: Flash option key register description: Flash option key register
fields: fields:
- name: OPTKEY - name: OPTKEY
description: Option byte key description: Option byte key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/SR: fieldset/SR:
description: Status register description: Status register
fields: fields:
- name: EOP - name: EOP
description: End of operation description: End of operation
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: OPERR - name: OPERR
description: Operation error description: Operation error
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: WRPERR - name: WRPERR
description: Write protection error description: Write protection error
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: PGAERR - name: PGAERR
description: Programming alignment error description: Programming alignment error
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: PGPERR - name: PGPERR
description: Programming parallelism error description: Programming parallelism error
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: PGSERR - name: PGSERR
description: Programming sequence error description: Programming sequence error
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: BSY - name: BSY
description: Busy description: Busy
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum/LATENCY: enum/LATENCY:
bit_size: 3 bit_size: 3
variants: variants:
- name: WS0 - name: WS0
description: 0 wait states description: 0 wait states
value: 0 value: 0
- name: WS1 - name: WS1
description: 1 wait states description: 1 wait states
value: 1 value: 1
- name: WS2 - name: WS2
description: 2 wait states description: 2 wait states
value: 2 value: 2
- name: WS3 - name: WS3
description: 3 wait states description: 3 wait states
value: 3 value: 3
- name: WS4 - name: WS4
description: 4 wait states description: 4 wait states
value: 4 value: 4
- name: WS5 - name: WS5
description: 5 wait states description: 5 wait states
value: 5 value: 5
- name: WS6 - name: WS6
description: 6 wait states description: 6 wait states
value: 6 value: 6
- name: WS7 - name: WS7
description: 7 wait states description: 7 wait states
value: 7 value: 7
- name: WS8 - name: WS8
description: 8 wait states description: 8 wait states
value: 8 value: 8
- name: WS9 - name: WS9
description: 9 wait states description: 9 wait states
value: 9 value: 9
- name: WS10 - name: WS10
description: 10 wait states description: 10 wait states
value: 10 value: 10
- name: WS11 - name: WS11
description: 11 wait states description: 11 wait states
value: 11 value: 11
- name: WS12 - name: WS12
description: 12 wait states description: 12 wait states
value: 12 value: 12
- name: WS13 - name: WS13
description: 13 wait states description: 13 wait states
value: 13 value: 13
- name: WS14 - name: WS14
description: 14 wait states description: 14 wait states
value: 14 value: 14
- name: WS15 - name: WS15
description: 15 wait states description: 15 wait states
value: 15 value: 15
enum/PSIZE: enum/PSIZE:
bit_size: 2 bit_size: 2
variants: variants:
- name: PSIZE8 - name: PSIZE8
description: Program x8 description: Program x8
value: 0 value: 0
- name: PSIZE16 - name: PSIZE16
description: Program x16 description: Program x16
value: 1 value: 1
- name: PSIZE32 - name: PSIZE32
description: Program x32 description: Program x32
value: 2 value: 2
- name: PSIZE64 - name: PSIZE64
description: Program x64 description: Program x64
value: 3 value: 3

521
data/registers/flash_f7.yaml
View File

@ -1,294 +1,293 @@
---
block/FLASH: block/FLASH:
description: FLASH description: FLASH
items: items:
- name: ACR - name: ACR
description: Flash access control register description: Flash access control register
byte_offset: 0 byte_offset: 0
fieldset: ACR fieldset: ACR
- name: KEYR - name: KEYR
description: Flash key register description: Flash key register
byte_offset: 4 byte_offset: 4
access: Write access: Write
fieldset: KEYR fieldset: KEYR
- name: OPTKEYR - name: OPTKEYR
description: Flash option key register description: Flash option key register
byte_offset: 8 byte_offset: 8
access: Write access: Write
fieldset: OPTKEYR fieldset: OPTKEYR
- name: SR - name: SR
description: Status register description: Status register
byte_offset: 12 byte_offset: 12
fieldset: SR fieldset: SR
- name: CR - name: CR
description: Control register description: Control register
byte_offset: 16 byte_offset: 16
fieldset: CR fieldset: CR
- name: OPTCR - name: OPTCR
description: Flash option control register description: Flash option control register
byte_offset: 20 byte_offset: 20
fieldset: OPTCR fieldset: OPTCR
- name: OPTCR1 - name: OPTCR1
description: Flash option control register 1 description: Flash option control register 1
byte_offset: 24 byte_offset: 24
fieldset: OPTCR1 fieldset: OPTCR1
- name: OPTCR2 - name: OPTCR2
description: Flash option control register description: Flash option control register
byte_offset: 28 byte_offset: 28
fieldset: OPTCR2 fieldset: OPTCR2
fieldset/ACR: fieldset/ACR:
description: Flash access control register description: Flash access control register
fields: fields:
- name: LATENCY - name: LATENCY
description: Latency description: Latency
bit_offset: 0 bit_offset: 0
bit_size: 4 bit_size: 4
enum: LATENCY enum: LATENCY
- name: PRFTEN - name: PRFTEN
description: Prefetch enable description: Prefetch enable
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: ARTEN - name: ARTEN
description: ART Accelerator Enable description: ART Accelerator Enable
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: ARTRST - name: ARTRST
description: ART Accelerator reset description: ART Accelerator reset
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Control register description: Control register
fields: fields:
- name: PG - name: PG
description: Programming description: Programming
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: SER - name: SER
description: Sector Erase description: Sector Erase
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: MER - name: MER
description: Mass Erase of sectors 0 to 11 description: Mass Erase of sectors 0 to 11
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: SNB - name: SNB
description: Sector number description: Sector number
bit_offset: 3 bit_offset: 3
bit_size: 4 bit_size: 4
- name: PSIZE - name: PSIZE
description: Program size description: Program size
bit_offset: 8 bit_offset: 8
bit_size: 2 bit_size: 2
enum: PSIZE enum: PSIZE
- name: STRT - name: STRT
description: Start description: Start
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: EOPIE - name: EOPIE
description: End of operation interrupt enable description: End of operation interrupt enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: ERRIE - name: ERRIE
description: Error interrupt enable description: Error interrupt enable
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: RDERRIE - name: RDERRIE
description: PCROP error interrupt enable description: PCROP error interrupt enable
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
- name: LOCK - name: LOCK
description: Lock description: Lock
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/KEYR: fieldset/KEYR:
description: Flash key register description: Flash key register
fields: fields:
- name: KEY - name: KEY
description: FPEC key description: FPEC key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/OPTCR: fieldset/OPTCR:
description: Flash option control register description: Flash option control register
fields: fields:
- name: OPTLOCK - name: OPTLOCK
description: Option lock description: Option lock
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: OPTSTRT - name: OPTSTRT
description: Option start description: Option start
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: BOR_LEV - name: BOR_LEV
description: BOR reset Level description: BOR reset Level
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
- name: WWDG_SW - name: WWDG_SW
description: User option bytes description: User option bytes
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: IWDG_SW - name: IWDG_SW
description: WDG_SW User option bytes description: WDG_SW User option bytes
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: nRST_STOP - name: nRST_STOP
description: nRST_STOP User option bytes description: nRST_STOP User option bytes
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: nRST_STDBY - name: nRST_STDBY
description: nRST_STDBY User option bytes description: nRST_STDBY User option bytes
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: RDP - name: RDP
description: Read protect description: Read protect
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
- name: nWRP - name: nWRP
description: Not write protect description: Not write protect
bit_offset: 16 bit_offset: 16
bit_size: 8 bit_size: 8
- name: nDBOOT - name: nDBOOT
description: Dual Boot mode (valid only when nDBANK=0) description: Dual Boot mode (valid only when nDBANK=0)
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
- name: nDBANK - name: nDBANK
description: Not dual bank mode description: Not dual bank mode
bit_offset: 29 bit_offset: 29
bit_size: 1 bit_size: 1
- name: IWDG_STDBY - name: IWDG_STDBY
description: Independent watchdog counter freeze in standby mode description: Independent watchdog counter freeze in standby mode
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
- name: IWDG_STOP - name: IWDG_STOP
description: Independent watchdog counter freeze in Stop mode description: Independent watchdog counter freeze in Stop mode
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/OPTCR1: fieldset/OPTCR1:
description: Flash option control register 1 description: Flash option control register 1
fields: fields:
- name: BOOT_ADD0 - name: BOOT_ADD0
description: Boot base address when Boot pin =0 description: Boot base address when Boot pin =0
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
- name: BOOT_ADD1 - name: BOOT_ADD1
description: Boot base address when Boot pin =1 description: Boot base address when Boot pin =1
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16
fieldset/OPTCR2: fieldset/OPTCR2:
description: Flash option control register description: Flash option control register
fields: fields:
- name: PCROPi - name: PCROPi
description: PCROP option byte description: PCROP option byte
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: PCROP_RDP - name: PCROP_RDP
description: PCROP zone preserved when RDP level decreased description: PCROP zone preserved when RDP level decreased
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/OPTKEYR: fieldset/OPTKEYR:
description: Flash option key register description: Flash option key register
fields: fields:
- name: OPTKEYR - name: OPTKEYR
description: Option byte key description: Option byte key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/SR: fieldset/SR:
description: Status register description: Status register
fields: fields:
- name: EOP - name: EOP
description: End of operation description: End of operation
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: OPERR - name: OPERR
description: Operation error description: Operation error
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: WRPERR - name: WRPERR
description: Write protection error description: Write protection error
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: PGAERR - name: PGAERR
description: Programming alignment error description: Programming alignment error
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: PGPERR - name: PGPERR
description: Programming parallelism error description: Programming parallelism error
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: ERSERR - name: ERSERR
description: Erase Sequence Error description: Erase Sequence Error
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: RDERR - name: RDERR
description: RDERR description: RDERR
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: BSY - name: BSY
description: Busy description: Busy
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum/LATENCY: enum/LATENCY:
bit_size: 4 bit_size: 4
variants: variants:
- name: WS0 - name: WS0
description: 0 wait states description: 0 wait states
value: 0 value: 0
- name: WS1 - name: WS1
description: 1 wait states description: 1 wait states
value: 1 value: 1
- name: WS2 - name: WS2
description: 2 wait states description: 2 wait states
value: 2 value: 2
- name: WS3 - name: WS3
description: 3 wait states description: 3 wait states
value: 3 value: 3
- name: WS4 - name: WS4
description: 4 wait states description: 4 wait states
value: 4 value: 4
- name: WS5 - name: WS5
description: 5 wait states description: 5 wait states
value: 5 value: 5
- name: WS6 - name: WS6
description: 6 wait states description: 6 wait states
value: 6 value: 6
- name: WS7 - name: WS7
description: 7 wait states description: 7 wait states
value: 7 value: 7
- name: WS8 - name: WS8
description: 8 wait states description: 8 wait states
value: 8 value: 8
- name: WS9 - name: WS9
description: 9 wait states description: 9 wait states
value: 9 value: 9
- name: WS10 - name: WS10
description: 10 wait states description: 10 wait states
value: 10 value: 10
- name: WS11 - name: WS11
description: 11 wait states description: 11 wait states
value: 11 value: 11
- name: WS12 - name: WS12
description: 12 wait states description: 12 wait states
value: 12 value: 12
- name: WS13 - name: WS13
description: 13 wait states description: 13 wait states
value: 13 value: 13
- name: WS14 - name: WS14
description: 14 wait states description: 14 wait states
value: 14 value: 14
- name: WS15 - name: WS15
description: 15 wait states description: 15 wait states
value: 15 value: 15
enum/PSIZE: enum/PSIZE:
bit_size: 2 bit_size: 2
variants: variants:
- name: PSIZE8 - name: PSIZE8
description: Program x8 description: Program x8
value: 0 value: 0
- name: PSIZE16 - name: PSIZE16
description: Program x16 description: Program x16
value: 1 value: 1
- name: PSIZE32 - name: PSIZE32
description: Program x32 description: Program x32
value: 2 value: 2
- name: PSIZE64 - name: PSIZE64
description: Program x64 description: Program x64
value: 3 value: 3

787
data/registers/flash_g0.yaml
View File

@ -1,454 +1,453 @@
---
block/FLASH: block/FLASH:
description: Flash description: Flash
items: items:
- name: ACR - name: ACR
description: Access control register description: Access control register
byte_offset: 0 byte_offset: 0
fieldset: ACR fieldset: ACR
- name: KEYR - name: KEYR
description: Flash key register description: Flash key register
byte_offset: 8 byte_offset: 8
access: Write access: Write
fieldset: KEYR fieldset: KEYR
- name: OPTKEYR - name: OPTKEYR
description: Option byte key register description: Option byte key register
byte_offset: 12 byte_offset: 12
access: Write access: Write
fieldset: OPTKEYR fieldset: OPTKEYR
- name: SR - name: SR
description: Status register description: Status register
byte_offset: 16 byte_offset: 16
fieldset: SR fieldset: SR
- name: CR - name: CR
description: Flash control register description: Flash control register
byte_offset: 20 byte_offset: 20
fieldset: CR fieldset: CR
- name: ECCR - name: ECCR
description: Flash ECC register description: Flash ECC register
byte_offset: 24 byte_offset: 24
fieldset: ECCR fieldset: ECCR
- name: OPTR - name: OPTR
description: Flash option register description: Flash option register
byte_offset: 32 byte_offset: 32
fieldset: OPTR fieldset: OPTR
- name: PCROP1ASR - name: PCROP1ASR
description: Flash PCROP zone A Start address register description: Flash PCROP zone A Start address register
byte_offset: 36 byte_offset: 36
access: Read access: Read
fieldset: PCROP1ASR fieldset: PCROP1ASR
- name: PCROP1AER - name: PCROP1AER
description: Flash PCROP zone A End address register description: Flash PCROP zone A End address register
byte_offset: 40 byte_offset: 40
access: Read access: Read
fieldset: PCROP1AER fieldset: PCROP1AER
- name: WRP1AR - name: WRP1AR
description: Flash WRP area A address register description: Flash WRP area A address register
byte_offset: 44 byte_offset: 44
access: Read access: Read
fieldset: WRP1AR fieldset: WRP1AR
- name: WRP1BR - name: WRP1BR
description: Flash WRP area B address register description: Flash WRP area B address register
byte_offset: 48 byte_offset: 48
access: Read access: Read
fieldset: WRP1BR fieldset: WRP1BR
- name: PCROP1BSR - name: PCROP1BSR
description: Flash PCROP zone B Start address register description: Flash PCROP zone B Start address register
byte_offset: 52 byte_offset: 52
access: Read access: Read
fieldset: PCROP1BSR fieldset: PCROP1BSR
- name: PCROP1BER - name: PCROP1BER
description: Flash PCROP zone B End address register description: Flash PCROP zone B End address register
byte_offset: 56 byte_offset: 56
access: Read access: Read
fieldset: PCROP1BER fieldset: PCROP1BER
- name: SECR - name: SECR
description: Flash Security register description: Flash Security register
byte_offset: 128 byte_offset: 128
access: Read access: Read
fieldset: SECR fieldset: SECR
fieldset/ACR: fieldset/ACR:
description: Access control register description: Access control register
fields: fields:
- name: LATENCY - name: LATENCY
description: Latency description: Latency
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
enum: LATENCY enum: LATENCY
- name: PRFTEN - name: PRFTEN
description: Prefetch enable description: Prefetch enable
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: ICEN - name: ICEN
description: Instruction cache enable description: Instruction cache enable
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: ICRST - name: ICRST
description: Instruction cache reset description: Instruction cache reset
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: EMPTY - name: EMPTY
description: Flash User area empty description: Flash User area empty
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: DBG_SWEN - name: DBG_SWEN
description: Debug access software enable description: Debug access software enable
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Flash control register description: Flash control register
fields: fields:
- name: PG - name: PG
description: Programming description: Programming
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: PER - name: PER
description: Page erase description: Page erase
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: MER - name: MER
description: Mass erase description: Mass erase
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: PNB - name: PNB
description: Page number description: Page number
bit_offset: 3 bit_offset: 3
bit_size: 6 bit_size: 6
- name: STRT - name: STRT
description: Start description: Start
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: OPTSTRT - name: OPTSTRT
description: Options modification start description: Options modification start
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: FSTPG - name: FSTPG
description: Fast programming description: Fast programming
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
- name: EOPIE - name: EOPIE
description: End of operation interrupt enable description: End of operation interrupt enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: ERRIE - name: ERRIE
description: Error interrupt enable description: Error interrupt enable
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: RDERRIE - name: RDERRIE
description: PCROP read error interrupt enable description: PCROP read error interrupt enable
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
- name: OBL_LAUNCH - name: OBL_LAUNCH
description: Force the option byte loading description: Force the option byte loading
bit_offset: 27 bit_offset: 27
bit_size: 1 bit_size: 1
- name: SEC_PROT - name: SEC_PROT
description: Securable memory area protection enable description: Securable memory area protection enable
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
- name: OPTLOCK - name: OPTLOCK
description: Options Lock description: Options Lock
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
- name: LOCK - name: LOCK
description: FLASH_CR Lock description: FLASH_CR Lock
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/ECCR: fieldset/ECCR:
description: Flash ECC register description: Flash ECC register
fields: fields:
- name: ADDR_ECC - name: ADDR_ECC
description: ECC fail address description: ECC fail address
bit_offset: 0 bit_offset: 0
bit_size: 14 bit_size: 14
- name: SYSF_ECC - name: SYSF_ECC
description: ECC fail for Corrected ECC Error or Double ECC Error in info block description: ECC fail for Corrected ECC Error or Double ECC Error in info block
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
- name: ECCIE - name: ECCIE
description: ECC correction interrupt enable description: ECC correction interrupt enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: ECCC - name: ECCC
description: ECC correction description: ECC correction
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
- name: ECCD - name: ECCD
description: ECC detection description: ECC detection
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/KEYR: fieldset/KEYR:
description: Flash key register description: Flash key register
fields: fields:
- name: KEYR - name: KEYR
description: KEYR description: KEYR
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/OPTKEYR: fieldset/OPTKEYR:
description: Option byte key register description: Option byte key register
fields: fields:
- name: OPTKEYR - name: OPTKEYR
description: Option byte key description: Option byte key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/OPTR: fieldset/OPTR:
description: Flash option register description: Flash option register
fields: fields:
- name: RDP - name: RDP
description: Read protection level description: Read protection level
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
enum: RDP enum: RDP
- name: BOREN - name: BOREN
description: BOR reset Level description: BOR reset Level
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: BORF_LEV - name: BORF_LEV
description: These bits contain the VDD supply level threshold that activates the reset description: These bits contain the VDD supply level threshold that activates the reset
bit_offset: 9 bit_offset: 9
bit_size: 2 bit_size: 2
enum: BORF_LEV enum: BORF_LEV
- name: BORR_LEV - name: BORR_LEV
description: These bits contain the VDD supply level threshold that releases the reset. description: These bits contain the VDD supply level threshold that releases the reset.
bit_offset: 11 bit_offset: 11
bit_size: 2 bit_size: 2
enum: BORR_LEV enum: BORR_LEV
- name: nRST_STOP - name: nRST_STOP
description: nRST_STOP description: nRST_STOP
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: nRST_STDBY - name: nRST_STDBY
description: nRST_STDBY description: nRST_STDBY
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: nRSTS_HDW - name: nRSTS_HDW
description: nRSTS_HDW description: nRSTS_HDW
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: IDWG_SW - name: IDWG_SW
description: Independent watchdog selection description: Independent watchdog selection
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: IWDG_STOP - name: IWDG_STOP
description: Independent watchdog counter freeze in Stop mode description: Independent watchdog counter freeze in Stop mode
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: IWDG_STDBY - name: IWDG_STDBY
description: Independent watchdog counter freeze in Standby mode description: Independent watchdog counter freeze in Standby mode
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
- name: WWDG_SW - name: WWDG_SW
description: Window watchdog selection description: Window watchdog selection
bit_offset: 19 bit_offset: 19
bit_size: 1 bit_size: 1
- name: RAM_PARITY_CHECK - name: RAM_PARITY_CHECK
description: SRAM parity check control description: SRAM parity check control
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: nBOOT_SEL - name: nBOOT_SEL
description: nBOOT_SEL description: nBOOT_SEL
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: nBOOT1 - name: nBOOT1
description: Boot configuration description: Boot configuration
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: nBOOT0 - name: nBOOT0
description: nBOOT0 option bit description: nBOOT0 option bit
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
- name: NRST_MODE - name: NRST_MODE
description: NRST_MODE description: NRST_MODE
bit_offset: 27 bit_offset: 27
bit_size: 2 bit_size: 2
enum: NRST_MODE enum: NRST_MODE
- name: IRHEN - name: IRHEN
description: Internal reset holder enable bit description: Internal reset holder enable bit
bit_offset: 29 bit_offset: 29
bit_size: 1 bit_size: 1
fieldset/PCROP1AER: fieldset/PCROP1AER:
description: Flash PCROP zone A End address register description: Flash PCROP zone A End address register
fields: fields:
- name: PCROP1A_END - name: PCROP1A_END
description: PCROP1A area end offset description: PCROP1A area end offset
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: PCROP_RDP - name: PCROP_RDP
description: PCROP area preserved when RDP level decreased description: PCROP area preserved when RDP level decreased
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/PCROP1ASR: fieldset/PCROP1ASR:
description: Flash PCROP zone A Start address register description: Flash PCROP zone A Start address register
fields: fields:
- name: PCROP1A_STRT - name: PCROP1A_STRT
description: PCROP1A area start offset description: PCROP1A area start offset
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
fieldset/PCROP1BER: fieldset/PCROP1BER:
description: Flash PCROP zone B End address register description: Flash PCROP zone B End address register
fields: fields:
- name: PCROP1B_END - name: PCROP1B_END
description: PCROP1B area end offset description: PCROP1B area end offset
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
fieldset/PCROP1BSR: fieldset/PCROP1BSR:
description: Flash PCROP zone B Start address register description: Flash PCROP zone B Start address register
fields: fields:
- name: PCROP1B_STRT - name: PCROP1B_STRT
description: PCROP1B area start offset description: PCROP1B area start offset
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
fieldset/SECR: fieldset/SECR:
description: Flash Security register description: Flash Security register
fields: fields:
- name: SEC_SIZE - name: SEC_SIZE
description: Securable memory area size description: Securable memory area size
bit_offset: 0 bit_offset: 0
bit_size: 7 bit_size: 7
- name: BOOT_LOCK - name: BOOT_LOCK
description: used to force boot from user area description: used to force boot from user area
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
fieldset/SR: fieldset/SR:
description: Status register description: Status register
fields: fields:
- name: EOP - name: EOP
description: End of operation description: End of operation
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: OPERR - name: OPERR
description: Operation error description: Operation error
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: PROGERR - name: PROGERR
description: Programming error description: Programming error
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: WRPERR - name: WRPERR
description: Write protected error description: Write protected error
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: PGAERR - name: PGAERR
description: Programming alignment error description: Programming alignment error
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: SIZERR - name: SIZERR
description: Size error description: Size error
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: PGSERR - name: PGSERR
description: Programming sequence error description: Programming sequence error
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: MISERR - name: MISERR
description: Fast programming data miss error description: Fast programming data miss error
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: FASTERR - name: FASTERR
description: Fast programming error description: Fast programming error
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: RDERR - name: RDERR
description: PCROP read error description: PCROP read error
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: OPTVERR - name: OPTVERR
description: Option and Engineering bits loading validity error description: Option and Engineering bits loading validity error
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: BSY - name: BSY
description: Busy description: Busy
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: CFGBSY - name: CFGBSY
description: Programming or erase configuration busy. description: Programming or erase configuration busy.
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/WRP1AR: fieldset/WRP1AR:
description: Flash WRP area A address register description: Flash WRP area A address register
fields: fields:
- name: WRP1A_STRT - name: WRP1A_STRT
description: WRP area A start offset description: WRP area A start offset
bit_offset: 0 bit_offset: 0
bit_size: 6 bit_size: 6
- name: WRP1A_END - name: WRP1A_END
description: WRP area A end offset description: WRP area A end offset
bit_offset: 16 bit_offset: 16
bit_size: 6 bit_size: 6
fieldset/WRP1BR: fieldset/WRP1BR:
description: Flash WRP area B address register description: Flash WRP area B address register
fields: fields:
- name: WRP1B_STRT - name: WRP1B_STRT
description: WRP area B start offset description: WRP area B start offset
bit_offset: 0 bit_offset: 0
bit_size: 6 bit_size: 6
- name: WRP1B_END - name: WRP1B_END
description: WRP area B end offset description: WRP area B end offset
bit_offset: 16 bit_offset: 16
bit_size: 6 bit_size: 6
enum/BORF_LEV: enum/BORF_LEV:
bit_size: 2 bit_size: 2
variants: variants:
- name: FALLING_0 - name: FALLING_0
description: BOR falling level 1 with threshold around 2.0V description: BOR falling level 1 with threshold around 2.0V
value: 0 value: 0
- name: FALLING_1 - name: FALLING_1
description: BOR falling level 2 with threshold around 2.2V description: BOR falling level 2 with threshold around 2.2V
value: 1 value: 1
- name: FALLING_2 - name: FALLING_2
description: BOR falling level 3 with threshold around 2.5V description: BOR falling level 3 with threshold around 2.5V
value: 2 value: 2
- name: FALLING_3 - name: FALLING_3
description: BOR falling level 4 with threshold around 2.8V description: BOR falling level 4 with threshold around 2.8V
value: 3 value: 3
enum/BORR_LEV: enum/BORR_LEV:
bit_size: 2 bit_size: 2
variants: variants:
- name: RISING_0 - name: RISING_0
description: BOR rising level 1 with threshold around 2.1V description: BOR rising level 1 with threshold around 2.1V
value: 0 value: 0
- name: RISING_1 - name: RISING_1
description: BOR rising level 2 with threshold around 2.3V description: BOR rising level 2 with threshold around 2.3V
value: 1 value: 1
- name: RISING_2 - name: RISING_2
description: BOR rising level 3 with threshold around 2.6V description: BOR rising level 3 with threshold around 2.6V
value: 2 value: 2
- name: RISING_3 - name: RISING_3
description: BOR rising level 4 with threshold around 2.9V description: BOR rising level 4 with threshold around 2.9V
value: 3 value: 3
enum/LATENCY: enum/LATENCY:
bit_size: 3 bit_size: 3
variants: variants:
- name: WS0 - name: WS0
description: Zero wait states description: Zero wait states
value: 0 value: 0
- name: WS1 - name: WS1
description: One wait state description: One wait state
value: 1 value: 1
- name: WS2 - name: WS2
description: Two wait states description: Two wait states
value: 2 value: 2
enum/NRST_MODE: enum/NRST_MODE:
bit_size: 2 bit_size: 2
variants: variants:
- name: INPUT_ONLY - name: INPUT_ONLY
description: Reset pin is in reset input mode only description: Reset pin is in reset input mode only
value: 1 value: 1
- name: GPIO - name: GPIO
description: Reset pin is in GPIO mode only description: Reset pin is in GPIO mode only
value: 2 value: 2
- name: INPUT_OUTPUT - name: INPUT_OUTPUT
description: Reset pin is in resety input and output mode description: Reset pin is in resety input and output mode
value: 3 value: 3
enum/RDP: enum/RDP:
bit_size: 8 bit_size: 8
variants: variants:
- name: LEVEL_0 - name: LEVEL_0
description: Read protection not active description: Read protection not active
value: 170 value: 170
- name: LEVEL_1 - name: LEVEL_1
description: Memories read protection active description: Memories read protection active
value: 187 value: 187
- name: LEVEL_2 - name: LEVEL_2
description: Chip read protection active description: Chip read protection active
value: 204 value: 204

751
data/registers/flash_g4.yaml
View File

@ -1,427 +1,426 @@
---
block/FLASH: block/FLASH:
description: Flash description: Flash
items: items:
- name: ACR - name: ACR
description: Access control register description: Access control register
byte_offset: 0 byte_offset: 0
fieldset: ACR fieldset: ACR
- name: PDKEYR - name: PDKEYR
description: Power down key register description: Power down key register
byte_offset: 4 byte_offset: 4
access: Write access: Write
fieldset: PDKEYR fieldset: PDKEYR
- name: KEYR - name: KEYR
description: Flash key register description: Flash key register
byte_offset: 8 byte_offset: 8
access: Write access: Write
fieldset: KEYR fieldset: KEYR
- name: OPTKEYR - name: OPTKEYR
description: Option byte key register description: Option byte key register
byte_offset: 12 byte_offset: 12
access: Write access: Write
fieldset: OPTKEYR fieldset: OPTKEYR
- name: SR - name: SR
description: Status register description: Status register
byte_offset: 16 byte_offset: 16
fieldset: SR fieldset: SR
- name: CR - name: CR
description: Flash control register description: Flash control register
byte_offset: 20 byte_offset: 20
fieldset: CR fieldset: CR
- name: ECCR - name: ECCR
description: Flash ECC register description: Flash ECC register
byte_offset: 24 byte_offset: 24
fieldset: ECCR fieldset: ECCR
- name: OPTR - name: OPTR
description: Flash option register description: Flash option register
byte_offset: 32 byte_offset: 32
fieldset: OPTR fieldset: OPTR
- name: PCROP1SR - name: PCROP1SR
description: Flash Bank 1 PCROP Start address register description: Flash Bank 1 PCROP Start address register
byte_offset: 36 byte_offset: 36
fieldset: PCROP1SR fieldset: PCROP1SR
- name: PCROP1ER - name: PCROP1ER
description: Flash Bank 1 PCROP End address register description: Flash Bank 1 PCROP End address register
byte_offset: 40 byte_offset: 40
fieldset: PCROP1ER fieldset: PCROP1ER
- name: WRP1AR - name: WRP1AR
description: Flash Bank 1 WRP area A address register description: Flash Bank 1 WRP area A address register
byte_offset: 44 byte_offset: 44
fieldset: WRP1AR fieldset: WRP1AR
- name: WRP1BR - name: WRP1BR
description: Flash Bank 1 WRP area B address register description: Flash Bank 1 WRP area B address register
byte_offset: 48 byte_offset: 48
fieldset: WRP1BR fieldset: WRP1BR
- name: SEC1R - name: SEC1R
description: securable area bank1 register description: securable area bank1 register
byte_offset: 112 byte_offset: 112
fieldset: SEC1R fieldset: SEC1R
fieldset/ACR: fieldset/ACR:
description: Access control register description: Access control register
fields: fields:
- name: LATENCY - name: LATENCY
description: Latency description: Latency
bit_offset: 0 bit_offset: 0
bit_size: 4 bit_size: 4
enum: LATENCY enum: LATENCY
- name: PRFTEN - name: PRFTEN
description: Prefetch enable description: Prefetch enable
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: ICEN - name: ICEN
description: Instruction cache enable description: Instruction cache enable
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: DCEN - name: DCEN
description: Data cache enable description: Data cache enable
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: ICRST - name: ICRST
description: Instruction cache reset description: Instruction cache reset
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: DCRST - name: DCRST
description: Data cache reset description: Data cache reset
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: RUN_PD - name: RUN_PD
description: Flash Power-down mode during Low-power run mode description: Flash Power-down mode during Low-power run mode
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: SLEEP_PD - name: SLEEP_PD
description: Flash Power-down mode during Low-power sleep mode description: Flash Power-down mode during Low-power sleep mode
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: DBG_SWEN - name: DBG_SWEN
description: Debug software enable description: Debug software enable
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Flash control register description: Flash control register
fields: fields:
- name: PG - name: PG
description: Programming description: Programming
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: PER - name: PER
description: Page erase description: Page erase
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: MER1 - name: MER1
description: Bank 1 Mass erase description: Bank 1 Mass erase
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: PNB - name: PNB
description: Page number description: Page number
bit_offset: 3 bit_offset: 3
bit_size: 7 bit_size: 7
- name: STRT - name: STRT
description: Start description: Start
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: OPTSTRT - name: OPTSTRT
description: Options modification start description: Options modification start
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: FSTPG - name: FSTPG
description: Fast programming description: Fast programming
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
- name: EOPIE - name: EOPIE
description: End of operation interrupt enable description: End of operation interrupt enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: ERRIE - name: ERRIE
description: Error interrupt enable description: Error interrupt enable
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: RDERRIE - name: RDERRIE
description: PCROP read error interrupt enable description: PCROP read error interrupt enable
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
- name: OBL_LAUNCH - name: OBL_LAUNCH
description: Force the option byte loading description: Force the option byte loading
bit_offset: 27 bit_offset: 27
bit_size: 1 bit_size: 1
- name: SEC_PROT1 - name: SEC_PROT1
description: Securable memory area protection enable description: Securable memory area protection enable
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
- name: OPTLOCK - name: OPTLOCK
description: Options Lock description: Options Lock
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
- name: LOCK - name: LOCK
description: FLASH_CR Lock description: FLASH_CR Lock
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/ECCR: fieldset/ECCR:
description: Flash ECC register description: Flash ECC register
fields: fields:
- name: ADDR_ECC - name: ADDR_ECC
description: ECC fail address description: ECC fail address
bit_offset: 0 bit_offset: 0
bit_size: 19 bit_size: 19
- name: BK_ECC - name: BK_ECC
description: ECC fail for Corrected ECC Error or Double ECC Error in info block description: ECC fail for Corrected ECC Error or Double ECC Error in info block
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: SYSF_ECC - name: SYSF_ECC
description: ECC fail for Corrected ECC Error or Double ECC Error in info block description: ECC fail for Corrected ECC Error or Double ECC Error in info block
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: ECCIE - name: ECCIE
description: ECC correction interrupt enable description: ECC correction interrupt enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: ECCC2 - name: ECCC2
description: ECC correction description: ECC correction
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
- name: ECCD2 - name: ECCD2
description: ECC2 detection description: ECC2 detection
bit_offset: 29 bit_offset: 29
bit_size: 1 bit_size: 1
- name: ECCC - name: ECCC
description: ECC correction description: ECC correction
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
- name: ECCD - name: ECCD
description: ECC detection description: ECC detection
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/KEYR: fieldset/KEYR:
description: Flash key register description: Flash key register
fields: fields:
- name: KEYR - name: KEYR
description: KEYR description: KEYR
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/OPTKEYR: fieldset/OPTKEYR:
description: Option byte key register description: Option byte key register
fields: fields:
- name: OPTKEYR - name: OPTKEYR
description: Option byte key description: Option byte key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/OPTR: fieldset/OPTR:
description: Flash option register description: Flash option register
fields: fields:
- name: RDP - name: RDP
description: Read protection level description: Read protection level
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
enum: RDP enum: RDP
- name: BOR_LEV - name: BOR_LEV
description: BOR reset Level description: BOR reset Level
bit_offset: 8 bit_offset: 8
bit_size: 3 bit_size: 3
- name: nRST_STOP - name: nRST_STOP
description: nRST_STOP description: nRST_STOP
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: nRST_STDBY - name: nRST_STDBY
description: nRST_STDBY description: nRST_STDBY
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: nRST_SHDW - name: nRST_SHDW
description: nRST_SHDW description: nRST_SHDW
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: IDWG_SW - name: IDWG_SW
description: Independent watchdog selection description: Independent watchdog selection
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: IWDG_STOP - name: IWDG_STOP
description: Independent watchdog counter freeze in Stop mode description: Independent watchdog counter freeze in Stop mode
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: IWDG_STDBY - name: IWDG_STDBY
description: Independent watchdog counter freeze in Standby mode description: Independent watchdog counter freeze in Standby mode
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
- name: WWDG_SW - name: WWDG_SW
description: Window watchdog selection description: Window watchdog selection
bit_offset: 19 bit_offset: 19
bit_size: 1 bit_size: 1
- name: nBOOT1 - name: nBOOT1
description: Boot configuration description: Boot configuration
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: SRAM2_PE - name: SRAM2_PE
description: SRAM2 parity check enable description: SRAM2 parity check enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: SRAM2_RST - name: SRAM2_RST
description: SRAM2 Erase when system reset description: SRAM2 Erase when system reset
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: nSWBOOT0 - name: nSWBOOT0
description: nSWBOOT0 description: nSWBOOT0
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
- name: nBOOT0 - name: nBOOT0
description: nBOOT0 option bit description: nBOOT0 option bit
bit_offset: 27 bit_offset: 27
bit_size: 1 bit_size: 1
- name: NRST_MODE - name: NRST_MODE
description: NRST_MODE description: NRST_MODE
bit_offset: 28 bit_offset: 28
bit_size: 2 bit_size: 2
enum: NRST_MODE enum: NRST_MODE
- name: IRHEN - name: IRHEN
description: Internal reset holder enable bit description: Internal reset holder enable bit
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
fieldset/PCROP1ER: fieldset/PCROP1ER:
description: Flash Bank 1 PCROP End address register description: Flash Bank 1 PCROP End address register
fields: fields:
- name: PCROP1_END - name: PCROP1_END
description: Bank 1 PCROP area end offset description: Bank 1 PCROP area end offset
bit_offset: 0 bit_offset: 0
bit_size: 15 bit_size: 15
- name: PCROP_RDP - name: PCROP_RDP
description: PCROP area preserved when RDP level decreased description: PCROP area preserved when RDP level decreased
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/PCROP1SR: fieldset/PCROP1SR:
description: Flash Bank 1 PCROP Start address register description: Flash Bank 1 PCROP Start address register
fields: fields:
- name: PCROP1_STRT - name: PCROP1_STRT
description: Bank 1 PCROP area start offset description: Bank 1 PCROP area start offset
bit_offset: 0 bit_offset: 0
bit_size: 15 bit_size: 15
fieldset/PDKEYR: fieldset/PDKEYR:
description: Power down key register description: Power down key register
fields: fields:
- name: PDKEYR - name: PDKEYR
description: RUN_PD in FLASH_ACR key description: RUN_PD in FLASH_ACR key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/SEC1R: fieldset/SEC1R:
description: securable area bank1 register description: securable area bank1 register
fields: fields:
- name: SEC_SIZE1 - name: SEC_SIZE1
description: SEC_SIZE1 description: SEC_SIZE1
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: BOOT_LOCK - name: BOOT_LOCK
description: used to force boot from user area description: used to force boot from user area
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
fieldset/SR: fieldset/SR:
description: Status register description: Status register
fields: fields:
- name: EOP - name: EOP
description: End of operation description: End of operation
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: OPERR - name: OPERR
description: Operation error description: Operation error
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: PROGERR - name: PROGERR
description: Programming error description: Programming error
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: WRPERR - name: WRPERR
description: Write protected error description: Write protected error
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: PGAERR - name: PGAERR
description: Programming alignment error description: Programming alignment error
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: SIZERR - name: SIZERR
description: Size error description: Size error
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: PGSERR - name: PGSERR
description: Programming sequence error description: Programming sequence error
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: MISERR - name: MISERR
description: Fast programming data miss error description: Fast programming data miss error
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: FASTERR - name: FASTERR
description: Fast programming error description: Fast programming error
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: RDERR - name: RDERR
description: PCROP read error description: PCROP read error
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: OPTVERR - name: OPTVERR
description: Option validity error description: Option validity error
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: BSY - name: BSY
description: Busy description: Busy
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
fieldset/WRP1AR: fieldset/WRP1AR:
description: Flash Bank 1 WRP area A address register description: Flash Bank 1 WRP area A address register
fields: fields:
- name: WRP1A_STRT - name: WRP1A_STRT
description: Bank 1 WRP first area start offset description: Bank 1 WRP first area start offset
bit_offset: 0 bit_offset: 0
bit_size: 7 bit_size: 7
- name: WRP1A_END - name: WRP1A_END
description: Bank 1 WRP first area A end offset description: Bank 1 WRP first area A end offset
bit_offset: 16 bit_offset: 16
bit_size: 7 bit_size: 7
fieldset/WRP1BR: fieldset/WRP1BR:
description: Flash Bank 1 WRP area B address register description: Flash Bank 1 WRP area B address register
fields: fields:
- name: WRP1B_STRT - name: WRP1B_STRT
description: Bank 1 WRP second area B end offset description: Bank 1 WRP second area B end offset
bit_offset: 0 bit_offset: 0
bit_size: 7 bit_size: 7
- name: WRP1B_END - name: WRP1B_END
description: Bank 1 WRP second area B start offset description: Bank 1 WRP second area B start offset
bit_offset: 16 bit_offset: 16
bit_size: 7 bit_size: 7
enum/LATENCY: enum/LATENCY:
bit_size: 3 bit_size: 3
variants: variants:
- name: WS0 - name: WS0
description: Zero wait states description: Zero wait states
value: 0 value: 0
- name: WS1 - name: WS1
description: One wait state description: One wait state
value: 1 value: 1
- name: WS2 - name: WS2
description: Two wait states description: Two wait states
value: 2 value: 2
- name: WS3 - name: WS3
description: Three wait states description: Three wait states
value: 3 value: 3
- name: WS4 - name: WS4
description: Four wait states description: Four wait states
value: 4 value: 4
enum/NRST_MODE: enum/NRST_MODE:
bit_size: 2 bit_size: 2
variants: variants:
- name: INPUT_ONLY - name: INPUT_ONLY
description: Reset pin is in reset input mode only description: Reset pin is in reset input mode only
value: 1 value: 1
- name: GPIO - name: GPIO
description: Reset pin is in GPIO mode only description: Reset pin is in GPIO mode only
value: 2 value: 2
- name: INPUT_OUTPUT - name: INPUT_OUTPUT
description: Reset pin is in reset input and output mode description: Reset pin is in reset input and output mode
value: 3 value: 3
enum/RDP: enum/RDP:
bit_size: 8 bit_size: 8
variants: variants:
- name: LEVEL_0 - name: LEVEL_0
description: Read protection not active description: Read protection not active
value: 170 value: 170
- name: LEVEL_1 - name: LEVEL_1
description: Memories read protection active description: Memories read protection active
value: 187 value: 187
- name: LEVEL_2 - name: LEVEL_2
description: Chip read protection active description: Chip read protection active
value: 204 value: 204

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block/BANK:
description: Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R
items:
- name: KEYR
description: FLASH key register for bank 1
byte_offset: 0
access: Write
fieldset: KEYR
- name: CR
description: FLASH control register for bank 1
byte_offset: 8
fieldset: CR
- name: SR
description: FLASH status register for bank 1
byte_offset: 12
fieldset: SR
- name: CCR
description: FLASH clear control register for bank 1
byte_offset: 16
fieldset: CCR
- name: PRAR_CUR
description: FLASH protection address for bank 1
byte_offset: 36
access: Read
fieldset: PRAR_CUR
- name: PRAR_PRG
description: FLASH protection address for bank 1
byte_offset: 40
fieldset: PRAR_PRG
- name: SCAR_CUR
description: FLASH secure address for bank 1
byte_offset: 44
fieldset: SCAR_CUR
- name: SCAR_PRG
description: FLASH secure address for bank 1
byte_offset: 48
fieldset: SCAR_PRG
- name: WPSN_CURR
description: FLASH write sector protection for bank 1
byte_offset: 52
access: Read
fieldset: WPSN_CURR
- name: WPSN_PRGR
description: FLASH write sector protection for bank 1
byte_offset: 56
fieldset: WPSN_PRGR
- name: CRCCR
description: FLASH CRC control register for bank 1
byte_offset: 76
fieldset: CRCCR
- name: CRCSADDR
description: FLASH CRC start address register for bank 1
byte_offset: 80
fieldset: CRCSADDR
- name: CRCEADDR
description: FLASH CRC end address register for bank 1
byte_offset: 84
fieldset: CRCEADDR
- name: FAR
description: FLASH ECC fail address for bank 1
byte_offset: 92
access: Read
fieldset: FAR
block/FLASH:
description: Flash
items:
- name: ACR
description: Access control register
byte_offset: 0
fieldset: ACR
- name: BANK
description: Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R
array:
len: 2
stride: 256
byte_offset: 4
block: BANK
- name: OPTKEYR
description: FLASH option key register
byte_offset: 8
fieldset: OPTKEYR
- name: OPTCR
description: FLASH option control register
byte_offset: 24
fieldset: OPTCR
- name: OPTSR_CUR
description: FLASH option status register
byte_offset: 28
fieldset: OPTSR_CUR
- name: OPTSR_PRG
description: FLASH option status register
byte_offset: 32
fieldset: OPTSR_PRG
- name: OPTCCR
description: FLASH option clear control register
byte_offset: 36
access: Write
fieldset: OPTCCR
- name: BOOT_CURR
description: FLASH register with boot address
byte_offset: 64
access: Read
fieldset: BOOT_CURR
- name: BOOT_PRGR
description: FLASH register with boot address
byte_offset: 68
fieldset: BOOT_PRGR
- name: CRCDATAR
description: FLASH CRC data register
byte_offset: 92
fieldset: CRCDATAR
fieldset/ACR:
description: Access control register
fields:
- name: LATENCY
description: Read latency
bit_offset: 0
bit_size: 3
- name: WRHIGHFREQ
description: Flash signal delay
bit_offset: 4
bit_size: 2
fieldset/BOOT_CURR:
description: FLASH register with boot address
fields:
- name: BOOT_ADD0
description: Boot address 0
bit_offset: 0
bit_size: 16
- name: BOOT_ADD1
description: Boot address 1
bit_offset: 16
bit_size: 16
fieldset/BOOT_PRGR:
description: FLASH register with boot address
fields:
- name: BOOT_ADD0
description: Boot address 0
bit_offset: 0
bit_size: 16
- name: BOOT_ADD1
description: Boot address 1
bit_offset: 16
bit_size: 16
fieldset/CCR:
description: FLASH clear control register for bank 1
fields:
- name: CLR_EOP
description: Bank 1 EOP1 flag clear bit
bit_offset: 16
bit_size: 1
- name: CLR_WRPERR
description: Bank 1 WRPERR1 flag clear bit
bit_offset: 17
bit_size: 1
- name: CLR_PGSERR
description: Bank 1 PGSERR1 flag clear bi
bit_offset: 18
bit_size: 1
- name: CLR_STRBERR
description: Bank 1 STRBERR1 flag clear bit
bit_offset: 19
bit_size: 1
- name: CLR_INCERR
description: Bank 1 INCERR1 flag clear bit
bit_offset: 21
bit_size: 1
- name: CLR_OPERR
description: Bank 1 OPERR1 flag clear bit
bit_offset: 22
bit_size: 1
- name: CLR_RDPERR
description: Bank 1 RDPERR1 flag clear bit
bit_offset: 23
bit_size: 1
- name: CLR_RDSERR
description: Bank 1 RDSERR1 flag clear bit
bit_offset: 24
bit_size: 1
- name: CLR_SNECCERR
description: Bank 1 SNECCERR1 flag clear bit
bit_offset: 25
bit_size: 1
- name: CLR_DBECCERR
description: Bank 1 DBECCERR1 flag clear bit
bit_offset: 26
bit_size: 1
- name: CLR_CRCEND
description: Bank 1 CRCEND1 flag clear bit
bit_offset: 27
bit_size: 1
- name: CLR_CRCRDERR
description: Bank 1 CRC read error clear bit
bit_offset: 28
bit_size: 1
fieldset/CR:
description: FLASH control register for bank 1
fields:
- name: LOCK
description: Bank 1 configuration lock bit
bit_offset: 0
bit_size: 1
- name: PG
description: Bank 1 program enable bit
bit_offset: 1
bit_size: 1
- name: SER
description: Bank 1 sector erase request
bit_offset: 2
bit_size: 1
- name: BER
description: Bank 1 erase request
bit_offset: 3
bit_size: 1
- name: FW
description: Bank 1 write forcing control bit
bit_offset: 4
bit_size: 1
- name: START
description: Bank 1 bank or sector erase start control bit
bit_offset: 5
bit_size: 1
- name: SSN
description: Bank 1 sector erase selection number
bit_offset: 6
bit_size: 7
- name: CRC_EN
description: Bank 1 CRC control bit
bit_offset: 15
bit_size: 1
- name: EOPIE
description: Bank 1 end-of-program interrupt control bit
bit_offset: 16
bit_size: 1
- name: WRPERRIE
description: Bank 1 write protection error interrupt enable bit
bit_offset: 17
bit_size: 1
- name: PGSERRIE
description: Bank 1 programming sequence error interrupt enable bit
bit_offset: 18
bit_size: 1
- name: STRBERRIE
description: Bank 1 strobe error interrupt enable bit
bit_offset: 19
bit_size: 1
- name: INCERRIE
description: Bank 1 inconsistency error interrupt enable bit
bit_offset: 21
bit_size: 1
- name: OPERRIE
description: Bank 1 write/erase error interrupt enable bit
bit_offset: 22
bit_size: 1
- name: RDPERRIE
description: Bank 1 read protection error interrupt enable bit
bit_offset: 23
bit_size: 1
- name: RDSERRIE
description: Bank 1 secure error interrupt enable bit
bit_offset: 24
bit_size: 1
- name: SNECCERRIE
description: Bank 1 ECC single correction error interrupt enable bit
bit_offset: 25
bit_size: 1
- name: DBECCERRIE
description: Bank 1 ECC double detection error interrupt enable bit
bit_offset: 26
bit_size: 1
- name: CRCENDIE
description: Bank 1 end of CRC calculation interrupt enable bit
bit_offset: 27
bit_size: 1
- name: CRCRDERRIE
description: Bank 1 CRC read error interrupt enable bit
bit_offset: 28
bit_size: 1
fieldset/CRCCR:
description: FLASH CRC control register for bank 1
fields:
- name: CRC_SECT
description: Bank 1 CRC sector number
bit_offset: 0
bit_size: 3
- name: ALL_BANK
description: Bank 1 CRC select bit
bit_offset: 7
bit_size: 1
- name: CRC_BY_SECT
description: Bank 1 CRC sector mode select bit
bit_offset: 8
bit_size: 1
- name: ADD_SECT
description: Bank 1 CRC sector select bit
bit_offset: 9
bit_size: 1
- name: CLEAN_SECT
description: Bank 1 CRC sector list clear bit
bit_offset: 10
bit_size: 1
- name: START_CRC
description: Bank 1 CRC start bit
bit_offset: 16
bit_size: 1
- name: CLEAN_CRC
description: Bank 1 CRC clear bit
bit_offset: 17
bit_size: 1
- name: CRC_BURST
description: Bank 1 CRC burst size
bit_offset: 20
bit_size: 2
fieldset/CRCDATAR:
description: FLASH CRC data register
fields:
- name: CRC_DATA
description: CRC result
bit_offset: 0
bit_size: 32
fieldset/CRCEADDR:
description: FLASH CRC end address register for bank 1
fields:
- name: CRC_END_ADDR
description: CRC end address on bank 1
bit_offset: 0
bit_size: 32
fieldset/CRCSADDR:
description: FLASH CRC start address register for bank 1
fields:
- name: CRC_START_ADDR
description: CRC start address on bank 1
bit_offset: 0
bit_size: 32
fieldset/FAR:
description: FLASH ECC fail address for bank 1
fields:
- name: FAIL_ECC_ADDR
description: Bank 1 ECC error address
bit_offset: 0
bit_size: 15
fieldset/KEYR:
description: FLASH key register for bank 1
fields:
- name: KEYR
description: Bank 1 access configuration unlock key
bit_offset: 0
bit_size: 32
fieldset/OPTCCR:
description: FLASH option clear control register
fields:
- name: CLR_OPTCHANGEERR
description: OPTCHANGEERR reset bit
bit_offset: 30
bit_size: 1
fieldset/OPTCR:
description: FLASH option control register
fields:
- name: OPTLOCK
description: FLASH_OPTCR lock option configuration bit
bit_offset: 0
bit_size: 1
- name: OPTSTART
description: Option byte start change option configuration bit
bit_offset: 1
bit_size: 1
- name: MER
description: Flash mass erase enable bit
bit_offset: 4
bit_size: 1
- name: PG_OTP
description: OTP program control bit
bit_offset: 5
bit_size: 1
- name: OPTCHANGEERRIE
description: Option byte change error interrupt enable bit
bit_offset: 30
bit_size: 1
- name: SWAP_BANK
description: Bank swapping configuration bit
bit_offset: 31
bit_size: 1
fieldset/OPTKEYR:
description: FLASH option key register
fields:
- name: OPTKEYR
description: Unlock key option bytes
bit_offset: 0
bit_size: 32
fieldset/OPTSR_CUR:
description: FLASH option status register
fields:
- name: OPT_BUSY
description: Option byte change ongoing flag
bit_offset: 0
bit_size: 1
- name: BOR_LEV
description: Brownout level option status bit
bit_offset: 2
bit_size: 2
- name: IWDG1_HW
description: IWDG1 control option status bit
bit_offset: 4
bit_size: 1
- name: nRST_STOP_D1
description: D1 DStop entry reset option status bit
bit_offset: 6
bit_size: 1
- name: nRST_STBY_D1
description: D1 DStandby entry reset option status bit
bit_offset: 7
bit_size: 1
- name: RDP
description: Readout protection level option status byte
bit_offset: 8
bit_size: 8
- name: FZ_IWDG_STOP
description: IWDG Stop mode freeze option status bit
bit_offset: 17
bit_size: 1
- name: FZ_IWDG_SDBY
description: IWDG Standby mode freeze option status bit
bit_offset: 18
bit_size: 1
- name: ST_RAM_SIZE
description: DTCM RAM size option status
bit_offset: 19
bit_size: 2
- name: SECURITY
description: Security enable option status bit
bit_offset: 21
bit_size: 1
- name: RSS1
description: User option bit 1
bit_offset: 26
bit_size: 1
- name: PERSO_OK
description: Device personalization status bit
bit_offset: 28
bit_size: 1
- name: IO_HSLV
description: I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V)
bit_offset: 29
bit_size: 1
- name: OPTCHANGEERR
description: Option byte change error flag
bit_offset: 30
bit_size: 1
- name: SWAP_BANK_OPT
description: Bank swapping option status bit
bit_offset: 31
bit_size: 1
fieldset/OPTSR_PRG:
description: FLASH option status register
fields:
- name: BOR_LEV
description: BOR reset level option configuration bits
bit_offset: 2
bit_size: 2
- name: IWDG1_HW
description: IWDG1 option configuration bit
bit_offset: 4
bit_size: 1
- name: nRST_STOP_D1
description: Option byte erase after D1 DStop option configuration bit
bit_offset: 6
bit_size: 1
- name: nRST_STBY_D1
description: Option byte erase after D1 DStandby option configuration bit
bit_offset: 7
bit_size: 1
- name: RDP
description: Readout protection level option configuration byte
bit_offset: 8
bit_size: 8
- name: FZ_IWDG_STOP
description: IWDG Stop mode freeze option configuration bit
bit_offset: 17
bit_size: 1
- name: FZ_IWDG_SDBY
description: IWDG Standby mode freeze option configuration bit
bit_offset: 18
bit_size: 1
- name: ST_RAM_SIZE
description: DTCM size select option configuration bits
bit_offset: 19
bit_size: 2
- name: SECURITY
description: Security option configuration bit
bit_offset: 21
bit_size: 1
- name: RSS1
description: User option configuration bit 1
bit_offset: 26
bit_size: 1
- name: RSS2
description: User option configuration bit 2
bit_offset: 27
bit_size: 1
- name: IO_HSLV
description: I/O high-speed at low-voltage (PRODUCT_BELOW_25V)
bit_offset: 29
bit_size: 1
- name: SWAP_BANK_OPT
description: Bank swapping option configuration bit
bit_offset: 31
bit_size: 1
fieldset/PRAR_CUR:
description: FLASH protection address for bank 1
fields:
- name: PROT_AREA_START
description: Bank 1 lowest PCROP protected address
bit_offset: 0
bit_size: 12
- name: PROT_AREA_END
description: Bank 1 highest PCROP protected address
bit_offset: 16
bit_size: 12
- name: DMEP
description: Bank 1 PCROP protected erase enable option status bit
bit_offset: 31
bit_size: 1
fieldset/PRAR_PRG:
description: FLASH protection address for bank 1
fields:
- name: PROT_AREA_START
description: Bank 1 lowest PCROP protected address configuration
bit_offset: 0
bit_size: 12
- name: PROT_AREA_END
description: Bank 1 highest PCROP protected address configuration
bit_offset: 16
bit_size: 12
- name: DMEP
description: Bank 1 PCROP protected erase enable option configuration bit
bit_offset: 31
bit_size: 1
fieldset/SCAR_CUR:
description: FLASH secure address for bank 1
fields:
- name: SEC_AREA_START
description: Bank 1 lowest secure protected address
bit_offset: 0
bit_size: 12
- name: SEC_AREA_END
description: Bank 1 highest secure protected address
bit_offset: 16
bit_size: 12
- name: DMES
description: Bank 1 secure protected erase enable option status bit
bit_offset: 31
bit_size: 1
fieldset/SCAR_PRG:
description: FLASH secure address for bank 1
fields:
- name: SEC_AREA_START
description: Bank 1 lowest secure protected address configuration
bit_offset: 0
bit_size: 12
- name: SEC_AREA_END
description: Bank 1 highest secure protected address configuration
bit_offset: 16
bit_size: 12
- name: DMES
description: Bank 1 secure protected erase enable option configuration bit
bit_offset: 31
bit_size: 1
fieldset/SR:
description: FLASH status register for bank 1
fields:
- name: BSY
description: Bank 1 ongoing program flag
bit_offset: 0
bit_size: 1
- name: WBNE
description: Bank 1 write buffer not empty flag
bit_offset: 1
bit_size: 1
- name: QW
description: Bank 1 wait queue flag
bit_offset: 2
bit_size: 1
- name: CRC_BUSY
description: Bank 1 CRC busy flag
bit_offset: 3
bit_size: 1
- name: EOP
description: Bank 1 end-of-program flag
bit_offset: 16
bit_size: 1
- name: WRPERR
description: Bank 1 write protection error flag
bit_offset: 17
bit_size: 1
- name: PGSERR
description: Bank 1 programming sequence error flag
bit_offset: 18
bit_size: 1
- name: STRBERR
description: Bank 1 strobe error flag
bit_offset: 19
bit_size: 1
- name: INCERR
description: Bank 1 inconsistency error flag
bit_offset: 21
bit_size: 1
- name: OPERR
description: Bank 1 write/erase error flag
bit_offset: 22
bit_size: 1
- name: RDPERR
description: Bank 1 read protection error flag
bit_offset: 23
bit_size: 1
- name: RDSERR
description: Bank 1 secure error flag
bit_offset: 24
bit_size: 1
- name: SNECCERR1
description: Bank 1 single correction error flag
bit_offset: 25
bit_size: 1
- name: DBECCERR
description: Bank 1 ECC double detection error flag
bit_offset: 26
bit_size: 1
- name: CRCEND
description: Bank 1 CRC-complete flag
bit_offset: 27
bit_size: 1
- name: CRCRDERR
description: Bank 1 CRC read error flag
bit_offset: 28
bit_size: 1
fieldset/WPSN_CURR:
description: FLASH write sector protection for bank 1
fields:
- name: WRPSn
description: Bank 1 sector write protection option status byte
bit_offset: 0
bit_size: 8
fieldset/WPSN_PRGR:
description: FLASH write sector protection for bank 1
fields:
- name: WRPSn
description: Bank 1 sector write protection configuration byte
bit_offset: 0
bit_size: 8

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data/registers/flash_l0.yaml
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@ -1,229 +1,228 @@
---
block/FLASH: block/FLASH:
description: Flash description: Flash
items: items:
- name: ACR - name: ACR
description: Access control register description: Access control register
byte_offset: 0 byte_offset: 0
fieldset: ACR fieldset: ACR
- name: PECR - name: PECR
description: Program/erase control register description: Program/erase control register
byte_offset: 4 byte_offset: 4
fieldset: PECR fieldset: PECR
- name: PDKEYR - name: PDKEYR
description: Power down key register description: Power down key register
byte_offset: 8 byte_offset: 8
access: Write access: Write
fieldset: PDKEYR fieldset: PDKEYR
- name: PEKEYR - name: PEKEYR
description: Program/erase key register description: Program/erase key register
byte_offset: 12 byte_offset: 12
access: Write access: Write
fieldset: PEKEYR fieldset: PEKEYR
- name: PRGKEYR - name: PRGKEYR
description: Program memory key register description: Program memory key register
byte_offset: 16 byte_offset: 16
access: Write access: Write
fieldset: PRGKEYR fieldset: PRGKEYR
- name: OPTKEYR - name: OPTKEYR
description: Option byte key register description: Option byte key register
byte_offset: 20 byte_offset: 20
access: Write access: Write
fieldset: OPTKEYR fieldset: OPTKEYR
- name: SR - name: SR
description: Status register description: Status register
byte_offset: 24 byte_offset: 24
fieldset: SR fieldset: SR
- name: OPTR - name: OPTR
description: Option byte register description: Option byte register
byte_offset: 28 byte_offset: 28
access: Read access: Read
fieldset: OPTR fieldset: OPTR
- name: WRPROT - name: WRPROT
description: Write Protection Register 1 description: Write Protection Register 1
byte_offset: 32 byte_offset: 32
access: Read access: Read
fieldset: WRPROT fieldset: WRPROT
- name: WRPROT2 - name: WRPROT2
description: Write Protection Register 2 description: Write Protection Register 2
byte_offset: 128 byte_offset: 128
access: Read access: Read
fieldset: WRPROT fieldset: WRPROT
fieldset/ACR: fieldset/ACR:
description: Access control register description: Access control register
fields: fields:
- name: LATENCY - name: LATENCY
description: Latency description: Latency
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: PRFTEN - name: PRFTEN
description: Prefetch enable description: Prefetch enable
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: SLEEP_PD - name: SLEEP_PD
description: Flash mode during Sleep description: Flash mode during Sleep
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: RUN_PD - name: RUN_PD
description: Flash mode during Run description: Flash mode during Run
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: DISAB_BUF - name: DISAB_BUF
description: Disable Buffer description: Disable Buffer
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: PRE_READ - name: PRE_READ
description: Pre-read data address description: Pre-read data address
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
fieldset/OPTKEYR: fieldset/OPTKEYR:
description: Option byte key register description: Option byte key register
fields: fields:
- name: OPTKEYR - name: OPTKEYR
description: Option byte key description: Option byte key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/OPTR: fieldset/OPTR:
description: Option byte register description: Option byte register
fields: fields:
- name: RDPROT - name: RDPROT
description: Read protection description: Read protection
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: WPRMOD - name: WPRMOD
description: Selection of protection mode of WPR bits description: Selection of protection mode of WPR bits
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: BOR_LEV - name: BOR_LEV
description: BOR_LEV description: BOR_LEV
bit_offset: 16 bit_offset: 16
bit_size: 4 bit_size: 4
fieldset/PDKEYR: fieldset/PDKEYR:
description: Power down key register description: Power down key register
fields: fields:
- name: PDKEYR - name: PDKEYR
description: RUN_PD in FLASH_ACR key description: RUN_PD in FLASH_ACR key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/PECR: fieldset/PECR:
description: Program/erase control register description: Program/erase control register
fields: fields:
- name: PELOCK - name: PELOCK
description: FLASH_PECR and data EEPROM lock description: FLASH_PECR and data EEPROM lock
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: PRGLOCK - name: PRGLOCK
description: Program memory lock description: Program memory lock
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: OPTLOCK - name: OPTLOCK
description: Option bytes block lock description: Option bytes block lock
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: PROG - name: PROG
description: Program memory selection description: Program memory selection
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: DATA - name: DATA
description: Data EEPROM selection description: Data EEPROM selection
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: FIX - name: FIX
description: "Fixed time data write for Byte, Half Word and Word programming" description: Fixed time data write for Byte, Half Word and Word programming
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: ERASE - name: ERASE
description: Page or Double Word erase mode description: Page or Double Word erase mode
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: FPRG - name: FPRG
description: Half Page/Double Word programming mode description: Half Page/Double Word programming mode
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: PARALLELBANK - name: PARALLELBANK
description: Parallel bank mode description: Parallel bank mode
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: EOPIE - name: EOPIE
description: End of programming interrupt enable description: End of programming interrupt enable
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: ERRIE - name: ERRIE
description: Error interrupt enable description: Error interrupt enable
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: OBL_LAUNCH - name: OBL_LAUNCH
description: Launch the option byte loading description: Launch the option byte loading
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/PEKEYR: fieldset/PEKEYR:
description: Program/erase key register description: Program/erase key register
fields: fields:
- name: PEKEYR - name: PEKEYR
description: FLASH_PEC and data EEPROM key description: FLASH_PEC and data EEPROM key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/PRGKEYR: fieldset/PRGKEYR:
description: Program memory key register description: Program memory key register
fields: fields:
- name: PRGKEYR - name: PRGKEYR
description: Program memory key description: Program memory key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/SR: fieldset/SR:
description: Status register description: Status register
fields: fields:
- name: BSY - name: BSY
description: Write/erase operations in progress description: Write/erase operations in progress
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: EOP - name: EOP
description: End of operation description: End of operation
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: ENDHV - name: ENDHV
description: End of high voltage description: End of high voltage
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: READY - name: READY
description: Flash memory module ready after low power mode description: Flash memory module ready after low power mode
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: WRPERR - name: WRPERR
description: Write protected error description: Write protected error
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: PGAERR - name: PGAERR
description: Programming alignment error description: Programming alignment error
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: SIZERR - name: SIZERR
description: Size error description: Size error
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: OPTVERR - name: OPTVERR
description: Option validity error description: Option validity error
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: RDERR - name: RDERR
description: RDERR description: RDERR
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: NOTZEROERR - name: NOTZEROERR
description: NOTZEROERR description: NOTZEROERR
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: FWWERR - name: FWWERR
description: FWWERR description: FWWERR
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
fieldset/WRPROT: fieldset/WRPROT:
description: Write Protection Register description: Write Protection Register
fields: fields:
- name: WRPROT - name: WRPROT
description: Write Protection description: Write Protection
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 32 len: 32
stride: 1 stride: 1

411
data/registers/flash_l1.yaml
View File

@ -1,242 +1,241 @@
---
block/FLASH: block/FLASH:
description: Flash description: Flash
items: items:
- name: ACR - name: ACR
description: Access control register description: Access control register
byte_offset: 0 byte_offset: 0
fieldset: ACR fieldset: ACR
- name: PECR - name: PECR
description: Program/erase control register description: Program/erase control register
byte_offset: 4 byte_offset: 4
fieldset: PECR fieldset: PECR
- name: PDKEYR - name: PDKEYR
description: Power down key register description: Power down key register
byte_offset: 8 byte_offset: 8
access: Write access: Write
fieldset: PDKEYR fieldset: PDKEYR
- name: PEKEYR - name: PEKEYR
description: Program/erase key register description: Program/erase key register
byte_offset: 12 byte_offset: 12
access: Write access: Write
fieldset: PEKEYR fieldset: PEKEYR
- name: PRGKEYR - name: PRGKEYR
description: Program memory key register description: Program memory key register
byte_offset: 16 byte_offset: 16
access: Write access: Write
fieldset: PRGKEYR fieldset: PRGKEYR
- name: OPTKEYR - name: OPTKEYR
description: Option byte key register description: Option byte key register
byte_offset: 20 byte_offset: 20
access: Write access: Write
fieldset: OPTKEYR fieldset: OPTKEYR
- name: SR - name: SR
description: Status register description: Status register
byte_offset: 24 byte_offset: 24
fieldset: SR fieldset: SR
- name: OBR - name: OBR
description: Option byte register description: Option byte register
byte_offset: 28 byte_offset: 28
access: Read access: Read
fieldset: OBR fieldset: OBR
- name: WRPR1 - name: WRPR1
description: Write protection register description: Write protection register
byte_offset: 32 byte_offset: 32
fieldset: WRPR1 fieldset: WRPR1
- name: WRPR2 - name: WRPR2
description: Write protection register description: Write protection register
byte_offset: 128 byte_offset: 128
fieldset: WRPR2 fieldset: WRPR2
- name: WRPR3 - name: WRPR3
description: Write protection register description: Write protection register
byte_offset: 132 byte_offset: 132
fieldset: WRPR3 fieldset: WRPR3
fieldset/ACR: fieldset/ACR:
description: Access control register description: Access control register
fields: fields:
- name: LATENCY - name: LATENCY
description: Latency description: Latency
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: PRFTEN - name: PRFTEN
description: Prefetch enable description: Prefetch enable
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: ACC64 - name: ACC64
description: 64-bit access description: 64-bit access
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: SLEEP_PD - name: SLEEP_PD
description: Flash mode during Sleep description: Flash mode during Sleep
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: RUN_PD - name: RUN_PD
description: Flash mode during Run description: Flash mode during Run
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
fieldset/OBR: fieldset/OBR:
description: Option byte register description: Option byte register
fields: fields:
- name: RDPRT - name: RDPRT
description: Read protection description: Read protection
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: BOR_LEV - name: BOR_LEV
description: BOR_LEV description: BOR_LEV
bit_offset: 16 bit_offset: 16
bit_size: 4 bit_size: 4
- name: IWDG_SW - name: IWDG_SW
description: IWDG_SW description: IWDG_SW
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
- name: nRTS_STOP - name: nRTS_STOP
description: nRTS_STOP description: nRTS_STOP
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: nRST_STDBY - name: nRST_STDBY
description: nRST_STDBY description: nRST_STDBY
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: BFB2 - name: BFB2
description: Boot From Bank 2 description: Boot From Bank 2
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
fieldset/OPTKEYR: fieldset/OPTKEYR:
description: Option byte key register description: Option byte key register
fields: fields:
- name: OPTKEYR - name: OPTKEYR
description: Option byte key description: Option byte key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/PDKEYR: fieldset/PDKEYR:
description: Power down key register description: Power down key register
fields: fields:
- name: PDKEYR - name: PDKEYR
description: RUN_PD in FLASH_ACR key description: RUN_PD in FLASH_ACR key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/PECR: fieldset/PECR:
description: Program/erase control register description: Program/erase control register
fields: fields:
- name: PELOCK - name: PELOCK
description: FLASH_PECR and data EEPROM lock description: FLASH_PECR and data EEPROM lock
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: PRGLOCK - name: PRGLOCK
description: Program memory lock description: Program memory lock
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: OPTLOCK - name: OPTLOCK
description: Option bytes block lock description: Option bytes block lock
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: PROG - name: PROG
description: Program memory selection description: Program memory selection
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: DATA - name: DATA
description: Data EEPROM selection description: Data EEPROM selection
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: FTDW - name: FTDW
description: "Fixed time data write for Byte, Half Word and Word programming" description: Fixed time data write for Byte, Half Word and Word programming
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: ERASE - name: ERASE
description: Page or Double Word erase mode description: Page or Double Word erase mode
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: FPRG - name: FPRG
description: Half Page/Double Word programming mode description: Half Page/Double Word programming mode
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: PARALLELBANK - name: PARALLELBANK
description: Parallel bank mode description: Parallel bank mode
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: EOPIE - name: EOPIE
description: End of programming interrupt enable description: End of programming interrupt enable
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: ERRIE - name: ERRIE
description: Error interrupt enable description: Error interrupt enable
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: OBL_LAUNCH - name: OBL_LAUNCH
description: Launch the option byte loading description: Launch the option byte loading
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
fieldset/PEKEYR: fieldset/PEKEYR:
description: Program/erase key register description: Program/erase key register
fields: fields:
- name: PEKEYR - name: PEKEYR
description: FLASH_PEC and data EEPROM key description: FLASH_PEC and data EEPROM key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/PRGKEYR: fieldset/PRGKEYR:
description: Program memory key register description: Program memory key register
fields: fields:
- name: PRGKEYR - name: PRGKEYR
description: Program memory key description: Program memory key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/SR: fieldset/SR:
description: Status register description: Status register
fields: fields:
- name: BSY - name: BSY
description: Write/erase operations in progress description: Write/erase operations in progress
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: EOP - name: EOP
description: End of operation description: End of operation
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: ENDHV - name: ENDHV
description: End of high voltage description: End of high voltage
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: READY - name: READY
description: Flash memory module ready after low power mode description: Flash memory module ready after low power mode
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: WRPERR - name: WRPERR
description: Write protected error description: Write protected error
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: PGAERR - name: PGAERR
description: Programming alignment error description: Programming alignment error
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: SIZERR - name: SIZERR
description: Size error description: Size error
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: OPTVERR - name: OPTVERR
description: Option validity error description: Option validity error
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: OPTVERRUSR - name: OPTVERRUSR
description: Option UserValidity Error description: Option UserValidity Error
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
fieldset/WRPR1: fieldset/WRPR1:
description: Write protection register description: Write protection register
fields: fields:
- name: WRP1 - name: WRP1
description: Write protection description: Write protection
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/WRPR2: fieldset/WRPR2:
description: Write protection register description: Write protection register
fields: fields:
- name: WRP2 - name: WRP2
description: WRP2 description: WRP2
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/WRPR3: fieldset/WRPR3:
description: Write protection register description: Write protection register
fields: fields:
- name: WRP3 - name: WRP3
description: WRP3 description: WRP3
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32

709
data/registers/flash_l4.yaml
View File

@ -1,406 +1,405 @@
---
block/FLASH: block/FLASH:
description: Flash description: Flash
items: items:
- name: ACR - name: ACR
description: Access control register description: Access control register
byte_offset: 0 byte_offset: 0
fieldset: ACR fieldset: ACR
- name: PDKEYR - name: PDKEYR
description: Power down key register description: Power down key register
byte_offset: 4 byte_offset: 4
access: Write access: Write
fieldset: PDKEYR fieldset: PDKEYR
- name: KEYR - name: KEYR
description: Flash key register description: Flash key register
byte_offset: 8 byte_offset: 8
access: Write access: Write
fieldset: KEYR fieldset: KEYR
- name: OPTKEYR - name: OPTKEYR
description: Option byte key register description: Option byte key register
byte_offset: 12 byte_offset: 12
access: Write access: Write
fieldset: OPTKEYR fieldset: OPTKEYR
- name: SR - name: SR
description: Status register description: Status register
byte_offset: 16 byte_offset: 16
fieldset: SR fieldset: SR
- name: CR - name: CR
description: Flash control register description: Flash control register
byte_offset: 20 byte_offset: 20
fieldset: CR fieldset: CR
- name: ECCR - name: ECCR
description: Flash ECC register description: Flash ECC register
byte_offset: 24 byte_offset: 24
fieldset: ECCR fieldset: ECCR
- name: OPTR - name: OPTR
description: Flash option register description: Flash option register
byte_offset: 32 byte_offset: 32
fieldset: OPTR fieldset: OPTR
- name: PCROP1SR - name: PCROP1SR
description: Flash Bank 1 PCROP Start address register description: Flash Bank 1 PCROP Start address register
byte_offset: 36 byte_offset: 36
fieldset: PCROP1SR fieldset: PCROP1SR
- name: PCROP1ER - name: PCROP1ER
description: Flash Bank 1 PCROP End address register description: Flash Bank 1 PCROP End address register
byte_offset: 40 byte_offset: 40
fieldset: PCROP1ER fieldset: PCROP1ER
- name: WRP1AR - name: WRP1AR
description: Flash Bank 1 WRP area A address register description: Flash Bank 1 WRP area A address register
byte_offset: 44 byte_offset: 44
fieldset: WRP1AR fieldset: WRP1AR
- name: WRP1BR - name: WRP1BR
description: Flash Bank 1 WRP area B address register description: Flash Bank 1 WRP area B address register
byte_offset: 48 byte_offset: 48
fieldset: WRP1BR fieldset: WRP1BR
- name: PCROP2SR - name: PCROP2SR
description: Flash Bank 2 PCROP Start address register description: Flash Bank 2 PCROP Start address register
byte_offset: 68 byte_offset: 68
fieldset: PCROP2SR fieldset: PCROP2SR
- name: PCROP2ER - name: PCROP2ER
description: Flash Bank 2 PCROP End address register description: Flash Bank 2 PCROP End address register
byte_offset: 72 byte_offset: 72
fieldset: PCROP2ER fieldset: PCROP2ER
- name: WRP2AR - name: WRP2AR
description: Flash Bank 2 WRP area A address register description: Flash Bank 2 WRP area A address register
byte_offset: 76 byte_offset: 76
fieldset: WRP2AR fieldset: WRP2AR
- name: WRP2BR - name: WRP2BR
description: Flash Bank 2 WRP area B address register description: Flash Bank 2 WRP area B address register
byte_offset: 80 byte_offset: 80
fieldset: WRP2BR fieldset: WRP2BR
fieldset/ACR: fieldset/ACR:
description: Access control register description: Access control register
fields: fields:
- name: LATENCY - name: LATENCY
description: Latency description: Latency
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
- name: PRFTEN - name: PRFTEN
description: Prefetch enable description: Prefetch enable
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: ICEN - name: ICEN
description: Instruction cache enable description: Instruction cache enable
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: DCEN - name: DCEN
description: Data cache enable description: Data cache enable
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: ICRST - name: ICRST
description: Instruction cache reset description: Instruction cache reset
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: DCRST - name: DCRST
description: Data cache reset description: Data cache reset
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: RUN_PD - name: RUN_PD
description: Flash Power-down mode during Low-power run mode description: Flash Power-down mode during Low-power run mode
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: SLEEP_PD - name: SLEEP_PD
description: Flash Power-down mode during Low-power sleep mode description: Flash Power-down mode during Low-power sleep mode
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
fieldset/CR: fieldset/CR:
description: Flash control register description: Flash control register
fields: fields:
- name: PG - name: PG
description: Programming description: Programming
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: PER - name: PER
description: Page erase description: Page erase
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: MER - name: MER
description: Bank 1 Mass erase description: Bank 1 Mass erase
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 13 stride: 13
- name: PNB - name: PNB
description: Page number description: Page number
bit_offset: 3 bit_offset: 3
bit_size: 8 bit_size: 8
- name: BKER - name: BKER
description: Bank erase description: Bank erase
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: START - name: START
description: Start description: Start
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: OPTSTRT - name: OPTSTRT
description: Options modification start description: Options modification start
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: FSTPG - name: FSTPG
description: Fast programming description: Fast programming
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
- name: EOPIE - name: EOPIE
description: End of operation interrupt enable description: End of operation interrupt enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: ERRIE - name: ERRIE
description: Error interrupt enable description: Error interrupt enable
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: RDERRIE - name: RDERRIE
description: PCROP read error interrupt enable description: PCROP read error interrupt enable
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
- name: OBL_LAUNCH - name: OBL_LAUNCH
description: Force the option byte loading description: Force the option byte loading
bit_offset: 27 bit_offset: 27
bit_size: 1 bit_size: 1
- name: OPTLOCK - name: OPTLOCK
description: Options Lock description: Options Lock
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
- name: LOCK - name: LOCK
description: FLASH_CR Lock description: FLASH_CR Lock
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/ECCR: fieldset/ECCR:
description: Flash ECC register description: Flash ECC register
fields: fields:
- name: ADDR_ECC - name: ADDR_ECC
description: ECC fail address description: ECC fail address
bit_offset: 0 bit_offset: 0
bit_size: 19 bit_size: 19
- name: BK_ECC - name: BK_ECC
description: ECC fail bank description: ECC fail bank
bit_offset: 19 bit_offset: 19
bit_size: 1 bit_size: 1
- name: SYSF_ECC - name: SYSF_ECC
description: System Flash ECC fail description: System Flash ECC fail
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
- name: ECCIE - name: ECCIE
description: ECC correction interrupt enable description: ECC correction interrupt enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: ECCC - name: ECCC
description: ECC correction description: ECC correction
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
- name: ECCD - name: ECCD
description: ECC detection description: ECC detection
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/KEYR: fieldset/KEYR:
description: Flash key register description: Flash key register
fields: fields:
- name: KEYR - name: KEYR
description: KEYR description: KEYR
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/OPTKEYR: fieldset/OPTKEYR:
description: Option byte key register description: Option byte key register
fields: fields:
- name: OPTKEYR - name: OPTKEYR
description: Option byte key description: Option byte key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/OPTR: fieldset/OPTR:
description: Flash option register description: Flash option register
fields: fields:
- name: RDP - name: RDP
description: Read protection level description: Read protection level
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: BOR_LEV - name: BOR_LEV
description: BOR reset Level description: BOR reset Level
bit_offset: 8 bit_offset: 8
bit_size: 3 bit_size: 3
- name: nRST_STOP - name: nRST_STOP
description: nRST_STOP description: nRST_STOP
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: nRST_STDBY - name: nRST_STDBY
description: nRST_STDBY description: nRST_STDBY
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: IDWG_SW - name: IDWG_SW
description: Independent watchdog selection description: Independent watchdog selection
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: IWDG_STOP - name: IWDG_STOP
description: Independent watchdog counter freeze in Stop mode description: Independent watchdog counter freeze in Stop mode
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: IWDG_STDBY - name: IWDG_STDBY
description: Independent watchdog counter freeze in Standby mode description: Independent watchdog counter freeze in Standby mode
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
- name: WWDG_SW - name: WWDG_SW
description: Window watchdog selection description: Window watchdog selection
bit_offset: 19 bit_offset: 19
bit_size: 1 bit_size: 1
- name: BFB - name: BFB
description: Dual-bank boot description: Dual-bank boot
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
- name: DUALBANK - name: DUALBANK
description: Dual-Bank on 512 KB or 256 KB Flash memory devices description: Dual-Bank on 512 KB or 256 KB Flash memory devices
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: nBOOT1 - name: nBOOT1
description: Boot configuration description: Boot configuration
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: SRAM2_PE - name: SRAM2_PE
description: SRAM2 parity check enable description: SRAM2 parity check enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: SRAM2_RST - name: SRAM2_RST
description: SRAM2 Erase when system reset description: SRAM2 Erase when system reset
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: nSWBOOT0 - name: nSWBOOT0
description: Software BOOT0 description: Software BOOT0
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
- name: nBOOT0 - name: nBOOT0
description: nBOOT0 option bit description: nBOOT0 option bit
bit_offset: 27 bit_offset: 27
bit_size: 1 bit_size: 1
fieldset/PCROP1ER: fieldset/PCROP1ER:
description: Flash Bank 1 PCROP End address register description: Flash Bank 1 PCROP End address register
fields: fields:
- name: PCROP1_END - name: PCROP1_END
description: Bank 1 PCROP area end offset description: Bank 1 PCROP area end offset
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
- name: PCROP_RDP - name: PCROP_RDP
description: PCROP area preserved when RDP level decreased description: PCROP area preserved when RDP level decreased
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/PCROP1SR: fieldset/PCROP1SR:
description: Flash Bank 1 PCROP Start address register description: Flash Bank 1 PCROP Start address register
fields: fields:
- name: PCROP1_STRT - name: PCROP1_STRT
description: Bank 1 PCROP area start offset description: Bank 1 PCROP area start offset
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
fieldset/PCROP2ER: fieldset/PCROP2ER:
description: Flash Bank 2 PCROP End address register description: Flash Bank 2 PCROP End address register
fields: fields:
- name: PCROP2_END - name: PCROP2_END
description: Bank 2 PCROP area end offset description: Bank 2 PCROP area end offset
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
fieldset/PCROP2SR: fieldset/PCROP2SR:
description: Flash Bank 2 PCROP Start address register description: Flash Bank 2 PCROP Start address register
fields: fields:
- name: PCROP2_STRT - name: PCROP2_STRT
description: Bank 2 PCROP area start offset description: Bank 2 PCROP area start offset
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
fieldset/PDKEYR: fieldset/PDKEYR:
description: Power down key register description: Power down key register
fields: fields:
- name: PDKEYR - name: PDKEYR
description: RUN_PD in FLASH_ACR key description: RUN_PD in FLASH_ACR key
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/SR: fieldset/SR:
description: Status register description: Status register
fields: fields:
- name: EOP - name: EOP
description: End of operation description: End of operation
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: OPERR - name: OPERR
description: Operation error description: Operation error
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: PROGERR - name: PROGERR
description: Programming error description: Programming error
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: WRPERR - name: WRPERR
description: Write protected error description: Write protected error
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: PGAERR - name: PGAERR
description: Programming alignment error description: Programming alignment error
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: SIZERR - name: SIZERR
description: Size error description: Size error
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: PGSERR - name: PGSERR
description: Programming sequence error description: Programming sequence error
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: MISERR - name: MISERR
description: Fast programming data miss error description: Fast programming data miss error
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: FASTERR - name: FASTERR
description: Fast programming error description: Fast programming error
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: RDERR - name: RDERR
description: PCROP read error description: PCROP read error
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: OPTVERR - name: OPTVERR
description: Option validity error description: Option validity error
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: BSY - name: BSY
description: Busy description: Busy
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
fieldset/WRP1AR: fieldset/WRP1AR:
description: Flash Bank 1 WRP area A address register description: Flash Bank 1 WRP area A address register
fields: fields:
- name: WRP1A_STRT - name: WRP1A_STRT
description: Bank 1 WRP first area tart offset description: Bank 1 WRP first area tart offset
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: WRP1A_END - name: WRP1A_END
description: Bank 1 WRP first area A end offset description: Bank 1 WRP first area A end offset
bit_offset: 16 bit_offset: 16
bit_size: 8 bit_size: 8
fieldset/WRP1BR: fieldset/WRP1BR:
description: Flash Bank 1 WRP area B address register description: Flash Bank 1 WRP area B address register
fields: fields:
- name: WRP1B_STRT - name: WRP1B_STRT
description: Bank 1 WRP second area B start offset description: Bank 1 WRP second area B start offset
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: WRP1B_END - name: WRP1B_END
description: Bank 1 WRP second area B end offset description: Bank 1 WRP second area B end offset
bit_offset: 16 bit_offset: 16
bit_size: 8 bit_size: 8
fieldset/WRP2AR: fieldset/WRP2AR:
description: Flash Bank 2 WRP area A address register description: Flash Bank 2 WRP area A address register
fields: fields:
- name: WRP2A_STRT - name: WRP2A_STRT
description: Bank 2 WRP first area A start offset description: Bank 2 WRP first area A start offset
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: WRP2A_END - name: WRP2A_END
description: Bank 2 WRP first area A end offset description: Bank 2 WRP first area A end offset
bit_offset: 16 bit_offset: 16
bit_size: 8 bit_size: 8
fieldset/WRP2BR: fieldset/WRP2BR:
description: Flash Bank 2 WRP area B address register description: Flash Bank 2 WRP area B address register
fields: fields:
- name: WRP2B_STRT - name: WRP2B_STRT
description: Bank 2 WRP second area B start offset description: Bank 2 WRP second area B start offset
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: WRP2B_END - name: WRP2B_END
description: Bank 2 WRP second area B end offset description: Bank 2 WRP second area B end offset
bit_offset: 16 bit_offset: 16
bit_size: 8 bit_size: 8

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block/FLASH:
description: Embedded memory
items:
- name: ACR
description: access control register
byte_offset: 0
fieldset: ACR
- name: NSKEYR
description: key register
byte_offset: 8
fieldset: NSKEYR
- name: SECKEYR
description: secure key register
byte_offset: 12
fieldset: SECKEYR
- name: OPTKEYR
description: option key register
byte_offset: 16
fieldset: OPTKEYR
- name: PDKEYR
description: power-down key register
byte_offset: 24
fieldset: PDKEYR
- name: NSSR
description: status register
byte_offset: 32
fieldset: NSSR
- name: SECSR
description: secure status register
byte_offset: 36
fieldset: SECSR
- name: NSCR1
description: control register
byte_offset: 40
fieldset: NSCR1
- name: SECCR1
description: secure control register
byte_offset: 44
fieldset: SECCR1
- name: ECCR
description: ECC register
byte_offset: 48
fieldset: ECCR
- name: OPSR
description: operation status register
byte_offset: 52
fieldset: OPSR
- name: NSCR2
description: control 2 register
byte_offset: 56
fieldset: NSCR2
- name: SECCR2
description: secure control 2 register
byte_offset: 60
fieldset: SECCR2
- name: OPTR
description: option register
byte_offset: 64
fieldset: OPTR
- name: NSBOOTADD0R
description: boot address 0 register
byte_offset: 68
fieldset: NSBOOTADD0R
- name: NSBOOTADD1R
description: boot address 1 register
byte_offset: 72
fieldset: NSBOOTADD1R
- name: SECBOOTADD0R
description: secure boot address 0 register
byte_offset: 76
fieldset: SECBOOTADD0R
- name: SECWMR1
description: secure watermark register 1
byte_offset: 80
fieldset: SECWMR1
- name: SECWMR2
description: secure watermark register 2
byte_offset: 84
fieldset: SECWMR2
- name: WRPAR
description: WRP area A address register
byte_offset: 88
fieldset: WRPAR
- name: WRPBR
description: WRP area B address register
byte_offset: 92
fieldset: WRPBR
- name: OEM1KEYR1
description: OEM1 key register 1
byte_offset: 112
- name: OEM1KEYR2
description: OEM1 key register 2
byte_offset: 116
- name: OEM2KEYR1
description: OEM2 key register 1
byte_offset: 120
- name: OEM2KEYR2
description: OEM2 key register 2
byte_offset: 124
- name: SECBBR
description: secure block based register 1
array:
len: 4
stride: 4
byte_offset: 128
fieldset: BBR
- name: SECHDPCR
description: secure HDP control register
byte_offset: 192
fieldset: SECHDPCR
- name: PRIFCFGR
description: privilege configuration register
byte_offset: 196
fieldset: PRIFCFGR
- name: PRIVBBR
description: privilege block based register 1
array:
len: 4
stride: 4
byte_offset: 208
fieldset: BBR
fieldset/ACR:
description: access control register
fields:
- name: LATENCY
description: "Latency\r These bits represent the ratio between the AHB hclk1 clock period and the memory access time.\r Access to the bit can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r ...\r Note: Before entering Stop 1 mode software must set wait state latency to at least 1."
bit_offset: 0
bit_size: 4
- name: PRFTEN
description: "Prefetch enable\r This bit enables the prefetch buffer in the embedded memory.\r This bit can be protected against unprivileged access by NSPRIV."
bit_offset: 8
bit_size: 1
- name: LPM
description: "Low-power read mode\r This bit puts the memory in low-power read mode.\r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r This bit can’t be written when a program or erase operation is busy (BSY = 1) or when the write buffer is not empty (WDW = 1). Changing this bit while a program or erase operation is busy (BSY = 1) is rejected."
bit_offset: 11
bit_size: 1
- name: PDREQ
description: "power-down mode request\r This bit requests to enter power-down mode. When enters power-down mode, this bit is cleared by hardware and the PDKEYR is locked.\r This bit is write-protected with PDKEYR. \r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
bit_offset: 12
bit_size: 1
- name: SLEEP_PD
description: "memory power-down mode during Sleep mode\r This bit determines whether the memory is in power-down mode or Idle mode when the device is in Sleep mode.\r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r The must not be put in power-down while a program or an erase operation is ongoing."
bit_offset: 14
bit_size: 1
fieldset/BBR:
description: block based register
fields:
- name: BLOCK
bit_offset: 0
bit_size: 1
array:
len: 32
stride: 1
fieldset/ECCR:
description: ECC register
fields:
- name: ADDR_ECC
description: "ECC fail address\r This field indicates which address is concerned by the ECC error correction or by the double ECC error detection. The address is given relative to base address, from offset 0x0<78>0000 to 0xF<78>FFF0.\r Note that bit 19 is reserved on STM32WBAxEx devices."
bit_offset: 0
bit_size: 20
- name: SYSF_ECC
description: "System memory ECC fail\r This bit indicates that the ECC error correction or double ECC error detection is located in the system memory."
bit_offset: 22
bit_size: 1
- name: ECCIE
description: "ECC correction interrupt enable\r This bit enables the interrupt generation when the ECCC bit in the ECCR register is set."
bit_offset: 24
bit_size: 1
- name: ECCC
description: "ECC correction\r This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1."
bit_offset: 30
bit_size: 1
- name: ECCD
description: "ECC detection\r This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1."
bit_offset: 31
bit_size: 1
fieldset/NSBOOTADD0R:
description: boot address 0 register
fields:
- name: NSBOOTADD0
description: "Non-secure boot base address 0\r This address is only used when TZEN = 0.\r The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state.\r Examples:\r NSBOOTADD0[24:0] = 0x0100000: Boot from memory (0x0800 0000)\r NSBOOTADD0[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000)\r NSBOOTADD0[24:0] = 0x0400200: Boot from SRAM2 on S-Bus (0x2001 0000)"
bit_offset: 7
bit_size: 25
fieldset/NSBOOTADD1R:
description: boot address 1 register
fields:
- name: NSBOOTADD1
description: "Non-secure boot address 1\r This address is only used when TZEN = 0.\r The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. \r Examples:\r NSBOOTADD1[24:0] = 0x0100000: Boot from memory (0x0800 0000)\r NSBOOTADD1[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000)\r NSBOOTADD1[24:0] = 0x0400200: Boot from SRAM2 (0x2001 0000)"
bit_offset: 7
bit_size: 25
fieldset/NSCR1:
description: control register
fields:
- name: PG
description: Non-secure programming
bit_offset: 0
bit_size: 1
- name: PER
description: Non-secure page erase
bit_offset: 1
bit_size: 1
- name: MER
description: "Non-secure mass erase\r This bit triggers the non-secure mass erase (all user pages) when set."
bit_offset: 2
bit_size: 1
- name: PNB
description: "Non-secure page number selection\r These bits select the page to erase.\r ...\r Note that bit 9 is reserved on STM32WBA5xEx devices."
bit_offset: 3
bit_size: 7
- name: BWR
description: "Non-secure burst write programming mode\r When set, this bit selects the burst write programming mode."
bit_offset: 14
bit_size: 1
- name: STRT
description: "Non-secure operation start \r This bit triggers a non-secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR bit in NSSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in NSSR."
bit_offset: 16
bit_size: 1
- name: OPTSTRT
description: "Options modification start\r This bit triggers an option bytes erase and program operation when set. This bit is write-protected with OPTLOCK.. This bit is set only by software, and is cleared when the BSY bit is cleared in NSSR."
bit_offset: 17
bit_size: 1
- name: EOPIE
description: "Non-secure end of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in the NSSR is set to 1."
bit_offset: 24
bit_size: 1
- name: ERRIE
description: "Non-secure error interrupt enable\r This bit enables the interrupt generation when the OPERR bit in the NSSR is set to 1."
bit_offset: 25
bit_size: 1
- name: OBL_LAUNCH
description: "Force the option byte loading\r When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. This bit is write-protected with OPTLOCK.\r Note: The LSE oscillator must be disabled, LSEON = 0 and LSERDY = 0, before starting OBL_LAUNCH."
bit_offset: 27
bit_size: 1
- name: OPTLOCK
description: "Option lock\r This bit is set only. When set, the NSCR1.OPTSRT and OBL_LAUNCH bits concerning user options write access is locked. This bit is cleared by hardware after detecting the unlock sequence in OPTKEYR. The NSCR1.LOCK bit must be cleared before doing the OPTKEYR unlock sequence.\r In case of an unsuccessful unlock operation, this bit remains set until the next reset."
bit_offset: 30
bit_size: 1
- name: LOCK
description: "Non-secure lock\r This bit is set only.\r When set, the NSCR1 register write access is locked. This bit is cleared by hardware after detecting the unlock sequence in NSKEYR.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset."
bit_offset: 31
bit_size: 1
fieldset/NSCR2:
description: control 2 register
fields:
- name: PS
description: Program suspend request
bit_offset: 0
bit_size: 1
- name: ES
description: Erase suspend request
bit_offset: 1
bit_size: 1
fieldset/NSKEYR:
description: key register
fields:
- name: NSKEY
description: "memory non-secure key\r The following values must be written consecutively to unlock the NSCR1 register, allowing the memory non-secure programming/erasing operations:\r KEY1: 0x4567<36>0123\r KEY2: 0xCDEF<45>89AB"
bit_offset: 0
bit_size: 32
fieldset/NSSR:
description: status register
fields:
- name: EOP
description: "Non-secure end of operation\r This bit is set by hardware when one or more memory non-secure operation (program/erase) has been completed successfully. This bit is set only if the non-secure end of operation interrupts are enabled (EOPIE = 1 in NSCR1). This bit is cleared by writing<6E>1."
bit_offset: 0
bit_size: 1
- name: OPERR
description: "Non-secure operation error\r This bit is set by hardware when a memory non-secure operation (program/erase) completes unsuccessfully. This bit is set only if non-secure error interrupts are enabled (NSERRIE = 1). This bit is cleared by writing 1."
bit_offset: 1
bit_size: 1
- name: PROGERR
description: "Non-secure programming error\r This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1."
bit_offset: 3
bit_size: 1
- name: WRPERR
description: "Non-secure write protection error\r This bit is set by hardware when a non-secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
bit_offset: 4
bit_size: 1
- name: PGAERR
description: "Non-secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1."
bit_offset: 5
bit_size: 1
- name: SIZERR
description: "Non-secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1."
bit_offset: 6
bit_size: 1
- name: PGSERR
description: "Non-secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
bit_offset: 7
bit_size: 1
- name: OPTWERR
description: "Option write error \r This bit is set by hardware when the options bytes are written with an invalid configuration or when modifying options in RDP level 2.. It is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
bit_offset: 13
bit_size: 1
- name: BSY
description: "Non-secure busy\r This indicates that a memory secure or non-secure operation is in progress. This bit is set at the beginning of a operation and reset when the operation finishes or when an error occurs."
bit_offset: 16
bit_size: 1
- name: WDW
description: "Non-secure wait data to write\r This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory."
bit_offset: 17
bit_size: 1
- name: OEM1LOCK
description: "OEM1 key RDP lock\r This bit indicates that the OEM1 key read during the OBL is not virgin. When set, the OEM1 key RDP lock mechanism is active."
bit_offset: 18
bit_size: 1
- name: OEM2LOCK
description: "OEM2 key RDP lock\r This bit indicates that the OEM2 key read during the OBL is not virgin. When set, the OEM2 key RDP lock mechanism is active."
bit_offset: 19
bit_size: 1
- name: PD
description: "in power-down mode\r This bit indicates that the memory is in power-down state. It is reset when is in normal mode or being awaken."
bit_offset: 20
bit_size: 1
fieldset/OPSR:
description: operation status register
fields:
- name: ADDR_OP
description: "Interrupted operation address\r This field indicates which address in the memory was accessed when reset occurred. The address is given relative to the base address, from offset 0x0<78>0000 to 0xF<78>FFF0.\r Note that bit 19 is reserved on STM32WBAxEx devices."
bit_offset: 0
bit_size: 20
- name: SYSF_OP
description: "Operation in system memory interrupted\r This bit indicates that the reset occurred during an operation in the system memory."
bit_offset: 22
bit_size: 1
- name: CODE_OP
description: "memory operation code\r This field indicates which memory operation has been interrupted by a system reset:"
bit_offset: 29
bit_size: 3
enum: CODE_OP
fieldset/OPTKEYR:
description: option key register
fields:
- name: OPTKEY
description: "Option byte key\r The LOCK bit in the NSCR1 must be cleared before doing the unlock sequence for OPTLOCK bit. The following values must be written consecutively to unlock the NSCR1.OPTSTRT and OBL_LAUNCH register bits concerning user option operations:\r KEY1: 0x0819<31>2A3B\r KEY2: 0x4C5D<35>6E7F"
bit_offset: 0
bit_size: 32
fieldset/OPTR:
description: option register
fields:
- name: RDP
description: "Readout protection level\r Others: Level 1 (memories readout protection active)\r Note: Refer to Section<6F>7.6.2: Readout protection (RDP) for more details."
bit_offset: 0
bit_size: 8
enum: RDP
- name: BOR_LEV
description: "BOR reset level\r These bits contain the V<sub>DD</sub> supply level threshold that activates/releases the reset."
bit_offset: 8
bit_size: 3
enum: BOR_LEV
- name: NRST_STOP
description: Reset generation in Stop mode
bit_offset: 12
bit_size: 1
- name: NRST_STDBY
description: Reset generation in Standby mode
bit_offset: 13
bit_size: 1
- name: SRAM1_RST
description: SRAM1 erase upon system reset
bit_offset: 15
bit_size: 1
- name: IWDG_SW
description: Independent watchdog enable selection
bit_offset: 16
bit_size: 1
- name: IWDG_STOP
description: Independent watchdog counter freeze in Stop mode
bit_offset: 17
bit_size: 1
- name: IWDG_STDBY
description: Independent watchdog counter freeze in Standby mode
bit_offset: 18
bit_size: 1
- name: WWDG_SW
description: Window watchdog selection
bit_offset: 19
bit_size: 1
- name: SRAM2_PE
description: SRAM2 parity check enable
bit_offset: 24
bit_size: 1
- name: SRAM2_RST
description: SRAM2 erase when system reset
bit_offset: 25
bit_size: 1
- name: NSWBOOT0
description: Software BOOT0
bit_offset: 26
bit_size: 1
- name: NBOOT0
description: NBOOT0 option bit
bit_offset: 27
bit_size: 1
- name: TZEN
description: Global TrustZone security enable
bit_offset: 31
bit_size: 1
fieldset/PDKEYR:
description: power-down key register
fields:
- name: PDKEY1
description: "power-down key\r The following values must be written consecutively to unlock the PDREQ bit in ACR:\r PDKEY_1: 0x0415<31>2637\r PDKEY_2: 0xFAFB<46>FCFD"
bit_offset: 0
bit_size: 32
fieldset/PRIFCFGR:
description: privilege configuration register
fields:
- name: SPRIV
description: "Privileged protection for secure registers\r This bit is secure write protected. It can only be written by a secure privileged access when TrustZone is enabled (TZEN<45>=<3D>1)."
bit_offset: 0
bit_size: 1
- name: NSPRIV
description: Privileged protection for non-secure registers
bit_offset: 1
bit_size: 1
fieldset/SECBOOTADD0R:
description: secure boot address 0 register
fields:
- name: BOOT_LOCK
description: "Boot lock\r This lock is only used when TZEN = 0.\r When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP regression level 1 to level 0."
bit_offset: 0
bit_size: 1
- name: SECBOOTADD0
description: "Secure boot base address 0\r This address is only used when TZEN = 1.\r The secure boot memory address can be programmed to any address in the valid address range (see Table<6C>28: Boot space versus RDP protection) with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. \r Examples:\r SECBOOTADD0[24:0] = 0x018 0000: Boot from secure user memory (0x0C00 0000)\r SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS system memory (0x0FF8 0000)\r SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000)"
bit_offset: 7
bit_size: 25
fieldset/SECCR1:
description: secure control register
fields:
- name: PG
description: Secure programming
bit_offset: 0
bit_size: 1
- name: PER
description: Secure page erase
bit_offset: 1
bit_size: 1
- name: MER
description: "Secure mass erase\r This bit triggers the secure mass erase (all user pages) when set."
bit_offset: 2
bit_size: 1
- name: PNB
description: "Secure page number selection\r These bits select the page to erase:\r ...\r Note that bit 9 is reserved on STM32WBA5xEx devices."
bit_offset: 3
bit_size: 7
- name: BWR
description: "Secure burst write programming mode\r When set, this bit selects the burst write programming mode."
bit_offset: 14
bit_size: 1
- name: STRT
description: "Secure start \r This bit triggers a secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR in the SECSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in SECSR."
bit_offset: 16
bit_size: 1
- name: EOPIE
description: "Secure End of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in SECSR is set to 1."
bit_offset: 24
bit_size: 1
- name: ERRIE
description: "Secure error interrupt enable\r This bit enables the interrupt generation when the OPERR bit in SECSR is set to 1."
bit_offset: 25
bit_size: 1
- name: INV
description: "memory security state invert\r This bit inverts the memory security state."
bit_offset: 29
bit_size: 1
- name: LOCK
description: "Secure lock\r This bit is set only. When set, the SECCR1 register is locked. It is cleared by hardware after detecting the unlock sequence in SECKEYR register.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset."
bit_offset: 31
bit_size: 1
fieldset/SECCR2:
description: secure control 2 register
fields:
- name: PS
description: Program suspend request
bit_offset: 0
bit_size: 1
- name: ES
description: Erase suspend request
bit_offset: 1
bit_size: 1
fieldset/SECHDPCR:
description: secure HDP control register
fields:
- name: HDP_ACCDIS
description: "Secure HDP area access disable \r When set, this bit is only cleared by a system reset."
bit_offset: 0
bit_size: 1
fieldset/SECKEYR:
description: secure key register
fields:
- name: SECKEY
description: "memory secure key\r The following values must be written consecutively to unlock the SECCR1 register, allowing the memory secure programming/erasing operations:\r KEY1: 0x4567<36>0123\r KEY2: 0xCDEF<45>89AB"
bit_offset: 0
bit_size: 32
fieldset/SECSR:
description: secure status register
fields:
- name: EOP
description: "Secure end of operation\r This bit is set by hardware when one or more memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in SECCR1). This bit is cleared by writing<6E>1."
bit_offset: 0
bit_size: 1
- name: OPERR
description: "Secure operation error\r This bit is set by hardware when a memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1."
bit_offset: 1
bit_size: 1
- name: PROGERR
description: "Secure programming error\r This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1."
bit_offset: 3
bit_size: 1
- name: WRPERR
description: "Secure write protection error\r This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
bit_offset: 4
bit_size: 1
- name: PGAERR
description: "Secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1."
bit_offset: 5
bit_size: 1
- name: SIZERR
description: "Secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1."
bit_offset: 6
bit_size: 1
- name: PGSERR
description: "Secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
bit_offset: 7
bit_size: 1
- name: BSY
description: "Secure busy\r This bit indicates that a memory secure or non-secure operation is in progress. This is set on the beginning of a operation and reset when the operation finishes or when an error occurs."
bit_offset: 16
bit_size: 1
- name: WDW
description: "Secure wait data to write\r This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory."
bit_offset: 17
bit_size: 1
fieldset/SECWMR1:
description: secure watermark register 1
fields:
- name: SECWM_PSTRT
description: "Start page of secure area\r This field contains the first page of the secure area."
bit_offset: 0
bit_size: 7
- name: SECWM_PEND
description: "End page of secure area\r This field contains the last page of the secure area."
bit_offset: 16
bit_size: 7
fieldset/SECWMR2:
description: secure watermark register 2
fields:
- name: HDP_PEND
description: "End page of secure hide protection area\r This field contains the last page of the secure HDP area."
bit_offset: 16
bit_size: 7
- name: HDPEN
description: Secure Hide protection area enable
bit_offset: 31
bit_size: 1
fieldset/WRPAR:
description: WRP area A address register
fields:
- name: WRPA_PSTRT
description: "WPR area A start page\r This field contains the first page of the WPR area A.\r Note that bit 6 is reserved on STM32WBAxEx devices."
bit_offset: 0
bit_size: 7
- name: WRPA_PEND
description: "WPR area A end page\r This field contains the last page of the WPR area A.\r Note that bit 22 is reserved on STM32WBAxEx devices."
bit_offset: 16
bit_size: 7
- name: UNLOCK
description: WPR area A unlock
bit_offset: 31
bit_size: 1
fieldset/WRPBR:
description: WRP area B address register
fields:
- name: WRPB_PSTRT
description: "WRP area B start page\r This field contains the first page of the WRP area B.\r Note that bit 6 is reserved on STM32WBAxEx devices."
bit_offset: 0
bit_size: 7
- name: WRPB_PEND
description: "WRP area B end page\r This field contains the last page of the WRP area B.\r Note that bit 22 is reserved on STM32WBAxEx devices."
bit_offset: 16
bit_size: 7
- name: UNLOCK
description: WPR area B unlock
bit_offset: 31
bit_size: 1
enum/BOR_LEV:
bit_size: 3
variants:
- name: Level0
description: BOR level 0 (reset level threshold around 1.7<EFBFBD>V)
value: 0
- name: Level1
description: BOR level 1 (reset level threshold around 2.0<EFBFBD>V)
value: 1
- name: Level2
description: BOR level 2 (reset level threshold around 2.2<EFBFBD>V)
value: 2
- name: Level3
description: BOR level 3 (reset level threshold around 2.5<EFBFBD>V)
value: 3
- name: Level4
description: BOR level 4 (reset level threshold around 2.8<EFBFBD>V)
value: 4
enum/CODE_OP:
bit_size: 3
variants:
- name: B_0x0
description: No operation interrupted by previous reset
value: 0
- name: B_0x1
description: Single write operation interrupted
value: 1
- name: B_0x2
description: Burst write operation interrupted
value: 2
- name: B_0x3
description: Page erase operation interrupted
value: 3
- name: B_0x4
description: Reserved
value: 4
- name: B_0x5
description: Mass erase operation interrupted
value: 5
- name: B_0x6
description: Option change operation interrupted
value: 6
- name: B_0x7
description: Reserved
value: 7
enum/RDP:
bit_size: 8
variants:
- name: B_0x55
description: Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1)
value: 85
- name: B_0xAA
description: Level 0 (readout protection not active)
value: 170
- name: B_0xCC
description: Level 2 (chip readout protection active)
value: 204

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data/registers/flash_wl.yaml
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data/registers/fmac_v1.yaml
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---
block/FMAC: block/FMAC:
description: Filter math accelerator description: Filter math accelerator
items: items:
- name: X1BUFCFG - name: X1BUFCFG
description: X1 buffer configuration register description: X1 buffer configuration register
byte_offset: 0 byte_offset: 0
fieldset: X1BUFCFG fieldset: X1BUFCFG
- name: X2BUFCFG - name: X2BUFCFG
description: X2 buffer configuration register description: X2 buffer configuration register
byte_offset: 4 byte_offset: 4
fieldset: X2BUFCFG fieldset: X2BUFCFG
- name: YBUFCFG - name: YBUFCFG
description: Y buffer configuration register description: Y buffer configuration register
byte_offset: 8 byte_offset: 8
fieldset: YBUFCFG fieldset: YBUFCFG
- name: PARAM - name: PARAM
description: Parameter register description: Parameter register
byte_offset: 12 byte_offset: 12
fieldset: PARAM fieldset: PARAM
- name: CR - name: CR
description: Control register description: Control register
byte_offset: 16 byte_offset: 16
fieldset: CR fieldset: CR
- name: SR - name: SR
description: Status register description: Status register
byte_offset: 20 byte_offset: 20
access: Read access: Read
fieldset: SR fieldset: SR
- name: WDATA - name: WDATA
description: Write data register description: Write data register
byte_offset: 24 byte_offset: 24
access: Write access: Write
fieldset: WDATA fieldset: WDATA
- name: RDATA - name: RDATA
description: Read data register description: Read data register
byte_offset: 28 byte_offset: 28
access: Read access: Read
fieldset: RDATA fieldset: RDATA
fieldset/CR: fieldset/CR:
description: Control register description: Control register
fields: fields:
- name: RIEN - name: RIEN
description: Enable read interrupt description: Enable read interrupt
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: WIEN - name: WIEN
description: Enable write interrupt description: Enable write interrupt
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: OVFLIEN - name: OVFLIEN
description: Enable overflow error interrupts description: Enable overflow error interrupts
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: UNFLIEN - name: UNFLIEN
description: Enable underflow error interrupts description: Enable underflow error interrupts
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: SATIEN - name: SATIEN
description: Enable saturation error interrupts description: Enable saturation error interrupts
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: DMAREN - name: DMAREN
description: Enable DMA read channel requests description: Enable DMA read channel requests
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: DMAWEN - name: DMAWEN
description: Enable DMA write channel requests description: Enable DMA write channel requests
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: CLIPEN - name: CLIPEN
description: Enable clipping description: Enable clipping
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: RESET - name: RESET
description: Reset FMAC unit description: Reset FMAC unit
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
fieldset/PARAM: fieldset/PARAM:
description: Parameter register description: Parameter register
fields: fields:
- name: P - name: P
description: Input parameter P description: Input parameter P
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: Q - name: Q
description: Input parameter Q description: Input parameter Q
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
- name: R - name: R
description: Input parameter R description: Input parameter R
bit_offset: 16 bit_offset: 16
bit_size: 8 bit_size: 8
- name: FUNC - name: FUNC
description: Function description: Function
bit_offset: 24 bit_offset: 24
bit_size: 7 bit_size: 7
- name: START - name: START
description: Enable execution description: Enable execution
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/RDATA: fieldset/RDATA:
description: Read data register description: Read data register
fields: fields:
- name: RES - name: RES
description: Read data (contents of the Y output buffer at the address indicated by the READ pointer) description: Read data (contents of the Y output buffer at the address indicated by the READ pointer)
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
fieldset/SR: fieldset/SR:
description: Status register description: Status register
fields: fields:
- name: YEMPTY - name: YEMPTY
description: Y buffer empty flag description: Y buffer empty flag
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: X1FULL - name: X1FULL
description: X1 buffer full flag description: X1 buffer full flag
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: OVFL - name: OVFL
description: Overflow error flag description: Overflow error flag
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: UNFL - name: UNFL
description: Underflow error flag description: Underflow error flag
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: SAT - name: SAT
description: Saturation error flag description: Saturation error flag
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
fieldset/WDATA: fieldset/WDATA:
description: Write data register description: Write data register
fields: fields:
- name: WDATA - name: WDATA
description: Write data (write data are transferred to the address indicated by the write pointer) description: Write data (write data are transferred to the address indicated by the write pointer)
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
fieldset/X1BUFCFG: fieldset/X1BUFCFG:
description: X1 buffer configuration register description: X1 buffer configuration register
fields: fields:
- name: X1_BASE - name: X1_BASE
description: Base address of X1 buffer description: Base address of X1 buffer
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: X1_BUF_SIZE - name: X1_BUF_SIZE
description: Allocated size of X1 buffer in 16-bit words description: Allocated size of X1 buffer in 16-bit words
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
- name: FULL_WM - name: FULL_WM
description: Watermark for buffer full flag description: Watermark for buffer full flag
bit_offset: 24 bit_offset: 24
bit_size: 2 bit_size: 2
fieldset/X2BUFCFG: fieldset/X2BUFCFG:
description: X2 buffer configuration register description: X2 buffer configuration register
fields: fields:
- name: X2_BASE - name: X2_BASE
description: Base address of X2 buffer description: Base address of X2 buffer
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: X2_BUF_SIZE - name: X2_BUF_SIZE
description: Size of X2 buffer in 16-bit words description: Size of X2 buffer in 16-bit words
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
fieldset/YBUFCFG: fieldset/YBUFCFG:
description: Y buffer configuration register description: Y buffer configuration register
fields: fields:
- name: Y_BASE - name: Y_BASE
description: Base address of Y buffer description: Base address of Y buffer
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: Y_BUF_SIZE - name: Y_BUF_SIZE
description: Size of Y buffer in 16-bit words description: Size of Y buffer in 16-bit words
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
- name: EMPTY_WM - name: EMPTY_WM
description: Watermark for buffer empty flag description: Watermark for buffer empty flag
bit_offset: 24 bit_offset: 24
bit_size: 2 bit_size: 2

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data/registers/fmc_v1x3.yaml
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data/registers/fmc_v2x1.yaml
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data/registers/fmc_v3x1.yaml
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data/registers/fsmc_v1x0.yaml
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---
block/FSMC: block/FSMC:
description: Flexible static memory controller description: Flexible static memory controller
items: items:
- name: BCR - name: BCR
description: SRAM/NOR-Flash chip-select control register 1-4 description: SRAM/NOR-Flash chip-select control register 1-4
array: array:
len: 4 len: 4
stride: 8 stride: 8
byte_offset: 0 byte_offset: 0
fieldset: BCR fieldset: BCR
- name: BTR - name: BTR
description: SRAM/NOR-Flash chip-select timing register 1-4 description: SRAM/NOR-Flash chip-select timing register 1-4
array: array:
len: 4 len: 4
stride: 8 stride: 8
byte_offset: 4 byte_offset: 4
fieldset: BTR fieldset: BTR
- name: BWTR - name: BWTR
description: SRAM/NOR-Flash write timing registers 1-4 description: SRAM/NOR-Flash write timing registers 1-4
array: array:
len: 4 len: 4
stride: 8 stride: 8
byte_offset: 260 byte_offset: 260
fieldset: BWTR fieldset: BWTR
fieldset/BCR: fieldset/BCR:
description: SRAM/NOR-Flash chip-select control register description: SRAM/NOR-Flash chip-select control register
fields: fields:
- name: MBKEN - name: MBKEN
description: Memory bank enable bit description: Memory bank enable bit
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: MUXEN - name: MUXEN
description: Address/data multiplexing enable bit description: Address/data multiplexing enable bit
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: MTYP - name: MTYP
description: Memory type description: Memory type
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
enum: MTYP enum: MTYP
- name: MWID - name: MWID
description: Memory data bus width description: Memory data bus width
bit_offset: 4 bit_offset: 4
bit_size: 2 bit_size: 2
enum: MWID enum: MWID
- name: FACCEN - name: FACCEN
description: Flash access enable description: Flash access enable
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: BURSTEN - name: BURSTEN
description: Burst enable bit description: Burst enable bit
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: WAITPOL - name: WAITPOL
description: Wait signal polarity bit description: Wait signal polarity bit
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
enum: WAITPOL enum: WAITPOL
- name: WRAPMOD - name: WRAPMOD
description: WRAPMOD description: WRAPMOD
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: WAITCFG - name: WAITCFG
description: Wait timing configuration description: Wait timing configuration
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
enum: WAITCFG enum: WAITCFG
- name: WREN - name: WREN
description: Write enable bit description: Write enable bit
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: WAITEN - name: WAITEN
description: Wait enable bit description: Wait enable bit
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: EXTMOD - name: EXTMOD
description: Extended mode enable description: Extended mode enable
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: ASYNCWAIT - name: ASYNCWAIT
description: Wait signal during asynchronous transfers description: Wait signal during asynchronous transfers
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: CPSIZE - name: CPSIZE
description: CRAM page size description: CRAM page size
bit_offset: 16 bit_offset: 16
bit_size: 3 bit_size: 3
enum: CPSIZE enum: CPSIZE
- name: CBURSTRW - name: CBURSTRW
description: Write burst enable description: Write burst enable
bit_offset: 19 bit_offset: 19
bit_size: 1 bit_size: 1
fieldset/BTR: fieldset/BTR:
description: SRAM/NOR-Flash chip-select timing register description: SRAM/NOR-Flash chip-select timing register
fields: fields:
- name: ADDSET - name: ADDSET
description: Address setup phase duration description: Address setup phase duration
bit_offset: 0 bit_offset: 0
bit_size: 4 bit_size: 4
- name: ADDHLD - name: ADDHLD
description: Address-hold phase duration description: Address-hold phase duration
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
- name: DATAST - name: DATAST
description: Data-phase duration description: Data-phase duration
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
- name: BUSTURN - name: BUSTURN
description: Bus turnaround phase duration description: Bus turnaround phase duration
bit_offset: 16 bit_offset: 16
bit_size: 4 bit_size: 4
- name: CLKDIV - name: CLKDIV
description: Clock divide ratio (for FMC_CLK signal) description: Clock divide ratio (for FMC_CLK signal)
bit_offset: 20 bit_offset: 20
bit_size: 4 bit_size: 4
- name: DATLAT - name: DATLAT
description: Data latency for synchronous memory description: Data latency for synchronous memory
bit_offset: 24 bit_offset: 24
bit_size: 4 bit_size: 4
- name: ACCMOD - name: ACCMOD
description: Access mode description: Access mode
bit_offset: 28 bit_offset: 28
bit_size: 2 bit_size: 2
enum: ACCMOD enum: ACCMOD
fieldset/BWTR: fieldset/BWTR:
description: SRAM/NOR-Flash write timing registers description: SRAM/NOR-Flash write timing registers
fields: fields:
- name: ADDSET - name: ADDSET
description: Address setup phase duration description: Address setup phase duration
bit_offset: 0 bit_offset: 0
bit_size: 4 bit_size: 4
- name: ADDHLD - name: ADDHLD
description: Address-hold phase duration description: Address-hold phase duration
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
- name: DATAST - name: DATAST
description: Data-phase duration description: Data-phase duration
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
- name: BUSTURN - name: BUSTURN
description: Bus turnaround phase duration description: Bus turnaround phase duration
bit_offset: 16 bit_offset: 16
bit_size: 4 bit_size: 4
- name: ACCMOD - name: ACCMOD
description: Access mode description: Access mode
bit_offset: 28 bit_offset: 28
bit_size: 2 bit_size: 2
enum: ACCMOD enum: ACCMOD
enum/ACCMOD: enum/ACCMOD:
bit_size: 2 bit_size: 2
variants: variants:
- name: A - name: A
description: Access mode A description: Access mode A
value: 0 value: 0
- name: B - name: B
description: Access mode B description: Access mode B
value: 1 value: 1
- name: C - name: C
description: Access mode C description: Access mode C
value: 2 value: 2
- name: D - name: D
description: Access mode D description: Access mode D
value: 3 value: 3
enum/CPSIZE: enum/CPSIZE:
bit_size: 3 bit_size: 3
variants: variants:
- name: NoBurstSplit - name: NoBurstSplit
description: No burst split when crossing page boundary description: No burst split when crossing page boundary
value: 0 value: 0
- name: Bytes128 - name: Bytes128
description: 128 bytes CRAM page size description: 128 bytes CRAM page size
value: 1 value: 1
- name: Bytes256 - name: Bytes256
description: 256 bytes CRAM page size description: 256 bytes CRAM page size
value: 2 value: 2
- name: Bytes512 - name: Bytes512
description: 512 bytes CRAM page size description: 512 bytes CRAM page size
value: 3 value: 3
- name: Bytes1024 - name: Bytes1024
description: 1024 bytes CRAM page size description: 1024 bytes CRAM page size
value: 4 value: 4
enum/MTYP: enum/MTYP:
bit_size: 2 bit_size: 2
variants: variants:
- name: SRAM - name: SRAM
description: SRAM memory type description: SRAM memory type
value: 0 value: 0
- name: PSRAM - name: PSRAM
description: PSRAM (CRAM) memory type description: PSRAM (CRAM) memory type
value: 1 value: 1
- name: Flash - name: Flash
description: NOR Flash/OneNAND Flash description: NOR Flash/OneNAND Flash
value: 2 value: 2
enum/MWID: enum/MWID:
bit_size: 2 bit_size: 2
variants: variants:
- name: Bits8 - name: Bits8
description: Memory data bus width 8 bits description: Memory data bus width 8 bits
value: 0 value: 0
- name: Bits16 - name: Bits16
description: Memory data bus width 16 bits description: Memory data bus width 16 bits
value: 1 value: 1
- name: Bits32 - name: Bits32
description: Memory data bus width 32 bits description: Memory data bus width 32 bits
value: 2 value: 2
enum/WAITCFG: enum/WAITCFG:
bit_size: 1 bit_size: 1
variants: variants:
- name: BeforeWaitState - name: BeforeWaitState
description: NWAIT signal is active one data cycle before wait state description: NWAIT signal is active one data cycle before wait state
value: 0 value: 0
- name: DuringWaitState - name: DuringWaitState
description: NWAIT signal is active during wait state description: NWAIT signal is active during wait state
value: 1 value: 1
enum/WAITPOL: enum/WAITPOL:
bit_size: 1 bit_size: 1
variants: variants:
- name: ActiveLow - name: ActiveLow
description: NWAIT active low description: NWAIT active low
value: 0 value: 0
- name: ActiveHigh - name: ActiveHigh
description: NWAIT active high description: NWAIT active high
value: 1 value: 1

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data/registers/fsmc_v1x3.yaml
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@ -1,433 +1,432 @@
---
block/FSMC: block/FSMC:
description: Flexible static memory controller description: Flexible static memory controller
items: items:
- name: BCR - name: BCR
description: SRAM/NOR-Flash chip-select control register 1-4 description: SRAM/NOR-Flash chip-select control register 1-4
array: array:
len: 4 len: 4
stride: 8 stride: 8
byte_offset: 0 byte_offset: 0
fieldset: BCR fieldset: BCR
- name: BTR - name: BTR
description: SRAM/NOR-Flash chip-select timing register 1-4 description: SRAM/NOR-Flash chip-select timing register 1-4
array: array:
len: 4 len: 4
stride: 8 stride: 8
byte_offset: 4 byte_offset: 4
fieldset: BTR fieldset: BTR
- name: PCR - name: PCR
description: PC Card/NAND Flash control register 2-4 description: PC Card/NAND Flash control register 2-4
array: array:
len: 3 len: 3
stride: 32 stride: 32
byte_offset: 96 byte_offset: 96
fieldset: PCR fieldset: PCR
- name: SR - name: SR
description: FIFO status and interrupt register 2-4 description: FIFO status and interrupt register 2-4
array: array:
len: 3 len: 3
stride: 32 stride: 32
byte_offset: 100 byte_offset: 100
fieldset: SR fieldset: SR
- name: PMEM - name: PMEM
description: Common memory space timing register 2-4 description: Common memory space timing register 2-4
array: array:
len: 3 len: 3
stride: 32 stride: 32
byte_offset: 104 byte_offset: 104
fieldset: PMEM fieldset: PMEM
- name: PATT - name: PATT
description: Attribute memory space timing register 2-4 description: Attribute memory space timing register 2-4
array: array:
len: 3 len: 3
stride: 32 stride: 32
byte_offset: 108 byte_offset: 108
fieldset: PATT fieldset: PATT
- name: ECCR - name: ECCR
description: ECC result register 2-3 description: ECC result register 2-3
array: array:
len: 2 len: 2
stride: 32 stride: 32
byte_offset: 116 byte_offset: 116
access: Read access: Read
fieldset: ECCR fieldset: ECCR
- name: PIO4 - name: PIO4
description: I/O space timing register 4 description: I/O space timing register 4
byte_offset: 176 byte_offset: 176
fieldset: PIO4 fieldset: PIO4
- name: BWTR - name: BWTR
description: SRAM/NOR-Flash write timing registers 1-4 description: SRAM/NOR-Flash write timing registers 1-4
array: array:
len: 4 len: 4
stride: 8 stride: 8
byte_offset: 260 byte_offset: 260
fieldset: BWTR fieldset: BWTR
fieldset/BCR: fieldset/BCR:
description: SRAM/NOR-Flash chip-select control register description: SRAM/NOR-Flash chip-select control register
fields: fields:
- name: MBKEN - name: MBKEN
description: Memory bank enable bit description: Memory bank enable bit
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: MUXEN - name: MUXEN
description: Address/data multiplexing enable bit description: Address/data multiplexing enable bit
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: MTYP - name: MTYP
description: Memory type description: Memory type
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
enum: MTYP enum: MTYP
- name: MWID - name: MWID
description: Memory data bus width description: Memory data bus width
bit_offset: 4 bit_offset: 4
bit_size: 2 bit_size: 2
enum: MWID enum: MWID
- name: FACCEN - name: FACCEN
description: Flash access enable description: Flash access enable
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: BURSTEN - name: BURSTEN
description: Burst enable bit description: Burst enable bit
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: WAITPOL - name: WAITPOL
description: Wait signal polarity bit description: Wait signal polarity bit
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
enum: WAITPOL enum: WAITPOL
- name: WRAPMOD - name: WRAPMOD
description: WRAPMOD description: WRAPMOD
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: WAITCFG - name: WAITCFG
description: Wait timing configuration description: Wait timing configuration
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
enum: WAITCFG enum: WAITCFG
- name: WREN - name: WREN
description: Write enable bit description: Write enable bit
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: WAITEN - name: WAITEN
description: Wait enable bit description: Wait enable bit
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: EXTMOD - name: EXTMOD
description: Extended mode enable description: Extended mode enable
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: ASYNCWAIT - name: ASYNCWAIT
description: Wait signal during asynchronous transfers description: Wait signal during asynchronous transfers
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: CPSIZE - name: CPSIZE
description: CRAM page size description: CRAM page size
bit_offset: 16 bit_offset: 16
bit_size: 3 bit_size: 3
enum: CPSIZE enum: CPSIZE
- name: CBURSTRW - name: CBURSTRW
description: Write burst enable description: Write burst enable
bit_offset: 19 bit_offset: 19
bit_size: 1 bit_size: 1
fieldset/BTR: fieldset/BTR:
description: SRAM/NOR-Flash chip-select timing register description: SRAM/NOR-Flash chip-select timing register
fields: fields:
- name: ADDSET - name: ADDSET
description: Address setup phase duration description: Address setup phase duration
bit_offset: 0 bit_offset: 0
bit_size: 4 bit_size: 4
- name: ADDHLD - name: ADDHLD
description: Address-hold phase duration description: Address-hold phase duration
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
- name: DATAST - name: DATAST
description: Data-phase duration description: Data-phase duration
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
- name: BUSTURN - name: BUSTURN
description: Bus turnaround phase duration description: Bus turnaround phase duration
bit_offset: 16 bit_offset: 16
bit_size: 4 bit_size: 4
- name: CLKDIV - name: CLKDIV
description: Clock divide ratio (for FMC_CLK signal) description: Clock divide ratio (for FMC_CLK signal)
bit_offset: 20 bit_offset: 20
bit_size: 4 bit_size: 4
- name: DATLAT - name: DATLAT
description: Data latency for synchronous memory description: Data latency for synchronous memory
bit_offset: 24 bit_offset: 24
bit_size: 4 bit_size: 4
- name: ACCMOD - name: ACCMOD
description: Access mode description: Access mode
bit_offset: 28 bit_offset: 28
bit_size: 2 bit_size: 2
enum: ACCMOD enum: ACCMOD
fieldset/BWTR: fieldset/BWTR:
description: SRAM/NOR-Flash write timing registers description: SRAM/NOR-Flash write timing registers
fields: fields:
- name: ADDSET - name: ADDSET
description: Address setup phase duration description: Address setup phase duration
bit_offset: 0 bit_offset: 0
bit_size: 4 bit_size: 4
- name: ADDHLD - name: ADDHLD
description: Address-hold phase duration description: Address-hold phase duration
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
- name: DATAST - name: DATAST
description: Data-phase duration description: Data-phase duration
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
- name: BUSTURN - name: BUSTURN
description: Bus turnaround phase duration description: Bus turnaround phase duration
bit_offset: 16 bit_offset: 16
bit_size: 4 bit_size: 4
- name: ACCMOD - name: ACCMOD
description: Access mode description: Access mode
bit_offset: 28 bit_offset: 28
bit_size: 2 bit_size: 2
enum: ACCMOD enum: ACCMOD
fieldset/ECCR: fieldset/ECCR:
description: ECC result register description: ECC result register
fields: fields:
- name: ECC - name: ECC
description: ECC computation result value description: ECC computation result value
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/PATT: fieldset/PATT:
description: Attribute memory space timing register description: Attribute memory space timing register
fields: fields:
- name: ATTSET - name: ATTSET
description: Attribute memory setup time description: Attribute memory setup time
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: ATTWAIT - name: ATTWAIT
description: Attribute memory wait time description: Attribute memory wait time
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
- name: ATTHOLD - name: ATTHOLD
description: Attribute memory hold time description: Attribute memory hold time
bit_offset: 16 bit_offset: 16
bit_size: 8 bit_size: 8
- name: ATTHIZ - name: ATTHIZ
description: Attribute memory data bus Hi-Z time description: Attribute memory data bus Hi-Z time
bit_offset: 24 bit_offset: 24
bit_size: 8 bit_size: 8
fieldset/PCR: fieldset/PCR:
description: PC Card/NAND Flash control register description: PC Card/NAND Flash control register
fields: fields:
- name: PWAITEN - name: PWAITEN
description: Wait feature enable bit description: Wait feature enable bit
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: PBKEN - name: PBKEN
description: NAND Flash memory bank enable bit description: NAND Flash memory bank enable bit
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: PTYP - name: PTYP
description: Memory type description: Memory type
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
enum: PTYP enum: PTYP
- name: PWID - name: PWID
description: Data bus width description: Data bus width
bit_offset: 4 bit_offset: 4
bit_size: 2 bit_size: 2
enum: PWID enum: PWID
- name: ECCEN - name: ECCEN
description: ECC computation logic enable bit description: ECC computation logic enable bit
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
- name: TCLR - name: TCLR
description: CLE to RE delay description: CLE to RE delay
bit_offset: 9 bit_offset: 9
bit_size: 4 bit_size: 4
- name: TAR - name: TAR
description: ALE to RE delay description: ALE to RE delay
bit_offset: 13 bit_offset: 13
bit_size: 4 bit_size: 4
- name: ECCPS - name: ECCPS
description: ECC page size description: ECC page size
bit_offset: 17 bit_offset: 17
bit_size: 3 bit_size: 3
enum: ECCPS enum: ECCPS
fieldset/PIO4: fieldset/PIO4:
description: I/O space timing register 4 description: I/O space timing register 4
fields: fields:
- name: IOSETx - name: IOSETx
description: IOSETx description: IOSETx
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: IOWAITx - name: IOWAITx
description: IOWAITx description: IOWAITx
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
- name: IOHOLDx - name: IOHOLDx
description: IOHOLDx description: IOHOLDx
bit_offset: 16 bit_offset: 16
bit_size: 8 bit_size: 8
- name: IOHIZx - name: IOHIZx
description: IOHIZx description: IOHIZx
bit_offset: 24 bit_offset: 24
bit_size: 8 bit_size: 8
fieldset/PMEM: fieldset/PMEM:
description: Common memory space timing register description: Common memory space timing register
fields: fields:
- name: MEMSET - name: MEMSET
description: Common memory x setup time description: Common memory x setup time
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: MEMWAIT - name: MEMWAIT
description: Common memory wait time description: Common memory wait time
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
- name: MEMHOLD - name: MEMHOLD
description: Common memory hold time description: Common memory hold time
bit_offset: 16 bit_offset: 16
bit_size: 8 bit_size: 8
- name: MEMHIZ - name: MEMHIZ
description: Common memory x data bus Hi-Z time description: Common memory x data bus Hi-Z time
bit_offset: 24 bit_offset: 24
bit_size: 8 bit_size: 8
fieldset/SR: fieldset/SR:
description: FIFO status and interrupt register description: FIFO status and interrupt register
fields: fields:
- name: IRS - name: IRS
description: Interrupt rising edge status description: Interrupt rising edge status
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: ILS - name: ILS
description: Interrupt high-level status description: Interrupt high-level status
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: IFS - name: IFS
description: Interrupt falling edge status description: Interrupt falling edge status
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: IREN - name: IREN
description: Interrupt rising edge detection enable bit description: Interrupt rising edge detection enable bit
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: ILEN - name: ILEN
description: Interrupt high-level detection enable bit description: Interrupt high-level detection enable bit
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: IFEN - name: IFEN
description: Interrupt falling edge detection enable bit description: Interrupt falling edge detection enable bit
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: FEMPT - name: FEMPT
description: FIFO empty status description: FIFO empty status
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum/ACCMOD: enum/ACCMOD:
bit_size: 2 bit_size: 2
variants: variants:
- name: A - name: A
description: Access mode A description: Access mode A
value: 0 value: 0
- name: B - name: B
description: Access mode B description: Access mode B
value: 1 value: 1
- name: C - name: C
description: Access mode C description: Access mode C
value: 2 value: 2
- name: D - name: D
description: Access mode D description: Access mode D
value: 3 value: 3
enum/CPSIZE: enum/CPSIZE:
bit_size: 3 bit_size: 3
variants: variants:
- name: NoBurstSplit - name: NoBurstSplit
description: No burst split when crossing page boundary description: No burst split when crossing page boundary
value: 0 value: 0
- name: Bytes128 - name: Bytes128
description: 128 bytes CRAM page size description: 128 bytes CRAM page size
value: 1 value: 1
- name: Bytes256 - name: Bytes256
description: 256 bytes CRAM page size description: 256 bytes CRAM page size
value: 2 value: 2
- name: Bytes512 - name: Bytes512
description: 512 bytes CRAM page size description: 512 bytes CRAM page size
value: 3 value: 3
- name: Bytes1024 - name: Bytes1024
description: 1024 bytes CRAM page size description: 1024 bytes CRAM page size
value: 4 value: 4
enum/ECCPS: enum/ECCPS:
bit_size: 3 bit_size: 3
variants: variants:
- name: Bytes256 - name: Bytes256
description: ECC page size 256 bytes description: ECC page size 256 bytes
value: 0 value: 0
- name: Bytes512 - name: Bytes512
description: ECC page size 512 bytes description: ECC page size 512 bytes
value: 1 value: 1
- name: Bytes1024 - name: Bytes1024
description: ECC page size 1024 bytes description: ECC page size 1024 bytes
value: 2 value: 2
- name: Bytes2048 - name: Bytes2048
description: ECC page size 2048 bytes description: ECC page size 2048 bytes
value: 3 value: 3
- name: Bytes4096 - name: Bytes4096
description: ECC page size 4096 bytes description: ECC page size 4096 bytes
value: 4 value: 4
- name: Bytes8192 - name: Bytes8192
description: ECC page size 8192 bytes description: ECC page size 8192 bytes
value: 5 value: 5
enum/MTYP: enum/MTYP:
bit_size: 2 bit_size: 2
variants: variants:
- name: SRAM - name: SRAM
description: SRAM memory type description: SRAM memory type
value: 0 value: 0
- name: PSRAM - name: PSRAM
description: PSRAM (CRAM) memory type description: PSRAM (CRAM) memory type
value: 1 value: 1
- name: Flash - name: Flash
description: NOR Flash/OneNAND Flash description: NOR Flash/OneNAND Flash
value: 2 value: 2
enum/MWID: enum/MWID:
bit_size: 2 bit_size: 2
variants: variants:
- name: Bits8 - name: Bits8
description: Memory data bus width 8 bits description: Memory data bus width 8 bits
value: 0 value: 0
- name: Bits16 - name: Bits16
description: Memory data bus width 16 bits description: Memory data bus width 16 bits
value: 1 value: 1
- name: Bits32 - name: Bits32
description: Memory data bus width 32 bits description: Memory data bus width 32 bits
value: 2 value: 2
enum/PTYP: enum/PTYP:
bit_size: 1 bit_size: 1
variants: variants:
- name: NANDFlash - name: NANDFlash
description: NAND Flash description: NAND Flash
value: 1 value: 1
enum/PWID: enum/PWID:
bit_size: 2 bit_size: 2
variants: variants:
- name: Bits8 - name: Bits8
description: External memory device width 8 bits description: External memory device width 8 bits
value: 0 value: 0
- name: Bits16 - name: Bits16
description: External memory device width 16 bits description: External memory device width 16 bits
value: 1 value: 1
enum/WAITCFG: enum/WAITCFG:
bit_size: 1 bit_size: 1
variants: variants:
- name: BeforeWaitState - name: BeforeWaitState
description: NWAIT signal is active one data cycle before wait state description: NWAIT signal is active one data cycle before wait state
value: 0 value: 0
- name: DuringWaitState - name: DuringWaitState
description: NWAIT signal is active during wait state description: NWAIT signal is active during wait state
value: 1 value: 1
enum/WAITPOL: enum/WAITPOL:
bit_size: 1 bit_size: 1
variants: variants:
- name: ActiveLow - name: ActiveLow
description: NWAIT active low description: NWAIT active low
value: 0 value: 0
- name: ActiveHigh - name: ActiveHigh
description: NWAIT active high description: NWAIT active high
value: 1 value: 1

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