Merge branch 'main' into f1_bkp
This commit is contained in:
chemicstry
commit
137611f0f6
@ -47,6 +47,7 @@ In order to run the generator, you will need to install the following tools:
|
||||
* `git`
|
||||
* `jq`
|
||||
* `svd` – `pip3 install svdtools`
|
||||
* `xmltodict` - `pip3 install xmltodict`
|
||||
|
||||
## Generating the YAMLs
|
||||
|
||||
|
||||
114
data/dmamux/U5_GPDMA1.yaml
Normal file
114
data/dmamux/U5_GPDMA1.yaml
Normal file
@ -0,0 +1,114 @@
|
||||
ADC1: 0
|
||||
ADC4: 1
|
||||
DAC1_CH1: 2
|
||||
DAC1_CH2: 3
|
||||
TIM6_UPD: 4
|
||||
TIM7_UPD: 5
|
||||
SPI1_RX: 6
|
||||
SPI1_TX: 7
|
||||
SPI2_RX: 8
|
||||
SPI2_TX: 9
|
||||
SPI3_RX: 10
|
||||
SPI3_TX: 11
|
||||
I2C1_RX: 12
|
||||
I2C1_TX: 13
|
||||
I2C1_EVC: 14
|
||||
I2C2_RX: 15
|
||||
I2C2_TX: 16
|
||||
I2C2_EVC: 17
|
||||
I2C3_RX: 18
|
||||
I2C3_TX: 19
|
||||
I2C3_EVC: 20
|
||||
I2C4_RX: 21
|
||||
I2C4_TX: 22
|
||||
I2C4_EVC: 23
|
||||
USART1_RX: 24
|
||||
USART1_TX: 25
|
||||
USART2_RX: 26
|
||||
USART2_TX: 27
|
||||
USART3_RX: 28
|
||||
USART3_TX: 29
|
||||
UART4_RX: 30
|
||||
UART4_TX: 31
|
||||
UART5_RX: 32
|
||||
UART5_TX: 33
|
||||
LPUART1_RX: 34
|
||||
LPUART1_TX: 35
|
||||
SAI1_A: 36
|
||||
SAI1_B: 37
|
||||
SAI2_A: 38
|
||||
SAI2_B: 39
|
||||
OCTOSPI1: 40
|
||||
OCTOSPI2: 41
|
||||
TIM1_CC1: 42
|
||||
TIM1_CC2: 43
|
||||
TIM1_CC3: 44
|
||||
TIM1_CC4: 45
|
||||
TIM1_UPD: 46
|
||||
TIM1_TRG: 47
|
||||
TIM1_COM: 48
|
||||
TIM8_CC1: 49
|
||||
TIM8_CC2: 50
|
||||
TIM8_CC3: 51
|
||||
TIM8_CC4: 52
|
||||
TIM8_UPD: 53
|
||||
TIM8_TRG: 54
|
||||
TIM8_COM: 55
|
||||
TIM2_CC1: 56
|
||||
TIM2_CC2: 57
|
||||
TIM2_CC3: 58
|
||||
TIM2_CC4: 59
|
||||
TIM2_UPD: 60
|
||||
TIM3_CC1: 61
|
||||
TIM3_CC2: 62
|
||||
TIM3_CC3: 63
|
||||
TIM3_CC4: 64
|
||||
TIM3_UPD: 65
|
||||
TIM3_TRG: 66
|
||||
TIM4_CC1: 67
|
||||
TIM4_CC2: 68
|
||||
TIM4_CC3: 69
|
||||
TIM4_CC4: 70
|
||||
TIM4_UPD: 71
|
||||
TIM5_CC1: 72
|
||||
TIM5_CC2: 73
|
||||
TIM5_CC3: 74
|
||||
TIM5_CC4: 75
|
||||
TIM5_UPD: 76
|
||||
TIM5_TRG: 77
|
||||
TIM15_CC1: 78
|
||||
TIM15_UPD: 79
|
||||
TIM15_TRG: 80
|
||||
TIM15_COM: 81
|
||||
TIM16_CC1: 82
|
||||
TIM16_UPD: 83
|
||||
TIM17_CC1: 84
|
||||
TIM17_UPD: 85
|
||||
DCMI: 86
|
||||
AES_IN: 87
|
||||
AES_OUT: 88
|
||||
HASH_IN: 89
|
||||
UCPD1_TX: 90
|
||||
UCPD1_RX: 91
|
||||
MDF1_FLT0: 92
|
||||
MDF1_FLT1: 93
|
||||
MDF1_FLT2: 94
|
||||
MDF1_FLT3: 95
|
||||
MDF1_FLT4: 96
|
||||
MDF1_FLT5: 97
|
||||
ADF1_FLT0: 98
|
||||
FMAC_READ: 99
|
||||
FMAC_WRITE: 100
|
||||
CORDIC_READ: 101
|
||||
CORDIC_WRITE: 102
|
||||
SAES_IN: 103
|
||||
SAES_OUT: 104
|
||||
LPTIM1_IC1: 105
|
||||
LPTIM1_IC2: 106
|
||||
LPTIM1_UE: 107
|
||||
LPTIM2_IC1: 108
|
||||
LPTIM2_IC2: 109
|
||||
LPTIM2_UE: 110
|
||||
LPTIM3_IC1: 111
|
||||
LPTIM3_IC2: 112
|
||||
LPTIM3_UE: 113
|
||||
487
data/registers/adc_v1.yaml
Normal file
487
data/registers/adc_v1.yaml
Normal file
@ -0,0 +1,487 @@
|
||||
---
|
||||
block/ADC:
|
||||
description: Analog-to-digital converter
|
||||
items:
|
||||
- name: ISR
|
||||
description: interrupt and status register
|
||||
byte_offset: 0
|
||||
fieldset: ISR
|
||||
- name: IER
|
||||
description: interrupt enable register
|
||||
byte_offset: 4
|
||||
fieldset: IER
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 8
|
||||
fieldset: CR
|
||||
- name: CFGR1
|
||||
description: configuration register 1
|
||||
byte_offset: 12
|
||||
fieldset: CFGR1
|
||||
- name: CFGR2
|
||||
description: configuration register 2
|
||||
byte_offset: 16
|
||||
fieldset: CFGR2
|
||||
- name: SMPR
|
||||
description: sampling time register
|
||||
byte_offset: 20
|
||||
fieldset: SMPR
|
||||
- name: TR
|
||||
description: watchdog threshold register
|
||||
byte_offset: 32
|
||||
fieldset: TR
|
||||
- name: CHSELR
|
||||
description: channel selection register
|
||||
byte_offset: 40
|
||||
fieldset: CHSELR
|
||||
- name: DR
|
||||
description: data register
|
||||
byte_offset: 64
|
||||
access: Read
|
||||
fieldset: DR
|
||||
- name: CCR
|
||||
description: common configuration register
|
||||
byte_offset: 776
|
||||
fieldset: CCR
|
||||
fieldset/CCR:
|
||||
description: common configuration register
|
||||
fields:
|
||||
- name: VREFEN
|
||||
description: Temperature sensor and VREFINT enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TSEN
|
||||
description: Temperature sensor enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: VBATEN
|
||||
description: VBAT enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/CFGR1:
|
||||
description: configuration register 1
|
||||
fields:
|
||||
- name: DMAEN
|
||||
description: Direct memory access enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DMACFG
|
||||
description: Direct memery access configuration
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
enum: DMACFG
|
||||
- name: SCANDIR
|
||||
description: Scan sequence direction
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum: SCANDIR
|
||||
- name: RES
|
||||
description: Data resolution
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
enum: RES
|
||||
- name: ALIGN
|
||||
description: Data alignment
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: ALIGN
|
||||
- name: EXTSEL
|
||||
description: External trigger selection
|
||||
bit_offset: 6
|
||||
bit_size: 3
|
||||
enum: EXTSEL
|
||||
- name: EXTEN
|
||||
description: External trigger enable and polarity selection
|
||||
bit_offset: 10
|
||||
bit_size: 2
|
||||
enum: EXTEN
|
||||
- name: OVRMOD
|
||||
description: Overrun management mode
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
enum: OVRMOD
|
||||
- name: CONT
|
||||
description: Single / continuous conversion mode
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: WAIT
|
||||
description: Wait conversion mode
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: AUTOFF
|
||||
description: Auto-off mode
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: DISCEN
|
||||
description: Discontinuous mode
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: AWDSGL
|
||||
description: Enable the watchdog on a single channel or on all channels
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
enum: AWDSGL
|
||||
- name: AWDEN
|
||||
description: Analog watchdog enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: AWDCH
|
||||
description: Analog watchdog channel selection
|
||||
bit_offset: 26
|
||||
bit_size: 5
|
||||
fieldset/CFGR2:
|
||||
description: configuration register 2
|
||||
fields:
|
||||
- name: CKMODE
|
||||
description: ADC clock mode
|
||||
bit_offset: 30
|
||||
bit_size: 2
|
||||
enum: CKMODE
|
||||
fieldset/CHSELR:
|
||||
description: channel selection register
|
||||
fields:
|
||||
- name: CHSEL x
|
||||
description: Channel-x selection
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 19
|
||||
stride: 1
|
||||
fieldset/CR:
|
||||
description: control register
|
||||
fields:
|
||||
- name: ADEN
|
||||
description: ADC enable command
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
enum_read: ADENR
|
||||
enum_write: ADENW
|
||||
- name: ADDIS
|
||||
description: ADC disable command
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
enum_read: ADDISR
|
||||
enum_write: ADDISW
|
||||
- name: ADSTART
|
||||
description: ADC start conversion command
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum_read: ADSTARTR
|
||||
enum_write: ADSTARTW
|
||||
- name: ADSTP
|
||||
description: ADC stop conversion command
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum_read: ADSTPR
|
||||
enum_write: ADSTPW
|
||||
- name: ADCAL
|
||||
description: ADC calibration
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
enum_read: ADCALR
|
||||
enum_write: ADCALW
|
||||
fieldset/DR:
|
||||
description: data register
|
||||
fields:
|
||||
- name: DATA
|
||||
description: Converted data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/IER:
|
||||
description: interrupt enable register
|
||||
fields:
|
||||
- name: ADRDYIE
|
||||
description: ADC ready interrupt enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMPIE
|
||||
description: End of sampling flag interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: EOCIE
|
||||
description: End of conversion interrupt enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOSEQIE
|
||||
description: End of conversion sequence interrupt enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: OVRIE
|
||||
description: Overrun interrupt enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: AWDIE
|
||||
description: Analog watchdog interrupt enable
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
fieldset/ISR:
|
||||
description: interrupt and status register
|
||||
fields:
|
||||
- name: ADRDY
|
||||
description: ADC ready
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMP
|
||||
description: End of sampling flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: EOC
|
||||
description: End of conversion flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOSEQ
|
||||
description: End of sequence flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: OVR
|
||||
description: ADC overrun
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: AWD
|
||||
description: Analog watchdog flag
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
fieldset/SMPR:
|
||||
description: sampling time register
|
||||
fields:
|
||||
- name: SMP
|
||||
description: Sampling time selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: SMP
|
||||
fieldset/TR:
|
||||
description: watchdog threshold register
|
||||
fields:
|
||||
- name: LT
|
||||
description: Analog watchdog lower threshold
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: HT
|
||||
description: Analog watchdog higher threshold
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
enum/ADCALR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotCalibrating
|
||||
description: ADC calibration either not yet performed or completed
|
||||
value: 0
|
||||
- name: Calibrating
|
||||
description: ADC calibration in progress
|
||||
value: 1
|
||||
enum/ADCALW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: StartCalibration
|
||||
description: Start the ADC calibration sequence
|
||||
value: 1
|
||||
enum/ADDISR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotDisabling
|
||||
description: No disable command active
|
||||
value: 0
|
||||
- name: Disabling
|
||||
description: ADC disabling
|
||||
value: 1
|
||||
enum/ADDISW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disable
|
||||
description: Disable the ADC
|
||||
value: 1
|
||||
enum/ADENR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: ADC disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: ADC enabled
|
||||
value: 1
|
||||
enum/ADENW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enabled
|
||||
description: Enable the ADC
|
||||
value: 1
|
||||
enum/ADSTARTR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotActive
|
||||
description: No conversion ongoing
|
||||
value: 0
|
||||
- name: Active
|
||||
description: ADC operating and may be converting
|
||||
value: 1
|
||||
enum/ADSTARTW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: StartConversion
|
||||
description: Start the ADC conversion (may be delayed for hardware triggers)
|
||||
value: 1
|
||||
enum/ADSTPR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotStopping
|
||||
description: No stop command active
|
||||
value: 0
|
||||
- name: Stopping
|
||||
description: ADC stopping conversion
|
||||
value: 1
|
||||
enum/ADSTPW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: StopConversion
|
||||
description: Stop the active conversion
|
||||
value: 1
|
||||
enum/ALIGN:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Right
|
||||
description: Right alignment
|
||||
value: 0
|
||||
- name: Left
|
||||
description: Left alignment
|
||||
value: 1
|
||||
enum/AWDSGL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: AllChannels
|
||||
description: Analog watchdog enabled on all channels
|
||||
value: 0
|
||||
- name: SingleChannel
|
||||
description: Analog watchdog enabled on a single channel
|
||||
value: 1
|
||||
enum/CKMODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: ADCCLK
|
||||
description: Asynchronous clock mode
|
||||
value: 0
|
||||
- name: PCLK_Div2
|
||||
description: Synchronous clock mode (PCLK/2)
|
||||
value: 1
|
||||
- name: PCLK_Div4
|
||||
description: Sychronous clock mode (PCLK/4)
|
||||
value: 2
|
||||
enum/DMACFG:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: OneShot
|
||||
description: DMA one shot mode
|
||||
value: 0
|
||||
- name: Circular
|
||||
description: DMA circular mode
|
||||
value: 1
|
||||
enum/EXTEN:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Trigger detection disabled
|
||||
value: 0
|
||||
- name: RisingEdge
|
||||
description: Trigger detection on the rising edge
|
||||
value: 1
|
||||
- name: FallingEdge
|
||||
description: Trigger detection on the falling edge
|
||||
value: 2
|
||||
- name: BothEdges
|
||||
description: Trigger detection on both the rising and falling edges
|
||||
value: 3
|
||||
enum/EXTSEL:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: TIM1_TRGO
|
||||
description: Timer 1 TRGO Event
|
||||
value: 0
|
||||
- name: TIM1_CC4
|
||||
description: Timer 1 CC4 event
|
||||
value: 1
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 2
|
||||
- name: TIM3_TRGO
|
||||
description: Timer 3 TRGO event
|
||||
value: 3
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 4
|
||||
enum/OVRMOD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Preserved
|
||||
description: ADC_DR register is preserved with the old data when an overrun is detected
|
||||
value: 0
|
||||
- name: Overwritten
|
||||
description: ADC_DR register is overwritten with the last conversion result when an overrun is detected
|
||||
value: 1
|
||||
enum/RES:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: TwelveBit
|
||||
description: 12-bit (14 ADCCLK cycles)
|
||||
value: 0
|
||||
- name: TenBit
|
||||
description: 10-bit (13 ADCCLK cycles)
|
||||
value: 1
|
||||
- name: EightBit
|
||||
description: 8-bit (11 ADCCLK cycles)
|
||||
value: 2
|
||||
- name: SixBit
|
||||
description: 6-bit (9 ADCCLK cycles)
|
||||
value: 3
|
||||
enum/SCANDIR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Upward
|
||||
description: Upward scan (from CHSEL0 to CHSEL18)
|
||||
value: 0
|
||||
- name: Backward
|
||||
description: Backward scan (from CHSEL18 to CHSEL0)
|
||||
value: 1
|
||||
enum/SMP:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Cycles1_5
|
||||
description: 1.5 cycles
|
||||
value: 0
|
||||
- name: Cycles7_5
|
||||
description: 7.5 cycles
|
||||
value: 1
|
||||
- name: Cycles13_5
|
||||
description: 13.5 cycles
|
||||
value: 2
|
||||
- name: Cycles28_5
|
||||
description: 28.5 cycles
|
||||
value: 3
|
||||
- name: Cycles41_5
|
||||
description: 41.5 cycles
|
||||
value: 4
|
||||
- name: Cycles55_5
|
||||
description: 55.5 cycles
|
||||
value: 5
|
||||
- name: Cycles71_5
|
||||
description: 71.5 cycles
|
||||
value: 6
|
||||
- name: Cycles239_5
|
||||
description: 239.5 cycles
|
||||
value: 7
|
||||
enum/TSEN:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Temperature sensor disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Temperature sensor enabled
|
||||
value: 1
|
||||
enum/VBATEN:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: V_BAT channel disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: V_BAT channel enabled
|
||||
value: 1
|
||||
968
data/registers/adc_v4.yaml
Normal file
968
data/registers/adc_v4.yaml
Normal file
@ -0,0 +1,968 @@
|
||||
---
|
||||
block/ADC:
|
||||
description: Analog to Digital Converter
|
||||
items:
|
||||
- name: ISR
|
||||
description: interrupt and status register
|
||||
byte_offset: 0
|
||||
fieldset: ISR
|
||||
- name: IER
|
||||
description: interrupt enable register
|
||||
byte_offset: 4
|
||||
fieldset: IER
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 8
|
||||
fieldset: CR
|
||||
- name: CFGR
|
||||
description: configuration register 1
|
||||
byte_offset: 12
|
||||
fieldset: CFGR
|
||||
- name: CFGR2
|
||||
description: configuration register 2
|
||||
byte_offset: 16
|
||||
fieldset: CFGR2
|
||||
- name: SMPR
|
||||
description: sampling time register 1-2
|
||||
byte_offset: 20
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
fieldset: SMPR
|
||||
- name: PCSEL
|
||||
description: pre channel selection register
|
||||
byte_offset: 28
|
||||
fieldset: PCSEL
|
||||
- name: LTR1
|
||||
description: analog watchdog 1 threshold register
|
||||
byte_offset: 32
|
||||
fieldset: LTR1
|
||||
- name: HTR1
|
||||
description: analog watchdog 2 threshold register
|
||||
byte_offset: 36
|
||||
fieldset: HTR1
|
||||
- name: SQR1
|
||||
description: group regular sequencer ranks register 1
|
||||
byte_offset: 48
|
||||
fieldset: SQR1
|
||||
- name: SQR2
|
||||
description: group regular sequencer ranks register 2
|
||||
byte_offset: 52
|
||||
fieldset: SQR2
|
||||
- name: SQR3
|
||||
description: group regular sequencer ranks register 3
|
||||
byte_offset: 56
|
||||
fieldset: SQR3
|
||||
- name: SQR4
|
||||
description: group regular sequencer ranks register 4
|
||||
byte_offset: 60
|
||||
fieldset: SQR4
|
||||
- name: DR
|
||||
description: group regular conversion data register
|
||||
byte_offset: 64
|
||||
access: Read
|
||||
fieldset: DR
|
||||
- name: JSQR
|
||||
description: group injected sequencer register
|
||||
byte_offset: 76
|
||||
fieldset: JSQR
|
||||
- name: OFR
|
||||
description: offset number 1-4 register
|
||||
byte_offset: 96
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
fieldset: OFR
|
||||
- name: JDR
|
||||
description: group injected sequencer rank 1-4 register
|
||||
byte_offset: 128
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
access: Read
|
||||
fieldset: JDR
|
||||
- name: AWD2CR
|
||||
description: analog watchdog 2 configuration register
|
||||
byte_offset: 160
|
||||
fieldset: AWD2CR
|
||||
- name: AWD3CR
|
||||
description: analog watchdog 3 configuration register
|
||||
byte_offset: 164
|
||||
fieldset: AWD3CR
|
||||
- name: LTR2
|
||||
description: watchdog lower threshold register 2
|
||||
byte_offset: 176
|
||||
fieldset: LTR2
|
||||
- name: HTR2
|
||||
description: watchdog higher threshold register 2
|
||||
byte_offset: 180
|
||||
fieldset: HTR2
|
||||
- name: LTR3
|
||||
description: watchdog lower threshold register 3
|
||||
byte_offset: 184
|
||||
fieldset: LTR3
|
||||
- name: HTR3
|
||||
description: watchdog higher threshold register 3
|
||||
byte_offset: 188
|
||||
fieldset: HTR3
|
||||
- name: DIFSEL
|
||||
description: channel differential or single-ended mode selection register
|
||||
byte_offset: 192
|
||||
fieldset: DIFSEL
|
||||
- name: CALFACT
|
||||
description: calibration factors register
|
||||
byte_offset: 196
|
||||
fieldset: CALFACT
|
||||
- name: CALFACT2
|
||||
description: Calibration Factor register 2
|
||||
byte_offset: 200
|
||||
fieldset: CALFACT2
|
||||
fieldset/AWD2CR:
|
||||
description: analog watchdog 2 configuration register
|
||||
fields:
|
||||
- name: AWD2CH
|
||||
description: analog watchdog 2 monitored channel selection
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 20
|
||||
stride: 1
|
||||
fieldset/AWD3CR:
|
||||
description: analog watchdog 3 configuration register
|
||||
fields:
|
||||
- name: AWD3CH
|
||||
description: analog watchdog 3 monitored channel selection
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 20
|
||||
stride: 1
|
||||
fieldset/CALFACT:
|
||||
description: calibration factors register
|
||||
fields:
|
||||
- name: CALFACT_S
|
||||
description: calibration factor in single-ended mode
|
||||
bit_offset: 0
|
||||
bit_size: 11
|
||||
- name: CALFACT_D
|
||||
description: calibration factor in differential mode
|
||||
bit_offset: 16
|
||||
bit_size: 11
|
||||
fieldset/CALFACT2:
|
||||
description: Calibration Factor register 2
|
||||
fields:
|
||||
- name: LINCALFACT
|
||||
description: Linearity Calibration Factor
|
||||
bit_offset: 0
|
||||
bit_size: 30
|
||||
fieldset/CFGR:
|
||||
description: configuration register 1
|
||||
fields:
|
||||
- name: DMNGT
|
||||
description: DMA transfer enable
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
enum: DMNGT
|
||||
- name: RES
|
||||
description: data resolution
|
||||
bit_offset: 2
|
||||
bit_size: 3
|
||||
enum: RES
|
||||
- name: EXTSEL
|
||||
description: group regular external trigger source
|
||||
bit_offset: 5
|
||||
bit_size: 5
|
||||
enum: EXTSEL
|
||||
- name: EXTEN
|
||||
description: group regular external trigger polarity
|
||||
bit_offset: 10
|
||||
bit_size: 2
|
||||
enum: EXTEN
|
||||
- name: OVRMOD
|
||||
description: group regular overrun configuration
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
enum: OVRMOD
|
||||
- name: CONT
|
||||
description: group regular continuous conversion mode
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: AUTDLY
|
||||
description: low power auto wait
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: DISCEN
|
||||
description: group regular sequencer discontinuous mode
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: DISCNUM
|
||||
description: group regular sequencer discontinuous number of ranks
|
||||
bit_offset: 17
|
||||
bit_size: 3
|
||||
- name: JDISCEN
|
||||
description: group injected sequencer discontinuous mode
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: JQM
|
||||
description: group injected contexts queue mode
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
enum: JQM
|
||||
- name: AWD1SGL
|
||||
description: analog watchdog 1 monitoring a single channel or all channels
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
enum: AWD1SGL
|
||||
- name: AWD1EN
|
||||
description: analog watchdog 1 enable on scope group regular
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: JAWD1EN
|
||||
description: analog watchdog 1 enable on scope group injected
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: JAUTO
|
||||
description: group injected automatic trigger mode
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: AWD1CH
|
||||
description: analog watchdog 1 monitored channel selection
|
||||
bit_offset: 26
|
||||
bit_size: 5
|
||||
- name: JQDIS
|
||||
description: group injected contexts queue disable
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/CFGR2:
|
||||
description: configuration register 2
|
||||
fields:
|
||||
- name: ROVSE
|
||||
description: oversampler enable on scope group regular
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: JOVSE
|
||||
description: oversampler enable on scope group injected
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: OVSS
|
||||
description: oversampling shift
|
||||
bit_offset: 5
|
||||
bit_size: 4
|
||||
- name: TROVS
|
||||
description: oversampling discontinuous mode (triggered mode) for group regular
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: TROVS
|
||||
- name: ROVSM
|
||||
description: Regular Oversampling mode
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: ROVSM
|
||||
- name: RSHIFT1
|
||||
description: Right-shift data after Offset 1 correction
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: RSHIFT2
|
||||
description: Right-shift data after Offset 2 correction
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: RSHIFT3
|
||||
description: Right-shift data after Offset 3 correction
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: RSHIFT4
|
||||
description: Right-shift data after Offset 4 correction
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: OSVR
|
||||
description: Oversampling ratio
|
||||
bit_offset: 16
|
||||
bit_size: 10
|
||||
- name: LSHIFT
|
||||
description: Left shift factor
|
||||
bit_offset: 28
|
||||
bit_size: 4
|
||||
fieldset/CR:
|
||||
description: control register
|
||||
fields:
|
||||
- name: ADEN
|
||||
description: enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
enum_write: ADENW
|
||||
- name: ADDIS
|
||||
description: disable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
enum_write: ADDISW
|
||||
- name: ADSTART
|
||||
description: group regular conversion start
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: JADSTART
|
||||
description: group injected conversion start
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: ADSTP
|
||||
description: group regular conversion stop
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: ADSTP
|
||||
- name: JADSTP
|
||||
description: group injected conversion stop
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: ADSTP
|
||||
- name: BOOST
|
||||
description: Boost mode control
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
enum: BOOST
|
||||
- name: ADCALLIN
|
||||
description: Linearity calibration
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: LINCALRDYW1
|
||||
description: Linearity calibration ready Word 1
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: LINCALRDYW2
|
||||
description: Linearity calibration ready Word 2
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: LINCALRDYW3
|
||||
description: Linearity calibration ready Word 3
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: LINCALRDYW4
|
||||
description: Linearity calibration ready Word 4
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: LINCALRDYW5
|
||||
description: Linearity calibration ready Word 5
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: LINCALRDYW6
|
||||
description: Linearity calibration ready Word 6
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: ADVREGEN
|
||||
description: voltage regulator enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: DEEPPWD
|
||||
description: deep power down enable
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: ADCALDIF
|
||||
description: differential mode for calibration
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
enum: ADCALDIF
|
||||
- name: ADCAL
|
||||
description: calibration
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/DIFSEL:
|
||||
description: channel differential or single-ended mode selection register
|
||||
fields:
|
||||
- name: DIFSEL
|
||||
description: channel differential or single-ended mode for channel
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 20
|
||||
stride: 1
|
||||
enum: DIFSEL
|
||||
fieldset/DR:
|
||||
description: group regular conversion data register
|
||||
fields:
|
||||
- name: RDATA
|
||||
description: group regular conversion data
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/HTR1:
|
||||
description: analog watchdog 2 threshold register
|
||||
fields:
|
||||
- name: HTR1
|
||||
description: analog watchdog 2 threshold low
|
||||
bit_offset: 0
|
||||
bit_size: 26
|
||||
fieldset/HTR2:
|
||||
description: watchdog higher threshold register 2
|
||||
fields:
|
||||
- name: HTR2
|
||||
description: Analog watchdog 2 higher threshold
|
||||
bit_offset: 0
|
||||
bit_size: 26
|
||||
fieldset/HTR3:
|
||||
description: watchdog higher threshold register 3
|
||||
fields:
|
||||
- name: HTR3
|
||||
description: Analog watchdog 3 higher threshold
|
||||
bit_offset: 0
|
||||
bit_size: 26
|
||||
fieldset/IER:
|
||||
description: interrupt enable register
|
||||
fields:
|
||||
- name: ADRDYIE
|
||||
description: ready interrupt
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMPIE
|
||||
description: group regular end of sampling interrupt
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: EOCIE
|
||||
description: group regular end of unitary conversion interrupt
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOSIE
|
||||
description: group regular end of sequence conversions interrupt
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: OVRIE
|
||||
description: group regular overrun interrupt
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: JEOCIE
|
||||
description: group injected end of unitary conversion interrupt
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: JEOSIE
|
||||
description: group injected end of sequence conversions interrupt
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: AWD1IE
|
||||
description: analog watchdog 1 interrupt
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: AWD2IE
|
||||
description: analog watchdog 2 interrupt
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: AWD3IE
|
||||
description: analog watchdog 3 interrupt
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: JQOVFIE
|
||||
description: group injected contexts queue overflow interrupt
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
fieldset/ISR:
|
||||
description: interrupt and status register
|
||||
fields:
|
||||
- name: ADRDY
|
||||
description: ready flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMP
|
||||
description: group regular end of sampling flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: EOC
|
||||
description: group regular end of unitary conversion flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOS
|
||||
description: group regular end of sequence conversions flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: OVR
|
||||
description: group regular overrun flag
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: JEOC
|
||||
description: group injected end of unitary conversion flag
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: JEOS
|
||||
description: group injected end of sequence conversions flag
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: AWD1
|
||||
description: analog watchdog 1 flag
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: AWD2
|
||||
description: analog watchdog 2 flag
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: AWD3
|
||||
description: analog watchdog 3 flag
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: JQOVF
|
||||
description: group injected contexts queue overflow flag
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: LDORDY
|
||||
description: ADC LDO output voltage ready (not always available)
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
fieldset/JDR:
|
||||
description: group injected sequencer rank 1 register
|
||||
fields:
|
||||
- name: JDATA
|
||||
description: group injected sequencer rank 1 conversion data
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/JSQR:
|
||||
description: group injected sequencer register
|
||||
fields:
|
||||
- name: JL
|
||||
description: group injected sequencer scan length
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
- name: JEXTSEL
|
||||
description: group injected external trigger source
|
||||
bit_offset: 2
|
||||
bit_size: 5
|
||||
enum: JEXTSEL
|
||||
- name: JEXTEN
|
||||
description: group injected external trigger polarity
|
||||
bit_offset: 7
|
||||
bit_size: 2
|
||||
enum: JEXTEN
|
||||
- name: JSQ1
|
||||
description: group injected sequencer rank 1-4
|
||||
bit_offset: 9
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 4
|
||||
stride: 6
|
||||
fieldset/LTR1:
|
||||
description: analog watchdog 1 threshold register
|
||||
fields:
|
||||
- name: LTR1
|
||||
description: analog watchdog 1 threshold low
|
||||
bit_offset: 0
|
||||
bit_size: 26
|
||||
fieldset/LTR2:
|
||||
description: watchdog lower threshold register 2
|
||||
fields:
|
||||
- name: LTR2
|
||||
description: Analog watchdog 2 lower threshold
|
||||
bit_offset: 0
|
||||
bit_size: 26
|
||||
fieldset/LTR3:
|
||||
description: watchdog lower threshold register 3
|
||||
fields:
|
||||
- name: LTR3
|
||||
description: Analog watchdog 3 lower threshold
|
||||
bit_offset: 0
|
||||
bit_size: 26
|
||||
fieldset/OFR:
|
||||
description: offset number x register
|
||||
fields:
|
||||
- name: OFFSET1
|
||||
description: offset number x offset level
|
||||
bit_offset: 0
|
||||
bit_size: 26
|
||||
- name: OFFSET1_CH
|
||||
description: offset number x channel selection
|
||||
bit_offset: 26
|
||||
bit_size: 5
|
||||
- name: SSATE
|
||||
description: Signed saturation enable
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/PCSEL:
|
||||
description: channel preselection register
|
||||
fields:
|
||||
- name: PCSEL
|
||||
description: "Channel x (VINP[i]) pre selection"
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 20
|
||||
stride: 1
|
||||
enum: PCSEL
|
||||
fieldset/SMPR:
|
||||
description: sampling time register n
|
||||
fields:
|
||||
- name: SMP
|
||||
description: channel n * 10 + x sampling time
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 10
|
||||
stride: 3
|
||||
enum: SMP
|
||||
fieldset/SQR1:
|
||||
description: group regular sequencer ranks register 1
|
||||
fields:
|
||||
- name: L
|
||||
description: L3
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: SQ
|
||||
description: group regular sequencer rank 1-4
|
||||
bit_offset: 6
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 4
|
||||
stride: 6
|
||||
fieldset/SQR2:
|
||||
description: group regular sequencer ranks register 2
|
||||
fields:
|
||||
- name: SQ
|
||||
description: group regular sequencer rank 5-9
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 5
|
||||
stride: 6
|
||||
fieldset/SQR3:
|
||||
description: group regular sequencer ranks register 3
|
||||
fields:
|
||||
- name: SQ
|
||||
description: group regular sequencer rank 10-14
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 5
|
||||
stride: 6
|
||||
fieldset/SQR4:
|
||||
description: group regular sequencer ranks register 4
|
||||
fields:
|
||||
- name: SQ
|
||||
description: group regular sequencer rank 15-16
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 2
|
||||
stride: 6
|
||||
enum/ADCALDIF:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: SingleEnded
|
||||
description: Calibration for single-ended mode
|
||||
value: 0
|
||||
- name: Differential
|
||||
description: Calibration for differential mode
|
||||
value: 1
|
||||
enum/ADDISW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disable
|
||||
description: Disable conversion and go to power down mode
|
||||
value: 0
|
||||
enum/ADENW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enable
|
||||
description: Enable ADC
|
||||
value: 1
|
||||
enum/ADSTP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Stop
|
||||
description: Stop conversion of channel
|
||||
value: 1
|
||||
enum/AWD1SGL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: All
|
||||
description: Analog watchdog 1 enabled on all channels
|
||||
value: 0
|
||||
- name: Single
|
||||
description: Analog watchdog 1 enabled on single channel selected in AWD1CH
|
||||
value: 1
|
||||
enum/BOOST:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: LT6_25
|
||||
description: Boost mode used when clock ≤ 6.25 MHz
|
||||
value: 0
|
||||
- name: LT12_5
|
||||
description: Boost mode used when 6.25 MHz < clock ≤ 12.5 MHz
|
||||
value: 1
|
||||
- name: LT25
|
||||
description: Boost mode used when 12.5 MHz < clock ≤ 25.0 MHz
|
||||
value: 2
|
||||
- name: LT50
|
||||
description: Boost mode used when 25.0 MHz < clock ≤ 50.0 MHz
|
||||
value: 3
|
||||
enum/DIFSEL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: SingleEnded
|
||||
description: Input channel is configured in single-ended mode
|
||||
value: 0
|
||||
- name: Differential
|
||||
description: Input channel is configured in differential mode
|
||||
value: 1
|
||||
enum/DMNGT:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: DR
|
||||
description: Store output data in DR only
|
||||
value: 0
|
||||
- name: DMA_OneShot
|
||||
description: DMA One Shot Mode selected
|
||||
value: 1
|
||||
- name: DFSDM
|
||||
description: DFSDM mode selected
|
||||
value: 2
|
||||
- name: DMA_Circular
|
||||
description: DMA Circular Mode selected
|
||||
value: 3
|
||||
enum/EXTEN:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Trigger detection disabled
|
||||
value: 0
|
||||
- name: RisingEdge
|
||||
description: Trigger detection on the rising edge
|
||||
value: 1
|
||||
- name: FallingEdge
|
||||
description: Trigger detection on the falling edge
|
||||
value: 2
|
||||
- name: BothEdges
|
||||
description: Trigger detection on both the rising and falling edges
|
||||
value: 3
|
||||
enum/EXTSEL:
|
||||
bit_size: 5
|
||||
variants:
|
||||
- name: TIM1_CC1
|
||||
description: Timer 1 CC1 event
|
||||
value: 0
|
||||
- name: TIM1_CC2
|
||||
description: Timer 1 CC2 event
|
||||
value: 1
|
||||
- name: TIM1_CC3
|
||||
description: Timer 1 CC3 event
|
||||
value: 2
|
||||
- name: TIM2_CC2
|
||||
description: Timer 2 CC2 event
|
||||
value: 3
|
||||
- name: TIM3_TRGO
|
||||
description: Timer 3 TRGO event
|
||||
value: 4
|
||||
- name: TIM4_CC4
|
||||
description: Timer 4 CC4 event
|
||||
value: 5
|
||||
- name: EXTI11
|
||||
description: EXTI line 11
|
||||
value: 6
|
||||
- name: TIM8_TRGO
|
||||
description: Timer 8 TRGO event
|
||||
value: 7
|
||||
- name: TIM8_TRGO2
|
||||
description: Timer 8 TRGO2 event
|
||||
value: 8
|
||||
- name: TIM1_TRGO
|
||||
description: Timer 1 TRGO event
|
||||
value: 9
|
||||
- name: TIM1_TRGO2
|
||||
description: Timer 1 TRGO2 event
|
||||
value: 10
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 11
|
||||
- name: TIM4_TRGO
|
||||
description: Timer 4 TRGO event
|
||||
value: 12
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 13
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 14
|
||||
- name: TIM3_CC4
|
||||
description: Timer 3 CC4 event
|
||||
value: 15
|
||||
- name: HRTIM1_ADCTRG1
|
||||
description: HRTIM1_ADCTRG1 event
|
||||
value: 16
|
||||
- name: HRTIM1_ADCTRG3
|
||||
description: HRTIM1_ADCTRG3 event
|
||||
value: 17
|
||||
- name: LPTIM1_OUT
|
||||
description: LPTIM1_OUT event
|
||||
value: 18
|
||||
- name: LPTIM2_OUT
|
||||
description: LPTIM2_OUT event
|
||||
value: 19
|
||||
- name: LPTIM3_OUT
|
||||
description: LPTIM3_OUT event
|
||||
value: 20
|
||||
enum/JEXTEN:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Trigger detection disabled
|
||||
value: 0
|
||||
- name: RisingEdge
|
||||
description: Trigger detection on the rising edge
|
||||
value: 1
|
||||
- name: FallingEdge
|
||||
description: Trigger detection on the falling edge
|
||||
value: 2
|
||||
- name: BothEdges
|
||||
description: Trigger detection on both the rising and falling edges
|
||||
value: 3
|
||||
enum/JEXTSEL:
|
||||
bit_size: 5
|
||||
variants:
|
||||
- name: TIM1_TRGO
|
||||
description: Timer 1 TRGO event
|
||||
value: 0
|
||||
- name: TIM1_CC4
|
||||
description: Timer 1 CC4 event
|
||||
value: 1
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 2
|
||||
- name: TIM2_CC1
|
||||
description: Timer 2 CC1 event
|
||||
value: 3
|
||||
- name: TIM3_CC4
|
||||
description: Timer 3 CC4 event
|
||||
value: 4
|
||||
- name: TIM4_TRGO
|
||||
description: Timer 4 TRGO event
|
||||
value: 5
|
||||
- name: EXTI15
|
||||
description: EXTI line 15
|
||||
value: 6
|
||||
- name: TIM8_CC4
|
||||
description: Timer 8 CC4 event
|
||||
value: 7
|
||||
- name: TIM1_TRGO2
|
||||
description: Timer 1 TRGO2 event
|
||||
value: 8
|
||||
- name: TIM8_TRGO
|
||||
description: Timer 8 TRGO event
|
||||
value: 9
|
||||
- name: TIM8_TRGO2
|
||||
description: Timer 8 TRGO2 event
|
||||
value: 10
|
||||
- name: TIM3_CC3
|
||||
description: Timer 3 CC3 event
|
||||
value: 11
|
||||
- name: TIM3_TRGO
|
||||
description: Timer 3 TRGO event
|
||||
value: 12
|
||||
- name: TIM3_CC1
|
||||
description: Timer 3 CC1 event
|
||||
value: 13
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 14
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 15
|
||||
- name: HRTIM1_ADCTRG2
|
||||
description: HRTIM1_ADCTRG2 event
|
||||
value: 16
|
||||
- name: HRTIM1_ADCTRG4
|
||||
description: HRTIM1_ADCTRG4 event
|
||||
value: 17
|
||||
- name: LPTIM1_OUT
|
||||
description: LPTIM1_OUT event
|
||||
value: 18
|
||||
- name: LPTIM2_OUT
|
||||
description: LPTIM2_OUT event
|
||||
value: 19
|
||||
- name: LPTIM3_OUT
|
||||
description: LPTIM3_OUT event
|
||||
value: 20
|
||||
enum/JQM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Mode0
|
||||
description: "JSQR Mode 0: Queue maintains the last written configuration into JSQR"
|
||||
value: 0
|
||||
- name: Mode1
|
||||
description: "JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence"
|
||||
value: 1
|
||||
enum/OVRMOD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Preserve
|
||||
description: Preserve DR register when an overrun is detected
|
||||
value: 0
|
||||
- name: Overwrite
|
||||
description: Overwrite DR register when an overrun is detected
|
||||
value: 1
|
||||
enum/PCSEL:
|
||||
bit_size: 20
|
||||
variants:
|
||||
- name: NotPreselected
|
||||
description: Input channel x is not pre-selected
|
||||
value: 0
|
||||
- name: Preselected
|
||||
description: Pre-select input channel x
|
||||
value: 1
|
||||
enum/RES:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: SixteenBit
|
||||
description: 16-bit resolution
|
||||
value: 0
|
||||
- name: FourteenBit
|
||||
description: 14-bit resolution in legacy mode (not optimized power consumption)
|
||||
value: 1
|
||||
- name: TwelveBit
|
||||
description: 12-bit resolution in legacy mode (not optimized power consumption)
|
||||
value: 2
|
||||
- name: TenBit
|
||||
description: 10-bit resolution
|
||||
value: 3
|
||||
- name: FourteenBitV
|
||||
description: 14-bit resolution
|
||||
value: 5
|
||||
- name: TwelveBitV
|
||||
description: 12-bit resolution
|
||||
value: 6
|
||||
- name: EightBit
|
||||
description: 8-bit resolution
|
||||
value: 7
|
||||
enum/ROVSM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Continued
|
||||
description: Oversampling is temporary stopped and continued after injection sequence
|
||||
value: 0
|
||||
- name: Resumed
|
||||
description: Oversampling is aborted and resumed from start after injection sequence
|
||||
value: 1
|
||||
enum/SMP:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Cycles1_5
|
||||
description: 1.5 clock cycles
|
||||
value: 0
|
||||
- name: Cycles2_5
|
||||
description: 2.5 clock cycles
|
||||
value: 1
|
||||
- name: Cycles8_5
|
||||
description: 8.5 clock cycles
|
||||
value: 2
|
||||
- name: Cycles16_5
|
||||
description: 16.5 clock cycles
|
||||
value: 3
|
||||
- name: Cycles32_5
|
||||
description: 32.5 clock cycles
|
||||
value: 4
|
||||
- name: Cycles64_5
|
||||
description: 64.5 clock cycles
|
||||
value: 5
|
||||
- name: Cycles387_5
|
||||
description: 387.5 clock cycles
|
||||
value: 6
|
||||
- name: Cycles810_5
|
||||
description: 810.5 clock cycles
|
||||
value: 7
|
||||
enum/TROVS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Automatic
|
||||
description: All oversampled conversions for a channel are run following a trigger
|
||||
value: 0
|
||||
- name: Triggered
|
||||
description: Each oversampled conversion for a channel needs a new trigger
|
||||
value: 1
|
||||
367
data/registers/adccommon_v4.yaml
Normal file
367
data/registers/adccommon_v4.yaml
Normal file
@ -0,0 +1,367 @@
|
||||
---
|
||||
block/ADC_COMMON:
|
||||
description: Analog-to-Digital Converter
|
||||
items:
|
||||
- name: CSR
|
||||
description: ADC Common status register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: CSR
|
||||
- name: CCR
|
||||
description: ADC common control register
|
||||
byte_offset: 8
|
||||
fieldset: CCR
|
||||
- name: CDR
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
byte_offset: 12
|
||||
access: Read
|
||||
fieldset: CDR
|
||||
- name: CDR2
|
||||
description: ADC x common regular data register for 32-bit dual mode
|
||||
byte_offset: 16
|
||||
access: Read
|
||||
fieldset: CDR2
|
||||
fieldset/CCR:
|
||||
description: ADC common control register
|
||||
fields:
|
||||
- name: DUAL
|
||||
description: Dual ADC mode selection
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
enum: DUAL
|
||||
- name: DELAY
|
||||
description: Delay between 2 sampling phases
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
- name: DAMDF
|
||||
description: Dual ADC Mode Data Format
|
||||
bit_offset: 14
|
||||
bit_size: 2
|
||||
enum: DAMDF
|
||||
- name: CKMODE
|
||||
description: ADC clock mode
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: CKMODE
|
||||
- name: PRESC
|
||||
description: ADC prescaler
|
||||
bit_offset: 18
|
||||
bit_size: 4
|
||||
enum: PRESC
|
||||
- name: VREFEN
|
||||
description: VREFINT enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: VSENSEEN
|
||||
description: Temperature sensor enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: VBATEN
|
||||
description: VBAT enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/CDR:
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
fields:
|
||||
- name: RDATA_MST
|
||||
description: Regular data of the master ADC
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: RDATA_SLV
|
||||
description: Regular data of the slave ADC
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/CDR2:
|
||||
description: ADC x common regular data register for 32-bit dual mode
|
||||
fields:
|
||||
- name: RDATA_ALT
|
||||
description: Regular data of the master/slave alternated ADCs
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/CSR:
|
||||
description: ADC Common status register
|
||||
fields:
|
||||
- name: ADRDY_MST
|
||||
description: Master ADC ready
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
enum: ADRDY_MST
|
||||
- name: EOSMP_MST
|
||||
description: End of Sampling phase flag of the master ADC
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
enum: EOSMP_MST
|
||||
- name: EOC_MST
|
||||
description: End of regular conversion of the master ADC
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum: EOC_MST
|
||||
- name: EOS_MST
|
||||
description: End of regular sequence flag of the master ADC
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
enum: EOS_MST
|
||||
- name: OVR_MST
|
||||
description: Overrun flag of the master ADC
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: OVR_MST
|
||||
- name: JEOC_MST
|
||||
description: End of injected conversion flag of the master ADC
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: JEOC_MST
|
||||
- name: JEOS_MST
|
||||
description: End of injected sequence flag of the master ADC
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
enum: JEOS_MST
|
||||
- name: AWD1_MST
|
||||
description: Analog watchdog 1 flag of the master ADC
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: AWD2_MST
|
||||
description: Analog watchdog 2 flag of the master ADC
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: AWD3_MST
|
||||
description: Analog watchdog 3 flag of the master ADC
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: JQOVF_MST
|
||||
description: Injected Context Queue Overflow flag of the master ADC
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: JQOVF_MST
|
||||
- name: ADRDY_SLV
|
||||
description: Slave ADC ready
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
enum: ADRDY_MST
|
||||
- name: EOSMP_SLV
|
||||
description: End of Sampling phase flag of the slave ADC
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
enum: EOSMP_MST
|
||||
- name: EOC_SLV
|
||||
description: End of regular conversion of the slave ADC
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
enum: EOC_MST
|
||||
- name: EOS_SLV
|
||||
description: End of regular sequence flag of the slave ADC
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
enum: EOS_MST
|
||||
- name: OVR_SLV
|
||||
description: Overrun flag of the slave ADC
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
enum: OVR_MST
|
||||
- name: JEOC_SLV
|
||||
description: End of injected conversion flag of the slave ADC
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
enum: JEOC_MST
|
||||
- name: JEOS_SLV
|
||||
description: End of injected sequence flag of the slave ADC
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
enum: JEOS_MST
|
||||
- name: AWD1_SLV
|
||||
description: Analog watchdog 1 flag of the slave ADC
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: AWD2_SLV
|
||||
description: Analog watchdog 2 flag of the slave ADC
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: AWD3_SLV
|
||||
description: Analog watchdog 3 flag of the slave ADC
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
enum: AWD1_MST
|
||||
- name: JQOVF_SLV
|
||||
description: Injected Context Queue Overflow flag of the slave ADC
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
enum: JQOVF_MST
|
||||
enum/ADRDY_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotReady
|
||||
description: ADC is not ready to start conversion
|
||||
value: 0
|
||||
- name: Ready
|
||||
description: ADC is ready to start conversion
|
||||
value: 1
|
||||
enum/AWD1_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoEvent
|
||||
description: No analog watchdog event occurred
|
||||
value: 0
|
||||
- name: Event
|
||||
description: Analog watchdog event occurred
|
||||
value: 1
|
||||
enum/CKMODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Asynchronous
|
||||
description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
|
||||
value: 0
|
||||
- name: SyncDiv1
|
||||
description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
|
||||
value: 1
|
||||
- name: SyncDiv2
|
||||
description: Use AHB clock rcc_hclk3 divided by 2
|
||||
value: 2
|
||||
- name: SyncDiv4
|
||||
description: Use AHB clock rcc_hclk3 divided by 4
|
||||
value: 3
|
||||
enum/DAMDF:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: NoPack
|
||||
description: "Without data packing, CDR/CDR2 not used"
|
||||
value: 0
|
||||
- name: Format32to10
|
||||
description: CDR formatted for 32-bit down to 10-bit resolution
|
||||
value: 2
|
||||
- name: Format8
|
||||
description: CDR formatted for 8-bit resolution
|
||||
value: 3
|
||||
enum/DUAL:
|
||||
bit_size: 5
|
||||
variants:
|
||||
- name: Independent
|
||||
description: Independent mode
|
||||
value: 0
|
||||
- name: DualRJ
|
||||
description: "Dual, combined regular simultaneous + injected simultaneous mode"
|
||||
value: 1
|
||||
- name: DualRA
|
||||
description: "Dual, combined regular simultaneous + alternate trigger mode"
|
||||
value: 2
|
||||
- name: DualIJ
|
||||
description: "Dual, combined interleaved mode + injected simultaneous mode"
|
||||
value: 3
|
||||
- name: DualJ
|
||||
description: "Dual, injected simultaneous mode only"
|
||||
value: 5
|
||||
- name: DualR
|
||||
description: "Dual, regular simultaneous mode only"
|
||||
value: 6
|
||||
- name: DualI
|
||||
description: "Dual, interleaved mode only"
|
||||
value: 7
|
||||
- name: DualA
|
||||
description: "Dual, alternate trigger mode only"
|
||||
value: 9
|
||||
enum/EOC_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotComplete
|
||||
description: Regular conversion is not complete
|
||||
value: 0
|
||||
- name: Complete
|
||||
description: Regular conversion complete
|
||||
value: 1
|
||||
enum/EOSMP_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotEnded
|
||||
description: End of sampling phase no yet reached
|
||||
value: 0
|
||||
- name: Ended
|
||||
description: End of sampling phase reached
|
||||
value: 1
|
||||
enum/EOS_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotComplete
|
||||
description: Regular sequence is not complete
|
||||
value: 0
|
||||
- name: Complete
|
||||
description: Regular sequence complete
|
||||
value: 1
|
||||
enum/JEOC_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotComplete
|
||||
description: Injected conversion is not complete
|
||||
value: 0
|
||||
- name: Complete
|
||||
description: Injected conversion complete
|
||||
value: 1
|
||||
enum/JEOS_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotComplete
|
||||
description: Injected sequence is not complete
|
||||
value: 0
|
||||
- name: Complete
|
||||
description: Injected sequence complete
|
||||
value: 1
|
||||
enum/JQOVF_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoOverflow
|
||||
description: No injected context queue overflow has occurred
|
||||
value: 0
|
||||
- name: Overflow
|
||||
description: Injected context queue overflow has occurred
|
||||
value: 1
|
||||
enum/OVR_MST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoOverrun
|
||||
description: No overrun occurred
|
||||
value: 0
|
||||
- name: Overrun
|
||||
description: Overrun occurred
|
||||
value: 1
|
||||
enum/PRESC:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Div1
|
||||
description: adc_ker_ck_input not divided
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: adc_ker_ck_input divided by 2
|
||||
value: 1
|
||||
- name: Div4
|
||||
description: adc_ker_ck_input divided by 4
|
||||
value: 2
|
||||
- name: Div6
|
||||
description: adc_ker_ck_input divided by 6
|
||||
value: 3
|
||||
- name: Div8
|
||||
description: adc_ker_ck_input divided by 8
|
||||
value: 4
|
||||
- name: Div10
|
||||
description: adc_ker_ck_input divided by 10
|
||||
value: 5
|
||||
- name: Div12
|
||||
description: adc_ker_ck_input divided by 12
|
||||
value: 6
|
||||
- name: Div16
|
||||
description: adc_ker_ck_input divided by 16
|
||||
value: 7
|
||||
- name: Div32
|
||||
description: adc_ker_ck_input divided by 32
|
||||
value: 8
|
||||
- name: Div64
|
||||
description: adc_ker_ck_input divided by 64
|
||||
value: 9
|
||||
- name: Div128
|
||||
description: adc_ker_ck_input divided by 128
|
||||
value: 10
|
||||
- name: Div256
|
||||
description: adc_ker_ck_input divided by 256
|
||||
value: 11
|
||||
2142
data/registers/eth_v1a.yaml
Normal file
2142
data/registers/eth_v1a.yaml
Normal file
File diff suppressed because it is too large
Load Diff
2220
data/registers/eth_v1b.yaml
Normal file
2220
data/registers/eth_v1b.yaml
Normal file
File diff suppressed because it is too large
Load Diff
@ -51,17 +51,14 @@ fieldset/ACR:
|
||||
description: Flash half cycle access enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
enum: HLFCYA
|
||||
- name: PRFTBE
|
||||
description: PRFTBE
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: PRFTBE
|
||||
- name: PRFTBS
|
||||
description: PRFTBS
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: PRFTBS
|
||||
fieldset/AR:
|
||||
description: Flash address register
|
||||
fields:
|
||||
@ -76,17 +73,14 @@ fieldset/CR:
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
enum: PG
|
||||
- name: PER
|
||||
description: Page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
enum: PER
|
||||
- name: MER
|
||||
description: Mass erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum: MER
|
||||
- name: OPTPG
|
||||
description: Option byte programming
|
||||
bit_offset: 4
|
||||
@ -96,33 +90,26 @@ fieldset/CR:
|
||||
description: Option byte erase
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: OPTER
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
enum: STRT
|
||||
- name: LOCK
|
||||
description: Lock
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum_read: LOCKR
|
||||
enum_write: LOCKW
|
||||
- name: OPTWRE
|
||||
description: Option bytes write enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: OPTWRE
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: ERRIE
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
enum: EOPIE
|
||||
- name: OBL_LAUNCH
|
||||
description: Force option byte loading
|
||||
bit_offset: 13
|
||||
@ -142,7 +129,6 @@ fieldset/OBR:
|
||||
description: Option byte error
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
enum: OPTERR
|
||||
- name: RDPRT
|
||||
description: Read protection Level status
|
||||
bit_offset: 1
|
||||
@ -167,12 +153,10 @@ fieldset/OBR:
|
||||
description: BOOT1
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
enum: nBOOT
|
||||
- name: VDDA_MONITOR
|
||||
description: VDDA_MONITOR
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
enum: VDDA_MONITOR
|
||||
- name: SRAM_PARITY_CHECK
|
||||
description: SRAM_PARITY_CHECK
|
||||
bit_offset: 14
|
||||
@ -181,7 +165,6 @@ fieldset/OBR:
|
||||
description: SDADC12_VDD_MONITOR
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum: SDADC_VDD_MONITOR
|
||||
- name: Data0
|
||||
description: Data0
|
||||
bit_offset: 16
|
||||
@ -204,25 +187,18 @@ fieldset/SR:
|
||||
description: Busy
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
enum_read: BSYR
|
||||
- name: PGERR
|
||||
description: Programming error
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum_read: PGERRR
|
||||
enum_write: PGERRW
|
||||
- name: WRPRTERR
|
||||
description: Write protection error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum_read: WRPRTERRR
|
||||
enum_write: WRPRTERRW
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum_read: EOPR
|
||||
enum_write: EOPW
|
||||
fieldset/WRPR:
|
||||
description: Write protection register
|
||||
fields:
|
||||
@ -230,57 +206,6 @@ fieldset/WRPR:
|
||||
description: Write protect
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
enum/BSYR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Inactive
|
||||
description: No write/erase operation is in progress
|
||||
value: 0
|
||||
- name: Active
|
||||
description: No write/erase operation is in progress
|
||||
value: 1
|
||||
enum/EOPIE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: End of operation interrupt disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: End of operation interrupt enabled
|
||||
value: 1
|
||||
enum/EOPR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoEvent
|
||||
description: No EOP event occurred
|
||||
value: 0
|
||||
- name: Event
|
||||
description: An EOP event occurred
|
||||
value: 1
|
||||
enum/EOPW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Reset
|
||||
description: Reset EOP event
|
||||
value: 1
|
||||
enum/ERRIE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Error interrupt generation disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Error interrupt generation enabled
|
||||
value: 1
|
||||
enum/HLFCYA:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Half cycle is disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Half cycle is enabled
|
||||
value: 1
|
||||
enum/LATENCY:
|
||||
bit_size: 3
|
||||
variants:
|
||||
@ -293,27 +218,6 @@ enum/LATENCY:
|
||||
- name: WS2
|
||||
description: "2 wait states, if 48 < HCLK <= 72 MHz"
|
||||
value: 2
|
||||
enum/LOCKR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Unlocked
|
||||
description: FLASH_CR register is unlocked
|
||||
value: 0
|
||||
- name: Locked
|
||||
description: FLASH_CR register is locked
|
||||
value: 1
|
||||
enum/LOCKW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Lock
|
||||
description: Lock the FLASH_CR register
|
||||
value: 1
|
||||
enum/MER:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: MassErase
|
||||
description: Erase activated for all user sectors
|
||||
value: 1
|
||||
enum/OBL_LAUNCH:
|
||||
bit_size: 1
|
||||
variants:
|
||||
@ -323,78 +227,12 @@ enum/OBL_LAUNCH:
|
||||
- name: Active
|
||||
description: Force option byte loading active
|
||||
value: 1
|
||||
enum/OPTER:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: OptionByteErase
|
||||
description: Erase option byte activated
|
||||
value: 1
|
||||
enum/OPTERR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: OptionByteError
|
||||
description: The loaded option byte and its complement do not match
|
||||
value: 1
|
||||
enum/OPTPG:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: OptionByteProgramming
|
||||
description: Program option byte activated
|
||||
value: 1
|
||||
enum/OPTWRE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Option byte write enabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Option byte write disabled
|
||||
value: 1
|
||||
enum/PER:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: PageErase
|
||||
description: Erase activated for selected page
|
||||
value: 1
|
||||
enum/PG:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Program
|
||||
description: Flash programming activated
|
||||
value: 1
|
||||
enum/PGERRR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoError
|
||||
description: No programming error occurred
|
||||
value: 0
|
||||
- name: Error
|
||||
description: A programming error occurred
|
||||
value: 1
|
||||
enum/PGERRW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Reset
|
||||
description: Reset programming error
|
||||
value: 1
|
||||
enum/PRFTBE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Prefetch is disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Prefetch is enabled
|
||||
value: 1
|
||||
enum/PRFTBS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Prefetch buffer is disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Prefetch buffer is enabled
|
||||
value: 1
|
||||
enum/RDPRT:
|
||||
bit_size: 2
|
||||
variants:
|
||||
@ -407,39 +245,6 @@ enum/RDPRT:
|
||||
- name: Level2
|
||||
description: Level 2
|
||||
value: 3
|
||||
enum/SDADC_VDD_MONITOR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: VDDSD12 monitoring disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: VDDSD12 monitoring enabled
|
||||
value: 1
|
||||
enum/SRAM_PARITY_CHECK:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: RAM parity check disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: RAM parity check enabled
|
||||
value: 1
|
||||
enum/STRT:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Start
|
||||
description: Trigger an erase operation
|
||||
value: 1
|
||||
enum/VDDA_MONITOR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: VDDA power supply supervisor disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: VDDA power supply supervisor enabled
|
||||
value: 1
|
||||
enum/WDG_SW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
@ -449,30 +254,6 @@ enum/WDG_SW:
|
||||
- name: Software
|
||||
description: Software watchdog
|
||||
value: 1
|
||||
enum/WRPRTERRR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoError
|
||||
description: No write protection error occurred
|
||||
value: 0
|
||||
- name: Error
|
||||
description: A write protection error occurred
|
||||
value: 1
|
||||
enum/WRPRTERRW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Reset
|
||||
description: Reset write protection error
|
||||
value: 1
|
||||
enum/nBOOT:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: "Together with BOOT0, select the device boot mode"
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "Together with BOOT0, select the device boot mode"
|
||||
value: 1
|
||||
enum/nRST_STDBY:
|
||||
bit_size: 1
|
||||
variants:
|
||||
|
||||
@ -48,17 +48,14 @@ fieldset/ACR:
|
||||
description: Prefetch enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: PRFTEN
|
||||
- name: ARTEN
|
||||
description: ART Accelerator Enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: ARTEN
|
||||
- name: ARTRST
|
||||
description: ART Accelerator reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
enum: ARTRST
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
@ -66,17 +63,14 @@ fieldset/CR:
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
enum: PG
|
||||
- name: SER
|
||||
description: Sector Erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
enum: SER
|
||||
- name: MER
|
||||
description: Mass Erase of sectors 0 to 11
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum: MER
|
||||
- name: SNB
|
||||
description: Sector number
|
||||
bit_offset: 3
|
||||
@ -90,17 +84,14 @@ fieldset/CR:
|
||||
description: Start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
enum: STRT
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
enum: EOPIE
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
enum: ERRIE
|
||||
- name: RDERRIE
|
||||
description: PCROP error interrupt enable
|
||||
bit_offset: 26
|
||||
@ -109,7 +100,6 @@ fieldset/CR:
|
||||
description: Lock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
enum: LOCK
|
||||
fieldset/KEYR:
|
||||
description: Flash key register
|
||||
fields:
|
||||
@ -236,15 +226,6 @@ fieldset/SR:
|
||||
description: Busy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
enum/ARTEN:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: ART Accelerator is disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: ART Accelerator is enabled
|
||||
value: 1
|
||||
enum/ARTRST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
@ -254,24 +235,6 @@ enum/ARTRST:
|
||||
- name: Reset
|
||||
description: Accelerator is reset
|
||||
value: 1
|
||||
enum/EOPIE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: End of operation interrupt disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: End of operation interrupt enabled
|
||||
value: 1
|
||||
enum/ERRIE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Error interrupt generation disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Error interrupt generation enabled
|
||||
value: 1
|
||||
enum/LATENCY:
|
||||
bit_size: 4
|
||||
variants:
|
||||
@ -323,36 +286,6 @@ enum/LATENCY:
|
||||
- name: WS15
|
||||
description: 15 wait states
|
||||
value: 15
|
||||
enum/LOCK:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Unlocked
|
||||
description: FLASH_CR register is unlocked
|
||||
value: 0
|
||||
- name: Locked
|
||||
description: FLASH_CR register is locked
|
||||
value: 1
|
||||
enum/MER:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: MassErase
|
||||
description: Erase activated for all user sectors
|
||||
value: 1
|
||||
enum/PG:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Program
|
||||
description: Flash programming activated
|
||||
value: 1
|
||||
enum/PRFTEN:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Prefetch is disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Prefetch is enabled
|
||||
value: 1
|
||||
enum/PSIZE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
@ -368,15 +301,3 @@ enum/PSIZE:
|
||||
- name: PSIZE64
|
||||
description: Program x64
|
||||
value: 3
|
||||
enum/SER:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: SectorErase
|
||||
description: Erase activated for selected sector
|
||||
value: 1
|
||||
enum/STRT:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Start
|
||||
description: Trigger an erase operation
|
||||
value: 1
|
||||
|
||||
@ -386,69 +386,69 @@ fieldset/WRP1BR:
|
||||
description: WRP area B end offset
|
||||
bit_offset: 16
|
||||
bit_size: 6
|
||||
enum/LATENCY:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: WS0
|
||||
description: Zero wait states
|
||||
value: 0b000
|
||||
- name: WS1
|
||||
description: One wait state
|
||||
value: 0b001
|
||||
- name: WS2
|
||||
description: Two wait states
|
||||
value: 0b010
|
||||
enum/NRST_MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: INPUT_ONLY
|
||||
description: Reset pin is in reset input mode only
|
||||
value: 0b01
|
||||
- name: GPIO
|
||||
description: Reset pin is in GPIO mode only
|
||||
value: 0b10
|
||||
- name: INPUT_OUTPUT
|
||||
description: Reset pin is in resety input and output mode
|
||||
value: 0b11
|
||||
enum/BORR_LEV:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: RISING_0
|
||||
description: BOR rising level 1 with threshold around 2.1V
|
||||
value: 0b00
|
||||
- name: RISING_1
|
||||
description: BOR rising level 2 with threshold around 2.3V
|
||||
value: 0b01
|
||||
- name: RISING_2
|
||||
description: BOR rising level 3 with threshold around 2.6V
|
||||
value: 0b10
|
||||
- name: RISING_3
|
||||
description: BOR rising level 4 with threshold around 2.9V
|
||||
value: 0b11
|
||||
enum/BORF_LEV:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: FALLING_0
|
||||
description: BOR falling level 1 with threshold around 2.0V
|
||||
value: 0b00
|
||||
value: 0
|
||||
- name: FALLING_1
|
||||
description: BOR falling level 2 with threshold around 2.2V
|
||||
value: 0b01
|
||||
value: 1
|
||||
- name: FALLING_2
|
||||
description: BOR falling level 3 with threshold around 2.5V
|
||||
value: 0b10
|
||||
value: 2
|
||||
- name: FALLING_3
|
||||
description: BOR falling level 4 with threshold around 2.8V
|
||||
value: 0b11
|
||||
value: 3
|
||||
enum/BORR_LEV:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: RISING_0
|
||||
description: BOR rising level 1 with threshold around 2.1V
|
||||
value: 0
|
||||
- name: RISING_1
|
||||
description: BOR rising level 2 with threshold around 2.3V
|
||||
value: 1
|
||||
- name: RISING_2
|
||||
description: BOR rising level 3 with threshold around 2.6V
|
||||
value: 2
|
||||
- name: RISING_3
|
||||
description: BOR rising level 4 with threshold around 2.9V
|
||||
value: 3
|
||||
enum/LATENCY:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: WS0
|
||||
description: Zero wait states
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: One wait state
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: Two wait states
|
||||
value: 2
|
||||
enum/NRST_MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: INPUT_ONLY
|
||||
description: Reset pin is in reset input mode only
|
||||
value: 1
|
||||
- name: GPIO
|
||||
description: Reset pin is in GPIO mode only
|
||||
value: 2
|
||||
- name: INPUT_OUTPUT
|
||||
description: Reset pin is in resety input and output mode
|
||||
value: 3
|
||||
enum/RDP:
|
||||
bit_size: 8
|
||||
variants:
|
||||
- name: LEVEL_0
|
||||
value: 0xAA
|
||||
description: Read protection not active
|
||||
value: 170
|
||||
- name: LEVEL_1
|
||||
value: 0xBB
|
||||
description: Memories read protection active
|
||||
value: 187
|
||||
- name: LEVEL_2
|
||||
value: 0xCC
|
||||
description: Chip read protection active
|
||||
value: 204
|
||||
|
||||
240
data/registers/flash_l0.yaml
Normal file
240
data/registers/flash_l0.yaml
Normal file
@ -0,0 +1,240 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
- name: ACR
|
||||
description: Access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: PECR
|
||||
description: Program/erase control register
|
||||
byte_offset: 4
|
||||
fieldset: PECR
|
||||
- name: PDKEYR
|
||||
description: Power down key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: PDKEYR
|
||||
- name: PEKEYR
|
||||
description: Program/erase key register
|
||||
byte_offset: 12
|
||||
access: Write
|
||||
fieldset: PEKEYR
|
||||
- name: PRGKEYR
|
||||
description: Program memory key register
|
||||
byte_offset: 16
|
||||
access: Write
|
||||
fieldset: PRGKEYR
|
||||
- name: OPTKEYR
|
||||
description: Option byte key register
|
||||
byte_offset: 20
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 24
|
||||
fieldset: SR
|
||||
- name: OPTR
|
||||
description: Option byte register
|
||||
byte_offset: 28
|
||||
access: Read
|
||||
fieldset: OPTR
|
||||
- name: WRPROT1
|
||||
description: Write Protection Register 1
|
||||
byte_offset: 32
|
||||
access: Read
|
||||
fieldset: WRPROT1
|
||||
- name: WRPROT2
|
||||
description: Write Protection Register 2
|
||||
byte_offset: 128
|
||||
access: Read
|
||||
fieldset: WRPROT2
|
||||
fieldset/ACR:
|
||||
description: Access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: SLEEP_PD
|
||||
description: Flash mode during Sleep
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: RUN_PD
|
||||
description: Flash mode during Run
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: DISAB_BUF
|
||||
description: Disable Buffer
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: PRE_READ
|
||||
description: Pre-read data address
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/OPTKEYR:
|
||||
description: Option byte key register
|
||||
fields:
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTR:
|
||||
description: Option byte register
|
||||
fields:
|
||||
- name: RDPROT
|
||||
description: Read protection
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: WPRMOD
|
||||
description: Selection of protection mode of WPR bits
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: BOR_LEV
|
||||
description: BOR_LEV
|
||||
bit_offset: 16
|
||||
bit_size: 4
|
||||
fieldset/PDKEYR:
|
||||
description: Power down key register
|
||||
fields:
|
||||
- name: PDKEYR
|
||||
description: RUN_PD in FLASH_ACR key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PECR:
|
||||
description: Program/erase control register
|
||||
fields:
|
||||
- name: PELOCK
|
||||
description: FLASH_PECR and data EEPROM lock
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PRGLOCK
|
||||
description: Program memory lock
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: Option bytes block lock
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PROG
|
||||
description: Program memory selection
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DATA
|
||||
description: Data EEPROM selection
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: FIX
|
||||
description: "Fixed time data write for Byte, Half Word and Word programming"
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ERASE
|
||||
description: Page or Double Word erase mode
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: FPRG
|
||||
description: Half Page/Double Word programming mode
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: PARALLELBANK
|
||||
description: Parallel bank mode
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of programming interrupt enable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: Launch the option byte loading
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
enum_write: OBL_LAUNCHW
|
||||
fieldset/PEKEYR:
|
||||
description: Program/erase key register
|
||||
fields:
|
||||
- name: PEKEYR
|
||||
description: FLASH_PEC and data EEPROM key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PRGKEYR:
|
||||
description: Program memory key register
|
||||
fields:
|
||||
- name: PRGKEYR
|
||||
description: Program memory key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: BSY
|
||||
description: Write/erase operations in progress
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: ENDHV
|
||||
description: End of high voltage
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: READY
|
||||
description: Flash memory module ready after low power mode
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protected error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: Size error
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: OPTVERR
|
||||
description: Option validity error
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: RDERR
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: NOTZEROERR
|
||||
description: NOTZEROERR
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: FWWERR
|
||||
description: FWWERR
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
fieldset/WRPROT1:
|
||||
description: Write Protection Register 1
|
||||
fields:
|
||||
- name: WRPROT
|
||||
description: Write Protection
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
array:
|
||||
len: 1
|
||||
stride: 0
|
||||
fieldset/WRPROT2:
|
||||
description: Write Protection Register 2
|
||||
fields:
|
||||
- name: WRPROT
|
||||
description: Write Protection
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
array:
|
||||
len: 1
|
||||
stride: 0
|
||||
698
data/registers/flash_l5.yaml
Normal file
698
data/registers/flash_l5.yaml
Normal file
@ -0,0 +1,698 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
- name: ACR
|
||||
description: Access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: PDKEYR
|
||||
description: Power down key register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: PDKEYR
|
||||
- name: NSKEYR
|
||||
description: Flash non-secure key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: NSKEYR
|
||||
- name: SECKEYR
|
||||
description: Flash secure key register
|
||||
byte_offset: 12
|
||||
access: Write
|
||||
fieldset: SECKEYR
|
||||
- name: OPTKEYR
|
||||
description: Flash option key register
|
||||
byte_offset: 16
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: LVEKEYR
|
||||
description: Flash low voltage key register
|
||||
byte_offset: 20
|
||||
access: Write
|
||||
fieldset: LVEKEYR
|
||||
- name: NSSR
|
||||
description: Flash status register
|
||||
byte_offset: 32
|
||||
fieldset: NSSR
|
||||
- name: SECSR
|
||||
description: Flash status register
|
||||
byte_offset: 36
|
||||
fieldset: SECSR
|
||||
- name: NSCR
|
||||
description: Flash non-secure control register
|
||||
byte_offset: 40
|
||||
fieldset: NSCR
|
||||
- name: SECCR
|
||||
description: Flash secure control register
|
||||
byte_offset: 44
|
||||
fieldset: SECCR
|
||||
- name: ECCR
|
||||
description: Flash ECC register
|
||||
byte_offset: 48
|
||||
fieldset: ECCR
|
||||
- name: OPTR
|
||||
description: Flash option register
|
||||
byte_offset: 64
|
||||
fieldset: OPTR
|
||||
- name: NSBOOTADD0R
|
||||
description: Flash non-secure boot address 0 register
|
||||
byte_offset: 68
|
||||
access: Write
|
||||
fieldset: NSBOOTADD0R
|
||||
- name: NSBOOTADD1R
|
||||
description: Flash non-secure boot address 1 register
|
||||
byte_offset: 72
|
||||
access: Write
|
||||
fieldset: NSBOOTADD1R
|
||||
- name: SECBOOTADD0R
|
||||
description: FFlash secure boot address 0 register
|
||||
byte_offset: 76
|
||||
fieldset: SECBOOTADD0R
|
||||
- name: SECWM1R1
|
||||
description: Flash bank 1 secure watermak1 register
|
||||
byte_offset: 80
|
||||
fieldset: SECWM1R1
|
||||
- name: SECWM1R2
|
||||
description: Flash secure watermak1 register 2
|
||||
byte_offset: 84
|
||||
fieldset: SECWM1R2
|
||||
- name: WRP1AR
|
||||
description: Flash Bank 1 WRP area A address register
|
||||
byte_offset: 88
|
||||
fieldset: WRP1AR
|
||||
- name: WRP1BR
|
||||
description: Flash Bank 1 WRP area B address register
|
||||
byte_offset: 92
|
||||
fieldset: WRP1BR
|
||||
- name: SECWM2R1
|
||||
description: Flash secure watermak2 register
|
||||
byte_offset: 96
|
||||
fieldset: SECWM2R1
|
||||
- name: SECWM2R2
|
||||
description: Flash secure watermak2 register2
|
||||
byte_offset: 100
|
||||
fieldset: SECWM2R2
|
||||
- name: WRP2AR
|
||||
description: Flash WPR2 area A address register
|
||||
byte_offset: 104
|
||||
fieldset: WRP2AR
|
||||
- name: WRP2BR
|
||||
description: Flash WPR2 area B address register
|
||||
byte_offset: 108
|
||||
fieldset: WRP2BR
|
||||
- name: SECBB1R1
|
||||
description: FLASH secure block based bank 1 register
|
||||
byte_offset: 128
|
||||
fieldset: SECBB1R1
|
||||
- name: SECBB1R2
|
||||
description: FLASH secure block based bank 1 register
|
||||
byte_offset: 132
|
||||
fieldset: SECBB1R2
|
||||
- name: SECBB1R3
|
||||
description: FLASH secure block based bank 1 register
|
||||
byte_offset: 136
|
||||
fieldset: SECBB1R3
|
||||
- name: SECBB1R4
|
||||
description: FLASH secure block based bank 1 register
|
||||
byte_offset: 140
|
||||
fieldset: SECBB1R4
|
||||
- name: SECBB2R1
|
||||
description: FLASH secure block based bank 2 register
|
||||
byte_offset: 160
|
||||
fieldset: SECBB2R1
|
||||
- name: SECBB2R2
|
||||
description: FLASH secure block based bank 2 register
|
||||
byte_offset: 164
|
||||
fieldset: SECBB2R2
|
||||
- name: SECBB2R3
|
||||
description: FLASH secure block based bank 2 register
|
||||
byte_offset: 168
|
||||
fieldset: SECBB2R3
|
||||
- name: SECBB2R4
|
||||
description: FLASH secure block based bank 2 register
|
||||
byte_offset: 172
|
||||
fieldset: SECBB2R4
|
||||
- name: SECHDPCR
|
||||
description: FLASH secure HDP control register
|
||||
byte_offset: 192
|
||||
fieldset: SECHDPCR
|
||||
- name: PRIVCFGR
|
||||
description: Power privilege configuration register
|
||||
byte_offset: 196
|
||||
fieldset: PRIVCFGR
|
||||
fieldset/ACR:
|
||||
description: Access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: RUN_PD
|
||||
description: Flash Power-down mode during Low-power run mode
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: SLEEP_PD
|
||||
description: Flash Power-down mode during Low-power sleep mode
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: LVEN
|
||||
description: LVEN
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
fieldset/ECCR:
|
||||
description: Flash ECC register
|
||||
fields:
|
||||
- name: ADDR_ECC
|
||||
description: ECC fail address
|
||||
bit_offset: 0
|
||||
bit_size: 19
|
||||
- name: BK_ECC
|
||||
description: BK_ECC
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: SYSF_ECC
|
||||
description: SYSF_ECC
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: ECCIE
|
||||
description: ECC correction interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ECCC2
|
||||
description: ECCC2
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: ECCD2
|
||||
description: ECCD2
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: ECCC
|
||||
description: ECC correction
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: ECCD
|
||||
description: ECC detection
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/LVEKEYR:
|
||||
description: Flash low voltage key register
|
||||
fields:
|
||||
- name: LVEKEYR
|
||||
description: LVEKEYR
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/NSBOOTADD0R:
|
||||
description: Flash non-secure boot address 0 register
|
||||
fields:
|
||||
- name: NSBOOTADD0
|
||||
description: NSBOOTADD0
|
||||
bit_offset: 7
|
||||
bit_size: 25
|
||||
fieldset/NSBOOTADD1R:
|
||||
description: Flash non-secure boot address 1 register
|
||||
fields:
|
||||
- name: NSBOOTADD1
|
||||
description: NSBOOTADD1
|
||||
bit_offset: 7
|
||||
bit_size: 25
|
||||
fieldset/NSCR:
|
||||
description: Flash non-secure control register
|
||||
fields:
|
||||
- name: NSPG
|
||||
description: NSPG
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: NSPER
|
||||
description: NSPER
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: NSMER1
|
||||
description: NSMER1
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: NSPNB
|
||||
description: NSPNB
|
||||
bit_offset: 3
|
||||
bit_size: 7
|
||||
- name: NSBKER
|
||||
description: NSBKER
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: NSMER2
|
||||
description: NSMER2
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: NSSTRT
|
||||
description: Options modification start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: Options modification start
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: NSEOPIE
|
||||
description: NSEOPIE
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: NSERRIE
|
||||
description: NSERRIE
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: Force the option byte loading
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: Options Lock
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: NSLOCK
|
||||
description: NSLOCK
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/NSKEYR:
|
||||
description: Flash non-secure key register
|
||||
fields:
|
||||
- name: NSKEYR
|
||||
description: NSKEYR
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/NSSR:
|
||||
description: Flash status register
|
||||
fields:
|
||||
- name: NSEOP
|
||||
description: NSEOP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: NSOPERR
|
||||
description: NSOPERR
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: NSPROGERR
|
||||
description: NSPROGERR
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: NSWRPERR
|
||||
description: NSWRPERR
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: NSPGAERR
|
||||
description: NSPGAERR
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: NSSIZERR
|
||||
description: NSSIZERR
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: NSPGSERR
|
||||
description: NSPGSERR
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: OPTWERR
|
||||
description: OPTWERR
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: OPTVERR
|
||||
description: OPTVERR
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: NSBSY
|
||||
description: NSBusy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
fieldset/OPTKEYR:
|
||||
description: Flash option key register
|
||||
fields:
|
||||
- name: OPTKEYR
|
||||
description: OPTKEYR
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTR:
|
||||
description: Flash option register
|
||||
fields:
|
||||
- name: RDP
|
||||
description: Read protection level
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: BOR_LEV
|
||||
description: BOR reset Level
|
||||
bit_offset: 8
|
||||
bit_size: 3
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: nRST_SHDW
|
||||
description: nRST_SHDW
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: IWDG_SW
|
||||
description: Independent watchdog selection
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: IWDG_STOP
|
||||
description: Independent watchdog counter freeze in Stop mode
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: IWDG_STDBY
|
||||
description: Independent watchdog counter freeze in Standby mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: WWDG_SW
|
||||
description: Window watchdog selection
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: SWAP_BANK
|
||||
description: SWAP_BANK
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: DB256K
|
||||
description: DB256K
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: DBANK
|
||||
description: DBANK
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: SRAM2_PE
|
||||
description: SRAM2 parity check enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: SRAM2_RST
|
||||
description: SRAM2 Erase when system reset
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: nSWBOOT0
|
||||
description: nSWBOOT0
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: nBOOT0
|
||||
description: nBOOT0
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: PA15_PUPEN
|
||||
description: PA15_PUPEN
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: TZEN
|
||||
description: TZEN
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/PDKEYR:
|
||||
description: Power down key register
|
||||
fields:
|
||||
- name: PDKEYR
|
||||
description: RUN_PD in FLASH_ACR key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PRIVCFGR:
|
||||
description: Power privilege configuration register
|
||||
fields:
|
||||
- name: PRIV
|
||||
description: PRIV
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
fieldset/SECBB1R1:
|
||||
description: FLASH secure block based bank 1 register
|
||||
fields:
|
||||
- name: SECBB1
|
||||
description: SECBB1
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SECBB1R2:
|
||||
description: FLASH secure block based bank 1 register
|
||||
fields:
|
||||
- name: SECBB1
|
||||
description: SECBB1
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SECBB1R3:
|
||||
description: FLASH secure block based bank 1 register
|
||||
fields:
|
||||
- name: SECBB1
|
||||
description: SECBB1
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SECBB1R4:
|
||||
description: FLASH secure block based bank 1 register
|
||||
fields:
|
||||
- name: SECBB1
|
||||
description: SECBB1
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SECBB2R1:
|
||||
description: FLASH secure block based bank 2 register
|
||||
fields:
|
||||
- name: SECBB2
|
||||
description: SECBB2
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SECBB2R2:
|
||||
description: FLASH secure block based bank 2 register
|
||||
fields:
|
||||
- name: SECBB2
|
||||
description: SECBB2
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SECBB2R3:
|
||||
description: FLASH secure block based bank 2 register
|
||||
fields:
|
||||
- name: SECBB2
|
||||
description: SECBB2
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SECBB2R4:
|
||||
description: FLASH secure block based bank 2 register
|
||||
fields:
|
||||
- name: SECBB2
|
||||
description: SECBB2
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SECBOOTADD0R:
|
||||
description: FFlash secure boot address 0 register
|
||||
fields:
|
||||
- name: BOOT_LOCK
|
||||
description: BOOT_LOCK
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SECBOOTADD0
|
||||
description: SECBOOTADD0
|
||||
bit_offset: 7
|
||||
bit_size: 25
|
||||
fieldset/SECCR:
|
||||
description: Flash secure control register
|
||||
fields:
|
||||
- name: SECPG
|
||||
description: SECPG
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SECPER
|
||||
description: SECPER
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: SECMER1
|
||||
description: SECMER1
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: SECPNB
|
||||
description: SECPNB
|
||||
bit_offset: 3
|
||||
bit_size: 7
|
||||
- name: SECBKER
|
||||
description: SECBKER
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: SECMER2
|
||||
description: SECMER2
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: SECSTRT
|
||||
description: SECSTRT
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: SECEOPIE
|
||||
description: SECEOPIE
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: SECERRIE
|
||||
description: SECERRIE
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: SECRDERRIE
|
||||
description: SECRDERRIE
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: SECINV
|
||||
description: SECINV
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: SECLOCK
|
||||
description: SECLOCK
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SECHDPCR:
|
||||
description: FLASH secure HDP control register
|
||||
fields:
|
||||
- name: HDP1_ACCDIS
|
||||
description: HDP1_ACCDIS
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: HDP2_ACCDIS
|
||||
description: HDP2_ACCDIS
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
fieldset/SECKEYR:
|
||||
description: Flash secure key register
|
||||
fields:
|
||||
- name: SECKEYR
|
||||
description: SECKEYR
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SECSR:
|
||||
description: Flash status register
|
||||
fields:
|
||||
- name: SECEOP
|
||||
description: SECEOP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SECOPERR
|
||||
description: SECOPERR
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: SECPROGERR
|
||||
description: SECPROGERR
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: SECWRPERR
|
||||
description: SECWRPERR
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: SECPGAERR
|
||||
description: SECPGAERR
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SECSIZERR
|
||||
description: SECSIZERR
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: SECPGSERR
|
||||
description: SECPGSERR
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: SECRDERR
|
||||
description: Secure read protection error
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: SECBSY
|
||||
description: SECBusy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
fieldset/SECWM1R1:
|
||||
description: Flash bank 1 secure watermak1 register
|
||||
fields:
|
||||
- name: SECWM1_PSTRT
|
||||
description: SECWM1_PSTRT
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: SECWM1_PEND
|
||||
description: SECWM1_PEND
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
fieldset/SECWM1R2:
|
||||
description: Flash secure watermak1 register 2
|
||||
fields:
|
||||
- name: PCROP1_PSTRT
|
||||
description: PCROP1_PSTRT
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: PCROP1EN
|
||||
description: PCROP1EN
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: HDP1_PEND
|
||||
description: HDP1_PEND
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
- name: HDP1EN
|
||||
description: HDP1EN
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SECWM2R1:
|
||||
description: Flash secure watermak2 register
|
||||
fields:
|
||||
- name: SECWM2_PSTRT
|
||||
description: SECWM2_PSTRT
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: SECWM2_PEND
|
||||
description: SECWM2_PEND
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
fieldset/SECWM2R2:
|
||||
description: Flash secure watermak2 register2
|
||||
fields:
|
||||
- name: PCROP2_PSTRT
|
||||
description: PCROP2_PSTRT
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: PCROP2EN
|
||||
description: PCROP2EN
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: HDP2_PEND
|
||||
description: HDP2_PEND
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
- name: HDP2EN
|
||||
description: HDP2EN
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/WRP1AR:
|
||||
description: Flash Bank 1 WRP area A address register
|
||||
fields:
|
||||
- name: WRP1A_PSTRT
|
||||
description: WRP1A_PSTRT
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: WRP1A_PEND
|
||||
description: WRP1A_PEND
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
fieldset/WRP1BR:
|
||||
description: Flash Bank 1 WRP area B address register
|
||||
fields:
|
||||
- name: WRP1B_PSTRT
|
||||
description: WRP1B_PSTRT
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: WRP1B_PEND
|
||||
description: WRP1B_PEND
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
fieldset/WRP2AR:
|
||||
description: Flash WPR2 area A address register
|
||||
fields:
|
||||
- name: WRP2A_PSTRT
|
||||
description: WRP2A_PSTRT
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: WRP2A_PEND
|
||||
description: WRP2A_PEND
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
fieldset/WRP2BR:
|
||||
description: Flash WPR2 area B address register
|
||||
fields:
|
||||
- name: WRP2B_PSTRT
|
||||
description: WRP2B_PSTRT
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: WRP2B_PEND
|
||||
description: WRP2B_PEND
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
@ -3,115 +3,115 @@ block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
- name: ACR
|
||||
description: "FLASH access control register "
|
||||
description: FLASH access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: NSKEYR
|
||||
description: "FLASH non-secure key register "
|
||||
description: FLASH non-secure key register
|
||||
byte_offset: 8
|
||||
fieldset: NSKEYR
|
||||
- name: SECKEYR
|
||||
description: "FLASH secure key register "
|
||||
description: FLASH secure key register
|
||||
byte_offset: 12
|
||||
fieldset: SECKEYR
|
||||
- name: OPTKEYR
|
||||
description: "FLASH option key register "
|
||||
description: FLASH option key register
|
||||
byte_offset: 16
|
||||
fieldset: OPTKEYR
|
||||
- name: PDKEY1R
|
||||
description: "FLASH bank 1 power-down key register "
|
||||
description: FLASH bank 1 power-down key register
|
||||
byte_offset: 24
|
||||
fieldset: PDKEY1R
|
||||
- name: PDKEY2R
|
||||
description: "FLASH bank 2 power-down key register "
|
||||
description: FLASH bank 2 power-down key register
|
||||
byte_offset: 28
|
||||
fieldset: PDKEY2R
|
||||
- name: NSSR
|
||||
description: "FLASH non-secure status register "
|
||||
description: FLASH non-secure status register
|
||||
byte_offset: 32
|
||||
fieldset: NSSR
|
||||
- name: SECSR
|
||||
description: "FLASH secure status register "
|
||||
description: FLASH secure status register
|
||||
byte_offset: 36
|
||||
fieldset: SECSR
|
||||
- name: NSCR
|
||||
description: "FLASH non-secure control register "
|
||||
description: FLASH non-secure control register
|
||||
byte_offset: 40
|
||||
fieldset: NSCR
|
||||
- name: SECCR
|
||||
description: "FLASH secure control register "
|
||||
description: FLASH secure control register
|
||||
byte_offset: 44
|
||||
fieldset: SECCR
|
||||
- name: ECCR
|
||||
description: "FLASH ECC register "
|
||||
description: FLASH ECC register
|
||||
byte_offset: 48
|
||||
fieldset: ECCR
|
||||
- name: OPSR
|
||||
description: "FLASH operation status register "
|
||||
description: FLASH operation status register
|
||||
byte_offset: 52
|
||||
fieldset: OPSR
|
||||
- name: OPTR
|
||||
description: "FLASH option register "
|
||||
description: FLASH option register
|
||||
byte_offset: 64
|
||||
fieldset: OPTR
|
||||
- name: NSBOOTADD0R
|
||||
description: "FLASH non-secure boot address 0 register\t"
|
||||
description: FLASH non-secure boot address 0 register
|
||||
byte_offset: 68
|
||||
fieldset: NSBOOTADD0R
|
||||
- name: NSBOOTADD1R
|
||||
description: "FLASH non-secure boot address 1 register\t"
|
||||
description: FLASH non-secure boot address 1 register
|
||||
byte_offset: 72
|
||||
fieldset: NSBOOTADD1R
|
||||
- name: SECBOOTADD0R
|
||||
description: "FLASH secure boot address 0 register "
|
||||
description: FLASH secure boot address 0 register
|
||||
byte_offset: 76
|
||||
fieldset: SECBOOTADD0R
|
||||
- name: SECWM1R1
|
||||
description: "FLASH secure watermark1 register 1 "
|
||||
description: FLASH secure watermark1 register 1
|
||||
byte_offset: 80
|
||||
fieldset: SECWM1R1
|
||||
- name: SECWM1R2
|
||||
description: "FLASH secure watermark1 register 2 "
|
||||
description: FLASH secure watermark1 register 2
|
||||
byte_offset: 84
|
||||
fieldset: SECWM1R2
|
||||
- name: WRP1AR
|
||||
description: "FLASH WRP1 area A address register "
|
||||
description: FLASH WRP1 area A address register
|
||||
byte_offset: 88
|
||||
fieldset: WRP1AR
|
||||
- name: WRP1BR
|
||||
description: "FLASH WRP1 area B address register "
|
||||
description: FLASH WRP1 area B address register
|
||||
byte_offset: 92
|
||||
fieldset: WRP1BR
|
||||
- name: SECWM2R1
|
||||
description: "FLASH secure watermark2 register 1 "
|
||||
description: FLASH secure watermark2 register 1
|
||||
byte_offset: 96
|
||||
fieldset: SECWM2R1
|
||||
- name: SECWM2R2
|
||||
description: "FLASH secure watermark2 register 2 "
|
||||
description: FLASH secure watermark2 register 2
|
||||
byte_offset: 100
|
||||
fieldset: SECWM2R2
|
||||
- name: WRP2AR
|
||||
description: "FLASH WPR2 area A address register "
|
||||
description: FLASH WPR2 area A address register
|
||||
byte_offset: 104
|
||||
fieldset: WRP2AR
|
||||
- name: WRP2BR
|
||||
description: "FLASH WPR2 area B address register "
|
||||
description: FLASH WPR2 area B address register
|
||||
byte_offset: 108
|
||||
fieldset: WRP2BR
|
||||
- name: OEM1KEYR1
|
||||
description: "FLASH OEM1 key register 1 "
|
||||
description: FLASH OEM1 key register 1
|
||||
byte_offset: 112
|
||||
fieldset: OEM1KEYR1
|
||||
- name: OEM1KEYR2
|
||||
description: "FLASH OEM1 key register 2 "
|
||||
description: FLASH OEM1 key register 2
|
||||
byte_offset: 116
|
||||
fieldset: OEM1KEYR2
|
||||
- name: OEM2KEYR1
|
||||
description: "FLASH OEM2 key register 1 "
|
||||
description: FLASH OEM2 key register 1
|
||||
byte_offset: 120
|
||||
fieldset: OEM2KEYR1
|
||||
- name: OEM2KEYR2
|
||||
description: "FLASH OEM2 key register 2 "
|
||||
description: FLASH OEM2 key register 2
|
||||
byte_offset: 124
|
||||
fieldset: OEM2KEYR2
|
||||
- name: SEC1BBR1
|
||||
@ -147,11 +147,11 @@ block/FLASH:
|
||||
byte_offset: 172
|
||||
fieldset: SEC2BBR4
|
||||
- name: SECHDPCR
|
||||
description: "FLASH secure HDP control register "
|
||||
description: FLASH secure HDP control register
|
||||
byte_offset: 192
|
||||
fieldset: SECHDPCR
|
||||
- name: PRIVCFGR
|
||||
description: "FLASH privilege configuration register "
|
||||
description: FLASH privilege configuration register
|
||||
byte_offset: 196
|
||||
fieldset: PRIVCFGR
|
||||
- name: PRIV1BBR1
|
||||
@ -187,7 +187,7 @@ block/FLASH:
|
||||
byte_offset: 252
|
||||
fieldset: PRIV2BBR4
|
||||
fieldset/ACR:
|
||||
description: "FLASH access control register "
|
||||
description: FLASH access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: "Latency\r These bits represent the ratio between the HCLK (AHB clock) period and the Flash memory access time.\r ..."
|
||||
@ -218,7 +218,7 @@ fieldset/ACR:
|
||||
bit_size: 1
|
||||
enum: SLEEP_PD
|
||||
fieldset/ECCR:
|
||||
description: "FLASH ECC register "
|
||||
description: FLASH ECC register
|
||||
fields:
|
||||
- name: ADDR_ECC
|
||||
description: ECC fail address
|
||||
@ -247,21 +247,21 @@ fieldset/ECCR:
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/NSBOOTADD0R:
|
||||
description: "FLASH non-secure boot address 0 register\t"
|
||||
description: FLASH non-secure boot address 0 register
|
||||
fields:
|
||||
- name: NSBOOTADD0
|
||||
description: "Non-secure boot base address 0\r The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state.\r Examples:\r NSBOOTADD0[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000)\r NSBOOTADD0[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000)\r NSBOOTADD0[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000)"
|
||||
bit_offset: 7
|
||||
bit_size: 25
|
||||
fieldset/NSBOOTADD1R:
|
||||
description: "FLASH non-secure boot address 1 register\t"
|
||||
description: FLASH non-secure boot address 1 register
|
||||
fields:
|
||||
- name: NSBOOTADD1
|
||||
description: "Non-secure boot address 1\r The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state.\r Examples:\r NSBOOTADD1[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000)\r NSBOOTADD1[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000)\r NSBOOTADD1[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000)"
|
||||
bit_offset: 7
|
||||
bit_size: 25
|
||||
fieldset/NSCR:
|
||||
description: "FLASH non-secure control register "
|
||||
description: FLASH non-secure control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Non-secure programming
|
||||
@ -326,14 +326,14 @@ fieldset/NSCR:
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/NSKEYR:
|
||||
description: "FLASH non-secure key register "
|
||||
description: FLASH non-secure key register
|
||||
fields:
|
||||
- name: NSKEY
|
||||
description: Flash memory non-secure key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/NSSR:
|
||||
description: "FLASH non-secure status register "
|
||||
description: FLASH non-secure status register
|
||||
fields:
|
||||
- name: EOP
|
||||
description: Non-secure end of operation
|
||||
@ -392,35 +392,35 @@ fieldset/NSSR:
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
fieldset/OEM1KEYR1:
|
||||
description: "FLASH OEM1 key register 1 "
|
||||
description: FLASH OEM1 key register 1
|
||||
fields:
|
||||
- name: OEM1KEY
|
||||
description: OEM1 least significant bytes key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OEM1KEYR2:
|
||||
description: "FLASH OEM1 key register 2 "
|
||||
description: FLASH OEM1 key register 2
|
||||
fields:
|
||||
- name: OEM1KEY
|
||||
description: OEM1 most significant bytes key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OEM2KEYR1:
|
||||
description: "FLASH OEM2 key register 1 "
|
||||
description: FLASH OEM2 key register 1
|
||||
fields:
|
||||
- name: OEM2KEY
|
||||
description: OEM2 least significant bytes key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OEM2KEYR2:
|
||||
description: "FLASH OEM2 key register 2 "
|
||||
description: FLASH OEM2 key register 2
|
||||
fields:
|
||||
- name: OEM2KEY
|
||||
description: OEM2 most significant bytes key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPSR:
|
||||
description: "FLASH operation status register "
|
||||
description: FLASH operation status register
|
||||
fields:
|
||||
- name: ADDR_OP
|
||||
description: "Interrupted operation address\r This field indicates which address in the Flash memory was accessed when reset occurred. The address is given by bank from address 0x0 0000 to 0xF FFF0."
|
||||
@ -441,14 +441,14 @@ fieldset/OPSR:
|
||||
bit_size: 3
|
||||
enum: CODE_OP
|
||||
fieldset/OPTKEYR:
|
||||
description: "FLASH option key register "
|
||||
description: FLASH option key register
|
||||
fields:
|
||||
- name: OPTKEY
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTR:
|
||||
description: "FLASH option register "
|
||||
description: FLASH option register
|
||||
fields:
|
||||
- name: RDP
|
||||
description: "Readout protection level\r Others: Level 1 (memories readout protection active)\r Note: Refer to for more details."
|
||||
@ -557,14 +557,14 @@ fieldset/OPTR:
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/PDKEY1R:
|
||||
description: "FLASH bank 1 power-down key register "
|
||||
description: FLASH bank 1 power-down key register
|
||||
fields:
|
||||
- name: PDKEY1
|
||||
description: Bank 1 power-down key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PDKEY2R:
|
||||
description: "FLASH bank 2 power-down key register "
|
||||
description: FLASH bank 2 power-down key register
|
||||
fields:
|
||||
- name: PDKEY2
|
||||
description: Bank 2 power-down key
|
||||
@ -1619,7 +1619,7 @@ fieldset/PRIV2BBR4:
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/PRIVCFGR:
|
||||
description: "FLASH privilege configuration register "
|
||||
description: FLASH privilege configuration register
|
||||
fields:
|
||||
- name: SPRIV
|
||||
description: "Privileged protection for secure registers\r This bit can be accessed only when TrustZone is enabled (TZEN = 1). This bit can be read by both privileged or unprivileged, secure and non-secure access.\r The SPRIV bit can be written only by a secure privileged access. A non-secure write access on SPRIV bit is ignored. A secure unprivileged write access on SPRIV bit is ignored."
|
||||
@ -2680,7 +2680,7 @@ fieldset/SEC2BBR4:
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SECBOOTADD0R:
|
||||
description: "FLASH secure boot address 0 register "
|
||||
description: FLASH secure boot address 0 register
|
||||
fields:
|
||||
- name: BOOT_LOCK
|
||||
description: "Boot lock\r When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP at level 0."
|
||||
@ -2691,7 +2691,7 @@ fieldset/SECBOOTADD0R:
|
||||
bit_offset: 7
|
||||
bit_size: 25
|
||||
fieldset/SECCR:
|
||||
description: "FLASH secure control register "
|
||||
description: FLASH secure control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Secure programming
|
||||
@ -2751,7 +2751,7 @@ fieldset/SECCR:
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SECHDPCR:
|
||||
description: "FLASH secure HDP control register "
|
||||
description: FLASH secure HDP control register
|
||||
fields:
|
||||
- name: HDP1_ACCDIS
|
||||
description: "HDP1 area access disable\r When set, this bit is only cleared by a system reset."
|
||||
@ -2764,14 +2764,14 @@ fieldset/SECHDPCR:
|
||||
bit_size: 1
|
||||
enum: HDP_ACCDIS
|
||||
fieldset/SECKEYR:
|
||||
description: "FLASH secure key register "
|
||||
description: FLASH secure key register
|
||||
fields:
|
||||
- name: SECKEY
|
||||
description: Flash memory secure key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SECSR:
|
||||
description: "FLASH secure status register "
|
||||
description: FLASH secure status register
|
||||
fields:
|
||||
- name: EOP
|
||||
description: "Secure end of operation\r This bit is set by hardware when one or more Flash memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_SECCR). This bit is cleared by writing 1."
|
||||
@ -2810,7 +2810,7 @@ fieldset/SECSR:
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
fieldset/SECWM1R1:
|
||||
description: "FLASH secure watermark1 register 1 "
|
||||
description: FLASH secure watermark1 register 1
|
||||
fields:
|
||||
- name: SECWM1_PSTRT
|
||||
description: "Start page of first secure area\r This field contains the first page of the secure area in bank 1."
|
||||
@ -2821,7 +2821,7 @@ fieldset/SECWM1R1:
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
fieldset/SECWM1R2:
|
||||
description: "FLASH secure watermark1 register 2 "
|
||||
description: FLASH secure watermark1 register 2
|
||||
fields:
|
||||
- name: HDP1_PEND
|
||||
description: "End page of first hide protection area\r This field contains the last page of the HDP area in bank 1."
|
||||
@ -2832,7 +2832,7 @@ fieldset/SECWM1R2:
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SECWM2R1:
|
||||
description: "FLASH secure watermark2 register 1 "
|
||||
description: FLASH secure watermark2 register 1
|
||||
fields:
|
||||
- name: SECWM2_PSTRT
|
||||
description: "Start page of second secure area\r This field contains the first page of the secure area in bank 2."
|
||||
@ -2843,7 +2843,7 @@ fieldset/SECWM2R1:
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
fieldset/SECWM2R2:
|
||||
description: "FLASH secure watermark2 register 2 "
|
||||
description: FLASH secure watermark2 register 2
|
||||
fields:
|
||||
- name: HDP2_PEND
|
||||
description: "End page of hide protection second area\r HDP2_PEND contains the last page of the HDP area in bank 2."
|
||||
@ -2854,7 +2854,7 @@ fieldset/SECWM2R2:
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/WRP1AR:
|
||||
description: "FLASH WRP1 area A address register "
|
||||
description: FLASH WRP1 area A address register
|
||||
fields:
|
||||
- name: WRP1A_PSTRT
|
||||
description: "bank 1 WPR first area A start page\r This field contains the first page of the first WPR area for bank 1."
|
||||
@ -2870,7 +2870,7 @@ fieldset/WRP1AR:
|
||||
bit_size: 1
|
||||
enum: WRPAR_UNLOCK
|
||||
fieldset/WRP1BR:
|
||||
description: "FLASH WRP1 area B address register "
|
||||
description: FLASH WRP1 area B address register
|
||||
fields:
|
||||
- name: WRP1B_PSTRT
|
||||
description: "Bank 1 WRP second area B start page\r This field contains the first page of the second WRP area for bank 1."
|
||||
@ -2886,7 +2886,7 @@ fieldset/WRP1BR:
|
||||
bit_size: 1
|
||||
enum: WRPBR_UNLOCK
|
||||
fieldset/WRP2AR:
|
||||
description: "FLASH WPR2 area A address register "
|
||||
description: FLASH WPR2 area A address register
|
||||
fields:
|
||||
- name: WRP2A_PSTRT
|
||||
description: "Bank 2 WPR first area A start page\r This field contains the first page of the first WRP area for bank 2."
|
||||
@ -2902,7 +2902,7 @@ fieldset/WRP2AR:
|
||||
bit_size: 1
|
||||
enum: WRPAR_UNLOCK
|
||||
fieldset/WRP2BR:
|
||||
description: "FLASH WPR2 area B address register "
|
||||
description: FLASH WPR2 area B address register
|
||||
fields:
|
||||
- name: WRP2B_PSTRT
|
||||
description: "Bank 2 WPR second area B start page\r This field contains the first page of the second WRP area for bank 2."
|
||||
@ -2948,19 +2948,19 @@ enum/BOR_LEV:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "BOR level 0 (reset level threshold around 1.7 V) "
|
||||
description: BOR level 0 (reset level threshold around 1.7 V)
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "BOR level 1 (reset level threshold around 2.0 V) "
|
||||
description: BOR level 1 (reset level threshold around 2.0 V)
|
||||
value: 1
|
||||
- name: B_0x2
|
||||
description: "BOR level 2 (reset level threshold around 2.2 V) "
|
||||
description: BOR level 2 (reset level threshold around 2.2 V)
|
||||
value: 2
|
||||
- name: B_0x3
|
||||
description: "BOR level 3 (reset level threshold around 2.5 V) "
|
||||
description: BOR level 3 (reset level threshold around 2.5 V)
|
||||
value: 3
|
||||
- name: B_0x4
|
||||
description: "BOR level 4 (reset level threshold around 2.8 V) "
|
||||
description: BOR level 4 (reset level threshold around 2.8 V)
|
||||
value: 4
|
||||
enum/CODE_OP:
|
||||
bit_size: 3
|
||||
@ -3017,19 +3017,19 @@ enum/IO_VDDIO_HSLV:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) "
|
||||
description: High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) "
|
||||
description: High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)
|
||||
value: 1
|
||||
enum/IO_VDD_HSLV:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) "
|
||||
description: High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) "
|
||||
description: High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)
|
||||
value: 1
|
||||
enum/IWDG_STDBY:
|
||||
bit_size: 1
|
||||
|
||||
559
data/registers/flash_wl.yaml
Normal file
559
data/registers/flash_wl.yaml
Normal file
@ -0,0 +1,559 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
- name: ACR
|
||||
description: Access control register
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: KEYR
|
||||
description: Flash key register
|
||||
byte_offset: 8
|
||||
access: Write
|
||||
fieldset: KEYR
|
||||
- name: OPTKEYR
|
||||
description: Option byte key register
|
||||
byte_offset: 12
|
||||
access: Write
|
||||
fieldset: OPTKEYR
|
||||
- name: SR
|
||||
description: Status register
|
||||
byte_offset: 16
|
||||
fieldset: SR
|
||||
- name: CR
|
||||
description: Flash control register
|
||||
byte_offset: 20
|
||||
fieldset: CR
|
||||
- name: ECCR
|
||||
description: Flash ECC register
|
||||
byte_offset: 24
|
||||
fieldset: ECCR
|
||||
- name: OPTR
|
||||
description: Flash option register
|
||||
byte_offset: 32
|
||||
fieldset: OPTR
|
||||
- name: PCROP1ASR
|
||||
description: Flash Bank 1 PCROP Start address zone A register
|
||||
byte_offset: 36
|
||||
fieldset: PCROP1ASR
|
||||
- name: PCROP1AER
|
||||
description: Flash Bank 1 PCROP End address zone A register
|
||||
byte_offset: 40
|
||||
fieldset: PCROP1AER
|
||||
- name: WRP1AR
|
||||
description: Flash Bank 1 WRP area A address register
|
||||
byte_offset: 44
|
||||
fieldset: WRP1AR
|
||||
- name: WRP1BR
|
||||
description: Flash Bank 1 WRP area B address register
|
||||
byte_offset: 48
|
||||
fieldset: WRP1BR
|
||||
- name: PCROP1BSR
|
||||
description: Flash Bank 1 PCROP Start address area B register
|
||||
byte_offset: 52
|
||||
fieldset: PCROP1BSR
|
||||
- name: PCROP1BER
|
||||
description: Flash Bank 1 PCROP End address area B register
|
||||
byte_offset: 56
|
||||
fieldset: PCROP1BER
|
||||
- name: IPCCBR
|
||||
description: IPCC mailbox data buffer address register
|
||||
byte_offset: 60
|
||||
fieldset: IPCCBR
|
||||
- name: C2ACR
|
||||
description: CPU2 cortex M0 access control register
|
||||
byte_offset: 92
|
||||
fieldset: C2ACR
|
||||
- name: C2SR
|
||||
description: CPU2 cortex M0 status register
|
||||
byte_offset: 96
|
||||
fieldset: C2SR
|
||||
- name: C2CR
|
||||
description: CPU2 cortex M0 control register
|
||||
byte_offset: 100
|
||||
fieldset: C2CR
|
||||
- name: SFR
|
||||
description: Secure flash start address register
|
||||
byte_offset: 128
|
||||
fieldset: SFR
|
||||
- name: SRRVR
|
||||
description: Secure SRAM2 start address and cortex M0 reset vector register
|
||||
byte_offset: 132
|
||||
fieldset: SRRVR
|
||||
fieldset/ACR:
|
||||
description: Access control register
|
||||
fields:
|
||||
- name: LATENCY
|
||||
description: Latency
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
- name: PRFTEN
|
||||
description: Prefetch enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ICEN
|
||||
description: Instruction cache enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: DCEN
|
||||
description: Data cache enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ICRST
|
||||
description: Instruction cache reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DCRST
|
||||
description: Data cache reset
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: PES
|
||||
description: CPU1 CortexM4 program erase suspend request
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: EMPTY
|
||||
description: Flash User area empty
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
fieldset/C2ACR:
|
||||
description: CPU2 cortex M0 access control register
|
||||
fields:
|
||||
- name: PRFTEN
|
||||
description: CPU2 cortex M0 prefetch enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ICEN
|
||||
description: CPU2 cortex M0 instruction cache enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ICRST
|
||||
description: CPU2 cortex M0 instruction cache reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: PES
|
||||
description: CPU2 cortex M0 program erase suspend request
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
fieldset/C2CR:
|
||||
description: CPU2 cortex M0 control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: Masse erase
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PNB
|
||||
description: Page Number selection
|
||||
bit_offset: 3
|
||||
bit_size: 8
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: FSTPG
|
||||
description: Fast programming
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: RDERRIE
|
||||
description: PCROP read error interrupt enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
fieldset/C2SR:
|
||||
description: CPU2 cortex M0 status register
|
||||
fields:
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Operation error
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PROGERR
|
||||
description: Programming error
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: write protection error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: Size error
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: Programming sequence error
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: MISSERR
|
||||
description: Fast programming data miss error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: FASTERR
|
||||
description: Fast programming error
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: PCROP read error
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: CFGBSY
|
||||
description: Programming or erase configuration busy
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: PESD
|
||||
description: Programming or erase operation suspended
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Flash control register
|
||||
fields:
|
||||
- name: PG
|
||||
description: Programming
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PER
|
||||
description: Page erase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MER
|
||||
description: This bit triggers the mass erase (all user pages) when set
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: PNB
|
||||
description: Page number selection
|
||||
bit_offset: 3
|
||||
bit_size: 8
|
||||
- name: STRT
|
||||
description: Start
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: OPTSTRT
|
||||
description: Options modification start
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: FSTPG
|
||||
description: Fast programming
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: EOPIE
|
||||
description: End of operation interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ERRIE
|
||||
description: Error interrupt enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: RDERRIE
|
||||
description: PCROP read error interrupt enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: OBL_LAUNCH
|
||||
description: Force the option byte loading
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: OPTLOCK
|
||||
description: Options Lock
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LOCK
|
||||
description: FLASH_CR Lock
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/ECCR:
|
||||
description: Flash ECC register
|
||||
fields:
|
||||
- name: ADDR_ECC
|
||||
description: ECC fail address
|
||||
bit_offset: 0
|
||||
bit_size: 17
|
||||
- name: SYSF_ECC
|
||||
description: System Flash ECC fail
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: ECCCIE
|
||||
description: ECC correction interrupt enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: CPUID
|
||||
description: CPU identification
|
||||
bit_offset: 26
|
||||
bit_size: 3
|
||||
- name: ECCC
|
||||
description: ECC correction
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: ECCD
|
||||
description: ECC detection
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/IPCCBR:
|
||||
description: IPCC mailbox data buffer address register
|
||||
fields:
|
||||
- name: IPCCDBA
|
||||
description: PCC mailbox data buffer base address
|
||||
bit_offset: 0
|
||||
bit_size: 14
|
||||
fieldset/KEYR:
|
||||
description: Flash key register
|
||||
fields:
|
||||
- name: KEYR
|
||||
description: KEYR
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTKEYR:
|
||||
description: Option byte key register
|
||||
fields:
|
||||
- name: OPTKEYR
|
||||
description: Option byte key
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OPTR:
|
||||
description: Flash option register
|
||||
fields:
|
||||
- name: RDP
|
||||
description: Read protection level
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: ESE
|
||||
description: Security enabled
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: BOR_LEV
|
||||
description: BOR reset Level
|
||||
bit_offset: 9
|
||||
bit_size: 3
|
||||
- name: nRST_STOP
|
||||
description: nRST_STOP
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: nRST_STDBY
|
||||
description: nRST_STDBY
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: nRST_SHDW
|
||||
description: nRST_SHDW
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: IDWG_SW
|
||||
description: Independent watchdog selection
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: IWDG_STOP
|
||||
description: Independent watchdog counter freeze in Stop mode
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: IWDG_STDBY
|
||||
description: Independent watchdog counter freeze in Standby mode
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: WWDG_SW
|
||||
description: Window watchdog selection
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: nBOOT1
|
||||
description: Boot configuration
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: SRAM2_PE
|
||||
description: SRAM2 parity check enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: SRAM2_RST
|
||||
description: SRAM2 Erase when system reset
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: nSWBOOT0
|
||||
description: Software Boot0
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: nBOOT0
|
||||
description: nBoot0 option bit
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: AGC_TRIM
|
||||
description: Radio Automatic Gain Control Trimming
|
||||
bit_offset: 29
|
||||
bit_size: 3
|
||||
fieldset/PCROP1AER:
|
||||
description: Flash Bank 1 PCROP End address zone A register
|
||||
fields:
|
||||
- name: PCROP1A_END
|
||||
description: Bank 1 PCROP area end offset
|
||||
bit_offset: 0
|
||||
bit_size: 9
|
||||
- name: PCROP_RDP
|
||||
description: PCROP area preserved when RDP level decreased
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/PCROP1ASR:
|
||||
description: Flash Bank 1 PCROP Start address zone A register
|
||||
fields:
|
||||
- name: PCROP1A_STRT
|
||||
description: Bank 1 PCROPQ area start offset
|
||||
bit_offset: 0
|
||||
bit_size: 9
|
||||
fieldset/PCROP1BER:
|
||||
description: Flash Bank 1 PCROP End address area B register
|
||||
fields:
|
||||
- name: PCROP1B_END
|
||||
description: Bank 1 PCROP area end area B offset
|
||||
bit_offset: 0
|
||||
bit_size: 9
|
||||
fieldset/PCROP1BSR:
|
||||
description: Flash Bank 1 PCROP Start address area B register
|
||||
fields:
|
||||
- name: PCROP1B_STRT
|
||||
description: Bank 1 PCROP area B start offset
|
||||
bit_offset: 0
|
||||
bit_size: 9
|
||||
fieldset/SFR:
|
||||
description: Secure flash start address register
|
||||
fields:
|
||||
- name: SFSA
|
||||
description: Secure flash start address
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: FSD
|
||||
description: Flash security disable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: DDS
|
||||
description: Disable Cortex M0 debug access
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
fieldset/SR:
|
||||
description: Status register
|
||||
fields:
|
||||
- name: EOP
|
||||
description: End of operation
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OPERR
|
||||
description: Operation error
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PROGERR
|
||||
description: Programming error
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WRPERR
|
||||
description: Write protected error
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PGAERR
|
||||
description: Programming alignment error
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SIZERR
|
||||
description: Size error
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: PGSERR
|
||||
description: Programming sequence error
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: MISERR
|
||||
description: Fast programming data miss error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: FASTERR
|
||||
description: Fast programming error
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: OPTNV
|
||||
description: User Option OPTVAL indication
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: RDERR
|
||||
description: PCROP read error
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: OPTVERR
|
||||
description: Option validity error
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: BSY
|
||||
description: Busy
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: CFGBSY
|
||||
description: Programming or erase configuration busy
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: PESD
|
||||
description: Programming or erase operation suspended
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
fieldset/SRRVR:
|
||||
description: Secure SRAM2 start address and cortex M0 reset vector register
|
||||
fields:
|
||||
- name: SBRV
|
||||
description: cortex M0 access control register
|
||||
bit_offset: 0
|
||||
bit_size: 18
|
||||
- name: SBRSA
|
||||
description: Secure backup SRAM2a start address
|
||||
bit_offset: 18
|
||||
bit_size: 5
|
||||
- name: BRSD
|
||||
description: backup SRAM2a security disable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: SNBRSA
|
||||
description: Secure non backup SRAM2a start address
|
||||
bit_offset: 25
|
||||
bit_size: 5
|
||||
- name: NBRSD
|
||||
description: non-backup SRAM2b security disable
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: C2OPT
|
||||
description: CPU2 cortex M0 boot reset vector memory selection
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/WRP1AR:
|
||||
description: Flash Bank 1 WRP area A address register
|
||||
fields:
|
||||
- name: WRP1A_STRT
|
||||
description: Bank 1 WRP first area A start offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: WRP1A_END
|
||||
description: Bank 1 WRP first area A end offset
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
fieldset/WRP1BR:
|
||||
description: Flash Bank 1 WRP area B address register
|
||||
fields:
|
||||
- name: WRP1B_END
|
||||
description: Bank 1 WRP second area B start offset
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: WRP1B_STRT
|
||||
description: Bank 1 WRP second area B end offset
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
@ -38,26 +38,10 @@ block/FSMC:
|
||||
description: PC Card/NAND Flash control register 2
|
||||
byte_offset: 96
|
||||
fieldset: PCR
|
||||
- name: PCR3
|
||||
description: PC Card/NAND Flash control register 3
|
||||
byte_offset: 128
|
||||
fieldset: PCR
|
||||
- name: PCR4
|
||||
description: PC Card/NAND Flash control register 4
|
||||
byte_offset: 160
|
||||
fieldset: PCR
|
||||
- name: SR2
|
||||
description: FIFO status and interrupt register 2
|
||||
byte_offset: 100
|
||||
fieldset: SR
|
||||
- name: SR3
|
||||
description: FIFO status and interrupt register 3
|
||||
byte_offset: 132
|
||||
fieldset: SR
|
||||
- name: SR4
|
||||
description: FIFO status and interrupt register 4
|
||||
byte_offset: 164
|
||||
fieldset: SR
|
||||
- name: PMEM2
|
||||
description: Common memory space timing register 2
|
||||
byte_offset: 104
|
||||
@ -71,6 +55,14 @@ block/FSMC:
|
||||
byte_offset: 116
|
||||
access: Read
|
||||
fieldset: ECCR
|
||||
- name: PCR3
|
||||
description: PC Card/NAND Flash control register 3
|
||||
byte_offset: 128
|
||||
fieldset: PCR
|
||||
- name: SR3
|
||||
description: FIFO status and interrupt register 3
|
||||
byte_offset: 132
|
||||
fieldset: SR
|
||||
- name: PMEM3
|
||||
description: Common memory space timing register 3
|
||||
byte_offset: 136
|
||||
@ -84,6 +76,14 @@ block/FSMC:
|
||||
byte_offset: 148
|
||||
access: Read
|
||||
fieldset: ECCR
|
||||
- name: PCR4
|
||||
description: PC Card/NAND Flash control register 4
|
||||
byte_offset: 160
|
||||
fieldset: PCR
|
||||
- name: SR4
|
||||
description: FIFO status and interrupt register 4
|
||||
byte_offset: 164
|
||||
fieldset: SR
|
||||
- name: PMEM4
|
||||
description: Common memory space timing register 4
|
||||
byte_offset: 168
|
||||
@ -141,7 +141,6 @@ block/FSMC:
|
||||
byte_offset: 344
|
||||
access: Read
|
||||
fieldset: SDSR
|
||||
|
||||
fieldset/BCR:
|
||||
description: SRAM/NOR-Flash chip-select control register
|
||||
fields:
|
||||
|
||||
597
data/registers/gpdma_v1.yaml
Normal file
597
data/registers/gpdma_v1.yaml
Normal file
@ -0,0 +1,597 @@
|
||||
---
|
||||
block/Channel:
|
||||
items:
|
||||
- name: LBAR
|
||||
description: GPDMA channel 15 linked-list base address register
|
||||
byte_offset: 0
|
||||
fieldset: CH_LBAR
|
||||
- name: FCR
|
||||
description: GPDMA channel 15 flag clear register
|
||||
byte_offset: 12
|
||||
fieldset: CH_FCR
|
||||
- name: SR
|
||||
description: GPDMA channel 15 status register
|
||||
byte_offset: 16
|
||||
fieldset: CH_SR
|
||||
- name: CR
|
||||
description: GPDMA channel 15 control register
|
||||
byte_offset: 20
|
||||
fieldset: CH_CR
|
||||
- name: TR1
|
||||
description: GPDMA channel 15 transfer register 1
|
||||
byte_offset: 64
|
||||
fieldset: CH_TR1
|
||||
- name: TR2
|
||||
description: GPDMA channel 15 transfer register 2
|
||||
byte_offset: 68
|
||||
fieldset: CH_TR2
|
||||
- name: BR1
|
||||
description: GPDMA channel 15 alternate block register 1
|
||||
byte_offset: 72
|
||||
fieldset: CH_BR1
|
||||
- name: SAR
|
||||
description: GPDMA channel 15 source address register
|
||||
byte_offset: 76
|
||||
- name: DAR
|
||||
description: GPDMA channel 15 destination address register
|
||||
byte_offset: 80
|
||||
- name: TR3
|
||||
description: GPDMA channel 15 transfer register 3
|
||||
byte_offset: 84
|
||||
fieldset: CH_TR3
|
||||
- name: BR2
|
||||
description: GPDMA channel 15 block register 2
|
||||
byte_offset: 88
|
||||
fieldset: CH_BR2
|
||||
- name: LLR
|
||||
description: GPDMA channel 15 alternate linked-list address register
|
||||
byte_offset: 124
|
||||
fieldset: CH_LLR
|
||||
block/GPDMA:
|
||||
description: GPDMA
|
||||
items:
|
||||
- name: SECCFGR
|
||||
description: GPDMA secure configuration register
|
||||
byte_offset: 0
|
||||
fieldset: SECCFGR
|
||||
- name: PRIVCFGR
|
||||
description: GPDMA privileged configuration register
|
||||
byte_offset: 4
|
||||
fieldset: PRIVCFGR
|
||||
- name: RCFGLOCKR
|
||||
description: GPDMA configuration lock register
|
||||
byte_offset: 8
|
||||
fieldset: RCFGLOCKR
|
||||
- name: MISR
|
||||
description: GPDMA non-secure masked interrupt status register
|
||||
byte_offset: 12
|
||||
fieldset: MISR
|
||||
- name: SMISR
|
||||
description: GPDMA secure masked interrupt status register
|
||||
byte_offset: 16
|
||||
fieldset: MISR
|
||||
- name: CH
|
||||
array:
|
||||
len: 16
|
||||
stride: 128
|
||||
byte_offset: 80
|
||||
block: Channel
|
||||
fieldset/CH_BR1:
|
||||
description: GPDMA channel 15 alternate block register 1
|
||||
fields:
|
||||
- name: BNDT
|
||||
description: "block number of data bytes to transfer from the source. Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if CH[x].LLR.UB1 = 1, this field is updated by the LLI in the memory. - if CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if CH[x].LLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (CH[x].TR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued."
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: BRC
|
||||
description: "Block repeat counter. This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If CH[x].LLR.UB1 = 1, all CH[x].BR1 fields are updated by the next LLI in the memory. If CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if CH[x].LLR = 0, this field is kept as zero following the last LLI and data transfer."
|
||||
bit_offset: 16
|
||||
bit_size: 11
|
||||
- name: SDEC
|
||||
description: source address decrement
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
enum: CH_BR1_DEC
|
||||
- name: DDEC
|
||||
description: destination address decrement
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
enum: CH_BR1_DEC
|
||||
- name: BRSDEC
|
||||
description: "Block repeat source address decrement. Note: On top of this increment/decrement (depending on BRSDEC), CH[x].SAR is in the same time also updated by the increment/decrement (depending on SDEC) of the CH[x].TR3.SAO value, as it is done after any programmed burst transfer."
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
enum: CH_BR1_DEC
|
||||
- name: BRDDEC
|
||||
description: "Block repeat destination address decrement. Note: On top of this increment/decrement (depending on BRDDEC), CH[x].DAR is in the same time also updated by the increment/decrement (depending on DDEC) of the CH[x].TR3.DAO value, as it is usually done at the end of each programmed burst transfer."
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
enum: CH_BR1_DEC
|
||||
fieldset/CH_BR2:
|
||||
description: GPDMA channel 12 block register 2
|
||||
fields:
|
||||
- name: BRSAO
|
||||
description: "Block repeated source address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRSDEC) the current source address (CH[x].SAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued."
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: BRDAO
|
||||
description: "Block repeated destination address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRDDEC) the current destination address (CH[x].DAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued."
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/CH_CR:
|
||||
description: GPDMA channel 11 control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: "enable. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RESET
|
||||
description: "reset. This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (CH[x].SR.SUSPF = 1 and CH[x].SR.IDLEF = CH[x].CR.EN = 1). - channel in disabled state (CH[x].SR.IDLEF = 1 and CH[x].CR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (CH[x].BR1, CH[x].SAR and CH[x].DAR) before enabling again the channel (see the programming sequence in )."
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: SUSP
|
||||
description: "suspend. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going GPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in ."
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TCIE
|
||||
description: transfer complete interrupt enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: HTIE
|
||||
description: half transfer complete interrupt enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: DTEIE
|
||||
description: data transfer error interrupt enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ULEIE
|
||||
description: update link transfer error interrupt enable
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: USEIE
|
||||
description: user setting error interrupt enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: SUSPIE
|
||||
description: completed suspension interrupt enable
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: TOIE
|
||||
description: trigger overrun interrupt enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: LSM
|
||||
description: "Link step mode. First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by CH[x].LLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1."
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
enum: CH_CR_LSM
|
||||
- name: LAP
|
||||
description: "linked-list allocated port. This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1."
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
enum: CH_CR_LAP
|
||||
- name: PRIO
|
||||
description: "priority level of the channel x GPDMA transfer versus others. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1."
|
||||
bit_offset: 22
|
||||
bit_size: 2
|
||||
enum: CH_CR_PRIO
|
||||
fieldset/CH_FCR:
|
||||
description: GPDMA channel 7 flag clear register
|
||||
fields:
|
||||
- name: TCF
|
||||
description: transfer complete flag clear
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: HTF
|
||||
description: half transfer flag clear
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: DTEF
|
||||
description: data transfer error flag clear
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ULEF
|
||||
description: update link transfer error flag clear
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: USEF
|
||||
description: user setting error flag clear
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: SUSPF
|
||||
description: completed suspension flag clear
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: TOF
|
||||
description: trigger overrun flag clear
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
fieldset/CH_LBAR:
|
||||
description: GPDMA channel 14 linked-list base address register
|
||||
fields:
|
||||
- name: LBA
|
||||
description: linked-list base address of GPDMA channel x
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/CH_LLR:
|
||||
description: GPDMA channel 15 alternate linked-list address register
|
||||
fields:
|
||||
- name: LA
|
||||
description: "pointer (16-bit low-significant address) to the next linked-list data structure. If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (CH[x].CTR1, CH[x].TR2, CH[x].BR1, CH[x].SAR, CH[x].DAR and CH[x].LLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored."
|
||||
bit_offset: 2
|
||||
bit_size: 14
|
||||
- name: ULL
|
||||
description: "Update CH[x].LLR register from memory. This bit is used to control the update of CH[x].LLR from the memory during the link transfer."
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: UB2
|
||||
description: "Update CH[x].BR2 from memory. This bit controls the update of CH[x].BR2 from the memory during the link transfer."
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: UT3
|
||||
description: "Update CH[x].TR3 from memory. This bit controls the update of CH[x].TR3 from the memory during the link transfer."
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: UDA
|
||||
description: "Update CH[x].DAR register from memory. This bit is used to control the update of CH[x].DAR from the memory during the link transfer."
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: USA
|
||||
description: "update CH[x].SAR from memory. This bit controls the update of CH[x].SAR from the memory during the link transfer."
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: UB1
|
||||
description: "Update CH[x].BR1 from memory. This bit controls the update of CH[x].BR1 from the memory during the link transfer. If UB1 = 0 and if CH[x].LLR ≠ 0, the linked-list is not completed. CH[x].BR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer."
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: UT2
|
||||
description: "Update CH[x].TR2 from memory. This bit controls the update of CH[x].TR2 from the memory during the link transfer."
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: UT1
|
||||
description: "Update CH[x].TR1 from memory. This bit controls the update of CH[x].TR1 from the memory during the link transfer."
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/CH_SR:
|
||||
description: GPDMA channel 15 status register
|
||||
fields:
|
||||
- name: IDLEF
|
||||
description: "idle flag. This idle flag is de-asserted by hardware when the channel is enabled (CH[x].CR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state)."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TCF
|
||||
description: "transfer complete flag. A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0])."
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: HTF
|
||||
description: "half transfer flag. An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of CH[x].BR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (CH[x].BR1.BRC[10:0]+1)/2)) has been transferred to the destination."
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: DTEF
|
||||
description: data transfer error flag
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ULEF
|
||||
description: update link transfer error flag
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: USEF
|
||||
description: user setting error flag
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: SUSPF
|
||||
description: completed suspension flag
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: TOF
|
||||
description: trigger overrun flag
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: FIFOL
|
||||
description: "monitored FIFO level. Number of available write beats in the FIFO, in units of the programmed destination data width (see CH[x].TR1.DDW[1:0], in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to CH[x].BR1.BDNT[15:0] and CH[x].BR1.BRC[10:0], to know how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be suspended (CH[x].SR.SUSPF = 1)."
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
fieldset/CH_TR1:
|
||||
description: GPDMA channel 8 transfer register 1
|
||||
fields:
|
||||
- name: SDW
|
||||
description: "binary logarithm of the source data width of a burst in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (CH[x].BR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address CH[x].SAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued."
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
enum: CH_TR1_DW
|
||||
- name: SINC
|
||||
description: "source incrementing burst. The source address, pointed by CH[x].SAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer."
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: SBL_1
|
||||
description: "source burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If SBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed."
|
||||
bit_offset: 4
|
||||
bit_size: 6
|
||||
- name: PAM
|
||||
description: "padding/alignment mode. If DDW[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer. - Case 2: If destination data width < source data width. 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination. Note:"
|
||||
bit_offset: 11
|
||||
bit_size: 2
|
||||
enum: CH_TR1_PAM
|
||||
- name: SBX
|
||||
description: "source byte exchange within the unaligned half-word of each source word. If set, the two consecutive bytes within the unaligned half-word of each source word are exchanged. If the source data width is shorter than a word, this bit is ignored."
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: SAP
|
||||
description: "source allocated port. This bit is used to allocate the master port for the source transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1."
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
enum: CH_TR1_AP
|
||||
- name: SSEC
|
||||
description: "security attribute of the GPDMA transfer from the source. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx =1 . A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer from the source is non-secure."
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: DDW
|
||||
description: "binary logarithm of the destination data width of a burst, in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address CH[x].DAR[2:0] and address offset CH[x].TR3.DAO[2:0], versus DDW[1:0]). Otherwise a user setting error is reported and no transfer is issued."
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: CH_TR1_DW
|
||||
- name: DINC
|
||||
description: "destination incrementing burst. The destination address, pointed by CH[x].DAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer."
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: DBL_1
|
||||
description: "destination burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If DBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed."
|
||||
bit_offset: 20
|
||||
bit_size: 6
|
||||
- name: DBX
|
||||
description: "destination byte exchange. IF set, the two consecutive (post PAM) bytes are exchanged in each destination half-word. If the destination data size is a byte, this bit is ignored."
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: DHX
|
||||
description: "destination half-word exchange. If set, e two consecutive (post PAM) half-words are exchanged in each destination word. If the destination data size is shorter than a word, this bit is ignored."
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: DAP
|
||||
description: "destination allocated port. This bit is used to allocate the master port for the destination transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1."
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
enum: CH_TR1_AP
|
||||
- name: DSEC
|
||||
description: "security attribute of the GPDMA transfer to the destination. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx = 1. A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer to the destination is non-secure."
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/CH_TR2:
|
||||
description: GPDMA channel 10 transfer register 2
|
||||
fields:
|
||||
- name: REQSEL
|
||||
description: "GPDMA hardware request selection. These bits are ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per . The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active GPDMA channels (CH[x].CR.EN = 1 and CH[x].TR2.SWREQ = 0 for these channels). GPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting."
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: SWREQ
|
||||
description: "software request. This bit is internally taken into account when CH[x].CR.EN is asserted."
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: CH_TR2_SWREQ
|
||||
- name: DREQ
|
||||
description: "destination hardware request. This bit is ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note:"
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: CH_TR2_DREQ
|
||||
- name: BREQ
|
||||
description: "Block hardware request. If the channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:"
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
enum: CH_TR2_BREQ
|
||||
- name: TRIGM
|
||||
description: "trigger mode. These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (CH[x].CR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a GPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. – If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. – If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The GPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the CH[x].TR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (CH[x].SR.TOF =1 ), and an interrupt is generated if enabled (CH[x].CR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger."
|
||||
bit_offset: 14
|
||||
bit_size: 2
|
||||
enum: CH_TR2_TRIGM
|
||||
- name: TRIGSEL
|
||||
description: "trigger event input selection. These bits select the trigger event input of the GPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0] ≠ 00."
|
||||
bit_offset: 16
|
||||
bit_size: 6
|
||||
- name: TRIGPOL
|
||||
description: "trigger event polarity. These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0]."
|
||||
bit_offset: 24
|
||||
bit_size: 2
|
||||
enum: CH_TR2_TRIGPOL
|
||||
- name: TCEM
|
||||
description: "transfer complete event mode. These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1."
|
||||
bit_offset: 30
|
||||
bit_size: 2
|
||||
enum: CH_TR2_TCEM
|
||||
fieldset/CH_TR3:
|
||||
description: GPDMA channel 14 transfer register 3
|
||||
fields:
|
||||
- name: SAO
|
||||
description: "source address offset increment. The source address, pointed by CH[x].SAR, is incremented or decremented (depending on CH[x].BR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional CH[x].TR3.SAO[12:0] is not applied."
|
||||
bit_offset: 0
|
||||
bit_size: 13
|
||||
- name: DAO
|
||||
description: "destination address offset increment. The destination address, pointed by CH[x].DAR, is incremented or decremented (depending on CH[x].BR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus CH[x].TR1.DDW[1:0]). Else, a user setting error is reported and no transfer is issued."
|
||||
bit_offset: 16
|
||||
bit_size: 13
|
||||
fieldset/MISR:
|
||||
description: GPDMA secure masked interrupt status register
|
||||
fields:
|
||||
- name: MIS
|
||||
description: MIS0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 16
|
||||
stride: 1
|
||||
fieldset/PRIVCFGR:
|
||||
description: GPDMA privileged configuration register
|
||||
fields:
|
||||
- name: PRIV
|
||||
description: PRIV0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 16
|
||||
stride: 1
|
||||
fieldset/RCFGLOCKR:
|
||||
description: GPDMA configuration lock register
|
||||
fields:
|
||||
- name: LOCK
|
||||
description: LOCK0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 16
|
||||
stride: 1
|
||||
fieldset/SECCFGR:
|
||||
description: GPDMA secure configuration register
|
||||
fields:
|
||||
- name: SEC
|
||||
description: SEC0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 16
|
||||
stride: 1
|
||||
enum/CH_BR1_DEC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Add
|
||||
description: The address is incremented by the programmed offset.
|
||||
value: 0
|
||||
- name: Subtract
|
||||
description: The address is decremented by the programmed offset.
|
||||
value: 1
|
||||
enum/CH_CR_LAP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Port0
|
||||
description: port 0 (AHB) allocated
|
||||
value: 0
|
||||
- name: Port1
|
||||
description: port 1 (AHB) allocated
|
||||
value: 1
|
||||
enum/CH_CR_LSM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: RunToCompletion
|
||||
description: "channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present."
|
||||
value: 0
|
||||
- name: LinkStep
|
||||
description: channel executed once for the current LLI
|
||||
value: 1
|
||||
enum/CH_CR_PRIO:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: LowWithLowhWeight
|
||||
description: "low priority, low weight"
|
||||
value: 0
|
||||
- name: LowWithMidWeight
|
||||
description: "low priority, mid weight"
|
||||
value: 1
|
||||
- name: LowWithHighWeight
|
||||
description: "low priority, high weight"
|
||||
value: 2
|
||||
- name: High
|
||||
description: high priority
|
||||
value: 3
|
||||
enum/CH_TR1_AP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Port0
|
||||
description: port 0 (AHB) allocated
|
||||
value: 0
|
||||
- name: Port1
|
||||
description: port 1 (AHB) allocated
|
||||
value: 1
|
||||
enum/CH_TR1_DW:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Byte
|
||||
description: byte
|
||||
value: 0
|
||||
- name: HalfWord
|
||||
description: half-word (2 bytes)
|
||||
value: 1
|
||||
- name: Word
|
||||
description: word (4 bytes)
|
||||
value: 2
|
||||
enum/CH_TR1_PAM:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: ZeroExtendOrLeftTruncate
|
||||
description: "If destination is wider: source data is transferred as right aligned, padded with 0s up to the destination data width\nIf source is wider: source data is transferred as right aligned, left-truncated down to the destination data width"
|
||||
value: 0
|
||||
- name: SignExtendOrRightTruncate
|
||||
description: "If destination is wider: source data is transferred as right aligned, sign extended up to the destination data width\nIf source is wider: source data is transferred as left-aligned, right-truncated down to the destination data width"
|
||||
value: 1
|
||||
- name: Pack
|
||||
description: "source data is FIFO queued and packed/unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination"
|
||||
value: 2
|
||||
enum/CH_TR2_BREQ:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Burst
|
||||
description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.
|
||||
value: 0
|
||||
- name: Block
|
||||
description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).
|
||||
value: 1
|
||||
enum/CH_TR2_DREQ:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: SourcePeripheral
|
||||
description: selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)
|
||||
value: 0
|
||||
- name: DestinationPeripheral
|
||||
description: selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)
|
||||
value: 1
|
||||
enum/CH_TR2_SWREQ:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Hardware
|
||||
description: "no software request. The selected hardware request REQSEL[6:0] is taken into account."
|
||||
value: 0
|
||||
- name: Software
|
||||
description: "software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored."
|
||||
value: 1
|
||||
enum/CH_TR2_TCEM:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: EachBlock
|
||||
description: "at block level (when CH[x].BR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block."
|
||||
value: 0
|
||||
- name: Each2DBlock
|
||||
description: "channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when CH[x].BR1.BRC[10:0] = 0 and CH[x].BR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block."
|
||||
value: 1
|
||||
- name: EachLinkedListItem
|
||||
description: "at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer."
|
||||
value: 2
|
||||
- name: LastLinkedListItem
|
||||
description: "at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address CH[x].LLR.LA[15:2] to zero and clears all the CH[x].LLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated."
|
||||
value: 3
|
||||
enum/CH_TR2_TRIGM:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Block
|
||||
description: "at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with CH[x].BR1.BRC[10:0] ≠ 0)."
|
||||
value: 0
|
||||
- name: 2DBlock
|
||||
description: "channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the"
|
||||
value: 1
|
||||
- name: LinkedListItem
|
||||
description: "at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned."
|
||||
value: 2
|
||||
- name: Burst
|
||||
description: "at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger."
|
||||
value: 3
|
||||
enum/CH_TR2_TRIGPOL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: None
|
||||
description: no trigger (masked trigger event)
|
||||
value: 0
|
||||
- name: RisingEdge
|
||||
description: trigger on the rising edge
|
||||
value: 1
|
||||
- name: FallingEdge
|
||||
description: trigger on the falling edge
|
||||
value: 2
|
||||
- name: NoneAlt
|
||||
description: same as 00
|
||||
value: 3
|
||||
@ -72,7 +72,7 @@ fieldset/CR:
|
||||
stride: 4
|
||||
enum: MODE
|
||||
- name: CNF_IN
|
||||
description: Port n configuration bits, for input mode
|
||||
description: "Port n configuration bits, for input mode"
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
array:
|
||||
@ -80,7 +80,7 @@ fieldset/CR:
|
||||
stride: 4
|
||||
enum: CNF_IN
|
||||
- name: CNF_OUT
|
||||
description: Port n configuration bits, for output mode
|
||||
description: "Port n configuration bits, for output mode"
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
array:
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,598 +0,0 @@
|
||||
---
|
||||
block/OTG_FS:
|
||||
description: USB on the go full speed
|
||||
items:
|
||||
- name: GOTGCTL
|
||||
description: Control and status register
|
||||
byte_offset: 0
|
||||
fieldset: GOTGCTL
|
||||
- name: GOTGINT
|
||||
description: Interrupt register
|
||||
byte_offset: 4
|
||||
fieldset: GOTGINT
|
||||
- name: GAHBCFG
|
||||
description: AHB configuration register
|
||||
byte_offset: 8
|
||||
fieldset: GAHBCFG
|
||||
- name: GUSBCFG
|
||||
description: USB configuration register
|
||||
byte_offset: 12
|
||||
fieldset: GUSBCFG
|
||||
- name: GRSTCTL
|
||||
description: Reset register
|
||||
byte_offset: 16
|
||||
fieldset: GRSTCTL
|
||||
- name: GINTSTS
|
||||
description: Core interrupt register
|
||||
byte_offset: 20
|
||||
fieldset: GINTSTS
|
||||
- name: GINTMSK
|
||||
description: Interrupt mask register
|
||||
byte_offset: 24
|
||||
fieldset: GINTMSK
|
||||
- name: GRXSTSR_Device
|
||||
description: Receive status debug read (Device mode)
|
||||
byte_offset: 28
|
||||
access: Read
|
||||
fieldset: GRXSTSR_Device
|
||||
- name: GRXSTSR_Host
|
||||
description: Receive status debug read (Host mode)
|
||||
byte_offset: 28
|
||||
access: Read
|
||||
fieldset: GRXSTSR_Host
|
||||
- name: GRXSTSP_Device
|
||||
description: Status read and pop (Device mode)
|
||||
byte_offset: 32
|
||||
access: Read
|
||||
fieldset: GRXSTSP_Device
|
||||
- name: GRXSTSP_Host
|
||||
description: Status read and pop (Host mode)
|
||||
byte_offset: 32
|
||||
access: Read
|
||||
fieldset: GRXSTSP_Host
|
||||
- name: GRXFSIZ
|
||||
description: Receive FIFO size register
|
||||
byte_offset: 36
|
||||
fieldset: GRXFSIZ
|
||||
- name: DIEPTXF0
|
||||
description: Non-periodic transmit FIFO size register (Device mode)
|
||||
byte_offset: 40
|
||||
fieldset: DIEPTXF0
|
||||
- name: HNPTXFSIZ
|
||||
description: Non-periodic transmit FIFO size register (Host mode)
|
||||
byte_offset: 40
|
||||
fieldset: HNPTXFSIZ
|
||||
- name: GNPTXSTS
|
||||
description: Non-periodic transmit FIFO/queue status register
|
||||
byte_offset: 44
|
||||
access: Read
|
||||
fieldset: GNPTXSTS
|
||||
- name: GCCFG
|
||||
description: General core configuration register
|
||||
byte_offset: 56
|
||||
fieldset: GCCFG
|
||||
- name: CID
|
||||
description: Core ID register
|
||||
byte_offset: 60
|
||||
fieldset: CID
|
||||
- name: HPTXFSIZ
|
||||
description: Host periodic transmit FIFO size register
|
||||
byte_offset: 256
|
||||
fieldset: HPTXFSIZ
|
||||
- name: DIEPTXF
|
||||
description: Device IN endpoint transmit FIFO size register
|
||||
array:
|
||||
len: 3
|
||||
stride: 4
|
||||
byte_offset: 260
|
||||
fieldset: DIEPTXF
|
||||
fieldset/CID:
|
||||
description: Core ID register
|
||||
fields:
|
||||
- name: PRODUCT_ID
|
||||
description: Product ID field
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/DIEPTXF:
|
||||
description: Device IN endpoint transmit FIFO size register
|
||||
fields:
|
||||
- name: INEPTXSA
|
||||
description: IN endpoint FIFO2 transmit RAM start address
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: INEPTXFD
|
||||
description: IN endpoint TxFIFO depth
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/DIEPTXF0:
|
||||
description: Non-periodic transmit FIFO size register (Device mode)
|
||||
fields:
|
||||
- name: TX0FSA
|
||||
description: Endpoint 0 transmit RAM start address
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: TX0FD
|
||||
description: Endpoint 0 TxFIFO depth
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/GAHBCFG:
|
||||
description: AHB configuration register
|
||||
fields:
|
||||
- name: GINT
|
||||
description: Global interrupt mask
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TXFELVL
|
||||
description: TxFIFO empty level
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: PTXFELVL
|
||||
description: Periodic TxFIFO empty level
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
fieldset/GCCFG:
|
||||
description: General core configuration register
|
||||
fields:
|
||||
- name: PWRDWN
|
||||
description: Power down
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: VBUSASEN
|
||||
description: Enable the VBUS sensing device
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: VBUSBSEN
|
||||
description: Enable the VBUS sensing device
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: SOFOUTEN
|
||||
description: SOF output enable
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
fieldset/GINTMSK:
|
||||
description: Interrupt mask register
|
||||
fields:
|
||||
- name: MMISM
|
||||
description: Mode mismatch interrupt mask
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: OTGINT
|
||||
description: OTG interrupt mask
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: SOFM
|
||||
description: Start of frame mask
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: RXFLVLM
|
||||
description: Receive FIFO non-empty mask
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: NPTXFEM
|
||||
description: Non-periodic TxFIFO empty mask
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: GINAKEFFM
|
||||
description: Global non-periodic IN NAK effective mask
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: GONAKEFFM
|
||||
description: Global OUT NAK effective mask
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: ESUSPM
|
||||
description: Early suspend mask
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: USBSUSPM
|
||||
description: USB suspend mask
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: USBRST
|
||||
description: USB reset mask
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: ENUMDNEM
|
||||
description: Enumeration done mask
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: ISOODRPM
|
||||
description: Isochronous OUT packet dropped interrupt mask
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: EOPFM
|
||||
description: End of periodic frame interrupt mask
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: IEPINT
|
||||
description: IN endpoints interrupt mask
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: OEPINT
|
||||
description: OUT endpoints interrupt mask
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: IISOIXFRM
|
||||
description: Incomplete isochronous IN transfer mask
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: IPXFRM_IISOOXFRM
|
||||
description: Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: PRTIM
|
||||
description: Host port interrupt mask
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: HCIM
|
||||
description: Host channels interrupt mask
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: PTXFEM
|
||||
description: Periodic TxFIFO empty mask
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: CIDSCHGM
|
||||
description: Connector ID status change mask
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: DISCINT
|
||||
description: Disconnect detected interrupt mask
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: SRQIM
|
||||
description: Session request/new session detected interrupt mask
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: WUIM
|
||||
description: Resume/remote wakeup detected interrupt mask
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/GINTSTS:
|
||||
description: Core interrupt register
|
||||
fields:
|
||||
- name: CMOD
|
||||
description: Current mode of operation
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: MMIS
|
||||
description: Mode mismatch interrupt
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: OTGINT
|
||||
description: OTG interrupt
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: SOF
|
||||
description: Start of frame
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: RXFLVL
|
||||
description: RxFIFO non-empty
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: NPTXFE
|
||||
description: Non-periodic TxFIFO empty
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: GINAKEFF
|
||||
description: Global IN non-periodic NAK effective
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: GOUTNAKEFF
|
||||
description: Global OUT NAK effective
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: ESUSP
|
||||
description: Early suspend
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: USBSUSP
|
||||
description: USB suspend
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: USBRST
|
||||
description: USB reset
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: ENUMDNE
|
||||
description: Enumeration done
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: ISOODRP
|
||||
description: Isochronous OUT packet dropped interrupt
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: EOPF
|
||||
description: End of periodic frame interrupt
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: IEPINT
|
||||
description: IN endpoint interrupt
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: OEPINT
|
||||
description: OUT endpoint interrupt
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: IISOIXFR
|
||||
description: Incomplete isochronous IN transfer
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: IPXFR_INCOMPISOOUT
|
||||
description: Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: HPRTINT
|
||||
description: Host port interrupt
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: HCINT
|
||||
description: Host channels interrupt
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: PTXFE
|
||||
description: Periodic TxFIFO empty
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: CIDSCHG
|
||||
description: Connector ID status change
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: DISCINT
|
||||
description: Disconnect detected interrupt
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: SRQINT
|
||||
description: Session request/new session detected interrupt
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: WKUPINT
|
||||
description: Resume/remote wakeup detected interrupt
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/GOTGCTL:
|
||||
description: Control and status register
|
||||
fields:
|
||||
- name: SRQSCS
|
||||
description: Session request success
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SRQ
|
||||
description: Session request
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: HNGSCS
|
||||
description: Host negotiation success
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: HNPRQ
|
||||
description: HNP request
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: HSHNPEN
|
||||
description: Host set HNP enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DHNPEN
|
||||
description: Device HNP enabled
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: CIDSTS
|
||||
description: Connector ID status
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: DBCT
|
||||
description: Long/short debounce time
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: ASVLD
|
||||
description: A-session valid
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: BSVLD
|
||||
description: B-session valid
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
fieldset/GOTGINT:
|
||||
description: Interrupt register
|
||||
fields:
|
||||
- name: SEDET
|
||||
description: Session end detected
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: SRSSCHG
|
||||
description: Session request success status change
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: HNSSCHG
|
||||
description: Host negotiation success status change
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: HNGDET
|
||||
description: Host negotiation detected
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: ADTOCHG
|
||||
description: A-device timeout change
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: DBCDNE
|
||||
description: Debounce done
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
fieldset/GRSTCTL:
|
||||
description: Reset register
|
||||
fields:
|
||||
- name: CSRST
|
||||
description: Core soft reset
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: HSRST
|
||||
description: HCLK soft reset
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: FCRST
|
||||
description: Host frame counter reset
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: RXFFLSH
|
||||
description: RxFIFO flush
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TXFFLSH
|
||||
description: TxFIFO flush
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TXFNUM
|
||||
description: TxFIFO number
|
||||
bit_offset: 6
|
||||
bit_size: 5
|
||||
- name: AHBIDL
|
||||
description: AHB master idle
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/GRXFSIZ:
|
||||
description: Receive FIFO size register
|
||||
fields:
|
||||
- name: RXFD
|
||||
description: RxFIFO depth
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/GRXSTSP_Device:
|
||||
description: Status read and pop (Device mode)
|
||||
fields:
|
||||
- name: EPNUM
|
||||
description: Endpoint number
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: BCNT
|
||||
description: Byte count
|
||||
bit_offset: 4
|
||||
bit_size: 11
|
||||
- name: DPID
|
||||
description: Data PID
|
||||
bit_offset: 15
|
||||
bit_size: 2
|
||||
- name: PKTSTS
|
||||
description: Packet status
|
||||
bit_offset: 17
|
||||
bit_size: 4
|
||||
- name: FRMNUM
|
||||
description: Frame number
|
||||
bit_offset: 21
|
||||
bit_size: 4
|
||||
fieldset/GRXSTSP_Host:
|
||||
description: Status read and pop (Host mode)
|
||||
fields:
|
||||
- name: CHNUM
|
||||
description: Channel number
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: BCNT
|
||||
description: Byte count
|
||||
bit_offset: 4
|
||||
bit_size: 11
|
||||
- name: DPID
|
||||
description: Data PID
|
||||
bit_offset: 15
|
||||
bit_size: 2
|
||||
- name: PKTSTS
|
||||
description: Packet status
|
||||
bit_offset: 17
|
||||
bit_size: 4
|
||||
fieldset/GRXSTSR_Device:
|
||||
description: Receive status debug read(Device mode)
|
||||
fields:
|
||||
- name: EPNUM
|
||||
description: Endpoint number
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: BCNT
|
||||
description: Byte count
|
||||
bit_offset: 4
|
||||
bit_size: 11
|
||||
- name: DPID
|
||||
description: Data PID
|
||||
bit_offset: 15
|
||||
bit_size: 2
|
||||
- name: PKTSTS
|
||||
description: Packet status
|
||||
bit_offset: 17
|
||||
bit_size: 4
|
||||
- name: FRMNUM
|
||||
description: Frame number
|
||||
bit_offset: 21
|
||||
bit_size: 4
|
||||
fieldset/GRXSTSR_Host:
|
||||
description: Receive status debug read(Host mode)
|
||||
fields:
|
||||
- name: EPNUM
|
||||
description: Endpoint number
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: BCNT
|
||||
description: Byte count
|
||||
bit_offset: 4
|
||||
bit_size: 11
|
||||
- name: DPID
|
||||
description: Data PID
|
||||
bit_offset: 15
|
||||
bit_size: 2
|
||||
- name: PKTSTS
|
||||
description: Packet status
|
||||
bit_offset: 17
|
||||
bit_size: 4
|
||||
fieldset/GUSBCFG:
|
||||
description: USB configuration register
|
||||
fields:
|
||||
- name: TOCAL
|
||||
description: FS timeout calibration
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
- name: PHYSEL
|
||||
description: Full Speed serial transceiver select
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: SRPCAP
|
||||
description: SRP-capable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: HNPCAP
|
||||
description: HNP-capable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: TRDT
|
||||
description: USB turnaround time
|
||||
bit_offset: 10
|
||||
bit_size: 4
|
||||
- name: FHMOD
|
||||
description: Force host mode
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: FDMOD
|
||||
description: Force device mode
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
fieldset/HNPTXFSIZ:
|
||||
description: Non-periodic transmit FIFO size register (Host mode)
|
||||
fields:
|
||||
- name: NPTXFSA
|
||||
description: Non-periodic transmit RAM start address
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: NPTXFD
|
||||
description: Non-periodic TxFIFO depth
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/HPTXFSIZ:
|
||||
description: Host periodic transmit FIFO size register
|
||||
fields:
|
||||
- name: PTXSA
|
||||
description: Host periodic TxFIFO start address
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: PTXFSIZ
|
||||
description: Host periodic TxFIFO depth
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
413
data/registers/pwr_l4.yaml
Normal file
413
data/registers/pwr_l4.yaml
Normal file
@ -0,0 +1,413 @@
|
||||
---
|
||||
block/PWR:
|
||||
description: Power control
|
||||
items:
|
||||
- name: CR1
|
||||
description: Power control register 1
|
||||
byte_offset: 0
|
||||
fieldset: CR1
|
||||
- name: CR2
|
||||
description: Power control register 2
|
||||
byte_offset: 4
|
||||
fieldset: CR2
|
||||
- name: CR3
|
||||
description: Power control register 3
|
||||
byte_offset: 8
|
||||
fieldset: CR3
|
||||
- name: CR4
|
||||
description: Power control register 4
|
||||
byte_offset: 12
|
||||
fieldset: CR4
|
||||
- name: SR1
|
||||
description: Power status register 1
|
||||
byte_offset: 16
|
||||
access: Read
|
||||
fieldset: SR1
|
||||
- name: SR2
|
||||
description: Power status register 2
|
||||
byte_offset: 20
|
||||
access: Read
|
||||
fieldset: SR2
|
||||
- name: SCR
|
||||
description: Power status clear register
|
||||
byte_offset: 24
|
||||
access: Write
|
||||
fieldset: SCR
|
||||
- name: PUCR
|
||||
description: Power Port A pull-up control register
|
||||
array:
|
||||
len: 8
|
||||
stride: 8
|
||||
byte_offset: 32
|
||||
fieldset: PCR
|
||||
- name: PDCR
|
||||
description: Power Port A pull-down control register
|
||||
array:
|
||||
len: 8
|
||||
stride: 8
|
||||
byte_offset: 36
|
||||
fieldset: PCR
|
||||
fieldset/CR1:
|
||||
description: Power control register 1
|
||||
fields:
|
||||
- name: LPMS
|
||||
description: Low-power mode selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: LPMS
|
||||
- name: DBP
|
||||
description: Disable backup domain write protection
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: DBP
|
||||
- name: VOS
|
||||
description: Voltage scaling range selection
|
||||
bit_offset: 9
|
||||
bit_size: 2
|
||||
enum: VOS
|
||||
- name: LPR
|
||||
description: Low-power run
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
enum: LPR
|
||||
fieldset/CR2:
|
||||
description: Power control register 2
|
||||
fields:
|
||||
- name: PVDE
|
||||
description: Power voltage detector enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
enum: PVDE
|
||||
- name: PLS
|
||||
description: Power voltage detector level selection
|
||||
bit_offset: 1
|
||||
bit_size: 3
|
||||
enum: PLS
|
||||
- name: PVME1
|
||||
description: "Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V"
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: PVME
|
||||
- name: PVME2
|
||||
description: "Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V"
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: PVME
|
||||
- name: PVME3
|
||||
description: "Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V"
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
enum: PVME
|
||||
- name: PVME4
|
||||
description: "Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V"
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: PVME
|
||||
- name: IOSV
|
||||
description: VDDIO2 Independent I/Os supply valid
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: IOSV
|
||||
- name: USV
|
||||
description: VDDUSB USB supply valid
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: USV
|
||||
fieldset/CR3:
|
||||
description: Power control register 3
|
||||
fields:
|
||||
- name: EWUP
|
||||
description: Enable Wakeup pin WKUP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
enum: EWUP
|
||||
- name: RRS
|
||||
description: SRAM2 retention in Standby mode
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: RRS
|
||||
- name: APC
|
||||
description: Apply pull-up and pull-down configuration
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: APC
|
||||
- name: EWF
|
||||
description: Enable internal wakeup line
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum: EWF
|
||||
fieldset/CR4:
|
||||
description: Power control register 4
|
||||
fields:
|
||||
- name: WP1
|
||||
description: Wakeup pin WKUP1 polarity
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: WP2
|
||||
description: Wakeup pin WKUP2 polarity
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WP3
|
||||
description: Wakeup pin WKUP3 polarity
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: WP4
|
||||
description: Wakeup pin WKUP4 polarity
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WP5
|
||||
description: Wakeup pin WKUP5 polarity
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: VBE
|
||||
description: VBAT battery charging enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: VBRS
|
||||
description: VBAT battery charging resistor selection
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
fieldset/PCR:
|
||||
description: Power Port pull control register
|
||||
fields:
|
||||
- name: P
|
||||
description: Port pull bit y (y=0..15)
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 16
|
||||
stride: 1
|
||||
fieldset/SCR:
|
||||
description: Power status clear register
|
||||
fields:
|
||||
- name: CWUF
|
||||
description: Clear wakeup flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
enum_write: CWUFW
|
||||
- name: SBF
|
||||
description: Clear standby flag
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
fieldset/SR1:
|
||||
description: Power status register 1
|
||||
fields:
|
||||
- name: CWUF1
|
||||
description: Wakeup flag 1
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: CWUF2
|
||||
description: Wakeup flag 2
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: CWUF3
|
||||
description: Wakeup flag 3
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: CWUF4
|
||||
description: Wakeup flag 4
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: CWUF5
|
||||
description: Wakeup flag 5
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: CSBF
|
||||
description: Standby flag
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: WUFI
|
||||
description: Wakeup flag internal
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
fieldset/SR2:
|
||||
description: Power status register 2
|
||||
fields:
|
||||
- name: REGLPS
|
||||
description: Low-power regulator started
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: REGLPF
|
||||
description: Low-power regulator flag
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: VOSF
|
||||
description: Voltage scaling flag
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: PVDO
|
||||
description: Power voltage detector output
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: PVMO1
|
||||
description: "Peripheral voltage monitoring output: VDDUSB vs. 1.2 V"
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: PVMO2
|
||||
description: "Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V"
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: PVMO3
|
||||
description: "Peripheral voltage monitoring output: VDDA vs. 1.62 V"
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: PVMO4
|
||||
description: "Peripheral voltage monitoring output: VDDA vs. 2.2 V"
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum/APC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied
|
||||
value: 1
|
||||
enum/CWUFW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Clear
|
||||
description: Setting this bit clears the WUF flag in the PWR_SR1 register. This bit is always read as 0.
|
||||
value: 1
|
||||
enum/DBP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Access to RTC and backup registers disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Access to RTC and backup registers enabled
|
||||
value: 1
|
||||
enum/EWF:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Internal wakeup line disable
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Internal wakeup line enable
|
||||
value: 1
|
||||
enum/EWUP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: WKUP pin x is used for general purpose I/Os. An event on the WKUP pin x does not wakeup the device from Standby mode
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: WKUP pin x is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin x wakes-up the system from Standby mode)
|
||||
value: 1
|
||||
enum/IOSV:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Invalid
|
||||
description: VDDIO2 is not present. Logical and electrical isolation is applied to ignore this supply
|
||||
value: 0
|
||||
- name: Valid
|
||||
description: VDDIO2 is valid
|
||||
value: 1
|
||||
enum/LPMS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Stop0
|
||||
description: Stop 0 mode
|
||||
value: 0
|
||||
- name: Stop1
|
||||
description: Stop 1 mode
|
||||
value: 1
|
||||
- name: Stop2
|
||||
description: Stop 2 mode
|
||||
value: 2
|
||||
- name: Standby
|
||||
description: Standby mode
|
||||
value: 3
|
||||
- name: Shutdown
|
||||
description: Shutdown mode
|
||||
value: 4
|
||||
enum/LPR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: MainMode
|
||||
description: Voltage regulator in Main mode
|
||||
value: 0
|
||||
- name: LowPowerMode
|
||||
description: Voltage regulator in low-power mode
|
||||
value: 1
|
||||
enum/PLS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: V2_0
|
||||
description: 2.0V
|
||||
value: 0
|
||||
- name: V2_2
|
||||
description: 2.2V
|
||||
value: 1
|
||||
- name: V2_4
|
||||
description: 2.4V
|
||||
value: 2
|
||||
- name: V2_5
|
||||
description: 2.5V
|
||||
value: 3
|
||||
- name: V2_6
|
||||
description: 2.6V
|
||||
value: 4
|
||||
- name: V2_8
|
||||
description: 2.8V
|
||||
value: 5
|
||||
- name: V2_9
|
||||
description: 2.9V
|
||||
value: 6
|
||||
- name: External
|
||||
description: External input analog voltage PVD_IN (compared internally to VREFINT)
|
||||
value: 7
|
||||
enum/PVDE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: PVD Disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: PVD Enabled
|
||||
value: 1
|
||||
enum/PVME:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Peripheral voltage monitoring disable
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Peripheral voltage monitoring enable
|
||||
value: 1
|
||||
enum/RRS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: PowerOff
|
||||
description: SRAM2 powered off in Standby mode (SRAM2 content lost)
|
||||
value: 0
|
||||
- name: OnLPR
|
||||
description: SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept)
|
||||
value: 1
|
||||
enum/USV:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Invalid
|
||||
description: VDDUSB is not present. Logical and electrical isolation is applied to ignore this supply
|
||||
value: 0
|
||||
- name: Valid
|
||||
description: VDDUSB is valid
|
||||
value: 1
|
||||
enum/VOS:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Range1
|
||||
description: Range 1
|
||||
value: 1
|
||||
- name: Range2
|
||||
description: Range 2
|
||||
value: 2
|
||||
487
data/registers/pwr_l5.yaml
Normal file
487
data/registers/pwr_l5.yaml
Normal file
@ -0,0 +1,487 @@
|
||||
---
|
||||
block/PWR:
|
||||
description: Power control
|
||||
items:
|
||||
- name: CR1
|
||||
description: Power control register 1
|
||||
byte_offset: 0
|
||||
fieldset: CR1
|
||||
- name: CR2
|
||||
description: Power control register 2
|
||||
byte_offset: 4
|
||||
fieldset: CR2
|
||||
- name: CR3
|
||||
description: Power control register 3
|
||||
byte_offset: 8
|
||||
fieldset: CR3
|
||||
- name: CR4
|
||||
description: Power control register 4
|
||||
byte_offset: 12
|
||||
fieldset: CR4
|
||||
- name: SR1
|
||||
description: Power status register 1
|
||||
byte_offset: 16
|
||||
access: Read
|
||||
fieldset: SR1
|
||||
- name: SR2
|
||||
description: Power status register 2
|
||||
byte_offset: 20
|
||||
access: Read
|
||||
fieldset: SR2
|
||||
- name: SCR
|
||||
description: Power status clear register
|
||||
byte_offset: 24
|
||||
access: Write
|
||||
fieldset: SCR
|
||||
- name: PUCR
|
||||
description: Power Port A pull-up control register
|
||||
array:
|
||||
len: 8
|
||||
stride: 8
|
||||
byte_offset: 32
|
||||
fieldset: PCR
|
||||
- name: PDCR
|
||||
description: Power Port A pull-down control register
|
||||
array:
|
||||
len: 8
|
||||
stride: 8
|
||||
byte_offset: 36
|
||||
fieldset: PCR
|
||||
- name: SECCFGR
|
||||
description: Power secure configuration register
|
||||
byte_offset: 120
|
||||
fieldset: SECCFGR
|
||||
- name: PRIVCFGR
|
||||
description: Power privilege configuration register
|
||||
byte_offset: 128
|
||||
fieldset: PRIVCFGR
|
||||
fieldset/CR1:
|
||||
description: Power control register 1
|
||||
fields:
|
||||
- name: LPMS
|
||||
description: Low-power mode selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: LPMS
|
||||
- name: DBP
|
||||
description: Disable backup domain write protection
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: DBP
|
||||
- name: VOS
|
||||
description: Voltage scaling range selection
|
||||
bit_offset: 9
|
||||
bit_size: 2
|
||||
enum: VOS
|
||||
- name: LPR
|
||||
description: Low-power run
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
enum: LPR
|
||||
fieldset/CR2:
|
||||
description: Power control register 2
|
||||
fields:
|
||||
- name: PVDE
|
||||
description: Power voltage detector enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
enum: PVDE
|
||||
- name: PLS
|
||||
description: Power voltage detector level selection
|
||||
bit_offset: 1
|
||||
bit_size: 3
|
||||
enum: PLS
|
||||
- name: PVME1
|
||||
description: "Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V"
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: PVME
|
||||
- name: PVME2
|
||||
description: "Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V"
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: PVME
|
||||
- name: PVME3
|
||||
description: "Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V"
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
enum: PVME
|
||||
- name: PVME4
|
||||
description: "Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V"
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: PVME
|
||||
- name: IOSV
|
||||
description: VDDIO2 Independent I/Os supply valid
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: IOSV
|
||||
- name: USV
|
||||
description: VDDUSB USB supply valid
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: USV
|
||||
fieldset/CR3:
|
||||
description: Power control register 3
|
||||
fields:
|
||||
- name: EWUP
|
||||
description: Enable Wakeup pin WKUP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
enum: EWUP
|
||||
- name: RRS
|
||||
description: SRAM2 retention in Standby mode
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
enum: RRS
|
||||
- name: APC
|
||||
description: Apply pull-up and pull-down configuration
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: APC
|
||||
- name: ULPMEN
|
||||
description: ULPMEN
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: UCPD_STDBY
|
||||
description: UCPD_STDBY
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: UCPD_DBDIS
|
||||
description: UCPD_DBDIS
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
fieldset/CR4:
|
||||
description: Power control register 4
|
||||
fields:
|
||||
- name: WP1
|
||||
description: Wakeup pin WKUP1 polarity
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: WP2
|
||||
description: Wakeup pin WKUP2 polarity
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WP3
|
||||
description: Wakeup pin WKUP3 polarity
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: WP4
|
||||
description: Wakeup pin WKUP4 polarity
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WP5
|
||||
description: Wakeup pin WKUP5 polarity
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: VBE
|
||||
description: VBAT battery charging enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: VBRS
|
||||
description: VBAT battery charging resistor selection
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: SMPSBYP
|
||||
description: SMPSBYP
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: EXTSMPSEN
|
||||
description: EXTSMPSEN
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: SMPSFSTEN
|
||||
description: SMPSFSTEN
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: SMPSLPEN
|
||||
description: SMPSLPEN
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
fieldset/PCR:
|
||||
description: Power Port pull control register
|
||||
fields:
|
||||
- name: P
|
||||
description: Port pull bit y (y=0..15)
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 16
|
||||
stride: 1
|
||||
fieldset/PRIVCFGR:
|
||||
description: Power privilege configuration register
|
||||
fields:
|
||||
- name: PRIV
|
||||
description: PRIV
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
fieldset/SCR:
|
||||
description: Power status clear register
|
||||
fields:
|
||||
- name: CWUF
|
||||
description: Clear wakeup flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
enum_write: CWUFW
|
||||
- name: SBF
|
||||
description: Clear standby flag
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
fieldset/SECCFGR:
|
||||
description: Power secure configuration register
|
||||
fields:
|
||||
- name: WUP1SEC
|
||||
description: WKUP1 pin security
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: WUP2SEC
|
||||
description: WKUP2 pin security
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: WUP3SEC
|
||||
description: WKUP3 pin security
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: WUP4SEC
|
||||
description: WKUP4 pin security
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: WUP5SEC
|
||||
description: WKUP5 pin security
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: LPMSEC
|
||||
description: LPMSEC
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: VDMSEC
|
||||
description: VDMSEC
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: VBSEC
|
||||
description: VBSEC
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: APCSEC
|
||||
description: APCSEC
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
fieldset/SR1:
|
||||
description: Power status register 1
|
||||
fields:
|
||||
- name: CWUF1
|
||||
description: Wakeup flag 1
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: CWUF2
|
||||
description: Wakeup flag 2
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: CWUF3
|
||||
description: Wakeup flag 3
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: CWUF4
|
||||
description: Wakeup flag 4
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: CWUF5
|
||||
description: Wakeup flag 5
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: CSBF
|
||||
description: Standby flag
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: WUFI
|
||||
description: Wakeup flag internal
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
fieldset/SR2:
|
||||
description: Power status register 2
|
||||
fields:
|
||||
- name: REGLPS
|
||||
description: Low-power regulator started
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: REGLPF
|
||||
description: Low-power regulator flag
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: VOSF
|
||||
description: Voltage scaling flag
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: PVDO
|
||||
description: Power voltage detector output
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: PVMO1
|
||||
description: "Peripheral voltage monitoring output: VDDUSB vs. 1.2 V"
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: PVMO2
|
||||
description: "Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V"
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: PVMO3
|
||||
description: "Peripheral voltage monitoring output: VDDA vs. 1.62 V"
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: PVMO4
|
||||
description: "Peripheral voltage monitoring output: VDDA vs. 2.2 V"
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum/APC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied
|
||||
value: 1
|
||||
enum/CWUFW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Clear
|
||||
description: Setting this bit clears the WUF flag in the PWR_SR1 register. This bit is always read as 0.
|
||||
value: 1
|
||||
enum/DBP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Access to RTC and backup registers disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Access to RTC and backup registers enabled
|
||||
value: 1
|
||||
enum/EWUP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: WKUP pin x is used for general purpose I/Os. An event on the WKUP pin x does not wakeup the device from Standby mode
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: WKUP pin x is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin x wakes-up the system from Standby mode)
|
||||
value: 1
|
||||
enum/IOSV:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Invalid
|
||||
description: VDDIO2 is not present. Logical and electrical isolation is applied to ignore this supply
|
||||
value: 0
|
||||
- name: Valid
|
||||
description: VDDIO2 is valid
|
||||
value: 1
|
||||
enum/LPMS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Stop0
|
||||
description: Stop 0 mode
|
||||
value: 0
|
||||
- name: Stop1
|
||||
description: Stop 1 mode
|
||||
value: 1
|
||||
- name: Stop2
|
||||
description: Stop 2 mode
|
||||
value: 2
|
||||
- name: Standby
|
||||
description: Standby mode
|
||||
value: 3
|
||||
- name: Shutdown
|
||||
description: Shutdown mode
|
||||
value: 4
|
||||
enum/LPR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: MainMode
|
||||
description: Voltage regulator in Main mode
|
||||
value: 0
|
||||
- name: LowPowerMode
|
||||
description: Voltage regulator in low-power mode
|
||||
value: 1
|
||||
enum/PLS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: V2_0
|
||||
description: 2.0V
|
||||
value: 0
|
||||
- name: V2_2
|
||||
description: 2.2V
|
||||
value: 1
|
||||
- name: V2_4
|
||||
description: 2.4V
|
||||
value: 2
|
||||
- name: V2_5
|
||||
description: 2.5V
|
||||
value: 3
|
||||
- name: V2_6
|
||||
description: 2.6V
|
||||
value: 4
|
||||
- name: V2_8
|
||||
description: 2.8V
|
||||
value: 5
|
||||
- name: V2_9
|
||||
description: 2.9V
|
||||
value: 6
|
||||
- name: External
|
||||
description: External input analog voltage PVD_IN (compared internally to VREFINT)
|
||||
value: 7
|
||||
enum/PVDE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: PVD Disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: PVD Enabled
|
||||
value: 1
|
||||
enum/PVME:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Peripheral voltage monitoring disable
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Peripheral voltage monitoring enable
|
||||
value: 1
|
||||
enum/RRS:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: PowerOff
|
||||
description: SRAM2 powered off in Standby mode (SRAM2 content lost)
|
||||
value: 0
|
||||
- name: OnLPR
|
||||
description: SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept)
|
||||
value: 1
|
||||
- name: OnLPRTop4kb
|
||||
description: Only the upper 4 Kbytes of SRAM2 are powered by the low-power regulator in Standby mode (upper 4 Kbytes of SRAM2 content 0x2003 F000 - 0x2003 FFFF is kept).
|
||||
value: 2
|
||||
enum/USV:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Invalid
|
||||
description: VDDUSB is not present. Logical and electrical isolation is applied to ignore this supply
|
||||
value: 0
|
||||
- name: Valid
|
||||
description: VDDUSB is valid
|
||||
value: 1
|
||||
enum/VOS:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Range0
|
||||
description: Range 0
|
||||
value: 0
|
||||
- name: Range1
|
||||
description: Range 1
|
||||
value: 1
|
||||
- name: Range2
|
||||
description: Range 2
|
||||
value: 2
|
||||
@ -3,82 +3,82 @@ block/PWR:
|
||||
description: Power control
|
||||
items:
|
||||
- name: CR1
|
||||
description: "PWR control register 1 "
|
||||
description: PWR control register 1
|
||||
byte_offset: 0
|
||||
fieldset: CR1
|
||||
- name: CR2
|
||||
description: "PWR control register 2 "
|
||||
description: PWR control register 2
|
||||
byte_offset: 4
|
||||
fieldset: CR2
|
||||
- name: CR3
|
||||
description: "PWR control register 3 "
|
||||
description: PWR control register 3
|
||||
byte_offset: 8
|
||||
fieldset: CR3
|
||||
- name: VOSR
|
||||
description: "PWR voltage scaling register "
|
||||
description: PWR voltage scaling register
|
||||
byte_offset: 12
|
||||
fieldset: VOSR
|
||||
- name: SVMCR
|
||||
description: "PWR supply voltage monitoring control register "
|
||||
description: PWR supply voltage monitoring control register
|
||||
byte_offset: 16
|
||||
fieldset: SVMCR
|
||||
- name: WUCR1
|
||||
description: "PWR wakeup control register 1 "
|
||||
description: PWR wakeup control register 1
|
||||
byte_offset: 20
|
||||
fieldset: WUCR1
|
||||
- name: WUCR2
|
||||
description: "PWR wakeup control register 2 "
|
||||
description: PWR wakeup control register 2
|
||||
byte_offset: 24
|
||||
fieldset: WUCR2
|
||||
- name: WUCR3
|
||||
description: "PWR wakeup control register 3 "
|
||||
description: PWR wakeup control register 3
|
||||
byte_offset: 28
|
||||
fieldset: WUCR3
|
||||
- name: BDCR1
|
||||
description: "PWR Backup domain control register 1 "
|
||||
description: PWR Backup domain control register 1
|
||||
byte_offset: 32
|
||||
fieldset: BDCR1
|
||||
- name: BDCR2
|
||||
description: "PWR Backup domain control register 2 "
|
||||
description: PWR Backup domain control register 2
|
||||
byte_offset: 36
|
||||
fieldset: BDCR2
|
||||
- name: DBPR
|
||||
description: "PWR disable Backup domain register "
|
||||
description: PWR disable Backup domain register
|
||||
byte_offset: 40
|
||||
fieldset: DBPR
|
||||
- name: UCPDR
|
||||
description: "PWR USB Type-C™ and Power Delivery register "
|
||||
description: PWR USB Type-C™ and Power Delivery register
|
||||
byte_offset: 44
|
||||
fieldset: UCPDR
|
||||
- name: SECCFGR
|
||||
description: "PWR security configuration register "
|
||||
description: PWR security configuration register
|
||||
byte_offset: 48
|
||||
fieldset: SECCFGR
|
||||
- name: PRIVCFGR
|
||||
description: "PWR privilege control register "
|
||||
description: PWR privilege control register
|
||||
byte_offset: 52
|
||||
fieldset: PRIVCFGR
|
||||
- name: SR
|
||||
description: "PWR status register "
|
||||
description: PWR status register
|
||||
byte_offset: 56
|
||||
fieldset: SR
|
||||
- name: SVMSR
|
||||
byte_offset: 60
|
||||
fieldset: SVMSR
|
||||
- name: BDSR
|
||||
description: "PWR Backup domain status register "
|
||||
description: PWR Backup domain status register
|
||||
byte_offset: 64
|
||||
fieldset: BDSR
|
||||
- name: WUSR
|
||||
description: "PWR wakeup status register "
|
||||
description: PWR wakeup status register
|
||||
byte_offset: 68
|
||||
fieldset: WUSR
|
||||
- name: WUSCR
|
||||
description: "PWR wakeup status clear register "
|
||||
description: PWR wakeup status clear register
|
||||
byte_offset: 72
|
||||
fieldset: WUSCR
|
||||
- name: APCR
|
||||
description: "PWR apply pull configuration register "
|
||||
description: PWR apply pull configuration register
|
||||
byte_offset: 76
|
||||
fieldset: APCR
|
||||
- name: PUCR
|
||||
@ -96,14 +96,14 @@ block/PWR:
|
||||
byte_offset: 84
|
||||
fieldset: PCR
|
||||
fieldset/APCR:
|
||||
description: "PWR apply pull configuration register "
|
||||
description: PWR apply pull configuration register
|
||||
fields:
|
||||
- name: APC
|
||||
description: "Apply pull-up and pull-down configuration\r When this bit is set, the I/O pull-up and pull-down configurations defined in PUCRx and PDCRx are applied. When this bit is cleared, PUCRx and PDCRx are not applied to the I/Os."
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
fieldset/BDCR1:
|
||||
description: "PWR Backup domain control register 1 "
|
||||
description: PWR Backup domain control register 1
|
||||
fields:
|
||||
- name: BREN
|
||||
description: "Backup RAM retention in Standby and VBAT modes\r When this bit is set, the backup RAM content is kept in Standby and VBAT modes.\r If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS.\r Note: Backup RAM cannot be preserved in Shutdown mode."
|
||||
@ -114,7 +114,7 @@ fieldset/BDCR1:
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
fieldset/BDCR2:
|
||||
description: "PWR Backup domain control register 2 "
|
||||
description: PWR Backup domain control register 2
|
||||
fields:
|
||||
- name: VBE
|
||||
description: VBAT charging enable
|
||||
@ -127,7 +127,7 @@ fieldset/BDCR2:
|
||||
bit_size: 1
|
||||
enum: VBRS
|
||||
fieldset/BDSR:
|
||||
description: "PWR Backup domain status register "
|
||||
description: PWR Backup domain status register
|
||||
fields:
|
||||
- name: VBATH
|
||||
description: Backup domain voltage level monitoring versus high threshold
|
||||
@ -145,7 +145,7 @@ fieldset/BDSR:
|
||||
bit_size: 1
|
||||
enum: TEMPH
|
||||
fieldset/CR1:
|
||||
description: "PWR control register 1 "
|
||||
description: PWR control register 1
|
||||
fields:
|
||||
- name: LPMS
|
||||
description: "Low-power mode selection\r These bits select the low-power mode entered when the CPU enters the Deepsleep mode.\r 10x: Standby mode (Standby mode also entered if LPMS = 11X in CR1\r with BREN = 1 in BDCR1)\r 11x: Shutdown mode if BREN = 0 in BDCR1"
|
||||
@ -187,7 +187,7 @@ fieldset/CR1:
|
||||
bit_size: 1
|
||||
enum: SRAMPD
|
||||
fieldset/CR2:
|
||||
description: "PWR control register 2 "
|
||||
description: PWR control register 2
|
||||
fields:
|
||||
- name: SRAM1PDS1
|
||||
description: "SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
|
||||
@ -300,7 +300,7 @@ fieldset/CR2:
|
||||
bit_size: 1
|
||||
enum: SRDRUN
|
||||
fieldset/CR3:
|
||||
description: "PWR control register 3 "
|
||||
description: PWR control register 3
|
||||
fields:
|
||||
- name: REGSEL
|
||||
description: "Regulator selection\r Note: REGSEL is reserved and must be kept at reset value in packages without SMPS."
|
||||
@ -312,7 +312,7 @@ fieldset/CR3:
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
fieldset/DBPR:
|
||||
description: "PWR disable Backup domain register "
|
||||
description: PWR disable Backup domain register
|
||||
fields:
|
||||
- name: DBP
|
||||
description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers."
|
||||
@ -330,7 +330,7 @@ fieldset/PCR:
|
||||
len: 16
|
||||
stride: 1
|
||||
fieldset/PRIVCFGR:
|
||||
description: "PWR privilege control register "
|
||||
description: PWR privilege control register
|
||||
fields:
|
||||
- name: SPRIV
|
||||
description: "PWR secure functions privilege configuration\r This bit is set and reset by software. It can be written only by a secure privileged access."
|
||||
@ -343,7 +343,7 @@ fieldset/PRIVCFGR:
|
||||
bit_size: 1
|
||||
enum: NSPRIV
|
||||
fieldset/SECCFGR:
|
||||
description: "PWR security configuration register "
|
||||
description: PWR security configuration register
|
||||
fields:
|
||||
- name: WUP1SEC
|
||||
description: WUP1 secure protection
|
||||
@ -406,7 +406,7 @@ fieldset/SECCFGR:
|
||||
bit_size: 1
|
||||
enum: APCSEC
|
||||
fieldset/SR:
|
||||
description: "PWR status register "
|
||||
description: PWR status register
|
||||
fields:
|
||||
- name: CSSF
|
||||
description: "Clear Stop and Standby flags\r This bit is protected against non-secure access when LPMSEC = 1 in SECCFGR.\r This bit is protected against unprivileged access when LPMSEC = 1 and SPRIV = 1 in PRIVCFGR, or when LPMSEC = 0 and NSPRIV = 1.\r Writing 1 to this bit clears the STOPF and SBF flags."
|
||||
@ -423,7 +423,7 @@ fieldset/SR:
|
||||
bit_size: 1
|
||||
enum: SBF
|
||||
fieldset/SVMCR:
|
||||
description: "PWR supply voltage monitoring control register "
|
||||
description: PWR supply voltage monitoring control register
|
||||
fields:
|
||||
- name: PVDE
|
||||
description: Power voltage detector enable
|
||||
@ -509,7 +509,7 @@ fieldset/SVMSR:
|
||||
bit_size: 1
|
||||
enum: VDDARDY
|
||||
fieldset/UCPDR:
|
||||
description: "PWR USB Type-C™ and Power Delivery register "
|
||||
description: PWR USB Type-C™ and Power Delivery register
|
||||
fields:
|
||||
- name: UCPD_DBDIS
|
||||
description: "UCPD dead battery disable\r After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable)."
|
||||
@ -521,7 +521,7 @@ fieldset/UCPDR:
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
fieldset/VOSR:
|
||||
description: "PWR voltage scaling register "
|
||||
description: PWR voltage scaling register
|
||||
fields:
|
||||
- name: BOOSTRDY
|
||||
description: "EPOD booster ready\r This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set."
|
||||
@ -543,7 +543,7 @@ fieldset/VOSR:
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/WUCR1:
|
||||
description: "PWR wakeup control register 1 "
|
||||
description: PWR wakeup control register 1
|
||||
fields:
|
||||
- name: WUPEN1
|
||||
description: Wakeup pin WKUP1 enable
|
||||
@ -578,7 +578,7 @@ fieldset/WUCR1:
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
fieldset/WUCR2:
|
||||
description: "PWR wakeup control register 2 "
|
||||
description: PWR wakeup control register 2
|
||||
fields:
|
||||
- name: WUPP1
|
||||
description: "Wakeup pin WKUP1 polarity.\r This bit must be configured when WUPEN1 = 0."
|
||||
@ -621,7 +621,7 @@ fieldset/WUCR2:
|
||||
bit_size: 1
|
||||
enum: WUPP
|
||||
fieldset/WUCR3:
|
||||
description: "PWR wakeup control register 3 "
|
||||
description: PWR wakeup control register 3
|
||||
fields:
|
||||
- name: WUSEL1
|
||||
description: "Wakeup pin WKUP1 selection\r This field must be configured when WUPEN1 = 0."
|
||||
@ -664,7 +664,7 @@ fieldset/WUCR3:
|
||||
bit_size: 2
|
||||
enum: WUSEL
|
||||
fieldset/WUSCR:
|
||||
description: "PWR wakeup status clear register "
|
||||
description: PWR wakeup status clear register
|
||||
fields:
|
||||
- name: CWUF1
|
||||
description: "Wakeup flag 1\r Writing 1 to this bit clears the WUF1 flag in WUSR."
|
||||
@ -699,7 +699,7 @@ fieldset/WUSCR:
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
fieldset/WUSR:
|
||||
description: "PWR wakeup status register "
|
||||
description: PWR wakeup status register
|
||||
fields:
|
||||
- name: WUF1
|
||||
description: "Wakeup flag 1\r This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1 = 0."
|
||||
@ -755,7 +755,7 @@ enum/ACTVOSRDY:
|
||||
description: "VCORE is above or below the current voltage scaling provided by ACTVOS[1:0]."
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "VCORE is equal to the current voltage scaling provided by ACTVOS[1:0] "
|
||||
description: "VCORE is equal to the current voltage scaling provided by ACTVOS[1:0]"
|
||||
value: 1
|
||||
enum/APCSEC:
|
||||
bit_size: 1
|
||||
@ -902,25 +902,25 @@ enum/PVDLS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "VPVD0 around 2.0 V "
|
||||
description: VPVD0 around 2.0 V
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "VPVD1 around 2.2 V "
|
||||
description: VPVD1 around 2.2 V
|
||||
value: 1
|
||||
- name: B_0x2
|
||||
description: "VPVD2 around 2.4 V "
|
||||
description: VPVD2 around 2.4 V
|
||||
value: 2
|
||||
- name: B_0x3
|
||||
description: "VPVD3 around 2.5 V "
|
||||
description: VPVD3 around 2.5 V
|
||||
value: 3
|
||||
- name: B_0x4
|
||||
description: "VPVD4 around 2.6 V "
|
||||
description: VPVD4 around 2.6 V
|
||||
value: 4
|
||||
- name: B_0x5
|
||||
description: "VPVD5 around 2.8 V "
|
||||
description: VPVD5 around 2.8 V
|
||||
value: 5
|
||||
- name: B_0x6
|
||||
description: "VPVD6 around 2.9 V "
|
||||
description: VPVD6 around 2.9 V
|
||||
value: 6
|
||||
- name: B_0x7
|
||||
description: External input analog voltage PVD_IN (compared internally to VREFINT)
|
||||
@ -932,7 +932,7 @@ enum/PVDO:
|
||||
description: "VDD is equal or above the PVD threshold selected by PVDLS[2:0]."
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "VDD is below the PVD threshold selected by PVDLS[2:0]. "
|
||||
description: "VDD is below the PVD threshold selected by PVDLS[2:0]."
|
||||
value: 1
|
||||
enum/REGS:
|
||||
bit_size: 1
|
||||
@ -983,10 +983,10 @@ enum/SRAMFWU:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "SRAM4 enters low-power mode in Stop 0, 1 and 2 modes (source biasing for lower-power consumption). "
|
||||
description: "SRAM4 enters low-power mode in Stop 0, 1 and 2 modes (source biasing for lower-power consumption)."
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "SRAM4 remains in normal mode in Stop 0, 1 and 2 modes (higher consumption but no SRAM4 wakeup time). "
|
||||
description: "SRAM4 remains in normal mode in Stop 0, 1 and 2 modes (higher consumption but no SRAM4 wakeup time)."
|
||||
value: 1
|
||||
enum/SRAMPD:
|
||||
bit_size: 1
|
||||
@ -1067,7 +1067,7 @@ enum/VBATH:
|
||||
description: Backup domain voltage level < high threshold
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "Backup domain voltage level ≥ high threshold "
|
||||
description: Backup domain voltage level ≥ high threshold
|
||||
value: 1
|
||||
enum/VBE:
|
||||
bit_size: 1
|
||||
@ -1100,10 +1100,10 @@ enum/VDDARDY:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "VDDA is below the threshold of the VDDA voltage monitor 2 (around 1.8 V). "
|
||||
description: VDDA is below the threshold of the VDDA voltage monitor 2 (around 1.8 V).
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "VDDA is equal or above the threshold of the VDDA voltage monitor 2 (around 1.8 V). "
|
||||
description: VDDA is equal or above the threshold of the VDDA voltage monitor 2 (around 1.8 V).
|
||||
value: 1
|
||||
enum/VDDIORDY:
|
||||
bit_size: 1
|
||||
|
||||
@ -42,14 +42,6 @@ block/RCC:
|
||||
description: Control/status register (RCC_CSR)
|
||||
byte_offset: 36
|
||||
fieldset: CSR
|
||||
- name: AHBRSTR
|
||||
description: AHB peripheral clock reset register (RCC_AHBRSTR)
|
||||
byte_offset: 40
|
||||
fieldset: AHBRSTR
|
||||
- name: CFGR2
|
||||
description: Clock configuration register 2
|
||||
byte_offset: 44
|
||||
fieldset: CFGR2
|
||||
fieldset/AHBENR:
|
||||
description: AHB Peripheral Clock enable register (RCC_AHBENR)
|
||||
fields:
|
||||
@ -81,33 +73,6 @@ fieldset/AHBENR:
|
||||
description: SDIO clock enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: USB_OTG_FSEN
|
||||
description: USB OTG FS clock enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: ETHMACEN
|
||||
description: Ethernet MAC clock enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: ETHMACTXEN
|
||||
description: Ethernet MAC TX clock enable
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: ETHMACRXEN
|
||||
description: Ethernet MAC RX clock enable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
fieldset/AHBRSTR:
|
||||
description: AHB peripheral clock reset register (RCC_AHBRSTR)
|
||||
fields:
|
||||
- name: USB_OTG_FSRST
|
||||
description: USB OTG FS reset
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: ETHMACRST
|
||||
description: Ethernet MAC reset
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
fieldset/APB1ENR:
|
||||
description: APB1 peripheral clock enable register (RCC_APB1ENR)
|
||||
fields:
|
||||
@ -187,18 +152,10 @@ fieldset/APB1ENR:
|
||||
description: USB clock enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: CAN1EN
|
||||
description: CAN1 clock enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: CANEN
|
||||
description: CAN clock enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: CAN2EN
|
||||
description: CAN2 clock enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: BKPEN
|
||||
description: Backup interface clock enable
|
||||
bit_offset: 27
|
||||
@ -211,10 +168,6 @@ fieldset/APB1ENR:
|
||||
description: DAC interface clock enable
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: CECEN
|
||||
description: CEC clock enable
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
fieldset/APB1RSTR:
|
||||
description: APB1 peripheral reset register (RCC_APB1RSTR)
|
||||
fields:
|
||||
@ -294,18 +247,10 @@ fieldset/APB1RSTR:
|
||||
description: USB reset
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: CAN1RST
|
||||
description: CAN1 reset
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: CANRST
|
||||
description: CAN reset
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: CAN2RST
|
||||
description: CAN2 reset
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: BKPRST
|
||||
description: Backup interface reset
|
||||
bit_offset: 27
|
||||
@ -318,10 +263,6 @@ fieldset/APB1RSTR:
|
||||
description: DAC interface reset
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: CECRST
|
||||
description: CEC reset
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
fieldset/APB2ENR:
|
||||
description: APB2 peripheral clock enable register (RCC_APB2ENR)
|
||||
fields:
|
||||
@ -385,18 +326,6 @@ fieldset/APB2ENR:
|
||||
description: ADC3 interface clock enable
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: TIM15EN
|
||||
description: TIM15 Timer clock enable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16EN
|
||||
description: TIM16 Timer clock enable
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17EN
|
||||
description: TIM17 Timer clock enable
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM9EN
|
||||
description: TIM9 Timer clock enable
|
||||
bit_offset: 19
|
||||
@ -472,18 +401,6 @@ fieldset/APB2RSTR:
|
||||
description: ADC 3 interface reset
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: TIM15RST
|
||||
description: TIM15 timer reset
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16RST
|
||||
description: TIM16 timer reset
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17RST
|
||||
description: TIM17 timer reset
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM9RST
|
||||
description: TIM9 timer reset
|
||||
bit_offset: 19
|
||||
@ -572,11 +489,6 @@ fieldset/CFGR:
|
||||
bit_offset: 18
|
||||
bit_size: 4
|
||||
enum: PLLMUL
|
||||
- name: OTGFSPRE
|
||||
description: USB OTG FS prescaler
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
enum: OTGFSPRE
|
||||
- name: USBPRE
|
||||
description: USB prescaler
|
||||
bit_offset: 22
|
||||
@ -587,44 +499,6 @@ fieldset/CFGR:
|
||||
bit_offset: 24
|
||||
bit_size: 3
|
||||
enum: MCO
|
||||
fieldset/CFGR2:
|
||||
description: Clock configuration register2 (RCC_CFGR2)
|
||||
fields:
|
||||
- name: PREDIV1
|
||||
description: PREDIV1 division factor
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
enum: PREDIV1
|
||||
- name: PREDIV2
|
||||
description: PREDIV2 division factor
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
enum: PREDIV1
|
||||
- name: PLL2MUL
|
||||
description: PLL2 Multiplication Factor
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
enum: PLL2MUL
|
||||
- name: PLL3MUL
|
||||
description: PLL3 Multiplication Factor
|
||||
bit_offset: 12
|
||||
bit_size: 4
|
||||
enum: PLL2MUL
|
||||
- name: PREDIV1SRC
|
||||
description: PREDIV1 entry clock source
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
enum: PREDIV1SRC
|
||||
- name: I2S2SRC
|
||||
description: I2S2 clock source
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
enum: I2S2SRC
|
||||
- name: I2S3SRC
|
||||
description: I2S3 clock source
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
enum: I2S2SRC
|
||||
fieldset/CIR:
|
||||
description: Clock interrupt register (RCC_CIR)
|
||||
fields:
|
||||
@ -648,14 +522,6 @@ fieldset/CIR:
|
||||
description: PLL Ready Interrupt flag
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PLL2RDYF
|
||||
description: PLL2 Ready Interrupt flag
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: PLL3RDYF
|
||||
description: PLL3 Ready Interrupt flag
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: CSSF
|
||||
description: Clock Security System Interrupt flag
|
||||
bit_offset: 7
|
||||
@ -680,14 +546,6 @@ fieldset/CIR:
|
||||
description: PLL Ready Interrupt Enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: PLL2RDYIE
|
||||
description: PLL2 Ready Interrupt Enable
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: PLL3RDYIE
|
||||
description: PLL3 Ready Interrupt Enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: LSIRDYC
|
||||
description: LSI Ready Interrupt Clear
|
||||
bit_offset: 16
|
||||
@ -708,14 +566,6 @@ fieldset/CIR:
|
||||
description: PLL Ready Interrupt Clear
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: PLL2RDYC
|
||||
description: PLL2 Ready Interrupt Clear
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: PLL3RDYC
|
||||
description: PLL3 Ready Interrupt Clear
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: CSSC
|
||||
description: Clock security system interrupt clear
|
||||
bit_offset: 23
|
||||
@ -763,22 +613,6 @@ fieldset/CR:
|
||||
description: PLL clock ready flag
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: PLL2ON
|
||||
description: PLL2 enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: PLL2RDY
|
||||
description: PLL2 clock ready flag
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: PLL3ON
|
||||
description: PLL3 enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: PLL3RDY
|
||||
description: PLL3 clock ready flag
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
fieldset/CSR:
|
||||
description: Control/status register (RCC_CSR)
|
||||
fields:
|
||||
@ -828,10 +662,10 @@ enum/ADCPRE:
|
||||
description: PCLK2 divided by 4
|
||||
value: 1
|
||||
- name: Div6
|
||||
description: PCLK2 divided by 8
|
||||
description: PCLK2 divided by 6
|
||||
value: 2
|
||||
- name: Div8
|
||||
description: PCLK2 divided by 16
|
||||
description: PCLK2 divided by 8
|
||||
value: 3
|
||||
enum/HPRE:
|
||||
bit_size: 4
|
||||
@ -863,17 +697,8 @@ enum/HPRE:
|
||||
- name: Div512
|
||||
description: SYSCLK divided by 512
|
||||
value: 15
|
||||
enum/I2S2SRC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: SYSCLK
|
||||
description: System clock (SYSCLK) selected as I2S clock entry
|
||||
value: 0
|
||||
- name: PLL3
|
||||
description: PLL3 VCO clock selected as I2S clock entry
|
||||
value: 1
|
||||
enum/MCO:
|
||||
bit_size: 4
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: NoMCO
|
||||
description: "MCO output disabled, no clock on MCO"
|
||||
@ -888,47 +713,8 @@ enum/MCO:
|
||||
description: HSE oscillator clock selected
|
||||
value: 6
|
||||
- name: PLL
|
||||
description: "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)"
|
||||
description: PLL clock divided by 2 selected
|
||||
value: 7
|
||||
enum/OTGFSPRE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: DIV1_5
|
||||
description: PLL clock is divided by 1.5
|
||||
value: 0
|
||||
- name: DIV1
|
||||
description: PLL clock is not divided
|
||||
value: 1
|
||||
enum/PLL2MUL:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Mul8
|
||||
description: PLL clock entry x8
|
||||
value: 6
|
||||
- name: Mul9
|
||||
description: PLL clock entry x9
|
||||
value: 7
|
||||
- name: Mul10
|
||||
description: PLL clock entry x10
|
||||
value: 8
|
||||
- name: Mul11
|
||||
description: PLL clock entry x11
|
||||
value: 9
|
||||
- name: Mul12
|
||||
description: PLL clock entry x12
|
||||
value: 10
|
||||
- name: Mul13
|
||||
description: PLL clock entry x13
|
||||
value: 11
|
||||
- name: Mul14
|
||||
description: PLL clock entry x14
|
||||
value: 12
|
||||
- name: Mul16
|
||||
description: PLL clock entry x16
|
||||
value: 14
|
||||
- name: Mul20
|
||||
description: PLL clock entry x20
|
||||
value: 15
|
||||
enum/PLLMUL:
|
||||
bit_size: 4
|
||||
variants:
|
||||
@ -1016,66 +802,6 @@ enum/PPRE1:
|
||||
- name: Div16
|
||||
description: HCLK divided by 16
|
||||
value: 7
|
||||
enum/PREDIV1:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Div1
|
||||
description: PREDIV input clock not divided
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: PREDIV input clock divided by 2
|
||||
value: 1
|
||||
- name: Div3
|
||||
description: PREDIV input clock divided by 3
|
||||
value: 2
|
||||
- name: Div4
|
||||
description: PREDIV input clock divided by 4
|
||||
value: 3
|
||||
- name: Div5
|
||||
description: PREDIV input clock divided by 5
|
||||
value: 4
|
||||
- name: Div6
|
||||
description: PREDIV input clock divided by 6
|
||||
value: 5
|
||||
- name: Div7
|
||||
description: PREDIV input clock divided by 7
|
||||
value: 6
|
||||
- name: Div8
|
||||
description: PREDIV input clock divided by 8
|
||||
value: 7
|
||||
- name: Div9
|
||||
description: PREDIV input clock divided by 9
|
||||
value: 8
|
||||
- name: Div10
|
||||
description: PREDIV input clock divided by 10
|
||||
value: 9
|
||||
- name: Div11
|
||||
description: PREDIV input clock divided by 11
|
||||
value: 10
|
||||
- name: Div12
|
||||
description: PREDIV input clock divided by 12
|
||||
value: 11
|
||||
- name: Div13
|
||||
description: PREDIV input clock divided by 13
|
||||
value: 12
|
||||
- name: Div14
|
||||
description: PREDIV input clock divided by 14
|
||||
value: 13
|
||||
- name: Div15
|
||||
description: PREDIV input clock divided by 15
|
||||
value: 14
|
||||
- name: Div16
|
||||
description: PREDIV input clock divided by 16
|
||||
value: 15
|
||||
enum/PREDIV1SRC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: HSE
|
||||
description: HSE oscillator clock selected as PREDIV1 clock entry
|
||||
value: 0
|
||||
- name: PLL2
|
||||
description: PLL2 selected as PREDIV1 clock entry
|
||||
value: 1
|
||||
enum/RTCSEL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
|
||||
865
data/registers/rcc_f100.yaml
Normal file
865
data/registers/rcc_f100.yaml
Normal file
@ -0,0 +1,865 @@
|
||||
---
|
||||
block/RCC:
|
||||
description: Reset and clock control
|
||||
items:
|
||||
- name: CR
|
||||
description: Clock control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: CFGR
|
||||
description: Clock configuration register (RCC_CFGR)
|
||||
byte_offset: 4
|
||||
fieldset: CFGR
|
||||
- name: CIR
|
||||
description: Clock interrupt register (RCC_CIR)
|
||||
byte_offset: 8
|
||||
fieldset: CIR
|
||||
- name: APB2RSTR
|
||||
description: APB2 peripheral reset register (RCC_APB2RSTR)
|
||||
byte_offset: 12
|
||||
fieldset: APB2RSTR
|
||||
- name: APB1RSTR
|
||||
description: APB1 peripheral reset register (RCC_APB1RSTR)
|
||||
byte_offset: 16
|
||||
fieldset: APB1RSTR
|
||||
- name: AHBENR
|
||||
description: AHB Peripheral Clock enable register (RCC_AHBENR)
|
||||
byte_offset: 20
|
||||
fieldset: AHBENR
|
||||
- name: APB2ENR
|
||||
description: APB2 peripheral clock enable register (RCC_APB2ENR)
|
||||
byte_offset: 24
|
||||
fieldset: APB2ENR
|
||||
- name: APB1ENR
|
||||
description: APB1 peripheral clock enable register (RCC_APB1ENR)
|
||||
byte_offset: 28
|
||||
fieldset: APB1ENR
|
||||
- name: BDCR
|
||||
description: Backup domain control register (RCC_BDCR)
|
||||
byte_offset: 32
|
||||
fieldset: BDCR
|
||||
- name: CSR
|
||||
description: Control/status register (RCC_CSR)
|
||||
byte_offset: 36
|
||||
fieldset: CSR
|
||||
- name: CFGR2
|
||||
description: Clock configuration register 2
|
||||
byte_offset: 44
|
||||
fieldset: CFGR2
|
||||
fieldset/AHBENR:
|
||||
description: AHB Peripheral Clock enable register (RCC_AHBENR)
|
||||
fields:
|
||||
- name: DMA1EN
|
||||
description: DMA1 clock enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DMA2EN
|
||||
description: DMA2 clock enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: SRAMEN
|
||||
description: SRAM interface clock enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: FLASHEN
|
||||
description: FLASH clock enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: CRCEN
|
||||
description: CRC clock enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: FSMCEN
|
||||
description: FSMC clock enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
fieldset/APB1ENR:
|
||||
description: APB1 peripheral clock enable register (RCC_APB1ENR)
|
||||
fields:
|
||||
- name: TIM2EN
|
||||
description: Timer 2 clock enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3EN
|
||||
description: Timer 3 clock enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4EN
|
||||
description: Timer 4 clock enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5EN
|
||||
description: Timer 5 clock enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6EN
|
||||
description: Timer 6 clock enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7EN
|
||||
description: Timer 7 clock enable
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM12EN
|
||||
description: Timer 12 clock enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM13EN
|
||||
description: Timer 13 clock enable
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM14EN
|
||||
description: Timer 14 clock enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: WWDGEN
|
||||
description: Window watchdog clock enable
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: SPI2EN
|
||||
description: SPI 2 clock enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: SPI3EN
|
||||
description: SPI 3 clock enable
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: USART2EN
|
||||
description: USART 2 clock enable
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: USART3EN
|
||||
description: USART 3 clock enable
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: UART4EN
|
||||
description: UART 4 clock enable
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: UART5EN
|
||||
description: UART 5 clock enable
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: I2C1EN
|
||||
description: I2C 1 clock enable
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2EN
|
||||
description: I2C 2 clock enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: BKPEN
|
||||
description: Backup interface clock enable
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: PWREN
|
||||
description: Power interface clock enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: DACEN
|
||||
description: DAC interface clock enable
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: CECEN
|
||||
description: CEC clock enable
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
fieldset/APB1RSTR:
|
||||
description: APB1 peripheral reset register (RCC_APB1RSTR)
|
||||
fields:
|
||||
- name: TIM2RST
|
||||
description: Timer 2 reset
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3RST
|
||||
description: Timer 3 reset
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4RST
|
||||
description: Timer 4 reset
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5RST
|
||||
description: Timer 5 reset
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6RST
|
||||
description: Timer 6 reset
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7RST
|
||||
description: Timer 7 reset
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM12RST
|
||||
description: Timer 12 reset
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM13RST
|
||||
description: Timer 13 reset
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM14RST
|
||||
description: Timer 14 reset
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: WWDGRST
|
||||
description: Window watchdog reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: SPI2RST
|
||||
description: SPI2 reset
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: SPI3RST
|
||||
description: SPI3 reset
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: USART2RST
|
||||
description: USART 2 reset
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: USART3RST
|
||||
description: USART 3 reset
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: UART4RST
|
||||
description: USART 4 reset
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: UART5RST
|
||||
description: USART 5 reset
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: I2C1RST
|
||||
description: I2C1 reset
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2RST
|
||||
description: I2C2 reset
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: BKPRST
|
||||
description: Backup interface reset
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: PWRRST
|
||||
description: Power interface reset
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: DACRST
|
||||
description: DAC interface reset
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: CECRST
|
||||
description: CEC reset
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
fieldset/APB2ENR:
|
||||
description: APB2 peripheral clock enable register (RCC_APB2ENR)
|
||||
fields:
|
||||
- name: AFIOEN
|
||||
description: Alternate function I/O clock enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: GPIOAEN
|
||||
description: I/O port A clock enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: GPIOBEN
|
||||
description: I/O port B clock enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: GPIOCEN
|
||||
description: I/O port C clock enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: GPIODEN
|
||||
description: I/O port D clock enable
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: GPIOEEN
|
||||
description: I/O port E clock enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: GPIOFEN
|
||||
description: I/O port F clock enable
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: GPIOGEN
|
||||
description: I/O port G clock enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ADC1EN
|
||||
description: ADC 1 interface clock enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: TIM1EN
|
||||
description: TIM1 Timer clock enable
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: SPI1EN
|
||||
description: SPI 1 clock enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: USART1EN
|
||||
description: USART1 clock enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: TIM15EN
|
||||
description: TIM15 Timer clock enable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16EN
|
||||
description: TIM16 Timer clock enable
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17EN
|
||||
description: TIM17 Timer clock enable
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/APB2RSTR:
|
||||
description: APB2 peripheral reset register (RCC_APB2RSTR)
|
||||
fields:
|
||||
- name: AFIORST
|
||||
description: Alternate function I/O reset
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: GPIOARST
|
||||
description: IO port A reset
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: GPIOBRST
|
||||
description: IO port B reset
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: GPIOCRST
|
||||
description: IO port C reset
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: GPIODRST
|
||||
description: IO port D reset
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: GPIOERST
|
||||
description: IO port E reset
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: GPIOFRST
|
||||
description: IO port F reset
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: GPIOGRST
|
||||
description: IO port G reset
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ADC1RST
|
||||
description: ADC 1 interface reset
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: TIM1RST
|
||||
description: TIM1 timer reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: SPI1RST
|
||||
description: SPI 1 reset
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: USART1RST
|
||||
description: USART1 reset
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: TIM15RST
|
||||
description: TIM15 timer reset
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16RST
|
||||
description: TIM16 timer reset
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17RST
|
||||
description: TIM17 timer reset
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/BDCR:
|
||||
description: Backup domain control register (RCC_BDCR)
|
||||
fields:
|
||||
- name: LSEON
|
||||
description: External Low Speed oscillator enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: LSERDY
|
||||
description: External Low Speed oscillator ready
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: LSEBYP
|
||||
description: External Low Speed oscillator bypass
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: RTCSEL
|
||||
description: RTC clock source selection
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
enum: RTCSEL
|
||||
- name: RTCEN
|
||||
description: RTC clock enable
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: BDRST
|
||||
description: Backup domain software reset
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
fieldset/CFGR:
|
||||
description: Clock configuration register (RCC_CFGR)
|
||||
fields:
|
||||
- name: SW
|
||||
description: System clock Switch
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
enum: SW
|
||||
- name: SWS
|
||||
description: System Clock Switch Status
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
enum_read: SWSR
|
||||
- name: HPRE
|
||||
description: AHB prescaler
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
enum: HPRE
|
||||
- name: PPRE1
|
||||
description: APB Low speed prescaler (APB1)
|
||||
bit_offset: 8
|
||||
bit_size: 3
|
||||
enum: PPRE1
|
||||
- name: PPRE2
|
||||
description: APB High speed prescaler (APB2)
|
||||
bit_offset: 11
|
||||
bit_size: 3
|
||||
enum: PPRE1
|
||||
- name: ADCPRE
|
||||
description: ADC prescaler
|
||||
bit_offset: 14
|
||||
bit_size: 2
|
||||
enum: ADCPRE
|
||||
- name: PLLSRC
|
||||
description: PLL entry clock source
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
enum: PLLSRC
|
||||
- name: PLLXTPRE
|
||||
description: HSE divider for PLL entry
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
enum: PLLXTPRE
|
||||
- name: PLLMUL
|
||||
description: PLL Multiplication Factor
|
||||
bit_offset: 18
|
||||
bit_size: 4
|
||||
enum: PLLMUL
|
||||
- name: MCO
|
||||
description: Microcontroller clock output
|
||||
bit_offset: 24
|
||||
bit_size: 3
|
||||
enum: MCO
|
||||
fieldset/CFGR2:
|
||||
description: Clock configuration register 2
|
||||
fields:
|
||||
- name: PREDIV1
|
||||
description: PREDIV1 division factor
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
enum: PREDIV1
|
||||
fieldset/CIR:
|
||||
description: Clock interrupt register (RCC_CIR)
|
||||
fields:
|
||||
- name: LSIRDYF
|
||||
description: LSI Ready Interrupt flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: LSERDYF
|
||||
description: LSE Ready Interrupt flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: HSIRDYF
|
||||
description: HSI Ready Interrupt flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: HSERDYF
|
||||
description: HSE Ready Interrupt flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: PLLRDYF
|
||||
description: PLL Ready Interrupt flag
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: CSSF
|
||||
description: Clock Security System Interrupt flag
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: LSIRDYIE
|
||||
description: LSI Ready Interrupt Enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: LSERDYIE
|
||||
description: LSE Ready Interrupt Enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: HSIRDYIE
|
||||
description: HSI Ready Interrupt Enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: HSERDYIE
|
||||
description: HSE Ready Interrupt Enable
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: PLLRDYIE
|
||||
description: PLL Ready Interrupt Enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: LSIRDYC
|
||||
description: LSI Ready Interrupt Clear
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: LSERDYC
|
||||
description: LSE Ready Interrupt Clear
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: HSIRDYC
|
||||
description: HSI Ready Interrupt Clear
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: HSERDYC
|
||||
description: HSE Ready Interrupt Clear
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: PLLRDYC
|
||||
description: PLL Ready Interrupt Clear
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: CSSC
|
||||
description: Clock security system interrupt clear
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Clock control register
|
||||
fields:
|
||||
- name: HSION
|
||||
description: Internal High Speed clock enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: HSIRDY
|
||||
description: Internal High Speed clock ready flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: HSITRIM
|
||||
description: Internal High Speed clock trimming
|
||||
bit_offset: 3
|
||||
bit_size: 5
|
||||
- name: HSICAL
|
||||
description: Internal High Speed clock Calibration
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: HSEON
|
||||
description: External High Speed clock enable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: HSERDY
|
||||
description: External High Speed clock ready flag
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: HSEBYP
|
||||
description: External High Speed clock Bypass
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: CSSON
|
||||
description: Clock Security System enable
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: PLLON
|
||||
description: PLL enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: PLLRDY
|
||||
description: PLL clock ready flag
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
fieldset/CSR:
|
||||
description: Control/status register (RCC_CSR)
|
||||
fields:
|
||||
- name: LSION
|
||||
description: Internal low speed oscillator enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: LSIRDY
|
||||
description: Internal low speed oscillator ready
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: RMVF
|
||||
description: Remove reset flag
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: PINRSTF
|
||||
description: PIN reset flag
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: PORRSTF
|
||||
description: POR/PDR reset flag
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: SFTRSTF
|
||||
description: Software reset flag
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: IWDGRSTF
|
||||
description: Independent watchdog reset flag
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: WWDGRSTF
|
||||
description: Window watchdog reset flag
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LPWRRSTF
|
||||
description: Low-power reset flag
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
enum/ADCPRE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Div2
|
||||
description: PCLK2 divided by 2
|
||||
value: 0
|
||||
- name: Div4
|
||||
description: PCLK2 divided by 4
|
||||
value: 1
|
||||
- name: Div6
|
||||
description: PCLK2 divided by 6
|
||||
value: 2
|
||||
- name: Div8
|
||||
description: PCLK2 divided by 8
|
||||
value: 3
|
||||
enum/HPRE:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Div1
|
||||
description: SYSCLK not divided
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: SYSCLK divided by 2
|
||||
value: 8
|
||||
- name: Div4
|
||||
description: SYSCLK divided by 4
|
||||
value: 9
|
||||
- name: Div8
|
||||
description: SYSCLK divided by 8
|
||||
value: 10
|
||||
- name: Div16
|
||||
description: SYSCLK divided by 16
|
||||
value: 11
|
||||
- name: Div64
|
||||
description: SYSCLK divided by 64
|
||||
value: 12
|
||||
- name: Div128
|
||||
description: SYSCLK divided by 128
|
||||
value: 13
|
||||
- name: Div256
|
||||
description: SYSCLK divided by 256
|
||||
value: 14
|
||||
- name: Div512
|
||||
description: SYSCLK divided by 512
|
||||
value: 15
|
||||
enum/MCO:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: NoMCO
|
||||
description: "MCO output disabled, no clock on MCO"
|
||||
value: 0
|
||||
- name: SYSCLK
|
||||
description: System clock selected
|
||||
value: 4
|
||||
- name: HSI
|
||||
description: HSI oscillator clock selected
|
||||
value: 5
|
||||
- name: HSE
|
||||
description: HSE oscillator clock selected
|
||||
value: 6
|
||||
- name: PLL
|
||||
description: PLL clock divided by 2 selected
|
||||
value: 7
|
||||
enum/PLLMUL:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Mul2
|
||||
description: PLL input clock x2
|
||||
value: 0
|
||||
- name: Mul3
|
||||
description: PLL input clock x3
|
||||
value: 1
|
||||
- name: Mul4
|
||||
description: PLL input clock x4
|
||||
value: 2
|
||||
- name: Mul5
|
||||
description: PLL input clock x5
|
||||
value: 3
|
||||
- name: Mul6
|
||||
description: PLL input clock x6
|
||||
value: 4
|
||||
- name: Mul7
|
||||
description: PLL input clock x7
|
||||
value: 5
|
||||
- name: Mul8
|
||||
description: PLL input clock x8
|
||||
value: 6
|
||||
- name: Mul9
|
||||
description: PLL input clock x9
|
||||
value: 7
|
||||
- name: Mul10
|
||||
description: PLL input clock x10
|
||||
value: 8
|
||||
- name: Mul11
|
||||
description: PLL input clock x11
|
||||
value: 9
|
||||
- name: Mul12
|
||||
description: PLL input clock x12
|
||||
value: 10
|
||||
- name: Mul13
|
||||
description: PLL input clock x13
|
||||
value: 11
|
||||
- name: Mul14
|
||||
description: PLL input clock x14
|
||||
value: 12
|
||||
- name: Mul15
|
||||
description: PLL input clock x15
|
||||
value: 13
|
||||
- name: Mul16
|
||||
description: PLL input clock x16
|
||||
value: 14
|
||||
- name: Mul16x
|
||||
description: PLL input clock x16
|
||||
value: 15
|
||||
enum/PLLSRC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: HSI_Div2
|
||||
description: HSI divided by 2 selected as PLL input clock
|
||||
value: 0
|
||||
- name: HSE_Div_PREDIV
|
||||
description: HSE divided by PREDIV selected as PLL input clock
|
||||
value: 1
|
||||
enum/PLLXTPRE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Div1
|
||||
description: HSE clock not divided
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: HSE clock divided by 2
|
||||
value: 1
|
||||
enum/PPRE1:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Div1
|
||||
description: HCLK not divided
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: HCLK divided by 2
|
||||
value: 4
|
||||
- name: Div4
|
||||
description: HCLK divided by 4
|
||||
value: 5
|
||||
- name: Div8
|
||||
description: HCLK divided by 8
|
||||
value: 6
|
||||
- name: Div16
|
||||
description: HCLK divided by 16
|
||||
value: 7
|
||||
enum/PREDIV1:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Div1
|
||||
description: PREDIV input clock not divided
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: PREDIV input clock divided by 2
|
||||
value: 1
|
||||
- name: Div3
|
||||
description: PREDIV input clock divided by 3
|
||||
value: 2
|
||||
- name: Div4
|
||||
description: PREDIV input clock divided by 4
|
||||
value: 3
|
||||
- name: Div5
|
||||
description: PREDIV input clock divided by 5
|
||||
value: 4
|
||||
- name: Div6
|
||||
description: PREDIV input clock divided by 6
|
||||
value: 5
|
||||
- name: Div7
|
||||
description: PREDIV input clock divided by 7
|
||||
value: 6
|
||||
- name: Div8
|
||||
description: PREDIV input clock divided by 8
|
||||
value: 7
|
||||
- name: Div9
|
||||
description: PREDIV input clock divided by 9
|
||||
value: 8
|
||||
- name: Div10
|
||||
description: PREDIV input clock divided by 10
|
||||
value: 9
|
||||
- name: Div11
|
||||
description: PREDIV input clock divided by 11
|
||||
value: 10
|
||||
- name: Div12
|
||||
description: PREDIV input clock divided by 12
|
||||
value: 11
|
||||
- name: Div13
|
||||
description: PREDIV input clock divided by 13
|
||||
value: 12
|
||||
- name: Div14
|
||||
description: PREDIV input clock divided by 14
|
||||
value: 13
|
||||
- name: Div15
|
||||
description: PREDIV input clock divided by 15
|
||||
value: 14
|
||||
- name: Div16
|
||||
description: PREDIV input clock divided by 16
|
||||
value: 15
|
||||
enum/RTCSEL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: NoClock
|
||||
description: No clock
|
||||
value: 0
|
||||
- name: LSE
|
||||
description: LSE oscillator clock used as RTC clock
|
||||
value: 1
|
||||
- name: LSI
|
||||
description: LSI oscillator clock used as RTC clock
|
||||
value: 2
|
||||
- name: HSE
|
||||
description: HSE oscillator clock divided by a prescaler used as RTC clock
|
||||
value: 3
|
||||
enum/SW:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: HSI
|
||||
description: HSI selected as system clock
|
||||
value: 0
|
||||
- name: HSE
|
||||
description: HSE selected as system clock
|
||||
value: 1
|
||||
- name: PLL
|
||||
description: PLL selected as system clock
|
||||
value: 2
|
||||
enum/SWSR:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: HSI
|
||||
description: HSI oscillator used as system clock
|
||||
value: 0
|
||||
- name: HSE
|
||||
description: HSE oscillator used as system clock
|
||||
value: 1
|
||||
- name: PLL
|
||||
description: PLL used as system clock
|
||||
value: 2
|
||||
961
data/registers/rcc_f1cl.yaml
Normal file
961
data/registers/rcc_f1cl.yaml
Normal file
@ -0,0 +1,961 @@
|
||||
---
|
||||
block/RCC:
|
||||
description: Reset and clock control
|
||||
items:
|
||||
- name: CR
|
||||
description: Clock control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: CFGR
|
||||
description: Clock configuration register (RCC_CFGR)
|
||||
byte_offset: 4
|
||||
fieldset: CFGR
|
||||
- name: CIR
|
||||
description: Clock interrupt register (RCC_CIR)
|
||||
byte_offset: 8
|
||||
fieldset: CIR
|
||||
- name: APB2RSTR
|
||||
description: APB2 peripheral reset register (RCC_APB2RSTR)
|
||||
byte_offset: 12
|
||||
fieldset: APB2RSTR
|
||||
- name: APB1RSTR
|
||||
description: APB1 peripheral reset register (RCC_APB1RSTR)
|
||||
byte_offset: 16
|
||||
fieldset: APB1RSTR
|
||||
- name: AHBENR
|
||||
description: AHB Peripheral Clock enable register (RCC_AHBENR)
|
||||
byte_offset: 20
|
||||
fieldset: AHBENR
|
||||
- name: APB2ENR
|
||||
description: APB2 peripheral clock enable register (RCC_APB2ENR)
|
||||
byte_offset: 24
|
||||
fieldset: APB2ENR
|
||||
- name: APB1ENR
|
||||
description: APB1 peripheral clock enable register (RCC_APB1ENR)
|
||||
byte_offset: 28
|
||||
fieldset: APB1ENR
|
||||
- name: BDCR
|
||||
description: Backup domain control register (RCC_BDCR)
|
||||
byte_offset: 32
|
||||
fieldset: BDCR
|
||||
- name: CSR
|
||||
description: Control/status register (RCC_CSR)
|
||||
byte_offset: 36
|
||||
fieldset: CSR
|
||||
- name: AHBRSTR
|
||||
description: AHB peripheral clock reset register (RCC_AHBRSTR)
|
||||
byte_offset: 40
|
||||
fieldset: AHBRSTR
|
||||
- name: CFGR2
|
||||
description: Clock configuration register 2
|
||||
byte_offset: 44
|
||||
fieldset: CFGR2
|
||||
fieldset/AHBENR:
|
||||
description: AHB Peripheral Clock enable register (RCC_AHBENR)
|
||||
fields:
|
||||
- name: DMA1EN
|
||||
description: DMA1 clock enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DMA2EN
|
||||
description: DMA2 clock enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: SRAMEN
|
||||
description: SRAM interface clock enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: FLASHEN
|
||||
description: FLASH clock enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: CRCEN
|
||||
description: CRC clock enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: USB_OTG_FSEN
|
||||
description: USB OTG FS clock enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: ETHEN
|
||||
description: Ethernet MAC clock enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: ETHTXEN
|
||||
description: Ethernet MAC TX clock enable
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: ETHRXEN
|
||||
description: Ethernet MAC RX clock enable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
fieldset/AHBRSTR:
|
||||
description: AHB peripheral clock reset register (RCC_AHBRSTR)
|
||||
fields:
|
||||
- name: USB_OTG_FSRST
|
||||
description: USB OTG FS reset
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: ETHRST
|
||||
description: Ethernet MAC reset
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
fieldset/APB1ENR:
|
||||
description: APB1 peripheral clock enable register (RCC_APB1ENR)
|
||||
fields:
|
||||
- name: TIM2EN
|
||||
description: Timer 2 clock enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3EN
|
||||
description: Timer 3 clock enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4EN
|
||||
description: Timer 4 clock enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5EN
|
||||
description: Timer 5 clock enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6EN
|
||||
description: Timer 6 clock enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7EN
|
||||
description: Timer 7 clock enable
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: WWDGEN
|
||||
description: Window watchdog clock enable
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: SPI2EN
|
||||
description: SPI 2 clock enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: SPI3EN
|
||||
description: SPI 3 clock enable
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: USART2EN
|
||||
description: USART 2 clock enable
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: USART3EN
|
||||
description: USART 3 clock enable
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: UART4EN
|
||||
description: UART 4 clock enable
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: UART5EN
|
||||
description: UART 5 clock enable
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: I2C1EN
|
||||
description: I2C 1 clock enable
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2EN
|
||||
description: I2C 2 clock enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: CAN1EN
|
||||
description: CAN1 clock enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: CAN2EN
|
||||
description: CAN2 clock enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: BKPEN
|
||||
description: Backup interface clock enable
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: PWREN
|
||||
description: Power interface clock enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: DACEN
|
||||
description: DAC interface clock enable
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
fieldset/APB1RSTR:
|
||||
description: APB1 peripheral reset register (RCC_APB1RSTR)
|
||||
fields:
|
||||
- name: TIM2RST
|
||||
description: Timer 2 reset
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3RST
|
||||
description: Timer 3 reset
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4RST
|
||||
description: Timer 4 reset
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5RST
|
||||
description: Timer 5 reset
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6RST
|
||||
description: Timer 6 reset
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7RST
|
||||
description: Timer 7 reset
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: WWDGRST
|
||||
description: Window watchdog reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: SPI2RST
|
||||
description: SPI2 reset
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: SPI3RST
|
||||
description: SPI3 reset
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: USART2RST
|
||||
description: USART 2 reset
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: USART3RST
|
||||
description: USART 3 reset
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: UART4RST
|
||||
description: USART 4 reset
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: UART5RST
|
||||
description: USART 5 reset
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: I2C1RST
|
||||
description: I2C1 reset
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2RST
|
||||
description: I2C2 reset
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: CAN1RST
|
||||
description: CAN1 reset
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: CAN2RST
|
||||
description: CAN2 reset
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: BKPRST
|
||||
description: Backup interface reset
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: PWRRST
|
||||
description: Power interface reset
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: DACRST
|
||||
description: DAC interface reset
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
fieldset/APB2ENR:
|
||||
description: APB2 peripheral clock enable register (RCC_APB2ENR)
|
||||
fields:
|
||||
- name: AFIOEN
|
||||
description: Alternate function I/O clock enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: GPIOAEN
|
||||
description: I/O port A clock enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: GPIOBEN
|
||||
description: I/O port B clock enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: GPIOCEN
|
||||
description: I/O port C clock enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: GPIODEN
|
||||
description: I/O port D clock enable
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: GPIOEEN
|
||||
description: I/O port E clock enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: ADC1EN
|
||||
description: ADC 1 interface clock enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ADC2EN
|
||||
description: ADC 2 interface clock enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: TIM1EN
|
||||
description: TIM1 Timer clock enable
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: SPI1EN
|
||||
description: SPI 1 clock enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: USART1EN
|
||||
description: USART1 clock enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
fieldset/APB2RSTR:
|
||||
description: APB2 peripheral reset register (RCC_APB2RSTR)
|
||||
fields:
|
||||
- name: AFIORST
|
||||
description: Alternate function I/O reset
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: GPIOARST
|
||||
description: IO port A reset
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: GPIOBRST
|
||||
description: IO port B reset
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: GPIOCRST
|
||||
description: IO port C reset
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: GPIODRST
|
||||
description: IO port D reset
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: GPIOERST
|
||||
description: IO port E reset
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: ADC1RST
|
||||
description: ADC 1 interface reset
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: ADC2RST
|
||||
description: ADC 2 interface reset
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: TIM1RST
|
||||
description: TIM1 timer reset
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: SPI1RST
|
||||
description: SPI 1 reset
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: USART1RST
|
||||
description: USART1 reset
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
fieldset/BDCR:
|
||||
description: Backup domain control register (RCC_BDCR)
|
||||
fields:
|
||||
- name: LSEON
|
||||
description: External Low Speed oscillator enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: LSERDY
|
||||
description: External Low Speed oscillator ready
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: LSEBYP
|
||||
description: External Low Speed oscillator bypass
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: RTCSEL
|
||||
description: RTC clock source selection
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
enum: RTCSEL
|
||||
- name: RTCEN
|
||||
description: RTC clock enable
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: BDRST
|
||||
description: Backup domain software reset
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
fieldset/CFGR:
|
||||
description: Clock configuration register (RCC_CFGR)
|
||||
fields:
|
||||
- name: SW
|
||||
description: System clock Switch
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
enum: SW
|
||||
- name: SWS
|
||||
description: System Clock Switch Status
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
enum_read: SWSR
|
||||
- name: HPRE
|
||||
description: AHB prescaler
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
enum: HPRE
|
||||
- name: PPRE1
|
||||
description: APB Low speed prescaler (APB1)
|
||||
bit_offset: 8
|
||||
bit_size: 3
|
||||
enum: PPRE1
|
||||
- name: PPRE2
|
||||
description: APB High speed prescaler (APB2)
|
||||
bit_offset: 11
|
||||
bit_size: 3
|
||||
enum: PPRE1
|
||||
- name: ADCPRE
|
||||
description: ADC prescaler
|
||||
bit_offset: 14
|
||||
bit_size: 2
|
||||
enum: ADCPRE
|
||||
- name: PLLSRC
|
||||
description: PLL entry clock source
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
enum: PLLSRC
|
||||
- name: PLLXTPRE
|
||||
description: HSE divider for PLL entry
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
enum: PLLXTPRE
|
||||
- name: PLLMUL
|
||||
description: PLL Multiplication Factor
|
||||
bit_offset: 18
|
||||
bit_size: 4
|
||||
enum: PLLMUL
|
||||
- name: USBPRE
|
||||
description: USB prescaler
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
enum: USBPRE
|
||||
- name: MCO
|
||||
description: Microcontroller clock output
|
||||
bit_offset: 24
|
||||
bit_size: 4
|
||||
enum: MCO
|
||||
fieldset/CFGR2:
|
||||
description: Clock configuration register2 (RCC_CFGR2)
|
||||
fields:
|
||||
- name: PREDIV1
|
||||
description: PREDIV1 division factor
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
enum: PREDIV1
|
||||
- name: PREDIV2
|
||||
description: PREDIV2 division factor
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
enum: PREDIV1
|
||||
- name: PLL2MUL
|
||||
description: PLL2 Multiplication Factor
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
enum: PLL2MUL
|
||||
- name: PLL3MUL
|
||||
description: PLL3 Multiplication Factor
|
||||
bit_offset: 12
|
||||
bit_size: 4
|
||||
enum: PLL2MUL
|
||||
- name: PREDIV1SRC
|
||||
description: PREDIV1 entry clock source
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
enum: PREDIV1SRC
|
||||
- name: I2S2SRC
|
||||
description: I2S2 clock source
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
enum: I2S2SRC
|
||||
- name: I2S3SRC
|
||||
description: I2S3 clock source
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
enum: I2S2SRC
|
||||
fieldset/CIR:
|
||||
description: Clock interrupt register (RCC_CIR)
|
||||
fields:
|
||||
- name: LSIRDYF
|
||||
description: LSI Ready Interrupt flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: LSERDYF
|
||||
description: LSE Ready Interrupt flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: HSIRDYF
|
||||
description: HSI Ready Interrupt flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: HSERDYF
|
||||
description: HSE Ready Interrupt flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: PLLRDYF
|
||||
description: PLL Ready Interrupt flag
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PLL2RDYF
|
||||
description: PLL2 Ready Interrupt flag
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: PLL3RDYF
|
||||
description: PLL3 Ready Interrupt flag
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: CSSF
|
||||
description: Clock Security System Interrupt flag
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: LSIRDYIE
|
||||
description: LSI Ready Interrupt Enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: LSERDYIE
|
||||
description: LSE Ready Interrupt Enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: HSIRDYIE
|
||||
description: HSI Ready Interrupt Enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: HSERDYIE
|
||||
description: HSE Ready Interrupt Enable
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: PLLRDYIE
|
||||
description: PLL Ready Interrupt Enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: PLL2RDYIE
|
||||
description: PLL2 Ready Interrupt Enable
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: PLL3RDYIE
|
||||
description: PLL3 Ready Interrupt Enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: LSIRDYC
|
||||
description: LSI Ready Interrupt Clear
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: LSERDYC
|
||||
description: LSE Ready Interrupt Clear
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: HSIRDYC
|
||||
description: HSI Ready Interrupt Clear
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: HSERDYC
|
||||
description: HSE Ready Interrupt Clear
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: PLLRDYC
|
||||
description: PLL Ready Interrupt Clear
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: PLL2RDYC
|
||||
description: PLL2 Ready Interrupt Clear
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: PLL3RDYC
|
||||
description: PLL3 Ready Interrupt Clear
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: CSSC
|
||||
description: Clock security system interrupt clear
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Clock control register
|
||||
fields:
|
||||
- name: HSION
|
||||
description: Internal High Speed clock enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: HSIRDY
|
||||
description: Internal High Speed clock ready flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: HSITRIM
|
||||
description: Internal High Speed clock trimming
|
||||
bit_offset: 3
|
||||
bit_size: 5
|
||||
- name: HSICAL
|
||||
description: Internal High Speed clock Calibration
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: HSEON
|
||||
description: External High Speed clock enable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: HSERDY
|
||||
description: External High Speed clock ready flag
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: HSEBYP
|
||||
description: External High Speed clock Bypass
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: CSSON
|
||||
description: Clock Security System enable
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: PLLON
|
||||
description: PLL enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: PLLRDY
|
||||
description: PLL clock ready flag
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: PLL2ON
|
||||
description: PLL2 enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: PLL2RDY
|
||||
description: PLL2 clock ready flag
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: PLL3ON
|
||||
description: PLL3 enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: PLL3RDY
|
||||
description: PLL3 clock ready flag
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
fieldset/CSR:
|
||||
description: Control/status register (RCC_CSR)
|
||||
fields:
|
||||
- name: LSION
|
||||
description: Internal low speed oscillator enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: LSIRDY
|
||||
description: Internal low speed oscillator ready
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: RMVF
|
||||
description: Remove reset flag
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: PINRSTF
|
||||
description: PIN reset flag
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: PORRSTF
|
||||
description: POR/PDR reset flag
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: SFTRSTF
|
||||
description: Software reset flag
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: IWDGRSTF
|
||||
description: Independent watchdog reset flag
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: WWDGRSTF
|
||||
description: Window watchdog reset flag
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LPWRRSTF
|
||||
description: Low-power reset flag
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
enum/ADCPRE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Div2
|
||||
description: PCLK2 divided by 2
|
||||
value: 0
|
||||
- name: Div4
|
||||
description: PCLK2 divided by 4
|
||||
value: 1
|
||||
- name: Div6
|
||||
description: PCLK2 divided by 6
|
||||
value: 2
|
||||
- name: Div8
|
||||
description: PCLK2 divided by 8
|
||||
value: 3
|
||||
enum/HPRE:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Div1
|
||||
description: SYSCLK not divided
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: SYSCLK divided by 2
|
||||
value: 8
|
||||
- name: Div4
|
||||
description: SYSCLK divided by 4
|
||||
value: 9
|
||||
- name: Div8
|
||||
description: SYSCLK divided by 8
|
||||
value: 10
|
||||
- name: Div16
|
||||
description: SYSCLK divided by 16
|
||||
value: 11
|
||||
- name: Div64
|
||||
description: SYSCLK divided by 64
|
||||
value: 12
|
||||
- name: Div128
|
||||
description: SYSCLK divided by 128
|
||||
value: 13
|
||||
- name: Div256
|
||||
description: SYSCLK divided by 256
|
||||
value: 14
|
||||
- name: Div512
|
||||
description: SYSCLK divided by 512
|
||||
value: 15
|
||||
enum/I2S2SRC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: SYSCLK
|
||||
description: System clock (SYSCLK) selected as I2S clock entry
|
||||
value: 0
|
||||
- name: PLL3
|
||||
description: PLL3 VCO clock selected as I2S clock entry
|
||||
value: 1
|
||||
enum/MCO:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: NoMCO
|
||||
description: "MCO output disabled, no clock on MCO"
|
||||
value: 0
|
||||
- name: SYSCLK
|
||||
description: System clock selected
|
||||
value: 4
|
||||
- name: HSI
|
||||
description: HSI oscillator clock selected
|
||||
value: 5
|
||||
- name: HSE
|
||||
description: HSE oscillator clock selected
|
||||
value: 6
|
||||
- name: PLL
|
||||
description: PLL clock divided by 2 selected
|
||||
value: 7
|
||||
- name: PLL2
|
||||
description: PLL2 clock selected
|
||||
value: 8
|
||||
- name: PLL3DIV2
|
||||
description: PLL3 clock divided by 2 selected
|
||||
value: 9
|
||||
- name: XT1
|
||||
description: XT1 external oscillator selected
|
||||
value: 10
|
||||
- name: PLL3
|
||||
description: PLL3 clock selected
|
||||
value: 11
|
||||
enum/PLL2MUL:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Mul8
|
||||
description: PLL clock entry x8
|
||||
value: 6
|
||||
- name: Mul9
|
||||
description: PLL clock entry x9
|
||||
value: 7
|
||||
- name: Mul10
|
||||
description: PLL clock entry x10
|
||||
value: 8
|
||||
- name: Mul11
|
||||
description: PLL clock entry x11
|
||||
value: 9
|
||||
- name: Mul12
|
||||
description: PLL clock entry x12
|
||||
value: 10
|
||||
- name: Mul13
|
||||
description: PLL clock entry x13
|
||||
value: 11
|
||||
- name: Mul14
|
||||
description: PLL clock entry x14
|
||||
value: 12
|
||||
- name: Mul16
|
||||
description: PLL clock entry x16
|
||||
value: 14
|
||||
- name: Mul20
|
||||
description: PLL clock entry x20
|
||||
value: 15
|
||||
enum/PLLMUL:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Mul4
|
||||
description: PLL input clock x4
|
||||
value: 2
|
||||
- name: Mul5
|
||||
description: PLL input clock x5
|
||||
value: 3
|
||||
- name: Mul6
|
||||
description: PLL input clock x6
|
||||
value: 4
|
||||
- name: Mul7
|
||||
description: PLL input clock x7
|
||||
value: 5
|
||||
- name: Mul8
|
||||
description: PLL input clock x8
|
||||
value: 6
|
||||
- name: Mul9
|
||||
description: PLL input clock x9
|
||||
value: 7
|
||||
- name: Mul6_5
|
||||
description: PLL input clock x6.5
|
||||
value: 13
|
||||
enum/PLLSRC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: HSI_Div2
|
||||
description: HSI divided by 2 selected as PLL input clock
|
||||
value: 0
|
||||
- name: HSE_Div_PREDIV
|
||||
description: HSE divided by PREDIV selected as PLL input clock
|
||||
value: 1
|
||||
enum/PLLXTPRE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Div1
|
||||
description: HSE clock not divided
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: HSE clock divided by 2
|
||||
value: 1
|
||||
enum/PPRE1:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Div1
|
||||
description: HCLK not divided
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: HCLK divided by 2
|
||||
value: 4
|
||||
- name: Div4
|
||||
description: HCLK divided by 4
|
||||
value: 5
|
||||
- name: Div8
|
||||
description: HCLK divided by 8
|
||||
value: 6
|
||||
- name: Div16
|
||||
description: HCLK divided by 16
|
||||
value: 7
|
||||
enum/PREDIV1:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Div1
|
||||
description: PREDIV input clock not divided
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: PREDIV input clock divided by 2
|
||||
value: 1
|
||||
- name: Div3
|
||||
description: PREDIV input clock divided by 3
|
||||
value: 2
|
||||
- name: Div4
|
||||
description: PREDIV input clock divided by 4
|
||||
value: 3
|
||||
- name: Div5
|
||||
description: PREDIV input clock divided by 5
|
||||
value: 4
|
||||
- name: Div6
|
||||
description: PREDIV input clock divided by 6
|
||||
value: 5
|
||||
- name: Div7
|
||||
description: PREDIV input clock divided by 7
|
||||
value: 6
|
||||
- name: Div8
|
||||
description: PREDIV input clock divided by 8
|
||||
value: 7
|
||||
- name: Div9
|
||||
description: PREDIV input clock divided by 9
|
||||
value: 8
|
||||
- name: Div10
|
||||
description: PREDIV input clock divided by 10
|
||||
value: 9
|
||||
- name: Div11
|
||||
description: PREDIV input clock divided by 11
|
||||
value: 10
|
||||
- name: Div12
|
||||
description: PREDIV input clock divided by 12
|
||||
value: 11
|
||||
- name: Div13
|
||||
description: PREDIV input clock divided by 13
|
||||
value: 12
|
||||
- name: Div14
|
||||
description: PREDIV input clock divided by 14
|
||||
value: 13
|
||||
- name: Div15
|
||||
description: PREDIV input clock divided by 15
|
||||
value: 14
|
||||
- name: Div16
|
||||
description: PREDIV input clock divided by 16
|
||||
value: 15
|
||||
enum/PREDIV1SRC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: HSE
|
||||
description: HSE oscillator clock selected as PREDIV1 clock entry
|
||||
value: 0
|
||||
- name: PLL2
|
||||
description: PLL2 selected as PREDIV1 clock entry
|
||||
value: 1
|
||||
enum/RTCSEL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: NoClock
|
||||
description: No clock
|
||||
value: 0
|
||||
- name: LSE
|
||||
description: LSE oscillator clock used as RTC clock
|
||||
value: 1
|
||||
- name: LSI
|
||||
description: LSI oscillator clock used as RTC clock
|
||||
value: 2
|
||||
- name: HSE
|
||||
description: HSE oscillator clock divided by a prescaler used as RTC clock
|
||||
value: 3
|
||||
enum/SW:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: HSI
|
||||
description: HSI selected as system clock
|
||||
value: 0
|
||||
- name: HSE
|
||||
description: HSE selected as system clock
|
||||
value: 1
|
||||
- name: PLL
|
||||
description: PLL selected as system clock
|
||||
value: 2
|
||||
enum/SWSR:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: HSI
|
||||
description: HSI oscillator used as system clock
|
||||
value: 0
|
||||
- name: HSE
|
||||
description: HSE oscillator used as system clock
|
||||
value: 1
|
||||
- name: PLL
|
||||
description: PLL used as system clock
|
||||
value: 2
|
||||
enum/USBPRE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: DIV1_5
|
||||
description: PLL clock is divided by 1.5
|
||||
value: 0
|
||||
- name: DIV1
|
||||
description: PLL clock is not divided
|
||||
value: 1
|
||||
@ -149,19 +149,19 @@ fieldset/AHB1ENR:
|
||||
description: DMA2 clock enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: ETHMACEN
|
||||
- name: ETHEN
|
||||
description: Ethernet MAC clock enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: ETHMACTXEN
|
||||
- name: ETHTXEN
|
||||
description: Ethernet Transmission clock enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: ETHMACRXEN
|
||||
- name: ETHRXEN
|
||||
description: Ethernet Reception clock enable
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: ETHMACPTPEN
|
||||
- name: ETHPTPEN
|
||||
description: Ethernet PTP clock enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
@ -240,19 +240,19 @@ fieldset/AHB1LPENR:
|
||||
description: DMA2 clock enable during Sleep mode
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: ETHMACLPEN
|
||||
- name: ETHLPEN
|
||||
description: Ethernet MAC clock enable during Sleep mode
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: ETHMACTXLPEN
|
||||
- name: ETHTXLPEN
|
||||
description: Ethernet transmission clock enable during Sleep mode
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: ETHMACRXLPEN
|
||||
- name: ETHRXLPEN
|
||||
description: Ethernet reception clock enable during Sleep mode
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: ETHMACPTPLPEN
|
||||
- name: ETHPTPLPEN
|
||||
description: Ethernet PTP clock enable during Sleep mode
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
@ -315,7 +315,7 @@ fieldset/AHB1RSTR:
|
||||
description: DMA2 reset
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: ETHMACRST
|
||||
- name: ETHRST
|
||||
description: Ethernet MAC reset
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
|
||||
@ -181,19 +181,19 @@ fieldset/AHB1ENR:
|
||||
description: DMA2D clock enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: ETHMACEN
|
||||
- name: ETHEN
|
||||
description: Ethernet MAC clock enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: ETHMACTXEN
|
||||
- name: ETHTXEN
|
||||
description: Ethernet Transmission clock enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: ETHMACRXEN
|
||||
- name: ETHRXEN
|
||||
description: Ethernet Reception clock enable
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: ETHMACPTPEN
|
||||
- name: ETHPTPEN
|
||||
description: Ethernet PTP clock enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
@ -288,19 +288,19 @@ fieldset/AHB1LPENR:
|
||||
description: DMA2D clock enable during Sleep mode
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: ETHMACLPEN
|
||||
- name: ETHLPEN
|
||||
description: Ethernet MAC clock enable during Sleep mode
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: ETHMACTXLPEN
|
||||
- name: ETHTXLPEN
|
||||
description: Ethernet transmission clock enable during Sleep mode
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: ETHMACRXLPEN
|
||||
- name: ETHRXLPEN
|
||||
description: Ethernet reception clock enable during Sleep mode
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: ETHMACPTPLPEN
|
||||
- name: ETHPTPLPEN
|
||||
description: Ethernet PTP clock enable during Sleep mode
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
@ -379,7 +379,7 @@ fieldset/AHB1RSTR:
|
||||
description: DMA2D reset
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: ETHMACRST
|
||||
- name: ETHRST
|
||||
description: Ethernet MAC reset
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
@ -1621,7 +1621,7 @@ fieldset/DCKCFGR2:
|
||||
bit_size: 1
|
||||
enum: CECSEL
|
||||
- name: CK48MSEL
|
||||
description: SDIO/USBFS clock selection
|
||||
description: SDIO/USB clock selection
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
enum: CKMSEL
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -322,7 +322,7 @@ fieldset/AHB1ENR:
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: USB2OTGHSULPIEN
|
||||
description: " Enable USB_PHY2 clocks "
|
||||
description: Enable USB_PHY2 clocks
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: USB1OTGEN
|
||||
|
||||
@ -246,7 +246,7 @@ fieldset/AHB1ENR:
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: USB2OTGHSULPIEN
|
||||
description: " Enable USB_PHY2 clocks "
|
||||
description: Enable USB_PHY2 clocks
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: USB1OTGEN
|
||||
@ -700,14 +700,14 @@ fieldset/AHB4ENR:
|
||||
description: CRC peripheral clock enable
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: BDMAEN
|
||||
description: BDMA and DMAMUX2 Clock Enable
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: BDMA2EN
|
||||
description: BDMA2 and DMAMUX2 Clock Enable
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: BDMAEN
|
||||
description: BDMA and DMAMUX2 Clock Enable
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: ADC3EN
|
||||
description: ADC3 Peripheral Clocks Enable
|
||||
bit_offset: 24
|
||||
@ -771,14 +771,14 @@ fieldset/AHB4LPENR:
|
||||
description: CRC peripheral clock enable during CSleep mode
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: BDMALPEN
|
||||
description: BDMA Clock Enable During CSleep Mode
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: BDMA2LPEN
|
||||
description: BDMA2 Clock Enable During CSleep Mode
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: BDMALPEN
|
||||
description: BDMA Clock Enable During CSleep Mode
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: ADC3LPEN
|
||||
description: ADC3 Peripheral Clocks Enable During CSleep Mode
|
||||
bit_offset: 24
|
||||
@ -842,14 +842,14 @@ fieldset/AHB4RSTR:
|
||||
description: CRC block reset
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: BDMARST
|
||||
description: BDMA block reset
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: BDMA2RST
|
||||
description: BDMA2 block reset
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: BDMARST
|
||||
description: BDMA block reset
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: ADC3RST
|
||||
description: ADC3 block reset
|
||||
bit_offset: 24
|
||||
@ -2163,14 +2163,14 @@ fieldset/D2CFGR:
|
||||
fieldset/D3AMR:
|
||||
description: RCC D3 Autonomous mode Register
|
||||
fields:
|
||||
- name: BDMAAMEN
|
||||
description: BDMA and DMAMUX Autonomous mode enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: BDMA2AMEN
|
||||
description: BDMA2 and DMAMUX Autonomous mode enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: BDMAAMEN
|
||||
description: BDMA and DMAMUX Autonomous mode enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: LPUART1AMEN
|
||||
description: LPUART1 Autonomous mode enable
|
||||
bit_offset: 3
|
||||
|
||||
@ -598,7 +598,7 @@ fieldset/APB1ENR1:
|
||||
description: CAN2 clock enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: USBFSEN
|
||||
- name: USBEN
|
||||
description: USB FS clock enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
@ -720,7 +720,7 @@ fieldset/APB1RSTR1:
|
||||
description: CAN2 reset
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: USBFSRST
|
||||
- name: USBRST
|
||||
description: USB FS reset
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
@ -846,7 +846,7 @@ fieldset/APB1SMENR1:
|
||||
description: CAN2 clocks enable during Sleep and Stop modes
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: USBFSSMEN
|
||||
- name: USBSMEN
|
||||
description: USB FS clock enable during Sleep and Stop modes
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
@ -1888,23 +1888,23 @@ enum/STOPWUCK:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: MSI
|
||||
description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock
|
||||
description: MSI oscillator selected as wake-up from Stop clock
|
||||
value: 0
|
||||
- name: HSI16
|
||||
description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1)
|
||||
description: HSI oscillator selected as wake-up from Stop clock
|
||||
value: 1
|
||||
enum/SW:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: MSI
|
||||
description: MSI oscillator used as system clock
|
||||
description: MSI selected as system clock
|
||||
value: 0
|
||||
- name: HSI16
|
||||
description: HSI oscillator used as system clock
|
||||
description: HSI selected as system clock
|
||||
value: 1
|
||||
- name: HSE
|
||||
description: HSE oscillator used as system clock
|
||||
description: HSE selected as system clock
|
||||
value: 2
|
||||
- name: PLL
|
||||
description: PLL used as system clock
|
||||
description: PLL selected as system clock
|
||||
value: 3
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -3,215 +3,215 @@ block/RCC:
|
||||
description: Reset and clock control
|
||||
items:
|
||||
- name: CR
|
||||
description: "RCC clock control register "
|
||||
description: RCC clock control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: ICSCR1
|
||||
description: "RCC internal clock sources calibration register 1 "
|
||||
description: RCC internal clock sources calibration register 1
|
||||
byte_offset: 8
|
||||
fieldset: ICSCR1
|
||||
- name: ICSCR2
|
||||
description: "RCC internal clock sources calibration register 2 "
|
||||
description: RCC internal clock sources calibration register 2
|
||||
byte_offset: 12
|
||||
fieldset: ICSCR2
|
||||
- name: ICSCR3
|
||||
description: "RCC internal clock sources calibration register 3 "
|
||||
description: RCC internal clock sources calibration register 3
|
||||
byte_offset: 16
|
||||
fieldset: ICSCR3
|
||||
- name: CRRCR
|
||||
description: "RCC clock recovery RC register "
|
||||
description: RCC clock recovery RC register
|
||||
byte_offset: 20
|
||||
fieldset: CRRCR
|
||||
- name: CFGR1
|
||||
description: "RCC clock configuration register 1 "
|
||||
description: RCC clock configuration register 1
|
||||
byte_offset: 28
|
||||
fieldset: CFGR1
|
||||
- name: CFGR2
|
||||
description: "RCC clock configuration register 2 "
|
||||
description: RCC clock configuration register 2
|
||||
byte_offset: 32
|
||||
fieldset: CFGR2
|
||||
- name: CFGR3
|
||||
description: "RCC clock configuration register 3 "
|
||||
description: RCC clock configuration register 3
|
||||
byte_offset: 36
|
||||
fieldset: CFGR3
|
||||
- name: PLL1CFGR
|
||||
description: "RCC PLL1 configuration register "
|
||||
description: RCC PLL1 configuration register
|
||||
byte_offset: 40
|
||||
fieldset: PLL1CFGR
|
||||
- name: PLL2CFGR
|
||||
description: "RCC PLL2 configuration register "
|
||||
description: RCC PLL2 configuration register
|
||||
byte_offset: 44
|
||||
fieldset: PLL2CFGR
|
||||
- name: PLL3CFGR
|
||||
description: "RCC PLL3 configuration register "
|
||||
description: RCC PLL3 configuration register
|
||||
byte_offset: 48
|
||||
fieldset: PLL3CFGR
|
||||
- name: PLL1DIVR
|
||||
description: "RCC PLL1 dividers register "
|
||||
description: RCC PLL1 dividers register
|
||||
byte_offset: 52
|
||||
fieldset: PLL1DIVR
|
||||
- name: PLL1FRACR
|
||||
description: "RCC PLL1 fractional divider register "
|
||||
description: RCC PLL1 fractional divider register
|
||||
byte_offset: 56
|
||||
fieldset: PLL1FRACR
|
||||
- name: PLL2DIVR
|
||||
description: "RCC PLL2 dividers configuration register "
|
||||
description: RCC PLL2 dividers configuration register
|
||||
byte_offset: 60
|
||||
fieldset: PLL2DIVR
|
||||
- name: PLL2FRACR
|
||||
description: "RCC PLL2 fractional divider register "
|
||||
description: RCC PLL2 fractional divider register
|
||||
byte_offset: 64
|
||||
fieldset: PLL2FRACR
|
||||
- name: PLL3DIVR
|
||||
description: "RCC PLL3 dividers configuration register "
|
||||
description: RCC PLL3 dividers configuration register
|
||||
byte_offset: 68
|
||||
fieldset: PLL3DIVR
|
||||
- name: PLL3FRACR
|
||||
description: "RCC PLL3 fractional divider register "
|
||||
description: RCC PLL3 fractional divider register
|
||||
byte_offset: 72
|
||||
fieldset: PLL3FRACR
|
||||
- name: CIER
|
||||
description: "RCC clock interrupt enable register "
|
||||
description: RCC clock interrupt enable register
|
||||
byte_offset: 80
|
||||
fieldset: CIER
|
||||
- name: CIFR
|
||||
description: "RCC clock interrupt flag register "
|
||||
description: RCC clock interrupt flag register
|
||||
byte_offset: 84
|
||||
fieldset: CIFR
|
||||
- name: CICR
|
||||
description: "RCC clock interrupt clear register "
|
||||
description: RCC clock interrupt clear register
|
||||
byte_offset: 88
|
||||
fieldset: CICR
|
||||
- name: AHB1RSTR
|
||||
description: "RCC AHB1 peripheral reset register "
|
||||
description: RCC AHB1 peripheral reset register
|
||||
byte_offset: 96
|
||||
fieldset: AHB1RSTR
|
||||
- name: AHB2RSTR1
|
||||
description: "RCC AHB2 peripheral reset register 1 "
|
||||
description: RCC AHB2 peripheral reset register 1
|
||||
byte_offset: 100
|
||||
fieldset: AHB2RSTR1
|
||||
- name: AHB2RSTR2
|
||||
description: "RCC AHB2 peripheral reset register 2 "
|
||||
description: RCC AHB2 peripheral reset register 2
|
||||
byte_offset: 104
|
||||
fieldset: AHB2RSTR2
|
||||
- name: AHB3RSTR
|
||||
description: "RCC AHB3 peripheral reset register "
|
||||
description: RCC AHB3 peripheral reset register
|
||||
byte_offset: 108
|
||||
fieldset: AHB3RSTR
|
||||
- name: APB1RSTR1
|
||||
description: "RCC APB1 peripheral reset register 1 "
|
||||
description: RCC APB1 peripheral reset register 1
|
||||
byte_offset: 116
|
||||
fieldset: APB1RSTR1
|
||||
- name: APB1RSTR2
|
||||
description: "RCC APB1 peripheral reset register 2 "
|
||||
description: RCC APB1 peripheral reset register 2
|
||||
byte_offset: 120
|
||||
fieldset: APB1RSTR2
|
||||
- name: APB2RSTR
|
||||
description: "RCC APB2 peripheral reset register "
|
||||
description: RCC APB2 peripheral reset register
|
||||
byte_offset: 124
|
||||
fieldset: APB2RSTR
|
||||
- name: APB3RSTR
|
||||
description: "RCC APB3 peripheral reset register "
|
||||
description: RCC APB3 peripheral reset register
|
||||
byte_offset: 128
|
||||
fieldset: APB3RSTR
|
||||
- name: AHB1ENR
|
||||
description: "RCC AHB1 peripheral clock enable register "
|
||||
description: RCC AHB1 peripheral clock enable register
|
||||
byte_offset: 136
|
||||
fieldset: AHB1ENR
|
||||
- name: AHB2ENR1
|
||||
description: "RCC AHB2 peripheral clock enable register 1 "
|
||||
description: RCC AHB2 peripheral clock enable register 1
|
||||
byte_offset: 140
|
||||
fieldset: AHB2ENR1
|
||||
- name: AHB2ENR2
|
||||
description: "RCC AHB2 peripheral clock enable register 2 "
|
||||
description: RCC AHB2 peripheral clock enable register 2
|
||||
byte_offset: 144
|
||||
fieldset: AHB2ENR2
|
||||
- name: AHB3ENR
|
||||
description: "RCC AHB3 peripheral clock enable register "
|
||||
description: RCC AHB3 peripheral clock enable register
|
||||
byte_offset: 148
|
||||
fieldset: AHB3ENR
|
||||
- name: APB1ENR1
|
||||
description: "RCC APB1 peripheral clock enable register 1 "
|
||||
description: RCC APB1 peripheral clock enable register 1
|
||||
byte_offset: 156
|
||||
fieldset: APB1ENR1
|
||||
- name: APB1ENR2
|
||||
description: "RCC APB1 peripheral clock enable register 2 "
|
||||
description: RCC APB1 peripheral clock enable register 2
|
||||
byte_offset: 160
|
||||
fieldset: APB1ENR2
|
||||
- name: APB2ENR
|
||||
description: "RCC APB2 peripheral clock enable register "
|
||||
description: RCC APB2 peripheral clock enable register
|
||||
byte_offset: 164
|
||||
fieldset: APB2ENR
|
||||
- name: APB3ENR
|
||||
description: "RCC APB3 peripheral clock enable register "
|
||||
description: RCC APB3 peripheral clock enable register
|
||||
byte_offset: 168
|
||||
fieldset: APB3ENR
|
||||
- name: AHB1SMENR
|
||||
description: "RCC AHB1 peripheral clocks enable in Sleep and Stop modes register\t"
|
||||
description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register
|
||||
byte_offset: 176
|
||||
fieldset: AHB1SMENR
|
||||
- name: AHB2SMENR1
|
||||
description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1 "
|
||||
description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1"
|
||||
byte_offset: 180
|
||||
fieldset: AHB2SMENR1
|
||||
- name: AHB2SMENR2
|
||||
description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2 "
|
||||
description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2"
|
||||
byte_offset: 184
|
||||
fieldset: AHB2SMENR2
|
||||
- name: AHB3SMENR
|
||||
description: "RCC AHB3 peripheral clocks enable in Sleep and Stop modes register\t"
|
||||
description: RCC AHB3 peripheral clocks enable in Sleep and Stop modes register
|
||||
byte_offset: 188
|
||||
fieldset: AHB3SMENR
|
||||
- name: APB1SMENR1
|
||||
description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1 "
|
||||
description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1"
|
||||
byte_offset: 196
|
||||
fieldset: APB1SMENR1
|
||||
- name: APB1SMENR2
|
||||
description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2 "
|
||||
description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2"
|
||||
byte_offset: 200
|
||||
fieldset: APB1SMENR2
|
||||
- name: APB2SMENR
|
||||
description: "RCC APB2 peripheral clocks enable in Sleep and Stop modes register\t"
|
||||
description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register
|
||||
byte_offset: 204
|
||||
fieldset: APB2SMENR
|
||||
- name: APB3SMENR
|
||||
description: "RCC APB3 peripheral clock enable in Sleep and Stop modes register\t"
|
||||
description: RCC APB3 peripheral clock enable in Sleep and Stop modes register
|
||||
byte_offset: 208
|
||||
fieldset: APB3SMENR
|
||||
- name: SRDAMR
|
||||
description: "RCC SmartRun domain peripheral autonomous mode register\t"
|
||||
description: RCC SmartRun domain peripheral autonomous mode register
|
||||
byte_offset: 216
|
||||
fieldset: SRDAMR
|
||||
- name: CCIPR1
|
||||
description: "RCC peripherals independent clock configuration register 1\t"
|
||||
description: RCC peripherals independent clock configuration register 1
|
||||
byte_offset: 224
|
||||
fieldset: CCIPR1
|
||||
- name: CCIPR2
|
||||
description: "RCC peripherals independent clock configuration register 2\t"
|
||||
description: RCC peripherals independent clock configuration register 2
|
||||
byte_offset: 228
|
||||
fieldset: CCIPR2
|
||||
- name: CCIPR3
|
||||
description: "RCC peripherals independent clock configuration register 3\t"
|
||||
description: RCC peripherals independent clock configuration register 3
|
||||
byte_offset: 232
|
||||
fieldset: CCIPR3
|
||||
- name: BDCR
|
||||
description: "RCC Backup domain control register "
|
||||
description: RCC Backup domain control register
|
||||
byte_offset: 240
|
||||
fieldset: BDCR
|
||||
- name: CSR
|
||||
description: "RCC control/status register "
|
||||
description: RCC control/status register
|
||||
byte_offset: 244
|
||||
fieldset: CSR
|
||||
- name: SECCFGR
|
||||
description: "RCC secure configuration register "
|
||||
description: RCC secure configuration register
|
||||
byte_offset: 272
|
||||
fieldset: SECCFGR
|
||||
- name: PRIVCFGR
|
||||
description: "RCC privilege configuration register "
|
||||
description: RCC privilege configuration register
|
||||
byte_offset: 276
|
||||
fieldset: PRIVCFGR
|
||||
fieldset/AHB1ENR:
|
||||
description: "RCC AHB1 peripheral clock enable register "
|
||||
description: RCC AHB1 peripheral clock enable register
|
||||
fields:
|
||||
- name: GPDMA1EN
|
||||
description: "GPDMA1 clock enable\r Set and cleared by software."
|
||||
@ -266,7 +266,7 @@ fieldset/AHB1ENR:
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/AHB1RSTR:
|
||||
description: "RCC AHB1 peripheral reset register "
|
||||
description: RCC AHB1 peripheral reset register
|
||||
fields:
|
||||
- name: GPDMA1RST
|
||||
description: "GPDMA1 reset\r Set and cleared by software."
|
||||
@ -301,7 +301,7 @@ fieldset/AHB1RSTR:
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/AHB1SMENR:
|
||||
description: "RCC AHB1 peripheral clocks enable in Sleep and Stop modes register\t"
|
||||
description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register
|
||||
fields:
|
||||
- name: GPDMA1SMEN
|
||||
description: "GPDMA1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
|
||||
@ -360,7 +360,7 @@ fieldset/AHB1SMENR:
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/AHB2ENR1:
|
||||
description: "RCC AHB2 peripheral clock enable register 1 "
|
||||
description: RCC AHB2 peripheral clock enable register 1
|
||||
fields:
|
||||
- name: GPIOAEN
|
||||
description: "IO port A clock enable\r Set and cleared by software."
|
||||
@ -459,7 +459,7 @@ fieldset/AHB2ENR1:
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/AHB2ENR2:
|
||||
description: "RCC AHB2 peripheral clock enable register 2 "
|
||||
description: RCC AHB2 peripheral clock enable register 2
|
||||
fields:
|
||||
- name: FSMCEN
|
||||
description: "FSMC clock enable\r Set and cleared by software."
|
||||
@ -474,7 +474,7 @@ fieldset/AHB2ENR2:
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
fieldset/AHB2RSTR1:
|
||||
description: "RCC AHB2 peripheral reset register 1 "
|
||||
description: RCC AHB2 peripheral reset register 1
|
||||
fields:
|
||||
- name: GPIOARST
|
||||
description: "IO port A reset\r Set and cleared by software."
|
||||
@ -565,7 +565,7 @@ fieldset/AHB2RSTR1:
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
fieldset/AHB2RSTR2:
|
||||
description: "RCC AHB2 peripheral reset register 2 "
|
||||
description: RCC AHB2 peripheral reset register 2
|
||||
fields:
|
||||
- name: FSMCRST
|
||||
description: "Flexible memory controller reset\r Set and cleared by software."
|
||||
@ -580,7 +580,7 @@ fieldset/AHB2RSTR2:
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
fieldset/AHB2SMENR1:
|
||||
description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1 "
|
||||
description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1"
|
||||
fields:
|
||||
- name: GPIOASMEN
|
||||
description: "IO port A clocks enable during Sleep and Stop modes\r Set and cleared by software."
|
||||
@ -679,7 +679,7 @@ fieldset/AHB2SMENR1:
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/AHB2SMENR2:
|
||||
description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2 "
|
||||
description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2"
|
||||
fields:
|
||||
- name: FSMCSMEN
|
||||
description: "FSMC clocks enable during Sleep and Stop modes\r Set and cleared by software."
|
||||
@ -694,7 +694,7 @@ fieldset/AHB2SMENR2:
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
fieldset/AHB3ENR:
|
||||
description: "RCC AHB3 peripheral clock enable register "
|
||||
description: RCC AHB3 peripheral clock enable register
|
||||
fields:
|
||||
- name: LPGPIO1EN
|
||||
description: "LPGPIO1 enable\r Set and cleared by software."
|
||||
@ -729,7 +729,7 @@ fieldset/AHB3ENR:
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/AHB3RSTR:
|
||||
description: "RCC AHB3 peripheral reset register "
|
||||
description: RCC AHB3 peripheral reset register
|
||||
fields:
|
||||
- name: LPGPIO1RST
|
||||
description: "LPGPIO1 reset\r Set and cleared by software."
|
||||
@ -752,7 +752,7 @@ fieldset/AHB3RSTR:
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
fieldset/AHB3SMENR:
|
||||
description: "RCC AHB3 peripheral clocks enable in Sleep and Stop modes register\t"
|
||||
description: RCC AHB3 peripheral clocks enable in Sleep and Stop modes register
|
||||
fields:
|
||||
- name: LPGPIO1SMEN
|
||||
description: "LPGPIO1 enable during Sleep and Stop modes\r Set and cleared by software."
|
||||
@ -787,7 +787,7 @@ fieldset/AHB3SMENR:
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/APB1ENR1:
|
||||
description: "RCC APB1 peripheral clock enable register 1 "
|
||||
description: RCC APB1 peripheral clock enable register 1
|
||||
fields:
|
||||
- name: TIM2EN
|
||||
description: "TIM2 clock enable\r Set and cleared by software."
|
||||
@ -850,7 +850,7 @@ fieldset/APB1ENR1:
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/APB1ENR2:
|
||||
description: "RCC APB1 peripheral clock enable register 2 "
|
||||
description: RCC APB1 peripheral clock enable register 2
|
||||
fields:
|
||||
- name: I2C4EN
|
||||
description: "I2C4 clock enable\r Set and cleared by software"
|
||||
@ -869,7 +869,7 @@ fieldset/APB1ENR2:
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/APB1RSTR1:
|
||||
description: "RCC APB1 peripheral reset register 1 "
|
||||
description: RCC APB1 peripheral reset register 1
|
||||
fields:
|
||||
- name: TIM2RST
|
||||
description: "TIM2 reset\r Set and cleared by software."
|
||||
@ -928,7 +928,7 @@ fieldset/APB1RSTR1:
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/APB1RSTR2:
|
||||
description: "RCC APB1 peripheral reset register 2 "
|
||||
description: RCC APB1 peripheral reset register 2
|
||||
fields:
|
||||
- name: I2C4RST
|
||||
description: "I2C4 reset\r Set and cleared by software"
|
||||
@ -947,7 +947,7 @@ fieldset/APB1RSTR2:
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/APB1SMENR1:
|
||||
description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1 "
|
||||
description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1"
|
||||
fields:
|
||||
- name: TIM2SMEN
|
||||
description: "TIM2 clocks enable during Sleep and Stop modes\r Set and cleared by software."
|
||||
@ -1010,7 +1010,7 @@ fieldset/APB1SMENR1:
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/APB1SMENR2:
|
||||
description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2 "
|
||||
description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2"
|
||||
fields:
|
||||
- name: I2C4SMEN
|
||||
description: "I2C4 clocks enable during Sleep and Stop modes\r Set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
|
||||
@ -1029,7 +1029,7 @@ fieldset/APB1SMENR2:
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/APB2ENR:
|
||||
description: "RCC APB2 peripheral clock enable register "
|
||||
description: RCC APB2 peripheral clock enable register
|
||||
fields:
|
||||
- name: TIM1EN
|
||||
description: "TIM1 clock enable\r Set and cleared by software."
|
||||
@ -1068,7 +1068,7 @@ fieldset/APB2ENR:
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
fieldset/APB2RSTR:
|
||||
description: "RCC APB2 peripheral reset register "
|
||||
description: RCC APB2 peripheral reset register
|
||||
fields:
|
||||
- name: TIM1RST
|
||||
description: "TIM1 reset\r Set and cleared by software."
|
||||
@ -1107,7 +1107,7 @@ fieldset/APB2RSTR:
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
fieldset/APB2SMENR:
|
||||
description: "RCC APB2 peripheral clocks enable in Sleep and Stop modes register\t"
|
||||
description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register
|
||||
fields:
|
||||
- name: TIM1SMEN
|
||||
description: "TIM1 clocks enable during Sleep and Stop modes\r Set and cleared by software."
|
||||
@ -1146,7 +1146,7 @@ fieldset/APB2SMENR:
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
fieldset/APB3ENR:
|
||||
description: "RCC APB3 peripheral clock enable register "
|
||||
description: RCC APB3 peripheral clock enable register
|
||||
fields:
|
||||
- name: SYSCFGEN
|
||||
description: "SYSCFG clock enable\r Set and cleared by software."
|
||||
@ -1193,7 +1193,7 @@ fieldset/APB3ENR:
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
fieldset/APB3RSTR:
|
||||
description: "RCC APB3 peripheral reset register "
|
||||
description: RCC APB3 peripheral reset register
|
||||
fields:
|
||||
- name: SYSCFGRST
|
||||
description: "SYSCFG reset\r Set and cleared by software."
|
||||
@ -1236,7 +1236,7 @@ fieldset/APB3RSTR:
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
fieldset/APB3SMENR:
|
||||
description: "RCC APB3 peripheral clock enable in Sleep and Stop modes register\t"
|
||||
description: RCC APB3 peripheral clock enable in Sleep and Stop modes register
|
||||
fields:
|
||||
- name: SYSCFGSMEN
|
||||
description: "SYSCFG clocks enable during Sleep and Stop modes\r Set and cleared by software."
|
||||
@ -1283,7 +1283,7 @@ fieldset/APB3SMENR:
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
fieldset/BDCR:
|
||||
description: "RCC Backup domain control register "
|
||||
description: RCC Backup domain control register
|
||||
fields:
|
||||
- name: LSEON
|
||||
description: "LSE oscillator enable\r Set and cleared by software."
|
||||
@ -1358,7 +1358,7 @@ fieldset/BDCR:
|
||||
bit_size: 1
|
||||
enum: LSIPREDIV
|
||||
fieldset/CCIPR1:
|
||||
description: "RCC peripherals independent clock configuration register 1\t"
|
||||
description: RCC peripherals independent clock configuration register 1
|
||||
fields:
|
||||
- name: USART1SEL
|
||||
description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE."
|
||||
@ -1436,7 +1436,7 @@ fieldset/CCIPR1:
|
||||
bit_size: 3
|
||||
enum: TIMICSEL
|
||||
fieldset/CCIPR2:
|
||||
description: "RCC peripherals independent clock configuration register 2\t"
|
||||
description: RCC peripherals independent clock configuration register 2
|
||||
fields:
|
||||
- name: MDF1SEL
|
||||
description: "MDF1 kernel clock source selection\r These bits are used to select the MDF1 kernel clock source.\r others: reserved"
|
||||
@ -1474,7 +1474,7 @@ fieldset/CCIPR2:
|
||||
bit_size: 2
|
||||
enum: OCTOSPISEL
|
||||
fieldset/CCIPR3:
|
||||
description: "RCC peripherals independent clock configuration register 3\t"
|
||||
description: RCC peripherals independent clock configuration register 3
|
||||
fields:
|
||||
- name: LPUART1SEL
|
||||
description: "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r others: reserved\r Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16, LSE or MSIK."
|
||||
@ -1517,7 +1517,7 @@ fieldset/CCIPR3:
|
||||
bit_size: 3
|
||||
enum: ADFSEL
|
||||
fieldset/CFGR1:
|
||||
description: "RCC clock configuration register 1 "
|
||||
description: RCC clock configuration register 1
|
||||
fields:
|
||||
- name: SW
|
||||
description: "system clock switch\r Set and cleared by software to select system clock source (SYSCLK).\r Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI16 oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value."
|
||||
@ -1550,7 +1550,7 @@ fieldset/CFGR1:
|
||||
bit_size: 3
|
||||
enum: MCOPRE
|
||||
fieldset/CFGR2:
|
||||
description: "RCC clock configuration register 2 "
|
||||
description: RCC clock configuration register 2
|
||||
fields:
|
||||
- name: HPRE
|
||||
description: "AHB prescaler\r Set and cleared by software to control the division factor of the AHB clock (HCLK).\r Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account.\r 0xxx: SYSCLK not divided"
|
||||
@ -1588,7 +1588,7 @@ fieldset/CFGR2:
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
fieldset/CFGR3:
|
||||
description: "RCC clock configuration register 3 "
|
||||
description: RCC clock configuration register 3
|
||||
fields:
|
||||
- name: PPRE3
|
||||
description: "APB3 prescaler\r Set and cleared by software to control the division factor of the APB3 clock (PCLK3).\r 0xx: HCLK not divided"
|
||||
@ -1604,7 +1604,7 @@ fieldset/CFGR3:
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
fieldset/CICR:
|
||||
description: "RCC clock interrupt clear register "
|
||||
description: RCC clock interrupt clear register
|
||||
fields:
|
||||
- name: LSIRDYC
|
||||
description: "LSI ready interrupt clear\r Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect."
|
||||
@ -1650,7 +1650,7 @@ fieldset/CICR:
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
fieldset/CIER:
|
||||
description: "RCC clock interrupt enable register "
|
||||
description: RCC clock interrupt enable register
|
||||
fields:
|
||||
- name: LSIRDYIE
|
||||
description: "LSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization."
|
||||
@ -1692,7 +1692,7 @@ fieldset/CIER:
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
fieldset/CIFR:
|
||||
description: "RCC clock interrupt flag register "
|
||||
description: RCC clock interrupt flag register
|
||||
fields:
|
||||
- name: LSIRDYF
|
||||
description: "LSI ready interrupt flag\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.\r Cleared by software setting the LSIRDYC bit."
|
||||
@ -1738,7 +1738,7 @@ fieldset/CIFR:
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: "RCC clock control register "
|
||||
description: RCC clock control register
|
||||
fields:
|
||||
- name: MSISON
|
||||
description: "MSIS clock enable\r Set and cleared by software.\r Cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when exiting Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator.\r Set by hardware when used directly or indirectly as system clock."
|
||||
@ -1838,14 +1838,14 @@ fieldset/CR:
|
||||
len: 3
|
||||
stride: 2
|
||||
fieldset/CRRCR:
|
||||
description: "RCC clock recovery RC register "
|
||||
description: RCC clock recovery RC register
|
||||
fields:
|
||||
- name: HSI48CAL
|
||||
description: "HSI48 clock calibration\r These bits are initialized at startup with the factory-programmed HSI48 calibration trim value."
|
||||
bit_offset: 0
|
||||
bit_size: 9
|
||||
fieldset/CSR:
|
||||
description: "RCC control/status register "
|
||||
description: RCC control/status register
|
||||
fields:
|
||||
- name: MSIKSRANGE
|
||||
description: "MSIK range after Standby mode\r Set by software to chose the MSIK frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSIKSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSIKSRANGE does not change the current MSIK frequency."
|
||||
@ -1890,7 +1890,7 @@ fieldset/CSR:
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/ICSCR1:
|
||||
description: "RCC internal clock sources calibration register 1 "
|
||||
description: RCC internal clock sources calibration register 1
|
||||
fields:
|
||||
- name: MSICAL3
|
||||
description: "MSIRC3 clock calibration for MSI ranges 12 to 15\r These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level."
|
||||
@ -1929,7 +1929,7 @@ fieldset/ICSCR1:
|
||||
bit_size: 4
|
||||
enum: MSIRANGE
|
||||
fieldset/ICSCR2:
|
||||
description: "RCC internal clock sources calibration register 2 "
|
||||
description: RCC internal clock sources calibration register 2
|
||||
fields:
|
||||
- name: MSITRIM3
|
||||
description: "MSI clock trimming for ranges 12 to 15\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI."
|
||||
@ -1948,7 +1948,7 @@ fieldset/ICSCR2:
|
||||
bit_offset: 15
|
||||
bit_size: 5
|
||||
fieldset/ICSCR3:
|
||||
description: "RCC internal clock sources calibration register 3 "
|
||||
description: RCC internal clock sources calibration register 3
|
||||
fields:
|
||||
- name: HSICAL
|
||||
description: "HSI clock calibration\r These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value."
|
||||
@ -1959,7 +1959,7 @@ fieldset/ICSCR3:
|
||||
bit_offset: 16
|
||||
bit_size: 5
|
||||
fieldset/PLL1CFGR:
|
||||
description: "RCC PLL1 configuration register "
|
||||
description: RCC PLL1 configuration register
|
||||
fields:
|
||||
- name: PLLSRC
|
||||
description: "PLL1 entry clock source\r Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled.\r In order to save power, when no PLL1 is used, the value of PLL1SRC must be 0."
|
||||
@ -1998,7 +1998,7 @@ fieldset/PLL1CFGR:
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/PLL1DIVR:
|
||||
description: "RCC PLL1 dividers register "
|
||||
description: RCC PLL1 dividers register
|
||||
fields:
|
||||
- name: PLLN
|
||||
description: "Multiplication factor for PLL1 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with:\r PLL1N between 4 and 512\r input frequency Fref1_ck between 4 and 16 MHz"
|
||||
@ -2017,14 +2017,14 @@ fieldset/PLL1DIVR:
|
||||
bit_offset: 24
|
||||
bit_size: 7
|
||||
fieldset/PLL1FRACR:
|
||||
description: "RCC PLL1 fractional divider register "
|
||||
description: RCC PLL1 fractional divider register
|
||||
fields:
|
||||
- name: PLLFRACN
|
||||
description: "Fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with:\r PLL1N must be between 4 and 512.\r PLL1FRACN can be between 0 and 213- 1.\r The input frequency Fref1_ck must be between 4 and 16 MHz.\r To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL1FRACEN to 0.\r Write the new fractional value into PLL1FRACN.\r Set the bit PLL1FRACEN to 1."
|
||||
bit_offset: 3
|
||||
bit_size: 13
|
||||
fieldset/PLL2CFGR:
|
||||
description: "RCC PLL2 configuration register "
|
||||
description: RCC PLL2 configuration register
|
||||
fields:
|
||||
- name: PLLSRC
|
||||
description: "PLL2 entry clock source\r Set and cleared by software to select PLL2 clock source. These bits can be written only when the PLL2 is disabled.\r In order to save power, when no PLL2 is used, the value of PLL2SRC must be 0."
|
||||
@ -2058,7 +2058,7 @@ fieldset/PLL2CFGR:
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/PLL2DIVR:
|
||||
description: "RCC PLL2 dividers configuration register "
|
||||
description: RCC PLL2 dividers configuration register
|
||||
fields:
|
||||
- name: PLLN
|
||||
description: "Multiplication factor for PLL2 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref2_ck x PLL2N, when fractional value 0 has been loaded into PLL2FRACN, with:\r PLL2N between 4 and 512\r input frequency Fref2_ck between 1MHz and 16MHz"
|
||||
@ -2077,14 +2077,14 @@ fieldset/PLL2DIVR:
|
||||
bit_offset: 24
|
||||
bit_size: 7
|
||||
fieldset/PLL2FRACR:
|
||||
description: "RCC PLL2 fractional divider register "
|
||||
description: RCC PLL2 fractional divider register
|
||||
fields:
|
||||
- name: PLLFRACN
|
||||
description: "Fractional part of the multiplication factor for PLL2 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO.\r VCO output frequency = Fref2_ck x (PLL2N + (PLL2FRACN / 213)), with\r PLL2N must be between 4 and 512.\r PLL2FRACN can be between 0 and 213 - 1.\r The input frequency Fref2_ck must be between 4 and 16 MHz.\r In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL2FRACEN to 0.\r Write the new fractional value into PLL2FRACN.\r Set the bit PLL2FRACEN to 1."
|
||||
bit_offset: 3
|
||||
bit_size: 13
|
||||
fieldset/PLL3CFGR:
|
||||
description: "RCC PLL3 configuration register "
|
||||
description: RCC PLL3 configuration register
|
||||
fields:
|
||||
- name: PLLSRC
|
||||
description: "PLL3 entry clock source\r Set and cleared by software to select PLL3 clock source. These bits can be written only when the PLL3 is disabled.\r In order to save power, when no PLL3 is used, the value of PLL3SRC must be 00."
|
||||
@ -2121,7 +2121,7 @@ fieldset/PLL3CFGR:
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/PLL3DIVR:
|
||||
description: "RCC PLL3 dividers configuration register "
|
||||
description: RCC PLL3 dividers configuration register
|
||||
fields:
|
||||
- name: PLLN
|
||||
description: "Multiplication factor for PLL3 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref3_ck x PLL3N, when fractional value 0 has been loaded into PLL3FRACN, with:\r PLL3N between 4 and 512\r input frequency Fref3_ck between 4 and 16MHz"
|
||||
@ -2140,14 +2140,14 @@ fieldset/PLL3DIVR:
|
||||
bit_offset: 24
|
||||
bit_size: 7
|
||||
fieldset/PLL3FRACR:
|
||||
description: "RCC PLL3 fractional divider register "
|
||||
description: RCC PLL3 fractional divider register
|
||||
fields:
|
||||
- name: PLLFRACN
|
||||
description: "Fractional part of the multiplication factor for PLL3 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO.\r VCO output frequency = Fref3_ck x (PLL3N + (PLL3FRACN / 213)), with:\r PLL3N must be between 4 and 512.\r PLL3FRACN can be between 0 and 213 - 1.\r The input frequency Fref3_ck must be between 4 and 16 MHz.\r In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL3FRACEN to 0.\r Write the new fractional value into PLL3FRACN.\r Set the bit PLL3FRACEN to 1."
|
||||
bit_offset: 3
|
||||
bit_size: 13
|
||||
fieldset/PRIVCFGR:
|
||||
description: "RCC privilege configuration register "
|
||||
description: RCC privilege configuration register
|
||||
fields:
|
||||
- name: SPRIV
|
||||
description: "RCC secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access."
|
||||
@ -2160,7 +2160,7 @@ fieldset/PRIVCFGR:
|
||||
bit_size: 1
|
||||
enum: PRIV
|
||||
fieldset/SECCFGR:
|
||||
description: "RCC secure configuration register "
|
||||
description: RCC secure configuration register
|
||||
fields:
|
||||
- name: HSISEC
|
||||
description: "HSI clock configuration and status bits security\r Set and reset by software."
|
||||
@ -2221,7 +2221,7 @@ fieldset/SECCFGR:
|
||||
bit_size: 1
|
||||
enum: SECURITY
|
||||
fieldset/SRDAMR:
|
||||
description: "RCC SmartRun domain peripheral autonomous mode register\t"
|
||||
description: RCC SmartRun domain peripheral autonomous mode register
|
||||
fields:
|
||||
- name: SPI3AMEN
|
||||
description: "SPI3 autonomous mode enable in Stop 0,1, 2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
|
||||
@ -2339,7 +2339,7 @@ enum/FDCANSEL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: HSE
|
||||
description: "HSE clock selected "
|
||||
description: HSE clock selected
|
||||
value: 0
|
||||
- name: PLL1_Q
|
||||
description: PLL1 Q (pll1_q_ck) selected
|
||||
@ -2471,7 +2471,7 @@ enum/LSEDRV:
|
||||
description: "'Xtal mode medium-high driving capability"
|
||||
value: 2
|
||||
- name: HIGH
|
||||
description: "'Xtal mode higher driving capability "
|
||||
description: "'Xtal mode higher driving capability"
|
||||
value: 3
|
||||
enum/LSIPREDIV:
|
||||
bit_size: 1
|
||||
@ -2573,7 +2573,7 @@ enum/MSIPLLSEL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: MSIK
|
||||
description: "PLL mode applied to MSIK (MSI kernel) clock output "
|
||||
description: PLL mode applied to MSIK (MSI kernel) clock output
|
||||
value: 0
|
||||
- name: MSIS
|
||||
description: PLL mode applied to MSIS (MSI system) clock output
|
||||
@ -2582,52 +2582,52 @@ enum/MSIRANGE:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: RANGE_48MHZ
|
||||
description: "range 0 around 48 MHz "
|
||||
description: range 0 around 48 MHz
|
||||
value: 0
|
||||
- name: RANGE_24MHZ
|
||||
description: "range 1 around 24 MHz "
|
||||
description: range 1 around 24 MHz
|
||||
value: 1
|
||||
- name: RANGE_16MHZ
|
||||
description: "range 2 around 16 MHz "
|
||||
description: range 2 around 16 MHz
|
||||
value: 2
|
||||
- name: RANGE_12MHZ
|
||||
description: "range 3 around 12 MHz "
|
||||
description: range 3 around 12 MHz
|
||||
value: 3
|
||||
- name: RANGE_4MHZ
|
||||
description: "range 4 around 4 MHz (reset value) "
|
||||
description: range 4 around 4 MHz (reset value)
|
||||
value: 4
|
||||
- name: RANGE_2MHZ
|
||||
description: "range 5 around 2 MHz "
|
||||
description: range 5 around 2 MHz
|
||||
value: 5
|
||||
- name: RANGE_1_33MHZ
|
||||
description: "range 6 around 1.33 MHz "
|
||||
description: range 6 around 1.33 MHz
|
||||
value: 6
|
||||
- name: RANGE_1MHZ
|
||||
description: "range 7 around 1 MHz "
|
||||
description: range 7 around 1 MHz
|
||||
value: 7
|
||||
- name: RANGE_3_072MHZ
|
||||
description: "range 8 around 3.072 MHz "
|
||||
description: range 8 around 3.072 MHz
|
||||
value: 8
|
||||
- name: RANGE_1_536MHZ
|
||||
description: "range 9 around 1.536 MHz "
|
||||
description: range 9 around 1.536 MHz
|
||||
value: 9
|
||||
- name: RANGE_1_024MHZ
|
||||
description: "range 10 around 1.024 MHz "
|
||||
description: range 10 around 1.024 MHz
|
||||
value: 10
|
||||
- name: RANGE_768KHZ
|
||||
description: "range 11 around 768 kHz "
|
||||
description: range 11 around 768 kHz
|
||||
value: 11
|
||||
- name: RANGE_400KHZ
|
||||
description: "range 12 around 400 kHz "
|
||||
description: range 12 around 400 kHz
|
||||
value: 12
|
||||
- name: RANGE_200KHZ
|
||||
description: "range 13 around 200 kHz "
|
||||
description: range 13 around 200 kHz
|
||||
value: 13
|
||||
- name: RANGE_133KHZ
|
||||
description: range 14 around 133 kHz
|
||||
value: 14
|
||||
- name: RANGE_100KHZ
|
||||
description: "range 15 around 100 kHz "
|
||||
description: range 15 around 100 kHz
|
||||
value: 15
|
||||
enum/MSIRGSEL:
|
||||
bit_size: 1
|
||||
@ -2642,19 +2642,19 @@ enum/MSIXSRANGE:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: RANGE_4MHZ
|
||||
description: "range 4 around 4M Hz (reset value) "
|
||||
description: range 4 around 4M Hz (reset value)
|
||||
value: 4
|
||||
- name: RANGE_2MHZ
|
||||
description: "range 5 around 2 MHz "
|
||||
description: range 5 around 2 MHz
|
||||
value: 5
|
||||
- name: RANGE_1_5MHZ
|
||||
description: "range 6 around 1.5 MHz "
|
||||
description: range 6 around 1.5 MHz
|
||||
value: 6
|
||||
- name: RANGE_1MHZ
|
||||
description: "range 7 around 1 MHz "
|
||||
description: range 7 around 1 MHz
|
||||
value: 7
|
||||
- name: RANGE_3_072MHZ
|
||||
description: "range 8 around 3.072 MHz "
|
||||
description: range 8 around 3.072 MHz
|
||||
value: 8
|
||||
enum/OCTOSPISEL:
|
||||
bit_size: 2
|
||||
@ -2771,7 +2771,7 @@ enum/RNGSEL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: HSI48
|
||||
description: "HSI48 selected "
|
||||
description: HSI48 selected
|
||||
value: 0
|
||||
- name: HSI48_DIV2
|
||||
description: "HSI48 / 2 selected, can be used in Range 4"
|
||||
@ -2828,7 +2828,7 @@ enum/SDMMCSEL:
|
||||
description: ICLK clock selected
|
||||
value: 0
|
||||
- name: PLL1_P
|
||||
description: "PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) "
|
||||
description: "PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode)"
|
||||
value: 1
|
||||
enum/SECURITY:
|
||||
bit_size: 1
|
||||
|
||||
@ -544,7 +544,7 @@ fieldset/APB1RSTR1:
|
||||
description: CRS reset
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: USBFSRST
|
||||
- name: USBRST
|
||||
description: USB FS reset
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
|
||||
@ -195,13 +195,6 @@ fieldset/DTIMER:
|
||||
description: Data timeout period
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/FIFOR:
|
||||
description: data FIFO register
|
||||
fields:
|
||||
- name: FIFOData
|
||||
description: Receive and transmit FIFO data
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/FIFOCNT:
|
||||
description: FIFO counter register
|
||||
fields:
|
||||
@ -209,6 +202,13 @@ fieldset/FIFOCNT:
|
||||
description: Remaining number of words to be written to or read from the FIFO
|
||||
bit_offset: 0
|
||||
bit_size: 24
|
||||
fieldset/FIFOR:
|
||||
description: data FIFO register
|
||||
fields:
|
||||
- name: FIFOData
|
||||
description: Receive and transmit FIFO data
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/ICR:
|
||||
description: interrupt clear register
|
||||
fields:
|
||||
|
||||
722
data/registers/spi_v4.yaml
Normal file
722
data/registers/spi_v4.yaml
Normal file
@ -0,0 +1,722 @@
|
||||
---
|
||||
block/SPI:
|
||||
description: Serial peripheral interface
|
||||
items:
|
||||
- name: CR1
|
||||
description: control register 1
|
||||
byte_offset: 0
|
||||
fieldset: CR1
|
||||
- name: CR2
|
||||
description: control register 2
|
||||
byte_offset: 4
|
||||
fieldset: CR2
|
||||
- name: CFG1
|
||||
description: configuration register 1
|
||||
byte_offset: 8
|
||||
fieldset: CFG1
|
||||
- name: CFG2
|
||||
description: configuration register 2
|
||||
byte_offset: 12
|
||||
fieldset: CFG2
|
||||
- name: IER
|
||||
description: Interrupt Enable Register
|
||||
byte_offset: 16
|
||||
fieldset: IER
|
||||
- name: SR
|
||||
description: Status Register
|
||||
byte_offset: 20
|
||||
access: Read
|
||||
fieldset: SR
|
||||
- name: IFCR
|
||||
description: Interrupt/Status Flags Clear Register
|
||||
byte_offset: 24
|
||||
access: Write
|
||||
fieldset: IFCR
|
||||
- name: AUTOCR
|
||||
byte_offset: 28
|
||||
fieldset: AUTOCR
|
||||
- name: TXDR
|
||||
description: Transmit Data Register
|
||||
byte_offset: 32
|
||||
access: Write
|
||||
fieldset: TXDR
|
||||
- name: RXDR
|
||||
description: Receive Data Register
|
||||
byte_offset: 48
|
||||
access: Read
|
||||
fieldset: RXDR
|
||||
- name: CRCPOLY
|
||||
description: Polynomial Register
|
||||
byte_offset: 64
|
||||
fieldset: CRCPOLY
|
||||
- name: TXCRC
|
||||
description: Transmitter CRC Register
|
||||
byte_offset: 68
|
||||
fieldset: TXCRC
|
||||
- name: RXCRC
|
||||
description: Receiver CRC Register
|
||||
byte_offset: 72
|
||||
fieldset: RXCRC
|
||||
- name: UDRDR
|
||||
description: Underrun Data Register
|
||||
byte_offset: 76
|
||||
fieldset: UDRDR
|
||||
fieldset/AUTOCR:
|
||||
fields:
|
||||
- name: TRIGSEL
|
||||
description: "trigger selection (refer ).\n ...\n Note: these bits can be written only when SPE = 0."
|
||||
bit_offset: 16
|
||||
bit_size: 4
|
||||
- name: TRIGPOL
|
||||
description: "trigger polarity\n Note: This bit can be written only when SPE = 0."
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
enum: TRIGPOL
|
||||
- name: TRIGEN
|
||||
description: "trigger of CSTART control enable\n Note: if user can't prevent trigger event during write, the TRIGEN has to be changed when SPI is disabled"
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
fieldset/CFG1:
|
||||
description: configuration register 1
|
||||
fields:
|
||||
- name: DSIZE
|
||||
description: Number of bits in at single SPI data frame
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: FTHLV
|
||||
description: threshold level
|
||||
bit_offset: 5
|
||||
bit_size: 4
|
||||
enum: FTHLV
|
||||
- name: UDRCFG
|
||||
description: Behavior of slave transmitter at underrun condition
|
||||
bit_offset: 9
|
||||
bit_size: 2
|
||||
enum: UDRCFG
|
||||
- name: RXDMAEN
|
||||
description: Rx DMA stream enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: TXDMAEN
|
||||
description: Tx DMA stream enable
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: CRCSIZE
|
||||
description: Length of CRC frame to be transacted and compared
|
||||
bit_offset: 16
|
||||
bit_size: 5
|
||||
- name: CRCEN
|
||||
description: Hardware CRC computation enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: MBR
|
||||
description: Master baud rate
|
||||
bit_offset: 28
|
||||
bit_size: 3
|
||||
enum: MBR
|
||||
- name: BPASS
|
||||
description: bypass of the prescaler at master baud rate clock generator
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/CFG2:
|
||||
description: configuration register 2
|
||||
fields:
|
||||
- name: MSSI
|
||||
description: Master SS Idleness
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: MIDI
|
||||
description: Master Inter-Data Idleness
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
- name: RDIOM
|
||||
description: "RDY signal input/output management\n Note: When DSIZE at the CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero."
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
enum: RDIOM
|
||||
- name: RDIOP
|
||||
description: RDY signal input/output polarity
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
enum: RDIOP
|
||||
- name: IOSWP
|
||||
description: Swap functionality of MISO and MOSI pins
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: COMM
|
||||
description: SPI Communication Mode
|
||||
bit_offset: 17
|
||||
bit_size: 2
|
||||
enum: COMM
|
||||
- name: SP
|
||||
description: Serial Protocol
|
||||
bit_offset: 19
|
||||
bit_size: 3
|
||||
enum: SP
|
||||
- name: MASTER
|
||||
description: SPI Master
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
enum: MASTER
|
||||
- name: LSBFIRST
|
||||
description: Data frame format
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
enum: LSBFIRST
|
||||
- name: CPHA
|
||||
description: Clock phase
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
enum: CPHA
|
||||
- name: CPOL
|
||||
description: Clock polarity
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
enum: CPOL
|
||||
- name: SSM
|
||||
description: Software management of SS signal input
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: SSIOP
|
||||
description: SS input/output polarity
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
enum: SSIOP
|
||||
- name: SSOE
|
||||
description: SS output enable
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: SSOM
|
||||
description: SS output management in master mode
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
enum: SSOM
|
||||
- name: AFCNTR
|
||||
description: Alternate function GPIOs control
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
enum: AFCNTR
|
||||
fieldset/CR1:
|
||||
description: control register 1
|
||||
fields:
|
||||
- name: SPE
|
||||
description: Serial Peripheral Enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: MASRX
|
||||
description: Master automatic SUSP in Receive mode
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: CSTART
|
||||
description: Master transfer start
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: CSUSP
|
||||
description: Master SUSPend request
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: HDDIR
|
||||
description: Rx/Tx direction at Half-duplex mode
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
enum: HDDIR
|
||||
- name: SSI
|
||||
description: Internal SS signal input level
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: CRC33_17
|
||||
description: 32-bit CRC polynomial configuration
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
enum: CRC_
|
||||
- name: RCRCINI
|
||||
description: CRC calculation initialization pattern control for receiver
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
enum: RCRCINI
|
||||
- name: TCRCINI
|
||||
description: CRC calculation initialization pattern control for transmitter
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum: TCRCINI
|
||||
- name: IOLOCK
|
||||
description: Locking the AF configuration of associated IOs
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
fieldset/CR2:
|
||||
description: control register 2
|
||||
fields:
|
||||
- name: TSIZE
|
||||
description: Number of data at current transfer
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/CRCPOLY:
|
||||
description: Polynomial Register
|
||||
fields:
|
||||
- name: CRCPOLY
|
||||
description: CRC polynomial register
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/IER:
|
||||
description: Interrupt Enable Register
|
||||
fields:
|
||||
- name: RXPIE
|
||||
description: RXP Interrupt Enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TXPIE
|
||||
description: TXP interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DXPIE
|
||||
description: DXP interrupt enabled
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOTIE
|
||||
description: "EOT, SUSP and TXC interrupt enable"
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TXTFIE
|
||||
description: TXTFIE interrupt enable
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: UDRIE
|
||||
description: UDR interrupt enable
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: OVRIE
|
||||
description: OVR interrupt enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: CRCEIE
|
||||
description: CRC Interrupt enable
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIFREIE
|
||||
description: TIFRE interrupt enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: MODFIE
|
||||
description: Mode Fault interrupt enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
fieldset/IFCR:
|
||||
description: Interrupt/Status Flags Clear Register
|
||||
fields:
|
||||
- name: EOTC
|
||||
description: End Of Transfer flag clear
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TXTFC
|
||||
description: Transmission Transfer Filled flag clear
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: UDRC
|
||||
description: Underrun flag clear
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: OVRC
|
||||
description: Overrun flag clear
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: CRCEC
|
||||
description: CRC Error flag clear
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIFREC
|
||||
description: TI frame format error flag clear
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: MODFC
|
||||
description: Mode Fault flag clear
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: SUSPC
|
||||
description: SUSPend flag clear
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
fieldset/RXCRC:
|
||||
description: Receiver CRC Register
|
||||
fields:
|
||||
- name: RXCRC
|
||||
description: CRC register for receiver
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/RXDR:
|
||||
description: Receive Data Register
|
||||
fields:
|
||||
- name: RXDR
|
||||
description: Receive data register
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SR:
|
||||
description: Status Register
|
||||
fields:
|
||||
- name: RXP
|
||||
description: Rx-Packet available
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TXP
|
||||
description: Tx-Packet space available
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DXP
|
||||
description: Duplex Packet
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOT
|
||||
description: End Of Transfer
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TXTF
|
||||
description: Transmission Transfer Filled
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: UDR
|
||||
description: Underrun at slave transmission mode
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: OVR
|
||||
description: Overrun
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: CRCE
|
||||
description: CRC Error
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIFRE
|
||||
description: TI frame format error
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: MODF
|
||||
description: Mode Fault
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: SUSP
|
||||
description: SUSPend
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TXC
|
||||
description: TxFIFO transmission complete
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: RXPLVL
|
||||
description: RxFIFO Packing LeVeL
|
||||
bit_offset: 13
|
||||
bit_size: 2
|
||||
enum: RXPLVL
|
||||
- name: RXWNE
|
||||
description: RxFIFO Word Not Empty
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum: RXWNE
|
||||
- name: CTSIZE
|
||||
description: Number of data frames remaining in current TSIZE session
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/TXCRC:
|
||||
description: Transmitter CRC Register
|
||||
fields:
|
||||
- name: TXCRC
|
||||
description: CRC register for transmitter
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/TXDR:
|
||||
description: Transmit Data Register
|
||||
fields:
|
||||
- name: TXDR
|
||||
description: Transmit data register
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/UDRDR:
|
||||
description: Underrun Data Register
|
||||
fields:
|
||||
- name: UDRDR
|
||||
description: Data at slave underrun condition
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
enum/AFCNTR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotControlled
|
||||
description: Peripheral takes no control of GPIOs while disabled
|
||||
value: 0
|
||||
- name: Controlled
|
||||
description: Peripheral controls GPIOs while disabled
|
||||
value: 1
|
||||
enum/COMM:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: FullDuplex
|
||||
description: Full duplex
|
||||
value: 0
|
||||
- name: Transmitter
|
||||
description: Simplex transmitter only
|
||||
value: 1
|
||||
- name: Receiver
|
||||
description: Simplex receiver only
|
||||
value: 2
|
||||
- name: HalfDuplex
|
||||
description: Half duplex
|
||||
value: 3
|
||||
enum/CPHA:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: FirstEdge
|
||||
description: The first clock transition is the first data capture edge
|
||||
value: 0
|
||||
- name: SecondEdge
|
||||
description: The second clock transition is the first data capture edge
|
||||
value: 1
|
||||
enum/CPOL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: IdleLow
|
||||
description: CK to 0 when idle
|
||||
value: 0
|
||||
- name: IdleHigh
|
||||
description: CK to 1 when idle
|
||||
value: 1
|
||||
enum/CRC_:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Full size (33/17 bit) CRC polynomial is not used
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Full size (33/17 bit) CRC polynomial is used
|
||||
value: 1
|
||||
enum/DATFMT:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: RightAligned
|
||||
description: The data inside RXDR and TXDR are right aligned
|
||||
value: 0
|
||||
- name: LeftAligned
|
||||
description: The data inside RXDR and TXDR are left aligned
|
||||
value: 1
|
||||
enum/DATLEN:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Bits16
|
||||
description: 16 bit data length
|
||||
value: 0
|
||||
- name: Bits24
|
||||
description: 24 bit data length
|
||||
value: 1
|
||||
- name: Bits32
|
||||
description: 32 bit data length
|
||||
value: 2
|
||||
enum/FTHLV:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: OneFrame
|
||||
description: 1 frame
|
||||
value: 0
|
||||
- name: TwoFrames
|
||||
description: 2 frames
|
||||
value: 1
|
||||
- name: ThreeFrames
|
||||
description: 3 frames
|
||||
value: 2
|
||||
- name: FourFrames
|
||||
description: 4 frames
|
||||
value: 3
|
||||
- name: FiveFrames
|
||||
description: 5 frames
|
||||
value: 4
|
||||
- name: SixFrames
|
||||
description: 6 frames
|
||||
value: 5
|
||||
- name: SevenFrames
|
||||
description: 7 frames
|
||||
value: 6
|
||||
- name: EightFrames
|
||||
description: 8 frames
|
||||
value: 7
|
||||
- name: NineFrames
|
||||
description: 9 frames
|
||||
value: 8
|
||||
- name: TenFrames
|
||||
description: 10 frames
|
||||
value: 9
|
||||
- name: ElevenFrames
|
||||
description: 11 frames
|
||||
value: 10
|
||||
- name: TwelveFrames
|
||||
description: 12 frames
|
||||
value: 11
|
||||
- name: ThirteenFrames
|
||||
description: 13 frames
|
||||
value: 12
|
||||
- name: FourteenFrames
|
||||
description: 14 frames
|
||||
value: 13
|
||||
- name: FifteenFrames
|
||||
description: 15 frames
|
||||
value: 14
|
||||
- name: SixteenFrames
|
||||
description: 16 frames
|
||||
value: 15
|
||||
enum/HDDIR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Receiver
|
||||
description: Receiver in half duplex mode
|
||||
value: 0
|
||||
- name: Transmitter
|
||||
description: Transmitter in half duplex mode
|
||||
value: 1
|
||||
enum/LSBFIRST:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: MSBFirst
|
||||
description: Data is transmitted/received with the MSB first
|
||||
value: 0
|
||||
- name: LSBFirst
|
||||
description: Data is transmitted/received with the LSB first
|
||||
value: 1
|
||||
enum/MASTER:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Slave
|
||||
description: Slave configuration
|
||||
value: 0
|
||||
- name: Master
|
||||
description: Master configuration
|
||||
value: 1
|
||||
enum/MBR:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Div2
|
||||
description: f_spi_ker_ck / 2
|
||||
value: 0
|
||||
- name: Div4
|
||||
description: f_spi_ker_ck / 4
|
||||
value: 1
|
||||
- name: Div8
|
||||
description: f_spi_ker_ck / 8
|
||||
value: 2
|
||||
- name: Div16
|
||||
description: f_spi_ker_ck / 16
|
||||
value: 3
|
||||
- name: Div32
|
||||
description: f_spi_ker_ck / 32
|
||||
value: 4
|
||||
- name: Div64
|
||||
description: f_spi_ker_ck / 64
|
||||
value: 5
|
||||
- name: Div128
|
||||
description: f_spi_ker_ck / 128
|
||||
value: 6
|
||||
- name: Div256
|
||||
description: f_spi_ker_ck / 256
|
||||
value: 7
|
||||
enum/RCRCINI:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: AllZeros
|
||||
description: All zeros RX CRC initialization pattern
|
||||
value: 0
|
||||
- name: AllOnes
|
||||
description: All ones RX CRC initialization pattern
|
||||
value: 1
|
||||
enum/RDIOM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: PermanentlyActive
|
||||
description: RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)
|
||||
value: 0
|
||||
- name: FromInput
|
||||
description: RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)
|
||||
value: 1
|
||||
enum/RDIOP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: ReadyHigh
|
||||
description: high level of the signal means the slave is ready for communication
|
||||
value: 0
|
||||
- name: ReadyLow
|
||||
description: low level of the signal means the slave is ready for communication
|
||||
value: 1
|
||||
enum/RXPLVL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: ZeroFrames
|
||||
description: Zero frames beyond packing ratio available
|
||||
value: 0
|
||||
- name: OneFrame
|
||||
description: One frame beyond packing ratio available
|
||||
value: 1
|
||||
- name: TwoFrames
|
||||
description: Two frame beyond packing ratio available
|
||||
value: 2
|
||||
- name: ThreeFrames
|
||||
description: Three frame beyond packing ratio available
|
||||
value: 3
|
||||
enum/RXWNE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: LessThan32
|
||||
description: Less than 32-bit data frame received
|
||||
value: 0
|
||||
- name: AtLeast32
|
||||
description: At least 32-bit data frame received
|
||||
value: 1
|
||||
enum/SP:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Motorola
|
||||
description: Motorola SPI protocol
|
||||
value: 0
|
||||
- name: TI
|
||||
description: TI SPI protocol
|
||||
value: 1
|
||||
enum/SSIOP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: ActiveLow
|
||||
description: Low level is active for SS signal
|
||||
value: 0
|
||||
- name: ActiveHigh
|
||||
description: High level is active for SS signal
|
||||
value: 1
|
||||
enum/SSOM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Asserted
|
||||
description: SS is asserted until data transfer complete
|
||||
value: 0
|
||||
- name: NotAsserted
|
||||
description: Data frames interleaved with SS not asserted during MIDI
|
||||
value: 1
|
||||
enum/TCRCINI:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: AllZeros
|
||||
description: All zeros TX CRC initialization pattern
|
||||
value: 0
|
||||
- name: AllOnes
|
||||
description: All ones TX CRC initialization pattern
|
||||
value: 1
|
||||
enum/TRIGPOL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: RisingEdge
|
||||
description: trigger is active on raising edge
|
||||
value: 0
|
||||
- name: FallingEdge
|
||||
description: trigger is active on falling edge
|
||||
value: 1
|
||||
enum/UDRCFG:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Constant
|
||||
description: Slave sends a constant underrun pattern
|
||||
value: 0
|
||||
- name: RepeatReceived
|
||||
description: Slave repeats last received data frame from master
|
||||
value: 1
|
||||
- name: RepeatTransmitted
|
||||
description: Slave repeats last transmitted data frame
|
||||
value: 2
|
||||
@ -22,6 +22,27 @@ block/SYSCFG:
|
||||
byte_offset: 32
|
||||
access: Read
|
||||
fieldset: CMPCR
|
||||
fieldset/CMPCR:
|
||||
description: Compensation cell control register
|
||||
fields:
|
||||
- name: CMP_PD
|
||||
description: Compensation cell power-down
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: READY
|
||||
description: Compensation cell ready flag
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
fieldset/EXTICR:
|
||||
description: external interrupt configuration register 1
|
||||
fields:
|
||||
- name: EXTI
|
||||
description: EXTI x configuration (x = 0 to 3)
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
fieldset/MEMRMP:
|
||||
description: memory remap register
|
||||
fields:
|
||||
@ -37,27 +58,6 @@ fieldset/PMC:
|
||||
description: Ethernet PHY interface selection
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/EXTICR:
|
||||
description: external interrupt configuration register 1
|
||||
fields:
|
||||
- name: EXTI
|
||||
description: EXTI x configuration (x = 0 to 3)
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
fieldset/CMPCR:
|
||||
description: Compensation cell control register
|
||||
fields:
|
||||
- name: CMP_PD
|
||||
description: Compensation cell power-down
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: READY
|
||||
description: Compensation cell ready flag
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum/MEM_MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
|
||||
@ -242,7 +242,7 @@ fieldset/PWRCR:
|
||||
description: SYSCFG power control register
|
||||
fields:
|
||||
- name: ODEN
|
||||
description: " Overdrive enable"
|
||||
description: Overdrive enable
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
fieldset/UR0:
|
||||
|
||||
456
data/registers/syscfg_l5.yaml
Normal file
456
data/registers/syscfg_l5.yaml
Normal file
@ -0,0 +1,456 @@
|
||||
---
|
||||
block/SYSCFG:
|
||||
description: System configuration controller
|
||||
items:
|
||||
- name: SECCFGR
|
||||
description: SYSCFG secure configuration register
|
||||
byte_offset: 0
|
||||
fieldset: SECCFGR
|
||||
- name: CFGR1
|
||||
description: configuration register 1
|
||||
byte_offset: 4
|
||||
fieldset: CFGR1
|
||||
- name: FPUIMR
|
||||
description: FPU interrupt mask register
|
||||
byte_offset: 8
|
||||
fieldset: FPUIMR
|
||||
- name: CNSLCKR
|
||||
description: SYSCFG CPU non-secure lock register
|
||||
byte_offset: 12
|
||||
fieldset: CNSLCKR
|
||||
- name: CSLOCKR
|
||||
description: SYSCFG CPU secure lock register
|
||||
byte_offset: 16
|
||||
fieldset: CSLOCKR
|
||||
- name: CFGR2
|
||||
description: CFGR2
|
||||
byte_offset: 20
|
||||
fieldset: CFGR2
|
||||
- name: SCSR
|
||||
description: SCSR
|
||||
byte_offset: 24
|
||||
fieldset: SCSR
|
||||
- name: SKR
|
||||
description: SKR
|
||||
byte_offset: 28
|
||||
access: Write
|
||||
fieldset: SKR
|
||||
- name: SWPR
|
||||
description: SWPR
|
||||
byte_offset: 32
|
||||
access: Write
|
||||
fieldset: SWPR
|
||||
- name: SWPR2
|
||||
description: SWPR2
|
||||
byte_offset: 36
|
||||
access: Write
|
||||
fieldset: SWPR2
|
||||
- name: RSSCMDR
|
||||
description: RSSCMDR
|
||||
byte_offset: 44
|
||||
fieldset: RSSCMDR
|
||||
fieldset/CFGR1:
|
||||
description: configuration register 1
|
||||
fields:
|
||||
- name: BOOSTEN
|
||||
description: I/O analog switch voltage booster enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ANASWVDD
|
||||
description: GPIO analog switch control voltage selection
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: I2C_PB6_FMP
|
||||
description: Fast-mode Plus (Fm+) driving capability activation on PB6
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: I2C_PB7_FMP
|
||||
description: Fast-mode Plus (Fm+) driving capability activation on PB7
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: I2C_PB8_FMP
|
||||
description: Fast-mode Plus (Fm+) driving capability activation on PB8
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: I2C_PB9_FMP
|
||||
description: Fast-mode Plus (Fm+) driving capability activation on PB9
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: I2C1_FMP
|
||||
description: I2C1 Fast-mode Plus driving capability activation
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: I2C2_FMP
|
||||
description: I2C2 Fast-mode Plus driving capability activation
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C3_FMP
|
||||
description: I2C3 Fast-mode Plus driving capability activation
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C4_FMP
|
||||
description: I2C4_FMP
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/CFGR2:
|
||||
description: CFGR2
|
||||
fields:
|
||||
- name: CLL
|
||||
description: LOCKUP (hardfault) output enable bit
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SPL
|
||||
description: SRAM2 parity lock bit
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PVDL
|
||||
description: PVD lock enable bit
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: ECCL
|
||||
description: ECC Lock
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: SPF
|
||||
description: SRAM2 parity error flag
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
fieldset/CNSLCKR:
|
||||
description: SYSCFG CPU non-secure lock register
|
||||
fields:
|
||||
- name: LOCKNSVTOR
|
||||
description: VTOR_NS register lock
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: LOCKNSMPU
|
||||
description: Non-secure MPU registers lock
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
fieldset/CSLOCKR:
|
||||
description: SYSCFG CPU secure lock register
|
||||
fields:
|
||||
- name: LOCKSVTAIRCR
|
||||
description: LOCKSVTAIRCR
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: LOCKSMPU
|
||||
description: LOCKSMPU
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: LOCKSAU
|
||||
description: LOCKSAU
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
fieldset/FPUIMR:
|
||||
description: FPU interrupt mask register
|
||||
fields:
|
||||
- name: FPU_IE
|
||||
description: Floating point unit interrupts enable bits
|
||||
bit_offset: 0
|
||||
bit_size: 6
|
||||
fieldset/RSSCMDR:
|
||||
description: RSSCMDR
|
||||
fields:
|
||||
- name: RSSCMD
|
||||
description: RSS commands
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/SCSR:
|
||||
description: SCSR
|
||||
fields:
|
||||
- name: SRAM2ER
|
||||
description: SRAM2 Erase
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: SRAM2BSY
|
||||
description: SRAM2 busy by erase operation
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
fieldset/SECCFGR:
|
||||
description: SYSCFG secure configuration register
|
||||
fields:
|
||||
- name: SYSCFGSEC
|
||||
description: SYSCFG clock control security
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: CLASSBSEC
|
||||
description: ClassB security
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: SRAM2SEC
|
||||
description: SRAM2 security
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: FPUSEC
|
||||
description: FPUSEC
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
fieldset/SKR:
|
||||
description: SKR
|
||||
fields:
|
||||
- name: KEY
|
||||
description: SRAM2 write protection key for software erase
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/SWPR:
|
||||
description: SWPR
|
||||
fields:
|
||||
- name: P0WP
|
||||
description: P0WP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: P1WP
|
||||
description: P1WP
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: P2WP
|
||||
description: P2WP
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: P3WP
|
||||
description: P3WP
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: P4WP
|
||||
description: P4WP
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: P5WP
|
||||
description: P5WP
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: P6WP
|
||||
description: P6WP
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: P7WP
|
||||
description: P7WP
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: P8WP
|
||||
description: P8WP
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: P9WP
|
||||
description: P9WP
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: P10WP
|
||||
description: P10WP
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: P11WP
|
||||
description: P11WP
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: P12WP
|
||||
description: P12WP
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: P13WP
|
||||
description: P13WP
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: P14WP
|
||||
description: P14WP
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: P15WP
|
||||
description: P15WP
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: P16WP
|
||||
description: P16WP
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: P17WP
|
||||
description: P17WP
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: P18WP
|
||||
description: P18WP
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: P19WP
|
||||
description: P19WP
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: P20WP
|
||||
description: P20WP
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: P21WP
|
||||
description: P21WP
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: P22WP
|
||||
description: P22WP
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: P23WP
|
||||
description: P23WP
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: P24WP
|
||||
description: P24WP
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: P25WP
|
||||
description: P25WP
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: P26WP
|
||||
description: P26WP
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: P27WP
|
||||
description: P27WP
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: P28WP
|
||||
description: P28WP
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: P29WP
|
||||
description: P29WP
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: P30WP
|
||||
description: P30WP
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: P31WP
|
||||
description: SRAM2 page 31 write protection
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SWPR2:
|
||||
description: SWPR2
|
||||
fields:
|
||||
- name: P32WP
|
||||
description: P32WP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: P33WP
|
||||
description: P33WP
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: P34WP
|
||||
description: P34WP
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: P35WP
|
||||
description: P35WP
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: P36WP
|
||||
description: P36WP
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: P37WP
|
||||
description: P37WP
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: P38WP
|
||||
description: P38WP
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: P39WP
|
||||
description: P39WP
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: P40WP
|
||||
description: P40WP
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: P41WP
|
||||
description: P41WP
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: P42WP
|
||||
description: P42WP
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: P43WP
|
||||
description: P43WP
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: P44WP
|
||||
description: P44WP
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: P45WP
|
||||
description: P45WP
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: P46WP
|
||||
description: P46WP
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: P47WP
|
||||
description: P47WP
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: P48WP
|
||||
description: P48WP
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: P49WP
|
||||
description: P49WP
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: P50WP
|
||||
description: P50WP
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: P51WP
|
||||
description: P51WP
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: P52WP
|
||||
description: P52WP
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: P53WP
|
||||
description: P53WP
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: P54WP
|
||||
description: P54WP
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: P55WP
|
||||
description: P55WP
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: P56WP
|
||||
description: P56WP
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: P57WP
|
||||
description: P57WP
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: P58WP
|
||||
description: P58WP
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: P59WP
|
||||
description: P59WP
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: P60WP
|
||||
description: P60WP
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: P61WP
|
||||
description: P61WP
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: P62WP
|
||||
description: P62WP
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: P63WP
|
||||
description: P63WP
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
@ -1000,6 +1000,9 @@ enum/TS:
|
||||
- name: ITR2
|
||||
description: Internal Trigger 2 (ITR2)
|
||||
value: 2
|
||||
- name: ITR3
|
||||
description: Internal Trigger 3 (ITR3)
|
||||
value: 3
|
||||
- name: TI1F_ED
|
||||
description: TI1 Edge Detector (TI1F_ED)
|
||||
value: 4
|
||||
|
||||
257
data/registers/usb_v1.yaml
Normal file
257
data/registers/usb_v1.yaml
Normal file
@ -0,0 +1,257 @@
|
||||
---
|
||||
block/USB:
|
||||
description: Universal serial bus full-speed device interface
|
||||
items:
|
||||
- name: EPR
|
||||
description: endpoint register
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
byte_offset: 0
|
||||
fieldset: EPR
|
||||
- name: CNTR
|
||||
description: control register
|
||||
byte_offset: 64
|
||||
fieldset: CNTR
|
||||
- name: ISTR
|
||||
description: interrupt status register
|
||||
byte_offset: 68
|
||||
fieldset: ISTR
|
||||
- name: FNR
|
||||
description: frame number register
|
||||
byte_offset: 72
|
||||
access: Read
|
||||
fieldset: FNR
|
||||
- name: DADDR
|
||||
description: device address
|
||||
byte_offset: 76
|
||||
fieldset: DADDR
|
||||
- name: BTABLE
|
||||
description: Buffer table address
|
||||
byte_offset: 80
|
||||
fieldset: BTABLE
|
||||
fieldset/BTABLE:
|
||||
description: Buffer table address
|
||||
fields:
|
||||
- name: BTABLE
|
||||
description: BTABLE
|
||||
bit_offset: 3
|
||||
bit_size: 13
|
||||
fieldset/CNTR:
|
||||
description: control register
|
||||
fields:
|
||||
- name: FRES
|
||||
description: "Force a reset of the USB peripheral, exactly like a RESET signaling on the USB"
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PDWN
|
||||
description: Enter power down mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: LPMODE
|
||||
description: Enter low-power mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: FSUSP
|
||||
description: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: RESUME
|
||||
description: Resume request
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: ESOFM
|
||||
description: "ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: SOFM
|
||||
description: "SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RESETM
|
||||
description: "RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: SUSPM
|
||||
description: "SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: WKUPM
|
||||
description: "WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: ERRM
|
||||
description: "ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: PMAOVRM
|
||||
description: "PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: CTRM
|
||||
description: "CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
fieldset/DADDR:
|
||||
description: device address
|
||||
fields:
|
||||
- name: ADD
|
||||
description: device address
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: EF
|
||||
description: USB device enabled
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
fieldset/EPR:
|
||||
description: endpoint register
|
||||
fields:
|
||||
- name: EA
|
||||
description: EA
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: STAT_TX
|
||||
description: STAT_TX
|
||||
bit_offset: 4
|
||||
bit_size: 2
|
||||
enum: STAT
|
||||
- name: DTOG_TX
|
||||
description: DTOG_TX
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: CTR_TX
|
||||
description: CTR_TX
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: EP_KIND
|
||||
description: EP_KIND
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: EP_TYPE
|
||||
description: EPTYPE
|
||||
bit_offset: 9
|
||||
bit_size: 2
|
||||
enum: EP_TYPE
|
||||
- name: SETUP
|
||||
description: SETUP
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: STAT_RX
|
||||
description: STAT_RX
|
||||
bit_offset: 12
|
||||
bit_size: 2
|
||||
enum: STAT
|
||||
- name: DTOG_RX
|
||||
description: DTOG_RX
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: CTR_RX
|
||||
description: CTR_RX
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
fieldset/FNR:
|
||||
description: frame number register
|
||||
fields:
|
||||
- name: FN
|
||||
description: FN
|
||||
bit_offset: 0
|
||||
bit_size: 11
|
||||
- name: LSOF
|
||||
description: LSOF
|
||||
bit_offset: 11
|
||||
bit_size: 2
|
||||
- name: LCK
|
||||
description: the frame timer remains in this state until an USB reset or USB suspend event occurs
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: RXDM
|
||||
description: received data minus upstream port data line
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: RXDP
|
||||
description: received data plus upstream port data line
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
fieldset/ISTR:
|
||||
description: interrupt status register
|
||||
fields:
|
||||
- name: EP_ID
|
||||
description: EP_ID
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: DIR
|
||||
description: DIR
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: DIR
|
||||
- name: ESOF
|
||||
description: an SOF packet is expected but not received
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: SOF
|
||||
description: beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RESET
|
||||
description: peripheral detects an active USB RESET signal at its inputs
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: SUSP
|
||||
description: "no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus"
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: WKUP
|
||||
description: activity is detected that wakes up the USB peripheral
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: ERR
|
||||
description: "One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred"
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: PMAOVR
|
||||
description: microcontroller has not been able to respond in time to an USB memory request
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: CTR
|
||||
description: endpoint has successfully completed a transaction
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum/DIR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: To
|
||||
description: data transmitted by the USB peripheral to the host PC
|
||||
value: 0
|
||||
- name: From
|
||||
description: data received by the USB peripheral from the host PC
|
||||
value: 1
|
||||
enum/EP_TYPE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Bulk
|
||||
description: Bulk endpoint
|
||||
value: 0
|
||||
- name: Control
|
||||
description: Control endpoint
|
||||
value: 1
|
||||
- name: Iso
|
||||
description: Iso endpoint
|
||||
value: 2
|
||||
- name: Interrupt
|
||||
description: Interrupt endpoint
|
||||
value: 3
|
||||
enum/STAT:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: all requests addressed to this endpoint are ignored
|
||||
value: 0
|
||||
- name: Stall
|
||||
description: the endpoint is stalled and all requests result in a STALL handshake
|
||||
value: 1
|
||||
- name: Nak
|
||||
description: the endpoint is naked and all requests result in a NAK handshake
|
||||
value: 2
|
||||
- name: Valid
|
||||
description: this endpoint is enabled, requests are ACKed
|
||||
value: 3
|
||||
355
data/registers/usb_v2.yaml
Normal file
355
data/registers/usb_v2.yaml
Normal file
@ -0,0 +1,355 @@
|
||||
---
|
||||
block/USB:
|
||||
description: Universal serial bus full-speed device interface
|
||||
items:
|
||||
- name: EPR
|
||||
description: endpoint register
|
||||
array:
|
||||
len: 8
|
||||
stride: 4
|
||||
byte_offset: 0
|
||||
fieldset: EPR
|
||||
- name: CNTR
|
||||
description: control register
|
||||
byte_offset: 64
|
||||
fieldset: CNTR
|
||||
- name: ISTR
|
||||
description: interrupt status register
|
||||
byte_offset: 68
|
||||
fieldset: ISTR
|
||||
- name: FNR
|
||||
description: frame number register
|
||||
byte_offset: 72
|
||||
access: Read
|
||||
fieldset: FNR
|
||||
- name: DADDR
|
||||
description: device address
|
||||
byte_offset: 76
|
||||
fieldset: DADDR
|
||||
- name: BTABLE
|
||||
description: Buffer table address
|
||||
byte_offset: 80
|
||||
fieldset: BTABLE
|
||||
- name: LPMCSR
|
||||
description: LPM control and status register
|
||||
byte_offset: 84
|
||||
fieldset: LPMCSR
|
||||
- name: BCDR
|
||||
description: Battery Charging Detector
|
||||
byte_offset: 88
|
||||
fieldset: BCDR
|
||||
fieldset/BCDR:
|
||||
description: Battery Charging Detector
|
||||
fields:
|
||||
- name: BCDEN
|
||||
description: Battery charging detector mode enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DCDEN
|
||||
description: Data contact detection mode enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: PDEN
|
||||
description: Primary detection mode enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: SDEN
|
||||
description: Secondary detection mode enable
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: DCDET
|
||||
description: Data contact detection status
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: PDET
|
||||
description: Primary detection status
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: SDET
|
||||
description: Secondary detection status
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
enum: SDET
|
||||
- name: PS2DET
|
||||
description: DM pull-up detection status
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: DPPU
|
||||
description: DP pull-up control
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
fieldset/BTABLE:
|
||||
description: Buffer table address
|
||||
fields:
|
||||
- name: BTABLE
|
||||
description: BTABLE
|
||||
bit_offset: 3
|
||||
bit_size: 13
|
||||
fieldset/CNTR:
|
||||
description: control register
|
||||
fields:
|
||||
- name: FRES
|
||||
description: "Force a reset of the USB peripheral, exactly like a RESET signaling on the USB"
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: PDWN
|
||||
description: Enter power down mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: LPMODE
|
||||
description: Enter low-power mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: FSUSP
|
||||
description: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: RESUME
|
||||
description: Resume request
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: L1RESUME
|
||||
description: LPM L1 request request
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: L1REQM
|
||||
description: "L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: ESOFM
|
||||
description: "ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: SOFM
|
||||
description: "SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RESETM
|
||||
description: "RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: SUSPM
|
||||
description: "SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: WKUPM
|
||||
description: "WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: ERRM
|
||||
description: "ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: PMAOVRM
|
||||
description: "PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: CTRM
|
||||
description: "CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
fieldset/DADDR:
|
||||
description: device address
|
||||
fields:
|
||||
- name: ADD
|
||||
description: device address
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: EF
|
||||
description: USB device enabled
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
fieldset/EPR:
|
||||
description: endpoint register
|
||||
fields:
|
||||
- name: EA
|
||||
description: EA
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: STAT_TX
|
||||
description: STAT_TX
|
||||
bit_offset: 4
|
||||
bit_size: 2
|
||||
enum: STAT
|
||||
- name: DTOG_TX
|
||||
description: DTOG_TX
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: CTR_TX
|
||||
description: CTR_TX
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: EP_KIND
|
||||
description: EP_KIND
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: EP_TYPE
|
||||
description: EPTYPE
|
||||
bit_offset: 9
|
||||
bit_size: 2
|
||||
enum: EP_TYPE
|
||||
- name: SETUP
|
||||
description: SETUP
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: STAT_RX
|
||||
description: STAT_RX
|
||||
bit_offset: 12
|
||||
bit_size: 2
|
||||
enum: STAT
|
||||
- name: DTOG_RX
|
||||
description: DTOG_RX
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: CTR_RX
|
||||
description: CTR_RX
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
fieldset/FNR:
|
||||
description: frame number register
|
||||
fields:
|
||||
- name: FN
|
||||
description: FN
|
||||
bit_offset: 0
|
||||
bit_size: 11
|
||||
- name: LSOF
|
||||
description: LSOF
|
||||
bit_offset: 11
|
||||
bit_size: 2
|
||||
- name: LCK
|
||||
description: the frame timer remains in this state until an USB reset or USB suspend event occurs
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: RXDM
|
||||
description: received data minus upstream port data line
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: RXDP
|
||||
description: received data plus upstream port data line
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
fieldset/ISTR:
|
||||
description: interrupt status register
|
||||
fields:
|
||||
- name: EP_ID
|
||||
description: EP_ID
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: DIR
|
||||
description: DIR
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: DIR
|
||||
- name: L1REQ
|
||||
description: LPM command to enter the L1 state is successfully received and acknowledged
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: ESOF
|
||||
description: an SOF packet is expected but not received
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: SOF
|
||||
description: beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RESET
|
||||
description: peripheral detects an active USB RESET signal at its inputs
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: SUSP
|
||||
description: "no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus"
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: WKUP
|
||||
description: activity is detected that wakes up the USB peripheral
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: ERR
|
||||
description: "One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred"
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: PMAOVR
|
||||
description: microcontroller has not been able to respond in time to an USB memory request
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: CTR
|
||||
description: endpoint has successfully completed a transaction
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
fieldset/LPMCSR:
|
||||
description: LPM control and status register
|
||||
fields:
|
||||
- name: LPMEN
|
||||
description: enable the LPM support within the USB device
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: LPMACK
|
||||
description: LPMACK
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
enum: LPMACK
|
||||
- name: REMWAKE
|
||||
description: REMWAKE
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: BESL
|
||||
description: BESL
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
enum/DIR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: To
|
||||
description: data transmitted by the USB peripheral to the host PC
|
||||
value: 0
|
||||
- name: From
|
||||
description: data received by the USB peripheral from the host PC
|
||||
value: 1
|
||||
enum/EP_TYPE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Bulk
|
||||
description: Bulk endpoint
|
||||
value: 0
|
||||
- name: Control
|
||||
description: Control endpoint
|
||||
value: 1
|
||||
- name: Iso
|
||||
description: Iso endpoint
|
||||
value: 2
|
||||
- name: Interrupt
|
||||
description: Interrupt endpoint
|
||||
value: 3
|
||||
enum/LPMACK:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Nyet
|
||||
description: the valid LPM Token will be NYET
|
||||
value: 0
|
||||
- name: Ack
|
||||
description: the valid LPM Token will be ACK
|
||||
value: 1
|
||||
enum/SDET:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: CDP
|
||||
description: CDP detected
|
||||
value: 0
|
||||
- name: DCP
|
||||
description: DCP detected
|
||||
value: 1
|
||||
enum/STAT:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: all requests addressed to this endpoint are ignored
|
||||
value: 0
|
||||
- name: Stall
|
||||
description: the endpoint is stalled and all requests result in a STALL handshake
|
||||
value: 1
|
||||
- name: Nak
|
||||
description: the endpoint is naked and all requests result in a NAK handshake
|
||||
value: 2
|
||||
- name: Valid
|
||||
description: this endpoint is enabled, requests are ACKed
|
||||
value: 3
|
||||
@ -105,6 +105,7 @@ perimap = [
|
||||
('.*:RNG:rng1_v2_1', ('rng', 'v1', 'RNG')),
|
||||
('.*:RNG:rng1_v3_1', ('rng', 'v1', 'RNG')),
|
||||
('.*:SPI:spi2_v1_4', ('spi', 'f1', 'SPI')),
|
||||
('.*:SPI:spi2s1_v2_1', ('spi', 'v1', 'SPI')),
|
||||
('.*:SPI:spi2s1_v2_2', ('spi', 'v1', 'SPI')),
|
||||
('.*:SPI:spi2s1_v3_2', ('spi', 'v2', 'SPI')),
|
||||
('.*:SPI:spi2s1_v3_3', ('spi', 'v2', 'SPI')),
|
||||
@ -113,30 +114,39 @@ perimap = [
|
||||
('.*:SPI:spi2s1_v3_1', ('spi', 'v2', 'SPI')),
|
||||
('.*:SPI:spi2s2_v1_1', ('spi', 'v3', 'SPI')),
|
||||
('.*:SPI:spi2s2_v1_0', ('spi', 'v3', 'SPI')),
|
||||
('.*:SPI:spi2s3_v1_1', ('spi', 'v4', 'SPI')),
|
||||
('.*:I2C:i2c1_v1_5', ('i2c', 'v1', 'I2C')),
|
||||
('.*:I2C:i2c2_v1_1', ('i2c', 'v2', 'I2C')),
|
||||
('.*:I2C:i2c2_v1_1F7', ('i2c', 'v2', 'I2C')),
|
||||
('.*:I2C:i2c2_v1_1U5', ('i2c', 'v2', 'I2C')),
|
||||
|
||||
('.*:DAC:dacif_v1_1', ('dac', 'v1', 'DAC')),
|
||||
('.*:DAC:dacif_v2_0', ('dac', 'v2', 'DAC')),
|
||||
('.*:DAC:dacif_v3_0', ('dac', 'v2', 'DAC')),
|
||||
|
||||
('.*:ADC:aditf_v2_5F1', ('adc', 'f1', 'ADC')),
|
||||
('.*:ADC:aditf4_v1_1', ('adc', 'v1', 'ADC')),
|
||||
('.*:ADC:aditf2_v1_1', ('adc', 'v2', 'ADC')),
|
||||
('.*:ADC:aditf5_v2_0', ('adc', 'v3', 'ADC')),
|
||||
('.*:ADC:aditf5_v3_0', ('adc', 'v4', 'ADC')),
|
||||
('STM32G0.*:ADC:.*', ('adc', 'g0', 'ADC')),
|
||||
('STM32G0.*:ADC_COMMON:.*', ('adccommon', 'v3', 'ADC_COMMON')),
|
||||
('.*:ADC_COMMON:aditf2_v1_1', ('adccommon', 'v2', 'ADC_COMMON')),
|
||||
('.*:ADC_COMMON:aditf5_v2_0', ('adccommon', 'v3', 'ADC_COMMON')),
|
||||
('.*:ADC_COMMON:aditf4_v3_0_WL', ('adccommon', 'v3', 'ADC_COMMON')),
|
||||
('STM32H7.*:ADC_COMMON:.*', ('adccommon', 'v4', 'ADC_COMMON')),
|
||||
('STM32H7.*:ADC3_COMMON:.*', ('adccommon', 'v4', 'ADC_COMMON')),
|
||||
|
||||
('.*:DCMI:.*', ('dcmi', 'v1', 'DCMI')),
|
||||
('STM32F0.*:SYSCFG:.*', ('syscfg', 'f0', 'SYSCFG')),
|
||||
('STM32F2.*:SYSCFG:.*', ('syscfg', 'f2', 'SYSCFG')),
|
||||
('STM32F3.*:SYSCFG:.*', ('syscfg', 'f3', 'SYSCFG')),
|
||||
('STM32F4.*:SYSCFG:.*', ('syscfg', 'f4', 'SYSCFG')),
|
||||
('STM32F7.*:SYSCFG:.*', ('syscfg', 'f7', 'SYSCFG')),
|
||||
('STM32L4.*:SYSCFG:.*', ('syscfg', 'l4', 'SYSCFG')),
|
||||
('STM32L0.*:SYSCFG:.*', ('syscfg', 'l0', 'SYSCFG')),
|
||||
('STM32L1.*:SYSCFG:.*', ('syscfg', 'l1', 'SYSCFG')),
|
||||
('STM32L4.*:SYSCFG:.*', ('syscfg', 'l4', 'SYSCFG')),
|
||||
('STM32L5.*:SYSCFG:.*', ('syscfg', 'l5', 'SYSCFG')),
|
||||
('STM32G0.*:SYSCFG:.*', ('syscfg', 'g0', 'SYSCFG')),
|
||||
('STM32G4.*:SYSCFG:.*', ('syscfg', 'g4', 'SYSCFG')),
|
||||
('STM32H7.*:SYSCFG:.*', ('syscfg', 'h7', 'SYSCFG')),
|
||||
@ -159,12 +169,18 @@ perimap = [
|
||||
('.*:SDIO:sdmmc_v1_2', ('sdmmc', 'v1', 'SDMMC')),
|
||||
('.*:SDMMC:sdmmc_v1_3', ('sdmmc', 'v1', 'SDMMC')),
|
||||
('.*:SPDIFRX:spdifrx1_v1_0', ('spdifrx', 'v1', 'SPDIFRX')),
|
||||
|
||||
# USB
|
||||
('STM32(F1|L1|F3).*:USB:.*', ('usb', 'v1', 'USB')),
|
||||
('.*:USB:.*', ('usb', 'v2', 'USB')),
|
||||
('.*:USB_OTG_FS:otgfs1_v1_.*', ('otgfs', 'v1', 'OTG_FS')),
|
||||
('.*:USB_OTG_FS:otgfs1_v3_.*', ('otgfs', 'v3', 'OTG_FS')),
|
||||
('.*:USB_OTG_FS:otgfs1_v3_.*', ('otgfs', 'v1', 'OTG_FS')),
|
||||
('.*:USB_OTG_HS:otghs1_v1_.*', ('otghs', 'v1', 'OTG_HS')),
|
||||
|
||||
('STM32F0.*:RCC:.*', ('rcc', 'f0', 'RCC')),
|
||||
('STM32F1.*:RCC:.*', ('rcc', 'f1', 'RCC')),
|
||||
('STM32F100.*:RCC:.*', ('rcc', 'f100', 'RCC')),
|
||||
('STM32F10[123].*:RCC:.*', ('rcc', 'f1', 'RCC')),
|
||||
('STM32F10[57].*:RCC:.*', ('rcc', 'f1cl', 'RCC')),
|
||||
('STM32F2.*:RCC:.*', ('rcc', 'f2', 'RCC')),
|
||||
('STM32F3.*:RCC:.*', ('rcc', 'f3', 'RCC')),
|
||||
('STM32F410.*:RCC:.*', ('rcc', 'f410', 'RCC')),
|
||||
@ -208,6 +224,8 @@ perimap = [
|
||||
('STM32F4.*:PWR:.*', ('pwr', 'f4', 'PWR')),
|
||||
('STM32F7.*:PWR:.*', ('pwr', 'f7', 'PWR')),
|
||||
('STM32L1.*:PWR:.*', ('pwr', 'l1', 'PWR')),
|
||||
('STM32L4.*:PWR:.*', ('pwr', 'l4', 'PWR')),
|
||||
('STM32L5.*:PWR:.*', ('pwr', 'l5', 'PWR')),
|
||||
('STM32U5.*:PWR:.*', ('pwr', 'u5', 'PWR')),
|
||||
('STM32WL.*:PWR:.*', ('pwr', 'wl5', 'PWR')),
|
||||
('STM32WB.*:PWR:.*', ('pwr', 'wb55', 'PWR')),
|
||||
@ -218,11 +236,16 @@ perimap = [
|
||||
('STM32F3.*:FLASH:.*', ('flash', 'f3', 'FLASH')),
|
||||
('STM32F4.*:FLASH:.*', ('flash', 'f4', 'FLASH')),
|
||||
('STM32F7.*:FLASH:.*', ('flash', 'f7', 'FLASH')),
|
||||
('STM32L0[0-9]2.*:FLASH:.*', ('flash', 'l0', 'FLASH')),
|
||||
('STM32L1.*:FLASH:.*', ('flash', 'l1', 'FLASH')),
|
||||
('STM32L4.*:FLASH:.*', ('flash', 'l4', 'FLASH')),
|
||||
('STM32L5.*:FLASH:.*', ('flash', 'l5', 'FLASH')),
|
||||
('STM32U5.*:FLASH:.*', ('flash', 'u5', 'FLASH')),
|
||||
('STM32WB.*:FLASH:.*', ('flash', 'wb55', 'FLASH')),
|
||||
('STM32WB.*:FLASH:.*', ('flash', 'wb', 'FLASH')),
|
||||
('STM32WL.*:FLASH:.*', ('flash', 'wl', 'FLASH')),
|
||||
('STM32G0.*:FLASH:.*', ('flash', 'g0', 'FLASH')),
|
||||
('STM32F107.*:ETH:.*', ('eth', 'v1a', 'ETH')),
|
||||
('STM32F[24].*:ETH:.*', ('eth', 'v1b', 'ETH')),
|
||||
('STM32F7.*:ETH:ETH:ethermac110_v2_0', ('eth', 'v1c', 'ETH')),
|
||||
('.*ETH:ethermac110_v3_0', ('eth', 'v2', 'ETH')),
|
||||
|
||||
@ -269,6 +292,7 @@ perimap = [
|
||||
('.*:IPCC:v1_0', ('ipcc', 'v1', 'IPCC')),
|
||||
('.*:DMAMUX.*', ('dmamux', 'v1', 'DMAMUX')),
|
||||
|
||||
('.*:GPDMA\d?:.*', ('gpdma', 'v1', 'GPDMA')),
|
||||
('.*:BDMA\d?:.*', ('bdma', 'v1', 'DMA')),
|
||||
('STM32H7.*:DMA2D:DMA2D:dma2d1_v1_0', ('dma2d', 'v2', 'DMA2D')),
|
||||
('.*:DMA2D:dma2d1_v1_0', ('dma2d', 'v1', 'DMA2D')),
|
||||
@ -671,6 +695,9 @@ def parse_chips():
|
||||
if pname.startswith('ADC'):
|
||||
if not 'ADC_COMMON' in peri_kinds:
|
||||
peri_kinds['ADC_COMMON'] = 'ADC_COMMON:' + removesuffix(ip['@Version'], '_Cube')
|
||||
if pname.startswith('ADC3'):
|
||||
if chip_name.startswith("STM32H7") and not 'ADC_COMMON3' in peri_kinds:
|
||||
peri_kinds['ADC3_COMMON'] = 'ADC3_COMMON:' + removesuffix(ip['@Version'], '_Cube')
|
||||
|
||||
peri_kinds[pname] = pkind
|
||||
|
||||
@ -758,12 +785,11 @@ def parse_chips():
|
||||
|
||||
# Collect DMA versions in the chip
|
||||
chip_dmas = []
|
||||
for want_kind in ('DMA', 'BDMA', 'BDMA1', 'BDMA2'):
|
||||
for ip in chip['ips'].values():
|
||||
pkind = ip['@Name']
|
||||
version = ip['@Version']
|
||||
if pkind == want_kind and version in dma_channels and version not in chip_dmas:
|
||||
chip_dmas.append(version)
|
||||
for ip in chip['ips'].values():
|
||||
pkind = ip['@Name']
|
||||
version = ip['@Version']
|
||||
if pkind in ('DMA', 'BDMA', 'BDMA1', 'BDMA2', 'GPDMA') and version in dma_channels and version not in chip_dmas:
|
||||
chip_dmas.append(version)
|
||||
|
||||
# Process DMA channels
|
||||
chs = []
|
||||
@ -829,6 +855,7 @@ def parse_chips():
|
||||
'kind': 'flash',
|
||||
'address': h['defines']['all'][each + '_BASE'],
|
||||
'size': size,
|
||||
'settings': memory.determine_flash_settings(chip_name),
|
||||
})
|
||||
|
||||
found = set()
|
||||
@ -1167,6 +1194,42 @@ def parse_dma():
|
||||
|
||||
dma_channels[ff] = chip_dma
|
||||
|
||||
# STM32U5
|
||||
|
||||
chip_dma = {
|
||||
'channels': [],
|
||||
'peripherals': {},
|
||||
}
|
||||
|
||||
with open('data/dmamux/U5_GPDMA1.yaml', 'r') as yaml_file:
|
||||
y = yaml.load(yaml_file)
|
||||
|
||||
for (request_name, request_num) in y.items():
|
||||
parts = request_name.split('_')
|
||||
target_peri_name = parts[0]
|
||||
if len(parts) < 2:
|
||||
request = target_peri_name
|
||||
else:
|
||||
request = parts[1]
|
||||
chip_dma['peripherals'].setdefault(target_peri_name, []).append({
|
||||
'signal': request,
|
||||
"dma": 'GPDMA1',
|
||||
"request": request_num,
|
||||
})
|
||||
|
||||
for i in range(16):
|
||||
chip_dma['channels'].append({
|
||||
'name': 'GPDMA1_CH' + str(i),
|
||||
'dma': 'GPDMA1',
|
||||
'channel': i,
|
||||
'supports_2d': i >= 12,
|
||||
})
|
||||
|
||||
ff = 'STM32U5_dma3_Cube'
|
||||
with open('tmp/dmas/' + ff + '.json', 'w') as f:
|
||||
json.dump(chip_dma, f, indent=4)
|
||||
dma_channels[ff] = chip_dma
|
||||
|
||||
|
||||
peripheral_to_clock = {}
|
||||
|
||||
@ -1207,7 +1270,7 @@ def parse_rcc_regs():
|
||||
'field': field['name'],
|
||||
}
|
||||
}
|
||||
if rstr := y[key.replace('ENR', 'RSTR')]:
|
||||
if rstr := y.get(key.replace('ENR', 'RSTR')):
|
||||
if field := next(filter(lambda f: f['name'] == f'{peri}RST', rstr['fields']), None):
|
||||
res['reset'] = {
|
||||
'register': reg.replace('ENR', 'RSTR'),
|
||||
|
||||
@ -45,13 +45,16 @@ memories = []
|
||||
|
||||
def parse():
|
||||
for f in sorted(glob('sources/cubeprogdb/db/*.xml')):
|
||||
#print("parsing ", f);
|
||||
# print("parsing ", f);
|
||||
device = xmltodict.parse(open(f, 'rb'))['Root']['Device']
|
||||
device_id = device['DeviceID']
|
||||
name = device['Name']
|
||||
names = split_names(name)
|
||||
flash_size = None
|
||||
flash_addr = None
|
||||
write_size = None
|
||||
erase_size = None
|
||||
erase_value = None
|
||||
ram_size = None
|
||||
ram_addr = None
|
||||
|
||||
@ -69,7 +72,20 @@ def parse():
|
||||
configs = [configs]
|
||||
flash_addr = int(configs[0]['Parameters']['@address'], 16)
|
||||
flash_size = int(configs[0]['Parameters']['@size'], 16)
|
||||
#print( f'flash {addr} {size}')
|
||||
erase_value = int(peripheral['ErasedValue'], 16)
|
||||
write_size = int(configs[0]['Allignement'], 16)
|
||||
bank = configs[0]['Bank']
|
||||
if type(bank) != list:
|
||||
bank = [bank]
|
||||
fields = bank[0]['Field']
|
||||
if type(fields) != list:
|
||||
fields = [fields]
|
||||
|
||||
erase_size = int(fields[0]['Parameters']['@size'], 16)
|
||||
for field in fields:
|
||||
# print("Field", field)
|
||||
erase_size = max(erase_size, int(field['Parameters']['@size'], 16))
|
||||
#print( f'flash {addr} {size}')
|
||||
|
||||
chunk = {
|
||||
'device-id': int(device_id, 16),
|
||||
@ -86,6 +102,9 @@ def parse():
|
||||
chunk['flash'] = {
|
||||
'address': flash_addr,
|
||||
'bytes': flash_size,
|
||||
'erase_value': erase_value,
|
||||
'write_size': write_size,
|
||||
'erase_size': erase_size,
|
||||
}
|
||||
|
||||
memories.append(chunk)
|
||||
@ -108,6 +127,18 @@ def determine_flash_size(chip_name):
|
||||
|
||||
return None
|
||||
|
||||
def determine_flash_settings(chip_name):
|
||||
for each in memories:
|
||||
for name in each['names']:
|
||||
if is_chip_name_match(name, chip_name):
|
||||
return {
|
||||
'erase_size': each['flash']['erase_size'],
|
||||
'write_size': each['flash']['write_size'],
|
||||
'erase_value': each['flash']['erase_value'],
|
||||
}
|
||||
|
||||
return None
|
||||
|
||||
|
||||
def determine_device_id(chip_name):
|
||||
for each in memories:
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user