1191 lines
28 KiB
YAML
1191 lines
28 KiB
YAML
---
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block/FSMC:
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description: Flexible memory controller
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items:
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- name: BCR1
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description: SRAM/NOR-Flash chip-select control register 1
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byte_offset: 0
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fieldset: BCR
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- name: BTR1
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description: SRAM/NOR-Flash chip-select timing register 1
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byte_offset: 4
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fieldset: BTR
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- name: BCR2
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description: SRAM/NOR-Flash chip-select control register 2
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byte_offset: 8
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fieldset: BCR
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- name: BTR2
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description: SRAM/NOR-Flash chip-select timing register 2
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byte_offset: 12
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fieldset: BTR
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- name: BCR3
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description: SRAM/NOR-Flash chip-select control register 3
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byte_offset: 16
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fieldset: BCR
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- name: BTR3
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description: SRAM/NOR-Flash chip-select timing register 3
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byte_offset: 20
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fieldset: BTR
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- name: BCR4
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description: SRAM/NOR-Flash chip-select control register 4
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byte_offset: 24
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fieldset: BCR
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- name: BTR4
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description: SRAM/NOR-Flash chip-select timing register 4
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byte_offset: 28
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fieldset: BTR
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- name: PCR2
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description: PC Card/NAND Flash control register 2
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byte_offset: 96
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fieldset: PCR
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- name: SR2
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description: FIFO status and interrupt register 2
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byte_offset: 100
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fieldset: SR
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- name: PMEM2
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description: Common memory space timing register 2
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byte_offset: 104
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fieldset: PMEM
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- name: PATT2
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description: Attribute memory space timing register 2
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byte_offset: 108
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fieldset: PATT
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- name: ECCR2
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description: ECC result register 2
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byte_offset: 116
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access: Read
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fieldset: ECCR
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- name: PCR3
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description: PC Card/NAND Flash control register 3
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byte_offset: 128
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fieldset: PCR
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- name: SR3
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description: FIFO status and interrupt register 3
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byte_offset: 132
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fieldset: SR
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- name: PMEM3
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description: Common memory space timing register 3
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byte_offset: 136
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fieldset: PMEM
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- name: PATT3
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description: Attribute memory space timing register 3
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byte_offset: 140
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fieldset: PATT
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- name: ECCR3
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description: ECC result register 3
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byte_offset: 148
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access: Read
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fieldset: ECCR
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- name: PCR4
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description: PC Card/NAND Flash control register 4
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byte_offset: 160
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fieldset: PCR
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- name: SR4
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description: FIFO status and interrupt register 4
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byte_offset: 164
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fieldset: SR
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- name: PMEM4
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description: Common memory space timing register 4
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byte_offset: 168
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fieldset: PMEM
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- name: PATT4
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description: Attribute memory space timing register 4
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byte_offset: 172
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fieldset: PATT
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- name: PIO4
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description: I/O space timing register 4
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byte_offset: 176
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fieldset: PIO
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- name: BWTR1
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description: SRAM/NOR-Flash write timing registers 1
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byte_offset: 260
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fieldset: BWTR
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- name: BWTR2
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description: SRAM/NOR-Flash write timing registers 2
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byte_offset: 268
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fieldset: BWTR
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- name: BWTR3
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description: SRAM/NOR-Flash write timing registers 3
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byte_offset: 276
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fieldset: BWTR
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- name: BWTR4
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description: SRAM/NOR-Flash write timing registers 4
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byte_offset: 284
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fieldset: BWTR
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- name: SDCR1
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description: SDRAM Control Register 1
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byte_offset: 320
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fieldset: SDCR
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- name: SDCR2
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description: SDRAM Control Register 2
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byte_offset: 324
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fieldset: SDCR
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- name: SDTR1
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description: SDRAM Timing register 1
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byte_offset: 328
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fieldset: SDTR
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- name: SDTR2
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description: SDRAM Timing register 2
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byte_offset: 332
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fieldset: SDTR
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- name: SDCMR
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description: SDRAM Command Mode register
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byte_offset: 336
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fieldset: SDCMR
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- name: SDRTR
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description: SDRAM Refresh Timer register
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byte_offset: 340
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fieldset: SDRTR
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- name: SDSR
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description: SDRAM Status register
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byte_offset: 344
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access: Read
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fieldset: SDSR
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fieldset/BCR:
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description: SRAM/NOR-Flash chip-select control register
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fields:
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- name: MBKEN
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description: MBKEN
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bit_offset: 0
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bit_size: 1
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enum: BCR_MBKEN
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- name: MUXEN
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description: MUXEN
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bit_offset: 1
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bit_size: 1
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enum: BCR_MUXEN
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- name: MTYP
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description: MTYP
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bit_offset: 2
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bit_size: 2
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enum: BCR_MTYP
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- name: MWID
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description: MWID
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bit_offset: 4
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bit_size: 2
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enum: BCR_MWID
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- name: FACCEN
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description: FACCEN
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bit_offset: 6
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bit_size: 1
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enum: BCR_FACCEN
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- name: BURSTEN
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description: BURSTEN
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bit_offset: 8
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bit_size: 1
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enum: BCR_BURSTEN
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- name: WAITPOL
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description: WAITPOL
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bit_offset: 9
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bit_size: 1
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enum: BCR_WAITPOL
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- name: WRAPMOD
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description: WRAPMOD
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bit_offset: 10
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bit_size: 1
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- name: WAITCFG
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description: WAITCFG
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bit_offset: 11
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bit_size: 1
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enum: BCR_WAITCFG
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- name: WREN
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description: WREN
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bit_offset: 12
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bit_size: 1
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enum: BCR_WREN
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- name: WAITEN
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description: WAITEN
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bit_offset: 13
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bit_size: 1
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enum: BCR_WAITEN
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- name: EXTMOD
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description: EXTMOD
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bit_offset: 14
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bit_size: 1
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enum: BCR_EXTMOD
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- name: ASYNCWAIT
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description: ASYNCWAIT
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bit_offset: 15
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bit_size: 1
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enum: BCR_ASYNCWAIT
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- name: CPSIZE
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description: CPSIZE
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bit_offset: 16
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bit_size: 3
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enum: BCR_CPSIZE
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- name: CBURSTRW
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description: CBURSTRW
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bit_offset: 19
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bit_size: 1
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enum: BCR_CBURSTRW
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- name: CCLKEN
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description: CCLKEN
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bit_offset: 20
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bit_size: 1
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fieldset/BTR:
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description: SRAM/NOR-Flash chip-select timing register
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fields:
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- name: ADDSET
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description: ADDSET
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bit_offset: 0
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bit_size: 4
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- name: ADDHLD
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description: ADDHLD
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bit_offset: 4
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bit_size: 4
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- name: DATAST
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description: DATAST
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bit_offset: 8
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bit_size: 8
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- name: BUSTURN
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description: BUSTURN
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bit_offset: 16
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bit_size: 4
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- name: CLKDIV
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description: CLKDIV
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bit_offset: 20
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bit_size: 4
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- name: DATLAT
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description: DATLAT
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bit_offset: 24
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bit_size: 4
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- name: ACCMOD
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description: ACCMOD
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bit_offset: 28
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bit_size: 2
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enum: BTR_ACCMOD
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fieldset/BWTR:
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description: SRAM/NOR-Flash write timing register
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fields:
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- name: ADDSET
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description: ADDSET
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bit_offset: 0
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bit_size: 4
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- name: ADDHLD
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description: ADDHLD
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bit_offset: 4
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bit_size: 4
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- name: DATAST
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description: DATAST
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bit_offset: 8
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bit_size: 8
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- name: BUSTURN
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description: BUSTURN
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bit_offset: 16
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bit_size: 4
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- name: CLKDIV
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description: CLKDIV
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bit_offset: 20
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bit_size: 4
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- name: ACCMOD
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description: ACCMOD
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bit_offset: 28
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bit_size: 2
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enum: BWTR_ACCMOD
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fieldset/ECCR:
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description: ECC result register
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fields:
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- name: ECC
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description: ECCx
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bit_offset: 0
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bit_size: 32
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fieldset/PATT:
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description: Attribute memory space timing register
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fields:
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- name: ATTSET
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description: ATTSETx
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bit_offset: 0
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bit_size: 8
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- name: ATTWAIT
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description: ATTWAITx
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bit_offset: 8
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bit_size: 8
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- name: ATTHOLD
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description: ATTHOLDx
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bit_offset: 16
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bit_size: 8
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- name: ATTHIZ
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description: ATTHIZx
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bit_offset: 24
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bit_size: 8
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fieldset/PCR:
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description: PC Card/NAND Flash control register
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fields:
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- name: PWAITEN
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description: PWAITEN
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bit_offset: 1
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bit_size: 1
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enum: PWAITEN
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- name: PBKEN
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description: PBKEN
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bit_offset: 2
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bit_size: 1
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enum: PBKEN
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- name: PTYP
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description: PTYP
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bit_offset: 3
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bit_size: 1
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enum: PTYP
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- name: PWID
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description: PWID
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bit_offset: 4
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bit_size: 2
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enum: PWID
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- name: ECCEN
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description: ECCEN
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bit_offset: 6
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bit_size: 1
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enum: ECCEN
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- name: TCLR
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description: TCLR
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bit_offset: 9
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bit_size: 4
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- name: TAR
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description: TAR
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bit_offset: 13
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bit_size: 4
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- name: ECCPS
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description: ECCPS
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bit_offset: 17
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bit_size: 3
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enum: ECCPS
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fieldset/PIO:
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description: I/O space timing register
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fields:
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- name: IOSETx
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description: IOSETx
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bit_offset: 0
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bit_size: 8
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- name: IOWAITx
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description: IOWAITx
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bit_offset: 8
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bit_size: 8
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- name: IOHOLDx
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description: IOHOLDx
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bit_offset: 16
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bit_size: 8
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- name: IOHIZx
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description: IOHIZx
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bit_offset: 24
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bit_size: 8
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fieldset/PMEM:
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description: Common memory space timing register
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fields:
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- name: MEMSET
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description: MEMSETx
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bit_offset: 0
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bit_size: 8
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- name: MEMWAIT
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description: MEMWAITx
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bit_offset: 8
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bit_size: 8
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- name: MEMHOLD
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description: MEMHOLDx
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bit_offset: 16
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bit_size: 8
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- name: MEMHIZ
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description: MEMHIZx
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bit_offset: 24
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bit_size: 8
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fieldset/SDCMR:
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description: SDRAM Command Mode register
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fields:
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- name: MODE
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description: Command mode
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bit_offset: 0
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bit_size: 3
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enum: MODE
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- name: CTB2
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description: Command target bank 2
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bit_offset: 3
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bit_size: 1
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enum: CTB2
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- name: CTB1
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description: Command target bank 1
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bit_offset: 4
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bit_size: 1
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enum: CTB2
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- name: NRFS
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description: Number of Auto-refresh
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bit_offset: 5
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bit_size: 4
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- name: MRD
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description: Mode Register definition
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bit_offset: 9
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bit_size: 13
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fieldset/SDCR:
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description: SDRAM Control Register
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fields:
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- name: NC
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description: Number of column address bits
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bit_offset: 0
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bit_size: 2
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enum: NC
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- name: NR
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description: Number of row address bits
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bit_offset: 2
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bit_size: 2
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enum: NR
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- name: MWID
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description: Memory data bus width
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bit_offset: 4
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bit_size: 2
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enum: SDCR_MWID
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- name: NB
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description: Number of internal banks
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bit_offset: 6
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bit_size: 1
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enum: NB
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- name: CAS
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description: CAS latency
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bit_offset: 7
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bit_size: 2
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enum: CAS
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- name: WP
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description: Write protection
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bit_offset: 9
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bit_size: 1
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enum: WP
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- name: SDCLK
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description: SDRAM clock configuration
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bit_offset: 10
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bit_size: 2
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enum: SDCLK
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- name: RBURST
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description: Burst read
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bit_offset: 12
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bit_size: 1
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enum: RBURST
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- name: RPIPE
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description: Read pipe
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bit_offset: 13
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bit_size: 2
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enum: RPIPE
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fieldset/SDRTR:
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description: SDRAM Refresh Timer register
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fields:
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- name: CRE
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description: Clear Refresh error flag
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bit_offset: 0
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bit_size: 1
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enum: CRE
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- name: COUNT
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description: Refresh Timer Count
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bit_offset: 1
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bit_size: 13
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- name: REIE
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description: RES Interrupt Enable
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bit_offset: 14
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bit_size: 1
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enum: REIE
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fieldset/SDSR:
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description: SDRAM Status register
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fields:
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- name: RE
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description: Refresh error flag
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bit_offset: 0
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bit_size: 1
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enum: RE
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- name: MODES1
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description: Status Mode for Bank 1
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bit_offset: 1
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bit_size: 2
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enum: MODES1
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- name: MODES2
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description: Status Mode for Bank 2
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bit_offset: 3
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bit_size: 2
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enum: MODES1
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- name: BUSY
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description: Busy status
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bit_offset: 5
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bit_size: 1
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enum: BUSY
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fieldset/SDTR:
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description: SDRAM Timing register
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fields:
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- name: TMRD
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description: Load Mode Register to Active
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bit_offset: 0
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bit_size: 4
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- name: TXSR
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description: Exit self-refresh delay
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bit_offset: 4
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bit_size: 4
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- name: TRAS
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description: Self refresh time
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bit_offset: 8
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bit_size: 4
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- name: TRC
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description: Row cycle delay
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bit_offset: 12
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bit_size: 4
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- name: TWR
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description: Recovery delay
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bit_offset: 16
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bit_size: 4
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- name: TRP
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description: Row precharge delay
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bit_offset: 20
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bit_size: 4
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- name: TRCD
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description: Row to column delay
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bit_offset: 24
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bit_size: 4
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fieldset/SR:
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description: FIFO status and interrupt register
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fields:
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- name: IRS
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description: IRS
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bit_offset: 0
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bit_size: 1
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enum: IRS
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- name: ILS
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description: ILS
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bit_offset: 1
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bit_size: 1
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enum: ILS
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- name: IFS
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description: IFS
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bit_offset: 2
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bit_size: 1
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enum: IFS
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- name: IREN
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description: IREN
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bit_offset: 3
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bit_size: 1
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enum: IREN
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- name: ILEN
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description: ILEN
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bit_offset: 4
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bit_size: 1
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enum: ILEN
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- name: IFEN
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description: IFEN
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bit_offset: 5
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bit_size: 1
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enum: IFEN
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- name: FEMPT
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description: FEMPT
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bit_offset: 6
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bit_size: 1
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enum: FEMPT
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enum/BCR1_ASYNCWAIT:
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bit_size: 1
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variants:
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- name: Disabled
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description: Wait signal not used in asynchronous mode
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value: 0
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- name: Enabled
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description: Wait signal used even in asynchronous mode
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value: 1
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enum/BCR1_BURSTEN:
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bit_size: 1
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variants:
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- name: Disabled
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description: Burst mode disabled
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value: 0
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- name: Enabled
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description: Burst mode enabled
|
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value: 1
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enum/BCR1_CBURSTRW:
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bit_size: 1
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variants:
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- name: Disabled
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description: Write operations are always performed in asynchronous mode
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value: 0
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- name: Enabled
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description: Write operations are performed in synchronous mode
|
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value: 1
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enum/BCR1_CPSIZE:
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bit_size: 3
|
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variants:
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|
- name: NoBurstSplit
|
|
description: No burst split when crossing page boundary
|
|
value: 0
|
|
- name: Bytes128
|
|
description: 128 bytes CRAM page size
|
|
value: 1
|
|
- name: Bytes256
|
|
description: 256 bytes CRAM page size
|
|
value: 2
|
|
- name: Bytes512
|
|
description: 512 bytes CRAM page size
|
|
value: 3
|
|
- name: Bytes1024
|
|
description: 1024 bytes CRAM page size
|
|
value: 4
|
|
enum/BCR1_EXTMOD:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Values inside the FMC_BWTR are not taken into account
|
|
value: 0
|
|
- name: Enabled
|
|
description: Values inside the FMC_BWTR are taken into account
|
|
value: 1
|
|
enum/BCR1_FACCEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Corresponding NOR Flash memory access is disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Corresponding NOR Flash memory access is enabled
|
|
value: 1
|
|
enum/BCR1_MBKEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Corresponding memory bank is disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Corresponding memory bank is enabled
|
|
value: 1
|
|
enum/BCR1_MTYP:
|
|
bit_size: 2
|
|
variants:
|
|
- name: SRAM
|
|
description: SRAM memory type
|
|
value: 0
|
|
- name: PSRAM
|
|
description: PSRAM (CRAM) memory type
|
|
value: 1
|
|
- name: Flash
|
|
description: NOR Flash/OneNAND Flash
|
|
value: 2
|
|
enum/BCR1_MUXEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Address/Data non-multiplexed
|
|
value: 0
|
|
- name: Enabled
|
|
description: Address/Data multiplexed on databus
|
|
value: 1
|
|
enum/BCR1_MWID:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Bits8
|
|
description: Memory data bus width 8 bits
|
|
value: 0
|
|
- name: Bits16
|
|
description: Memory data bus width 16 bits
|
|
value: 1
|
|
- name: Bits32
|
|
description: Memory data bus width 32 bits
|
|
value: 2
|
|
enum/BCR1_WAITCFG:
|
|
bit_size: 1
|
|
variants:
|
|
- name: BeforeWaitState
|
|
description: NWAIT signal is active one data cycle before wait state
|
|
value: 0
|
|
- name: DuringWaitState
|
|
description: NWAIT signal is active during wait state
|
|
value: 1
|
|
enum/BCR1_WAITEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Values inside the FMC_BWTR are taken into account
|
|
value: 0
|
|
- name: Enabled
|
|
description: NWAIT signal enabled
|
|
value: 1
|
|
enum/BCR1_WAITPOL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: ActiveLow
|
|
description: NWAIT active low
|
|
value: 0
|
|
- name: ActiveHigh
|
|
description: NWAIT active high
|
|
value: 1
|
|
enum/BCR1_WREN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Write operations disabled for the bank by the FMC
|
|
value: 0
|
|
- name: Enabled
|
|
description: Write operations enabled for the bank by the FMC
|
|
value: 1
|
|
enum/BCR_ASYNCWAIT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Wait signal not used in asynchronous mode
|
|
value: 0
|
|
- name: Enabled
|
|
description: Wait signal used even in asynchronous mode
|
|
value: 1
|
|
enum/BCR_BURSTEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Burst mode disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Burst mode enabled
|
|
value: 1
|
|
enum/BCR_CBURSTRW:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Write operations are always performed in asynchronous mode
|
|
value: 0
|
|
- name: Enabled
|
|
description: Write operations are performed in synchronous mode
|
|
value: 1
|
|
enum/BCR_CPSIZE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: NoBurstSplit
|
|
description: No burst split when crossing page boundary
|
|
value: 0
|
|
- name: Bytes128
|
|
description: 128 bytes CRAM page size
|
|
value: 1
|
|
- name: Bytes256
|
|
description: 256 bytes CRAM page size
|
|
value: 2
|
|
- name: Bytes512
|
|
description: 512 bytes CRAM page size
|
|
value: 3
|
|
- name: Bytes1024
|
|
description: 1024 bytes CRAM page size
|
|
value: 4
|
|
enum/BCR_EXTMOD:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Values inside the FMC_BWTR are not taken into account
|
|
value: 0
|
|
- name: Enabled
|
|
description: Values inside the FMC_BWTR are taken into account
|
|
value: 1
|
|
enum/BCR_FACCEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Corresponding NOR Flash memory access is disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Corresponding NOR Flash memory access is enabled
|
|
value: 1
|
|
enum/BCR_MBKEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Corresponding memory bank is disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Corresponding memory bank is enabled
|
|
value: 1
|
|
enum/BCR_MTYP:
|
|
bit_size: 2
|
|
variants:
|
|
- name: SRAM
|
|
description: SRAM memory type
|
|
value: 0
|
|
- name: PSRAM
|
|
description: PSRAM (CRAM) memory type
|
|
value: 1
|
|
- name: Flash
|
|
description: NOR Flash/OneNAND Flash
|
|
value: 2
|
|
enum/BCR_MUXEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Address/Data non-multiplexed
|
|
value: 0
|
|
- name: Enabled
|
|
description: Address/Data multiplexed on databus
|
|
value: 1
|
|
enum/BCR_MWID:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Bits8
|
|
description: Memory data bus width 8 bits
|
|
value: 0
|
|
- name: Bits16
|
|
description: Memory data bus width 16 bits
|
|
value: 1
|
|
- name: Bits32
|
|
description: Memory data bus width 32 bits
|
|
value: 2
|
|
enum/BCR_WAITCFG:
|
|
bit_size: 1
|
|
variants:
|
|
- name: BeforeWaitState
|
|
description: NWAIT signal is active one data cycle before wait state
|
|
value: 0
|
|
- name: DuringWaitState
|
|
description: NWAIT signal is active during wait state
|
|
value: 1
|
|
enum/BCR_WAITEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Values inside the FMC_BWTR are taken into account
|
|
value: 0
|
|
- name: Enabled
|
|
description: NWAIT signal enabled
|
|
value: 1
|
|
enum/BCR_WAITPOL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: ActiveLow
|
|
description: NWAIT active low
|
|
value: 0
|
|
- name: ActiveHigh
|
|
description: NWAIT active high
|
|
value: 1
|
|
enum/BCR_WREN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Write operations disabled for the bank by the FMC
|
|
value: 0
|
|
- name: Enabled
|
|
description: Write operations enabled for the bank by the FMC
|
|
value: 1
|
|
enum/BTR_ACCMOD:
|
|
bit_size: 2
|
|
variants:
|
|
- name: A
|
|
description: Access mode A
|
|
value: 0
|
|
- name: B
|
|
description: Access mode B
|
|
value: 1
|
|
- name: C
|
|
description: Access mode C
|
|
value: 2
|
|
- name: D
|
|
description: Access mode D
|
|
value: 3
|
|
enum/BUSY:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotBusy
|
|
description: SDRAM Controller is ready to accept a new request
|
|
value: 0
|
|
- name: Busy
|
|
description: SDRAM Controller is not ready to accept a new request
|
|
value: 1
|
|
enum/BWTR_ACCMOD:
|
|
bit_size: 2
|
|
variants:
|
|
- name: A
|
|
description: Access mode A
|
|
value: 0
|
|
- name: B
|
|
description: Access mode B
|
|
value: 1
|
|
- name: C
|
|
description: Access mode C
|
|
value: 2
|
|
- name: D
|
|
description: Access mode D
|
|
value: 3
|
|
enum/CAS:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Clocks1
|
|
description: 1 cycle
|
|
value: 1
|
|
- name: Clocks2
|
|
description: 2 cycles
|
|
value: 2
|
|
- name: Clocks3
|
|
description: 3 cycles
|
|
value: 3
|
|
enum/CRE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: Refresh Error Flag is cleared
|
|
value: 1
|
|
enum/CTB2:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotIssued
|
|
description: Command not issued to SDRAM Bank 1
|
|
value: 0
|
|
- name: Issued
|
|
description: Command issued to SDRAM Bank 1
|
|
value: 1
|
|
enum/ECCEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: ECC logic is disabled and reset
|
|
value: 0
|
|
- name: Enabled
|
|
description: ECC logic is enabled
|
|
value: 1
|
|
enum/ECCPS:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Bytes256
|
|
description: ECC page size 256 bytes
|
|
value: 0
|
|
- name: Bytes512
|
|
description: ECC page size 512 bytes
|
|
value: 1
|
|
- name: Bytes1024
|
|
description: ECC page size 1024 bytes
|
|
value: 2
|
|
- name: Bytes2048
|
|
description: ECC page size 2048 bytes
|
|
value: 3
|
|
- name: Bytes4096
|
|
description: ECC page size 4096 bytes
|
|
value: 4
|
|
- name: Bytes8192
|
|
description: ECC page size 8192 bytes
|
|
value: 5
|
|
enum/FEMPT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotEmpty
|
|
description: FIFO not empty
|
|
value: 0
|
|
- name: Empty
|
|
description: FIFO empty
|
|
value: 1
|
|
enum/IFEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Interrupt falling edge detection request disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Interrupt falling edge detection request enabled
|
|
value: 1
|
|
enum/IFS:
|
|
bit_size: 1
|
|
variants:
|
|
- name: DidNotOccur
|
|
description: Interrupt falling edge did not occur
|
|
value: 0
|
|
- name: Occurred
|
|
description: Interrupt falling edge occurred
|
|
value: 1
|
|
enum/ILEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Interrupt high-level detection request disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Interrupt high-level detection request enabled
|
|
value: 1
|
|
enum/ILS:
|
|
bit_size: 1
|
|
variants:
|
|
- name: DidNotOccur
|
|
description: Interrupt high-level did not occur
|
|
value: 0
|
|
- name: Occurred
|
|
description: Interrupt high-level occurred
|
|
value: 1
|
|
enum/IREN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Interrupt rising edge detection request disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Interrupt rising edge detection request enabled
|
|
value: 1
|
|
enum/IRS:
|
|
bit_size: 1
|
|
variants:
|
|
- name: DidNotOccur
|
|
description: Interrupt rising edge did not occur
|
|
value: 0
|
|
- name: Occurred
|
|
description: Interrupt rising edge occurred
|
|
value: 1
|
|
enum/MODE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Normal
|
|
description: Normal Mode
|
|
value: 0
|
|
- name: ClockConfigurationEnable
|
|
description: Clock Configuration Enable
|
|
value: 1
|
|
- name: PALL
|
|
description: PALL (All Bank Precharge) command
|
|
value: 2
|
|
- name: AutoRefreshCommand
|
|
description: Auto-refresh command
|
|
value: 3
|
|
- name: LoadModeRegister
|
|
description: Load Mode Resgier
|
|
value: 4
|
|
- name: SelfRefreshCommand
|
|
description: Self-refresh command
|
|
value: 5
|
|
- name: PowerDownCommand
|
|
description: Power-down command
|
|
value: 6
|
|
enum/MODES1:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Normal
|
|
description: Normal Mode
|
|
value: 0
|
|
- name: SelfRefresh
|
|
description: Self-refresh mode
|
|
value: 1
|
|
- name: PowerDown
|
|
description: Power-down mode
|
|
value: 2
|
|
enum/NB:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NB2
|
|
description: Two internal Banks
|
|
value: 0
|
|
- name: NB4
|
|
description: Four internal Banks
|
|
value: 1
|
|
enum/NC:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Bits8
|
|
description: 8 bits
|
|
value: 0
|
|
- name: Bits9
|
|
description: 9 bits
|
|
value: 1
|
|
- name: Bits10
|
|
description: 10 bits
|
|
value: 2
|
|
- name: Bits11
|
|
description: 11 bits
|
|
value: 3
|
|
enum/NR:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Bits11
|
|
description: 11 bits
|
|
value: 0
|
|
- name: Bits12
|
|
description: 12 bits
|
|
value: 1
|
|
- name: Bits13
|
|
description: 13 bits
|
|
value: 2
|
|
enum/PBKEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Corresponding memory bank is disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Corresponding memory bank is enabled
|
|
value: 1
|
|
enum/PTYP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NANDFlash
|
|
description: NAND Flash
|
|
value: 1
|
|
enum/PWAITEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Wait feature disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Wait feature enabled
|
|
value: 1
|
|
enum/PWID:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Bits8
|
|
description: External memory device width 8 bits
|
|
value: 0
|
|
- name: Bits16
|
|
description: External memory device width 16 bits
|
|
value: 1
|
|
enum/RBURST:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Single read requests are not managed as bursts
|
|
value: 0
|
|
- name: Enabled
|
|
description: Single read requests are always managed as bursts
|
|
value: 1
|
|
enum/RE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoError
|
|
description: No refresh error has been detected
|
|
value: 0
|
|
- name: Error
|
|
description: A refresh error has been detected
|
|
value: 1
|
|
enum/REIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Interrupt is disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Interrupt is generated if RE = 1
|
|
value: 1
|
|
enum/RPIPE:
|
|
bit_size: 2
|
|
variants:
|
|
- name: NoDelay
|
|
description: No clock cycle delay
|
|
value: 0
|
|
- name: Clocks1
|
|
description: One clock cycle delay
|
|
value: 1
|
|
- name: Clocks2
|
|
description: Two clock cycles delay
|
|
value: 2
|
|
enum/SDCLK:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Disabled
|
|
description: SDCLK clock disabled
|
|
value: 0
|
|
- name: Div2
|
|
description: SDCLK period = 2 x HCLK period
|
|
value: 2
|
|
- name: Div3
|
|
description: SDCLK period = 3 x HCLK period
|
|
value: 3
|
|
enum/SDCR_MWID:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Bits8
|
|
description: Memory data bus width 8 bits
|
|
value: 0
|
|
- name: Bits16
|
|
description: Memory data bus width 16 bits
|
|
value: 1
|
|
- name: Bits32
|
|
description: Memory data bus width 32 bits
|
|
value: 2
|
|
enum/WP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Write accesses allowed
|
|
value: 0
|
|
- name: Enabled
|
|
description: Write accesses ignored
|
|
value: 1
|