From 62ebc483f9d2d275f5c5fe92607f46b1bc890ca6 Mon Sep 17 00:00:00 2001 From: Philip A Reimer Date: Mon, 28 Mar 2022 22:34:25 -0600 Subject: [PATCH 01/35] use otg v1 for v3 --- data/registers/otgfs_v3.yaml | 598 ----------------------------------- stm32data/__main__.py | 2 +- 2 files changed, 1 insertion(+), 599 deletions(-) delete mode 100644 data/registers/otgfs_v3.yaml diff --git a/data/registers/otgfs_v3.yaml b/data/registers/otgfs_v3.yaml deleted file mode 100644 index 9323360..0000000 --- a/data/registers/otgfs_v3.yaml +++ /dev/null @@ -1,598 +0,0 @@ ---- -block/OTG_FS: - description: USB on the go full speed - items: - - name: GOTGCTL - description: Control and status register - byte_offset: 0 - fieldset: GOTGCTL - - name: GOTGINT - description: Interrupt register - byte_offset: 4 - fieldset: GOTGINT - - name: GAHBCFG - description: AHB configuration register - byte_offset: 8 - fieldset: GAHBCFG - - name: GUSBCFG - description: USB configuration register - byte_offset: 12 - fieldset: GUSBCFG - - name: GRSTCTL - description: Reset register - byte_offset: 16 - fieldset: GRSTCTL - - name: GINTSTS - description: Core interrupt register - byte_offset: 20 - fieldset: GINTSTS - - name: GINTMSK - description: Interrupt mask register - byte_offset: 24 - fieldset: GINTMSK - - name: GRXSTSR_Device - description: Receive status debug read (Device mode) - byte_offset: 28 - access: Read - fieldset: GRXSTSR_Device - - name: GRXSTSR_Host - description: Receive status debug read (Host mode) - byte_offset: 28 - access: Read - fieldset: GRXSTSR_Host - - name: GRXSTSP_Device - description: Status read and pop (Device mode) - byte_offset: 32 - access: Read - fieldset: GRXSTSP_Device - - name: GRXSTSP_Host - description: Status read and pop (Host mode) - byte_offset: 32 - access: Read - fieldset: GRXSTSP_Host - - name: GRXFSIZ - description: Receive FIFO size register - byte_offset: 36 - fieldset: GRXFSIZ - - name: DIEPTXF0 - description: Non-periodic transmit FIFO size register (Device mode) - byte_offset: 40 - fieldset: DIEPTXF0 - - name: HNPTXFSIZ - description: Non-periodic transmit FIFO size register (Host mode) - byte_offset: 40 - fieldset: HNPTXFSIZ - - name: GNPTXSTS - description: Non-periodic transmit FIFO/queue status register - byte_offset: 44 - access: Read - fieldset: GNPTXSTS - - name: GCCFG - description: General core configuration register - byte_offset: 56 - fieldset: GCCFG - - name: CID - description: Core ID register - byte_offset: 60 - fieldset: CID - - name: HPTXFSIZ - description: Host periodic transmit FIFO size register - byte_offset: 256 - fieldset: HPTXFSIZ - - name: DIEPTXF - description: Device IN endpoint transmit FIFO size register - array: - len: 3 - stride: 4 - byte_offset: 260 - fieldset: DIEPTXF -fieldset/CID: - description: Core ID register - fields: - - name: PRODUCT_ID - description: Product ID field - bit_offset: 0 - bit_size: 32 -fieldset/DIEPTXF: - description: Device IN endpoint transmit FIFO size register - fields: - - name: INEPTXSA - description: IN endpoint FIFO2 transmit RAM start address - bit_offset: 0 - bit_size: 16 - - name: INEPTXFD - description: IN endpoint TxFIFO depth - bit_offset: 16 - bit_size: 16 -fieldset/DIEPTXF0: - description: Non-periodic transmit FIFO size register (Device mode) - fields: - - name: TX0FSA - description: Endpoint 0 transmit RAM start address - bit_offset: 0 - bit_size: 16 - - name: TX0FD - description: Endpoint 0 TxFIFO depth - bit_offset: 16 - bit_size: 16 -fieldset/GAHBCFG: - description: AHB configuration register - fields: - - name: GINT - description: Global interrupt mask - bit_offset: 0 - bit_size: 1 - - name: TXFELVL - description: TxFIFO empty level - bit_offset: 7 - bit_size: 1 - - name: PTXFELVL - description: Periodic TxFIFO empty level - bit_offset: 8 - bit_size: 1 -fieldset/GCCFG: - description: General core configuration register - fields: - - name: PWRDWN - description: Power down - bit_offset: 16 - bit_size: 1 - - name: VBUSASEN - description: Enable the VBUS sensing device - bit_offset: 18 - bit_size: 1 - - name: VBUSBSEN - description: Enable the VBUS sensing device - bit_offset: 19 - bit_size: 1 - - name: SOFOUTEN - description: SOF output enable - bit_offset: 20 - bit_size: 1 -fieldset/GINTMSK: - description: Interrupt mask register - fields: - - name: MMISM - description: Mode mismatch interrupt mask - bit_offset: 1 - bit_size: 1 - - name: OTGINT - description: OTG interrupt mask - bit_offset: 2 - bit_size: 1 - - name: SOFM - description: Start of frame mask - bit_offset: 3 - bit_size: 1 - - name: RXFLVLM - description: Receive FIFO non-empty mask - bit_offset: 4 - bit_size: 1 - - name: NPTXFEM - description: Non-periodic TxFIFO empty mask - bit_offset: 5 - bit_size: 1 - - name: GINAKEFFM - description: Global non-periodic IN NAK effective mask - bit_offset: 6 - bit_size: 1 - - name: GONAKEFFM - description: Global OUT NAK effective mask - bit_offset: 7 - bit_size: 1 - - name: ESUSPM - description: Early suspend mask - bit_offset: 10 - bit_size: 1 - - name: USBSUSPM - description: USB suspend mask - bit_offset: 11 - bit_size: 1 - - name: USBRST - description: USB reset mask - bit_offset: 12 - bit_size: 1 - - name: ENUMDNEM - description: Enumeration done mask - bit_offset: 13 - bit_size: 1 - - name: ISOODRPM - description: Isochronous OUT packet dropped interrupt mask - bit_offset: 14 - bit_size: 1 - - name: EOPFM - description: End of periodic frame interrupt mask - bit_offset: 15 - bit_size: 1 - - name: IEPINT - description: IN endpoints interrupt mask - bit_offset: 18 - bit_size: 1 - - name: OEPINT - description: OUT endpoints interrupt mask - bit_offset: 19 - bit_size: 1 - - name: IISOIXFRM - description: Incomplete isochronous IN transfer mask - bit_offset: 20 - bit_size: 1 - - name: IPXFRM_IISOOXFRM - description: Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) - bit_offset: 21 - bit_size: 1 - - name: PRTIM - description: Host port interrupt mask - bit_offset: 24 - bit_size: 1 - - name: HCIM - description: Host channels interrupt mask - bit_offset: 25 - bit_size: 1 - - name: PTXFEM - description: Periodic TxFIFO empty mask - bit_offset: 26 - bit_size: 1 - - name: CIDSCHGM - description: Connector ID status change mask - bit_offset: 28 - bit_size: 1 - - name: DISCINT - description: Disconnect detected interrupt mask - bit_offset: 29 - bit_size: 1 - - name: SRQIM - description: Session request/new session detected interrupt mask - bit_offset: 30 - bit_size: 1 - - name: WUIM - description: Resume/remote wakeup detected interrupt mask - bit_offset: 31 - bit_size: 1 -fieldset/GINTSTS: - description: Core interrupt register - fields: - - name: CMOD - description: Current mode of operation - bit_offset: 0 - bit_size: 1 - - name: MMIS - description: Mode mismatch interrupt - bit_offset: 1 - bit_size: 1 - - name: OTGINT - description: OTG interrupt - bit_offset: 2 - bit_size: 1 - - name: SOF - description: Start of frame - bit_offset: 3 - bit_size: 1 - - name: RXFLVL - description: RxFIFO non-empty - bit_offset: 4 - bit_size: 1 - - name: NPTXFE - description: Non-periodic TxFIFO empty - bit_offset: 5 - bit_size: 1 - - name: GINAKEFF - description: Global IN non-periodic NAK effective - bit_offset: 6 - bit_size: 1 - - name: GOUTNAKEFF - description: Global OUT NAK effective - bit_offset: 7 - bit_size: 1 - - name: ESUSP - description: Early suspend - bit_offset: 10 - bit_size: 1 - - name: USBSUSP - description: USB suspend - bit_offset: 11 - bit_size: 1 - - name: USBRST - description: USB reset - bit_offset: 12 - bit_size: 1 - - name: ENUMDNE - description: Enumeration done - bit_offset: 13 - bit_size: 1 - - name: ISOODRP - description: Isochronous OUT packet dropped interrupt - bit_offset: 14 - bit_size: 1 - - name: EOPF - description: End of periodic frame interrupt - bit_offset: 15 - bit_size: 1 - - name: IEPINT - description: IN endpoint interrupt - bit_offset: 18 - bit_size: 1 - - name: OEPINT - description: OUT endpoint interrupt - bit_offset: 19 - bit_size: 1 - - name: IISOIXFR - description: Incomplete isochronous IN transfer - bit_offset: 20 - bit_size: 1 - - name: IPXFR_INCOMPISOOUT - description: Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) - bit_offset: 21 - bit_size: 1 - - name: HPRTINT - description: Host port interrupt - bit_offset: 24 - bit_size: 1 - - name: HCINT - description: Host channels interrupt - bit_offset: 25 - bit_size: 1 - - name: PTXFE - description: Periodic TxFIFO empty - bit_offset: 26 - bit_size: 1 - - name: CIDSCHG - description: Connector ID status change - bit_offset: 28 - bit_size: 1 - - name: DISCINT - description: Disconnect detected interrupt - bit_offset: 29 - bit_size: 1 - - name: SRQINT - description: Session request/new session detected interrupt - bit_offset: 30 - bit_size: 1 - - name: WKUPINT - description: Resume/remote wakeup detected interrupt - bit_offset: 31 - bit_size: 1 -fieldset/GOTGCTL: - description: Control and status register - fields: - - name: SRQSCS - description: Session request success - bit_offset: 0 - bit_size: 1 - - name: SRQ - description: Session request - bit_offset: 1 - bit_size: 1 - - name: HNGSCS - description: Host negotiation success - bit_offset: 8 - bit_size: 1 - - name: HNPRQ - description: HNP request - bit_offset: 9 - bit_size: 1 - - name: HSHNPEN - description: Host set HNP enable - bit_offset: 10 - bit_size: 1 - - name: DHNPEN - description: Device HNP enabled - bit_offset: 11 - bit_size: 1 - - name: CIDSTS - description: Connector ID status - bit_offset: 16 - bit_size: 1 - - name: DBCT - description: Long/short debounce time - bit_offset: 17 - bit_size: 1 - - name: ASVLD - description: A-session valid - bit_offset: 18 - bit_size: 1 - - name: BSVLD - description: B-session valid - bit_offset: 19 - bit_size: 1 -fieldset/GOTGINT: - description: Interrupt register - fields: - - name: SEDET - description: Session end detected - bit_offset: 2 - bit_size: 1 - - name: SRSSCHG - description: Session request success status change - bit_offset: 8 - bit_size: 1 - - name: HNSSCHG - description: Host negotiation success status change - bit_offset: 9 - bit_size: 1 - - name: HNGDET - description: Host negotiation detected - bit_offset: 17 - bit_size: 1 - - name: ADTOCHG - description: A-device timeout change - bit_offset: 18 - bit_size: 1 - - name: DBCDNE - description: Debounce done - bit_offset: 19 - bit_size: 1 -fieldset/GRSTCTL: - description: Reset register - fields: - - name: CSRST - description: Core soft reset - bit_offset: 0 - bit_size: 1 - - name: HSRST - description: HCLK soft reset - bit_offset: 1 - bit_size: 1 - - name: FCRST - description: Host frame counter reset - bit_offset: 2 - bit_size: 1 - - name: RXFFLSH - description: RxFIFO flush - bit_offset: 4 - bit_size: 1 - - name: TXFFLSH - description: TxFIFO flush - bit_offset: 5 - bit_size: 1 - - name: TXFNUM - description: TxFIFO number - bit_offset: 6 - bit_size: 5 - - name: AHBIDL - description: AHB master idle - bit_offset: 31 - bit_size: 1 -fieldset/GRXFSIZ: - description: Receive FIFO size register - fields: - - name: RXFD - description: RxFIFO depth - bit_offset: 0 - bit_size: 16 -fieldset/GRXSTSP_Device: - description: Status read and pop (Device mode) - fields: - - name: EPNUM - description: Endpoint number - bit_offset: 0 - bit_size: 4 - - name: BCNT - description: Byte count - bit_offset: 4 - bit_size: 11 - - name: DPID - description: Data PID - bit_offset: 15 - bit_size: 2 - - name: PKTSTS - description: Packet status - bit_offset: 17 - bit_size: 4 - - name: FRMNUM - description: Frame number - bit_offset: 21 - bit_size: 4 -fieldset/GRXSTSP_Host: - description: Status read and pop (Host mode) - fields: - - name: CHNUM - description: Channel number - bit_offset: 0 - bit_size: 4 - - name: BCNT - description: Byte count - bit_offset: 4 - bit_size: 11 - - name: DPID - description: Data PID - bit_offset: 15 - bit_size: 2 - - name: PKTSTS - description: Packet status - bit_offset: 17 - bit_size: 4 -fieldset/GRXSTSR_Device: - description: Receive status debug read(Device mode) - fields: - - name: EPNUM - description: Endpoint number - bit_offset: 0 - bit_size: 4 - - name: BCNT - description: Byte count - bit_offset: 4 - bit_size: 11 - - name: DPID - description: Data PID - bit_offset: 15 - bit_size: 2 - - name: PKTSTS - description: Packet status - bit_offset: 17 - bit_size: 4 - - name: FRMNUM - description: Frame number - bit_offset: 21 - bit_size: 4 -fieldset/GRXSTSR_Host: - description: Receive status debug read(Host mode) - fields: - - name: EPNUM - description: Endpoint number - bit_offset: 0 - bit_size: 4 - - name: BCNT - description: Byte count - bit_offset: 4 - bit_size: 11 - - name: DPID - description: Data PID - bit_offset: 15 - bit_size: 2 - - name: PKTSTS - description: Packet status - bit_offset: 17 - bit_size: 4 -fieldset/GUSBCFG: - description: USB configuration register - fields: - - name: TOCAL - description: FS timeout calibration - bit_offset: 0 - bit_size: 3 - - name: PHYSEL - description: Full Speed serial transceiver select - bit_offset: 6 - bit_size: 1 - - name: SRPCAP - description: SRP-capable - bit_offset: 8 - bit_size: 1 - - name: HNPCAP - description: HNP-capable - bit_offset: 9 - bit_size: 1 - - name: TRDT - description: USB turnaround time - bit_offset: 10 - bit_size: 4 - - name: FHMOD - description: Force host mode - bit_offset: 29 - bit_size: 1 - - name: FDMOD - description: Force device mode - bit_offset: 30 - bit_size: 1 -fieldset/HNPTXFSIZ: - description: Non-periodic transmit FIFO size register (Host mode) - fields: - - name: NPTXFSA - description: Non-periodic transmit RAM start address - bit_offset: 0 - bit_size: 16 - - name: NPTXFD - description: Non-periodic TxFIFO depth - bit_offset: 16 - bit_size: 16 -fieldset/HPTXFSIZ: - description: Host periodic transmit FIFO size register - fields: - - name: PTXSA - description: Host periodic TxFIFO start address - bit_offset: 0 - bit_size: 16 - - name: PTXFSIZ - description: Host periodic TxFIFO depth - bit_offset: 16 - bit_size: 16 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 6e500ed..80d77f6 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -159,7 +159,7 @@ perimap = [ ('.*:SDMMC:sdmmc_v1_3', ('sdmmc', 'v1', 'SDMMC')), ('.*:SPDIFRX:spdifrx1_v1_0', ('spdifrx', 'v1', 'SPDIFRX')), ('.*:USB_OTG_FS:otgfs1_v1_.*', ('otgfs', 'v1', 'OTG_FS')), - ('.*:USB_OTG_FS:otgfs1_v3_.*', ('otgfs', 'v3', 'OTG_FS')), + ('.*:USB_OTG_FS:otgfs1_v3_.*', ('otgfs', 'v1', 'OTG_FS')), ('.*:USB_OTG_HS:otghs1_v1_.*', ('otghs', 'v1', 'OTG_HS')), ('STM32F0.*:RCC:.*', ('rcc', 'f0', 'RCC')), From 1d9e453670d45a5bff460b75c4ba952d91244890 Mon Sep 17 00:00:00 2001 From: chemicstry Date: Wed, 30 Mar 2022 01:59:08 +0300 Subject: [PATCH 02/35] Add missing timer ITR3 field --- data/registers/timer_v1.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index 7df0f79..595175f 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -1000,6 +1000,9 @@ enum/TS: - name: ITR2 description: Internal Trigger 2 (ITR2) value: 2 + - name: ITR3 + description: Internal Trigger 3 (ITR3) + value: 3 - name: TI1F_ED description: TI1 Edge Detector (TI1F_ED) value: 4 From 1d5853be405488f8623f11e69e1c91b543f6b04e Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Fri, 8 Apr 2022 01:17:53 +0200 Subject: [PATCH 03/35] run chiptool fmt with new version that trims descriptions. --- data/registers/flash_g0.yaml | 92 +-- data/registers/flash_u5.yaml | 138 ++-- data/registers/fsmc_v1.yaml | 33 +- data/registers/gpio_v1.yaml | 4 +- data/registers/otgfs_v1.yaml | 1194 ++++++++++++++++----------------- data/registers/pwr_u5.yaml | 104 +-- data/registers/rcc_g0.yaml | 982 +++++++++++++-------------- data/registers/rcc_h7.yaml | 2 +- data/registers/rcc_h7ab.yaml | 34 +- data/registers/rcc_l5.yaml | 382 +++++------ data/registers/rcc_u5.yaml | 258 +++---- data/registers/sdmmc_v1.yaml | 14 +- data/registers/syscfg_f2.yaml | 42 +- data/registers/syscfg_h7.yaml | 2 +- 14 files changed, 1636 insertions(+), 1645 deletions(-) diff --git a/data/registers/flash_g0.yaml b/data/registers/flash_g0.yaml index dfc132b..f95eafb 100644 --- a/data/registers/flash_g0.yaml +++ b/data/registers/flash_g0.yaml @@ -386,69 +386,69 @@ fieldset/WRP1BR: description: WRP area B end offset bit_offset: 16 bit_size: 6 -enum/LATENCY: - bit_size: 3 - variants: - - name: WS0 - description: Zero wait states - value: 0b000 - - name: WS1 - description: One wait state - value: 0b001 - - name: WS2 - description: Two wait states - value: 0b010 -enum/NRST_MODE: - bit_size: 2 - variants: - - name: INPUT_ONLY - description: Reset pin is in reset input mode only - value: 0b01 - - name: GPIO - description: Reset pin is in GPIO mode only - value: 0b10 - - name: INPUT_OUTPUT - description: Reset pin is in resety input and output mode - value: 0b11 -enum/BORR_LEV: - bit_size: 2 - variants: - - name: RISING_0 - description: BOR rising level 1 with threshold around 2.1V - value: 0b00 - - name: RISING_1 - description: BOR rising level 2 with threshold around 2.3V - value: 0b01 - - name: RISING_2 - description: BOR rising level 3 with threshold around 2.6V - value: 0b10 - - name: RISING_3 - description: BOR rising level 4 with threshold around 2.9V - value: 0b11 enum/BORF_LEV: bit_size: 2 variants: - name: FALLING_0 description: BOR falling level 1 with threshold around 2.0V - value: 0b00 + value: 0 - name: FALLING_1 description: BOR falling level 2 with threshold around 2.2V - value: 0b01 + value: 1 - name: FALLING_2 description: BOR falling level 3 with threshold around 2.5V - value: 0b10 + value: 2 - name: FALLING_3 description: BOR falling level 4 with threshold around 2.8V - value: 0b11 + value: 3 +enum/BORR_LEV: + bit_size: 2 + variants: + - name: RISING_0 + description: BOR rising level 1 with threshold around 2.1V + value: 0 + - name: RISING_1 + description: BOR rising level 2 with threshold around 2.3V + value: 1 + - name: RISING_2 + description: BOR rising level 3 with threshold around 2.6V + value: 2 + - name: RISING_3 + description: BOR rising level 4 with threshold around 2.9V + value: 3 +enum/LATENCY: + bit_size: 3 + variants: + - name: WS0 + description: Zero wait states + value: 0 + - name: WS1 + description: One wait state + value: 1 + - name: WS2 + description: Two wait states + value: 2 +enum/NRST_MODE: + bit_size: 2 + variants: + - name: INPUT_ONLY + description: Reset pin is in reset input mode only + value: 1 + - name: GPIO + description: Reset pin is in GPIO mode only + value: 2 + - name: INPUT_OUTPUT + description: Reset pin is in resety input and output mode + value: 3 enum/RDP: bit_size: 8 variants: - name: LEVEL_0 - value: 0xAA description: Read protection not active + value: 170 - name: LEVEL_1 - value: 0xBB description: Memories read protection active + value: 187 - name: LEVEL_2 - value: 0xCC description: Chip read protection active + value: 204 diff --git a/data/registers/flash_u5.yaml b/data/registers/flash_u5.yaml index 7dde2e9..d31533f 100644 --- a/data/registers/flash_u5.yaml +++ b/data/registers/flash_u5.yaml @@ -3,115 +3,115 @@ block/FLASH: description: Flash items: - name: ACR - description: "FLASH access control register " + description: FLASH access control register byte_offset: 0 fieldset: ACR - name: NSKEYR - description: "FLASH non-secure key register " + description: FLASH non-secure key register byte_offset: 8 fieldset: NSKEYR - name: SECKEYR - description: "FLASH secure key register " + description: FLASH secure key register byte_offset: 12 fieldset: SECKEYR - name: OPTKEYR - description: "FLASH option key register " + description: FLASH option key register byte_offset: 16 fieldset: OPTKEYR - name: PDKEY1R - description: "FLASH bank 1 power-down key register " + description: FLASH bank 1 power-down key register byte_offset: 24 fieldset: PDKEY1R - name: PDKEY2R - description: "FLASH bank 2 power-down key register " + description: FLASH bank 2 power-down key register byte_offset: 28 fieldset: PDKEY2R - name: NSSR - description: "FLASH non-secure status register " + description: FLASH non-secure status register byte_offset: 32 fieldset: NSSR - name: SECSR - description: "FLASH secure status register " + description: FLASH secure status register byte_offset: 36 fieldset: SECSR - name: NSCR - description: "FLASH non-secure control register " + description: FLASH non-secure control register byte_offset: 40 fieldset: NSCR - name: SECCR - description: "FLASH secure control register " + description: FLASH secure control register byte_offset: 44 fieldset: SECCR - name: ECCR - description: "FLASH ECC register " + description: FLASH ECC register byte_offset: 48 fieldset: ECCR - name: OPSR - description: "FLASH operation status register " + description: FLASH operation status register byte_offset: 52 fieldset: OPSR - name: OPTR - description: "FLASH option register " + description: FLASH option register byte_offset: 64 fieldset: OPTR - name: NSBOOTADD0R - description: "FLASH non-secure boot address 0 register\t" + description: FLASH non-secure boot address 0 register byte_offset: 68 fieldset: NSBOOTADD0R - name: NSBOOTADD1R - description: "FLASH non-secure boot address 1 register\t" + description: FLASH non-secure boot address 1 register byte_offset: 72 fieldset: NSBOOTADD1R - name: SECBOOTADD0R - description: "FLASH secure boot address 0 register " + description: FLASH secure boot address 0 register byte_offset: 76 fieldset: SECBOOTADD0R - name: SECWM1R1 - description: "FLASH secure watermark1 register 1 " + description: FLASH secure watermark1 register 1 byte_offset: 80 fieldset: SECWM1R1 - name: SECWM1R2 - description: "FLASH secure watermark1 register 2 " + description: FLASH secure watermark1 register 2 byte_offset: 84 fieldset: SECWM1R2 - name: WRP1AR - description: "FLASH WRP1 area A address register " + description: FLASH WRP1 area A address register byte_offset: 88 fieldset: WRP1AR - name: WRP1BR - description: "FLASH WRP1 area B address register " + description: FLASH WRP1 area B address register byte_offset: 92 fieldset: WRP1BR - name: SECWM2R1 - description: "FLASH secure watermark2 register 1 " + description: FLASH secure watermark2 register 1 byte_offset: 96 fieldset: SECWM2R1 - name: SECWM2R2 - description: "FLASH secure watermark2 register 2 " + description: FLASH secure watermark2 register 2 byte_offset: 100 fieldset: SECWM2R2 - name: WRP2AR - description: "FLASH WPR2 area A address register " + description: FLASH WPR2 area A address register byte_offset: 104 fieldset: WRP2AR - name: WRP2BR - description: "FLASH WPR2 area B address register " + description: FLASH WPR2 area B address register byte_offset: 108 fieldset: WRP2BR - name: OEM1KEYR1 - description: "FLASH OEM1 key register 1 " + description: FLASH OEM1 key register 1 byte_offset: 112 fieldset: OEM1KEYR1 - name: OEM1KEYR2 - description: "FLASH OEM1 key register 2 " + description: FLASH OEM1 key register 2 byte_offset: 116 fieldset: OEM1KEYR2 - name: OEM2KEYR1 - description: "FLASH OEM2 key register 1 " + description: FLASH OEM2 key register 1 byte_offset: 120 fieldset: OEM2KEYR1 - name: OEM2KEYR2 - description: "FLASH OEM2 key register 2 " + description: FLASH OEM2 key register 2 byte_offset: 124 fieldset: OEM2KEYR2 - name: SEC1BBR1 @@ -147,11 +147,11 @@ block/FLASH: byte_offset: 172 fieldset: SEC2BBR4 - name: SECHDPCR - description: "FLASH secure HDP control register " + description: FLASH secure HDP control register byte_offset: 192 fieldset: SECHDPCR - name: PRIVCFGR - description: "FLASH privilege configuration register " + description: FLASH privilege configuration register byte_offset: 196 fieldset: PRIVCFGR - name: PRIV1BBR1 @@ -187,7 +187,7 @@ block/FLASH: byte_offset: 252 fieldset: PRIV2BBR4 fieldset/ACR: - description: "FLASH access control register " + description: FLASH access control register fields: - name: LATENCY description: "Latency\r These bits represent the ratio between the HCLK (AHB clock) period and the Flash memory access time.\r ..." @@ -218,7 +218,7 @@ fieldset/ACR: bit_size: 1 enum: SLEEP_PD fieldset/ECCR: - description: "FLASH ECC register " + description: FLASH ECC register fields: - name: ADDR_ECC description: ECC fail address @@ -247,21 +247,21 @@ fieldset/ECCR: bit_offset: 31 bit_size: 1 fieldset/NSBOOTADD0R: - description: "FLASH non-secure boot address 0 register\t" + description: FLASH non-secure boot address 0 register fields: - name: NSBOOTADD0 description: "Non-secure boot base address 0\r The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state.\r Examples:\r NSBOOTADD0[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000)\r NSBOOTADD0[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000)\r NSBOOTADD0[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000)" bit_offset: 7 bit_size: 25 fieldset/NSBOOTADD1R: - description: "FLASH non-secure boot address 1 register\t" + description: FLASH non-secure boot address 1 register fields: - name: NSBOOTADD1 description: "Non-secure boot address 1\r The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state.\r Examples:\r NSBOOTADD1[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000)\r NSBOOTADD1[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000)\r NSBOOTADD1[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000)" bit_offset: 7 bit_size: 25 fieldset/NSCR: - description: "FLASH non-secure control register " + description: FLASH non-secure control register fields: - name: PG description: Non-secure programming @@ -326,14 +326,14 @@ fieldset/NSCR: bit_offset: 31 bit_size: 1 fieldset/NSKEYR: - description: "FLASH non-secure key register " + description: FLASH non-secure key register fields: - name: NSKEY description: Flash memory non-secure key bit_offset: 0 bit_size: 32 fieldset/NSSR: - description: "FLASH non-secure status register " + description: FLASH non-secure status register fields: - name: EOP description: Non-secure end of operation @@ -392,35 +392,35 @@ fieldset/NSSR: bit_offset: 21 bit_size: 1 fieldset/OEM1KEYR1: - description: "FLASH OEM1 key register 1 " + description: FLASH OEM1 key register 1 fields: - name: OEM1KEY description: OEM1 least significant bytes key bit_offset: 0 bit_size: 32 fieldset/OEM1KEYR2: - description: "FLASH OEM1 key register 2 " + description: FLASH OEM1 key register 2 fields: - name: OEM1KEY description: OEM1 most significant bytes key bit_offset: 0 bit_size: 32 fieldset/OEM2KEYR1: - description: "FLASH OEM2 key register 1 " + description: FLASH OEM2 key register 1 fields: - name: OEM2KEY description: OEM2 least significant bytes key bit_offset: 0 bit_size: 32 fieldset/OEM2KEYR2: - description: "FLASH OEM2 key register 2 " + description: FLASH OEM2 key register 2 fields: - name: OEM2KEY description: OEM2 most significant bytes key bit_offset: 0 bit_size: 32 fieldset/OPSR: - description: "FLASH operation status register " + description: FLASH operation status register fields: - name: ADDR_OP description: "Interrupted operation address\r This field indicates which address in the Flash memory was accessed when reset occurred. The address is given by bank from address 0x0 0000 to 0xF FFF0." @@ -441,14 +441,14 @@ fieldset/OPSR: bit_size: 3 enum: CODE_OP fieldset/OPTKEYR: - description: "FLASH option key register " + description: FLASH option key register fields: - name: OPTKEY description: Option byte key bit_offset: 0 bit_size: 32 fieldset/OPTR: - description: "FLASH option register " + description: FLASH option register fields: - name: RDP description: "Readout protection level\r Others: Level 1 (memories readout protection active)\r Note: Refer to for more details." @@ -557,14 +557,14 @@ fieldset/OPTR: bit_offset: 31 bit_size: 1 fieldset/PDKEY1R: - description: "FLASH bank 1 power-down key register " + description: FLASH bank 1 power-down key register fields: - name: PDKEY1 description: Bank 1 power-down key bit_offset: 0 bit_size: 32 fieldset/PDKEY2R: - description: "FLASH bank 2 power-down key register " + description: FLASH bank 2 power-down key register fields: - name: PDKEY2 description: Bank 2 power-down key @@ -1619,7 +1619,7 @@ fieldset/PRIV2BBR4: bit_offset: 31 bit_size: 1 fieldset/PRIVCFGR: - description: "FLASH privilege configuration register " + description: FLASH privilege configuration register fields: - name: SPRIV description: "Privileged protection for secure registers\r This bit can be accessed only when TrustZone is enabled (TZEN = 1). This bit can be read by both privileged or unprivileged, secure and non-secure access.\r The SPRIV bit can be written only by a secure privileged access. A non-secure write access on SPRIV bit is ignored. A secure unprivileged write access on SPRIV bit is ignored." @@ -2680,7 +2680,7 @@ fieldset/SEC2BBR4: bit_offset: 31 bit_size: 1 fieldset/SECBOOTADD0R: - description: "FLASH secure boot address 0 register " + description: FLASH secure boot address 0 register fields: - name: BOOT_LOCK description: "Boot lock\r When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP at level 0." @@ -2691,7 +2691,7 @@ fieldset/SECBOOTADD0R: bit_offset: 7 bit_size: 25 fieldset/SECCR: - description: "FLASH secure control register " + description: FLASH secure control register fields: - name: PG description: Secure programming @@ -2751,7 +2751,7 @@ fieldset/SECCR: bit_offset: 31 bit_size: 1 fieldset/SECHDPCR: - description: "FLASH secure HDP control register " + description: FLASH secure HDP control register fields: - name: HDP1_ACCDIS description: "HDP1 area access disable\r When set, this bit is only cleared by a system reset." @@ -2764,14 +2764,14 @@ fieldset/SECHDPCR: bit_size: 1 enum: HDP_ACCDIS fieldset/SECKEYR: - description: "FLASH secure key register " + description: FLASH secure key register fields: - name: SECKEY description: Flash memory secure key bit_offset: 0 bit_size: 32 fieldset/SECSR: - description: "FLASH secure status register " + description: FLASH secure status register fields: - name: EOP description: "Secure end of operation\r This bit is set by hardware when one or more Flash memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_SECCR). This bit is cleared by writing 1." @@ -2810,7 +2810,7 @@ fieldset/SECSR: bit_offset: 17 bit_size: 1 fieldset/SECWM1R1: - description: "FLASH secure watermark1 register 1 " + description: FLASH secure watermark1 register 1 fields: - name: SECWM1_PSTRT description: "Start page of first secure area\r This field contains the first page of the secure area in bank 1." @@ -2821,7 +2821,7 @@ fieldset/SECWM1R1: bit_offset: 16 bit_size: 7 fieldset/SECWM1R2: - description: "FLASH secure watermark1 register 2 " + description: FLASH secure watermark1 register 2 fields: - name: HDP1_PEND description: "End page of first hide protection area\r This field contains the last page of the HDP area in bank 1." @@ -2832,7 +2832,7 @@ fieldset/SECWM1R2: bit_offset: 31 bit_size: 1 fieldset/SECWM2R1: - description: "FLASH secure watermark2 register 1 " + description: FLASH secure watermark2 register 1 fields: - name: SECWM2_PSTRT description: "Start page of second secure area\r This field contains the first page of the secure area in bank 2." @@ -2843,7 +2843,7 @@ fieldset/SECWM2R1: bit_offset: 16 bit_size: 7 fieldset/SECWM2R2: - description: "FLASH secure watermark2 register 2 " + description: FLASH secure watermark2 register 2 fields: - name: HDP2_PEND description: "End page of hide protection second area\r HDP2_PEND contains the last page of the HDP area in bank 2." @@ -2854,7 +2854,7 @@ fieldset/SECWM2R2: bit_offset: 31 bit_size: 1 fieldset/WRP1AR: - description: "FLASH WRP1 area A address register " + description: FLASH WRP1 area A address register fields: - name: WRP1A_PSTRT description: "bank 1 WPR first area A start page\r This field contains the first page of the first WPR area for bank 1." @@ -2870,7 +2870,7 @@ fieldset/WRP1AR: bit_size: 1 enum: WRPAR_UNLOCK fieldset/WRP1BR: - description: "FLASH WRP1 area B address register " + description: FLASH WRP1 area B address register fields: - name: WRP1B_PSTRT description: "Bank 1 WRP second area B start page\r This field contains the first page of the second WRP area for bank 1." @@ -2886,7 +2886,7 @@ fieldset/WRP1BR: bit_size: 1 enum: WRPBR_UNLOCK fieldset/WRP2AR: - description: "FLASH WPR2 area A address register " + description: FLASH WPR2 area A address register fields: - name: WRP2A_PSTRT description: "Bank 2 WPR first area A start page\r This field contains the first page of the first WRP area for bank 2." @@ -2902,7 +2902,7 @@ fieldset/WRP2AR: bit_size: 1 enum: WRPAR_UNLOCK fieldset/WRP2BR: - description: "FLASH WPR2 area B address register " + description: FLASH WPR2 area B address register fields: - name: WRP2B_PSTRT description: "Bank 2 WPR second area B start page\r This field contains the first page of the second WRP area for bank 2." @@ -2948,19 +2948,19 @@ enum/BOR_LEV: bit_size: 3 variants: - name: B_0x0 - description: "BOR level 0 (reset level threshold around 1.7 V) " + description: BOR level 0 (reset level threshold around 1.7 V) value: 0 - name: B_0x1 - description: "BOR level 1 (reset level threshold around 2.0 V) " + description: BOR level 1 (reset level threshold around 2.0 V) value: 1 - name: B_0x2 - description: "BOR level 2 (reset level threshold around 2.2 V) " + description: BOR level 2 (reset level threshold around 2.2 V) value: 2 - name: B_0x3 - description: "BOR level 3 (reset level threshold around 2.5 V) " + description: BOR level 3 (reset level threshold around 2.5 V) value: 3 - name: B_0x4 - description: "BOR level 4 (reset level threshold around 2.8 V) " + description: BOR level 4 (reset level threshold around 2.8 V) value: 4 enum/CODE_OP: bit_size: 3 @@ -3017,19 +3017,19 @@ enum/IO_VDDIO_HSLV: bit_size: 1 variants: - name: B_0x0 - description: "High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) " + description: High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) value: 0 - name: B_0x1 - description: "High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) " + description: High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) value: 1 enum/IO_VDD_HSLV: bit_size: 1 variants: - name: B_0x0 - description: "High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) " + description: High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) value: 0 - name: B_0x1 - description: "High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) " + description: High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) value: 1 enum/IWDG_STDBY: bit_size: 1 diff --git a/data/registers/fsmc_v1.yaml b/data/registers/fsmc_v1.yaml index f4b5ab3..65dbd6b 100644 --- a/data/registers/fsmc_v1.yaml +++ b/data/registers/fsmc_v1.yaml @@ -38,26 +38,10 @@ block/FSMC: description: PC Card/NAND Flash control register 2 byte_offset: 96 fieldset: PCR - - name: PCR3 - description: PC Card/NAND Flash control register 3 - byte_offset: 128 - fieldset: PCR - - name: PCR4 - description: PC Card/NAND Flash control register 4 - byte_offset: 160 - fieldset: PCR - name: SR2 description: FIFO status and interrupt register 2 byte_offset: 100 fieldset: SR - - name: SR3 - description: FIFO status and interrupt register 3 - byte_offset: 132 - fieldset: SR - - name: SR4 - description: FIFO status and interrupt register 4 - byte_offset: 164 - fieldset: SR - name: PMEM2 description: Common memory space timing register 2 byte_offset: 104 @@ -71,6 +55,14 @@ block/FSMC: byte_offset: 116 access: Read fieldset: ECCR + - name: PCR3 + description: PC Card/NAND Flash control register 3 + byte_offset: 128 + fieldset: PCR + - name: SR3 + description: FIFO status and interrupt register 3 + byte_offset: 132 + fieldset: SR - name: PMEM3 description: Common memory space timing register 3 byte_offset: 136 @@ -84,6 +76,14 @@ block/FSMC: byte_offset: 148 access: Read fieldset: ECCR + - name: PCR4 + description: PC Card/NAND Flash control register 4 + byte_offset: 160 + fieldset: PCR + - name: SR4 + description: FIFO status and interrupt register 4 + byte_offset: 164 + fieldset: SR - name: PMEM4 description: Common memory space timing register 4 byte_offset: 168 @@ -141,7 +141,6 @@ block/FSMC: byte_offset: 344 access: Read fieldset: SDSR - fieldset/BCR: description: SRAM/NOR-Flash chip-select control register fields: diff --git a/data/registers/gpio_v1.yaml b/data/registers/gpio_v1.yaml index dc99224..10a495e 100644 --- a/data/registers/gpio_v1.yaml +++ b/data/registers/gpio_v1.yaml @@ -72,7 +72,7 @@ fieldset/CR: stride: 4 enum: MODE - name: CNF_IN - description: Port n configuration bits, for input mode + description: "Port n configuration bits, for input mode" bit_offset: 2 bit_size: 2 array: @@ -80,7 +80,7 @@ fieldset/CR: stride: 4 enum: CNF_IN - name: CNF_OUT - description: Port n configuration bits, for output mode + description: "Port n configuration bits, for output mode" bit_offset: 2 bit_size: 2 array: diff --git a/data/registers/otgfs_v1.yaml b/data/registers/otgfs_v1.yaml index d58d504..1c1d5ec 100644 --- a/data/registers/otgfs_v1.yaml +++ b/data/registers/otgfs_v1.yaml @@ -1,8 +1,3 @@ -# The OTG registers are provided in 4 different sub-blocks (GLOBAL, HOST, -# DEVICE, PWRCLK), which doesn't make much sense from a usability perspective. -# On top of that, there are offsets for the FIFO at different addresses that are -# not part any register blocks, but should be. -# This register definition merges all these different sub-register blocks. --- block/OTG_FS: description: USB on the go full speed @@ -281,8 +276,6 @@ block/OTG_FS: stride: 4096 byte_offset: 4096 fieldset: FIFO - # Omitting the Debug FIFO regions - fieldset/CID: description: Core ID register fields: @@ -290,6 +283,302 @@ fieldset/CID: description: Product ID field bit_offset: 0 bit_size: 32 +fieldset/DAINT: + description: Device all endpoints interrupt register + fields: + - name: IEPINT + description: IN endpoint interrupt bits + bit_offset: 0 + bit_size: 16 + - name: OEPINT + description: OUT endpoint interrupt bits + bit_offset: 16 + bit_size: 16 +fieldset/DAINTMSK: + description: All endpoints interrupt mask register + fields: + - name: IEPM + description: IN EP interrupt mask bits + bit_offset: 0 + bit_size: 16 + - name: OEPM + description: OUT EP interrupt mask bits + bit_offset: 16 + bit_size: 16 +fieldset/DCFG: + description: Device configuration register + fields: + - name: DSPD + description: Device speed + bit_offset: 0 + bit_size: 2 + - name: NZLSOHSK + description: Non-zero-length status OUT handshake + bit_offset: 2 + bit_size: 1 + - name: DAD + description: Device address + bit_offset: 4 + bit_size: 7 + - name: PFIVL + description: Periodic frame interval + bit_offset: 11 + bit_size: 2 +fieldset/DCTL: + description: Device control register + fields: + - name: RWUSIG + description: Remote wakeup signaling + bit_offset: 0 + bit_size: 1 + - name: SDIS + description: Soft disconnect + bit_offset: 1 + bit_size: 1 + - name: GINSTS + description: Global IN NAK status + bit_offset: 2 + bit_size: 1 + - name: GONSTS + description: Global OUT NAK status + bit_offset: 3 + bit_size: 1 + - name: TCTL + description: Test control + bit_offset: 4 + bit_size: 3 + - name: SGINAK + description: Set global IN NAK + bit_offset: 7 + bit_size: 1 + - name: CGINAK + description: Clear global IN NAK + bit_offset: 8 + bit_size: 1 + - name: SGONAK + description: Set global OUT NAK + bit_offset: 9 + bit_size: 1 + - name: CGONAK + description: Clear global OUT NAK + bit_offset: 10 + bit_size: 1 + - name: POPRGDNE + description: Power-on programming done + bit_offset: 11 + bit_size: 1 +fieldset/DIEPCTL: + description: Device endpoint control register + fields: + - name: MPSIZ + description: MPSIZ + bit_offset: 0 + bit_size: 11 + - name: USBAEP + description: USBAEP + bit_offset: 15 + bit_size: 1 + - name: EONUM_DPID + description: EONUM/DPID + bit_offset: 16 + bit_size: 1 + - name: NAKSTS + description: NAKSTS + bit_offset: 17 + bit_size: 1 + - name: EPTYP + description: EPTYP + bit_offset: 18 + bit_size: 2 + - name: STALL + description: STALL + bit_offset: 21 + bit_size: 1 + - name: TXFNUM + description: TXFNUM + bit_offset: 22 + bit_size: 4 + - name: CNAK + description: CNAK + bit_offset: 26 + bit_size: 1 + - name: SNAK + description: SNAK + bit_offset: 27 + bit_size: 1 + - name: SD0PID_SEVNFRM + description: SD0PID/SEVNFRM + bit_offset: 28 + bit_size: 1 + - name: SODDFRM_SD1PID + description: SODDFRM/SD1PID + bit_offset: 29 + bit_size: 1 + - name: EPDIS + description: EPDIS + bit_offset: 30 + bit_size: 1 + - name: EPENA + description: EPENA + bit_offset: 31 + bit_size: 1 +fieldset/DIEPCTL0: + description: Device control IN endpoint 0 control register + fields: + - name: MPSIZ + description: Maximum packet size + bit_offset: 0 + bit_size: 2 + - name: USBAEP + description: USB active endpoint + bit_offset: 15 + bit_size: 1 + - name: NAKSTS + description: NAK status + bit_offset: 17 + bit_size: 1 + - name: EPTYP + description: Endpoint type + bit_offset: 18 + bit_size: 2 + - name: STALL + description: STALL handshake + bit_offset: 21 + bit_size: 1 + - name: TXFNUM + description: TxFIFO number + bit_offset: 22 + bit_size: 4 + - name: CNAK + description: Clear NAK + bit_offset: 26 + bit_size: 1 + - name: SNAK + description: Set NAK + bit_offset: 27 + bit_size: 1 + - name: EPDIS + description: Endpoint disable + bit_offset: 30 + bit_size: 1 + - name: EPENA + description: Endpoint enable + bit_offset: 31 + bit_size: 1 +fieldset/DIEPEMPMSK: + description: Device IN endpoint FIFO empty interrupt mask register + fields: + - name: INEPTXFEM + description: IN EP Tx FIFO empty interrupt mask bits + bit_offset: 0 + bit_size: 16 +fieldset/DIEPINT: + description: Device endpoint interrupt register + fields: + - name: XFRC + description: XFRC + bit_offset: 0 + bit_size: 1 + - name: EPDISD + description: EPDISD + bit_offset: 1 + bit_size: 1 + - name: TOC + description: TOC + bit_offset: 3 + bit_size: 1 + - name: ITTXFE + description: ITTXFE + bit_offset: 4 + bit_size: 1 + - name: INEPNE + description: INEPNE + bit_offset: 6 + bit_size: 1 + - name: TXFE + description: TXFE + bit_offset: 7 + bit_size: 1 +fieldset/DIEPINT0: + description: Device endpoint 0 interrupt register + fields: + - name: XFRC + description: XFRC + bit_offset: 0 + bit_size: 1 + - name: EPDISD + description: EPDISD + bit_offset: 1 + bit_size: 1 + - name: TOC + description: TOC + bit_offset: 3 + bit_size: 1 + - name: ITTXFE + description: ITTXFE + bit_offset: 4 + bit_size: 1 + - name: INEPNE + description: INEPNE + bit_offset: 6 + bit_size: 1 + - name: TXFE + description: TXFE + bit_offset: 7 + bit_size: 1 +fieldset/DIEPMSK: + description: Device IN endpoint common interrupt mask register + fields: + - name: XFRCM + description: Transfer completed interrupt mask + bit_offset: 0 + bit_size: 1 + - name: EPDM + description: Endpoint disabled interrupt mask + bit_offset: 1 + bit_size: 1 + - name: TOM + description: Timeout condition mask (Non-isochronous endpoints) + bit_offset: 3 + bit_size: 1 + - name: ITTXFEMSK + description: IN token received when TxFIFO empty mask + bit_offset: 4 + bit_size: 1 + - name: INEPNMM + description: IN token received with EP mismatch mask + bit_offset: 5 + bit_size: 1 + - name: INEPNEM + description: IN endpoint NAK effective mask + bit_offset: 6 + bit_size: 1 +fieldset/DIEPTSIZ: + description: Device endpoint transfer size register + fields: + - name: XFRSIZ + description: Transfer size + bit_offset: 0 + bit_size: 19 + - name: PKTCNT + description: Packet count + bit_offset: 19 + bit_size: 10 + - name: MCNT + description: Multi count + bit_offset: 29 + bit_size: 2 +fieldset/DIEPTSIZ0: + description: Device endpoint 0 transfer size register + fields: + - name: XFRSIZ + description: Transfer size + bit_offset: 0 + bit_size: 7 + - name: PKTCNT + description: Packet count + bit_offset: 19 + bit_size: 2 fieldset/DIEPTXF: description: Device IN endpoint transmit FIFO size register fields: @@ -312,6 +601,253 @@ fieldset/DIEPTXF0: description: Endpoint 0 TxFIFO depth bit_offset: 16 bit_size: 16 +fieldset/DOEPCTL: + description: Device endpoint control register + fields: + - name: MPSIZ + description: MPSIZ + bit_offset: 0 + bit_size: 11 + - name: USBAEP + description: USBAEP + bit_offset: 15 + bit_size: 1 + - name: EONUM_DPID + description: EONUM/DPID + bit_offset: 16 + bit_size: 1 + - name: NAKSTS + description: NAKSTS + bit_offset: 17 + bit_size: 1 + - name: EPTYP + description: EPTYP + bit_offset: 18 + bit_size: 2 + - name: SNPM + description: SNPM + bit_offset: 20 + bit_size: 1 + - name: STALL + description: STALL + bit_offset: 21 + bit_size: 1 + - name: CNAK + description: CNAK + bit_offset: 26 + bit_size: 1 + - name: SNAK + description: SNAK + bit_offset: 27 + bit_size: 1 + - name: SD0PID_SEVNFRM + description: SD0PID/SEVNFRM + bit_offset: 28 + bit_size: 1 + - name: SODDFRM + description: SODDFRM + bit_offset: 29 + bit_size: 1 + - name: EPDIS + description: EPDIS + bit_offset: 30 + bit_size: 1 + - name: EPENA + description: EPENA + bit_offset: 31 + bit_size: 1 +fieldset/DOEPCTL0: + description: Device endpoint 0 control register + fields: + - name: MPSIZ + description: MPSIZ + bit_offset: 0 + bit_size: 2 + - name: USBAEP + description: USBAEP + bit_offset: 15 + bit_size: 1 + - name: NAKSTS + description: NAKSTS + bit_offset: 17 + bit_size: 1 + - name: EPTYP + description: EPTYP + bit_offset: 18 + bit_size: 2 + - name: SNPM + description: SNPM + bit_offset: 20 + bit_size: 1 + - name: STALL + description: STALL + bit_offset: 21 + bit_size: 1 + - name: CNAK + description: CNAK + bit_offset: 26 + bit_size: 1 + - name: SNAK + description: SNAK + bit_offset: 27 + bit_size: 1 + - name: EPDIS + description: EPDIS + bit_offset: 30 + bit_size: 1 + - name: EPENA + description: EPENA + bit_offset: 31 + bit_size: 1 +fieldset/DOEPINT: + description: Device endpoint interrupt register + fields: + - name: XFRC + description: XFRC + bit_offset: 0 + bit_size: 1 + - name: EPDISD + description: EPDISD + bit_offset: 1 + bit_size: 1 + - name: STUP + description: STUP + bit_offset: 3 + bit_size: 1 + - name: OTEPDIS + description: OTEPDIS + bit_offset: 4 + bit_size: 1 + - name: B2BSTUP + description: B2BSTUP + bit_offset: 6 + bit_size: 1 +fieldset/DOEPINT0: + description: Device endpoint 0 interrupt register + fields: + - name: XFRC + description: XFRC + bit_offset: 0 + bit_size: 1 + - name: EPDISD + description: EPDISD + bit_offset: 1 + bit_size: 1 + - name: STUP + description: STUP + bit_offset: 3 + bit_size: 1 + - name: OTEPDIS + description: OTEPDIS + bit_offset: 4 + bit_size: 1 + - name: B2BSTUP + description: B2BSTUP + bit_offset: 6 + bit_size: 1 +fieldset/DOEPMSK: + description: Device OUT endpoint common interrupt mask register + fields: + - name: XFRCM + description: Transfer completed interrupt mask + bit_offset: 0 + bit_size: 1 + - name: EPDM + description: Endpoint disabled interrupt mask + bit_offset: 1 + bit_size: 1 + - name: STUPM + description: SETUP phase done mask + bit_offset: 3 + bit_size: 1 + - name: OTEPDM + description: OUT token received when endpoint disabled mask + bit_offset: 4 + bit_size: 1 +fieldset/DOEPTSIZ: + description: Device OUT endpoint transfer size register + fields: + - name: XFRSIZ + description: Transfer size + bit_offset: 0 + bit_size: 19 + - name: PKTCNT + description: Packet count + bit_offset: 19 + bit_size: 10 + - name: RXDPID_STUPCNT + description: Received data PID/SETUP packet count + bit_offset: 29 + bit_size: 2 +fieldset/DOEPTSIZ0: + description: Device OUT endpoint 0 transfer size register + fields: + - name: XFRSIZ + description: Transfer size + bit_offset: 0 + bit_size: 7 + - name: PKTCNT + description: Packet count + bit_offset: 19 + bit_size: 1 + - name: STUPCNT + description: SETUP packet count + bit_offset: 29 + bit_size: 2 +fieldset/DSTS: + description: Device status register + fields: + - name: SUSPSTS + description: Suspend status + bit_offset: 0 + bit_size: 1 + - name: ENUMSPD + description: Enumerated speed + bit_offset: 1 + bit_size: 2 + - name: EERR + description: Erratic error + bit_offset: 3 + bit_size: 1 + - name: FNSOF + description: Frame number of the received SOF + bit_offset: 8 + bit_size: 14 +fieldset/DTXFSTS: + description: Device IN endpoint transmit FIFO status register + fields: + - name: INEPTFSAV + description: IN endpoint TxFIFO space available + bit_offset: 0 + bit_size: 16 +fieldset/DTXFSTS0: + description: Device IN endpoint transmit FIFO status register + fields: + - name: INEPTFSAV + description: IN endpoint TxFIFO space available + bit_offset: 0 + bit_size: 16 +fieldset/DVBUSDIS: + description: Device VBUS discharge time register + fields: + - name: VBUSDT + description: Device VBUS discharge time + bit_offset: 0 + bit_size: 16 +fieldset/DVBUSPULSE: + description: Device VBUS pulsing time register + fields: + - name: DVBUSP + description: Device VBUS pulsing time + bit_offset: 0 + bit_size: 12 +fieldset/FIFO: + description: Fifo register + fields: + - name: DATA + description: Data + bit_offset: 0 + bit_size: 32 fieldset/GAHBCFG: description: AHB configuration register fields: @@ -756,28 +1292,6 @@ fieldset/GUSBCFG: description: Corrupt Tx packet bit_offset: 31 bit_size: 1 -fieldset/HNPTXFSIZ: - description: Non-periodic transmit FIFO size register (Host mode) - fields: - - name: NPTXFSA - description: Non-periodic transmit RAM start address - bit_offset: 0 - bit_size: 16 - - name: NPTXFD - description: Non-periodic TxFIFO depth - bit_offset: 16 - bit_size: 16 -fieldset/HPTXFSIZ: - description: Host periodic transmit FIFO size register - fields: - - name: PTXSA - description: Host periodic TxFIFO start address - bit_offset: 0 - bit_size: 16 - - name: PTXFSIZ - description: Host periodic TxFIFO depth - bit_offset: 16 - bit_size: 16 fieldset/HAINT: description: Host all channels interrupt register fields: @@ -962,6 +1476,17 @@ fieldset/HFNUM: description: Frame time remaining bit_offset: 16 bit_size: 16 +fieldset/HNPTXFSIZ: + description: Non-periodic transmit FIFO size register (Host mode) + fields: + - name: NPTXFSA + description: Non-periodic transmit RAM start address + bit_offset: 0 + bit_size: 16 + - name: NPTXFD + description: Non-periodic TxFIFO depth + bit_offset: 16 + bit_size: 16 fieldset/HPRT: description: Host port control and status register fields: @@ -1018,6 +1543,17 @@ fieldset/HPRT: bit_offset: 17 bit_size: 2 enum: SPEED +fieldset/HPTXFSIZ: + description: Host periodic transmit FIFO size register + fields: + - name: PTXSA + description: Host periodic TxFIFO start address + bit_offset: 0 + bit_size: 16 + - name: PTXFSIZ + description: Host periodic TxFIFO depth + bit_offset: 16 + bit_size: 16 fieldset/HPTXSTS: description: Periodic transmit FIFO/queue status register fields: @@ -1033,542 +1569,6 @@ fieldset/HPTXSTS: description: Top of the periodic transmit request queue bit_offset: 24 bit_size: 8 -fieldset/DAINT: - description: Device all endpoints interrupt register - fields: - - name: IEPINT - description: IN endpoint interrupt bits - bit_offset: 0 - bit_size: 16 - - name: OEPINT - description: OUT endpoint interrupt bits - bit_offset: 16 - bit_size: 16 -fieldset/DAINTMSK: - description: All endpoints interrupt mask register - fields: - - name: IEPM - description: IN EP interrupt mask bits - bit_offset: 0 - bit_size: 16 - - name: OEPM - description: OUT EP interrupt mask bits - bit_offset: 16 - bit_size: 16 -fieldset/DCFG: - description: Device configuration register - fields: - - name: DSPD - description: Device speed - bit_offset: 0 - bit_size: 2 - - name: NZLSOHSK - description: Non-zero-length status OUT handshake - bit_offset: 2 - bit_size: 1 - - name: DAD - description: Device address - bit_offset: 4 - bit_size: 7 - - name: PFIVL - description: Periodic frame interval - bit_offset: 11 - bit_size: 2 -fieldset/DCTL: - description: Device control register - fields: - - name: RWUSIG - description: Remote wakeup signaling - bit_offset: 0 - bit_size: 1 - - name: SDIS - description: Soft disconnect - bit_offset: 1 - bit_size: 1 - - name: GINSTS - description: Global IN NAK status - bit_offset: 2 - bit_size: 1 - - name: GONSTS - description: Global OUT NAK status - bit_offset: 3 - bit_size: 1 - - name: TCTL - description: Test control - bit_offset: 4 - bit_size: 3 - - name: SGINAK - description: Set global IN NAK - bit_offset: 7 - bit_size: 1 - - name: CGINAK - description: Clear global IN NAK - bit_offset: 8 - bit_size: 1 - - name: SGONAK - description: Set global OUT NAK - bit_offset: 9 - bit_size: 1 - - name: CGONAK - description: Clear global OUT NAK - bit_offset: 10 - bit_size: 1 - - name: POPRGDNE - description: Power-on programming done - bit_offset: 11 - bit_size: 1 -fieldset/DIEPCTL: - description: Device endpoint control register - fields: - - name: MPSIZ - description: MPSIZ - bit_offset: 0 - bit_size: 11 - - name: USBAEP - description: USBAEP - bit_offset: 15 - bit_size: 1 - - name: EONUM_DPID - description: EONUM/DPID - bit_offset: 16 - bit_size: 1 - - name: NAKSTS - description: NAKSTS - bit_offset: 17 - bit_size: 1 - - name: EPTYP - description: EPTYP - bit_offset: 18 - bit_size: 2 - - name: STALL - description: STALL - bit_offset: 21 - bit_size: 1 - - name: TXFNUM - description: TXFNUM - bit_offset: 22 - bit_size: 4 - - name: CNAK - description: CNAK - bit_offset: 26 - bit_size: 1 - - name: SNAK - description: SNAK - bit_offset: 27 - bit_size: 1 - - name: SD0PID_SEVNFRM - description: SD0PID/SEVNFRM - bit_offset: 28 - bit_size: 1 - - name: SODDFRM_SD1PID - description: SODDFRM/SD1PID - bit_offset: 29 - bit_size: 1 - - name: EPDIS - description: EPDIS - bit_offset: 30 - bit_size: 1 - - name: EPENA - description: EPENA - bit_offset: 31 - bit_size: 1 -fieldset/DIEPCTL0: - description: Device control IN endpoint 0 control register - fields: - - name: MPSIZ - description: Maximum packet size - bit_offset: 0 - bit_size: 2 - - name: USBAEP - description: USB active endpoint - bit_offset: 15 - bit_size: 1 - - name: NAKSTS - description: NAK status - bit_offset: 17 - bit_size: 1 - - name: EPTYP - description: Endpoint type - bit_offset: 18 - bit_size: 2 - - name: STALL - description: STALL handshake - bit_offset: 21 - bit_size: 1 - - name: TXFNUM - description: TxFIFO number - bit_offset: 22 - bit_size: 4 - - name: CNAK - description: Clear NAK - bit_offset: 26 - bit_size: 1 - - name: SNAK - description: Set NAK - bit_offset: 27 - bit_size: 1 - - name: EPDIS - description: Endpoint disable - bit_offset: 30 - bit_size: 1 - - name: EPENA - description: Endpoint enable - bit_offset: 31 - bit_size: 1 -fieldset/DIEPEMPMSK: - description: Device IN endpoint FIFO empty interrupt mask register - fields: - - name: INEPTXFEM - description: IN EP Tx FIFO empty interrupt mask bits - bit_offset: 0 - bit_size: 16 -fieldset/DIEPINT: - description: Device endpoint interrupt register - fields: - - name: XFRC - description: XFRC - bit_offset: 0 - bit_size: 1 - - name: EPDISD - description: EPDISD - bit_offset: 1 - bit_size: 1 - - name: TOC - description: TOC - bit_offset: 3 - bit_size: 1 - - name: ITTXFE - description: ITTXFE - bit_offset: 4 - bit_size: 1 - - name: INEPNE - description: INEPNE - bit_offset: 6 - bit_size: 1 - - name: TXFE - description: TXFE - bit_offset: 7 - bit_size: 1 -fieldset/DIEPINT0: - description: Device endpoint 0 interrupt register - fields: - - name: XFRC - description: XFRC - bit_offset: 0 - bit_size: 1 - - name: EPDISD - description: EPDISD - bit_offset: 1 - bit_size: 1 - - name: TOC - description: TOC - bit_offset: 3 - bit_size: 1 - - name: ITTXFE - description: ITTXFE - bit_offset: 4 - bit_size: 1 - - name: INEPNE - description: INEPNE - bit_offset: 6 - bit_size: 1 - - name: TXFE - description: TXFE - bit_offset: 7 - bit_size: 1 -fieldset/DIEPMSK: - description: Device IN endpoint common interrupt mask register - fields: - - name: XFRCM - description: Transfer completed interrupt mask - bit_offset: 0 - bit_size: 1 - - name: EPDM - description: Endpoint disabled interrupt mask - bit_offset: 1 - bit_size: 1 - - name: TOM - description: Timeout condition mask (Non-isochronous endpoints) - bit_offset: 3 - bit_size: 1 - - name: ITTXFEMSK - description: IN token received when TxFIFO empty mask - bit_offset: 4 - bit_size: 1 - - name: INEPNMM - description: IN token received with EP mismatch mask - bit_offset: 5 - bit_size: 1 - - name: INEPNEM - description: IN endpoint NAK effective mask - bit_offset: 6 - bit_size: 1 -fieldset/DIEPTSIZ: - description: Device endpoint transfer size register - fields: - - name: XFRSIZ - description: Transfer size - bit_offset: 0 - bit_size: 19 - - name: PKTCNT - description: Packet count - bit_offset: 19 - bit_size: 10 - - name: MCNT - description: Multi count - bit_offset: 29 - bit_size: 2 -fieldset/DIEPTSIZ0: - description: Device endpoint 0 transfer size register - fields: - - name: XFRSIZ - description: Transfer size - bit_offset: 0 - bit_size: 7 - - name: PKTCNT - description: Packet count - bit_offset: 19 - bit_size: 2 -fieldset/DOEPCTL: - description: Device endpoint control register - fields: - - name: MPSIZ - description: MPSIZ - bit_offset: 0 - bit_size: 11 - - name: USBAEP - description: USBAEP - bit_offset: 15 - bit_size: 1 - - name: EONUM_DPID - description: EONUM/DPID - bit_offset: 16 - bit_size: 1 - - name: NAKSTS - description: NAKSTS - bit_offset: 17 - bit_size: 1 - - name: EPTYP - description: EPTYP - bit_offset: 18 - bit_size: 2 - - name: SNPM - description: SNPM - bit_offset: 20 - bit_size: 1 - - name: STALL - description: STALL - bit_offset: 21 - bit_size: 1 - - name: CNAK - description: CNAK - bit_offset: 26 - bit_size: 1 - - name: SNAK - description: SNAK - bit_offset: 27 - bit_size: 1 - - name: SD0PID_SEVNFRM - description: SD0PID/SEVNFRM - bit_offset: 28 - bit_size: 1 - - name: SODDFRM - description: SODDFRM - bit_offset: 29 - bit_size: 1 - - name: EPDIS - description: EPDIS - bit_offset: 30 - bit_size: 1 - - name: EPENA - description: EPENA - bit_offset: 31 - bit_size: 1 -fieldset/DOEPCTL0: - description: Device endpoint 0 control register - fields: - - name: MPSIZ - description: MPSIZ - bit_offset: 0 - bit_size: 2 - - name: USBAEP - description: USBAEP - bit_offset: 15 - bit_size: 1 - - name: NAKSTS - description: NAKSTS - bit_offset: 17 - bit_size: 1 - - name: EPTYP - description: EPTYP - bit_offset: 18 - bit_size: 2 - - name: SNPM - description: SNPM - bit_offset: 20 - bit_size: 1 - - name: STALL - description: STALL - bit_offset: 21 - bit_size: 1 - - name: CNAK - description: CNAK - bit_offset: 26 - bit_size: 1 - - name: SNAK - description: SNAK - bit_offset: 27 - bit_size: 1 - - name: EPDIS - description: EPDIS - bit_offset: 30 - bit_size: 1 - - name: EPENA - description: EPENA - bit_offset: 31 - bit_size: 1 -fieldset/DOEPINT: - description: Device endpoint interrupt register - fields: - - name: XFRC - description: XFRC - bit_offset: 0 - bit_size: 1 - - name: EPDISD - description: EPDISD - bit_offset: 1 - bit_size: 1 - - name: STUP - description: STUP - bit_offset: 3 - bit_size: 1 - - name: OTEPDIS - description: OTEPDIS - bit_offset: 4 - bit_size: 1 - - name: B2BSTUP - description: B2BSTUP - bit_offset: 6 - bit_size: 1 -fieldset/DOEPINT0: - description: Device endpoint 0 interrupt register - fields: - - name: XFRC - description: XFRC - bit_offset: 0 - bit_size: 1 - - name: EPDISD - description: EPDISD - bit_offset: 1 - bit_size: 1 - - name: STUP - description: STUP - bit_offset: 3 - bit_size: 1 - - name: OTEPDIS - description: OTEPDIS - bit_offset: 4 - bit_size: 1 - - name: B2BSTUP - description: B2BSTUP - bit_offset: 6 - bit_size: 1 -fieldset/DOEPMSK: - description: Device OUT endpoint common interrupt mask register - fields: - - name: XFRCM - description: Transfer completed interrupt mask - bit_offset: 0 - bit_size: 1 - - name: EPDM - description: Endpoint disabled interrupt mask - bit_offset: 1 - bit_size: 1 - - name: STUPM - description: SETUP phase done mask - bit_offset: 3 - bit_size: 1 - - name: OTEPDM - description: OUT token received when endpoint disabled mask - bit_offset: 4 - bit_size: 1 -fieldset/DOEPTSIZ: - description: Device OUT endpoint transfer size register - fields: - - name: XFRSIZ - description: Transfer size - bit_offset: 0 - bit_size: 19 - - name: PKTCNT - description: Packet count - bit_offset: 19 - bit_size: 10 - - name: RXDPID_STUPCNT - description: Received data PID/SETUP packet count - bit_offset: 29 - bit_size: 2 -fieldset/DOEPTSIZ0: - description: Device OUT endpoint 0 transfer size register - fields: - - name: XFRSIZ - description: Transfer size - bit_offset: 0 - bit_size: 7 - - name: PKTCNT - description: Packet count - bit_offset: 19 - bit_size: 1 - - name: STUPCNT - description: SETUP packet count - bit_offset: 29 - bit_size: 2 -fieldset/DSTS: - description: Device status register - fields: - - name: SUSPSTS - description: Suspend status - bit_offset: 0 - bit_size: 1 - - name: ENUMSPD - description: Enumerated speed - bit_offset: 1 - bit_size: 2 - - name: EERR - description: Erratic error - bit_offset: 3 - bit_size: 1 - - name: FNSOF - description: Frame number of the received SOF - bit_offset: 8 - bit_size: 14 -fieldset/DTXFSTS: - description: Device IN endpoint transmit FIFO status register - fields: - - name: INEPTFSAV - description: IN endpoint TxFIFO space available - bit_offset: 0 - bit_size: 16 -fieldset/DTXFSTS0: - description: Device IN endpoint transmit FIFO status register - fields: - - name: INEPTFSAV - description: IN endpoint TxFIFO space available - bit_offset: 0 - bit_size: 16 -fieldset/DVBUSDIS: - description: Device VBUS discharge time register - fields: - - name: VBUSDT - description: Device VBUS discharge time - bit_offset: 0 - bit_size: 16 -fieldset/DVBUSPULSE: - description: Device VBUS pulsing time register - fields: - - name: DVBUSP - description: Device VBUS pulsing time - bit_offset: 0 - bit_size: 12 fieldset/PCGCCTL: description: Power and clock gating control register fields: @@ -1584,67 +1584,59 @@ fieldset/PCGCCTL: description: PHY Suspended bit_offset: 4 bit_size: 1 -fieldset/FIFO: - description: Fifo register - fields: - - name: DATA - description: Data - bit_offset: 0 - bit_size: 32 - -enum/SPEED: - bit_size: 2 - variants: - - name: FULL_SPEED - value: 0b01 - - name: LOW_SPEED - value: 0b10 -enum/TXFNUM: - bit_size: 5 - variants: - - name: ALL - value: 0b10000 enum/DPID: bit_size: 2 variants: - name: DATA0 - value: 0b00 - - name: DATA1 - value: 0b10 + value: 0 - name: DATA2 - value: 0b01 + value: 1 + - name: DATA1 + value: 2 - name: MDATA - value: 0b11 + value: 3 enum/PKTSTSD: bit_size: 4 variants: - name: OUT_NAK description: Global OUT NAK (triggers an interrupt) - value: 0b0001 + value: 1 - name: OUT_DATA_RX description: OUT data packet received - value: 0b0010 + value: 2 - name: OUT_DATA_DONE description: OUT transfer completed (triggers an interrupt) - value: 0b0011 - - name: SETUP_DATA_RX - description: SETUP data packet received - value: 0b0110 + value: 3 - name: SETUP_DATA_DONE description: SETUP transaction completed (triggers an interrupt) - value: 0b0100 + value: 4 + - name: SETUP_DATA_RX + description: SETUP data packet received + value: 6 enum/PKTSTSH: bit_size: 4 variants: - name: IN_DATA_RX description: IN data packet received - value: 0b0010 + value: 2 - name: IN_DATA_DONE description: IN transfer completed (triggers an interrupt) - value: 0b0011 + value: 3 - name: DATA_TOGGLE_ERR description: Data toggle error (triggers an interrupt) - value: 0b0101 + value: 5 - name: CHANNEL_HALTED description: Channel halted (triggers an interrupt) - value: 0b0111 + value: 7 +enum/SPEED: + bit_size: 2 + variants: + - name: FULL_SPEED + value: 1 + - name: LOW_SPEED + value: 2 +enum/TXFNUM: + bit_size: 5 + variants: + - name: ALL + value: 16 diff --git a/data/registers/pwr_u5.yaml b/data/registers/pwr_u5.yaml index fd5e25b..f675be9 100644 --- a/data/registers/pwr_u5.yaml +++ b/data/registers/pwr_u5.yaml @@ -3,82 +3,82 @@ block/PWR: description: Power control items: - name: CR1 - description: "PWR control register 1 " + description: PWR control register 1 byte_offset: 0 fieldset: CR1 - name: CR2 - description: "PWR control register 2 " + description: PWR control register 2 byte_offset: 4 fieldset: CR2 - name: CR3 - description: "PWR control register 3 " + description: PWR control register 3 byte_offset: 8 fieldset: CR3 - name: VOSR - description: "PWR voltage scaling register " + description: PWR voltage scaling register byte_offset: 12 fieldset: VOSR - name: SVMCR - description: "PWR supply voltage monitoring control register " + description: PWR supply voltage monitoring control register byte_offset: 16 fieldset: SVMCR - name: WUCR1 - description: "PWR wakeup control register 1 " + description: PWR wakeup control register 1 byte_offset: 20 fieldset: WUCR1 - name: WUCR2 - description: "PWR wakeup control register 2 " + description: PWR wakeup control register 2 byte_offset: 24 fieldset: WUCR2 - name: WUCR3 - description: "PWR wakeup control register 3 " + description: PWR wakeup control register 3 byte_offset: 28 fieldset: WUCR3 - name: BDCR1 - description: "PWR Backup domain control register 1 " + description: PWR Backup domain control register 1 byte_offset: 32 fieldset: BDCR1 - name: BDCR2 - description: "PWR Backup domain control register 2 " + description: PWR Backup domain control register 2 byte_offset: 36 fieldset: BDCR2 - name: DBPR - description: "PWR disable Backup domain register " + description: PWR disable Backup domain register byte_offset: 40 fieldset: DBPR - name: UCPDR - description: "PWR USB Type-C™ and Power Delivery register " + description: PWR USB Type-C™ and Power Delivery register byte_offset: 44 fieldset: UCPDR - name: SECCFGR - description: "PWR security configuration register " + description: PWR security configuration register byte_offset: 48 fieldset: SECCFGR - name: PRIVCFGR - description: "PWR privilege control register " + description: PWR privilege control register byte_offset: 52 fieldset: PRIVCFGR - name: SR - description: "PWR status register " + description: PWR status register byte_offset: 56 fieldset: SR - name: SVMSR byte_offset: 60 fieldset: SVMSR - name: BDSR - description: "PWR Backup domain status register " + description: PWR Backup domain status register byte_offset: 64 fieldset: BDSR - name: WUSR - description: "PWR wakeup status register " + description: PWR wakeup status register byte_offset: 68 fieldset: WUSR - name: WUSCR - description: "PWR wakeup status clear register " + description: PWR wakeup status clear register byte_offset: 72 fieldset: WUSCR - name: APCR - description: "PWR apply pull configuration register " + description: PWR apply pull configuration register byte_offset: 76 fieldset: APCR - name: PUCR @@ -96,14 +96,14 @@ block/PWR: byte_offset: 84 fieldset: PCR fieldset/APCR: - description: "PWR apply pull configuration register " + description: PWR apply pull configuration register fields: - name: APC description: "Apply pull-up and pull-down configuration\r When this bit is set, the I/O pull-up and pull-down configurations defined in PUCRx and PDCRx are applied. When this bit is cleared, PUCRx and PDCRx are not applied to the I/Os." bit_offset: 0 bit_size: 1 fieldset/BDCR1: - description: "PWR Backup domain control register 1 " + description: PWR Backup domain control register 1 fields: - name: BREN description: "Backup RAM retention in Standby and VBAT modes\r When this bit is set, the backup RAM content is kept in Standby and VBAT modes.\r If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS.\r Note: Backup RAM cannot be preserved in Shutdown mode." @@ -114,7 +114,7 @@ fieldset/BDCR1: bit_offset: 4 bit_size: 1 fieldset/BDCR2: - description: "PWR Backup domain control register 2 " + description: PWR Backup domain control register 2 fields: - name: VBE description: VBAT charging enable @@ -127,7 +127,7 @@ fieldset/BDCR2: bit_size: 1 enum: VBRS fieldset/BDSR: - description: "PWR Backup domain status register " + description: PWR Backup domain status register fields: - name: VBATH description: Backup domain voltage level monitoring versus high threshold @@ -145,7 +145,7 @@ fieldset/BDSR: bit_size: 1 enum: TEMPH fieldset/CR1: - description: "PWR control register 1 " + description: PWR control register 1 fields: - name: LPMS description: "Low-power mode selection\r These bits select the low-power mode entered when the CPU enters the Deepsleep mode.\r 10x: Standby mode (Standby mode also entered if LPMS = 11X in CR1\r with BREN = 1 in BDCR1)\r 11x: Shutdown mode if BREN = 0 in BDCR1" @@ -187,7 +187,7 @@ fieldset/CR1: bit_size: 1 enum: SRAMPD fieldset/CR2: - description: "PWR control register 2 " + description: PWR control register 2 fields: - name: SRAM1PDS1 description: "SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)" @@ -300,7 +300,7 @@ fieldset/CR2: bit_size: 1 enum: SRDRUN fieldset/CR3: - description: "PWR control register 3 " + description: PWR control register 3 fields: - name: REGSEL description: "Regulator selection\r Note: REGSEL is reserved and must be kept at reset value in packages without SMPS." @@ -312,7 +312,7 @@ fieldset/CR3: bit_offset: 2 bit_size: 1 fieldset/DBPR: - description: "PWR disable Backup domain register " + description: PWR disable Backup domain register fields: - name: DBP description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers." @@ -330,7 +330,7 @@ fieldset/PCR: len: 16 stride: 1 fieldset/PRIVCFGR: - description: "PWR privilege control register " + description: PWR privilege control register fields: - name: SPRIV description: "PWR secure functions privilege configuration\r This bit is set and reset by software. It can be written only by a secure privileged access." @@ -343,7 +343,7 @@ fieldset/PRIVCFGR: bit_size: 1 enum: NSPRIV fieldset/SECCFGR: - description: "PWR security configuration register " + description: PWR security configuration register fields: - name: WUP1SEC description: WUP1 secure protection @@ -406,7 +406,7 @@ fieldset/SECCFGR: bit_size: 1 enum: APCSEC fieldset/SR: - description: "PWR status register " + description: PWR status register fields: - name: CSSF description: "Clear Stop and Standby flags\r This bit is protected against non-secure access when LPMSEC = 1 in SECCFGR.\r This bit is protected against unprivileged access when LPMSEC = 1 and SPRIV = 1 in PRIVCFGR, or when LPMSEC = 0 and NSPRIV = 1.\r Writing 1 to this bit clears the STOPF and SBF flags." @@ -423,7 +423,7 @@ fieldset/SR: bit_size: 1 enum: SBF fieldset/SVMCR: - description: "PWR supply voltage monitoring control register " + description: PWR supply voltage monitoring control register fields: - name: PVDE description: Power voltage detector enable @@ -509,7 +509,7 @@ fieldset/SVMSR: bit_size: 1 enum: VDDARDY fieldset/UCPDR: - description: "PWR USB Type-C™ and Power Delivery register " + description: PWR USB Type-C™ and Power Delivery register fields: - name: UCPD_DBDIS description: "UCPD dead battery disable\r After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable)." @@ -521,7 +521,7 @@ fieldset/UCPDR: bit_offset: 1 bit_size: 1 fieldset/VOSR: - description: "PWR voltage scaling register " + description: PWR voltage scaling register fields: - name: BOOSTRDY description: "EPOD booster ready\r This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set." @@ -543,7 +543,7 @@ fieldset/VOSR: bit_offset: 18 bit_size: 1 fieldset/WUCR1: - description: "PWR wakeup control register 1 " + description: PWR wakeup control register 1 fields: - name: WUPEN1 description: Wakeup pin WKUP1 enable @@ -578,7 +578,7 @@ fieldset/WUCR1: bit_offset: 7 bit_size: 1 fieldset/WUCR2: - description: "PWR wakeup control register 2 " + description: PWR wakeup control register 2 fields: - name: WUPP1 description: "Wakeup pin WKUP1 polarity.\r This bit must be configured when WUPEN1 = 0." @@ -621,7 +621,7 @@ fieldset/WUCR2: bit_size: 1 enum: WUPP fieldset/WUCR3: - description: "PWR wakeup control register 3 " + description: PWR wakeup control register 3 fields: - name: WUSEL1 description: "Wakeup pin WKUP1 selection\r This field must be configured when WUPEN1 = 0." @@ -664,7 +664,7 @@ fieldset/WUCR3: bit_size: 2 enum: WUSEL fieldset/WUSCR: - description: "PWR wakeup status clear register " + description: PWR wakeup status clear register fields: - name: CWUF1 description: "Wakeup flag 1\r Writing 1 to this bit clears the WUF1 flag in WUSR." @@ -699,7 +699,7 @@ fieldset/WUSCR: bit_offset: 7 bit_size: 1 fieldset/WUSR: - description: "PWR wakeup status register " + description: PWR wakeup status register fields: - name: WUF1 description: "Wakeup flag 1\r This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1 = 0." @@ -755,7 +755,7 @@ enum/ACTVOSRDY: description: "VCORE is above or below the current voltage scaling provided by ACTVOS[1:0]." value: 0 - name: B_0x1 - description: "VCORE is equal to the current voltage scaling provided by ACTVOS[1:0] " + description: "VCORE is equal to the current voltage scaling provided by ACTVOS[1:0]" value: 1 enum/APCSEC: bit_size: 1 @@ -902,25 +902,25 @@ enum/PVDLS: bit_size: 3 variants: - name: B_0x0 - description: "VPVD0 around 2.0 V " + description: VPVD0 around 2.0 V value: 0 - name: B_0x1 - description: "VPVD1 around 2.2 V " + description: VPVD1 around 2.2 V value: 1 - name: B_0x2 - description: "VPVD2 around 2.4 V " + description: VPVD2 around 2.4 V value: 2 - name: B_0x3 - description: "VPVD3 around 2.5 V " + description: VPVD3 around 2.5 V value: 3 - name: B_0x4 - description: "VPVD4 around 2.6 V " + description: VPVD4 around 2.6 V value: 4 - name: B_0x5 - description: "VPVD5 around 2.8 V " + description: VPVD5 around 2.8 V value: 5 - name: B_0x6 - description: "VPVD6 around 2.9 V " + description: VPVD6 around 2.9 V value: 6 - name: B_0x7 description: External input analog voltage PVD_IN (compared internally to VREFINT) @@ -932,7 +932,7 @@ enum/PVDO: description: "VDD is equal or above the PVD threshold selected by PVDLS[2:0]." value: 0 - name: B_0x1 - description: "VDD is below the PVD threshold selected by PVDLS[2:0]. " + description: "VDD is below the PVD threshold selected by PVDLS[2:0]." value: 1 enum/REGS: bit_size: 1 @@ -983,10 +983,10 @@ enum/SRAMFWU: bit_size: 1 variants: - name: B_0x0 - description: "SRAM4 enters low-power mode in Stop 0, 1 and 2 modes (source biasing for lower-power consumption). " + description: "SRAM4 enters low-power mode in Stop 0, 1 and 2 modes (source biasing for lower-power consumption)." value: 0 - name: B_0x1 - description: "SRAM4 remains in normal mode in Stop 0, 1 and 2 modes (higher consumption but no SRAM4 wakeup time). " + description: "SRAM4 remains in normal mode in Stop 0, 1 and 2 modes (higher consumption but no SRAM4 wakeup time)." value: 1 enum/SRAMPD: bit_size: 1 @@ -1067,7 +1067,7 @@ enum/VBATH: description: Backup domain voltage level < high threshold value: 0 - name: B_0x1 - description: "Backup domain voltage level ≥ high threshold " + description: Backup domain voltage level ≥ high threshold value: 1 enum/VBE: bit_size: 1 @@ -1100,10 +1100,10 @@ enum/VDDARDY: bit_size: 1 variants: - name: B_0x0 - description: "VDDA is below the threshold of the VDDA voltage monitor 2 (around 1.8 V). " + description: VDDA is below the threshold of the VDDA voltage monitor 2 (around 1.8 V). value: 0 - name: B_0x1 - description: "VDDA is equal or above the threshold of the VDDA voltage monitor 2 (around 1.8 V). " + description: VDDA is equal or above the threshold of the VDDA voltage monitor 2 (around 1.8 V). value: 1 enum/VDDIORDY: bit_size: 1 diff --git a/data/registers/rcc_g0.yaml b/data/registers/rcc_g0.yaml index 6947243..c448596 100644 --- a/data/registers/rcc_g0.yaml +++ b/data/registers/rcc_g0.yaml @@ -1172,321 +1172,489 @@ fieldset/PLLSYSCFGR: description: PLL VCO division factor R for PLLRCLK clock output bit_offset: 29 bit_size: 3 -enum/HSIDIV: - bit_size: 3 - variants: - - name: Div1 - description: HSI clock is not divided - value: 0b000 - - name: Div2 - description: HSI clock is divided by 2 - value: 0b001 - - name: Div4 - description: HSI clock is divided by 4 - value: 0b010 - - name: Div8 - description: HSI clock is divided by 8 - value: 0b011 - - name: Div16 - description: HSI clock is divided by 16 - value: 0b100 - - name: Div32 - description: HSI clock is divided by 32 - value: 0b101 - - name: Div64 - description: HSI clock is divided by 64 - value: 0b110 - - name: Div128 - description: HSI clock is divided by 128 - value: 0b111 -enum/MCOPRE: - bit_size: 4 - variants: - - name: Div1 - description: MCO1 not divided - value: 0b0000 - - name: Div2 - description: MCO1 clock is divided by 2 - value: 0b0001 - - name: Div4 - description: MCO1 clock is divided by 4 - value: 0b0010 - - name: Div8 - description: MCO1 clock is divided by 8 - value: 0b0011 - - name: Div16 - description: MCO1 clock is divided divided by 16 - value: 0b0100 - - name: Div32 - description: MCO1 clock is divided divided by 32 - value: 0b0101 - - name: Div64 - description: MCO1 clock is divided divided by 64 - value: 0b0110 - - name: Div128 - description: MCO1 clock is divided divided by 128 - value: 0b0111 - - name: Div256 - description: MCO1 clock is divided divided by 256 - value: 0b1000 - - name: Div512 - description: MCO1 clock is divided divided by 512 - value: 0b1001 - - name: Div1024 - description: MCO1 clock is divided divided by 1024 - value: 0b1010 -enum/MCOSEL: - bit_size: 4 - variants: - - name: NoClock - description: No clock, MCO output disabled - value: 0b0000 - - name: SYSCLK - description: SYSCLK selected as MCO1 source - value: 0b0001 - - name: HSI48 - description: HSI48 selected as MCO1 source - value: 0b0010 - - name: HSI16 - description: HSI16 selected as MCO1 source - value: 0b0011 - - name: HSE - description: HSE selected as MCO1 source - value: 0b0100 - - name: PLLRCLK - description: PLLRCLK selected as MCO1 source - value: 0b0101 - - name: LSI - description: LSI selected as MCO1 source - value: 0b0110 - - name: LSE - description: LSE selected as MCO1 source - value: 0b0111 - - name: PLLPCLK - description: PLLPCLK selected as MCO1 source - value: 0b1000 - - name: PLLQCLK - description: PLLQCLK selected as MCO1 source - value: 0b1001 - - name: RTCCLK - description: RTCCLK selected as MCO1 source - value: 0b1010 - - name: RTC_WKUP - description: RTC_Wakeup selected as MCO1 source - value: 0b1011 -enum/MCO2PRE: - bit_size: 4 - variants: - - name: Div1 - description: MCO2 not divided - value: 0b0000 - - name: Div2 - description: MCO2 clock is divided by 2 - value: 0b0001 - - name: Div4 - description: MCO2 clock is divided by 4 - value: 0b0010 - - name: Div8 - description: MCO2 clock is divided by 8 - value: 0b0011 - - name: Div16 - description: MCO2 clock is divided divided by 16 - value: 0b0100 - - name: Div32 - description: MCO2 clock is divided divided by 32 - value: 0b0101 - - name: Div64 - description: MCO2 clock is divided divided by 64 - value: 0b0110 - - name: Div128 - description: MCO2 clock is divided divided by 128 - value: 0b0111 - - name: Div256 - description: MCO2 clock is divided divided by 256 - value: 0b1000 - - name: Div512 - description: MCO2 clock is divided divided by 512 - value: 0b1001 - - name: Div1024 - description: MCO2 clock is divided divided by 1024 - value: 0b1010 -enum/MCO2SEL: - bit_size: 4 - variants: - - name: NoClock - description: No clock, MCO2 output disabled - value: 0b0000 - - name: SYSCLK - description: SYSCLK selected as MCO2 source - value: 0b0001 - - name: HSI48 - description: HSI48 selected as MCO2 source - value: 0b0010 - - name: HSI16 - description: HSI16 selected as MCO2 source - value: 0b0011 - - name: HSE - description: HSE selected as MCO2 source - value: 0b0100 - - name: PLLRCLK - description: PLLRCLK selected as MCO2 source - value: 0b0101 - - name: LSI - description: LSI selected as MCO2 source - value: 0b0110 - - name: LSE - description: LSE selected as MCO2 source - value: 0b0111 - - name: PLLPCLK - description: PLLPCLK selected as MCO2 source - value: 0b1000 - - name: PLLQCLK - description: PLLQCLK selected as MCO2 source - value: 0b1001 - - name: RTCCLK - description: RTCCLK selected as MCO2 source - value: 0b1010 - - name: RTC_WKUP - description: RTC_Wakeup selected as MCO2 source - value: 0b1011 -enum/PPRE: - bit_size: 4 - variants: - - name: Div1 - description: HCLK not divided - value: 0b00 - - name: Div2 - description: HCLK is divided by 2 - value: 0b100 - - name: Div4 - description: HCLK is divided by 4 - value: 0b101 - - name: Div8 - description: HCLK is divided by 8 - value: 0b110 - - name: Div16 - description: HCLK is divided by 16 - value: 0b111 -enum/HPRE: - bit_size: 4 - variants: - - name: Div1 - description: SYSCLK not divided - value: 0b0000 - - name: Div2 - description: SYSCLK is divided by 2 - value: 0b1000 - - name: Div4 - description: SYSCLK is divided by 4 - value: 0b1001 - - name: Div8 - description: SYSCLK is divided by 8 - value: 0b1010 - - name: Div16 - description: SYSCLK is divided by 16 - value: 0b1011 - - name: Div64 - description: SYSCLK is divided by 64 - value: 0b1100 - - name: Div128 - description: SYSCLK is divided by 128 - value: 0b1101 - - name: Div256 - description: SYSCLK is divided by 256 - value: 0b1110 - - name: Div512 - description: SYSCLK is divided by 512 - value: 0b1111 -enum/SWS: - bit_size: 3 - variants: - - name: HSI - description: HSI used as system clock - value: 0b000 - - name: HSE - description: HSE used as system clock - value: 0b001 - - name: PLLRCLK - description: PLLRCLK used as system clock - value: 0b010 - - name: LSI - description: LSI used as system clock - value: 0b011 - - name: LSE - description: LSE used as system clock - value: 0b100 -enum/SW: - bit_size: 3 - variants: - - name: HSI - description: HSI selected as system clock - value: 0b000 - - name: HSE - description: HSE selected as system clock - value: 0b001 - - name: PLLRCLK - description: PLLRCLK selected as system clock - value: 0b010 - - name: LSI - description: LSI selected as system clock - value: 0b011 - - name: LSE - description: LSE selected as system clock - value: 0b100 -enum/PLLSRC: - bit_size: 2 - variants: - - name: NoClock - description: No clock selected as PLL entry clock source - value: 0b00 - - name: HSI16 - description: HSI16 selected as PLL entry clock source - value: 0b10 - - name: HSE - description: HSE selected as PLL entry clock source - value: 0b11 enum/ADCSEL: bit_size: 2 variants: - name: SYSCLK description: SYSCLK used as ADC clock source - value: 0b00 + value: 0 - name: PLLPCLK description: PLLPCLK used as ADC clock source - value: 0b01 + value: 1 - name: HSI16 description: HSI16 used as ADC clock source - value: 0b10 + value: 2 +enum/CECSEL: + bit_size: 1 + variants: + - name: HSI16_Div488 + description: HSI16 divided by 488 used as CEC clock + value: 0 + - name: LSE + description: LSE used as CEC clock + value: 1 +enum/FDCANSEL: + bit_size: 2 + variants: + - name: PCLK + description: PCLK used as FDCAN clock source + value: 0 + - name: PLLQCLK + description: PLLQCLK used as FDCAN clock source + value: 1 + - name: HSE + description: HSE used as FDCAN clock source + value: 2 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK is divided by 2 + value: 8 + - name: Div4 + description: SYSCLK is divided by 4 + value: 9 + - name: Div8 + description: SYSCLK is divided by 8 + value: 10 + - name: Div16 + description: SYSCLK is divided by 16 + value: 11 + - name: Div64 + description: SYSCLK is divided by 64 + value: 12 + - name: Div128 + description: SYSCLK is divided by 128 + value: 13 + - name: Div256 + description: SYSCLK is divided by 256 + value: 14 + - name: Div512 + description: SYSCLK is divided by 512 + value: 15 +enum/HSIDIV: + bit_size: 3 + variants: + - name: Div1 + description: HSI clock is not divided + value: 0 + - name: Div2 + description: HSI clock is divided by 2 + value: 1 + - name: Div4 + description: HSI clock is divided by 4 + value: 2 + - name: Div8 + description: HSI clock is divided by 8 + value: 3 + - name: Div16 + description: HSI clock is divided by 16 + value: 4 + - name: Div32 + description: HSI clock is divided by 32 + value: 5 + - name: Div64 + description: HSI clock is divided by 64 + value: 6 + - name: Div128 + description: HSI clock is divided by 128 + value: 7 +enum/I2C1SEL: + bit_size: 2 + variants: + - name: PCLK + description: PCLK used as I2C1 clock source + value: 0 + - name: SYSCLK + description: SYSCLK used as I2C1 clock source + value: 1 + - name: HSI16 + description: HSI16 used as I2C1 clock source + value: 2 +enum/I2C2I2S1SEL: + bit_size: 2 + variants: + - name: PCLK + description: PCLK used as I2C2/I2S2 clock source + value: 0 + - name: SYSCLK + description: SYSCLK used as I2C2/I2S2 clock source + value: 1 + - name: HSI16 + description: HSI16 used as I2C2/I2S2 clock source + value: 2 + - name: I2S_CKIN + description: External clock used as I2C2/I2S2 clock source + value: 3 +enum/I2S1SEL: + bit_size: 2 + variants: + - name: SYSCLK + description: SYSCLK used as I2S1 clock source + value: 0 + - name: PLLPCLK + description: PLLPCLK used as I2S1 clock source + value: 1 + - name: HSI16 + description: HSI used as I2S1 clock source + value: 2 + - name: I2S_CKIN + description: External clock used as I2S1 clock source + value: 3 +enum/I2S2SEL: + bit_size: 2 + variants: + - name: SYSCLK + description: SYSCLK used as I2S2 clock source + value: 0 + - name: PLLPCLK + description: PLLPCLK used as I2S2 clock source + value: 1 + - name: HSI16 + description: HSI used as I2S2 clock source + value: 2 + - name: I2S_CKIN + description: External clock used as I2S2 clock source + value: 3 +enum/LPTIM1SEL: + bit_size: 2 + variants: + - name: PCLK + description: PCLK used as LPTIM1 clock source + value: 0 + - name: LSI + description: LSI used as LPTIM1 clock source + value: 1 + - name: HSI16 + description: HSI16 used as LPTIM1 clock source + value: 2 + - name: LSE + description: LSE used as LPTIM1 clock source + value: 3 +enum/LPTIM2SEL: + bit_size: 2 + variants: + - name: PCLK + description: PCLK used as LPTIM2 clock source + value: 0 + - name: LSI + description: LSI used as LPTIM2 clock source + value: 1 + - name: HSI16 + description: HSI16 used as LPTIM2 clock source + value: 2 + - name: LSE + description: LSE used as LPTIM2 clock source + value: 3 +enum/LPUART1SEL: + bit_size: 2 + variants: + - name: PCLK + description: PCLK used as LPUART1 clock source + value: 0 + - name: SYSCLK + description: SYSCLK used as LPUART1 clock source + value: 1 + - name: HSI16 + description: HSI16 used as LPUART1 clock source + value: 2 + - name: LSE + description: LSE used as LPUART1 clock source + value: 3 +enum/LPUART2SEL: + bit_size: 2 + variants: + - name: PCLK + description: PCLK used as LPUART2 clock source + value: 0 + - name: SYSCLK + description: SYSCLK used as LPUART2 clock source + value: 1 + - name: HSI16 + description: HSI16 used as LPUART2 clock source + value: 2 + - name: LSE + description: LSE used as LPUART2 clock source + value: 3 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Low + description: Low driving capability + value: 0 + - name: MediumLow + description: Medium low driving capability + value: 1 + - name: MediumHigh + description: Medium high driving capability + value: 2 + - name: High + description: High driving capability + value: 3 +enum/MCO2PRE: + bit_size: 4 + variants: + - name: Div1 + description: MCO2 not divided + value: 0 + - name: Div2 + description: MCO2 clock is divided by 2 + value: 1 + - name: Div4 + description: MCO2 clock is divided by 4 + value: 2 + - name: Div8 + description: MCO2 clock is divided by 8 + value: 3 + - name: Div16 + description: MCO2 clock is divided divided by 16 + value: 4 + - name: Div32 + description: MCO2 clock is divided divided by 32 + value: 5 + - name: Div64 + description: MCO2 clock is divided divided by 64 + value: 6 + - name: Div128 + description: MCO2 clock is divided divided by 128 + value: 7 + - name: Div256 + description: MCO2 clock is divided divided by 256 + value: 8 + - name: Div512 + description: MCO2 clock is divided divided by 512 + value: 9 + - name: Div1024 + description: MCO2 clock is divided divided by 1024 + value: 10 +enum/MCO2SEL: + bit_size: 4 + variants: + - name: NoClock + description: "No clock, MCO2 output disabled" + value: 0 + - name: SYSCLK + description: SYSCLK selected as MCO2 source + value: 1 + - name: HSI48 + description: HSI48 selected as MCO2 source + value: 2 + - name: HSI16 + description: HSI16 selected as MCO2 source + value: 3 + - name: HSE + description: HSE selected as MCO2 source + value: 4 + - name: PLLRCLK + description: PLLRCLK selected as MCO2 source + value: 5 + - name: LSI + description: LSI selected as MCO2 source + value: 6 + - name: LSE + description: LSE selected as MCO2 source + value: 7 + - name: PLLPCLK + description: PLLPCLK selected as MCO2 source + value: 8 + - name: PLLQCLK + description: PLLQCLK selected as MCO2 source + value: 9 + - name: RTCCLK + description: RTCCLK selected as MCO2 source + value: 10 + - name: RTC_WKUP + description: RTC_Wakeup selected as MCO2 source + value: 11 +enum/MCOPRE: + bit_size: 4 + variants: + - name: Div1 + description: MCO1 not divided + value: 0 + - name: Div2 + description: MCO1 clock is divided by 2 + value: 1 + - name: Div4 + description: MCO1 clock is divided by 4 + value: 2 + - name: Div8 + description: MCO1 clock is divided by 8 + value: 3 + - name: Div16 + description: MCO1 clock is divided divided by 16 + value: 4 + - name: Div32 + description: MCO1 clock is divided divided by 32 + value: 5 + - name: Div64 + description: MCO1 clock is divided divided by 64 + value: 6 + - name: Div128 + description: MCO1 clock is divided divided by 128 + value: 7 + - name: Div256 + description: MCO1 clock is divided divided by 256 + value: 8 + - name: Div512 + description: MCO1 clock is divided divided by 512 + value: 9 + - name: Div1024 + description: MCO1 clock is divided divided by 1024 + value: 10 +enum/MCOSEL: + bit_size: 4 + variants: + - name: NoClock + description: "No clock, MCO output disabled" + value: 0 + - name: SYSCLK + description: SYSCLK selected as MCO1 source + value: 1 + - name: HSI48 + description: HSI48 selected as MCO1 source + value: 2 + - name: HSI16 + description: HSI16 selected as MCO1 source + value: 3 + - name: HSE + description: HSE selected as MCO1 source + value: 4 + - name: PLLRCLK + description: PLLRCLK selected as MCO1 source + value: 5 + - name: LSI + description: LSI selected as MCO1 source + value: 6 + - name: LSE + description: LSE selected as MCO1 source + value: 7 + - name: PLLPCLK + description: PLLPCLK selected as MCO1 source + value: 8 + - name: PLLQCLK + description: PLLQCLK selected as MCO1 source + value: 9 + - name: RTCCLK + description: RTCCLK selected as MCO1 source + value: 10 + - name: RTC_WKUP + description: RTC_Wakeup selected as MCO1 source + value: 11 +enum/PLLSRC: + bit_size: 2 + variants: + - name: NoClock + description: No clock selected as PLL entry clock source + value: 0 + - name: HSI16 + description: HSI16 selected as PLL entry clock source + value: 2 + - name: HSE + description: HSE selected as PLL entry clock source + value: 3 +enum/PPRE: + bit_size: 4 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK is divided by 2 + value: 4 + - name: Div4 + description: HCLK is divided by 4 + value: 5 + - name: Div8 + description: HCLK is divided by 8 + value: 6 + - name: Div16 + description: HCLK is divided by 16 + value: 7 enum/RNGDIV: bit_size: 2 variants: - name: Div1 description: RNG clock is not divided - value: 0b00 + value: 0 - name: Div2 description: RNG clock is divided by 2 - value: 0b01 + value: 1 - name: Div4 description: RNG clock is divided by 4 - value: 0b10 + value: 2 - name: Div8 description: RNG clock is divided by 8 - value: 0b11 + value: 3 enum/RNGSEL: bit_size: 2 variants: - name: NoClock description: No clock used as RNG clock source - value: 0b00 + value: 0 - name: HSI16_Div8 description: HSI divided by 8 used as RNG clock source - value: 0b01 + value: 1 - name: SYSCLK description: SYSCLK used as RNG clock source - value: 0b10 + value: 2 - name: PLLQCLK description: PLLQCLK used as RNG clock source - value: 0b11 + value: 3 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock used as RTC clock + value: 0 + - name: LSE + description: LSE used as RTC clock + value: 1 + - name: LSI + description: LSI used as RTC clock + value: 2 + - name: HSE_Div32 + description: HSE divided by 32 used as RTC clock + value: 3 +enum/SW: + bit_size: 3 + variants: + - name: HSI + description: HSI selected as system clock + value: 0 + - name: HSE + description: HSE selected as system clock + value: 1 + - name: PLLRCLK + description: PLLRCLK selected as system clock + value: 2 + - name: LSI + description: LSI selected as system clock + value: 3 + - name: LSE + description: LSE selected as system clock + value: 4 +enum/SWS: + bit_size: 3 + variants: + - name: HSI + description: HSI used as system clock + value: 0 + - name: HSE + description: HSE used as system clock + value: 1 + - name: PLLRCLK + description: PLLRCLK used as system clock + value: 2 + - name: LSI + description: LSI used as system clock + value: 3 + - name: LSE + description: LSE used as system clock + value: 4 enum/TIM15SEL: bit_size: 1 variants: @@ -1501,232 +1669,64 @@ enum/TIM1SEL: variants: - name: TIMPCLK description: TIMPCLK used as TIM1 clock source - value: 0b0 + value: 0 - name: PLLQCLK description: PLLQCLK used as TIM1 clock source - value: 0b1 -enum/LPTIM2SEL: - bit_size: 2 - variants: - - name: PCLK - description: PCLK used as LPTIM2 clock source - value: 0b00 - - name: LSI - description: LSI used as LPTIM2 clock source - value: 0b01 - - name: HSI16 - description: HSI16 used as LPTIM2 clock source - value: 0b10 - - name: LSE - description: LSE used as LPTIM2 clock source - value: 0b11 -enum/LPTIM1SEL: - bit_size: 2 - variants: - - name: PCLK - description: PCLK used as LPTIM1 clock source - value: 0b00 - - name: LSI - description: LSI used as LPTIM1 clock source - value: 0b01 - - name: HSI16 - description: HSI16 used as LPTIM1 clock source - value: 0b10 - - name: LSE - description: LSE used as LPTIM1 clock source - value: 0b11 -enum/I2C2I2S1SEL: - bit_size: 2 - variants: - - name: PCLK - description: PCLK used as I2C2/I2S2 clock source - value: 0b00 - - name: SYSCLK - description: SYSCLK used as I2C2/I2S2 clock source - value: 0b01 - - name: HSI16 - description: HSI16 used as I2C2/I2S2 clock source - value: 0b10 - - name: I2S_CKIN - description: External clock used as I2C2/I2S2 clock source - value: 0b11 -enum/I2C1SEL: - bit_size: 2 - variants: - - name: PCLK - description: PCLK used as I2C1 clock source - value: 0b00 - - name: SYSCLK - description: SYSCLK used as I2C1 clock source - value: 0b01 - - name: HSI16 - description: HSI16 used as I2C1 clock source - value: 0b10 -enum/LPUART1SEL: - bit_size: 2 - variants: - - name: PCLK - description: PCLK used as LPUART1 clock source - value: 0b00 - - name: SYSCLK - description: SYSCLK used as LPUART1 clock source - value: 0b01 - - name: HSI16 - description: HSI16 used as LPUART1 clock source - value: 0b10 - - name: LSE - description: LSE used as LPUART1 clock source - value: 0b11 -enum/LPUART2SEL: - bit_size: 2 - variants: - - name: PCLK - description: PCLK used as LPUART2 clock source - value: 0b00 - - name: SYSCLK - description: SYSCLK used as LPUART2 clock source - value: 0b01 - - name: HSI16 - description: HSI16 used as LPUART2 clock source - value: 0b10 - - name: LSE - description: LSE used as LPUART2 clock source - value: 0b11 -enum/CECSEL: - bit_size: 1 - variants: - - name: HSI16_Div488 - description: HSI16 divided by 488 used as CEC clock - value: 0b0 - - name: LSE - description: LSE used as CEC clock - value: 0b1 -enum/USART3SEL: - bit_size: 2 - variants: - - name: PCLK - description: PCLK used as USART3 clock source - value: 0b00 - - name: SYSCLK - description: SYSCLK used as USART3 clock source - value: 0b01 - - name: HSI16 - description: HSI16 used as USART3 clock source - value: 0b10 - - name: LSE - description: LSE used as USART3 clock source - value: 0b11 -enum/USART2SEL: - bit_size: 2 - variants: - - name: PCLK - description: PCLK used as USART2 clock source - value: 0b00 - - name: SYSCLK - description: SYSCLK used as USART2 clock source - value: 0b01 - - name: HSI16 - description: HSI16 used as USART2 clock source - value: 0b10 - - name: LSE - description: LSE used as USART2 clock source - value: 0b11 + value: 1 enum/USART1SEL: bit_size: 2 variants: - name: PCLK description: PCLK used as USART1 clock source - value: 0b00 + value: 0 - name: SYSCLK description: SYSCLK used as USART1 clock source - value: 0b01 + value: 1 - name: HSI16 description: HSI16 used as USART1 clock source - value: 0b10 + value: 2 - name: LSE description: LSE used as USART1 clock source - value: 0b11 + value: 3 +enum/USART2SEL: + bit_size: 2 + variants: + - name: PCLK + description: PCLK used as USART2 clock source + value: 0 + - name: SYSCLK + description: SYSCLK used as USART2 clock source + value: 1 + - name: HSI16 + description: HSI16 used as USART2 clock source + value: 2 + - name: LSE + description: LSE used as USART2 clock source + value: 3 +enum/USART3SEL: + bit_size: 2 + variants: + - name: PCLK + description: PCLK used as USART3 clock source + value: 0 + - name: SYSCLK + description: SYSCLK used as USART3 clock source + value: 1 + - name: HSI16 + description: HSI16 used as USART3 clock source + value: 2 + - name: LSE + description: LSE used as USART3 clock source + value: 3 enum/USBSEL: bit_size: 2 variants: - name: HSI48 description: HSI48 used as USB clock source - value: 0b00 + value: 0 - name: PLLQCLK description: PLLQCLK used as USB clock source - value: 0b01 + value: 1 - name: HSE description: HSE used as USB clock source - value: 0b10 -enum/FDCANSEL: - bit_size: 2 - variants: - - name: PCLK - description: PCLK used as FDCAN clock source - value: 0b00 - - name: PLLQCLK - description: PLLQCLK used as FDCAN clock source - value: 0b01 - - name: HSE - description: HSE used as FDCAN clock source - value: 0b10 -enum/I2S2SEL: - bit_size: 2 - variants: - - name: SYSCLK - description: SYSCLK used as I2S2 clock source - value: 0b00 - - name: PLLPCLK - description: PLLPCLK used as I2S2 clock source - value: 0b01 - - name: HSI16 - description: HSI used as I2S2 clock source - value: 0b10 - - name: I2S_CKIN - description: External clock used as I2S2 clock source - value: 0b11 -enum/I2S1SEL: - bit_size: 2 - variants: - - name: SYSCLK - description: SYSCLK used as I2S1 clock source - value: 0b00 - - name: PLLPCLK - description: PLLPCLK used as I2S1 clock source - value: 0b01 - - name: HSI16 - description: HSI used as I2S1 clock source - value: 0b10 - - name: I2S_CKIN - description: External clock used as I2S1 clock source - value: 0b11 -enum/RTCSEL: - bit_size: 2 - variants: - - name: NoClock - description: No clock used as RTC clock - value: 0b00 - - name: LSE - description: LSE used as RTC clock - value: 0b01 - - name: LSI - description: LSI used as RTC clock - value: 0b10 - - name: HSE_Div32 - description: HSE divided by 32 used as RTC clock - value: 0b11 -enum/LSEDRV: - bit_size: 2 - variants: - - name: Low - description: Low driving capability - value: 0b00 - - name: MediumLow - description: Medium low driving capability - value: 0b01 - - name: MediumHigh - description: Medium high driving capability - value: 0b10 - - name: High - description: High driving capability - value: 0b11 + value: 2 diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index 6e88a9b..ad247b0 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -322,7 +322,7 @@ fieldset/AHB1ENR: bit_offset: 17 bit_size: 1 - name: USB2OTGHSULPIEN - description: " Enable USB_PHY2 clocks " + description: Enable USB_PHY2 clocks bit_offset: 18 bit_size: 1 - name: USB1OTGEN diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml index eedd8ee..05d1795 100644 --- a/data/registers/rcc_h7ab.yaml +++ b/data/registers/rcc_h7ab.yaml @@ -246,7 +246,7 @@ fieldset/AHB1ENR: bit_offset: 17 bit_size: 1 - name: USB2OTGHSULPIEN - description: " Enable USB_PHY2 clocks " + description: Enable USB_PHY2 clocks bit_offset: 18 bit_size: 1 - name: USB1OTGEN @@ -700,14 +700,14 @@ fieldset/AHB4ENR: description: CRC peripheral clock enable bit_offset: 19 bit_size: 1 - - name: BDMAEN - description: BDMA and DMAMUX2 Clock Enable - bit_offset: 21 - bit_size: 1 - name: BDMA2EN description: BDMA2 and DMAMUX2 Clock Enable bit_offset: 21 bit_size: 1 + - name: BDMAEN + description: BDMA and DMAMUX2 Clock Enable + bit_offset: 21 + bit_size: 1 - name: ADC3EN description: ADC3 Peripheral Clocks Enable bit_offset: 24 @@ -771,14 +771,14 @@ fieldset/AHB4LPENR: description: CRC peripheral clock enable during CSleep mode bit_offset: 19 bit_size: 1 - - name: BDMALPEN - description: BDMA Clock Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - name: BDMA2LPEN description: BDMA2 Clock Enable During CSleep Mode bit_offset: 21 bit_size: 1 + - name: BDMALPEN + description: BDMA Clock Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 - name: ADC3LPEN description: ADC3 Peripheral Clocks Enable During CSleep Mode bit_offset: 24 @@ -842,14 +842,14 @@ fieldset/AHB4RSTR: description: CRC block reset bit_offset: 19 bit_size: 1 - - name: BDMARST - description: BDMA block reset - bit_offset: 21 - bit_size: 1 - name: BDMA2RST description: BDMA2 block reset bit_offset: 21 bit_size: 1 + - name: BDMARST + description: BDMA block reset + bit_offset: 21 + bit_size: 1 - name: ADC3RST description: ADC3 block reset bit_offset: 24 @@ -2163,14 +2163,14 @@ fieldset/D2CFGR: fieldset/D3AMR: description: RCC D3 Autonomous mode Register fields: - - name: BDMAAMEN - description: BDMA and DMAMUX Autonomous mode enable - bit_offset: 0 - bit_size: 1 - name: BDMA2AMEN description: BDMA2 and DMAMUX Autonomous mode enable bit_offset: 0 bit_size: 1 + - name: BDMAAMEN + description: BDMA and DMAMUX Autonomous mode enable + bit_offset: 0 + bit_size: 1 - name: LPUART1AMEN description: LPUART1 Autonomous mode enable bit_offset: 3 diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml index 7ee9c5a..df38606 100644 --- a/data/registers/rcc_l5.yaml +++ b/data/registers/rcc_l5.yaml @@ -7,7 +7,7 @@ block/RCC: byte_offset: 0 fieldset: CR - name: ICSCR - description: " Internal clock sources calibration register " + description: Internal clock sources calibration register byte_offset: 4 fieldset: ICSCR - name: CFGR @@ -27,7 +27,7 @@ block/RCC: byte_offset: 20 fieldset: PLLSAI2CFGR - name: CIER - description: " Clock interrupt enable register " + description: Clock interrupt enable register byte_offset: 24 fieldset: CIER - name: CIFR @@ -53,11 +53,11 @@ block/RCC: byte_offset: 48 fieldset: AHB3RSTR - name: APB1RSTR1 - description: " APB1 peripheral reset register 1 " + description: APB1 peripheral reset register 1 byte_offset: 56 fieldset: APB1RSTR1 - name: APB1RSTR2 - description: " APB1 peripheral reset register 2 " + description: APB1 peripheral reset register 2 byte_offset: 60 fieldset: APB1RSTR2 - name: APB2RSTR @@ -65,15 +65,15 @@ block/RCC: byte_offset: 64 fieldset: APB2RSTR - name: AHB1ENR - description: " AHB1 peripheral clock enable register " + description: AHB1 peripheral clock enable register byte_offset: 72 fieldset: AHB1ENR - name: AHB2ENR - description: " AHB2 peripheral clock enable register " + description: AHB2 peripheral clock enable register byte_offset: 76 fieldset: AHB2ENR - name: AHB3ENR - description: " AHB3 peripheral clock enable register " + description: AHB3 peripheral clock enable register byte_offset: 80 fieldset: AHB3ENR - name: APB1ENR1 @@ -81,7 +81,7 @@ block/RCC: byte_offset: 88 fieldset: APB1ENR1 - name: APB1ENR2 - description: " APB1 peripheral clock enable register 2 " + description: APB1 peripheral clock enable register 2 byte_offset: 92 fieldset: APB1ENR2 - name: APB2ENR @@ -89,15 +89,15 @@ block/RCC: byte_offset: 96 fieldset: APB2ENR - name: AHB1SMENR - description: " AHB1 peripheral clocks enable in Sleep and Stop modes register " + description: AHB1 peripheral clocks enable in Sleep and Stop modes register byte_offset: 104 fieldset: AHB1SMENR - name: AHB2SMENR - description: " AHB2 peripheral clocks enable in Sleep and Stop modes register " + description: AHB2 peripheral clocks enable in Sleep and Stop modes register byte_offset: 108 fieldset: AHB2SMENR - name: AHB3SMENR - description: " AHB3 peripheral clocks enable in Sleep and Stop modes register " + description: AHB3 peripheral clocks enable in Sleep and Stop modes register byte_offset: 112 fieldset: AHB3SMENR - name: APB1SMENR1 @@ -105,7 +105,7 @@ block/RCC: byte_offset: 120 fieldset: APB1SMENR1 - name: APB1SMENR2 - description: " APB1 peripheral clocks enable in Sleep and Stop modes register 2 " + description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 byte_offset: 124 fieldset: APB1SMENR2 - name: APB2SMENR @@ -129,11 +129,11 @@ block/RCC: byte_offset: 152 fieldset: CRRCR - name: CCIPR2 - description: " Peripherals independent clock configuration register " + description: Peripherals independent clock configuration register byte_offset: 156 fieldset: CCIPR2 - name: SECCFGR - description: " RCC secure configuration register " + description: RCC secure configuration register byte_offset: 184 fieldset: SECCFGR - name: SECSR @@ -141,37 +141,37 @@ block/RCC: byte_offset: 188 fieldset: SECSR - name: AHB1SECSR - description: " RCC AHB1 security status register " + description: RCC AHB1 security status register byte_offset: 232 access: Read fieldset: AHB1SECSR - name: AHB2SECSR - description: " RCC AHB2 security status register " + description: RCC AHB2 security status register byte_offset: 236 access: Read fieldset: AHB2SECSR - name: AHB3SECSR - description: " RCC AHB3 security status register " + description: RCC AHB3 security status register byte_offset: 240 access: Read fieldset: AHB3SECSR - name: APB1SECSR1 - description: " RCC APB1 security status register 1 " + description: RCC APB1 security status register 1 byte_offset: 248 access: Read fieldset: APB1SECSR1 - name: APB1SECSR2 - description: " RCC APB1 security status register 2 " + description: RCC APB1 security status register 2 byte_offset: 252 access: Read fieldset: APB1SECSR2 - name: APB2SECSR - description: " RCC APB2 security status register " + description: RCC APB2 security status register byte_offset: 256 access: Read fieldset: APB2SECSR fieldset/AHB1ENR: - description: " AHB1 peripheral clock enable register " + description: AHB1 peripheral clock enable register fields: - name: DMA1EN description: DMA1 clock enable @@ -186,7 +186,7 @@ fieldset/AHB1ENR: bit_offset: 2 bit_size: 1 - name: FLASHEN - description: " Flash memory interface clock enable " + description: Flash memory interface clock enable bit_offset: 8 bit_size: 1 - name: CRCEN @@ -194,7 +194,7 @@ fieldset/AHB1ENR: bit_offset: 12 bit_size: 1 - name: TSCEN - description: " Touch Sensing Controller clock enable " + description: Touch Sensing Controller clock enable bit_offset: 16 bit_size: 1 - name: GTZCEN @@ -217,7 +217,7 @@ fieldset/AHB1RSTR: bit_offset: 2 bit_size: 1 - name: FLASHRST - description: " Flash memory interface reset " + description: Flash memory interface reset bit_offset: 8 bit_size: 1 - name: CRCRST @@ -225,7 +225,7 @@ fieldset/AHB1RSTR: bit_offset: 12 bit_size: 1 - name: TSCRST - description: " Touch Sensing Controller reset " + description: Touch Sensing Controller reset bit_offset: 16 bit_size: 1 - name: GTZCRST @@ -233,7 +233,7 @@ fieldset/AHB1RSTR: bit_offset: 22 bit_size: 1 fieldset/AHB1SECSR: - description: " RCC AHB1 security status register " + description: RCC AHB1 security status register fields: - name: DMA1SECF description: DMA1SECF @@ -272,26 +272,26 @@ fieldset/AHB1SECSR: bit_offset: 23 bit_size: 1 fieldset/AHB1SMENR: - description: " AHB1 peripheral clocks enable in Sleep and Stop modes register " + description: AHB1 peripheral clocks enable in Sleep and Stop modes register fields: - name: DMA1SMEN - description: " DMA1 clocks enable during Sleep and Stop modes " + description: DMA1 clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: DMA2SMEN - description: " DMA2 clocks enable during Sleep and Stop modes " + description: DMA2 clocks enable during Sleep and Stop modes bit_offset: 1 bit_size: 1 - name: DMAMUX1SMEN - description: " DMAMUX clock enable during Sleep and Stop modes " + description: DMAMUX clock enable during Sleep and Stop modes bit_offset: 2 bit_size: 1 - name: FLASHSMEN - description: " Flash memory interface clocks enable during Sleep and Stop modes " + description: Flash memory interface clocks enable during Sleep and Stop modes bit_offset: 8 bit_size: 1 - name: SRAM1SMEN - description: " SRAM1 interface clocks enable during Sleep and Stop modes " + description: SRAM1 interface clocks enable during Sleep and Stop modes bit_offset: 9 bit_size: 1 - name: CRCSMEN @@ -299,7 +299,7 @@ fieldset/AHB1SMENR: bit_offset: 12 bit_size: 1 - name: TSCSMEN - description: " Touch Sensing Controller clocks enable during Sleep and Stop modes " + description: Touch Sensing Controller clocks enable during Sleep and Stop modes bit_offset: 16 bit_size: 1 - name: GTZCSMEN @@ -311,7 +311,7 @@ fieldset/AHB1SMENR: bit_offset: 23 bit_size: 1 fieldset/AHB2ENR: - description: " AHB2 peripheral clock enable register " + description: AHB2 peripheral clock enable register fields: - name: GPIOAEN description: IO port A clock enable @@ -350,7 +350,7 @@ fieldset/AHB2ENR: bit_offset: 13 bit_size: 1 - name: AESEN - description: " AES accelerator clock enable " + description: AES accelerator clock enable bit_offset: 16 bit_size: 1 - name: HASHEN @@ -358,7 +358,7 @@ fieldset/AHB2ENR: bit_offset: 17 bit_size: 1 - name: RNGEN - description: " Random Number Generator clock enable " + description: Random Number Generator clock enable bit_offset: 18 bit_size: 1 - name: PKAEN @@ -413,7 +413,7 @@ fieldset/AHB2RSTR: bit_offset: 13 bit_size: 1 - name: AESRST - description: " AES hardware accelerator reset " + description: AES hardware accelerator reset bit_offset: 16 bit_size: 1 - name: HASHRST @@ -421,7 +421,7 @@ fieldset/AHB2RSTR: bit_offset: 17 bit_size: 1 - name: RNGRST - description: " Random number generator reset " + description: Random number generator reset bit_offset: 18 bit_size: 1 - name: PKARST @@ -437,7 +437,7 @@ fieldset/AHB2RSTR: bit_offset: 22 bit_size: 1 fieldset/AHB2SECSR: - description: " RCC AHB2 security status register " + description: RCC AHB2 security status register fields: - name: GPIOASECF description: GPIOASECF @@ -484,58 +484,58 @@ fieldset/AHB2SECSR: bit_offset: 22 bit_size: 1 fieldset/AHB2SMENR: - description: " AHB2 peripheral clocks enable in Sleep and Stop modes register " + description: AHB2 peripheral clocks enable in Sleep and Stop modes register fields: - name: GPIOASMEN - description: " IO port A clocks enable during Sleep and Stop modes " + description: IO port A clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: GPIOBSMEN - description: " IO port B clocks enable during Sleep and Stop modes " + description: IO port B clocks enable during Sleep and Stop modes bit_offset: 1 bit_size: 1 - name: GPIOCSMEN - description: " IO port C clocks enable during Sleep and Stop modes " + description: IO port C clocks enable during Sleep and Stop modes bit_offset: 2 bit_size: 1 - name: GPIODSMEN - description: " IO port D clocks enable during Sleep and Stop modes " + description: IO port D clocks enable during Sleep and Stop modes bit_offset: 3 bit_size: 1 - name: GPIOESMEN - description: " IO port E clocks enable during Sleep and Stop modes " + description: IO port E clocks enable during Sleep and Stop modes bit_offset: 4 bit_size: 1 - name: GPIOFSMEN - description: " IO port F clocks enable during Sleep and Stop modes " + description: IO port F clocks enable during Sleep and Stop modes bit_offset: 5 bit_size: 1 - name: GPIOGSMEN - description: " IO port G clocks enable during Sleep and Stop modes " + description: IO port G clocks enable during Sleep and Stop modes bit_offset: 6 bit_size: 1 - name: GPIOHSMEN - description: " IO port H clocks enable during Sleep and Stop modes " + description: IO port H clocks enable during Sleep and Stop modes bit_offset: 7 bit_size: 1 - name: SRAM2SMEN - description: " SRAM2 interface clocks enable during Sleep and Stop modes " + description: SRAM2 interface clocks enable during Sleep and Stop modes bit_offset: 9 bit_size: 1 - name: ADCFSSMEN - description: " ADC clocks enable during Sleep and Stop modes " + description: ADC clocks enable during Sleep and Stop modes bit_offset: 13 bit_size: 1 - name: AESSMEN - description: " AES accelerator clocks enable during Sleep and Stop modes " + description: AES accelerator clocks enable during Sleep and Stop modes bit_offset: 16 bit_size: 1 - name: HASHSMEN - description: " HASH clock enable during Sleep and Stop modes " + description: HASH clock enable during Sleep and Stop modes bit_offset: 17 bit_size: 1 - name: RNGSMEN - description: " Random Number Generator clocks enable during Sleep and Stop modes " + description: Random Number Generator clocks enable during Sleep and Stop modes bit_offset: 18 bit_size: 1 - name: PKASMEN @@ -547,14 +547,14 @@ fieldset/AHB2SMENR: bit_offset: 21 bit_size: 1 - name: SDMMC1SMEN - description: " SDMMC1 clocks enable during Sleep and Stop modes " + description: SDMMC1 clocks enable during Sleep and Stop modes bit_offset: 22 bit_size: 1 fieldset/AHB3ENR: - description: " AHB3 peripheral clock enable register " + description: AHB3 peripheral clock enable register fields: - name: FMCEN - description: " Flexible memory controller clock enable " + description: Flexible memory controller clock enable bit_offset: 0 bit_size: 1 - name: OSPI1EN @@ -565,7 +565,7 @@ fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - name: FMCRST - description: " Flexible memory controller reset " + description: Flexible memory controller reset bit_offset: 0 bit_size: 1 - name: OSPI1RST @@ -573,7 +573,7 @@ fieldset/AHB3RSTR: bit_offset: 8 bit_size: 1 fieldset/AHB3SECSR: - description: " RCC AHB3 security status register " + description: RCC AHB3 security status register fields: - name: FSMCSECF description: FSMCSECF @@ -584,10 +584,10 @@ fieldset/AHB3SECSR: bit_offset: 8 bit_size: 1 fieldset/AHB3SMENR: - description: " AHB3 peripheral clocks enable in Sleep and Stop modes register " + description: AHB3 peripheral clocks enable in Sleep and Stop modes register fields: - name: FMCSMEN - description: " Flexible memory controller clocks enable during Sleep and Stop modes " + description: Flexible memory controller clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: OSPI1SMEN @@ -626,7 +626,7 @@ fieldset/APB1ENR1: bit_offset: 10 bit_size: 1 - name: WWDGEN - description: " Window watchdog clock enable " + description: Window watchdog clock enable bit_offset: 11 bit_size: 1 - name: SPI2EN @@ -666,30 +666,30 @@ fieldset/APB1ENR1: bit_offset: 23 bit_size: 1 - name: CRSEN - description: " Clock Recovery System clock enable " + description: Clock Recovery System clock enable bit_offset: 24 bit_size: 1 - name: PWREN - description: " Power interface clock enable " + description: Power interface clock enable bit_offset: 28 bit_size: 1 - name: DAC1EN - description: " DAC1 interface clock enable " + description: DAC1 interface clock enable bit_offset: 29 bit_size: 1 - name: OPAMPEN - description: " OPAMP interface clock enable " + description: OPAMP interface clock enable bit_offset: 30 bit_size: 1 - name: LPTIM1EN - description: " Low power timer 1 clock enable " + description: Low power timer 1 clock enable bit_offset: 31 bit_size: 1 fieldset/APB1ENR2: - description: " APB1 peripheral clock enable register 2 " + description: APB1 peripheral clock enable register 2 fields: - name: LPUART1EN - description: " Low power UART 1 clock enable " + description: Low power UART 1 clock enable bit_offset: 0 bit_size: 1 - name: I2C4EN @@ -717,7 +717,7 @@ fieldset/APB1ENR2: bit_offset: 23 bit_size: 1 fieldset/APB1RSTR1: - description: " APB1 peripheral reset register 1 " + description: APB1 peripheral reset register 1 fields: - name: TIM2RST description: TIM2 timer reset @@ -800,7 +800,7 @@ fieldset/APB1RSTR1: bit_offset: 31 bit_size: 1 fieldset/APB1RSTR2: - description: " APB1 peripheral reset register 2 " + description: APB1 peripheral reset register 2 fields: - name: LPUART1RST description: Low-power UART 1 reset @@ -831,7 +831,7 @@ fieldset/APB1RSTR2: bit_offset: 23 bit_size: 1 fieldset/APB1SECSR1: - description: " RCC APB1 security status register 1 " + description: RCC APB1 security status register 1 fields: - name: TIM2SECF description: TIM2SECF @@ -922,7 +922,7 @@ fieldset/APB1SECSR1: bit_offset: 31 bit_size: 1 fieldset/APB1SECSR2: - description: " RCC APB1 security status register 2 " + description: RCC APB1 security status register 2 fields: - name: LPUART1SECF description: LPUART1SECF @@ -956,102 +956,102 @@ fieldset/APB1SMENR1: description: APB1SMENR1 fields: - name: TIM2SMEN - description: " TIM2 timer clocks enable during Sleep and Stop modes " + description: TIM2 timer clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: TIM3SMEN - description: " TIM3 timer clocks enable during Sleep and Stop modes " + description: TIM3 timer clocks enable during Sleep and Stop modes bit_offset: 1 bit_size: 1 - name: TIM4SMEN - description: " TIM4 timer clocks enable during Sleep and Stop modes " + description: TIM4 timer clocks enable during Sleep and Stop modes bit_offset: 2 bit_size: 1 - name: TIM5SMEN - description: " TIM5 timer clocks enable during Sleep and Stop modes " + description: TIM5 timer clocks enable during Sleep and Stop modes bit_offset: 3 bit_size: 1 - name: TIM6SMEN - description: " TIM6 timer clocks enable during Sleep and Stop modes " + description: TIM6 timer clocks enable during Sleep and Stop modes bit_offset: 4 bit_size: 1 - name: TIM7SMEN - description: " TIM7 timer clocks enable during Sleep and Stop modes " + description: TIM7 timer clocks enable during Sleep and Stop modes bit_offset: 5 bit_size: 1 - name: RTCAPBSMEN - description: " RTC APB clock enable during Sleep and Stop modes " + description: RTC APB clock enable during Sleep and Stop modes bit_offset: 10 bit_size: 1 - name: WWDGSMEN - description: " Window watchdog clocks enable during Sleep and Stop modes " + description: Window watchdog clocks enable during Sleep and Stop modes bit_offset: 11 bit_size: 1 - name: SPI2SMEN - description: " SPI2 clocks enable during Sleep and Stop modes " + description: SPI2 clocks enable during Sleep and Stop modes bit_offset: 14 bit_size: 1 - name: SP3SMEN - description: " SPI3 clocks enable during Sleep and Stop modes " + description: SPI3 clocks enable during Sleep and Stop modes bit_offset: 15 bit_size: 1 - name: USART2SMEN - description: " USART2 clocks enable during Sleep and Stop modes " + description: USART2 clocks enable during Sleep and Stop modes bit_offset: 17 bit_size: 1 - name: USART3SMEN - description: " USART3 clocks enable during Sleep and Stop modes " + description: USART3 clocks enable during Sleep and Stop modes bit_offset: 18 bit_size: 1 - name: UART4SMEN - description: " UART4 clocks enable during Sleep and Stop modes " + description: UART4 clocks enable during Sleep and Stop modes bit_offset: 19 bit_size: 1 - name: UART5SMEN - description: " UART5 clocks enable during Sleep and Stop modes " + description: UART5 clocks enable during Sleep and Stop modes bit_offset: 20 bit_size: 1 - name: I2C1SMEN - description: " I2C1 clocks enable during Sleep and Stop modes " + description: I2C1 clocks enable during Sleep and Stop modes bit_offset: 21 bit_size: 1 - name: I2C2SMEN - description: " I2C2 clocks enable during Sleep and Stop modes " + description: I2C2 clocks enable during Sleep and Stop modes bit_offset: 22 bit_size: 1 - name: I2C3SMEN - description: " I2C3 clocks enable during Sleep and Stop modes " + description: I2C3 clocks enable during Sleep and Stop modes bit_offset: 23 bit_size: 1 - name: CRSSMEN - description: " CRS clock enable during Sleep and Stop modes " + description: CRS clock enable during Sleep and Stop modes bit_offset: 24 bit_size: 1 - name: PWRSMEN - description: " Power interface clocks enable during Sleep and Stop modes " + description: Power interface clocks enable during Sleep and Stop modes bit_offset: 28 bit_size: 1 - name: DAC1SMEN - description: " DAC1 interface clocks enable during Sleep and Stop modes " + description: DAC1 interface clocks enable during Sleep and Stop modes bit_offset: 29 bit_size: 1 - name: OPAMPSMEN - description: " OPAMP interface clocks enable during Sleep and Stop modes " + description: OPAMP interface clocks enable during Sleep and Stop modes bit_offset: 30 bit_size: 1 - name: LPTIM1SMEN - description: " Low power timer 1 clocks enable during Sleep and Stop modes " + description: Low power timer 1 clocks enable during Sleep and Stop modes bit_offset: 31 bit_size: 1 fieldset/APB1SMENR2: - description: " APB1 peripheral clocks enable in Sleep and Stop modes register 2 " + description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 fields: - name: LPUART1SMEN - description: " Low power UART 1 clocks enable during Sleep and Stop modes " + description: Low power UART 1 clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: I2C4SMEN - description: " I2C4 clocks enable during Sleep and Stop modes " + description: I2C4 clocks enable during Sleep and Stop modes bit_offset: 1 bit_size: 1 - name: LPTIM2SMEN @@ -1125,7 +1125,7 @@ fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - name: SYSCFGRST - description: " System configuration (SYSCFG) reset " + description: System configuration (SYSCFG) reset bit_offset: 0 bit_size: 1 - name: TIM1RST @@ -1157,19 +1157,19 @@ fieldset/APB2RSTR: bit_offset: 18 bit_size: 1 - name: SAI1RST - description: " Serial audio interface 1 (SAI1) reset " + description: Serial audio interface 1 (SAI1) reset bit_offset: 21 bit_size: 1 - name: SAI2RST - description: " Serial audio interface 2 (SAI2) reset " + description: Serial audio interface 2 (SAI2) reset bit_offset: 22 bit_size: 1 - name: DFSDM1RST - description: " Digital filters for sigma-delata modulators (DFSDM) reset " + description: Digital filters for sigma-delata modulators (DFSDM) reset bit_offset: 24 bit_size: 1 fieldset/APB2SECSR: - description: " RCC APB2 security status register " + description: RCC APB2 security status register fields: - name: SYSCFGSECF description: SYSCFGSECF @@ -1219,47 +1219,47 @@ fieldset/APB2SMENR: description: APB2SMENR fields: - name: SYSCFGSMEN - description: " SYSCFG clocks enable during Sleep and Stop modes " + description: SYSCFG clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: TIM1SMEN - description: " TIM1 timer clocks enable during Sleep and Stop modes " + description: TIM1 timer clocks enable during Sleep and Stop modes bit_offset: 11 bit_size: 1 - name: SPI1SMEN - description: " SPI1 clocks enable during Sleep and Stop modes " + description: SPI1 clocks enable during Sleep and Stop modes bit_offset: 12 bit_size: 1 - name: TIM8SMEN - description: " TIM8 timer clocks enable during Sleep and Stop modes " + description: TIM8 timer clocks enable during Sleep and Stop modes bit_offset: 13 bit_size: 1 - name: USART1SMEN - description: " USART1clocks enable during Sleep and Stop modes " + description: USART1clocks enable during Sleep and Stop modes bit_offset: 14 bit_size: 1 - name: TIM15SMEN - description: " TIM15 timer clocks enable during Sleep and Stop modes " + description: TIM15 timer clocks enable during Sleep and Stop modes bit_offset: 16 bit_size: 1 - name: TIM16SMEN - description: " TIM16 timer clocks enable during Sleep and Stop modes " + description: TIM16 timer clocks enable during Sleep and Stop modes bit_offset: 17 bit_size: 1 - name: TIM17SMEN - description: " TIM17 timer clocks enable during Sleep and Stop modes " + description: TIM17 timer clocks enable during Sleep and Stop modes bit_offset: 18 bit_size: 1 - name: SAI1SMEN - description: " SAI1 clocks enable during Sleep and Stop modes " + description: SAI1 clocks enable during Sleep and Stop modes bit_offset: 21 bit_size: 1 - name: SAI2SMEN - description: " SAI2 clocks enable during Sleep and Stop modes " + description: SAI2 clocks enable during Sleep and Stop modes bit_offset: 22 bit_size: 1 - name: DFSDM1SMEN - description: " DFSDM timer clocks enable during Sleep and Stop modes " + description: DFSDM timer clocks enable during Sleep and Stop modes bit_offset: 24 bit_size: 1 fieldset/BDCR: @@ -1278,7 +1278,7 @@ fieldset/BDCR: bit_offset: 2 bit_size: 1 - name: LSEDRV - description: " SE oscillator drive capability " + description: SE oscillator drive capability bit_offset: 3 bit_size: 2 enum: LSEDRV @@ -1308,15 +1308,15 @@ fieldset/BDCR: bit_offset: 15 bit_size: 1 - name: BDRST - description: " Backup domain software reset " + description: Backup domain software reset bit_offset: 16 bit_size: 1 - name: LSCOEN - description: " Low speed clock output enable " + description: Low speed clock output enable bit_offset: 24 bit_size: 1 - name: LSCOSEL - description: " Low speed clock output selection " + description: Low speed clock output selection bit_offset: 25 bit_size: 1 enum: LSCOSEL @@ -1324,86 +1324,86 @@ fieldset/CCIPR1: description: CCIPR1 fields: - name: USART1SEL - description: " USART1 clock source selection " + description: USART1 clock source selection bit_offset: 0 bit_size: 2 - name: USART2SEL - description: " USART2 clock source selection " + description: USART2 clock source selection bit_offset: 2 bit_size: 2 - name: USART3SEL - description: " USART3 clock source selection " + description: USART3 clock source selection bit_offset: 4 bit_size: 2 - name: UART4SEL - description: " UART4 clock source selection " + description: UART4 clock source selection bit_offset: 6 bit_size: 2 - name: UART5SEL - description: " UART5 clock source selection " + description: UART5 clock source selection bit_offset: 8 bit_size: 2 - name: LPUART1SEL - description: " LPUART1 clock source selection " + description: LPUART1 clock source selection bit_offset: 10 bit_size: 2 - name: I2C1SEL - description: " I2C1 clock source selection " + description: I2C1 clock source selection bit_offset: 12 bit_size: 2 - name: I2C2SEL - description: " I2C2 clock source selection " + description: I2C2 clock source selection bit_offset: 14 bit_size: 2 - name: I2C3SEL - description: " I2C3 clock source selection " + description: I2C3 clock source selection bit_offset: 16 bit_size: 2 - name: LPTIM1SEL - description: " Low power timer 1 clock source selection " + description: Low power timer 1 clock source selection bit_offset: 18 bit_size: 2 - name: LPTIM2SEL - description: " Low power timer 2 clock source selection " + description: Low power timer 2 clock source selection bit_offset: 20 bit_size: 2 - name: LPTIM3SEL - description: " Low-power timer 3 clock source selection " + description: Low-power timer 3 clock source selection bit_offset: 22 bit_size: 2 - name: FDCANSEL - description: " FDCAN clock source selection " + description: FDCAN clock source selection bit_offset: 24 bit_size: 2 - name: CLK48MSEL - description: " 48 MHz clock source selection " + description: 48 MHz clock source selection bit_offset: 26 bit_size: 2 - name: ADCSEL - description: " ADCs clock source selection " + description: ADCs clock source selection bit_offset: 28 bit_size: 2 fieldset/CCIPR2: - description: " Peripherals independent clock configuration register " + description: Peripherals independent clock configuration register fields: - name: I2C4SEL - description: " I2C4 clock source selection " + description: I2C4 clock source selection bit_offset: 0 bit_size: 2 - name: DFSDMSEL - description: " Digital filter for sigma delta modulator kernel clock source selection " + description: Digital filter for sigma delta modulator kernel clock source selection bit_offset: 2 bit_size: 1 - name: ADFSDMSEL - description: " Digital filter for sigma delta modulator audio clock source selection " + description: Digital filter for sigma delta modulator audio clock source selection bit_offset: 3 bit_size: 2 - name: SAI1SEL - description: " SAI1 clock source selection " + description: SAI1 clock source selection bit_offset: 5 bit_size: 3 - name: SAI2SEL - description: " SAI2 clock source selection " + description: SAI2 clock source selection bit_offset: 8 bit_size: 3 - name: SDMMCSEL @@ -1411,7 +1411,7 @@ fieldset/CCIPR2: bit_offset: 14 bit_size: 1 - name: OSPISEL - description: " Octospi clock source selection " + description: Octospi clock source selection bit_offset: 20 bit_size: 2 fieldset/CFGR: @@ -1433,27 +1433,27 @@ fieldset/CFGR: bit_size: 4 enum: HPRE - name: PPRE1 - description: " PB low-speed prescaler (APB1) " + description: PB low-speed prescaler (APB1) bit_offset: 8 bit_size: 3 enum: PPRE - name: PPRE2 - description: " APB high-speed prescaler (APB2) " + description: APB high-speed prescaler (APB2) bit_offset: 11 bit_size: 3 enum: PPRE - name: STOPWUCK - description: " Wakeup from Stop and CSS backup clock selection " + description: Wakeup from Stop and CSS backup clock selection bit_offset: 15 bit_size: 1 enum: STOPWUCK - name: MCOSEL - description: " Microcontroller clock output " + description: Microcontroller clock output bit_offset: 24 bit_size: 4 enum: MCOSEL - name: MCOPRE - description: " Microcontroller clock output prescaler " + description: Microcontroller clock output prescaler bit_offset: 28 bit_size: 3 enum: MCOPRE @@ -1485,27 +1485,27 @@ fieldset/CICR: bit_offset: 5 bit_size: 1 - name: PLLSAI1RDYC - description: " PLLSAI1 ready interrupt clear " + description: PLLSAI1 ready interrupt clear bit_offset: 6 bit_size: 1 - name: PLLSAI2RDYC - description: " PLLSAI2 ready interrupt clear " + description: PLLSAI2 ready interrupt clear bit_offset: 7 bit_size: 1 - name: CSSC - description: " Clock security system interrupt clear " + description: Clock security system interrupt clear bit_offset: 8 bit_size: 1 - name: LSECSSC - description: " LSE Clock security system interrupt clear " + description: LSE Clock security system interrupt clear bit_offset: 9 bit_size: 1 - name: HSI48RDYC - description: " HSI48 oscillator ready interrupt clear " + description: HSI48 oscillator ready interrupt clear bit_offset: 10 bit_size: 1 fieldset/CIER: - description: " Clock interrupt enable register " + description: Clock interrupt enable register fields: - name: LSIRDYIE description: LSI ready interrupt enable @@ -1532,19 +1532,19 @@ fieldset/CIER: bit_offset: 5 bit_size: 1 - name: PLLSAI1RDYIE - description: " PLLSAI1 ready interrupt enable " + description: PLLSAI1 ready interrupt enable bit_offset: 6 bit_size: 1 - name: PLLSAI2RDYIE - description: " PLLSAI2 ready interrupt enable " + description: PLLSAI2 ready interrupt enable bit_offset: 7 bit_size: 1 - name: LSECSSIE - description: " LSE clock security system interrupt enable " + description: LSE clock security system interrupt enable bit_offset: 9 bit_size: 1 - name: HSI48RDYIE - description: " HSI48 ready interrupt enable " + description: HSI48 ready interrupt enable bit_offset: 10 bit_size: 1 fieldset/CIFR: @@ -1575,19 +1575,19 @@ fieldset/CIFR: bit_offset: 5 bit_size: 1 - name: PLLSAI1RDYF - description: " PLLSAI1 ready interrupt flag " + description: PLLSAI1 ready interrupt flag bit_offset: 6 bit_size: 1 - name: PLLSAI2RDYF - description: " PLLSAI2 ready interrupt flag " + description: PLLSAI2 ready interrupt flag bit_offset: 7 bit_size: 1 - name: CSSF - description: " Clock security system interrupt flag " + description: Clock security system interrupt flag bit_offset: 8 bit_size: 1 - name: LSECSSF - description: " LSE Clock security system interrupt flag " + description: LSE Clock security system interrupt flag bit_offset: 9 bit_size: 1 - name: HSI48RDYF @@ -1622,7 +1622,7 @@ fieldset/CR: bit_offset: 8 bit_size: 1 - name: HSIKERON - description: " HSI always enable for peripheral kernels " + description: HSI always enable for peripheral kernels bit_offset: 9 bit_size: 1 - name: HSIRDY @@ -1630,7 +1630,7 @@ fieldset/CR: bit_offset: 10 bit_size: 1 - name: HSIASFS - description: " HSI automatic start from Stop " + description: HSI automatic start from Stop bit_offset: 11 bit_size: 1 - name: HSEON @@ -1642,11 +1642,11 @@ fieldset/CR: bit_offset: 17 bit_size: 1 - name: HSEBYP - description: " HSE crystal oscillator bypass " + description: HSE crystal oscillator bypass bit_offset: 18 bit_size: 1 - name: CSSON - description: " Clock security system enable " + description: Clock security system enable bit_offset: 19 bit_size: 1 - name: PLLON @@ -1708,7 +1708,7 @@ fieldset/CSR: bit_offset: 4 bit_size: 1 - name: MSISRANGE - description: " SI range after Standby mode " + description: SI range after Standby mode bit_offset: 8 bit_size: 4 - name: RMVF @@ -1716,7 +1716,7 @@ fieldset/CSR: bit_offset: 23 bit_size: 1 - name: OBLRSTF - description: " Option byte loader reset flag " + description: Option byte loader reset flag bit_offset: 25 bit_size: 1 - name: PINRSTF @@ -1732,7 +1732,7 @@ fieldset/CSR: bit_offset: 28 bit_size: 1 - name: IWWDGRSTF - description: " Independent window watchdog reset flag " + description: Independent window watchdog reset flag bit_offset: 29 bit_size: 1 - name: WWDGRSTF @@ -1744,7 +1744,7 @@ fieldset/CSR: bit_offset: 31 bit_size: 1 fieldset/ICSCR: - description: " Internal clock sources calibration register " + description: Internal clock sources calibration register fields: - name: MSICAL description: MSI clock calibration @@ -1766,43 +1766,43 @@ fieldset/PLLCFGR: description: PLL configuration register fields: - name: PLLSRC - description: " Main PLL, PLLSAI1 and PLLSAI2 entry clock source " + description: "Main PLL, PLLSAI1 and PLLSAI2 entry clock source" bit_offset: 0 bit_size: 2 - name: PLLM - description: " Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock " + description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock bit_offset: 4 bit_size: 4 - name: PLLN - description: " Main PLL multiplication factor for VCO " + description: Main PLL multiplication factor for VCO bit_offset: 8 bit_size: 7 - name: PLLPEN - description: " Main PLL PLLSAI3CLK output enable " + description: Main PLL PLLSAI3CLK output enable bit_offset: 16 bit_size: 1 - name: PLLP - description: " Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) " + description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) bit_offset: 17 bit_size: 1 - name: PLLQEN - description: " Main PLL PLLUSB1CLK output enable " + description: Main PLL PLLUSB1CLK output enable bit_offset: 20 bit_size: 1 - name: PLLQ - description: " Main PLL division factor for PLLUSB1CLK(48 MHz clock) " + description: Main PLL division factor for PLLUSB1CLK(48 MHz clock) bit_offset: 21 bit_size: 2 - name: PLLREN - description: " Main PLL PLLCLK output enable " + description: Main PLL PLLCLK output enable bit_offset: 24 bit_size: 1 - name: PLLR - description: " Main PLL division factor for PLLCLK (system clock) " + description: Main PLL division factor for PLLCLK (system clock) bit_offset: 25 bit_size: 2 - name: PLLPDIV - description: " Main PLL division factor for PLLSAI2CLK " + description: Main PLL division factor for PLLSAI2CLK bit_offset: 27 bit_size: 5 fieldset/PLLSAI1CFGR: @@ -1813,39 +1813,39 @@ fieldset/PLLSAI1CFGR: bit_offset: 0 bit_size: 2 - name: PLLSAI1M - description: " Division factor for PLLSAI1 input clock " + description: Division factor for PLLSAI1 input clock bit_offset: 4 bit_size: 4 - name: PLLSAI1N - description: " SAI1PLL multiplication factor for VCO " + description: SAI1PLL multiplication factor for VCO bit_offset: 8 bit_size: 7 - name: PLLSAI1PEN - description: " SAI1PLL PLLSAI1CLK output enable " + description: SAI1PLL PLLSAI1CLK output enable bit_offset: 16 bit_size: 1 - name: PLLSAI1P - description: " SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) " + description: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) bit_offset: 17 bit_size: 1 - name: PLLSAI1QEN - description: " SAI1PLL PLLUSB2CLK output enable " + description: SAI1PLL PLLUSB2CLK output enable bit_offset: 20 bit_size: 1 - name: PLLSAI1Q - description: " SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) " + description: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) bit_offset: 21 bit_size: 2 - name: PLLSAI1REN - description: " PLLSAI1 PLLADC1CLK output enable " + description: PLLSAI1 PLLADC1CLK output enable bit_offset: 24 bit_size: 1 - name: PLLSAI1R - description: " PLLSAI1 division factor for PLLADC1CLK (ADC clock) " + description: PLLSAI1 division factor for PLLADC1CLK (ADC clock) bit_offset: 25 bit_size: 2 - name: PLLSAI1PDIV - description: " PLLSAI1 division factor for PLLSAI1CLK " + description: PLLSAI1 division factor for PLLSAI1CLK bit_offset: 27 bit_size: 5 fieldset/PLLSAI2CFGR: @@ -1856,27 +1856,27 @@ fieldset/PLLSAI2CFGR: bit_offset: 0 bit_size: 2 - name: PLLSAI2M - description: " Division factor for PLLSAI2 input clock " + description: Division factor for PLLSAI2 input clock bit_offset: 4 bit_size: 4 - name: PLLSAI2N - description: " SAI2PLL multiplication factor for VCO " + description: SAI2PLL multiplication factor for VCO bit_offset: 8 bit_size: 7 - name: PLLSAI2PEN - description: " SAI2PLL PLLSAI2CLK output enable " + description: SAI2PLL PLLSAI2CLK output enable bit_offset: 16 bit_size: 1 - name: PLLSAI2P - description: " SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock) " + description: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock) bit_offset: 17 bit_size: 1 - name: PLLSAI2PDIV - description: " PLLSAI2 division factor for PLLSAI2CLK " + description: PLLSAI2 division factor for PLLSAI2CLK bit_offset: 27 bit_size: 5 fieldset/SECCFGR: - description: " RCC secure configuration register " + description: RCC secure configuration register fields: - name: HSISEC description: HSISEC diff --git a/data/registers/rcc_u5.yaml b/data/registers/rcc_u5.yaml index f6a8b21..5426603 100644 --- a/data/registers/rcc_u5.yaml +++ b/data/registers/rcc_u5.yaml @@ -3,215 +3,215 @@ block/RCC: description: Reset and clock control items: - name: CR - description: "RCC clock control register " + description: RCC clock control register byte_offset: 0 fieldset: CR - name: ICSCR1 - description: "RCC internal clock sources calibration register 1 " + description: RCC internal clock sources calibration register 1 byte_offset: 8 fieldset: ICSCR1 - name: ICSCR2 - description: "RCC internal clock sources calibration register 2 " + description: RCC internal clock sources calibration register 2 byte_offset: 12 fieldset: ICSCR2 - name: ICSCR3 - description: "RCC internal clock sources calibration register 3 " + description: RCC internal clock sources calibration register 3 byte_offset: 16 fieldset: ICSCR3 - name: CRRCR - description: "RCC clock recovery RC register " + description: RCC clock recovery RC register byte_offset: 20 fieldset: CRRCR - name: CFGR1 - description: "RCC clock configuration register 1 " + description: RCC clock configuration register 1 byte_offset: 28 fieldset: CFGR1 - name: CFGR2 - description: "RCC clock configuration register 2 " + description: RCC clock configuration register 2 byte_offset: 32 fieldset: CFGR2 - name: CFGR3 - description: "RCC clock configuration register 3 " + description: RCC clock configuration register 3 byte_offset: 36 fieldset: CFGR3 - name: PLL1CFGR - description: "RCC PLL1 configuration register " + description: RCC PLL1 configuration register byte_offset: 40 fieldset: PLL1CFGR - name: PLL2CFGR - description: "RCC PLL2 configuration register " + description: RCC PLL2 configuration register byte_offset: 44 fieldset: PLL2CFGR - name: PLL3CFGR - description: "RCC PLL3 configuration register " + description: RCC PLL3 configuration register byte_offset: 48 fieldset: PLL3CFGR - name: PLL1DIVR - description: "RCC PLL1 dividers register " + description: RCC PLL1 dividers register byte_offset: 52 fieldset: PLL1DIVR - name: PLL1FRACR - description: "RCC PLL1 fractional divider register " + description: RCC PLL1 fractional divider register byte_offset: 56 fieldset: PLL1FRACR - name: PLL2DIVR - description: "RCC PLL2 dividers configuration register " + description: RCC PLL2 dividers configuration register byte_offset: 60 fieldset: PLL2DIVR - name: PLL2FRACR - description: "RCC PLL2 fractional divider register " + description: RCC PLL2 fractional divider register byte_offset: 64 fieldset: PLL2FRACR - name: PLL3DIVR - description: "RCC PLL3 dividers configuration register " + description: RCC PLL3 dividers configuration register byte_offset: 68 fieldset: PLL3DIVR - name: PLL3FRACR - description: "RCC PLL3 fractional divider register " + description: RCC PLL3 fractional divider register byte_offset: 72 fieldset: PLL3FRACR - name: CIER - description: "RCC clock interrupt enable register " + description: RCC clock interrupt enable register byte_offset: 80 fieldset: CIER - name: CIFR - description: "RCC clock interrupt flag register " + description: RCC clock interrupt flag register byte_offset: 84 fieldset: CIFR - name: CICR - description: "RCC clock interrupt clear register " + description: RCC clock interrupt clear register byte_offset: 88 fieldset: CICR - name: AHB1RSTR - description: "RCC AHB1 peripheral reset register " + description: RCC AHB1 peripheral reset register byte_offset: 96 fieldset: AHB1RSTR - name: AHB2RSTR1 - description: "RCC AHB2 peripheral reset register 1 " + description: RCC AHB2 peripheral reset register 1 byte_offset: 100 fieldset: AHB2RSTR1 - name: AHB2RSTR2 - description: "RCC AHB2 peripheral reset register 2 " + description: RCC AHB2 peripheral reset register 2 byte_offset: 104 fieldset: AHB2RSTR2 - name: AHB3RSTR - description: "RCC AHB3 peripheral reset register " + description: RCC AHB3 peripheral reset register byte_offset: 108 fieldset: AHB3RSTR - name: APB1RSTR1 - description: "RCC APB1 peripheral reset register 1 " + description: RCC APB1 peripheral reset register 1 byte_offset: 116 fieldset: APB1RSTR1 - name: APB1RSTR2 - description: "RCC APB1 peripheral reset register 2 " + description: RCC APB1 peripheral reset register 2 byte_offset: 120 fieldset: APB1RSTR2 - name: APB2RSTR - description: "RCC APB2 peripheral reset register " + description: RCC APB2 peripheral reset register byte_offset: 124 fieldset: APB2RSTR - name: APB3RSTR - description: "RCC APB3 peripheral reset register " + description: RCC APB3 peripheral reset register byte_offset: 128 fieldset: APB3RSTR - name: AHB1ENR - description: "RCC AHB1 peripheral clock enable register " + description: RCC AHB1 peripheral clock enable register byte_offset: 136 fieldset: AHB1ENR - name: AHB2ENR1 - description: "RCC AHB2 peripheral clock enable register 1 " + description: RCC AHB2 peripheral clock enable register 1 byte_offset: 140 fieldset: AHB2ENR1 - name: AHB2ENR2 - description: "RCC AHB2 peripheral clock enable register 2 " + description: RCC AHB2 peripheral clock enable register 2 byte_offset: 144 fieldset: AHB2ENR2 - name: AHB3ENR - description: "RCC AHB3 peripheral clock enable register " + description: RCC AHB3 peripheral clock enable register byte_offset: 148 fieldset: AHB3ENR - name: APB1ENR1 - description: "RCC APB1 peripheral clock enable register 1 " + description: RCC APB1 peripheral clock enable register 1 byte_offset: 156 fieldset: APB1ENR1 - name: APB1ENR2 - description: "RCC APB1 peripheral clock enable register 2 " + description: RCC APB1 peripheral clock enable register 2 byte_offset: 160 fieldset: APB1ENR2 - name: APB2ENR - description: "RCC APB2 peripheral clock enable register " + description: RCC APB2 peripheral clock enable register byte_offset: 164 fieldset: APB2ENR - name: APB3ENR - description: "RCC APB3 peripheral clock enable register " + description: RCC APB3 peripheral clock enable register byte_offset: 168 fieldset: APB3ENR - name: AHB1SMENR - description: "RCC AHB1 peripheral clocks enable in Sleep and Stop modes register\t" + description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register byte_offset: 176 fieldset: AHB1SMENR - name: AHB2SMENR1 - description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1 " + description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1" byte_offset: 180 fieldset: AHB2SMENR1 - name: AHB2SMENR2 - description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2 " + description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2" byte_offset: 184 fieldset: AHB2SMENR2 - name: AHB3SMENR - description: "RCC AHB3 peripheral clocks enable in Sleep and Stop modes register\t" + description: RCC AHB3 peripheral clocks enable in Sleep and Stop modes register byte_offset: 188 fieldset: AHB3SMENR - name: APB1SMENR1 - description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1 " + description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1" byte_offset: 196 fieldset: APB1SMENR1 - name: APB1SMENR2 - description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2 " + description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2" byte_offset: 200 fieldset: APB1SMENR2 - name: APB2SMENR - description: "RCC APB2 peripheral clocks enable in Sleep and Stop modes register\t" + description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register byte_offset: 204 fieldset: APB2SMENR - name: APB3SMENR - description: "RCC APB3 peripheral clock enable in Sleep and Stop modes register\t" + description: RCC APB3 peripheral clock enable in Sleep and Stop modes register byte_offset: 208 fieldset: APB3SMENR - name: SRDAMR - description: "RCC SmartRun domain peripheral autonomous mode register\t" + description: RCC SmartRun domain peripheral autonomous mode register byte_offset: 216 fieldset: SRDAMR - name: CCIPR1 - description: "RCC peripherals independent clock configuration register 1\t" + description: RCC peripherals independent clock configuration register 1 byte_offset: 224 fieldset: CCIPR1 - name: CCIPR2 - description: "RCC peripherals independent clock configuration register 2\t" + description: RCC peripherals independent clock configuration register 2 byte_offset: 228 fieldset: CCIPR2 - name: CCIPR3 - description: "RCC peripherals independent clock configuration register 3\t" + description: RCC peripherals independent clock configuration register 3 byte_offset: 232 fieldset: CCIPR3 - name: BDCR - description: "RCC Backup domain control register " + description: RCC Backup domain control register byte_offset: 240 fieldset: BDCR - name: CSR - description: "RCC control/status register " + description: RCC control/status register byte_offset: 244 fieldset: CSR - name: SECCFGR - description: "RCC secure configuration register " + description: RCC secure configuration register byte_offset: 272 fieldset: SECCFGR - name: PRIVCFGR - description: "RCC privilege configuration register " + description: RCC privilege configuration register byte_offset: 276 fieldset: PRIVCFGR fieldset/AHB1ENR: - description: "RCC AHB1 peripheral clock enable register " + description: RCC AHB1 peripheral clock enable register fields: - name: GPDMA1EN description: "GPDMA1 clock enable\r Set and cleared by software." @@ -266,7 +266,7 @@ fieldset/AHB1ENR: bit_offset: 31 bit_size: 1 fieldset/AHB1RSTR: - description: "RCC AHB1 peripheral reset register " + description: RCC AHB1 peripheral reset register fields: - name: GPDMA1RST description: "GPDMA1 reset\r Set and cleared by software." @@ -301,7 +301,7 @@ fieldset/AHB1RSTR: bit_offset: 18 bit_size: 1 fieldset/AHB1SMENR: - description: "RCC AHB1 peripheral clocks enable in Sleep and Stop modes register\t" + description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register fields: - name: GPDMA1SMEN description: "GPDMA1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." @@ -360,7 +360,7 @@ fieldset/AHB1SMENR: bit_offset: 31 bit_size: 1 fieldset/AHB2ENR1: - description: "RCC AHB2 peripheral clock enable register 1 " + description: RCC AHB2 peripheral clock enable register 1 fields: - name: GPIOAEN description: "IO port A clock enable\r Set and cleared by software." @@ -459,7 +459,7 @@ fieldset/AHB2ENR1: bit_offset: 31 bit_size: 1 fieldset/AHB2ENR2: - description: "RCC AHB2 peripheral clock enable register 2 " + description: RCC AHB2 peripheral clock enable register 2 fields: - name: FSMCEN description: "FSMC clock enable\r Set and cleared by software." @@ -474,7 +474,7 @@ fieldset/AHB2ENR2: bit_offset: 8 bit_size: 1 fieldset/AHB2RSTR1: - description: "RCC AHB2 peripheral reset register 1 " + description: RCC AHB2 peripheral reset register 1 fields: - name: GPIOARST description: "IO port A reset\r Set and cleared by software." @@ -565,7 +565,7 @@ fieldset/AHB2RSTR1: bit_offset: 28 bit_size: 1 fieldset/AHB2RSTR2: - description: "RCC AHB2 peripheral reset register 2 " + description: RCC AHB2 peripheral reset register 2 fields: - name: FSMCRST description: "Flexible memory controller reset\r Set and cleared by software." @@ -580,7 +580,7 @@ fieldset/AHB2RSTR2: bit_offset: 8 bit_size: 1 fieldset/AHB2SMENR1: - description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1 " + description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1" fields: - name: GPIOASMEN description: "IO port A clocks enable during Sleep and Stop modes\r Set and cleared by software." @@ -679,7 +679,7 @@ fieldset/AHB2SMENR1: bit_offset: 31 bit_size: 1 fieldset/AHB2SMENR2: - description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2 " + description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2" fields: - name: FSMCSMEN description: "FSMC clocks enable during Sleep and Stop modes\r Set and cleared by software." @@ -694,7 +694,7 @@ fieldset/AHB2SMENR2: bit_offset: 8 bit_size: 1 fieldset/AHB3ENR: - description: "RCC AHB3 peripheral clock enable register " + description: RCC AHB3 peripheral clock enable register fields: - name: LPGPIO1EN description: "LPGPIO1 enable\r Set and cleared by software." @@ -729,7 +729,7 @@ fieldset/AHB3ENR: bit_offset: 31 bit_size: 1 fieldset/AHB3RSTR: - description: "RCC AHB3 peripheral reset register " + description: RCC AHB3 peripheral reset register fields: - name: LPGPIO1RST description: "LPGPIO1 reset\r Set and cleared by software." @@ -752,7 +752,7 @@ fieldset/AHB3RSTR: bit_offset: 10 bit_size: 1 fieldset/AHB3SMENR: - description: "RCC AHB3 peripheral clocks enable in Sleep and Stop modes register\t" + description: RCC AHB3 peripheral clocks enable in Sleep and Stop modes register fields: - name: LPGPIO1SMEN description: "LPGPIO1 enable during Sleep and Stop modes\r Set and cleared by software." @@ -787,7 +787,7 @@ fieldset/AHB3SMENR: bit_offset: 31 bit_size: 1 fieldset/APB1ENR1: - description: "RCC APB1 peripheral clock enable register 1 " + description: RCC APB1 peripheral clock enable register 1 fields: - name: TIM2EN description: "TIM2 clock enable\r Set and cleared by software." @@ -850,7 +850,7 @@ fieldset/APB1ENR1: bit_offset: 24 bit_size: 1 fieldset/APB1ENR2: - description: "RCC APB1 peripheral clock enable register 2 " + description: RCC APB1 peripheral clock enable register 2 fields: - name: I2C4EN description: "I2C4 clock enable\r Set and cleared by software" @@ -869,7 +869,7 @@ fieldset/APB1ENR2: bit_offset: 23 bit_size: 1 fieldset/APB1RSTR1: - description: "RCC APB1 peripheral reset register 1 " + description: RCC APB1 peripheral reset register 1 fields: - name: TIM2RST description: "TIM2 reset\r Set and cleared by software." @@ -928,7 +928,7 @@ fieldset/APB1RSTR1: bit_offset: 24 bit_size: 1 fieldset/APB1RSTR2: - description: "RCC APB1 peripheral reset register 2 " + description: RCC APB1 peripheral reset register 2 fields: - name: I2C4RST description: "I2C4 reset\r Set and cleared by software" @@ -947,7 +947,7 @@ fieldset/APB1RSTR2: bit_offset: 23 bit_size: 1 fieldset/APB1SMENR1: - description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1 " + description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1" fields: - name: TIM2SMEN description: "TIM2 clocks enable during Sleep and Stop modes\r Set and cleared by software." @@ -1010,7 +1010,7 @@ fieldset/APB1SMENR1: bit_offset: 24 bit_size: 1 fieldset/APB1SMENR2: - description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2 " + description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2" fields: - name: I2C4SMEN description: "I2C4 clocks enable during Sleep and Stop modes\r Set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." @@ -1029,7 +1029,7 @@ fieldset/APB1SMENR2: bit_offset: 23 bit_size: 1 fieldset/APB2ENR: - description: "RCC APB2 peripheral clock enable register " + description: RCC APB2 peripheral clock enable register fields: - name: TIM1EN description: "TIM1 clock enable\r Set and cleared by software." @@ -1068,7 +1068,7 @@ fieldset/APB2ENR: bit_offset: 22 bit_size: 1 fieldset/APB2RSTR: - description: "RCC APB2 peripheral reset register " + description: RCC APB2 peripheral reset register fields: - name: TIM1RST description: "TIM1 reset\r Set and cleared by software." @@ -1107,7 +1107,7 @@ fieldset/APB2RSTR: bit_offset: 22 bit_size: 1 fieldset/APB2SMENR: - description: "RCC APB2 peripheral clocks enable in Sleep and Stop modes register\t" + description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register fields: - name: TIM1SMEN description: "TIM1 clocks enable during Sleep and Stop modes\r Set and cleared by software." @@ -1146,7 +1146,7 @@ fieldset/APB2SMENR: bit_offset: 22 bit_size: 1 fieldset/APB3ENR: - description: "RCC APB3 peripheral clock enable register " + description: RCC APB3 peripheral clock enable register fields: - name: SYSCFGEN description: "SYSCFG clock enable\r Set and cleared by software." @@ -1193,7 +1193,7 @@ fieldset/APB3ENR: bit_offset: 21 bit_size: 1 fieldset/APB3RSTR: - description: "RCC APB3 peripheral reset register " + description: RCC APB3 peripheral reset register fields: - name: SYSCFGRST description: "SYSCFG reset\r Set and cleared by software." @@ -1236,7 +1236,7 @@ fieldset/APB3RSTR: bit_offset: 20 bit_size: 1 fieldset/APB3SMENR: - description: "RCC APB3 peripheral clock enable in Sleep and Stop modes register\t" + description: RCC APB3 peripheral clock enable in Sleep and Stop modes register fields: - name: SYSCFGSMEN description: "SYSCFG clocks enable during Sleep and Stop modes\r Set and cleared by software." @@ -1283,7 +1283,7 @@ fieldset/APB3SMENR: bit_offset: 21 bit_size: 1 fieldset/BDCR: - description: "RCC Backup domain control register " + description: RCC Backup domain control register fields: - name: LSEON description: "LSE oscillator enable\r Set and cleared by software." @@ -1358,7 +1358,7 @@ fieldset/BDCR: bit_size: 1 enum: LSIPREDIV fieldset/CCIPR1: - description: "RCC peripherals independent clock configuration register 1\t" + description: RCC peripherals independent clock configuration register 1 fields: - name: USART1SEL description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." @@ -1436,7 +1436,7 @@ fieldset/CCIPR1: bit_size: 3 enum: TIMICSEL fieldset/CCIPR2: - description: "RCC peripherals independent clock configuration register 2\t" + description: RCC peripherals independent clock configuration register 2 fields: - name: MDF1SEL description: "MDF1 kernel clock source selection\r These bits are used to select the MDF1 kernel clock source.\r others: reserved" @@ -1474,7 +1474,7 @@ fieldset/CCIPR2: bit_size: 2 enum: OCTOSPISEL fieldset/CCIPR3: - description: "RCC peripherals independent clock configuration register 3\t" + description: RCC peripherals independent clock configuration register 3 fields: - name: LPUART1SEL description: "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r others: reserved\r Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16, LSE or MSIK." @@ -1517,7 +1517,7 @@ fieldset/CCIPR3: bit_size: 3 enum: ADFSEL fieldset/CFGR1: - description: "RCC clock configuration register 1 " + description: RCC clock configuration register 1 fields: - name: SW description: "system clock switch\r Set and cleared by software to select system clock source (SYSCLK).\r Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI16 oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value." @@ -1550,7 +1550,7 @@ fieldset/CFGR1: bit_size: 3 enum: MCOPRE fieldset/CFGR2: - description: "RCC clock configuration register 2 " + description: RCC clock configuration register 2 fields: - name: HPRE description: "AHB prescaler\r Set and cleared by software to control the division factor of the AHB clock (HCLK).\r Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account.\r 0xxx: SYSCLK not divided" @@ -1588,7 +1588,7 @@ fieldset/CFGR2: bit_offset: 20 bit_size: 1 fieldset/CFGR3: - description: "RCC clock configuration register 3 " + description: RCC clock configuration register 3 fields: - name: PPRE3 description: "APB3 prescaler\r Set and cleared by software to control the division factor of the APB3 clock (PCLK3).\r 0xx: HCLK not divided" @@ -1604,7 +1604,7 @@ fieldset/CFGR3: bit_offset: 17 bit_size: 1 fieldset/CICR: - description: "RCC clock interrupt clear register " + description: RCC clock interrupt clear register fields: - name: LSIRDYC description: "LSI ready interrupt clear\r Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect." @@ -1650,7 +1650,7 @@ fieldset/CICR: bit_offset: 12 bit_size: 1 fieldset/CIER: - description: "RCC clock interrupt enable register " + description: RCC clock interrupt enable register fields: - name: LSIRDYIE description: "LSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization." @@ -1692,7 +1692,7 @@ fieldset/CIER: bit_offset: 12 bit_size: 1 fieldset/CIFR: - description: "RCC clock interrupt flag register " + description: RCC clock interrupt flag register fields: - name: LSIRDYF description: "LSI ready interrupt flag\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.\r Cleared by software setting the LSIRDYC bit." @@ -1738,7 +1738,7 @@ fieldset/CIFR: bit_offset: 12 bit_size: 1 fieldset/CR: - description: "RCC clock control register " + description: RCC clock control register fields: - name: MSISON description: "MSIS clock enable\r Set and cleared by software.\r Cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when exiting Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator.\r Set by hardware when used directly or indirectly as system clock." @@ -1838,14 +1838,14 @@ fieldset/CR: len: 3 stride: 2 fieldset/CRRCR: - description: "RCC clock recovery RC register " + description: RCC clock recovery RC register fields: - name: HSI48CAL description: "HSI48 clock calibration\r These bits are initialized at startup with the factory-programmed HSI48 calibration trim value." bit_offset: 0 bit_size: 9 fieldset/CSR: - description: "RCC control/status register " + description: RCC control/status register fields: - name: MSIKSRANGE description: "MSIK range after Standby mode\r Set by software to chose the MSIK frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSIKSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSIKSRANGE does not change the current MSIK frequency." @@ -1890,7 +1890,7 @@ fieldset/CSR: bit_offset: 31 bit_size: 1 fieldset/ICSCR1: - description: "RCC internal clock sources calibration register 1 " + description: RCC internal clock sources calibration register 1 fields: - name: MSICAL3 description: "MSIRC3 clock calibration for MSI ranges 12 to 15\r These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level." @@ -1929,7 +1929,7 @@ fieldset/ICSCR1: bit_size: 4 enum: MSIRANGE fieldset/ICSCR2: - description: "RCC internal clock sources calibration register 2 " + description: RCC internal clock sources calibration register 2 fields: - name: MSITRIM3 description: "MSI clock trimming for ranges 12 to 15\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." @@ -1948,7 +1948,7 @@ fieldset/ICSCR2: bit_offset: 15 bit_size: 5 fieldset/ICSCR3: - description: "RCC internal clock sources calibration register 3 " + description: RCC internal clock sources calibration register 3 fields: - name: HSICAL description: "HSI clock calibration\r These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value." @@ -1959,7 +1959,7 @@ fieldset/ICSCR3: bit_offset: 16 bit_size: 5 fieldset/PLL1CFGR: - description: "RCC PLL1 configuration register " + description: RCC PLL1 configuration register fields: - name: PLLSRC description: "PLL1 entry clock source\r Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled.\r In order to save power, when no PLL1 is used, the value of PLL1SRC must be 0." @@ -1998,7 +1998,7 @@ fieldset/PLL1CFGR: bit_offset: 18 bit_size: 1 fieldset/PLL1DIVR: - description: "RCC PLL1 dividers register " + description: RCC PLL1 dividers register fields: - name: PLLN description: "Multiplication factor for PLL1 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with:\r PLL1N between 4 and 512\r input frequency Fref1_ck between 4 and 16 MHz" @@ -2017,14 +2017,14 @@ fieldset/PLL1DIVR: bit_offset: 24 bit_size: 7 fieldset/PLL1FRACR: - description: "RCC PLL1 fractional divider register " + description: RCC PLL1 fractional divider register fields: - name: PLLFRACN description: "Fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with:\r PLL1N must be between 4 and 512.\r PLL1FRACN can be between 0 and 213- 1.\r The input frequency Fref1_ck must be between 4 and 16 MHz.\r To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL1FRACEN to 0.\r Write the new fractional value into PLL1FRACN.\r Set the bit PLL1FRACEN to 1." bit_offset: 3 bit_size: 13 fieldset/PLL2CFGR: - description: "RCC PLL2 configuration register " + description: RCC PLL2 configuration register fields: - name: PLLSRC description: "PLL2 entry clock source\r Set and cleared by software to select PLL2 clock source. These bits can be written only when the PLL2 is disabled.\r In order to save power, when no PLL2 is used, the value of PLL2SRC must be 0." @@ -2058,7 +2058,7 @@ fieldset/PLL2CFGR: bit_offset: 18 bit_size: 1 fieldset/PLL2DIVR: - description: "RCC PLL2 dividers configuration register " + description: RCC PLL2 dividers configuration register fields: - name: PLLN description: "Multiplication factor for PLL2 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref2_ck x PLL2N, when fractional value 0 has been loaded into PLL2FRACN, with:\r PLL2N between 4 and 512\r input frequency Fref2_ck between 1MHz and 16MHz" @@ -2077,14 +2077,14 @@ fieldset/PLL2DIVR: bit_offset: 24 bit_size: 7 fieldset/PLL2FRACR: - description: "RCC PLL2 fractional divider register " + description: RCC PLL2 fractional divider register fields: - name: PLLFRACN description: "Fractional part of the multiplication factor for PLL2 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO.\r VCO output frequency = Fref2_ck x (PLL2N + (PLL2FRACN / 213)), with\r PLL2N must be between 4 and 512.\r PLL2FRACN can be between 0 and 213 - 1.\r The input frequency Fref2_ck must be between 4 and 16 MHz.\r In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL2FRACEN to 0.\r Write the new fractional value into PLL2FRACN.\r Set the bit PLL2FRACEN to 1." bit_offset: 3 bit_size: 13 fieldset/PLL3CFGR: - description: "RCC PLL3 configuration register " + description: RCC PLL3 configuration register fields: - name: PLLSRC description: "PLL3 entry clock source\r Set and cleared by software to select PLL3 clock source. These bits can be written only when the PLL3 is disabled.\r In order to save power, when no PLL3 is used, the value of PLL3SRC must be 00." @@ -2121,7 +2121,7 @@ fieldset/PLL3CFGR: bit_offset: 18 bit_size: 1 fieldset/PLL3DIVR: - description: "RCC PLL3 dividers configuration register " + description: RCC PLL3 dividers configuration register fields: - name: PLLN description: "Multiplication factor for PLL3 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref3_ck x PLL3N, when fractional value 0 has been loaded into PLL3FRACN, with:\r PLL3N between 4 and 512\r input frequency Fref3_ck between 4 and 16MHz" @@ -2140,14 +2140,14 @@ fieldset/PLL3DIVR: bit_offset: 24 bit_size: 7 fieldset/PLL3FRACR: - description: "RCC PLL3 fractional divider register " + description: RCC PLL3 fractional divider register fields: - name: PLLFRACN description: "Fractional part of the multiplication factor for PLL3 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO.\r VCO output frequency = Fref3_ck x (PLL3N + (PLL3FRACN / 213)), with:\r PLL3N must be between 4 and 512.\r PLL3FRACN can be between 0 and 213 - 1.\r The input frequency Fref3_ck must be between 4 and 16 MHz.\r In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL3FRACEN to 0.\r Write the new fractional value into PLL3FRACN.\r Set the bit PLL3FRACEN to 1." bit_offset: 3 bit_size: 13 fieldset/PRIVCFGR: - description: "RCC privilege configuration register " + description: RCC privilege configuration register fields: - name: SPRIV description: "RCC secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access." @@ -2160,7 +2160,7 @@ fieldset/PRIVCFGR: bit_size: 1 enum: PRIV fieldset/SECCFGR: - description: "RCC secure configuration register " + description: RCC secure configuration register fields: - name: HSISEC description: "HSI clock configuration and status bits security\r Set and reset by software." @@ -2221,7 +2221,7 @@ fieldset/SECCFGR: bit_size: 1 enum: SECURITY fieldset/SRDAMR: - description: "RCC SmartRun domain peripheral autonomous mode register\t" + description: RCC SmartRun domain peripheral autonomous mode register fields: - name: SPI3AMEN description: "SPI3 autonomous mode enable in Stop 0,1, 2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." @@ -2339,7 +2339,7 @@ enum/FDCANSEL: bit_size: 2 variants: - name: HSE - description: "HSE clock selected " + description: HSE clock selected value: 0 - name: PLL1_Q description: PLL1 Q (pll1_q_ck) selected @@ -2471,7 +2471,7 @@ enum/LSEDRV: description: "'Xtal mode medium-high driving capability" value: 2 - name: HIGH - description: "'Xtal mode higher driving capability " + description: "'Xtal mode higher driving capability" value: 3 enum/LSIPREDIV: bit_size: 1 @@ -2573,7 +2573,7 @@ enum/MSIPLLSEL: bit_size: 1 variants: - name: MSIK - description: "PLL mode applied to MSIK (MSI kernel) clock output " + description: PLL mode applied to MSIK (MSI kernel) clock output value: 0 - name: MSIS description: PLL mode applied to MSIS (MSI system) clock output @@ -2582,52 +2582,52 @@ enum/MSIRANGE: bit_size: 4 variants: - name: RANGE_48MHZ - description: "range 0 around 48 MHz " + description: range 0 around 48 MHz value: 0 - name: RANGE_24MHZ - description: "range 1 around 24 MHz " + description: range 1 around 24 MHz value: 1 - name: RANGE_16MHZ - description: "range 2 around 16 MHz " + description: range 2 around 16 MHz value: 2 - name: RANGE_12MHZ - description: "range 3 around 12 MHz " + description: range 3 around 12 MHz value: 3 - name: RANGE_4MHZ - description: "range 4 around 4 MHz (reset value) " + description: range 4 around 4 MHz (reset value) value: 4 - name: RANGE_2MHZ - description: "range 5 around 2 MHz " + description: range 5 around 2 MHz value: 5 - name: RANGE_1_33MHZ - description: "range 6 around 1.33 MHz " + description: range 6 around 1.33 MHz value: 6 - name: RANGE_1MHZ - description: "range 7 around 1 MHz " + description: range 7 around 1 MHz value: 7 - name: RANGE_3_072MHZ - description: "range 8 around 3.072 MHz " + description: range 8 around 3.072 MHz value: 8 - name: RANGE_1_536MHZ - description: "range 9 around 1.536 MHz " + description: range 9 around 1.536 MHz value: 9 - name: RANGE_1_024MHZ - description: "range 10 around 1.024 MHz " + description: range 10 around 1.024 MHz value: 10 - name: RANGE_768KHZ - description: "range 11 around 768 kHz " + description: range 11 around 768 kHz value: 11 - name: RANGE_400KHZ - description: "range 12 around 400 kHz " + description: range 12 around 400 kHz value: 12 - name: RANGE_200KHZ - description: "range 13 around 200 kHz " + description: range 13 around 200 kHz value: 13 - name: RANGE_133KHZ description: range 14 around 133 kHz value: 14 - name: RANGE_100KHZ - description: "range 15 around 100 kHz " + description: range 15 around 100 kHz value: 15 enum/MSIRGSEL: bit_size: 1 @@ -2642,19 +2642,19 @@ enum/MSIXSRANGE: bit_size: 4 variants: - name: RANGE_4MHZ - description: "range 4 around 4M Hz (reset value) " + description: range 4 around 4M Hz (reset value) value: 4 - name: RANGE_2MHZ - description: "range 5 around 2 MHz " + description: range 5 around 2 MHz value: 5 - name: RANGE_1_5MHZ - description: "range 6 around 1.5 MHz " + description: range 6 around 1.5 MHz value: 6 - name: RANGE_1MHZ - description: "range 7 around 1 MHz " + description: range 7 around 1 MHz value: 7 - name: RANGE_3_072MHZ - description: "range 8 around 3.072 MHz " + description: range 8 around 3.072 MHz value: 8 enum/OCTOSPISEL: bit_size: 2 @@ -2771,7 +2771,7 @@ enum/RNGSEL: bit_size: 2 variants: - name: HSI48 - description: "HSI48 selected " + description: HSI48 selected value: 0 - name: HSI48_DIV2 description: "HSI48 / 2 selected, can be used in Range 4" @@ -2828,7 +2828,7 @@ enum/SDMMCSEL: description: ICLK clock selected value: 0 - name: PLL1_P - description: "PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) " + description: "PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode)" value: 1 enum/SECURITY: bit_size: 1 diff --git a/data/registers/sdmmc_v1.yaml b/data/registers/sdmmc_v1.yaml index 03b59fa..8841d50 100644 --- a/data/registers/sdmmc_v1.yaml +++ b/data/registers/sdmmc_v1.yaml @@ -195,13 +195,6 @@ fieldset/DTIMER: description: Data timeout period bit_offset: 0 bit_size: 32 -fieldset/FIFOR: - description: data FIFO register - fields: - - name: FIFOData - description: Receive and transmit FIFO data - bit_offset: 0 - bit_size: 32 fieldset/FIFOCNT: description: FIFO counter register fields: @@ -209,6 +202,13 @@ fieldset/FIFOCNT: description: Remaining number of words to be written to or read from the FIFO bit_offset: 0 bit_size: 24 +fieldset/FIFOR: + description: data FIFO register + fields: + - name: FIFOData + description: Receive and transmit FIFO data + bit_offset: 0 + bit_size: 32 fieldset/ICR: description: interrupt clear register fields: diff --git a/data/registers/syscfg_f2.yaml b/data/registers/syscfg_f2.yaml index 32fabc8..31160f9 100644 --- a/data/registers/syscfg_f2.yaml +++ b/data/registers/syscfg_f2.yaml @@ -22,6 +22,27 @@ block/SYSCFG: byte_offset: 32 access: Read fieldset: CMPCR +fieldset/CMPCR: + description: Compensation cell control register + fields: + - name: CMP_PD + description: Compensation cell power-down + bit_offset: 0 + bit_size: 1 + - name: READY + description: Compensation cell ready flag + bit_offset: 8 + bit_size: 1 +fieldset/EXTICR: + description: external interrupt configuration register 1 + fields: + - name: EXTI + description: EXTI x configuration (x = 0 to 3) + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 fieldset/MEMRMP: description: memory remap register fields: @@ -37,27 +58,6 @@ fieldset/PMC: description: Ethernet PHY interface selection bit_offset: 23 bit_size: 1 -fieldset/EXTICR: - description: external interrupt configuration register 1 - fields: - - name: EXTI - description: EXTI x configuration (x = 0 to 3) - bit_offset: 0 - bit_size: 4 - array: - len: 4 - stride: 4 -fieldset/CMPCR: - description: Compensation cell control register - fields: - - name: CMP_PD - description: Compensation cell power-down - bit_offset: 0 - bit_size: 1 - - name: READY - description: Compensation cell ready flag - bit_offset: 8 - bit_size: 1 enum/MEM_MODE: bit_size: 2 variants: diff --git a/data/registers/syscfg_h7.yaml b/data/registers/syscfg_h7.yaml index b88c7ec..2afe710 100644 --- a/data/registers/syscfg_h7.yaml +++ b/data/registers/syscfg_h7.yaml @@ -242,7 +242,7 @@ fieldset/PWRCR: description: SYSCFG power control register fields: - name: ODEN - description: " Overdrive enable" + description: Overdrive enable bit_offset: 0 bit_size: 4 fieldset/UR0: From eb678443a3c94e355c6d115dcffcafe46bfe4a72 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Fri, 8 Apr 2022 02:54:37 +0200 Subject: [PATCH 04/35] L5: fix RCC --- data/registers/rcc_l4.yaml | 12 +++--- data/registers/rcc_l5.yaml | 87 ++++++++++++++++++++++++++++---------- 2 files changed, 70 insertions(+), 29 deletions(-) diff --git a/data/registers/rcc_l4.yaml b/data/registers/rcc_l4.yaml index 832eb6c..9751c26 100644 --- a/data/registers/rcc_l4.yaml +++ b/data/registers/rcc_l4.yaml @@ -1888,23 +1888,23 @@ enum/STOPWUCK: bit_size: 1 variants: - name: MSI - description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock + description: MSI oscillator selected as wake-up from Stop clock value: 0 - name: HSI16 - description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1) + description: HSI oscillator selected as wake-up from Stop clock value: 1 enum/SW: bit_size: 2 variants: - name: MSI - description: MSI oscillator used as system clock + description: MSI selected as system clock value: 0 - name: HSI16 - description: HSI oscillator used as system clock + description: HSI selected as system clock value: 1 - name: HSE - description: HSE oscillator used as system clock + description: HSE selected as system clock value: 2 - name: PLL - description: PLL used as system clock + description: PLL selected as system clock value: 3 diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml index df38606..94c79fb 100644 --- a/data/registers/rcc_l5.yaml +++ b/data/registers/rcc_l5.yaml @@ -1426,14 +1426,14 @@ fieldset/CFGR: description: System clock switch status bit_offset: 2 bit_size: 2 - enum_read: SWSR + enum: SW - name: HPRE description: AHB prescaler bit_offset: 4 bit_size: 4 enum: HPRE - name: PPRE1 - description: PB low-speed prescaler (APB1) + description: APB low-speed prescaler (APB1) bit_offset: 8 bit_size: 3 enum: PPRE @@ -1448,7 +1448,7 @@ fieldset/CFGR: bit_size: 1 enum: STOPWUCK - name: MCOSEL - description: Microcontroller clock output + description: Microcontroller clock output selection bit_offset: 24 bit_size: 4 enum: MCOSEL @@ -1617,6 +1617,7 @@ fieldset/CR: description: MSI clock ranges bit_offset: 4 bit_size: 4 + enum: MSIRANGE - name: HSION description: HSI clock enable bit_offset: 8 @@ -1731,7 +1732,7 @@ fieldset/CSR: description: Software reset flag bit_offset: 28 bit_size: 1 - - name: IWWDGRSTF + - name: IWDGRSTF description: Independent window watchdog reset flag bit_offset: 29 bit_size: 1 @@ -1769,6 +1770,7 @@ fieldset/PLLCFGR: description: "Main PLL, PLLSAI1 and PLLSAI2 entry clock source" bit_offset: 0 bit_size: 2 + enum: PLLSRC - name: PLLM description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock bit_offset: 4 @@ -2087,6 +2089,60 @@ enum/MCOSEL: - name: HSI48 description: Internal HSI48 clock selected value: 8 +enum/MSIRANGE: + bit_size: 4 + variants: + - name: Range100K + description: range 0 around 100 kHz + value: 0 + - name: Range200K + description: range 1 around 200 kHz + value: 1 + - name: Range400K + description: range 2 around 400 kHz + value: 2 + - name: Range800K + description: range 3 around 800 kHz + value: 3 + - name: Range1M + description: range 4 around 1 MHz + value: 4 + - name: Range2M + description: range 5 around 2 MHz + value: 5 + - name: Range4M + description: range 6 around 4 MHz + value: 6 + - name: Range8M + description: range 7 around 8 MHz + value: 7 + - name: Range16M + description: range 8 around 16 MHz + value: 8 + - name: Range24M + description: range 9 around 24 MHz + value: 9 + - name: Range32M + description: range 10 around 32 MHz + value: 10 + - name: Range48M + description: range 11 around 48 MHz + value: 11 +enum/PLLSRC: + bit_size: 2 + variants: + - name: None + description: No clock sent to PLL + value: 0 + - name: MSI + description: MSI selected as PLL input clock + value: 1 + - name: HSI16 + description: HSI selected as PLL input clock + value: 2 + - name: HSE + description: HSE selected as PLL input clock + value: 3 enum/PPRE: bit_size: 3 variants: @@ -2124,10 +2180,10 @@ enum/STOPWUCK: bit_size: 1 variants: - name: MSI - description: MSI oscillator selected as wakeup from stop clock and CSS backup clock + description: MSI oscillator selected as wake-up from Stop clock and CSS backup clock value: 0 - - name: HSI - description: HSI oscillator selected as wakeup from stop clock and CSS backup clock + - name: HSI16 + description: HSI oscillator selected as wake-up from stop clock and CSS backup clock value: 1 enum/SW: bit_size: 2 @@ -2135,7 +2191,7 @@ enum/SW: - name: MSI description: MSI selected as system clock value: 0 - - name: HSI + - name: HSI16 description: HSI selected as system clock value: 1 - name: HSE @@ -2144,18 +2200,3 @@ enum/SW: - name: PLL description: PLL selected as system clock value: 3 -enum/SWSR: - bit_size: 2 - variants: - - name: MSI - description: MSI oscillator used as system clock - value: 0 - - name: HSI - description: HSI oscillator used as system clock - value: 1 - - name: HSE - description: HSE used as system clock - value: 2 - - name: PLL - description: PLL used as system clock - value: 3 From b5d84de6e60462245df1aad983c3cf36add048e4 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Fri, 8 Apr 2022 02:54:56 +0200 Subject: [PATCH 05/35] L5: add FLASH, SYSCFG --- data/registers/flash_l5.yaml | 698 ++++++++++++++++++++++++++++++++++ data/registers/syscfg_l5.yaml | 456 ++++++++++++++++++++++ stm32data/__main__.py | 4 +- 3 files changed, 1157 insertions(+), 1 deletion(-) create mode 100644 data/registers/flash_l5.yaml create mode 100644 data/registers/syscfg_l5.yaml diff --git a/data/registers/flash_l5.yaml b/data/registers/flash_l5.yaml new file mode 100644 index 0000000..20edc2a --- /dev/null +++ b/data/registers/flash_l5.yaml @@ -0,0 +1,698 @@ +--- +block/FLASH: + description: Flash + items: + - name: ACR + description: Access control register + byte_offset: 0 + fieldset: ACR + - name: PDKEYR + description: Power down key register + byte_offset: 4 + access: Write + fieldset: PDKEYR + - name: NSKEYR + description: Flash non-secure key register + byte_offset: 8 + access: Write + fieldset: NSKEYR + - name: SECKEYR + description: Flash secure key register + byte_offset: 12 + access: Write + fieldset: SECKEYR + - name: OPTKEYR + description: Flash option key register + byte_offset: 16 + access: Write + fieldset: OPTKEYR + - name: LVEKEYR + description: Flash low voltage key register + byte_offset: 20 + access: Write + fieldset: LVEKEYR + - name: NSSR + description: Flash status register + byte_offset: 32 + fieldset: NSSR + - name: SECSR + description: Flash status register + byte_offset: 36 + fieldset: SECSR + - name: NSCR + description: Flash non-secure control register + byte_offset: 40 + fieldset: NSCR + - name: SECCR + description: Flash secure control register + byte_offset: 44 + fieldset: SECCR + - name: ECCR + description: Flash ECC register + byte_offset: 48 + fieldset: ECCR + - name: OPTR + description: Flash option register + byte_offset: 64 + fieldset: OPTR + - name: NSBOOTADD0R + description: Flash non-secure boot address 0 register + byte_offset: 68 + access: Write + fieldset: NSBOOTADD0R + - name: NSBOOTADD1R + description: Flash non-secure boot address 1 register + byte_offset: 72 + access: Write + fieldset: NSBOOTADD1R + - name: SECBOOTADD0R + description: FFlash secure boot address 0 register + byte_offset: 76 + fieldset: SECBOOTADD0R + - name: SECWM1R1 + description: Flash bank 1 secure watermak1 register + byte_offset: 80 + fieldset: SECWM1R1 + - name: SECWM1R2 + description: Flash secure watermak1 register 2 + byte_offset: 84 + fieldset: SECWM1R2 + - name: WRP1AR + description: Flash Bank 1 WRP area A address register + byte_offset: 88 + fieldset: WRP1AR + - name: WRP1BR + description: Flash Bank 1 WRP area B address register + byte_offset: 92 + fieldset: WRP1BR + - name: SECWM2R1 + description: Flash secure watermak2 register + byte_offset: 96 + fieldset: SECWM2R1 + - name: SECWM2R2 + description: Flash secure watermak2 register2 + byte_offset: 100 + fieldset: SECWM2R2 + - name: WRP2AR + description: Flash WPR2 area A address register + byte_offset: 104 + fieldset: WRP2AR + - name: WRP2BR + description: Flash WPR2 area B address register + byte_offset: 108 + fieldset: WRP2BR + - name: SECBB1R1 + description: FLASH secure block based bank 1 register + byte_offset: 128 + fieldset: SECBB1R1 + - name: SECBB1R2 + description: FLASH secure block based bank 1 register + byte_offset: 132 + fieldset: SECBB1R2 + - name: SECBB1R3 + description: FLASH secure block based bank 1 register + byte_offset: 136 + fieldset: SECBB1R3 + - name: SECBB1R4 + description: FLASH secure block based bank 1 register + byte_offset: 140 + fieldset: SECBB1R4 + - name: SECBB2R1 + description: FLASH secure block based bank 2 register + byte_offset: 160 + fieldset: SECBB2R1 + - name: SECBB2R2 + description: FLASH secure block based bank 2 register + byte_offset: 164 + fieldset: SECBB2R2 + - name: SECBB2R3 + description: FLASH secure block based bank 2 register + byte_offset: 168 + fieldset: SECBB2R3 + - name: SECBB2R4 + description: FLASH secure block based bank 2 register + byte_offset: 172 + fieldset: SECBB2R4 + - name: SECHDPCR + description: FLASH secure HDP control register + byte_offset: 192 + fieldset: SECHDPCR + - name: PRIVCFGR + description: Power privilege configuration register + byte_offset: 196 + fieldset: PRIVCFGR +fieldset/ACR: + description: Access control register + fields: + - name: LATENCY + description: Latency + bit_offset: 0 + bit_size: 4 + - name: RUN_PD + description: Flash Power-down mode during Low-power run mode + bit_offset: 13 + bit_size: 1 + - name: SLEEP_PD + description: Flash Power-down mode during Low-power sleep mode + bit_offset: 14 + bit_size: 1 + - name: LVEN + description: LVEN + bit_offset: 15 + bit_size: 1 +fieldset/ECCR: + description: Flash ECC register + fields: + - name: ADDR_ECC + description: ECC fail address + bit_offset: 0 + bit_size: 19 + - name: BK_ECC + description: BK_ECC + bit_offset: 21 + bit_size: 1 + - name: SYSF_ECC + description: SYSF_ECC + bit_offset: 22 + bit_size: 1 + - name: ECCIE + description: ECC correction interrupt enable + bit_offset: 24 + bit_size: 1 + - name: ECCC2 + description: ECCC2 + bit_offset: 28 + bit_size: 1 + - name: ECCD2 + description: ECCD2 + bit_offset: 29 + bit_size: 1 + - name: ECCC + description: ECC correction + bit_offset: 30 + bit_size: 1 + - name: ECCD + description: ECC detection + bit_offset: 31 + bit_size: 1 +fieldset/LVEKEYR: + description: Flash low voltage key register + fields: + - name: LVEKEYR + description: LVEKEYR + bit_offset: 0 + bit_size: 32 +fieldset/NSBOOTADD0R: + description: Flash non-secure boot address 0 register + fields: + - name: NSBOOTADD0 + description: NSBOOTADD0 + bit_offset: 7 + bit_size: 25 +fieldset/NSBOOTADD1R: + description: Flash non-secure boot address 1 register + fields: + - name: NSBOOTADD1 + description: NSBOOTADD1 + bit_offset: 7 + bit_size: 25 +fieldset/NSCR: + description: Flash non-secure control register + fields: + - name: NSPG + description: NSPG + bit_offset: 0 + bit_size: 1 + - name: NSPER + description: NSPER + bit_offset: 1 + bit_size: 1 + - name: NSMER1 + description: NSMER1 + bit_offset: 2 + bit_size: 1 + - name: NSPNB + description: NSPNB + bit_offset: 3 + bit_size: 7 + - name: NSBKER + description: NSBKER + bit_offset: 11 + bit_size: 1 + - name: NSMER2 + description: NSMER2 + bit_offset: 15 + bit_size: 1 + - name: NSSTRT + description: Options modification start + bit_offset: 16 + bit_size: 1 + - name: OPTSTRT + description: Options modification start + bit_offset: 17 + bit_size: 1 + - name: NSEOPIE + description: NSEOPIE + bit_offset: 24 + bit_size: 1 + - name: NSERRIE + description: NSERRIE + bit_offset: 25 + bit_size: 1 + - name: OBL_LAUNCH + description: Force the option byte loading + bit_offset: 27 + bit_size: 1 + - name: OPTLOCK + description: Options Lock + bit_offset: 30 + bit_size: 1 + - name: NSLOCK + description: NSLOCK + bit_offset: 31 + bit_size: 1 +fieldset/NSKEYR: + description: Flash non-secure key register + fields: + - name: NSKEYR + description: NSKEYR + bit_offset: 0 + bit_size: 32 +fieldset/NSSR: + description: Flash status register + fields: + - name: NSEOP + description: NSEOP + bit_offset: 0 + bit_size: 1 + - name: NSOPERR + description: NSOPERR + bit_offset: 1 + bit_size: 1 + - name: NSPROGERR + description: NSPROGERR + bit_offset: 3 + bit_size: 1 + - name: NSWRPERR + description: NSWRPERR + bit_offset: 4 + bit_size: 1 + - name: NSPGAERR + description: NSPGAERR + bit_offset: 5 + bit_size: 1 + - name: NSSIZERR + description: NSSIZERR + bit_offset: 6 + bit_size: 1 + - name: NSPGSERR + description: NSPGSERR + bit_offset: 7 + bit_size: 1 + - name: OPTWERR + description: OPTWERR + bit_offset: 13 + bit_size: 1 + - name: OPTVERR + description: OPTVERR + bit_offset: 15 + bit_size: 1 + - name: NSBSY + description: NSBusy + bit_offset: 16 + bit_size: 1 +fieldset/OPTKEYR: + description: Flash option key register + fields: + - name: OPTKEYR + description: OPTKEYR + bit_offset: 0 + bit_size: 32 +fieldset/OPTR: + description: Flash option register + fields: + - name: RDP + description: Read protection level + bit_offset: 0 + bit_size: 8 + - name: BOR_LEV + description: BOR reset Level + bit_offset: 8 + bit_size: 3 + - name: nRST_STOP + description: nRST_STOP + bit_offset: 12 + bit_size: 1 + - name: nRST_STDBY + description: nRST_STDBY + bit_offset: 13 + bit_size: 1 + - name: nRST_SHDW + description: nRST_SHDW + bit_offset: 14 + bit_size: 1 + - name: IWDG_SW + description: Independent watchdog selection + bit_offset: 16 + bit_size: 1 + - name: IWDG_STOP + description: Independent watchdog counter freeze in Stop mode + bit_offset: 17 + bit_size: 1 + - name: IWDG_STDBY + description: Independent watchdog counter freeze in Standby mode + bit_offset: 18 + bit_size: 1 + - name: WWDG_SW + description: Window watchdog selection + bit_offset: 19 + bit_size: 1 + - name: SWAP_BANK + description: SWAP_BANK + bit_offset: 20 + bit_size: 1 + - name: DB256K + description: DB256K + bit_offset: 21 + bit_size: 1 + - name: DBANK + description: DBANK + bit_offset: 22 + bit_size: 1 + - name: SRAM2_PE + description: SRAM2 parity check enable + bit_offset: 24 + bit_size: 1 + - name: SRAM2_RST + description: SRAM2 Erase when system reset + bit_offset: 25 + bit_size: 1 + - name: nSWBOOT0 + description: nSWBOOT0 + bit_offset: 26 + bit_size: 1 + - name: nBOOT0 + description: nBOOT0 + bit_offset: 27 + bit_size: 1 + - name: PA15_PUPEN + description: PA15_PUPEN + bit_offset: 28 + bit_size: 1 + - name: TZEN + description: TZEN + bit_offset: 31 + bit_size: 1 +fieldset/PDKEYR: + description: Power down key register + fields: + - name: PDKEYR + description: RUN_PD in FLASH_ACR key + bit_offset: 0 + bit_size: 32 +fieldset/PRIVCFGR: + description: Power privilege configuration register + fields: + - name: PRIV + description: PRIV + bit_offset: 0 + bit_size: 1 +fieldset/SECBB1R1: + description: FLASH secure block based bank 1 register + fields: + - name: SECBB1 + description: SECBB1 + bit_offset: 0 + bit_size: 32 +fieldset/SECBB1R2: + description: FLASH secure block based bank 1 register + fields: + - name: SECBB1 + description: SECBB1 + bit_offset: 0 + bit_size: 32 +fieldset/SECBB1R3: + description: FLASH secure block based bank 1 register + fields: + - name: SECBB1 + description: SECBB1 + bit_offset: 0 + bit_size: 32 +fieldset/SECBB1R4: + description: FLASH secure block based bank 1 register + fields: + - name: SECBB1 + description: SECBB1 + bit_offset: 0 + bit_size: 32 +fieldset/SECBB2R1: + description: FLASH secure block based bank 2 register + fields: + - name: SECBB2 + description: SECBB2 + bit_offset: 0 + bit_size: 32 +fieldset/SECBB2R2: + description: FLASH secure block based bank 2 register + fields: + - name: SECBB2 + description: SECBB2 + bit_offset: 0 + bit_size: 32 +fieldset/SECBB2R3: + description: FLASH secure block based bank 2 register + fields: + - name: SECBB2 + description: SECBB2 + bit_offset: 0 + bit_size: 32 +fieldset/SECBB2R4: + description: FLASH secure block based bank 2 register + fields: + - name: SECBB2 + description: SECBB2 + bit_offset: 0 + bit_size: 32 +fieldset/SECBOOTADD0R: + description: FFlash secure boot address 0 register + fields: + - name: BOOT_LOCK + description: BOOT_LOCK + bit_offset: 0 + bit_size: 1 + - name: SECBOOTADD0 + description: SECBOOTADD0 + bit_offset: 7 + bit_size: 25 +fieldset/SECCR: + description: Flash secure control register + fields: + - name: SECPG + description: SECPG + bit_offset: 0 + bit_size: 1 + - name: SECPER + description: SECPER + bit_offset: 1 + bit_size: 1 + - name: SECMER1 + description: SECMER1 + bit_offset: 2 + bit_size: 1 + - name: SECPNB + description: SECPNB + bit_offset: 3 + bit_size: 7 + - name: SECBKER + description: SECBKER + bit_offset: 11 + bit_size: 1 + - name: SECMER2 + description: SECMER2 + bit_offset: 15 + bit_size: 1 + - name: SECSTRT + description: SECSTRT + bit_offset: 16 + bit_size: 1 + - name: SECEOPIE + description: SECEOPIE + bit_offset: 24 + bit_size: 1 + - name: SECERRIE + description: SECERRIE + bit_offset: 25 + bit_size: 1 + - name: SECRDERRIE + description: SECRDERRIE + bit_offset: 26 + bit_size: 1 + - name: SECINV + description: SECINV + bit_offset: 29 + bit_size: 1 + - name: SECLOCK + description: SECLOCK + bit_offset: 31 + bit_size: 1 +fieldset/SECHDPCR: + description: FLASH secure HDP control register + fields: + - name: HDP1_ACCDIS + description: HDP1_ACCDIS + bit_offset: 0 + bit_size: 1 + - name: HDP2_ACCDIS + description: HDP2_ACCDIS + bit_offset: 1 + bit_size: 1 +fieldset/SECKEYR: + description: Flash secure key register + fields: + - name: SECKEYR + description: SECKEYR + bit_offset: 0 + bit_size: 32 +fieldset/SECSR: + description: Flash status register + fields: + - name: SECEOP + description: SECEOP + bit_offset: 0 + bit_size: 1 + - name: SECOPERR + description: SECOPERR + bit_offset: 1 + bit_size: 1 + - name: SECPROGERR + description: SECPROGERR + bit_offset: 3 + bit_size: 1 + - name: SECWRPERR + description: SECWRPERR + bit_offset: 4 + bit_size: 1 + - name: SECPGAERR + description: SECPGAERR + bit_offset: 5 + bit_size: 1 + - name: SECSIZERR + description: SECSIZERR + bit_offset: 6 + bit_size: 1 + - name: SECPGSERR + description: SECPGSERR + bit_offset: 7 + bit_size: 1 + - name: SECRDERR + description: Secure read protection error + bit_offset: 14 + bit_size: 1 + - name: SECBSY + description: SECBusy + bit_offset: 16 + bit_size: 1 +fieldset/SECWM1R1: + description: Flash bank 1 secure watermak1 register + fields: + - name: SECWM1_PSTRT + description: SECWM1_PSTRT + bit_offset: 0 + bit_size: 7 + - name: SECWM1_PEND + description: SECWM1_PEND + bit_offset: 16 + bit_size: 7 +fieldset/SECWM1R2: + description: Flash secure watermak1 register 2 + fields: + - name: PCROP1_PSTRT + description: PCROP1_PSTRT + bit_offset: 0 + bit_size: 7 + - name: PCROP1EN + description: PCROP1EN + bit_offset: 15 + bit_size: 1 + - name: HDP1_PEND + description: HDP1_PEND + bit_offset: 16 + bit_size: 7 + - name: HDP1EN + description: HDP1EN + bit_offset: 31 + bit_size: 1 +fieldset/SECWM2R1: + description: Flash secure watermak2 register + fields: + - name: SECWM2_PSTRT + description: SECWM2_PSTRT + bit_offset: 0 + bit_size: 7 + - name: SECWM2_PEND + description: SECWM2_PEND + bit_offset: 16 + bit_size: 7 +fieldset/SECWM2R2: + description: Flash secure watermak2 register2 + fields: + - name: PCROP2_PSTRT + description: PCROP2_PSTRT + bit_offset: 0 + bit_size: 7 + - name: PCROP2EN + description: PCROP2EN + bit_offset: 15 + bit_size: 1 + - name: HDP2_PEND + description: HDP2_PEND + bit_offset: 16 + bit_size: 7 + - name: HDP2EN + description: HDP2EN + bit_offset: 31 + bit_size: 1 +fieldset/WRP1AR: + description: Flash Bank 1 WRP area A address register + fields: + - name: WRP1A_PSTRT + description: WRP1A_PSTRT + bit_offset: 0 + bit_size: 7 + - name: WRP1A_PEND + description: WRP1A_PEND + bit_offset: 16 + bit_size: 7 +fieldset/WRP1BR: + description: Flash Bank 1 WRP area B address register + fields: + - name: WRP1B_PSTRT + description: WRP1B_PSTRT + bit_offset: 0 + bit_size: 7 + - name: WRP1B_PEND + description: WRP1B_PEND + bit_offset: 16 + bit_size: 7 +fieldset/WRP2AR: + description: Flash WPR2 area A address register + fields: + - name: WRP2A_PSTRT + description: WRP2A_PSTRT + bit_offset: 0 + bit_size: 7 + - name: WRP2A_PEND + description: WRP2A_PEND + bit_offset: 16 + bit_size: 7 +fieldset/WRP2BR: + description: Flash WPR2 area B address register + fields: + - name: WRP2B_PSTRT + description: WRP2B_PSTRT + bit_offset: 0 + bit_size: 7 + - name: WRP2B_PEND + description: WRP2B_PEND + bit_offset: 16 + bit_size: 7 diff --git a/data/registers/syscfg_l5.yaml b/data/registers/syscfg_l5.yaml new file mode 100644 index 0000000..9692d9b --- /dev/null +++ b/data/registers/syscfg_l5.yaml @@ -0,0 +1,456 @@ +--- +block/SYSCFG: + description: System configuration controller + items: + - name: SECCFGR + description: SYSCFG secure configuration register + byte_offset: 0 + fieldset: SECCFGR + - name: CFGR1 + description: configuration register 1 + byte_offset: 4 + fieldset: CFGR1 + - name: FPUIMR + description: FPU interrupt mask register + byte_offset: 8 + fieldset: FPUIMR + - name: CNSLCKR + description: SYSCFG CPU non-secure lock register + byte_offset: 12 + fieldset: CNSLCKR + - name: CSLOCKR + description: SYSCFG CPU secure lock register + byte_offset: 16 + fieldset: CSLOCKR + - name: CFGR2 + description: CFGR2 + byte_offset: 20 + fieldset: CFGR2 + - name: SCSR + description: SCSR + byte_offset: 24 + fieldset: SCSR + - name: SKR + description: SKR + byte_offset: 28 + access: Write + fieldset: SKR + - name: SWPR + description: SWPR + byte_offset: 32 + access: Write + fieldset: SWPR + - name: SWPR2 + description: SWPR2 + byte_offset: 36 + access: Write + fieldset: SWPR2 + - name: RSSCMDR + description: RSSCMDR + byte_offset: 44 + fieldset: RSSCMDR +fieldset/CFGR1: + description: configuration register 1 + fields: + - name: BOOSTEN + description: I/O analog switch voltage booster enable + bit_offset: 8 + bit_size: 1 + - name: ANASWVDD + description: GPIO analog switch control voltage selection + bit_offset: 9 + bit_size: 1 + - name: I2C_PB6_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB6 + bit_offset: 16 + bit_size: 1 + - name: I2C_PB7_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB7 + bit_offset: 17 + bit_size: 1 + - name: I2C_PB8_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB8 + bit_offset: 18 + bit_size: 1 + - name: I2C_PB9_FMP + description: Fast-mode Plus (Fm+) driving capability activation on PB9 + bit_offset: 19 + bit_size: 1 + - name: I2C1_FMP + description: I2C1 Fast-mode Plus driving capability activation + bit_offset: 20 + bit_size: 1 + - name: I2C2_FMP + description: I2C2 Fast-mode Plus driving capability activation + bit_offset: 21 + bit_size: 1 + - name: I2C3_FMP + description: I2C3 Fast-mode Plus driving capability activation + bit_offset: 22 + bit_size: 1 + - name: I2C4_FMP + description: I2C4_FMP + bit_offset: 23 + bit_size: 1 +fieldset/CFGR2: + description: CFGR2 + fields: + - name: CLL + description: LOCKUP (hardfault) output enable bit + bit_offset: 0 + bit_size: 1 + - name: SPL + description: SRAM2 parity lock bit + bit_offset: 1 + bit_size: 1 + - name: PVDL + description: PVD lock enable bit + bit_offset: 2 + bit_size: 1 + - name: ECCL + description: ECC Lock + bit_offset: 3 + bit_size: 1 + - name: SPF + description: SRAM2 parity error flag + bit_offset: 8 + bit_size: 1 +fieldset/CNSLCKR: + description: SYSCFG CPU non-secure lock register + fields: + - name: LOCKNSVTOR + description: VTOR_NS register lock + bit_offset: 0 + bit_size: 1 + - name: LOCKNSMPU + description: Non-secure MPU registers lock + bit_offset: 1 + bit_size: 1 +fieldset/CSLOCKR: + description: SYSCFG CPU secure lock register + fields: + - name: LOCKSVTAIRCR + description: LOCKSVTAIRCR + bit_offset: 0 + bit_size: 1 + - name: LOCKSMPU + description: LOCKSMPU + bit_offset: 1 + bit_size: 1 + - name: LOCKSAU + description: LOCKSAU + bit_offset: 2 + bit_size: 1 +fieldset/FPUIMR: + description: FPU interrupt mask register + fields: + - name: FPU_IE + description: Floating point unit interrupts enable bits + bit_offset: 0 + bit_size: 6 +fieldset/RSSCMDR: + description: RSSCMDR + fields: + - name: RSSCMD + description: RSS commands + bit_offset: 0 + bit_size: 8 +fieldset/SCSR: + description: SCSR + fields: + - name: SRAM2ER + description: SRAM2 Erase + bit_offset: 0 + bit_size: 1 + - name: SRAM2BSY + description: SRAM2 busy by erase operation + bit_offset: 1 + bit_size: 1 +fieldset/SECCFGR: + description: SYSCFG secure configuration register + fields: + - name: SYSCFGSEC + description: SYSCFG clock control security + bit_offset: 0 + bit_size: 1 + - name: CLASSBSEC + description: ClassB security + bit_offset: 1 + bit_size: 1 + - name: SRAM2SEC + description: SRAM2 security + bit_offset: 2 + bit_size: 1 + - name: FPUSEC + description: FPUSEC + bit_offset: 3 + bit_size: 1 +fieldset/SKR: + description: SKR + fields: + - name: KEY + description: SRAM2 write protection key for software erase + bit_offset: 0 + bit_size: 8 +fieldset/SWPR: + description: SWPR + fields: + - name: P0WP + description: P0WP + bit_offset: 0 + bit_size: 1 + - name: P1WP + description: P1WP + bit_offset: 1 + bit_size: 1 + - name: P2WP + description: P2WP + bit_offset: 2 + bit_size: 1 + - name: P3WP + description: P3WP + bit_offset: 3 + bit_size: 1 + - name: P4WP + description: P4WP + bit_offset: 4 + bit_size: 1 + - name: P5WP + description: P5WP + bit_offset: 5 + bit_size: 1 + - name: P6WP + description: P6WP + bit_offset: 6 + bit_size: 1 + - name: P7WP + description: P7WP + bit_offset: 7 + bit_size: 1 + - name: P8WP + description: P8WP + bit_offset: 8 + bit_size: 1 + - name: P9WP + description: P9WP + bit_offset: 9 + bit_size: 1 + - name: P10WP + description: P10WP + bit_offset: 10 + bit_size: 1 + - name: P11WP + description: P11WP + bit_offset: 11 + bit_size: 1 + - name: P12WP + description: P12WP + bit_offset: 12 + bit_size: 1 + - name: P13WP + description: P13WP + bit_offset: 13 + bit_size: 1 + - name: P14WP + description: P14WP + bit_offset: 14 + bit_size: 1 + - name: P15WP + description: P15WP + bit_offset: 15 + bit_size: 1 + - name: P16WP + description: P16WP + bit_offset: 16 + bit_size: 1 + - name: P17WP + description: P17WP + bit_offset: 17 + bit_size: 1 + - name: P18WP + description: P18WP + bit_offset: 18 + bit_size: 1 + - name: P19WP + description: P19WP + bit_offset: 19 + bit_size: 1 + - name: P20WP + description: P20WP + bit_offset: 20 + bit_size: 1 + - name: P21WP + description: P21WP + bit_offset: 21 + bit_size: 1 + - name: P22WP + description: P22WP + bit_offset: 22 + bit_size: 1 + - name: P23WP + description: P23WP + bit_offset: 23 + bit_size: 1 + - name: P24WP + description: P24WP + bit_offset: 24 + bit_size: 1 + - name: P25WP + description: P25WP + bit_offset: 25 + bit_size: 1 + - name: P26WP + description: P26WP + bit_offset: 26 + bit_size: 1 + - name: P27WP + description: P27WP + bit_offset: 27 + bit_size: 1 + - name: P28WP + description: P28WP + bit_offset: 28 + bit_size: 1 + - name: P29WP + description: P29WP + bit_offset: 29 + bit_size: 1 + - name: P30WP + description: P30WP + bit_offset: 30 + bit_size: 1 + - name: P31WP + description: SRAM2 page 31 write protection + bit_offset: 31 + bit_size: 1 +fieldset/SWPR2: + description: SWPR2 + fields: + - name: P32WP + description: P32WP + bit_offset: 0 + bit_size: 1 + - name: P33WP + description: P33WP + bit_offset: 1 + bit_size: 1 + - name: P34WP + description: P34WP + bit_offset: 2 + bit_size: 1 + - name: P35WP + description: P35WP + bit_offset: 3 + bit_size: 1 + - name: P36WP + description: P36WP + bit_offset: 4 + bit_size: 1 + - name: P37WP + description: P37WP + bit_offset: 5 + bit_size: 1 + - name: P38WP + description: P38WP + bit_offset: 6 + bit_size: 1 + - name: P39WP + description: P39WP + bit_offset: 7 + bit_size: 1 + - name: P40WP + description: P40WP + bit_offset: 8 + bit_size: 1 + - name: P41WP + description: P41WP + bit_offset: 9 + bit_size: 1 + - name: P42WP + description: P42WP + bit_offset: 10 + bit_size: 1 + - name: P43WP + description: P43WP + bit_offset: 11 + bit_size: 1 + - name: P44WP + description: P44WP + bit_offset: 12 + bit_size: 1 + - name: P45WP + description: P45WP + bit_offset: 13 + bit_size: 1 + - name: P46WP + description: P46WP + bit_offset: 14 + bit_size: 1 + - name: P47WP + description: P47WP + bit_offset: 15 + bit_size: 1 + - name: P48WP + description: P48WP + bit_offset: 16 + bit_size: 1 + - name: P49WP + description: P49WP + bit_offset: 17 + bit_size: 1 + - name: P50WP + description: P50WP + bit_offset: 18 + bit_size: 1 + - name: P51WP + description: P51WP + bit_offset: 19 + bit_size: 1 + - name: P52WP + description: P52WP + bit_offset: 20 + bit_size: 1 + - name: P53WP + description: P53WP + bit_offset: 21 + bit_size: 1 + - name: P54WP + description: P54WP + bit_offset: 22 + bit_size: 1 + - name: P55WP + description: P55WP + bit_offset: 23 + bit_size: 1 + - name: P56WP + description: P56WP + bit_offset: 24 + bit_size: 1 + - name: P57WP + description: P57WP + bit_offset: 25 + bit_size: 1 + - name: P58WP + description: P58WP + bit_offset: 26 + bit_size: 1 + - name: P59WP + description: P59WP + bit_offset: 27 + bit_size: 1 + - name: P60WP + description: P60WP + bit_offset: 28 + bit_size: 1 + - name: P61WP + description: P61WP + bit_offset: 29 + bit_size: 1 + - name: P62WP + description: P62WP + bit_offset: 30 + bit_size: 1 + - name: P63WP + description: P63WP + bit_offset: 31 + bit_size: 1 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 80d77f6..d7d21c2 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -134,9 +134,10 @@ perimap = [ ('STM32F3.*:SYSCFG:.*', ('syscfg', 'f3', 'SYSCFG')), ('STM32F4.*:SYSCFG:.*', ('syscfg', 'f4', 'SYSCFG')), ('STM32F7.*:SYSCFG:.*', ('syscfg', 'f7', 'SYSCFG')), - ('STM32L4.*:SYSCFG:.*', ('syscfg', 'l4', 'SYSCFG')), ('STM32L0.*:SYSCFG:.*', ('syscfg', 'l0', 'SYSCFG')), ('STM32L1.*:SYSCFG:.*', ('syscfg', 'l1', 'SYSCFG')), + ('STM32L4.*:SYSCFG:.*', ('syscfg', 'l4', 'SYSCFG')), + ('STM32L5.*:SYSCFG:.*', ('syscfg', 'l5', 'SYSCFG')), ('STM32G0.*:SYSCFG:.*', ('syscfg', 'g0', 'SYSCFG')), ('STM32G4.*:SYSCFG:.*', ('syscfg', 'g4', 'SYSCFG')), ('STM32H7.*:SYSCFG:.*', ('syscfg', 'h7', 'SYSCFG')), @@ -219,6 +220,7 @@ perimap = [ ('STM32F7.*:FLASH:.*', ('flash', 'f7', 'FLASH')), ('STM32L1.*:FLASH:.*', ('flash', 'l1', 'FLASH')), ('STM32L4.*:FLASH:.*', ('flash', 'l4', 'FLASH')), + ('STM32L5.*:FLASH:.*', ('flash', 'l5', 'FLASH')), ('STM32U5.*:FLASH:.*', ('flash', 'u5', 'FLASH')), ('STM32WB.*:FLASH:.*', ('flash', 'wb55', 'FLASH')), ('STM32G0.*:FLASH:.*', ('flash', 'g0', 'FLASH')), From 6107d5a72ed9041548943c071c2933df516e17b6 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Sat, 9 Apr 2022 00:28:44 +0200 Subject: [PATCH 06/35] Add USB --- data/registers/usb_v1.yaml | 272 +++++++++++++++++++++++++++ data/registers/usb_v2.yaml | 370 +++++++++++++++++++++++++++++++++++++ stm32data/__main__.py | 4 + 3 files changed, 646 insertions(+) create mode 100644 data/registers/usb_v1.yaml create mode 100644 data/registers/usb_v2.yaml diff --git a/data/registers/usb_v1.yaml b/data/registers/usb_v1.yaml new file mode 100644 index 0000000..259b17f --- /dev/null +++ b/data/registers/usb_v1.yaml @@ -0,0 +1,272 @@ +--- +block/USB: + description: Universal serial bus full-speed device interface + items: + - name: EPR + description: endpoint register + array: + len: 8 + stride: 4 + byte_offset: 0 + fieldset: EPR + - name: CNTR + description: control register + byte_offset: 64 + fieldset: CNTR + - name: ISTR + description: interrupt status register + byte_offset: 68 + fieldset: ISTR + - name: FNR + description: frame number register + byte_offset: 72 + access: Read + fieldset: FNR + - name: DADDR + description: device address + byte_offset: 76 + fieldset: DADDR + - name: BTABLE + description: Buffer table address + byte_offset: 80 + fieldset: BTABLE +fieldset/BTABLE: + description: Buffer table address + fields: + - name: BTABLE + description: BTABLE + bit_offset: 3 + bit_size: 13 +fieldset/CNTR: + description: control register + fields: + - name: FRES + description: "Force a reset of the USB peripheral, exactly like a RESET signaling on the USB" + bit_offset: 0 + bit_size: 1 + - name: PDWN + description: Enter power down mode + bit_offset: 1 + bit_size: 1 + - name: LPMODE + description: Enter low-power mode + bit_offset: 2 + bit_size: 1 + - name: FSUSP + description: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected + bit_offset: 3 + bit_size: 1 + - name: RESUME + description: Resume request + bit_offset: 4 + bit_size: 1 + - name: ESOFM + description: "ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" + bit_offset: 8 + bit_size: 1 + - name: SOFM + description: "SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" + bit_offset: 9 + bit_size: 1 + - name: RESETM + description: "RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" + bit_offset: 10 + bit_size: 1 + - name: SUSPM + description: "SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" + bit_offset: 11 + bit_size: 1 + - name: WKUPM + description: "WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" + bit_offset: 12 + bit_size: 1 + - name: ERRM + description: "ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" + bit_offset: 13 + bit_size: 1 + - name: PMAOVRM + description: "PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" + bit_offset: 14 + bit_size: 1 + - name: CTRM + description: "CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" + bit_offset: 15 + bit_size: 1 +fieldset/DADDR: + description: device address + fields: + - name: ADD + description: device address + bit_offset: 0 + bit_size: 7 + - name: EF + description: USB device enabled + bit_offset: 7 + bit_size: 1 +fieldset/EPR: + description: endpoint register + fields: + - name: EA + description: EA + bit_offset: 0 + bit_size: 4 + - name: STAT_TX + description: STAT_TX + bit_offset: 4 + bit_size: 2 + enum: STAT_TX + - name: DTOG_TX + description: DTOG_TX + bit_offset: 6 + bit_size: 1 + - name: CTR_TX + description: CTR_TX + bit_offset: 7 + bit_size: 1 + - name: EP_KIND + description: EP_KIND + bit_offset: 8 + bit_size: 1 + - name: EP_TYPE + description: EPTYPE + bit_offset: 9 + bit_size: 2 + enum: EP_TYPE + - name: SETUP + description: SETUP + bit_offset: 11 + bit_size: 1 + - name: STAT_RX + description: STAT_RX + bit_offset: 12 + bit_size: 2 + enum: STAT_RX + - name: DTOG_RX + description: DTOG_RX + bit_offset: 14 + bit_size: 1 + - name: CTR_RX + description: CTR_RX + bit_offset: 15 + bit_size: 1 +fieldset/FNR: + description: frame number register + fields: + - name: FN + description: FN + bit_offset: 0 + bit_size: 11 + - name: LSOF + description: LSOF + bit_offset: 11 + bit_size: 2 + - name: LCK + description: the frame timer remains in this state until an USB reset or USB suspend event occurs + bit_offset: 13 + bit_size: 1 + - name: RXDM + description: received data minus upstream port data line + bit_offset: 14 + bit_size: 1 + - name: RXDP + description: received data plus upstream port data line + bit_offset: 15 + bit_size: 1 +fieldset/ISTR: + description: interrupt status register + fields: + - name: EP_ID + description: EP_ID + bit_offset: 0 + bit_size: 4 + - name: DIR + description: DIR + bit_offset: 4 + bit_size: 1 + enum: DIR + - name: ESOF + description: an SOF packet is expected but not received + bit_offset: 8 + bit_size: 1 + - name: SOF + description: beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus + bit_offset: 9 + bit_size: 1 + - name: RESET + description: peripheral detects an active USB RESET signal at its inputs + bit_offset: 10 + bit_size: 1 + - name: SUSP + description: "no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus" + bit_offset: 11 + bit_size: 1 + - name: WKUP + description: activity is detected that wakes up the USB peripheral + bit_offset: 12 + bit_size: 1 + - name: ERR + description: "One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred" + bit_offset: 13 + bit_size: 1 + - name: PMAOVR + description: microcontroller has not been able to respond in time to an USB memory request + bit_offset: 14 + bit_size: 1 + - name: CTR + description: endpoint has successfully completed a transaction + bit_offset: 15 + bit_size: 1 +enum/DIR: + bit_size: 1 + variants: + - name: To + description: data transmitted by the USB peripheral to the host PC + value: 0 + - name: From + description: data received by the USB peripheral from the host PC + value: 1 +enum/EP_TYPE: + bit_size: 2 + variants: + - name: Bulk + description: Bulk endpoint + value: 0 + - name: Control + description: Control endpoint + value: 1 + - name: Iso + description: Iso endpoint + value: 2 + - name: Interrupt + description: Interrupt endpoint + value: 3 +enum/STAT_RX: + bit_size: 2 + variants: + - name: Disabled + description: all reception requests addressed to this endpoint are ignored + value: 0 + - name: Stall + description: the endpoint is stalled and all reception requests result in a STALL handshake + value: 1 + - name: Nak + description: the endpoint is naked and all reception requests result in a NAK handshake + value: 2 + - name: Valid + description: this endpoint is enabled for reception + value: 3 +enum/STAT_TX: + bit_size: 2 + variants: + - name: Disabled + description: all transmission requests addressed to this endpoint are ignored + value: 0 + - name: Stall + description: the endpoint is stalled and all transmission requests result in a STALL handshake + value: 1 + - name: Nak + description: the endpoint is naked and all transmission requests result in a NAK handshake + value: 2 + - name: Valid + description: this endpoint is enabled for transmission + value: 3 diff --git a/data/registers/usb_v2.yaml b/data/registers/usb_v2.yaml new file mode 100644 index 0000000..f5d20de --- /dev/null +++ b/data/registers/usb_v2.yaml @@ -0,0 +1,370 @@ +--- +block/USB: + description: Universal serial bus full-speed device interface + items: + - name: EPR + description: endpoint register + array: + len: 8 + stride: 4 + byte_offset: 0 + fieldset: EPR + - name: CNTR + description: control register + byte_offset: 64 + fieldset: CNTR + - name: ISTR + description: interrupt status register + byte_offset: 68 + fieldset: ISTR + - name: FNR + description: frame number register + byte_offset: 72 + access: Read + fieldset: FNR + - name: DADDR + description: device address + byte_offset: 76 + fieldset: DADDR + - name: BTABLE + description: Buffer table address + byte_offset: 80 + fieldset: BTABLE + - name: LPMCSR + description: LPM control and status register + byte_offset: 84 + fieldset: LPMCSR + - name: BCDR + description: Battery Charging Detector + byte_offset: 88 + fieldset: BCDR +fieldset/BCDR: + description: Battery Charging Detector + fields: + - name: BCDEN + description: Battery charging detector mode enable + bit_offset: 0 + bit_size: 1 + - name: DCDEN + description: Data contact detection mode enable + bit_offset: 1 + bit_size: 1 + - name: PDEN + description: Primary detection mode enable + bit_offset: 2 + bit_size: 1 + - name: SDEN + description: Secondary detection mode enable + bit_offset: 3 + bit_size: 1 + - name: DCDET + description: Data contact detection status + bit_offset: 4 + bit_size: 1 + - name: PDET + description: Primary detection status + bit_offset: 5 + bit_size: 1 + - name: SDET + description: Secondary detection status + bit_offset: 6 + bit_size: 1 + enum: SDET + - name: PS2DET + description: DM pull-up detection status + bit_offset: 7 + bit_size: 1 + - name: DPPU + description: DP pull-up control + bit_offset: 15 + bit_size: 1 +fieldset/BTABLE: + description: Buffer table address + fields: + - name: BTABLE + description: BTABLE + bit_offset: 3 + bit_size: 13 +fieldset/CNTR: + description: control register + fields: + - name: FRES + description: "Force a reset of the USB peripheral, exactly like a RESET signaling on the USB" + bit_offset: 0 + bit_size: 1 + - name: PDWN + description: Enter power down mode + bit_offset: 1 + bit_size: 1 + - name: LPMODE + description: Enter low-power mode + bit_offset: 2 + bit_size: 1 + - name: FSUSP + description: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected + bit_offset: 3 + bit_size: 1 + - name: RESUME + description: Resume request + bit_offset: 4 + bit_size: 1 + - name: L1RESUME + description: LPM L1 request request + bit_offset: 5 + bit_size: 1 + - name: L1REQM + description: "L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" + bit_offset: 7 + bit_size: 1 + - name: ESOFM + description: "ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" + bit_offset: 8 + bit_size: 1 + - name: SOFM + description: "SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" + bit_offset: 9 + bit_size: 1 + - name: RESETM + description: "RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" + bit_offset: 10 + bit_size: 1 + - name: SUSPM + description: "SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" + bit_offset: 11 + bit_size: 1 + - name: WKUPM + description: "WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" + bit_offset: 12 + bit_size: 1 + - name: ERRM + description: "ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" + bit_offset: 13 + bit_size: 1 + - name: PMAOVRM + description: "PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" + bit_offset: 14 + bit_size: 1 + - name: CTRM + description: "CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set" + bit_offset: 15 + bit_size: 1 +fieldset/DADDR: + description: device address + fields: + - name: ADD + description: device address + bit_offset: 0 + bit_size: 7 + - name: EF + description: USB device enabled + bit_offset: 7 + bit_size: 1 +fieldset/EPR: + description: endpoint register + fields: + - name: EA + description: EA + bit_offset: 0 + bit_size: 4 + - name: STAT_TX + description: STAT_TX + bit_offset: 4 + bit_size: 2 + enum: STAT_TX + - name: DTOG_TX + description: DTOG_TX + bit_offset: 6 + bit_size: 1 + - name: CTR_TX + description: CTR_TX + bit_offset: 7 + bit_size: 1 + - name: EP_KIND + description: EP_KIND + bit_offset: 8 + bit_size: 1 + - name: EP_TYPE + description: EPTYPE + bit_offset: 9 + bit_size: 2 + enum: EP_TYPE + - name: SETUP + description: SETUP + bit_offset: 11 + bit_size: 1 + - name: STAT_RX + description: STAT_RX + bit_offset: 12 + bit_size: 2 + enum: STAT_RX + - name: DTOG_RX + description: DTOG_RX + bit_offset: 14 + bit_size: 1 + - name: CTR_RX + description: CTR_RX + bit_offset: 15 + bit_size: 1 +fieldset/FNR: + description: frame number register + fields: + - name: FN + description: FN + bit_offset: 0 + bit_size: 11 + - name: LSOF + description: LSOF + bit_offset: 11 + bit_size: 2 + - name: LCK + description: the frame timer remains in this state until an USB reset or USB suspend event occurs + bit_offset: 13 + bit_size: 1 + - name: RXDM + description: received data minus upstream port data line + bit_offset: 14 + bit_size: 1 + - name: RXDP + description: received data plus upstream port data line + bit_offset: 15 + bit_size: 1 +fieldset/ISTR: + description: interrupt status register + fields: + - name: EP_ID + description: EP_ID + bit_offset: 0 + bit_size: 4 + - name: DIR + description: DIR + bit_offset: 4 + bit_size: 1 + enum: DIR + - name: L1REQ + description: LPM command to enter the L1 state is successfully received and acknowledged + bit_offset: 7 + bit_size: 1 + - name: ESOF + description: an SOF packet is expected but not received + bit_offset: 8 + bit_size: 1 + - name: SOF + description: beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus + bit_offset: 9 + bit_size: 1 + - name: RESET + description: peripheral detects an active USB RESET signal at its inputs + bit_offset: 10 + bit_size: 1 + - name: SUSP + description: "no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus" + bit_offset: 11 + bit_size: 1 + - name: WKUP + description: activity is detected that wakes up the USB peripheral + bit_offset: 12 + bit_size: 1 + - name: ERR + description: "One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred" + bit_offset: 13 + bit_size: 1 + - name: PMAOVR + description: microcontroller has not been able to respond in time to an USB memory request + bit_offset: 14 + bit_size: 1 + - name: CTR + description: endpoint has successfully completed a transaction + bit_offset: 15 + bit_size: 1 +fieldset/LPMCSR: + description: LPM control and status register + fields: + - name: LPMEN + description: enable the LPM support within the USB device + bit_offset: 0 + bit_size: 1 + - name: LPMACK + description: LPMACK + bit_offset: 1 + bit_size: 1 + enum: LPMACK + - name: REMWAKE + description: REMWAKE + bit_offset: 3 + bit_size: 1 + - name: BESL + description: BESL + bit_offset: 4 + bit_size: 4 +enum/DIR: + bit_size: 1 + variants: + - name: To + description: data transmitted by the USB peripheral to the host PC + value: 0 + - name: From + description: data received by the USB peripheral from the host PC + value: 1 +enum/EP_TYPE: + bit_size: 2 + variants: + - name: Bulk + description: Bulk endpoint + value: 0 + - name: Control + description: Control endpoint + value: 1 + - name: Iso + description: Iso endpoint + value: 2 + - name: Interrupt + description: Interrupt endpoint + value: 3 +enum/LPMACK: + bit_size: 1 + variants: + - name: Nyet + description: the valid LPM Token will be NYET + value: 0 + - name: Ack + description: the valid LPM Token will be ACK + value: 1 +enum/SDET: + bit_size: 1 + variants: + - name: CDP + description: CDP detected + value: 0 + - name: DCP + description: DCP detected + value: 1 +enum/STAT_RX: + bit_size: 2 + variants: + - name: Disabled + description: all reception requests addressed to this endpoint are ignored + value: 0 + - name: Stall + description: the endpoint is stalled and all reception requests result in a STALL handshake + value: 1 + - name: Nak + description: the endpoint is naked and all reception requests result in a NAK handshake + value: 2 + - name: Valid + description: this endpoint is enabled for reception + value: 3 +enum/STAT_TX: + bit_size: 2 + variants: + - name: Disabled + description: all transmission requests addressed to this endpoint are ignored + value: 0 + - name: Stall + description: the endpoint is stalled and all transmission requests result in a STALL handshake + value: 1 + - name: Nak + description: the endpoint is naked and all transmission requests result in a NAK handshake + value: 2 + - name: Valid + description: this endpoint is enabled for transmission + value: 3 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index d7d21c2..3d31e96 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -159,6 +159,10 @@ perimap = [ ('.*:SDIO:sdmmc_v1_2', ('sdmmc', 'v1', 'SDMMC')), ('.*:SDMMC:sdmmc_v1_3', ('sdmmc', 'v1', 'SDMMC')), ('.*:SPDIFRX:spdifrx1_v1_0', ('spdifrx', 'v1', 'SPDIFRX')), + + # USB + ('STM32(F1|L1|F3).*:USB:.*', ('usb', 'v1', 'USB')), + ('.*:USB:.*', ('usb', 'v2', 'USB')), ('.*:USB_OTG_FS:otgfs1_v1_.*', ('otgfs', 'v1', 'OTG_FS')), ('.*:USB_OTG_FS:otgfs1_v3_.*', ('otgfs', 'v1', 'OTG_FS')), ('.*:USB_OTG_HS:otghs1_v1_.*', ('otghs', 'v1', 'OTG_HS')), From c90234583ea5c17b21774a8e439dbe6e0b3699f5 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Sat, 9 Apr 2022 00:43:48 +0200 Subject: [PATCH 07/35] RCC: fix USBFS -> USB --- data/registers/rcc_f4.yaml | 2 +- data/registers/rcc_l4.yaml | 6 +++--- data/registers/rcc_l5.yaml | 16 ++++++++-------- data/registers/rcc_wb.yaml | 2 +- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index 52910a9..08512a0 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -1621,7 +1621,7 @@ fieldset/DCKCFGR2: bit_size: 1 enum: CECSEL - name: CK48MSEL - description: SDIO/USBFS clock selection + description: SDIO/USB clock selection bit_offset: 27 bit_size: 1 enum: CKMSEL diff --git a/data/registers/rcc_l4.yaml b/data/registers/rcc_l4.yaml index 9751c26..eff25cc 100644 --- a/data/registers/rcc_l4.yaml +++ b/data/registers/rcc_l4.yaml @@ -598,7 +598,7 @@ fieldset/APB1ENR1: description: CAN2 clock enable bit_offset: 26 bit_size: 1 - - name: USBFSEN + - name: USBEN description: USB FS clock enable bit_offset: 26 bit_size: 1 @@ -720,7 +720,7 @@ fieldset/APB1RSTR1: description: CAN2 reset bit_offset: 26 bit_size: 1 - - name: USBFSRST + - name: USBRST description: USB FS reset bit_offset: 26 bit_size: 1 @@ -846,7 +846,7 @@ fieldset/APB1SMENR1: description: CAN2 clocks enable during Sleep and Stop modes bit_offset: 26 bit_size: 1 - - name: USBFSSMEN + - name: USBSMEN description: USB FS clock enable during Sleep and Stop modes bit_offset: 26 bit_size: 1 diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml index 94c79fb..9cf1aaa 100644 --- a/data/registers/rcc_l5.yaml +++ b/data/registers/rcc_l5.yaml @@ -708,8 +708,8 @@ fieldset/APB1ENR2: description: FDCAN1EN bit_offset: 9 bit_size: 1 - - name: USBFSEN - description: USBFSEN + - name: USBEN + description: USBEN bit_offset: 21 bit_size: 1 - name: UCPD1EN @@ -822,8 +822,8 @@ fieldset/APB1RSTR2: description: FDCAN1RST bit_offset: 9 bit_size: 1 - - name: USBFSRST - description: USBFSRST + - name: USBRST + description: USBRST bit_offset: 21 bit_size: 1 - name: UCPD1RST @@ -944,8 +944,8 @@ fieldset/APB1SECSR2: description: FDCAN1SECF bit_offset: 9 bit_size: 1 - - name: USBFSSECF - description: USBFSSECF + - name: USBSECF + description: USBSECF bit_offset: 21 bit_size: 1 - name: UCPD1SECF @@ -1066,8 +1066,8 @@ fieldset/APB1SMENR2: description: FDCAN1SMEN bit_offset: 9 bit_size: 1 - - name: USBFSSMEN - description: USBFSSMEN + - name: USBSMEN + description: USBSMEN bit_offset: 21 bit_size: 1 - name: UCPD1SMEN diff --git a/data/registers/rcc_wb.yaml b/data/registers/rcc_wb.yaml index 7d8307b..dc63453 100644 --- a/data/registers/rcc_wb.yaml +++ b/data/registers/rcc_wb.yaml @@ -544,7 +544,7 @@ fieldset/APB1RSTR1: description: CRS reset bit_offset: 24 bit_size: 1 - - name: USBFSRST + - name: USBRST description: USB FS reset bit_offset: 26 bit_size: 1 From e81eeb157e5cee616f6b142bc59219e759728897 Mon Sep 17 00:00:00 2001 From: Philip A Reimer Date: Sat, 9 Apr 2022 10:06:32 -0600 Subject: [PATCH 08/35] add pwr_l4 --- data/registers/pwr_l4.yaml | 1272 ++++++++++++++++++++++++++++++++++++ stm32data/__main__.py | 1 + 2 files changed, 1273 insertions(+) create mode 100644 data/registers/pwr_l4.yaml diff --git a/data/registers/pwr_l4.yaml b/data/registers/pwr_l4.yaml new file mode 100644 index 0000000..4b1e590 --- /dev/null +++ b/data/registers/pwr_l4.yaml @@ -0,0 +1,1272 @@ +--- +block/PWR: + description: Power control + items: + - name: CR1 + description: Power control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Power control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: Power control register 3 + byte_offset: 8 + fieldset: CR3 + - name: CR4 + description: Power control register 4 + byte_offset: 12 + fieldset: CR4 + - name: SR1 + description: Power status register 1 + byte_offset: 16 + access: Read + fieldset: SR1 + - name: SR2 + description: Power status register 2 + byte_offset: 20 + access: Read + fieldset: SR2 + - name: SCR + description: Power status clear register + byte_offset: 24 + access: Write + fieldset: SCR + - name: PUCRA + description: Power Port A pull-up control register + byte_offset: 32 + fieldset: PUCRA + - name: PDCRA + description: Power Port A pull-down control register + byte_offset: 36 + fieldset: PDCRA + - name: PUCRB + description: Power Port B pull-up control register + byte_offset: 40 + fieldset: PUCRB + - name: PDCRB + description: Power Port B pull-down control register + byte_offset: 44 + fieldset: PDCRB + - name: PUCRC + description: Power Port C pull-up control register + byte_offset: 48 + fieldset: PUCRC + - name: PDCRC + description: Power Port C pull-down control register + byte_offset: 52 + fieldset: PDCRC + - name: PUCRD + description: Power Port D pull-up control register + byte_offset: 56 + fieldset: PUCRD + - name: PDCRD + description: Power Port D pull-down control register + byte_offset: 60 + fieldset: PDCRD + - name: PUCRE + description: Power Port E pull-up control register + byte_offset: 64 + fieldset: PUCRE + - name: PDCRE + description: Power Port E pull-down control register + byte_offset: 68 + fieldset: PDCRE + - name: PUCRF + description: Power Port F pull-up control register + byte_offset: 72 + fieldset: PUCRF + - name: PDCRF + description: Power Port F pull-down control register + byte_offset: 76 + fieldset: PDCRF + - name: PUCRG + description: Power Port G pull-up control register + byte_offset: 80 + fieldset: PUCRG + - name: PDCRG + description: Power Port G pull-down control register + byte_offset: 84 + fieldset: PDCRG + - name: PUCRH + description: Power Port H pull-up control register + byte_offset: 88 + fieldset: PUCRH + - name: PDCRH + description: Power Port H pull-down control register + byte_offset: 92 + fieldset: PDCRH +fieldset/CR1: + description: Power control register 1 + fields: + - name: LPMS + description: Low-power mode selection + bit_offset: 0 + bit_size: 3 + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: VOS + description: Voltage scaling range selection + bit_offset: 9 + bit_size: 2 + - name: LPR + description: Low-power run + bit_offset: 14 + bit_size: 1 +fieldset/CR2: + description: Power control register 2 + fields: + - name: PVDE + description: Power voltage detector enable + bit_offset: 0 + bit_size: 1 + - name: PLS + description: Power voltage detector level selection + bit_offset: 1 + bit_size: 3 + - name: PVME1 + description: "Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V" + bit_offset: 4 + bit_size: 1 + - name: PVME2 + description: "Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V" + bit_offset: 5 + bit_size: 1 + - name: PVME3 + description: "Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" + bit_offset: 6 + bit_size: 1 + - name: PVME4 + description: "Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V" + bit_offset: 7 + bit_size: 1 + - name: IOSV + description: VDDIO2 Independent I/Os supply valid + bit_offset: 9 + bit_size: 1 + - name: USV + description: VDDUSB USB supply valid + bit_offset: 10 + bit_size: 1 +fieldset/CR3: + description: Power control register 3 + fields: + - name: EWUP1 + description: Enable Wakeup pin WKUP1 + bit_offset: 0 + bit_size: 1 + - name: EWUP2 + description: Enable Wakeup pin WKUP2 + bit_offset: 1 + bit_size: 1 + - name: EWUP3 + description: Enable Wakeup pin WKUP3 + bit_offset: 2 + bit_size: 1 + - name: EWUP4 + description: Enable Wakeup pin WKUP4 + bit_offset: 3 + bit_size: 1 + - name: EWUP5 + description: Enable Wakeup pin WKUP5 + bit_offset: 4 + bit_size: 1 + - name: RRS + description: SRAM2 retention in Standby mode + bit_offset: 8 + bit_size: 1 + - name: APC + description: Apply pull-up and pull-down configuration + bit_offset: 10 + bit_size: 1 + - name: EWF + description: Enable internal wakeup line + bit_offset: 15 + bit_size: 1 +fieldset/CR4: + description: Power control register 4 + fields: + - name: WP1 + description: Wakeup pin WKUP1 polarity + bit_offset: 0 + bit_size: 1 + - name: WP2 + description: Wakeup pin WKUP2 polarity + bit_offset: 1 + bit_size: 1 + - name: WP3 + description: Wakeup pin WKUP3 polarity + bit_offset: 2 + bit_size: 1 + - name: WP4 + description: Wakeup pin WKUP4 polarity + bit_offset: 3 + bit_size: 1 + - name: WP5 + description: Wakeup pin WKUP5 polarity + bit_offset: 4 + bit_size: 1 + - name: VBE + description: VBAT battery charging enable + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT battery charging resistor selection + bit_offset: 9 + bit_size: 1 +fieldset/PDCRA: + description: Power Port A pull-down control register + fields: + - name: PD0 + description: Port A pull-down bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: Port A pull-down bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PD2 + description: Port A pull-down bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: Port A pull-down bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PD4 + description: Port A pull-down bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PD5 + description: Port A pull-down bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PD6 + description: Port A pull-down bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PD7 + description: Port A pull-down bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PD8 + description: Port A pull-down bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PD9 + description: Port A pull-down bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PD10 + description: Port A pull-down bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PD11 + description: Port A pull-down bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PD12 + description: Port A pull-down bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PD13 + description: Port A pull-down bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PD14 + description: Port A pull-down bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PD15 + description: Port A pull-down bit y (y=0..15) + bit_offset: 15 + bit_size: 1 +fieldset/PDCRB: + description: Power Port B pull-down control register + fields: + - name: PD0 + description: Port B pull-down bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: Port B pull-down bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PD2 + description: Port B pull-down bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: Port B pull-down bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PD4 + description: Port B pull-down bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PD5 + description: Port B pull-down bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PD6 + description: Port B pull-down bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PD7 + description: Port B pull-down bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PD8 + description: Port B pull-down bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PD9 + description: Port B pull-down bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PD10 + description: Port B pull-down bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PD11 + description: Port B pull-down bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PD12 + description: Port B pull-down bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PD13 + description: Port B pull-down bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PD14 + description: Port B pull-down bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PD15 + description: Port B pull-down bit y (y=0..15) + bit_offset: 15 + bit_size: 1 +fieldset/PDCRC: + description: Power Port C pull-down control register + fields: + - name: PD0 + description: Port C pull-down bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: Port C pull-down bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PD2 + description: Port C pull-down bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: Port C pull-down bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PD4 + description: Port C pull-down bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PD5 + description: Port C pull-down bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PD6 + description: Port C pull-down bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PD7 + description: Port C pull-down bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PD8 + description: Port C pull-down bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PD9 + description: Port C pull-down bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PD10 + description: Port C pull-down bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PD11 + description: Port C pull-down bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PD12 + description: Port C pull-down bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PD13 + description: Port C pull-down bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PD14 + description: Port C pull-down bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PD15 + description: Port C pull-down bit y (y=0..15) + bit_offset: 15 + bit_size: 1 +fieldset/PDCRD: + description: Power Port D pull-down control register + fields: + - name: PD0 + description: Port D pull-down bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: Port D pull-down bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PD2 + description: Port D pull-down bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: Port D pull-down bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PD4 + description: Port D pull-down bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PD5 + description: Port D pull-down bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PD6 + description: Port D pull-down bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PD7 + description: Port D pull-down bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PD8 + description: Port D pull-down bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PD9 + description: Port D pull-down bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PD10 + description: Port D pull-down bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PD11 + description: Port D pull-down bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PD12 + description: Port D pull-down bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PD13 + description: Port D pull-down bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PD14 + description: Port D pull-down bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PD15 + description: Port D pull-down bit y (y=0..15) + bit_offset: 15 + bit_size: 1 +fieldset/PDCRE: + description: Power Port E pull-down control register + fields: + - name: PD0 + description: Port E pull-down bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: Port E pull-down bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PD2 + description: Port E pull-down bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: Port E pull-down bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PD4 + description: Port E pull-down bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PD5 + description: Port E pull-down bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PD6 + description: Port E pull-down bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PD7 + description: Port E pull-down bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PD8 + description: Port E pull-down bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PD9 + description: Port E pull-down bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PD10 + description: Port E pull-down bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PD11 + description: Port E pull-down bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PD12 + description: Port E pull-down bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PD13 + description: Port E pull-down bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PD14 + description: Port E pull-down bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PD15 + description: Port E pull-down bit y (y=0..15) + bit_offset: 15 + bit_size: 1 +fieldset/PDCRF: + description: Power Port F pull-down control register + fields: + - name: PD0 + description: Port F pull-down bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: Port F pull-down bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PD2 + description: Port F pull-down bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: Port F pull-down bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PD4 + description: Port F pull-down bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PD5 + description: Port F pull-down bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PD6 + description: Port F pull-down bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PD7 + description: Port F pull-down bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PD8 + description: Port F pull-down bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PD9 + description: Port F pull-down bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PD10 + description: Port F pull-down bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PD11 + description: Port F pull-down bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PD12 + description: Port F pull-down bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PD13 + description: Port F pull-down bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PD14 + description: Port F pull-down bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PD15 + description: Port F pull-down bit y (y=0..15) + bit_offset: 15 + bit_size: 1 +fieldset/PDCRG: + description: Power Port G pull-down control register + fields: + - name: PD0 + description: Port G pull-down bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: Port G pull-down bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PD2 + description: Port G pull-down bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: Port G pull-down bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PD4 + description: Port G pull-down bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PD5 + description: Port G pull-down bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PD6 + description: Port G pull-down bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PD7 + description: Port G pull-down bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PD8 + description: Port G pull-down bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PD9 + description: Port G pull-down bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PD10 + description: Port G pull-down bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PD11 + description: Port G pull-down bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PD12 + description: Port G pull-down bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PD13 + description: Port G pull-down bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PD14 + description: Port G pull-down bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PD15 + description: Port G pull-down bit y (y=0..15) + bit_offset: 15 + bit_size: 1 +fieldset/PDCRH: + description: Power Port H pull-down control register + fields: + - name: PD0 + description: Port H pull-down bit y (y=0..1) + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: Port H pull-down bit y (y=0..1) + bit_offset: 1 + bit_size: 1 +fieldset/PUCRA: + description: Power Port A pull-up control register + fields: + - name: PU0 + description: Port A pull-up bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: Port A pull-up bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PU2 + description: Port A pull-up bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: Port A pull-up bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: Port A pull-up bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PU5 + description: Port A pull-up bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PU6 + description: Port A pull-up bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PU7 + description: Port A pull-up bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PU8 + description: Port A pull-up bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PU9 + description: Port A pull-up bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PU10 + description: Port A pull-up bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PU11 + description: Port A pull-up bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PU12 + description: Port A pull-up bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PU13 + description: Port A pull-up bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PU14 + description: Port A pull-up bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PU15 + description: Port A pull-up bit y (y=0..15) + bit_offset: 15 + bit_size: 1 +fieldset/PUCRB: + description: Power Port B pull-up control register + fields: + - name: PU0 + description: Port B pull-up bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: Port B pull-up bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PU2 + description: Port B pull-up bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: Port B pull-up bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: Port B pull-up bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PU5 + description: Port B pull-up bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PU6 + description: Port B pull-up bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PU7 + description: Port B pull-up bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PU8 + description: Port B pull-up bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PU9 + description: Port B pull-up bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PU10 + description: Port B pull-up bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PU11 + description: Port B pull-up bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PU12 + description: Port B pull-up bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PU13 + description: Port B pull-up bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PU14 + description: Port B pull-up bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PU15 + description: Port B pull-up bit y (y=0..15) + bit_offset: 15 + bit_size: 1 +fieldset/PUCRC: + description: Power Port C pull-up control register + fields: + - name: PU0 + description: Port C pull-up bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: Port C pull-up bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PU2 + description: Port C pull-up bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: Port C pull-up bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: Port C pull-up bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PU5 + description: Port C pull-up bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PU6 + description: Port C pull-up bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PU7 + description: Port C pull-up bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PU8 + description: Port C pull-up bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PU9 + description: Port C pull-up bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PU10 + description: Port C pull-up bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PU11 + description: Port C pull-up bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PU12 + description: Port C pull-up bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PU13 + description: Port C pull-up bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PU14 + description: Port C pull-up bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PU15 + description: Port C pull-up bit y (y=0..15) + bit_offset: 15 + bit_size: 1 +fieldset/PUCRD: + description: Power Port D pull-up control register + fields: + - name: PU0 + description: Port D pull-up bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: Port D pull-up bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PU2 + description: Port D pull-up bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: Port D pull-up bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: Port D pull-up bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PU5 + description: Port D pull-up bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PU6 + description: Port D pull-up bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PU7 + description: Port D pull-up bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PU8 + description: Port D pull-up bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PU9 + description: Port D pull-up bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PU10 + description: Port D pull-up bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PU11 + description: Port D pull-up bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PU12 + description: Port D pull-up bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PU13 + description: Port D pull-up bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PU14 + description: Port D pull-up bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PU15 + description: Port D pull-up bit y (y=0..15) + bit_offset: 15 + bit_size: 1 +fieldset/PUCRE: + description: Power Port E pull-up control register + fields: + - name: PU0 + description: Port E pull-up bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: Port E pull-up bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PU2 + description: Port E pull-up bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: Port E pull-up bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: Port E pull-up bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PU5 + description: Port E pull-up bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PU6 + description: Port E pull-up bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PU7 + description: Port E pull-up bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PU8 + description: Port E pull-up bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PU9 + description: Port E pull-up bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PU10 + description: Port E pull-up bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PU11 + description: Port E pull-up bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PU12 + description: Port E pull-up bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PU13 + description: Port E pull-up bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PU14 + description: Port E pull-up bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PU15 + description: Port E pull-up bit y (y=0..15) + bit_offset: 15 + bit_size: 1 +fieldset/PUCRF: + description: Power Port F pull-up control register + fields: + - name: PU0 + description: Port F pull-up bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: Port F pull-up bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PU2 + description: Port F pull-up bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: Port F pull-up bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: Port F pull-up bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PU5 + description: Port F pull-up bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PU6 + description: Port F pull-up bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PU7 + description: Port F pull-up bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PU8 + description: Port F pull-up bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PU9 + description: Port F pull-up bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PU10 + description: Port F pull-up bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PU11 + description: Port F pull-up bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PU12 + description: Port F pull-up bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PU13 + description: Port F pull-up bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PU14 + description: Port F pull-up bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PU15 + description: Port F pull-up bit y (y=0..15) + bit_offset: 15 + bit_size: 1 +fieldset/PUCRG: + description: Power Port G pull-up control register + fields: + - name: PU0 + description: Port G pull-up bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: Port G pull-up bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PU2 + description: Port G pull-up bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: Port G pull-up bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: Port G pull-up bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PU5 + description: Port G pull-up bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PU6 + description: Port G pull-up bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PU7 + description: Port G pull-up bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PU8 + description: Port G pull-up bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PU9 + description: Port G pull-up bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PU10 + description: Port G pull-up bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PU11 + description: Port G pull-up bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PU12 + description: Port G pull-up bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PU13 + description: Port G pull-up bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PU14 + description: Port G pull-up bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PU15 + description: Port G pull-up bit y (y=0..15) + bit_offset: 15 + bit_size: 1 +fieldset/PUCRH: + description: Power Port H pull-up control register + fields: + - name: PU0 + description: Port H pull-up bit y (y=0..1) + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: Port H pull-up bit y (y=0..1) + bit_offset: 1 + bit_size: 1 +fieldset/SCR: + description: Power status clear register + fields: + - name: WUF1 + description: Clear wakeup flag 1 + bit_offset: 0 + bit_size: 1 + - name: WUF2 + description: Clear wakeup flag 2 + bit_offset: 1 + bit_size: 1 + - name: WUF3 + description: Clear wakeup flag 3 + bit_offset: 2 + bit_size: 1 + - name: WUF4 + description: Clear wakeup flag 4 + bit_offset: 3 + bit_size: 1 + - name: WUF5 + description: Clear wakeup flag 5 + bit_offset: 4 + bit_size: 1 + - name: SBF + description: Clear standby flag + bit_offset: 8 + bit_size: 1 +fieldset/SR1: + description: Power status register 1 + fields: + - name: CWUF1 + description: Wakeup flag 1 + bit_offset: 0 + bit_size: 1 + - name: CWUF2 + description: Wakeup flag 2 + bit_offset: 1 + bit_size: 1 + - name: CWUF3 + description: Wakeup flag 3 + bit_offset: 2 + bit_size: 1 + - name: CWUF4 + description: Wakeup flag 4 + bit_offset: 3 + bit_size: 1 + - name: CWUF5 + description: Wakeup flag 5 + bit_offset: 4 + bit_size: 1 + - name: CSBF + description: Standby flag + bit_offset: 8 + bit_size: 1 + - name: WUFI + description: Wakeup flag internal + bit_offset: 15 + bit_size: 1 +fieldset/SR2: + description: Power status register 2 + fields: + - name: REGLPS + description: Low-power regulator started + bit_offset: 8 + bit_size: 1 + - name: REGLPF + description: Low-power regulator flag + bit_offset: 9 + bit_size: 1 + - name: VOSF + description: Voltage scaling flag + bit_offset: 10 + bit_size: 1 + - name: PVDO + description: Power voltage detector output + bit_offset: 11 + bit_size: 1 + - name: PVMO1 + description: "Peripheral voltage monitoring output: VDDUSB vs. 1.2 V" + bit_offset: 12 + bit_size: 1 + - name: PVMO2 + description: "Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V" + bit_offset: 13 + bit_size: 1 + - name: PVMO3 + description: "Peripheral voltage monitoring output: VDDA vs. 1.62 V" + bit_offset: 14 + bit_size: 1 + - name: PVMO4 + description: "Peripheral voltage monitoring output: VDDA vs. 2.2 V" + bit_offset: 15 + bit_size: 1 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 3d31e96..0e77029 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -212,6 +212,7 @@ perimap = [ ('STM32F4.*:PWR:.*', ('pwr', 'f4', 'PWR')), ('STM32F7.*:PWR:.*', ('pwr', 'f7', 'PWR')), ('STM32L1.*:PWR:.*', ('pwr', 'l1', 'PWR')), + ('STM32L4.*:PWR:.*', ('pwr', 'l4', 'PWR')), ('STM32U5.*:PWR:.*', ('pwr', 'u5', 'PWR')), ('STM32WL.*:PWR:.*', ('pwr', 'wl5', 'PWR')), ('STM32WB.*:PWR:.*', ('pwr', 'wb55', 'PWR')), From 5f64d3d1480c76e85fa6f29a520f799c4242d301 Mon Sep 17 00:00:00 2001 From: Philip A Reimer Date: Sat, 9 Apr 2022 10:08:35 -0600 Subject: [PATCH 09/35] arrayify l4 power control registers --- data/registers/pwr_l4.yaml | 1034 +----------------------------------- 1 file changed, 17 insertions(+), 1017 deletions(-) diff --git a/data/registers/pwr_l4.yaml b/data/registers/pwr_l4.yaml index 4b1e590..ec57a9c 100644 --- a/data/registers/pwr_l4.yaml +++ b/data/registers/pwr_l4.yaml @@ -33,70 +33,20 @@ block/PWR: byte_offset: 24 access: Write fieldset: SCR - - name: PUCRA + - name: PUCR description: Power Port A pull-up control register + array: + len: 8 + stride: 8 byte_offset: 32 - fieldset: PUCRA - - name: PDCRA + fieldset: PCR + - name: PDCR description: Power Port A pull-down control register + array: + len: 8 + stride: 8 byte_offset: 36 - fieldset: PDCRA - - name: PUCRB - description: Power Port B pull-up control register - byte_offset: 40 - fieldset: PUCRB - - name: PDCRB - description: Power Port B pull-down control register - byte_offset: 44 - fieldset: PDCRB - - name: PUCRC - description: Power Port C pull-up control register - byte_offset: 48 - fieldset: PUCRC - - name: PDCRC - description: Power Port C pull-down control register - byte_offset: 52 - fieldset: PDCRC - - name: PUCRD - description: Power Port D pull-up control register - byte_offset: 56 - fieldset: PUCRD - - name: PDCRD - description: Power Port D pull-down control register - byte_offset: 60 - fieldset: PDCRD - - name: PUCRE - description: Power Port E pull-up control register - byte_offset: 64 - fieldset: PUCRE - - name: PDCRE - description: Power Port E pull-down control register - byte_offset: 68 - fieldset: PDCRE - - name: PUCRF - description: Power Port F pull-up control register - byte_offset: 72 - fieldset: PUCRF - - name: PDCRF - description: Power Port F pull-down control register - byte_offset: 76 - fieldset: PDCRF - - name: PUCRG - description: Power Port G pull-up control register - byte_offset: 80 - fieldset: PUCRG - - name: PDCRG - description: Power Port G pull-down control register - byte_offset: 84 - fieldset: PDCRG - - name: PUCRH - description: Power Port H pull-up control register - byte_offset: 88 - fieldset: PUCRH - - name: PDCRH - description: Power Port H pull-down control register - byte_offset: 92 - fieldset: PDCRH + fieldset: PCR fieldset/CR1: description: Power control register 1 fields: @@ -217,966 +167,16 @@ fieldset/CR4: description: VBAT battery charging resistor selection bit_offset: 9 bit_size: 1 -fieldset/PDCRA: - description: Power Port A pull-down control register +fieldset/PCR: + description: Power Port pull control register fields: - - name: PD0 - description: Port A pull-down bit y (y=0..15) + - name: P + description: Port pull bit y (y=0..15) bit_offset: 0 bit_size: 1 - - name: PD1 - description: Port A pull-down bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PD2 - description: Port A pull-down bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PD3 - description: Port A pull-down bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PD4 - description: Port A pull-down bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PD5 - description: Port A pull-down bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PD6 - description: Port A pull-down bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PD7 - description: Port A pull-down bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PD8 - description: Port A pull-down bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PD9 - description: Port A pull-down bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PD10 - description: Port A pull-down bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PD11 - description: Port A pull-down bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PD12 - description: Port A pull-down bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PD13 - description: Port A pull-down bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PD14 - description: Port A pull-down bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PD15 - description: Port A pull-down bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PDCRB: - description: Power Port B pull-down control register - fields: - - name: PD0 - description: Port B pull-down bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PD1 - description: Port B pull-down bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PD2 - description: Port B pull-down bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PD3 - description: Port B pull-down bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PD4 - description: Port B pull-down bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PD5 - description: Port B pull-down bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PD6 - description: Port B pull-down bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PD7 - description: Port B pull-down bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PD8 - description: Port B pull-down bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PD9 - description: Port B pull-down bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PD10 - description: Port B pull-down bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PD11 - description: Port B pull-down bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PD12 - description: Port B pull-down bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PD13 - description: Port B pull-down bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PD14 - description: Port B pull-down bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PD15 - description: Port B pull-down bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PDCRC: - description: Power Port C pull-down control register - fields: - - name: PD0 - description: Port C pull-down bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PD1 - description: Port C pull-down bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PD2 - description: Port C pull-down bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PD3 - description: Port C pull-down bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PD4 - description: Port C pull-down bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PD5 - description: Port C pull-down bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PD6 - description: Port C pull-down bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PD7 - description: Port C pull-down bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PD8 - description: Port C pull-down bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PD9 - description: Port C pull-down bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PD10 - description: Port C pull-down bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PD11 - description: Port C pull-down bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PD12 - description: Port C pull-down bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PD13 - description: Port C pull-down bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PD14 - description: Port C pull-down bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PD15 - description: Port C pull-down bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PDCRD: - description: Power Port D pull-down control register - fields: - - name: PD0 - description: Port D pull-down bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PD1 - description: Port D pull-down bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PD2 - description: Port D pull-down bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PD3 - description: Port D pull-down bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PD4 - description: Port D pull-down bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PD5 - description: Port D pull-down bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PD6 - description: Port D pull-down bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PD7 - description: Port D pull-down bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PD8 - description: Port D pull-down bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PD9 - description: Port D pull-down bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PD10 - description: Port D pull-down bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PD11 - description: Port D pull-down bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PD12 - description: Port D pull-down bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PD13 - description: Port D pull-down bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PD14 - description: Port D pull-down bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PD15 - description: Port D pull-down bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PDCRE: - description: Power Port E pull-down control register - fields: - - name: PD0 - description: Port E pull-down bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PD1 - description: Port E pull-down bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PD2 - description: Port E pull-down bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PD3 - description: Port E pull-down bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PD4 - description: Port E pull-down bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PD5 - description: Port E pull-down bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PD6 - description: Port E pull-down bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PD7 - description: Port E pull-down bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PD8 - description: Port E pull-down bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PD9 - description: Port E pull-down bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PD10 - description: Port E pull-down bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PD11 - description: Port E pull-down bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PD12 - description: Port E pull-down bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PD13 - description: Port E pull-down bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PD14 - description: Port E pull-down bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PD15 - description: Port E pull-down bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PDCRF: - description: Power Port F pull-down control register - fields: - - name: PD0 - description: Port F pull-down bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PD1 - description: Port F pull-down bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PD2 - description: Port F pull-down bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PD3 - description: Port F pull-down bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PD4 - description: Port F pull-down bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PD5 - description: Port F pull-down bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PD6 - description: Port F pull-down bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PD7 - description: Port F pull-down bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PD8 - description: Port F pull-down bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PD9 - description: Port F pull-down bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PD10 - description: Port F pull-down bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PD11 - description: Port F pull-down bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PD12 - description: Port F pull-down bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PD13 - description: Port F pull-down bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PD14 - description: Port F pull-down bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PD15 - description: Port F pull-down bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PDCRG: - description: Power Port G pull-down control register - fields: - - name: PD0 - description: Port G pull-down bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PD1 - description: Port G pull-down bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PD2 - description: Port G pull-down bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PD3 - description: Port G pull-down bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PD4 - description: Port G pull-down bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PD5 - description: Port G pull-down bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PD6 - description: Port G pull-down bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PD7 - description: Port G pull-down bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PD8 - description: Port G pull-down bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PD9 - description: Port G pull-down bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PD10 - description: Port G pull-down bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PD11 - description: Port G pull-down bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PD12 - description: Port G pull-down bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PD13 - description: Port G pull-down bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PD14 - description: Port G pull-down bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PD15 - description: Port G pull-down bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PDCRH: - description: Power Port H pull-down control register - fields: - - name: PD0 - description: Port H pull-down bit y (y=0..1) - bit_offset: 0 - bit_size: 1 - - name: PD1 - description: Port H pull-down bit y (y=0..1) - bit_offset: 1 - bit_size: 1 -fieldset/PUCRA: - description: Power Port A pull-up control register - fields: - - name: PU0 - description: Port A pull-up bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PU1 - description: Port A pull-up bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PU2 - description: Port A pull-up bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PU3 - description: Port A pull-up bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PU4 - description: Port A pull-up bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PU5 - description: Port A pull-up bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PU6 - description: Port A pull-up bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PU7 - description: Port A pull-up bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PU8 - description: Port A pull-up bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PU9 - description: Port A pull-up bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PU10 - description: Port A pull-up bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PU11 - description: Port A pull-up bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PU12 - description: Port A pull-up bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PU13 - description: Port A pull-up bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PU14 - description: Port A pull-up bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PU15 - description: Port A pull-up bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PUCRB: - description: Power Port B pull-up control register - fields: - - name: PU0 - description: Port B pull-up bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PU1 - description: Port B pull-up bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PU2 - description: Port B pull-up bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PU3 - description: Port B pull-up bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PU4 - description: Port B pull-up bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PU5 - description: Port B pull-up bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PU6 - description: Port B pull-up bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PU7 - description: Port B pull-up bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PU8 - description: Port B pull-up bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PU9 - description: Port B pull-up bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PU10 - description: Port B pull-up bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PU11 - description: Port B pull-up bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PU12 - description: Port B pull-up bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PU13 - description: Port B pull-up bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PU14 - description: Port B pull-up bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PU15 - description: Port B pull-up bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PUCRC: - description: Power Port C pull-up control register - fields: - - name: PU0 - description: Port C pull-up bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PU1 - description: Port C pull-up bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PU2 - description: Port C pull-up bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PU3 - description: Port C pull-up bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PU4 - description: Port C pull-up bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PU5 - description: Port C pull-up bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PU6 - description: Port C pull-up bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PU7 - description: Port C pull-up bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PU8 - description: Port C pull-up bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PU9 - description: Port C pull-up bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PU10 - description: Port C pull-up bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PU11 - description: Port C pull-up bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PU12 - description: Port C pull-up bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PU13 - description: Port C pull-up bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PU14 - description: Port C pull-up bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PU15 - description: Port C pull-up bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PUCRD: - description: Power Port D pull-up control register - fields: - - name: PU0 - description: Port D pull-up bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PU1 - description: Port D pull-up bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PU2 - description: Port D pull-up bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PU3 - description: Port D pull-up bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PU4 - description: Port D pull-up bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PU5 - description: Port D pull-up bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PU6 - description: Port D pull-up bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PU7 - description: Port D pull-up bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PU8 - description: Port D pull-up bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PU9 - description: Port D pull-up bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PU10 - description: Port D pull-up bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PU11 - description: Port D pull-up bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PU12 - description: Port D pull-up bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PU13 - description: Port D pull-up bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PU14 - description: Port D pull-up bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PU15 - description: Port D pull-up bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PUCRE: - description: Power Port E pull-up control register - fields: - - name: PU0 - description: Port E pull-up bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PU1 - description: Port E pull-up bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PU2 - description: Port E pull-up bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PU3 - description: Port E pull-up bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PU4 - description: Port E pull-up bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PU5 - description: Port E pull-up bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PU6 - description: Port E pull-up bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PU7 - description: Port E pull-up bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PU8 - description: Port E pull-up bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PU9 - description: Port E pull-up bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PU10 - description: Port E pull-up bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PU11 - description: Port E pull-up bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PU12 - description: Port E pull-up bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PU13 - description: Port E pull-up bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PU14 - description: Port E pull-up bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PU15 - description: Port E pull-up bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PUCRF: - description: Power Port F pull-up control register - fields: - - name: PU0 - description: Port F pull-up bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PU1 - description: Port F pull-up bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PU2 - description: Port F pull-up bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PU3 - description: Port F pull-up bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PU4 - description: Port F pull-up bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PU5 - description: Port F pull-up bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PU6 - description: Port F pull-up bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PU7 - description: Port F pull-up bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PU8 - description: Port F pull-up bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PU9 - description: Port F pull-up bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PU10 - description: Port F pull-up bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PU11 - description: Port F pull-up bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PU12 - description: Port F pull-up bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PU13 - description: Port F pull-up bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PU14 - description: Port F pull-up bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PU15 - description: Port F pull-up bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PUCRG: - description: Power Port G pull-up control register - fields: - - name: PU0 - description: Port G pull-up bit y (y=0..15) - bit_offset: 0 - bit_size: 1 - - name: PU1 - description: Port G pull-up bit y (y=0..15) - bit_offset: 1 - bit_size: 1 - - name: PU2 - description: Port G pull-up bit y (y=0..15) - bit_offset: 2 - bit_size: 1 - - name: PU3 - description: Port G pull-up bit y (y=0..15) - bit_offset: 3 - bit_size: 1 - - name: PU4 - description: Port G pull-up bit y (y=0..15) - bit_offset: 4 - bit_size: 1 - - name: PU5 - description: Port G pull-up bit y (y=0..15) - bit_offset: 5 - bit_size: 1 - - name: PU6 - description: Port G pull-up bit y (y=0..15) - bit_offset: 6 - bit_size: 1 - - name: PU7 - description: Port G pull-up bit y (y=0..15) - bit_offset: 7 - bit_size: 1 - - name: PU8 - description: Port G pull-up bit y (y=0..15) - bit_offset: 8 - bit_size: 1 - - name: PU9 - description: Port G pull-up bit y (y=0..15) - bit_offset: 9 - bit_size: 1 - - name: PU10 - description: Port G pull-up bit y (y=0..15) - bit_offset: 10 - bit_size: 1 - - name: PU11 - description: Port G pull-up bit y (y=0..15) - bit_offset: 11 - bit_size: 1 - - name: PU12 - description: Port G pull-up bit y (y=0..15) - bit_offset: 12 - bit_size: 1 - - name: PU13 - description: Port G pull-up bit y (y=0..15) - bit_offset: 13 - bit_size: 1 - - name: PU14 - description: Port G pull-up bit y (y=0..15) - bit_offset: 14 - bit_size: 1 - - name: PU15 - description: Port G pull-up bit y (y=0..15) - bit_offset: 15 - bit_size: 1 -fieldset/PUCRH: - description: Power Port H pull-up control register - fields: - - name: PU0 - description: Port H pull-up bit y (y=0..1) - bit_offset: 0 - bit_size: 1 - - name: PU1 - description: Port H pull-up bit y (y=0..1) - bit_offset: 1 - bit_size: 1 + array: + len: 16 + stride: 1 fieldset/SCR: description: Power status clear register fields: From 13a9eebb52a7adfe320d7c7ec0fea26e8f6bc252 Mon Sep 17 00:00:00 2001 From: Philip A Reimer Date: Sat, 9 Apr 2022 10:54:07 -0600 Subject: [PATCH 10/35] add l4 pwr enums --- data/registers/pwr_l4.yaml | 213 ++++++++++++++++++++++++++++++------- 1 file changed, 177 insertions(+), 36 deletions(-) diff --git a/data/registers/pwr_l4.yaml b/data/registers/pwr_l4.yaml index ec57a9c..a5a497e 100644 --- a/data/registers/pwr_l4.yaml +++ b/data/registers/pwr_l4.yaml @@ -54,18 +54,22 @@ fieldset/CR1: description: Low-power mode selection bit_offset: 0 bit_size: 3 + enum: LPMS - name: DBP description: Disable backup domain write protection bit_offset: 8 bit_size: 1 + enum: DBP - name: VOS description: Voltage scaling range selection bit_offset: 9 bit_size: 2 + enum: VOS - name: LPR description: Low-power run bit_offset: 14 bit_size: 1 + enum: LPR fieldset/CR2: description: Power control register 2 fields: @@ -73,69 +77,68 @@ fieldset/CR2: description: Power voltage detector enable bit_offset: 0 bit_size: 1 + enum: PVDE - name: PLS description: Power voltage detector level selection bit_offset: 1 bit_size: 3 + enum: PLS - name: PVME1 description: "Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V" bit_offset: 4 bit_size: 1 + enum: PVME - name: PVME2 description: "Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V" bit_offset: 5 bit_size: 1 + enum: PVME - name: PVME3 description: "Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" bit_offset: 6 bit_size: 1 + enum: PVME - name: PVME4 description: "Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V" bit_offset: 7 bit_size: 1 + enum: PVME - name: IOSV description: VDDIO2 Independent I/Os supply valid bit_offset: 9 bit_size: 1 + enum: IOSV - name: USV description: VDDUSB USB supply valid bit_offset: 10 bit_size: 1 + enum: USV fieldset/CR3: description: Power control register 3 fields: - - name: EWUP1 - description: Enable Wakeup pin WKUP1 + - name: EWUP + description: Enable Wakeup pin WKUP bit_offset: 0 bit_size: 1 - - name: EWUP2 - description: Enable Wakeup pin WKUP2 - bit_offset: 1 - bit_size: 1 - - name: EWUP3 - description: Enable Wakeup pin WKUP3 - bit_offset: 2 - bit_size: 1 - - name: EWUP4 - description: Enable Wakeup pin WKUP4 - bit_offset: 3 - bit_size: 1 - - name: EWUP5 - description: Enable Wakeup pin WKUP5 - bit_offset: 4 - bit_size: 1 + array: + len: 5 + stride: 1 + enum: EWUP - name: RRS description: SRAM2 retention in Standby mode bit_offset: 8 bit_size: 1 + enum: RRS - name: APC description: Apply pull-up and pull-down configuration bit_offset: 10 bit_size: 1 + enum: APC - name: EWF description: Enable internal wakeup line bit_offset: 15 bit_size: 1 + enum: EWF fieldset/CR4: description: Power control register 4 fields: @@ -180,26 +183,14 @@ fieldset/PCR: fieldset/SCR: description: Power status clear register fields: - - name: WUF1 - description: Clear wakeup flag 1 + - name: CWUF + description: Clear wakeup flag bit_offset: 0 bit_size: 1 - - name: WUF2 - description: Clear wakeup flag 2 - bit_offset: 1 - bit_size: 1 - - name: WUF3 - description: Clear wakeup flag 3 - bit_offset: 2 - bit_size: 1 - - name: WUF4 - description: Clear wakeup flag 4 - bit_offset: 3 - bit_size: 1 - - name: WUF5 - description: Clear wakeup flag 5 - bit_offset: 4 - bit_size: 1 + array: + len: 5 + stride: 1 + enum_write: CWUFW - name: SBF description: Clear standby flag bit_offset: 8 @@ -270,3 +261,153 @@ fieldset/SR2: description: "Peripheral voltage monitoring output: VDDA vs. 2.2 V" bit_offset: 15 bit_size: 1 +enum/LPMS: + bit_size: 3 + variants: + - name: Stop0 + description: Stop 0 mode + value: 0 + - name: Stop1 + description: Stop 1 mode + value: 1 + - name: Stop2 + description: Stop 2 mode + value: 2 + - name: Standby + description: Standby mode + value: 3 + - name: Shutdown + description: Shutdown mode + value: 4 +enum/DBP: + bit_size: 1 + variants: + - name: Disabled + description: Access to RTC and backup registers disabled + value: 0 + - name: Enabled + description: Access to RTC and backup registers enabled + value: 1 +enum/VOS: + bit_size: 2 + variants: + - name: Range1 + description: Range 1 + value: 1 + - name: Range2 + description: Range 2 + value: 2 +enum/LPR: + bit_size: 1 + variants: + - name: MainMode + description: Voltage regulator in Main mode + value: 0 + - name: LowPowerMode + description: Voltage regulator in low-power mode + value: 1 +enum/PVDE: + bit_size: 1 + variants: + - name: Disabled + description: PVD Disabled + value: 0 + - name: Enabled + description: PVD Enabled + value: 1 +enum/PLS: + bit_size: 3 + variants: + - name: V2_0 + description: 2.0V + value: 0 + - name: V2_2 + description: 2.2V + value: 1 + - name: V2_4 + description: 2.4V + value: 2 + - name: V2_5 + description: 2.5V + value: 3 + - name: V2_6 + description: 2.6V + value: 4 + - name: V2_8 + description: 2.8V + value: 5 + - name: V2_9 + description: 2.9V + value: 6 + - name: External + description: External input analog voltage PVD_IN (compared internally to VREFINT) + value: 7 +enum/PVME: + bit_size: 1 + variants: + - name: Disabled + description: Peripheral voltage monitoring disable + value: 0 + - name: Enabled + description: Peripheral voltage monitoring enable + value: 1 +enum/IOSV: + bit_size: 1 + variants: + - name: Invalid + description: VDDIO2 is not present. Logical and electrical isolation is applied to ignore this supply + value: 0 + - name: Valid + description: VDDIO2 is valid + value: 1 +enum/USV: + bit_size: 1 + variants: + - name: Invalid + description: VDDUSB is not present. Logical and electrical isolation is applied to ignore this supply + value: 0 + - name: Valid + description: VDDUSB is valid + value: 1 +enum/EWUP: + bit_size: 1 + variants: + - name: Disabled + description: WKUP pin x is used for general purpose I/Os. An event on the WKUP pin x does not wakeup the device from Standby mode + value: 0 + - name: Enabled + description: WKUP pin x is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin x wakes-up the system from Standby mode) + value: 1 +enum/RRS: + bit_size: 1 + variants: + - name: PowerOff + description: SRAM2 powered off in Standby mode (SRAM2 content lost) + value: 0 + - name: OnLPR + description: SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept) + value: 1 +enum/APC: + bit_size: 1 + variants: + - name: Disabled + description: PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os + value: 0 + - name: Enabled + description: I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied + value: 1 +enum/EWF: + bit_size: 1 + variants: + - name: Disabled + description: Internal wakeup line disable + value: 0 + - name: Enabled + description: Internal wakeup line enable + value: 1 +enum/CWUFW: + bit_size: 1 + variants: + - name: Clear + description: Setting this bit clears the WUF flag in the PWR_SR1 register. This bit is always read as 0. + value: 1 From c01cb449e9b8aaae0acea6f4b81253e490ff4ff1 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Sun, 10 Apr 2022 01:46:46 +0200 Subject: [PATCH 11/35] Add L5 PWR --- data/registers/pwr_l4.yaml | 144 +++++------ data/registers/pwr_l5.yaml | 484 +++++++++++++++++++++++++++++++++++++ stm32data/__main__.py | 1 + 3 files changed, 557 insertions(+), 72 deletions(-) create mode 100644 data/registers/pwr_l5.yaml diff --git a/data/registers/pwr_l4.yaml b/data/registers/pwr_l4.yaml index a5a497e..64696f6 100644 --- a/data/registers/pwr_l4.yaml +++ b/data/registers/pwr_l4.yaml @@ -261,6 +261,57 @@ fieldset/SR2: description: "Peripheral voltage monitoring output: VDDA vs. 2.2 V" bit_offset: 15 bit_size: 1 +enum/APC: + bit_size: 1 + variants: + - name: Disabled + description: PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os + value: 0 + - name: Enabled + description: I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied + value: 1 +enum/CWUFW: + bit_size: 1 + variants: + - name: Clear + description: Setting this bit clears the WUF flag in the PWR_SR1 register. This bit is always read as 0. + value: 1 +enum/DBP: + bit_size: 1 + variants: + - name: Disabled + description: Access to RTC and backup registers disabled + value: 0 + - name: Enabled + description: Access to RTC and backup registers enabled + value: 1 +enum/EWF: + bit_size: 1 + variants: + - name: Disabled + description: Internal wakeup line disable + value: 0 + - name: Enabled + description: Internal wakeup line enable + value: 1 +enum/EWUP: + bit_size: 1 + variants: + - name: Disabled + description: WKUP pin x is used for general purpose I/Os. An event on the WKUP pin x does not wakeup the device from Standby mode + value: 0 + - name: Enabled + description: WKUP pin x is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin x wakes-up the system from Standby mode) + value: 1 +enum/IOSV: + bit_size: 1 + variants: + - name: Invalid + description: VDDIO2 is not present. Logical and electrical isolation is applied to ignore this supply + value: 0 + - name: Valid + description: VDDIO2 is valid + value: 1 enum/LPMS: bit_size: 3 variants: @@ -279,24 +330,6 @@ enum/LPMS: - name: Shutdown description: Shutdown mode value: 4 -enum/DBP: - bit_size: 1 - variants: - - name: Disabled - description: Access to RTC and backup registers disabled - value: 0 - - name: Enabled - description: Access to RTC and backup registers enabled - value: 1 -enum/VOS: - bit_size: 2 - variants: - - name: Range1 - description: Range 1 - value: 1 - - name: Range2 - description: Range 2 - value: 2 enum/LPR: bit_size: 1 variants: @@ -306,15 +339,6 @@ enum/LPR: - name: LowPowerMode description: Voltage regulator in low-power mode value: 1 -enum/PVDE: - bit_size: 1 - variants: - - name: Disabled - description: PVD Disabled - value: 0 - - name: Enabled - description: PVD Enabled - value: 1 enum/PLS: bit_size: 3 variants: @@ -342,6 +366,15 @@ enum/PLS: - name: External description: External input analog voltage PVD_IN (compared internally to VREFINT) value: 7 +enum/PVDE: + bit_size: 1 + variants: + - name: Disabled + description: PVD Disabled + value: 0 + - name: Enabled + description: PVD Enabled + value: 1 enum/PVME: bit_size: 1 variants: @@ -351,33 +384,6 @@ enum/PVME: - name: Enabled description: Peripheral voltage monitoring enable value: 1 -enum/IOSV: - bit_size: 1 - variants: - - name: Invalid - description: VDDIO2 is not present. Logical and electrical isolation is applied to ignore this supply - value: 0 - - name: Valid - description: VDDIO2 is valid - value: 1 -enum/USV: - bit_size: 1 - variants: - - name: Invalid - description: VDDUSB is not present. Logical and electrical isolation is applied to ignore this supply - value: 0 - - name: Valid - description: VDDUSB is valid - value: 1 -enum/EWUP: - bit_size: 1 - variants: - - name: Disabled - description: WKUP pin x is used for general purpose I/Os. An event on the WKUP pin x does not wakeup the device from Standby mode - value: 0 - - name: Enabled - description: WKUP pin x is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin x wakes-up the system from Standby mode) - value: 1 enum/RRS: bit_size: 1 variants: @@ -387,27 +393,21 @@ enum/RRS: - name: OnLPR description: SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept) value: 1 -enum/APC: +enum/USV: bit_size: 1 variants: - - name: Disabled - description: PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os + - name: Invalid + description: VDDUSB is not present. Logical and electrical isolation is applied to ignore this supply value: 0 - - name: Enabled - description: I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied + - name: Valid + description: VDDUSB is valid value: 1 -enum/EWF: - bit_size: 1 +enum/VOS: + bit_size: 2 variants: - - name: Disabled - description: Internal wakeup line disable - value: 0 - - name: Enabled - description: Internal wakeup line enable - value: 1 -enum/CWUFW: - bit_size: 1 - variants: - - name: Clear - description: Setting this bit clears the WUF flag in the PWR_SR1 register. This bit is always read as 0. + - name: Range1 + description: Range 1 value: 1 + - name: Range2 + description: Range 2 + value: 2 diff --git a/data/registers/pwr_l5.yaml b/data/registers/pwr_l5.yaml new file mode 100644 index 0000000..6689429 --- /dev/null +++ b/data/registers/pwr_l5.yaml @@ -0,0 +1,484 @@ +--- +block/PWR: + description: Power control + items: + - name: CR1 + description: Power control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Power control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: Power control register 3 + byte_offset: 8 + fieldset: CR3 + - name: CR4 + description: Power control register 4 + byte_offset: 12 + fieldset: CR4 + - name: SR1 + description: Power status register 1 + byte_offset: 16 + access: Read + fieldset: SR1 + - name: SR2 + description: Power status register 2 + byte_offset: 20 + access: Read + fieldset: SR2 + - name: SCR + description: Power status clear register + byte_offset: 24 + access: Write + fieldset: SCR + - name: PUCR + description: Power Port A pull-up control register + array: + len: 8 + stride: 8 + byte_offset: 32 + fieldset: PCR + - name: PDCR + description: Power Port A pull-down control register + array: + len: 8 + stride: 8 + byte_offset: 36 + fieldset: PCR + - name: SECCFGR + description: Power secure configuration register + byte_offset: 120 + fieldset: SECCFGR + - name: PRIVCFGR + description: Power privilege configuration register + byte_offset: 128 + fieldset: PRIVCFGR +fieldset/CR1: + description: Power control register 1 + fields: + - name: LPMS + description: Low-power mode selection + bit_offset: 0 + bit_size: 3 + enum: LPMS + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + enum: DBP + - name: VOS + description: Voltage scaling range selection + bit_offset: 9 + bit_size: 2 + enum: VOS + - name: LPR + description: Low-power run + bit_offset: 14 + bit_size: 1 + enum: LPR +fieldset/CR2: + description: Power control register 2 + fields: + - name: PVDE + description: Power voltage detector enable + bit_offset: 0 + bit_size: 1 + enum: PVDE + - name: PLS + description: Power voltage detector level selection + bit_offset: 1 + bit_size: 3 + enum: PLS + - name: PVME1 + description: "Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V" + bit_offset: 4 + bit_size: 1 + enum: PVME + - name: PVME2 + description: "Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V" + bit_offset: 5 + bit_size: 1 + enum: PVME + - name: PVME3 + description: "Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" + bit_offset: 6 + bit_size: 1 + enum: PVME + - name: PVME4 + description: "Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V" + bit_offset: 7 + bit_size: 1 + enum: PVME + - name: IOSV + description: VDDIO2 Independent I/Os supply valid + bit_offset: 9 + bit_size: 1 + enum: IOSV + - name: USV + description: VDDUSB USB supply valid + bit_offset: 10 + bit_size: 1 + enum: USV +fieldset/CR3: + description: Power control register 3 + fields: + - name: EWUP + description: Enable Wakeup pin WKUP + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + enum: EWUP + - name: RRS + description: SRAM2 retention in Standby mode + bit_offset: 8 + bit_size: 2 + enum: RRS + - name: APC + description: Apply pull-up and pull-down configuration + bit_offset: 10 + bit_size: 1 + enum: APC + - name: ULPMEN + description: ULPMEN + bit_offset: 11 + bit_size: 1 + - name: UCPD_STDBY + description: UCPD_STDBY + bit_offset: 13 + bit_size: 1 + - name: UCPD_DBDIS + description: UCPD_DBDIS + bit_offset: 14 + bit_size: 1 +fieldset/CR4: + description: Power control register 4 + fields: + - name: WP1 + description: Wakeup pin WKUP1 polarity + bit_offset: 0 + bit_size: 1 + - name: WP2 + description: Wakeup pin WKUP2 polarity + bit_offset: 1 + bit_size: 1 + - name: WP3 + description: Wakeup pin WKUP3 polarity + bit_offset: 2 + bit_size: 1 + - name: WP4 + description: Wakeup pin WKUP4 polarity + bit_offset: 3 + bit_size: 1 + - name: WP5 + description: Wakeup pin WKUP5 polarity + bit_offset: 4 + bit_size: 1 + - name: VBE + description: VBAT battery charging enable + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT battery charging resistor selection + bit_offset: 9 + bit_size: 1 + - name: SMPSBYP + description: SMPSBYP + bit_offset: 12 + bit_size: 1 + - name: EXTSMPSEN + description: EXTSMPSEN + bit_offset: 13 + bit_size: 1 + - name: SMPSFSTEN + description: SMPSFSTEN + bit_offset: 14 + bit_size: 1 + - name: SMPSLPEN + description: SMPSLPEN + bit_offset: 15 + bit_size: 1 +fieldset/PCR: + description: Power Port pull control register + fields: + - name: P + description: Port pull bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 +fieldset/PRIVCFGR: + description: Power privilege configuration register + fields: + - name: PRIV + description: PRIV + bit_offset: 0 + bit_size: 1 +fieldset/SCR: + description: Power status clear register + fields: + - name: CWUF + description: Clear wakeup flag + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + enum_write: CWUFW + - name: SBF + description: Clear standby flag + bit_offset: 8 + bit_size: 1 +fieldset/SECCFGR: + description: Power secure configuration register + fields: + - name: WUP1SEC + description: WKUP1 pin security + bit_offset: 0 + bit_size: 1 + - name: WUP2SEC + description: WKUP2 pin security + bit_offset: 1 + bit_size: 1 + - name: WUP3SEC + description: WKUP3 pin security + bit_offset: 2 + bit_size: 1 + - name: WUP4SEC + description: WKUP4 pin security + bit_offset: 3 + bit_size: 1 + - name: WUP5SEC + description: WKUP5 pin security + bit_offset: 4 + bit_size: 1 + - name: LPMSEC + description: LPMSEC + bit_offset: 8 + bit_size: 1 + - name: VDMSEC + description: VDMSEC + bit_offset: 9 + bit_size: 1 + - name: VBSEC + description: VBSEC + bit_offset: 10 + bit_size: 1 + - name: APCSEC + description: APCSEC + bit_offset: 11 + bit_size: 1 +fieldset/SR1: + description: Power status register 1 + fields: + - name: CWUF1 + description: Wakeup flag 1 + bit_offset: 0 + bit_size: 1 + - name: CWUF2 + description: Wakeup flag 2 + bit_offset: 1 + bit_size: 1 + - name: CWUF3 + description: Wakeup flag 3 + bit_offset: 2 + bit_size: 1 + - name: CWUF4 + description: Wakeup flag 4 + bit_offset: 3 + bit_size: 1 + - name: CWUF5 + description: Wakeup flag 5 + bit_offset: 4 + bit_size: 1 + - name: CSBF + description: Standby flag + bit_offset: 8 + bit_size: 1 + - name: WUFI + description: Wakeup flag internal + bit_offset: 15 + bit_size: 1 +fieldset/SR2: + description: Power status register 2 + fields: + - name: REGLPS + description: Low-power regulator started + bit_offset: 8 + bit_size: 1 + - name: REGLPF + description: Low-power regulator flag + bit_offset: 9 + bit_size: 1 + - name: VOSF + description: Voltage scaling flag + bit_offset: 10 + bit_size: 1 + - name: PVDO + description: Power voltage detector output + bit_offset: 11 + bit_size: 1 + - name: PVMO1 + description: "Peripheral voltage monitoring output: VDDUSB vs. 1.2 V" + bit_offset: 12 + bit_size: 1 + - name: PVMO2 + description: "Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V" + bit_offset: 13 + bit_size: 1 + - name: PVMO3 + description: "Peripheral voltage monitoring output: VDDA vs. 1.62 V" + bit_offset: 14 + bit_size: 1 + - name: PVMO4 + description: "Peripheral voltage monitoring output: VDDA vs. 2.2 V" + bit_offset: 15 + bit_size: 1 +enum/APC: + bit_size: 1 + variants: + - name: Disabled + description: PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os + value: 0 + - name: Enabled + description: I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied + value: 1 +enum/CWUFW: + bit_size: 1 + variants: + - name: Clear + description: Setting this bit clears the WUF flag in the PWR_SR1 register. This bit is always read as 0. + value: 1 +enum/DBP: + bit_size: 1 + variants: + - name: Disabled + description: Access to RTC and backup registers disabled + value: 0 + - name: Enabled + description: Access to RTC and backup registers enabled + value: 1 +enum/EWUP: + bit_size: 1 + variants: + - name: Disabled + description: WKUP pin x is used for general purpose I/Os. An event on the WKUP pin x does not wakeup the device from Standby mode + value: 0 + - name: Enabled + description: WKUP pin x is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin x wakes-up the system from Standby mode) + value: 1 +enum/IOSV: + bit_size: 1 + variants: + - name: Invalid + description: VDDIO2 is not present. Logical and electrical isolation is applied to ignore this supply + value: 0 + - name: Valid + description: VDDIO2 is valid + value: 1 +enum/LPMS: + bit_size: 3 + variants: + - name: Stop0 + description: Stop 0 mode + value: 0 + - name: Stop1 + description: Stop 1 mode + value: 1 + - name: Stop2 + description: Stop 2 mode + value: 2 + - name: Standby + description: Standby mode + value: 3 + - name: Shutdown + description: Shutdown mode + value: 4 +enum/LPR: + bit_size: 1 + variants: + - name: MainMode + description: Voltage regulator in Main mode + value: 0 + - name: LowPowerMode + description: Voltage regulator in low-power mode + value: 1 +enum/PLS: + bit_size: 3 + variants: + - name: V2_0 + description: 2.0V + value: 0 + - name: V2_2 + description: 2.2V + value: 1 + - name: V2_4 + description: 2.4V + value: 2 + - name: V2_5 + description: 2.5V + value: 3 + - name: V2_6 + description: 2.6V + value: 4 + - name: V2_8 + description: 2.8V + value: 5 + - name: V2_9 + description: 2.9V + value: 6 + - name: External + description: External input analog voltage PVD_IN (compared internally to VREFINT) + value: 7 +enum/PVDE: + bit_size: 1 + variants: + - name: Disabled + description: PVD Disabled + value: 0 + - name: Enabled + description: PVD Enabled + value: 1 +enum/PVME: + bit_size: 1 + variants: + - name: Disabled + description: Peripheral voltage monitoring disable + value: 0 + - name: Enabled + description: Peripheral voltage monitoring enable + value: 1 +enum/RRS: + bit_size: 2 + variants: + - name: PowerOff + description: SRAM2 powered off in Standby mode (SRAM2 content lost) + value: 0 + - name: OnLPR + description: SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept) + value: 1 + - name: OnLPRTop4kb + description: Only the upper 4 Kbytes of SRAM2 are powered by the low-power regulator in Standby mode (upper 4 Kbytes of SRAM2 content 0x2003 F000 - 0x2003 FFFF is kept). + value: 2 +enum/USV: + bit_size: 1 + variants: + - name: Invalid + description: VDDUSB is not present. Logical and electrical isolation is applied to ignore this supply + value: 0 + - name: Valid + description: VDDUSB is valid + value: 1 +enum/VOS: + bit_size: 2 + variants: + - name: Range1 + description: Range 1 + value: 1 + - name: Range2 + description: Range 2 + value: 2 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 0e77029..0e5a878 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -213,6 +213,7 @@ perimap = [ ('STM32F7.*:PWR:.*', ('pwr', 'f7', 'PWR')), ('STM32L1.*:PWR:.*', ('pwr', 'l1', 'PWR')), ('STM32L4.*:PWR:.*', ('pwr', 'l4', 'PWR')), + ('STM32L5.*:PWR:.*', ('pwr', 'l5', 'PWR')), ('STM32U5.*:PWR:.*', ('pwr', 'u5', 'PWR')), ('STM32WL.*:PWR:.*', ('pwr', 'wl5', 'PWR')), ('STM32WB.*:PWR:.*', ('pwr', 'wb55', 'PWR')), From 670f270c0a265c03613d632a995d39e3bff40d53 Mon Sep 17 00:00:00 2001 From: David Lenfesty Date: Thu, 21 Apr 2022 17:04:59 -0600 Subject: [PATCH 12/35] add xmltodict requirement to README --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index e403ad9..d9efcd5 100644 --- a/README.md +++ b/README.md @@ -47,6 +47,7 @@ In order to run the generator, you will need to install the following tools: * `git` * `jq` * `svd` – `pip3 install svdtools` +* `xmltodict` - `pip3 install xmltodict` ## Generating the YAMLs From a0368410a5fc24f1bd291c7b2235183fa30403c6 Mon Sep 17 00:00:00 2001 From: David Lenfesty Date: Thu, 21 Apr 2022 17:05:23 -0600 Subject: [PATCH 13/35] Add STM32F107 ethernet v1a peripheral --- data/registers/eth_v1a.yaml | 2142 +++++++++++++++++++++++++++++++++++ stm32data/__main__.py | 1 + 2 files changed, 2143 insertions(+) create mode 100644 data/registers/eth_v1a.yaml diff --git a/data/registers/eth_v1a.yaml b/data/registers/eth_v1a.yaml new file mode 100644 index 0000000..7f19043 --- /dev/null +++ b/data/registers/eth_v1a.yaml @@ -0,0 +1,2142 @@ +--- +block/ETH: + description: Ethernet Peripheral + items: + - name: ETHERNET_MAC + description: "Ethernet: media access control (MAC)" + byte_offset: 0 + block: ETHERNET_MAC + - name: ETHERNET_PTP + description: "Ethernet: Precision Time Protocol (PTP)" + byte_offset: 1792 + block: ETHERNET_PTP + - name: ETHERNET_DMA + description: "Ethernet: DMA mode register (DMA)" + byte_offset: 4096 + block: ETHERNET_DMA +block/ETHERNET_DMA: + description: "Ethernet: DMA controller operation" + items: + - name: DMABMR + description: Ethernet DMA bus mode register + byte_offset: 0 + fieldset: DMABMR + - name: DMATPDR + description: Ethernet DMA transmit poll demand register + byte_offset: 4 + fieldset: DMATPDR + - name: DMARPDR + description: EHERNET DMA receive poll demand register + byte_offset: 8 + fieldset: DMARPDR + - name: DMARDLAR + description: Ethernet DMA receive descriptor list address register + byte_offset: 12 + fieldset: DMARDLAR + - name: DMATDLAR + description: Ethernet DMA transmit descriptor list address register + byte_offset: 16 + fieldset: DMATDLAR + - name: DMASR + description: Ethernet DMA status register + byte_offset: 20 + fieldset: DMASR + - name: DMAOMR + description: Ethernet DMA operation mode register + byte_offset: 24 + fieldset: DMAOMR + - name: DMAIER + description: Ethernet DMA interrupt enable register + byte_offset: 28 + fieldset: DMAIER + - name: DMAMFBOCR + description: Ethernet DMA missed frame and buffer overflow counter register + byte_offset: 32 + fieldset: DMAMFBOCR + - name: DMACHTDR + description: Ethernet DMA current host transmit descriptor register + byte_offset: 72 + access: Read + fieldset: DMACHTDR + - name: DMACHRDR + description: Ethernet DMA current host receive descriptor register + byte_offset: 76 + access: Read + fieldset: DMACHRDR + - name: DMACHTBAR + description: Ethernet DMA current host transmit buffer address register + byte_offset: 80 + access: Read + fieldset: DMACHTBAR + - name: DMACHRBAR + description: Ethernet DMA current host receive buffer address register + byte_offset: 84 + access: Read + fieldset: DMACHRBAR +block/ETHERNET_MAC: + description: "Ethernet: media access control (MAC)" + items: + - name: MACCR + description: Ethernet MAC configuration register + byte_offset: 0 + fieldset: MACCR + - name: MACFFR + description: Ethernet MAC frame filter register + byte_offset: 4 + fieldset: MACFFR + - name: MACHTHR + description: Ethernet MAC hash table high register + byte_offset: 8 + fieldset: MACHTHR + - name: MACHTLR + description: Ethernet MAC hash table low register + byte_offset: 12 + fieldset: MACHTLR + - name: MACMIIAR + description: Ethernet MAC MII address register + byte_offset: 16 + fieldset: MACMIIAR + - name: MACMIIDR + description: Ethernet MAC MII data register + byte_offset: 20 + fieldset: MACMIIDR + - name: MACFCR + description: Ethernet MAC flow control register + byte_offset: 24 + fieldset: MACFCR + - name: MACVLANTR + description: Ethernet MAC VLAN tag register + byte_offset: 28 + fieldset: MACVLANTR + - name: MACRWUFFR + description: Ethernet MAC remote wakeup frame filter register + byte_offset: 40 + - name: MACPMTCSR + description: Ethernet MAC PMT control and status register + byte_offset: 44 + fieldset: MACPMTCSR + - name: MACDBGR + description: Ethernet MAC debug register + byte_offset: 52 + access: Read + fieldset: MACDBGR + - name: MACSR + description: Ethernet MAC interrupt status register + byte_offset: 56 + fieldset: MACSR + - name: MACIMR + description: Ethernet MAC interrupt mask register + byte_offset: 60 + fieldset: MACIMR + - name: MACA0HR + description: Ethernet MAC address 0 high register + byte_offset: 64 + fieldset: MACA0HR + - name: MACA0LR + description: Ethernet MAC address 0 low register + byte_offset: 68 + fieldset: MACA0LR + - name: MACA1HR + description: Ethernet MAC address 1 high register + byte_offset: 72 + fieldset: MACA1HR + - name: MACA1LR + description: Ethernet MAC address1 low register + byte_offset: 76 + fieldset: MACA1LR + - name: MACA2HR + description: Ethernet MAC address 2 high register + byte_offset: 80 + fieldset: MACA2HR + - name: MACA2LR + description: Ethernet MAC address 2 low register + byte_offset: 84 + fieldset: MACA2LR + - name: MACA3HR + description: Ethernet MAC address 3 high register + byte_offset: 88 + fieldset: MACA3HR + - name: MACA3LR + description: Ethernet MAC address 3 low register + byte_offset: 92 + fieldset: MACA3LR + - name: MMCCR + description: Ethernet MMC control register + byte_offset: 256 + fieldset: MMCCR + - name: MMCRIR + description: Ethernet MMC receive interrupt register + byte_offset: 260 + fieldset: MMCRIR + - name: MMCTIR + description: Ethernet MMC transmit interrupt register + byte_offset: 264 + access: Read + fieldset: MMCTIR + - name: MMCRIMR + description: Ethernet MMC receive interrupt mask register + byte_offset: 268 + fieldset: MMCRIMR + - name: MMCTIMR + description: Ethernet MMC transmit interrupt mask register + byte_offset: 272 + fieldset: MMCTIMR + - name: MMCTGFSCCR + description: Ethernet MMC transmitted good frames after a single collision counter + byte_offset: 332 + access: Read + fieldset: MMCTGFSCCR + - name: MMCTGFMSCCR + description: Ethernet MMC transmitted good frames after more than a single collision + byte_offset: 336 + access: Read + fieldset: MMCTGFMSCCR + - name: MMCTGFCR + description: Ethernet MMC transmitted good frames counter register + byte_offset: 360 + access: Read + fieldset: MMCTGFCR + - name: MMCRFCECR + description: Ethernet MMC received frames with CRC error counter register + byte_offset: 404 + access: Read + fieldset: MMCRFCECR + - name: MMCRFAECR + description: Ethernet MMC received frames with alignment error counter register + byte_offset: 408 + access: Read + fieldset: MMCRFAECR + - name: MMCRGUFCR + description: MMC received good unicast frames counter register + byte_offset: 452 + access: Read + fieldset: MMCRGUFCR +block/ETHERNET_PTP: + description: "Ethernet: Precision time protocol" + items: + - name: PTPTSCR + description: Ethernet PTP time stamp control register + byte_offset: 0 + fieldset: PTPTSCR + - name: PTPSSIR + description: Ethernet PTP subsecond increment register + byte_offset: 4 + fieldset: PTPSSIR + - name: PTPTSHR + description: Ethernet PTP time stamp high register + byte_offset: 8 + access: Read + fieldset: PTPTSHR + - name: PTPTSLR + description: Ethernet PTP time stamp low register + byte_offset: 12 + access: Read + fieldset: PTPTSLR + - name: PTPTSHUR + description: Ethernet PTP time stamp high update register + byte_offset: 16 + fieldset: PTPTSHUR + - name: PTPTSLUR + description: Ethernet PTP time stamp low update register + byte_offset: 20 + fieldset: PTPTSLUR + - name: PTPTSAR + description: Ethernet PTP time stamp addend register + byte_offset: 24 + fieldset: PTPTSAR + - name: PTPTTHR + description: Ethernet PTP target time high register + byte_offset: 28 + fieldset: PTPTTHR + - name: PTPTTLR + description: Ethernet PTP target time low register + byte_offset: 32 + fieldset: PTPTTLR + - name: PTPTSSR + description: Ethernet PTP time stamp status register + byte_offset: 40 + access: Read + fieldset: PTPTSSR + - name: PTPPPSCR + description: Ethernet PTP PPS control register + byte_offset: 44 + access: Read + fieldset: PTPPPSCR +fieldset/DMABMR: + description: Ethernet DMA bus mode register + fields: + - name: SR + description: Software reset + bit_offset: 0 + bit_size: 1 + - name: DA + description: DMA arbitration + bit_offset: 1 + bit_size: 1 + enum: DA + - name: DSL + description: Descriptor skip length + bit_offset: 2 + bit_size: 5 + - name: PBL + description: Programmable burst length + bit_offset: 8 + bit_size: 6 + enum: PBL + - name: PM + description: Rx-Tx priority ratio + bit_offset: 14 + bit_size: 2 + enum: PriorityRxOverTx + - name: FB + description: Fixed burst + bit_offset: 16 + bit_size: 1 + enum: FB + - name: RDP + description: Rx DMA PBL + bit_offset: 17 + bit_size: 6 + enum: RDP + - name: USP + description: Use separate PBL + bit_offset: 23 + bit_size: 1 + enum: USP + - name: FPM + description: 4xPBL mode + bit_offset: 24 + bit_size: 1 + enum: FPM + - name: AAB + description: Address-aligned beats + bit_offset: 25 + bit_size: 1 + enum: AAB +fieldset/DMACHRBAR: + description: Ethernet DMA current host receive buffer address register + fields: + - name: HRBAP + description: Host receive buffer address pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACHRDR: + description: Ethernet DMA current host receive descriptor register + fields: + - name: HRDAP + description: Host receive descriptor address pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACHTBAR: + description: Ethernet DMA current host transmit buffer address register + fields: + - name: HTBAP + description: Host transmit buffer address pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACHTDR: + description: Ethernet DMA current host transmit descriptor register + fields: + - name: HTDAP + description: Host transmit descriptor address pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMAIER: + description: Ethernet DMA interrupt enable register + fields: + - name: TIE + description: Transmit interrupt enable + bit_offset: 0 + bit_size: 1 + - name: TPSIE + description: Transmit process stopped interrupt enable + bit_offset: 1 + bit_size: 1 + - name: TBUIE + description: Transmit buffer unavailable interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TJTIE + description: Transmit jabber timeout interrupt enable + bit_offset: 3 + bit_size: 1 + - name: ROIE + description: Receive overflow interrupt enable + bit_offset: 4 + bit_size: 1 + - name: TUIE + description: Transmit underflow interrupt enable + bit_offset: 5 + bit_size: 1 + - name: RIE + description: Receive interrupt enable + bit_offset: 6 + bit_size: 1 + - name: RBUIE + description: Receive buffer unavailable interrupt enable + bit_offset: 7 + bit_size: 1 + - name: RPSIE + description: Receive process stopped interrupt enable + bit_offset: 8 + bit_size: 1 + - name: RWTIE + description: Receive watchdog timeout interrupt enable + bit_offset: 9 + bit_size: 1 + - name: ETIE + description: Early transmit interrupt enable + bit_offset: 10 + bit_size: 1 + - name: FBEIE + description: Fatal bus error interrupt enable + bit_offset: 13 + bit_size: 1 + - name: ERIE + description: Early receive interrupt enable + bit_offset: 14 + bit_size: 1 + - name: AISE + description: Abnormal interrupt summary enable + bit_offset: 15 + bit_size: 1 + - name: NISE + description: Normal interrupt summary enable + bit_offset: 16 + bit_size: 1 +fieldset/DMAMFBOCR: + description: Ethernet DMA missed frame and buffer overflow counter register + fields: + - name: MFC + description: Missed frames by the controller + bit_offset: 0 + bit_size: 16 + - name: OMFC + description: Overflow bit for missed frame counter + bit_offset: 16 + bit_size: 1 + - name: MFA + description: Missed frames by the application + bit_offset: 17 + bit_size: 11 + - name: OFOC + description: Overflow bit for FIFO overflow counter + bit_offset: 28 + bit_size: 1 +fieldset/DMAOMR: + description: Ethernet DMA operation mode register + fields: + - name: SR + description: Start/stop receive + bit_offset: 1 + bit_size: 1 + enum: DMAOMR_SR + - name: OSF + description: Operate on second frame + bit_offset: 2 + bit_size: 1 + - name: RTC + description: Receive threshold control + bit_offset: 3 + bit_size: 2 + enum: RTC + - name: FUGF + description: Forward undersized good frames + bit_offset: 6 + bit_size: 1 + enum: FUGF + - name: FEF + description: Forward error frames + bit_offset: 7 + bit_size: 1 + enum: FEF + - name: ST + description: Start/stop transmission + bit_offset: 13 + bit_size: 1 + enum: ST + - name: TTC + description: Transmit threshold control + bit_offset: 14 + bit_size: 3 + enum: TTC + - name: FTF + description: Flush transmit FIFO + bit_offset: 20 + bit_size: 1 + enum: FTF + - name: TSF + description: Transmit store and forward + bit_offset: 21 + bit_size: 1 + enum: TSF + - name: DFRF + description: Disable flushing of received frames + bit_offset: 24 + bit_size: 1 + - name: RSF + description: Receive store and forward + bit_offset: 25 + bit_size: 1 + enum: RSF + - name: DTCEFD + description: Dropping of TCP/IP checksum error frames disable + bit_offset: 26 + bit_size: 1 + enum: DTCEFD +fieldset/DMARDLAR: + description: Ethernet DMA receive descriptor list address register + fields: + - name: SRL + description: Start of receive list + bit_offset: 0 + bit_size: 32 +fieldset/DMARPDR: + description: EHERNET DMA receive poll demand register + fields: + - name: RPD + description: Receive poll demand + bit_offset: 0 + bit_size: 32 + enum: RPD +fieldset/DMASR: + description: Ethernet DMA status register + fields: + - name: TS + description: Transmit status + bit_offset: 0 + bit_size: 1 + - name: TPSS + description: Transmit process stopped status + bit_offset: 1 + bit_size: 1 + - name: TBUS + description: Transmit buffer unavailable status + bit_offset: 2 + bit_size: 1 + - name: TJTS + description: Transmit jabber timeout status + bit_offset: 3 + bit_size: 1 + - name: ROS + description: Receive overflow status + bit_offset: 4 + bit_size: 1 + - name: TUS + description: Transmit underflow status + bit_offset: 5 + bit_size: 1 + - name: RS + description: Receive status + bit_offset: 6 + bit_size: 1 + - name: RBUS + description: Receive buffer unavailable status + bit_offset: 7 + bit_size: 1 + - name: RPSS + description: Receive process stopped status + bit_offset: 8 + bit_size: 1 + - name: PWTS + description: PWTS + bit_offset: 9 + bit_size: 1 + - name: ETS + description: Early transmit status + bit_offset: 10 + bit_size: 1 + - name: FBES + description: Fatal bus error status + bit_offset: 13 + bit_size: 1 + - name: ERS + description: Early receive status + bit_offset: 14 + bit_size: 1 + - name: AIS + description: Abnormal interrupt summary + bit_offset: 15 + bit_size: 1 + - name: NIS + description: Normal interrupt summary + bit_offset: 16 + bit_size: 1 + - name: RPS + description: Receive process state + bit_offset: 17 + bit_size: 3 + enum: RPS + - name: TPS + description: Transmit process state + bit_offset: 20 + bit_size: 3 + enum: TPS + - name: EBS + description: Error bits status + bit_offset: 23 + bit_size: 3 + - name: MMCS + description: MMC status + bit_offset: 27 + bit_size: 1 + - name: PMTS + description: PMT status + bit_offset: 28 + bit_size: 1 + - name: TSTS + description: Time stamp trigger status + bit_offset: 29 + bit_size: 1 +fieldset/DMATDLAR: + description: Ethernet DMA transmit descriptor list address register + fields: + - name: STL + description: Start of transmit list + bit_offset: 0 + bit_size: 32 +fieldset/DMATPDR: + description: Ethernet DMA transmit poll demand register + fields: + - name: TPD + description: Transmit poll demand + bit_offset: 0 + bit_size: 32 + enum: TPD +fieldset/MACA0HR: + description: Ethernet MAC address 0 high register + fields: + - name: MACA0H + description: MAC address0 high + bit_offset: 0 + bit_size: 16 + - name: MO + description: Always 1 + bit_offset: 31 + bit_size: 1 +fieldset/MACA0LR: + description: Ethernet MAC address 0 low register + fields: + - name: MACA0L + description: "0" + bit_offset: 0 + bit_size: 32 +fieldset/MACA1HR: + description: Ethernet MAC address 1 high register + fields: + - name: MACA1H + description: MACA1H + bit_offset: 0 + bit_size: 16 + - name: MBC + description: MBC + bit_offset: 24 + bit_size: 6 + - name: SA + description: SA + bit_offset: 30 + bit_size: 1 + enum: MACAHR_SA + - name: AE + description: AE + bit_offset: 31 + bit_size: 1 + enum: MACAHR_AE +fieldset/MACA1LR: + description: Ethernet MAC address1 low register + fields: + - name: MACA1L + description: MACA1LR + bit_offset: 0 + bit_size: 32 +fieldset/MACA2HR: + description: Ethernet MAC address 2 high register + fields: + - name: MACA2H + description: MAC2AH + bit_offset: 0 + bit_size: 16 + - name: MBC + description: MBC + bit_offset: 24 + bit_size: 6 + - name: SA + description: SA + bit_offset: 30 + bit_size: 1 + enum: MACAHR_SA + - name: AE + description: AE + bit_offset: 31 + bit_size: 1 + enum: MACAHR_AE +fieldset/MACA2LR: + description: Ethernet MAC address 2 low register + fields: + - name: MACA2L + description: MACA2L + bit_offset: 0 + bit_size: 32 +fieldset/MACA3HR: + description: Ethernet MAC address 3 high register + fields: + - name: MACA3H + description: MACA3H + bit_offset: 0 + bit_size: 16 + - name: MBC + description: MBC + bit_offset: 24 + bit_size: 6 + - name: SA + description: SA + bit_offset: 30 + bit_size: 1 + enum: MACAHR_SA + - name: AE + description: AE + bit_offset: 31 + bit_size: 1 + enum: MACAHR_AE +fieldset/MACA3LR: + description: Ethernet MAC address 3 low register + fields: + - name: MACA3L + description: MBCA3L + bit_offset: 0 + bit_size: 32 +fieldset/MACCR: + description: Ethernet MAC configuration register + fields: + - name: RE + description: Receiver enable + bit_offset: 2 + bit_size: 1 + - name: TE + description: Transmitter enable + bit_offset: 3 + bit_size: 1 + - name: DC + description: Deferral check + bit_offset: 4 + bit_size: 1 + enum: DC + - name: BL + description: Back-off limit + bit_offset: 5 + bit_size: 2 + enum: BL + - name: APCS + description: Automatic pad/CRC stripping + bit_offset: 7 + bit_size: 1 + enum: APCS + - name: RD + description: Retry disable + bit_offset: 9 + bit_size: 1 + enum: RD + - name: IPCO + description: IPv4 checksum offload + bit_offset: 10 + bit_size: 1 + enum: IPCO + - name: DM + description: Duplex mode + bit_offset: 11 + bit_size: 1 + enum: DM + - name: LM + description: Loopback mode + bit_offset: 12 + bit_size: 1 + enum: LM + - name: ROD + description: Receive own disable + bit_offset: 13 + bit_size: 1 + enum: ROD + - name: FES + description: Fast Ethernet speed + bit_offset: 14 + bit_size: 1 + enum: FES + - name: CSD + description: Carrier sense disable + bit_offset: 16 + bit_size: 1 + enum: CSD + - name: IFG + description: Interframe gap + bit_offset: 17 + bit_size: 3 + enum: IFG + - name: JD + description: Jabber disable + bit_offset: 22 + bit_size: 1 + enum: JD + - name: WD + description: Watchdog disable + bit_offset: 23 + bit_size: 1 + enum: WD +fieldset/MACDBGR: + description: Ethernet MAC debug register + fields: + - name: MMRPEA + description: MAC MII receive protocol engine active + bit_offset: 0 + bit_size: 1 + - name: MSFRWCS + description: MAC small FIFO read/write controllers status + bit_offset: 1 + bit_size: 2 + - name: RFWRA + description: Rx FIFO write controller active + bit_offset: 4 + bit_size: 1 + - name: RFRCS + description: Rx FIFO read controller status + bit_offset: 5 + bit_size: 2 + - name: RFFL + description: Rx FIFO fill level + bit_offset: 8 + bit_size: 2 + - name: MMTEA + description: MAC MII transmit engine active + bit_offset: 16 + bit_size: 1 + - name: MTFCS + description: MAC transmit frame controller status + bit_offset: 17 + bit_size: 2 + - name: MTP + description: MAC transmitter in pause + bit_offset: 19 + bit_size: 1 + - name: TFRS + description: Tx FIFO read status + bit_offset: 20 + bit_size: 2 + - name: TFWA + description: Tx FIFO write active + bit_offset: 22 + bit_size: 1 + - name: TFNE + description: Tx FIFO not empty + bit_offset: 24 + bit_size: 1 + - name: TFF + description: Tx FIFO full + bit_offset: 25 + bit_size: 1 +fieldset/MACFCR: + description: Ethernet MAC flow control register + fields: + - name: FCB + description: Flow control busy/back pressure activate + bit_offset: 0 + bit_size: 1 + enum: FCB + - name: TFCE + description: Transmit flow control enable + bit_offset: 1 + bit_size: 1 + enum: TFCE + - name: RFCE + description: Receive flow control enable + bit_offset: 2 + bit_size: 1 + enum: RFCE + - name: UPFD + description: Unicast pause frame detect + bit_offset: 3 + bit_size: 1 + enum: UPFD + - name: PLT + description: Pause low threshold + bit_offset: 4 + bit_size: 2 + enum: PLT + - name: ZQPD + description: Zero-quanta pause disable + bit_offset: 7 + bit_size: 1 + enum: ZQPD + - name: PT + description: Pause time + bit_offset: 16 + bit_size: 16 +fieldset/MACFFR: + description: Ethernet MAC frame filter register + fields: + - name: PM + description: Promiscuous mode + bit_offset: 0 + bit_size: 1 + enum: PM + - name: HU + description: Hash unicast + bit_offset: 1 + bit_size: 1 + enum: HU + - name: HM + description: Hash multicast + bit_offset: 2 + bit_size: 1 + enum: HM + - name: DAIF + description: Destination address unique filtering + bit_offset: 3 + bit_size: 1 + enum: DAIF + - name: PAM + description: Pass all multicast + bit_offset: 4 + bit_size: 1 + enum: PAM + - name: BFD + description: Broadcast frames disable + bit_offset: 5 + bit_size: 1 + enum: BFD + - name: PCF + description: Pass control frames + bit_offset: 6 + bit_size: 2 + enum: PCF + - name: SAIF + description: Source address inverse filtering + bit_offset: 7 + bit_size: 1 + enum: SAIF + - name: SAF + description: Source address filter + bit_offset: 8 + bit_size: 1 + enum: SAF + - name: HPF + description: Hash or perfect filter + bit_offset: 9 + bit_size: 1 + enum: HPF + - name: RA + description: Receive all + bit_offset: 31 + bit_size: 1 + enum: RA +fieldset/MACHTHR: + description: Ethernet MAC hash table high register + fields: + - name: HTH + description: Upper 32 bits of hash table + bit_offset: 0 + bit_size: 32 +fieldset/MACHTLR: + description: Ethernet MAC hash table low register + fields: + - name: HTL + description: Lower 32 bits of hash table + bit_offset: 0 + bit_size: 32 +fieldset/MACIMR: + description: Ethernet MAC interrupt mask register + fields: + - name: PMTIM + description: PMT interrupt mask + bit_offset: 3 + bit_size: 1 + enum: PMTIM + - name: TSTIM + description: Time stamp trigger interrupt mask + bit_offset: 9 + bit_size: 1 + enum: TSTIM +fieldset/MACMIIAR: + description: Ethernet MAC MII address register + fields: + - name: MB + description: MII busy + bit_offset: 0 + bit_size: 1 + enum: MB_progress + - name: MW + description: MII write + bit_offset: 1 + bit_size: 1 + enum: MW + - name: CR + description: Clock range + bit_offset: 2 + bit_size: 3 + enum: CR + - name: MR + description: MII register - select the desired MII register in the PHY device + bit_offset: 6 + bit_size: 5 + - name: PA + description: PHY address - select which of possible 32 PHYs is being accessed + bit_offset: 11 + bit_size: 5 +fieldset/MACMIIDR: + description: Ethernet MAC MII data register + fields: + - name: MD + description: MII data read from/written to the PHY + bit_offset: 0 + bit_size: 16 +fieldset/MACPMTCSR: + description: Ethernet MAC PMT control and status register + fields: + - name: PD + description: Power down + bit_offset: 0 + bit_size: 1 + enum: PD + - name: MPE + description: Magic packet enable + bit_offset: 1 + bit_size: 1 + enum: MPE + - name: WFE + description: Wakeup frame enable + bit_offset: 2 + bit_size: 1 + enum: WFE + - name: MPR + description: Magic packet received + bit_offset: 5 + bit_size: 1 + - name: WFR + description: Wakeup frame received + bit_offset: 6 + bit_size: 1 + - name: GU + description: Global unicast + bit_offset: 9 + bit_size: 1 + enum: GU + - name: WFFRPR + description: Wakeup frame filter register pointer reset + bit_offset: 31 + bit_size: 1 + enum: WFFRPR +fieldset/MACSR: + description: Ethernet MAC interrupt status register + fields: + - name: PMTS + description: PMT status + bit_offset: 3 + bit_size: 1 + - name: MMCS + description: MMC status + bit_offset: 4 + bit_size: 1 + - name: MMCRS + description: MMC receive status + bit_offset: 5 + bit_size: 1 + - name: MMCTS + description: MMC transmit status + bit_offset: 6 + bit_size: 1 + - name: TSTS + description: Time stamp trigger status + bit_offset: 9 + bit_size: 1 +fieldset/MACVLANTR: + description: Ethernet MAC VLAN tag register + fields: + - name: VLANTI + description: VLAN tag identifier (for receive frames) + bit_offset: 0 + bit_size: 16 + - name: VLANTC + description: 12-bit VLAN tag comparison + bit_offset: 16 + bit_size: 1 + enum: VLANTC +fieldset/MMCCR: + description: Ethernet MMC control register + fields: + - name: CR + description: Counter reset + bit_offset: 0 + bit_size: 1 + enum: CounterReset + - name: CSR + description: Counter stop rollover + bit_offset: 1 + bit_size: 1 + enum: CSR + - name: ROR + description: Reset on read + bit_offset: 2 + bit_size: 1 + enum: ROR + - name: MCF + description: MMC counter freeze + bit_offset: 3 + bit_size: 1 + enum: MCF +fieldset/MMCRFAECR: + description: Ethernet MMC received frames with alignment error counter register + fields: + - name: RFAEC + description: RFAEC + bit_offset: 0 + bit_size: 32 +fieldset/MMCRFCECR: + description: Ethernet MMC received frames with CRC error counter register + fields: + - name: RFCFC + description: RFCFC + bit_offset: 0 + bit_size: 32 +fieldset/MMCRGUFCR: + description: MMC received good unicast frames counter register + fields: + - name: RGUFC + description: RGUFC + bit_offset: 0 + bit_size: 32 +fieldset/MMCRIMR: + description: Ethernet MMC receive interrupt mask register + fields: + - name: RFCEM + description: Received frame CRC error mask + bit_offset: 5 + bit_size: 1 + enum: RFCEM + - name: RFAEM + description: Received frames alignment error mask + bit_offset: 6 + bit_size: 1 + enum: RFAEM + - name: RGUFM + description: Received good Unicast frames mask + bit_offset: 17 + bit_size: 1 + enum: RGUFM +fieldset/MMCRIR: + description: Ethernet MMC receive interrupt register + fields: + - name: RFCES + description: Received frames CRC error status + bit_offset: 5 + bit_size: 1 + - name: RFAES + description: Received frames alignment error status + bit_offset: 6 + bit_size: 1 + - name: RGUFS + description: Received good Unicast frames status + bit_offset: 17 + bit_size: 1 +fieldset/MMCTGFCR: + description: Ethernet MMC transmitted good frames counter register + fields: + - name: TGFC + description: HTL + bit_offset: 0 + bit_size: 32 +fieldset/MMCTGFMSCCR: + description: Ethernet MMC transmitted good frames after more than a single collision + fields: + - name: TGFMSCC + description: TGFMSCC + bit_offset: 0 + bit_size: 32 +fieldset/MMCTGFSCCR: + description: Ethernet MMC transmitted good frames after a single collision counter + fields: + - name: TGFSCC + description: Transmitted good frames single collision counter + bit_offset: 0 + bit_size: 32 +fieldset/MMCTIMR: + description: Ethernet MMC transmit interrupt mask register + fields: + - name: TGFSCM + description: Transmitted good frames single collision mask + bit_offset: 14 + bit_size: 1 + enum: TGFSCM + - name: TGFMSCM + description: Transmitted good frames more than single collision mask + bit_offset: 15 + bit_size: 1 + enum: TGFMSCM + - name: TGFM + description: Transmitted good frames mask + bit_offset: 16 + bit_size: 1 + enum: TGFM +fieldset/MMCTIR: + description: Ethernet MMC transmit interrupt register + fields: + - name: TGFSCS + description: Transmitted good frames single collision status + bit_offset: 14 + bit_size: 1 + - name: TGFMSCS + description: Transmitted good frames more than single collision status + bit_offset: 15 + bit_size: 1 + - name: TGFS + description: Transmitted good frames status + bit_offset: 21 + bit_size: 1 +fieldset/PTPPPSCR: + description: Ethernet PTP PPS control register + fields: + - name: TSSO + description: TSSO + bit_offset: 0 + bit_size: 1 + - name: TSTTR + description: TSTTR + bit_offset: 1 + bit_size: 1 +fieldset/PTPSSIR: + description: Ethernet PTP subsecond increment register + fields: + - name: STSSI + description: STSSI + bit_offset: 0 + bit_size: 8 +fieldset/PTPTSAR: + description: Ethernet PTP time stamp addend register + fields: + - name: TSA + description: TSA + bit_offset: 0 + bit_size: 32 +fieldset/PTPTSCR: + description: Ethernet PTP time stamp control register + fields: + - name: TSE + description: TSE + bit_offset: 0 + bit_size: 1 + - name: TSFCU + description: TSFCU + bit_offset: 1 + bit_size: 1 + - name: TSSTI + description: TSSTI + bit_offset: 2 + bit_size: 1 + - name: TSSTU + description: TSSTU + bit_offset: 3 + bit_size: 1 + - name: TSITE + description: TSITE + bit_offset: 4 + bit_size: 1 + - name: TTSARU + description: TTSARU + bit_offset: 5 + bit_size: 1 + - name: TSSARFE + description: TSSARFE + bit_offset: 8 + bit_size: 1 + - name: TSSSR + description: TSSSR + bit_offset: 9 + bit_size: 1 + - name: TSPTPPSV2E + description: TSPTPPSV2E + bit_offset: 10 + bit_size: 1 + - name: TSSPTPOEFE + description: TSSPTPOEFE + bit_offset: 11 + bit_size: 1 + - name: TSSIPV6FE + description: TSSIPV6FE + bit_offset: 12 + bit_size: 1 + - name: TSSIPV4FE + description: TSSIPV4FE + bit_offset: 13 + bit_size: 1 + - name: TSSEME + description: TSSEME + bit_offset: 14 + bit_size: 1 + - name: TSSMRME + description: TSSMRME + bit_offset: 15 + bit_size: 1 + - name: TSCNT + description: TSCNT + bit_offset: 16 + bit_size: 2 + - name: TSPFFMAE + description: TSPFFMAE + bit_offset: 18 + bit_size: 1 +fieldset/PTPTSHR: + description: Ethernet PTP time stamp high register + fields: + - name: STS + description: STS + bit_offset: 0 + bit_size: 32 +fieldset/PTPTSHUR: + description: Ethernet PTP time stamp high update register + fields: + - name: TSUS + description: TSUS + bit_offset: 0 + bit_size: 32 +fieldset/PTPTSLR: + description: Ethernet PTP time stamp low register + fields: + - name: STSS + description: STSS + bit_offset: 0 + bit_size: 31 + - name: STPNS + description: STPNS + bit_offset: 31 + bit_size: 1 +fieldset/PTPTSLUR: + description: Ethernet PTP time stamp low update register + fields: + - name: TSUSS + description: TSUSS + bit_offset: 0 + bit_size: 31 + - name: TSUPNS + description: TSUPNS + bit_offset: 31 + bit_size: 1 +fieldset/PTPTSSR: + description: Ethernet PTP time stamp status register + fields: + - name: TSSO + description: TSSO + bit_offset: 0 + bit_size: 1 + - name: TSTTR + description: TSSO + bit_offset: 1 + bit_size: 1 +fieldset/PTPTTHR: + description: Ethernet PTP target time high register + fields: + - name: TTSH + description: "0" + bit_offset: 0 + bit_size: 32 +fieldset/PTPTTLR: + description: Ethernet PTP target time low register + fields: + - name: TTSL + description: TTSL + bit_offset: 0 + bit_size: 32 +enum/AAB: + bit_size: 1 + variants: + - name: Unaligned + description: Bursts are not aligned + value: 0 + - name: Aligned + description: Align bursts to start address LS bits. First burst alignment depends on FB bit + value: 1 +enum/APCS: + bit_size: 1 + variants: + - name: Disabled + description: MAC passes all incoming frames unmodified + value: 0 + - name: Strip + description: MAC strips the Pad/FCS field on incoming frames only for lengths less than or equal to 1500 bytes + value: 1 +enum/BFD: + bit_size: 1 + variants: + - name: Enabled + description: Address filters pass all received broadcast frames + value: 0 + - name: Disabled + description: Address filters filter all incoming broadcast frames + value: 1 +enum/BL: + bit_size: 2 + variants: + - name: BL10 + description: "For retransmission n, wait up to 2^min(n, 10) time slots" + value: 0 + - name: BL8 + description: "For retransmission n, wait up to 2^min(n, 8) time slots" + value: 1 + - name: BL4 + description: "For retransmission n, wait up to 2^min(n, 4) time slots" + value: 2 + - name: BL1 + description: "For retransmission n, wait up to 2^min(n, 1) time slots" + value: 3 +enum/CR: + bit_size: 3 + variants: + - name: CR_60_100 + description: 60-100MHz HCLK/42 + value: 0 + - name: CR_100_150 + description: 100-150 MHz HCLK/62 + value: 1 + - name: CR_20_35 + description: 20-35MHz HCLK/16 + value: 2 + - name: CR_35_60 + description: 35-60MHz HCLK/16 + value: 3 + - name: CR_150_168 + description: 150-168MHz HCLK/102 + value: 4 +enum/CSD: + bit_size: 1 + variants: + - name: Enabled + description: Errors generated due to loss of carrier + value: 0 + - name: Disabled + description: No error generated due to loss of carrier + value: 1 +enum/CSR: + bit_size: 1 + variants: + - name: Disabled + description: Counters roll over to zero after reaching the maximum value + value: 0 + - name: Enabled + description: Counters do not roll over to zero after reaching the maximum value + value: 1 +enum/CounterReset: + bit_size: 1 + variants: + - name: Reset + description: Reset all counters. Cleared automatically + value: 1 +enum/DA: + bit_size: 1 + variants: + - name: RoundRobin + description: "Round-robin with Rx:Tx priority given by PM" + value: 0 + - name: RxPriority + description: Rx has priority over Tx + value: 1 +enum/DAIF: + bit_size: 1 + variants: + - name: Normal + description: Normal filtering of frames + value: 0 + - name: Invert + description: Address check block operates in inverse filtering mode for the DA address comparison + value: 1 +enum/DC: + bit_size: 1 + variants: + - name: Disabled + description: MAC defers until CRS signal goes inactive + value: 0 + - name: Enabled + description: Deferral check function enabled + value: 1 +enum/DM: + bit_size: 1 + variants: + - name: HalfDuplex + description: MAC operates in half-duplex mode + value: 0 + - name: FullDuplex + description: MAC operates in full-duplex mode + value: 1 +enum/DMABMR_SR: + bit_size: 1 + variants: + - name: Reset + description: Reset all MAC subsystem internal registers and logic. Cleared automatically + value: 1 +enum/DMAOMR_SR: + bit_size: 1 + variants: + - name: Stopped + description: Reception is stopped after transfer of the current frame + value: 0 + - name: Started + description: Reception is placed in the Running state + value: 1 +enum/DTCEFD: + bit_size: 1 + variants: + - name: Enabled + description: Drop frames with errors only in the receive checksum offload engine + value: 0 + - name: Disabled + description: Do not drop frames that only have errors in the receive checksum offload engine + value: 1 +enum/FB: + bit_size: 1 + variants: + - name: Variable + description: AHB uses SINGLE and INCR burst transfers + value: 0 + - name: Fixed + description: AHB uses only fixed burst transfers + value: 1 +enum/FCB: + bit_size: 1 + variants: + - name: DisableBackPressure + description: "In half duplex only, deasserts back pressure" + value: 0 + - name: PauseOrBackPressure + description: "In full duplex, initiate a Pause control frame. In half duplex, assert back pressure" + value: 1 +enum/FEF: + bit_size: 1 + variants: + - name: Drop + description: Rx FIFO drops frames with error status + value: 0 + - name: Forward + description: All frames except runt error frames are forwarded to the DMA + value: 1 +enum/FES: + bit_size: 1 + variants: + - name: FES10 + description: 10 Mbit/s + value: 0 + - name: FES100 + description: 100 Mbit/s + value: 1 +enum/FPM: + bit_size: 1 + variants: + - name: x1 + description: PBL values used as-is + value: 0 + - name: x4 + description: PBL values multiplied by 4 + value: 1 +enum/FTF: + bit_size: 1 + variants: + - name: Flush + description: Transmit FIFO controller logic is reset to its default values. Cleared automatically + value: 1 +enum/FUGF: + bit_size: 1 + variants: + - name: Drop + description: Rx FIFO drops all frames of less than 64 bytes + value: 0 + - name: Forward + description: Rx FIFO forwards undersized frames + value: 1 +enum/GU: + bit_size: 1 + variants: + - name: Disabled + description: Normal operation + value: 0 + - name: Enabled + description: Any unicast packet filtered by the MAC address recognition may be a wakeup frame + value: 1 +enum/HM: + bit_size: 1 + variants: + - name: Perfect + description: MAC performs a perfect destination address filtering for multicast frames + value: 0 + - name: Hash + description: MAC performs destination address filtering of received multicast frames according to the hash table + value: 1 +enum/HPF: + bit_size: 1 + variants: + - name: HashOnly + description: "If HM or HU is set, only frames that match the Hash filter are passed" + value: 0 + - name: HashOrPerfect + description: "If HM or HU is set, frames that match either the perfect filter or the hash filter are passed" + value: 1 +enum/HU: + bit_size: 1 + variants: + - name: Perfect + description: MAC performs a perfect destination address filtering for unicast frames + value: 0 + - name: Hash + description: MAC performs destination address filtering of received unicast frames according to the hash table + value: 1 +enum/IFG: + bit_size: 3 + variants: + - name: IFG96 + description: 96 bit times + value: 0 + - name: IFG88 + description: 88 bit times + value: 1 + - name: IFG80 + description: 80 bit times + value: 2 + - name: IFG72 + description: 72 bit times + value: 3 + - name: IFG64 + description: 64 bit times + value: 4 + - name: IFG56 + description: 56 bit times + value: 5 + - name: IFG48 + description: 48 bit times + value: 6 + - name: IFG40 + description: 40 bit times + value: 7 +enum/IPCO: + bit_size: 1 + variants: + - name: Disabled + description: IPv4 checksum offload disabled + value: 0 + - name: Offload + description: IPv4 checksums are checked in received frames + value: 1 +enum/JD: + bit_size: 1 + variants: + - name: Enabled + description: "Jabber enabled, transmit frames up to 2048 bytes" + value: 0 + - name: Disabled + description: "Jabber disabled, transmit frames up to 16384 bytes" + value: 1 +enum/LM: + bit_size: 1 + variants: + - name: Normal + description: Normal mode + value: 0 + - name: Loopback + description: MAC operates in loopback mode at the MII + value: 1 +enum/MACAHR_AE: + bit_size: 1 + variants: + - name: Disabled + description: Address filters ignore this address + value: 0 + - name: Enabled + description: Address filters use this address + value: 1 +enum/MACAHR_SA: + bit_size: 1 + variants: + - name: Destination + description: This address is used for comparison with DA fields of the received frame + value: 0 + - name: Source + description: This address is used for comparison with SA fields of received frames + value: 1 +enum/MB_progress: + bit_size: 1 + variants: + - name: Busy + description: This bit is set to 1 by the application to indicate that a read or write access is in progress + value: 1 +enum/MCF: + bit_size: 1 + variants: + - name: Unfrozen + description: All MMC counters update normally + value: 0 + - name: Frozen + description: All MMC counters frozen to their current value + value: 1 +enum/MPE: + bit_size: 1 + variants: + - name: Disabled + description: No power management event generated due to Magic Packet reception + value: 0 + - name: Enabled + description: Enable generation of a power management event due to Magic Packet reception + value: 1 +enum/MW: + bit_size: 1 + variants: + - name: Read + description: Read operation + value: 0 + - name: Write + description: Write operation + value: 1 +enum/PAM: + bit_size: 1 + variants: + - name: Disabled + description: Filtering of multicast frames depends on HM + value: 0 + - name: Enabled + description: All received frames with a multicast destination address are passed + value: 1 +enum/PBL: + bit_size: 6 + variants: + - name: PBL1 + description: Maximum of 1 beat per DMA transaction + value: 1 + - name: PBL2 + description: Maximum of 2 beats per DMA transaction + value: 2 + - name: PBL4 + description: Maximum of 4 beats per DMA transaction + value: 4 + - name: PBL8 + description: Maximum of 8 beats per DMA transaction + value: 8 + - name: PBL16 + description: Maximum of 16 beats per DMA transaction + value: 16 + - name: PBL32 + description: Maximum of 32 beats per DMA transaction + value: 32 +enum/PCF: + bit_size: 2 + variants: + - name: PreventAll + description: MAC prevents all control frames from reaching the application + value: 0 + - name: ForwardAllExceptPause + description: MAC forwards all control frames to application except Pause + value: 1 + - name: ForwardAll + description: MAC forwards all control frames to application even if they fail the address filter + value: 2 + - name: ForwardAllFiltered + description: MAC forwards control frames that pass the address filter + value: 3 +enum/PD: + bit_size: 1 + variants: + - name: Enabled + description: All received frames will be dropped. Cleared automatically when a magic packet or wakeup frame is received + value: 1 +enum/PLT: + bit_size: 2 + variants: + - name: PLT4 + description: Pause time minus 4 slot times + value: 0 + - name: PLT28 + description: Pause time minus 28 slot times + value: 1 + - name: PLT144 + description: Pause time minus 144 slot times + value: 2 + - name: PLT256 + description: Pause time minus 256 slot times + value: 3 +enum/PM: + bit_size: 1 + variants: + - name: Disabled + description: Normal address filtering + value: 0 + - name: Enabled + description: Address filters pass all incoming frames regardless of their destination or source address + value: 1 +enum/PMTIM: + bit_size: 1 + variants: + - name: Unmasked + description: PMT Status interrupt generation enabled + value: 0 + - name: Masked + description: PMT Status interrupt generation disabled + value: 1 +enum/PriorityRxOverTx: + bit_size: 2 + variants: + - name: OneToOne + description: "RxDMA priority over TxDMA is 1:1" + value: 0 + - name: TwoToOne + description: "RxDMA priority over TxDMA is 2:1" + value: 1 + - name: ThreeToOne + description: "RxDMA priority over TxDMA is 3:1" + value: 2 + - name: FourToOne + description: "RxDMA priority over TxDMA is 4:1" + value: 3 +enum/RA: + bit_size: 1 + variants: + - name: Disabled + description: MAC receiver passes on to the application only those frames that have passed the SA/DA address file + value: 0 + - name: Enabled + description: MAC receiver passes oll received frames on to the application + value: 1 +enum/RD: + bit_size: 1 + variants: + - name: Enabled + description: MAC attempts retries based on the settings of BL + value: 0 + - name: Disabled + description: MAC attempts only 1 transmission + value: 1 +enum/RDP: + bit_size: 6 + variants: + - name: RDP1 + description: 1 beat per RxDMA transaction + value: 1 + - name: RDP2 + description: 2 beats per RxDMA transaction + value: 2 + - name: RDP4 + description: 4 beats per RxDMA transaction + value: 4 + - name: RDP8 + description: 8 beats per RxDMA transaction + value: 8 + - name: RDP16 + description: 16 beats per RxDMA transaction + value: 16 + - name: RDP32 + description: 32 beats per RxDMA transaction + value: 32 +enum/RE: + bit_size: 1 + variants: + - name: Disabled + description: MAC receive state machine is disabled after the completion of the reception of the current frame + value: 0 + - name: Enabled + description: MAC receive state machine is enabled + value: 1 +enum/RFAEM: + bit_size: 1 + variants: + - name: Unmasked + description: Received-alignment-error counter half-full interrupt enabled + value: 0 + - name: Masked + description: Received-alignment-error counter half-full interrupt disabled + value: 1 +enum/RFCE: + bit_size: 1 + variants: + - name: Disabled + description: Pause frames are not decoded + value: 0 + - name: Enabled + description: MAC decodes received Pause frames and disables its transmitted for a specified time + value: 1 +enum/RFCEM: + bit_size: 1 + variants: + - name: Unmasked + description: Received-crc-error counter half-full interrupt enabled + value: 0 + - name: Masked + description: Received-crc-error counter half-full interrupt disabled + value: 1 +enum/RGUFM: + bit_size: 1 + variants: + - name: Unmasked + description: Received-good-unicast counter half-full interrupt enabled + value: 0 + - name: Masked + description: Received-good-unicast counter half-full interrupt disabled + value: 1 +enum/ROD: + bit_size: 1 + variants: + - name: Enabled + description: MAC receives all packets from PHY while transmitting + value: 0 + - name: Disabled + description: MAC disables reception of frames in half-duplex mode + value: 1 +enum/ROR: + bit_size: 1 + variants: + - name: Disabled + description: MMC counters do not reset on read + value: 0 + - name: Enabled + description: MMC counters reset to zero after read + value: 1 +enum/RPD: + bit_size: 32 + variants: + - name: Poll + description: Poll the receive descriptor list + value: 0 +enum/RPS: + bit_size: 3 + variants: + - name: Stopped + description: "Stopped, reset or Stop Receive command issued" + value: 0 + - name: RunningFetching + description: "Running, fetching receive transfer descriptor" + value: 1 + - name: RunningWaiting + description: "Running, waiting for receive packet" + value: 3 + - name: Suspended + description: "Suspended, receive descriptor unavailable" + value: 4 + - name: RunningWriting + description: "Running, writing data to host memory buffer" + value: 7 +enum/RSF: + bit_size: 1 + variants: + - name: CutThrough + description: "Rx FIFO operates in cut-through mode, subject to RTC bits" + value: 0 + - name: StoreForward + description: Frames are read from Rx FIFO after complete frame has been written + value: 1 +enum/RTC: + bit_size: 2 + variants: + - name: RTC64 + description: 64 bytes + value: 0 + - name: RTC32 + description: 32 bytes + value: 1 + - name: RTC96 + description: 96 bytes + value: 2 + - name: RTC128 + description: 128 bytes + value: 3 +enum/SAF: + bit_size: 1 + variants: + - name: Disabled + description: Source address ignored + value: 0 + - name: Enabled + description: MAC drops frames that fail the source address filter + value: 1 +enum/SAIF: + bit_size: 1 + variants: + - name: Normal + description: Source address filter operates normally + value: 0 + - name: Invert + description: Source address filter operation inverted + value: 1 +enum/ST: + bit_size: 1 + variants: + - name: Stopped + description: Transmission is placed in the Stopped state + value: 0 + - name: Started + description: Transmission is placed in Running state + value: 1 +enum/TE: + bit_size: 1 + variants: + - name: Disabled + description: MAC transmit state machine is disabled after completion of the transmission of the current frame + value: 0 + - name: Enabled + description: MAC transmit state machine is enabled + value: 1 +enum/TFCE: + bit_size: 1 + variants: + - name: Disabled + description: "In full duplex, flow control is disabled. In half duplex, back pressure is disabled" + value: 0 + - name: Enabled + description: "In full duplex, flow control is enabled. In half duplex, back pressure is enabled" + value: 1 +enum/TGFM: + bit_size: 1 + variants: + - name: Unmasked + description: Transmitted-good counter half-full interrupt enabled + value: 0 + - name: Masked + description: Transmitted-good counter half-full interrupt disabled + value: 1 +enum/TGFMSCM: + bit_size: 1 + variants: + - name: Unmasked + description: Transmitted-good-multiple-collision half-full interrupt enabled + value: 0 + - name: Masked + description: Transmitted-good-multiple-collision half-full interrupt disabled + value: 1 +enum/TGFSCM: + bit_size: 1 + variants: + - name: Unmasked + description: Transmitted-good-single-collision half-full interrupt enabled + value: 0 + - name: Masked + description: Transmitted-good-single-collision half-full interrupt disabled + value: 1 +enum/TPD: + bit_size: 32 + variants: + - name: Poll + description: Poll the transmit descriptor list + value: 0 +enum/TPS: + bit_size: 3 + variants: + - name: Stopped + description: "Stopped, Reset or Stop Transmit command issued" + value: 0 + - name: RunningFetching + description: "Running, fetching transmit transfer descriptor" + value: 1 + - name: RunningWaiting + description: "Running, waiting for status" + value: 2 + - name: RunningReading + description: "Running, reading data from host memory buffer" + value: 3 + - name: Suspended + description: "Suspended, transmit descriptor unavailable or transmit buffer underflow" + value: 6 + - name: Running + description: "Running, closing transmit descriptor" + value: 7 +enum/TSF: + bit_size: 1 + variants: + - name: CutThrough + description: Transmission starts when the frame size in the Tx FIFO exceeds TTC threshold + value: 0 + - name: StoreForward + description: Transmission starts when a full frame is in the Tx FIFO + value: 1 +enum/TSTIM: + bit_size: 1 + variants: + - name: Unmasked + description: Time stamp interrupt generation enabled + value: 0 + - name: Masked + description: Time stamp interrupt generation disabled + value: 1 +enum/TTC: + bit_size: 3 + variants: + - name: TTC64 + description: 64 bytes + value: 0 + - name: TTC128 + description: 128 bytes + value: 1 + - name: TTC192 + description: 192 bytes + value: 2 + - name: TTC256 + description: 256 bytes + value: 3 + - name: TTC40 + description: 40 bytes + value: 4 + - name: TTC32 + description: 32 bytes + value: 5 + - name: TTC24 + description: 24 bytes + value: 6 + - name: TTC16 + description: 16 bytes + value: 7 +enum/UPFD: + bit_size: 1 + variants: + - name: Disabled + description: MAC detects only a Pause frame with the multicast address specified in the 802.3x standard + value: 0 + - name: Enabled + description: "MAC additionally detects Pause frames with the station's unicast address" + value: 1 +enum/USP: + bit_size: 1 + variants: + - name: Combined + description: PBL value used for both Rx and Tx DMA + value: 0 + - name: Separate + description: "RxDMA uses RDP value, TxDMA uses PBL value" + value: 1 +enum/VLANTC: + bit_size: 1 + variants: + - name: VLANTC16 + description: Full 16 bit VLAN identifiers are used for comparison and filtering + value: 0 + - name: VLANTC12 + description: 12 bit VLAN identifies are used for comparison and filtering + value: 1 +enum/WD: + bit_size: 1 + variants: + - name: Enabled + description: "Watchdog enabled, receive frames limited to 2048 bytes" + value: 0 + - name: Disabled + description: "Watchdog disabled, receive frames may be up to to 16384 bytes" + value: 1 +enum/WFE: + bit_size: 1 + variants: + - name: Disabled + description: No power management event generated due to wakeup frame reception + value: 0 + - name: Enabled + description: Enable generation of a power management event due to wakeup frame reception + value: 1 +enum/WFFRPR: + bit_size: 1 + variants: + - name: Reset + description: Reset wakeup frame filter register point to 0b000. Automatically cleared + value: 1 +enum/ZQPD: + bit_size: 1 + variants: + - name: Enabled + description: Normal operation with automatic zero-quanta pause control frame generation + value: 0 + - name: Disabled + description: Automatic generation of zero-quanta pause control frames is disabled + value: 1 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 0e5a878..4fdd096 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -230,6 +230,7 @@ perimap = [ ('STM32U5.*:FLASH:.*', ('flash', 'u5', 'FLASH')), ('STM32WB.*:FLASH:.*', ('flash', 'wb55', 'FLASH')), ('STM32G0.*:FLASH:.*', ('flash', 'g0', 'FLASH')), + ('STM32F107.*:ETH:.*', ('eth', 'v1a', 'ETH')), ('STM32F7.*:ETH:ETH:ethermac110_v2_0', ('eth', 'v1c', 'ETH')), ('.*ETH:ethermac110_v3_0', ('eth', 'v2', 'ETH')), From 3dd39de9461995f473eeef467c15894e89658831 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Wed, 20 Apr 2022 13:49:09 +0200 Subject: [PATCH 14/35] Add flash for stm32wl --- data/registers/flash_wl55.yaml | 559 +++++++++++++++++++++++++++++++++ stm32data/__main__.py | 1 + 2 files changed, 560 insertions(+) create mode 100644 data/registers/flash_wl55.yaml diff --git a/data/registers/flash_wl55.yaml b/data/registers/flash_wl55.yaml new file mode 100644 index 0000000..da253b4 --- /dev/null +++ b/data/registers/flash_wl55.yaml @@ -0,0 +1,559 @@ +--- +block/FLASH: + description: Flash + items: + - name: ACR + description: Access control register + byte_offset: 0 + fieldset: ACR + - name: KEYR + description: Flash key register + byte_offset: 8 + access: Write + fieldset: KEYR + - name: OPTKEYR + description: Option byte key register + byte_offset: 12 + access: Write + fieldset: OPTKEYR + - name: SR + description: Status register + byte_offset: 16 + fieldset: SR + - name: CR + description: Flash control register + byte_offset: 20 + fieldset: CR + - name: ECCR + description: Flash ECC register + byte_offset: 24 + fieldset: ECCR + - name: OPTR + description: Flash option register + byte_offset: 32 + fieldset: OPTR + - name: PCROP1ASR + description: Flash Bank 1 PCROP Start address zone A register + byte_offset: 36 + fieldset: PCROP1ASR + - name: PCROP1AER + description: Flash Bank 1 PCROP End address zone A register + byte_offset: 40 + fieldset: PCROP1AER + - name: WRP1AR + description: Flash Bank 1 WRP area A address register + byte_offset: 44 + fieldset: WRP1AR + - name: WRP1BR + description: Flash Bank 1 WRP area B address register + byte_offset: 48 + fieldset: WRP1BR + - name: PCROP1BSR + description: Flash Bank 1 PCROP Start address area B register + byte_offset: 52 + fieldset: PCROP1BSR + - name: PCROP1BER + description: Flash Bank 1 PCROP End address area B register + byte_offset: 56 + fieldset: PCROP1BER + - name: IPCCBR + description: IPCC mailbox data buffer address register + byte_offset: 60 + fieldset: IPCCBR + - name: C2ACR + description: CPU2 cortex M0 access control register + byte_offset: 92 + fieldset: C2ACR + - name: C2SR + description: CPU2 cortex M0 status register + byte_offset: 96 + fieldset: C2SR + - name: C2CR + description: CPU2 cortex M0 control register + byte_offset: 100 + fieldset: C2CR + - name: SFR + description: Secure flash start address register + byte_offset: 128 + fieldset: SFR + - name: SRRVR + description: Secure SRAM2 start address and cortex M0 reset vector register + byte_offset: 132 + fieldset: SRRVR +fieldset/ACR: + description: Access control register + fields: + - name: LATENCY + description: Latency + bit_offset: 0 + bit_size: 3 + - name: PRFTEN + description: Prefetch enable + bit_offset: 8 + bit_size: 1 + - name: ICEN + description: Instruction cache enable + bit_offset: 9 + bit_size: 1 + - name: DCEN + description: Data cache enable + bit_offset: 10 + bit_size: 1 + - name: ICRST + description: Instruction cache reset + bit_offset: 11 + bit_size: 1 + - name: DCRST + description: Data cache reset + bit_offset: 12 + bit_size: 1 + - name: PES + description: CPU1 CortexM4 program erase suspend request + bit_offset: 15 + bit_size: 1 + - name: EMPTY + description: Flash User area empty + bit_offset: 16 + bit_size: 1 +fieldset/C2ACR: + description: CPU2 cortex M0 access control register + fields: + - name: PRFTEN + description: CPU2 cortex M0 prefetch enable + bit_offset: 8 + bit_size: 1 + - name: ICEN + description: CPU2 cortex M0 instruction cache enable + bit_offset: 9 + bit_size: 1 + - name: ICRST + description: CPU2 cortex M0 instruction cache reset + bit_offset: 11 + bit_size: 1 + - name: PES + description: CPU2 cortex M0 program erase suspend request + bit_offset: 15 + bit_size: 1 +fieldset/C2CR: + description: CPU2 cortex M0 control register + fields: + - name: PG + description: Programming + bit_offset: 0 + bit_size: 1 + - name: PER + description: Page erase + bit_offset: 1 + bit_size: 1 + - name: MER + description: Masse erase + bit_offset: 2 + bit_size: 1 + - name: PNB + description: Page Number selection + bit_offset: 3 + bit_size: 8 + - name: STRT + description: Start + bit_offset: 16 + bit_size: 1 + - name: FSTPG + description: Fast programming + bit_offset: 18 + bit_size: 1 + - name: EOPIE + description: End of operation interrupt enable + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 25 + bit_size: 1 + - name: RDERRIE + description: PCROP read error interrupt enable + bit_offset: 26 + bit_size: 1 +fieldset/C2SR: + description: CPU2 cortex M0 status register + fields: + - name: EOP + description: End of operation + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: Operation error + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: Programming error + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: write protection error + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: Programming alignment error + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: Size error + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: Programming sequence error + bit_offset: 7 + bit_size: 1 + - name: MISSERR + description: Fast programming data miss error + bit_offset: 8 + bit_size: 1 + - name: FASTERR + description: Fast programming error + bit_offset: 9 + bit_size: 1 + - name: RDERR + description: PCROP read error + bit_offset: 14 + bit_size: 1 + - name: BSY + description: Busy + bit_offset: 16 + bit_size: 1 + - name: CFGBSY + description: Programming or erase configuration busy + bit_offset: 18 + bit_size: 1 + - name: PESD + description: Programming or erase operation suspended + bit_offset: 19 + bit_size: 1 +fieldset/CR: + description: Flash control register + fields: + - name: PG + description: Programming + bit_offset: 0 + bit_size: 1 + - name: PER + description: Page erase + bit_offset: 1 + bit_size: 1 + - name: MER + description: This bit triggers the mass erase (all user pages) when set + bit_offset: 2 + bit_size: 1 + - name: PNB + description: Page number selection + bit_offset: 3 + bit_size: 8 + - name: STRT + description: Start + bit_offset: 16 + bit_size: 1 + - name: OPTSTRT + description: Options modification start + bit_offset: 17 + bit_size: 1 + - name: FSTPG + description: Fast programming + bit_offset: 18 + bit_size: 1 + - name: EOPIE + description: End of operation interrupt enable + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 25 + bit_size: 1 + - name: RDERRIE + description: PCROP read error interrupt enable + bit_offset: 26 + bit_size: 1 + - name: OBL_LAUNCH + description: Force the option byte loading + bit_offset: 27 + bit_size: 1 + - name: OPTLOCK + description: Options Lock + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: FLASH_CR Lock + bit_offset: 31 + bit_size: 1 +fieldset/ECCR: + description: Flash ECC register + fields: + - name: ADDR_ECC + description: ECC fail address + bit_offset: 0 + bit_size: 17 + - name: SYSF_ECC + description: System Flash ECC fail + bit_offset: 20 + bit_size: 1 + - name: ECCCIE + description: ECC correction interrupt enable + bit_offset: 24 + bit_size: 1 + - name: CPUID + description: CPU identification + bit_offset: 26 + bit_size: 3 + - name: ECCC + description: ECC correction + bit_offset: 30 + bit_size: 1 + - name: ECCD + description: ECC detection + bit_offset: 31 + bit_size: 1 +fieldset/IPCCBR: + description: IPCC mailbox data buffer address register + fields: + - name: IPCCDBA + description: PCC mailbox data buffer base address + bit_offset: 0 + bit_size: 14 +fieldset/KEYR: + description: Flash key register + fields: + - name: KEYR + description: KEYR + bit_offset: 0 + bit_size: 32 +fieldset/OPTKEYR: + description: Option byte key register + fields: + - name: OPTKEYR + description: Option byte key + bit_offset: 0 + bit_size: 32 +fieldset/OPTR: + description: Flash option register + fields: + - name: RDP + description: Read protection level + bit_offset: 0 + bit_size: 8 + - name: ESE + description: Security enabled + bit_offset: 8 + bit_size: 1 + - name: BOR_LEV + description: BOR reset Level + bit_offset: 9 + bit_size: 3 + - name: nRST_STOP + description: nRST_STOP + bit_offset: 12 + bit_size: 1 + - name: nRST_STDBY + description: nRST_STDBY + bit_offset: 13 + bit_size: 1 + - name: nRST_SHDW + description: nRST_SHDW + bit_offset: 14 + bit_size: 1 + - name: IDWG_SW + description: Independent watchdog selection + bit_offset: 16 + bit_size: 1 + - name: IWDG_STOP + description: Independent watchdog counter freeze in Stop mode + bit_offset: 17 + bit_size: 1 + - name: IWDG_STDBY + description: Independent watchdog counter freeze in Standby mode + bit_offset: 18 + bit_size: 1 + - name: WWDG_SW + description: Window watchdog selection + bit_offset: 19 + bit_size: 1 + - name: nBOOT1 + description: Boot configuration + bit_offset: 23 + bit_size: 1 + - name: SRAM2_PE + description: SRAM2 parity check enable + bit_offset: 24 + bit_size: 1 + - name: SRAM2_RST + description: SRAM2 Erase when system reset + bit_offset: 25 + bit_size: 1 + - name: nSWBOOT0 + description: Software Boot0 + bit_offset: 26 + bit_size: 1 + - name: nBOOT0 + description: nBoot0 option bit + bit_offset: 27 + bit_size: 1 + - name: AGC_TRIM + description: Radio Automatic Gain Control Trimming + bit_offset: 29 + bit_size: 3 +fieldset/PCROP1AER: + description: Flash Bank 1 PCROP End address zone A register + fields: + - name: PCROP1A_END + description: Bank 1 PCROP area end offset + bit_offset: 0 + bit_size: 9 + - name: PCROP_RDP + description: PCROP area preserved when RDP level decreased + bit_offset: 31 + bit_size: 1 +fieldset/PCROP1ASR: + description: Flash Bank 1 PCROP Start address zone A register + fields: + - name: PCROP1A_STRT + description: Bank 1 PCROPQ area start offset + bit_offset: 0 + bit_size: 9 +fieldset/PCROP1BER: + description: Flash Bank 1 PCROP End address area B register + fields: + - name: PCROP1B_END + description: Bank 1 PCROP area end area B offset + bit_offset: 0 + bit_size: 9 +fieldset/PCROP1BSR: + description: Flash Bank 1 PCROP Start address area B register + fields: + - name: PCROP1B_STRT + description: Bank 1 PCROP area B start offset + bit_offset: 0 + bit_size: 9 +fieldset/SFR: + description: Secure flash start address register + fields: + - name: SFSA + description: Secure flash start address + bit_offset: 0 + bit_size: 8 + - name: FSD + description: Flash security disable + bit_offset: 8 + bit_size: 1 + - name: DDS + description: Disable Cortex M0 debug access + bit_offset: 12 + bit_size: 1 +fieldset/SR: + description: Status register + fields: + - name: EOP + description: End of operation + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: Operation error + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: Programming error + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: Write protected error + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: Programming alignment error + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: Size error + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: Programming sequence error + bit_offset: 7 + bit_size: 1 + - name: MISERR + description: Fast programming data miss error + bit_offset: 8 + bit_size: 1 + - name: FASTERR + description: Fast programming error + bit_offset: 9 + bit_size: 1 + - name: OPTNV + description: User Option OPTVAL indication + bit_offset: 13 + bit_size: 1 + - name: RDERR + description: PCROP read error + bit_offset: 14 + bit_size: 1 + - name: OPTVERR + description: Option validity error + bit_offset: 15 + bit_size: 1 + - name: BSY + description: Busy + bit_offset: 16 + bit_size: 1 + - name: CFGBSY + description: Programming or erase configuration busy + bit_offset: 18 + bit_size: 1 + - name: PESD + description: Programming or erase operation suspended + bit_offset: 19 + bit_size: 1 +fieldset/SRRVR: + description: Secure SRAM2 start address and cortex M0 reset vector register + fields: + - name: SBRV + description: cortex M0 access control register + bit_offset: 0 + bit_size: 18 + - name: SBRSA + description: Secure backup SRAM2a start address + bit_offset: 18 + bit_size: 5 + - name: BRSD + description: backup SRAM2a security disable + bit_offset: 23 + bit_size: 1 + - name: SNBRSA + description: Secure non backup SRAM2a start address + bit_offset: 25 + bit_size: 5 + - name: NBRSD + description: non-backup SRAM2b security disable + bit_offset: 30 + bit_size: 1 + - name: C2OPT + description: CPU2 cortex M0 boot reset vector memory selection + bit_offset: 31 + bit_size: 1 +fieldset/WRP1AR: + description: Flash Bank 1 WRP area A address register + fields: + - name: WRP1A_STRT + description: Bank 1 WRP first area A start offset + bit_offset: 0 + bit_size: 8 + - name: WRP1A_END + description: Bank 1 WRP first area A end offset + bit_offset: 16 + bit_size: 8 +fieldset/WRP1BR: + description: Flash Bank 1 WRP area B address register + fields: + - name: WRP1B_END + description: Bank 1 WRP second area B start offset + bit_offset: 0 + bit_size: 8 + - name: WRP1B_STRT + description: Bank 1 WRP second area B end offset + bit_offset: 16 + bit_size: 8 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 0e5a878..e38f745 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -229,6 +229,7 @@ perimap = [ ('STM32L5.*:FLASH:.*', ('flash', 'l5', 'FLASH')), ('STM32U5.*:FLASH:.*', ('flash', 'u5', 'FLASH')), ('STM32WB.*:FLASH:.*', ('flash', 'wb55', 'FLASH')), + ('STM32WL.*:FLASH:.*', ('flash', 'wl55', 'FLASH')), ('STM32G0.*:FLASH:.*', ('flash', 'g0', 'FLASH')), ('STM32F7.*:ETH:ETH:ethermac110_v2_0', ('eth', 'v1c', 'ETH')), ('.*ETH:ethermac110_v3_0', ('eth', 'v2', 'ETH')), From 004542bf86fd8a91c78d6193433e730af7f578b9 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Fri, 22 Apr 2022 09:39:42 +0200 Subject: [PATCH 15/35] Add l0 flash support --- data/registers/flash_l0.yaml | 630 +++++++++++++++++++++++++++++++++++ stm32data/__main__.py | 1 + 2 files changed, 631 insertions(+) create mode 100644 data/registers/flash_l0.yaml diff --git a/data/registers/flash_l0.yaml b/data/registers/flash_l0.yaml new file mode 100644 index 0000000..774a776 --- /dev/null +++ b/data/registers/flash_l0.yaml @@ -0,0 +1,630 @@ +--- +block/FLASH: + description: Flash + items: + - name: ACR + description: Access control register + byte_offset: 0 + fieldset: ACR + - name: PECR + description: Program/erase control register + byte_offset: 4 + fieldset: PECR + - name: PDKEYR + description: Power down key register + byte_offset: 8 + access: Write + fieldset: PDKEYR + - name: PEKEYR + description: Program/erase key register + byte_offset: 12 + access: Write + fieldset: PEKEYR + - name: PRGKEYR + description: Program memory key register + byte_offset: 16 + access: Write + fieldset: PRGKEYR + - name: OPTKEYR + description: Option byte key register + byte_offset: 20 + access: Write + fieldset: OPTKEYR + - name: SR + description: Status register + byte_offset: 24 + fieldset: SR + - name: OPTR + description: Option byte register + byte_offset: 28 + access: Read + fieldset: OPTR + - name: WRPROT1 + description: Write Protection Register 1 + byte_offset: 32 + access: Read + fieldset: WRPROT1 + - name: WRPROT2 + description: Write Protection Register 2 + byte_offset: 128 + access: Read + fieldset: WRPROT2 +fieldset/ACR: + description: Access control register + fields: + - name: LATENCY + description: Latency + bit_offset: 0 + bit_size: 1 + enum: LATENCY + - name: PRFTEN + description: Prefetch enable + bit_offset: 1 + bit_size: 1 + enum: PRFTEN + - name: SLEEP_PD + description: Flash mode during Sleep + bit_offset: 3 + bit_size: 1 + enum: SLEEP_PD + - name: RUN_PD + description: Flash mode during Run + bit_offset: 4 + bit_size: 1 + enum: RUN_PD + - name: DISAB_BUF + description: Disable Buffer + bit_offset: 5 + bit_size: 1 + enum: DISAB_BUF + - name: PRE_READ + description: Pre-read data address + bit_offset: 6 + bit_size: 1 + enum: PRE_READ +fieldset/OPTKEYR: + description: Option byte key register + fields: + - name: OPTKEYR + description: Option byte key + bit_offset: 0 + bit_size: 32 +fieldset/OPTR: + description: Option byte register + fields: + - name: RDPROT + description: Read protection + bit_offset: 0 + bit_size: 8 + enum: RDPROT + - name: WPRMOD + description: Selection of protection mode of WPR bits + bit_offset: 8 + bit_size: 1 + enum: WPRMOD + - name: BOR_LEV + description: BOR_LEV + bit_offset: 16 + bit_size: 4 + enum: BOR_LEV +fieldset/PDKEYR: + description: Power down key register + fields: + - name: PDKEYR + description: RUN_PD in FLASH_ACR key + bit_offset: 0 + bit_size: 32 +fieldset/PECR: + description: Program/erase control register + fields: + - name: PELOCK + description: FLASH_PECR and data EEPROM lock + bit_offset: 0 + bit_size: 1 + enum: PELOCK + - name: PRGLOCK + description: Program memory lock + bit_offset: 1 + bit_size: 1 + enum: PRGLOCK + - name: OPTLOCK + description: Option bytes block lock + bit_offset: 2 + bit_size: 1 + enum: OPTLOCK + - name: PROG + description: Program memory selection + bit_offset: 3 + bit_size: 1 + enum: PROG + - name: DATA + description: Data EEPROM selection + bit_offset: 4 + bit_size: 1 + enum: DATA + - name: FIX + description: "Fixed time data write for Byte, Half Word and Word programming" + bit_offset: 8 + bit_size: 1 + enum: FIX + - name: ERASE + description: Page or Double Word erase mode + bit_offset: 9 + bit_size: 1 + enum: ERASE + - name: FPRG + description: Half Page/Double Word programming mode + bit_offset: 10 + bit_size: 1 + enum: FPRG + - name: PARALLELBANK + description: Parallel bank mode + bit_offset: 15 + bit_size: 1 + enum: PARALLELBANK + - name: EOPIE + description: End of programming interrupt enable + bit_offset: 16 + bit_size: 1 + enum: EOPIE + - name: ERRIE + description: Error interrupt enable + bit_offset: 17 + bit_size: 1 + enum: ERRIE + - name: OBL_LAUNCH + description: Launch the option byte loading + bit_offset: 18 + bit_size: 1 + enum_read: OBL_LAUNCHR + enum_write: OBL_LAUNCHW +fieldset/PEKEYR: + description: Program/erase key register + fields: + - name: PEKEYR + description: FLASH_PEC and data EEPROM key + bit_offset: 0 + bit_size: 32 +fieldset/PRGKEYR: + description: Program memory key register + fields: + - name: PRGKEYR + description: Program memory key + bit_offset: 0 + bit_size: 32 +fieldset/SR: + description: Status register + fields: + - name: BSY + description: Write/erase operations in progress + bit_offset: 0 + bit_size: 1 + enum: BSY + - name: EOP + description: End of operation + bit_offset: 1 + bit_size: 1 + enum: EOP + - name: ENDHV + description: End of high voltage + bit_offset: 2 + bit_size: 1 + enum: ENDHV + - name: READY + description: Flash memory module ready after low power mode + bit_offset: 3 + bit_size: 1 + enum: READY + - name: WRPERR + description: Write protected error + bit_offset: 8 + bit_size: 1 + enum_read: WRPERRR + enum_write: WRPERRW + - name: PGAERR + description: Programming alignment error + bit_offset: 9 + bit_size: 1 + enum_read: PGAERRR + enum_write: PGAERRW + - name: SIZERR + description: Size error + bit_offset: 10 + bit_size: 1 + enum_read: SIZERRR + enum_write: SIZERRW + - name: OPTVERR + description: Option validity error + bit_offset: 11 + bit_size: 1 + enum_read: OPTVERRR + enum_write: OPTVERRW + - name: RDERR + description: RDERR + bit_offset: 14 + bit_size: 1 + enum_read: RDERRR + enum_write: RDERRW + - name: NOTZEROERR + description: NOTZEROERR + bit_offset: 16 + bit_size: 1 + enum_read: NOTZEROERRR + enum_write: NOTZEROERRW + - name: FWWERR + description: FWWERR + bit_offset: 17 + bit_size: 1 + enum_read: FWWERRR + enum_write: FWWERRW +fieldset/WRPROT1: + description: Write Protection Register 1 + fields: + - name: WRPROT + description: Write Protection + bit_offset: 0 + bit_size: 32 + array: + len: 1 + stride: 0 +fieldset/WRPROT2: + description: Write Protection Register 2 + fields: + - name: WRPROT + description: Write Protection + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 +enum/BOR_LEV: + bit_size: 4 + variants: + - name: BOR_Off + description: This is the reset threshold level for the 1.45 V - 1.55 V voltage range (power-down only) + value: 0 + - name: BOR_Level1 + description: Reset threshold level for VBOR0 (around 1.8 V) + value: 1 + - name: BOR_Level2 + description: Reset threshold level for VBOR1 (around 2.0 V) + value: 2 + - name: BOR_Level3 + description: Reset threshold level for VBOR2 (around 2.5 V) + value: 3 + - name: BOR_Level4 + description: Reset threshold level for VBOR3 (around 2.7 V) + value: 4 + - name: BOR_Level5 + description: Reset threshold level for VBOR4 (around 3.0 V) + value: 5 +enum/BSY: + bit_size: 1 + variants: + - name: Inactive + description: No write/erase operation is in progress + value: 0 + - name: Active + description: No write/erase operation is in progress + value: 1 +enum/DATA: + bit_size: 1 + variants: + - name: NotSelected + description: Data EEPROM not selected + value: 0 + - name: Selected + description: Data memory selected + value: 1 +enum/DISAB_BUF: + bit_size: 1 + variants: + - name: Enabled + description: The buffers are enabled + value: 0 + - name: Disabled + description: The buffers are disabled + value: 1 +enum/ENDHV: + bit_size: 1 + variants: + - name: Active + description: High voltage is executing a write/erase operation in the NVM + value: 0 + - name: Inactive + description: "High voltage is off, no write/erase operation is ongoing" + value: 1 +enum/EOP: + bit_size: 1 + variants: + - name: NoEvent + description: No EOP operation occurred + value: 0 + - name: Event + description: An EOP event occurred + value: 1 +enum/EOPIE: + bit_size: 1 + variants: + - name: Disabled + description: End of program interrupt disable + value: 0 + - name: Enabled + description: End of program interrupt enable + value: 1 +enum/ERASE: + bit_size: 1 + variants: + - name: NoErase + description: No erase operation requested + value: 0 + - name: Erase + description: Erase operation requested + value: 1 +enum/ERRIE: + bit_size: 1 + variants: + - name: Disabled + description: Error interrupt disable + value: 0 + - name: Enabled + description: Error interrupt enable + value: 1 +enum/FIX: + bit_size: 1 + variants: + - name: AutoErase + description: An erase phase is automatically performed + value: 0 + - name: PrelimErase + description: The program operation is always performed with a preliminary erase + value: 1 +enum/FPRG: + bit_size: 1 + variants: + - name: Disabled + description: Half Page programming disabled + value: 0 + - name: Enabled + description: Half Page programming enabled + value: 1 +enum/FWWERRR: + bit_size: 1 + variants: + - name: NoError + description: No write/erase operation aborted to perform a fetch + value: 0 + - name: Error + description: A write/erase operation aborted to perform a fetch + value: 1 +enum/FWWERRW: + bit_size: 1 + variants: + - name: Clear + description: Clear the flag + value: 1 +enum/LATENCY: + bit_size: 1 + variants: + - name: WS0 + description: Zero wait state is used to read a word in the NVM + value: 0 + - name: WS1 + description: One wait state is used to read a word in the NVM + value: 1 +enum/NOTZEROERRR: + bit_size: 1 + variants: + - name: NoEvent + description: The write operation is done in an erased region or the memory interface can apply an erase before a write + value: 0 + - name: Event + description: The write operation is attempting to write to a not-erased region and the memory interface cannot apply an erase before a write + value: 1 +enum/NOTZEROERRW: + bit_size: 1 + variants: + - name: Clear + description: Clear the flag + value: 1 +enum/OBL_LAUNCHR: + bit_size: 1 + variants: + - name: Complete + description: Option byte loaded + value: 0 + - name: NotComplete + description: Option byte loading to be done + value: 1 +enum/OBL_LAUNCHW: + bit_size: 1 + variants: + - name: Reload + description: Reload option byte + value: 1 +enum/OPTLOCK: + bit_size: 1 + variants: + - name: Unlocked + description: The write and erase operations in the Option bytes area are disabled + value: 0 + - name: Locked + description: The write and erase operations in the Option bytes area are enabled + value: 1 +enum/OPTVERRR: + bit_size: 1 + variants: + - name: NoError + description: No error happened during the Option bytes loading + value: 0 + - name: Error + description: One or more errors happened during the Option bytes loading + value: 1 +enum/OPTVERRW: + bit_size: 1 + variants: + - name: Clear + description: Clear the flag + value: 1 +enum/PARALLELBANK: + bit_size: 1 + variants: + - name: Disabled + description: Parallel bank mode disabled + value: 0 + - name: Enabled + description: Parallel bank mode enabled + value: 1 +enum/PELOCK: + bit_size: 1 + variants: + - name: Unlocked + description: The FLASH_PECR register is unlocked + value: 0 + - name: Locked + description: The FLASH_PECR register is locked and no write/erase operation can start + value: 1 +enum/PGAERRR: + bit_size: 1 + variants: + - name: NoError + description: No alignment error happened + value: 0 + - name: Error + description: One alignment error happened + value: 1 +enum/PGAERRW: + bit_size: 1 + variants: + - name: Clear + description: Clear the flag + value: 1 +enum/PRE_READ: + bit_size: 1 + variants: + - name: Disabled + description: The pre-read is disabled + value: 0 + - name: Enabled + description: The pre-read is enabled + value: 1 +enum/PRFTEN: + bit_size: 1 + variants: + - name: Disabled + description: Prefetch is disabled + value: 0 + - name: Enabled + description: Prefetch is enabled + value: 1 +enum/PRGLOCK: + bit_size: 1 + variants: + - name: Unlocked + description: The write and erase operations in the Flash program memory are disabled + value: 0 + - name: Locked + description: The write and erase operations in the Flash program memory are enabled + value: 1 +enum/PROG: + bit_size: 1 + variants: + - name: NotSelected + description: The Flash program memory is not selected + value: 0 + - name: Selected + description: The Flash program memory is selected + value: 1 +enum/RDERRR: + bit_size: 1 + variants: + - name: NoError + description: No read protection error happened. + value: 0 + - name: Error + description: One read protection error happened + value: 1 +enum/RDERRW: + bit_size: 1 + variants: + - name: Clear + description: Clear the flag + value: 1 +enum/RDPROT: + bit_size: 8 + variants: + - name: Level1 + description: Level 1 + value: 0 + - name: Level0 + description: Level 0 + value: 170 + - name: Level2 + description: Level 2 + value: 204 +enum/READY: + bit_size: 1 + variants: + - name: NotReady + description: The NVM is not ready + value: 0 + - name: Ready + description: The NVM is ready + value: 1 +enum/RUN_PD: + bit_size: 1 + variants: + - name: NVMIdleMode + description: "When the device is in Run mode, the NVM is in Idle mode" + value: 0 + - name: NVMPwrDownMode + description: "When the device is in Run mode, the NVM is in power-down mode" + value: 1 +enum/SIZERRR: + bit_size: 1 + variants: + - name: NoError + description: No size error happened + value: 0 + - name: Error + description: One size error happened + value: 1 +enum/SIZERRW: + bit_size: 1 + variants: + - name: Clear + description: Clear the flag + value: 1 +enum/SLEEP_PD: + bit_size: 1 + variants: + - name: NVMIdleMode + description: "When the device is in Sleep mode, the NVM is in Idle mode" + value: 0 + - name: NVMPwrDownMode + description: "When the device is in Sleep mode, the NVM is in power-down mode" + value: 1 +enum/WPRMOD: + bit_size: 1 + variants: + - name: Disabled + description: PCROP disabled. The WRPROT bits are used as a write protection on a sector. + value: 0 + - name: Enabled + description: PCROP enabled. The WRPROT bits are used as a read protection on a sector. + value: 1 +enum/WRPERRR: + bit_size: 1 + variants: + - name: NoError + description: No protection error happened + value: 0 + - name: Error + description: One protection error happened + value: 1 +enum/WRPERRW: + bit_size: 1 + variants: + - name: Clear + description: Clear the flag + value: 1 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index e38f745..f6414fb 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -224,6 +224,7 @@ perimap = [ ('STM32F3.*:FLASH:.*', ('flash', 'f3', 'FLASH')), ('STM32F4.*:FLASH:.*', ('flash', 'f4', 'FLASH')), ('STM32F7.*:FLASH:.*', ('flash', 'f7', 'FLASH')), + ('STM32L0[0-9]2.*:FLASH:.*', ('flash', 'l0', 'FLASH')), ('STM32L1.*:FLASH:.*', ('flash', 'l1', 'FLASH')), ('STM32L4.*:FLASH:.*', ('flash', 'l4', 'FLASH')), ('STM32L5.*:FLASH:.*', ('flash', 'l5', 'FLASH')), From 83544cfdfcdcc2d6546d0db4238145ac6ca22d7a Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Tue, 26 Apr 2022 14:53:40 +0200 Subject: [PATCH 16/35] Remove enums from l0 regs --- data/registers/flash_l0.yaml | 390 ----------------------------------- 1 file changed, 390 deletions(-) diff --git a/data/registers/flash_l0.yaml b/data/registers/flash_l0.yaml index 774a776..aa1b7d9 100644 --- a/data/registers/flash_l0.yaml +++ b/data/registers/flash_l0.yaml @@ -56,32 +56,26 @@ fieldset/ACR: description: Latency bit_offset: 0 bit_size: 1 - enum: LATENCY - name: PRFTEN description: Prefetch enable bit_offset: 1 bit_size: 1 - enum: PRFTEN - name: SLEEP_PD description: Flash mode during Sleep bit_offset: 3 bit_size: 1 - enum: SLEEP_PD - name: RUN_PD description: Flash mode during Run bit_offset: 4 bit_size: 1 - enum: RUN_PD - name: DISAB_BUF description: Disable Buffer bit_offset: 5 bit_size: 1 - enum: DISAB_BUF - name: PRE_READ description: Pre-read data address bit_offset: 6 bit_size: 1 - enum: PRE_READ fieldset/OPTKEYR: description: Option byte key register fields: @@ -96,17 +90,14 @@ fieldset/OPTR: description: Read protection bit_offset: 0 bit_size: 8 - enum: RDPROT - name: WPRMOD description: Selection of protection mode of WPR bits bit_offset: 8 bit_size: 1 - enum: WPRMOD - name: BOR_LEV description: BOR_LEV bit_offset: 16 bit_size: 4 - enum: BOR_LEV fieldset/PDKEYR: description: Power down key register fields: @@ -121,62 +112,50 @@ fieldset/PECR: description: FLASH_PECR and data EEPROM lock bit_offset: 0 bit_size: 1 - enum: PELOCK - name: PRGLOCK description: Program memory lock bit_offset: 1 bit_size: 1 - enum: PRGLOCK - name: OPTLOCK description: Option bytes block lock bit_offset: 2 bit_size: 1 - enum: OPTLOCK - name: PROG description: Program memory selection bit_offset: 3 bit_size: 1 - enum: PROG - name: DATA description: Data EEPROM selection bit_offset: 4 bit_size: 1 - enum: DATA - name: FIX description: "Fixed time data write for Byte, Half Word and Word programming" bit_offset: 8 bit_size: 1 - enum: FIX - name: ERASE description: Page or Double Word erase mode bit_offset: 9 bit_size: 1 - enum: ERASE - name: FPRG description: Half Page/Double Word programming mode bit_offset: 10 bit_size: 1 - enum: FPRG - name: PARALLELBANK description: Parallel bank mode bit_offset: 15 bit_size: 1 - enum: PARALLELBANK - name: EOPIE description: End of programming interrupt enable bit_offset: 16 bit_size: 1 - enum: EOPIE - name: ERRIE description: Error interrupt enable bit_offset: 17 bit_size: 1 - enum: ERRIE - name: OBL_LAUNCH description: Launch the option byte loading bit_offset: 18 bit_size: 1 - enum_read: OBL_LAUNCHR enum_write: OBL_LAUNCHW fieldset/PEKEYR: description: Program/erase key register @@ -199,64 +178,46 @@ fieldset/SR: description: Write/erase operations in progress bit_offset: 0 bit_size: 1 - enum: BSY - name: EOP description: End of operation bit_offset: 1 bit_size: 1 - enum: EOP - name: ENDHV description: End of high voltage bit_offset: 2 bit_size: 1 - enum: ENDHV - name: READY description: Flash memory module ready after low power mode bit_offset: 3 bit_size: 1 - enum: READY - name: WRPERR description: Write protected error bit_offset: 8 bit_size: 1 - enum_read: WRPERRR - enum_write: WRPERRW - name: PGAERR description: Programming alignment error bit_offset: 9 bit_size: 1 - enum_read: PGAERRR - enum_write: PGAERRW - name: SIZERR description: Size error bit_offset: 10 bit_size: 1 - enum_read: SIZERRR - enum_write: SIZERRW - name: OPTVERR description: Option validity error bit_offset: 11 bit_size: 1 - enum_read: OPTVERRR - enum_write: OPTVERRW - name: RDERR description: RDERR bit_offset: 14 bit_size: 1 - enum_read: RDERRR - enum_write: RDERRW - name: NOTZEROERR description: NOTZEROERR bit_offset: 16 bit_size: 1 - enum_read: NOTZEROERRR - enum_write: NOTZEROERRW - name: FWWERR description: FWWERR bit_offset: 17 bit_size: 1 - enum_read: FWWERRR - enum_write: FWWERRW fieldset/WRPROT1: description: Write Protection Register 1 fields: @@ -277,354 +238,3 @@ fieldset/WRPROT2: array: len: 1 stride: 0 -enum/BOR_LEV: - bit_size: 4 - variants: - - name: BOR_Off - description: This is the reset threshold level for the 1.45 V - 1.55 V voltage range (power-down only) - value: 0 - - name: BOR_Level1 - description: Reset threshold level for VBOR0 (around 1.8 V) - value: 1 - - name: BOR_Level2 - description: Reset threshold level for VBOR1 (around 2.0 V) - value: 2 - - name: BOR_Level3 - description: Reset threshold level for VBOR2 (around 2.5 V) - value: 3 - - name: BOR_Level4 - description: Reset threshold level for VBOR3 (around 2.7 V) - value: 4 - - name: BOR_Level5 - description: Reset threshold level for VBOR4 (around 3.0 V) - value: 5 -enum/BSY: - bit_size: 1 - variants: - - name: Inactive - description: No write/erase operation is in progress - value: 0 - - name: Active - description: No write/erase operation is in progress - value: 1 -enum/DATA: - bit_size: 1 - variants: - - name: NotSelected - description: Data EEPROM not selected - value: 0 - - name: Selected - description: Data memory selected - value: 1 -enum/DISAB_BUF: - bit_size: 1 - variants: - - name: Enabled - description: The buffers are enabled - value: 0 - - name: Disabled - description: The buffers are disabled - value: 1 -enum/ENDHV: - bit_size: 1 - variants: - - name: Active - description: High voltage is executing a write/erase operation in the NVM - value: 0 - - name: Inactive - description: "High voltage is off, no write/erase operation is ongoing" - value: 1 -enum/EOP: - bit_size: 1 - variants: - - name: NoEvent - description: No EOP operation occurred - value: 0 - - name: Event - description: An EOP event occurred - value: 1 -enum/EOPIE: - bit_size: 1 - variants: - - name: Disabled - description: End of program interrupt disable - value: 0 - - name: Enabled - description: End of program interrupt enable - value: 1 -enum/ERASE: - bit_size: 1 - variants: - - name: NoErase - description: No erase operation requested - value: 0 - - name: Erase - description: Erase operation requested - value: 1 -enum/ERRIE: - bit_size: 1 - variants: - - name: Disabled - description: Error interrupt disable - value: 0 - - name: Enabled - description: Error interrupt enable - value: 1 -enum/FIX: - bit_size: 1 - variants: - - name: AutoErase - description: An erase phase is automatically performed - value: 0 - - name: PrelimErase - description: The program operation is always performed with a preliminary erase - value: 1 -enum/FPRG: - bit_size: 1 - variants: - - name: Disabled - description: Half Page programming disabled - value: 0 - - name: Enabled - description: Half Page programming enabled - value: 1 -enum/FWWERRR: - bit_size: 1 - variants: - - name: NoError - description: No write/erase operation aborted to perform a fetch - value: 0 - - name: Error - description: A write/erase operation aborted to perform a fetch - value: 1 -enum/FWWERRW: - bit_size: 1 - variants: - - name: Clear - description: Clear the flag - value: 1 -enum/LATENCY: - bit_size: 1 - variants: - - name: WS0 - description: Zero wait state is used to read a word in the NVM - value: 0 - - name: WS1 - description: One wait state is used to read a word in the NVM - value: 1 -enum/NOTZEROERRR: - bit_size: 1 - variants: - - name: NoEvent - description: The write operation is done in an erased region or the memory interface can apply an erase before a write - value: 0 - - name: Event - description: The write operation is attempting to write to a not-erased region and the memory interface cannot apply an erase before a write - value: 1 -enum/NOTZEROERRW: - bit_size: 1 - variants: - - name: Clear - description: Clear the flag - value: 1 -enum/OBL_LAUNCHR: - bit_size: 1 - variants: - - name: Complete - description: Option byte loaded - value: 0 - - name: NotComplete - description: Option byte loading to be done - value: 1 -enum/OBL_LAUNCHW: - bit_size: 1 - variants: - - name: Reload - description: Reload option byte - value: 1 -enum/OPTLOCK: - bit_size: 1 - variants: - - name: Unlocked - description: The write and erase operations in the Option bytes area are disabled - value: 0 - - name: Locked - description: The write and erase operations in the Option bytes area are enabled - value: 1 -enum/OPTVERRR: - bit_size: 1 - variants: - - name: NoError - description: No error happened during the Option bytes loading - value: 0 - - name: Error - description: One or more errors happened during the Option bytes loading - value: 1 -enum/OPTVERRW: - bit_size: 1 - variants: - - name: Clear - description: Clear the flag - value: 1 -enum/PARALLELBANK: - bit_size: 1 - variants: - - name: Disabled - description: Parallel bank mode disabled - value: 0 - - name: Enabled - description: Parallel bank mode enabled - value: 1 -enum/PELOCK: - bit_size: 1 - variants: - - name: Unlocked - description: The FLASH_PECR register is unlocked - value: 0 - - name: Locked - description: The FLASH_PECR register is locked and no write/erase operation can start - value: 1 -enum/PGAERRR: - bit_size: 1 - variants: - - name: NoError - description: No alignment error happened - value: 0 - - name: Error - description: One alignment error happened - value: 1 -enum/PGAERRW: - bit_size: 1 - variants: - - name: Clear - description: Clear the flag - value: 1 -enum/PRE_READ: - bit_size: 1 - variants: - - name: Disabled - description: The pre-read is disabled - value: 0 - - name: Enabled - description: The pre-read is enabled - value: 1 -enum/PRFTEN: - bit_size: 1 - variants: - - name: Disabled - description: Prefetch is disabled - value: 0 - - name: Enabled - description: Prefetch is enabled - value: 1 -enum/PRGLOCK: - bit_size: 1 - variants: - - name: Unlocked - description: The write and erase operations in the Flash program memory are disabled - value: 0 - - name: Locked - description: The write and erase operations in the Flash program memory are enabled - value: 1 -enum/PROG: - bit_size: 1 - variants: - - name: NotSelected - description: The Flash program memory is not selected - value: 0 - - name: Selected - description: The Flash program memory is selected - value: 1 -enum/RDERRR: - bit_size: 1 - variants: - - name: NoError - description: No read protection error happened. - value: 0 - - name: Error - description: One read protection error happened - value: 1 -enum/RDERRW: - bit_size: 1 - variants: - - name: Clear - description: Clear the flag - value: 1 -enum/RDPROT: - bit_size: 8 - variants: - - name: Level1 - description: Level 1 - value: 0 - - name: Level0 - description: Level 0 - value: 170 - - name: Level2 - description: Level 2 - value: 204 -enum/READY: - bit_size: 1 - variants: - - name: NotReady - description: The NVM is not ready - value: 0 - - name: Ready - description: The NVM is ready - value: 1 -enum/RUN_PD: - bit_size: 1 - variants: - - name: NVMIdleMode - description: "When the device is in Run mode, the NVM is in Idle mode" - value: 0 - - name: NVMPwrDownMode - description: "When the device is in Run mode, the NVM is in power-down mode" - value: 1 -enum/SIZERRR: - bit_size: 1 - variants: - - name: NoError - description: No size error happened - value: 0 - - name: Error - description: One size error happened - value: 1 -enum/SIZERRW: - bit_size: 1 - variants: - - name: Clear - description: Clear the flag - value: 1 -enum/SLEEP_PD: - bit_size: 1 - variants: - - name: NVMIdleMode - description: "When the device is in Sleep mode, the NVM is in Idle mode" - value: 0 - - name: NVMPwrDownMode - description: "When the device is in Sleep mode, the NVM is in power-down mode" - value: 1 -enum/WPRMOD: - bit_size: 1 - variants: - - name: Disabled - description: PCROP disabled. The WRPROT bits are used as a write protection on a sector. - value: 0 - - name: Enabled - description: PCROP enabled. The WRPROT bits are used as a read protection on a sector. - value: 1 -enum/WRPERRR: - bit_size: 1 - variants: - - name: NoError - description: No protection error happened - value: 0 - - name: Error - description: One protection error happened - value: 1 -enum/WRPERRW: - bit_size: 1 - variants: - - name: Clear - description: Clear the flag - value: 1 From 05bf8c23c11f421d81b3e8ed866b25e1392e4b72 Mon Sep 17 00:00:00 2001 From: David Lenfesty Date: Tue, 26 Apr 2022 09:44:38 -0600 Subject: [PATCH 17/35] fix RCC MCO register for f1 CL variants --- data/registers/rcc_f1.yaml | 4 +- data/registers/rcc_f1cl.yaml | 1138 ++++++++++++++++++++++++++++++++++ stm32data/__main__.py | 3 +- 3 files changed, 1142 insertions(+), 3 deletions(-) create mode 100644 data/registers/rcc_f1cl.yaml diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml index 4af8492..7564024 100644 --- a/data/registers/rcc_f1.yaml +++ b/data/registers/rcc_f1.yaml @@ -873,7 +873,7 @@ enum/I2S2SRC: description: PLL3 VCO clock selected as I2S clock entry value: 1 enum/MCO: - bit_size: 4 + bit_size: 3 variants: - name: NoMCO description: "MCO output disabled, no clock on MCO" @@ -888,7 +888,7 @@ enum/MCO: description: HSE oscillator clock selected value: 6 - name: PLL - description: "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)" + description: "PLL clock divided by 2 selected" value: 7 enum/OTGFSPRE: bit_size: 1 diff --git a/data/registers/rcc_f1cl.yaml b/data/registers/rcc_f1cl.yaml new file mode 100644 index 0000000..93d8031 --- /dev/null +++ b/data/registers/rcc_f1cl.yaml @@ -0,0 +1,1138 @@ +--- +block/RCC: + description: Reset and clock control + items: + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: CFGR + description: Clock configuration register (RCC_CFGR) + byte_offset: 4 + fieldset: CFGR + - name: CIR + description: Clock interrupt register (RCC_CIR) + byte_offset: 8 + fieldset: CIR + - name: APB2RSTR + description: APB2 peripheral reset register (RCC_APB2RSTR) + byte_offset: 12 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register (RCC_APB1RSTR) + byte_offset: 16 + fieldset: APB1RSTR + - name: AHBENR + description: AHB Peripheral Clock enable register (RCC_AHBENR) + byte_offset: 20 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register (RCC_APB2ENR) + byte_offset: 24 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register (RCC_APB1ENR) + byte_offset: 28 + fieldset: APB1ENR + - name: BDCR + description: Backup domain control register (RCC_BDCR) + byte_offset: 32 + fieldset: BDCR + - name: CSR + description: Control/status register (RCC_CSR) + byte_offset: 36 + fieldset: CSR + - name: AHBRSTR + description: AHB peripheral clock reset register (RCC_AHBRSTR) + byte_offset: 40 + fieldset: AHBRSTR + - name: CFGR2 + description: Clock configuration register 2 + byte_offset: 44 + fieldset: CFGR2 +fieldset/AHBENR: + description: AHB Peripheral Clock enable register (RCC_AHBENR) + fields: + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: SRAMEN + description: SRAM interface clock enable + bit_offset: 2 + bit_size: 1 + - name: FLASHEN + description: FLASH clock enable + bit_offset: 4 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 6 + bit_size: 1 + - name: FSMCEN + description: FSMC clock enable + bit_offset: 8 + bit_size: 1 + - name: SDIOEN + description: SDIO clock enable + bit_offset: 10 + bit_size: 1 + - name: USB_OTG_FSEN + description: USB OTG FS clock enable + bit_offset: 12 + bit_size: 1 + - name: ETHMACEN + description: Ethernet MAC clock enable + bit_offset: 14 + bit_size: 1 + - name: ETHMACTXEN + description: Ethernet MAC TX clock enable + bit_offset: 15 + bit_size: 1 + - name: ETHMACRXEN + description: Ethernet MAC RX clock enable + bit_offset: 16 + bit_size: 1 +fieldset/AHBRSTR: + description: AHB peripheral clock reset register (RCC_AHBRSTR) + fields: + - name: USB_OTG_FSRST + description: USB OTG FS reset + bit_offset: 12 + bit_size: 1 + - name: ETHMACRST + description: Ethernet MAC reset + bit_offset: 14 + bit_size: 1 +fieldset/APB1ENR: + description: APB1 peripheral clock enable register (RCC_APB1ENR) + fields: + - name: TIM2EN + description: Timer 2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: Timer 4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: Timer 5 clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: Timer 7 clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: Timer 12 clock enable + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: Timer 13 clock enable + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: Timer 14 clock enable + bit_offset: 8 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI 2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI 3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART 3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART 4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART 5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C 2 clock enable + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: USB clock enable + bit_offset: 23 + bit_size: 1 + - name: CAN1EN + description: CAN1 clock enable + bit_offset: 25 + bit_size: 1 + - name: CANEN + description: CAN clock enable + bit_offset: 25 + bit_size: 1 + - name: CAN2EN + description: CAN2 clock enable + bit_offset: 26 + bit_size: 1 + - name: BKPEN + description: Backup interface clock enable + bit_offset: 27 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: CECEN + description: CEC clock enable + bit_offset: 30 + bit_size: 1 +fieldset/APB1RSTR: + description: APB1 peripheral reset register (RCC_APB1RSTR) + fields: + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: Timer 4 reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: Timer 5 reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: Timer 6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: Timer 7 reset + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: Timer 12 reset + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: Timer 13 reset + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: Timer 14 reset + bit_offset: 8 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART 3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: USART 4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: USART 5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: USB reset + bit_offset: 23 + bit_size: 1 + - name: CAN1RST + description: CAN1 reset + bit_offset: 25 + bit_size: 1 + - name: CANRST + description: CAN reset + bit_offset: 25 + bit_size: 1 + - name: CAN2RST + description: CAN2 reset + bit_offset: 26 + bit_size: 1 + - name: BKPRST + description: Backup interface reset + bit_offset: 27 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 + - name: CECRST + description: CEC reset + bit_offset: 30 + bit_size: 1 +fieldset/APB2ENR: + description: APB2 peripheral clock enable register (RCC_APB2ENR) + fields: + - name: AFIOEN + description: Alternate function I/O clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOAEN + description: I/O port A clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIOBEN + description: I/O port B clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOCEN + description: I/O port C clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIODEN + description: I/O port D clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOEEN + description: I/O port E clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOFEN + description: I/O port F clock enable + bit_offset: 7 + bit_size: 1 + - name: GPIOGEN + description: I/O port G clock enable + bit_offset: 8 + bit_size: 1 + - name: ADC1EN + description: ADC 1 interface clock enable + bit_offset: 9 + bit_size: 1 + - name: ADC2EN + description: ADC 2 interface clock enable + bit_offset: 10 + bit_size: 1 + - name: TIM1EN + description: TIM1 Timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable + bit_offset: 12 + bit_size: 1 + - name: TIM8EN + description: TIM8 Timer clock enable + bit_offset: 13 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 + - name: ADC3EN + description: ADC3 interface clock enable + bit_offset: 15 + bit_size: 1 + - name: TIM15EN + description: TIM15 Timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 Timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 Timer clock enable + bit_offset: 18 + bit_size: 1 + - name: TIM9EN + description: TIM9 Timer clock enable + bit_offset: 19 + bit_size: 1 + - name: TIM10EN + description: TIM10 Timer clock enable + bit_offset: 20 + bit_size: 1 + - name: TIM11EN + description: TIM11 Timer clock enable + bit_offset: 21 + bit_size: 1 +fieldset/APB2RSTR: + description: APB2 peripheral reset register (RCC_APB2RSTR) + fields: + - name: AFIORST + description: Alternate function I/O reset + bit_offset: 0 + bit_size: 1 + - name: GPIOARST + description: IO port A reset + bit_offset: 2 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 3 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 4 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 5 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 6 + bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 7 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 8 + bit_size: 1 + - name: ADC1RST + description: ADC 1 interface reset + bit_offset: 9 + bit_size: 1 + - name: ADC2RST + description: ADC 2 interface reset + bit_offset: 10 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: TIM8RST + description: TIM8 timer reset + bit_offset: 13 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: ADC3RST + description: ADC 3 interface reset + bit_offset: 15 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: TIM9RST + description: TIM9 timer reset + bit_offset: 19 + bit_size: 1 + - name: TIM10RST + description: TIM10 timer reset + bit_offset: 20 + bit_size: 1 + - name: TIM11RST + description: TIM11 timer reset + bit_offset: 21 + bit_size: 1 +fieldset/BDCR: + description: Backup domain control register (RCC_BDCR) + fields: + - name: LSEON + description: External Low Speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External Low Speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: External Low Speed oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 +fieldset/CFGR: + description: Clock configuration register (RCC_3FGR) + fields: + - name: SW + description: System clock Switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System Clock Switch Status + bit_offset: 2 + bit_size: 2 + enum_read: SWSR + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE1 + - name: PPRE2 + description: APB High speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE1 + - name: ADCPRE + description: ADC prescaler + bit_offset: 14 + bit_size: 2 + enum: ADCPRE + - name: PLLSRC + description: PLL entry clock source + bit_offset: 16 + bit_size: 1 + enum: PLLSRC + - name: PLLXTPRE + description: HSE divider for PLL entry + bit_offset: 17 + bit_size: 1 + enum: PLLXTPRE + - name: PLLMUL + description: PLL Multiplication Factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: OTGFSPRE + description: USB OTG FS prescaler + bit_offset: 22 + bit_size: 1 + enum: OTGFSPRE + - name: USBPRE + description: USB prescaler + bit_offset: 22 + bit_size: 1 + enum: USBPRE + - name: MCO + description: Microcontroller clock output + bit_offset: 24 + bit_size: 4 + enum: MCO +fieldset/CFGR2: + description: Clock configuration register2 (RCC_CFGR2) + fields: + - name: PREDIV1 + description: PREDIV1 division factor + bit_offset: 0 + bit_size: 4 + enum: PREDIV1 + - name: PREDIV2 + description: PREDIV2 division factor + bit_offset: 4 + bit_size: 4 + enum: PREDIV1 + - name: PLL2MUL + description: PLL2 Multiplication Factor + bit_offset: 8 + bit_size: 4 + enum: PLL2MUL + - name: PLL3MUL + description: PLL3 Multiplication Factor + bit_offset: 12 + bit_size: 4 + enum: PLL2MUL + - name: PREDIV1SRC + description: PREDIV1 entry clock source + bit_offset: 16 + bit_size: 1 + enum: PREDIV1SRC + - name: I2S2SRC + description: I2S2 clock source + bit_offset: 17 + bit_size: 1 + enum: I2S2SRC + - name: I2S3SRC + description: I2S3 clock source + bit_offset: 18 + bit_size: 1 + enum: I2S2SRC +fieldset/CIR: + description: Clock interrupt register (RCC_CIR) + fields: + - name: LSIRDYF + description: LSI Ready Interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE Ready Interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI Ready Interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE Ready Interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: PLL Ready Interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLL2RDYF + description: PLL2 Ready Interrupt flag + bit_offset: 5 + bit_size: 1 + - name: PLL3RDYF + description: PLL3 Ready Interrupt flag + bit_offset: 6 + bit_size: 1 + - name: CSSF + description: Clock Security System Interrupt flag + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI Ready Interrupt Enable + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE Ready Interrupt Enable + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI Ready Interrupt Enable + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE Ready Interrupt Enable + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: PLL Ready Interrupt Enable + bit_offset: 12 + bit_size: 1 + - name: PLL2RDYIE + description: PLL2 Ready Interrupt Enable + bit_offset: 13 + bit_size: 1 + - name: PLL3RDYIE + description: PLL3 Ready Interrupt Enable + bit_offset: 14 + bit_size: 1 + - name: LSIRDYC + description: LSI Ready Interrupt Clear + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE Ready Interrupt Clear + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI Ready Interrupt Clear + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE Ready Interrupt Clear + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: PLL Ready Interrupt Clear + bit_offset: 20 + bit_size: 1 + - name: PLL2RDYC + description: PLL2 Ready Interrupt Clear + bit_offset: 21 + bit_size: 1 + - name: PLL3RDYC + description: PLL3 Ready Interrupt Clear + bit_offset: 22 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 +fieldset/CR: + description: Clock control register + fields: + - name: HSION + description: Internal High Speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal High Speed clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSITRIM + description: Internal High Speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal High Speed clock Calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: External High Speed clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: External High Speed clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: External High Speed clock Bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 + - name: PLL2ON + description: PLL2 enable + bit_offset: 26 + bit_size: 1 + - name: PLL2RDY + description: PLL2 clock ready flag + bit_offset: 27 + bit_size: 1 + - name: PLL3ON + description: PLL3 enable + bit_offset: 28 + bit_size: 1 + - name: PLL3RDY + description: PLL3 clock ready flag + bit_offset: 29 + bit_size: 1 +fieldset/CSR: + description: Control/status register (RCC_CSR) + fields: + - name: LSION + description: Internal low speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 +enum/ADCPRE: + bit_size: 2 + variants: + - name: Div2 + description: PCLK2 divided by 2 + value: 0 + - name: Div4 + description: PCLK2 divided by 4 + value: 1 + - name: Div6 + description: PCLK2 divided by 8 + value: 2 + - name: Div8 + description: PCLK2 divided by 16 + value: 3 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 +enum/I2S2SRC: + bit_size: 1 + variants: + - name: SYSCLK + description: System clock (SYSCLK) selected as I2S clock entry + value: 0 + - name: PLL3 + description: PLL3 VCO clock selected as I2S clock entry + value: 1 +enum/MCO: + bit_size: 4 + variants: + - name: NoMCO + description: "MCO output disabled, no clock on MCO" + value: 0 + - name: SYSCLK + description: System clock selected + value: 4 + - name: HSI + description: HSI oscillator clock selected + value: 5 + - name: HSE + description: HSE oscillator clock selected + value: 6 + - name: PLL + description: "PLL clock divided by 2 selected" + value: 7 + - name: PLL2 + description: "PLL2 clock selected" + value: 8 + - name: PLL3DIV2 + description: "PLL3 clock divided by 2 selected" + value: 9 + - name: XT1 + description: "XT1 external oscillator selected" + value: 10 + - name: PLL3 + description: "PLL3 clock selected" + value: 11 +enum/OTGFSPRE: + bit_size: 1 + variants: + - name: DIV1_5 + description: PLL clock is divided by 1.5 + value: 0 + - name: DIV1 + description: PLL clock is not divided + value: 1 +enum/PLL2MUL: + bit_size: 4 + variants: + - name: Mul8 + description: PLL clock entry x8 + value: 6 + - name: Mul9 + description: PLL clock entry x9 + value: 7 + - name: Mul10 + description: PLL clock entry x10 + value: 8 + - name: Mul11 + description: PLL clock entry x11 + value: 9 + - name: Mul12 + description: PLL clock entry x12 + value: 10 + - name: Mul13 + description: PLL clock entry x13 + value: 11 + - name: Mul14 + description: PLL clock entry x14 + value: 12 + - name: Mul16 + description: PLL clock entry x16 + value: 14 + - name: Mul20 + description: PLL clock entry x20 + value: 15 +enum/PLLMUL: + bit_size: 4 + variants: + - name: Mul2 + description: PLL input clock x2 + value: 0 + - name: Mul3 + description: PLL input clock x3 + value: 1 + - name: Mul4 + description: PLL input clock x4 + value: 2 + - name: Mul5 + description: PLL input clock x5 + value: 3 + - name: Mul6 + description: PLL input clock x6 + value: 4 + - name: Mul7 + description: PLL input clock x7 + value: 5 + - name: Mul8 + description: PLL input clock x8 + value: 6 + - name: Mul9 + description: PLL input clock x9 + value: 7 + - name: Mul10 + description: PLL input clock x10 + value: 8 + - name: Mul11 + description: PLL input clock x11 + value: 9 + - name: Mul12 + description: PLL input clock x12 + value: 10 + - name: Mul13 + description: PLL input clock x13 + value: 11 + - name: Mul14 + description: PLL input clock x14 + value: 12 + - name: Mul15 + description: PLL input clock x15 + value: 13 + - name: Mul16 + description: PLL input clock x16 + value: 14 + - name: Mul16x + description: PLL input clock x16 + value: 15 +enum/PLLSRC: + bit_size: 1 + variants: + - name: HSI_Div2 + description: HSI divided by 2 selected as PLL input clock + value: 0 + - name: HSE_Div_PREDIV + description: HSE divided by PREDIV selected as PLL input clock + value: 1 +enum/PLLXTPRE: + bit_size: 1 + variants: + - name: Div1 + description: HSE clock not divided + value: 0 + - name: Div2 + description: HSE clock divided by 2 + value: 1 +enum/PPRE1: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/PREDIV1: + bit_size: 4 + variants: + - name: Div1 + description: PREDIV input clock not divided + value: 0 + - name: Div2 + description: PREDIV input clock divided by 2 + value: 1 + - name: Div3 + description: PREDIV input clock divided by 3 + value: 2 + - name: Div4 + description: PREDIV input clock divided by 4 + value: 3 + - name: Div5 + description: PREDIV input clock divided by 5 + value: 4 + - name: Div6 + description: PREDIV input clock divided by 6 + value: 5 + - name: Div7 + description: PREDIV input clock divided by 7 + value: 6 + - name: Div8 + description: PREDIV input clock divided by 8 + value: 7 + - name: Div9 + description: PREDIV input clock divided by 9 + value: 8 + - name: Div10 + description: PREDIV input clock divided by 10 + value: 9 + - name: Div11 + description: PREDIV input clock divided by 11 + value: 10 + - name: Div12 + description: PREDIV input clock divided by 12 + value: 11 + - name: Div13 + description: PREDIV input clock divided by 13 + value: 12 + - name: Div14 + description: PREDIV input clock divided by 14 + value: 13 + - name: Div15 + description: PREDIV input clock divided by 15 + value: 14 + - name: Div16 + description: PREDIV input clock divided by 16 + value: 15 +enum/PREDIV1SRC: + bit_size: 1 + variants: + - name: HSE + description: HSE oscillator clock selected as PREDIV1 clock entry + value: 0 + - name: PLL2 + description: PLL2 selected as PREDIV1 clock entry + value: 1 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 +enum/SW: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as system clock + value: 0 + - name: HSE + description: HSE selected as system clock + value: 1 + - name: PLL + description: PLL selected as system clock + value: 2 +enum/SWSR: + bit_size: 2 + variants: + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL + description: PLL used as system clock + value: 2 +enum/USBPRE: + bit_size: 1 + variants: + - name: DIV1_5 + description: PLL clock is divided by 1.5 + value: 0 + - name: DIV1 + description: PLL clock is not divided + value: 1 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 4fdd096..3202bbb 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -168,7 +168,8 @@ perimap = [ ('.*:USB_OTG_HS:otghs1_v1_.*', ('otghs', 'v1', 'OTG_HS')), ('STM32F0.*:RCC:.*', ('rcc', 'f0', 'RCC')), - ('STM32F1.*:RCC:.*', ('rcc', 'f1', 'RCC')), + ('STM32F10[0123].*:RCC:.*', ('rcc', 'f1', 'RCC')), + ('STM32F10[57].*:RCC:.*', ('rcc', 'f1cl', 'RCC')), ('STM32F2.*:RCC:.*', ('rcc', 'f2', 'RCC')), ('STM32F3.*:RCC:.*', ('rcc', 'f3', 'RCC')), ('STM32F410.*:RCC:.*', ('rcc', 'f410', 'RCC')), From 121e5bc92bdfb3402c9cc0b314451237be50fac3 Mon Sep 17 00:00:00 2001 From: David Lenfesty Date: Tue, 26 Apr 2022 10:09:28 -0600 Subject: [PATCH 18/35] Generate ethernet peripherals for f2 and f4 These are eth v1b, according to stm32-rs it should have the same register changes as v1c, so I just copied it over. --- data/registers/eth_v1b.yaml | 2220 +++++++++++++++++++++++++++++++++++ stm32data/__main__.py | 1 + 2 files changed, 2221 insertions(+) create mode 100644 data/registers/eth_v1b.yaml diff --git a/data/registers/eth_v1b.yaml b/data/registers/eth_v1b.yaml new file mode 100644 index 0000000..fec0571 --- /dev/null +++ b/data/registers/eth_v1b.yaml @@ -0,0 +1,2220 @@ +--- +block/ETH: + description: Ethernet Peripheral + items: + - name: ETHERNET_MAC + description: "Ethernet: media access control (MAC)" + byte_offset: 0 + block: ETHERNET_MAC + - name: ETHERNET_PTP + description: "Ethernet: Precision Time Protocol (PTP)" + byte_offset: 1792 + block: ETHERNET_PTP + - name: ETHERNET_DMA + description: "Ethernet: DMA mode register (DMA)" + byte_offset: 4096 + block: ETHERNET_DMA +block/ETHERNET_DMA: + description: "Ethernet: DMA controller operation" + items: + - name: DMABMR + description: Ethernet DMA bus mode register + byte_offset: 0 + fieldset: DMABMR + - name: DMATPDR + description: Ethernet DMA transmit poll demand register + byte_offset: 4 + fieldset: DMATPDR + - name: DMARPDR + description: EHERNET DMA receive poll demand register + byte_offset: 8 + fieldset: DMARPDR + - name: DMARDLAR + description: Ethernet DMA receive descriptor list address register + byte_offset: 12 + fieldset: DMARDLAR + - name: DMATDLAR + description: Ethernet DMA transmit descriptor list address register + byte_offset: 16 + fieldset: DMATDLAR + - name: DMASR + description: Ethernet DMA status register + byte_offset: 20 + fieldset: DMASR + - name: DMAOMR + description: Ethernet DMA operation mode register + byte_offset: 24 + fieldset: DMAOMR + - name: DMAIER + description: Ethernet DMA interrupt enable register + byte_offset: 28 + fieldset: DMAIER + - name: DMAMFBOCR + description: Ethernet DMA missed frame and buffer overflow counter register + byte_offset: 32 + fieldset: DMAMFBOCR + - name: DMARSWTR + description: Ethernet DMA receive status watchdog timer register + byte_offset: 36 + fieldset: DMARSWTR + - name: DMACHTDR + description: Ethernet DMA current host transmit descriptor register + byte_offset: 72 + access: Read + fieldset: DMACHTDR + - name: DMACHRDR + description: Ethernet DMA current host receive descriptor register + byte_offset: 76 + access: Read + fieldset: DMACHRDR + - name: DMACHTBAR + description: Ethernet DMA current host transmit buffer address register + byte_offset: 80 + access: Read + fieldset: DMACHTBAR + - name: DMACHRBAR + description: Ethernet DMA current host receive buffer address register + byte_offset: 84 + access: Read + fieldset: DMACHRBAR +block/ETHERNET_MAC: + description: "Ethernet: media access control (MAC)" + items: + - name: MACCR + description: Ethernet MAC configuration register + byte_offset: 0 + fieldset: MACCR + - name: MACFFR + description: Ethernet MAC frame filter register + byte_offset: 4 + fieldset: MACFFR + - name: MACHTHR + description: Ethernet MAC hash table high register + byte_offset: 8 + fieldset: MACHTHR + - name: MACHTLR + description: Ethernet MAC hash table low register + byte_offset: 12 + fieldset: MACHTLR + - name: MACMIIAR + description: Ethernet MAC MII address register + byte_offset: 16 + fieldset: MACMIIAR + - name: MACMIIDR + description: Ethernet MAC MII data register + byte_offset: 20 + fieldset: MACMIIDR + - name: MACFCR + description: Ethernet MAC flow control register + byte_offset: 24 + fieldset: MACFCR + - name: MACVLANTR + description: Ethernet MAC VLAN tag register + byte_offset: 28 + fieldset: MACVLANTR + - name: MACRWUFFR + description: Ethernet MAC remote wakeup frame filter register + byte_offset: 40 + - name: MACPMTCSR + description: Ethernet MAC PMT control and status register + byte_offset: 44 + fieldset: MACPMTCSR + - name: MACDBGR + description: Ethernet MAC debug register + byte_offset: 52 + access: Read + fieldset: MACDBGR + - name: MACSR + description: Ethernet MAC interrupt status register + byte_offset: 56 + fieldset: MACSR + - name: MACIMR + description: Ethernet MAC interrupt mask register + byte_offset: 60 + fieldset: MACIMR + - name: MACA0HR + description: Ethernet MAC address 0 high register + byte_offset: 64 + fieldset: MACA0HR + - name: MACA0LR + description: Ethernet MAC address 0 low register + byte_offset: 68 + fieldset: MACA0LR + - name: MACA1HR + description: Ethernet MAC address 1 high register + byte_offset: 72 + fieldset: MACA1HR + - name: MACA1LR + description: Ethernet MAC address1 low register + byte_offset: 76 + fieldset: MACA1LR + - name: MACA2HR + description: Ethernet MAC address 2 high register + byte_offset: 80 + fieldset: MACA2HR + - name: MACA2LR + description: Ethernet MAC address 2 low register + byte_offset: 84 + fieldset: MACA2LR + - name: MACA3HR + description: Ethernet MAC address 3 high register + byte_offset: 88 + fieldset: MACA3HR + - name: MACA3LR + description: Ethernet MAC address 3 low register + byte_offset: 92 + fieldset: MACA3LR + - name: MMCCR + description: Ethernet MMC control register + byte_offset: 256 + fieldset: MMCCR + - name: MMCRIR + description: Ethernet MMC receive interrupt register + byte_offset: 260 + fieldset: MMCRIR + - name: MMCTIR + description: Ethernet MMC transmit interrupt register + byte_offset: 264 + access: Read + fieldset: MMCTIR + - name: MMCRIMR + description: Ethernet MMC receive interrupt mask register + byte_offset: 268 + fieldset: MMCRIMR + - name: MMCTIMR + description: Ethernet MMC transmit interrupt mask register + byte_offset: 272 + fieldset: MMCTIMR + - name: MMCTGFSCCR + description: Ethernet MMC transmitted good frames after a single collision counter + byte_offset: 332 + access: Read + fieldset: MMCTGFSCCR + - name: MMCTGFMSCCR + description: Ethernet MMC transmitted good frames after more than a single collision + byte_offset: 336 + access: Read + fieldset: MMCTGFMSCCR + - name: MMCTGFCR + description: Ethernet MMC transmitted good frames counter register + byte_offset: 360 + access: Read + fieldset: MMCTGFCR + - name: MMCRFCECR + description: Ethernet MMC received frames with CRC error counter register + byte_offset: 404 + access: Read + fieldset: MMCRFCECR + - name: MMCRFAECR + description: Ethernet MMC received frames with alignment error counter register + byte_offset: 408 + access: Read + fieldset: MMCRFAECR + - name: MMCRGUFCR + description: MMC received good unicast frames counter register + byte_offset: 452 + access: Read + fieldset: MMCRGUFCR +block/ETHERNET_PTP: + description: "Ethernet: Precision time protocol" + items: + - name: PTPTSCR + description: Ethernet PTP time stamp control register + byte_offset: 0 + fieldset: PTPTSCR + - name: PTPSSIR + description: Ethernet PTP subsecond increment register + byte_offset: 4 + fieldset: PTPSSIR + - name: PTPTSHR + description: Ethernet PTP time stamp high register + byte_offset: 8 + access: Read + fieldset: PTPTSHR + - name: PTPTSLR + description: Ethernet PTP time stamp low register + byte_offset: 12 + access: Read + fieldset: PTPTSLR + - name: PTPTSHUR + description: Ethernet PTP time stamp high update register + byte_offset: 16 + fieldset: PTPTSHUR + - name: PTPTSLUR + description: Ethernet PTP time stamp low update register + byte_offset: 20 + fieldset: PTPTSLUR + - name: PTPTSAR + description: Ethernet PTP time stamp addend register + byte_offset: 24 + fieldset: PTPTSAR + - name: PTPTTHR + description: Ethernet PTP target time high register + byte_offset: 28 + fieldset: PTPTTHR + - name: PTPTTLR + description: Ethernet PTP target time low register + byte_offset: 32 + fieldset: PTPTTLR + - name: PTPTSSR + description: Ethernet PTP time stamp status register + byte_offset: 40 + access: Read + fieldset: PTPTSSR + - name: PTPPPSCR + description: Ethernet PTP PPS control register + byte_offset: 44 + access: Read + fieldset: PTPPPSCR +fieldset/DMABMR: + description: Ethernet DMA bus mode register + fields: + - name: SR + description: Software reset + bit_offset: 0 + bit_size: 1 + - name: DA + description: DMA arbitration + bit_offset: 1 + bit_size: 1 + enum: DA + - name: DSL + description: Descriptor skip length + bit_offset: 2 + bit_size: 5 + - name: EDFE + description: Enhanced descriptor format enable + bit_offset: 7 + bit_size: 1 + enum: EDFE + - name: PBL + description: Programmable burst length + bit_offset: 8 + bit_size: 6 + enum: PBL + - name: PM + description: Rx-Tx priority ratio + bit_offset: 14 + bit_size: 2 + enum: PriorityRxOverTx + - name: FB + description: Fixed burst + bit_offset: 16 + bit_size: 1 + enum: FB + - name: RDP + description: Rx DMA PBL + bit_offset: 17 + bit_size: 6 + enum: RDP + - name: USP + description: Use separate PBL + bit_offset: 23 + bit_size: 1 + enum: USP + - name: FPM + description: 4xPBL mode + bit_offset: 24 + bit_size: 1 + enum: FPM + - name: AAB + description: Address-aligned beats + bit_offset: 25 + bit_size: 1 + enum: AAB + - name: MB + description: Mixed burst + bit_offset: 26 + bit_size: 1 + enum: MB +fieldset/DMACHRBAR: + description: Ethernet DMA current host receive buffer address register + fields: + - name: HRBAP + description: Host receive buffer address pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACHRDR: + description: Ethernet DMA current host receive descriptor register + fields: + - name: HRDAP + description: Host receive descriptor address pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACHTBAR: + description: Ethernet DMA current host transmit buffer address register + fields: + - name: HTBAP + description: Host transmit buffer address pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACHTDR: + description: Ethernet DMA current host transmit descriptor register + fields: + - name: HTDAP + description: Host transmit descriptor address pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMAIER: + description: Ethernet DMA interrupt enable register + fields: + - name: TIE + description: Transmit interrupt enable + bit_offset: 0 + bit_size: 1 + - name: TPSIE + description: Transmit process stopped interrupt enable + bit_offset: 1 + bit_size: 1 + - name: TBUIE + description: Transmit buffer unavailable interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TJTIE + description: Transmit jabber timeout interrupt enable + bit_offset: 3 + bit_size: 1 + - name: ROIE + description: Receive overflow interrupt enable + bit_offset: 4 + bit_size: 1 + - name: TUIE + description: Transmit underflow interrupt enable + bit_offset: 5 + bit_size: 1 + - name: RIE + description: Receive interrupt enable + bit_offset: 6 + bit_size: 1 + - name: RBUIE + description: Receive buffer unavailable interrupt enable + bit_offset: 7 + bit_size: 1 + - name: RPSIE + description: Receive process stopped interrupt enable + bit_offset: 8 + bit_size: 1 + - name: RWTIE + description: Receive watchdog timeout interrupt enable + bit_offset: 9 + bit_size: 1 + - name: ETIE + description: Early transmit interrupt enable + bit_offset: 10 + bit_size: 1 + - name: FBEIE + description: Fatal bus error interrupt enable + bit_offset: 13 + bit_size: 1 + - name: ERIE + description: Early receive interrupt enable + bit_offset: 14 + bit_size: 1 + - name: AISE + description: Abnormal interrupt summary enable + bit_offset: 15 + bit_size: 1 + - name: NISE + description: Normal interrupt summary enable + bit_offset: 16 + bit_size: 1 +fieldset/DMAMFBOCR: + description: Ethernet DMA missed frame and buffer overflow counter register + fields: + - name: MFC + description: Missed frames by the controller + bit_offset: 0 + bit_size: 16 + - name: OMFC + description: Overflow bit for missed frame counter + bit_offset: 16 + bit_size: 1 + - name: MFA + description: Missed frames by the application + bit_offset: 17 + bit_size: 11 + - name: OFOC + description: Overflow bit for FIFO overflow counter + bit_offset: 28 + bit_size: 1 +fieldset/DMAOMR: + description: Ethernet DMA operation mode register + fields: + - name: SR + description: Start/stop receive + bit_offset: 1 + bit_size: 1 + enum: DMAOMR_SR + - name: OSF + description: Operate on second frame + bit_offset: 2 + bit_size: 1 + - name: RTC + description: Receive threshold control + bit_offset: 3 + bit_size: 2 + enum: RTC + - name: FUGF + description: Forward undersized good frames + bit_offset: 6 + bit_size: 1 + enum: FUGF + - name: FEF + description: Forward error frames + bit_offset: 7 + bit_size: 1 + enum: FEF + - name: ST + description: Start/stop transmission + bit_offset: 13 + bit_size: 1 + enum: ST + - name: TTC + description: Transmit threshold control + bit_offset: 14 + bit_size: 3 + enum: TTC + - name: FTF + description: Flush transmit FIFO + bit_offset: 20 + bit_size: 1 + enum: FTF + - name: TSF + description: Transmit store and forward + bit_offset: 21 + bit_size: 1 + enum: TSF + - name: DFRF + description: Disable flushing of received frames + bit_offset: 24 + bit_size: 1 + - name: RSF + description: Receive store and forward + bit_offset: 25 + bit_size: 1 + enum: RSF + - name: DTCEFD + description: Dropping of TCP/IP checksum error frames disable + bit_offset: 26 + bit_size: 1 + enum: DTCEFD +fieldset/DMARDLAR: + description: Ethernet DMA receive descriptor list address register + fields: + - name: SRL + description: Start of receive list + bit_offset: 0 + bit_size: 32 +fieldset/DMARPDR: + description: EHERNET DMA receive poll demand register + fields: + - name: RPD + description: Receive poll demand + bit_offset: 0 + bit_size: 32 + enum: RPD +fieldset/DMARSWTR: + description: Ethernet DMA receive status watchdog timer register + fields: + - name: RSWTC + description: Receive status watchdog timer count + bit_offset: 0 + bit_size: 8 +fieldset/DMASR: + description: Ethernet DMA status register + fields: + - name: TS + description: Transmit status + bit_offset: 0 + bit_size: 1 + - name: TPSS + description: Transmit process stopped status + bit_offset: 1 + bit_size: 1 + - name: TBUS + description: Transmit buffer unavailable status + bit_offset: 2 + bit_size: 1 + - name: TJTS + description: Transmit jabber timeout status + bit_offset: 3 + bit_size: 1 + - name: ROS + description: Receive overflow status + bit_offset: 4 + bit_size: 1 + - name: TUS + description: Transmit underflow status + bit_offset: 5 + bit_size: 1 + - name: RS + description: Receive status + bit_offset: 6 + bit_size: 1 + - name: RBUS + description: Receive buffer unavailable status + bit_offset: 7 + bit_size: 1 + - name: RPSS + description: Receive process stopped status + bit_offset: 8 + bit_size: 1 + - name: PWTS + description: PWTS + bit_offset: 9 + bit_size: 1 + - name: ETS + description: Early transmit status + bit_offset: 10 + bit_size: 1 + - name: FBES + description: Fatal bus error status + bit_offset: 13 + bit_size: 1 + - name: ERS + description: Early receive status + bit_offset: 14 + bit_size: 1 + - name: AIS + description: Abnormal interrupt summary + bit_offset: 15 + bit_size: 1 + - name: NIS + description: Normal interrupt summary + bit_offset: 16 + bit_size: 1 + - name: RPS + description: Receive process state + bit_offset: 17 + bit_size: 3 + enum: RPS + - name: TPS + description: Transmit process state + bit_offset: 20 + bit_size: 3 + enum: TPS + - name: EBS + description: Error bits status + bit_offset: 23 + bit_size: 3 + - name: MMCS + description: MMC status + bit_offset: 27 + bit_size: 1 + - name: PMTS + description: PMT status + bit_offset: 28 + bit_size: 1 + - name: TSTS + description: Time stamp trigger status + bit_offset: 29 + bit_size: 1 +fieldset/DMATDLAR: + description: Ethernet DMA transmit descriptor list address register + fields: + - name: STL + description: Start of transmit list + bit_offset: 0 + bit_size: 32 +fieldset/DMATPDR: + description: Ethernet DMA transmit poll demand register + fields: + - name: TPD + description: Transmit poll demand + bit_offset: 0 + bit_size: 32 + enum: TPD +fieldset/MACA0HR: + description: Ethernet MAC address 0 high register + fields: + - name: MACA0H + description: MAC address0 high + bit_offset: 0 + bit_size: 16 + - name: MO + description: Always 1 + bit_offset: 31 + bit_size: 1 +fieldset/MACA0LR: + description: Ethernet MAC address 0 low register + fields: + - name: MACA0L + description: "0" + bit_offset: 0 + bit_size: 32 +fieldset/MACA1HR: + description: Ethernet MAC address 1 high register + fields: + - name: MACA1H + description: MACA1H + bit_offset: 0 + bit_size: 16 + - name: MBC + description: MBC + bit_offset: 24 + bit_size: 6 + - name: SA + description: SA + bit_offset: 30 + bit_size: 1 + enum: MACAHR_SA + - name: AE + description: AE + bit_offset: 31 + bit_size: 1 + enum: MACAHR_AE +fieldset/MACA1LR: + description: Ethernet MAC address1 low register + fields: + - name: MACA1L + description: MACA1LR + bit_offset: 0 + bit_size: 32 +fieldset/MACA2HR: + description: Ethernet MAC address 2 high register + fields: + - name: MACA2H + description: MAC2AH + bit_offset: 0 + bit_size: 16 + - name: MBC + description: MBC + bit_offset: 24 + bit_size: 6 + - name: SA + description: SA + bit_offset: 30 + bit_size: 1 + enum: MACAHR_SA + - name: AE + description: AE + bit_offset: 31 + bit_size: 1 + enum: MACAHR_AE +fieldset/MACA2LR: + description: Ethernet MAC address 2 low register + fields: + - name: MACA2L + description: MACA2L + bit_offset: 0 + bit_size: 32 +fieldset/MACA3HR: + description: Ethernet MAC address 3 high register + fields: + - name: MACA3H + description: MACA3H + bit_offset: 0 + bit_size: 16 + - name: MBC + description: MBC + bit_offset: 24 + bit_size: 6 + - name: SA + description: SA + bit_offset: 30 + bit_size: 1 + enum: MACAHR_SA + - name: AE + description: AE + bit_offset: 31 + bit_size: 1 + enum: MACAHR_AE +fieldset/MACA3LR: + description: Ethernet MAC address 3 low register + fields: + - name: MACA3L + description: MBCA3L + bit_offset: 0 + bit_size: 32 +fieldset/MACCR: + description: Ethernet MAC configuration register + fields: + - name: RE + description: Receiver enable + bit_offset: 2 + bit_size: 1 + - name: TE + description: Transmitter enable + bit_offset: 3 + bit_size: 1 + - name: DC + description: Deferral check + bit_offset: 4 + bit_size: 1 + enum: DC + - name: BL + description: Back-off limit + bit_offset: 5 + bit_size: 2 + enum: BL + - name: APCS + description: Automatic pad/CRC stripping + bit_offset: 7 + bit_size: 1 + enum: APCS + - name: RD + description: Retry disable + bit_offset: 9 + bit_size: 1 + enum: RD + - name: IPCO + description: IPv4 checksum offload + bit_offset: 10 + bit_size: 1 + enum: IPCO + - name: DM + description: Duplex mode + bit_offset: 11 + bit_size: 1 + enum: DM + - name: LM + description: Loopback mode + bit_offset: 12 + bit_size: 1 + enum: LM + - name: ROD + description: Receive own disable + bit_offset: 13 + bit_size: 1 + enum: ROD + - name: FES + description: Fast Ethernet speed + bit_offset: 14 + bit_size: 1 + enum: FES + - name: CSD + description: Carrier sense disable + bit_offset: 16 + bit_size: 1 + enum: CSD + - name: IFG + description: Interframe gap + bit_offset: 17 + bit_size: 3 + enum: IFG + - name: JD + description: Jabber disable + bit_offset: 22 + bit_size: 1 + enum: JD + - name: WD + description: Watchdog disable + bit_offset: 23 + bit_size: 1 + enum: WD + - name: CSTF + description: CRC stripping for type frames + bit_offset: 25 + bit_size: 1 + enum: CSTF +fieldset/MACDBGR: + description: Ethernet MAC debug register + fields: + - name: MMRPEA + description: MAC MII receive protocol engine active + bit_offset: 0 + bit_size: 1 + - name: MSFRWCS + description: MAC small FIFO read/write controllers status + bit_offset: 1 + bit_size: 2 + - name: RFWRA + description: Rx FIFO write controller active + bit_offset: 4 + bit_size: 1 + - name: RFRCS + description: Rx FIFO read controller status + bit_offset: 5 + bit_size: 2 + - name: RFFL + description: Rx FIFO fill level + bit_offset: 8 + bit_size: 2 + - name: MMTEA + description: MAC MII transmit engine active + bit_offset: 16 + bit_size: 1 + - name: MTFCS + description: MAC transmit frame controller status + bit_offset: 17 + bit_size: 2 + - name: MTP + description: MAC transmitter in pause + bit_offset: 19 + bit_size: 1 + - name: TFRS + description: Tx FIFO read status + bit_offset: 20 + bit_size: 2 + - name: TFWA + description: Tx FIFO write active + bit_offset: 22 + bit_size: 1 + - name: TFNE + description: Tx FIFO not empty + bit_offset: 24 + bit_size: 1 + - name: TFF + description: Tx FIFO full + bit_offset: 25 + bit_size: 1 +fieldset/MACFCR: + description: Ethernet MAC flow control register + fields: + - name: FCB + description: Flow control busy/back pressure activate + bit_offset: 0 + bit_size: 1 + enum: FCB + - name: TFCE + description: Transmit flow control enable + bit_offset: 1 + bit_size: 1 + enum: TFCE + - name: RFCE + description: Receive flow control enable + bit_offset: 2 + bit_size: 1 + enum: RFCE + - name: UPFD + description: Unicast pause frame detect + bit_offset: 3 + bit_size: 1 + enum: UPFD + - name: PLT + description: Pause low threshold + bit_offset: 4 + bit_size: 2 + enum: PLT + - name: ZQPD + description: Zero-quanta pause disable + bit_offset: 7 + bit_size: 1 + enum: ZQPD + - name: PT + description: Pause time + bit_offset: 16 + bit_size: 16 +fieldset/MACFFR: + description: Ethernet MAC frame filter register + fields: + - name: PM + description: Promiscuous mode + bit_offset: 0 + bit_size: 1 + enum: PM + - name: HU + description: Hash unicast + bit_offset: 1 + bit_size: 1 + enum: HU + - name: HM + description: Hash multicast + bit_offset: 2 + bit_size: 1 + enum: HM + - name: DAIF + description: Destination address unique filtering + bit_offset: 3 + bit_size: 1 + enum: DAIF + - name: PAM + description: Pass all multicast + bit_offset: 4 + bit_size: 1 + enum: PAM + - name: BFD + description: Broadcast frames disable + bit_offset: 5 + bit_size: 1 + enum: BFD + - name: PCF + description: Pass control frames + bit_offset: 6 + bit_size: 2 + enum: PCF + - name: SAIF + description: Source address inverse filtering + bit_offset: 7 + bit_size: 1 + enum: SAIF + - name: SAF + description: Source address filter + bit_offset: 8 + bit_size: 1 + enum: SAF + - name: HPF + description: Hash or perfect filter + bit_offset: 9 + bit_size: 1 + enum: HPF + - name: RA + description: Receive all + bit_offset: 31 + bit_size: 1 + enum: RA +fieldset/MACHTHR: + description: Ethernet MAC hash table high register + fields: + - name: HTH + description: Upper 32 bits of hash table + bit_offset: 0 + bit_size: 32 +fieldset/MACHTLR: + description: Ethernet MAC hash table low register + fields: + - name: HTL + description: Lower 32 bits of hash table + bit_offset: 0 + bit_size: 32 +fieldset/MACIMR: + description: Ethernet MAC interrupt mask register + fields: + - name: PMTIM + description: PMT interrupt mask + bit_offset: 3 + bit_size: 1 + enum: PMTIM + - name: TSTIM + description: Time stamp trigger interrupt mask + bit_offset: 9 + bit_size: 1 + enum: TSTIM +fieldset/MACMIIAR: + description: Ethernet MAC MII address register + fields: + - name: MB + description: MII busy + bit_offset: 0 + bit_size: 1 + enum: MB_progress + - name: MW + description: MII write + bit_offset: 1 + bit_size: 1 + enum: MW + - name: CR + description: Clock range + bit_offset: 2 + bit_size: 3 + enum: CR + - name: MR + description: MII register - select the desired MII register in the PHY device + bit_offset: 6 + bit_size: 5 + - name: PA + description: PHY address - select which of possible 32 PHYs is being accessed + bit_offset: 11 + bit_size: 5 +fieldset/MACMIIDR: + description: Ethernet MAC MII data register + fields: + - name: MD + description: MII data read from/written to the PHY + bit_offset: 0 + bit_size: 16 +fieldset/MACPMTCSR: + description: Ethernet MAC PMT control and status register + fields: + - name: PD + description: Power down + bit_offset: 0 + bit_size: 1 + enum: PD + - name: MPE + description: Magic packet enable + bit_offset: 1 + bit_size: 1 + enum: MPE + - name: WFE + description: Wakeup frame enable + bit_offset: 2 + bit_size: 1 + enum: WFE + - name: MPR + description: Magic packet received + bit_offset: 5 + bit_size: 1 + - name: WFR + description: Wakeup frame received + bit_offset: 6 + bit_size: 1 + - name: GU + description: Global unicast + bit_offset: 9 + bit_size: 1 + enum: GU + - name: WFFRPR + description: Wakeup frame filter register pointer reset + bit_offset: 31 + bit_size: 1 + enum: WFFRPR +fieldset/MACSR: + description: Ethernet MAC interrupt status register + fields: + - name: PMTS + description: PMT status + bit_offset: 3 + bit_size: 1 + - name: MMCS + description: MMC status + bit_offset: 4 + bit_size: 1 + - name: MMCRS + description: MMC receive status + bit_offset: 5 + bit_size: 1 + - name: MMCTS + description: MMC transmit status + bit_offset: 6 + bit_size: 1 + - name: TSTS + description: Time stamp trigger status + bit_offset: 9 + bit_size: 1 +fieldset/MACVLANTR: + description: Ethernet MAC VLAN tag register + fields: + - name: VLANTI + description: VLAN tag identifier (for receive frames) + bit_offset: 0 + bit_size: 16 + - name: VLANTC + description: 12-bit VLAN tag comparison + bit_offset: 16 + bit_size: 1 + enum: VLANTC +fieldset/MMCCR: + description: Ethernet MMC control register + fields: + - name: CR + description: Counter reset + bit_offset: 0 + bit_size: 1 + enum: CounterReset + - name: CSR + description: Counter stop rollover + bit_offset: 1 + bit_size: 1 + enum: CSR + - name: ROR + description: Reset on read + bit_offset: 2 + bit_size: 1 + enum: ROR + - name: MCF + description: MMC counter freeze + bit_offset: 3 + bit_size: 1 + enum: MCF + - name: MCP + description: MMC counter preset + bit_offset: 4 + bit_size: 1 + enum: MCP + - name: MCFHP + description: MMC counter Full-Half preset + bit_offset: 5 + bit_size: 1 + enum: MCFHP +fieldset/MMCRFAECR: + description: Ethernet MMC received frames with alignment error counter register + fields: + - name: RFAEC + description: RFAEC + bit_offset: 0 + bit_size: 32 +fieldset/MMCRFCECR: + description: Ethernet MMC received frames with CRC error counter register + fields: + - name: RFCFC + description: RFCFC + bit_offset: 0 + bit_size: 32 +fieldset/MMCRGUFCR: + description: MMC received good unicast frames counter register + fields: + - name: RGUFC + description: RGUFC + bit_offset: 0 + bit_size: 32 +fieldset/MMCRIMR: + description: Ethernet MMC receive interrupt mask register + fields: + - name: RFCEM + description: Received frame CRC error mask + bit_offset: 5 + bit_size: 1 + enum: RFCEM + - name: RFAEM + description: Received frames alignment error mask + bit_offset: 6 + bit_size: 1 + enum: RFAEM + - name: RGUFM + description: Received good Unicast frames mask + bit_offset: 17 + bit_size: 1 + enum: RGUFM +fieldset/MMCRIR: + description: Ethernet MMC receive interrupt register + fields: + - name: RFCES + description: Received frames CRC error status + bit_offset: 5 + bit_size: 1 + - name: RFAES + description: Received frames alignment error status + bit_offset: 6 + bit_size: 1 + - name: RGUFS + description: Received good Unicast frames status + bit_offset: 17 + bit_size: 1 +fieldset/MMCTGFCR: + description: Ethernet MMC transmitted good frames counter register + fields: + - name: TGFC + description: HTL + bit_offset: 0 + bit_size: 32 +fieldset/MMCTGFMSCCR: + description: Ethernet MMC transmitted good frames after more than a single collision + fields: + - name: TGFMSCC + description: TGFMSCC + bit_offset: 0 + bit_size: 32 +fieldset/MMCTGFSCCR: + description: Ethernet MMC transmitted good frames after a single collision counter + fields: + - name: TGFSCC + description: Transmitted good frames single collision counter + bit_offset: 0 + bit_size: 32 +fieldset/MMCTIMR: + description: Ethernet MMC transmit interrupt mask register + fields: + - name: TGFSCM + description: Transmitted good frames single collision mask + bit_offset: 14 + bit_size: 1 + enum: TGFSCM + - name: TGFMSCM + description: Transmitted good frames more than single collision mask + bit_offset: 15 + bit_size: 1 + enum: TGFMSCM + - name: TGFM + description: Transmitted good frames mask + bit_offset: 16 + bit_size: 1 + enum: TGFM +fieldset/MMCTIR: + description: Ethernet MMC transmit interrupt register + fields: + - name: TGFSCS + description: Transmitted good frames single collision status + bit_offset: 14 + bit_size: 1 + - name: TGFMSCS + description: Transmitted good frames more than single collision status + bit_offset: 15 + bit_size: 1 + - name: TGFS + description: Transmitted good frames status + bit_offset: 21 + bit_size: 1 +fieldset/PTPPPSCR: + description: Ethernet PTP PPS control register + fields: + - name: TSSO + description: TSSO + bit_offset: 0 + bit_size: 1 + - name: TSTTR + description: TSTTR + bit_offset: 1 + bit_size: 1 +fieldset/PTPSSIR: + description: Ethernet PTP subsecond increment register + fields: + - name: STSSI + description: STSSI + bit_offset: 0 + bit_size: 8 +fieldset/PTPTSAR: + description: Ethernet PTP time stamp addend register + fields: + - name: TSA + description: TSA + bit_offset: 0 + bit_size: 32 +fieldset/PTPTSCR: + description: Ethernet PTP time stamp control register + fields: + - name: TSE + description: TSE + bit_offset: 0 + bit_size: 1 + - name: TSFCU + description: TSFCU + bit_offset: 1 + bit_size: 1 + - name: TSSTI + description: TSSTI + bit_offset: 2 + bit_size: 1 + - name: TSSTU + description: TSSTU + bit_offset: 3 + bit_size: 1 + - name: TSITE + description: TSITE + bit_offset: 4 + bit_size: 1 + - name: TTSARU + description: TTSARU + bit_offset: 5 + bit_size: 1 + - name: TSSARFE + description: TSSARFE + bit_offset: 8 + bit_size: 1 + - name: TSSSR + description: TSSSR + bit_offset: 9 + bit_size: 1 + - name: TSPTPPSV2E + description: TSPTPPSV2E + bit_offset: 10 + bit_size: 1 + - name: TSSPTPOEFE + description: TSSPTPOEFE + bit_offset: 11 + bit_size: 1 + - name: TSSIPV6FE + description: TSSIPV6FE + bit_offset: 12 + bit_size: 1 + - name: TSSIPV4FE + description: TSSIPV4FE + bit_offset: 13 + bit_size: 1 + - name: TSSEME + description: TSSEME + bit_offset: 14 + bit_size: 1 + - name: TSSMRME + description: TSSMRME + bit_offset: 15 + bit_size: 1 + - name: TSCNT + description: TSCNT + bit_offset: 16 + bit_size: 2 + - name: TSPFFMAE + description: TSPFFMAE + bit_offset: 18 + bit_size: 1 +fieldset/PTPTSHR: + description: Ethernet PTP time stamp high register + fields: + - name: STS + description: STS + bit_offset: 0 + bit_size: 32 +fieldset/PTPTSHUR: + description: Ethernet PTP time stamp high update register + fields: + - name: TSUS + description: TSUS + bit_offset: 0 + bit_size: 32 +fieldset/PTPTSLR: + description: Ethernet PTP time stamp low register + fields: + - name: STSS + description: STSS + bit_offset: 0 + bit_size: 31 + - name: STPNS + description: STPNS + bit_offset: 31 + bit_size: 1 +fieldset/PTPTSLUR: + description: Ethernet PTP time stamp low update register + fields: + - name: TSUSS + description: TSUSS + bit_offset: 0 + bit_size: 31 + - name: TSUPNS + description: TSUPNS + bit_offset: 31 + bit_size: 1 +fieldset/PTPTSSR: + description: Ethernet PTP time stamp status register + fields: + - name: TSSO + description: TSSO + bit_offset: 0 + bit_size: 1 + - name: TSTTR + description: TSSO + bit_offset: 1 + bit_size: 1 +fieldset/PTPTTHR: + description: Ethernet PTP target time high register + fields: + - name: TTSH + description: "0" + bit_offset: 0 + bit_size: 32 +fieldset/PTPTTLR: + description: Ethernet PTP target time low register + fields: + - name: TTSL + description: TTSL + bit_offset: 0 + bit_size: 32 +enum/AAB: + bit_size: 1 + variants: + - name: Unaligned + description: Bursts are not aligned + value: 0 + - name: Aligned + description: Align bursts to start address LS bits. First burst alignment depends on FB bit + value: 1 +enum/APCS: + bit_size: 1 + variants: + - name: Disabled + description: MAC passes all incoming frames unmodified + value: 0 + - name: Strip + description: MAC strips the Pad/FCS field on incoming frames only for lengths less than or equal to 1500 bytes + value: 1 +enum/BFD: + bit_size: 1 + variants: + - name: Enabled + description: Address filters pass all received broadcast frames + value: 0 + - name: Disabled + description: Address filters filter all incoming broadcast frames + value: 1 +enum/BL: + bit_size: 2 + variants: + - name: BL10 + description: "For retransmission n, wait up to 2^min(n, 10) time slots" + value: 0 + - name: BL8 + description: "For retransmission n, wait up to 2^min(n, 8) time slots" + value: 1 + - name: BL4 + description: "For retransmission n, wait up to 2^min(n, 4) time slots" + value: 2 + - name: BL1 + description: "For retransmission n, wait up to 2^min(n, 1) time slots" + value: 3 +enum/CR: + bit_size: 3 + variants: + - name: CR_60_100 + description: 60-100MHz HCLK/42 + value: 0 + - name: CR_100_150 + description: 100-150 MHz HCLK/62 + value: 1 + - name: CR_20_35 + description: 20-35MHz HCLK/16 + value: 2 + - name: CR_35_60 + description: 35-60MHz HCLK/16 + value: 3 + - name: CR_150_168 + description: 150-168MHz HCLK/102 + value: 4 +enum/CSD: + bit_size: 1 + variants: + - name: Enabled + description: Errors generated due to loss of carrier + value: 0 + - name: Disabled + description: No error generated due to loss of carrier + value: 1 +enum/CSR: + bit_size: 1 + variants: + - name: Disabled + description: Counters roll over to zero after reaching the maximum value + value: 0 + - name: Enabled + description: Counters do not roll over to zero after reaching the maximum value + value: 1 +enum/CSTF: + bit_size: 1 + variants: + - name: Disabled + description: CRC not stripped + value: 0 + - name: Enabled + description: CRC stripped + value: 1 +enum/CounterReset: + bit_size: 1 + variants: + - name: Reset + description: Reset all counters. Cleared automatically + value: 1 +enum/DA: + bit_size: 1 + variants: + - name: RoundRobin + description: "Round-robin with Rx:Tx priority given by PM" + value: 0 + - name: RxPriority + description: Rx has priority over Tx + value: 1 +enum/DAIF: + bit_size: 1 + variants: + - name: Normal + description: Normal filtering of frames + value: 0 + - name: Invert + description: Address check block operates in inverse filtering mode for the DA address comparison + value: 1 +enum/DC: + bit_size: 1 + variants: + - name: Disabled + description: MAC defers until CRS signal goes inactive + value: 0 + - name: Enabled + description: Deferral check function enabled + value: 1 +enum/DM: + bit_size: 1 + variants: + - name: HalfDuplex + description: MAC operates in half-duplex mode + value: 0 + - name: FullDuplex + description: MAC operates in full-duplex mode + value: 1 +enum/DMABMR_SR: + bit_size: 1 + variants: + - name: Reset + description: Reset all MAC subsystem internal registers and logic. Cleared automatically + value: 1 +enum/DMAOMR_SR: + bit_size: 1 + variants: + - name: Stopped + description: Reception is stopped after transfer of the current frame + value: 0 + - name: Started + description: Reception is placed in the Running state + value: 1 +enum/DTCEFD: + bit_size: 1 + variants: + - name: Enabled + description: Drop frames with errors only in the receive checksum offload engine + value: 0 + - name: Disabled + description: Do not drop frames that only have errors in the receive checksum offload engine + value: 1 +enum/EDFE: + bit_size: 1 + variants: + - name: Disabled + description: Normal descriptor format + value: 0 + - name: Enabled + description: "Enhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload" + value: 1 +enum/FB: + bit_size: 1 + variants: + - name: Variable + description: AHB uses SINGLE and INCR burst transfers + value: 0 + - name: Fixed + description: AHB uses only fixed burst transfers + value: 1 +enum/FCB: + bit_size: 1 + variants: + - name: DisableBackPressure + description: "In half duplex only, deasserts back pressure" + value: 0 + - name: PauseOrBackPressure + description: "In full duplex, initiate a Pause control frame. In half duplex, assert back pressure" + value: 1 +enum/FEF: + bit_size: 1 + variants: + - name: Drop + description: Rx FIFO drops frames with error status + value: 0 + - name: Forward + description: All frames except runt error frames are forwarded to the DMA + value: 1 +enum/FES: + bit_size: 1 + variants: + - name: FES10 + description: 10 Mbit/s + value: 0 + - name: FES100 + description: 100 Mbit/s + value: 1 +enum/FPM: + bit_size: 1 + variants: + - name: x1 + description: PBL values used as-is + value: 0 + - name: x4 + description: PBL values multiplied by 4 + value: 1 +enum/FTF: + bit_size: 1 + variants: + - name: Flush + description: Transmit FIFO controller logic is reset to its default values. Cleared automatically + value: 1 +enum/FUGF: + bit_size: 1 + variants: + - name: Drop + description: Rx FIFO drops all frames of less than 64 bytes + value: 0 + - name: Forward + description: Rx FIFO forwards undersized frames + value: 1 +enum/GU: + bit_size: 1 + variants: + - name: Disabled + description: Normal operation + value: 0 + - name: Enabled + description: Any unicast packet filtered by the MAC address recognition may be a wakeup frame + value: 1 +enum/HM: + bit_size: 1 + variants: + - name: Perfect + description: MAC performs a perfect destination address filtering for multicast frames + value: 0 + - name: Hash + description: MAC performs destination address filtering of received multicast frames according to the hash table + value: 1 +enum/HPF: + bit_size: 1 + variants: + - name: HashOnly + description: "If HM or HU is set, only frames that match the Hash filter are passed" + value: 0 + - name: HashOrPerfect + description: "If HM or HU is set, frames that match either the perfect filter or the hash filter are passed" + value: 1 +enum/HU: + bit_size: 1 + variants: + - name: Perfect + description: MAC performs a perfect destination address filtering for unicast frames + value: 0 + - name: Hash + description: MAC performs destination address filtering of received unicast frames according to the hash table + value: 1 +enum/IFG: + bit_size: 3 + variants: + - name: IFG96 + description: 96 bit times + value: 0 + - name: IFG88 + description: 88 bit times + value: 1 + - name: IFG80 + description: 80 bit times + value: 2 + - name: IFG72 + description: 72 bit times + value: 3 + - name: IFG64 + description: 64 bit times + value: 4 + - name: IFG56 + description: 56 bit times + value: 5 + - name: IFG48 + description: 48 bit times + value: 6 + - name: IFG40 + description: 40 bit times + value: 7 +enum/IPCO: + bit_size: 1 + variants: + - name: Disabled + description: IPv4 checksum offload disabled + value: 0 + - name: Offload + description: IPv4 checksums are checked in received frames + value: 1 +enum/JD: + bit_size: 1 + variants: + - name: Enabled + description: "Jabber enabled, transmit frames up to 2048 bytes" + value: 0 + - name: Disabled + description: "Jabber disabled, transmit frames up to 16384 bytes" + value: 1 +enum/LM: + bit_size: 1 + variants: + - name: Normal + description: Normal mode + value: 0 + - name: Loopback + description: MAC operates in loopback mode at the MII + value: 1 +enum/MACAHR_AE: + bit_size: 1 + variants: + - name: Disabled + description: Address filters ignore this address + value: 0 + - name: Enabled + description: Address filters use this address + value: 1 +enum/MACAHR_SA: + bit_size: 1 + variants: + - name: Destination + description: This address is used for comparison with DA fields of the received frame + value: 0 + - name: Source + description: This address is used for comparison with SA fields of received frames + value: 1 +enum/MB: + bit_size: 1 + variants: + - name: Normal + description: Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below + value: 0 + - name: Mixed + description: "If FB is low, start all bursts greater than 16 with INCR (undefined burst)" + value: 1 +enum/MB_progress: + bit_size: 1 + variants: + - name: Busy + description: This bit is set to 1 by the application to indicate that a read or write access is in progress + value: 1 +enum/MCF: + bit_size: 1 + variants: + - name: Unfrozen + description: All MMC counters update normally + value: 0 + - name: Frozen + description: All MMC counters frozen to their current value + value: 1 +enum/MCFHP: + bit_size: 1 + variants: + - name: AlmostHalf + description: "When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0" + value: 0 + - name: AlmostFull + description: "When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0" + value: 1 +enum/MCP: + bit_size: 1 + variants: + - name: Preset + description: MMC counters will be preset to almost full or almost half. Cleared automatically + value: 1 +enum/MPE: + bit_size: 1 + variants: + - name: Disabled + description: No power management event generated due to Magic Packet reception + value: 0 + - name: Enabled + description: Enable generation of a power management event due to Magic Packet reception + value: 1 +enum/MW: + bit_size: 1 + variants: + - name: Read + description: Read operation + value: 0 + - name: Write + description: Write operation + value: 1 +enum/PAM: + bit_size: 1 + variants: + - name: Disabled + description: Filtering of multicast frames depends on HM + value: 0 + - name: Enabled + description: All received frames with a multicast destination address are passed + value: 1 +enum/PBL: + bit_size: 6 + variants: + - name: PBL1 + description: Maximum of 1 beat per DMA transaction + value: 1 + - name: PBL2 + description: Maximum of 2 beats per DMA transaction + value: 2 + - name: PBL4 + description: Maximum of 4 beats per DMA transaction + value: 4 + - name: PBL8 + description: Maximum of 8 beats per DMA transaction + value: 8 + - name: PBL16 + description: Maximum of 16 beats per DMA transaction + value: 16 + - name: PBL32 + description: Maximum of 32 beats per DMA transaction + value: 32 +enum/PCF: + bit_size: 2 + variants: + - name: PreventAll + description: MAC prevents all control frames from reaching the application + value: 0 + - name: ForwardAllExceptPause + description: MAC forwards all control frames to application except Pause + value: 1 + - name: ForwardAll + description: MAC forwards all control frames to application even if they fail the address filter + value: 2 + - name: ForwardAllFiltered + description: MAC forwards control frames that pass the address filter + value: 3 +enum/PD: + bit_size: 1 + variants: + - name: Enabled + description: All received frames will be dropped. Cleared automatically when a magic packet or wakeup frame is received + value: 1 +enum/PLT: + bit_size: 2 + variants: + - name: PLT4 + description: Pause time minus 4 slot times + value: 0 + - name: PLT28 + description: Pause time minus 28 slot times + value: 1 + - name: PLT144 + description: Pause time minus 144 slot times + value: 2 + - name: PLT256 + description: Pause time minus 256 slot times + value: 3 +enum/PM: + bit_size: 1 + variants: + - name: Disabled + description: Normal address filtering + value: 0 + - name: Enabled + description: Address filters pass all incoming frames regardless of their destination or source address + value: 1 +enum/PMTIM: + bit_size: 1 + variants: + - name: Unmasked + description: PMT Status interrupt generation enabled + value: 0 + - name: Masked + description: PMT Status interrupt generation disabled + value: 1 +enum/PriorityRxOverTx: + bit_size: 2 + variants: + - name: OneToOne + description: "RxDMA priority over TxDMA is 1:1" + value: 0 + - name: TwoToOne + description: "RxDMA priority over TxDMA is 2:1" + value: 1 + - name: ThreeToOne + description: "RxDMA priority over TxDMA is 3:1" + value: 2 + - name: FourToOne + description: "RxDMA priority over TxDMA is 4:1" + value: 3 +enum/RA: + bit_size: 1 + variants: + - name: Disabled + description: MAC receiver passes on to the application only those frames that have passed the SA/DA address file + value: 0 + - name: Enabled + description: MAC receiver passes oll received frames on to the application + value: 1 +enum/RD: + bit_size: 1 + variants: + - name: Enabled + description: MAC attempts retries based on the settings of BL + value: 0 + - name: Disabled + description: MAC attempts only 1 transmission + value: 1 +enum/RDP: + bit_size: 6 + variants: + - name: RDP1 + description: 1 beat per RxDMA transaction + value: 1 + - name: RDP2 + description: 2 beats per RxDMA transaction + value: 2 + - name: RDP4 + description: 4 beats per RxDMA transaction + value: 4 + - name: RDP8 + description: 8 beats per RxDMA transaction + value: 8 + - name: RDP16 + description: 16 beats per RxDMA transaction + value: 16 + - name: RDP32 + description: 32 beats per RxDMA transaction + value: 32 +enum/RE: + bit_size: 1 + variants: + - name: Disabled + description: MAC receive state machine is disabled after the completion of the reception of the current frame + value: 0 + - name: Enabled + description: MAC receive state machine is enabled + value: 1 +enum/RFAEM: + bit_size: 1 + variants: + - name: Unmasked + description: Received-alignment-error counter half-full interrupt enabled + value: 0 + - name: Masked + description: Received-alignment-error counter half-full interrupt disabled + value: 1 +enum/RFCE: + bit_size: 1 + variants: + - name: Disabled + description: Pause frames are not decoded + value: 0 + - name: Enabled + description: MAC decodes received Pause frames and disables its transmitted for a specified time + value: 1 +enum/RFCEM: + bit_size: 1 + variants: + - name: Unmasked + description: Received-crc-error counter half-full interrupt enabled + value: 0 + - name: Masked + description: Received-crc-error counter half-full interrupt disabled + value: 1 +enum/RGUFM: + bit_size: 1 + variants: + - name: Unmasked + description: Received-good-unicast counter half-full interrupt enabled + value: 0 + - name: Masked + description: Received-good-unicast counter half-full interrupt disabled + value: 1 +enum/ROD: + bit_size: 1 + variants: + - name: Enabled + description: MAC receives all packets from PHY while transmitting + value: 0 + - name: Disabled + description: MAC disables reception of frames in half-duplex mode + value: 1 +enum/ROR: + bit_size: 1 + variants: + - name: Disabled + description: MMC counters do not reset on read + value: 0 + - name: Enabled + description: MMC counters reset to zero after read + value: 1 +enum/RPD: + bit_size: 32 + variants: + - name: Poll + description: Poll the receive descriptor list + value: 0 +enum/RPS: + bit_size: 3 + variants: + - name: Stopped + description: "Stopped, reset or Stop Receive command issued" + value: 0 + - name: RunningFetching + description: "Running, fetching receive transfer descriptor" + value: 1 + - name: RunningWaiting + description: "Running, waiting for receive packet" + value: 3 + - name: Suspended + description: "Suspended, receive descriptor unavailable" + value: 4 + - name: RunningWriting + description: "Running, writing data to host memory buffer" + value: 7 +enum/RSF: + bit_size: 1 + variants: + - name: CutThrough + description: "Rx FIFO operates in cut-through mode, subject to RTC bits" + value: 0 + - name: StoreForward + description: Frames are read from Rx FIFO after complete frame has been written + value: 1 +enum/RTC: + bit_size: 2 + variants: + - name: RTC64 + description: 64 bytes + value: 0 + - name: RTC32 + description: 32 bytes + value: 1 + - name: RTC96 + description: 96 bytes + value: 2 + - name: RTC128 + description: 128 bytes + value: 3 +enum/SAF: + bit_size: 1 + variants: + - name: Disabled + description: Source address ignored + value: 0 + - name: Enabled + description: MAC drops frames that fail the source address filter + value: 1 +enum/SAIF: + bit_size: 1 + variants: + - name: Normal + description: Source address filter operates normally + value: 0 + - name: Invert + description: Source address filter operation inverted + value: 1 +enum/ST: + bit_size: 1 + variants: + - name: Stopped + description: Transmission is placed in the Stopped state + value: 0 + - name: Started + description: Transmission is placed in Running state + value: 1 +enum/TE: + bit_size: 1 + variants: + - name: Disabled + description: MAC transmit state machine is disabled after completion of the transmission of the current frame + value: 0 + - name: Enabled + description: MAC transmit state machine is enabled + value: 1 +enum/TFCE: + bit_size: 1 + variants: + - name: Disabled + description: "In full duplex, flow control is disabled. In half duplex, back pressure is disabled" + value: 0 + - name: Enabled + description: "In full duplex, flow control is enabled. In half duplex, back pressure is enabled" + value: 1 +enum/TGFM: + bit_size: 1 + variants: + - name: Unmasked + description: Transmitted-good counter half-full interrupt enabled + value: 0 + - name: Masked + description: Transmitted-good counter half-full interrupt disabled + value: 1 +enum/TGFMSCM: + bit_size: 1 + variants: + - name: Unmasked + description: Transmitted-good-multiple-collision half-full interrupt enabled + value: 0 + - name: Masked + description: Transmitted-good-multiple-collision half-full interrupt disabled + value: 1 +enum/TGFSCM: + bit_size: 1 + variants: + - name: Unmasked + description: Transmitted-good-single-collision half-full interrupt enabled + value: 0 + - name: Masked + description: Transmitted-good-single-collision half-full interrupt disabled + value: 1 +enum/TPD: + bit_size: 32 + variants: + - name: Poll + description: Poll the transmit descriptor list + value: 0 +enum/TPS: + bit_size: 3 + variants: + - name: Stopped + description: "Stopped, Reset or Stop Transmit command issued" + value: 0 + - name: RunningFetching + description: "Running, fetching transmit transfer descriptor" + value: 1 + - name: RunningWaiting + description: "Running, waiting for status" + value: 2 + - name: RunningReading + description: "Running, reading data from host memory buffer" + value: 3 + - name: Suspended + description: "Suspended, transmit descriptor unavailable or transmit buffer underflow" + value: 6 + - name: Running + description: "Running, closing transmit descriptor" + value: 7 +enum/TSF: + bit_size: 1 + variants: + - name: CutThrough + description: Transmission starts when the frame size in the Tx FIFO exceeds TTC threshold + value: 0 + - name: StoreForward + description: Transmission starts when a full frame is in the Tx FIFO + value: 1 +enum/TSTIM: + bit_size: 1 + variants: + - name: Unmasked + description: Time stamp interrupt generation enabled + value: 0 + - name: Masked + description: Time stamp interrupt generation disabled + value: 1 +enum/TTC: + bit_size: 3 + variants: + - name: TTC64 + description: 64 bytes + value: 0 + - name: TTC128 + description: 128 bytes + value: 1 + - name: TTC192 + description: 192 bytes + value: 2 + - name: TTC256 + description: 256 bytes + value: 3 + - name: TTC40 + description: 40 bytes + value: 4 + - name: TTC32 + description: 32 bytes + value: 5 + - name: TTC24 + description: 24 bytes + value: 6 + - name: TTC16 + description: 16 bytes + value: 7 +enum/UPFD: + bit_size: 1 + variants: + - name: Disabled + description: MAC detects only a Pause frame with the multicast address specified in the 802.3x standard + value: 0 + - name: Enabled + description: "MAC additionally detects Pause frames with the station's unicast address" + value: 1 +enum/USP: + bit_size: 1 + variants: + - name: Combined + description: PBL value used for both Rx and Tx DMA + value: 0 + - name: Separate + description: "RxDMA uses RDP value, TxDMA uses PBL value" + value: 1 +enum/VLANTC: + bit_size: 1 + variants: + - name: VLANTC16 + description: Full 16 bit VLAN identifiers are used for comparison and filtering + value: 0 + - name: VLANTC12 + description: 12 bit VLAN identifies are used for comparison and filtering + value: 1 +enum/WD: + bit_size: 1 + variants: + - name: Enabled + description: "Watchdog enabled, receive frames limited to 2048 bytes" + value: 0 + - name: Disabled + description: "Watchdog disabled, receive frames may be up to to 16384 bytes" + value: 1 +enum/WFE: + bit_size: 1 + variants: + - name: Disabled + description: No power management event generated due to wakeup frame reception + value: 0 + - name: Enabled + description: Enable generation of a power management event due to wakeup frame reception + value: 1 +enum/WFFRPR: + bit_size: 1 + variants: + - name: Reset + description: Reset wakeup frame filter register point to 0b000. Automatically cleared + value: 1 +enum/ZQPD: + bit_size: 1 + variants: + - name: Enabled + description: Normal operation with automatic zero-quanta pause control frame generation + value: 0 + - name: Disabled + description: Automatic generation of zero-quanta pause control frames is disabled + value: 1 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 3202bbb..f30e201 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -232,6 +232,7 @@ perimap = [ ('STM32WB.*:FLASH:.*', ('flash', 'wb55', 'FLASH')), ('STM32G0.*:FLASH:.*', ('flash', 'g0', 'FLASH')), ('STM32F107.*:ETH:.*', ('eth', 'v1a', 'ETH')), + ('STM32F[24].*:ETH:.*', ('eth', 'v1b', 'ETH')), ('STM32F7.*:ETH:ETH:ethermac110_v2_0', ('eth', 'v1c', 'ETH')), ('.*ETH:ethermac110_v3_0', ('eth', 'v2', 'ETH')), From afcd7a7d6973dd8d063d052b1e832243b482dcf4 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Tue, 26 Apr 2022 18:17:09 +0200 Subject: [PATCH 19/35] Rename flash_w[bl]55 flash_w[bl] --- data/registers/{flash_wb55.yaml => flash_wb.yaml} | 0 data/registers/{flash_wl55.yaml => flash_wl.yaml} | 0 stm32data/__main__.py | 4 ++-- 3 files changed, 2 insertions(+), 2 deletions(-) rename data/registers/{flash_wb55.yaml => flash_wb.yaml} (100%) rename data/registers/{flash_wl55.yaml => flash_wl.yaml} (100%) diff --git a/data/registers/flash_wb55.yaml b/data/registers/flash_wb.yaml similarity index 100% rename from data/registers/flash_wb55.yaml rename to data/registers/flash_wb.yaml diff --git a/data/registers/flash_wl55.yaml b/data/registers/flash_wl.yaml similarity index 100% rename from data/registers/flash_wl55.yaml rename to data/registers/flash_wl.yaml diff --git a/stm32data/__main__.py b/stm32data/__main__.py index f6414fb..6d77461 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -229,8 +229,8 @@ perimap = [ ('STM32L4.*:FLASH:.*', ('flash', 'l4', 'FLASH')), ('STM32L5.*:FLASH:.*', ('flash', 'l5', 'FLASH')), ('STM32U5.*:FLASH:.*', ('flash', 'u5', 'FLASH')), - ('STM32WB.*:FLASH:.*', ('flash', 'wb55', 'FLASH')), - ('STM32WL.*:FLASH:.*', ('flash', 'wl55', 'FLASH')), + ('STM32WB.*:FLASH:.*', ('flash', 'wb', 'FLASH')), + ('STM32WL.*:FLASH:.*', ('flash', 'wl', 'FLASH')), ('STM32G0.*:FLASH:.*', ('flash', 'g0', 'FLASH')), ('STM32F7.*:ETH:ETH:ethermac110_v2_0', ('eth', 'v1c', 'ETH')), ('.*ETH:ethermac110_v3_0', ('eth', 'v2', 'ETH')), From ad291b5af3aa5cdcf48a10d47efc7ebbfde68373 Mon Sep 17 00:00:00 2001 From: Joonas Javanainen Date: Tue, 26 Apr 2022 20:19:15 +0300 Subject: [PATCH 20/35] Map spi2s1_v2_1 used on F2 devices This seems identical to v2_2 (as used by F429) with one naming exception in status register SR bit 8 (TI frame format error): v2_1 data names the bit "TIFRFE" and the enum TIFRERR v2_2 data names the bit "FRE" and the enum FRER The register bit layout is identical. --- stm32data/__main__.py | 1 + 1 file changed, 1 insertion(+) diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 1834e51..b25c0bb 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -105,6 +105,7 @@ perimap = [ ('.*:RNG:rng1_v2_1', ('rng', 'v1', 'RNG')), ('.*:RNG:rng1_v3_1', ('rng', 'v1', 'RNG')), ('.*:SPI:spi2_v1_4', ('spi', 'f1', 'SPI')), + ('.*:SPI:spi2s1_v2_1', ('spi', 'v1', 'SPI')), ('.*:SPI:spi2s1_v2_2', ('spi', 'v1', 'SPI')), ('.*:SPI:spi2s1_v3_2', ('spi', 'v2', 'SPI')), ('.*:SPI:spi2s1_v3_3', ('spi', 'v2', 'SPI')), From bb6053d4ee6906fab1d40a1e9b93a336d8baa12b Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Tue, 26 Apr 2022 21:16:00 +0200 Subject: [PATCH 21/35] chiptool fmt --- data/registers/rcc_f1.yaml | 2 +- data/registers/rcc_f1cl.yaml | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml index 7564024..4244347 100644 --- a/data/registers/rcc_f1.yaml +++ b/data/registers/rcc_f1.yaml @@ -888,7 +888,7 @@ enum/MCO: description: HSE oscillator clock selected value: 6 - name: PLL - description: "PLL clock divided by 2 selected" + description: PLL clock divided by 2 selected value: 7 enum/OTGFSPRE: bit_size: 1 diff --git a/data/registers/rcc_f1cl.yaml b/data/registers/rcc_f1cl.yaml index 93d8031..dbb7dfa 100644 --- a/data/registers/rcc_f1cl.yaml +++ b/data/registers/rcc_f1cl.yaml @@ -888,19 +888,19 @@ enum/MCO: description: HSE oscillator clock selected value: 6 - name: PLL - description: "PLL clock divided by 2 selected" + description: PLL clock divided by 2 selected value: 7 - name: PLL2 - description: "PLL2 clock selected" + description: PLL2 clock selected value: 8 - name: PLL3DIV2 - description: "PLL3 clock divided by 2 selected" + description: PLL3 clock divided by 2 selected value: 9 - name: XT1 - description: "XT1 external oscillator selected" + description: XT1 external oscillator selected value: 10 - name: PLL3 - description: "PLL3 clock selected" + description: PLL3 clock selected value: 11 enum/OTGFSPRE: bit_size: 1 From eff26e3e77176cb9bde37978cdb3eaad20bf065b Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Tue, 26 Apr 2022 23:53:28 +0200 Subject: [PATCH 22/35] Add stm32u5 GPDMA, SPI --- data/dmamux/U5_GPDMA1.yaml | 114 ++++++ data/registers/gpdma_v1.yaml | 597 +++++++++++++++++++++++++++++ data/registers/spi_v4.yaml | 722 +++++++++++++++++++++++++++++++++++ stm32data/__main__.py | 49 ++- 4 files changed, 1476 insertions(+), 6 deletions(-) create mode 100644 data/dmamux/U5_GPDMA1.yaml create mode 100644 data/registers/gpdma_v1.yaml create mode 100644 data/registers/spi_v4.yaml diff --git a/data/dmamux/U5_GPDMA1.yaml b/data/dmamux/U5_GPDMA1.yaml new file mode 100644 index 0000000..e395940 --- /dev/null +++ b/data/dmamux/U5_GPDMA1.yaml @@ -0,0 +1,114 @@ +ADC1: 0 +ADC4: 1 +DAC1_CH1: 2 +DAC1_CH2: 3 +TIM6_UPD: 4 +TIM7_UPD: 5 +SPI1_RX: 6 +SPI1_TX: 7 +SPI2_RX: 8 +SPI2_TX: 9 +SPI3_RX: 10 +SPI3_TX: 11 +I2C1_RX: 12 +I2C1_TX: 13 +I2C1_EVC: 14 +I2C2_RX: 15 +I2C2_TX: 16 +I2C2_EVC: 17 +I2C3_RX: 18 +I2C3_TX: 19 +I2C3_EVC: 20 +I2C4_RX: 21 +I2C4_TX: 22 +I2C4_EVC: 23 +USART1_RX: 24 +USART1_TX: 25 +USART2_RX: 26 +USART2_TX: 27 +USART3_RX: 28 +USART3_TX: 29 +UART4_RX: 30 +UART4_TX: 31 +UART5_RX: 32 +UART5_TX: 33 +LPUART1_RX: 34 +LPUART1_TX: 35 +SAI1_A: 36 +SAI1_B: 37 +SAI2_A: 38 +SAI2_B: 39 +OCTOSPI1: 40 +OCTOSPI2: 41 +TIM1_CC1: 42 +TIM1_CC2: 43 +TIM1_CC3: 44 +TIM1_CC4: 45 +TIM1_UPD: 46 +TIM1_TRG: 47 +TIM1_COM: 48 +TIM8_CC1: 49 +TIM8_CC2: 50 +TIM8_CC3: 51 +TIM8_CC4: 52 +TIM8_UPD: 53 +TIM8_TRG: 54 +TIM8_COM: 55 +TIM2_CC1: 56 +TIM2_CC2: 57 +TIM2_CC3: 58 +TIM2_CC4: 59 +TIM2_UPD: 60 +TIM3_CC1: 61 +TIM3_CC2: 62 +TIM3_CC3: 63 +TIM3_CC4: 64 +TIM3_UPD: 65 +TIM3_TRG: 66 +TIM4_CC1: 67 +TIM4_CC2: 68 +TIM4_CC3: 69 +TIM4_CC4: 70 +TIM4_UPD: 71 +TIM5_CC1: 72 +TIM5_CC2: 73 +TIM5_CC3: 74 +TIM5_CC4: 75 +TIM5_UPD: 76 +TIM5_TRG: 77 +TIM15_CC1: 78 +TIM15_UPD: 79 +TIM15_TRG: 80 +TIM15_COM: 81 +TIM16_CC1: 82 +TIM16_UPD: 83 +TIM17_CC1: 84 +TIM17_UPD: 85 +DCMI: 86 +AES_IN: 87 +AES_OUT: 88 +HASH_IN: 89 +UCPD1_TX: 90 +UCPD1_RX: 91 +MDF1_FLT0: 92 +MDF1_FLT1: 93 +MDF1_FLT2: 94 +MDF1_FLT3: 95 +MDF1_FLT4: 96 +MDF1_FLT5: 97 +ADF1_FLT0: 98 +FMAC_READ: 99 +FMAC_WRITE: 100 +CORDIC_READ: 101 +CORDIC_WRITE: 102 +SAES_IN: 103 +SAES_OUT: 104 +LPTIM1_IC1: 105 +LPTIM1_IC2: 106 +LPTIM1_UE: 107 +LPTIM2_IC1: 108 +LPTIM2_IC2: 109 +LPTIM2_UE: 110 +LPTIM3_IC1: 111 +LPTIM3_IC2: 112 +LPTIM3_UE: 113 \ No newline at end of file diff --git a/data/registers/gpdma_v1.yaml b/data/registers/gpdma_v1.yaml new file mode 100644 index 0000000..f285c3d --- /dev/null +++ b/data/registers/gpdma_v1.yaml @@ -0,0 +1,597 @@ +--- +block/Channel: + items: + - name: LBAR + description: GPDMA channel 15 linked-list base address register + byte_offset: 0 + fieldset: CH_LBAR + - name: FCR + description: GPDMA channel 15 flag clear register + byte_offset: 12 + fieldset: CH_FCR + - name: SR + description: GPDMA channel 15 status register + byte_offset: 16 + fieldset: CH_SR + - name: CR + description: GPDMA channel 15 control register + byte_offset: 20 + fieldset: CH_CR + - name: TR1 + description: GPDMA channel 15 transfer register 1 + byte_offset: 64 + fieldset: CH_TR1 + - name: TR2 + description: GPDMA channel 15 transfer register 2 + byte_offset: 68 + fieldset: CH_TR2 + - name: BR1 + description: GPDMA channel 15 alternate block register 1 + byte_offset: 72 + fieldset: CH_BR1 + - name: SAR + description: GPDMA channel 15 source address register + byte_offset: 76 + - name: DAR + description: GPDMA channel 15 destination address register + byte_offset: 80 + - name: TR3 + description: GPDMA channel 15 transfer register 3 + byte_offset: 84 + fieldset: CH_TR3 + - name: BR2 + description: GPDMA channel 15 block register 2 + byte_offset: 88 + fieldset: CH_BR2 + - name: LLR + description: GPDMA channel 15 alternate linked-list address register + byte_offset: 124 + fieldset: CH_LLR +block/GPDMA: + description: GPDMA + items: + - name: SECCFGR + description: GPDMA secure configuration register + byte_offset: 0 + fieldset: SECCFGR + - name: PRIVCFGR + description: GPDMA privileged configuration register + byte_offset: 4 + fieldset: PRIVCFGR + - name: RCFGLOCKR + description: GPDMA configuration lock register + byte_offset: 8 + fieldset: RCFGLOCKR + - name: MISR + description: GPDMA non-secure masked interrupt status register + byte_offset: 12 + fieldset: MISR + - name: SMISR + description: GPDMA secure masked interrupt status register + byte_offset: 16 + fieldset: MISR + - name: CH + array: + len: 16 + stride: 128 + byte_offset: 80 + block: Channel +fieldset/CH_BR1: + description: GPDMA channel 15 alternate block register 1 + fields: + - name: BNDT + description: "block number of data bytes to transfer from the source. Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if CH[x].LLR.UB1 = 1, this field is updated by the LLI in the memory. - if CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if CH[x].LLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (CH[x].TR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued." + bit_offset: 0 + bit_size: 16 + - name: BRC + description: "Block repeat counter. This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If CH[x].LLR.UB1 = 1, all CH[x].BR1 fields are updated by the next LLI in the memory. If CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if CH[x].LLR = 0, this field is kept as zero following the last LLI and data transfer." + bit_offset: 16 + bit_size: 11 + - name: SDEC + description: source address decrement + bit_offset: 28 + bit_size: 1 + enum: CH_BR1_DEC + - name: DDEC + description: destination address decrement + bit_offset: 29 + bit_size: 1 + enum: CH_BR1_DEC + - name: BRSDEC + description: "Block repeat source address decrement. Note: On top of this increment/decrement (depending on BRSDEC), CH[x].SAR is in the same time also updated by the increment/decrement (depending on SDEC) of the CH[x].TR3.SAO value, as it is done after any programmed burst transfer." + bit_offset: 30 + bit_size: 1 + enum: CH_BR1_DEC + - name: BRDDEC + description: "Block repeat destination address decrement. Note: On top of this increment/decrement (depending on BRDDEC), CH[x].DAR is in the same time also updated by the increment/decrement (depending on DDEC) of the CH[x].TR3.DAO value, as it is usually done at the end of each programmed burst transfer." + bit_offset: 31 + bit_size: 1 + enum: CH_BR1_DEC +fieldset/CH_BR2: + description: GPDMA channel 12 block register 2 + fields: + - name: BRSAO + description: "Block repeated source address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRSDEC) the current source address (CH[x].SAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued." + bit_offset: 0 + bit_size: 16 + - name: BRDAO + description: "Block repeated destination address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRDDEC) the current destination address (CH[x].DAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued." + bit_offset: 16 + bit_size: 16 +fieldset/CH_CR: + description: GPDMA channel 11 control register + fields: + - name: EN + description: "enable. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored." + bit_offset: 0 + bit_size: 1 + - name: RESET + description: "reset. This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (CH[x].SR.SUSPF = 1 and CH[x].SR.IDLEF = CH[x].CR.EN = 1). - channel in disabled state (CH[x].SR.IDLEF = 1 and CH[x].CR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (CH[x].BR1, CH[x].SAR and CH[x].DAR) before enabling again the channel (see the programming sequence in )." + bit_offset: 1 + bit_size: 1 + - name: SUSP + description: "suspend. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going GPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in ." + bit_offset: 2 + bit_size: 1 + - name: TCIE + description: transfer complete interrupt enable + bit_offset: 8 + bit_size: 1 + - name: HTIE + description: half transfer complete interrupt enable + bit_offset: 9 + bit_size: 1 + - name: DTEIE + description: data transfer error interrupt enable + bit_offset: 10 + bit_size: 1 + - name: ULEIE + description: update link transfer error interrupt enable + bit_offset: 11 + bit_size: 1 + - name: USEIE + description: user setting error interrupt enable + bit_offset: 12 + bit_size: 1 + - name: SUSPIE + description: completed suspension interrupt enable + bit_offset: 13 + bit_size: 1 + - name: TOIE + description: trigger overrun interrupt enable + bit_offset: 14 + bit_size: 1 + - name: LSM + description: "Link step mode. First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by CH[x].LLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1." + bit_offset: 16 + bit_size: 1 + enum: CH_CR_LSM + - name: LAP + description: "linked-list allocated port. This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1." + bit_offset: 17 + bit_size: 1 + enum: CH_CR_LAP + - name: PRIO + description: "priority level of the channel x GPDMA transfer versus others. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1." + bit_offset: 22 + bit_size: 2 + enum: CH_CR_PRIO +fieldset/CH_FCR: + description: GPDMA channel 7 flag clear register + fields: + - name: TCF + description: transfer complete flag clear + bit_offset: 8 + bit_size: 1 + - name: HTF + description: half transfer flag clear + bit_offset: 9 + bit_size: 1 + - name: DTEF + description: data transfer error flag clear + bit_offset: 10 + bit_size: 1 + - name: ULEF + description: update link transfer error flag clear + bit_offset: 11 + bit_size: 1 + - name: USEF + description: user setting error flag clear + bit_offset: 12 + bit_size: 1 + - name: SUSPF + description: completed suspension flag clear + bit_offset: 13 + bit_size: 1 + - name: TOF + description: trigger overrun flag clear + bit_offset: 14 + bit_size: 1 +fieldset/CH_LBAR: + description: GPDMA channel 14 linked-list base address register + fields: + - name: LBA + description: linked-list base address of GPDMA channel x + bit_offset: 16 + bit_size: 16 +fieldset/CH_LLR: + description: GPDMA channel 15 alternate linked-list address register + fields: + - name: LA + description: "pointer (16-bit low-significant address) to the next linked-list data structure. If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (CH[x].CTR1, CH[x].TR2, CH[x].BR1, CH[x].SAR, CH[x].DAR and CH[x].LLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored." + bit_offset: 2 + bit_size: 14 + - name: ULL + description: "Update CH[x].LLR register from memory. This bit is used to control the update of CH[x].LLR from the memory during the link transfer." + bit_offset: 16 + bit_size: 1 + - name: UB2 + description: "Update CH[x].BR2 from memory. This bit controls the update of CH[x].BR2 from the memory during the link transfer." + bit_offset: 25 + bit_size: 1 + - name: UT3 + description: "Update CH[x].TR3 from memory. This bit controls the update of CH[x].TR3 from the memory during the link transfer." + bit_offset: 26 + bit_size: 1 + - name: UDA + description: "Update CH[x].DAR register from memory. This bit is used to control the update of CH[x].DAR from the memory during the link transfer." + bit_offset: 27 + bit_size: 1 + - name: USA + description: "update CH[x].SAR from memory. This bit controls the update of CH[x].SAR from the memory during the link transfer." + bit_offset: 28 + bit_size: 1 + - name: UB1 + description: "Update CH[x].BR1 from memory. This bit controls the update of CH[x].BR1 from the memory during the link transfer. If UB1 = 0 and if CH[x].LLR ≠ 0, the linked-list is not completed. CH[x].BR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer." + bit_offset: 29 + bit_size: 1 + - name: UT2 + description: "Update CH[x].TR2 from memory. This bit controls the update of CH[x].TR2 from the memory during the link transfer." + bit_offset: 30 + bit_size: 1 + - name: UT1 + description: "Update CH[x].TR1 from memory. This bit controls the update of CH[x].TR1 from the memory during the link transfer." + bit_offset: 31 + bit_size: 1 +fieldset/CH_SR: + description: GPDMA channel 15 status register + fields: + - name: IDLEF + description: "idle flag. This idle flag is de-asserted by hardware when the channel is enabled (CH[x].CR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state)." + bit_offset: 0 + bit_size: 1 + - name: TCF + description: "transfer complete flag. A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0])." + bit_offset: 8 + bit_size: 1 + - name: HTF + description: "half transfer flag. An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of CH[x].BR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (CH[x].BR1.BRC[10:0]+1)/2)) has been transferred to the destination." + bit_offset: 9 + bit_size: 1 + - name: DTEF + description: data transfer error flag + bit_offset: 10 + bit_size: 1 + - name: ULEF + description: update link transfer error flag + bit_offset: 11 + bit_size: 1 + - name: USEF + description: user setting error flag + bit_offset: 12 + bit_size: 1 + - name: SUSPF + description: completed suspension flag + bit_offset: 13 + bit_size: 1 + - name: TOF + description: trigger overrun flag + bit_offset: 14 + bit_size: 1 + - name: FIFOL + description: "monitored FIFO level. Number of available write beats in the FIFO, in units of the programmed destination data width (see CH[x].TR1.DDW[1:0], in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to CH[x].BR1.BDNT[15:0] and CH[x].BR1.BRC[10:0], to know how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be suspended (CH[x].SR.SUSPF = 1)." + bit_offset: 16 + bit_size: 8 +fieldset/CH_TR1: + description: GPDMA channel 8 transfer register 1 + fields: + - name: SDW + description: "binary logarithm of the source data width of a burst in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (CH[x].BR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address CH[x].SAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued." + bit_offset: 0 + bit_size: 2 + enum: CH_TR1_DW + - name: SINC + description: "source incrementing burst. The source address, pointed by CH[x].SAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer." + bit_offset: 3 + bit_size: 1 + - name: SBL_1 + description: "source burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If SBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed." + bit_offset: 4 + bit_size: 6 + - name: PAM + description: "padding/alignment mode. If DDW[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer. - Case 2: If destination data width < source data width. 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination. Note:" + bit_offset: 11 + bit_size: 2 + enum: CH_TR1_PAM + - name: SBX + description: "source byte exchange within the unaligned half-word of each source word. If set, the two consecutive bytes within the unaligned half-word of each source word are exchanged. If the source data width is shorter than a word, this bit is ignored." + bit_offset: 13 + bit_size: 1 + - name: SAP + description: "source allocated port. This bit is used to allocate the master port for the source transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1." + bit_offset: 14 + bit_size: 1 + enum: CH_TR1_AP + - name: SSEC + description: "security attribute of the GPDMA transfer from the source. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx =1 . A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer from the source is non-secure." + bit_offset: 15 + bit_size: 1 + - name: DDW + description: "binary logarithm of the destination data width of a burst, in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address CH[x].DAR[2:0] and address offset CH[x].TR3.DAO[2:0], versus DDW[1:0]). Otherwise a user setting error is reported and no transfer is issued." + bit_offset: 16 + bit_size: 2 + enum: CH_TR1_DW + - name: DINC + description: "destination incrementing burst. The destination address, pointed by CH[x].DAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer." + bit_offset: 19 + bit_size: 1 + - name: DBL_1 + description: "destination burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If DBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed." + bit_offset: 20 + bit_size: 6 + - name: DBX + description: "destination byte exchange. IF set, the two consecutive (post PAM) bytes are exchanged in each destination half-word. If the destination data size is a byte, this bit is ignored." + bit_offset: 26 + bit_size: 1 + - name: DHX + description: "destination half-word exchange. If set, e two consecutive (post PAM) half-words are exchanged in each destination word. If the destination data size is shorter than a word, this bit is ignored." + bit_offset: 27 + bit_size: 1 + - name: DAP + description: "destination allocated port. This bit is used to allocate the master port for the destination transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1." + bit_offset: 30 + bit_size: 1 + enum: CH_TR1_AP + - name: DSEC + description: "security attribute of the GPDMA transfer to the destination. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx = 1. A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer to the destination is non-secure." + bit_offset: 31 + bit_size: 1 +fieldset/CH_TR2: + description: GPDMA channel 10 transfer register 2 + fields: + - name: REQSEL + description: "GPDMA hardware request selection. These bits are ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per . The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active GPDMA channels (CH[x].CR.EN = 1 and CH[x].TR2.SWREQ = 0 for these channels). GPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting." + bit_offset: 0 + bit_size: 7 + - name: SWREQ + description: "software request. This bit is internally taken into account when CH[x].CR.EN is asserted." + bit_offset: 9 + bit_size: 1 + enum: CH_TR2_SWREQ + - name: DREQ + description: "destination hardware request. This bit is ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note:" + bit_offset: 10 + bit_size: 1 + enum: CH_TR2_DREQ + - name: BREQ + description: "Block hardware request. If the channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:" + bit_offset: 11 + bit_size: 1 + enum: CH_TR2_BREQ + - name: TRIGM + description: "trigger mode. These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (CH[x].CR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a GPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. – If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. – If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The GPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the CH[x].TR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (CH[x].SR.TOF =1 ), and an interrupt is generated if enabled (CH[x].CR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger." + bit_offset: 14 + bit_size: 2 + enum: CH_TR2_TRIGM + - name: TRIGSEL + description: "trigger event input selection. These bits select the trigger event input of the GPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0] ≠ 00." + bit_offset: 16 + bit_size: 6 + - name: TRIGPOL + description: "trigger event polarity. These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0]." + bit_offset: 24 + bit_size: 2 + enum: CH_TR2_TRIGPOL + - name: TCEM + description: "transfer complete event mode. These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1." + bit_offset: 30 + bit_size: 2 + enum: CH_TR2_TCEM +fieldset/CH_TR3: + description: GPDMA channel 14 transfer register 3 + fields: + - name: SAO + description: "source address offset increment. The source address, pointed by CH[x].SAR, is incremented or decremented (depending on CH[x].BR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional CH[x].TR3.SAO[12:0] is not applied." + bit_offset: 0 + bit_size: 13 + - name: DAO + description: "destination address offset increment. The destination address, pointed by CH[x].DAR, is incremented or decremented (depending on CH[x].BR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus CH[x].TR1.DDW[1:0]). Else, a user setting error is reported and no transfer is issued." + bit_offset: 16 + bit_size: 13 +fieldset/MISR: + description: GPDMA secure masked interrupt status register + fields: + - name: MIS + description: MIS0 + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 +fieldset/PRIVCFGR: + description: GPDMA privileged configuration register + fields: + - name: PRIV + description: PRIV0 + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 +fieldset/RCFGLOCKR: + description: GPDMA configuration lock register + fields: + - name: LOCK + description: LOCK0 + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 +fieldset/SECCFGR: + description: GPDMA secure configuration register + fields: + - name: SEC + description: SEC0 + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 +enum/CH_BR1_DEC: + bit_size: 1 + variants: + - name: Add + description: The address is incremented by the programmed offset. + value: 0 + - name: Subtract + description: The address is decremented by the programmed offset. + value: 1 +enum/CH_CR_LAP: + bit_size: 1 + variants: + - name: Port0 + description: port 0 (AHB) allocated + value: 0 + - name: Port1 + description: port 1 (AHB) allocated + value: 1 +enum/CH_CR_LSM: + bit_size: 1 + variants: + - name: RunToCompletion + description: "channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present." + value: 0 + - name: LinkStep + description: channel executed once for the current LLI + value: 1 +enum/CH_CR_PRIO: + bit_size: 2 + variants: + - name: LowWithLowhWeight + description: "low priority, low weight" + value: 0 + - name: LowWithMidWeight + description: "low priority, mid weight" + value: 1 + - name: LowWithHighWeight + description: "low priority, high weight" + value: 2 + - name: High + description: high priority + value: 3 +enum/CH_TR1_AP: + bit_size: 1 + variants: + - name: Port0 + description: port 0 (AHB) allocated + value: 0 + - name: Port1 + description: port 1 (AHB) allocated + value: 1 +enum/CH_TR1_DW: + bit_size: 2 + variants: + - name: Byte + description: byte + value: 0 + - name: HalfWord + description: half-word (2 bytes) + value: 1 + - name: Word + description: word (4 bytes) + value: 2 +enum/CH_TR1_PAM: + bit_size: 2 + variants: + - name: ZeroExtendOrLeftTruncate + description: "If destination is wider: source data is transferred as right aligned, padded with 0s up to the destination data width\nIf source is wider: source data is transferred as right aligned, left-truncated down to the destination data width" + value: 0 + - name: SignExtendOrRightTruncate + description: "If destination is wider: source data is transferred as right aligned, sign extended up to the destination data width\nIf source is wider: source data is transferred as left-aligned, right-truncated down to the destination data width" + value: 1 + - name: Pack + description: "source data is FIFO queued and packed/unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination" + value: 2 +enum/CH_TR2_BREQ: + bit_size: 1 + variants: + - name: Burst + description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + value: 0 + - name: Block + description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ). + value: 1 +enum/CH_TR2_DREQ: + bit_size: 1 + variants: + - name: SourcePeripheral + description: selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + value: 0 + - name: DestinationPeripheral + description: selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + value: 1 +enum/CH_TR2_SWREQ: + bit_size: 1 + variants: + - name: Hardware + description: "no software request. The selected hardware request REQSEL[6:0] is taken into account." + value: 0 + - name: Software + description: "software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored." + value: 1 +enum/CH_TR2_TCEM: + bit_size: 2 + variants: + - name: EachBlock + description: "at block level (when CH[x].BR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." + value: 0 + - name: Each2DBlock + description: "channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when CH[x].BR1.BRC[10:0] = 0 and CH[x].BR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." + value: 1 + - name: EachLinkedListItem + description: "at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." + value: 2 + - name: LastLinkedListItem + description: "at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address CH[x].LLR.LA[15:2] to zero and clears all the CH[x].LLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." + value: 3 +enum/CH_TR2_TRIGM: + bit_size: 2 + variants: + - name: Block + description: "at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with CH[x].BR1.BRC[10:0] ≠ 0)." + value: 0 + - name: 2DBlock + description: "channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" + value: 1 + - name: LinkedListItem + description: "at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." + value: 2 + - name: Burst + description: "at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." + value: 3 +enum/CH_TR2_TRIGPOL: + bit_size: 2 + variants: + - name: None + description: no trigger (masked trigger event) + value: 0 + - name: RisingEdge + description: trigger on the rising edge + value: 1 + - name: FallingEdge + description: trigger on the falling edge + value: 2 + - name: NoneAlt + description: same as 00 + value: 3 diff --git a/data/registers/spi_v4.yaml b/data/registers/spi_v4.yaml new file mode 100644 index 0000000..b7f7092 --- /dev/null +++ b/data/registers/spi_v4.yaml @@ -0,0 +1,722 @@ +--- +block/SPI: + description: Serial peripheral interface + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CFG1 + description: configuration register 1 + byte_offset: 8 + fieldset: CFG1 + - name: CFG2 + description: configuration register 2 + byte_offset: 12 + fieldset: CFG2 + - name: IER + description: Interrupt Enable Register + byte_offset: 16 + fieldset: IER + - name: SR + description: Status Register + byte_offset: 20 + access: Read + fieldset: SR + - name: IFCR + description: Interrupt/Status Flags Clear Register + byte_offset: 24 + access: Write + fieldset: IFCR + - name: AUTOCR + byte_offset: 28 + fieldset: AUTOCR + - name: TXDR + description: Transmit Data Register + byte_offset: 32 + access: Write + fieldset: TXDR + - name: RXDR + description: Receive Data Register + byte_offset: 48 + access: Read + fieldset: RXDR + - name: CRCPOLY + description: Polynomial Register + byte_offset: 64 + fieldset: CRCPOLY + - name: TXCRC + description: Transmitter CRC Register + byte_offset: 68 + fieldset: TXCRC + - name: RXCRC + description: Receiver CRC Register + byte_offset: 72 + fieldset: RXCRC + - name: UDRDR + description: Underrun Data Register + byte_offset: 76 + fieldset: UDRDR +fieldset/AUTOCR: + fields: + - name: TRIGSEL + description: "trigger selection (refer ).\n ...\n Note: these bits can be written only when SPE = 0." + bit_offset: 16 + bit_size: 4 + - name: TRIGPOL + description: "trigger polarity\n Note: This bit can be written only when SPE = 0." + bit_offset: 20 + bit_size: 1 + enum: TRIGPOL + - name: TRIGEN + description: "trigger of CSTART control enable\n Note: if user can't prevent trigger event during write, the TRIGEN has to be changed when SPI is disabled" + bit_offset: 21 + bit_size: 1 +fieldset/CFG1: + description: configuration register 1 + fields: + - name: DSIZE + description: Number of bits in at single SPI data frame + bit_offset: 0 + bit_size: 5 + - name: FTHLV + description: threshold level + bit_offset: 5 + bit_size: 4 + enum: FTHLV + - name: UDRCFG + description: Behavior of slave transmitter at underrun condition + bit_offset: 9 + bit_size: 2 + enum: UDRCFG + - name: RXDMAEN + description: Rx DMA stream enable + bit_offset: 14 + bit_size: 1 + - name: TXDMAEN + description: Tx DMA stream enable + bit_offset: 15 + bit_size: 1 + - name: CRCSIZE + description: Length of CRC frame to be transacted and compared + bit_offset: 16 + bit_size: 5 + - name: CRCEN + description: Hardware CRC computation enable + bit_offset: 22 + bit_size: 1 + - name: MBR + description: Master baud rate + bit_offset: 28 + bit_size: 3 + enum: MBR + - name: BPASS + description: bypass of the prescaler at master baud rate clock generator + bit_offset: 31 + bit_size: 1 +fieldset/CFG2: + description: configuration register 2 + fields: + - name: MSSI + description: Master SS Idleness + bit_offset: 0 + bit_size: 4 + - name: MIDI + description: Master Inter-Data Idleness + bit_offset: 4 + bit_size: 4 + - name: RDIOM + description: "RDY signal input/output management\n Note: When DSIZE at the CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero." + bit_offset: 13 + bit_size: 1 + enum: RDIOM + - name: RDIOP + description: RDY signal input/output polarity + bit_offset: 14 + bit_size: 1 + enum: RDIOP + - name: IOSWP + description: Swap functionality of MISO and MOSI pins + bit_offset: 15 + bit_size: 1 + - name: COMM + description: SPI Communication Mode + bit_offset: 17 + bit_size: 2 + enum: COMM + - name: SP + description: Serial Protocol + bit_offset: 19 + bit_size: 3 + enum: SP + - name: MASTER + description: SPI Master + bit_offset: 22 + bit_size: 1 + enum: MASTER + - name: LSBFIRST + description: Data frame format + bit_offset: 23 + bit_size: 1 + enum: LSBFIRST + - name: CPHA + description: Clock phase + bit_offset: 24 + bit_size: 1 + enum: CPHA + - name: CPOL + description: Clock polarity + bit_offset: 25 + bit_size: 1 + enum: CPOL + - name: SSM + description: Software management of SS signal input + bit_offset: 26 + bit_size: 1 + - name: SSIOP + description: SS input/output polarity + bit_offset: 28 + bit_size: 1 + enum: SSIOP + - name: SSOE + description: SS output enable + bit_offset: 29 + bit_size: 1 + - name: SSOM + description: SS output management in master mode + bit_offset: 30 + bit_size: 1 + enum: SSOM + - name: AFCNTR + description: Alternate function GPIOs control + bit_offset: 31 + bit_size: 1 + enum: AFCNTR +fieldset/CR1: + description: control register 1 + fields: + - name: SPE + description: Serial Peripheral Enable + bit_offset: 0 + bit_size: 1 + - name: MASRX + description: Master automatic SUSP in Receive mode + bit_offset: 8 + bit_size: 1 + - name: CSTART + description: Master transfer start + bit_offset: 9 + bit_size: 1 + - name: CSUSP + description: Master SUSPend request + bit_offset: 10 + bit_size: 1 + - name: HDDIR + description: Rx/Tx direction at Half-duplex mode + bit_offset: 11 + bit_size: 1 + enum: HDDIR + - name: SSI + description: Internal SS signal input level + bit_offset: 12 + bit_size: 1 + - name: CRC33_17 + description: 32-bit CRC polynomial configuration + bit_offset: 13 + bit_size: 1 + enum: CRC_ + - name: RCRCINI + description: CRC calculation initialization pattern control for receiver + bit_offset: 14 + bit_size: 1 + enum: RCRCINI + - name: TCRCINI + description: CRC calculation initialization pattern control for transmitter + bit_offset: 15 + bit_size: 1 + enum: TCRCINI + - name: IOLOCK + description: Locking the AF configuration of associated IOs + bit_offset: 16 + bit_size: 1 +fieldset/CR2: + description: control register 2 + fields: + - name: TSIZE + description: Number of data at current transfer + bit_offset: 0 + bit_size: 16 +fieldset/CRCPOLY: + description: Polynomial Register + fields: + - name: CRCPOLY + description: CRC polynomial register + bit_offset: 0 + bit_size: 32 +fieldset/IER: + description: Interrupt Enable Register + fields: + - name: RXPIE + description: RXP Interrupt Enable + bit_offset: 0 + bit_size: 1 + - name: TXPIE + description: TXP interrupt enable + bit_offset: 1 + bit_size: 1 + - name: DXPIE + description: DXP interrupt enabled + bit_offset: 2 + bit_size: 1 + - name: EOTIE + description: "EOT, SUSP and TXC interrupt enable" + bit_offset: 3 + bit_size: 1 + - name: TXTFIE + description: TXTFIE interrupt enable + bit_offset: 4 + bit_size: 1 + - name: UDRIE + description: UDR interrupt enable + bit_offset: 5 + bit_size: 1 + - name: OVRIE + description: OVR interrupt enable + bit_offset: 6 + bit_size: 1 + - name: CRCEIE + description: CRC Interrupt enable + bit_offset: 7 + bit_size: 1 + - name: TIFREIE + description: TIFRE interrupt enable + bit_offset: 8 + bit_size: 1 + - name: MODFIE + description: Mode Fault interrupt enable + bit_offset: 9 + bit_size: 1 +fieldset/IFCR: + description: Interrupt/Status Flags Clear Register + fields: + - name: EOTC + description: End Of Transfer flag clear + bit_offset: 3 + bit_size: 1 + - name: TXTFC + description: Transmission Transfer Filled flag clear + bit_offset: 4 + bit_size: 1 + - name: UDRC + description: Underrun flag clear + bit_offset: 5 + bit_size: 1 + - name: OVRC + description: Overrun flag clear + bit_offset: 6 + bit_size: 1 + - name: CRCEC + description: CRC Error flag clear + bit_offset: 7 + bit_size: 1 + - name: TIFREC + description: TI frame format error flag clear + bit_offset: 8 + bit_size: 1 + - name: MODFC + description: Mode Fault flag clear + bit_offset: 9 + bit_size: 1 + - name: SUSPC + description: SUSPend flag clear + bit_offset: 11 + bit_size: 1 +fieldset/RXCRC: + description: Receiver CRC Register + fields: + - name: RXCRC + description: CRC register for receiver + bit_offset: 0 + bit_size: 32 +fieldset/RXDR: + description: Receive Data Register + fields: + - name: RXDR + description: Receive data register + bit_offset: 0 + bit_size: 32 +fieldset/SR: + description: Status Register + fields: + - name: RXP + description: Rx-Packet available + bit_offset: 0 + bit_size: 1 + - name: TXP + description: Tx-Packet space available + bit_offset: 1 + bit_size: 1 + - name: DXP + description: Duplex Packet + bit_offset: 2 + bit_size: 1 + - name: EOT + description: End Of Transfer + bit_offset: 3 + bit_size: 1 + - name: TXTF + description: Transmission Transfer Filled + bit_offset: 4 + bit_size: 1 + - name: UDR + description: Underrun at slave transmission mode + bit_offset: 5 + bit_size: 1 + - name: OVR + description: Overrun + bit_offset: 6 + bit_size: 1 + - name: CRCE + description: CRC Error + bit_offset: 7 + bit_size: 1 + - name: TIFRE + description: TI frame format error + bit_offset: 8 + bit_size: 1 + - name: MODF + description: Mode Fault + bit_offset: 9 + bit_size: 1 + - name: SUSP + description: SUSPend + bit_offset: 11 + bit_size: 1 + - name: TXC + description: TxFIFO transmission complete + bit_offset: 12 + bit_size: 1 + - name: RXPLVL + description: RxFIFO Packing LeVeL + bit_offset: 13 + bit_size: 2 + enum: RXPLVL + - name: RXWNE + description: RxFIFO Word Not Empty + bit_offset: 15 + bit_size: 1 + enum: RXWNE + - name: CTSIZE + description: Number of data frames remaining in current TSIZE session + bit_offset: 16 + bit_size: 16 +fieldset/TXCRC: + description: Transmitter CRC Register + fields: + - name: TXCRC + description: CRC register for transmitter + bit_offset: 0 + bit_size: 32 +fieldset/TXDR: + description: Transmit Data Register + fields: + - name: TXDR + description: Transmit data register + bit_offset: 0 + bit_size: 32 +fieldset/UDRDR: + description: Underrun Data Register + fields: + - name: UDRDR + description: Data at slave underrun condition + bit_offset: 0 + bit_size: 32 +enum/AFCNTR: + bit_size: 1 + variants: + - name: NotControlled + description: Peripheral takes no control of GPIOs while disabled + value: 0 + - name: Controlled + description: Peripheral controls GPIOs while disabled + value: 1 +enum/COMM: + bit_size: 2 + variants: + - name: FullDuplex + description: Full duplex + value: 0 + - name: Transmitter + description: Simplex transmitter only + value: 1 + - name: Receiver + description: Simplex receiver only + value: 2 + - name: HalfDuplex + description: Half duplex + value: 3 +enum/CPHA: + bit_size: 1 + variants: + - name: FirstEdge + description: The first clock transition is the first data capture edge + value: 0 + - name: SecondEdge + description: The second clock transition is the first data capture edge + value: 1 +enum/CPOL: + bit_size: 1 + variants: + - name: IdleLow + description: CK to 0 when idle + value: 0 + - name: IdleHigh + description: CK to 1 when idle + value: 1 +enum/CRC_: + bit_size: 1 + variants: + - name: Disabled + description: Full size (33/17 bit) CRC polynomial is not used + value: 0 + - name: Enabled + description: Full size (33/17 bit) CRC polynomial is used + value: 1 +enum/DATFMT: + bit_size: 1 + variants: + - name: RightAligned + description: The data inside RXDR and TXDR are right aligned + value: 0 + - name: LeftAligned + description: The data inside RXDR and TXDR are left aligned + value: 1 +enum/DATLEN: + bit_size: 2 + variants: + - name: Bits16 + description: 16 bit data length + value: 0 + - name: Bits24 + description: 24 bit data length + value: 1 + - name: Bits32 + description: 32 bit data length + value: 2 +enum/FTHLV: + bit_size: 4 + variants: + - name: OneFrame + description: 1 frame + value: 0 + - name: TwoFrames + description: 2 frames + value: 1 + - name: ThreeFrames + description: 3 frames + value: 2 + - name: FourFrames + description: 4 frames + value: 3 + - name: FiveFrames + description: 5 frames + value: 4 + - name: SixFrames + description: 6 frames + value: 5 + - name: SevenFrames + description: 7 frames + value: 6 + - name: EightFrames + description: 8 frames + value: 7 + - name: NineFrames + description: 9 frames + value: 8 + - name: TenFrames + description: 10 frames + value: 9 + - name: ElevenFrames + description: 11 frames + value: 10 + - name: TwelveFrames + description: 12 frames + value: 11 + - name: ThirteenFrames + description: 13 frames + value: 12 + - name: FourteenFrames + description: 14 frames + value: 13 + - name: FifteenFrames + description: 15 frames + value: 14 + - name: SixteenFrames + description: 16 frames + value: 15 +enum/HDDIR: + bit_size: 1 + variants: + - name: Receiver + description: Receiver in half duplex mode + value: 0 + - name: Transmitter + description: Transmitter in half duplex mode + value: 1 +enum/LSBFIRST: + bit_size: 1 + variants: + - name: MSBFirst + description: Data is transmitted/received with the MSB first + value: 0 + - name: LSBFirst + description: Data is transmitted/received with the LSB first + value: 1 +enum/MASTER: + bit_size: 1 + variants: + - name: Slave + description: Slave configuration + value: 0 + - name: Master + description: Master configuration + value: 1 +enum/MBR: + bit_size: 3 + variants: + - name: Div2 + description: f_spi_ker_ck / 2 + value: 0 + - name: Div4 + description: f_spi_ker_ck / 4 + value: 1 + - name: Div8 + description: f_spi_ker_ck / 8 + value: 2 + - name: Div16 + description: f_spi_ker_ck / 16 + value: 3 + - name: Div32 + description: f_spi_ker_ck / 32 + value: 4 + - name: Div64 + description: f_spi_ker_ck / 64 + value: 5 + - name: Div128 + description: f_spi_ker_ck / 128 + value: 6 + - name: Div256 + description: f_spi_ker_ck / 256 + value: 7 +enum/RCRCINI: + bit_size: 1 + variants: + - name: AllZeros + description: All zeros RX CRC initialization pattern + value: 0 + - name: AllOnes + description: All ones RX CRC initialization pattern + value: 1 +enum/RDIOM: + bit_size: 1 + variants: + - name: PermanentlyActive + description: RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) + value: 0 + - name: FromInput + description: RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) + value: 1 +enum/RDIOP: + bit_size: 1 + variants: + - name: ReadyHigh + description: high level of the signal means the slave is ready for communication + value: 0 + - name: ReadyLow + description: low level of the signal means the slave is ready for communication + value: 1 +enum/RXPLVL: + bit_size: 2 + variants: + - name: ZeroFrames + description: Zero frames beyond packing ratio available + value: 0 + - name: OneFrame + description: One frame beyond packing ratio available + value: 1 + - name: TwoFrames + description: Two frame beyond packing ratio available + value: 2 + - name: ThreeFrames + description: Three frame beyond packing ratio available + value: 3 +enum/RXWNE: + bit_size: 1 + variants: + - name: LessThan32 + description: Less than 32-bit data frame received + value: 0 + - name: AtLeast32 + description: At least 32-bit data frame received + value: 1 +enum/SP: + bit_size: 3 + variants: + - name: Motorola + description: Motorola SPI protocol + value: 0 + - name: TI + description: TI SPI protocol + value: 1 +enum/SSIOP: + bit_size: 1 + variants: + - name: ActiveLow + description: Low level is active for SS signal + value: 0 + - name: ActiveHigh + description: High level is active for SS signal + value: 1 +enum/SSOM: + bit_size: 1 + variants: + - name: Asserted + description: SS is asserted until data transfer complete + value: 0 + - name: NotAsserted + description: Data frames interleaved with SS not asserted during MIDI + value: 1 +enum/TCRCINI: + bit_size: 1 + variants: + - name: AllZeros + description: All zeros TX CRC initialization pattern + value: 0 + - name: AllOnes + description: All ones TX CRC initialization pattern + value: 1 +enum/TRIGPOL: + bit_size: 1 + variants: + - name: RisingEdge + description: trigger is active on raising edge + value: 0 + - name: FallingEdge + description: trigger is active on falling edge + value: 1 +enum/UDRCFG: + bit_size: 2 + variants: + - name: Constant + description: Slave sends a constant underrun pattern + value: 0 + - name: RepeatReceived + description: Slave repeats last received data frame from master + value: 1 + - name: RepeatTransmitted + description: Slave repeats last transmitted data frame + value: 2 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index b25c0bb..57d19eb 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -114,6 +114,7 @@ perimap = [ ('.*:SPI:spi2s1_v3_1', ('spi', 'v2', 'SPI')), ('.*:SPI:spi2s2_v1_1', ('spi', 'v3', 'SPI')), ('.*:SPI:spi2s2_v1_0', ('spi', 'v3', 'SPI')), + ('.*:SPI:spi2s3_v1_1', ('spi', 'v4', 'SPI')), ('.*:I2C:i2c1_v1_5', ('i2c', 'v1', 'I2C')), ('.*:I2C:i2c2_v1_1', ('i2c', 'v2', 'I2C')), ('.*:I2C:i2c2_v1_1F7', ('i2c', 'v2', 'I2C')), @@ -282,6 +283,7 @@ perimap = [ ('.*:IPCC:v1_0', ('ipcc', 'v1', 'IPCC')), ('.*:DMAMUX.*', ('dmamux', 'v1', 'DMAMUX')), + ('.*:GPDMA\d?:.*', ('gpdma', 'v1', 'GPDMA')), ('.*:BDMA\d?:.*', ('bdma', 'v1', 'DMA')), ('STM32H7.*:DMA2D:DMA2D:dma2d1_v1_0', ('dma2d', 'v2', 'DMA2D')), ('.*:DMA2D:dma2d1_v1_0', ('dma2d', 'v1', 'DMA2D')), @@ -771,12 +773,11 @@ def parse_chips(): # Collect DMA versions in the chip chip_dmas = [] - for want_kind in ('DMA', 'BDMA', 'BDMA1', 'BDMA2'): - for ip in chip['ips'].values(): - pkind = ip['@Name'] - version = ip['@Version'] - if pkind == want_kind and version in dma_channels and version not in chip_dmas: - chip_dmas.append(version) + for ip in chip['ips'].values(): + pkind = ip['@Name'] + version = ip['@Version'] + if pkind in ('DMA', 'BDMA', 'BDMA1', 'BDMA2', 'GPDMA') and version in dma_channels and version not in chip_dmas: + chip_dmas.append(version) # Process DMA channels chs = [] @@ -1180,6 +1181,42 @@ def parse_dma(): dma_channels[ff] = chip_dma + # STM32U5 + + chip_dma = { + 'channels': [], + 'peripherals': {}, + } + + with open('data/dmamux/U5_GPDMA1.yaml', 'r') as yaml_file: + y = yaml.load(yaml_file) + + for (request_name, request_num) in y.items(): + parts = request_name.split('_') + target_peri_name = parts[0] + if len(parts) < 2: + request = target_peri_name + else: + request = parts[1] + chip_dma['peripherals'].setdefault(target_peri_name, []).append({ + 'signal': request, + "dma": 'GPDMA1', + "request": request_num, + }) + + for i in range(16): + chip_dma['channels'].append({ + 'name': 'GPDMA1_CH' + str(i), + 'dma': 'GPDMA1', + 'channel': i, + 'supports_2d': i >= 12, + }) + + ff = 'STM32U5_dma3_Cube' + with open('tmp/dmas/' + ff + '.json', 'w') as f: + json.dump(chip_dma, f, indent=4) + dma_channels[ff] = chip_dma + peripheral_to_clock = {} From a87cf3419731d0060191a1e7017a46cbe2190bd0 Mon Sep 17 00:00:00 2001 From: Matous Hybl Date: Wed, 2 Mar 2022 18:33:42 +0100 Subject: [PATCH 23/35] Add ADC registers for F1 and H7 --- data/registers/adc_v1.yaml | 487 ++++++++++++++++ data/registers/adc_v4.yaml | 968 +++++++++++++++++++++++++++++++ data/registers/adccommon_v4.yaml | 367 ++++++++++++ stm32data/__main__.py | 6 + 4 files changed, 1828 insertions(+) create mode 100644 data/registers/adc_v1.yaml create mode 100644 data/registers/adc_v4.yaml create mode 100644 data/registers/adccommon_v4.yaml diff --git a/data/registers/adc_v1.yaml b/data/registers/adc_v1.yaml new file mode 100644 index 0000000..16f2352 --- /dev/null +++ b/data/registers/adc_v1.yaml @@ -0,0 +1,487 @@ +--- +block/ADC: + description: Analog-to-digital converter + items: + - name: ISR + description: interrupt and status register + byte_offset: 0 + fieldset: ISR + - name: IER + description: interrupt enable register + byte_offset: 4 + fieldset: IER + - name: CR + description: control register + byte_offset: 8 + fieldset: CR + - name: CFGR1 + description: configuration register 1 + byte_offset: 12 + fieldset: CFGR1 + - name: CFGR2 + description: configuration register 2 + byte_offset: 16 + fieldset: CFGR2 + - name: SMPR + description: sampling time register + byte_offset: 20 + fieldset: SMPR + - name: TR + description: watchdog threshold register + byte_offset: 32 + fieldset: TR + - name: CHSELR + description: channel selection register + byte_offset: 40 + fieldset: CHSELR + - name: DR + description: data register + byte_offset: 64 + access: Read + fieldset: DR + - name: CCR + description: common configuration register + byte_offset: 776 + fieldset: CCR +fieldset/CCR: + description: common configuration register + fields: + - name: VREFEN + description: Temperature sensor and VREFINT enable + bit_offset: 22 + bit_size: 1 + - name: TSEN + description: Temperature sensor enable + bit_offset: 23 + bit_size: 1 + - name: VBATEN + description: VBAT enable + bit_offset: 24 + bit_size: 1 +fieldset/CFGR1: + description: configuration register 1 + fields: + - name: DMAEN + description: Direct memory access enable + bit_offset: 0 + bit_size: 1 + - name: DMACFG + description: Direct memery access configuration + bit_offset: 1 + bit_size: 1 + enum: DMACFG + - name: SCANDIR + description: Scan sequence direction + bit_offset: 2 + bit_size: 1 + enum: SCANDIR + - name: RES + description: Data resolution + bit_offset: 3 + bit_size: 2 + enum: RES + - name: ALIGN + description: Data alignment + bit_offset: 5 + bit_size: 1 + enum: ALIGN + - name: EXTSEL + description: External trigger selection + bit_offset: 6 + bit_size: 3 + enum: EXTSEL + - name: EXTEN + description: External trigger enable and polarity selection + bit_offset: 10 + bit_size: 2 + enum: EXTEN + - name: OVRMOD + description: Overrun management mode + bit_offset: 12 + bit_size: 1 + enum: OVRMOD + - name: CONT + description: Single / continuous conversion mode + bit_offset: 13 + bit_size: 1 + - name: WAIT + description: Wait conversion mode + bit_offset: 14 + bit_size: 1 + - name: AUTOFF + description: Auto-off mode + bit_offset: 15 + bit_size: 1 + - name: DISCEN + description: Discontinuous mode + bit_offset: 16 + bit_size: 1 + - name: AWDSGL + description: Enable the watchdog on a single channel or on all channels + bit_offset: 22 + bit_size: 1 + enum: AWDSGL + - name: AWDEN + description: Analog watchdog enable + bit_offset: 23 + bit_size: 1 + - name: AWDCH + description: Analog watchdog channel selection + bit_offset: 26 + bit_size: 5 +fieldset/CFGR2: + description: configuration register 2 + fields: + - name: CKMODE + description: ADC clock mode + bit_offset: 30 + bit_size: 2 + enum: CKMODE +fieldset/CHSELR: + description: channel selection register + fields: + - name: CHSEL x + description: Channel-x selection + bit_offset: 0 + bit_size: 1 + array: + len: 19 + stride: 1 +fieldset/CR: + description: control register + fields: + - name: ADEN + description: ADC enable command + bit_offset: 0 + bit_size: 1 + enum_read: ADENR + enum_write: ADENW + - name: ADDIS + description: ADC disable command + bit_offset: 1 + bit_size: 1 + enum_read: ADDISR + enum_write: ADDISW + - name: ADSTART + description: ADC start conversion command + bit_offset: 2 + bit_size: 1 + enum_read: ADSTARTR + enum_write: ADSTARTW + - name: ADSTP + description: ADC stop conversion command + bit_offset: 4 + bit_size: 1 + enum_read: ADSTPR + enum_write: ADSTPW + - name: ADCAL + description: ADC calibration + bit_offset: 31 + bit_size: 1 + enum_read: ADCALR + enum_write: ADCALW +fieldset/DR: + description: data register + fields: + - name: DATA + description: Converted data + bit_offset: 0 + bit_size: 16 +fieldset/IER: + description: interrupt enable register + fields: + - name: ADRDYIE + description: ADC ready interrupt enable + bit_offset: 0 + bit_size: 1 + - name: EOSMPIE + description: End of sampling flag interrupt enable + bit_offset: 1 + bit_size: 1 + - name: EOCIE + description: End of conversion interrupt enable + bit_offset: 2 + bit_size: 1 + - name: EOSEQIE + description: End of conversion sequence interrupt enable + bit_offset: 3 + bit_size: 1 + - name: OVRIE + description: Overrun interrupt enable + bit_offset: 4 + bit_size: 1 + - name: AWDIE + description: Analog watchdog interrupt enable + bit_offset: 7 + bit_size: 1 +fieldset/ISR: + description: interrupt and status register + fields: + - name: ADRDY + description: ADC ready + bit_offset: 0 + bit_size: 1 + - name: EOSMP + description: End of sampling flag + bit_offset: 1 + bit_size: 1 + - name: EOC + description: End of conversion flag + bit_offset: 2 + bit_size: 1 + - name: EOSEQ + description: End of sequence flag + bit_offset: 3 + bit_size: 1 + - name: OVR + description: ADC overrun + bit_offset: 4 + bit_size: 1 + - name: AWD + description: Analog watchdog flag + bit_offset: 7 + bit_size: 1 +fieldset/SMPR: + description: sampling time register + fields: + - name: SMP + description: Sampling time selection + bit_offset: 0 + bit_size: 3 + enum: SMP +fieldset/TR: + description: watchdog threshold register + fields: + - name: LT + description: Analog watchdog lower threshold + bit_offset: 0 + bit_size: 12 + - name: HT + description: Analog watchdog higher threshold + bit_offset: 16 + bit_size: 12 +enum/ADCALR: + bit_size: 1 + variants: + - name: NotCalibrating + description: ADC calibration either not yet performed or completed + value: 0 + - name: Calibrating + description: ADC calibration in progress + value: 1 +enum/ADCALW: + bit_size: 1 + variants: + - name: StartCalibration + description: Start the ADC calibration sequence + value: 1 +enum/ADDISR: + bit_size: 1 + variants: + - name: NotDisabling + description: No disable command active + value: 0 + - name: Disabling + description: ADC disabling + value: 1 +enum/ADDISW: + bit_size: 1 + variants: + - name: Disable + description: Disable the ADC + value: 1 +enum/ADENR: + bit_size: 1 + variants: + - name: Disabled + description: ADC disabled + value: 0 + - name: Enabled + description: ADC enabled + value: 1 +enum/ADENW: + bit_size: 1 + variants: + - name: Enabled + description: Enable the ADC + value: 1 +enum/ADSTARTR: + bit_size: 1 + variants: + - name: NotActive + description: No conversion ongoing + value: 0 + - name: Active + description: ADC operating and may be converting + value: 1 +enum/ADSTARTW: + bit_size: 1 + variants: + - name: StartConversion + description: Start the ADC conversion (may be delayed for hardware triggers) + value: 1 +enum/ADSTPR: + bit_size: 1 + variants: + - name: NotStopping + description: No stop command active + value: 0 + - name: Stopping + description: ADC stopping conversion + value: 1 +enum/ADSTPW: + bit_size: 1 + variants: + - name: StopConversion + description: Stop the active conversion + value: 1 +enum/ALIGN: + bit_size: 1 + variants: + - name: Right + description: Right alignment + value: 0 + - name: Left + description: Left alignment + value: 1 +enum/AWDSGL: + bit_size: 1 + variants: + - name: AllChannels + description: Analog watchdog enabled on all channels + value: 0 + - name: SingleChannel + description: Analog watchdog enabled on a single channel + value: 1 +enum/CKMODE: + bit_size: 2 + variants: + - name: ADCCLK + description: Asynchronous clock mode + value: 0 + - name: PCLK_Div2 + description: Synchronous clock mode (PCLK/2) + value: 1 + - name: PCLK_Div4 + description: Sychronous clock mode (PCLK/4) + value: 2 +enum/DMACFG: + bit_size: 1 + variants: + - name: OneShot + description: DMA one shot mode + value: 0 + - name: Circular + description: DMA circular mode + value: 1 +enum/EXTEN: + bit_size: 2 + variants: + - name: Disabled + description: Trigger detection disabled + value: 0 + - name: RisingEdge + description: Trigger detection on the rising edge + value: 1 + - name: FallingEdge + description: Trigger detection on the falling edge + value: 2 + - name: BothEdges + description: Trigger detection on both the rising and falling edges + value: 3 +enum/EXTSEL: + bit_size: 3 + variants: + - name: TIM1_TRGO + description: Timer 1 TRGO Event + value: 0 + - name: TIM1_CC4 + description: Timer 1 CC4 event + value: 1 + - name: TIM2_TRGO + description: Timer 2 TRGO event + value: 2 + - name: TIM3_TRGO + description: Timer 3 TRGO event + value: 3 + - name: TIM15_TRGO + description: Timer 15 TRGO event + value: 4 +enum/OVRMOD: + bit_size: 1 + variants: + - name: Preserved + description: ADC_DR register is preserved with the old data when an overrun is detected + value: 0 + - name: Overwritten + description: ADC_DR register is overwritten with the last conversion result when an overrun is detected + value: 1 +enum/RES: + bit_size: 2 + variants: + - name: TwelveBit + description: 12-bit (14 ADCCLK cycles) + value: 0 + - name: TenBit + description: 10-bit (13 ADCCLK cycles) + value: 1 + - name: EightBit + description: 8-bit (11 ADCCLK cycles) + value: 2 + - name: SixBit + description: 6-bit (9 ADCCLK cycles) + value: 3 +enum/SCANDIR: + bit_size: 1 + variants: + - name: Upward + description: Upward scan (from CHSEL0 to CHSEL18) + value: 0 + - name: Backward + description: Backward scan (from CHSEL18 to CHSEL0) + value: 1 +enum/SMP: + bit_size: 3 + variants: + - name: Cycles1_5 + description: 1.5 cycles + value: 0 + - name: Cycles7_5 + description: 7.5 cycles + value: 1 + - name: Cycles13_5 + description: 13.5 cycles + value: 2 + - name: Cycles28_5 + description: 28.5 cycles + value: 3 + - name: Cycles41_5 + description: 41.5 cycles + value: 4 + - name: Cycles55_5 + description: 55.5 cycles + value: 5 + - name: Cycles71_5 + description: 71.5 cycles + value: 6 + - name: Cycles239_5 + description: 239.5 cycles + value: 7 +enum/TSEN: + bit_size: 1 + variants: + - name: Disabled + description: Temperature sensor disabled + value: 0 + - name: Enabled + description: Temperature sensor enabled + value: 1 +enum/VBATEN: + bit_size: 1 + variants: + - name: Disabled + description: V_BAT channel disabled + value: 0 + - name: Enabled + description: V_BAT channel enabled + value: 1 diff --git a/data/registers/adc_v4.yaml b/data/registers/adc_v4.yaml new file mode 100644 index 0000000..ceebe11 --- /dev/null +++ b/data/registers/adc_v4.yaml @@ -0,0 +1,968 @@ +--- +block/ADC: + description: Analog to Digital Converter + items: + - name: ISR + description: interrupt and status register + byte_offset: 0 + fieldset: ISR + - name: IER + description: interrupt enable register + byte_offset: 4 + fieldset: IER + - name: CR + description: control register + byte_offset: 8 + fieldset: CR + - name: CFGR + description: configuration register 1 + byte_offset: 12 + fieldset: CFGR + - name: CFGR2 + description: configuration register 2 + byte_offset: 16 + fieldset: CFGR2 + - name: SMPR + description: sampling time register 1-2 + byte_offset: 20 + array: + len: 2 + stride: 4 + fieldset: SMPR + - name: PCSEL + description: pre channel selection register + byte_offset: 28 + fieldset: PCSEL + - name: LTR1 + description: analog watchdog 1 threshold register + byte_offset: 32 + fieldset: LTR1 + - name: HTR1 + description: analog watchdog 2 threshold register + byte_offset: 36 + fieldset: HTR1 + - name: SQR1 + description: group regular sequencer ranks register 1 + byte_offset: 48 + fieldset: SQR1 + - name: SQR2 + description: group regular sequencer ranks register 2 + byte_offset: 52 + fieldset: SQR2 + - name: SQR3 + description: group regular sequencer ranks register 3 + byte_offset: 56 + fieldset: SQR3 + - name: SQR4 + description: group regular sequencer ranks register 4 + byte_offset: 60 + fieldset: SQR4 + - name: DR + description: group regular conversion data register + byte_offset: 64 + access: Read + fieldset: DR + - name: JSQR + description: group injected sequencer register + byte_offset: 76 + fieldset: JSQR + - name: OFR + description: offset number 1-4 register + byte_offset: 96 + array: + len: 4 + stride: 4 + fieldset: OFR + - name: JDR + description: group injected sequencer rank 1-4 register + byte_offset: 128 + array: + len: 4 + stride: 4 + access: Read + fieldset: JDR + - name: AWD2CR + description: analog watchdog 2 configuration register + byte_offset: 160 + fieldset: AWD2CR + - name: AWD3CR + description: analog watchdog 3 configuration register + byte_offset: 164 + fieldset: AWD3CR + - name: LTR2 + description: watchdog lower threshold register 2 + byte_offset: 176 + fieldset: LTR2 + - name: HTR2 + description: watchdog higher threshold register 2 + byte_offset: 180 + fieldset: HTR2 + - name: LTR3 + description: watchdog lower threshold register 3 + byte_offset: 184 + fieldset: LTR3 + - name: HTR3 + description: watchdog higher threshold register 3 + byte_offset: 188 + fieldset: HTR3 + - name: DIFSEL + description: channel differential or single-ended mode selection register + byte_offset: 192 + fieldset: DIFSEL + - name: CALFACT + description: calibration factors register + byte_offset: 196 + fieldset: CALFACT + - name: CALFACT2 + description: Calibration Factor register 2 + byte_offset: 200 + fieldset: CALFACT2 +fieldset/AWD2CR: + description: analog watchdog 2 configuration register + fields: + - name: AWD2CH + description: analog watchdog 2 monitored channel selection + bit_offset: 0 + bit_size: 1 + array: + len: 20 + stride: 1 +fieldset/AWD3CR: + description: analog watchdog 3 configuration register + fields: + - name: AWD3CH + description: analog watchdog 3 monitored channel selection + bit_offset: 1 + bit_size: 1 + array: + len: 20 + stride: 1 +fieldset/CALFACT: + description: calibration factors register + fields: + - name: CALFACT_S + description: calibration factor in single-ended mode + bit_offset: 0 + bit_size: 11 + - name: CALFACT_D + description: calibration factor in differential mode + bit_offset: 16 + bit_size: 11 +fieldset/CALFACT2: + description: Calibration Factor register 2 + fields: + - name: LINCALFACT + description: Linearity Calibration Factor + bit_offset: 0 + bit_size: 30 +fieldset/CFGR: + description: configuration register 1 + fields: + - name: DMNGT + description: DMA transfer enable + bit_offset: 0 + bit_size: 2 + enum: DMNGT + - name: RES + description: data resolution + bit_offset: 2 + bit_size: 3 + enum: RES + - name: EXTSEL + description: group regular external trigger source + bit_offset: 5 + bit_size: 5 + enum: EXTSEL + - name: EXTEN + description: group regular external trigger polarity + bit_offset: 10 + bit_size: 2 + enum: EXTEN + - name: OVRMOD + description: group regular overrun configuration + bit_offset: 12 + bit_size: 1 + enum: OVRMOD + - name: CONT + description: group regular continuous conversion mode + bit_offset: 13 + bit_size: 1 + - name: AUTDLY + description: low power auto wait + bit_offset: 14 + bit_size: 1 + - name: DISCEN + description: group regular sequencer discontinuous mode + bit_offset: 16 + bit_size: 1 + - name: DISCNUM + description: group regular sequencer discontinuous number of ranks + bit_offset: 17 + bit_size: 3 + - name: JDISCEN + description: group injected sequencer discontinuous mode + bit_offset: 20 + bit_size: 1 + - name: JQM + description: group injected contexts queue mode + bit_offset: 21 + bit_size: 1 + enum: JQM + - name: AWD1SGL + description: analog watchdog 1 monitoring a single channel or all channels + bit_offset: 22 + bit_size: 1 + enum: AWD1SGL + - name: AWD1EN + description: analog watchdog 1 enable on scope group regular + bit_offset: 23 + bit_size: 1 + - name: JAWD1EN + description: analog watchdog 1 enable on scope group injected + bit_offset: 24 + bit_size: 1 + - name: JAUTO + description: group injected automatic trigger mode + bit_offset: 25 + bit_size: 1 + - name: AWD1CH + description: analog watchdog 1 monitored channel selection + bit_offset: 26 + bit_size: 5 + - name: JQDIS + description: group injected contexts queue disable + bit_offset: 31 + bit_size: 1 +fieldset/CFGR2: + description: configuration register 2 + fields: + - name: ROVSE + description: oversampler enable on scope group regular + bit_offset: 0 + bit_size: 1 + - name: JOVSE + description: oversampler enable on scope group injected + bit_offset: 1 + bit_size: 1 + - name: OVSS + description: oversampling shift + bit_offset: 5 + bit_size: 4 + - name: TROVS + description: oversampling discontinuous mode (triggered mode) for group regular + bit_offset: 9 + bit_size: 1 + enum: TROVS + - name: ROVSM + description: Regular Oversampling mode + bit_offset: 10 + bit_size: 1 + enum: ROVSM + - name: RSHIFT1 + description: Right-shift data after Offset 1 correction + bit_offset: 11 + bit_size: 1 + - name: RSHIFT2 + description: Right-shift data after Offset 2 correction + bit_offset: 12 + bit_size: 1 + - name: RSHIFT3 + description: Right-shift data after Offset 3 correction + bit_offset: 13 + bit_size: 1 + - name: RSHIFT4 + description: Right-shift data after Offset 4 correction + bit_offset: 14 + bit_size: 1 + - name: OSVR + description: Oversampling ratio + bit_offset: 16 + bit_size: 10 + - name: LSHIFT + description: Left shift factor + bit_offset: 28 + bit_size: 4 +fieldset/CR: + description: control register + fields: + - name: ADEN + description: enable + bit_offset: 0 + bit_size: 1 + enum_write: ADENW + - name: ADDIS + description: disable + bit_offset: 1 + bit_size: 1 + enum_write: ADDISW + - name: ADSTART + description: group regular conversion start + bit_offset: 2 + bit_size: 1 + - name: JADSTART + description: group injected conversion start + bit_offset: 3 + bit_size: 1 + - name: ADSTP + description: group regular conversion stop + bit_offset: 4 + bit_size: 1 + enum: ADSTP + - name: JADSTP + description: group injected conversion stop + bit_offset: 5 + bit_size: 1 + enum: ADSTP + - name: BOOST + description: Boost mode control + bit_offset: 8 + bit_size: 2 + enum: BOOST + - name: ADCALLIN + description: Linearity calibration + bit_offset: 16 + bit_size: 1 + - name: LINCALRDYW1 + description: Linearity calibration ready Word 1 + bit_offset: 22 + bit_size: 1 + - name: LINCALRDYW2 + description: Linearity calibration ready Word 2 + bit_offset: 23 + bit_size: 1 + - name: LINCALRDYW3 + description: Linearity calibration ready Word 3 + bit_offset: 24 + bit_size: 1 + - name: LINCALRDYW4 + description: Linearity calibration ready Word 4 + bit_offset: 25 + bit_size: 1 + - name: LINCALRDYW5 + description: Linearity calibration ready Word 5 + bit_offset: 26 + bit_size: 1 + - name: LINCALRDYW6 + description: Linearity calibration ready Word 6 + bit_offset: 27 + bit_size: 1 + - name: ADVREGEN + description: voltage regulator enable + bit_offset: 28 + bit_size: 1 + - name: DEEPPWD + description: deep power down enable + bit_offset: 29 + bit_size: 1 + - name: ADCALDIF + description: differential mode for calibration + bit_offset: 30 + bit_size: 1 + enum: ADCALDIF + - name: ADCAL + description: calibration + bit_offset: 31 + bit_size: 1 +fieldset/DIFSEL: + description: channel differential or single-ended mode selection register + fields: + - name: DIFSEL + description: channel differential or single-ended mode for channel + bit_offset: 0 + bit_size: 1 + array: + len: 20 + stride: 1 + enum: DIFSEL +fieldset/DR: + description: group regular conversion data register + fields: + - name: RDATA + description: group regular conversion data + bit_offset: 0 + bit_size: 16 +fieldset/HTR1: + description: analog watchdog 2 threshold register + fields: + - name: HTR1 + description: analog watchdog 2 threshold low + bit_offset: 0 + bit_size: 26 +fieldset/HTR2: + description: watchdog higher threshold register 2 + fields: + - name: HTR2 + description: Analog watchdog 2 higher threshold + bit_offset: 0 + bit_size: 26 +fieldset/HTR3: + description: watchdog higher threshold register 3 + fields: + - name: HTR3 + description: Analog watchdog 3 higher threshold + bit_offset: 0 + bit_size: 26 +fieldset/IER: + description: interrupt enable register + fields: + - name: ADRDYIE + description: ready interrupt + bit_offset: 0 + bit_size: 1 + - name: EOSMPIE + description: group regular end of sampling interrupt + bit_offset: 1 + bit_size: 1 + - name: EOCIE + description: group regular end of unitary conversion interrupt + bit_offset: 2 + bit_size: 1 + - name: EOSIE + description: group regular end of sequence conversions interrupt + bit_offset: 3 + bit_size: 1 + - name: OVRIE + description: group regular overrun interrupt + bit_offset: 4 + bit_size: 1 + - name: JEOCIE + description: group injected end of unitary conversion interrupt + bit_offset: 5 + bit_size: 1 + - name: JEOSIE + description: group injected end of sequence conversions interrupt + bit_offset: 6 + bit_size: 1 + - name: AWD1IE + description: analog watchdog 1 interrupt + bit_offset: 7 + bit_size: 1 + - name: AWD2IE + description: analog watchdog 2 interrupt + bit_offset: 8 + bit_size: 1 + - name: AWD3IE + description: analog watchdog 3 interrupt + bit_offset: 9 + bit_size: 1 + - name: JQOVFIE + description: group injected contexts queue overflow interrupt + bit_offset: 10 + bit_size: 1 +fieldset/ISR: + description: interrupt and status register + fields: + - name: ADRDY + description: ready flag + bit_offset: 0 + bit_size: 1 + - name: EOSMP + description: group regular end of sampling flag + bit_offset: 1 + bit_size: 1 + - name: EOC + description: group regular end of unitary conversion flag + bit_offset: 2 + bit_size: 1 + - name: EOS + description: group regular end of sequence conversions flag + bit_offset: 3 + bit_size: 1 + - name: OVR + description: group regular overrun flag + bit_offset: 4 + bit_size: 1 + - name: JEOC + description: group injected end of unitary conversion flag + bit_offset: 5 + bit_size: 1 + - name: JEOS + description: group injected end of sequence conversions flag + bit_offset: 6 + bit_size: 1 + - name: AWD1 + description: analog watchdog 1 flag + bit_offset: 7 + bit_size: 1 + - name: AWD2 + description: analog watchdog 2 flag + bit_offset: 8 + bit_size: 1 + - name: AWD3 + description: analog watchdog 3 flag + bit_offset: 9 + bit_size: 1 + - name: JQOVF + description: group injected contexts queue overflow flag + bit_offset: 10 + bit_size: 1 + - name: LDORDY + description: ADC LDO output voltage ready (not always available) + bit_offset: 12 + bit_size: 1 +fieldset/JDR: + description: group injected sequencer rank 1 register + fields: + - name: JDATA + description: group injected sequencer rank 1 conversion data + bit_offset: 0 + bit_size: 32 +fieldset/JSQR: + description: group injected sequencer register + fields: + - name: JL + description: group injected sequencer scan length + bit_offset: 0 + bit_size: 2 + - name: JEXTSEL + description: group injected external trigger source + bit_offset: 2 + bit_size: 5 + enum: JEXTSEL + - name: JEXTEN + description: group injected external trigger polarity + bit_offset: 7 + bit_size: 2 + enum: JEXTEN + - name: JSQ1 + description: group injected sequencer rank 1-4 + bit_offset: 9 + bit_size: 5 + array: + len: 4 + stride: 6 +fieldset/LTR1: + description: analog watchdog 1 threshold register + fields: + - name: LTR1 + description: analog watchdog 1 threshold low + bit_offset: 0 + bit_size: 26 +fieldset/LTR2: + description: watchdog lower threshold register 2 + fields: + - name: LTR2 + description: Analog watchdog 2 lower threshold + bit_offset: 0 + bit_size: 26 +fieldset/LTR3: + description: watchdog lower threshold register 3 + fields: + - name: LTR3 + description: Analog watchdog 3 lower threshold + bit_offset: 0 + bit_size: 26 +fieldset/OFR: + description: offset number x register + fields: + - name: OFFSET1 + description: offset number x offset level + bit_offset: 0 + bit_size: 26 + - name: OFFSET1_CH + description: offset number x channel selection + bit_offset: 26 + bit_size: 5 + - name: SSATE + description: Signed saturation enable + bit_offset: 31 + bit_size: 1 +fieldset/PCSEL: + description: channel preselection register + fields: + - name: PCSEL + description: "Channel x (VINP[i]) pre selection" + bit_offset: 0 + bit_size: 1 + array: + len: 20 + stride: 1 + enum: PCSEL +fieldset/SMPR: + description: sampling time register n + fields: + - name: SMP + description: channel n * 10 + x sampling time + bit_offset: 0 + bit_size: 3 + array: + len: 10 + stride: 3 + enum: SMP +fieldset/SQR1: + description: group regular sequencer ranks register 1 + fields: + - name: L + description: L3 + bit_offset: 0 + bit_size: 4 + - name: SQ + description: group regular sequencer rank 1-4 + bit_offset: 6 + bit_size: 5 + array: + len: 4 + stride: 6 +fieldset/SQR2: + description: group regular sequencer ranks register 2 + fields: + - name: SQ + description: group regular sequencer rank 5-9 + bit_offset: 0 + bit_size: 5 + array: + len: 5 + stride: 6 +fieldset/SQR3: + description: group regular sequencer ranks register 3 + fields: + - name: SQ + description: group regular sequencer rank 10-14 + bit_offset: 0 + bit_size: 5 + array: + len: 5 + stride: 6 +fieldset/SQR4: + description: group regular sequencer ranks register 4 + fields: + - name: SQ + description: group regular sequencer rank 15-16 + bit_offset: 0 + bit_size: 5 + array: + len: 2 + stride: 6 +enum/ADCALDIF: + bit_size: 1 + variants: + - name: SingleEnded + description: Calibration for single-ended mode + value: 0 + - name: Differential + description: Calibration for differential mode + value: 1 +enum/ADDISW: + bit_size: 1 + variants: + - name: Disable + description: Disable conversion and go to power down mode + value: 0 +enum/ADENW: + bit_size: 1 + variants: + - name: Enable + description: Enable ADC + value: 1 +enum/ADSTP: + bit_size: 1 + variants: + - name: Stop + description: Stop conversion of channel + value: 1 +enum/AWD1SGL: + bit_size: 1 + variants: + - name: All + description: Analog watchdog 1 enabled on all channels + value: 0 + - name: Single + description: Analog watchdog 1 enabled on single channel selected in AWD1CH + value: 1 +enum/BOOST: + bit_size: 2 + variants: + - name: LT6_25 + description: Boost mode used when clock ≤ 6.25 MHz + value: 0 + - name: LT12_5 + description: Boost mode used when 6.25 MHz < clock ≤ 12.5 MHz + value: 1 + - name: LT25 + description: Boost mode used when 12.5 MHz < clock ≤ 25.0 MHz + value: 2 + - name: LT50 + description: Boost mode used when 25.0 MHz < clock ≤ 50.0 MHz + value: 3 +enum/DIFSEL: + bit_size: 1 + variants: + - name: SingleEnded + description: Input channel is configured in single-ended mode + value: 0 + - name: Differential + description: Input channel is configured in differential mode + value: 1 +enum/DMNGT: + bit_size: 2 + variants: + - name: DR + description: Store output data in DR only + value: 0 + - name: DMA_OneShot + description: DMA One Shot Mode selected + value: 1 + - name: DFSDM + description: DFSDM mode selected + value: 2 + - name: DMA_Circular + description: DMA Circular Mode selected + value: 3 +enum/EXTEN: + bit_size: 2 + variants: + - name: Disabled + description: Trigger detection disabled + value: 0 + - name: RisingEdge + description: Trigger detection on the rising edge + value: 1 + - name: FallingEdge + description: Trigger detection on the falling edge + value: 2 + - name: BothEdges + description: Trigger detection on both the rising and falling edges + value: 3 +enum/EXTSEL: + bit_size: 5 + variants: + - name: TIM1_CC1 + description: Timer 1 CC1 event + value: 0 + - name: TIM1_CC2 + description: Timer 1 CC2 event + value: 1 + - name: TIM1_CC3 + description: Timer 1 CC3 event + value: 2 + - name: TIM2_CC2 + description: Timer 2 CC2 event + value: 3 + - name: TIM3_TRGO + description: Timer 3 TRGO event + value: 4 + - name: TIM4_CC4 + description: Timer 4 CC4 event + value: 5 + - name: EXTI11 + description: EXTI line 11 + value: 6 + - name: TIM8_TRGO + description: Timer 8 TRGO event + value: 7 + - name: TIM8_TRGO2 + description: Timer 8 TRGO2 event + value: 8 + - name: TIM1_TRGO + description: Timer 1 TRGO event + value: 9 + - name: TIM1_TRGO2 + description: Timer 1 TRGO2 event + value: 10 + - name: TIM2_TRGO + description: Timer 2 TRGO event + value: 11 + - name: TIM4_TRGO + description: Timer 4 TRGO event + value: 12 + - name: TIM6_TRGO + description: Timer 6 TRGO event + value: 13 + - name: TIM15_TRGO + description: Timer 15 TRGO event + value: 14 + - name: TIM3_CC4 + description: Timer 3 CC4 event + value: 15 + - name: HRTIM1_ADCTRG1 + description: HRTIM1_ADCTRG1 event + value: 16 + - name: HRTIM1_ADCTRG3 + description: HRTIM1_ADCTRG3 event + value: 17 + - name: LPTIM1_OUT + description: LPTIM1_OUT event + value: 18 + - name: LPTIM2_OUT + description: LPTIM2_OUT event + value: 19 + - name: LPTIM3_OUT + description: LPTIM3_OUT event + value: 20 +enum/JEXTEN: + bit_size: 2 + variants: + - name: Disabled + description: Trigger detection disabled + value: 0 + - name: RisingEdge + description: Trigger detection on the rising edge + value: 1 + - name: FallingEdge + description: Trigger detection on the falling edge + value: 2 + - name: BothEdges + description: Trigger detection on both the rising and falling edges + value: 3 +enum/JEXTSEL: + bit_size: 5 + variants: + - name: TIM1_TRGO + description: Timer 1 TRGO event + value: 0 + - name: TIM1_CC4 + description: Timer 1 CC4 event + value: 1 + - name: TIM2_TRGO + description: Timer 2 TRGO event + value: 2 + - name: TIM2_CC1 + description: Timer 2 CC1 event + value: 3 + - name: TIM3_CC4 + description: Timer 3 CC4 event + value: 4 + - name: TIM4_TRGO + description: Timer 4 TRGO event + value: 5 + - name: EXTI15 + description: EXTI line 15 + value: 6 + - name: TIM8_CC4 + description: Timer 8 CC4 event + value: 7 + - name: TIM1_TRGO2 + description: Timer 1 TRGO2 event + value: 8 + - name: TIM8_TRGO + description: Timer 8 TRGO event + value: 9 + - name: TIM8_TRGO2 + description: Timer 8 TRGO2 event + value: 10 + - name: TIM3_CC3 + description: Timer 3 CC3 event + value: 11 + - name: TIM3_TRGO + description: Timer 3 TRGO event + value: 12 + - name: TIM3_CC1 + description: Timer 3 CC1 event + value: 13 + - name: TIM6_TRGO + description: Timer 6 TRGO event + value: 14 + - name: TIM15_TRGO + description: Timer 15 TRGO event + value: 15 + - name: HRTIM1_ADCTRG2 + description: HRTIM1_ADCTRG2 event + value: 16 + - name: HRTIM1_ADCTRG4 + description: HRTIM1_ADCTRG4 event + value: 17 + - name: LPTIM1_OUT + description: LPTIM1_OUT event + value: 18 + - name: LPTIM2_OUT + description: LPTIM2_OUT event + value: 19 + - name: LPTIM3_OUT + description: LPTIM3_OUT event + value: 20 +enum/JQM: + bit_size: 1 + variants: + - name: Mode0 + description: "JSQR Mode 0: Queue maintains the last written configuration into JSQR" + value: 0 + - name: Mode1 + description: "JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence" + value: 1 +enum/OVRMOD: + bit_size: 1 + variants: + - name: Preserve + description: Preserve DR register when an overrun is detected + value: 0 + - name: Overwrite + description: Overwrite DR register when an overrun is detected + value: 1 +enum/PCSEL: + bit_size: 20 + variants: + - name: NotPreselected + description: Input channel x is not pre-selected + value: 0 + - name: Preselected + description: Pre-select input channel x + value: 1 +enum/RES: + bit_size: 3 + variants: + - name: SixteenBit + description: 16-bit resolution + value: 0 + - name: FourteenBit + description: 14-bit resolution in legacy mode (not optimized power consumption) + value: 1 + - name: TwelveBit + description: 12-bit resolution in legacy mode (not optimized power consumption) + value: 2 + - name: TenBit + description: 10-bit resolution + value: 3 + - name: FourteenBitV + description: 14-bit resolution + value: 5 + - name: TwelveBitV + description: 12-bit resolution + value: 6 + - name: EightBit + description: 8-bit resolution + value: 7 +enum/ROVSM: + bit_size: 1 + variants: + - name: Continued + description: Oversampling is temporary stopped and continued after injection sequence + value: 0 + - name: Resumed + description: Oversampling is aborted and resumed from start after injection sequence + value: 1 +enum/SMP: + bit_size: 3 + variants: + - name: Cycles1_5 + description: 1.5 clock cycles + value: 0 + - name: Cycles2_5 + description: 2.5 clock cycles + value: 1 + - name: Cycles8_5 + description: 8.5 clock cycles + value: 2 + - name: Cycles16_5 + description: 16.5 clock cycles + value: 3 + - name: Cycles32_5 + description: 32.5 clock cycles + value: 4 + - name: Cycles64_5 + description: 64.5 clock cycles + value: 5 + - name: Cycles387_5 + description: 387.5 clock cycles + value: 6 + - name: Cycles810_5 + description: 810.5 clock cycles + value: 7 +enum/TROVS: + bit_size: 1 + variants: + - name: Automatic + description: All oversampled conversions for a channel are run following a trigger + value: 0 + - name: Triggered + description: Each oversampled conversion for a channel needs a new trigger + value: 1 diff --git a/data/registers/adccommon_v4.yaml b/data/registers/adccommon_v4.yaml new file mode 100644 index 0000000..1c50f5f --- /dev/null +++ b/data/registers/adccommon_v4.yaml @@ -0,0 +1,367 @@ +--- +block/ADC_COMMON: + description: Analog-to-Digital Converter + items: + - name: CSR + description: ADC Common status register + byte_offset: 0 + access: Read + fieldset: CSR + - name: CCR + description: ADC common control register + byte_offset: 8 + fieldset: CCR + - name: CDR + description: ADC common regular data register for dual and triple modes + byte_offset: 12 + access: Read + fieldset: CDR + - name: CDR2 + description: ADC x common regular data register for 32-bit dual mode + byte_offset: 16 + access: Read + fieldset: CDR2 +fieldset/CCR: + description: ADC common control register + fields: + - name: DUAL + description: Dual ADC mode selection + bit_offset: 0 + bit_size: 5 + enum: DUAL + - name: DELAY + description: Delay between 2 sampling phases + bit_offset: 8 + bit_size: 4 + - name: DAMDF + description: Dual ADC Mode Data Format + bit_offset: 14 + bit_size: 2 + enum: DAMDF + - name: CKMODE + description: ADC clock mode + bit_offset: 16 + bit_size: 2 + enum: CKMODE + - name: PRESC + description: ADC prescaler + bit_offset: 18 + bit_size: 4 + enum: PRESC + - name: VREFEN + description: VREFINT enable + bit_offset: 22 + bit_size: 1 + - name: VSENSEEN + description: Temperature sensor enable + bit_offset: 23 + bit_size: 1 + - name: VBATEN + description: VBAT enable + bit_offset: 24 + bit_size: 1 +fieldset/CDR: + description: ADC common regular data register for dual and triple modes + fields: + - name: RDATA_MST + description: Regular data of the master ADC + bit_offset: 0 + bit_size: 16 + - name: RDATA_SLV + description: Regular data of the slave ADC + bit_offset: 16 + bit_size: 16 +fieldset/CDR2: + description: ADC x common regular data register for 32-bit dual mode + fields: + - name: RDATA_ALT + description: Regular data of the master/slave alternated ADCs + bit_offset: 0 + bit_size: 32 +fieldset/CSR: + description: ADC Common status register + fields: + - name: ADRDY_MST + description: Master ADC ready + bit_offset: 0 + bit_size: 1 + enum: ADRDY_MST + - name: EOSMP_MST + description: End of Sampling phase flag of the master ADC + bit_offset: 1 + bit_size: 1 + enum: EOSMP_MST + - name: EOC_MST + description: End of regular conversion of the master ADC + bit_offset: 2 + bit_size: 1 + enum: EOC_MST + - name: EOS_MST + description: End of regular sequence flag of the master ADC + bit_offset: 3 + bit_size: 1 + enum: EOS_MST + - name: OVR_MST + description: Overrun flag of the master ADC + bit_offset: 4 + bit_size: 1 + enum: OVR_MST + - name: JEOC_MST + description: End of injected conversion flag of the master ADC + bit_offset: 5 + bit_size: 1 + enum: JEOC_MST + - name: JEOS_MST + description: End of injected sequence flag of the master ADC + bit_offset: 6 + bit_size: 1 + enum: JEOS_MST + - name: AWD1_MST + description: Analog watchdog 1 flag of the master ADC + bit_offset: 7 + bit_size: 1 + enum: AWD1_MST + - name: AWD2_MST + description: Analog watchdog 2 flag of the master ADC + bit_offset: 8 + bit_size: 1 + enum: AWD1_MST + - name: AWD3_MST + description: Analog watchdog 3 flag of the master ADC + bit_offset: 9 + bit_size: 1 + enum: AWD1_MST + - name: JQOVF_MST + description: Injected Context Queue Overflow flag of the master ADC + bit_offset: 10 + bit_size: 1 + enum: JQOVF_MST + - name: ADRDY_SLV + description: Slave ADC ready + bit_offset: 16 + bit_size: 1 + enum: ADRDY_MST + - name: EOSMP_SLV + description: End of Sampling phase flag of the slave ADC + bit_offset: 17 + bit_size: 1 + enum: EOSMP_MST + - name: EOC_SLV + description: End of regular conversion of the slave ADC + bit_offset: 18 + bit_size: 1 + enum: EOC_MST + - name: EOS_SLV + description: End of regular sequence flag of the slave ADC + bit_offset: 19 + bit_size: 1 + enum: EOS_MST + - name: OVR_SLV + description: Overrun flag of the slave ADC + bit_offset: 20 + bit_size: 1 + enum: OVR_MST + - name: JEOC_SLV + description: End of injected conversion flag of the slave ADC + bit_offset: 21 + bit_size: 1 + enum: JEOC_MST + - name: JEOS_SLV + description: End of injected sequence flag of the slave ADC + bit_offset: 22 + bit_size: 1 + enum: JEOS_MST + - name: AWD1_SLV + description: Analog watchdog 1 flag of the slave ADC + bit_offset: 23 + bit_size: 1 + enum: AWD1_MST + - name: AWD2_SLV + description: Analog watchdog 2 flag of the slave ADC + bit_offset: 24 + bit_size: 1 + enum: AWD1_MST + - name: AWD3_SLV + description: Analog watchdog 3 flag of the slave ADC + bit_offset: 25 + bit_size: 1 + enum: AWD1_MST + - name: JQOVF_SLV + description: Injected Context Queue Overflow flag of the slave ADC + bit_offset: 26 + bit_size: 1 + enum: JQOVF_MST +enum/ADRDY_MST: + bit_size: 1 + variants: + - name: NotReady + description: ADC is not ready to start conversion + value: 0 + - name: Ready + description: ADC is ready to start conversion + value: 1 +enum/AWD1_MST: + bit_size: 1 + variants: + - name: NoEvent + description: No analog watchdog event occurred + value: 0 + - name: Event + description: Analog watchdog event occurred + value: 1 +enum/CKMODE: + bit_size: 2 + variants: + - name: Asynchronous + description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock + value: 0 + - name: SyncDiv1 + description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck + value: 1 + - name: SyncDiv2 + description: Use AHB clock rcc_hclk3 divided by 2 + value: 2 + - name: SyncDiv4 + description: Use AHB clock rcc_hclk3 divided by 4 + value: 3 +enum/DAMDF: + bit_size: 2 + variants: + - name: NoPack + description: "Without data packing, CDR/CDR2 not used" + value: 0 + - name: Format32to10 + description: CDR formatted for 32-bit down to 10-bit resolution + value: 2 + - name: Format8 + description: CDR formatted for 8-bit resolution + value: 3 +enum/DUAL: + bit_size: 5 + variants: + - name: Independent + description: Independent mode + value: 0 + - name: DualRJ + description: "Dual, combined regular simultaneous + injected simultaneous mode" + value: 1 + - name: DualRA + description: "Dual, combined regular simultaneous + alternate trigger mode" + value: 2 + - name: DualIJ + description: "Dual, combined interleaved mode + injected simultaneous mode" + value: 3 + - name: DualJ + description: "Dual, injected simultaneous mode only" + value: 5 + - name: DualR + description: "Dual, regular simultaneous mode only" + value: 6 + - name: DualI + description: "Dual, interleaved mode only" + value: 7 + - name: DualA + description: "Dual, alternate trigger mode only" + value: 9 +enum/EOC_MST: + bit_size: 1 + variants: + - name: NotComplete + description: Regular conversion is not complete + value: 0 + - name: Complete + description: Regular conversion complete + value: 1 +enum/EOSMP_MST: + bit_size: 1 + variants: + - name: NotEnded + description: End of sampling phase no yet reached + value: 0 + - name: Ended + description: End of sampling phase reached + value: 1 +enum/EOS_MST: + bit_size: 1 + variants: + - name: NotComplete + description: Regular sequence is not complete + value: 0 + - name: Complete + description: Regular sequence complete + value: 1 +enum/JEOC_MST: + bit_size: 1 + variants: + - name: NotComplete + description: Injected conversion is not complete + value: 0 + - name: Complete + description: Injected conversion complete + value: 1 +enum/JEOS_MST: + bit_size: 1 + variants: + - name: NotComplete + description: Injected sequence is not complete + value: 0 + - name: Complete + description: Injected sequence complete + value: 1 +enum/JQOVF_MST: + bit_size: 1 + variants: + - name: NoOverflow + description: No injected context queue overflow has occurred + value: 0 + - name: Overflow + description: Injected context queue overflow has occurred + value: 1 +enum/OVR_MST: + bit_size: 1 + variants: + - name: NoOverrun + description: No overrun occurred + value: 0 + - name: Overrun + description: Overrun occurred + value: 1 +enum/PRESC: + bit_size: 4 + variants: + - name: Div1 + description: adc_ker_ck_input not divided + value: 0 + - name: Div2 + description: adc_ker_ck_input divided by 2 + value: 1 + - name: Div4 + description: adc_ker_ck_input divided by 4 + value: 2 + - name: Div6 + description: adc_ker_ck_input divided by 6 + value: 3 + - name: Div8 + description: adc_ker_ck_input divided by 8 + value: 4 + - name: Div10 + description: adc_ker_ck_input divided by 10 + value: 5 + - name: Div12 + description: adc_ker_ck_input divided by 12 + value: 6 + - name: Div16 + description: adc_ker_ck_input divided by 16 + value: 7 + - name: Div32 + description: adc_ker_ck_input divided by 32 + value: 8 + - name: Div64 + description: adc_ker_ck_input divided by 64 + value: 9 + - name: Div128 + description: adc_ker_ck_input divided by 128 + value: 10 + - name: Div256 + description: adc_ker_ck_input divided by 256 + value: 11 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 57d19eb..972052b 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -119,17 +119,23 @@ perimap = [ ('.*:I2C:i2c2_v1_1', ('i2c', 'v2', 'I2C')), ('.*:I2C:i2c2_v1_1F7', ('i2c', 'v2', 'I2C')), ('.*:I2C:i2c2_v1_1U5', ('i2c', 'v2', 'I2C')), + ('.*:DAC:dacif_v1_1', ('dac', 'v1', 'DAC')), ('.*:DAC:dacif_v2_0', ('dac', 'v2', 'DAC')), ('.*:DAC:dacif_v3_0', ('dac', 'v2', 'DAC')), + ('.*:ADC:aditf_v2_5F1', ('adc', 'f1', 'ADC')), + ('.*:ADC:aditf4_v1_1', ('adc', 'v1', 'ADC')), ('.*:ADC:aditf2_v1_1', ('adc', 'v2', 'ADC')), ('.*:ADC:aditf5_v2_0', ('adc', 'v3', 'ADC')), + ('.*:ADC:aditf5_v3_0', ('adc', 'v4', 'ADC')), ('STM32G0.*:ADC:.*', ('adc', 'g0', 'ADC')), ('STM32G0.*:ADC_COMMON:.*', ('adccommon', 'v3', 'ADC_COMMON')), ('.*:ADC_COMMON:aditf2_v1_1', ('adccommon', 'v2', 'ADC_COMMON')), ('.*:ADC_COMMON:aditf5_v2_0', ('adccommon', 'v3', 'ADC_COMMON')), ('.*:ADC_COMMON:aditf4_v3_0_WL', ('adccommon', 'v3', 'ADC_COMMON')), + ('STM32H7.*:ADC_COMMON:.*', ('adccommon', 'v4', 'ADC_COMMON')), + ('.*:DCMI:.*', ('dcmi', 'v1', 'DCMI')), ('STM32F0.*:SYSCFG:.*', ('syscfg', 'f0', 'SYSCFG')), ('STM32F2.*:SYSCFG:.*', ('syscfg', 'f2', 'SYSCFG')), From 0c9329fe944738bd71dad9187e8b914a62f389d7 Mon Sep 17 00:00:00 2001 From: Matous Hybl Date: Tue, 12 Apr 2022 16:02:18 +0200 Subject: [PATCH 24/35] Add ADC3 common for H7s --- stm32data/__main__.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 972052b..d883047 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -135,6 +135,7 @@ perimap = [ ('.*:ADC_COMMON:aditf5_v2_0', ('adccommon', 'v3', 'ADC_COMMON')), ('.*:ADC_COMMON:aditf4_v3_0_WL', ('adccommon', 'v3', 'ADC_COMMON')), ('STM32H7.*:ADC_COMMON:.*', ('adccommon', 'v4', 'ADC_COMMON')), + ('STM32H7.*:ADC3_COMMON:.*', ('adccommon', 'v4', 'ADC_COMMON')), ('.*:DCMI:.*', ('dcmi', 'v1', 'DCMI')), ('STM32F0.*:SYSCFG:.*', ('syscfg', 'f0', 'SYSCFG')), @@ -692,6 +693,9 @@ def parse_chips(): if pname.startswith('ADC'): if not 'ADC_COMMON' in peri_kinds: peri_kinds['ADC_COMMON'] = 'ADC_COMMON:' + removesuffix(ip['@Version'], '_Cube') + if pname.startswith('ADC3'): + if chip_name.startswith("STM32H7") and not 'ADC_COMMON3' in peri_kinds: + peri_kinds['ADC3_COMMON'] = 'ADC3_COMMON:' + removesuffix(ip['@Version'], '_Cube') peri_kinds[pname] = pkind From bd97be07b316ec7bbe48ea61d56b3192ed0c2318 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Wed, 27 Apr 2022 11:58:52 +0200 Subject: [PATCH 25/35] Generate more flash settings --- stm32data/__main__.py | 1 + stm32data/memory.py | 32 +++++++++++++++++++++++++++++++- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/stm32data/__main__.py b/stm32data/__main__.py index d883047..76f8fa9 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -853,6 +853,7 @@ def parse_chips(): 'kind': 'flash', 'address': h['defines']['all'][each + '_BASE'], 'size': size, + 'settings': memory.determine_flash_settings(chip_name), }) found = set() diff --git a/stm32data/memory.py b/stm32data/memory.py index 7815abe..3a14ad8 100644 --- a/stm32data/memory.py +++ b/stm32data/memory.py @@ -45,13 +45,16 @@ memories = [] def parse(): for f in sorted(glob('sources/cubeprogdb/db/*.xml')): - #print("parsing ", f); + # print("parsing ", f); device = xmltodict.parse(open(f, 'rb'))['Root']['Device'] device_id = device['DeviceID'] name = device['Name'] names = split_names(name) flash_size = None flash_addr = None + write_size = None + erase_size = None + erase_value = None ram_size = None ram_addr = None @@ -69,6 +72,18 @@ def parse(): configs = [configs] flash_addr = int(configs[0]['Parameters']['@address'], 16) flash_size = int(configs[0]['Parameters']['@size'], 16) + erase_value = int(peripheral['ErasedValue'], 16) + write_size = int(configs[0]['Allignement'], 16) + bank = configs[0]['Bank'] + if type(bank) != list: + bank = [bank] + field = bank[0]['Field'] + if type(field) != list: + field = [field] + # print("Field", field) + p = field[0]['Parameters'] + print("pwrams", str(p)) + erase_size = int(p['@size'], 16) #print( f'flash {addr} {size}') chunk = { @@ -86,6 +101,9 @@ def parse(): chunk['flash'] = { 'address': flash_addr, 'bytes': flash_size, + 'erase_value': erase_value, + 'write_size': write_size, + 'erase_size': erase_size, } memories.append(chunk) @@ -108,6 +126,18 @@ def determine_flash_size(chip_name): return None +def determine_flash_settings(chip_name): + for each in memories: + for name in each['names']: + if is_chip_name_match(name, chip_name): + return { + 'erase_size': each['flash']['erase_size'], + 'write_size': each['flash']['write_size'], + 'erase_value': each['flash']['erase_value'], + } + + return None + def determine_device_id(chip_name): for each in memories: From 4535a98b19ee9ef14a4643ba0d3118a39c11e647 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Wed, 27 Apr 2022 14:20:29 +0200 Subject: [PATCH 26/35] Use the largest sector size --- stm32data/memory.py | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/stm32data/memory.py b/stm32data/memory.py index 3a14ad8..4ef8cf3 100644 --- a/stm32data/memory.py +++ b/stm32data/memory.py @@ -77,14 +77,15 @@ def parse(): bank = configs[0]['Bank'] if type(bank) != list: bank = [bank] - field = bank[0]['Field'] - if type(field) != list: - field = [field] - # print("Field", field) - p = field[0]['Parameters'] - print("pwrams", str(p)) - erase_size = int(p['@size'], 16) - #print( f'flash {addr} {size}') + fields = bank[0]['Field'] + if type(fields) != list: + fields = [fields] + + erase_size = int(fields[0]['Parameters']['@size'], 16) + for field in fields: + # print("Field", field) + erase_size = max(erase_size, int(field['Parameters']['@size'], 16)) + #print( f'flash {addr} {size}') chunk = { 'device-id': int(device_id, 16), From c36a510e472eaaa48bd25c309c911d36da11a141 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Thu, 28 Apr 2022 01:54:55 +0200 Subject: [PATCH 27/35] unify ETH vs ETHMAC in RCC regs. --- data/registers/rcc_f1.yaml | 8 ++++---- data/registers/rcc_f1cl.yaml | 8 ++++---- data/registers/rcc_f2.yaml | 18 +++++++++--------- data/registers/rcc_f4.yaml | 18 +++++++++--------- 4 files changed, 26 insertions(+), 26 deletions(-) diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml index 4244347..3b7a5d2 100644 --- a/data/registers/rcc_f1.yaml +++ b/data/registers/rcc_f1.yaml @@ -85,15 +85,15 @@ fieldset/AHBENR: description: USB OTG FS clock enable bit_offset: 12 bit_size: 1 - - name: ETHMACEN + - name: ETHEN description: Ethernet MAC clock enable bit_offset: 14 bit_size: 1 - - name: ETHMACTXEN + - name: ETHTXEN description: Ethernet MAC TX clock enable bit_offset: 15 bit_size: 1 - - name: ETHMACRXEN + - name: ETHRXEN description: Ethernet MAC RX clock enable bit_offset: 16 bit_size: 1 @@ -104,7 +104,7 @@ fieldset/AHBRSTR: description: USB OTG FS reset bit_offset: 12 bit_size: 1 - - name: ETHMACRST + - name: ETHRST description: Ethernet MAC reset bit_offset: 14 bit_size: 1 diff --git a/data/registers/rcc_f1cl.yaml b/data/registers/rcc_f1cl.yaml index dbb7dfa..ff4bbf3 100644 --- a/data/registers/rcc_f1cl.yaml +++ b/data/registers/rcc_f1cl.yaml @@ -85,15 +85,15 @@ fieldset/AHBENR: description: USB OTG FS clock enable bit_offset: 12 bit_size: 1 - - name: ETHMACEN + - name: ETHEN description: Ethernet MAC clock enable bit_offset: 14 bit_size: 1 - - name: ETHMACTXEN + - name: ETHTXEN description: Ethernet MAC TX clock enable bit_offset: 15 bit_size: 1 - - name: ETHMACRXEN + - name: ETHRXEN description: Ethernet MAC RX clock enable bit_offset: 16 bit_size: 1 @@ -104,7 +104,7 @@ fieldset/AHBRSTR: description: USB OTG FS reset bit_offset: 12 bit_size: 1 - - name: ETHMACRST + - name: ETHRST description: Ethernet MAC reset bit_offset: 14 bit_size: 1 diff --git a/data/registers/rcc_f2.yaml b/data/registers/rcc_f2.yaml index 63e9555..7517af8 100644 --- a/data/registers/rcc_f2.yaml +++ b/data/registers/rcc_f2.yaml @@ -149,19 +149,19 @@ fieldset/AHB1ENR: description: DMA2 clock enable bit_offset: 22 bit_size: 1 - - name: ETHMACEN + - name: ETHEN description: Ethernet MAC clock enable bit_offset: 25 bit_size: 1 - - name: ETHMACTXEN + - name: ETHTXEN description: Ethernet Transmission clock enable bit_offset: 26 bit_size: 1 - - name: ETHMACRXEN + - name: ETHRXEN description: Ethernet Reception clock enable bit_offset: 27 bit_size: 1 - - name: ETHMACPTPEN + - name: ETHPTPEN description: Ethernet PTP clock enable bit_offset: 28 bit_size: 1 @@ -240,19 +240,19 @@ fieldset/AHB1LPENR: description: DMA2 clock enable during Sleep mode bit_offset: 22 bit_size: 1 - - name: ETHMACLPEN + - name: ETHLPEN description: Ethernet MAC clock enable during Sleep mode bit_offset: 25 bit_size: 1 - - name: ETHMACTXLPEN + - name: ETHTXLPEN description: Ethernet transmission clock enable during Sleep mode bit_offset: 26 bit_size: 1 - - name: ETHMACRXLPEN + - name: ETHRXLPEN description: Ethernet reception clock enable during Sleep mode bit_offset: 27 bit_size: 1 - - name: ETHMACPTPLPEN + - name: ETHPTPLPEN description: Ethernet PTP clock enable during Sleep mode bit_offset: 28 bit_size: 1 @@ -315,7 +315,7 @@ fieldset/AHB1RSTR: description: DMA2 reset bit_offset: 22 bit_size: 1 - - name: ETHMACRST + - name: ETHRST description: Ethernet MAC reset bit_offset: 25 bit_size: 1 diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index 08512a0..5004958 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -181,19 +181,19 @@ fieldset/AHB1ENR: description: DMA2D clock enable bit_offset: 23 bit_size: 1 - - name: ETHMACEN + - name: ETHEN description: Ethernet MAC clock enable bit_offset: 25 bit_size: 1 - - name: ETHMACTXEN + - name: ETHTXEN description: Ethernet Transmission clock enable bit_offset: 26 bit_size: 1 - - name: ETHMACRXEN + - name: ETHRXEN description: Ethernet Reception clock enable bit_offset: 27 bit_size: 1 - - name: ETHMACPTPEN + - name: ETHPTPEN description: Ethernet PTP clock enable bit_offset: 28 bit_size: 1 @@ -288,19 +288,19 @@ fieldset/AHB1LPENR: description: DMA2D clock enable during Sleep mode bit_offset: 23 bit_size: 1 - - name: ETHMACLPEN + - name: ETHLPEN description: Ethernet MAC clock enable during Sleep mode bit_offset: 25 bit_size: 1 - - name: ETHMACTXLPEN + - name: ETHTXLPEN description: Ethernet transmission clock enable during Sleep mode bit_offset: 26 bit_size: 1 - - name: ETHMACRXLPEN + - name: ETHRXLPEN description: Ethernet reception clock enable during Sleep mode bit_offset: 27 bit_size: 1 - - name: ETHMACPTPLPEN + - name: ETHPTPLPEN description: Ethernet PTP clock enable during Sleep mode bit_offset: 28 bit_size: 1 @@ -379,7 +379,7 @@ fieldset/AHB1RSTR: description: DMA2D reset bit_offset: 23 bit_size: 1 - - name: ETHMACRST + - name: ETHRST description: Ethernet MAC reset bit_offset: 25 bit_size: 1 From 9ea9bd52157d55efc9ecbfb35c4172b4c3300d08 Mon Sep 17 00:00:00 2001 From: Grant Miller Date: Tue, 26 Apr 2022 21:39:16 -0500 Subject: [PATCH 28/35] Prevent crash if `xENR` exists but `xRSTR` doesn't --- stm32data/__main__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 76f8fa9..9cd4d81 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -1268,7 +1268,7 @@ def parse_rcc_regs(): 'field': field['name'], } } - if rstr := y[key.replace('ENR', 'RSTR')]: + if rstr := y.get(key.replace('ENR', 'RSTR')): if field := next(filter(lambda f: f['name'] == f'{peri}RST', rstr['fields']), None): res['reset'] = { 'register': reg.replace('ENR', 'RSTR'), From d7674ab524587ee7632aa4e86e7c0046bb2a5dca Mon Sep 17 00:00:00 2001 From: Grant Miller Date: Sun, 1 May 2022 13:38:41 -0500 Subject: [PATCH 29/35] Create rcc_f100.yaml --- data/registers/rcc_f100.yaml | 865 +++++++++++++++++++++++++++++++++++ stm32data/__main__.py | 3 +- 2 files changed, 867 insertions(+), 1 deletion(-) create mode 100644 data/registers/rcc_f100.yaml diff --git a/data/registers/rcc_f100.yaml b/data/registers/rcc_f100.yaml new file mode 100644 index 0000000..aaf80b7 --- /dev/null +++ b/data/registers/rcc_f100.yaml @@ -0,0 +1,865 @@ +--- +block/RCC: + description: Reset and clock control + items: + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: CFGR + description: Clock configuration register (RCC_CFGR) + byte_offset: 4 + fieldset: CFGR + - name: CIR + description: Clock interrupt register (RCC_CIR) + byte_offset: 8 + fieldset: CIR + - name: APB2RSTR + description: APB2 peripheral reset register (RCC_APB2RSTR) + byte_offset: 12 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register (RCC_APB1RSTR) + byte_offset: 16 + fieldset: APB1RSTR + - name: AHBENR + description: AHB Peripheral Clock enable register (RCC_AHBENR) + byte_offset: 20 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register (RCC_APB2ENR) + byte_offset: 24 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register (RCC_APB1ENR) + byte_offset: 28 + fieldset: APB1ENR + - name: BDCR + description: Backup domain control register (RCC_BDCR) + byte_offset: 32 + fieldset: BDCR + - name: CSR + description: Control/status register (RCC_CSR) + byte_offset: 36 + fieldset: CSR + - name: CFGR2 + description: Clock configuration register 2 + byte_offset: 44 + fieldset: CFGR2 +fieldset/AHBENR: + description: AHB Peripheral Clock enable register (RCC_AHBENR) + fields: + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: SRAMEN + description: SRAM interface clock enable + bit_offset: 2 + bit_size: 1 + - name: FLASHEN + description: FLASH clock enable + bit_offset: 4 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 6 + bit_size: 1 + - name: FSMCEN + description: FSMC clock enable + bit_offset: 8 + bit_size: 1 +fieldset/APB1ENR: + description: APB1 peripheral clock enable register (RCC_APB1ENR) + fields: + - name: TIM2EN + description: Timer 2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: Timer 4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: Timer 5 clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: Timer 7 clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: Timer 12 clock enable + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: Timer 13 clock enable + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: Timer 14 clock enable + bit_offset: 8 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI 2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI 3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART 3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART 4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART 5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C 2 clock enable + bit_offset: 22 + bit_size: 1 + - name: BKPEN + description: Backup interface clock enable + bit_offset: 27 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: CECEN + description: CEC clock enable + bit_offset: 30 + bit_size: 1 +fieldset/APB1RSTR: + description: APB1 peripheral reset register (RCC_APB1RSTR) + fields: + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: Timer 4 reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: Timer 5 reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: Timer 6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: Timer 7 reset + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: Timer 12 reset + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: Timer 13 reset + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: Timer 14 reset + bit_offset: 8 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART 3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: USART 4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: USART 5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: BKPRST + description: Backup interface reset + bit_offset: 27 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 + - name: CECRST + description: CEC reset + bit_offset: 30 + bit_size: 1 +fieldset/APB2ENR: + description: APB2 peripheral clock enable register (RCC_APB2ENR) + fields: + - name: AFIOEN + description: Alternate function I/O clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOAEN + description: I/O port A clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIOBEN + description: I/O port B clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOCEN + description: I/O port C clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIODEN + description: I/O port D clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOEEN + description: I/O port E clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOFEN + description: I/O port F clock enable + bit_offset: 7 + bit_size: 1 + - name: GPIOGEN + description: I/O port G clock enable + bit_offset: 8 + bit_size: 1 + - name: ADC1EN + description: ADC 1 interface clock enable + bit_offset: 9 + bit_size: 1 + - name: TIM1EN + description: TIM1 Timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM15EN + description: TIM15 Timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 Timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 Timer clock enable + bit_offset: 18 + bit_size: 1 +fieldset/APB2RSTR: + description: APB2 peripheral reset register (RCC_APB2RSTR) + fields: + - name: AFIORST + description: Alternate function I/O reset + bit_offset: 0 + bit_size: 1 + - name: GPIOARST + description: IO port A reset + bit_offset: 2 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 3 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 4 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 5 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 6 + bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 7 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 8 + bit_size: 1 + - name: ADC1RST + description: ADC 1 interface reset + bit_offset: 9 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 +fieldset/BDCR: + description: Backup domain control register (RCC_BDCR) + fields: + - name: LSEON + description: External Low Speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External Low Speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: External Low Speed oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 +fieldset/CFGR: + description: Clock configuration register (RCC_CFGR) + fields: + - name: SW + description: System clock Switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System Clock Switch Status + bit_offset: 2 + bit_size: 2 + enum_read: SWSR + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE1 + - name: PPRE2 + description: APB High speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE1 + - name: ADCPRE + description: ADC prescaler + bit_offset: 14 + bit_size: 2 + enum: ADCPRE + - name: PLLSRC + description: PLL entry clock source + bit_offset: 16 + bit_size: 1 + enum: PLLSRC + - name: PLLXTPRE + description: HSE divider for PLL entry + bit_offset: 17 + bit_size: 1 + enum: PLLXTPRE + - name: PLLMUL + description: PLL Multiplication Factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: MCO + description: Microcontroller clock output + bit_offset: 24 + bit_size: 3 + enum: MCO +fieldset/CFGR2: + description: Clock configuration register 2 + fields: + - name: PREDIV1 + description: PREDIV1 division factor + bit_offset: 0 + bit_size: 4 + enum: PREDIV1 +fieldset/CIR: + description: Clock interrupt register (RCC_CIR) + fields: + - name: LSIRDYF + description: LSI Ready Interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE Ready Interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI Ready Interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE Ready Interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: PLL Ready Interrupt flag + bit_offset: 4 + bit_size: 1 + - name: CSSF + description: Clock Security System Interrupt flag + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI Ready Interrupt Enable + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE Ready Interrupt Enable + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI Ready Interrupt Enable + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE Ready Interrupt Enable + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: PLL Ready Interrupt Enable + bit_offset: 12 + bit_size: 1 + - name: LSIRDYC + description: LSI Ready Interrupt Clear + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE Ready Interrupt Clear + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI Ready Interrupt Clear + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE Ready Interrupt Clear + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: PLL Ready Interrupt Clear + bit_offset: 20 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 +fieldset/CR: + description: Clock control register + fields: + - name: HSION + description: Internal High Speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal High Speed clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSITRIM + description: Internal High Speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal High Speed clock Calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: External High Speed clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: External High Speed clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: External High Speed clock Bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 +fieldset/CSR: + description: Control/status register (RCC_CSR) + fields: + - name: LSION + description: Internal low speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 +enum/ADCPRE: + bit_size: 2 + variants: + - name: Div2 + description: PCLK2 divided by 2 + value: 0 + - name: Div4 + description: PCLK2 divided by 4 + value: 1 + - name: Div6 + description: PCLK2 divided by 8 + value: 2 + - name: Div8 + description: PCLK2 divided by 16 + value: 3 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 +enum/MCO: + bit_size: 3 + variants: + - name: NoMCO + description: "MCO output disabled, no clock on MCO" + value: 0 + - name: SYSCLK + description: System clock selected + value: 4 + - name: HSI + description: HSI oscillator clock selected + value: 5 + - name: HSE + description: HSE oscillator clock selected + value: 6 + - name: PLL + description: PLL clock divided by 2 selected + value: 7 +enum/PLLMUL: + bit_size: 4 + variants: + - name: Mul2 + description: PLL input clock x2 + value: 0 + - name: Mul3 + description: PLL input clock x3 + value: 1 + - name: Mul4 + description: PLL input clock x4 + value: 2 + - name: Mul5 + description: PLL input clock x5 + value: 3 + - name: Mul6 + description: PLL input clock x6 + value: 4 + - name: Mul7 + description: PLL input clock x7 + value: 5 + - name: Mul8 + description: PLL input clock x8 + value: 6 + - name: Mul9 + description: PLL input clock x9 + value: 7 + - name: Mul10 + description: PLL input clock x10 + value: 8 + - name: Mul11 + description: PLL input clock x11 + value: 9 + - name: Mul12 + description: PLL input clock x12 + value: 10 + - name: Mul13 + description: PLL input clock x13 + value: 11 + - name: Mul14 + description: PLL input clock x14 + value: 12 + - name: Mul15 + description: PLL input clock x15 + value: 13 + - name: Mul16 + description: PLL input clock x16 + value: 14 + - name: Mul16x + description: PLL input clock x16 + value: 15 +enum/PLLSRC: + bit_size: 1 + variants: + - name: HSI_Div2 + description: HSI divided by 2 selected as PLL input clock + value: 0 + - name: HSE_Div_PREDIV + description: HSE divided by PREDIV selected as PLL input clock + value: 1 +enum/PLLXTPRE: + bit_size: 1 + variants: + - name: Div1 + description: HSE clock not divided + value: 0 + - name: Div2 + description: HSE clock divided by 2 + value: 1 +enum/PPRE1: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/PREDIV1: + bit_size: 4 + variants: + - name: Div1 + description: PREDIV input clock not divided + value: 0 + - name: Div2 + description: PREDIV input clock divided by 2 + value: 1 + - name: Div3 + description: PREDIV input clock divided by 3 + value: 2 + - name: Div4 + description: PREDIV input clock divided by 4 + value: 3 + - name: Div5 + description: PREDIV input clock divided by 5 + value: 4 + - name: Div6 + description: PREDIV input clock divided by 6 + value: 5 + - name: Div7 + description: PREDIV input clock divided by 7 + value: 6 + - name: Div8 + description: PREDIV input clock divided by 8 + value: 7 + - name: Div9 + description: PREDIV input clock divided by 9 + value: 8 + - name: Div10 + description: PREDIV input clock divided by 10 + value: 9 + - name: Div11 + description: PREDIV input clock divided by 11 + value: 10 + - name: Div12 + description: PREDIV input clock divided by 12 + value: 11 + - name: Div13 + description: PREDIV input clock divided by 13 + value: 12 + - name: Div14 + description: PREDIV input clock divided by 14 + value: 13 + - name: Div15 + description: PREDIV input clock divided by 15 + value: 14 + - name: Div16 + description: PREDIV input clock divided by 16 + value: 15 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 +enum/SW: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as system clock + value: 0 + - name: HSE + description: HSE selected as system clock + value: 1 + - name: PLL + description: PLL selected as system clock + value: 2 +enum/SWSR: + bit_size: 2 + variants: + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL + description: PLL used as system clock + value: 2 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 9cd4d81..fb74191 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -177,7 +177,8 @@ perimap = [ ('.*:USB_OTG_HS:otghs1_v1_.*', ('otghs', 'v1', 'OTG_HS')), ('STM32F0.*:RCC:.*', ('rcc', 'f0', 'RCC')), - ('STM32F10[0123].*:RCC:.*', ('rcc', 'f1', 'RCC')), + ('STM32F100.*:RCC:.*', ('rcc', 'f100', 'RCC')), + ('STM32F10[123].*:RCC:.*', ('rcc', 'f1', 'RCC')), ('STM32F10[57].*:RCC:.*', ('rcc', 'f1cl', 'RCC')), ('STM32F2.*:RCC:.*', ('rcc', 'f2', 'RCC')), ('STM32F3.*:RCC:.*', ('rcc', 'f3', 'RCC')), From e905859bdfe3a479cd44bc68f07b3a0811f0cff3 Mon Sep 17 00:00:00 2001 From: Grant Miller Date: Sun, 1 May 2022 13:31:59 -0500 Subject: [PATCH 30/35] Clean up rcc_f1.yaml --- data/registers/rcc_f1.yaml | 274 ------------------------------------- 1 file changed, 274 deletions(-) diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml index 3b7a5d2..77ea7b2 100644 --- a/data/registers/rcc_f1.yaml +++ b/data/registers/rcc_f1.yaml @@ -42,14 +42,6 @@ block/RCC: description: Control/status register (RCC_CSR) byte_offset: 36 fieldset: CSR - - name: AHBRSTR - description: AHB peripheral clock reset register (RCC_AHBRSTR) - byte_offset: 40 - fieldset: AHBRSTR - - name: CFGR2 - description: Clock configuration register 2 - byte_offset: 44 - fieldset: CFGR2 fieldset/AHBENR: description: AHB Peripheral Clock enable register (RCC_AHBENR) fields: @@ -81,33 +73,6 @@ fieldset/AHBENR: description: SDIO clock enable bit_offset: 10 bit_size: 1 - - name: USB_OTG_FSEN - description: USB OTG FS clock enable - bit_offset: 12 - bit_size: 1 - - name: ETHEN - description: Ethernet MAC clock enable - bit_offset: 14 - bit_size: 1 - - name: ETHTXEN - description: Ethernet MAC TX clock enable - bit_offset: 15 - bit_size: 1 - - name: ETHRXEN - description: Ethernet MAC RX clock enable - bit_offset: 16 - bit_size: 1 -fieldset/AHBRSTR: - description: AHB peripheral clock reset register (RCC_AHBRSTR) - fields: - - name: USB_OTG_FSRST - description: USB OTG FS reset - bit_offset: 12 - bit_size: 1 - - name: ETHRST - description: Ethernet MAC reset - bit_offset: 14 - bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register (RCC_APB1ENR) fields: @@ -187,18 +152,10 @@ fieldset/APB1ENR: description: USB clock enable bit_offset: 23 bit_size: 1 - - name: CAN1EN - description: CAN1 clock enable - bit_offset: 25 - bit_size: 1 - name: CANEN description: CAN clock enable bit_offset: 25 bit_size: 1 - - name: CAN2EN - description: CAN2 clock enable - bit_offset: 26 - bit_size: 1 - name: BKPEN description: Backup interface clock enable bit_offset: 27 @@ -211,10 +168,6 @@ fieldset/APB1ENR: description: DAC interface clock enable bit_offset: 29 bit_size: 1 - - name: CECEN - description: CEC clock enable - bit_offset: 30 - bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register (RCC_APB1RSTR) fields: @@ -294,18 +247,10 @@ fieldset/APB1RSTR: description: USB reset bit_offset: 23 bit_size: 1 - - name: CAN1RST - description: CAN1 reset - bit_offset: 25 - bit_size: 1 - name: CANRST description: CAN reset bit_offset: 25 bit_size: 1 - - name: CAN2RST - description: CAN2 reset - bit_offset: 26 - bit_size: 1 - name: BKPRST description: Backup interface reset bit_offset: 27 @@ -318,10 +263,6 @@ fieldset/APB1RSTR: description: DAC interface reset bit_offset: 29 bit_size: 1 - - name: CECRST - description: CEC reset - bit_offset: 30 - bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register (RCC_APB2ENR) fields: @@ -385,18 +326,6 @@ fieldset/APB2ENR: description: ADC3 interface clock enable bit_offset: 15 bit_size: 1 - - name: TIM15EN - description: TIM15 Timer clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: TIM16 Timer clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: TIM17 Timer clock enable - bit_offset: 18 - bit_size: 1 - name: TIM9EN description: TIM9 Timer clock enable bit_offset: 19 @@ -472,18 +401,6 @@ fieldset/APB2RSTR: description: ADC 3 interface reset bit_offset: 15 bit_size: 1 - - name: TIM15RST - description: TIM15 timer reset - bit_offset: 16 - bit_size: 1 - - name: TIM16RST - description: TIM16 timer reset - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: TIM17 timer reset - bit_offset: 18 - bit_size: 1 - name: TIM9RST description: TIM9 timer reset bit_offset: 19 @@ -572,11 +489,6 @@ fieldset/CFGR: bit_offset: 18 bit_size: 4 enum: PLLMUL - - name: OTGFSPRE - description: USB OTG FS prescaler - bit_offset: 22 - bit_size: 1 - enum: OTGFSPRE - name: USBPRE description: USB prescaler bit_offset: 22 @@ -587,44 +499,6 @@ fieldset/CFGR: bit_offset: 24 bit_size: 3 enum: MCO -fieldset/CFGR2: - description: Clock configuration register2 (RCC_CFGR2) - fields: - - name: PREDIV1 - description: PREDIV1 division factor - bit_offset: 0 - bit_size: 4 - enum: PREDIV1 - - name: PREDIV2 - description: PREDIV2 division factor - bit_offset: 4 - bit_size: 4 - enum: PREDIV1 - - name: PLL2MUL - description: PLL2 Multiplication Factor - bit_offset: 8 - bit_size: 4 - enum: PLL2MUL - - name: PLL3MUL - description: PLL3 Multiplication Factor - bit_offset: 12 - bit_size: 4 - enum: PLL2MUL - - name: PREDIV1SRC - description: PREDIV1 entry clock source - bit_offset: 16 - bit_size: 1 - enum: PREDIV1SRC - - name: I2S2SRC - description: I2S2 clock source - bit_offset: 17 - bit_size: 1 - enum: I2S2SRC - - name: I2S3SRC - description: I2S3 clock source - bit_offset: 18 - bit_size: 1 - enum: I2S2SRC fieldset/CIR: description: Clock interrupt register (RCC_CIR) fields: @@ -648,14 +522,6 @@ fieldset/CIR: description: PLL Ready Interrupt flag bit_offset: 4 bit_size: 1 - - name: PLL2RDYF - description: PLL2 Ready Interrupt flag - bit_offset: 5 - bit_size: 1 - - name: PLL3RDYF - description: PLL3 Ready Interrupt flag - bit_offset: 6 - bit_size: 1 - name: CSSF description: Clock Security System Interrupt flag bit_offset: 7 @@ -680,14 +546,6 @@ fieldset/CIR: description: PLL Ready Interrupt Enable bit_offset: 12 bit_size: 1 - - name: PLL2RDYIE - description: PLL2 Ready Interrupt Enable - bit_offset: 13 - bit_size: 1 - - name: PLL3RDYIE - description: PLL3 Ready Interrupt Enable - bit_offset: 14 - bit_size: 1 - name: LSIRDYC description: LSI Ready Interrupt Clear bit_offset: 16 @@ -708,14 +566,6 @@ fieldset/CIR: description: PLL Ready Interrupt Clear bit_offset: 20 bit_size: 1 - - name: PLL2RDYC - description: PLL2 Ready Interrupt Clear - bit_offset: 21 - bit_size: 1 - - name: PLL3RDYC - description: PLL3 Ready Interrupt Clear - bit_offset: 22 - bit_size: 1 - name: CSSC description: Clock security system interrupt clear bit_offset: 23 @@ -763,22 +613,6 @@ fieldset/CR: description: PLL clock ready flag bit_offset: 25 bit_size: 1 - - name: PLL2ON - description: PLL2 enable - bit_offset: 26 - bit_size: 1 - - name: PLL2RDY - description: PLL2 clock ready flag - bit_offset: 27 - bit_size: 1 - - name: PLL3ON - description: PLL3 enable - bit_offset: 28 - bit_size: 1 - - name: PLL3RDY - description: PLL3 clock ready flag - bit_offset: 29 - bit_size: 1 fieldset/CSR: description: Control/status register (RCC_CSR) fields: @@ -863,15 +697,6 @@ enum/HPRE: - name: Div512 description: SYSCLK divided by 512 value: 15 -enum/I2S2SRC: - bit_size: 1 - variants: - - name: SYSCLK - description: System clock (SYSCLK) selected as I2S clock entry - value: 0 - - name: PLL3 - description: PLL3 VCO clock selected as I2S clock entry - value: 1 enum/MCO: bit_size: 3 variants: @@ -890,45 +715,6 @@ enum/MCO: - name: PLL description: PLL clock divided by 2 selected value: 7 -enum/OTGFSPRE: - bit_size: 1 - variants: - - name: DIV1_5 - description: PLL clock is divided by 1.5 - value: 0 - - name: DIV1 - description: PLL clock is not divided - value: 1 -enum/PLL2MUL: - bit_size: 4 - variants: - - name: Mul8 - description: PLL clock entry x8 - value: 6 - - name: Mul9 - description: PLL clock entry x9 - value: 7 - - name: Mul10 - description: PLL clock entry x10 - value: 8 - - name: Mul11 - description: PLL clock entry x11 - value: 9 - - name: Mul12 - description: PLL clock entry x12 - value: 10 - - name: Mul13 - description: PLL clock entry x13 - value: 11 - - name: Mul14 - description: PLL clock entry x14 - value: 12 - - name: Mul16 - description: PLL clock entry x16 - value: 14 - - name: Mul20 - description: PLL clock entry x20 - value: 15 enum/PLLMUL: bit_size: 4 variants: @@ -1016,66 +802,6 @@ enum/PPRE1: - name: Div16 description: HCLK divided by 16 value: 7 -enum/PREDIV1: - bit_size: 4 - variants: - - name: Div1 - description: PREDIV input clock not divided - value: 0 - - name: Div2 - description: PREDIV input clock divided by 2 - value: 1 - - name: Div3 - description: PREDIV input clock divided by 3 - value: 2 - - name: Div4 - description: PREDIV input clock divided by 4 - value: 3 - - name: Div5 - description: PREDIV input clock divided by 5 - value: 4 - - name: Div6 - description: PREDIV input clock divided by 6 - value: 5 - - name: Div7 - description: PREDIV input clock divided by 7 - value: 6 - - name: Div8 - description: PREDIV input clock divided by 8 - value: 7 - - name: Div9 - description: PREDIV input clock divided by 9 - value: 8 - - name: Div10 - description: PREDIV input clock divided by 10 - value: 9 - - name: Div11 - description: PREDIV input clock divided by 11 - value: 10 - - name: Div12 - description: PREDIV input clock divided by 12 - value: 11 - - name: Div13 - description: PREDIV input clock divided by 13 - value: 12 - - name: Div14 - description: PREDIV input clock divided by 14 - value: 13 - - name: Div15 - description: PREDIV input clock divided by 15 - value: 14 - - name: Div16 - description: PREDIV input clock divided by 16 - value: 15 -enum/PREDIV1SRC: - bit_size: 1 - variants: - - name: HSE - description: HSE oscillator clock selected as PREDIV1 clock entry - value: 0 - - name: PLL2 - description: PLL2 selected as PREDIV1 clock entry - value: 1 enum/RTCSEL: bit_size: 2 variants: From ad6f5a5434337364251402d71b87cc2c92a4a67b Mon Sep 17 00:00:00 2001 From: Grant Miller Date: Sun, 1 May 2022 14:25:38 -0500 Subject: [PATCH 31/35] Clean up rcc_f1cl.yaml --- data/registers/rcc_f1cl.yaml | 183 +---------------------------------- 1 file changed, 3 insertions(+), 180 deletions(-) diff --git a/data/registers/rcc_f1cl.yaml b/data/registers/rcc_f1cl.yaml index ff4bbf3..bcdb5e9 100644 --- a/data/registers/rcc_f1cl.yaml +++ b/data/registers/rcc_f1cl.yaml @@ -73,14 +73,6 @@ fieldset/AHBENR: description: CRC clock enable bit_offset: 6 bit_size: 1 - - name: FSMCEN - description: FSMC clock enable - bit_offset: 8 - bit_size: 1 - - name: SDIOEN - description: SDIO clock enable - bit_offset: 10 - bit_size: 1 - name: USB_OTG_FSEN description: USB OTG FS clock enable bit_offset: 12 @@ -135,18 +127,6 @@ fieldset/APB1ENR: description: Timer 7 clock enable bit_offset: 5 bit_size: 1 - - name: TIM12EN - description: Timer 12 clock enable - bit_offset: 6 - bit_size: 1 - - name: TIM13EN - description: Timer 13 clock enable - bit_offset: 7 - bit_size: 1 - - name: TIM14EN - description: Timer 14 clock enable - bit_offset: 8 - bit_size: 1 - name: WWDGEN description: Window watchdog clock enable bit_offset: 11 @@ -183,18 +163,10 @@ fieldset/APB1ENR: description: I2C 2 clock enable bit_offset: 22 bit_size: 1 - - name: USBEN - description: USB clock enable - bit_offset: 23 - bit_size: 1 - name: CAN1EN description: CAN1 clock enable bit_offset: 25 bit_size: 1 - - name: CANEN - description: CAN clock enable - bit_offset: 25 - bit_size: 1 - name: CAN2EN description: CAN2 clock enable bit_offset: 26 @@ -211,10 +183,6 @@ fieldset/APB1ENR: description: DAC interface clock enable bit_offset: 29 bit_size: 1 - - name: CECEN - description: CEC clock enable - bit_offset: 30 - bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register (RCC_APB1RSTR) fields: @@ -242,18 +210,6 @@ fieldset/APB1RSTR: description: Timer 7 reset bit_offset: 5 bit_size: 1 - - name: TIM12RST - description: Timer 12 reset - bit_offset: 6 - bit_size: 1 - - name: TIM13RST - description: Timer 13 reset - bit_offset: 7 - bit_size: 1 - - name: TIM14RST - description: Timer 14 reset - bit_offset: 8 - bit_size: 1 - name: WWDGRST description: Window watchdog reset bit_offset: 11 @@ -290,18 +246,10 @@ fieldset/APB1RSTR: description: I2C2 reset bit_offset: 22 bit_size: 1 - - name: USBRST - description: USB reset - bit_offset: 23 - bit_size: 1 - name: CAN1RST description: CAN1 reset bit_offset: 25 bit_size: 1 - - name: CANRST - description: CAN reset - bit_offset: 25 - bit_size: 1 - name: CAN2RST description: CAN2 reset bit_offset: 26 @@ -318,10 +266,6 @@ fieldset/APB1RSTR: description: DAC interface reset bit_offset: 29 bit_size: 1 - - name: CECRST - description: CEC reset - bit_offset: 30 - bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register (RCC_APB2ENR) fields: @@ -349,14 +293,6 @@ fieldset/APB2ENR: description: I/O port E clock enable bit_offset: 6 bit_size: 1 - - name: GPIOFEN - description: I/O port F clock enable - bit_offset: 7 - bit_size: 1 - - name: GPIOGEN - description: I/O port G clock enable - bit_offset: 8 - bit_size: 1 - name: ADC1EN description: ADC 1 interface clock enable bit_offset: 9 @@ -373,42 +309,10 @@ fieldset/APB2ENR: description: SPI 1 clock enable bit_offset: 12 bit_size: 1 - - name: TIM8EN - description: TIM8 Timer clock enable - bit_offset: 13 - bit_size: 1 - name: USART1EN description: USART1 clock enable bit_offset: 14 bit_size: 1 - - name: ADC3EN - description: ADC3 interface clock enable - bit_offset: 15 - bit_size: 1 - - name: TIM15EN - description: TIM15 Timer clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: TIM16 Timer clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: TIM17 Timer clock enable - bit_offset: 18 - bit_size: 1 - - name: TIM9EN - description: TIM9 Timer clock enable - bit_offset: 19 - bit_size: 1 - - name: TIM10EN - description: TIM10 Timer clock enable - bit_offset: 20 - bit_size: 1 - - name: TIM11EN - description: TIM11 Timer clock enable - bit_offset: 21 - bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register (RCC_APB2RSTR) fields: @@ -436,14 +340,6 @@ fieldset/APB2RSTR: description: IO port E reset bit_offset: 6 bit_size: 1 - - name: GPIOFRST - description: IO port F reset - bit_offset: 7 - bit_size: 1 - - name: GPIOGRST - description: IO port G reset - bit_offset: 8 - bit_size: 1 - name: ADC1RST description: ADC 1 interface reset bit_offset: 9 @@ -460,42 +356,10 @@ fieldset/APB2RSTR: description: SPI 1 reset bit_offset: 12 bit_size: 1 - - name: TIM8RST - description: TIM8 timer reset - bit_offset: 13 - bit_size: 1 - name: USART1RST description: USART1 reset bit_offset: 14 bit_size: 1 - - name: ADC3RST - description: ADC 3 interface reset - bit_offset: 15 - bit_size: 1 - - name: TIM15RST - description: TIM15 timer reset - bit_offset: 16 - bit_size: 1 - - name: TIM16RST - description: TIM16 timer reset - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: TIM17 timer reset - bit_offset: 18 - bit_size: 1 - - name: TIM9RST - description: TIM9 timer reset - bit_offset: 19 - bit_size: 1 - - name: TIM10RST - description: TIM10 timer reset - bit_offset: 20 - bit_size: 1 - - name: TIM11RST - description: TIM11 timer reset - bit_offset: 21 - bit_size: 1 fieldset/BDCR: description: Backup domain control register (RCC_BDCR) fields: @@ -525,7 +389,7 @@ fieldset/BDCR: bit_offset: 16 bit_size: 1 fieldset/CFGR: - description: Clock configuration register (RCC_3FGR) + description: Clock configuration register (RCC_CFGR) fields: - name: SW description: System clock Switch @@ -572,11 +436,6 @@ fieldset/CFGR: bit_offset: 18 bit_size: 4 enum: PLLMUL - - name: OTGFSPRE - description: USB OTG FS prescaler - bit_offset: 22 - bit_size: 1 - enum: OTGFSPRE - name: USBPRE description: USB prescaler bit_offset: 22 @@ -902,15 +761,6 @@ enum/MCO: - name: PLL3 description: PLL3 clock selected value: 11 -enum/OTGFSPRE: - bit_size: 1 - variants: - - name: DIV1_5 - description: PLL clock is divided by 1.5 - value: 0 - - name: DIV1 - description: PLL clock is not divided - value: 1 enum/PLL2MUL: bit_size: 4 variants: @@ -944,12 +794,6 @@ enum/PLL2MUL: enum/PLLMUL: bit_size: 4 variants: - - name: Mul2 - description: PLL input clock x2 - value: 0 - - name: Mul3 - description: PLL input clock x3 - value: 1 - name: Mul4 description: PLL input clock x4 value: 2 @@ -968,30 +812,9 @@ enum/PLLMUL: - name: Mul9 description: PLL input clock x9 value: 7 - - name: Mul10 - description: PLL input clock x10 - value: 8 - - name: Mul11 - description: PLL input clock x11 - value: 9 - - name: Mul12 - description: PLL input clock x12 - value: 10 - - name: Mul13 - description: PLL input clock x13 - value: 11 - - name: Mul14 - description: PLL input clock x14 - value: 12 - - name: Mul15 - description: PLL input clock x15 + - name: Mul6_5 + description: PLL input clock x6.5 value: 13 - - name: Mul16 - description: PLL input clock x16 - value: 14 - - name: Mul16x - description: PLL input clock x16 - value: 15 enum/PLLSRC: bit_size: 1 variants: From 423a80a8f8361b4b04b4efaab7dc010b5d5bc017 Mon Sep 17 00:00:00 2001 From: Grant Miller Date: Sun, 1 May 2022 16:15:54 -0500 Subject: [PATCH 32/35] Fix ADCPRE descriptions --- data/registers/rcc_f1.yaml | 4 ++-- data/registers/rcc_f100.yaml | 4 ++-- data/registers/rcc_f1cl.yaml | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml index 77ea7b2..57fd23e 100644 --- a/data/registers/rcc_f1.yaml +++ b/data/registers/rcc_f1.yaml @@ -662,10 +662,10 @@ enum/ADCPRE: description: PCLK2 divided by 4 value: 1 - name: Div6 - description: PCLK2 divided by 8 + description: PCLK2 divided by 6 value: 2 - name: Div8 - description: PCLK2 divided by 16 + description: PCLK2 divided by 8 value: 3 enum/HPRE: bit_size: 4 diff --git a/data/registers/rcc_f100.yaml b/data/registers/rcc_f100.yaml index aaf80b7..6caf3a9 100644 --- a/data/registers/rcc_f100.yaml +++ b/data/registers/rcc_f100.yaml @@ -633,10 +633,10 @@ enum/ADCPRE: description: PCLK2 divided by 4 value: 1 - name: Div6 - description: PCLK2 divided by 8 + description: PCLK2 divided by 6 value: 2 - name: Div8 - description: PCLK2 divided by 16 + description: PCLK2 divided by 8 value: 3 enum/HPRE: bit_size: 4 diff --git a/data/registers/rcc_f1cl.yaml b/data/registers/rcc_f1cl.yaml index bcdb5e9..2512e2d 100644 --- a/data/registers/rcc_f1cl.yaml +++ b/data/registers/rcc_f1cl.yaml @@ -687,10 +687,10 @@ enum/ADCPRE: description: PCLK2 divided by 4 value: 1 - name: Div6 - description: PCLK2 divided by 8 + description: PCLK2 divided by 6 value: 2 - name: Div8 - description: PCLK2 divided by 16 + description: PCLK2 divided by 8 value: 3 enum/HPRE: bit_size: 4 From f2498652f1497474c59ff3e460ebd04a37b1a3b7 Mon Sep 17 00:00:00 2001 From: Matous Hybl Date: Fri, 6 May 2022 21:52:51 +0200 Subject: [PATCH 33/35] Clean-up F3 and F7 flash registers --- data/registers/flash_f3.yaml | 219 ----------------------------------- data/registers/flash_f7.yaml | 79 ------------- 2 files changed, 298 deletions(-) diff --git a/data/registers/flash_f3.yaml b/data/registers/flash_f3.yaml index b8cdd2b..102491e 100644 --- a/data/registers/flash_f3.yaml +++ b/data/registers/flash_f3.yaml @@ -51,17 +51,14 @@ fieldset/ACR: description: Flash half cycle access enable bit_offset: 3 bit_size: 1 - enum: HLFCYA - name: PRFTBE description: PRFTBE bit_offset: 4 bit_size: 1 - enum: PRFTBE - name: PRFTBS description: PRFTBS bit_offset: 5 bit_size: 1 - enum: PRFTBS fieldset/AR: description: Flash address register fields: @@ -76,17 +73,14 @@ fieldset/CR: description: Programming bit_offset: 0 bit_size: 1 - enum: PG - name: PER description: Page erase bit_offset: 1 bit_size: 1 - enum: PER - name: MER description: Mass erase bit_offset: 2 bit_size: 1 - enum: MER - name: OPTPG description: Option byte programming bit_offset: 4 @@ -96,33 +90,26 @@ fieldset/CR: description: Option byte erase bit_offset: 5 bit_size: 1 - enum: OPTER - name: STRT description: Start bit_offset: 6 bit_size: 1 - enum: STRT - name: LOCK description: Lock bit_offset: 7 bit_size: 1 - enum_read: LOCKR - enum_write: LOCKW - name: OPTWRE description: Option bytes write enable bit_offset: 9 bit_size: 1 - enum: OPTWRE - name: ERRIE description: Error interrupt enable bit_offset: 10 bit_size: 1 - enum: ERRIE - name: EOPIE description: End of operation interrupt enable bit_offset: 12 bit_size: 1 - enum: EOPIE - name: OBL_LAUNCH description: Force option byte loading bit_offset: 13 @@ -142,7 +129,6 @@ fieldset/OBR: description: Option byte error bit_offset: 0 bit_size: 1 - enum: OPTERR - name: RDPRT description: Read protection Level status bit_offset: 1 @@ -167,12 +153,10 @@ fieldset/OBR: description: BOOT1 bit_offset: 12 bit_size: 1 - enum: nBOOT - name: VDDA_MONITOR description: VDDA_MONITOR bit_offset: 13 bit_size: 1 - enum: VDDA_MONITOR - name: SRAM_PARITY_CHECK description: SRAM_PARITY_CHECK bit_offset: 14 @@ -181,7 +165,6 @@ fieldset/OBR: description: SDADC12_VDD_MONITOR bit_offset: 15 bit_size: 1 - enum: SDADC_VDD_MONITOR - name: Data0 description: Data0 bit_offset: 16 @@ -204,25 +187,18 @@ fieldset/SR: description: Busy bit_offset: 0 bit_size: 1 - enum_read: BSYR - name: PGERR description: Programming error bit_offset: 2 bit_size: 1 - enum_read: PGERRR - enum_write: PGERRW - name: WRPRTERR description: Write protection error bit_offset: 4 bit_size: 1 - enum_read: WRPRTERRR - enum_write: WRPRTERRW - name: EOP description: End of operation bit_offset: 5 bit_size: 1 - enum_read: EOPR - enum_write: EOPW fieldset/WRPR: description: Write protection register fields: @@ -230,57 +206,6 @@ fieldset/WRPR: description: Write protect bit_offset: 0 bit_size: 32 -enum/BSYR: - bit_size: 1 - variants: - - name: Inactive - description: No write/erase operation is in progress - value: 0 - - name: Active - description: No write/erase operation is in progress - value: 1 -enum/EOPIE: - bit_size: 1 - variants: - - name: Disabled - description: End of operation interrupt disabled - value: 0 - - name: Enabled - description: End of operation interrupt enabled - value: 1 -enum/EOPR: - bit_size: 1 - variants: - - name: NoEvent - description: No EOP event occurred - value: 0 - - name: Event - description: An EOP event occurred - value: 1 -enum/EOPW: - bit_size: 1 - variants: - - name: Reset - description: Reset EOP event - value: 1 -enum/ERRIE: - bit_size: 1 - variants: - - name: Disabled - description: Error interrupt generation disabled - value: 0 - - name: Enabled - description: Error interrupt generation enabled - value: 1 -enum/HLFCYA: - bit_size: 1 - variants: - - name: Disabled - description: Half cycle is disabled - value: 0 - - name: Enabled - description: Half cycle is enabled - value: 1 enum/LATENCY: bit_size: 3 variants: @@ -293,27 +218,6 @@ enum/LATENCY: - name: WS2 description: "2 wait states, if 48 < HCLK <= 72 MHz" value: 2 -enum/LOCKR: - bit_size: 1 - variants: - - name: Unlocked - description: FLASH_CR register is unlocked - value: 0 - - name: Locked - description: FLASH_CR register is locked - value: 1 -enum/LOCKW: - bit_size: 1 - variants: - - name: Lock - description: Lock the FLASH_CR register - value: 1 -enum/MER: - bit_size: 1 - variants: - - name: MassErase - description: Erase activated for all user sectors - value: 1 enum/OBL_LAUNCH: bit_size: 1 variants: @@ -323,78 +227,12 @@ enum/OBL_LAUNCH: - name: Active description: Force option byte loading active value: 1 -enum/OPTER: - bit_size: 1 - variants: - - name: OptionByteErase - description: Erase option byte activated - value: 1 -enum/OPTERR: - bit_size: 1 - variants: - - name: OptionByteError - description: The loaded option byte and its complement do not match - value: 1 enum/OPTPG: bit_size: 1 variants: - name: OptionByteProgramming description: Program option byte activated value: 1 -enum/OPTWRE: - bit_size: 1 - variants: - - name: Disabled - description: Option byte write enabled - value: 0 - - name: Enabled - description: Option byte write disabled - value: 1 -enum/PER: - bit_size: 1 - variants: - - name: PageErase - description: Erase activated for selected page - value: 1 -enum/PG: - bit_size: 1 - variants: - - name: Program - description: Flash programming activated - value: 1 -enum/PGERRR: - bit_size: 1 - variants: - - name: NoError - description: No programming error occurred - value: 0 - - name: Error - description: A programming error occurred - value: 1 -enum/PGERRW: - bit_size: 1 - variants: - - name: Reset - description: Reset programming error - value: 1 -enum/PRFTBE: - bit_size: 1 - variants: - - name: Disabled - description: Prefetch is disabled - value: 0 - - name: Enabled - description: Prefetch is enabled - value: 1 -enum/PRFTBS: - bit_size: 1 - variants: - - name: Disabled - description: Prefetch buffer is disabled - value: 0 - - name: Enabled - description: Prefetch buffer is enabled - value: 1 enum/RDPRT: bit_size: 2 variants: @@ -407,39 +245,6 @@ enum/RDPRT: - name: Level2 description: Level 2 value: 3 -enum/SDADC_VDD_MONITOR: - bit_size: 1 - variants: - - name: Disabled - description: VDDSD12 monitoring disabled - value: 0 - - name: Enabled - description: VDDSD12 monitoring enabled - value: 1 -enum/SRAM_PARITY_CHECK: - bit_size: 1 - variants: - - name: Disabled - description: RAM parity check disabled - value: 0 - - name: Enabled - description: RAM parity check enabled - value: 1 -enum/STRT: - bit_size: 1 - variants: - - name: Start - description: Trigger an erase operation - value: 1 -enum/VDDA_MONITOR: - bit_size: 1 - variants: - - name: Disabled - description: VDDA power supply supervisor disabled - value: 0 - - name: Enabled - description: VDDA power supply supervisor enabled - value: 1 enum/WDG_SW: bit_size: 1 variants: @@ -449,30 +254,6 @@ enum/WDG_SW: - name: Software description: Software watchdog value: 1 -enum/WRPRTERRR: - bit_size: 1 - variants: - - name: NoError - description: No write protection error occurred - value: 0 - - name: Error - description: A write protection error occurred - value: 1 -enum/WRPRTERRW: - bit_size: 1 - variants: - - name: Reset - description: Reset write protection error - value: 1 -enum/nBOOT: - bit_size: 1 - variants: - - name: Disabled - description: "Together with BOOT0, select the device boot mode" - value: 0 - - name: Enabled - description: "Together with BOOT0, select the device boot mode" - value: 1 enum/nRST_STDBY: bit_size: 1 variants: diff --git a/data/registers/flash_f7.yaml b/data/registers/flash_f7.yaml index 5f34009..3e9ae06 100644 --- a/data/registers/flash_f7.yaml +++ b/data/registers/flash_f7.yaml @@ -48,17 +48,14 @@ fieldset/ACR: description: Prefetch enable bit_offset: 8 bit_size: 1 - enum: PRFTEN - name: ARTEN description: ART Accelerator Enable bit_offset: 9 bit_size: 1 - enum: ARTEN - name: ARTRST description: ART Accelerator reset bit_offset: 11 bit_size: 1 - enum: ARTRST fieldset/CR: description: Control register fields: @@ -66,17 +63,14 @@ fieldset/CR: description: Programming bit_offset: 0 bit_size: 1 - enum: PG - name: SER description: Sector Erase bit_offset: 1 bit_size: 1 - enum: SER - name: MER description: Mass Erase of sectors 0 to 11 bit_offset: 2 bit_size: 1 - enum: MER - name: SNB description: Sector number bit_offset: 3 @@ -90,17 +84,14 @@ fieldset/CR: description: Start bit_offset: 16 bit_size: 1 - enum: STRT - name: EOPIE description: End of operation interrupt enable bit_offset: 24 bit_size: 1 - enum: EOPIE - name: ERRIE description: Error interrupt enable bit_offset: 25 bit_size: 1 - enum: ERRIE - name: RDERRIE description: PCROP error interrupt enable bit_offset: 26 @@ -109,7 +100,6 @@ fieldset/CR: description: Lock bit_offset: 31 bit_size: 1 - enum: LOCK fieldset/KEYR: description: Flash key register fields: @@ -236,15 +226,6 @@ fieldset/SR: description: Busy bit_offset: 16 bit_size: 1 -enum/ARTEN: - bit_size: 1 - variants: - - name: Disabled - description: ART Accelerator is disabled - value: 0 - - name: Enabled - description: ART Accelerator is enabled - value: 1 enum/ARTRST: bit_size: 1 variants: @@ -254,24 +235,6 @@ enum/ARTRST: - name: Reset description: Accelerator is reset value: 1 -enum/EOPIE: - bit_size: 1 - variants: - - name: Disabled - description: End of operation interrupt disabled - value: 0 - - name: Enabled - description: End of operation interrupt enabled - value: 1 -enum/ERRIE: - bit_size: 1 - variants: - - name: Disabled - description: Error interrupt generation disabled - value: 0 - - name: Enabled - description: Error interrupt generation enabled - value: 1 enum/LATENCY: bit_size: 4 variants: @@ -323,36 +286,6 @@ enum/LATENCY: - name: WS15 description: 15 wait states value: 15 -enum/LOCK: - bit_size: 1 - variants: - - name: Unlocked - description: FLASH_CR register is unlocked - value: 0 - - name: Locked - description: FLASH_CR register is locked - value: 1 -enum/MER: - bit_size: 1 - variants: - - name: MassErase - description: Erase activated for all user sectors - value: 1 -enum/PG: - bit_size: 1 - variants: - - name: Program - description: Flash programming activated - value: 1 -enum/PRFTEN: - bit_size: 1 - variants: - - name: Disabled - description: Prefetch is disabled - value: 0 - - name: Enabled - description: Prefetch is enabled - value: 1 enum/PSIZE: bit_size: 2 variants: @@ -368,15 +301,3 @@ enum/PSIZE: - name: PSIZE64 description: Program x64 value: 3 -enum/SER: - bit_size: 1 - variants: - - name: SectorErase - description: Erase activated for selected sector - value: 1 -enum/STRT: - bit_size: 1 - variants: - - name: Start - description: Trigger an erase operation - value: 1 From 805f86c8cbbdea59aa10ae3b14eb98f0333f931d Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Mon, 30 May 2022 00:58:10 +0200 Subject: [PATCH 34/35] pwr_l5: add missing State0 VOS --- data/registers/pwr_l5.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/data/registers/pwr_l5.yaml b/data/registers/pwr_l5.yaml index 6689429..ffca43e 100644 --- a/data/registers/pwr_l5.yaml +++ b/data/registers/pwr_l5.yaml @@ -476,6 +476,9 @@ enum/USV: enum/VOS: bit_size: 2 variants: + - name: Range0 + description: Range 0 + value: 0 - name: Range1 description: Range 1 value: 1 From ed612cb8a297b1baa31ec88ad263cc47cbf46108 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Mon, 30 May 2022 00:58:22 +0200 Subject: [PATCH 35/35] usb: unify StatRx, StatTx. --- data/registers/usb_v1.yaml | 29 +++++++---------------------- data/registers/usb_v2.yaml | 29 +++++++---------------------- 2 files changed, 14 insertions(+), 44 deletions(-) diff --git a/data/registers/usb_v1.yaml b/data/registers/usb_v1.yaml index 259b17f..db68627 100644 --- a/data/registers/usb_v1.yaml +++ b/data/registers/usb_v1.yaml @@ -114,7 +114,7 @@ fieldset/EPR: description: STAT_TX bit_offset: 4 bit_size: 2 - enum: STAT_TX + enum: STAT - name: DTOG_TX description: DTOG_TX bit_offset: 6 @@ -140,7 +140,7 @@ fieldset/EPR: description: STAT_RX bit_offset: 12 bit_size: 2 - enum: STAT_RX + enum: STAT - name: DTOG_RX description: DTOG_RX bit_offset: 14 @@ -240,33 +240,18 @@ enum/EP_TYPE: - name: Interrupt description: Interrupt endpoint value: 3 -enum/STAT_RX: +enum/STAT: bit_size: 2 variants: - name: Disabled - description: all reception requests addressed to this endpoint are ignored + description: all requests addressed to this endpoint are ignored value: 0 - name: Stall - description: the endpoint is stalled and all reception requests result in a STALL handshake + description: the endpoint is stalled and all requests result in a STALL handshake value: 1 - name: Nak - description: the endpoint is naked and all reception requests result in a NAK handshake + description: the endpoint is naked and all requests result in a NAK handshake value: 2 - name: Valid - description: this endpoint is enabled for reception - value: 3 -enum/STAT_TX: - bit_size: 2 - variants: - - name: Disabled - description: all transmission requests addressed to this endpoint are ignored - value: 0 - - name: Stall - description: the endpoint is stalled and all transmission requests result in a STALL handshake - value: 1 - - name: Nak - description: the endpoint is naked and all transmission requests result in a NAK handshake - value: 2 - - name: Valid - description: this endpoint is enabled for transmission + description: this endpoint is enabled, requests are ACKed value: 3 diff --git a/data/registers/usb_v2.yaml b/data/registers/usb_v2.yaml index f5d20de..f326227 100644 --- a/data/registers/usb_v2.yaml +++ b/data/registers/usb_v2.yaml @@ -170,7 +170,7 @@ fieldset/EPR: description: STAT_TX bit_offset: 4 bit_size: 2 - enum: STAT_TX + enum: STAT - name: DTOG_TX description: DTOG_TX bit_offset: 6 @@ -196,7 +196,7 @@ fieldset/EPR: description: STAT_RX bit_offset: 12 bit_size: 2 - enum: STAT_RX + enum: STAT - name: DTOG_RX description: DTOG_RX bit_offset: 14 @@ -338,33 +338,18 @@ enum/SDET: - name: DCP description: DCP detected value: 1 -enum/STAT_RX: +enum/STAT: bit_size: 2 variants: - name: Disabled - description: all reception requests addressed to this endpoint are ignored + description: all requests addressed to this endpoint are ignored value: 0 - name: Stall - description: the endpoint is stalled and all reception requests result in a STALL handshake + description: the endpoint is stalled and all requests result in a STALL handshake value: 1 - name: Nak - description: the endpoint is naked and all reception requests result in a NAK handshake + description: the endpoint is naked and all requests result in a NAK handshake value: 2 - name: Valid - description: this endpoint is enabled for reception - value: 3 -enum/STAT_TX: - bit_size: 2 - variants: - - name: Disabled - description: all transmission requests addressed to this endpoint are ignored - value: 0 - - name: Stall - description: the endpoint is stalled and all transmission requests result in a STALL handshake - value: 1 - - name: Nak - description: the endpoint is naked and all transmission requests result in a NAK handshake - value: 2 - - name: Valid - description: this endpoint is enabled for transmission + description: this endpoint is enabled, requests are ACKed value: 3