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Add stm32c0, fixes for updated stm32-data-sources.

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This commit is contained in:
Dario Nieuwenhuis 2023-01-17 18:51:41 +01:00
parent 026038a23c
commit 10fcc5d9dd
11 changed files with 2247 additions and 13 deletions
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2
Cargo.toml
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@ -17,7 +17,7 @@ quick-xml = { version = "0.26.0", features = ["serialize"] }
regex = "1.6.0" regex = "1.6.0"
serde = { version = "1.0.147", features = ["derive"] } serde = { version = "1.0.147", features = ["derive"] }
serde_yaml = "0.9.14" serde_yaml = "0.9.14"
chiptool = { git = "https://github.com/embassy-rs/chiptool", rev = "28ffa8a19d84914089547f52900ffb5877a5dc23" } chiptool = { git = "https://github.com/embassy-rs/chiptool", rev = "1d9e0a39a6acc291e50cabc4ed617a87f06d5e89" }
serde_json = "1.0.87" serde_json = "1.0.87"
rayon = { version = "1.5.3", optional = true } rayon = { version = "1.5.3", optional = true }
stm32-data-serde = { version = "0.1.0", path = "stm32-data-serde" } stm32-data-serde = { version = "0.1.0", path = "stm32-data-serde" }

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data/registers/dbgmcu_c0.yaml Normal file
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---
block/DBGMCU:
description: Debug support
items:
- name: IDCODE
description: MCU Device ID Code Register
byte_offset: 0
access: Read
fieldset: IDCODE
- name: CR
description: Debug MCU Configuration Register
byte_offset: 4
fieldset: CR
- name: APB1FZR
description: DBG APB freeze register 1
byte_offset: 8
fieldset: APB1FZR
- name: APB2FZR
description: DBG APB freeze register 2
byte_offset: 12
fieldset: APB2FZR
fieldset/APB1FZR:
description: DBG APB freeze register 1
fields:
- name: TIM3
description: TIM3 counter stopped when core is halted
bit_offset: 1
bit_size: 1
- name: RTC
description: Debug RTC stopped when Core is halted
bit_offset: 10
bit_size: 1
- name: WWDG
description: Debug Window Wachdog stopped when Core is halted
bit_offset: 11
bit_size: 1
- name: IWDG
description: Debug Independent Wachdog stopped when Core is halted
bit_offset: 12
bit_size: 1
- name: I2C1
description: I2C1 SMBUS timeout mode stopped when core is halted
bit_offset: 21
bit_size: 1
fieldset/APB2FZR:
description: DBG APB freeze register 2
fields:
- name: TIM1
description: TIM1
bit_offset: 11
bit_size: 1
- name: TIM14
description: TIM14
bit_offset: 15
bit_size: 1
- name: TIM16
description: TIM16
bit_offset: 17
bit_size: 1
- name: TIM17
description: TIM17
bit_offset: 18
bit_size: 1
fieldset/CR:
description: Debug MCU Configuration Register
fields:
- name: DBG_STOP
description: Debug Stop Mode
bit_offset: 1
bit_size: 1
- name: DBG_STANDBY
description: Debug Standby Mode
bit_offset: 2
bit_size: 1
fieldset/IDCODE:
description: MCU Device ID Code Register
fields:
- name: DEV_ID
description: Device Identifier
bit_offset: 0
bit_size: 16
- name: REV_ID
description: Revision Identifier
bit_offset: 16
bit_size: 16

80
data/registers/exti_c0.yaml Normal file
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---
block/EXTI:
description: External interrupt/event controller
items:
- name: RTSR
description: Rising Trigger selection register
array:
len: 1
stride: 40
byte_offset: 0
fieldset: LINES
- name: FTSR
description: Falling Trigger selection register
array:
len: 1
stride: 40
byte_offset: 4
fieldset: LINES
- name: SWIER
description: Software interrupt event register
array:
len: 1
stride: 40
byte_offset: 8
fieldset: LINES
- name: RPR
description: Rising pending register
array:
len: 1
stride: 40
byte_offset: 12
fieldset: LINES
- name: FPR
description: Falling pending register
array:
len: 1
stride: 40
byte_offset: 16
fieldset: LINES
- name: EXTICR
description: Configuration register
array:
len: 4
stride: 4
byte_offset: 96
fieldset: EXTICR
- name: IMR
description: Interrupt mask register
array:
len: 1
stride: 16
byte_offset: 128
fieldset: LINES
- name: EMR
description: Event mask register
array:
len: 1
stride: 16
byte_offset: 132
fieldset: LINES
fieldset/EXTICR:
description: external interrupt configuration register 1
fields:
- name: EXTI
description: EXTI configuration bits
bit_offset: 0
bit_size: 8
array:
len: 4
stride: 8
fieldset/LINES:
description: "EXTI lines register, 1 bit per line"
fields:
- name: LINE
description: EXTI line
bit_offset: 0
bit_size: 1
array:
len: 32
stride: 1

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data/registers/flash_c0.yaml Normal file
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---
block/FLASH:
description: Flash
items:
- name: ACR
description: Access control register
byte_offset: 0
fieldset: ACR
- name: KEYR
description: Flash key register
byte_offset: 8
access: Write
fieldset: KEYR
- name: OPTKEYR
description: Option byte key register
byte_offset: 12
access: Write
fieldset: OPTKEYR
- name: SR
description: Status register
byte_offset: 16
fieldset: SR
- name: CR
description: Flash control register
byte_offset: 20
fieldset: CR
- name: OPTR
description: Flash option register
byte_offset: 32
fieldset: OPTR
- name: PCROP1ASR
description: Flash PCROP zone A Start address register
byte_offset: 36
access: Read
fieldset: PCROP1ASR
- name: PCROP1AER
description: Flash PCROP zone A End address register
byte_offset: 40
access: Read
fieldset: PCROP1AER
- name: WRP1AR
description: Flash WRP area A address register
byte_offset: 44
access: Read
fieldset: WRP1AR
- name: WRP1BR
description: Flash WRP area B address register
byte_offset: 48
access: Read
fieldset: WRP1BR
- name: PCROP1BSR
description: Flash PCROP zone B Start address register
byte_offset: 52
access: Read
fieldset: PCROP1BSR
- name: PCROP1BER
description: Flash PCROP zone B End address register
byte_offset: 56
access: Read
fieldset: PCROP1BER
- name: SECR
description: Flash Security register
byte_offset: 128
access: Read
fieldset: SECR
fieldset/ACR:
description: Access control register
fields:
- name: LATENCY
description: Latency
bit_offset: 0
bit_size: 3
enum: LATENCY
- name: PRFTEN
description: Prefetch enable
bit_offset: 8
bit_size: 1
- name: ICEN
description: Instruction cache enable
bit_offset: 9
bit_size: 1
- name: ICRST
description: Instruction cache reset
bit_offset: 11
bit_size: 1
- name: EMPTY
description: Flash User area empty
bit_offset: 16
bit_size: 1
- name: DBG_SWEN
description: Debug access software enable
bit_offset: 18
bit_size: 1
fieldset/CR:
description: Flash control register
fields:
- name: PG
description: Programming
bit_offset: 0
bit_size: 1
- name: PER
description: Page erase
bit_offset: 1
bit_size: 1
- name: MER
description: Mass erase
bit_offset: 2
bit_size: 1
- name: PNB
description: Page number
bit_offset: 3
bit_size: 4
- name: STRT
description: Start
bit_offset: 16
bit_size: 1
- name: OPTSTRT
description: Options modification start
bit_offset: 17
bit_size: 1
- name: FSTPG
description: Fast programming
bit_offset: 18
bit_size: 1
- name: EOPIE
description: End of operation interrupt enable
bit_offset: 24
bit_size: 1
- name: ERRIE
description: Error interrupt enable
bit_offset: 25
bit_size: 1
- name: RDERRIE
description: PCROP read error interrupt enable
bit_offset: 26
bit_size: 1
- name: OBL_LAUNCH
description: Force the option byte loading
bit_offset: 27
bit_size: 1
- name: SEC_PROT
description: Securable memory area protection enable
bit_offset: 28
bit_size: 1
- name: OPTLOCK
description: Options Lock
bit_offset: 30
bit_size: 1
- name: LOCK
description: FLASH_CR Lock
bit_offset: 31
bit_size: 1
fieldset/KEYR:
description: Flash key register
fields:
- name: KEYR
description: KEYR
bit_offset: 0
bit_size: 32
fieldset/OPTKEYR:
description: Option byte key register
fields:
- name: OPTKEYR
description: Option byte key
bit_offset: 0
bit_size: 32
fieldset/OPTR:
description: Flash option register
fields:
- name: RDP
description: Read protection level
bit_offset: 0
bit_size: 8
enum: RDP
- name: BOREN
description: BOR reset Level
bit_offset: 8
bit_size: 1
- name: BORF_LEV
description: These bits contain the VDD supply level threshold that activates the reset
bit_offset: 9
bit_size: 2
enum: BORF_LEV
- name: BORR_LEV
description: These bits contain the VDD supply level threshold that releases the reset.
bit_offset: 11
bit_size: 2
enum: BORR_LEV
- name: nRST_STOP
description: nRST_STOP
bit_offset: 13
bit_size: 1
- name: nRST_STDBY
description: nRST_STDBY
bit_offset: 14
bit_size: 1
- name: nRSTS_HDW
description: nRSTS_HDW
bit_offset: 15
bit_size: 1
- name: IDWG_SW
description: Independent watchdog selection
bit_offset: 16
bit_size: 1
- name: IWDG_STOP
description: Independent watchdog counter freeze in Stop mode
bit_offset: 17
bit_size: 1
- name: IWDG_STDBY
description: Independent watchdog counter freeze in Standby mode
bit_offset: 18
bit_size: 1
- name: WWDG_SW
description: Window watchdog selection
bit_offset: 19
bit_size: 1
- name: RAM_PARITY_CHECK
description: SRAM parity check control
bit_offset: 22
bit_size: 1
- name: nBOOT_SEL
description: nBOOT_SEL
bit_offset: 24
bit_size: 1
- name: nBOOT1
description: Boot configuration
bit_offset: 25
bit_size: 1
- name: nBOOT0
description: nBOOT0 option bit
bit_offset: 26
bit_size: 1
- name: NRST_MODE
description: NRST_MODE
bit_offset: 27
bit_size: 2
enum: NRST_MODE
- name: IRHEN
description: Internal reset holder enable bit
bit_offset: 29
bit_size: 1
fieldset/PCROP1AER:
description: Flash PCROP zone A End address register
fields:
- name: PCROP1A_END
description: PCROP1A area end offset
bit_offset: 0
bit_size: 6
- name: PCROP_RDP
description: PCROP area preserved when RDP level decreased
bit_offset: 31
bit_size: 1
fieldset/PCROP1ASR:
description: Flash PCROP zone A Start address register
fields:
- name: PCROP1A_STRT
description: PCROP1A area start offset
bit_offset: 0
bit_size: 6
fieldset/PCROP1BER:
description: Flash PCROP zone B End address register
fields:
- name: PCROP1B_END
description: PCROP1B area end offset
bit_offset: 0
bit_size: 6
fieldset/PCROP1BSR:
description: Flash PCROP zone B Start address register
fields:
- name: PCROP1B_STRT
description: PCROP1B area start offset
bit_offset: 0
bit_size: 6
fieldset/SECR:
description: Flash Security register
fields:
- name: SEC_SIZE
description: Securable memory area size
bit_offset: 0
bit_size: 5
- name: BOOT_LOCK
description: used to force boot from user area
bit_offset: 16
bit_size: 1
fieldset/SR:
description: Status register
fields:
- name: EOP
description: End of operation
bit_offset: 0
bit_size: 1
- name: OPERR
description: Operation error
bit_offset: 1
bit_size: 1
- name: PROGERR
description: Programming error
bit_offset: 3
bit_size: 1
- name: WRPERR
description: Write protected error
bit_offset: 4
bit_size: 1
- name: PGAERR
description: Programming alignment error
bit_offset: 5
bit_size: 1
- name: SIZERR
description: Size error
bit_offset: 6
bit_size: 1
- name: PGSERR
description: Programming sequence error
bit_offset: 7
bit_size: 1
- name: MISERR
description: Fast programming data miss error
bit_offset: 8
bit_size: 1
- name: FASTERR
description: Fast programming error
bit_offset: 9
bit_size: 1
- name: RDERR
description: PCROP read error
bit_offset: 14
bit_size: 1
- name: OPTVERR
description: Option and Engineering bits loading validity error
bit_offset: 15
bit_size: 1
- name: BSY
description: Busy
bit_offset: 16
bit_size: 1
- name: CFGBSY
description: Programming or erase configuration busy.
bit_offset: 18
bit_size: 1
fieldset/WRP1AR:
description: Flash WRP area A address register
fields:
- name: WRP1A_STRT
description: WRP area A start offset
bit_offset: 0
bit_size: 6
- name: WRP1A_END
description: WRP area A end offset
bit_offset: 16
bit_size: 6
fieldset/WRP1BR:
description: Flash WRP area B address register
fields:
- name: WRP1B_STRT
description: WRP area B start offset
bit_offset: 0
bit_size: 6
- name: WRP1B_END
description: WRP area B end offset
bit_offset: 16
bit_size: 6
enum/BORF_LEV:
bit_size: 2
variants:
- name: FALLING_0
description: BOR falling level 1 with threshold around 2.0V
value: 0
- name: FALLING_1
description: BOR falling level 2 with threshold around 2.2V
value: 1
- name: FALLING_2
description: BOR falling level 3 with threshold around 2.5V
value: 2
- name: FALLING_3
description: BOR falling level 4 with threshold around 2.8V
value: 3
enum/BORR_LEV:
bit_size: 2
variants:
- name: RISING_0
description: BOR rising level 1 with threshold around 2.1V
value: 0
- name: RISING_1
description: BOR rising level 2 with threshold around 2.3V
value: 1
- name: RISING_2
description: BOR rising level 3 with threshold around 2.6V
value: 2
- name: RISING_3
description: BOR rising level 4 with threshold around 2.9V
value: 3
enum/LATENCY:
bit_size: 3
variants:
- name: WS0
description: Zero wait states
value: 0
- name: WS1
description: One wait state
value: 1
enum/NRST_MODE:
bit_size: 2
variants:
- name: INPUT_ONLY
description: Reset pin is in reset input mode only
value: 1
- name: GPIO
description: Reset pin is in GPIO mode only
value: 2
- name: INPUT_OUTPUT
description: Reset pin is in resety input and output mode
value: 3
enum/RDP:
bit_size: 8
variants:
- name: LEVEL_0
description: Read protection not active
value: 170
- name: LEVEL_1
description: Memories read protection active
value: 187
- name: LEVEL_2
description: Chip read protection active
value: 204

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data/registers/pwr_c0.yaml Normal file
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---
block/PWR:
description: PWR address block description
items:
- name: CR1
description: PWR control register 1
byte_offset: 0
fieldset: CR1
- name: CR3
description: PWR control register 3
byte_offset: 8
fieldset: CR3
- name: CR4
description: PWR control register 4
byte_offset: 12
fieldset: CR4
- name: SR1
description: PWR status register 1
byte_offset: 16
fieldset: SR1
- name: SR2
description: PWR status register 2
byte_offset: 20
fieldset: SR2
- name: SCR
description: PWR status clear register
byte_offset: 24
fieldset: SCR
- name: PUCR
description: PWR Port pull-up control register
array:
len: 6
stride: 8
byte_offset: 32
fieldset: PCR
- name: PDCR
description: PWR Port pull-down control register
array:
len: 6
stride: 8
byte_offset: 36
fieldset: PCR
fieldset/CR1:
description: PWR control register 1
fields:
- name: LPMS
description: "Low-power mode selection\r These bits select the low-power mode entered when CPU enters deepsleep mode.\r 1XX: Shutdown mode"
bit_offset: 0
bit_size: 3
- name: FPD_STOP
description: "Flash memory powered down during Stop mode\r This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode."
bit_offset: 3
bit_size: 1
- name: FPD_SLP
description: "Flash memory powered down during Sleep mode\r This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Sleep mode."
bit_offset: 5
bit_size: 1
fieldset/CR3:
description: PWR control register 3
fields:
- name: EWUP
description: Enable Wakeup pin
bit_offset: 0
bit_size: 1
array:
len: 6
stride: 1
- name: APC
description: "Apply pull-up and pull-down configuration\r This bit determines whether the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied."
bit_offset: 10
bit_size: 1
- name: EIWUL
description: "Enable internal wakeup line\r When set, a rising edge on the internal wakeup line triggers a wakeup event."
bit_offset: 15
bit_size: 1
fieldset/CR4:
description: PWR control register 4
fields:
- name: WP
description: Wakeup pin WKUP1 polarity
bit_offset: 0
bit_size: 1
array:
len: 6
stride: 1
fieldset/PCR:
description: Power Port pull control register
fields:
- name: P
description: Port pull bit y (y=0..15)
bit_offset: 0
bit_size: 1
array:
len: 16
stride: 1
fieldset/SCR:
description: PWR status clear register
fields:
- name: CWUF
description: Clear Wakeup flag
bit_offset: 0
bit_size: 1
array:
len: 6
stride: 1
- name: CSBF
description: "Clear standby flag\r Setting this bit clears the SBF flag in the PWR_SR1 register."
bit_offset: 8
bit_size: 1
fieldset/SR1:
description: PWR status register 1
fields:
- name: WUF
description: Wakeup flag
bit_offset: 0
bit_size: 1
array:
len: 6
stride: 1
- name: SBF
description: "Standby/Shutdown flag\r This bit is set by hardware when the device enters Standby or Shutdown mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset."
bit_offset: 8
bit_size: 1
- name: WUFI
description: "Wakeup flag internal\r This bit is set when a wakeup condition is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared."
bit_offset: 15
bit_size: 1
fieldset/SR2:
description: PWR status register 2
fields:
- name: FLASH_RDY
description: "Flash ready flag\r This bit is set by hardware to indicate when the Flash memory is ready to be accessed after wakeup from power-down. To place the Flash memory in power-down, set either FPD_SLP or FPD_STP bit.\r Note: If the system boots from SRAM, the user application must wait till FLASH_RDY bit is set, prior to jumping to Flash memory."
bit_offset: 7
bit_size: 1

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data/registers/rcc_c0.yaml Normal file
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---
block/RCC:
description: RCC address block description
items:
- name: CR
description: RCC clock control register
byte_offset: 0
fieldset: CR
- name: ICSCR
description: RCC internal clock source calibration register
byte_offset: 4
fieldset: ICSCR
- name: CFGR
description: RCC clock configuration register
byte_offset: 8
fieldset: CFGR
- name: CIER
description: RCC clock interrupt enable register
byte_offset: 24
fieldset: CIER
- name: CIFR
description: RCC clock interrupt flag register
byte_offset: 28
fieldset: CIFR
- name: CICR
description: RCC clock interrupt clear register
byte_offset: 32
fieldset: CICR
- name: GPIORSTR
description: RCC I/O port reset register
byte_offset: 36
fieldset: GPIORSTR
- name: AHBRSTR
description: RCC AHB peripheral reset register
byte_offset: 40
fieldset: AHBRSTR
- name: APBRSTR1
description: RCC APB peripheral reset register 1
byte_offset: 44
fieldset: APBRSTR1
- name: APBRSTR2
description: RCC APB peripheral reset register 2
byte_offset: 48
fieldset: APBRSTR2
- name: GPIOENR
description: RCC I/O port clock enable register
byte_offset: 52
fieldset: GPIOENR
- name: AHBENR
description: RCC AHB peripheral clock enable register
byte_offset: 56
fieldset: AHBENR
- name: APBENR1
description: RCC APB peripheral clock enable register 1
byte_offset: 60
fieldset: APBENR1
- name: APBENR2
description: RCC APB peripheral clock enable register 2
byte_offset: 64
fieldset: APBENR2
- name: GPIOSMENR
description: RCC I/O port in Sleep mode clock enable register
byte_offset: 68
fieldset: GPIOSMENR
- name: AHBSMENR
description: RCC AHB peripheral clock enable in Sleep/Stop mode register
byte_offset: 72
fieldset: AHBSMENR
- name: APBSMENR1
description: RCC APB peripheral clock enable in Sleep/Stop mode register 1
byte_offset: 76
fieldset: APBSMENR1
- name: APBSMENR2
description: RCC APB peripheral clock enable in Sleep/Stop mode register 2
byte_offset: 80
fieldset: APBSMENR2
- name: CCIPR
description: RCC peripherals independent clock configuration register
byte_offset: 84
fieldset: CCIPR
- name: CSR1
description: RCC control/status register 1
byte_offset: 92
fieldset: CSR1
- name: CSR2
description: RCC control/status register 2
byte_offset: 96
fieldset: CSR2
fieldset/AHBENR:
description: RCC AHB peripheral clock enable register
fields:
- name: DMA1EN
description: "DMA1 and DMAMUX clock enable\r Set and cleared by software.\r DMAMUX is enabled as long as at least one DMA peripheral is enabled."
bit_offset: 0
bit_size: 1
- name: FLASHEN
description: "Flash memory interface clock enable\r Set and cleared by software.\r This bit can only be cleared when the Flash memory is in power down mode."
bit_offset: 8
bit_size: 1
- name: CRCEN
description: "CRC clock enable\r Set and cleared by software."
bit_offset: 12
bit_size: 1
fieldset/AHBRSTR:
description: RCC AHB peripheral reset register
fields:
- name: DMA1RST
description: "DMA1 and DMAMUX reset\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: FLASHRST
description: "Flash memory interface reset\r Set and cleared by software.\r This bit can only be set when the Flash memory is in power down mode."
bit_offset: 8
bit_size: 1
- name: CRCRST
description: "CRC reset\r Set and cleared by software."
bit_offset: 12
bit_size: 1
fieldset/AHBSMENR:
description: RCC AHB peripheral clock enable in Sleep/Stop mode register
fields:
- name: DMA1SMEN
description: "DMA1 and DMAMUX clock enable during Sleep mode\r Set and cleared by software.\r Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral."
bit_offset: 0
bit_size: 1
- name: FLASHSMEN
description: "Flash memory interface clock enable during Sleep mode\r Set and cleared by software.\r This bit can be activated only when the Flash memory is in power down mode."
bit_offset: 8
bit_size: 1
- name: SRAMSMEN
description: "SRAM clock enable during Sleep mode\r Set and cleared by software."
bit_offset: 9
bit_size: 1
- name: CRCSMEN
description: "CRC clock enable during Sleep mode\r Set and cleared by software."
bit_offset: 12
bit_size: 1
fieldset/APBENR1:
description: RCC APB peripheral clock enable register 1
fields:
- name: TIM3EN
description: "TIM3 timer clock enable\r Set and cleared by software."
bit_offset: 1
bit_size: 1
- name: RTCAPBEN
description: "RTC APB clock enable\r Set and cleared by software."
bit_offset: 10
bit_size: 1
- name: WWDGEN
description: "WWDG clock enable\r Set by software to enable the window watchdog clock. Cleared by hardware system reset\r This bit can also be set by hardware if the WWDG_SW option bit is 0."
bit_offset: 11
bit_size: 1
- name: USART2EN
description: "USART2 clock enable\r Set and cleared by software."
bit_offset: 17
bit_size: 1
- name: I2C1EN
description: "I2C1 clock enable\r Set and cleared by software."
bit_offset: 21
bit_size: 1
- name: DBGEN
description: "Debug support clock enable\r Set and cleared by software."
bit_offset: 27
bit_size: 1
- name: PWREN
description: "Power interface clock enable\r Set and cleared by software."
bit_offset: 28
bit_size: 1
fieldset/APBENR2:
description: RCC APB peripheral clock enable register 2
fields:
- name: SYSCFGEN
description: "SYSCFG clock enable\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: TIM1EN
description: "TIM1 timer clock enable\r Set and cleared by software."
bit_offset: 11
bit_size: 1
- name: SPI1EN
description: "SPI1 clock enable\r Set and cleared by software."
bit_offset: 12
bit_size: 1
- name: USART1EN
description: "USART1 clock enable\r Set and cleared by software."
bit_offset: 14
bit_size: 1
- name: TIM14EN
description: "TIM14 timer clock enable\r Set and cleared by software."
bit_offset: 15
bit_size: 1
- name: TIM16EN
description: "TIM16 timer clock enable\r Set and cleared by software."
bit_offset: 17
bit_size: 1
- name: TIM17EN
description: "TIM16 timer clock enable\r Set and cleared by software."
bit_offset: 18
bit_size: 1
- name: ADCEN
description: "ADC clock enable\r Set and cleared by software."
bit_offset: 20
bit_size: 1
fieldset/APBRSTR1:
description: RCC APB peripheral reset register 1
fields:
- name: TIM3RST
description: "TIM3 timer reset\r Set and cleared by software."
bit_offset: 1
bit_size: 1
- name: USART2RST
description: "USART2 reset\r Set and cleared by software."
bit_offset: 17
bit_size: 1
- name: I2C1RST
description: "I2C1 reset\r Set and cleared by software."
bit_offset: 21
bit_size: 1
- name: DBGRST
description: "Debug support reset\r Set and cleared by software."
bit_offset: 27
bit_size: 1
- name: PWRRST
description: "Power interface reset\r Set and cleared by software."
bit_offset: 28
bit_size: 1
fieldset/APBRSTR2:
description: RCC APB peripheral reset register 2
fields:
- name: SYSCFGRST
description: "SYSCFG reset\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: TIM1RST
description: "TIM1 timer reset\r Set and cleared by software."
bit_offset: 11
bit_size: 1
- name: SPI1RST
description: "SPI1 reset\r Set and cleared by software."
bit_offset: 12
bit_size: 1
- name: USART1RST
description: "USART1 reset\r Set and cleared by software."
bit_offset: 14
bit_size: 1
- name: TIM14RST
description: "TIM14 timer reset\r Set and cleared by software."
bit_offset: 15
bit_size: 1
- name: TIM16RST
description: "TIM16 timer reset\r Set and cleared by software."
bit_offset: 17
bit_size: 1
- name: TIM17RST
description: "TIM16 timer reset\r Set and cleared by software."
bit_offset: 18
bit_size: 1
- name: ADCRST
description: "ADC reset\r Set and cleared by software."
bit_offset: 20
bit_size: 1
fieldset/APBSMENR1:
description: RCC APB peripheral clock enable in Sleep/Stop mode register 1
fields:
- name: TIM3SMEN
description: "TIM3 timer clock enable during Sleep mode\r Set and cleared by software."
bit_offset: 1
bit_size: 1
- name: RTCAPBSMEN
description: "RTC APB clock enable during Sleep mode\r Set and cleared by software."
bit_offset: 10
bit_size: 1
- name: WWDGSMEN
description: "WWDG clock enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 11
bit_size: 1
- name: USART2SMEN
description: "USART2 clock enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 17
bit_size: 1
- name: I2C1SMEN
description: "I2C1 clock enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 21
bit_size: 1
- name: DBGSMEN
description: "Debug support clock enable during Sleep mode\r Set and cleared by software."
bit_offset: 27
bit_size: 1
- name: PWRSMEN
description: "Power interface clock enable during Sleep mode\r Set and cleared by software."
bit_offset: 28
bit_size: 1
fieldset/APBSMENR2:
description: RCC APB peripheral clock enable in Sleep/Stop mode register 2
fields:
- name: SYSCFGSMEN
description: "SYSCFG clock enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: TIM1SMEN
description: "TIM1 timer clock enable during Sleep mode\r Set and cleared by software."
bit_offset: 11
bit_size: 1
- name: SPI1SMEN
description: "SPI1 clock enable during Sleep mode\r Set and cleared by software."
bit_offset: 12
bit_size: 1
- name: USART1SMEN
description: "USART1 clock enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 14
bit_size: 1
- name: TIM14SMEN
description: "TIM14 timer clock enable during Sleep mode\r Set and cleared by software."
bit_offset: 15
bit_size: 1
- name: TIM16SMEN
description: "TIM16 timer clock enable during Sleep mode\r Set and cleared by software."
bit_offset: 17
bit_size: 1
- name: TIM17SMEN
description: "TIM16 timer clock enable during Sleep mode\r Set and cleared by software."
bit_offset: 18
bit_size: 1
- name: ADCSMEN
description: "ADC clock enable during Sleep mode\r Set and cleared by software."
bit_offset: 20
bit_size: 1
fieldset/CCIPR:
description: RCC peripherals independent clock configuration register
fields:
- name: USART1SEL
description: "USART1 clock source selection\r This bitfield is controlled by software to select USART1 clock source as follows:"
bit_offset: 0
bit_size: 2
enum: USART1SEL
- name: I2C1SEL
description: "I2C1 clock source selection\r This bitfield is controlled by software to select I2C1 clock source as follows:"
bit_offset: 12
bit_size: 2
enum: I2C1SEL
- name: I2S1SEL
description: "I2S1 clock source selection\r This bitfield is controlled by software to select I2S1 clock source as follows:"
bit_offset: 14
bit_size: 2
enum: I2S1SEL
- name: ADCSEL
description: "ADCs clock source selection\r This bitfield is controlled by software to select the clock source for ADC:"
bit_offset: 30
bit_size: 2
enum: ADCSEL
fieldset/CFGR:
description: RCC clock configuration register
fields:
- name: SW
description: "System clock switch\r This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows:\r Others: Reserved\r The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, or Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected."
bit_offset: 0
bit_size: 3
enum: SW
- name: SWS
description: "System clock switch status\r This bitfield is controlled by hardware to indicate the clock source used as system clock:\r Others: Reserved"
bit_offset: 3
bit_size: 3
enum: SW
- name: HPRE
description: "AHB prescaler\r This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows:\r 0xxx: 1"
bit_offset: 8
bit_size: 4
enum: HPRE
- name: PPRE
description: "APB prescaler\r This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows:\r 0xx: 1"
bit_offset: 12
bit_size: 3
enum: PPRE
- name: MCO2SEL
description: "Microcontroller clock output 2 clock selector\r This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows:\r This bitfield is controlled by software. It sets the clock selector for MCO output as follows:\r Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching."
bit_offset: 16
bit_size: 4
enum: MCOSEL
- name: MCO2PRE
description: "Microcontroller clock output 2 prescaler\r This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows:\r ...\r It is highly recommended to set this field before the MCO2 output is enabled."
bit_offset: 20
bit_size: 4
enum: MCOPRE
- name: MCOSEL
description: "Microcontroller clock output clock selector\r This bitfield is controlled by software. It sets the clock selector for MCO output as follows:\r Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Any other value means no clock on MCO."
bit_offset: 24
bit_size: 4
enum: MCOSEL
- name: MCOPRE
description: "Microcontroller clock output prescaler\r This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows:\r ...\r It is highly recommended to set this field before the MCO output is enabled."
bit_offset: 28
bit_size: 4
enum: MCOPRE
fieldset/CICR:
description: RCC clock interrupt clear register
fields:
- name: LSIRDYC
description: "LSI ready interrupt clear\r This bit is set by software to clear the LSIRDYF flag."
bit_offset: 0
bit_size: 1
- name: LSERDYC
description: "LSE ready interrupt clear\r This bit is set by software to clear the LSERDYF flag."
bit_offset: 1
bit_size: 1
- name: HSIRDYC
description: "HSI16 ready interrupt clear\r This bit is set software to clear the HSIRDYF flag."
bit_offset: 3
bit_size: 1
- name: HSERDYC
description: "HSE ready interrupt clear\r This bit is set by software to clear the HSERDYF flag."
bit_offset: 4
bit_size: 1
- name: CSSC
description: "Clock security system interrupt clear\r This bit is set by software to clear the HSECSSF flag."
bit_offset: 8
bit_size: 1
- name: LSECSSC
description: "LSE Clock security system interrupt clear\r This bit is set by software to clear the LSECSSF flag."
bit_offset: 9
bit_size: 1
fieldset/CIER:
description: RCC clock interrupt enable register
fields:
- name: LSIRDYIE
description: "LSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization:"
bit_offset: 0
bit_size: 1
- name: LSERDYIE
description: "LSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization:"
bit_offset: 1
bit_size: 1
- name: HSIRDYIE
description: "HSI16 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization:"
bit_offset: 3
bit_size: 1
- name: HSERDYIE
description: "HSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization:"
bit_offset: 4
bit_size: 1
fieldset/CIFR:
description: RCC clock interrupt flag register
fields:
- name: LSIRDYF
description: "LSI ready interrupt flag\r This flag indicates a pending interrupt upon LSE clock getting ready.\r Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.\r Cleared by software setting the LSIRDYC bit."
bit_offset: 0
bit_size: 1
- name: LSERDYF
description: "LSE ready interrupt flag\r This flag indicates a pending interrupt upon LSE clock getting ready.\r Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.\r Cleared by software setting the LSERDYC bit."
bit_offset: 1
bit_size: 1
- name: HSIRDYF
description: "HSI16 ready interrupt flag\r This flag indicates a pending interrupt upon HSI16 clock getting ready.\r Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in response to setting the HSION (refer to ). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Cleared by software setting the HSIRDYC bit."
bit_offset: 3
bit_size: 1
- name: HSERDYF
description: "HSE ready interrupt flag\r This flag indicates a pending interrupt upon HSE clock getting ready.\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set.\r Cleared by software setting the HSERDYC bit."
bit_offset: 4
bit_size: 1
- name: CSSF
description: "HSE clock security system interrupt flag\r This flag indicates a pending interrupt upon HSE clock failure.\r Set by hardware when a failure is detected in the HSE oscillator.\r Cleared by software setting the CSSC bit."
bit_offset: 8
bit_size: 1
- name: LSECSSF
description: "LSE clock security system interrupt flag\r This flag indicates a pending interrupt upon LSE clock failure.\r Set by hardware when a failure is detected in the LSE oscillator.\r Cleared by software by setting the LSECSSC bit."
bit_offset: 9
bit_size: 1
fieldset/CR:
description: RCC clock control register
fields:
- name: SYSDIV
description: "System clock division factor\r This bitfield controlled by software sets the division factor of the system clock divider to produce SYSCLK clock:"
bit_offset: 2
bit_size: 3
enum: SYSDIV
- name: HSIKERDIV
description: "HSI48 kernel clock division factor\r This bitfield controlled by software sets the division factor of the kernel clock divider to produce HSIKER clock:"
bit_offset: 5
bit_size: 3
enum: HSIKERDIV
- name: HSION
description: "HSI48 clock enable\r Set and cleared by software and hardware, with hardware taking priority.\r Kept low by hardware as long as the device is in a low-power mode.\r Kept high by hardware as long as the system is clocked with a clock derived from HSI48. This includes the exit from low-power modes and the system clock fall-back to HSI48 upon failing HSE oscillator clock selected as system clock source."
bit_offset: 8
bit_size: 1
- name: HSIKERON
description: "HSI48 always-enable for peripheral kernels.\r Set and cleared by software.\r Setting the bit activates the HSI48 oscillator in Run and Stop modes, regardless of the HSION bit state. The HSI48 clock can only feed USART1, USART2, and I2C1 peripherals configured with HSI48 as kernel clock.\r Note: Keeping the HSI48 active in Stop mode allows speeding up the serial interface communication as the HSI48 clock is ready immediately upon exiting Stop mode."
bit_offset: 9
bit_size: 1
- name: HSIRDY
description: "HSI48 clock ready flag\r Set by hardware when the HSI48 oscillator is enabled through HSION and ready to use (stable).\r Note: Upon clearing HSION, HSIRDY goes low after six HSI48 clock cycles."
bit_offset: 10
bit_size: 1
- name: HSIDIV
description: "HSI48 clock division factor\r This bitfield controlled by software sets the division factor of the HSI48 clock divider to produce HSISYS clock:"
bit_offset: 11
bit_size: 3
enum: HSIDIV
- name: HSEON
description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE oscillator when entering Stop, or Standby, or Shutdown mode. This bit cannot be cleared if the HSE oscillator is used directly or indirectly as the system clock."
bit_offset: 16
bit_size: 1
- name: HSERDY
description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable and ready for use.\r Note: Upon clearing HSEON, HSERDY goes low after six HSE clock cycles."
bit_offset: 17
bit_size: 1
- name: HSEBYP
description: "HSE crystal oscillator bypass\r Set and cleared by software.\r When the bit is set, the internal HSE oscillator is bypassed for use of an external clock. The external clock must then be enabled with the HSEON bit set. Write access to the bit is only effective when the HSE oscillator is disabled."
bit_offset: 18
bit_size: 1
- name: CSSON
description: "Clock security system enable\r Set by software to enable the clock security system. When the bit is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. The bit is cleared by hardware upon reset."
bit_offset: 19
bit_size: 1
fieldset/CSR1:
description: RCC control/status register 1
fields:
- name: LSEON
description: "LSE oscillator enable\r Set and cleared by software to enable LSE oscillator:"
bit_offset: 0
bit_size: 1
- name: LSERDY
description: "LSE oscillator ready\r Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable):\r After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles."
bit_offset: 1
bit_size: 1
- name: LSEBYP
description: "LSE oscillator bypass\r Set and cleared by software to bypass the LSE oscillator (in debug mode).\r This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0)."
bit_offset: 2
bit_size: 1
- name: LSEDRV
description: "LSE oscillator drive capability\r Set by software to select the LSE oscillator drive capability as follows:\r Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode."
bit_offset: 3
bit_size: 2
enum: LSEDRV
- name: LSECSSON
description: "CSS on LSE enable\r Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows:\r LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD\r =1). In that case the software must disable the LSECSSON bit."
bit_offset: 5
bit_size: 1
- name: LSECSSD
description: "CSS on LSE failure Detection\r Set by hardware to indicate when a failure is detected by the clock security system\r on the external 32 kHz oscillator (LSE):"
bit_offset: 6
bit_size: 1
- name: RTCSEL
description: "RTC clock source selection\r Set by software to select the clock source for the RTC as follows:\r Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The RTCRST bit can be used to reset this bitfield to 00."
bit_offset: 8
bit_size: 2
enum: RTCSEL
- name: RTCEN
description: "RTC clock enable\r Set and cleared by software. The bit enables clock to RTC and TAMP."
bit_offset: 15
bit_size: 1
- name: RTCRST
description: "RTC domain software reset\r Set and cleared by software to reset the RTC domain:"
bit_offset: 16
bit_size: 1
- name: LSCOEN
description: "Low-speed clock output (LSCO) enable\r Set and cleared by software."
bit_offset: 24
bit_size: 1
- name: LSCOSEL
description: "Low-speed clock output selection\r Set and cleared by software to select the low-speed output clock:"
bit_offset: 25
bit_size: 1
enum: LSCOSEL
fieldset/CSR2:
description: RCC control/status register 2
fields:
- name: LSION
description: "LSI oscillator enable\r Set and cleared by software to enable/disable the LSI oscillator:"
bit_offset: 0
bit_size: 1
- name: LSIRDY
description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is ready (stable):\r After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC."
bit_offset: 1
bit_size: 1
- name: RMVF
description: "Remove reset flags\r Set by software to clear the reset flags."
bit_offset: 23
bit_size: 1
- name: OBLRSTF
description: "Option byte loader reset flag\r Set by hardware when a reset from the Option byte loading occurs.\r Cleared by setting the RMVF bit."
bit_offset: 25
bit_size: 1
- name: PINRSTF
description: "Pin reset flag\r Set by hardware when a reset from the NRST pin occurs.\r Cleared by setting the RMVF bit."
bit_offset: 26
bit_size: 1
- name: PWRRSTF
description: "BOR or POR/PDR flag\r Set by hardware when a BOR or POR/PDR occurs.\r Cleared by setting the RMVF bit."
bit_offset: 27
bit_size: 1
- name: SFTRSTF
description: "Software reset flag\r Set by hardware when a software reset occurs.\r Cleared by setting the RMVF bit."
bit_offset: 28
bit_size: 1
- name: IWDGRSTF
description: "Independent window watchdog reset flag\r Set by hardware when an independent watchdog reset domain occurs.\r Cleared by setting the RMVF bit."
bit_offset: 29
bit_size: 1
- name: WWDGRSTF
description: "Window watchdog reset flag\r Set by hardware when a window watchdog reset occurs.\r Cleared by setting the RMVF bit."
bit_offset: 30
bit_size: 1
- name: LPWRRSTF
description: "Low-power reset flag\r Set by hardware when a reset occurs due to illegal Stop, or Standby, or Shutdown mode entry.\r Cleared by setting the RMVF bit.\r This operates only if nRST_STOP, or nRST_STDBY or nRST_SHDW option bits are cleared."
bit_offset: 31
bit_size: 1
fieldset/ICSCR:
description: RCC internal clock source calibration register
fields:
- name: HSICAL
description: "HSI48 clock calibration\r This bitfield directly acts on the HSI48 clock frequency. Its value is a sum of an internal factory-programmed number and the value of the HSITRIM[6:0] bitfield. In the factory, the internal number is set to calibrate the HSI48 clock frequency to 48 MHz (with HSITRIM[6:0] left at its reset value). Refer to the device datasheet for HSI48 calibration accuracy and for the frequency trimming granularity.\r Note: The trimming effect presents discontinuities at HSICAL[7:0] multiples of 64."
bit_offset: 0
bit_size: 8
- name: HSITRIM
description: "HSI48 clock trimming\r The value of this bitfield contributes to the HSICAL[7:0] bitfield value.\r It allows HSI48 clock frequency user trimming.\r The HSI48 frequency accuracy as stated in the device datasheet applies when this bitfield is left at its reset value."
bit_offset: 8
bit_size: 7
fieldset/GPIOENR:
description: RCC I/O port clock enable register
fields:
- name: GPIOAEN
description: "I/O port A clock enable\r This bit is set and cleared by software."
bit_offset: 0
bit_size: 1
- name: GPIOBEN
description: "I/O port B clock enable\r This bit is set and cleared by software."
bit_offset: 1
bit_size: 1
- name: GPIOCEN
description: "I/O port C clock enable\r This bit is set and cleared by software."
bit_offset: 2
bit_size: 1
- name: GPIODEN
description: "I/O port D clock enable\r This bit is set and cleared by software."
bit_offset: 3
bit_size: 1
- name: GPIOFEN
description: "I/O port F clock enable\r This bit is set and cleared by software."
bit_offset: 5
bit_size: 1
fieldset/GPIORSTR:
description: RCC I/O port reset register
fields:
- name: GPIOARST
description: "I/O port A reset\r This bit is set and cleared by software."
bit_offset: 0
bit_size: 1
- name: GPIOBRST
description: "I/O port B reset\r This bit is set and cleared by software."
bit_offset: 1
bit_size: 1
- name: GPIOCRST
description: "I/O port C reset\r This bit is set and cleared by software."
bit_offset: 2
bit_size: 1
- name: GPIODRST
description: "I/O port D reset\r This bit is set and cleared by software."
bit_offset: 3
bit_size: 1
- name: GPIOFRST
description: "I/O port F reset\r This bit is set and cleared by software."
bit_offset: 5
bit_size: 1
fieldset/GPIOSMENR:
description: RCC I/O port in Sleep mode clock enable register
fields:
- name: GPIOASMEN
description: "I/O port A clock enable during Sleep mode\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: GPIOBSMEN
description: "I/O port B clock enable during Sleep mode\r Set and cleared by software."
bit_offset: 1
bit_size: 1
- name: GPIOCSMEN
description: "I/O port C clock enable during Sleep mode\r Set and cleared by software."
bit_offset: 2
bit_size: 1
- name: GPIODSMEN
description: "I/O port D clock enable during Sleep mode\r Set and cleared by software."
bit_offset: 3
bit_size: 1
- name: GPIOFSMEN
description: "I/O port F clock enable during Sleep mode\r Set and cleared by software."
bit_offset: 5
bit_size: 1
enum/ADCSEL:
bit_size: 2
variants:
- name: SYSCLK
description: System clock
value: 0
- name: HSIKER
description: HSIKER
value: 2
enum/HPRE:
bit_size: 4
variants:
- name: Div1
description: SYSCLK not divided
value: 0
- name: Div2
description: SYSCLK is divided by 2
value: 8
- name: Div4
description: SYSCLK is divided by 4
value: 9
- name: Div8
description: SYSCLK is divided by 8
value: 10
- name: Div16
description: SYSCLK is divided by 16
value: 11
- name: Div64
description: SYSCLK is divided by 64
value: 12
- name: Div128
description: SYSCLK is divided by 128
value: 13
- name: Div256
description: SYSCLK is divided by 256
value: 14
- name: Div512
description: SYSCLK is divided by 512
value: 15
enum/HSIDIV:
bit_size: 3
variants:
- name: Div1
description: HSI clock is not divided
value: 0
- name: Div2
description: HSI clock is divided by 2
value: 1
- name: Div4
description: HSI clock is divided by 4
value: 2
- name: Div8
description: HSI clock is divided by 8
value: 3
- name: Div16
description: HSI clock is divided by 16
value: 4
- name: Div32
description: HSI clock is divided by 32
value: 5
- name: Div64
description: HSI clock is divided by 64
value: 6
- name: Div128
description: HSI clock is divided by 128
value: 7
enum/HSIKERDIV:
bit_size: 3
variants:
- name: Div1
description: "1"
value: 0
- name: Div2
description: "2"
value: 1
- name: Div3
description: 3 (reset value)
value: 2
- name: Div4
description: "4"
value: 3
- name: Div5
description: "5"
value: 4
- name: Div6
description: "6"
value: 5
- name: Div7
description: "7"
value: 6
- name: Div8
description: "8"
value: 7
enum/I2C1SEL:
bit_size: 2
variants:
- name: PCLK
description: PCLK
value: 0
- name: SYSCLK
description: SYSCLK
value: 1
- name: HSIKER
description: HSIKER
value: 2
enum/I2S1SEL:
bit_size: 2
variants:
- name: SYSCLK
description: SYSCLK
value: 0
- name: HSIKER
description: HSIKER
value: 2
- name: I2S_CKIN
description: I2S_CKIN
value: 3
enum/LSCOSEL:
bit_size: 1
variants:
- name: LSI
description: LSI
value: 0
- name: LSE
description: LSE
value: 1
enum/LSEDRV:
bit_size: 2
variants:
- name: Low
description: Low driving capability
value: 0
- name: MediumLow
description: Medium low driving capability
value: 1
- name: MediumHigh
description: Medium high driving capability
value: 2
- name: High
description: High driving capability
value: 3
enum/MCOPRE:
bit_size: 4
variants:
- name: Div1
description: MCO2 not divided
value: 0
- name: Div2
description: MCO clock is divided by 2
value: 1
- name: Div4
description: MCO clock is divided by 4
value: 2
- name: Div8
description: MCO clock is divided by 8
value: 3
- name: Div16
description: MCO clock is divided divided by 16
value: 4
- name: Div32
description: MCO clock is divided divided by 32
value: 5
- name: Div64
description: MCO clock is divided divided by 64
value: 6
- name: Div128
description: MCO clock is divided divided by 128
value: 7
enum/MCOSEL:
bit_size: 4
variants:
- name: NoClock
description: "No clock, MCO output disabled"
value: 0
- name: SYSCLK
description: SYSCLK selected as MCO source
value: 1
- name: HSI48
description: HSI48 selected as MCO source
value: 3
- name: HSE
description: HSE selected as MCO source
value: 4
- name: LSI
description: LSI selected as MCO source
value: 6
- name: LSE
description: LSE selected as MCO source
value: 7
enum/PPRE:
bit_size: 3
variants:
- name: Div1
description: HCLK not divided
value: 0
- name: Div2
description: HCLK is divided by 2
value: 4
- name: Div4
description: HCLK is divided by 4
value: 5
- name: Div8
description: HCLK is divided by 8
value: 6
- name: Div16
description: HCLK is divided by 16
value: 7
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
description: No clock used as RTC clock
value: 0
- name: LSE
description: LSE used as RTC clock
value: 1
- name: LSI
description: LSI used as RTC clock
value: 2
- name: HSE_Div32
description: HSE divided by 32 used as RTC clock
value: 3
enum/SW:
bit_size: 3
variants:
- name: HSI
description: HSI selected as system clock
value: 0
- name: HSE
description: HSE selected as system clock
value: 1
- name: LSI
description: LSI selected as system clock
value: 3
- name: LSE
description: LSE selected as system clock
value: 4
enum/SYSDIV:
bit_size: 3
variants:
- name: Div1
description: "1"
value: 0
- name: Div2
description: "2"
value: 1
- name: Div3
description: 3 (reset value)
value: 2
- name: Div4
description: "4"
value: 3
- name: Div5
description: "5"
value: 4
- name: Div6
description: "6"
value: 5
- name: Div7
description: "7"
value: 6
- name: Div8
description: "8"
value: 7
enum/USART1SEL:
bit_size: 2
variants:
- name: PCLK
description: PCLK
value: 0
- name: SYSCLK
description: SYSCLK
value: 1
- name: HSIKER
description: HSIKER
value: 2
- name: LSE
description: LSE
value: 3

516
data/registers/syscfg_c0.yaml Normal file
View File

@ -0,0 +1,516 @@
---
block/SYSCFG:
description: register block
items:
- name: CFGR1
description: configuration register 1
byte_offset: 0
fieldset: CFGR1
- name: CFGR2
description: configuration register 2
byte_offset: 24
fieldset: CFGR2
- name: CFGR3
description: configuration register 3
byte_offset: 60
fieldset: CFGR3
- name: ITLINE0
description: interrupt line 0 status register
byte_offset: 128
access: Read
fieldset: ITLINE0
- name: ITLINE2
description: interrupt line 2 status register
byte_offset: 136
access: Read
fieldset: ITLINE2
- name: ITLINE3
description: interrupt line 3 status register
byte_offset: 140
access: Read
fieldset: ITLINE3
- name: ITLINE4
description: interrupt line 4 status register
byte_offset: 144
access: Read
fieldset: ITLINE4
- name: ITLINE5
description: interrupt line 5 status register
byte_offset: 148
access: Read
fieldset: ITLINE5
- name: ITLINE6
description: interrupt line 6 status register
byte_offset: 152
access: Read
fieldset: ITLINE6
- name: ITLINE7
description: interrupt line 7 status register
byte_offset: 156
access: Read
fieldset: ITLINE7
- name: ITLINE9
description: interrupt line 9 status register
byte_offset: 164
access: Read
fieldset: ITLINE9
- name: ITLINE10
description: interrupt line 10 status register
byte_offset: 168
access: Read
fieldset: ITLINE10
- name: ITLINE11
description: interrupt line 11 status register
byte_offset: 172
access: Read
fieldset: ITLINE11
- name: ITLINE12
description: interrupt line 12 status register
byte_offset: 176
access: Read
fieldset: ITLINE12
- name: ITLINE13
description: interrupt line 13 status register
byte_offset: 180
access: Read
fieldset: ITLINE13
- name: ITLINE14
description: interrupt line 14 status register
byte_offset: 184
access: Read
fieldset: ITLINE14
- name: ITLINE16
description: interrupt line 16 status register
byte_offset: 192
access: Read
fieldset: ITLINE16
- name: ITLINE19
description: interrupt line 19 status register
byte_offset: 204
access: Read
fieldset: ITLINE19
- name: ITLINE21
description: interrupt line 21 status register
byte_offset: 212
access: Read
fieldset: ITLINE21
- name: ITLINE22
description: interrupt line 22 status register
byte_offset: 216
access: Read
fieldset: ITLINE22
- name: ITLINE23
description: interrupt line 23 status register
byte_offset: 220
access: Read
fieldset: ITLINE23
- name: ITLINE25
description: interrupt line 25 status register
byte_offset: 228
access: Read
fieldset: ITLINE25
- name: ITLINE27
description: interrupt line 27 status register
byte_offset: 236
access: Read
fieldset: ITLINE27
- name: ITLINE28
description: interrupt line 28 status register
byte_offset: 240
access: Read
fieldset: ITLINE28
fieldset/CFGR1:
description: configuration register 1
fields:
- name: MEM_MODE
description: "Memory mapping selection bits\r This bitfield controlled by software selects the memory internally mapped at the address 0x0000 0000. Its reset value is determined by the boot mode configuration. Refer to for more details.\r x0: Main Flash memory"
bit_offset: 0
bit_size: 2
enum: MEM_MODE
- name: PA11_RMP
description: "PA11 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port."
bit_offset: 3
bit_size: 1
- name: PA12_RMP
description: "PA12 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port."
bit_offset: 4
bit_size: 1
- name: IR_POL
description: IR output polarity selection
bit_offset: 5
bit_size: 1
- name: IR_MOD
description: "IR Modulation Envelope signal selection\r This bitfield selects the signal for IR modulation envelope:"
bit_offset: 6
bit_size: 2
enum: IR_MOD
- name: I2C_PB6_FMP
description: "Fast Mode Plus (FM+) enable for PB6\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
bit_offset: 16
bit_size: 1
- name: I2C_PB7_FMP
description: "Fast Mode Plus (FM+) enable for PB7\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
bit_offset: 17
bit_size: 1
- name: I2C_PB8_FMP
description: "Fast Mode Plus (FM+) enable for PB8\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
bit_offset: 18
bit_size: 1
- name: I2C_PB9_FMP
description: "Fast Mode Plus (FM+) enable for PB9\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
bit_offset: 19
bit_size: 1
- name: I2C1_FMP
description: "Fast Mode Plus (FM+) enable for I2C1\r This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports configured as I2C1 through GPIOx_AFR registers.\r With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C1 can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the speed control is ignored."
bit_offset: 20
bit_size: 1
- name: I2C_PA9_FMP
description: "Fast Mode Plus (FM+) enable for PA9\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
bit_offset: 22
bit_size: 1
- name: I2C_PA10_FMP
description: "Fast Mode Plus (FM+) enable for PA10\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
bit_offset: 23
bit_size: 1
- name: I2C_PC14_FMP
description: "Fast Mode Plus (FM+) enable for PC14\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PC14 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
bit_offset: 24
bit_size: 1
fieldset/CFGR2:
description: configuration register 2
fields:
- name: LOCKUP_LOCK
description: "Cortex<Superscript><3E><Default <20> Font>-M0+ LOCKUP enable\r This bit is set by software and cleared by system reset. When set, it enables the connection of Cortex<Superscript><3E><Default <20> Font>-M0+ LOCKUP (HardFault) output to the TIM1/16/17 Break input."
bit_offset: 0
bit_size: 1
fieldset/CFGR3:
description: configuration register 3
fields:
- name: PINMUX0
description: "Pin GPIO multiplexer 0\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved\r Pin F2 of WLCSP14 package GPIO assignment\r 1x: Reserved"
bit_offset: 0
bit_size: 2
enum: PINMUX0
- name: PINMUX1
description: "Pin GPIO multiplexer 1\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved"
bit_offset: 2
bit_size: 2
enum: PINMUX1
- name: PINMUX2
description: "Pin GPIO multiplexer 2\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved\r 1x: Reserved"
bit_offset: 4
bit_size: 2
enum: PINMUX2
- name: PINMUX3
description: "Pin GPIO multiplexer 3\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved"
bit_offset: 6
bit_size: 2
enum: PINMUX3
- name: PINMUX4
description: "Pin GPIO multiplexer 4\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved\r 1x: Reserved"
bit_offset: 8
bit_size: 2
enum: PINMUX4
- name: PINMUX5
description: "Pin GPIO multiplexer 5\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved"
bit_offset: 10
bit_size: 2
enum: PINMUX5
fieldset/ITLINE0:
description: interrupt line 0 status register
fields:
- name: WWDG
description: Window watchdog interrupt pending flag
bit_offset: 0
bit_size: 1
fieldset/ITLINE10:
description: interrupt line 10 status register
fields:
- name: DMA1_CH2
description: DMA1 channel 2 interrupt request pending
bit_offset: 0
bit_size: 1
- name: DMA1_CH3
description: DMA1 channel 3 interrupt request pending
bit_offset: 1
bit_size: 1
fieldset/ITLINE11:
description: interrupt line 11 status register
fields:
- name: DMAMUX
description: DMAMUX interrupt request pending
bit_offset: 0
bit_size: 1
fieldset/ITLINE12:
description: interrupt line 12 status register
fields:
- name: ADC
description: ADC interrupt request pending
bit_offset: 0
bit_size: 1
fieldset/ITLINE13:
description: interrupt line 13 status register
fields:
- name: TIM1_CCU
description: Timer 1 commutation interrupt request pending
bit_offset: 0
bit_size: 1
- name: TIM1_TRG
description: Timer 1 trigger interrupt request pending
bit_offset: 1
bit_size: 1
- name: TIM1_UPD
description: Timer 1 update interrupt request pending
bit_offset: 2
bit_size: 1
- name: TIM1_BRK
description: Timer 1 break interrupt request pending
bit_offset: 3
bit_size: 1
fieldset/ITLINE14:
description: interrupt line 14 status register
fields:
- name: TIM1_CC
description: Timer 1 capture compare interrupt request pending
bit_offset: 0
bit_size: 1
fieldset/ITLINE16:
description: interrupt line 16 status register
fields:
- name: TIM3
description: Timer 3 interrupt request pending
bit_offset: 0
bit_size: 1
fieldset/ITLINE19:
description: interrupt line 19 status register
fields:
- name: TIM14
description: Timer 14 interrupt request pending
bit_offset: 0
bit_size: 1
fieldset/ITLINE2:
description: interrupt line 2 status register
fields:
- name: RTC
description: RTC interrupt request pending (EXTI line 19)
bit_offset: 1
bit_size: 1
fieldset/ITLINE21:
description: interrupt line 21 status register
fields:
- name: TIM16
description: Timer 16 interrupt request pending
bit_offset: 0
bit_size: 1
fieldset/ITLINE22:
description: interrupt line 22 status register
fields:
- name: TIM17
description: Timer 17 interrupt request pending
bit_offset: 0
bit_size: 1
fieldset/ITLINE23:
description: interrupt line 23 status register
fields:
- name: I2C1
description: "I2C1 interrupt request pending, combined with EXTI line 23"
bit_offset: 0
bit_size: 1
fieldset/ITLINE25:
description: interrupt line 25 status register
fields:
- name: SPI1
description: SPI1 interrupt request pending
bit_offset: 0
bit_size: 1
fieldset/ITLINE27:
description: interrupt line 27 status register
fields:
- name: USART1
description: "USART1 interrupt request pending, combined with EXTI line 25"
bit_offset: 0
bit_size: 1
fieldset/ITLINE28:
description: interrupt line 28 status register
fields:
- name: USART2
description: USART2 interrupt request pending (EXTI line 26)
bit_offset: 0
bit_size: 1
fieldset/ITLINE3:
description: interrupt line 3 status register
fields:
- name: FLASH_ITF
description: Flash interface interrupt request pending
bit_offset: 1
bit_size: 1
fieldset/ITLINE4:
description: interrupt line 4 status register
fields:
- name: RCC
description: Reset and clock control interrupt request pending
bit_offset: 0
bit_size: 1
fieldset/ITLINE5:
description: interrupt line 5 status register
fields:
- name: EXTI
description: EXTI
bit_offset: 0
bit_size: 1
array:
len: 2
stride: 1
fieldset/ITLINE6:
description: interrupt line 6 status register
fields:
- name: EXTI
description: EXTI
bit_offset: 0
bit_size: 1
array:
len: 2
stride: 1
fieldset/ITLINE7:
description: interrupt line 7 status register
fields:
- name: EXTI
description: EXTI
bit_offset: 0
bit_size: 1
array:
len: 12
stride: 1
fieldset/ITLINE9:
description: interrupt line 9 status register
fields:
- name: DMA1_CH1
description: DMA1 channel 1interrupt request pending
bit_offset: 0
bit_size: 1
enum/IR_MOD:
bit_size: 2
variants:
- name: TIM16
description: TIM16
value: 0
- name: USART1
description: USART1
value: 1
- name: USART2
description: USART2
value: 2
enum/MEM_MODE:
bit_size: 2
variants:
- name: FLASH
description: System Flash memory
value: 1
- name: SRAM
description: Embedded SRAM
value: 3
enum/PINMUX0:
bit_size: 2
variants:
- name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1
description: PB7
value: 0
- name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_F2
description: PA1
value: 0
- name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1
description: PC14
value: 1
- name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_F2
description: PA2
value: 1
enum/PINMUX1:
bit_size: 2
variants:
- name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4
description: PF2
value: 0
- name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G3
description: PF2
value: 0
- name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4
description: PA0
value: 1
- name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G3
description: PA0
value: 1
- name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4
description: PA1
value: 2
- name: B_0x3_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4
description: PA2
value: 3
enum/PINMUX2:
bit_size: 2
variants:
- name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5
description: PA8
value: 0
- name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J1
description: PA8
value: 0
- name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5
description: PA11
value: 1
- name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J1
description: PA11
value: 1
enum/PINMUX3:
bit_size: 2
variants:
- name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8
description: PA14
value: 0
- name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_H2
description: PA5
value: 0
- name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8
description: PB6
value: 1
- name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_H2
description: PA6
value: 1
- name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8
description: PC15
value: 2
enum/PINMUX4:
bit_size: 2
variants:
- name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2
description: PA7
value: 0
- name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G1
description: PA7
value: 0
- name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2
description: PA12
value: 1
- name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G1
description: PA12
value: 1
enum/PINMUX5:
bit_size: 2
variants:
- name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1
description: PA3
value: 0
- name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J3
description: PA3
value: 0
- name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1
description: PA4
value: 1
- name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J3
description: PA4
value: 1
- name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1
description: PA5
value: 2
- name: B_0x3_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1
description: PA6
value: 3

44
src/chips.rs
View File

@ -77,7 +77,7 @@ fn chip_name_from_package_name(x: &str) -> String {
(regex!("^(STM32L1....).x([AX])$"), "$1-$2"), (regex!("^(STM32L1....).x([AX])$"), "$1-$2"),
(regex!("^(STM32G0....).xN$"), "$1"), (regex!("^(STM32G0....).xN$"), "$1"),
(regex!("^(STM32F412..).xP$"), "$1"), (regex!("^(STM32F412..).xP$"), "$1"),
(regex!("^(STM32L4....).xP$"), "$1"), (regex!("^(STM32L4....).x[PS]$"), "$1"),
(regex!("^(STM32WB....).x[AE]$"), "$1"), (regex!("^(STM32WB....).x[AE]$"), "$1"),
(regex!("^(STM32G0....).xN$"), "$1"), (regex!("^(STM32G0....).xN$"), "$1"),
(regex!("^(STM32L5....).x[PQ]$"), "$1"), (regex!("^(STM32L5....).x[PQ]$"), "$1"),
@ -163,6 +163,7 @@ impl PeriMatcher {
("STM32H7.*:ADC_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")), ("STM32H7.*:ADC_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")),
("STM32H7.*:ADC3_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")), ("STM32H7.*:ADC3_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")),
(".*:DCMI:.*", ("dcmi", "v1", "DCMI")), (".*:DCMI:.*", ("dcmi", "v1", "DCMI")),
("STM32C0.*:SYSCFG:.*", ("syscfg", "c0", "SYSCFG")),
("STM32F0.*:SYSCFG:.*", ("syscfg", "f0", "SYSCFG")), ("STM32F0.*:SYSCFG:.*", ("syscfg", "f0", "SYSCFG")),
("STM32F2.*:SYSCFG:.*", ("syscfg", "f2", "SYSCFG")), ("STM32F2.*:SYSCFG:.*", ("syscfg", "f2", "SYSCFG")),
("STM32F3.*:SYSCFG:.*", ("syscfg", "f3", "SYSCFG")), ("STM32F3.*:SYSCFG:.*", ("syscfg", "f3", "SYSCFG")),
@ -220,6 +221,7 @@ impl PeriMatcher {
// # USB OTG // # USB OTG
(".*:USB_OTG_FS:otgfs1_.*", ("otg", "v1", "OTG")), (".*:USB_OTG_FS:otgfs1_.*", ("otg", "v1", "OTG")),
(".*:USB_OTG_HS:otghs1_.*", ("otg", "v1", "OTG")), (".*:USB_OTG_HS:otghs1_.*", ("otg", "v1", "OTG")),
("STM32C0.*:RCC:.*", ("rcc", "c0", "RCC")),
("STM32F0.*:RCC:.*", ("rcc", "f0", "RCC")), ("STM32F0.*:RCC:.*", ("rcc", "f0", "RCC")),
("STM32F100.*:RCC:.*", ("rcc", "f100", "RCC")), ("STM32F100.*:RCC:.*", ("rcc", "f100", "RCC")),
("STM32F10[123].*:RCC:.*", ("rcc", "f1", "RCC")), ("STM32F10[123].*:RCC:.*", ("rcc", "f1", "RCC")),
@ -245,6 +247,7 @@ impl PeriMatcher {
("STM32F3.*:SPI[1234]:.*", ("spi", "v2", "SPI")), ("STM32F3.*:SPI[1234]:.*", ("spi", "v2", "SPI")),
("STM32F1.*:AFIO:.*", ("afio", "f1", "AFIO")), ("STM32F1.*:AFIO:.*", ("afio", "f1", "AFIO")),
("STM32L5.*:EXTI:.*", ("exti", "l5", "EXTI")), ("STM32L5.*:EXTI:.*", ("exti", "l5", "EXTI")),
("STM32C0.*:EXTI:.*", ("exti", "c0", "EXTI")),
("STM32G0.*:EXTI:.*", ("exti", "g0", "EXTI")), ("STM32G0.*:EXTI:.*", ("exti", "g0", "EXTI")),
("STM32H7.*:EXTI:.*", ("exti", "h7", "EXTI")), ("STM32H7.*:EXTI:.*", ("exti", "h7", "EXTI")),
("STM32U5.*:EXTI:.*", ("exti", "u5", "EXTI")), ("STM32U5.*:EXTI:.*", ("exti", "u5", "EXTI")),
@ -254,6 +257,7 @@ impl PeriMatcher {
(".*:EXTI:.*", ("exti", "v1", "EXTI")), (".*:EXTI:.*", ("exti", "v1", "EXTI")),
("STM32L0.*:CRS:.*", ("crs", "l0", "CRS")), ("STM32L0.*:CRS:.*", ("crs", "l0", "CRS")),
(".*SDMMC:sdmmc2_v1_0", ("sdmmc", "v2", "SDMMC")), (".*SDMMC:sdmmc2_v1_0", ("sdmmc", "v2", "SDMMC")),
("STM32C0.*:PWR:.*", ("pwr", "c0", "PWR")),
("STM32G0.*:PWR:.*", ("pwr", "g0", "PWR")), ("STM32G0.*:PWR:.*", ("pwr", "g0", "PWR")),
("STM32G4.*:PWR:.*", ("pwr", "g4", "PWR")), ("STM32G4.*:PWR:.*", ("pwr", "g4", "PWR")),
("STM32H7(42|43|53|50).*:PWR:.*", ("pwr", "h7", "PWR")), ("STM32H7(42|43|53|50).*:PWR:.*", ("pwr", "h7", "PWR")),
@ -282,6 +286,7 @@ impl PeriMatcher {
("STM32U5.*:FLASH:.*", ("flash", "u5", "FLASH")), ("STM32U5.*:FLASH:.*", ("flash", "u5", "FLASH")),
("STM32WB.*:FLASH:.*", ("flash", "wb", "FLASH")), ("STM32WB.*:FLASH:.*", ("flash", "wb", "FLASH")),
("STM32WL.*:FLASH:.*", ("flash", "wl", "FLASH")), ("STM32WL.*:FLASH:.*", ("flash", "wl", "FLASH")),
("STM32C0.*:FLASH:.*", ("flash", "c0", "FLASH")),
("STM32G0.*:FLASH:.*", ("flash", "g0", "FLASH")), ("STM32G0.*:FLASH:.*", ("flash", "g0", "FLASH")),
("STM32F107.*:ETH:.*", ("eth", "v1a", "ETH")), ("STM32F107.*:ETH:.*", ("eth", "v1a", "ETH")),
("STM32F[24].*:ETH:.*", ("eth", "v1b", "ETH")), ("STM32F[24].*:ETH:.*", ("eth", "v1b", "ETH")),
@ -305,6 +310,7 @@ impl PeriMatcher {
("STM32F3.*:DBGMCU:.*", ("dbgmcu", "f3", "DBGMCU")), ("STM32F3.*:DBGMCU:.*", ("dbgmcu", "f3", "DBGMCU")),
("STM32F4.*:DBGMCU:.*", ("dbgmcu", "f4", "DBGMCU")), ("STM32F4.*:DBGMCU:.*", ("dbgmcu", "f4", "DBGMCU")),
("STM32F7.*:DBGMCU:.*", ("dbgmcu", "f7", "DBGMCU")), ("STM32F7.*:DBGMCU:.*", ("dbgmcu", "f7", "DBGMCU")),
("STM32C0.*:DBGMCU:.*", ("dbgmcu", "c0", "DBGMCU")),
("STM32G0.*:DBGMCU:.*", ("dbgmcu", "g0", "DBGMCU")), ("STM32G0.*:DBGMCU:.*", ("dbgmcu", "g0", "DBGMCU")),
("STM32G4.*:DBGMCU:.*", ("dbgmcu", "g4", "DBGMCU")), ("STM32G4.*:DBGMCU:.*", ("dbgmcu", "g4", "DBGMCU")),
("STM32H7.*:DBGMCU:.*", ("dbgmcu", "h7", "DBGMCU")), ("STM32H7.*:DBGMCU:.*", ("dbgmcu", "h7", "DBGMCU")),
@ -447,6 +453,22 @@ pub fn parse_groups() -> Result<(HashMap<String, Chip>, Vec<ChipGroup>), anyhow:
Ok((chips, chip_groups)) Ok((chips, chip_groups))
} }
static NOPELIST: &[&str] = &[
// Not supported
"STM32MP",
// Does not exist in ST website. No datasheet, no RM.
"STM32GBK",
"STM32L485",
"STM32U59",
"STM32U5A",
// STM32WxM modules. These are based on a chip that's supported on its own,
// not sure why we want a separate target for it.
"STM32WL5M",
"STM32WB1M",
"STM32WB3M",
"STM32WB5M",
];
fn parse_group( fn parse_group(
f: std::path::PathBuf, f: std::path::PathBuf,
chips: &mut HashMap<String, Chip>, chips: &mut HashMap<String, Chip>,
@ -454,14 +476,10 @@ fn parse_group(
) -> anyhow::Result<()> { ) -> anyhow::Result<()> {
let ff = f.file_name().unwrap().to_string_lossy(); let ff = f.file_name().unwrap().to_string_lossy();
// Not supported for nope in NOPELIST {
if ff.contains("STM32MP") { if ff.contains(nope) {
return Ok(()); return Ok(());
} }
// Does not exist in ST website. No datasheet, no RM.
if ff.contains("STM32GBK") || ff.contains("STM32L485") {
return Ok(());
} }
let parsed: xml::Mcu = quick_xml::de::from_str(&std::fs::read_to_string(f)?)?; let parsed: xml::Mcu = quick_xml::de::from_str(&std::fs::read_to_string(f)?)?;
@ -567,8 +585,12 @@ fn process_group(
group.line = Some(group.xml.line.clone()); group.line = Some(group.xml.line.clone());
group.die = Some(group.xml.die.clone()); group.die = Some(group.xml.die.clone());
let rcc_kind = group.ips.values().find(|x| x.name == "RCC").unwrap().version.clone(); let rcc_kind = group.ips.values().find(|x| x.name == "RCC").unwrap().version.clone();
let rcc_block = peri_matcher.match_peri(&format!("{chip_name}:RCC:{rcc_kind}")).unwrap(); let rcc_block = peri_matcher
let h = headers.get_for_chip(&chip_name).unwrap(); .match_peri(&format!("{chip_name}:RCC:{rcc_kind}"))
.unwrap_or_else(|| panic!("could not get rcc for {}", &chip_name));
let h = headers
.get_for_chip(&chip_name)
.unwrap_or_else(|| panic!("could not get header for {}", &chip_name));
let chip_af = &group.ips.values().find(|x| x.name == "GPIO").unwrap().version; let chip_af = &group.ips.values().find(|x| x.name == "GPIO").unwrap().version;
let chip_af = chip_af.strip_suffix("_gpio_v1_0").unwrap(); let chip_af = chip_af.strip_suffix("_gpio_v1_0").unwrap();
let chip_af = af.0.get(chip_af); let chip_af = af.0.get(chip_af);

8
src/dma.rs
View File

@ -1,5 +1,7 @@
use std::collections::HashMap; use std::collections::HashMap;
use anyhow::Context;
mod xml { mod xml {
use serde::Deserialize; use serde::Deserialize;
@ -83,7 +85,11 @@ impl DmaChannels {
for f in glob::glob("sources/cubedb/mcu/IP/DMA*Modes.xml")? for f in glob::glob("sources/cubedb/mcu/IP/DMA*Modes.xml")?
.chain(glob::glob("sources/cubedb/mcu/IP/BDMA*Modes.xml")?) .chain(glob::glob("sources/cubedb/mcu/IP/BDMA*Modes.xml")?)
{ {
let parsed: xml::Ip = quick_xml::de::from_str(&std::fs::read_to_string(f?)?)?; let f = f?;
if f.to_string_lossy().contains("DMAMUX") {
continue;
}
let parsed: xml::Ip = quick_xml::de::from_str(&std::fs::read_to_string(&f)?).context(format!("{:?}", f))?;
let ff = parsed.version.clone(); let ff = parsed.version.clone();
let is_explicitly_bdma = match parsed.name.as_str() { let is_explicitly_bdma = match parsed.name.as_str() {

2
src/docs.rs
View File

@ -134,6 +134,7 @@ fn parse_document_type(t: &str) -> &'static str {
"Errata sheet" => "errata_sheet", "Errata sheet" => "errata_sheet",
"Application note" => "application_note", "Application note" => "application_note",
"User manual" => "user_manual", "User manual" => "user_manual",
"Data brief" => "data_brief",
_ => panic!("Unknown doc type {t}"), _ => panic!("Unknown doc type {t}"),
} }
} }
@ -145,6 +146,7 @@ fn order_doc_type(t: &str) -> u8 {
"datahseet" => 2, // TODO: fix me "datahseet" => 2, // TODO: fix me
"errata_sheet" => 3, "errata_sheet" => 3,
"application_note" => 4, "application_note" => 4,
"data_brief" => 5,
_ => panic!("Unknown doc type {t}"), _ => panic!("Unknown doc type {t}"),
} }
} }

1
src/interrupts.rs
View File

@ -374,6 +374,7 @@ fn valid_signals(peri: &str) -> Vec<String> {
("USB_OTG_FS", &["GLOBAL", "EP1_OUT", "EP1_IN", "WKUP"]), ("USB_OTG_FS", &["GLOBAL", "EP1_OUT", "EP1_IN", "WKUP"]),
("USB_OTG_HS", &["GLOBAL", "EP1_OUT", "EP1_IN", "WKUP"]), ("USB_OTG_HS", &["GLOBAL", "EP1_OUT", "EP1_IN", "WKUP"]),
("USB", &["LP", "HP", "WKUP"]), ("USB", &["LP", "HP", "WKUP"]),
("GPU2D", &["ER"]),
]; ];
for (prefix, signals) in IRQ_SIGNALS_MAP { for (prefix, signals) in IRQ_SIGNALS_MAP {