stm32-data/data/registers/syscfg_c0.yaml

---
block/SYSCFG:
  description: register block
  items:
    - name: CFGR1
      description: configuration register 1
      byte_offset: 0
      fieldset: CFGR1
    - name: CFGR2
      description: configuration register 2
      byte_offset: 24
      fieldset: CFGR2
    - name: CFGR3
      description: configuration register 3
      byte_offset: 60
      fieldset: CFGR3
    - name: ITLINE0
      description: interrupt line 0 status register
      byte_offset: 128
      access: Read
      fieldset: ITLINE0
    - name: ITLINE2
      description: interrupt line 2 status register
      byte_offset: 136
      access: Read
      fieldset: ITLINE2
    - name: ITLINE3
      description: interrupt line 3 status register
      byte_offset: 140
      access: Read
      fieldset: ITLINE3
    - name: ITLINE4
      description: interrupt line 4 status register
      byte_offset: 144
      access: Read
      fieldset: ITLINE4
    - name: ITLINE5
      description: interrupt line 5 status register
      byte_offset: 148
      access: Read
      fieldset: ITLINE5
    - name: ITLINE6
      description: interrupt line 6 status register
      byte_offset: 152
      access: Read
      fieldset: ITLINE6
    - name: ITLINE7
      description: interrupt line 7 status register
      byte_offset: 156
      access: Read
      fieldset: ITLINE7
    - name: ITLINE9
      description: interrupt line 9 status register
      byte_offset: 164
      access: Read
      fieldset: ITLINE9
    - name: ITLINE10
      description: interrupt line 10 status register
      byte_offset: 168
      access: Read
      fieldset: ITLINE10
    - name: ITLINE11
      description: interrupt line 11 status register
      byte_offset: 172
      access: Read
      fieldset: ITLINE11
    - name: ITLINE12
      description: interrupt line 12 status register
      byte_offset: 176
      access: Read
      fieldset: ITLINE12
    - name: ITLINE13
      description: interrupt line 13 status register
      byte_offset: 180
      access: Read
      fieldset: ITLINE13
    - name: ITLINE14
      description: interrupt line 14 status register
      byte_offset: 184
      access: Read
      fieldset: ITLINE14
    - name: ITLINE16
      description: interrupt line 16 status register
      byte_offset: 192
      access: Read
      fieldset: ITLINE16
    - name: ITLINE19
      description: interrupt line 19 status register
      byte_offset: 204
      access: Read
      fieldset: ITLINE19
    - name: ITLINE21
      description: interrupt line 21 status register
      byte_offset: 212
      access: Read
      fieldset: ITLINE21
    - name: ITLINE22
      description: interrupt line 22 status register
      byte_offset: 216
      access: Read
      fieldset: ITLINE22
    - name: ITLINE23
      description: interrupt line 23 status register
      byte_offset: 220
      access: Read
      fieldset: ITLINE23
    - name: ITLINE25
      description: interrupt line 25 status register
      byte_offset: 228
      access: Read
      fieldset: ITLINE25
    - name: ITLINE27
      description: interrupt line 27 status register
      byte_offset: 236
      access: Read
      fieldset: ITLINE27
    - name: ITLINE28
      description: interrupt line 28 status register
      byte_offset: 240
      access: Read
      fieldset: ITLINE28
fieldset/CFGR1:
  description: configuration register 1
  fields:
    - name: MEM_MODE
      description: "Memory mapping selection bits\r This bitfield controlled by software selects the memory internally mapped at the address 0x0000 0000. Its reset value is determined by the boot mode configuration. Refer to for more details.\r x0: Main Flash memory"
      bit_offset: 0
      bit_size: 2
      enum: MEM_MODE
    - name: PA11_RMP
      description: "PA11 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port."
      bit_offset: 3
      bit_size: 1
    - name: PA12_RMP
      description: "PA12 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port."
      bit_offset: 4
      bit_size: 1
    - name: IR_POL
      description: IR output polarity selection
      bit_offset: 5
      bit_size: 1
    - name: IR_MOD
      description: "IR Modulation Envelope signal selection\r This bitfield selects the signal for IR modulation envelope:"
      bit_offset: 6
      bit_size: 2
      enum: IR_MOD
    - name: I2C_PB6_FMP
      description: "Fast Mode Plus (FM+) enable for PB6\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
      bit_offset: 16
      bit_size: 1
    - name: I2C_PB7_FMP
      description: "Fast Mode Plus (FM+) enable for PB7\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
      bit_offset: 17
      bit_size: 1
    - name: I2C_PB8_FMP
      description: "Fast Mode Plus (FM+) enable for PB8\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
      bit_offset: 18
      bit_size: 1
    - name: I2C_PB9_FMP
      description: "Fast Mode Plus (FM+) enable for PB9\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
      bit_offset: 19
      bit_size: 1
    - name: I2C1_FMP
      description: "Fast Mode Plus (FM+) enable for I2C1\r This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports configured as I2C1 through GPIOx_AFR registers.\r With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C1 can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the speed control is ignored."
      bit_offset: 20
      bit_size: 1
    - name: I2C_PA9_FMP
      description: "Fast Mode Plus (FM+) enable for PA9\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
      bit_offset: 22
      bit_size: 1
    - name: I2C_PA10_FMP
      description: "Fast Mode Plus (FM+) enable for PA10\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
      bit_offset: 23
      bit_size: 1
    - name: I2C_PC14_FMP
      description: "Fast Mode Plus (FM+) enable for PC14\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PC14 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
      bit_offset: 24
      bit_size: 1
fieldset/CFGR2:
  description: configuration register 2
  fields:
    - name: LOCKUP_LOCK
      description: "Cortex<Superscript><3E><Default <20> Font>-M0+ LOCKUP enable\r This bit is set by software and cleared by system reset. When set, it enables the connection of Cortex<Superscript><3E><Default <20> Font>-M0+ LOCKUP (HardFault) output to the TIM1/16/17 Break input."
      bit_offset: 0
      bit_size: 1
fieldset/CFGR3:
  description: configuration register 3
  fields:
    - name: PINMUX0
      description: "Pin GPIO multiplexer 0\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved\r Pin F2 of WLCSP14 package GPIO assignment\r 1x: Reserved"
      bit_offset: 0
      bit_size: 2
      enum: PINMUX0
    - name: PINMUX1
      description: "Pin GPIO multiplexer 1\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved"
      bit_offset: 2
      bit_size: 2
      enum: PINMUX1
    - name: PINMUX2
      description: "Pin GPIO multiplexer 2\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved\r 1x: Reserved"
      bit_offset: 4
      bit_size: 2
      enum: PINMUX2
    - name: PINMUX3
      description: "Pin GPIO multiplexer 3\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved"
      bit_offset: 6
      bit_size: 2
      enum: PINMUX3
    - name: PINMUX4
      description: "Pin GPIO multiplexer 4\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved\r 1x: Reserved"
      bit_offset: 8
      bit_size: 2
      enum: PINMUX4
    - name: PINMUX5
      description: "Pin GPIO multiplexer 5\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved"
      bit_offset: 10
      bit_size: 2
      enum: PINMUX5
fieldset/ITLINE0:
  description: interrupt line 0 status register
  fields:
    - name: WWDG
      description: Window watchdog interrupt pending flag
      bit_offset: 0
      bit_size: 1
fieldset/ITLINE10:
  description: interrupt line 10 status register
  fields:
    - name: DMA1_CH2
      description: DMA1 channel 2 interrupt request pending
      bit_offset: 0
      bit_size: 1
    - name: DMA1_CH3
      description: DMA1 channel 3 interrupt request pending
      bit_offset: 1
      bit_size: 1
fieldset/ITLINE11:
  description: interrupt line 11 status register
  fields:
    - name: DMAMUX
      description: DMAMUX interrupt request pending
      bit_offset: 0
      bit_size: 1
fieldset/ITLINE12:
  description: interrupt line 12 status register
  fields:
    - name: ADC
      description: ADC interrupt request pending
      bit_offset: 0
      bit_size: 1
fieldset/ITLINE13:
  description: interrupt line 13 status register
  fields:
    - name: TIM1_CCU
      description: Timer 1 commutation interrupt request pending
      bit_offset: 0
      bit_size: 1
    - name: TIM1_TRG
      description: Timer 1 trigger interrupt request pending
      bit_offset: 1
      bit_size: 1
    - name: TIM1_UPD
      description: Timer 1 update interrupt request pending
      bit_offset: 2
      bit_size: 1
    - name: TIM1_BRK
      description: Timer 1 break interrupt request pending
      bit_offset: 3
      bit_size: 1
fieldset/ITLINE14:
  description: interrupt line 14 status register
  fields:
    - name: TIM1_CC
      description: Timer 1 capture compare interrupt request pending
      bit_offset: 0
      bit_size: 1
fieldset/ITLINE16:
  description: interrupt line 16 status register
  fields:
    - name: TIM3
      description: Timer 3 interrupt request pending
      bit_offset: 0
      bit_size: 1
fieldset/ITLINE19:
  description: interrupt line 19 status register
  fields:
    - name: TIM14
      description: Timer 14 interrupt request pending
      bit_offset: 0
      bit_size: 1
fieldset/ITLINE2:
  description: interrupt line 2 status register
  fields:
    - name: RTC
      description: RTC interrupt request pending (EXTI line 19)
      bit_offset: 1
      bit_size: 1
fieldset/ITLINE21:
  description: interrupt line 21 status register
  fields:
    - name: TIM16
      description: Timer 16 interrupt request pending
      bit_offset: 0
      bit_size: 1
fieldset/ITLINE22:
  description: interrupt line 22 status register
  fields:
    - name: TIM17
      description: Timer 17 interrupt request pending
      bit_offset: 0
      bit_size: 1
fieldset/ITLINE23:
  description: interrupt line 23 status register
  fields:
    - name: I2C1
      description: "I2C1 interrupt request pending, combined with EXTI line 23"
      bit_offset: 0
      bit_size: 1
fieldset/ITLINE25:
  description: interrupt line 25 status register
  fields:
    - name: SPI1
      description: SPI1 interrupt request pending
      bit_offset: 0
      bit_size: 1
fieldset/ITLINE27:
  description: interrupt line 27 status register
  fields:
    - name: USART1
      description: "USART1 interrupt request pending, combined with EXTI line 25"
      bit_offset: 0
      bit_size: 1
fieldset/ITLINE28:
  description: interrupt line 28 status register
  fields:
    - name: USART2
      description: USART2 interrupt request pending (EXTI line 26)
      bit_offset: 0
      bit_size: 1
fieldset/ITLINE3:
  description: interrupt line 3 status register
  fields:
    - name: FLASH_ITF
      description: Flash interface interrupt request pending
      bit_offset: 1
      bit_size: 1
fieldset/ITLINE4:
  description: interrupt line 4 status register
  fields:
    - name: RCC
      description: Reset and clock control interrupt request pending
      bit_offset: 0
      bit_size: 1
fieldset/ITLINE5:
  description: interrupt line 5 status register
  fields:
    - name: EXTI
      description: EXTI
      bit_offset: 0
      bit_size: 1
      array:
        len: 2
        stride: 1
fieldset/ITLINE6:
  description: interrupt line 6 status register
  fields:
    - name: EXTI
      description: EXTI
      bit_offset: 0
      bit_size: 1
      array:
        len: 2
        stride: 1
fieldset/ITLINE7:
  description: interrupt line 7 status register
  fields:
    - name: EXTI
      description: EXTI
      bit_offset: 0
      bit_size: 1
      array:
        len: 12
        stride: 1
fieldset/ITLINE9:
  description: interrupt line 9 status register
  fields:
    - name: DMA1_CH1
      description: DMA1 channel 1interrupt request pending
      bit_offset: 0
      bit_size: 1
enum/IR_MOD:
  bit_size: 2
  variants:
    - name: TIM16
      description: TIM16
      value: 0
    - name: USART1
      description: USART1
      value: 1
    - name: USART2
      description: USART2
      value: 2
enum/MEM_MODE:
  bit_size: 2
  variants:
    - name: FLASH
      description: System Flash memory
      value: 1
    - name: SRAM
      description: Embedded SRAM
      value: 3
enum/PINMUX0:
  bit_size: 2
  variants:
    - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1
      description: PB7
      value: 0
    - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_F2
      description: PA1
      value: 0
    - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1
      description: PC14
      value: 1
    - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_F2
      description: PA2
      value: 1
enum/PINMUX1:
  bit_size: 2
  variants:
    - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4
      description: PF2
      value: 0
    - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G3
      description: PF2
      value: 0
    - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4
      description: PA0
      value: 1
    - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G3
      description: PA0
      value: 1
    - name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4
      description: PA1
      value: 2
    - name: B_0x3_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4
      description: PA2
      value: 3
enum/PINMUX2:
  bit_size: 2
  variants:
    - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5
      description: PA8
      value: 0
    - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J1
      description: PA8
      value: 0
    - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5
      description: PA11
      value: 1
    - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J1
      description: PA11
      value: 1
enum/PINMUX3:
  bit_size: 2
  variants:
    - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8
      description: PA14
      value: 0
    - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_H2
      description: PA5
      value: 0
    - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8
      description: PB6
      value: 1
    - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_H2
      description: PA6
      value: 1
    - name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8
      description: PC15
      value: 2
enum/PINMUX4:
  bit_size: 2
  variants:
    - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2
      description: PA7
      value: 0
    - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G1
      description: PA7
      value: 0
    - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2
      description: PA12
      value: 1
    - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G1
      description: PA12
      value: 1
enum/PINMUX5:
  bit_size: 2
  variants:
    - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1
      description: PA3
      value: 0
    - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J3
      description: PA3
      value: 0
    - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1
      description: PA4
      value: 1
    - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J3
      description: PA4
      value: 1
    - name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1
      description: PA5
      value: 2
    - name: B_0x3_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1
      description: PA6
      value: 3