xoviat
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f81c15c0b7
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Merge branch 'main' of https://github.com/embassy-rs/stm32-data into rcc
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2023-10-13 20:56:36 -05:00 |
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xoviat
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aa5e909e11
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rcc: more enum cleanup
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2023-10-13 20:54:24 -05:00 |
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JackN
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bcaacfcfa2
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GFXMMU: Add transform to automate cleanup and array creation.
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2023-10-13 17:15:33 -04:00 |
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JackN
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0f0517404e
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GFXMMU: Add new peripherals to perimap
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2023-10-13 17:12:57 -04:00 |
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JackN
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53c636386b
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GFXMMU: New peripheral yamls
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2023-10-13 17:12:57 -04:00 |
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JackN
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48199eea42
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Update transform*.yaml with new serde-yaml syntax
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2023-10-13 13:04:03 -04:00 |
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xoviat
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65a6b20e60
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Merge pull request #280 from xoviat/rcc
rcc: rename h5 clock enum variants and add check
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2023-10-13 01:51:21 +00:00 |
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xoviat
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c4cd46927d
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rcc: rename h5 clock enum variants and add check
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2023-10-12 20:48:35 -05:00 |
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Dario Nieuwenhuis
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e97ad65e67
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Merge pull request #279 from noppej/stm32u5_updates
Add OCTOSPI and OCTOSPIM peripherals.
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2023-10-12 23:06:29 +00:00 |
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JackN
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019e802e27
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OCTOSPI: Fix "MAXTRAN was in wrong yaml".
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2023-10-12 18:52:50 -04:00 |
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JackN
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af1a5f5877
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OCTOSPI: Merge peri yamls
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2023-10-12 17:44:41 -04:00 |
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JackN
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4e2bf3eb20
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PR Review corrections
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2023-10-12 16:45:54 -04:00 |
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JackN
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0ceaa321a3
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Add additional check instructions to README
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2023-10-12 15:50:35 -04:00 |
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JackN
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e99c97f0f6
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OCTOSPI: Merge peripheral yamls and consolidate enums
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2023-10-12 15:43:04 -04:00 |
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JackN
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b07f5a1ba2
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Reformat yaml's with chiptool fmt
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2023-10-12 10:49:41 -04:00 |
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JackN
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2ab8cf7d44
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Remove blanket matches from perimap
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2023-10-12 10:45:54 -04:00 |
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JackN
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c34f46566e
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Add STM32u5xx to header_map.yaml
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2023-10-12 10:24:00 -04:00 |
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JackN
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dc7bc1272a
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Add OCTOSPIM and OCTOSPI to perimap
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2023-10-12 10:24:00 -04:00 |
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JackN
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e933ee6cc4
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New peripherals: octospim_v1+v2, and octospi_v1-v4
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2023-10-12 10:23:59 -04:00 |
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JackN
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a40d19e6e9
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Ensure download-all gets latest STM32U5 svd's
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2023-10-11 10:36:30 -04:00 |
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Dario Nieuwenhuis
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6bfa5a0dce
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rtc/bd fixes.
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2023-10-11 03:41:10 +02:00 |
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Dario Nieuwenhuis
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9f45b0c48c
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Rename HSI to HSI16 in L1.
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2023-10-11 01:21:46 +02:00 |
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Dario Nieuwenhuis
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f40f5a40c1
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Not all L0s have HSI48/CRS.
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2023-10-11 01:21:26 +02:00 |
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Dario Nieuwenhuis
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71f81b44e3
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Rename HSE32 -> HSE.
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2023-10-11 00:29:01 +02:00 |
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Dario Nieuwenhuis
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ff45aa382e
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rcc: add more missing enums.
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2023-10-11 00:07:28 +02:00 |
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Dario Nieuwenhuis
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e89b8cfc30
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rcc: add PLL enums.
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2023-10-09 02:44:42 +02:00 |
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xoviat
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eecd80c34d
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Merge pull request #278 from xoviat/rcc
rcc: lower field names
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2023-10-08 23:15:53 +00:00 |
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xoviat
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926dfb5ed2
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Merge branch 'main' of https://github.com/embassy-rs/stm32-data into rcc
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2023-10-08 18:05:40 -05:00 |
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xoviat
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421c595a13
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rcc: lower reg data
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2023-10-08 18:05:16 -05:00 |
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xoviat
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81fbbfdf56
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Merge pull request #277 from xoviat/mux
rcc: fix mux determinism
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2023-10-08 20:53:18 +00:00 |
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xoviat
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61c9f8c691
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rcc: fix mux determinism
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2023-10-08 15:43:06 -05:00 |
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xoviat
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6371d5472b
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Merge pull request #276 from xoviat/pretty-print
gen: pretty print ir
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2023-10-08 20:05:41 +00:00 |
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xoviat
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ee8e8c82dc
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gen: pretty print ir
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2023-10-08 14:46:58 -05:00 |
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Dario Nieuwenhuis
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a7bf7f02d1
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Fix MCO/MCO1 inconsistency in G0, C0.
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2023-10-07 01:13:03 +02:00 |
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Dario Nieuwenhuis
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6c73ffbd0b
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rcc: make naming consistent between "mco" and "mcosel".
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2023-10-07 00:46:19 +02:00 |
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Dario Nieuwenhuis
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8d112b7a93
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rcc: add MCO enums for WB
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2023-10-07 00:20:42 +02:00 |
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Dario Nieuwenhuis
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e701705d79
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rcc: add MCOPRE enum for h5, h7.
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2023-10-07 00:10:08 +02:00 |
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Dario Nieuwenhuis
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11256dc370
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chiptool fmt.
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2023-10-07 00:09:14 +02:00 |
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xoviat
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f0f06b4c95
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Merge pull request #274 from xoviat/pin-sort
sort pins by key
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2023-10-06 01:17:59 +00:00 |
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xoviat
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e7a291e659
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sort pins by key
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2023-10-05 20:04:58 -05:00 |
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xoviat
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9075e499c2
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Merge pull request #272 from mattico/h7-lsedrv-errata
RCC: LSEDRV Register Fixes
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2023-10-06 00:49:46 +00:00 |
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xoviat
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2271da1671
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Merge branch 'main' of https://github.com/embassy-rs/stm32-data into h7-lsedrv-errata
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2023-10-05 19:30:38 -05:00 |
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xoviat
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5b75119688
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Merge pull request #273 from xoviat/pin-sorting
sort pins to avoid diff
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2023-10-06 00:14:36 +00:00 |
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xoviat
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ab12bb45b1
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sort pins to avoid diff
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2023-10-05 19:08:51 -05:00 |
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Matt Ickstadt
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2ceed56e94
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RCC: add LSEDRV enums for WB and WL series
These are in the RMs but previously missing.
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2023-10-05 11:18:49 -05:00 |
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Matt Ickstadt
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60d034f9fa
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RCC: unify LSEDRV enum variant names and descriptions
Now the only differences are the series which have swapped medium low/high bits: F0, F3v2, F3, F7, and H7_RM0433.
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2023-10-05 10:56:02 -05:00 |
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Matt Ickstadt
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32b3bd75ea
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H7: Fix LSEDRV bits of RM0433
Errata ES0392 2.2.14
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2023-10-05 10:37:07 -05:00 |
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Matt Ickstadt
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568a7058a1
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Create rcc_h7rm04ee.yaml as a copy of rcc_h7.yaml
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2023-10-05 10:35:43 -05:00 |
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xoviat
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172c5ea188
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Merge pull request #271 from xoviat/opamp
opamp: add other pins for f3 and g4
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2023-10-04 01:45:36 +00:00 |
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xoviat
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feec3c1617
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opamp: add other pins for f3 and g4
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2023-10-03 20:38:38 -05:00 |
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