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Author SHA1 Message Date
Dario Nieuwenhuis
49e579e97f Add F2 RCC 2021-08-19 22:12:39 +02:00
Dario Nieuwenhuis
e289dd883f Cleanup EXTI 2021-08-19 21:54:22 +02:00
Dario Nieuwenhuis
701ab04c2a Cleanup SYSCFG naming 2021-08-19 21:28:32 +02:00
Dario Nieuwenhuis
31997049ea Fix wrong register offsets in WB SYSCFG 2021-08-19 19:20:13 +02:00
Dario Nieuwenhuis
6af9f2c0d1 Add RCC for F3, F7, G4, H7AB, L1, L5, WB*, WL5, WLE 2021-08-19 19:13:30 +02:00
Dario Nieuwenhuis
bd402a58f2 Merge pull request #72 from bgamari/stm32g0 
STM32G0 support
 2021-08-19 16:05:29 +02:00
Ben Gamari
254c59c064 Introduce STM32G0 ADC support 2021-08-19 15:57:17 +02:00
Ben Gamari
f57a268b9f Add STM32G0 support 
Includes manually specified register layouts for EXTI and SYSCFG.
 2021-08-19 15:57:00 +02:00
Ben Gamari
075d283354 parse: Drop duplicate pin definitions 
The STM32G0 SVDs contain duplicate pin declarations.
 2021-08-19 15:55:13 +02:00
Ben Gamari
9c753da57b Add a bit of documentation for register extraction process 2021-08-19 15:54:36 +02:00
Ben Gamari
f5808de749 Add RCC support for STM32G0 2021-08-19 15:54:36 +02:00
Ben Gamari
e735ea9769 Fix hash-bangs 
/usr/bin/bash isn't portable.
 2021-08-19 15:54:36 +02:00
Dario Nieuwenhuis
8bb9c26d38 Update README.md 2021-08-18 22:17:16 +02:00
Dario Nieuwenhuis
f0e85a7e0d Merge pull request #81 from embassy-rs/add-wl55-radio-spi 
Add wl55 radio spi
 2021-08-18 15:21:45 +02:00
Ulf Lilleengen
63d1af4eca Rerun parse.py 2021-08-18 14:16:49 +02:00
Ulf Lilleengen
d9708f6bfc Use correct peripheral name for SUBGHZ SPI 
* Add SPI2s1_v3_5 register block for SUBGHZSPI peripheral
 2021-08-18 14:00:14 +02:00
Ulf Lilleengen
04ae6ce25e Add SPI2s1_v3_5 2021-08-18 13:59:51 +02:00
Dario Nieuwenhuis
80af84607a Merge pull request #80 from lulf/stm32wl55-regs 
Stm32wl55 exti regs
 2021-08-17 15:51:18 +02:00
Ulf Lilleengen
919a61e847 Add STM32WL5x exti block 2021-08-17 13:02:49 +02:00
Dario Nieuwenhuis
32b5c5c890 Merge pull request #79 from bobmcwhirter/h7_exti 
H7 exti
 2021-08-16 21:30:12 +02:00
Bob McWhirter
541091cded Include the reg block. 2021-08-16 15:12:17 -04:00
Bob McWhirter
2c7422ab76 Special-case the H7 EXTI reg layout. 2021-08-16 14:59:16 -04:00
Ulf Lilleengen
4c801c1234 Merge pull request #78 from lulf/parse-bugfix 
Parse bugfix and expose shared usart irqs
 2021-08-16 16:48:39 +02:00
Ulf Lilleengen
154d226f7a Handle shared USART IRQs 2021-08-16 13:02:25 +02:00
Ulf Lilleengen
a84e7d8b8c Add ability to override peripheral address if bug in header sources 2021-08-16 13:01:25 +02:00
Ulf Lilleengen
7489588564 Give different names to secure and non-secure cores 2021-08-16 12:38:33 +02:00
Dario Nieuwenhuis
a7bebbd2ef Merge pull request #77 from timokroeger/can-interrupts 
CAN interrupts
 2021-08-15 13:20:09 +02:00
Timo Kröger
c5a86b0744 CAN interrupts 2021-08-15 11:13:26 +02:00
Dario Nieuwenhuis
8c392a059b Merge pull request #74 from timokroeger/bxcan 
bxCAN Peripheral
 2021-08-15 00:10:26 +02:00
Dario Nieuwenhuis
946eb0bb59 Merge pull request #76 from FrozenDroid/main 
add UART:sci2_v2_1 to parser
 2021-08-13 16:35:11 +02:00
Vincent Stakenburg
67c16f80cf add UART:sci2_v2_1 to parser 2021-08-13 16:02:12 +02:00
Timo Kröger
198e4f3247 Add bxcan registers 2021-08-06 11:52:47 +02:00
Dario Nieuwenhuis
e7998ed4c2 Merge pull request #73 from timokroeger/fix-rcc 
Fix RCC enable bits
 2021-08-03 22:05:43 +02:00
Timo Kröger
7506b50031 rcc_l4: Remove duplicate bits 2021-08-03 16:33:59 +02:00
Timo Kröger
f865878b4b rcc_f4: Fix RCC bits 
## LPTIM1EN / LPTIMER1EN

Only stm32f413 has LPTIM1 peripheral, ref manual bit names:
LPTIMER1EN, LPTIMER1RST, LPTIMER1LPEN, LPTIMER1SEL

action: Rename to LPTIM1(EN|RST|...) for consistency (matches peripheral name)

## FMC / FSMC

not available as peripheral in the YAML anyway.. TODO: why?

EN and RST

FSMC: f405, f407, f412, f413
FSC: f427, f429, f446, f469

action: none

## CECEN / CAN3EN

mutually exclusive peripherals, alias ok?

CECEN: f446
CAN3EN: f413

action: split off f4x3 yaml, f423 exists, but not available as svd

## USART / UART

all over the place, register names in ref manual not always consistent
stm32 follows a simple rule for the actual peripherals:
USART 1-3, 6
UART 4, 5, 7-10

action: rename enable/rst bits to rules above
 2021-08-03 14:55:36 +02:00
Timo Kröger
babbe782f3 rcc_l0: Remove non existing RCC bits 
## firewall

l0x0, l0x1: FWEN - Firewall clock enable bit
l0x2, l0x3: MIFIEN - MiFaRe Firewall clock enable bit
action: none

## watchdog

peripheral: WWDG
WWDGRST vs WWDRST
action: remove

## CRS vs CRC

l0x2, l0x3: CRC reset is wrong
action: remove duplicate CRC bit

## LPUART12RST vs USART2RST

action: rename, it sholud be USART2
 2021-08-03 14:31:36 +02:00
Timo Kröger
d1597c646d rcc_l0: Remove duplicate I2C3 reset bit 2021-08-03 10:55:51 +02:00
Timo Kröger
ded4f52051 rcc_f4: Remove duplicate USBF bit 2021-08-03 10:55:51 +02:00
Bob McWhirter
f8e3e7b5de Merge pull request #70 from bobmcwhirter/memoryx 
Include base addresses for flash and ram.
 2021-08-02 11:09:36 -04:00
Bob McWhirter
cd939ee553 Download cubeprogdb and point the parser to that. 2021-08-02 11:06:28 -04:00
Bob McWhirter
4a67203c86 Keep device-id as hex. 2021-08-02 11:06:26 -04:00
Bob McWhirter
93490bc42f Ensure that any bank is not larger than the total from the SVD. 2021-08-02 11:06:26 -04:00
Bob McWhirter
83f5b39ecb Parse memory names slightly better from the XML. 2021-08-02 11:06:26 -04:00
Bob McWhirter
72478d1bc5 Reparse to include memory sizes. 2021-08-02 11:06:26 -04:00
Bob McWhirter
99cd26c33f Parse memory layouts for actual region sizes. 2021-08-02 11:06:25 -04:00
Bob McWhirter
2e7af6b842 Parse our memory location bases and name them well-ish. 2021-08-02 11:06:24 -04:00
Bob McWhirter
2d38aad861 Include base addresses for flash and ram. 
Remove 'null' entries for datasheets/reference-manuals.
 2021-08-02 11:06:23 -04:00
Dario Nieuwenhuis
4f2e1dad78 Merge pull request #71 from timokroeger/fix-f4-l4-rcc 
Remove invalid bits from F4, L4 RCC
 2021-07-31 19:01:30 +02:00
Timo Kröger
c02e3dc9ab Split f410 and f4 RCC yamls 
f410 has the RNGEN at a different position
 2021-07-31 17:40:30 +02:00
Timo Kröger
074aad8a66 Remove invalid bits from F4, L4 RCC 2021-07-30 17:35:52 +02:00