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Author SHA1 Message Date
Dario Nieuwenhuis
150bba33db Merge pull request #115 from sjoerdsimons/wip/sjoerd/stm32f1-adc 
stm32f1xx adc support
 2022-01-01 10:34:42 +01:00
Sjoerd Simons
8ed35ce95b Add registers for F1 ADC block 2021-12-29 15:51:27 +01:00
Sjoerd Simons
2616e499c6 Recognize ADC on STM32F1xx 
Translate the ADC block available in the F1 family to adc_f1
 2021-12-29 15:50:38 +01:00
Dario Nieuwenhuis
73902044de Fix typo 2021-12-23 20:32:39 +01:00
Dario Nieuwenhuis
ce7607e119 Merge pull request #112 from VasanthakumarV/f3-timers 
Assign correct register blocks for F3 Timers
 2021-12-23 11:46:55 +01:00
VasanthakumarV
a5008c71d5 [manual] Map register blocks to timers for F3 chips 2021-12-23 16:10:22 +05:30
Dario Nieuwenhuis
0e9fa2f438 Merge pull request #109 from VasanthakumarV/f3-registers 
Add `SYSCFG`, `PWR`, `FLASH` and `SPI` registers for `STM32F3`
 2021-12-16 08:12:07 +01:00
VasanthakumarV
b9193128ed [manual] Make EXTICRx in SYSCFG register an array 
The four variants of EXTICRx has been manually edited into
an array of size and stride four.
The corresponding fieldset was also manually changed.
 2021-12-09 13:47:55 +05:30
VasanthakumarV
fdf0cc95b9 [manual] Deduplicate PLLSRC entry of RCC_CFGR register 
I have manually removed the single bit PLLSRC under RCC_CFGR register,
and I have manually updated the `enum/PLLSRC` to have 3 variants to match
the bit_size of PLLSRC.
 2021-12-09 13:24:25 +05:30
Dario Nieuwenhuis
8011bfa629 Merge pull request #111 from matoushybl/feat/fmc 
FMC
 2021-12-08 20:20:52 +01:00
Matous Hybl
8402040d17 Fix generation of FMC peripheral in chip yamls. Add FMC registers. 2021-12-08 20:01:57 +01:00
VasanthakumarV
3275e41057 [manual] Add register mappings for F3 
Pattern matching for `FLASH`, `SYSCFG`, `PWR` and `SPI` registers
added for F3.
 2021-12-08 15:43:23 +05:30
VasanthakumarV
ef950a6feb [generate] Create SYSCFG, PWR, FLASH register files 2021-12-08 15:43:23 +05:30
Dario Nieuwenhuis
f6c9772cf4 usart: make v1 and v2 more consistent. 2021-12-08 04:48:21 +01:00
Ulf Lilleengen
cc3ea51778 Merge pull request #108 from embassy-rs/detect-iop-clock 
Detect iop bus
 2021-12-02 11:25:27 +01:00
Ulf Lilleengen
6eab78746e Fix wording 2021-12-02 11:23:16 +01:00
Ulf Lilleengen
57c7058739 Detect GPIO enable/reset registers on chips with separate bus for GPIO 2021-12-02 11:17:52 +01:00
Dario Nieuwenhuis
9afa81e824 Merge pull request #107 from matoushybl/timers 
Add correct timer register mapping for the H7 family.
 2021-11-30 20:16:05 +01:00
Dario Nieuwenhuis
372de46ad1 Merge pull request #106 from matoushybl/dcmi-fixes 
Dcmi fixes
 2021-11-30 19:43:12 +01:00
Matous Hybl
c2e87d9cc8 Relax DCMI peripheral matching condition. 2021-11-30 11:49:31 +01:00
Matous Hybl
2b56ec9e99 Add correct H7 timer register blocks. 2021-11-30 11:28:22 +01:00
Dario Nieuwenhuis
8f150ead7f Merge pull request #105 from embassy-rs/cleanups 
Expanded RCC, cleanups
 2021-11-29 17:08:13 +01:00
Dario Nieuwenhuis
cf665a99f3 better handling of naming exceptions. 2021-11-29 01:57:34 +01:00
Dario Nieuwenhuis
620afab503 more complete rcc info: clock, and enable/reset registers 2021-11-29 01:57:34 +01:00
Dario Nieuwenhuis
f93860b894 Do not output kind to the yamls. 
I originally added it for debugging of the stm32-data script itself.
It is useless to anyone trying to consume the yamls, due to the wonky st versioning.
 2021-11-29 01:57:34 +01:00
Dario Nieuwenhuis
a83949d082 Only parse rcc from the registers, not the modes xml. 
The info we have is available in both, the registers seem a bit
more reliable.
 2021-11-29 01:57:34 +01:00
Dario Nieuwenhuis
2d6befa3a4 Unify handling of "ghost peripherals" missing from the XMLs. 2021-11-29 01:57:34 +01:00
Dario Nieuwenhuis
a447451969 Ban STM32GBK1CB. 
It's a ghost stm32g4 chip that completely breaks the naming convention
and is apparently full-unobtainium (doesn't exist on mouser, digikey, etc.)
 2021-11-28 23:34:12 +01:00
Dario Nieuwenhuis
df6b1a13b0 rcc_f3: add lots of missing stuff. 2021-11-28 23:25:16 +01:00
Dario Nieuwenhuis
3780dbab57 rcc_l5: fix typo 2021-11-28 22:45:06 +01:00
Dario Nieuwenhuis
b4191f4d1c clocks: accept regs like xxENR1 (previously it'd only accept xxENR) 
This adds a few more `clock` entries.
 2021-11-28 22:26:22 +01:00
Dario Nieuwenhuis
ac50274c95 Ensure consistent order for dmamuxes. 2021-11-28 21:56:02 +01:00
Dario Nieuwenhuis
2e8c0bc791 Fix stm32u5 accidentally removed fieldset/PRIVCFGR 2021-11-27 02:32:51 +01:00
Dario Nieuwenhuis
b643072930 Merge pull request #104 from embassy-rs/stm32g4 
Stm32g4
 2021-11-27 02:21:32 +01:00
Dario Nieuwenhuis
353411841c stm32g4 support. 2021-11-27 02:20:17 +01:00
Dario Nieuwenhuis
6af084d858 SYSCFG_H7: random typo fix 2021-11-27 02:19:55 +01:00
Dario Nieuwenhuis
b630a96365 PWR: arrayify PUCRx, PDCRx 2021-11-27 02:19:38 +01:00
Ulf Lilleengen
064d70c85c Merge pull request #103 from embassy-rs/add-overrides 
Add overrides for missing GPIO blocks for STM32L432
 2021-11-22 13:29:44 +01:00
Ulf Lilleengen
6e3877238c Add overrides for missing GPIO blocks for STM32L432 2021-11-22 13:27:04 +01:00
Dario Nieuwenhuis
0dcaaa07fe cleanup spi v1/f1, add missing i2s stuff 2021-11-17 21:30:52 +01:00
Dario Nieuwenhuis
c6c5c099bb fmt all register yamls 2021-11-17 21:23:26 +01:00
Dario Nieuwenhuis
e00ad29955 Merge pull request #102 from bobmcwhirter/u5_i2c 
U5 i2c
 2021-11-12 03:19:36 +01:00
Bob McWhirter
2f142fadef Adjust to apply I2C for U5. 2021-11-11 15:52:31 -05:00
Dario Nieuwenhuis
5ee8e96dd0 Merge pull request #101 from bobmcwhirter/u5_rcc_enum 
U5 rcc enum
 2021-11-11 20:59:45 +01:00
Bob McWhirter
e501a9746f Complete enum cleanup. 2021-11-11 14:52:45 -05:00
Bob McWhirter
91c77958bd Remove some useless enums. 
Apply better variant names to some enums.
 2021-11-11 14:09:49 -05:00
Bob McWhirter
117e3f3f4b Clean up some enum variants, reduce some enums that duplicate. 2021-11-11 10:25:04 -05:00
Dario Nieuwenhuis
ca1fa7e249 Merge pull request #100 from matoushybl/fix/dcmi-rst 
Fix DCMI reset.
 2021-11-10 23:30:41 +01:00
Matous Hybl
bfc7856d75 Fix DCMI reset. 2021-11-10 17:31:06 +01:00
Dario Nieuwenhuis
6229ccf12a Merge pull request #99 from bobmcwhirter/u5supportmore 
More support for STM32U5
 2021-11-09 14:58:27 +01:00