JackN
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53c636386b
|
GFXMMU: New peripheral yamls
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2023-10-13 17:12:57 -04:00 |
|
xoviat
|
c4cd46927d
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rcc: rename h5 clock enum variants and add check
|
2023-10-12 20:48:35 -05:00 |
|
JackN
|
019e802e27
|
OCTOSPI: Fix "MAXTRAN was in wrong yaml".
|
2023-10-12 18:52:50 -04:00 |
|
JackN
|
af1a5f5877
|
OCTOSPI: Merge peri yamls
|
2023-10-12 17:44:41 -04:00 |
|
JackN
|
4e2bf3eb20
|
PR Review corrections
|
2023-10-12 16:45:54 -04:00 |
|
JackN
|
e99c97f0f6
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OCTOSPI: Merge peripheral yamls and consolidate enums
|
2023-10-12 15:43:04 -04:00 |
|
JackN
|
b07f5a1ba2
|
Reformat yaml's with chiptool fmt
|
2023-10-12 10:49:41 -04:00 |
|
JackN
|
c34f46566e
|
Add STM32u5xx to header_map.yaml
|
2023-10-12 10:24:00 -04:00 |
|
JackN
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e933ee6cc4
|
New peripherals: octospim_v1+v2, and octospi_v1-v4
|
2023-10-12 10:23:59 -04:00 |
|
Dario Nieuwenhuis
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6bfa5a0dce
|
rtc/bd fixes.
|
2023-10-11 03:41:10 +02:00 |
|
Dario Nieuwenhuis
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9f45b0c48c
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Rename HSI to HSI16 in L1.
|
2023-10-11 01:21:46 +02:00 |
|
Dario Nieuwenhuis
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f40f5a40c1
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Not all L0s have HSI48/CRS.
|
2023-10-11 01:21:26 +02:00 |
|
Dario Nieuwenhuis
|
71f81b44e3
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Rename HSE32 -> HSE.
|
2023-10-11 00:29:01 +02:00 |
|
Dario Nieuwenhuis
|
ff45aa382e
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rcc: add more missing enums.
|
2023-10-11 00:07:28 +02:00 |
|
Dario Nieuwenhuis
|
e89b8cfc30
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rcc: add PLL enums.
|
2023-10-09 02:44:42 +02:00 |
|
Dario Nieuwenhuis
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6c73ffbd0b
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rcc: make naming consistent between "mco" and "mcosel".
|
2023-10-07 00:46:19 +02:00 |
|
Dario Nieuwenhuis
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8d112b7a93
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rcc: add MCO enums for WB
|
2023-10-07 00:20:42 +02:00 |
|
Dario Nieuwenhuis
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e701705d79
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rcc: add MCOPRE enum for h5, h7.
|
2023-10-07 00:10:08 +02:00 |
|
Dario Nieuwenhuis
|
11256dc370
|
chiptool fmt.
|
2023-10-07 00:09:14 +02:00 |
|
Matt Ickstadt
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2ceed56e94
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RCC: add LSEDRV enums for WB and WL series
These are in the RMs but previously missing.
|
2023-10-05 11:18:49 -05:00 |
|
Matt Ickstadt
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60d034f9fa
|
RCC: unify LSEDRV enum variant names and descriptions
Now the only differences are the series which have swapped medium low/high bits: F0, F3v2, F3, F7, and H7_RM0433.
|
2023-10-05 10:56:02 -05:00 |
|
Matt Ickstadt
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32b3bd75ea
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H7: Fix LSEDRV bits of RM0433
Errata ES0392 2.2.14
|
2023-10-05 10:37:07 -05:00 |
|
Matt Ickstadt
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568a7058a1
|
Create rcc_h7rm04ee.yaml as a copy of rcc_h7.yaml
|
2023-10-05 10:35:43 -05:00 |
|
xoviat
|
feec3c1617
|
opamp: add other pins for f3 and g4
|
2023-10-03 20:38:38 -05:00 |
|
xoviat
|
06d13dfd24
|
Merge pull request #267 from oll3/tamp_block
add TAMP register block for g0, g4, l5, u5 and wl
|
2023-10-02 21:00:10 +00:00 |
|
Olle Sandberg
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00894c8e3d
|
clean up TAMP registers
Remove obvious 1 bit enums and make arrays of repeated fields.
|
2023-10-02 07:15:40 +02:00 |
|
xoviat
|
4a893c37da
|
add man impl. pin signals
|
2023-10-01 13:28:31 -05:00 |
|
xoviat
|
e36d73af66
|
Merge branch 'main' of https://github.com/embassy-rs/stm32-data into sbs
|
2023-09-28 18:52:19 -05:00 |
|
xoviat
|
97a4fb22b2
|
rename sbs to syscfg
|
2023-09-28 18:50:30 -05:00 |
|
xoviat
|
0041cf976c
|
opamp: add f3 and g4
|
2023-09-28 18:32:30 -05:00 |
|
xoviat
|
1b39301d8c
|
Merge branch 'master' into lptim-basic
|
2023-09-27 21:09:34 -05:00 |
|
Olle Sandberg
|
e7de675353
|
add TAMP register block for g0, g4, l5, u5 and wl
|
2023-09-27 07:35:27 +02:00 |
|
shakencodes
|
0adf2a75d1
|
Add enums MCOPRE & MCOSEL to wl5 & wle targets
|
2023-09-26 10:55:19 -07:00 |
|
Dario Nieuwenhuis
|
4f83d5d9cf
|
pwr: add f0, f1.
|
2023-09-25 00:27:32 +02:00 |
|
Dario Nieuwenhuis
|
d6b0763327
|
More rcc cleanups.
|
2023-09-19 04:17:00 +02:00 |
|
Dario Nieuwenhuis
|
2f97514774
|
pwr: add all VOS enums.
|
2023-09-18 02:57:23 +02:00 |
|
xoviat
|
a70aa2f06a
|
rcc: use same name for bus psc
|
2023-09-16 15:43:03 -05:00 |
|
Dario Nieuwenhuis
|
43c1e7b3be
|
Add STM32WBA support.
|
2023-09-16 02:34:03 +02:00 |
|
Dario Nieuwenhuis
|
8fec79a722
|
rcc consistency fixes.
|
2023-09-16 02:34:03 +02:00 |
|
Dario Nieuwenhuis
|
05ea13251c
|
pwr u5 cleanup
|
2023-09-16 02:34:03 +02:00 |
|
Dario Nieuwenhuis
|
86fb0cfc2f
|
chiptool fmt.
|
2023-09-16 02:34:03 +02:00 |
|
xoviat
|
1e9067e0f0
|
pwr/l0: cleanup enums
|
2023-09-14 17:32:36 -05:00 |
|
xoviat
|
1118eb4c96
|
cleanup adc common v2
|
2023-09-14 17:10:13 -05:00 |
|
xoviat
|
c3548f2b7a
|
add pwr l0
|
2023-09-14 17:10:04 -05:00 |
|
xoviat
|
4e6a74f69c
|
Merge pull request #252 from xoviat/adc-g4
g4: fix rcc adc generation and cleanup enums
|
2023-09-11 21:08:12 +00:00 |
|
xoviat
|
db70d16691
|
adc/v2: cleanup enums
|
2023-09-11 16:06:43 -05:00 |
|
xoviat
|
85e6808094
|
Merge pull request #241 from ExplodingWaffle/main
Add UCPD
|
2023-09-10 18:24:38 +00:00 |
|
xoviat
|
bbff2b9e6b
|
Merge pull request #249 from andresv/add-aes
Add AES registers
|
2023-09-10 18:19:31 +00:00 |
|
Scott Mabin
|
27b99b9d24
|
Add stbiterr field for sdmmc_v1
|
2023-09-10 12:37:48 +01:00 |
|
ExplodingWaffle
|
32bbb683af
|
finishing touches
|
2023-09-09 14:55:57 +01:00 |
|