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737 Commits

Author SHA1 Message Date
eZio Pan
837685460b remove OCPE, OPM, ECE enum of TIM 2023-12-23 18:54:07 +08:00
eZio Pan
9a5ac3abce DMA cleanup 2023-12-19 13:47:15 +08:00
eZio Pan
9e680c8d69 no need TIM CR1 ARPE enum, just a enable/disable field 2023-12-14 21:09:00 +08:00
Dario Nieuwenhuis
8f5fcae8c2 Fix QUADSPI RCC bit names. 2023-12-08 23:43:52 +01:00
Dario Nieuwenhuis
6fe2c922b8 Update headers. 2023-12-08 23:19:12 +01:00
Dario Nieuwenhuis
3634020845 Fix qspi for all chips. 
Co-Authored-By: Tupelov <64274155+Tupelov@users.noreply.github.com>
 2023-12-08 21:54:03 +01:00
Sam
b53fd35116 ADC afit_v1_1 implementation 2023-12-08 18:55:38 +01:00
Dario Nieuwenhuis
b6181ce3f3
Merge pull request #308 from tcbennun/fdcan-fix 
fdcan: add H7 support; fix regs for others; add message RAM blocks
 2023-12-08 17:21:24 +00:00
Aurélien Jacobs
2e467a5373 ADC: remove EXTSEL and JEXTSEL enum as they can be inconsistent between chips 2023-12-06 18:27:20 +01:00
Torin Cooper-Bennun
d5d131a702 rcc: g4,l5: add missing enums for FDCANSEL; fix a few incorrect descs 2023-11-21 14:57:43 +00:00
Torin Cooper-Bennun
389f547c13 fdcan: array-ify fields with 1 bit per FIFO element 2023-11-21 12:42:29 +00:00
Torin Cooper-Bennun
27c71ac451 fdcan: generate register blocks for message RAM 
this is a special case, as most data sources don't mention this as a
separate peripheral at all, and those that do don't handle the offsets
in the case of multiple FDCANS

H7 chips have a single 10KB block shared between all FDCANs
 2023-11-21 10:45:51 +00:00
Torin Cooper-Bennun
f65fd694e1 fdcan: fix register block definitions; separate version for H7 
the Cube XMLs refer to "fdcan_v1_0" and "fdcan_v1_1" but these seem to
have no bearing on the actual registers used. Thus chips.rs should make
no distinction between v1_0 and v1_1.

the previous YAML seems to have been generated from a G4 SVD, but this
series' SVDs consistently have several errata.

I have therefore replaced can_fdcan.yaml with can_fdcan_v1.yaml, built
from an H5 SVD which appears to match the RMs of G0, G4, H5 and L5
chips.

the H7 series has a totally different FDCAN, so I've added a separate
YAML for it.
 2023-11-21 10:45:51 +00:00
Adam Greig
be9d7fd584
H5: rename DAC12EN to DAC1EN to match peripheral name 2023-11-19 13:47:13 +00:00
Adam Greig
a0f7bc881a
WL5/WLE: rename DAC1EN to DACEN in RCC, per reference manual and peripheral name 2023-11-19 13:29:43 +00:00
Adam Greig
78232c013e
Rework DACs for all STM32 2023-11-19 04:51:20 +00:00
Adam Greig
82101c985c
DAC v1-4: Remove TSEL enum from TSEL fields, arrayify TSEL fields 2023-11-19 04:51:20 +00:00
Adam Greig
7ce7dc901f
Add DACv4 support for STM32G4 2023-11-19 04:51:19 +00:00
Dario Nieuwenhuis
fbb8f77326 rcc: consistency fixes on f2 2023-11-13 01:47:21 +01:00
Dario Nieuwenhuis
c551c07bf1 rcc: consistency fixes. 2023-11-13 01:00:53 +01:00
shakencodes
9ba39f0f2d Corrects name of enum/ADCSEL::PLLSAI1_R on smt32l5 2023-11-01 13:04:57 -07:00
shakencodes
445f314531 Add enum/ADCSET to rcc_l5.yaml 2023-11-01 12:39:09 -07:00
Dario Nieuwenhuis
bcc9b6bf9f rcc/wb: add misrange enum 2023-10-23 01:02:53 +02:00
Dario Nieuwenhuis
4ddcb77c9d rcc: rename NONE -> DISABLED 2023-10-23 00:30:16 +02:00
Dario Nieuwenhuis
b59a5c1812 rcc: add missing enums to wb, wl. 2023-10-23 00:30:16 +02:00
Dario Nieuwenhuis
ee64389697 Rename HSI16 -> HSI 2023-10-22 22:32:08 +02:00
xoviat
e20aed5f9a rcc/l4: fix dup enable 2023-10-20 18:43:56 -05:00
xoviat
e4b19a6fd9 rcc: fix l4 sw enum 2023-10-19 21:06:26 -05:00
Olle Sandberg
9f019bd9ba wwdg: register definitions for window watchdog v2 2023-10-19 14:49:41 +02:00
xoviat
8bd7ff51b0 rcc: expand checker to all chips 2023-10-18 21:01:57 -05:00
Dario Nieuwenhuis
5b04234fbe rcc: cleanup f4, f7 plls. 2023-10-18 05:08:14 +02:00
xoviat
3d9c8b70e3 rcc: check l4plus and l5 2023-10-17 17:21:06 -05:00
xoviat
c61495fd4e rcc: more cleanup 2023-10-17 16:57:33 -05:00
xoviat
fb84c0ac55 rcc: fixup clock names and expand checking 2023-10-16 17:53:26 -05:00
JackN
120168456f TSC: Add transform and new peripheral 2023-10-16 09:54:09 -04:00
Dario Nieuwenhuis
5ecc410f93 rcc/l5: cleanup 2023-10-16 03:56:19 +02:00
Dario Nieuwenhuis
73e3f8a965 rcc: separate L4 and L4+ 2023-10-16 03:11:00 +02:00
Dario Nieuwenhuis
f437c33b41 rcc/l5: unify clk48sel vs clk48msel 2023-10-16 01:37:21 +02:00
xoviat
b9a89a1851 rcc: cleanup variants and rename ahb -> clk 2023-10-15 18:01:50 -05:00
xoviat
8b8686a852 rcc: more mux and enum cleanup 2023-10-15 10:37:36 -05:00
xoviat
5d51e3b706 rcc: add more mux data 2023-10-14 17:20:25 -05:00
xoviat
68d77f487b rcc: add more mux data 2023-10-14 11:41:21 -05:00
xoviat
b14427f2d1 Merge branch 'main' of https://github.com/embassy-rs/stm32-data into rcc 2023-10-13 22:22:05 -05:00
xoviat
8a09bbb62c rcc: more cleanup 2023-10-13 22:20:18 -05:00
xoviat
e90a83a4f0
Merge pull request #281 from noppej/gfxmmu 
Add GFXMMU peripheral
 2023-10-14 02:26:15 +00:00
xoviat
aa5e909e11 rcc: more enum cleanup 2023-10-13 20:54:24 -05:00
JackN
53c636386b GFXMMU: New peripheral yamls 2023-10-13 17:12:57 -04:00
xoviat
c4cd46927d rcc: rename h5 clock enum variants and add check 2023-10-12 20:48:35 -05:00
JackN
019e802e27 OCTOSPI: Fix "MAXTRAN was in wrong yaml". 2023-10-12 18:52:50 -04:00
JackN
af1a5f5877 OCTOSPI: Merge peri yamls 2023-10-12 17:44:41 -04:00