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792 Commits

Author SHA1 Message Date
Joël Schulz-Ansres
8ec40e422c
Add DSIHOST support 2024-04-15 09:19:55 +02:00
Dario Nieuwenhuis
d4a97f60b1 Add stm32u0. 2024-04-13 03:16:25 +02:00
Dario Nieuwenhuis
b1034db59a
Merge pull request #463 from MaxiluxSystems/feature/product-states 
flash_h50: add PRODUCT_STATE enum; improve a couple other fields
 2024-04-12 19:38:24 +00:00
Torin Cooper-Bennun
62b1ab50db flash_h50: rename BKSEL variants 2024-04-12 17:04:33 +01:00
Torin Cooper-Bennun
4df4f6840c flash_h50: plain bool for SWAP_BANK fields 2024-04-12 17:03:44 +01:00
Torin Cooper-Bennun
a0c7c136fa flash_h50: add PRODUCT_STATE enum 
the values are taken from the official HAL headers; I have only included
enum variants which are definitively mentioned in RM0492, excluding
other variants mentioned in the HAL headers
 2024-04-11 10:25:07 +01:00
Torin Cooper-Bennun
f60ad0d665 flash_h50: make _CUR registers read-only 2024-04-11 10:24:55 +01:00
Dario Nieuwenhuis
604890b9ba hsem: rename more MASTERID->COREID 2024-04-08 14:07:46 +02:00
Michael Zill
b782384611 Arrayfied IER, ICR, ISR and MISR 
IRQ registers have for all 4 variants the same name.
V1 - array size = 2 (2 cores)
V2 - array size = 1 (1 core)
V3 - array size = 2 (2 cores)
V4 - array size = 1 (1 core)

HSEM added to GHOST_PERIS
 2024-04-08 13:38:36 +02:00
Michael Zill
840e5ec5db Fixed length COREID in v1, v2 renamed MASTERID to COREID 2024-04-08 13:36:40 +02:00
Michael Zill
e029a55f7a Arrayfied v2, v3, v4 - removed enums, aligned yaml structure 
The following list shows the different hsem yaml versions and the coresponding chips.

    wba is on purpose not included at is complex and very different from the others which will
    also make the HSEM implementation in the HAL more complex. I leave this out for another PR.

    h747
    wb55

    h735
    h7b3
    h753v
    h753
    h743
    h743v

    wl5x_cm0p
    wl5x_cm4

    wle5
 2024-04-08 13:36:40 +02:00
Michael Zill
bde330f46e Fixed C1ICR, C2ICR read/write 2024-04-08 13:36:40 +02:00
Michael Zill
d1f1f4bfeb Arrayfied v1 and v8 - preliminary fix for missing HSEM in Cube XML 2024-04-08 13:36:40 +02:00
Michael Zill
44967f3776 Initial add 2024-04-08 13:36:40 +02:00
David Lawrence
bef34f5e8a Add 8 and 16 bit wide SPI data registers 2024-04-05 14:07:39 -04:00
David Lawrence
d258cf858d Split STM32G4 flash peripheral by device category 2024-04-05 12:10:59 -04:00
Dario Nieuwenhuis
73ab4d3f67
Merge pull request #451 from eZioPan/lptim-v2 
lptim v2
 2024-04-05 11:28:05 +00:00
eZio Pan
16b4fd12c1 merge lptim CCMR output and input 
move overlap to field level
 2024-04-05 15:01:07 +08:00
qff233
a2c4423ed5 Fix DMA enum 2024-04-05 13:07:24 +08:00
qff233
408a20839a Fix serial registers for stm32g4 serial:q 2024-04-05 12:58:59 +08:00
eZio Pan
f789074a4b merge input mode and output mode 2024-04-05 12:36:35 +08:00
qff233
9dfb42cd91 Fix ADC sample_time enum for stm32g4 2024-04-05 01:39:04 +08:00
qff233
cf5ab0f41b Fix ADC resolution enum for stm32g4 2024-04-05 01:13:23 +08:00
eZio Pan
d9625637f2 add lptim_v2a to chips.rs 2024-04-05 00:06:01 +08:00
eZio Pan
8b036d7f87 add enum 2024-04-04 23:47:06 +08:00
eZio Pan
c25b401647 extract lptim_v2a from l5 2024-04-04 23:40:12 +08:00
eZio Pan
029320446b add lptim to u5 wba 2024-04-04 23:29:48 +08:00
eZio Pan
59cb83596f add to chips.rs 2024-04-04 23:04:21 +08:00
eZio Pan
8bd35deb56 add enum 2024-04-04 23:04:21 +08:00
eZio Pan
8bfe8b90f4 split lptim and bug fix ... 
LPTIM4 has less function, so it's a LPTIM_Basic, the reset are full feature, thus a LPTIM_Adv.
 2024-04-04 23:04:21 +08:00
eZio Pan
43e02bf3ec apply transform 2024-04-04 23:04:21 +08:00
eZio Pan
ac23a24b9b extract lptim_v2h5 from h573 lptim1 2024-04-04 23:04:21 +08:00
Karun Koppula
ad31d48657 Fix mislabeling for h7ab octospi rcc registers 2024-04-03 13:16:08 -04:00
Karun Koppula
c4be0da68c updated l4plus and l5 rcc registers 2024-04-02 15:05:12 -04:00
eZio Pan
a671657453 add enums 2024-04-01 13:20:00 +08:00
eZio Pan
187a8d68af apply transform 2024-03-31 17:14:34 +08:00
eZio Pan
b87360cd61 extract 2024-03-31 15:37:00 +08:00
eZio Pan
868dec1630 timer: add 16-bit register info 2024-03-13 01:11:26 +08:00
eZio Pan
cc525f1b25 timer: remove PSC fieldset 2024-03-13 01:06:29 +08:00
eZio Pan
f0532de10a cordic: add scale enum 2024-03-13 01:06:16 +08:00
eZio Pan
ec4e31491e update desc 2024-03-07 01:41:36 +08:00
eZio Pan
f0d4f717ea merge enums 2024-03-07 01:40:36 +08:00
Torin Cooper-Bennun
d1f376978d fix ADC, DAC clock muxes for H5, U5 
the clock selection bit is named ADCDACSEL, shared between all ADCs and
DACs
 2024-03-04 10:52:06 +00:00
Dario Nieuwenhuis
e7f91751fb rcc/c0: sysdiv doesn't exist. 2024-03-03 23:50:04 +01:00
Dario Nieuwenhuis
59bb84fbcb rcc/c0: fix HSI -> HSISYS/HSIKER 2024-03-03 23:50:04 +01:00
Dario Nieuwenhuis
448e82b56a rcc/c0: consistencify HSI48 -> HSI 2024-03-03 23:44:12 +01:00
Dario Nieuwenhuis
114c075601 rcc/g0: unify USARTxSEL 2024-03-03 23:43:23 +01:00
Dario Nieuwenhuis
6911e21bfd chiptool fmt. 2024-03-03 23:43:11 +01:00
Dario Nieuwenhuis
d67103f97f More accurate USB muxes. 2024-03-01 22:50:31 +01:00
eZio Pan
409019e987 add PGA_GAIN enum, rename OPAEN 2024-02-28 23:34:57 +08:00