xoviat
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3d9c8b70e3
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rcc: check l4plus and l5
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2023-10-17 17:21:06 -05:00 |
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xoviat
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c61495fd4e
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rcc: more cleanup
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2023-10-17 16:57:33 -05:00 |
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xoviat
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fb84c0ac55
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rcc: fixup clock names and expand checking
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2023-10-16 17:53:26 -05:00 |
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xoviat
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b9a89a1851
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rcc: cleanup variants and rename ahb -> clk
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2023-10-15 18:01:50 -05:00 |
|
xoviat
|
8b8686a852
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rcc: more mux and enum cleanup
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2023-10-15 10:37:36 -05:00 |
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Dario Nieuwenhuis
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ff45aa382e
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rcc: add more missing enums.
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2023-10-11 00:07:28 +02:00 |
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Dario Nieuwenhuis
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e89b8cfc30
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rcc: add PLL enums.
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2023-10-09 02:44:42 +02:00 |
|
Dario Nieuwenhuis
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6c73ffbd0b
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rcc: make naming consistent between "mco" and "mcosel".
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2023-10-07 00:46:19 +02:00 |
|
Dario Nieuwenhuis
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11256dc370
|
chiptool fmt.
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2023-10-07 00:09:14 +02:00 |
|
Matt Ickstadt
|
60d034f9fa
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RCC: unify LSEDRV enum variant names and descriptions
Now the only differences are the series which have swapped medium low/high bits: F0, F3v2, F3, F7, and H7_RM0433.
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2023-10-05 10:56:02 -05:00 |
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Dario Nieuwenhuis
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d6b0763327
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More rcc cleanups.
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2023-09-19 04:17:00 +02:00 |
|
Dario Nieuwenhuis
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8fec79a722
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rcc consistency fixes.
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2023-09-16 02:34:03 +02:00 |
|
Dario Nieuwenhuis
|
86fb0cfc2f
|
chiptool fmt.
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2023-09-16 02:34:03 +02:00 |
|
Don Reilly
|
dff9c321f3
|
readd DBGMCU back into F3 and F3v2
|
2023-08-07 15:04:18 -05:00 |
|
Don Reilly
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42273a7f02
|
rework f3 series rcc take 2
|
2023-08-07 14:38:22 -05:00 |
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