xoviat
3d9c8b70e3
rcc: check l4plus and l5
2023-10-17 17:21:06 -05:00
xoviat
c61495fd4e
rcc: more cleanup
2023-10-17 16:57:33 -05:00
xoviat
fb84c0ac55
rcc: fixup clock names and expand checking
2023-10-16 17:53:26 -05:00
xoviat
b9a89a1851
rcc: cleanup variants and rename ahb -> clk
2023-10-15 18:01:50 -05:00
xoviat
8b8686a852
rcc: more mux and enum cleanup
2023-10-15 10:37:36 -05:00
Dario Nieuwenhuis
ff45aa382e
rcc: add more missing enums.
2023-10-11 00:07:28 +02:00
Dario Nieuwenhuis
e89b8cfc30
rcc: add PLL enums.
2023-10-09 02:44:42 +02:00
Dario Nieuwenhuis
6c73ffbd0b
rcc: make naming consistent between "mco" and "mcosel".
2023-10-07 00:46:19 +02:00
Dario Nieuwenhuis
11256dc370
chiptool fmt.
2023-10-07 00:09:14 +02:00
Matt Ickstadt
60d034f9fa
RCC: unify LSEDRV enum variant names and descriptions
...
Now the only differences are the series which have swapped medium low/high bits: F0, F3v2, F3, F7, and H7_RM0433.
2023-10-05 10:56:02 -05:00
Dario Nieuwenhuis
d6b0763327
More rcc cleanups.
2023-09-19 04:17:00 +02:00
Dario Nieuwenhuis
8fec79a722
rcc consistency fixes.
2023-09-16 02:34:03 +02:00
Dario Nieuwenhuis
86fb0cfc2f
chiptool fmt.
2023-09-16 02:34:03 +02:00
Don Reilly
dff9c321f3
readd DBGMCU back into F3 and F3v2
2023-08-07 15:04:18 -05:00
Don Reilly
42273a7f02
rework f3 series rcc take 2
2023-08-07 14:38:22 -05:00
xoviat
4bbc7a3d12
rcc/f3: add hrtim clock
2023-07-06 20:12:22 -05:00
Dario Nieuwenhuis
3f01ff4545
Remove enum_read, enum_write.
2023-06-28 22:36:19 +02:00
Catherine
20034cc19a
Add support for DAC in STM32F3x that only have a single DAC.
2023-06-16 22:47:18 +00:00
Dario Nieuwenhuis
c2804abc9a
rcc: fix inconsistent naming.
2022-02-14 02:07:08 +01:00
Dario Nieuwenhuis
2c5e858584
chiptool fmt
2022-02-14 00:45:36 +01:00
Dario Nieuwenhuis
7b2df420ac
rcc: remove useless enums.
2022-02-14 00:26:46 +01:00
VasanthakumarV
fdf0cc95b9
[manual] Deduplicate PLLSRC entry of RCC_CFGR register
...
I have manually removed the single bit PLLSRC under RCC_CFGR register,
and I have manually updated the `enum/PLLSRC` to have 3 variants to match
the bit_size of PLLSRC.
2021-12-09 13:24:25 +05:30
Dario Nieuwenhuis
df6b1a13b0
rcc_f3: add lots of missing stuff.
2021-11-28 23:25:16 +01:00
Dario Nieuwenhuis
8534ae884d
rcc: make GPIO EN/RST regs naming consistent.
2021-08-19 23:50:42 +02:00
Dario Nieuwenhuis
6af9f2c0d1
Add RCC for F3, F7, G4, H7AB, L1, L5, WB*, WL5, WLE
2021-08-19 19:13:30 +02:00
