Jensenn
521417bbb0
make LCD display memory an array
2022-05-06 14:26:20 -06:00
Matous Hybl
f2498652f1
Clean-up F3 and F7 flash registers
2022-05-06 21:52:51 +02:00
Grant Miller
423a80a8f8
Fix ADCPRE descriptions
2022-05-01 19:31:43 -05:00
Grant Miller
ad6f5a5434
Clean up rcc_f1cl.yaml
2022-05-01 19:29:40 -05:00
Grant Miller
e905859bdf
Clean up rcc_f1.yaml
2022-05-01 19:28:29 -05:00
Grant Miller
d7674ab524
Create rcc_f100.yaml
2022-05-01 19:27:28 -05:00
Grant Miller
9ea9bd5215
Prevent crash if xENR exists but xRSTR doesn't
2022-05-01 19:20:48 -05:00
Dario Nieuwenhuis
c36a510e47
unify ETH vs ETHMAC in RCC regs.
2022-04-28 01:54:55 +02:00
Dario Nieuwenhuis
b8325a23ac
Merge pull request #142 from embassy-rs/generate-flash-settings
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Generate flash settings
2022-04-27 14:34:55 +02:00
Ulf Lilleengen
4535a98b19
Use the largest sector size
2022-04-27 14:20:29 +02:00
Ulf Lilleengen
bd97be07b3
Generate more flash settings
2022-04-27 13:25:48 +02:00
Matous Hybl
0c9329fe94
Add ADC3 common for H7s
2022-04-27 00:51:20 +02:00
Matous Hybl
a87cf34197
Add ADC registers for F1 and H7
2022-04-27 00:50:46 +02:00
Dario Nieuwenhuis
eff26e3e77
Add stm32u5 GPDMA, SPI
2022-04-26 23:53:28 +02:00
Dario Nieuwenhuis
bb6053d4ee
chiptool fmt
2022-04-26 21:16:00 +02:00
Dario Nieuwenhuis
6e8a2d8868
Merge pull request #141 from Gekkio/f2-spi
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Add SPI for F2 devices (spi2s1_v2_1)
2022-04-26 19:32:52 +02:00
Joonas Javanainen
ad291b5af3
Map spi2s1_v2_1 used on F2 devices
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This seems identical to v2_2 (as used by F429) with one naming exception
in status register SR bit 8 (TI frame format error):
v2_1 data names the bit "TIFRFE" and the enum TIFRERR
v2_2 data names the bit "FRE" and the enum FRER
The register bit layout is identical.
2022-04-26 20:24:36 +03:00
Dario Nieuwenhuis
2db5d47cc6
Merge pull request #140 from davidlenfesty/eth-v1a
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Generate support for ethernet v1a and v1b
2022-04-26 18:28:41 +02:00
Dario Nieuwenhuis
7e9d04b342
Merge pull request #139 from embassy-rs/stm32wl-flash
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Stm32wl flash
2022-04-26 18:18:13 +02:00
Ulf Lilleengen
afcd7a7d69
Rename flash_w[bl]55 flash_w[bl]
2022-04-26 18:17:09 +02:00
David Lenfesty
121e5bc92b
Generate ethernet peripherals for f2 and f4
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These are eth v1b, according to stm32-rs it should have the same register
changes as v1c, so I just copied it over.
2022-04-26 10:09:28 -06:00
David Lenfesty
05bf8c23c1
fix RCC MCO register for f1 CL variants
2022-04-26 10:04:50 -06:00
Ulf Lilleengen
83544cfdfc
Remove enums from l0 regs
2022-04-26 14:53:40 +02:00
Ulf Lilleengen
004542bf86
Add l0 flash support
2022-04-26 14:51:37 +02:00
Ulf Lilleengen
3dd39de946
Add flash for stm32wl
2022-04-26 14:51:37 +02:00
Jensenn
b7d299d2a8
Update perimap for LCD peripheral
2022-04-25 13:20:57 -06:00
Jensenn
9728ff7a95
Remove useless fieldsets in LCD display memory
2022-04-25 12:08:32 -06:00
Jensenn
974de5f19b
Add BUFEN field from l4xx devices
2022-04-25 12:05:36 -06:00
Jensenn
338c78b771
Add LCD register set from l100 device
2022-04-25 12:04:23 -06:00
David Lenfesty
a0368410a5
Add STM32F107 ethernet v1a peripheral
2022-04-21 17:05:23 -06:00
David Lenfesty
670f270c0a
add xmltodict requirement to README
2022-04-21 17:04:59 -06:00
Dario Nieuwenhuis
c01cb449e9
Add L5 PWR
2022-04-10 01:46:46 +02:00
Dario Nieuwenhuis
4c99f450b3
Merge pull request #138 from ant32/main
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add stm32l4 power registers
2022-04-09 20:53:33 +02:00
Philip A Reimer
13a9eebb52
add l4 pwr enums
2022-04-09 11:05:50 -06:00
Philip A Reimer
5f64d3d148
arrayify l4 power control registers
2022-04-09 11:05:50 -06:00
Philip A Reimer
e81eeb157e
add pwr_l4
2022-04-09 11:05:50 -06:00
Dario Nieuwenhuis
c90234583e
RCC: fix USBFS -> USB
2022-04-09 00:43:48 +02:00
Dario Nieuwenhuis
6107d5a72e
Add USB
2022-04-09 00:28:44 +02:00
Dario Nieuwenhuis
b5d84de6e6
L5: add FLASH, SYSCFG
2022-04-08 02:54:56 +02:00
Dario Nieuwenhuis
eb678443a3
L5: fix RCC
2022-04-08 02:54:37 +02:00
Dario Nieuwenhuis
1d5853be40
run chiptool fmt with new version that trims descriptions.
2022-04-08 01:17:53 +02:00
Dario Nieuwenhuis
b797baeb14
Merge pull request #136 from ant32/main
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Use OTG v1 for v3
2022-03-30 01:27:02 +02:00
Dario Nieuwenhuis
e130607888
Merge pull request #137 from chemicstry/timer_regs
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Add missing timer ITR3 field
2022-03-30 01:01:32 +02:00
chemicstry
1d9e453670
Add missing timer ITR3 field
2022-03-30 01:59:08 +03:00
Philip A Reimer
62ebc483f9
use otg v1 for v3
2022-03-28 22:37:11 -06:00
Dario Nieuwenhuis
9838bd78f3
Merge pull request #135 from ant32/main
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WIP: add usb registers to l4r5
2022-03-26 18:53:45 +01:00
Philip A Reimer
55163d5857
Add OTG FS v3
2022-03-24 21:16:11 -06:00
Dario Nieuwenhuis
ecad66103f
Merge pull request #134 from nviennot/otg
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Add USB_OTG_FS registers
2022-03-22 17:11:27 +01:00
Nicolas Viennot
4ed9a42360
Add OTG register definitions
2022-03-20 19:07:24 -04:00
Dario Nieuwenhuis
b5ffa60b5f
Merge pull request #133 from nviennot/fsmc
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FSMC register block
2022-03-20 21:01:20 +01:00
