Philip A Reimer
55163d5857
Add OTG FS v3
2022-03-24 21:16:11 -06:00
Nicolas Viennot
4ed9a42360
Add OTG register definitions
2022-03-20 19:07:24 -04:00
Dario Nieuwenhuis
b5ffa60b5f
Merge pull request #133 from nviennot/fsmc
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FSMC register block
2022-03-20 21:01:20 +01:00
Dario Nieuwenhuis
6ee54e8bf1
Merge pull request #131 from chemicstry/f4_uart
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Fix F4 UART definitions
2022-03-20 21:00:04 +01:00
Dario Nieuwenhuis
d5b53707d0
Merge pull request #132 from Gekkio/improve-f2-support
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F2: Add SYSCFG/FLASH/PWR, fix DBGMCU SVD typos
2022-03-20 20:59:33 +01:00
Dario Nieuwenhuis
ca8f4b3e0d
Merge pull request #130 from chemicstry/sdio_fix2
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Unify SDMMC v1 and v2 register names
2022-03-20 20:52:20 +01:00
Dario Nieuwenhuis
5c2ec818f6
Merge pull request #129 from nviennot/timer_clock
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Timers use the clock speed apb1_tim and apb2_tim
2022-03-20 20:51:45 +01:00
Nicolas Viennot
f9301d42f0
Add the FSMC register block
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The current v1 yaml has a few extra registers defined that don't belong to
some of the chips out there (the ones at byte_offset 320 and above), but
the rest of registers are identical.
2022-03-18 23:41:56 -04:00
Joonas Javanainen
f622be8f03
Add PWR block for F2
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Verified using RM0033 (F205xx/F207xx/F215xx/F217xx) Rev 9
2022-03-17 21:44:23 +02:00
Joonas Javanainen
e36b972e3c
Add FLASH block for F2
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Verified using PM0059 Programming manual (F205/215, F207/217) Rev 5
2022-03-17 21:32:59 +02:00
Joonas Javanainen
b47951b4a2
Add SYSCFG block for F2
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Verified using RM0033 (F205xx/F207xx/F215xx/F217xx) Rev 9
2022-03-17 21:32:37 +02:00
chemicstry
0f80d10a1f
Fix F4 UART parsing
2022-03-17 16:33:34 +02:00
chemicstry
caa613eab2
Unify SDMMC register names
2022-03-16 18:40:36 +02:00
Nicolas Viennot
b3f9f3e286
Timers use the clock speed apb1_tim and apb2_tim
2022-03-15 02:55:33 -04:00
Nicolas Viennot
2cd7632fc9
Add SPI modules for F1 family
2022-03-15 02:51:18 -04:00
Grant Miller
ea9e59931f
Don't rename DMA channels if they don't start at zero
2022-03-08 16:18:24 -06:00
Grant Miller
a1972e7a22
Create tmp/dmas/ if it doesn't exist
2022-03-08 15:53:16 -06:00
Matthew W. Samsonoff
1a4706a799
stm32g0: add registers for FLASH
2022-03-02 11:27:38 -05:00
Dario Nieuwenhuis
ce7ba764c9
fix multicore nvic
2022-02-25 01:14:39 +01:00
Dario Nieuwenhuis
8a935d22e5
Fix parsing of H7ab BDMA1/BDMA2
2022-02-24 05:55:16 +01:00
Dario Nieuwenhuis
66ecaf8b98
rcc: unify rcc_f0, rcc_f0x0
2022-02-14 00:25:12 +01:00
Dario Nieuwenhuis
3d6895a77f
Rename clocks AHB -> AHB1, APB -> APB1.
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This makes it more consistent across chips, no more "AHB vs AHB1" issues.
2022-02-13 23:22:10 +01:00
Dario Nieuwenhuis
8402b43853
remove 'registers' nested struct in rcc
2022-02-07 23:12:40 +01:00
Dario Nieuwenhuis
5365ea053a
split "magic" block string into an object, so consumers don't have to do tricky parsing.
2022-02-07 23:12:40 +01:00
Dario Nieuwenhuis
32b5a815c6
change memory regions from dict to array
2022-02-07 20:37:35 +01:00
Dario Nieuwenhuis
00fc25453d
switch chip files from yaml to json. remove OrderedDict.
2022-02-07 02:06:23 +01:00
Dario Nieuwenhuis
7b368b0035
move memory parsing to own file
2022-02-07 02:06:23 +01:00
Dario Nieuwenhuis
48fdf50203
Change peripherals from dict to array
2022-02-07 02:05:30 +01:00
Dario Nieuwenhuis
d8b8bac3a5
change dma channels from dict to array
2022-02-07 02:05:30 +01:00
Dario Nieuwenhuis
f07c93a64a
change chip interrupts from dict to array
2022-02-07 02:05:30 +01:00
Dario Nieuwenhuis
2a14936a5e
Split interrupt parsing to separate module
2022-02-05 01:45:34 +01:00
Dario Nieuwenhuis
048f6766fd
lpuart: cleanup v1, v2. Merge v2 and v3
2022-02-05 00:59:20 +01:00
Maarten Oosting
e5da7538e1
LPUART: append lpuart peripherals to perimap
2022-02-05 00:59:20 +01:00
chemicstry
432619467f
Fix encoding on windows
2022-02-04 15:49:56 +02:00
chemicstry
f1d0a09b79
Fix USB OTG pin AF parsing
2022-02-04 02:32:39 +02:00
chemicstry
8e1a07b928
Fix peripheral names with underscores
2022-02-04 01:49:39 +02:00
chemicstry
ce95fe0ac5
Fix path separators on windows
2022-02-04 01:47:29 +02:00
Dario Nieuwenhuis
11290fd274
rcc: make GPIOxEN/IOPxEN consistent.
2022-01-24 02:13:24 +01:00
Greg V
76572f3d55
Add flash for STM32L1
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NOTE: named 'Flash' instead of 'FLASH' in SVD
2022-01-14 16:50:35 +03:00
Dario Nieuwenhuis
e5e7e26d05
Fix duplicated irqn in stm32f100
2022-01-06 16:30:33 +01:00
Dominik Boehi
bb6321bc87
Extract flash information for STM32WB by looking for FLASH_REG_BASE define
2022-01-04 19:38:05 +01:00
Dominik Boehi
d8189255fa
Add Flash, RTC, PWR for STM32WB55, fix IPCC CPU registers
2022-01-04 18:52:34 +01:00
Dario Nieuwenhuis
36e6571960
Add exception for STM32WL SUBGHZSPI naming.
2022-01-01 12:05:51 +01:00
Dario Nieuwenhuis
398fb17bf4
Ignore EXTIx signals in ADCs.
2022-01-01 11:28:02 +01:00
Nikita Strygin
d50f6b4676
Use signals from MCU xml
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Use MCU xml as a source of truth for signal and pin assignments
This has some nice side-effects as exposing analog signals without
handling them as special cases and not having __some__ (or maybe all)
pins not exposed in the chip package occur in the yamls
But the most useful part probably is the better support for F1 series,
which don't have all pins defined in GPIO due to not being remappable
2022-01-01 10:52:39 +01:00
Dario Nieuwenhuis
8e9e8522d1
Sort analog pins
2022-01-01 10:51:45 +01:00
Sjoerd Simons
2616e499c6
Recognize ADC on STM32F1xx
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Translate the ADC block available in the F1 family to adc_f1
2021-12-29 15:50:38 +01:00
Dario Nieuwenhuis
73902044de
Fix typo
2021-12-23 20:32:39 +01:00
VasanthakumarV
a5008c71d5
[manual] Map register blocks to timers for F3 chips
2021-12-23 16:10:22 +05:30
Dario Nieuwenhuis
0e9fa2f438
Merge pull request #109 from VasanthakumarV/f3-registers
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Add `SYSCFG`, `PWR`, `FLASH` and `SPI` registers for `STM32F3`
2021-12-16 08:12:07 +01:00
