7 Commits

Author SHA1 Message Date
Dario Nieuwenhuis
1cfb795d6b Fix accidental arrayifications. 2023-06-29 00:57:25 +02:00
Dario Nieuwenhuis
0d958def0e chiptool fmt. 2023-06-28 22:22:17 +02:00
Cliff L. Biffle
b93e9286d3 G0/C0: fix SYSCFG.CFGR1.MEM_MODE definition
- Added docs from reference manual / fixed existing partial copy of
  reference manual docs
- Renamed System Flash case to SYSTEM_FLASH because FLASH was ambiguous
  (you really don't want to activate the System Flash when you wanted
  Main Flash, where your program lives!)
- Added Main Flash case.
2023-06-28 10:06:46 -07:00
Cliff L. Biffle
3d86ef6d30 G0 SYSCFG: fix PA11/PA12 RMP definitions
It looks like the G0 file here picked up the F0-style "one remapping bit
for both pins" field definition. The G0 series actually has C0-style
dual remapping bits.
2023-06-28 08:50:53 -07:00
Dario Nieuwenhuis
1d97fa1f80 Some g0 reg fixups. 2023-01-17 18:37:22 +01:00
Dario Nieuwenhuis
c6c5c099bb fmt all register yamls 2021-11-17 21:23:26 +01:00
Ben Gamari
f57a268b9f Add STM32G0 support
Includes manually specified register layouts for EXTI and SYSCFG.
2021-08-19 15:57:00 +02:00