guangzong/stm32-data
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309 Commits

Author SHA1 Message Date
Süha
6f0aff1df4
Correct flash size for g03 and g04 2024-04-17 22:18:34 +08:00
Dario Nieuwenhuis
9db1729024
Merge pull request #468 from Systemscape/main 
Add DSIHOST support
 2024-04-17 10:08:21 +00:00
Dario Nieuwenhuis
0e2a82de8d
Merge pull request #456 from eZioPan/lptim 
rework on LPTIM
 2024-04-17 10:03:22 +00:00
Dion Dokter
e44b6798dc Clean up ADC 2024-04-16 16:42:50 +02:00
Dion Dokter
50f329f131 Add opamp and rtc 2024-04-16 14:44:38 +02:00
JuliDi
804326f93f
add dsihost for u5 chip family 2024-04-15 09:20:50 +02:00
JuliDi
95ff92f362
remove DSISEL from other register ymls where it is not present 2024-04-15 09:20:50 +02:00
JuliDi
c8a3e8875d
add DSI as fallback for DSIHOST in stm32-data-gen rcc.rs 2024-04-15 09:20:50 +02:00
Joël Schulz-Ansres
8ec40e422c
Add DSIHOST support 2024-04-15 09:19:55 +02:00
Dion Dokter
a4d4695635 Add aes, crc, tsc and comp 2024-04-14 02:01:06 +02:00
Dion Dokter
7b08f67dfb Add ADC which is basically the G0 adc but not really 2024-04-14 00:04:06 +02:00
Dion Dokter
8490e2c8c9 Add rng, dac, crs, and usb 2024-04-13 18:39:00 +02:00
eZio Pan
471c377368 clippy fix 2024-04-13 23:36:32 +08:00
eZio Pan
510f269a69 add lptim_v2b for u0 2024-04-13 23:36:32 +08:00
eZio Pan
0d43029663 lptim_v1 for l0 2024-04-13 23:27:11 +08:00
eZio Pan
d2fcff2e5e lptim_v1a for l4(no plus), f4, f7 2024-04-13 23:27:11 +08:00
eZio Pan
096616ceda lptim_v1b for l4+, g0, wb 2024-04-13 23:27:11 +08:00
eZio Pan
e90a3f9246 lptim_v1b_g4 for g4 2024-04-13 23:27:11 +08:00
eZio Pan
14301aa848 lptim_v1b_h7 for h7 2024-04-13 23:27:11 +08:00
eZio Pan
c3fb098274 lptim_v1c for l5 wl 2024-04-13 23:27:11 +08:00
eZio Pan
af7aefa4fe keep lptim_v2 and remove others 2024-04-13 23:26:04 +08:00
Dario Nieuwenhuis
0c4baf4783 Remove a few zero-sized memory regions that are breaking memory.x generation. 2024-04-13 03:27:35 +02:00
Dario Nieuwenhuis
d4a97f60b1 Add stm32u0. 2024-04-13 03:16:25 +02:00
Warren Campbell
af9e902172 Corrects STM32U5 memory sizes 2024-04-11 18:04:35 -04:00
Dario Nieuwenhuis
8e26f36a8e Manually maintain memory maps instead of parsing them from cubeprogdb. 
First step towards fixing #301

The cubeprogdb has turned out to be a quite bad data source. It's not granular
enough (it has one entry per chip die, not per chip) so the previous code joined
the data with the C headers and cubedb to fill in the gaps, essentialy "guessing"
stuff. This has been quite error prone (see #301) and hard to make fixes to.

Instead, we're going to manually maintain memory maps in a .rs file. This way, if
something is wrong we can simply go and fix it.

This commit just migrates the existing data, even if it's wrong. (it does fix
a few very minor mistakes). Next steps is actually fixing the memory maps.
 2024-04-09 03:38:33 +02:00
Dario Nieuwenhuis
9d3d5c9690 Sort memory regions by addr. 2024-04-09 02:43:44 +02:00
Dario Nieuwenhuis
4e3ed9abee Remove OTP from memory map. 2024-04-09 02:19:17 +02:00
Michael Zill
b782384611 Arrayfied IER, ICR, ISR and MISR 
IRQ registers have for all 4 variants the same name.
V1 - array size = 2 (2 cores)
V2 - array size = 1 (1 core)
V3 - array size = 2 (2 cores)
V4 - array size = 1 (1 core)

HSEM added to GHOST_PERIS
 2024-04-08 13:38:36 +02:00
Michael Zill
e029a55f7a Arrayfied v2, v3, v4 - removed enums, aligned yaml structure 
The following list shows the different hsem yaml versions and the coresponding chips.

    wba is on purpose not included at is complex and very different from the others which will
    also make the HSEM implementation in the HAL more complex. I leave this out for another PR.

    h747
    wb55

    h735
    h7b3
    h753v
    h753
    h743
    h743v

    wl5x_cm0p
    wl5x_cm4

    wle5
 2024-04-08 13:36:40 +02:00
Michael Zill
6ba934d366 Remote debug code 2024-04-08 13:36:40 +02:00
Michael Zill
d1f1f4bfeb Arrayfied v1 and v8 - preliminary fix for missing HSEM in Cube XML 2024-04-08 13:36:40 +02:00
Michael Zill
44967f3776 Initial add 2024-04-08 13:36:40 +02:00
eZio Pan
60398cad51 move "UID" to "GHOST_PERIS" 2024-04-06 22:07:19 +08:00
David Lawrence
d258cf858d Split STM32G4 flash peripheral by device category 2024-04-05 12:10:59 -04:00
Dario Nieuwenhuis
73ab4d3f67
Merge pull request #451 from eZioPan/lptim-v2 
lptim v2
 2024-04-05 11:28:05 +00:00
qff233
cf5ab0f41b Fix ADC resolution enum for stm32g4 2024-04-05 01:13:23 +08:00
eZio Pan
d9625637f2 add lptim_v2a to chips.rs 2024-04-05 00:06:01 +08:00
eZio Pan
029320446b add lptim to u5 wba 2024-04-04 23:29:48 +08:00
eZio Pan
59cb83596f add to chips.rs 2024-04-04 23:04:21 +08:00
Romain Goyet
e7b493c058 Add TSC support for STM32WBA 2024-04-02 20:30:35 -04:00
Adam Greig
544184c70e
rcc: add override so SAI23SEL is used 2024-03-09 18:53:48 +00:00
Torin Cooper-Bennun
d1f376978d fix ADC, DAC clock muxes for H5, U5 
the clock selection bit is named ADCDACSEL, shared between all ADCs and
DACs
 2024-03-04 10:52:06 +00:00
Dario Nieuwenhuis
59bb84fbcb rcc/c0: fix HSI -> HSISYS/HSIKER 2024-03-03 23:50:04 +01:00
Dario Nieuwenhuis
d67103f97f More accurate USB muxes. 2024-03-01 22:50:31 +01:00
Dario Nieuwenhuis
d7462d805e
Merge pull request #432 from caleb-garrett/cryp 
CRYP perimap order
 2024-02-29 15:17:40 +00:00
Caleb Garrett
c6e42fff7c Correct CRYP perimap order. 2024-02-27 10:57:20 -05:00
eZio Pan
81d3b42d80 rename 2024-02-27 20:12:05 +08:00
eZio Pan
147d16f2e6 add to chips.rs 2024-02-27 20:03:37 +08:00
Dario Nieuwenhuis
0e12074b14
Merge pull request #427 from eZioPan/comp_h 
COMP for H7 and H5
 2024-02-27 11:10:30 +00:00
eZio Pan
4e8b96a7f0 add to chips.rs 2024-02-27 11:34:13 +08:00