guangzong/stm32-data
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811 Commits

Author SHA1 Message Date
Dario Nieuwenhuis
8534ae884d rcc: make GPIO EN/RST regs naming consistent. 2021-08-19 23:50:42 +02:00
Dario Nieuwenhuis
3b6363dffb wl rcc: rename SPI2S2 -> SPI2 2021-08-19 22:37:07 +02:00
Dario Nieuwenhuis
49e579e97f Add F2 RCC 2021-08-19 22:12:39 +02:00
Dario Nieuwenhuis
e289dd883f Cleanup EXTI 2021-08-19 21:54:22 +02:00
Dario Nieuwenhuis
701ab04c2a Cleanup SYSCFG naming 2021-08-19 21:28:32 +02:00
Dario Nieuwenhuis
31997049ea Fix wrong register offsets in WB SYSCFG 2021-08-19 19:20:13 +02:00
Dario Nieuwenhuis
6af9f2c0d1 Add RCC for F3, F7, G4, H7AB, L1, L5, WB*, WL5, WLE 2021-08-19 19:13:30 +02:00
Ben Gamari
f57a268b9f Add STM32G0 support 
Includes manually specified register layouts for EXTI and SYSCFG.
 2021-08-19 15:57:00 +02:00
Ben Gamari
f5808de749 Add RCC support for STM32G0 2021-08-19 15:54:36 +02:00
Ulf Lilleengen
919a61e847 Add STM32WL5x exti block 2021-08-17 13:02:49 +02:00
Bob McWhirter
541091cded Include the reg block. 2021-08-16 15:12:17 -04:00
Timo Kröger
198e4f3247 Add bxcan registers 2021-08-06 11:52:47 +02:00
Timo Kröger
7506b50031 rcc_l4: Remove duplicate bits 2021-08-03 16:33:59 +02:00
Timo Kröger
f865878b4b rcc_f4: Fix RCC bits 
## LPTIM1EN / LPTIMER1EN

Only stm32f413 has LPTIM1 peripheral, ref manual bit names:
LPTIMER1EN, LPTIMER1RST, LPTIMER1LPEN, LPTIMER1SEL

action: Rename to LPTIM1(EN|RST|...) for consistency (matches peripheral name)

## FMC / FSMC

not available as peripheral in the YAML anyway.. TODO: why?

EN and RST

FSMC: f405, f407, f412, f413
FSC: f427, f429, f446, f469

action: none

## CECEN / CAN3EN

mutually exclusive peripherals, alias ok?

CECEN: f446
CAN3EN: f413

action: split off f4x3 yaml, f423 exists, but not available as svd

## USART / UART

all over the place, register names in ref manual not always consistent
stm32 follows a simple rule for the actual peripherals:
USART 1-3, 6
UART 4, 5, 7-10

action: rename enable/rst bits to rules above
 2021-08-03 14:55:36 +02:00
Timo Kröger
babbe782f3 rcc_l0: Remove non existing RCC bits 
## firewall

l0x0, l0x1: FWEN - Firewall clock enable bit
l0x2, l0x3: MIFIEN - MiFaRe Firewall clock enable bit
action: none

## watchdog

peripheral: WWDG
WWDGRST vs WWDRST
action: remove

## CRS vs CRC

l0x2, l0x3: CRC reset is wrong
action: remove duplicate CRC bit

## LPUART12RST vs USART2RST

action: rename, it sholud be USART2
 2021-08-03 14:31:36 +02:00
Timo Kröger
d1597c646d rcc_l0: Remove duplicate I2C3 reset bit 2021-08-03 10:55:51 +02:00
Timo Kröger
ded4f52051 rcc_f4: Remove duplicate USBF bit 2021-08-03 10:55:51 +02:00
Bob McWhirter
83f5b39ecb Parse memory names slightly better from the XML. 2021-08-02 11:06:26 -04:00
Bob McWhirter
99cd26c33f Parse memory layouts for actual region sizes. 2021-08-02 11:06:25 -04:00
Timo Kröger
c02e3dc9ab Split f410 and f4 RCC yamls 
f410 has the RNGEN at a different position
 2021-07-31 17:40:30 +02:00
Timo Kröger
074aad8a66 Remove invalid bits from F4, L4 RCC 2021-07-30 17:35:52 +02:00
Thales Fragoso
02b44906c9 Add F4 PWR 2021-07-28 19:14:39 -03:00
Dario Nieuwenhuis
0bbd7c2d31 Merge pull request #67 from embassy-rs/f4-flash 
Add F4 FLASH
 2021-07-28 11:45:51 +02:00
Thales Fragoso
d53b964978 Add F4 FLASH 2021-07-27 21:53:08 -03:00
Grant Miller
d80e5e736c Remove trivial enums 2021-07-27 12:11:36 -05:00
Grant Miller
369401ca07 Add F1 RCC 2021-07-27 12:11:25 -05:00
Dario Nieuwenhuis
60b4b7d155 Add dmamux yamls, use them instead of xml/c parsing. 2021-07-17 07:23:48 +02:00
Bob McWhirter
02dd4e13f2 Parse in the dma HAL headers for the actual request numbers. 
Then apply them to fix up where possible because the XML is crap.
 2021-07-16 13:44:40 -04:00
Dario Nieuwenhuis
134d22af37 Add H7 SMPS 2021-07-16 00:38:49 +02:00
Dario Nieuwenhuis
ac29cdf3cd Add write-only access to TDR 2021-07-15 00:47:27 +02:00
Dario Nieuwenhuis
48b70bdf76 Merge USARTv2 and USARTv3, they're identical. 2021-07-15 00:20:17 +02:00
Dario Nieuwenhuis
7112b12a9d Cleanup USARTv2 regs. 2021-07-15 00:12:08 +02:00
Bob McWhirter
9040fafc33 Ensure the RCC reg is named DMA1EN and not just DMAEN 2021-07-12 15:55:13 -04:00
Bob McWhirter
2c3dfeb352 Reparse to include UART. 2021-06-30 14:36:04 -04:00
Bob McWhirter
c48e894dbe USART v3 reg block. 2021-06-30 13:31:48 -04:00
Bob McWhirter
3bfe1bdee5 Rename some USART regs, needs more work. 2021-06-29 10:52:44 -04:00
Dario Nieuwenhuis
a4902ab5c3 dmamux: merge CSR and CFR 2021-06-23 04:17:18 +02:00
Dario Nieuwenhuis
ac9c476561 Split DMA/BDMA into v1 (no selection) and v2 (has request selection). 2021-06-23 04:02:06 +02:00
Dario Nieuwenhuis
e3c6e44b76 Rename DMAv1 to BDMA, to allow DMA and BDMA to coexist in H7 2021-06-23 02:47:27 +02:00
Dario Nieuwenhuis
d260d9f2cf remove gpio_af 2021-06-23 02:34:00 +02:00
Dario Nieuwenhuis
29f70ac45f Add DMAMUX 2021-06-23 02:30:55 +02:00
Thales Fragoso
6656c5c059 Add F0 syscfg 2021-06-22 23:53:50 +02:00
Thales Fragoso
26e4f541ba Add F0 FLASH 2021-06-22 23:53:50 +02:00
Thales Fragoso
ae8455a336 Add F0 RCCs 2021-06-22 23:53:37 +02:00
Dominik Boehi
51395f941a Use arrays and blocks for everything in EXTI 2021-06-21 19:13:26 +02:00
Dominik Boehi
481e607977 Add IPCC peripheral to STM32WB55 2021-06-21 19:13:24 +02:00
Dominik Boehi
454854d527 Add EXTI for STM32WB55 2021-06-21 19:12:00 +02:00
Dario Nieuwenhuis
77d4ae203b Add DBGMCU for all chips 2021-06-21 01:27:36 +02:00
Ulf Lilleengen
3ef6421aa8 Add more peripherals for wl5x 2021-06-16 16:07:00 +02:00
Ulf Lilleengen
9161dbcac9 Regenerate with dual core support 
* Add support for WL55 chip family
 2021-06-16 15:10:42 +02:00