Karun Koppula
1ab47a96b4
Update rcc config for l0 family tsc
2024-04-22 12:53:23 -04:00
Dario Nieuwenhuis
e2c7a7eae0
rcc: fix tons of wrong muxes.
2024-02-16 00:11:14 +01:00
Dario Nieuwenhuis
d04eaeb0d5
Rename ICSEL -> I2CSEL
2024-02-05 00:42:54 +01:00
Dario Nieuwenhuis
c551c07bf1
rcc: consistency fixes.
2023-11-13 01:00:53 +01:00
Dario Nieuwenhuis
ee64389697
Rename HSI16 -> HSI
2023-10-22 22:32:08 +02:00
xoviat
8bd7ff51b0
rcc: expand checker to all chips
2023-10-18 21:01:57 -05:00
xoviat
c61495fd4e
rcc: more cleanup
2023-10-17 16:57:33 -05:00
xoviat
fb84c0ac55
rcc: fixup clock names and expand checking
2023-10-16 17:53:26 -05:00
xoviat
8b8686a852
rcc: more mux and enum cleanup
2023-10-15 10:37:36 -05:00
Dario Nieuwenhuis
f40f5a40c1
Not all L0s have HSI48/CRS.
2023-10-11 01:21:26 +02:00
Matt Ickstadt
60d034f9fa
RCC: unify LSEDRV enum variant names and descriptions
...
Now the only differences are the series which have swapped medium low/high bits: F0, F3v2, F3, F7, and H7_RM0433.
2023-10-05 10:56:02 -05:00
Dario Nieuwenhuis
86fb0cfc2f
chiptool fmt.
2023-09-16 02:34:03 +02:00
Dario Nieuwenhuis
c2804abc9a
rcc: fix inconsistent naming.
2022-02-14 02:07:08 +01:00
Dario Nieuwenhuis
2c5e858584
chiptool fmt
2022-02-14 00:45:36 +01:00
Dario Nieuwenhuis
7b2df420ac
rcc: remove useless enums.
2022-02-14 00:26:46 +01:00
Dario Nieuwenhuis
11290fd274
rcc: make GPIOxEN/IOPxEN consistent.
2022-01-24 02:13:24 +01:00
Dario Nieuwenhuis
0f04776eaa
rcc: l0, l1, l4: add missing enums.
2022-01-04 23:56:52 +01:00
Dario Nieuwenhuis
c6c5c099bb
fmt all register yamls
2021-11-17 21:23:26 +01:00
Dario Nieuwenhuis
8534ae884d
rcc: make GPIO EN/RST regs naming consistent.
2021-08-19 23:50:42 +02:00
Timo Kröger
babbe782f3
rcc_l0: Remove non existing RCC bits
...
## firewall
l0x0, l0x1: FWEN - Firewall clock enable bit
l0x2, l0x3: MIFIEN - MiFaRe Firewall clock enable bit
action: none
## watchdog
peripheral: WWDG
WWDGRST vs WWDRST
action: remove
## CRS vs CRC
l0x2, l0x3: CRC reset is wrong
action: remove duplicate CRC bit
## LPUART12RST vs USART2RST
action: rename, it sholud be USART2
2021-08-03 14:31:36 +02:00
Timo Kröger
d1597c646d
rcc_l0: Remove duplicate I2C3 reset bit
2021-08-03 10:55:51 +02:00
Bob McWhirter
9040fafc33
Ensure the RCC reg is named DMA1EN and not just DMAEN
2021-07-12 15:55:13 -04:00
Ulf Lilleengen
c1aae8d3d8
Run through transform again
2021-06-07 12:22:09 +02:00
Ulf Lilleengen
fea5e31f8b
Regen and remove *ON enums
2021-06-03 15:13:46 +02:00
Ulf Lilleengen
529b991404
Do merge
2021-06-03 14:31:27 +02:00
Ulf Lilleengen
18a99a3a3b
Add RCC register for STM32F4 and STM32L4
...
Register block based in STM32F427ZI and STM32L4R9.
Use bool for reset registers.
Define clock mapping for RNG peripherals. There are no 1 <-> 1 mapping
of RNG peripheral to clock in the Cubedb sources. The mapping will
pre-select the clock source for RNG for now.
2021-06-03 11:33:24 +02:00
Ulf Lilleengen
9ad584c149
Remove enums from enable registers
...
Add transform for RCC
2021-06-02 16:32:43 +02:00
Ulf Lilleengen
2ff87b75ce
Add RCC register block for STM32L0
2021-05-20 13:26:25 +02:00
