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stm32-data/data/registers/rcc_l0.yaml
Ulf Lilleengen 18a99a3a3b Add RCC register for STM32F4 and STM32L4 
Register block based in STM32F427ZI and STM32L4R9.

Use bool for reset registers.

Define clock mapping for RNG peripherals. There are no 1 <-> 1 mapping
of RNG peripheral to clock in the Cubedb sources. The mapping will
pre-select the clock source for RNG for now.
2021-06-03 11:33:24 +02:00

1536 lines
38 KiB
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---
block/RCC:
description: Reset and clock control
items:
- name: CR
description: Clock control register
byte_offset: 0
fieldset: CR
- name: ICSCR
description: Internal clock sources calibration register
byte_offset: 4
fieldset: ICSCR
- name: CRRCR
description: Clock recovery RC register
byte_offset: 8
fieldset: CRRCR
- name: CFGR
description: Clock configuration register
byte_offset: 12
fieldset: CFGR
- name: CIER
description: Clock interrupt enable register
byte_offset: 16
access: Read
fieldset: CIER
- name: CIFR
description: Clock interrupt flag register
byte_offset: 20
access: Read
fieldset: CIFR
- name: CICR
description: Clock interrupt clear register
byte_offset: 24
access: Read
fieldset: CICR
- name: IOPRSTR
description: GPIO reset register
byte_offset: 28
fieldset: IOPRSTR
- name: AHBRSTR
description: AHB peripheral reset register
byte_offset: 32
fieldset: AHBRSTR
- name: APB2RSTR
description: APB2 peripheral reset register
byte_offset: 36
fieldset: APB2RSTR
- name: APB1RSTR
description: APB1 peripheral reset register
byte_offset: 40
fieldset: APB1RSTR
- name: IOPENR
description: GPIO clock enable register
byte_offset: 44
fieldset: IOPENR
- name: AHBENR
description: AHB peripheral clock enable register
byte_offset: 48
fieldset: AHBENR
- name: APB2ENR
description: APB2 peripheral clock enable register
byte_offset: 52
fieldset: APB2ENR
- name: APB1ENR
description: APB1 peripheral clock enable register
byte_offset: 56
fieldset: APB1ENR
- name: IOPSMEN
description: GPIO clock enable in sleep mode register
byte_offset: 60
fieldset: IOPSMEN
- name: AHBSMENR
description: AHB peripheral clock enable in sleep mode register
byte_offset: 64
fieldset: AHBSMENR
- name: APB2SMENR
description: APB2 peripheral clock enable in sleep mode register
byte_offset: 68
fieldset: APB2SMENR
- name: APB1SMENR
description: APB1 peripheral clock enable in sleep mode register
byte_offset: 72
fieldset: APB1SMENR
- name: CCIPR
description: Clock configuration register
byte_offset: 76
fieldset: CCIPR
- name: CSR
description: Control and status register
byte_offset: 80
fieldset: CSR
fieldset/AHBENR:
description: AHB peripheral clock enable register
fields:
- name: DMAEN
description: DMA clock enable bit
bit_offset: 0
bit_size: 1
- name: MIFEN
description: NVM interface clock enable bit
bit_offset: 8
bit_size: 1
- name: CRCEN
description: CRC clock enable bit
bit_offset: 12
bit_size: 1
- name: TOUCHEN
description: Touch Sensing clock enable bit
bit_offset: 16
bit_size: 1
- name: RNGEN
description: Random Number Generator clock enable bit
bit_offset: 20
bit_size: 1
- name: CRYPEN
description: Crypto clock enable bit
bit_offset: 24
bit_size: 1
fieldset/AHBRSTR:
description: AHB peripheral reset register
fields:
- name: DMARST
description: DMA reset
bit_offset: 0
bit_size: 1
enum_write: CRYPRSTW
- name: MIFRST
description: Memory interface reset
bit_offset: 8
bit_size: 1
enum_write: CRYPRSTW
- name: CRCRST
description: Test integration module reset
bit_offset: 12
bit_size: 1
enum_write: CRYPRSTW
- name: TOUCHRST
description: Touch Sensing reset
bit_offset: 16
bit_size: 1
enum_write: CRYPRSTW
- name: RNGRST
description: Random Number Generator module reset
bit_offset: 20
bit_size: 1
enum_write: CRYPRSTW
- name: CRYPRST
description: Crypto module reset
bit_offset: 24
bit_size: 1
enum_write: CRYPRSTW
fieldset/AHBSMENR:
description: AHB peripheral clock enable in sleep mode register
fields:
- name: DMASMEN
description: DMA clock enable during sleep mode bit
bit_offset: 0
bit_size: 1
- name: MIFSMEN
description: NVM interface clock enable during sleep mode bit
bit_offset: 8
bit_size: 1
- name: SRAMSMEN
description: SRAM interface clock enable during sleep mode bit
bit_offset: 9
bit_size: 1
- name: CRCSMEN
description: CRC clock enable during sleep mode bit
bit_offset: 12
bit_size: 1
- name: TOUCHSMEN
description: Touch Sensing clock enable during sleep mode bit
bit_offset: 16
bit_size: 1
- name: RNGSMEN
description: Random Number Generator clock enable during sleep mode bit
bit_offset: 20
bit_size: 1
- name: CRYPSMEN
description: Crypto clock enable during sleep mode bit
bit_offset: 24
bit_size: 1
fieldset/APB1ENR:
description: APB1 peripheral clock enable register
fields:
- name: TIM2EN
description: Timer2 clock enable bit
bit_offset: 0
bit_size: 1
- name: TIM3EN
description: Timer3 clock enable bit
bit_offset: 1
bit_size: 1
- name: TIM6EN
description: Timer 6 clock enable bit
bit_offset: 4
bit_size: 1
- name: TIM7EN
description: Timer 7 clock enable bit
bit_offset: 5
bit_size: 1
- name: WWDGEN
description: Window watchdog clock enable bit
bit_offset: 11
bit_size: 1
- name: SPI2EN
description: SPI2 clock enable bit
bit_offset: 14
bit_size: 1
- name: USART2EN
description: UART2 clock enable bit
bit_offset: 17
bit_size: 1
- name: LPUART1EN
description: LPUART1 clock enable bit
bit_offset: 18
bit_size: 1
- name: USART4EN
description: USART4 clock enable bit
bit_offset: 19
bit_size: 1
- name: USART5EN
description: USART5 clock enable bit
bit_offset: 20
bit_size: 1
- name: I2C1EN
description: I2C1 clock enable bit
bit_offset: 21
bit_size: 1
- name: I2C2EN
description: I2C2 clock enable bit
bit_offset: 22
bit_size: 1
- name: USBEN
description: USB clock enable bit
bit_offset: 23
bit_size: 1
- name: CRSEN
description: Clock recovery system clock enable bit
bit_offset: 27
bit_size: 1
- name: PWREN
description: Power interface clock enable bit
bit_offset: 28
bit_size: 1
- name: DACEN
description: DAC interface clock enable bit
bit_offset: 29
bit_size: 1
- name: I2C3EN
description: I2C3 clock enable bit
bit_offset: 30
bit_size: 1
- name: LPTIM1EN
description: Low power timer clock enable bit
bit_offset: 31
bit_size: 1
fieldset/APB1RSTR:
description: APB1 peripheral reset register
fields:
- name: TIM2RST
description: Timer2 reset
bit_offset: 0
bit_size: 1
enum_write: LPTIMRSTW
- name: TIM3RST
description: Timer3 reset
bit_offset: 1
bit_size: 1
enum_write: LPTIMRSTW
- name: TIM6RST
description: Timer 6 reset
bit_offset: 4
bit_size: 1
enum_write: LPTIMRSTW
- name: TIM7RST
description: Timer 7 reset
bit_offset: 5
bit_size: 1
enum_write: LPTIMRSTW
- name: WWDRST
description: Window watchdog reset
bit_offset: 11
bit_size: 1
enum_write: LPTIMRSTW
- name: SPI2RST
description: SPI2 reset
bit_offset: 14
bit_size: 1
enum_write: LPTIMRSTW
- name: LPUART12RST
description: UART2 reset
bit_offset: 17
bit_size: 1
enum_write: LPTIMRSTW
- name: LPUART1RST
description: LPUART1 reset
bit_offset: 18
bit_size: 1
enum_write: LPTIMRSTW
- name: USART4RST
description: USART4 reset
bit_offset: 19
bit_size: 1
enum_write: LPTIMRSTW
- name: USART5RST
description: USART5 reset
bit_offset: 20
bit_size: 1
enum_write: LPTIMRSTW
- name: I2C1RST
description: I2C1 reset
bit_offset: 21
bit_size: 1
enum_write: LPTIMRSTW
- name: I2C2RST
description: I2C2 reset
bit_offset: 22
bit_size: 1
enum_write: LPTIMRSTW
- name: USBRST
description: USB reset
bit_offset: 23
bit_size: 1
enum_write: LPTIMRSTW
- name: CRSRST
description: Clock recovery system reset
bit_offset: 27
bit_size: 1
enum_write: LPTIMRSTW
- name: PWRRST
description: Power interface reset
bit_offset: 28
bit_size: 1
enum_write: LPTIMRSTW
- name: DACRST
description: DAC interface reset
bit_offset: 29
bit_size: 1
enum_write: LPTIMRSTW
- name: I2C3RST
description: I2C3 reset
bit_offset: 30
bit_size: 1
enum_write: LPTIMRSTW
- name: LPTIM1RST
description: Low power timer reset
bit_offset: 31
bit_size: 1
enum_write: LPTIMRSTW
fieldset/APB1SMENR:
description: APB1 peripheral clock enable in sleep mode register
fields:
- name: TIM2SMEN
description: Timer2 clock enable during sleep mode bit
bit_offset: 0
bit_size: 1
- name: TIM3SMEN
description: Timer3 clock enable during Sleep mode bit
bit_offset: 1
bit_size: 1
- name: TIM6SMEN
description: Timer 6 clock enable during sleep mode bit
bit_offset: 4
bit_size: 1
- name: TIM7SMEN
description: Timer 7 clock enable during Sleep mode bit
bit_offset: 5
bit_size: 1
- name: WWDGSMEN
description: Window watchdog clock enable during sleep mode bit
bit_offset: 11
bit_size: 1
- name: SPI2SMEN
description: SPI2 clock enable during sleep mode bit
bit_offset: 14
bit_size: 1
- name: USART2SMEN
description: UART2 clock enable during sleep mode bit
bit_offset: 17
bit_size: 1
- name: LPUART1SMEN
description: LPUART1 clock enable during sleep mode bit
bit_offset: 18
bit_size: 1
- name: USART4SMEN
description: USART4 clock enable during Sleep mode bit
bit_offset: 19
bit_size: 1
- name: USART5SMEN
description: USART5 clock enable during Sleep mode bit
bit_offset: 20
bit_size: 1
- name: I2C1SMEN
description: I2C1 clock enable during sleep mode bit
bit_offset: 21
bit_size: 1
- name: I2C2SMEN
description: I2C2 clock enable during sleep mode bit
bit_offset: 22
bit_size: 1
- name: USBSMEN
description: USB clock enable during sleep mode bit
bit_offset: 23
bit_size: 1
- name: CRSSMEN
description: Clock recovery system clock enable during sleep mode bit
bit_offset: 27
bit_size: 1
- name: PWRSMEN
description: Power interface clock enable during sleep mode bit
bit_offset: 28
bit_size: 1
- name: DACSMEN
description: DAC interface clock enable during sleep mode bit
bit_offset: 29
bit_size: 1
- name: I2C3SMEN
description: 2C3 clock enable during Sleep mode bit
bit_offset: 30
bit_size: 1
- name: LPTIM1SMEN
description: Low power timer clock enable during sleep mode bit
bit_offset: 31
bit_size: 1
fieldset/APB2ENR:
description: APB2 peripheral clock enable register
fields:
- name: SYSCFGEN
description: System configuration controller clock enable bit
bit_offset: 0
bit_size: 1
- name: TIM21EN
description: TIM21 timer clock enable bit
bit_offset: 2
bit_size: 1
- name: TIM22EN
description: TIM22 timer clock enable bit
bit_offset: 5
bit_size: 1
- name: MIFIEN
description: MiFaRe Firewall clock enable bit
bit_offset: 7
bit_size: 1
- name: ADCEN
description: ADC clock enable bit
bit_offset: 9
bit_size: 1
- name: SPI1EN
description: SPI1 clock enable bit
bit_offset: 12
bit_size: 1
- name: USART1EN
description: USART1 clock enable bit
bit_offset: 14
bit_size: 1
- name: DBGEN
description: DBG clock enable bit
bit_offset: 22
bit_size: 1
fieldset/APB2RSTR:
description: APB2 peripheral reset register
fields:
- name: SYSCFGRST
description: System configuration controller reset
bit_offset: 0
bit_size: 1
enum_write: DBGRSTW
- name: TIM21RST
description: TIM21 timer reset
bit_offset: 2
bit_size: 1
enum_write: DBGRSTW
- name: TIM22RST
description: TIM22 timer reset
bit_offset: 5
bit_size: 1
enum_write: DBGRSTW
- name: ADCRST
description: ADC interface reset
bit_offset: 9
bit_size: 1
enum_write: DBGRSTW
- name: SPI1RST
description: SPI 1 reset
bit_offset: 12
bit_size: 1
enum_write: DBGRSTW
- name: USART1RST
description: USART1 reset
bit_offset: 14
bit_size: 1
enum_write: DBGRSTW
- name: DBGRST
description: DBG reset
bit_offset: 22
bit_size: 1
enum_write: DBGRSTW
fieldset/APB2SMENR:
description: APB2 peripheral clock enable in sleep mode register
fields:
- name: SYSCFGSMEN
description: System configuration controller clock enable during sleep mode bit
bit_offset: 0
bit_size: 1
- name: TIM21SMEN
description: TIM21 timer clock enable during sleep mode bit
bit_offset: 2
bit_size: 1
- name: TIM22SMEN
description: TIM22 timer clock enable during sleep mode bit
bit_offset: 5
bit_size: 1
- name: ADCSMEN
description: ADC clock enable during sleep mode bit
bit_offset: 9
bit_size: 1
- name: SPI1SMEN
description: SPI1 clock enable during sleep mode bit
bit_offset: 12
bit_size: 1
- name: USART1SMEN
description: USART1 clock enable during sleep mode bit
bit_offset: 14
bit_size: 1
- name: DBGSMEN
description: DBG clock enable during sleep mode bit
bit_offset: 22
bit_size: 1
fieldset/CCIPR:
description: Clock configuration register
fields:
- name: USART1SEL
description: USART1 clock source selection bits
bit_offset: 0
bit_size: 2
enum: LPUARTSEL
- name: USART2SEL
description: USART2 clock source selection bits
bit_offset: 2
bit_size: 2
enum: LPUARTSEL
- name: LPUART1SEL
description: LPUART1 clock source selection bits
bit_offset: 10
bit_size: 2
enum: LPUARTSEL
- name: I2C1SEL
description: I2C1 clock source selection bits
bit_offset: 12
bit_size: 2
enum: ICSEL
- name: I2C3SEL
description: I2C3 clock source selection bits
bit_offset: 16
bit_size: 2
enum: ICSEL
- name: LPTIM1SEL
description: Low Power Timer clock source selection bits
bit_offset: 18
bit_size: 2
enum: LPTIMSEL
- name: HSI48MSEL
description: 48 MHz HSI48 clock source selection bit
bit_offset: 26
bit_size: 1
fieldset/CFGR:
description: Clock configuration register
fields:
- name: SW
description: System clock switch
bit_offset: 0
bit_size: 2
enum: SW
- name: SWS
description: System clock switch status
bit_offset: 2
bit_size: 2
enum: SWS
- name: HPRE
description: AHB prescaler
bit_offset: 4
bit_size: 4
enum: HPRE
- name: PPRE
description: APB low-speed prescaler (APB1)
bit_offset: 8
bit_size: 3
array:
len: 2
stride: 3
enum: PPRE
- name: STOPWUCK
description: Wake-up from stop clock selection
bit_offset: 15
bit_size: 1
enum: STOPWUCK
- name: PLLSRC
description: PLL entry clock source
bit_offset: 16
bit_size: 1
enum: PLLSRC
- name: PLLMUL
description: PLL multiplication factor
bit_offset: 18
bit_size: 4
enum: PLLMUL
- name: PLLDIV
description: PLL output division
bit_offset: 22
bit_size: 2
enum: PLLDIV
- name: MCOSEL
description: Microcontroller clock output selection
bit_offset: 24
bit_size: 4
enum: MCOSEL
- name: MCOPRE
description: Microcontroller clock output prescaler
bit_offset: 28
bit_size: 3
enum: MCOPRE
fieldset/CICR:
description: Clock interrupt clear register
fields:
- name: LSIRDYC
description: LSI ready Interrupt clear
bit_offset: 0
bit_size: 1
enum_write: CSSHSECW
- name: LSERDYC
description: LSE ready Interrupt clear
bit_offset: 1
bit_size: 1
enum_write: CSSHSECW
- name: HSI16RDYC
description: HSI16 ready Interrupt clear
bit_offset: 2
bit_size: 1
enum_write: CSSHSECW
- name: HSERDYC
description: HSE ready Interrupt clear
bit_offset: 3
bit_size: 1
enum_write: CSSHSECW
- name: PLLRDYC
description: PLL ready Interrupt clear
bit_offset: 4
bit_size: 1
enum_write: CSSHSECW
- name: MSIRDYC
description: MSI ready Interrupt clear
bit_offset: 5
bit_size: 1
enum_write: CSSHSECW
- name: HSI48RDYC
description: HSI48 ready Interrupt clear
bit_offset: 6
bit_size: 1
enum_write: CSSHSECW
- name: CSSLSEC
description: LSE Clock Security System Interrupt clear
bit_offset: 7
bit_size: 1
enum_write: CSSHSECW
- name: CSSHSEC
description: Clock Security System Interrupt clear
bit_offset: 8
bit_size: 1
enum_write: CSSHSECW
fieldset/CIER:
description: Clock interrupt enable register
fields:
- name: LSIRDYIE
description: LSI ready interrupt flag
bit_offset: 0
bit_size: 1
enum: HSIRDYIE
- name: LSERDYIE
description: LSE ready interrupt flag
bit_offset: 1
bit_size: 1
enum: HSIRDYIE
- name: HSI16RDYIE
description: HSI16 ready interrupt flag
bit_offset: 2
bit_size: 1
enum: HSIRDYIE
- name: HSERDYIE
description: HSE ready interrupt flag
bit_offset: 3
bit_size: 1
enum: HSIRDYIE
- name: PLLRDYIE
description: PLL ready interrupt flag
bit_offset: 4
bit_size: 1
enum: HSIRDYIE
- name: MSIRDYIE
description: MSI ready interrupt flag
bit_offset: 5
bit_size: 1
enum: HSIRDYIE
- name: HSI48RDYIE
description: HSI48 ready interrupt flag
bit_offset: 6
bit_size: 1
enum: HSIRDYIE
- name: CSSLSE
description: LSE CSS interrupt flag
bit_offset: 7
bit_size: 1
enum: CSSLSE
fieldset/CIFR:
description: Clock interrupt flag register
fields:
- name: LSIRDYF
description: LSI ready interrupt flag
bit_offset: 0
bit_size: 1
enum_read: HSI48RDYFR
- name: LSERDYF
description: LSE ready interrupt flag
bit_offset: 1
bit_size: 1
enum_read: HSI48RDYFR
- name: HSI16RDYF
description: HSI16 ready interrupt flag
bit_offset: 2
bit_size: 1
enum_read: HSI48RDYFR
- name: HSERDYF
description: HSE ready interrupt flag
bit_offset: 3
bit_size: 1
enum_read: HSI48RDYFR
- name: PLLRDYF
description: PLL ready interrupt flag
bit_offset: 4
bit_size: 1
enum_read: HSI48RDYFR
- name: MSIRDYF
description: MSI ready interrupt flag
bit_offset: 5
bit_size: 1
enum_read: HSI48RDYFR
- name: HSI48RDYF
description: HSI48 ready interrupt flag
bit_offset: 6
bit_size: 1
enum_read: HSI48RDYFR
- name: CSSLSEF
description: LSE Clock Security System Interrupt flag
bit_offset: 7
bit_size: 1
enum: CSSLSEF
- name: CSSHSEF
description: Clock Security System Interrupt flag
bit_offset: 8
bit_size: 1
enum: CSSHSEF
fieldset/CR:
description: Clock control register
fields:
- name: HSI16ON
description: 16 MHz high-speed internal clock enable
bit_offset: 0
bit_size: 1
enum: PLLON
- name: HSI16KERON
description: High-speed internal clock enable bit for some IP kernels
bit_offset: 1
bit_size: 1
enum: PLLON
- name: HSI16RDYF
description: Internal high-speed clock ready flag
bit_offset: 2
bit_size: 1
enum_read: HSI16RDYFR
- name: HSI16DIVEN
description: HSI16DIVEN
bit_offset: 3
bit_size: 1
- name: HSI16DIVF
description: HSI16DIVF
bit_offset: 4
bit_size: 1
enum_read: HSIDIVFR
- name: HSI16OUTEN
description: 16 MHz high-speed internal clock output enable
bit_offset: 5
bit_size: 1
- name: MSION
description: MSI clock enable bit
bit_offset: 8
bit_size: 1
enum: PLLON
- name: MSIRDY
description: MSI clock ready flag
bit_offset: 9
bit_size: 1
enum_read: HSERDYR
- name: HSEON
description: HSE clock enable bit
bit_offset: 16
bit_size: 1
enum: PLLON
- name: HSERDY
description: HSE clock ready flag
bit_offset: 17
bit_size: 1
enum_read: HSERDYR
- name: HSEBYP
description: HSE clock bypass bit
bit_offset: 18
bit_size: 1
enum: HSEBYP
- name: CSSHSEON
description: Clock security system on HSE enable bit
bit_offset: 19
bit_size: 1
enum: PLLON
- name: RTCPRE
description: TC/LCD prescaler
bit_offset: 20
bit_size: 2
enum: RTCPRE
- name: PLLON
description: PLL enable bit
bit_offset: 24
bit_size: 1
enum: PLLON
- name: PLLRDY
description: PLL clock ready flag
bit_offset: 25
bit_size: 1
enum_read: PLLRDYR
fieldset/CRRCR:
description: Clock recovery RC register
fields:
- name: HSI48ON
description: 48MHz HSI clock enable bit
bit_offset: 0
bit_size: 1
- name: HSI48RDY
description: 48MHz HSI clock ready flag
bit_offset: 1
bit_size: 1
- name: HSI48DIV6EN
description: 48 MHz HSI clock divided by 6 output enable
bit_offset: 2
bit_size: 1
- name: HSI48CAL
description: 48 MHz HSI clock calibration
bit_offset: 8
bit_size: 8
fieldset/CSR:
description: Control and status register
fields:
- name: LSION
description: Internal low-speed oscillator enable
bit_offset: 0
bit_size: 1
enum: CSSLSEON
- name: LSIRDY
description: Internal low-speed oscillator ready bit
bit_offset: 1
bit_size: 1
enum: LSERDY
- name: LSEON
description: External low-speed oscillator enable bit
bit_offset: 8
bit_size: 1
enum: CSSLSEON
- name: LSERDY
description: External low-speed oscillator ready bit
bit_offset: 9
bit_size: 1
enum: LSERDY
- name: LSEBYP
description: External low-speed oscillator bypass bit
bit_offset: 10
bit_size: 1
enum: LSEBYP
- name: LSEDRV
description: LSEDRV
bit_offset: 11
bit_size: 2
enum: LSEDRV
- name: CSSLSEON
description: CSSLSEON
bit_offset: 13
bit_size: 1
enum: CSSLSEON
- name: CSSLSED
description: CSS on LSE failure detection flag
bit_offset: 14
bit_size: 1
enum: CSSLSED
- name: RTCSEL
description: RTC and LCD clock source selection bits
bit_offset: 16
bit_size: 2
enum: RTCSEL
- name: RTCEN
description: RTC clock enable bit
bit_offset: 18
bit_size: 1
- name: RTCRST
description: RTC software reset bit
bit_offset: 19
bit_size: 1
enum_write: RTCRSTW
- name: RMVF
description: Remove reset flag
bit_offset: 24
bit_size: 1
enum_write: RMVFW
- name: OBLRSTF
description: OBLRSTF
bit_offset: 25
bit_size: 1
enum_read: LPWRRSTFR
- name: PINRSTF
description: PIN reset flag
bit_offset: 26
bit_size: 1
enum_read: LPWRRSTFR
- name: PORRSTF
description: POR/PDR reset flag
bit_offset: 27
bit_size: 1
enum_read: LPWRRSTFR
- name: SFTRSTF
description: Software reset flag
bit_offset: 28
bit_size: 1
enum_read: LPWRRSTFR
- name: IWDGRSTF
description: Independent watchdog reset flag
bit_offset: 29
bit_size: 1
enum_read: LPWRRSTFR
- name: WWDGRSTF
description: Window watchdog reset flag
bit_offset: 30
bit_size: 1
enum_read: LPWRRSTFR
- name: LPWRRSTF
description: Low-power reset flag
bit_offset: 31
bit_size: 1
enum_read: LPWRRSTFR
fieldset/ICSCR:
description: Internal clock sources calibration register
fields:
- name: HSI16CAL
description: nternal high speed clock calibration
bit_offset: 0
bit_size: 8
- name: HSI16TRIM
description: High speed internal clock trimming
bit_offset: 8
bit_size: 5
- name: MSIRANGE
description: MSI clock ranges
bit_offset: 13
bit_size: 3
enum: MSIRANGE
- name: MSICAL
description: MSI clock calibration
bit_offset: 16
bit_size: 8
- name: MSITRIM
description: MSI clock trimming
bit_offset: 24
bit_size: 8
fieldset/IOPENR:
description: GPIO clock enable register
fields:
- name: IOPAEN
description: IO port A clock enable bit
bit_offset: 0
bit_size: 1
- name: IOPBEN
description: IO port B clock enable bit
bit_offset: 1
bit_size: 1
- name: IOPCEN
description: IO port A clock enable bit
bit_offset: 2
bit_size: 1
- name: IOPDEN
description: I/O port D clock enable bit
bit_offset: 3
bit_size: 1
- name: IOPEEN
description: I/O port E clock enable bit
bit_offset: 4
bit_size: 1
- name: IOPHEN
description: I/O port H clock enable bit
bit_offset: 7
bit_size: 1
fieldset/IOPRSTR:
description: GPIO reset register
fields:
- name: IOPARST
description: I/O port A reset
bit_offset: 0
bit_size: 1
- name: IOPBRST
description: I/O port B reset
bit_offset: 1
bit_size: 1
- name: IOPCRST
description: I/O port A reset
bit_offset: 2
bit_size: 1
- name: IOPDRST
description: I/O port D reset
bit_offset: 3
bit_size: 1
- name: IOPERST
description: I/O port E reset
bit_offset: 4
bit_size: 1
- name: IOPHRST
description: I/O port H reset
bit_offset: 7
bit_size: 1
fieldset/IOPSMEN:
description: GPIO clock enable in sleep mode register
fields:
- name: IOPASMEN
description: IOPASMEN
bit_offset: 0
bit_size: 1
- name: IOPBSMEN
description: IOPBSMEN
bit_offset: 1
bit_size: 1
- name: IOPCSMEN
description: IOPCSMEN
bit_offset: 2
bit_size: 1
- name: IOPDSMEN
description: IOPDSMEN
bit_offset: 3
bit_size: 1
- name: IOPESMEN
description: Port E clock enable during Sleep mode bit
bit_offset: 4
bit_size: 1
- name: IOPHSMEN
description: IOPHSMEN
bit_offset: 7
bit_size: 1
enum/CRYPRSTW:
bit_size: 1
variants:
- name: Reset
description: Reset the module
value: 1
enum/CSSHSECW:
bit_size: 1
variants:
- name: Clear
description: Clear interrupt flag
value: 1
enum/CSSHSEF:
bit_size: 1
variants:
- name: NoClock
description: No clock security interrupt caused by HSE clock failure
value: 0
- name: Clock
description: Clock security interrupt caused by HSE clock failure
value: 1
enum/CSSLSE:
bit_size: 1
variants:
- name: Disabled
description: LSE CSS interrupt disabled
value: 0
- name: Enabled
description: LSE CSS interrupt enabled
value: 1
enum/CSSLSED:
bit_size: 1
variants:
- name: NoFailure
description: No failure detected on LSE (32 kHz oscillator)
value: 0
- name: Failure
description: Failure detected on LSE (32 kHz oscillator)
value: 1
enum/CSSLSEF:
bit_size: 1
variants:
- name: NoFailure
description: No failure detected on LSE clock failure
value: 0
- name: Failure
description: Failure detected on LSE clock failure
value: 1
enum/CSSLSEON:
bit_size: 1
variants:
- name: "Off"
description: Oscillator OFF
value: 0
- name: "On"
description: Oscillator ON
value: 1
enum/DBGRSTW:
bit_size: 1
variants:
- name: Reset
description: Reset the module
value: 1
enum/HPRE:
bit_size: 4
variants:
- name: Div1
description: system clock not divided
value: 0
- name: Div2
description: system clock divided by 2
value: 8
- name: Div4
description: system clock divided by 4
value: 9
- name: Div8
description: system clock divided by 8
value: 10
- name: Div16
description: system clock divided by 16
value: 11
- name: Div64
description: system clock divided by 64
value: 12
- name: Div128
description: system clock divided by 128
value: 13
- name: Div256
description: system clock divided by 256
value: 14
- name: Div512
description: system clock divided by 512
value: 15
enum/HSEBYP:
bit_size: 1
variants:
- name: NotBypassed
description: HSE oscillator not bypassed
value: 0
- name: Bypassed
description: HSE oscillator bypassed
value: 1
enum/HSERDYR:
bit_size: 1
variants:
- name: NotReady
description: Oscillator is not stable
value: 0
- name: Ready
description: Oscillator is stable
value: 1
enum/HSI16RDYFR:
bit_size: 1
variants:
- name: NotReady
description: HSI 16 MHz oscillator not ready
value: 0
- name: Ready
description: HSI 16 MHz oscillator ready
value: 1
enum/HSI48RDYFR:
bit_size: 1
variants:
- name: NotInterrupted
description: No clock ready interrupt
value: 0
- name: Interrupted
description: Clock ready interrupt
value: 1
enum/HSIDIVFR:
bit_size: 1
variants:
- name: NotDivided
description: 16 MHz HSI clock not divided
value: 0
- name: Div4
description: 16 MHz HSI clock divided by 4
value: 1
enum/HSIRDYIE:
bit_size: 1
variants:
- name: Disabled
description: Ready interrupt disabled
value: 0
- name: Enabled
description: Ready interrupt enabled
value: 1
enum/ICSEL:
bit_size: 2
variants:
- name: APB
description: APB clock selected as peripheral clock
value: 0
- name: SYSTEM
description: System clock selected as peripheral clock
value: 1
- name: HSI16
description: HSI16 clock selected as peripheral clock
value: 2
enum/LPTIMRSTW:
bit_size: 1
variants:
- name: Reset
description: Reset the module
value: 1
enum/LPTIMSEL:
bit_size: 2
variants:
- name: APB
description: APB clock selected as Timer clock
value: 0
- name: LSI
description: LSI clock selected as Timer clock
value: 1
- name: HSI16
description: HSI16 clock selected as Timer clock
value: 2
- name: LSE
description: LSE clock selected as Timer clock
value: 3
enum/LPUARTSEL:
bit_size: 2
variants:
- name: APB
description: APB clock selected as peripheral clock
value: 0
- name: SYSTEM
description: System clock selected as peripheral clock
value: 1
- name: HSI16
description: HSI16 clock selected as peripheral clock
value: 2
- name: LSE
description: LSE clock selected as peripheral clock
value: 3
enum/LPWRRSTFR:
bit_size: 1
variants:
- name: NoReset
description: No reset has occured
value: 0
- name: Reset
description: A reset has occured
value: 1
enum/LSEBYP:
bit_size: 1
variants:
- name: NotBypassed
description: LSE oscillator not bypassed
value: 0
- name: Bypassed
description: LSE oscillator bypassed
value: 1
enum/LSEDRV:
bit_size: 2
variants:
- name: Low
description: Lowest drive
value: 0
- name: MediumLow
description: Medium low drive
value: 1
- name: MediumHigh
description: Medium high drive
value: 2
- name: High
description: Highest drive
value: 3
enum/LSERDY:
bit_size: 1
variants:
- name: NotReady
description: Oscillator not ready
value: 0
- name: Ready
description: Oscillator ready
value: 1
enum/MCOPRE:
bit_size: 3
variants:
- name: Div1
description: No division
value: 0
- name: Div2
description: Division by 2
value: 1
- name: Div4
description: Division by 4
value: 2
- name: Div8
description: Division by 8
value: 3
- name: Div16
description: Division by 16
value: 4
enum/MCOSEL:
bit_size: 4
variants:
- name: NoClock
description: No clock
value: 0
- name: SYSCLK
description: SYSCLK clock selected
value: 1
- name: HSI16
description: HSI oscillator clock selected
value: 2
- name: MSI
description: MSI oscillator clock selected
value: 3
- name: HSE
description: HSE oscillator clock selected
value: 4
- name: PLL
description: PLL clock selected
value: 5
- name: LSI
description: LSI oscillator clock selected
value: 6
- name: LSE
description: LSE oscillator clock selected
value: 7
enum/MSIRANGE:
bit_size: 3
variants:
- name: Range0
description: range 0 around 65.536 kHz
value: 0
- name: Range1
description: range 1 around 131.072 kHz
value: 1
- name: Range2
description: range 2 around 262.144 kHz
value: 2
- name: Range3
description: range 3 around 524.288 kHz
value: 3
- name: Range4
description: range 4 around 1.048 MHz
value: 4
- name: Range5
description: range 5 around 2.097 MHz (reset value)
value: 5
- name: Range6
description: range 6 around 4.194 MHz
value: 6
- name: Range7
description: not allowed
value: 7
enum/PLLDIV:
bit_size: 2
variants:
- name: Div2
description: PLLVCO / 2
value: 1
- name: Div3
description: PLLVCO / 3
value: 2
- name: Div4
description: PLLVCO / 4
value: 3
enum/PLLMUL:
bit_size: 4
variants:
- name: Mul3
description: PLL clock entry x 3
value: 0
- name: Mul4
description: PLL clock entry x 4
value: 1
- name: Mul6
description: PLL clock entry x 6
value: 2
- name: Mul8
description: PLL clock entry x 8
value: 3
- name: Mul12
description: PLL clock entry x 12
value: 4
- name: Mul16
description: PLL clock entry x 16
value: 5
- name: Mul24
description: PLL clock entry x 24
value: 6
- name: Mul32
description: PLL clock entry x 32
value: 7
- name: Mul48
description: PLL clock entry x 48
value: 8
enum/PLLON:
bit_size: 1
variants:
- name: Disabled
description: Clock disabled
value: 0
- name: Enabled
description: Clock enabled
value: 1
enum/PLLRDYR:
bit_size: 1
variants:
- name: Unlocked
description: PLL unlocked
value: 0
- name: Locked
description: PLL locked
value: 1
enum/PLLSRC:
bit_size: 1
variants:
- name: HSI16
description: HSI selected as PLL input clock
value: 0
- name: HSE
description: HSE selected as PLL input clock
value: 1
enum/PPRE:
bit_size: 3
variants:
- name: Div1
description: HCLK not divided
value: 0
- name: Div2
description: HCLK divided by 2
value: 4
- name: Div4
description: HCLK divided by 4
value: 5
- name: Div8
description: HCLK divided by 8
value: 6
- name: Div16
description: HCLK divided by 16
value: 7
enum/RMVFW:
bit_size: 1
variants:
- name: Clear
description: Clears the reset flag
value: 1
enum/RTCPRE:
bit_size: 2
variants:
- name: Div2
description: HSE divided by 2
value: 0
- name: Div4
description: HSE divided by 4
value: 1
- name: Div8
description: HSE divided by 8
value: 2
- name: Div16
description: HSE divided by 16
value: 3
enum/RTCRSTW:
bit_size: 1
variants:
- name: Reset
description: Resets the RTC peripheral
value: 1
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
description: No clock
value: 0
- name: LSE
description: LSE oscillator clock used as RTC clock
value: 1
- name: LSI
description: LSI oscillator clock used as RTC clock
value: 2
- name: HSE
description: "HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock"
value: 3
enum/STOPWUCK:
bit_size: 1
variants:
- name: MSI
description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock
value: 0
- name: HSI16
description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1)
value: 1
enum/SW:
bit_size: 2
variants:
- name: MSI
description: MSI oscillator used as system clock
value: 0
- name: HSI16
description: HSI oscillator used as system clock
value: 1
- name: HSE
description: HSE oscillator used as system clock
value: 2
- name: PLL
description: PLL used as system clock
value: 3
enum/SWS:
bit_size: 2
variants:
- name: MSI
description: MSI oscillator used as system clock
value: 0
- name: HSI16
description: HSI oscillator used as system clock
value: 1
- name: HSE
description: HSE oscillator used as system clock
value: 2
- name: PLL
description: PLL used as system clock
value: 3
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