Dario Nieuwenhuis
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5cd5d2b110
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Add back parsing for ADC pins.
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2021-11-05 17:46:12 +01:00 |
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Dario Nieuwenhuis
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ffc40c718a
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Unify all docs under the docs key, sort them.
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2021-11-05 17:46:11 +01:00 |
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Dario Nieuwenhuis
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ae9ff6f3a5
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Simplify main parsing code, fix AF parsing missing stuff.
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2021-11-05 02:23:38 +01:00 |
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Dario Nieuwenhuis
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5eb3c378ef
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Sort pins to make diffing easier.
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2021-11-05 02:23:37 +01:00 |
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Dario Nieuwenhuis
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cf494447ff
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Ignore pins with broken names. Only Pxyy.
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2021-11-05 00:39:36 +01:00 |
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Dario Nieuwenhuis
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ca3da1b2de
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Split python code in a few modules
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2021-11-04 19:25:43 +01:00 |
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Dario Nieuwenhuis
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b645ff267c
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Merge pull request #97 from matoushybl/h7
Support for STM32H72x family.
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2021-11-04 15:59:10 +01:00 |
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Matous Hybl
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6ef7659b9d
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Add support for H723 RCC differences.
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2021-11-04 15:26:52 +01:00 |
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Matous Hybl
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dac1140b17
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Fix pin names by removing pin functions in brackets.
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2021-11-04 10:35:18 +01:00 |
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Dario Nieuwenhuis
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2e06408221
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Merge pull request #96 from matoushybl/f7-support
Fix v1c ethernet definition.
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2021-11-04 00:23:50 +01:00 |
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Matous Hybl
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3d7e46e6c9
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Fix v1c ethernet definition.
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2021-11-03 10:13:15 +01:00 |
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Dario Nieuwenhuis
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c40960c953
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Merge pull request #95 from bobmcwhirter/weird_u5_headers
Weird u5 headers
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2021-11-02 17:35:16 +01:00 |
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Bob McWhirter
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21f31372a6
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Adjust the d script.
Extract some peripherals for U5.
Update parse.py for some U5 perculiarities.
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2021-11-02 12:02:38 -04:00 |
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Bob McWhirter
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dc4a94e868
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Parse out U5xx packages.
Avoid barfing if we're not yet parsing DMA, because we aren't for GPDMA.
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2021-10-29 13:08:21 -04:00 |
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Bob McWhirter
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dca5886b25
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Parse decimal in the form of '08U'.
Parse division such as FLASH_BANK_SIZE / FLASH_SOMETHING in defines.
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2021-10-29 11:45:27 -04:00 |
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Bob McWhirter
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0358c950da
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Change d to just clone the -sources repository.
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2021-10-28 13:48:36 -04:00 |
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Dario Nieuwenhuis
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09c1a7102a
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Merge pull request #93 from bgamari/wip/lptim
stm32g0: Add support for LPTIM peripherals
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2021-10-26 17:57:15 +02:00 |
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Ben Gamari
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2f42ebcd2c
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Add support for LPTIM peripherals
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2021-10-26 17:55:48 +02:00 |
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Dario Nieuwenhuis
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6bedd95ce1
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Merge pull request #92 from matoushybl/f7-support
Initial support for STM32F767ZI.
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2021-10-26 17:21:47 +02:00 |
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Matous Hybl
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2e1302c4e8
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Support for STM32F767ZI and basic support for the rest of the family.
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2021-10-25 10:38:28 +02:00 |
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Ulf Lilleengen
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a90f756dda
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Merge pull request #91 from topisani/main
feat: Add F1 SPI registers
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2021-10-07 13:54:48 +02:00 |
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Tobias Pisani
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b8de47fa04
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feat: Add F1 SPI registers
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2021-10-06 20:51:27 +02:00 |
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Dario Nieuwenhuis
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6caf69650a
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Merge pull request #90 from mryndzionek/dev
Added AFIO block definition to STM32F103C8 chip
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2021-09-27 16:04:27 +02:00 |
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Mariusz Ryndzionek
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9e6eff587c
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Correct AFIO support (code review request)
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2021-09-27 15:35:29 +02:00 |
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Dario Nieuwenhuis
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fccbab0aae
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Merge pull request #89 from theunkn0wn1/feature/crc32
F4 CRC peripheral
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2021-09-27 00:30:21 +02:00 |
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Dario Nieuwenhuis
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f6ce6dc36b
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CRC register cleanup
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2021-09-27 00:26:24 +02:00 |
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Joshua Salzedo
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fb4d8b7033
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Add CRC rules to parse.py
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2021-09-26 15:09:45 -07:00 |
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Joshua Salzedo
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24dabf68e5
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Add three distinct versions of CRC
- remove F4 specific version
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2021-09-26 14:58:47 -07:00 |
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Joshua Salzedo
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a8a8b88661
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add CRC32 peripheral for the F4 family
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2021-09-24 16:59:18 -07:00 |
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Dario Nieuwenhuis
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9752672268
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Merge pull request #88 from FrozenDroid/add-l4-flash
Add L4 flash register
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2021-09-24 18:30:52 +02:00 |
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Vincent Stakenburg
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97fd020941
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add l4 flash register
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2021-09-24 16:45:59 +02:00 |
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Vincent Stakenburg
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f699571831
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add l4 flash parse line
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2021-09-24 16:45:17 +02:00 |
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Dario Nieuwenhuis
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e317d781d8
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Merge pull request #87 from mryndzionek/stm32f1_support
Updated register mapping for STM32 F1 AFIO
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2021-09-23 18:57:52 +02:00 |
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Mariusz Ryndzionek
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8dde100c15
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Updated register mapping for STM32 F1 AFIO
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2021-09-23 18:54:22 +02:00 |
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Dario Nieuwenhuis
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5dec590202
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Merge pull request #85 from mryndzionek/stm32f1_support
Add initial register mapping for STM32 F1 AFIO and FLASH
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2021-09-23 17:36:38 +02:00 |
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Ulf Lilleengen
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f1e7e9ef84
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Merge pull request #86 from lulf/stm32l1-pwr-and-fix
Add PWR register block and fix RCC register block
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2021-09-23 14:42:49 +02:00 |
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Ulf Lilleengen
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a302947e87
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Add PWR register block and fix RCC register block
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2021-09-23 14:40:59 +02:00 |
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Mariusz Ryndzionek
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fbea23bd00
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Added missing FLASH registers (generated automatically)
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2021-09-23 07:09:11 +02:00 |
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Mariusz Ryndzionek
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c0938c9102
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Add initial register mapping for STM32 F1 AFIO and FLASH
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2021-09-22 18:22:36 +02:00 |
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Dario Nieuwenhuis
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1d62ba5e14
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Merge pull request #84 from lulf/l1-regs
L1 regs
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2021-09-15 14:55:09 +02:00 |
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Ulf Lilleengen
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9f1bd7d0d0
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Update chip yaml
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2021-09-15 14:47:33 +02:00 |
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Ulf Lilleengen
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e2bf041808
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Add register mapping for STM32 L1 SYSCFG and DBGMCU
Add missing GPIO port mapping
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2021-09-15 14:47:01 +02:00 |
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Dario Nieuwenhuis
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616a2779d0
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Merge pull request #82 from bgamari/stm32g0
Fix ADC register layout on STM32G0
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2021-08-31 22:21:51 +02:00 |
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Dario Nieuwenhuis
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96c902c66c
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Merge pull request #83 from lulf/stm32wl55-pwr
Stm32wl55 pwr
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2021-08-31 22:18:57 +02:00 |
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Ulf Lilleengen
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201510407c
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Handle SUBGHZSPI peripheral so it is recognized as an SPI peripheral
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2021-08-31 14:43:02 +02:00 |
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Ulf Lilleengen
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902b9a6986
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Add PWR peripheral for STM32WL5
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2021-08-31 14:34:54 +02:00 |
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Ben Gamari
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3a88360dc6
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Add PWR registers for STM32G0
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2021-08-31 01:46:26 -04:00 |
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Ben Gamari
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5366833cbd
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Introduce ADC register set for STM32G0
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2021-08-31 01:46:02 -04:00 |
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Dario Nieuwenhuis
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deb37365d7
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exti: g0 and l5 are 8 bits per line...
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2021-08-20 01:26:33 +02:00 |
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Dario Nieuwenhuis
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8534ae884d
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rcc: make GPIO EN/RST regs naming consistent.
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2021-08-19 23:50:42 +02:00 |
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