24 Commits

Author SHA1 Message Date
xoviat
b9a89a1851 rcc: cleanup variants and rename ahb -> clk 2023-10-15 18:01:50 -05:00
xoviat
8b8686a852 rcc: more mux and enum cleanup 2023-10-15 10:37:36 -05:00
Dario Nieuwenhuis
e89b8cfc30 rcc: add PLL enums. 2023-10-09 02:44:42 +02:00
Dario Nieuwenhuis
6c73ffbd0b rcc: make naming consistent between "mco" and "mcosel". 2023-10-07 00:46:19 +02:00
Dario Nieuwenhuis
d6b0763327 More rcc cleanups. 2023-09-19 04:17:00 +02:00
Dario Nieuwenhuis
86fb0cfc2f chiptool fmt. 2023-09-16 02:34:03 +02:00
Dario Nieuwenhuis
3f01ff4545 Remove enum_read, enum_write. 2023-06-28 22:36:19 +02:00
Dario Nieuwenhuis
78c43e0dba rcc: fix QSPIEN vs QUADSPIEN reg names. 2023-03-27 12:17:47 +02:00
Dario Nieuwenhuis
c36a510e47 unify ETH vs ETHMAC in RCC regs. 2022-04-28 01:54:55 +02:00
Dario Nieuwenhuis
c90234583e RCC: fix USBFS -> USB 2022-04-09 00:43:48 +02:00
Dario Nieuwenhuis
c2804abc9a rcc: fix inconsistent naming. 2022-02-14 02:07:08 +01:00
Dario Nieuwenhuis
2c5e858584 chiptool fmt 2022-02-14 00:45:36 +01:00
Dario Nieuwenhuis
7b2df420ac rcc: remove useless enums. 2022-02-14 00:26:46 +01:00
chemicstry
2aaec03094 Fix USB OTG field names in RCC registers 2022-02-04 03:34:08 +02:00
Dario Nieuwenhuis
c6c5c099bb fmt all register yamls 2021-11-17 21:23:26 +01:00
Timo Kröger
7506b50031 rcc_l4: Remove duplicate bits 2021-08-03 16:33:59 +02:00
Timo Kröger
f865878b4b rcc_f4: Fix RCC bits
## LPTIM1EN / LPTIMER1EN

Only stm32f413 has LPTIM1 peripheral, ref manual bit names:
LPTIMER1EN, LPTIMER1RST, LPTIMER1LPEN, LPTIMER1SEL

action: Rename to LPTIM1(EN|RST|...) for consistency (matches peripheral name)

## FMC / FSMC

not available as peripheral in the YAML anyway.. TODO: why?

EN and RST

FSMC: f405, f407, f412, f413
FSC: f427, f429, f446, f469

action: none

## CECEN / CAN3EN

mutually exclusive peripherals, alias ok?

CECEN: f446
CAN3EN: f413

action: split off f4x3 yaml, f423 exists, but not available as svd

## USART / UART

all over the place, register names in ref manual not always consistent
stm32 follows a simple rule for the actual peripherals:
USART 1-3, 6
UART 4, 5, 7-10

action: rename enable/rst bits to rules above
2021-08-03 14:55:36 +02:00
Timo Kröger
c02e3dc9ab Split f410 and f4 RCC yamls
f410 has the RNGEN at a different position
2021-07-31 17:40:30 +02:00
Timo Kröger
074aad8a66 Remove invalid bits from F4, L4 RCC 2021-07-30 17:35:52 +02:00
Bob McWhirter
3bfe1bdee5 Rename some USART regs, needs more work. 2021-06-29 10:52:44 -04:00
Ulf Lilleengen
c1aae8d3d8 Run through transform again 2021-06-07 12:22:09 +02:00
Ulf Lilleengen
fea5e31f8b Regen and remove *ON enums 2021-06-03 15:13:46 +02:00
Ulf Lilleengen
529b991404 Do merge 2021-06-03 14:31:27 +02:00
Ulf Lilleengen
18a99a3a3b Add RCC register for STM32F4 and STM32L4
Register block based in STM32F427ZI and STM32L4R9.

Use bool for reset registers.

Define clock mapping for RNG peripherals. There are no 1 <-> 1 mapping
of RNG peripheral to clock in the Cubedb sources. The mapping will
pre-select the clock source for RNG for now.
2021-06-03 11:33:24 +02:00