stm32-data/data/registers/rcc_f4.yaml

block/RCC:
  description: Reset and clock control
  items:
  - byte_offset: 0
    description: clock control register
    fieldset: CR
    name: CR
  - byte_offset: 4
    description: PLL configuration register
    fieldset: PLLCFGR
    name: PLLCFGR
  - byte_offset: 8
    description: clock configuration register
    fieldset: CFGR
    name: CFGR
  - byte_offset: 12
    description: clock interrupt register
    fieldset: CIR
    name: CIR
  - byte_offset: 16
    description: AHB1 peripheral reset register
    fieldset: AHB1RSTR
    name: AHB1RSTR
  - byte_offset: 20
    description: AHB2 peripheral reset register
    fieldset: AHB2RSTR
    name: AHB2RSTR
  - byte_offset: 32
    description: APB1 peripheral reset register
    fieldset: APB1RSTR
    name: APB1RSTR
  - byte_offset: 36
    description: APB2 peripheral reset register
    fieldset: APB2RSTR
    name: APB2RSTR
  - byte_offset: 48
    description: AHB1 peripheral clock register
    fieldset: AHB1ENR
    name: AHB1ENR
  - byte_offset: 52
    description: AHB2 peripheral clock enable register
    fieldset: AHB2ENR
    name: AHB2ENR
  - byte_offset: 64
    description: APB1 peripheral clock enable register
    fieldset: APB1ENR
    name: APB1ENR
  - byte_offset: 68
    description: APB2 peripheral clock enable register
    fieldset: APB2ENR
    name: APB2ENR
  - byte_offset: 80
    description: AHB1 peripheral clock enable in low power mode register
    fieldset: AHB1LPENR
    name: AHB1LPENR
  - byte_offset: 84
    description: AHB2 peripheral clock enable in low power mode register
    fieldset: AHB2LPENR
    name: AHB2LPENR
  - byte_offset: 96
    description: APB1 peripheral clock enable in low power mode register
    fieldset: APB1LPENR
    name: APB1LPENR
  - byte_offset: 100
    description: APB2 peripheral clock enabled in low power mode register
    fieldset: APB2LPENR
    name: APB2LPENR
  - byte_offset: 112
    description: Backup domain control register
    fieldset: BDCR
    name: BDCR
  - byte_offset: 116
    description: clock control & status register
    fieldset: CSR
    name: CSR
  - byte_offset: 128
    description: spread spectrum clock generation register
    fieldset: SSCGR
    name: SSCGR
  - byte_offset: 132
    description: PLLI2S configuration register
    fieldset: PLLI2SCFGR
    name: PLLI2SCFGR
  - byte_offset: 140
    description: RCC Dedicated Clock Configuration Register
    fieldset: DCKCFGR
    name: DCKCFGR
  - byte_offset: 24
    description: AHB3 peripheral reset register
    fieldset: AHB3RSTR
    name: AHB3RSTR
  - byte_offset: 56
    description: AHB3 peripheral clock enable register
    fieldset: AHB3ENR
    name: AHB3ENR
  - byte_offset: 88
    description: AHB3 peripheral clock enable in low power mode register
    fieldset: AHB3LPENR
    name: AHB3LPENR
  - byte_offset: 148
    description: DCKCFGR2 register
    fieldset: DCKCFGR2
    name: DCKCFGR2
  - byte_offset: 144
    description: Clocks gated enable register
    fieldset: CKGATENR
    name: CKGATENR
  - byte_offset: 136
    description: RCC PLL configuration register
    fieldset: PLLSAICFGR
    name: PLLSAICFGR
enum/CECSEL:
  bit_size: 1
  variants:
  - description: LSE clock is selected as HDMI-CEC clock
    name: LSE
    value: 0
  - description: HSI divided by 488 clock is selected as HDMI-CEC clock
    name: HSI_Div488
    value: 1
enum/CKDFSDMASEL:
  bit_size: 1
  variants:
  - description: CK_I2S_APB1 selected as audio clock
    name: I2S1
    value: 0
  - description: CK_I2S_APB2 selected as audio clock
    name: I2S2
    value: 1
enum/CKDFSDMSEL:
  bit_size: 1
  variants:
  - description: APB2 clock used as Kernel clock
    name: APB2
    value: 0
  - description: System clock used as Kernel clock
    name: SYSCLK
    value: 1
enum/CKMSEL:
  bit_size: 1
  variants:
  - description: 48MHz clock from PLL is selected
    name: PLL
    value: 0
  - description: 48MHz clock from PLLSAI is selected
    name: PLLSAI
    value: 1
enum/CSSCW:
  bit_size: 1
  variants:
  - description: Clear CSSF flag
    name: Clear
    value: 1
enum/CSSFR:
  bit_size: 1
  variants:
  - description: No clock security interrupt caused by HSE clock failure
    name: NotInterrupted
    value: 0
  - description: Clock security interrupt caused by HSE clock failure
    name: Interrupted
    value: 1
enum/CSSON:
  bit_size: 1
  variants:
  - description: Clock security system disabled (clock detector OFF)
    name: 'Off'
    value: 0
  - description: Clock security system enable (clock detector ON if the HSE is ready,
      OFF if not)
    name: 'On'
    value: 1
enum/DSISEL:
  bit_size: 1
  variants:
  - description: DSI-PHY used as DSI byte lane clock source (usual case)
    name: DSI_PHY
    value: 0
  - description: PLLR used as DSI byte lane clock source, used in case DSI PLL and
      DSI-PHY are off (low power mode)
    name: PLLR
    value: 1
enum/FMPICSEL:
  bit_size: 2
  variants:
  - description: APB clock selected as I2C clock
    name: APB
    value: 0
  - description: System clock selected as I2C clock
    name: SYSCLK
    value: 1
  - description: HSI clock selected as I2C clock
    name: HSI
    value: 2
enum/HPRE:
  bit_size: 4
  variants:
  - description: SYSCLK not divided
    name: Div1
    value: 0
  - description: SYSCLK divided by 2
    name: Div2
    value: 8
  - description: SYSCLK divided by 4
    name: Div4
    value: 9
  - description: SYSCLK divided by 8
    name: Div8
    value: 10
  - description: SYSCLK divided by 16
    name: Div16
    value: 11
  - description: SYSCLK divided by 64
    name: Div64
    value: 12
  - description: SYSCLK divided by 128
    name: Div128
    value: 13
  - description: SYSCLK divided by 256
    name: Div256
    value: 14
  - description: SYSCLK divided by 512
    name: Div512
    value: 15
enum/HSEBYP:
  bit_size: 1
  variants:
  - description: HSE crystal oscillator not bypassed
    name: NotBypassed
    value: 0
  - description: HSE crystal oscillator bypassed with external clock
    name: Bypassed
    value: 1
enum/HSION:
  bit_size: 1
  variants:
  - description: Clock Off
    name: 'Off'
    value: 0
  - description: Clock On
    name: 'On'
    value: 1
enum/HSIRDYR:
  bit_size: 1
  variants:
  - description: Clock not ready
    name: NotReady
    value: 0
  - description: Clock ready
    name: Ready
    value: 1
enum/I2S1SRC:
  bit_size: 2
  variants:
  - description: I2Sx clock frequency = f(PLLI2S_R)
    name: PLLI2SR
    value: 0
  - description: I2Sx clock frequency = I2S_CKIN Alternate function input frequency
    name: I2S_CKIN
    value: 1
  - description: I2Sx clock frequency = f(PLL_R)
    name: PLLR
    value: 2
  - description: I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])
    name: HSI_HSE
    value: 3
enum/I2SSRC:
  bit_size: 1
  variants:
  - description: PLLI2S clock used as I2S clock source
    name: PLLI2S
    value: 0
  - description: External clock mapped on the I2S_CKIN pin used as I2S clock source
    name: CKIN
    value: 1
enum/ISSRC:
  bit_size: 1
  variants:
  - description: PLLI2S clock used as I2S clock source
    name: PLLI2S
    value: 0
  - description: External clock mapped on the I2S_CKIN pin used as I2S clock source
    name: CKIN
    value: 1
enum/LPTIMSEL:
  bit_size: 2
  variants:
  - description: APB1 clock (PCLK1) selected as LPTILM1 clock
    name: APB1
    value: 0
  - description: LSI clock is selected as LPTILM1 clock
    name: LSI
    value: 1
  - description: HSI clock is selected as LPTILM1 clock
    name: HSI
    value: 2
  - description: LSE clock is selected as LPTILM1 clock
    name: LSE
    value: 3
enum/LPWRRSTFR:
  bit_size: 1
  variants:
  - description: No reset has occured
    name: NoReset
    value: 0
  - description: A reset has occured
    name: Reset
    value: 1
enum/LSEBYP:
  bit_size: 1
  variants:
  - description: LSE crystal oscillator not bypassed
    name: NotBypassed
    value: 0
  - description: LSE crystal oscillator bypassed with external clock
    name: Bypassed
    value: 1
enum/LSEMOD:
  bit_size: 1
  variants:
  - description: LSE oscillator low power mode selection
    name: Low
    value: 0
  - description: LSE oscillator high drive mode selection
    name: High
    value: 1
enum/LSEON:
  bit_size: 1
  variants:
  - description: LSE oscillator Off
    name: 'Off'
    value: 0
  - description: LSE oscillator On
    name: 'On'
    value: 1
enum/LSERDYR:
  bit_size: 1
  variants:
  - description: LSE oscillator not ready
    name: NotReady
    value: 0
  - description: LSE oscillator ready
    name: Ready
    value: 1
enum/LSION:
  bit_size: 1
  variants:
  - description: LSI oscillator Off
    name: 'Off'
    value: 0
  - description: LSI oscillator On
    name: 'On'
    value: 1
enum/LSIRDYR:
  bit_size: 1
  variants:
  - description: LSI oscillator not ready
    name: NotReady
    value: 0
  - description: LSI oscillator ready
    name: Ready
    value: 1
enum/MCO1:
  bit_size: 2
  variants:
  - description: HSI clock selected
    name: HSI
    value: 0
  - description: LSE oscillator selected
    name: LSE
    value: 1
  - description: HSE oscillator clock selected
    name: HSE
    value: 2
  - description: PLL clock selected
    name: PLL
    value: 3
enum/MCO2:
  bit_size: 2
  variants:
  - description: System clock (SYSCLK) selected
    name: SYSCLK
    value: 0
  - description: PLLI2S clock selected
    name: PLLI2S
    value: 1
  - description: HSE oscillator clock selected
    name: HSE
    value: 2
  - description: PLL clock selected
    name: PLL
    value: 3
enum/MCOPRE:
  bit_size: 3
  variants:
  - description: No division
    name: Div1
    value: 0
  - description: Division by 2
    name: Div2
    value: 4
  - description: Division by 3
    name: Div3
    value: 5
  - description: Division by 4
    name: Div4
    value: 6
  - description: Division by 5
    name: Div5
    value: 7
enum/PLLDIVR:
  bit_size: 5
  variants:
  - description: PLLSAIDIVQ = /1
    name: Div1
    value: 0
  - description: PLLSAIDIVQ = /2
    name: Div2
    value: 1
  - description: PLLSAIDIVQ = /3
    name: Div3
    value: 2
  - description: PLLSAIDIVQ = /4
    name: Div4
    value: 3
  - description: PLLSAIDIVQ = /5
    name: Div5
    value: 4
  - description: PLLSAIDIVQ = /6
    name: Div6
    value: 5
  - description: PLLSAIDIVQ = /7
    name: Div7
    value: 6
  - description: PLLSAIDIVQ = /8
    name: Div8
    value: 7
  - description: PLLSAIDIVQ = /9
    name: Div9
    value: 8
  - description: PLLSAIDIVQ = /10
    name: Div10
    value: 9
  - description: PLLSAIDIVQ = /11
    name: Div11
    value: 10
  - description: PLLSAIDIVQ = /12
    name: Div12
    value: 11
  - description: PLLSAIDIVQ = /13
    name: Div13
    value: 12
  - description: PLLSAIDIVQ = /14
    name: Div14
    value: 13
  - description: PLLSAIDIVQ = /15
    name: Div15
    value: 14
  - description: PLLSAIDIVQ = /16
    name: Div16
    value: 15
  - description: PLLSAIDIVQ = /17
    name: Div17
    value: 16
  - description: PLLSAIDIVQ = /18
    name: Div18
    value: 17
  - description: PLLSAIDIVQ = /19
    name: Div19
    value: 18
  - description: PLLSAIDIVQ = /20
    name: Div20
    value: 19
  - description: PLLSAIDIVQ = /21
    name: Div21
    value: 20
  - description: PLLSAIDIVQ = /22
    name: Div22
    value: 21
  - description: PLLSAIDIVQ = /23
    name: Div23
    value: 22
  - description: PLLSAIDIVQ = /24
    name: Div24
    value: 23
  - description: PLLSAIDIVQ = /25
    name: Div25
    value: 24
  - description: PLLSAIDIVQ = /26
    name: Div26
    value: 25
  - description: PLLSAIDIVQ = /27
    name: Div27
    value: 26
  - description: PLLSAIDIVQ = /28
    name: Div28
    value: 27
  - description: PLLSAIDIVQ = /29
    name: Div29
    value: 28
  - description: PLLSAIDIVQ = /30
    name: Div30
    value: 29
  - description: PLLSAIDIVQ = /31
    name: Div31
    value: 30
  - description: PLLSAIDIVQ = /32
    name: Div32
    value: 31
enum/PLLISDIVQ:
  bit_size: 5
  variants:
  - description: PLLI2SDIVQ = /1
    name: Div1
    value: 0
  - description: PLLI2SDIVQ = /2
    name: Div2
    value: 1
  - description: PLLI2SDIVQ = /3
    name: Div3
    value: 2
  - description: PLLI2SDIVQ = /4
    name: Div4
    value: 3
  - description: PLLI2SDIVQ = /5
    name: Div5
    value: 4
  - description: PLLI2SDIVQ = /6
    name: Div6
    value: 5
  - description: PLLI2SDIVQ = /7
    name: Div7
    value: 6
  - description: PLLI2SDIVQ = /8
    name: Div8
    value: 7
  - description: PLLI2SDIVQ = /9
    name: Div9
    value: 8
  - description: PLLI2SDIVQ = /10
    name: Div10
    value: 9
  - description: PLLI2SDIVQ = /11
    name: Div11
    value: 10
  - description: PLLI2SDIVQ = /12
    name: Div12
    value: 11
  - description: PLLI2SDIVQ = /13
    name: Div13
    value: 12
  - description: PLLI2SDIVQ = /14
    name: Div14
    value: 13
  - description: PLLI2SDIVQ = /15
    name: Div15
    value: 14
  - description: PLLI2SDIVQ = /16
    name: Div16
    value: 15
  - description: PLLI2SDIVQ = /17
    name: Div17
    value: 16
  - description: PLLI2SDIVQ = /18
    name: Div18
    value: 17
  - description: PLLI2SDIVQ = /19
    name: Div19
    value: 18
  - description: PLLI2SDIVQ = /20
    name: Div20
    value: 19
  - description: PLLI2SDIVQ = /21
    name: Div21
    value: 20
  - description: PLLI2SDIVQ = /22
    name: Div22
    value: 21
  - description: PLLI2SDIVQ = /23
    name: Div23
    value: 22
  - description: PLLI2SDIVQ = /24
    name: Div24
    value: 23
  - description: PLLI2SDIVQ = /25
    name: Div25
    value: 24
  - description: PLLI2SDIVQ = /26
    name: Div26
    value: 25
  - description: PLLI2SDIVQ = /27
    name: Div27
    value: 26
  - description: PLLI2SDIVQ = /28
    name: Div28
    value: 27
  - description: PLLI2SDIVQ = /29
    name: Div29
    value: 28
  - description: PLLI2SDIVQ = /30
    name: Div30
    value: 29
  - description: PLLI2SDIVQ = /31
    name: Div31
    value: 30
  - description: PLLI2SDIVQ = /32
    name: Div32
    value: 31
enum/PLLISDIVR:
  bit_size: 5
  variants:
  - description: PLLI2SDIVQ = /1
    name: Div1
    value: 0
  - description: PLLI2SDIVQ = /2
    name: Div2
    value: 1
  - description: PLLI2SDIVQ = /3
    name: Div3
    value: 2
  - description: PLLI2SDIVQ = /4
    name: Div4
    value: 3
  - description: PLLI2SDIVQ = /5
    name: Div5
    value: 4
  - description: PLLI2SDIVQ = /6
    name: Div6
    value: 5
  - description: PLLI2SDIVQ = /7
    name: Div7
    value: 6
  - description: PLLI2SDIVQ = /8
    name: Div8
    value: 7
  - description: PLLI2SDIVQ = /9
    name: Div9
    value: 8
  - description: PLLI2SDIVQ = /10
    name: Div10
    value: 9
  - description: PLLI2SDIVQ = /11
    name: Div11
    value: 10
  - description: PLLI2SDIVQ = /12
    name: Div12
    value: 11
  - description: PLLI2SDIVQ = /13
    name: Div13
    value: 12
  - description: PLLI2SDIVQ = /14
    name: Div14
    value: 13
  - description: PLLI2SDIVQ = /15
    name: Div15
    value: 14
  - description: PLLI2SDIVQ = /16
    name: Div16
    value: 15
  - description: PLLI2SDIVQ = /17
    name: Div17
    value: 16
  - description: PLLI2SDIVQ = /18
    name: Div18
    value: 17
  - description: PLLI2SDIVQ = /19
    name: Div19
    value: 18
  - description: PLLI2SDIVQ = /20
    name: Div20
    value: 19
  - description: PLLI2SDIVQ = /21
    name: Div21
    value: 20
  - description: PLLI2SDIVQ = /22
    name: Div22
    value: 21
  - description: PLLI2SDIVQ = /23
    name: Div23
    value: 22
  - description: PLLI2SDIVQ = /24
    name: Div24
    value: 23
  - description: PLLI2SDIVQ = /25
    name: Div25
    value: 24
  - description: PLLI2SDIVQ = /26
    name: Div26
    value: 25
  - description: PLLI2SDIVQ = /27
    name: Div27
    value: 26
  - description: PLLI2SDIVQ = /28
    name: Div28
    value: 27
  - description: PLLI2SDIVQ = /29
    name: Div29
    value: 28
  - description: PLLI2SDIVQ = /30
    name: Div30
    value: 29
  - description: PLLI2SDIVQ = /31
    name: Div31
    value: 30
  - description: PLLI2SDIVQ = /32
    name: Div32
    value: 31
enum/PLLISON:
  bit_size: 1
  variants:
  - description: Clock Off
    name: 'Off'
    value: 0
  - description: Clock On
    name: 'On'
    value: 1
enum/PLLISP:
  bit_size: 2
  variants:
  - description: PLL*P=2
    name: Div2
    value: 0
  - description: PLL*P=4
    name: Div4
    value: 1
  - description: PLL*P=6
    name: Div6
    value: 2
  - description: PLL*P=8
    name: Div8
    value: 3
enum/PLLISRDYCW:
  bit_size: 1
  variants:
  - description: Clear interrupt flag
    name: Clear
    value: 1
enum/PLLISRDYFR:
  bit_size: 1
  variants:
  - description: No clock ready interrupt
    name: NotInterrupted
    value: 0
  - description: Clock ready interrupt
    name: Interrupted
    value: 1
enum/PLLISRDYIE:
  bit_size: 1
  variants:
  - description: Interrupt disabled
    name: Disabled
    value: 0
  - description: Interrupt enabled
    name: Enabled
    value: 1
enum/PLLISRDYR:
  bit_size: 1
  variants:
  - description: Clock not ready
    name: NotReady
    value: 0
  - description: Clock ready
    name: Ready
    value: 1
enum/PLLISSRC:
  bit_size: 1
  variants:
  - description: HSE or HSI depending on PLLSRC of PLLCFGR
    name: HSE_HSI
    value: 0
  - description: External AFI clock (CK_PLLI2S_EXT) selected as PLL clock entry
    name: External
    value: 1
enum/PLLON:
  bit_size: 1
  variants:
  - description: Clock Off
    name: 'Off'
    value: 0
  - description: Clock On
    name: 'On'
    value: 1
enum/PLLP:
  bit_size: 2
  variants:
  - description: PLLP=2
    name: Div2
    value: 0
  - description: PLLP=4
    name: Div4
    value: 1
  - description: PLLP=6
    name: Div6
    value: 2
  - description: PLLP=8
    name: Div8
    value: 3
enum/PLLRDYFR:
  bit_size: 1
  variants:
  - description: No clock ready interrupt
    name: NotInterrupted
    value: 0
  - description: Clock ready interrupt
    name: Interrupted
    value: 1
enum/PLLRDYIE:
  bit_size: 1
  variants:
  - description: Interrupt disabled
    name: Disabled
    value: 0
  - description: Interrupt enabled
    name: Enabled
    value: 1
enum/PLLRDYR:
  bit_size: 1
  variants:
  - description: Clock not ready
    name: NotReady
    value: 0
  - description: Clock ready
    name: Ready
    value: 1
enum/PLLSAIDIVQ:
  bit_size: 5
  variants:
  - description: PLLSAIDIVQ = /1
    name: Div1
    value: 0
  - description: PLLSAIDIVQ = /2
    name: Div2
    value: 1
  - description: PLLSAIDIVQ = /3
    name: Div3
    value: 2
  - description: PLLSAIDIVQ = /4
    name: Div4
    value: 3
  - description: PLLSAIDIVQ = /5
    name: Div5
    value: 4
  - description: PLLSAIDIVQ = /6
    name: Div6
    value: 5
  - description: PLLSAIDIVQ = /7
    name: Div7
    value: 6
  - description: PLLSAIDIVQ = /8
    name: Div8
    value: 7
  - description: PLLSAIDIVQ = /9
    name: Div9
    value: 8
  - description: PLLSAIDIVQ = /10
    name: Div10
    value: 9
  - description: PLLSAIDIVQ = /11
    name: Div11
    value: 10
  - description: PLLSAIDIVQ = /12
    name: Div12
    value: 11
  - description: PLLSAIDIVQ = /13
    name: Div13
    value: 12
  - description: PLLSAIDIVQ = /14
    name: Div14
    value: 13
  - description: PLLSAIDIVQ = /15
    name: Div15
    value: 14
  - description: PLLSAIDIVQ = /16
    name: Div16
    value: 15
  - description: PLLSAIDIVQ = /17
    name: Div17
    value: 16
  - description: PLLSAIDIVQ = /18
    name: Div18
    value: 17
  - description: PLLSAIDIVQ = /19
    name: Div19
    value: 18
  - description: PLLSAIDIVQ = /20
    name: Div20
    value: 19
  - description: PLLSAIDIVQ = /21
    name: Div21
    value: 20
  - description: PLLSAIDIVQ = /22
    name: Div22
    value: 21
  - description: PLLSAIDIVQ = /23
    name: Div23
    value: 22
  - description: PLLSAIDIVQ = /24
    name: Div24
    value: 23
  - description: PLLSAIDIVQ = /25
    name: Div25
    value: 24
  - description: PLLSAIDIVQ = /26
    name: Div26
    value: 25
  - description: PLLSAIDIVQ = /27
    name: Div27
    value: 26
  - description: PLLSAIDIVQ = /28
    name: Div28
    value: 27
  - description: PLLSAIDIVQ = /29
    name: Div29
    value: 28
  - description: PLLSAIDIVQ = /30
    name: Div30
    value: 29
  - description: PLLSAIDIVQ = /31
    name: Div31
    value: 30
  - description: PLLSAIDIVQ = /32
    name: Div32
    value: 31
enum/PLLSAIDIVR:
  bit_size: 2
  variants:
  - description: PLLSAIDIVR = /2
    name: Div2
    value: 0
  - description: PLLSAIDIVR = /4
    name: Div4
    value: 1
  - description: PLLSAIDIVR = /8
    name: Div8
    value: 2
  - description: PLLSAIDIVR = /16
    name: Div16
    value: 3
enum/PLLSAIP:
  bit_size: 2
  variants:
  - description: PLL*P=2
    name: Div2
    value: 0
  - description: PLL*P=4
    name: Div4
    value: 1
  - description: PLL*P=6
    name: Div6
    value: 2
  - description: PLL*P=8
    name: Div8
    value: 3
enum/PLLSAIRDYCW:
  bit_size: 1
  variants:
  - description: Clear interrupt flag
    name: Clear
    value: 1
enum/PLLSAIRDYFR:
  bit_size: 1
  variants:
  - description: No clock ready interrupt
    name: NotInterrupted
    value: 0
  - description: Clock ready interrupt
    name: Interrupted
    value: 1
enum/PLLSAIRDYIE:
  bit_size: 1
  variants:
  - description: Interrupt disabled
    name: Disabled
    value: 0
  - description: Interrupt enabled
    name: Enabled
    value: 1
enum/PLLSRC:
  bit_size: 1
  variants:
  - description: HSI clock selected as PLL and PLLI2S clock entry
    name: HSI
    value: 0
  - description: HSE oscillator clock selected as PLL and PLLI2S clock entry
    name: HSE
    value: 1
enum/PPRE:
  bit_size: 3
  variants:
  - description: HCLK not divided
    name: Div1
    value: 0
  - description: HCLK divided by 2
    name: Div2
    value: 4
  - description: HCLK divided by 4
    name: Div4
    value: 5
  - description: HCLK divided by 8
    name: Div8
    value: 6
  - description: HCLK divided by 16
    name: Div16
    value: 7
enum/RMVFW:
  bit_size: 1
  variants:
  - description: Clears the reset flag
    name: Clear
    value: 1
enum/RTCSEL:
  bit_size: 2
  variants:
  - description: No clock
    name: NoClock
    value: 0
  - description: LSE oscillator clock used as RTC clock
    name: LSE
    value: 1
  - description: LSI oscillator clock used as RTC clock
    name: LSI
    value: 2
  - description: HSE oscillator clock divided by a prescaler used as RTC clock
    name: HSE
    value: 3
enum/SAI1SRC:
  bit_size: 2
  variants:
  - description: SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ
    name: PLLSAI
    value: 0
  - description: SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ
    name: PLLI2S
    value: 1
  - description: SAI1 clock frequency = f(PLL_R)
    name: PLLR
    value: 2
  - description: I2S_CKIN Alternate function input frequency
    name: I2S_CKIN
    value: 3
enum/SAI2SRC:
  bit_size: 2
  variants:
  - description: SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ
    name: PLLSAI
    value: 0
  - description: SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ
    name: PLLI2S
    value: 1
  - description: SAI2 clock frequency = f(PLL_R)
    name: PLLR
    value: 2
  - description: SAI2 clock frequency = Alternate function input frequency
    name: HSI_HSE
    value: 3
enum/SAIASRC:
  bit_size: 2
  variants:
  - description: SAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ
    name: PLLSAI
    value: 0
  - description: SAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ
    name: PLLI2S
    value: 1
  - description: SAI1-A clock frequency = Alternate function input frequency
    name: I2S_CKIN
    value: 2
enum/SAIBSRC:
  bit_size: 2
  variants:
  - description: SAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ
    name: PLLSAI
    value: 0
  - description: SAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ
    name: PLLI2S
    value: 1
  - description: SAI1-B clock frequency = Alternate function input frequency
    name: I2S_CKIN
    value: 2
enum/SDIOSEL:
  bit_size: 1
  variants:
  - description: 48 MHz clock is selected as SD clock
    name: CK48M
    value: 0
  - description: System clock is selected as SD clock
    name: SYSCLK
    value: 1
enum/SPDIFRXSEL:
  bit_size: 1
  variants:
  - description: SPDIF-Rx clock from PLL is selected
    name: PLL
    value: 0
  - description: SPDIF-Rx clock from PLLI2S is selected
    name: PLLI2S
    value: 1
enum/SPREADSEL:
  bit_size: 1
  variants:
  - description: Center spread
    name: Center
    value: 0
  - description: Down spread
    name: Down
    value: 1
enum/SW:
  bit_size: 2
  variants:
  - description: HSI selected as system clock
    name: HSI
    value: 0
  - description: HSE selected as system clock
    name: HSE
    value: 1
  - description: PLL selected as system clock
    name: PLL
    value: 2
enum/SWSR:
  bit_size: 2
  variants:
  - description: HSI oscillator used as system clock
    name: HSI
    value: 0
  - description: HSE oscillator used as system clock
    name: HSE
    value: 1
  - description: PLL used as system clock
    name: PLL
    value: 2
enum/TIMPRE:
  bit_size: 1
  variants:
  - description: If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise,
      TIMxCLK = 2xPCLKx
    name: Mul2
    value: 0
  - description: If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise,
      TIMxCLK = 4xPCLKx
    name: Mul4
    value: 1
fieldset/AHB1ENR:
  description: AHB1 peripheral clock register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: IO port A clock enable
    name: GPIOAEN
  - bit_offset: 1
    bit_size: 1
    description: IO port B clock enable
    name: GPIOBEN
  - bit_offset: 2
    bit_size: 1
    description: IO port C clock enable
    name: GPIOCEN
  - bit_offset: 3
    bit_size: 1
    description: IO port D clock enable
    name: GPIODEN
  - bit_offset: 4
    bit_size: 1
    description: IO port E clock enable
    name: GPIOEEN
  - bit_offset: 7
    bit_size: 1
    description: IO port H clock enable
    name: GPIOHEN
  - bit_offset: 12
    bit_size: 1
    description: CRC clock enable
    name: CRCEN
  - bit_offset: 21
    bit_size: 1
    description: DMA1 clock enable
    name: DMA1EN
  - bit_offset: 22
    bit_size: 1
    description: DMA2 clock enable
    name: DMA2EN
  - bit_offset: 5
    bit_size: 1
    description: IO port F clock enable
    name: GPIOFEN
  - bit_offset: 6
    bit_size: 1
    description: IO port G clock enable
    name: GPIOGEN
  - bit_offset: 8
    bit_size: 1
    description: IO port I clock enable
    name: GPIOIEN
  - bit_offset: 18
    bit_size: 1
    description: Backup SRAM interface clock enable
    name: BKPSRAMEN
  - bit_offset: 25
    bit_size: 1
    description: Ethernet MAC clock enable
    name: ETHMACEN
  - bit_offset: 26
    bit_size: 1
    description: Ethernet Transmission clock enable
    name: ETHMACTXEN
  - bit_offset: 27
    bit_size: 1
    description: Ethernet Reception clock enable
    name: ETHMACRXEN
  - bit_offset: 28
    bit_size: 1
    description: Ethernet PTP clock enable
    name: ETHMACPTPEN
  - bit_offset: 29
    bit_size: 1
    description: USB OTG HS clock enable
    name: OTGHSEN
  - bit_offset: 30
    bit_size: 1
    description: USB OTG HSULPI clock enable
    name: OTGHSULPIEN
  - bit_offset: 31
    bit_size: 1
    description: RNG clock enable
    name: RNGEN
  - bit_offset: 9
    bit_size: 1
    description: IO port J clock enable
    name: GPIOJEN
  - bit_offset: 10
    bit_size: 1
    description: IO port K clock enable
    name: GPIOKEN
  - bit_offset: 23
    bit_size: 1
    description: DMA2D clock enable
    name: DMA2DEN
  - bit_offset: 20
    bit_size: 1
    description: CCM data RAM clock enable
    name: CCMDATARAMEN
fieldset/AHB1LPENR:
  description: AHB1 peripheral clock enable in low power mode register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: IO port A clock enable during sleep mode
    name: GPIOALPEN
  - bit_offset: 1
    bit_size: 1
    description: IO port B clock enable during Sleep mode
    name: GPIOBLPEN
  - bit_offset: 2
    bit_size: 1
    description: IO port C clock enable during Sleep mode
    name: GPIOCLPEN
  - bit_offset: 3
    bit_size: 1
    description: IO port D clock enable during Sleep mode
    name: GPIODLPEN
  - bit_offset: 4
    bit_size: 1
    description: IO port E clock enable during Sleep mode
    name: GPIOELPEN
  - bit_offset: 7
    bit_size: 1
    description: IO port H clock enable during Sleep mode
    name: GPIOHLPEN
  - bit_offset: 12
    bit_size: 1
    description: CRC clock enable during Sleep mode
    name: CRCLPEN
  - bit_offset: 15
    bit_size: 1
    description: Flash interface clock enable during Sleep mode
    name: FLITFLPEN
  - bit_offset: 16
    bit_size: 1
    description: SRAM 1interface clock enable during Sleep mode
    name: SRAM1LPEN
  - bit_offset: 21
    bit_size: 1
    description: DMA1 clock enable during Sleep mode
    name: DMA1LPEN
  - bit_offset: 22
    bit_size: 1
    description: DMA2 clock enable during Sleep mode
    name: DMA2LPEN
  - bit_offset: 5
    bit_size: 1
    description: IO port F clock enable during Sleep mode
    name: GPIOFLPEN
  - bit_offset: 6
    bit_size: 1
    description: IO port G clock enable during Sleep mode
    name: GPIOGLPEN
  - bit_offset: 8
    bit_size: 1
    description: IO port I clock enable during Sleep mode
    name: GPIOILPEN
  - bit_offset: 17
    bit_size: 1
    description: SRAM 2 interface clock enable during Sleep mode
    name: SRAM2LPEN
  - bit_offset: 18
    bit_size: 1
    description: Backup SRAM interface clock enable during Sleep mode
    name: BKPSRAMLPEN
  - bit_offset: 25
    bit_size: 1
    description: Ethernet MAC clock enable during Sleep mode
    name: ETHMACLPEN
  - bit_offset: 26
    bit_size: 1
    description: Ethernet transmission clock enable during Sleep mode
    name: ETHMACTXLPEN
  - bit_offset: 27
    bit_size: 1
    description: Ethernet reception clock enable during Sleep mode
    name: ETHMACRXLPEN
  - bit_offset: 28
    bit_size: 1
    description: Ethernet PTP clock enable during Sleep mode
    name: ETHMACPTPLPEN
  - bit_offset: 29
    bit_size: 1
    description: USB OTG HS clock enable during Sleep mode
    name: OTGHSLPEN
  - bit_offset: 30
    bit_size: 1
    description: USB OTG HS ULPI clock enable during Sleep mode
    name: OTGHSULPILPEN
  - bit_offset: 31
    bit_size: 1
    description: RNG clock enable during sleep mode
    name: RNGLPEN
  - bit_offset: 9
    bit_size: 1
    description: IO port J clock enable during Sleep mode
    name: GPIOJLPEN
  - bit_offset: 10
    bit_size: 1
    description: IO port K clock enable during Sleep mode
    name: GPIOKLPEN
  - bit_offset: 19
    bit_size: 1
    description: SRAM 3 interface clock enable during Sleep mode
    name: SRAM3LPEN
  - bit_offset: 23
    bit_size: 1
    description: DMA2D clock enable during Sleep mode
    name: DMA2DLPEN
fieldset/AHB1RSTR:
  description: AHB1 peripheral reset register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: IO port A reset
    name: GPIOARST
  - bit_offset: 1
    bit_size: 1
    description: IO port B reset
    name: GPIOBRST
  - bit_offset: 2
    bit_size: 1
    description: IO port C reset
    name: GPIOCRST
  - bit_offset: 3
    bit_size: 1
    description: IO port D reset
    name: GPIODRST
  - bit_offset: 4
    bit_size: 1
    description: IO port E reset
    name: GPIOERST
  - bit_offset: 7
    bit_size: 1
    description: IO port H reset
    name: GPIOHRST
  - bit_offset: 12
    bit_size: 1
    description: CRC reset
    name: CRCRST
  - bit_offset: 21
    bit_size: 1
    description: DMA2 reset
    name: DMA1RST
  - bit_offset: 22
    bit_size: 1
    description: DMA2 reset
    name: DMA2RST
  - bit_offset: 5
    bit_size: 1
    description: IO port F reset
    name: GPIOFRST
  - bit_offset: 6
    bit_size: 1
    description: IO port G reset
    name: GPIOGRST
  - bit_offset: 8
    bit_size: 1
    description: IO port I reset
    name: GPIOIRST
  - bit_offset: 25
    bit_size: 1
    description: Ethernet MAC reset
    name: ETHMACRST
  - bit_offset: 29
    bit_size: 1
    description: USB OTG HS module reset
    name: OTGHSRST
  - bit_offset: 31
    bit_size: 1
    description: RNGRST
    name: RNGRST
  - bit_offset: 9
    bit_size: 1
    description: IO port J reset
    name: GPIOJRST
  - bit_offset: 10
    bit_size: 1
    description: IO port K reset
    name: GPIOKRST
  - bit_offset: 23
    bit_size: 1
    description: DMA2D reset
    name: DMA2DRST
fieldset/AHB2ENR:
  description: AHB2 peripheral clock enable register
  fields:
  - bit_offset: 7
    bit_size: 1
    description: USB OTG FS clock enable
    name: OTGFSEN
  - bit_offset: 0
    bit_size: 1
    description: Camera interface enable
    name: DCMIEN
  - bit_offset: 6
    bit_size: 1
    description: Random number generator clock enable
    name: RNGEN
  - bit_offset: 4
    bit_size: 1
    description: CRYP clock enable
    name: CRYPEN
  - bit_offset: 5
    bit_size: 1
    description: Hash modules clock enable
    name: HASHEN
fieldset/AHB2LPENR:
  description: AHB2 peripheral clock enable in low power mode register
  fields:
  - bit_offset: 7
    bit_size: 1
    description: USB OTG FS clock enable during Sleep mode
    name: OTGFSLPEN
  - bit_offset: 0
    bit_size: 1
    description: Camera interface enable during Sleep mode
    name: DCMILPEN
  - bit_offset: 6
    bit_size: 1
    description: Random number generator clock enable during Sleep mode
    name: RNGLPEN
  - bit_offset: 0
    bit_size: 1
    description: Flexible memory controller module clock enable during Sleep mode
    name: FSMCLPEN
  - bit_offset: 1
    bit_size: 1
    description: QUADSPI memory controller module clock enable during Sleep mode
    name: QSPILPEN
  - bit_offset: 4
    bit_size: 1
    description: Cryptography modules clock enable during Sleep mode
    name: CRYPLPEN
  - bit_offset: 5
    bit_size: 1
    description: Hash modules clock enable during Sleep mode
    name: HASHLPEN
fieldset/AHB2RSTR:
  description: AHB2 peripheral reset register
  fields:
  - bit_offset: 7
    bit_size: 1
    description: USB OTG FS module reset
    name: OTGFSRST
  - bit_offset: 0
    bit_size: 1
    description: Camera interface reset
    name: DCMIRST
  - bit_offset: 6
    bit_size: 1
    description: Random number generator module reset
    name: RNGRST
  - bit_offset: 4
    bit_size: 1
    description: CRYP module reset
    name: CRYPRST
  - bit_offset: 5
    bit_size: 1
    description: Hash module reset
    name: HSAHRST
fieldset/AHB3ENR:
  description: AHB3 peripheral clock enable register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Flexible static memory controller module clock enable
    name: FSMCEN
  - bit_offset: 1
    bit_size: 1
    description: QUADSPI memory controller module clock enable
    name: QSPIEN
  - bit_offset: 0
    bit_size: 1
    description: Flexible static memory controller module clock enable
    name: FMCEN
fieldset/AHB3LPENR:
  description: AHB3 peripheral clock enable in low power mode register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Flexible static memory controller module clock enable during Sleep
      mode
    name: FSMCLPEN
  - bit_offset: 1
    bit_size: 1
    description: QUADSPI memory controller module clock enable during Sleep mode
    name: QSPILPEN
  - bit_offset: 0
    bit_size: 1
    description: Flexible static memory controller module clock enable during Sleep
      mode
    name: FMCLPEN
fieldset/AHB3RSTR:
  description: AHB3 peripheral reset register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Flexible static memory controller module reset
    name: FSMCRST
  - bit_offset: 1
    bit_size: 1
    description: QUADSPI module reset
    name: QSPIRST
  - bit_offset: 0
    bit_size: 1
    description: Flexible static memory controller module reset
    name: FMCRST
fieldset/APB1ENR:
  description: APB1 peripheral clock enable register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: TIM2 clock enable
    name: TIM2EN
  - bit_offset: 1
    bit_size: 1
    description: TIM3 clock enable
    name: TIM3EN
  - bit_offset: 2
    bit_size: 1
    description: TIM4 clock enable
    name: TIM4EN
  - bit_offset: 3
    bit_size: 1
    description: TIM5 clock enable
    name: TIM5EN
  - bit_offset: 11
    bit_size: 1
    description: Window watchdog clock enable
    name: WWDGEN
  - bit_offset: 14
    bit_size: 1
    description: SPI2 clock enable
    name: SPI2EN
  - bit_offset: 15
    bit_size: 1
    description: SPI3 clock enable
    name: SPI3EN
  - bit_offset: 17
    bit_size: 1
    description: USART 2 clock enable
    name: USART2EN
  - bit_offset: 21
    bit_size: 1
    description: I2C1 clock enable
    name: I2C1EN
  - bit_offset: 22
    bit_size: 1
    description: I2C2 clock enable
    name: I2C2EN
  - bit_offset: 23
    bit_size: 1
    description: I2C3 clock enable
    name: I2C3EN
  - bit_offset: 28
    bit_size: 1
    description: Power interface clock enable
    name: PWREN
  - bit_offset: 4
    bit_size: 1
    description: TIM6 clock enable
    name: TIM6EN
  - bit_offset: 5
    bit_size: 1
    description: TIM7 clock enable
    name: TIM7EN
  - bit_offset: 6
    bit_size: 1
    description: TIM12 clock enable
    name: TIM12EN
  - bit_offset: 7
    bit_size: 1
    description: TIM13 clock enable
    name: TIM13EN
  - bit_offset: 8
    bit_size: 1
    description: TIM14 clock enable
    name: TIM14EN
  - bit_offset: 18
    bit_size: 1
    description: USART3 clock enable
    name: USART3EN
  - bit_offset: 19
    bit_size: 1
    description: UART4 clock enable
    name: UART4EN
  - bit_offset: 20
    bit_size: 1
    description: UART5 clock enable
    name: UART5EN
  - bit_offset: 25
    bit_size: 1
    description: CAN 1 clock enable
    name: CAN1EN
  - bit_offset: 26
    bit_size: 1
    description: CAN 2 clock enable
    name: CAN2EN
  - bit_offset: 29
    bit_size: 1
    description: DAC interface clock enable
    name: DACEN
  - bit_offset: 9
    bit_size: 1
    description: LPTIM1 clock enable
    name: LPTIM1EN
  - bit_offset: 10
    bit_size: 1
    description: RTC APB clock enable
    name: RTCAPBEN
  - bit_offset: 24
    bit_size: 1
    description: FMPI2C1 clock enable
    name: FMPI2C1EN
  - bit_offset: 9
    bit_size: 1
    description: LPTimer 1 clock enable
    name: LPTIMER1EN
  - bit_offset: 27
    bit_size: 1
    description: CAN 3 clock enable
    name: CAN3EN
  - bit_offset: 30
    bit_size: 1
    description: UART7 clock enable
    name: UART7EN
  - bit_offset: 31
    bit_size: 1
    description: UART8 clock enable
    name: UART8EN
  - bit_offset: 16
    bit_size: 1
    description: SPDIF-IN clock enable
    name: SPDIFEN
  - bit_offset: 27
    bit_size: 1
    description: CEC interface clock enable
    name: CECEN
fieldset/APB1LPENR:
  description: APB1 peripheral clock enable in low power mode register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: TIM2 clock enable during Sleep mode
    name: TIM2LPEN
  - bit_offset: 1
    bit_size: 1
    description: TIM3 clock enable during Sleep mode
    name: TIM3LPEN
  - bit_offset: 2
    bit_size: 1
    description: TIM4 clock enable during Sleep mode
    name: TIM4LPEN
  - bit_offset: 3
    bit_size: 1
    description: TIM5 clock enable during Sleep mode
    name: TIM5LPEN
  - bit_offset: 11
    bit_size: 1
    description: Window watchdog clock enable during Sleep mode
    name: WWDGLPEN
  - bit_offset: 14
    bit_size: 1
    description: SPI2 clock enable during Sleep mode
    name: SPI2LPEN
  - bit_offset: 15
    bit_size: 1
    description: SPI3 clock enable during Sleep mode
    name: SPI3LPEN
  - bit_offset: 17
    bit_size: 1
    description: USART2 clock enable during Sleep mode
    name: USART2LPEN
  - bit_offset: 21
    bit_size: 1
    description: I2C1 clock enable during Sleep mode
    name: I2C1LPEN
  - bit_offset: 22
    bit_size: 1
    description: I2C2 clock enable during Sleep mode
    name: I2C2LPEN
  - bit_offset: 23
    bit_size: 1
    description: I2C3 clock enable during Sleep mode
    name: I2C3LPEN
  - bit_offset: 28
    bit_size: 1
    description: Power interface clock enable during Sleep mode
    name: PWRLPEN
  - bit_offset: 4
    bit_size: 1
    description: TIM6 clock enable during Sleep mode
    name: TIM6LPEN
  - bit_offset: 5
    bit_size: 1
    description: TIM7 clock enable during Sleep mode
    name: TIM7LPEN
  - bit_offset: 6
    bit_size: 1
    description: TIM12 clock enable during Sleep mode
    name: TIM12LPEN
  - bit_offset: 7
    bit_size: 1
    description: TIM13 clock enable during Sleep mode
    name: TIM13LPEN
  - bit_offset: 8
    bit_size: 1
    description: TIM14 clock enable during Sleep mode
    name: TIM14LPEN
  - bit_offset: 18
    bit_size: 1
    description: USART3 clock enable during Sleep mode
    name: USART3LPEN
  - bit_offset: 19
    bit_size: 1
    description: UART4 clock enable during Sleep mode
    name: UART4LPEN
  - bit_offset: 20
    bit_size: 1
    description: UART5 clock enable during Sleep mode
    name: UART5LPEN
  - bit_offset: 25
    bit_size: 1
    description: CAN 1 clock enable during Sleep mode
    name: CAN1LPEN
  - bit_offset: 26
    bit_size: 1
    description: CAN 2 clock enable during Sleep mode
    name: CAN2LPEN
  - bit_offset: 29
    bit_size: 1
    description: DAC interface clock enable during Sleep mode
    name: DACLPEN
  - bit_offset: 9
    bit_size: 1
    description: LPTIM1 clock enable during sleep mode
    name: LPTIM1LPEN
  - bit_offset: 10
    bit_size: 1
    description: RTC APB clock enable during sleep mode
    name: RTCAPBLPEN
  - bit_offset: 24
    bit_size: 1
    description: FMPI2C1 clock enable during Sleep
    name: FMPI2C1LPEN
  - bit_offset: 9
    bit_size: 1
    description: TIM14 clock enable during Sleep mode
    name: LPTIMER1LPEN
  - bit_offset: 19
    bit_size: 1
    description: USART4 clock enable during Sleep mode
    name: USART4LPEN
  - bit_offset: 20
    bit_size: 1
    description: USART5 clock enable during Sleep mode
    name: USART5LPEN
  - bit_offset: 27
    bit_size: 1
    description: CAN3 clock enable during Sleep mode
    name: CAN3LPEN
  - bit_offset: 30
    bit_size: 1
    description: UART7 clock enable during Sleep mode
    name: UART7LPEN
  - bit_offset: 31
    bit_size: 1
    description: UART8 clock enable during Sleep mode
    name: UART8LPEN
  - bit_offset: 16
    bit_size: 1
    description: SPDIF clock enable during Sleep mode
    name: SPDIFLPEN
  - bit_offset: 27
    bit_size: 1
    description: CEC clock enable during Sleep mode
    name: CECLPEN
fieldset/APB1RSTR:
  description: APB1 peripheral reset register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: TIM2 reset
    name: TIM2RST
  - bit_offset: 1
    bit_size: 1
    description: TIM3 reset
    name: TIM3RST
  - bit_offset: 2
    bit_size: 1
    description: TIM4 reset
    name: TIM4RST
  - bit_offset: 3
    bit_size: 1
    description: TIM5 reset
    name: TIM5RST
  - bit_offset: 11
    bit_size: 1
    description: Window watchdog reset
    name: WWDGRST
  - bit_offset: 14
    bit_size: 1
    description: SPI 2 reset
    name: SPI2RST
  - bit_offset: 15
    bit_size: 1
    description: SPI 3 reset
    name: SPI3RST
  - bit_offset: 17
    bit_size: 1
    description: USART 2 reset
    name: UART2RST
  - bit_offset: 21
    bit_size: 1
    description: I2C 1 reset
    name: I2C1RST
  - bit_offset: 22
    bit_size: 1
    description: I2C 2 reset
    name: I2C2RST
  - bit_offset: 23
    bit_size: 1
    description: I2C3 reset
    name: I2C3RST
  - bit_offset: 28
    bit_size: 1
    description: Power interface reset
    name: PWRRST
  - bit_offset: 4
    bit_size: 1
    description: TIM6 reset
    name: TIM6RST
  - bit_offset: 5
    bit_size: 1
    description: TIM7 reset
    name: TIM7RST
  - bit_offset: 6
    bit_size: 1
    description: TIM12 reset
    name: TIM12RST
  - bit_offset: 7
    bit_size: 1
    description: TIM13 reset
    name: TIM13RST
  - bit_offset: 8
    bit_size: 1
    description: TIM14 reset
    name: TIM14RST
  - bit_offset: 18
    bit_size: 1
    description: USART 3 reset
    name: UART3RST
  - bit_offset: 19
    bit_size: 1
    description: USART 4 reset
    name: UART4RST
  - bit_offset: 20
    bit_size: 1
    description: USART 5 reset
    name: UART5RST
  - bit_offset: 25
    bit_size: 1
    description: CAN1 reset
    name: CAN1RST
  - bit_offset: 26
    bit_size: 1
    description: CAN2 reset
    name: CAN2RST
  - bit_offset: 29
    bit_size: 1
    description: DAC reset
    name: DACRST
  - bit_offset: 9
    bit_size: 1
    description: LPTIM1 reset
    name: LPTIM1RST
  - bit_offset: 24
    bit_size: 1
    description: FMPI2C1 reset
    name: FMPI2C1RST
  - bit_offset: 18
    bit_size: 1
    description: USART3RST
    name: USART3RST
  - bit_offset: 9
    bit_size: 1
    description: LPTimer1 reset
    name: LPTIMER1RST
  - bit_offset: 19
    bit_size: 1
    description: USART4 reset
    name: USART4RST
  - bit_offset: 20
    bit_size: 1
    description: USART5 reset
    name: USART5RST
  - bit_offset: 27
    bit_size: 1
    description: CAN 3 reset
    name: CAN3RST
  - bit_offset: 30
    bit_size: 1
    description: UART 7 reset
    name: UART7RST
  - bit_offset: 31
    bit_size: 1
    description: UART 8 reset
    name: UART8RST
  - bit_offset: 16
    bit_size: 1
    description: SPDIF-IN reset
    name: SPDIFRST
fieldset/APB2ENR:
  description: APB2 peripheral clock enable register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: TIM1 clock enable
    name: TIM1EN
  - bit_offset: 4
    bit_size: 1
    description: USART1 clock enable
    name: USART1EN
  - bit_offset: 5
    bit_size: 1
    description: USART6 clock enable
    name: USART6EN
  - bit_offset: 8
    bit_size: 1
    description: ADC1 clock enable
    name: ADC1EN
  - bit_offset: 11
    bit_size: 1
    description: SDIO clock enable
    name: SDIOEN
  - bit_offset: 12
    bit_size: 1
    description: SPI1 clock enable
    name: SPI1EN
  - bit_offset: 13
    bit_size: 1
    description: SPI4 clock enable
    name: SPI4EN
  - bit_offset: 14
    bit_size: 1
    description: System configuration controller clock enable
    name: SYSCFGEN
  - bit_offset: 16
    bit_size: 1
    description: TIM9 clock enable
    name: TIM9EN
  - bit_offset: 17
    bit_size: 1
    description: TIM10 clock enable
    name: TIM10EN
  - bit_offset: 18
    bit_size: 1
    description: TIM11 clock enable
    name: TIM11EN
  - bit_offset: 1
    bit_size: 1
    description: TIM8 clock enable
    name: TIM8EN
  - bit_offset: 9
    bit_size: 1
    description: ADC2 clock enable
    name: ADC2EN
  - bit_offset: 10
    bit_size: 1
    description: ADC3 clock enable
    name: ADC3EN
  - bit_offset: 15
    bit_size: 1
    description: EXTI ans external IT clock enable
    name: EXTITEN
  - bit_offset: 20
    bit_size: 1
    description: SPI5 clock enable
    name: SPI5EN
  - bit_offset: 24
    bit_size: 1
    description: DFSDMEN
    name: DFSDMEN
  - bit_offset: 6
    bit_size: 1
    description: UART9 clock enable
    name: UART9EN
  - bit_offset: 7
    bit_size: 1
    description: UART10 clock enable
    name: UART10EN
  - bit_offset: 22
    bit_size: 1
    description: SAI 1 clock enable
    name: SAI1EN
  - bit_offset: 25
    bit_size: 1
    description: DFSDM2 clock enable
    name: DFSDM2EN
  - bit_offset: 21
    bit_size: 1
    description: SPI6 clock enable
    name: SPI6EN
  - bit_offset: 26
    bit_size: 1
    description: LTDC clock enable
    name: LTDCEN
  - bit_offset: 23
    bit_size: 1
    description: SAI2 clock enable
    name: SAI2EN
  - bit_offset: 27
    bit_size: 1
    description: DSI clocks enable
    name: DSIEN
fieldset/APB2LPENR:
  description: APB2 peripheral clock enabled in low power mode register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: TIM1 clock enable during Sleep mode
    name: TIM1LPEN
  - bit_offset: 4
    bit_size: 1
    description: USART1 clock enable during Sleep mode
    name: USART1LPEN
  - bit_offset: 5
    bit_size: 1
    description: USART6 clock enable during Sleep mode
    name: USART6LPEN
  - bit_offset: 8
    bit_size: 1
    description: ADC1 clock enable during Sleep mode
    name: ADC1LPEN
  - bit_offset: 11
    bit_size: 1
    description: SDIO clock enable during Sleep mode
    name: SDIOLPEN
  - bit_offset: 12
    bit_size: 1
    description: SPI 1 clock enable during Sleep mode
    name: SPI1LPEN
  - bit_offset: 13
    bit_size: 1
    description: SPI4 clock enable during Sleep mode
    name: SPI4LPEN
  - bit_offset: 14
    bit_size: 1
    description: System configuration controller clock enable during Sleep mode
    name: SYSCFGLPEN
  - bit_offset: 16
    bit_size: 1
    description: TIM9 clock enable during sleep mode
    name: TIM9LPEN
  - bit_offset: 17
    bit_size: 1
    description: TIM10 clock enable during Sleep mode
    name: TIM10LPEN
  - bit_offset: 18
    bit_size: 1
    description: TIM11 clock enable during Sleep mode
    name: TIM11LPEN
  - bit_offset: 1
    bit_size: 1
    description: TIM8 clock enable during Sleep mode
    name: TIM8LPEN
  - bit_offset: 9
    bit_size: 1
    description: ADC2 clock enable during Sleep mode
    name: ADC2LPEN
  - bit_offset: 10
    bit_size: 1
    description: ADC 3 clock enable during Sleep mode
    name: ADC3LPEN
  - bit_offset: 15
    bit_size: 1
    description: EXTI and External IT clock enable during sleep mode
    name: EXTITLPEN
  - bit_offset: 20
    bit_size: 1
    description: SPI5 clock enable during Sleep mode
    name: SPI5LPEN
  - bit_offset: 24
    bit_size: 1
    description: DFSDMLPEN
    name: DFSDMLPEN
  - bit_offset: 6
    bit_size: 1
    description: UART9 clock enable during Sleep mode
    name: UART9LPEN
  - bit_offset: 6
    bit_size: 1
    description: USART9 clock enable during Sleep mode
    name: USART9LPEN
  - bit_offset: 7
    bit_size: 1
    description: UART10 clock enable during Sleep mode
    name: UART10LPEN
  - bit_offset: 7
    bit_size: 1
    description: USART10 clock enable during Sleep mode
    name: USART10LPEN
  - bit_offset: 22
    bit_size: 1
    description: SAI1 clock enable during Sleep mode
    name: SAI1LPEN
  - bit_offset: 25
    bit_size: 1
    description: DFSDM2 clock enable during Sleep mode
    name: DFSDM2LPEN
  - bit_offset: 21
    bit_size: 1
    description: SPI 6 clock enable during Sleep mode
    name: SPI6LPEN
  - bit_offset: 26
    bit_size: 1
    description: LTDC clock enable during Sleep mode
    name: LTDCLPEN
  - bit_offset: 23
    bit_size: 1
    description: SAI2 clock enable
    name: SAI2LPEN
  - bit_offset: 27
    bit_size: 1
    description: DSI clocks enable during Sleep mode
    name: DSILPEN
fieldset/APB2RSTR:
  description: APB2 peripheral reset register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: TIM1 reset
    name: TIM1RST
  - bit_offset: 4
    bit_size: 1
    description: USART1 reset
    name: USART1RST
  - bit_offset: 5
    bit_size: 1
    description: USART6 reset
    name: USART6RST
  - bit_offset: 8
    bit_size: 1
    description: ADC interface reset (common to all ADCs)
    name: ADCRST
  - bit_offset: 11
    bit_size: 1
    description: SDIO reset
    name: SDIORST
  - bit_offset: 12
    bit_size: 1
    description: SPI 1 reset
    name: SPI1RST
  - bit_offset: 13
    bit_size: 1
    description: SPI4 reset
    name: SPI4RST
  - bit_offset: 14
    bit_size: 1
    description: System configuration controller reset
    name: SYSCFGRST
  - bit_offset: 16
    bit_size: 1
    description: TIM9 reset
    name: TIM9RST
  - bit_offset: 17
    bit_size: 1
    description: TIM10 reset
    name: TIM10RST
  - bit_offset: 18
    bit_size: 1
    description: TIM11 reset
    name: TIM11RST
  - bit_offset: 1
    bit_size: 1
    description: TIM8 reset
    name: TIM8RST
  - bit_offset: 20
    bit_size: 1
    description: SPI5 reset
    name: SPI5RST
  - bit_offset: 24
    bit_size: 1
    description: DFSDMRST
    name: DFSDMRST
  - bit_offset: 6
    bit_size: 1
    description: UART9 reset
    name: UART9RST
  - bit_offset: 6
    bit_size: 1
    description: USART9 reset
    name: USART9RST
  - bit_offset: 7
    bit_size: 1
    description: USART10 reset
    name: SART10RST
  - bit_offset: 7
    bit_size: 1
    description: UART10 reset
    name: UART10RST
  - bit_offset: 22
    bit_size: 1
    description: SAI1 reset
    name: SAI1RST
  - bit_offset: 25
    bit_size: 1
    description: DFSDM2 reset
    name: DFSDM2RST
  - bit_offset: 21
    bit_size: 1
    description: SPI6 reset
    name: SPI6RST
  - bit_offset: 26
    bit_size: 1
    description: LTDC reset
    name: LTDCRST
  - bit_offset: 23
    bit_size: 1
    description: SAI2 reset
    name: SAI2RST
  - bit_offset: 27
    bit_size: 1
    description: DSI host reset
    name: DSIRST
fieldset/BDCR:
  description: Backup domain control register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: External low-speed oscillator enable
    enum: LSEON
    name: LSEON
  - bit_offset: 1
    bit_size: 1
    description: External low-speed oscillator ready
    enum_read: LSERDYR
    name: LSERDY
  - bit_offset: 2
    bit_size: 1
    description: External low-speed oscillator bypass
    enum: LSEBYP
    name: LSEBYP
  - bit_offset: 8
    bit_size: 2
    description: RTC clock source selection
    enum: RTCSEL
    name: RTCSEL
  - bit_offset: 15
    bit_size: 1
    description: RTC clock enable
    name: RTCEN
  - bit_offset: 16
    bit_size: 1
    description: Backup domain software reset
    name: BDRST
  - bit_offset: 3
    bit_size: 1
    description: External low-speed oscillator bypass
    enum: LSEMOD
    name: LSEMOD
fieldset/CFGR:
  description: clock configuration register
  fields:
  - bit_offset: 0
    bit_size: 2
    description: System clock switch
    enum: SW
    name: SW
  - bit_offset: 2
    bit_size: 2
    description: System clock switch status
    enum_read: SWSR
    name: SWS
  - bit_offset: 4
    bit_size: 4
    description: AHB prescaler
    enum: HPRE
    name: HPRE
  - array:
      len: 2
      stride: 3
    bit_offset: 10
    bit_size: 3
    description: APB Low speed prescaler (APB1)
    enum: PPRE
    name: PPRE
  - bit_offset: 16
    bit_size: 5
    description: HSE division factor for RTC clock
    name: RTCPRE
  - array:
      len: 2
      stride: 9
    bit_offset: 21
    bit_size: 2
    description: Microcontroller clock output 1
    enum: MCO1
    name: MCO
  - bit_offset: 23
    bit_size: 1
    description: I2S clock selection
    enum: ISSRC
    name: I2SSRC
  - bit_offset: 24
    bit_size: 3
    description: MCO1 prescaler
    enum: MCOPRE
    name: MCO1PRE
  - bit_offset: 27
    bit_size: 3
    description: MCO2 prescaler
    enum: MCOPRE
    name: MCO2PRE
  - bit_offset: 8
    bit_size: 1
    description: MCO output enable
    name: MCO1EN
  - bit_offset: 9
    bit_size: 1
    description: MCO output enable
    name: MCO2EN
fieldset/CIR:
  description: clock interrupt register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: LSI ready interrupt flag
    enum_read: PLLISRDYFR
    name: LSIRDYF
  - bit_offset: 1
    bit_size: 1
    description: LSE ready interrupt flag
    enum_read: PLLISRDYFR
    name: LSERDYF
  - bit_offset: 2
    bit_size: 1
    description: HSI ready interrupt flag
    enum_read: PLLISRDYFR
    name: HSIRDYF
  - bit_offset: 3
    bit_size: 1
    description: HSE ready interrupt flag
    enum_read: PLLISRDYFR
    name: HSERDYF
  - bit_offset: 4
    bit_size: 1
    description: Main PLL (PLL) ready interrupt flag
    enum_read: PLLISRDYFR
    name: PLLRDYF
  - bit_offset: 5
    bit_size: 1
    description: PLLI2S ready interrupt flag
    enum_read: PLLISRDYFR
    name: PLLI2SRDYF
  - bit_offset: 7
    bit_size: 1
    description: Clock security system interrupt flag
    enum_read: CSSFR
    name: CSSF
  - bit_offset: 8
    bit_size: 1
    description: LSI ready interrupt enable
    enum: PLLISRDYIE
    name: LSIRDYIE
  - bit_offset: 9
    bit_size: 1
    description: LSE ready interrupt enable
    enum: PLLISRDYIE
    name: LSERDYIE
  - bit_offset: 10
    bit_size: 1
    description: HSI ready interrupt enable
    enum: PLLISRDYIE
    name: HSIRDYIE
  - bit_offset: 11
    bit_size: 1
    description: HSE ready interrupt enable
    enum: PLLISRDYIE
    name: HSERDYIE
  - bit_offset: 12
    bit_size: 1
    description: Main PLL (PLL) ready interrupt enable
    enum: PLLISRDYIE
    name: PLLRDYIE
  - bit_offset: 13
    bit_size: 1
    description: PLLI2S ready interrupt enable
    enum: PLLISRDYIE
    name: PLLI2SRDYIE
  - bit_offset: 16
    bit_size: 1
    description: LSI ready interrupt clear
    enum_write: PLLISRDYCW
    name: LSIRDYC
  - bit_offset: 17
    bit_size: 1
    description: LSE ready interrupt clear
    enum_write: PLLISRDYCW
    name: LSERDYC
  - bit_offset: 18
    bit_size: 1
    description: HSI ready interrupt clear
    enum_write: PLLISRDYCW
    name: HSIRDYC
  - bit_offset: 19
    bit_size: 1
    description: HSE ready interrupt clear
    enum_write: PLLISRDYCW
    name: HSERDYC
  - bit_offset: 20
    bit_size: 1
    description: Main PLL(PLL) ready interrupt clear
    enum_write: PLLISRDYCW
    name: PLLRDYC
  - bit_offset: 21
    bit_size: 1
    description: PLLI2S ready interrupt clear
    enum_write: PLLISRDYCW
    name: PLLI2SRDYC
  - bit_offset: 23
    bit_size: 1
    description: Clock security system interrupt clear
    enum_write: CSSCW
    name: CSSC
  - bit_offset: 6
    bit_size: 1
    description: PLLSAI ready interrupt flag
    enum_read: PLLSAIRDYFR
    name: PLLSAIRDYF
  - bit_offset: 14
    bit_size: 1
    description: PLLSAI Ready Interrupt Enable
    enum: PLLSAIRDYIE
    name: PLLSAIRDYIE
  - bit_offset: 22
    bit_size: 1
    description: PLLSAI Ready Interrupt Clear
    enum_write: PLLSAIRDYCW
    name: PLLSAIRDYC
fieldset/CKGATENR:
  description: clocks gated enable register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: AHB to APB1 Bridge clock enable
    name: AHB2APB1_CKEN
  - bit_offset: 1
    bit_size: 1
    description: AHB to APB2 Bridge clock enable
    name: AHB2APB2_CKEN
  - bit_offset: 2
    bit_size: 1
    description: Cortex M4 ETM clock enable
    name: CM4DBG_CKEN
  - bit_offset: 3
    bit_size: 1
    description: Spare clock enable
    name: SPARE_CKEN
  - bit_offset: 4
    bit_size: 1
    description: SRAM controller clock enable
    name: SRAM_CKEN
  - bit_offset: 5
    bit_size: 1
    description: Flash interface clock enable
    name: FLITF_CKEN
  - bit_offset: 6
    bit_size: 1
    description: RCC clock enable
    name: RCC_CKEN
  - bit_offset: 7
    bit_size: 1
    description: EVTCL clock enable
    name: EVTCL_CKEN
fieldset/CR:
  description: clock control register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Internal high-speed clock enable
    enum: PLLISON
    name: HSION
  - bit_offset: 1
    bit_size: 1
    description: Internal high-speed clock ready flag
    enum_read: PLLISRDYR
    name: HSIRDY
  - bit_offset: 3
    bit_size: 5
    description: Internal high-speed clock trimming
    name: HSITRIM
  - bit_offset: 8
    bit_size: 8
    description: Internal high-speed clock calibration
    name: HSICAL
  - bit_offset: 16
    bit_size: 1
    description: HSE clock enable
    enum: PLLISON
    name: HSEON
  - bit_offset: 17
    bit_size: 1
    description: HSE clock ready flag
    enum_read: PLLISRDYR
    name: HSERDY
  - bit_offset: 18
    bit_size: 1
    description: HSE clock bypass
    enum: HSEBYP
    name: HSEBYP
  - bit_offset: 19
    bit_size: 1
    description: Clock security system enable
    enum: CSSON
    name: CSSON
  - bit_offset: 24
    bit_size: 1
    description: Main PLL (PLL) enable
    enum: PLLISON
    name: PLLON
  - bit_offset: 25
    bit_size: 1
    description: Main PLL (PLL) clock ready flag
    enum_read: PLLISRDYR
    name: PLLRDY
  - bit_offset: 26
    bit_size: 1
    description: PLLI2S enable
    enum: PLLISON
    name: PLLI2SON
  - bit_offset: 27
    bit_size: 1
    description: PLLI2S clock ready flag
    enum_read: PLLISRDYR
    name: PLLI2SRDY
  - bit_offset: 28
    bit_size: 1
    description: PLLSAI enable
    enum: PLLISON
    name: PLLSAION
  - bit_offset: 29
    bit_size: 1
    description: PLLSAI clock ready flag
    enum_read: PLLISRDYR
    name: PLLSAIRDY
fieldset/CSR:
  description: clock control & status register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Internal low-speed oscillator enable
    enum: LSION
    name: LSION
  - bit_offset: 1
    bit_size: 1
    description: Internal low-speed oscillator ready
    enum_read: LSIRDYR
    name: LSIRDY
  - bit_offset: 24
    bit_size: 1
    description: Remove reset flag
    enum_write: RMVFW
    name: RMVF
  - bit_offset: 25
    bit_size: 1
    description: BOR reset flag
    enum_read: LPWRRSTFR
    name: BORRSTF
  - bit_offset: 26
    bit_size: 1
    description: PIN reset flag
    enum_read: LPWRRSTFR
    name: PADRSTF
  - bit_offset: 27
    bit_size: 1
    description: POR/PDR reset flag
    enum_read: LPWRRSTFR
    name: PORRSTF
  - bit_offset: 28
    bit_size: 1
    description: Software reset flag
    enum_read: LPWRRSTFR
    name: SFTRSTF
  - bit_offset: 29
    bit_size: 1
    description: Independent watchdog reset flag
    enum_read: LPWRRSTFR
    name: WDGRSTF
  - bit_offset: 30
    bit_size: 1
    description: Window watchdog reset flag
    enum_read: LPWRRSTFR
    name: WWDGRSTF
  - bit_offset: 31
    bit_size: 1
    description: Low-power reset flag
    enum_read: LPWRRSTFR
    name: LPWRRSTF
fieldset/DCKCFGR:
  description: Dedicated Clock Configuration Register
  fields:
  - bit_offset: 24
    bit_size: 1
    description: Timers clocks prescalers selection
    enum: TIMPRE
    name: TIMPRE
  - bit_offset: 25
    bit_size: 2
    description: I2SSRC
    enum: ISSRC
    name: I2SSRC
  - bit_offset: 15
    bit_size: 5
    description: DFSDM1 audio clock selection
    enum: CKDFSDMASEL
    name: CKDFSDM1ASEL
  - bit_offset: 25
    bit_size: 2
    description: I2S APB1 clocks source selection (I2S2/3)
    enum: I2S1SRC
    name: I2S1SRC
  - bit_offset: 27
    bit_size: 2
    description: I2S APB2 clocks source selection (I2S1/4/5)
    enum: I2S1SRC
    name: I2S2SRC
  - bit_offset: 31
    bit_size: 1
    description: DFSDM1 Kernel clock selection
    enum: CKDFSDMSEL
    name: CKDFSDM1SEL
  - bit_offset: 0
    bit_size: 5
    description: PLLI2S division factor for SAI1 A/B clock
    enum: PLLISDIVR
    name: PLLI2SDIVR
  - bit_offset: 8
    bit_size: 5
    description: PLL division factor for SAI1 A/B clock
    enum: PLLDIVR
    name: PLLDIVR
  - bit_offset: 14
    bit_size: 1
    description: DFSDM2 audio clock selection
    enum: CKDFSDMASEL
    name: CKDFSDM2ASEL
  - bit_offset: 20
    bit_size: 2
    description: SAI1-A clock source selection
    enum: SAIASRC
    name: SAI1ASRC
  - bit_offset: 22
    bit_size: 2
    description: SAI1-B clock source selection
    enum: SAIBSRC
    name: SAI1BSRC
  - bit_offset: 0
    bit_size: 5
    description: PLLI2S division factor for SAI1 clock
    enum: PLLISDIVQ
    name: PLLI2SDIVQ
  - bit_offset: 8
    bit_size: 5
    description: PLLSAI division factor for SAI1 clock
    enum: PLLSAIDIVQ
    name: PLLSAIDIVQ
  - bit_offset: 16
    bit_size: 2
    description: division factor for LCD_CLK
    enum: PLLSAIDIVR
    name: PLLSAIDIVR
  - bit_offset: 20
    bit_size: 2
    description: SAI1 clock source selection
    enum: SAI1SRC
    name: SAI1SRC
  - bit_offset: 22
    bit_size: 2
    description: SAI2 clock source selection
    enum: SAI2SRC
    name: SAI2SRC
  - bit_offset: 27
    bit_size: 1
    description: 48 MHz clock source selection
    enum: CKMSEL
    name: CK48MSEL
  - bit_offset: 28
    bit_size: 1
    description: SDIO clock source selection
    enum: SDIOSEL
    name: SDIOSEL
  - bit_offset: 29
    bit_size: 1
    description: DSI clock source selection
    enum: DSISEL
    name: DSISEL
fieldset/DCKCFGR2:
  description: dedicated clocks configuration register 2
  fields:
  - bit_offset: 22
    bit_size: 2
    description: FMPI2C1 kernel clock source selection
    enum: FMPICSEL
    name: FMPI2C1SEL
  - bit_offset: 30
    bit_size: 2
    description: LPTIM1SEL
    enum: LPTIMSEL
    name: LPTIM1SEL
  - bit_offset: 27
    bit_size: 1
    description: SDIO/USBFS clock selection
    enum: CKMSEL
    name: CK48MSEL
  - bit_offset: 28
    bit_size: 1
    description: SDIO clock selection
    enum: SDIOSEL
    name: SDIOSEL
  - bit_offset: 26
    bit_size: 1
    description: HDMI CEC clock source selection
    enum: CECSEL
    name: CECSEL
  - bit_offset: 29
    bit_size: 1
    description: SPDIF clock selection
    enum: SPDIFRXSEL
    name: SPDIFRXSEL
fieldset/PLLCFGR:
  description: PLL configuration register
  fields:
  - bit_offset: 0
    bit_size: 6
    description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input
      clock
    name: PLLM
  - bit_offset: 6
    bit_size: 9
    description: Main PLL (PLL) multiplication factor for VCO
    name: PLLN
  - bit_offset: 16
    bit_size: 2
    description: Main PLL (PLL) division factor for main system clock
    enum: PLLP
    name: PLLP
  - bit_offset: 22
    bit_size: 1
    description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
    enum: PLLSRC
    name: PLLSRC
  - bit_offset: 24
    bit_size: 4
    description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number
      generator clocks
    name: PLLQ
  - bit_offset: 28
    bit_size: 3
    description: PLL division factor for I2S and System clocks
    name: PLLR
fieldset/PLLI2SCFGR:
  description: PLLI2S configuration register
  fields:
  - bit_offset: 6
    bit_size: 9
    description: PLLI2S multiplication factor for VCO
    name: PLLI2SN
  - bit_offset: 28
    bit_size: 3
    description: PLLI2S division factor for I2S clocks
    name: PLLI2SR
  - bit_offset: 0
    bit_size: 6
    description: Division factor for the audio PLL (PLLI2S) input clock
    name: PLLI2SM
  - bit_offset: 22
    bit_size: 1
    description: PLLI2S entry clock source
    enum: PLLISSRC
    name: PLLI2SSRC
  - bit_offset: 24
    bit_size: 4
    description: PLLI2S division factor for USB OTG FS/SDIO/RNG clock
    name: PLLI2SQ
  - bit_offset: 16
    bit_size: 2
    description: PLLI2S division factor for SPDIF-IN clock
    enum: PLLISP
    name: PLLI2SP
fieldset/PLLSAICFGR:
  description: PLL configuration register
  fields:
  - bit_offset: 6
    bit_size: 9
    description: PLLSAI division factor for VCO
    name: PLLSAIN
  - bit_offset: 24
    bit_size: 4
    description: PLLSAI division factor for SAI1 clock
    name: PLLSAIQ
  - bit_offset: 28
    bit_size: 3
    description: PLLSAI division factor for LCD clock
    name: PLLSAIR
  - bit_offset: 0
    bit_size: 6
    description: Division factor for audio PLLSAI input clock
    name: PLLSAIM
  - bit_offset: 16
    bit_size: 2
    description: PLLSAI division factor for 48 MHz clock
    enum: PLLSAIP
    name: PLLSAIP
fieldset/SSCGR:
  description: spread spectrum clock generation register
  fields:
  - bit_offset: 0
    bit_size: 13
    description: Modulation period
    name: MODPER
  - bit_offset: 13
    bit_size: 15
    description: Incrementation step
    name: INCSTEP
  - bit_offset: 30
    bit_size: 1
    description: Spread Select
    enum: SPREADSEL
    name: SPREADSEL
  - bit_offset: 31
    bit_size: 1
    description: Spread spectrum modulation enable
    name: SSCGEN