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change DSIPHY to DSI_PHY for rcc_l4plus.yaml to match other families

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JuliDi 2024-04-08 13:48:25 +02:00
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commit dd12c3787a
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data/registers/rcc_l4plus.yaml
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@ -1713,7 +1713,7 @@ enum/DFSDMSEL:
enum/DSISEL:
bit_size: 1
variants:
- name: DSIPHY
- name: DSI_PHY
description: DSI-PHY is selected as DSI byte lane clock source (usual case)
value: 0
- name: PLLSAI2_Q