From dd12c3787ae4b1c812595a5ce9662955045c0a3d Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Mon, 8 Apr 2024 13:48:25 +0200
Subject: [PATCH] change DSIPHY to DSI_PHY for rcc_l4plus.yaml to match other
 families

---
 data/registers/rcc_l4plus.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/data/registers/rcc_l4plus.yaml b/data/registers/rcc_l4plus.yaml
index 17e9f27..9db03de 100644
--- a/data/registers/rcc_l4plus.yaml
+++ b/data/registers/rcc_l4plus.yaml
@@ -1713,7 +1713,7 @@ enum/DFSDMSEL:
 enum/DSISEL:
   bit_size: 1
   variants:
-  - name: DSIPHY
+  - name: DSI_PHY
     description: DSI-PHY is selected as DSI byte lane clock source (usual case)
     value: 0
   - name: PLLSAI2_Q