add free-running clock mode for quadspi

2023-09-03 17:06:27 +02:00 · 2023-09-03 17:06:27 +02:00 · cc8759f205
commit cc8759f205
parent 9a61a1f090
1 changed files with 5 additions and 1 deletions
--- a/data/registers/quadspi_v1.yaml
+++ b/data/registers/quadspi_v1.yaml
@ -112,6 +112,10 @@ fieldset/CCR:
      description: Send instruction only once mode
      bit_offset: 28
      bit_size: 1
+    - name: FRCM
+      description: Free-running clock mode (not available on all chips!)
+      bit_offset: 29
+      bit_size: 1
    - name: DHHC
      description: DDR hold half cycle
      bit_offset: 30
@ -132,7 +136,7 @@ fieldset/CR:
      bit_offset: 1
      bit_size: 1
    - name: DMAEN
-      description: DMA enable
+      description: DMA enable (not available on all chips!)
      bit_offset: 2
      bit_size: 1
    - name: TCEN