From cc8759f205d4813c02b67231b930713b6a48d25a Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Sun, 3 Sep 2023 17:06:27 +0200
Subject: [PATCH] add free-running clock mode for quadspi

---
 data/registers/quadspi_v1.yaml | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/data/registers/quadspi_v1.yaml b/data/registers/quadspi_v1.yaml
index 23c9011..d2012ba 100644
--- a/data/registers/quadspi_v1.yaml
+++ b/data/registers/quadspi_v1.yaml
@@ -112,6 +112,10 @@ fieldset/CCR:
       description: Send instruction only once mode
       bit_offset: 28
       bit_size: 1
+    - name: FRCM
+      description: Free-running clock mode (not available on all chips!)
+      bit_offset: 29
+      bit_size: 1
     - name: DHHC
       description: DDR hold half cycle
       bit_offset: 30
@@ -132,7 +136,7 @@ fieldset/CR:
       bit_offset: 1
       bit_size: 1
     - name: DMAEN
-      description: DMA enable
+      description: DMA enable (not available on all chips!)
       bit_offset: 2
       bit_size: 1
     - name: TCEN