301 lines
6.8 KiB
YAML
301 lines
6.8 KiB
YAML
---
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block/QUADSPI:
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description: QuadSPI interface
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items:
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- name: CR
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description: control register
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byte_offset: 0
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fieldset: CR
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- name: DCR
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description: device configuration register
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byte_offset: 4
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fieldset: DCR
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- name: SR
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description: status register
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byte_offset: 8
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access: Read
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fieldset: SR
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- name: FCR
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description: flag clear register
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byte_offset: 12
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fieldset: FCR
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- name: DLR
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description: data length register
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byte_offset: 16
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fieldset: DLR
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- name: CCR
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description: communication configuration register
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byte_offset: 20
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fieldset: CCR
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- name: AR
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description: address register
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byte_offset: 24
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fieldset: AR
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- name: ABR
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description: ABR
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byte_offset: 28
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fieldset: ABR
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- name: DR
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description: data register
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byte_offset: 32
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fieldset: DR
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- name: PSMKR
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description: polling status mask register
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byte_offset: 36
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fieldset: PSMKR
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- name: PSMAR
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description: polling status match register
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byte_offset: 40
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fieldset: PSMAR
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- name: PIR
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description: polling interval register
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byte_offset: 44
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fieldset: PIR
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- name: LPTR
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description: low-power timeout register
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byte_offset: 48
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fieldset: LPTR
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fieldset/ABR:
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description: ABR
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fields:
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- name: ALTERNATE
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description: ALTERNATE
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bit_offset: 0
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bit_size: 32
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fieldset/AR:
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description: address register
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fields:
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- name: ADDRESS
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description: Address
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bit_offset: 0
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bit_size: 32
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fieldset/CCR:
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description: communication configuration register
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fields:
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- name: INSTRUCTION
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description: Instruction
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bit_offset: 0
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bit_size: 8
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- name: IMODE
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description: Instruction mode
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bit_offset: 8
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bit_size: 2
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- name: ADMODE
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description: Address mode
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bit_offset: 10
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bit_size: 2
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- name: ADSIZE
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description: Address size
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bit_offset: 12
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bit_size: 2
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- name: ABMODE
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description: Alternate bytes mode
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bit_offset: 14
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bit_size: 2
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- name: ABSIZE
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description: Alternate bytes size
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bit_offset: 16
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bit_size: 2
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- name: DCYC
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description: Number of dummy cycles
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bit_offset: 18
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bit_size: 5
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- name: DMODE
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description: Data mode
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bit_offset: 24
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bit_size: 2
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- name: FMODE
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description: Functional mode
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bit_offset: 26
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bit_size: 2
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- name: SIOO
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description: Send instruction only once mode
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bit_offset: 28
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bit_size: 1
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- name: FRCM
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description: Free-running clock mode (not available on all chips!)
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bit_offset: 29
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bit_size: 1
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- name: DHHC
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description: DDR hold half cycle
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bit_offset: 30
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bit_size: 1
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- name: DDRM
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description: Double data rate mode
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bit_offset: 31
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bit_size: 1
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fieldset/CR:
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description: control register
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fields:
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- name: EN
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description: Enable
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bit_offset: 0
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bit_size: 1
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- name: ABORT
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description: Abort request
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bit_offset: 1
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bit_size: 1
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- name: DMAEN
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description: DMA enable (not available on all chips!)
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bit_offset: 2
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bit_size: 1
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- name: TCEN
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description: Timeout counter enable
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bit_offset: 3
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bit_size: 1
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- name: SSHIFT
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description: Sample shift
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bit_offset: 4
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bit_size: 1
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- name: DFM
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description: Dual-flash mode
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bit_offset: 6
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bit_size: 1
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- name: FSEL
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description: FLASH memory selection
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bit_offset: 7
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bit_size: 1
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- name: FTHRES
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description: IFO threshold level
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bit_offset: 8
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bit_size: 5
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- name: TEIE
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description: Transfer error interrupt enable
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bit_offset: 16
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bit_size: 1
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- name: TCIE
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description: Transfer complete interrupt enable
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bit_offset: 17
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bit_size: 1
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- name: FTIE
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description: FIFO threshold interrupt enable
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bit_offset: 18
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bit_size: 1
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- name: SMIE
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description: Status match interrupt enable
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bit_offset: 19
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bit_size: 1
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- name: TOIE
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description: TimeOut interrupt enable
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bit_offset: 20
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bit_size: 1
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- name: APMS
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description: Automatic poll mode stop
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bit_offset: 22
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bit_size: 1
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- name: PMM
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description: Polling match mode
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bit_offset: 23
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bit_size: 1
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- name: PRESCALER
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description: Clock prescaler
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bit_offset: 24
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bit_size: 8
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fieldset/DCR:
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description: device configuration register
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fields:
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- name: CKMODE
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description: Mode 0 / mode 3
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bit_offset: 0
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bit_size: 1
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- name: CSHT
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description: Chip select high time
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bit_offset: 8
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bit_size: 3
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- name: FSIZE
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description: FLASH memory size
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bit_offset: 16
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bit_size: 5
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fieldset/DLR:
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description: data length register
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fields:
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- name: DL
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description: Data length
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bit_offset: 0
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bit_size: 32
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fieldset/DR:
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description: data register
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fields:
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- name: DATA
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description: Data
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bit_offset: 0
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bit_size: 32
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fieldset/FCR:
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description: flag clear register
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fields:
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- name: CTEF
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description: Clear transfer error flag
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bit_offset: 0
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bit_size: 1
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- name: CTCF
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description: Clear transfer complete flag
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bit_offset: 1
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bit_size: 1
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- name: CSMF
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description: Clear status match flag
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bit_offset: 3
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bit_size: 1
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- name: CTOF
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description: Clear timeout flag
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bit_offset: 4
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bit_size: 1
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fieldset/LPTR:
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description: low-power timeout register
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fields:
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- name: TIMEOUT
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description: Timeout period
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bit_offset: 0
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bit_size: 16
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fieldset/PIR:
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description: polling interval register
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fields:
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- name: INTERVAL
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description: Polling interval
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bit_offset: 0
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bit_size: 16
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fieldset/PSMAR:
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description: polling status match register
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fields:
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- name: MATCH
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description: Status match
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bit_offset: 0
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bit_size: 32
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fieldset/PSMKR:
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description: polling status mask register
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fields:
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- name: MASK
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description: Status mask
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bit_offset: 0
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bit_size: 32
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fieldset/SR:
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description: status register
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fields:
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- name: TEF
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description: Transfer error flag
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bit_offset: 0
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bit_size: 1
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- name: TCF
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description: Transfer complete flag
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bit_offset: 1
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bit_size: 1
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- name: FTF
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description: FIFO threshold flag
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bit_offset: 2
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bit_size: 1
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- name: SMF
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description: Status match flag
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bit_offset: 3
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bit_size: 1
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- name: TOF
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description: Timeout flag
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bit_offset: 4
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bit_size: 1
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- name: BUSY
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description: Busy
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bit_offset: 5
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bit_size: 1
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- name: FLEVEL
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description: FIFO level
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bit_offset: 8
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bit_size: 7
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