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add free-running clock mode for quadspi

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JuliDi 2023-09-03 17:06:27 +02:00
parent 9a61a1f090
commit cc8759f205
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GPG Key ID: 0C98FD5D6597BC5B
1 changed files with 5 additions and 1 deletions
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data/registers/quadspi_v1.yaml
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@ -112,6 +112,10 @@ fieldset/CCR:
description: Send instruction only once mode description: Send instruction only once mode
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
- name: FRCM
description: Free-running clock mode (not available on all chips!)
bit_offset: 29
bit_size: 1
- name: DHHC - name: DHHC
description: DDR hold half cycle description: DDR hold half cycle
bit_offset: 30 bit_offset: 30
@ -132,7 +136,7 @@ fieldset/CR:
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: DMAEN - name: DMAEN
description: DMA enable description: DMA enable (not available on all chips!)
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TCEN - name: TCEN