Dario Nieuwenhuis
GitHub
commit
9d536f55a8
776
data/registers/adc_f3.yaml
Normal file
776
data/registers/adc_f3.yaml
Normal file
@ -0,0 +1,776 @@
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---
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block/ADC:
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description: Analog-to-Digital Converter
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items:
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- name: ISR
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description: interrupt and status register
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byte_offset: 0
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fieldset: ISR
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- name: IER
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description: interrupt enable register
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byte_offset: 4
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fieldset: IER
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- name: CR
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description: control register
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byte_offset: 8
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fieldset: CR
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- name: CFGR
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description: configuration register
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byte_offset: 12
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fieldset: CFGR
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- name: SMPR1
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description: sample time register 1
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byte_offset: 20
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fieldset: SMPR1
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- name: SMPR2
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description: sample time register 2
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byte_offset: 24
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fieldset: SMPR2
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- name: TR1
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description: watchdog threshold register 1
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byte_offset: 32
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fieldset: TR1
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- name: TR2
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description: watchdog threshold register
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byte_offset: 36
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fieldset: TR2
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- name: TR3
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description: watchdog threshold register 3
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byte_offset: 40
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fieldset: TR3
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- name: SQR1
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description: regular sequence register 1
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byte_offset: 48
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fieldset: SQR1
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- name: SQR2
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description: regular sequence register 2
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byte_offset: 52
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fieldset: SQR2
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- name: SQR3
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description: regular sequence register 3
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byte_offset: 56
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fieldset: SQR3
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- name: SQR4
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description: regular sequence register 4
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byte_offset: 60
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fieldset: SQR4
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- name: DR
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description: regular Data Register
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byte_offset: 64
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access: Read
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fieldset: DR
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- name: JSQR
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description: injected sequence register
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byte_offset: 76
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fieldset: JSQR
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- name: OFR
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description: offset register X
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byte_offset: 96
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fieldset: OFR
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array:
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len: 4
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stride: 4
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- name: JDR
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description: injected data register X
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byte_offset: 128
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access: Read
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fieldset: JDR
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array:
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len: 4
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stride: 4
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- name: AWDCR
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description: "Analog Watchdog X Configuration\r Register"
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byte_offset: 160
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fieldset: AWDCR
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array:
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len: 2
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stride: 4
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- name: DIFSEL
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description: "Differential Mode Selection Register\r 2"
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byte_offset: 176
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fieldset: DIFSEL
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- name: CALFACT
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description: Calibration Factors
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byte_offset: 180
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fieldset: CALFACT
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fieldset/AWDCR:
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description: "Analog Watchdog 2 Configuration\r Register"
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fields:
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- name: AWD2CH0
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description: AWD2CH
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bit_offset: 1
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bit_size: 1
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array:
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len: 17
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stride: 1
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fieldset/CALFACT:
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description: Calibration Factors
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fields:
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- name: CALFACT_S
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description: CALFACT_S
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bit_offset: 0
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bit_size: 7
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- name: CALFACT_D
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description: CALFACT_D
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bit_offset: 16
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bit_size: 7
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fieldset/CFGR:
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description: configuration register
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fields:
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- name: DMAEN
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description: Direct memory access enable
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bit_offset: 0
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bit_size: 1
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- name: DMACFG
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description: Direct memory access configuration
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bit_offset: 1
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bit_size: 1
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- name: RES
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description: Data resolution
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bit_offset: 3
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bit_size: 2
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enum: RES
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- name: ALIGN
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description: Data alignment
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bit_offset: 5
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bit_size: 1
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enum: ALIGN
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- name: EXTSEL
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description: External trigger selection for regular group
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bit_offset: 6
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bit_size: 4
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enum: EXTSEL
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- name: EXTEN
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description: External trigger enable and polarity selection for regular channels
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bit_offset: 10
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bit_size: 2
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enum: EXTEN
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- name: OVRMOD
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description: Overrun Mode
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bit_offset: 12
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bit_size: 1
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- name: CONT
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description: Single / continuous conversion mode for regular conversions
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bit_offset: 13
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bit_size: 1
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- name: AUTDLY
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description: Delayed conversion mode
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bit_offset: 14
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bit_size: 1
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- name: DISCEN
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description: Discontinuous mode for regular channels
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bit_offset: 16
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bit_size: 1
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- name: DISCNUM
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description: Discontinuous mode channel count
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bit_offset: 17
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bit_size: 3
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- name: JDISCEN
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description: Discontinuous mode on injected channels
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bit_offset: 20
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bit_size: 1
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- name: JQM
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description: JSQR queue mode
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bit_offset: 21
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bit_size: 1
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enum: JQM
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- name: AWD1SGL
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description: Enable the watchdog 1 on a single channel or on all channels
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bit_offset: 22
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bit_size: 1
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enum: AWD1SGL
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- name: AWD1EN
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description: Analog watchdog 1 enable on regular channels
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bit_offset: 23
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bit_size: 1
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- name: JAWD1EN
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description: Analog watchdog 1 enable on injected channels
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bit_offset: 24
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bit_size: 1
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- name: JAUTO
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description: Automatic injected group conversion
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bit_offset: 25
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bit_size: 1
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- name: AWD1CH
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description: Analog watchdog 1 channel selection
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bit_offset: 26
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bit_size: 5
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fieldset/CR:
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description: control register
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fields:
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- name: ADEN
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description: ADC enable control
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bit_offset: 0
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bit_size: 1
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- name: ADDIS
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description: ADC disable command
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bit_offset: 1
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bit_size: 1
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- name: ADSTART
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description: ADC start of regular conversion
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bit_offset: 2
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bit_size: 1
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- name: JADSTART
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description: ADC start of injected conversion
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bit_offset: 3
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bit_size: 1
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- name: ADSTP
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description: ADC stop of regular conversion command
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bit_offset: 4
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bit_size: 1
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- name: JADSTP
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description: ADC stop of injected conversion command
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bit_offset: 5
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bit_size: 1
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- name: ADVREGEN
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description: ADC voltage regulator enable
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bit_offset: 28
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bit_size: 2
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enum: ADVREGEN
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- name: ADCALDIF
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description: Differential mode for calibration
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bit_offset: 30
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bit_size: 1
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- name: ADCAL
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description: ADC calibration
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bit_offset: 31
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bit_size: 1
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fieldset/DIFSEL:
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description: "Differential Mode Selection Register\r 2"
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fields:
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- name: DIFSEL_10
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 1
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_11
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 2
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_12
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 3
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_13
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 4
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_14
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 5
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_15
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 6
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_16
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 7
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_17
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 8
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_18
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 9
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_19
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 10
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_110
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 11
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_111
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 12
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_112
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 13
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_113
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 14
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_114
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 15
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_115
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 16
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_116
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 17
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_117
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 18
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bit_size: 1
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enum: DIFSEL_10
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fieldset/DR:
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description: regular Data Register
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fields:
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- name: RDATA
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description: Regular data
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bit_offset: 0
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bit_size: 16
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fieldset/IER:
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description: interrupt enable register
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fields:
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- name: ADRDYIE
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description: ADC ready interrupt enable
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bit_offset: 0
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bit_size: 1
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- name: EOSMPIE
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description: End of sampling flag interrupt enable for regular conversions
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bit_offset: 1
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bit_size: 1
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- name: EOCIE
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description: End of regular conversion interrupt enable
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bit_offset: 2
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bit_size: 1
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- name: EOSIE
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description: End of regular sequence of conversions interrupt enable
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bit_offset: 3
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bit_size: 1
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- name: OVRIE
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description: Overrun interrupt enable
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bit_offset: 4
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bit_size: 1
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- name: JEOCIE
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description: End of injected conversion interrupt enable
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bit_offset: 5
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bit_size: 1
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- name: JEOSIE
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description: End of injected sequence of conversions interrupt enable
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bit_offset: 6
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bit_size: 1
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- name: AWDIE
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description: Analog watchdog X interrupt enable
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bit_offset: 7
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bit_size: 1
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array:
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len: 3
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stride: 1
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- name: JQOVFIE
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description: Injected context queue overflow interrupt enable
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bit_offset: 10
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bit_size: 1
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fieldset/ISR:
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description: interrupt and status register
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fields:
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- name: ADRDY
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description: ADC Ready
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bit_offset: 0
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bit_size: 1
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- name: EOSMP
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description: End of sampling flag
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bit_offset: 1
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bit_size: 1
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- name: EOC
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description: End of conversion flag
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bit_offset: 2
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bit_size: 1
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- name: EOS
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description: End of regular sequence flag
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bit_offset: 3
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bit_size: 1
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- name: OVR
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description: ADC overrun
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bit_offset: 4
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bit_size: 1
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- name: JEOC
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description: Injected channel end of conversion flag
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bit_offset: 5
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bit_size: 1
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- name: JEOS
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description: Injected channel end of sequence flag
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bit_offset: 6
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bit_size: 1
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- name: AWD
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description: Analog watchdog flag
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bit_offset: 7
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bit_size: 1
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array:
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len: 3
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stride: 1
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- name: JQOVF
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description: Injected context queue overflow
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bit_offset: 10
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bit_size: 1
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fieldset/JDR:
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description: injected data register 1
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fields:
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- name: JDATA
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description: Injected data
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bit_offset: 0
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bit_size: 16
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fieldset/JSQR:
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description: injected sequence register
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fields:
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- name: JL
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||||
description: Injected channel sequence length
|
||||
bit_offset: 0
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||||
bit_size: 2
|
||||
- name: JEXTSEL
|
||||
description: External Trigger Selection for injected group
|
||||
bit_offset: 2
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||||
bit_size: 4
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enum: JEXTSEL
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||||
- name: JEXTEN
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||||
description: External Trigger Enable and Polarity Selection for injected channels
|
||||
bit_offset: 6
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||||
bit_size: 2
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||||
enum: JEXTEN
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||||
- name: JSQ
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||||
description: X conversion in the injected sequence
|
||||
bit_offset: 8
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 4
|
||||
stride: 6
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||||
fieldset/OFR:
|
||||
description: offset register 1
|
||||
fields:
|
||||
- name: OFFSET
|
||||
description: Data offset y for the channel programmed into bits OFFSETy_CH
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: CH
|
||||
description: Data offset y for the channel programmed into bits OFFSETy_CH
|
||||
bit_offset: 26
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||||
bit_size: 5
|
||||
- name: EN
|
||||
description: Offset y Enable
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SMPR1:
|
||||
description: sample time register 1
|
||||
fields:
|
||||
- name: SMP
|
||||
description: Channel x sampling time selection
|
||||
bit_offset: 3
|
||||
bit_size: 3
|
||||
enum: SMP
|
||||
array:
|
||||
len: 9
|
||||
stride: 3
|
||||
fieldset/SMPR2:
|
||||
description: sample time register 2
|
||||
fields:
|
||||
- name: SMP
|
||||
description: Channel x sampling time selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: SMP
|
||||
array:
|
||||
len: 9
|
||||
stride: 3
|
||||
fieldset/SQR1:
|
||||
description: regular sequence register 1
|
||||
fields:
|
||||
- name: L
|
||||
description: Regular channel sequence length
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: SQ
|
||||
description: X conversion in regular sequence
|
||||
bit_offset: 6
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 4
|
||||
stride: 6
|
||||
fieldset/SQR2:
|
||||
description: regular sequence register 2
|
||||
fields:
|
||||
- name: SQ
|
||||
description: X conversion in regular sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 5
|
||||
stride: 6
|
||||
fieldset/SQR3:
|
||||
description: regular sequence register 3
|
||||
fields:
|
||||
- name: SQ
|
||||
description: X conversion in regular sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 5
|
||||
stride: 6
|
||||
fieldset/SQR4:
|
||||
description: regular sequence register 4
|
||||
fields:
|
||||
- name: SQ
|
||||
description: X conversion in regular sequence
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 2
|
||||
stride: 6
|
||||
fieldset/TR1:
|
||||
description: watchdog threshold register 1
|
||||
fields:
|
||||
- name: LT1
|
||||
description: LT1
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: HT1
|
||||
description: HT1
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
fieldset/TR2:
|
||||
description: watchdog threshold register
|
||||
fields:
|
||||
- name: LT2
|
||||
description: LT2
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: HT2
|
||||
description: HT2
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
fieldset/TR3:
|
||||
description: watchdog threshold register 3
|
||||
fields:
|
||||
- name: LT3
|
||||
description: LT3
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: HT3
|
||||
description: HT3
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
enum/ADVREGEN:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Intermediate
|
||||
description: Intermediate state required when moving the ADC voltage regulator between states
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: ADC voltage regulator enabled
|
||||
value: 1
|
||||
- name: Disabled
|
||||
description: ADC voltage regulator disabled
|
||||
value: 2
|
||||
enum/ALIGN:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Right
|
||||
description: Right alignment
|
||||
value: 0
|
||||
- name: Left
|
||||
description: Left alignment
|
||||
value: 1
|
||||
enum/AWD1SGL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: All
|
||||
description: Analog watchdog 1 enabled on all channels
|
||||
value: 0
|
||||
- name: Single
|
||||
description: Analog watchdog 1 enabled on single channel selected in AWD1CH
|
||||
value: 1
|
||||
enum/DIFSEL_10:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: SingleEnded
|
||||
description: Input channel is configured in single-ended mode
|
||||
value: 0
|
||||
- name: Differential
|
||||
description: Input channel is configured in differential mode
|
||||
value: 1
|
||||
enum/EXTEN:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Trigger detection disabled
|
||||
value: 0
|
||||
- name: RisingEdge
|
||||
description: Trigger detection on the rising edge
|
||||
value: 1
|
||||
- name: FallingEdge
|
||||
description: Trigger detection on the falling edge
|
||||
value: 2
|
||||
- name: BothEdges
|
||||
description: Trigger detection on both the rising and falling edges
|
||||
value: 3
|
||||
enum/EXTSEL:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: TIM1_CC1
|
||||
description: Timer 1 CC1 event
|
||||
value: 0
|
||||
- name: TIM1_CC2
|
||||
description: Timer 1 CC2 event
|
||||
value: 1
|
||||
- name: TIM1_CC3
|
||||
description: Timer 1 CC3 event
|
||||
value: 2
|
||||
- name: TIM2_CC2
|
||||
description: Timer 2 CC2 event
|
||||
value: 3
|
||||
- name: TIM3_TRGO
|
||||
description: Timer 3 TRGO event
|
||||
value: 4
|
||||
- name: EXTI11
|
||||
description: EXTI line 11
|
||||
value: 6
|
||||
- name: HRTIM_ADCTRG1
|
||||
description: HRTIM_ADCTRG1 event
|
||||
value: 7
|
||||
- name: HRTIM_ADCTRG3
|
||||
description: HRTIM_ADCTRG3 event
|
||||
value: 8
|
||||
- name: TIM1_TRGO
|
||||
description: Timer 1 TRGO event
|
||||
value: 9
|
||||
- name: TIM1_TRGO2
|
||||
description: Timer 1 TRGO2 event
|
||||
value: 10
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 11
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 13
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 14
|
||||
- name: TIM3_CC4
|
||||
description: Timer 3 CC4 event
|
||||
value: 15
|
||||
enum/JEXTEN:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Trigger detection disabled
|
||||
value: 0
|
||||
- name: RisingEdge
|
||||
description: Trigger detection on the rising edge
|
||||
value: 1
|
||||
- name: FallingEdge
|
||||
description: Trigger detection on the falling edge
|
||||
value: 2
|
||||
- name: BothEdges
|
||||
description: Trigger detection on both the rising and falling edges
|
||||
value: 3
|
||||
enum/JEXTSEL:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: TIM1_TRGO
|
||||
description: Timer 1 TRGO event
|
||||
value: 0
|
||||
- name: TIM1_CC4
|
||||
description: Timer 1 CC4 event
|
||||
value: 1
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 2
|
||||
- name: TIM2_CC1
|
||||
description: Timer 2 CC1 event
|
||||
value: 3
|
||||
- name: TIM3_CC4
|
||||
description: Timer 3 CC4 event
|
||||
value: 4
|
||||
- name: EXTI15
|
||||
description: EXTI line 15
|
||||
value: 6
|
||||
- name: TIM1_TRGO2
|
||||
description: Timer 1 TRGO2 event
|
||||
value: 8
|
||||
- name: HRTIM_ADCTRG2
|
||||
description: HRTIM_ADCTRG2 event
|
||||
value: 9
|
||||
- name: HRTIM_ADCTRG4
|
||||
description: HRTIM_ADCTRG4 event
|
||||
value: 10
|
||||
- name: TIM3_CC3
|
||||
description: Timer 3 CC3 event
|
||||
value: 11
|
||||
- name: TIM3_TRGO
|
||||
description: Timer 3 TRGO event
|
||||
value: 12
|
||||
- name: TIM3_CC1
|
||||
description: Timer 3 CC1 event
|
||||
value: 13
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 14
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 15
|
||||
enum/JQM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Mode0
|
||||
description: "JSQR Mode 0: Queue maintains the last written configuration into JSQR"
|
||||
value: 0
|
||||
- name: Mode1
|
||||
description: "JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence"
|
||||
value: 1
|
||||
enum/RES:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Bits12
|
||||
description: 12-bit
|
||||
value: 0
|
||||
- name: Bits10
|
||||
description: 10-bit
|
||||
value: 1
|
||||
- name: Bits8
|
||||
description: 8-bit
|
||||
value: 2
|
||||
- name: Bits6
|
||||
description: 6-bit
|
||||
value: 3
|
||||
enum/SMP:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Cycles1_5
|
||||
description: 1.5 ADC clock cycles
|
||||
value: 0
|
||||
- name: Cycles2_5
|
||||
description: 2.5 ADC clock cycles
|
||||
value: 1
|
||||
- name: Cycles4_5
|
||||
description: 4.5 ADC clock cycles
|
||||
value: 2
|
||||
- name: Cycles7_5
|
||||
description: 7.5 ADC clock cycles
|
||||
value: 3
|
||||
- name: Cycles19_5
|
||||
description: 19.5 ADC clock cycles
|
||||
value: 4
|
||||
- name: Cycles61_5
|
||||
description: 61.5 ADC clock cycles
|
||||
value: 5
|
||||
- name: Cycles181_5
|
||||
description: 181.5 ADC clock cycles
|
||||
value: 6
|
||||
- name: Cycles601_5
|
||||
description: 601.5 ADC clock cycles
|
||||
value: 7
|
||||
@ -169,6 +169,7 @@ impl PeriMatcher {
|
||||
(".*:DAC:dacif_v3_0", ("dac", "v3", "DAC")),
|
||||
(".*:DAC:F3_dacif_v1_1", ("dac", "v1", "DAC")),
|
||||
(".*:ADC:aditf_v2_5F1", ("adc", "f1", "ADC")),
|
||||
(".*:ADC:aditf5_v1_1", ("adc", "f3", "ADC")),
|
||||
(".*:ADC:aditf4_v1_1", ("adc", "v1", "ADC")),
|
||||
(".*:ADC:aditf2_v1_1", ("adc", "v2", "ADC")),
|
||||
(".*:ADC:aditf5_v2_0", ("adc", "v3", "ADC")),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user