From feb4f685ed555760e43fede4e3213959bca7dc09 Mon Sep 17 00:00:00 2001 From: xoviat Date: Tue, 11 Jul 2023 21:10:08 -0500 Subject: [PATCH 1/6] adc: add f3 --- data/registers/adc_f3.yaml | 1695 +++++++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 1 + 2 files changed, 1696 insertions(+) create mode 100644 data/registers/adc_f3.yaml diff --git a/data/registers/adc_f3.yaml b/data/registers/adc_f3.yaml new file mode 100644 index 0000000..12d23f9 --- /dev/null +++ b/data/registers/adc_f3.yaml @@ -0,0 +1,1695 @@ +--- +block/ADC1: + description: Analog-to-Digital Converter + items: + - name: ISR + description: interrupt and status register + byte_offset: 0 + fieldset: ISR + - name: IER + description: interrupt enable register + byte_offset: 4 + fieldset: IER + - name: CR + description: control register + byte_offset: 8 + fieldset: CR + - name: CFGR + description: configuration register + byte_offset: 12 + fieldset: CFGR + - name: SMPR1 + description: sample time register 1 + byte_offset: 20 + fieldset: SMPR1 + - name: SMPR2 + description: sample time register 2 + byte_offset: 24 + fieldset: SMPR2 + - name: TR1 + description: watchdog threshold register 1 + byte_offset: 32 + fieldset: TR1 + - name: TR2 + description: watchdog threshold register + byte_offset: 36 + fieldset: TR2 + - name: TR3 + description: watchdog threshold register 3 + byte_offset: 40 + fieldset: TR3 + - name: SQR1 + description: regular sequence register 1 + byte_offset: 48 + fieldset: SQR1 + - name: SQR2 + description: regular sequence register 2 + byte_offset: 52 + fieldset: SQR2 + - name: SQR3 + description: regular sequence register 3 + byte_offset: 56 + fieldset: SQR3 + - name: SQR4 + description: regular sequence register 4 + byte_offset: 60 + fieldset: SQR4 + - name: DR + description: regular Data Register + byte_offset: 64 + access: Read + fieldset: DR + - name: JSQR + description: injected sequence register + byte_offset: 76 + fieldset: JSQR + - name: OFR1 + description: offset register 1 + byte_offset: 96 + fieldset: OFR1 + - name: OFR2 + description: offset register 2 + byte_offset: 100 + fieldset: OFR2 + - name: OFR3 + description: offset register 3 + byte_offset: 104 + fieldset: OFR3 + - name: OFR4 + description: offset register 4 + byte_offset: 108 + fieldset: OFR4 + - name: JDR1 + description: injected data register 1 + byte_offset: 128 + access: Read + fieldset: JDR1 + - name: JDR2 + description: injected data register 2 + byte_offset: 132 + access: Read + fieldset: JDR2 + - name: JDR3 + description: injected data register 3 + byte_offset: 136 + access: Read + fieldset: JDR3 + - name: JDR4 + description: injected data register 4 + byte_offset: 140 + access: Read + fieldset: JDR4 + - name: AWD2CR + description: "Analog Watchdog 2 Configuration\r Register" + byte_offset: 160 + fieldset: AWD2CR + - name: AWD3CR + description: "Analog Watchdog 3 Configuration\r Register" + byte_offset: 164 + fieldset: AWD3CR + - name: DIFSEL + description: "Differential Mode Selection Register\r 2" + byte_offset: 176 + fieldset: DIFSEL + - name: CALFACT + description: Calibration Factors + byte_offset: 180 + fieldset: CALFACT +fieldset/AWD2CR: + description: "Analog Watchdog 2 Configuration\r Register" + fields: + - name: AWD2CH0 + description: AWD2CH + bit_offset: 1 + bit_size: 1 + enum: AWD2CH0 + - name: AWD2CH1 + description: AWD2CH + bit_offset: 2 + bit_size: 1 + enum: AWD2CH0 + - name: AWD2CH2 + description: AWD2CH + bit_offset: 3 + bit_size: 1 + enum: AWD2CH0 + - name: AWD2CH3 + description: AWD2CH + bit_offset: 4 + bit_size: 1 + enum: AWD2CH0 + - name: AWD2CH4 + description: AWD2CH + bit_offset: 5 + bit_size: 1 + enum: AWD2CH0 + - name: AWD2CH5 + description: AWD2CH + bit_offset: 6 + bit_size: 1 + enum: AWD2CH0 + - name: AWD2CH6 + description: AWD2CH + bit_offset: 7 + bit_size: 1 + enum: AWD2CH0 + - name: AWD2CH7 + description: AWD2CH + bit_offset: 8 + bit_size: 1 + enum: AWD2CH0 + - name: AWD2CH8 + description: AWD2CH + bit_offset: 9 + bit_size: 1 + enum: AWD2CH0 + - name: AWD2CH9 + description: AWD2CH + bit_offset: 10 + bit_size: 1 + enum: AWD2CH0 + - name: AWD2CH10 + description: AWD2CH + bit_offset: 11 + bit_size: 1 + enum: AWD2CH0 + - name: AWD2CH11 + description: AWD2CH + bit_offset: 12 + bit_size: 1 + enum: AWD2CH0 + - name: AWD2CH12 + description: AWD2CH + bit_offset: 13 + bit_size: 1 + enum: AWD2CH0 + - name: AWD2CH13 + description: AWD2CH + bit_offset: 14 + bit_size: 1 + enum: AWD2CH0 + - name: AWD2CH14 + description: AWD2CH + bit_offset: 15 + bit_size: 1 + enum: AWD2CH0 + - name: AWD2CH15 + description: AWD2CH + bit_offset: 16 + bit_size: 1 + enum: AWD2CH0 + - name: AWD2CH16 + description: AWD2CH + bit_offset: 17 + bit_size: 1 + enum: AWD2CH0 + - name: AWD2CH17 + description: AWD2CH + bit_offset: 18 + bit_size: 1 + enum: AWD2CH0 +fieldset/AWD3CR: + description: "Analog Watchdog 3 Configuration\r Register" + fields: + - name: AWD3CH0 + description: AWD3CH + bit_offset: 1 + bit_size: 1 + enum: AWD3CH0 + - name: AWD3CH1 + description: AWD3CH + bit_offset: 2 + bit_size: 1 + enum: AWD3CH0 + - name: AWD3CH2 + description: AWD3CH + bit_offset: 3 + bit_size: 1 + enum: AWD3CH0 + - name: AWD3CH3 + description: AWD3CH + bit_offset: 4 + bit_size: 1 + enum: AWD3CH0 + - name: AWD3CH4 + description: AWD3CH + bit_offset: 5 + bit_size: 1 + enum: AWD3CH0 + - name: AWD3CH5 + description: AWD3CH + bit_offset: 6 + bit_size: 1 + enum: AWD3CH0 + - name: AWD3CH6 + description: AWD3CH + bit_offset: 7 + bit_size: 1 + enum: AWD3CH0 + - name: AWD3CH7 + description: AWD3CH + bit_offset: 8 + bit_size: 1 + enum: AWD3CH0 + - name: AWD3CH8 + description: AWD3CH + bit_offset: 9 + bit_size: 1 + enum: AWD3CH0 + - name: AWD3CH9 + description: AWD3CH + bit_offset: 10 + bit_size: 1 + enum: AWD3CH0 + - name: AWD3CH10 + description: AWD3CH + bit_offset: 11 + bit_size: 1 + enum: AWD3CH0 + - name: AWD3CH11 + description: AWD3CH + bit_offset: 12 + bit_size: 1 + enum: AWD3CH0 + - name: AWD3CH12 + description: AWD3CH + bit_offset: 13 + bit_size: 1 + enum: AWD3CH0 + - name: AWD3CH13 + description: AWD3CH + bit_offset: 14 + bit_size: 1 + enum: AWD3CH0 + - name: AWD3CH14 + description: AWD3CH + bit_offset: 15 + bit_size: 1 + enum: AWD3CH0 + - name: AWD3CH15 + description: AWD3CH + bit_offset: 16 + bit_size: 1 + enum: AWD3CH0 + - name: AWD3CH16 + description: AWD3CH + bit_offset: 17 + bit_size: 1 + enum: AWD3CH0 + - name: AWD3CH17 + description: AWD3CH + bit_offset: 18 + bit_size: 1 + enum: AWD3CH0 +fieldset/CALFACT: + description: Calibration Factors + fields: + - name: CALFACT_S + description: CALFACT_S + bit_offset: 0 + bit_size: 7 + - name: CALFACT_D + description: CALFACT_D + bit_offset: 16 + bit_size: 7 +fieldset/CFGR: + description: configuration register + fields: + - name: DMAEN + description: DMAEN + bit_offset: 0 + bit_size: 1 + enum: DMAEN + - name: DMACFG + description: DMACFG + bit_offset: 1 + bit_size: 1 + enum: DMACFG + - name: RES + description: RES + bit_offset: 3 + bit_size: 2 + enum: RES + - name: ALIGN + description: ALIGN + bit_offset: 5 + bit_size: 1 + enum: ALIGN + - name: EXTSEL + description: EXTSEL + bit_offset: 6 + bit_size: 4 + enum: EXTSEL + - name: EXTEN + description: EXTEN + bit_offset: 10 + bit_size: 2 + enum: EXTEN + - name: OVRMOD + description: OVRMOD + bit_offset: 12 + bit_size: 1 + enum: OVRMOD + - name: CONT + description: CONT + bit_offset: 13 + bit_size: 1 + enum: CONT + - name: AUTDLY + description: AUTDLY + bit_offset: 14 + bit_size: 1 + enum: AUTDLY + - name: DISCEN + description: DISCEN + bit_offset: 16 + bit_size: 1 + enum: DISCEN + - name: DISCNUM + description: DISCNUM + bit_offset: 17 + bit_size: 3 + - name: JDISCEN + description: JDISCEN + bit_offset: 20 + bit_size: 1 + enum: JDISCEN + - name: JQM + description: JQM + bit_offset: 21 + bit_size: 1 + enum: JQM + - name: AWD1SGL + description: AWD1SGL + bit_offset: 22 + bit_size: 1 + enum: AWD1SGL + - name: AWD1EN + description: AWD1EN + bit_offset: 23 + bit_size: 1 + enum: AWD1EN + - name: JAWD1EN + description: JAWD1EN + bit_offset: 24 + bit_size: 1 + enum: JAWD1EN + - name: JAUTO + description: JAUTO + bit_offset: 25 + bit_size: 1 + enum: JAUTO + - name: AWD1CH + description: AWDCH1CH + bit_offset: 26 + bit_size: 5 +fieldset/CR: + description: control register + fields: + - name: ADEN + description: ADEN + bit_offset: 0 + bit_size: 1 + enum_read: ADENR + enum_write: ADENW + - name: ADDIS + description: ADDIS + bit_offset: 1 + bit_size: 1 + enum_read: ADDISR + enum_write: ADDISW + - name: ADSTART + description: ADSTART + bit_offset: 2 + bit_size: 1 + enum_read: ADSTARTR + enum_write: ADSTARTW + - name: JADSTART + description: JADSTART + bit_offset: 3 + bit_size: 1 + enum_read: ADSTARTR + enum_write: ADSTARTW + - name: ADSTP + description: ADSTP + bit_offset: 4 + bit_size: 1 + enum_read: ADSTPR + enum_write: ADSTPW + - name: JADSTP + description: JADSTP + bit_offset: 5 + bit_size: 1 + enum_read: ADSTPR + enum_write: ADSTPW + - name: ADVREGEN + description: ADVREGEN + bit_offset: 28 + bit_size: 2 + enum: ADVREGEN + - name: ADCALDIF + description: ADCALDIF + bit_offset: 30 + bit_size: 1 + enum: ADCALDIF + - name: ADCAL + description: ADCAL + bit_offset: 31 + bit_size: 1 + enum: ADCAL +fieldset/DIFSEL: + description: "Differential Mode Selection Register\r 2" + fields: + - name: DIFSEL_10 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 1 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_11 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 2 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_12 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 3 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_13 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 4 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_14 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 5 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_15 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 6 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_16 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 7 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_17 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 8 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_18 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 9 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_19 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 10 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_110 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 11 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_111 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 12 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_112 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 13 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_113 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 14 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_114 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 15 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_115 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 16 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_116 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 17 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_117 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 18 + bit_size: 1 + enum: DIFSEL_10 +fieldset/DR: + description: regular Data Register + fields: + - name: RDATA + description: Regular data + bit_offset: 0 + bit_size: 16 +fieldset/IER: + description: interrupt enable register + fields: + - name: ADRDYIE + description: ADRDYIE + bit_offset: 0 + bit_size: 1 + enum: ADRDYIE + - name: EOSMPIE + description: EOSMPIE + bit_offset: 1 + bit_size: 1 + enum: EOSMPIE + - name: EOCIE + description: EOCIE + bit_offset: 2 + bit_size: 1 + enum: EOCIE + - name: EOSIE + description: EOSIE + bit_offset: 3 + bit_size: 1 + enum: EOSIE + - name: OVRIE + description: OVRIE + bit_offset: 4 + bit_size: 1 + enum: OVRIE + - name: JEOCIE + description: JEOCIE + bit_offset: 5 + bit_size: 1 + enum: JEOCIE + - name: JEOSIE + description: JEOSIE + bit_offset: 6 + bit_size: 1 + enum: JEOSIE + - name: AWD1IE + description: AWD1IE + bit_offset: 7 + bit_size: 1 + enum: AWD1IE + - name: AWD2IE + description: AWD2IE + bit_offset: 8 + bit_size: 1 + enum: AWD1IE + - name: AWD3IE + description: AWD3IE + bit_offset: 9 + bit_size: 1 + enum: AWD1IE + - name: JQOVFIE + description: JQOVFIE + bit_offset: 10 + bit_size: 1 + enum: JQOVFIE +fieldset/ISR: + description: interrupt and status register + fields: + - name: ADRDY + description: ADRDY + bit_offset: 0 + bit_size: 1 + enum_read: ADRDYR + enum_write: ADRDYW + - name: EOSMP + description: EOSMP + bit_offset: 1 + bit_size: 1 + enum_read: EOSMPR + enum_write: EOSMPW + - name: EOC + description: EOC + bit_offset: 2 + bit_size: 1 + enum_read: EOCR + enum_write: EOCW + - name: EOS + description: EOS + bit_offset: 3 + bit_size: 1 + enum_read: EOSR + enum_write: EOSW + - name: OVR + description: OVR + bit_offset: 4 + bit_size: 1 + enum_read: OVRR + enum_write: OVRW + - name: JEOC + description: JEOC + bit_offset: 5 + bit_size: 1 + enum_read: JEOCR + enum_write: JEOCW + - name: JEOS + description: JEOS + bit_offset: 6 + bit_size: 1 + enum_read: JEOSR + enum_write: JEOSW + - name: AWD1 + description: AWD1 + bit_offset: 7 + bit_size: 1 + enum_read: AWD1R + enum_write: AWD1W + - name: AWD2 + description: AWD2 + bit_offset: 8 + bit_size: 1 + enum_read: AWD1R + enum_write: AWD1W + - name: AWD3 + description: AWD3 + bit_offset: 9 + bit_size: 1 + enum_read: AWD1R + enum_write: AWD1W + - name: JQOVF + description: JQOVF + bit_offset: 10 + bit_size: 1 + enum_read: JQOVFR + enum_write: JQOVFW +fieldset/JDR1: + description: injected data register 1 + fields: + - name: JDATA1 + description: JDATA1 + bit_offset: 0 + bit_size: 16 +fieldset/JDR2: + description: injected data register 2 + fields: + - name: JDATA2 + description: JDATA2 + bit_offset: 0 + bit_size: 16 +fieldset/JDR3: + description: injected data register 3 + fields: + - name: JDATA3 + description: JDATA3 + bit_offset: 0 + bit_size: 16 +fieldset/JDR4: + description: injected data register 4 + fields: + - name: JDATA4 + description: JDATA4 + bit_offset: 0 + bit_size: 16 +fieldset/JSQR: + description: injected sequence register + fields: + - name: JL + description: JL + bit_offset: 0 + bit_size: 2 + - name: JEXTSEL + description: JEXTSEL + bit_offset: 2 + bit_size: 4 + enum: JEXTSEL + - name: JEXTEN + description: JEXTEN + bit_offset: 6 + bit_size: 2 + enum: JEXTEN + - name: JSQ1 + description: JSQ1 + bit_offset: 8 + bit_size: 5 + - name: JSQ2 + description: JSQ2 + bit_offset: 14 + bit_size: 5 + - name: JSQ3 + description: JSQ3 + bit_offset: 20 + bit_size: 5 + - name: JSQ4 + description: JSQ4 + bit_offset: 26 + bit_size: 5 +fieldset/OFR1: + description: offset register 1 + fields: + - name: OFFSET1 + description: OFFSET1 + bit_offset: 0 + bit_size: 12 + - name: OFFSET1_CH + description: OFFSET1_CH + bit_offset: 26 + bit_size: 5 + - name: OFFSET1_EN + description: OFFSET1_EN + bit_offset: 31 + bit_size: 1 + enum: OFFSET1_EN +fieldset/OFR2: + description: offset register 2 + fields: + - name: OFFSET2 + description: OFFSET2 + bit_offset: 0 + bit_size: 12 + - name: OFFSET2_CH + description: OFFSET2_CH + bit_offset: 26 + bit_size: 5 + - name: OFFSET2_EN + description: OFFSET2_EN + bit_offset: 31 + bit_size: 1 + enum: OFFSET2_EN +fieldset/OFR3: + description: offset register 3 + fields: + - name: OFFSET3 + description: OFFSET3 + bit_offset: 0 + bit_size: 12 + - name: OFFSET3_CH + description: OFFSET3_CH + bit_offset: 26 + bit_size: 5 + - name: OFFSET3_EN + description: OFFSET3_EN + bit_offset: 31 + bit_size: 1 + enum: OFFSET3_EN +fieldset/OFR4: + description: offset register 4 + fields: + - name: OFFSET4 + description: OFFSET4 + bit_offset: 0 + bit_size: 12 + - name: OFFSET4_CH + description: OFFSET4_CH + bit_offset: 26 + bit_size: 5 + - name: OFFSET4_EN + description: OFFSET4_EN + bit_offset: 31 + bit_size: 1 + enum: OFFSET4_EN +fieldset/SMPR1: + description: sample time register 1 + fields: + - name: SMP1 + description: SMP1 + bit_offset: 3 + bit_size: 3 + enum: SMP1 + - name: SMP2 + description: SMP2 + bit_offset: 6 + bit_size: 3 + enum: SMP1 + - name: SMP3 + description: SMP3 + bit_offset: 9 + bit_size: 3 + enum: SMP1 + - name: SMP4 + description: SMP4 + bit_offset: 12 + bit_size: 3 + enum: SMP1 + - name: SMP5 + description: SMP5 + bit_offset: 15 + bit_size: 3 + enum: SMP1 + - name: SMP6 + description: SMP6 + bit_offset: 18 + bit_size: 3 + enum: SMP1 + - name: SMP7 + description: SMP7 + bit_offset: 21 + bit_size: 3 + enum: SMP1 + - name: SMP8 + description: SMP8 + bit_offset: 24 + bit_size: 3 + enum: SMP1 + - name: SMP9 + description: SMP9 + bit_offset: 27 + bit_size: 3 + enum: SMP1 +fieldset/SMPR2: + description: sample time register 2 + fields: + - name: SMP10 + description: SMP10 + bit_offset: 0 + bit_size: 3 + enum: SMP10 + - name: SMP11 + description: SMP11 + bit_offset: 3 + bit_size: 3 + enum: SMP10 + - name: SMP12 + description: SMP12 + bit_offset: 6 + bit_size: 3 + enum: SMP10 + - name: SMP13 + description: SMP13 + bit_offset: 9 + bit_size: 3 + enum: SMP10 + - name: SMP14 + description: SMP14 + bit_offset: 12 + bit_size: 3 + enum: SMP10 + - name: SMP15 + description: SMP15 + bit_offset: 15 + bit_size: 3 + enum: SMP10 + - name: SMP16 + description: SMP16 + bit_offset: 18 + bit_size: 3 + enum: SMP10 + - name: SMP17 + description: SMP17 + bit_offset: 21 + bit_size: 3 + enum: SMP10 + - name: SMP18 + description: SMP18 + bit_offset: 24 + bit_size: 3 + enum: SMP10 +fieldset/SQR1: + description: regular sequence register 1 + fields: + - name: L + description: L3 + bit_offset: 0 + bit_size: 4 + - name: SQ1 + description: SQ1 + bit_offset: 6 + bit_size: 5 + - name: SQ2 + description: SQ2 + bit_offset: 12 + bit_size: 5 + - name: SQ3 + description: SQ3 + bit_offset: 18 + bit_size: 5 + - name: SQ4 + description: SQ4 + bit_offset: 24 + bit_size: 5 +fieldset/SQR2: + description: regular sequence register 2 + fields: + - name: SQ5 + description: SQ5 + bit_offset: 0 + bit_size: 5 + - name: SQ6 + description: SQ6 + bit_offset: 6 + bit_size: 5 + - name: SQ7 + description: SQ7 + bit_offset: 12 + bit_size: 5 + - name: SQ8 + description: SQ8 + bit_offset: 18 + bit_size: 5 + - name: SQ9 + description: SQ9 + bit_offset: 24 + bit_size: 5 +fieldset/SQR3: + description: regular sequence register 3 + fields: + - name: SQ10 + description: SQ10 + bit_offset: 0 + bit_size: 5 + - name: SQ11 + description: SQ11 + bit_offset: 6 + bit_size: 5 + - name: SQ12 + description: SQ12 + bit_offset: 12 + bit_size: 5 + - name: SQ13 + description: SQ13 + bit_offset: 18 + bit_size: 5 + - name: SQ14 + description: SQ14 + bit_offset: 24 + bit_size: 5 +fieldset/SQR4: + description: regular sequence register 4 + fields: + - name: SQ15 + description: SQ15 + bit_offset: 0 + bit_size: 5 + - name: SQ16 + description: SQ16 + bit_offset: 6 + bit_size: 5 +fieldset/TR1: + description: watchdog threshold register 1 + fields: + - name: LT1 + description: LT1 + bit_offset: 0 + bit_size: 12 + - name: HT1 + description: HT1 + bit_offset: 16 + bit_size: 12 +fieldset/TR2: + description: watchdog threshold register + fields: + - name: LT2 + description: LT2 + bit_offset: 0 + bit_size: 8 + - name: HT2 + description: HT2 + bit_offset: 16 + bit_size: 8 +fieldset/TR3: + description: watchdog threshold register 3 + fields: + - name: LT3 + description: LT3 + bit_offset: 0 + bit_size: 8 + - name: HT3 + description: HT3 + bit_offset: 16 + bit_size: 8 +enum/ADCAL: + bit_size: 1 + variants: + - name: Complete + description: Calibration complete + value: 0 + - name: Calibration + description: Start the calibration of the ADC + value: 1 +enum/ADCALDIF: + bit_size: 1 + variants: + - name: SingleEnded + description: Calibration for single-ended mode + value: 0 + - name: Differential + description: Calibration for differential mode + value: 1 +enum/ADDISR: + bit_size: 1 + variants: + - name: NotDisabling + description: No disable command active + value: 0 + - name: Disabling + description: ADC disabling + value: 1 +enum/ADDISW: + bit_size: 1 + variants: + - name: Disable + description: Disable the ADC + value: 1 +enum/ADENR: + bit_size: 1 + variants: + - name: Disabled + description: ADC disabled + value: 0 + - name: Enabled + description: ADC enabled + value: 1 +enum/ADENW: + bit_size: 1 + variants: + - name: Enabled + description: Enable the ADC + value: 1 +enum/ADRDYIE: + bit_size: 1 + variants: + - name: Disabled + description: ADC ready interrupt disabled + value: 0 + - name: Enabled + description: ADC ready interrupt enabled + value: 1 +enum/ADRDYR: + bit_size: 1 + variants: + - name: NotReady + description: ADC is not ready to start conversion + value: 0 + - name: Ready + description: ADC is ready to start conversion + value: 1 +enum/ADRDYW: + bit_size: 1 + variants: + - name: Clear + description: Clear ADC is ready to start conversion flag + value: 1 +enum/ADSTARTR: + bit_size: 1 + variants: + - name: NotActive + description: No conversion ongoing + value: 0 + - name: Active + description: ADC operating and may be converting + value: 1 +enum/ADSTARTW: + bit_size: 1 + variants: + - name: StartConversion + description: Start the ADC conversion (may be delayed for hardware triggers) + value: 1 +enum/ADSTPR: + bit_size: 1 + variants: + - name: NotStopping + description: No stop command active + value: 0 + - name: Stopping + description: ADC stopping conversion + value: 1 +enum/ADSTPW: + bit_size: 1 + variants: + - name: StopConversion + description: Stop the active conversion + value: 1 +enum/ADVREGEN: + bit_size: 2 + variants: + - name: Intermediate + description: Intermediate state required when moving the ADC voltage regulator between states + value: 0 + - name: Enabled + description: ADC voltage regulator enabled + value: 1 + - name: Disabled + description: ADC voltage regulator disabled + value: 2 +enum/ALIGN: + bit_size: 1 + variants: + - name: Right + description: Right alignment + value: 0 + - name: Left + description: Left alignment + value: 1 +enum/AUTDLY: + bit_size: 1 + variants: + - name: "Off" + description: Auto delayed conversion mode off + value: 0 + - name: "On" + description: Auto delayed conversion mode on + value: 1 +enum/AWD1EN: + bit_size: 1 + variants: + - name: Disabled + description: Analog watchdog 1 disabled on regular channels + value: 0 + - name: Enabled + description: Analog watchdog 1 enabled on regular channels + value: 1 +enum/AWD1IE: + bit_size: 1 + variants: + - name: Disabled + description: Analog watchdog interrupt disabled + value: 0 + - name: Enabled + description: Analog watchdog interrupt enabled + value: 1 +enum/AWD1R: + bit_size: 1 + variants: + - name: NoEvent + description: No analog watchdog event occurred + value: 0 + - name: Event + description: Analog watchdog event occurred + value: 1 +enum/AWD1SGL: + bit_size: 1 + variants: + - name: All + description: Analog watchdog 1 enabled on all channels + value: 0 + - name: Single + description: Analog watchdog 1 enabled on single channel selected in AWD1CH + value: 1 +enum/AWD1W: + bit_size: 1 + variants: + - name: Clear + description: Clear analog watchdog event occurred flag + value: 1 +enum/AWD2CH0: + bit_size: 1 + variants: + - name: NotMonitored + description: Input channel not monitored by AWDx + value: 0 + - name: Monitored + description: Input channel monitored by AWDx + value: 1 +enum/AWD3CH0: + bit_size: 1 + variants: + - name: NotMonitored + description: Input channel not monitored by AWDx + value: 0 + - name: Monitored + description: Input channel monitored by AWDx + value: 1 +enum/CONT: + bit_size: 1 + variants: + - name: Single + description: Single conversion mode + value: 0 + - name: Continuous + description: Continuous conversion mode + value: 1 +enum/DIFSEL_10: + bit_size: 1 + variants: + - name: SingleEnded + description: Input channel is configured in single-ended mode + value: 0 + - name: Differential + description: Input channel is configured in differential mode + value: 1 +enum/DISCEN: + bit_size: 1 + variants: + - name: Disabled + description: Discontinuous mode on regular channels disabled + value: 0 + - name: Enabled + description: Discontinuous mode on regular channels enabled + value: 1 +enum/DMACFG: + bit_size: 1 + variants: + - name: OneShot + description: DMA One Shot Mode selected + value: 0 + - name: Circular + description: DMA circular mode selected + value: 1 +enum/DMAEN: + bit_size: 1 + variants: + - name: Disabled + description: DMA disabled + value: 0 + - name: Enabled + description: DMA enabled + value: 1 +enum/EOCIE: + bit_size: 1 + variants: + - name: Disabled + description: End of regular conversion interrupt disabled + value: 0 + - name: Enabled + description: End of regular conversion interrupt enabled + value: 1 +enum/EOCR: + bit_size: 1 + variants: + - name: NotComplete + description: Regular conversion is not complete + value: 0 + - name: Complete + description: Regular conversion complete + value: 1 +enum/EOCW: + bit_size: 1 + variants: + - name: Clear + description: Clear regular conversion complete flag + value: 1 +enum/EOSIE: + bit_size: 1 + variants: + - name: Disabled + description: End of regular sequence interrupt disabled + value: 0 + - name: Enabled + description: End of regular sequence interrupt enabled + value: 1 +enum/EOSMPIE: + bit_size: 1 + variants: + - name: Disabled + description: End of regular conversion sampling phase interrupt disabled + value: 0 + - name: Enabled + description: End of regular conversion sampling phase interrupt enabled + value: 1 +enum/EOSMPR: + bit_size: 1 + variants: + - name: NotEnded + description: End of sampling phase no yet reached + value: 0 + - name: Ended + description: End of sampling phase reached + value: 1 +enum/EOSMPW: + bit_size: 1 + variants: + - name: Clear + description: Clear end of sampling phase reached flag + value: 1 +enum/EOSR: + bit_size: 1 + variants: + - name: NotComplete + description: Regular sequence is not complete + value: 0 + - name: Complete + description: Regular sequence complete + value: 1 +enum/EOSW: + bit_size: 1 + variants: + - name: Clear + description: Clear regular sequence complete flag + value: 1 +enum/EXTEN: + bit_size: 2 + variants: + - name: Disabled + description: Trigger detection disabled + value: 0 + - name: RisingEdge + description: Trigger detection on the rising edge + value: 1 + - name: FallingEdge + description: Trigger detection on the falling edge + value: 2 + - name: BothEdges + description: Trigger detection on both the rising and falling edges + value: 3 +enum/EXTSEL: + bit_size: 4 + variants: + - name: TIM1_CC1 + description: Timer 1 CC1 event + value: 0 + - name: TIM1_CC2 + description: Timer 1 CC2 event + value: 1 + - name: TIM1_CC3 + description: Timer 1 CC3 event + value: 2 + - name: TIM2_CC2 + description: Timer 2 CC2 event + value: 3 + - name: TIM3_TRGO + description: Timer 3 TRGO event + value: 4 + - name: EXTI11 + description: EXTI line 11 + value: 6 + - name: HRTIM_ADCTRG1 + description: HRTIM_ADCTRG1 event + value: 7 + - name: HRTIM_ADCTRG3 + description: HRTIM_ADCTRG3 event + value: 8 + - name: TIM1_TRGO + description: Timer 1 TRGO event + value: 9 + - name: TIM1_TRGO2 + description: Timer 1 TRGO2 event + value: 10 + - name: TIM2_TRGO + description: Timer 2 TRGO event + value: 11 + - name: TIM6_TRGO + description: Timer 6 TRGO event + value: 13 + - name: TIM15_TRGO + description: Timer 15 TRGO event + value: 14 + - name: TIM3_CC4 + description: Timer 3 CC4 event + value: 15 +enum/JAUTO: + bit_size: 1 + variants: + - name: Disabled + description: Automatic injected group conversion disabled + value: 0 + - name: Enabled + description: Automatic injected group conversion enabled + value: 1 +enum/JAWD1EN: + bit_size: 1 + variants: + - name: Disabled + description: Analog watchdog 1 disabled on injected channels + value: 0 + - name: Enabled + description: Analog watchdog 1 enabled on injected channels + value: 1 +enum/JDISCEN: + bit_size: 1 + variants: + - name: Disabled + description: Discontinuous mode on injected channels disabled + value: 0 + - name: Enabled + description: Discontinuous mode on injected channels enabled + value: 1 +enum/JEOCIE: + bit_size: 1 + variants: + - name: Disabled + description: End of injected conversion interrupt disabled + value: 0 + - name: Enabled + description: End of injected conversion interrupt enabled + value: 1 +enum/JEOCR: + bit_size: 1 + variants: + - name: NotComplete + description: Injected conversion is not complete + value: 0 + - name: Complete + description: Injected conversion complete + value: 1 +enum/JEOCW: + bit_size: 1 + variants: + - name: Clear + description: Clear injected conversion complete flag + value: 1 +enum/JEOSIE: + bit_size: 1 + variants: + - name: Disabled + description: End of injected sequence interrupt disabled + value: 0 + - name: Enabled + description: End of injected sequence interrupt enabled + value: 1 +enum/JEOSR: + bit_size: 1 + variants: + - name: NotComplete + description: Injected sequence is not complete + value: 0 + - name: Complete + description: Injected sequence complete + value: 1 +enum/JEOSW: + bit_size: 1 + variants: + - name: Clear + description: Clear Injected sequence complete flag + value: 1 +enum/JEXTEN: + bit_size: 2 + variants: + - name: Disabled + description: Trigger detection disabled + value: 0 + - name: RisingEdge + description: Trigger detection on the rising edge + value: 1 + - name: FallingEdge + description: Trigger detection on the falling edge + value: 2 + - name: BothEdges + description: Trigger detection on both the rising and falling edges + value: 3 +enum/JEXTSEL: + bit_size: 4 + variants: + - name: TIM1_TRGO + description: Timer 1 TRGO event + value: 0 + - name: TIM1_CC4 + description: Timer 1 CC4 event + value: 1 + - name: TIM2_TRGO + description: Timer 2 TRGO event + value: 2 + - name: TIM2_CC1 + description: Timer 2 CC1 event + value: 3 + - name: TIM3_CC4 + description: Timer 3 CC4 event + value: 4 + - name: EXTI15 + description: EXTI line 15 + value: 6 + - name: TIM1_TRGO2 + description: Timer 1 TRGO2 event + value: 8 + - name: HRTIM_ADCTRG2 + description: HRTIM_ADCTRG2 event + value: 9 + - name: HRTIM_ADCTRG4 + description: HRTIM_ADCTRG4 event + value: 10 + - name: TIM3_CC3 + description: Timer 3 CC3 event + value: 11 + - name: TIM3_TRGO + description: Timer 3 TRGO event + value: 12 + - name: TIM3_CC1 + description: Timer 3 CC1 event + value: 13 + - name: TIM6_TRGO + description: Timer 6 TRGO event + value: 14 + - name: TIM15_TRGO + description: Timer 15 TRGO event + value: 15 +enum/JQM: + bit_size: 1 + variants: + - name: Mode0 + description: "JSQR Mode 0: Queue maintains the last written configuration into JSQR" + value: 0 + - name: Mode1 + description: "JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence" + value: 1 +enum/JQOVFIE: + bit_size: 1 + variants: + - name: Disabled + description: Injected context queue overflow interrupt disabled + value: 0 + - name: Enabled + description: Injected context queue overflow interrupt enabled + value: 1 +enum/JQOVFR: + bit_size: 1 + variants: + - name: NoOverflow + description: No injected context queue overflow has occurred + value: 0 + - name: Overflow + description: Injected context queue overflow has occurred + value: 1 +enum/JQOVFW: + bit_size: 1 + variants: + - name: Clear + description: Clear injected context queue overflow flag + value: 1 +enum/OFFSET1_EN: + bit_size: 1 + variants: + - name: Disabled + description: Offset disabled + value: 0 + - name: Enabled + description: Offset enabled + value: 1 +enum/OFFSET2_EN: + bit_size: 1 + variants: + - name: Disabled + description: Offset disabled + value: 0 + - name: Enabled + description: Offset enabled + value: 1 +enum/OFFSET3_EN: + bit_size: 1 + variants: + - name: Disabled + description: Offset disabled + value: 0 + - name: Enabled + description: Offset enabled + value: 1 +enum/OFFSET4_EN: + bit_size: 1 + variants: + - name: Disabled + description: Offset disabled + value: 0 + - name: Enabled + description: Offset enabled + value: 1 +enum/OVRIE: + bit_size: 1 + variants: + - name: Disabled + description: Overrun interrupt disabled + value: 0 + - name: Enabled + description: Overrun interrupt enabled + value: 1 +enum/OVRMOD: + bit_size: 1 + variants: + - name: Preserve + description: Preserve DR register when an overrun is detected + value: 0 + - name: Overwrite + description: Overwrite DR register when an overrun is detected + value: 1 +enum/OVRR: + bit_size: 1 + variants: + - name: NoOverrun + description: No overrun occurred + value: 0 + - name: Overrun + description: Overrun occurred + value: 1 +enum/OVRW: + bit_size: 1 + variants: + - name: Clear + description: Clear overrun occurred flag + value: 1 +enum/RES: + bit_size: 2 + variants: + - name: Bits12 + description: 12-bit + value: 0 + - name: Bits10 + description: 10-bit + value: 1 + - name: Bits8 + description: 8-bit + value: 2 + - name: Bits6 + description: 6-bit + value: 3 +enum/SMP1: + bit_size: 3 + variants: + - name: Cycles1_5 + description: 1.5 ADC clock cycles + value: 0 + - name: Cycles2_5 + description: 2.5 ADC clock cycles + value: 1 + - name: Cycles4_5 + description: 4.5 ADC clock cycles + value: 2 + - name: Cycles7_5 + description: 7.5 ADC clock cycles + value: 3 + - name: Cycles19_5 + description: 19.5 ADC clock cycles + value: 4 + - name: Cycles61_5 + description: 61.5 ADC clock cycles + value: 5 + - name: Cycles181_5 + description: 181.5 ADC clock cycles + value: 6 + - name: Cycles601_5 + description: 601.5 ADC clock cycles + value: 7 +enum/SMP10: + bit_size: 3 + variants: + - name: Cycles1_5 + description: 1.5 ADC clock cycles + value: 0 + - name: Cycles2_5 + description: 2.5 ADC clock cycles + value: 1 + - name: Cycles4_5 + description: 4.5 ADC clock cycles + value: 2 + - name: Cycles7_5 + description: 7.5 ADC clock cycles + value: 3 + - name: Cycles19_5 + description: 19.5 ADC clock cycles + value: 4 + - name: Cycles61_5 + description: 61.5 ADC clock cycles + value: 5 + - name: Cycles181_5 + description: 181.5 ADC clock cycles + value: 6 + - name: Cycles601_5 + description: 601.5 ADC clock cycles + value: 7 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 6fd8359..e1f8907 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -163,6 +163,7 @@ impl PeriMatcher { (".*:DAC:dacif_v3_0", ("dac", "v2", "DAC")), (".*:DAC:F3_dacif_v1_1", ("dac", "v1", "DAC")), (".*:ADC:aditf_v2_5F1", ("adc", "f1", "ADC")), + (".*:ADC:aditf5_v1_1", ("adc", "f3", "ADC")), (".*:ADC:aditf4_v1_1", ("adc", "v1", "ADC")), (".*:ADC:aditf2_v1_1", ("adc", "v2", "ADC")), (".*:ADC:aditf5_v2_0", ("adc", "v3", "ADC")), From 48041c787ea9d3398d982a2b06906ce8e2cafb59 Mon Sep 17 00:00:00 2001 From: xoviat Date: Wed, 12 Jul 2023 17:33:23 -0500 Subject: [PATCH 2/6] adc/f3: some cleanup --- data/registers/adc_f3.yaml | 579 +++---------------------------------- 1 file changed, 44 insertions(+), 535 deletions(-) diff --git a/data/registers/adc_f3.yaml b/data/registers/adc_f3.yaml index 12d23f9..b25c66a 100644 --- a/data/registers/adc_f3.yaml +++ b/data/registers/adc_f3.yaml @@ -79,34 +79,21 @@ block/ADC1: description: offset register 4 byte_offset: 108 fieldset: OFR4 - - name: JDR1 + - name: JDR description: injected data register 1 byte_offset: 128 access: Read - fieldset: JDR1 - - name: JDR2 - description: injected data register 2 - byte_offset: 132 - access: Read - fieldset: JDR2 - - name: JDR3 - description: injected data register 3 - byte_offset: 136 - access: Read - fieldset: JDR3 - - name: JDR4 - description: injected data register 4 - byte_offset: 140 - access: Read - fieldset: JDR4 - - name: AWD2CR - description: "Analog Watchdog 2 Configuration\r Register" + fieldset: JDR + array: + len: 4 + stride: 4 + - name: AWDCR + description: "Analog Watchdog X Configuration\r Register" byte_offset: 160 - fieldset: AWD2CR - - name: AWD3CR - description: "Analog Watchdog 3 Configuration\r Register" - byte_offset: 164 - fieldset: AWD3CR + fieldset: AWDCR + array: + len: 2 + stride: 4 - name: DIFSEL description: "Differential Mode Selection Register\r 2" byte_offset: 176 @@ -115,192 +102,16 @@ block/ADC1: description: Calibration Factors byte_offset: 180 fieldset: CALFACT -fieldset/AWD2CR: +fieldset/AWDCR: description: "Analog Watchdog 2 Configuration\r Register" fields: - name: AWD2CH0 description: AWD2CH bit_offset: 1 bit_size: 1 - enum: AWD2CH0 - - name: AWD2CH1 - description: AWD2CH - bit_offset: 2 - bit_size: 1 - enum: AWD2CH0 - - name: AWD2CH2 - description: AWD2CH - bit_offset: 3 - bit_size: 1 - enum: AWD2CH0 - - name: AWD2CH3 - description: AWD2CH - bit_offset: 4 - bit_size: 1 - enum: AWD2CH0 - - name: AWD2CH4 - description: AWD2CH - bit_offset: 5 - bit_size: 1 - enum: AWD2CH0 - - name: AWD2CH5 - description: AWD2CH - bit_offset: 6 - bit_size: 1 - enum: AWD2CH0 - - name: AWD2CH6 - description: AWD2CH - bit_offset: 7 - bit_size: 1 - enum: AWD2CH0 - - name: AWD2CH7 - description: AWD2CH - bit_offset: 8 - bit_size: 1 - enum: AWD2CH0 - - name: AWD2CH8 - description: AWD2CH - bit_offset: 9 - bit_size: 1 - enum: AWD2CH0 - - name: AWD2CH9 - description: AWD2CH - bit_offset: 10 - bit_size: 1 - enum: AWD2CH0 - - name: AWD2CH10 - description: AWD2CH - bit_offset: 11 - bit_size: 1 - enum: AWD2CH0 - - name: AWD2CH11 - description: AWD2CH - bit_offset: 12 - bit_size: 1 - enum: AWD2CH0 - - name: AWD2CH12 - description: AWD2CH - bit_offset: 13 - bit_size: 1 - enum: AWD2CH0 - - name: AWD2CH13 - description: AWD2CH - bit_offset: 14 - bit_size: 1 - enum: AWD2CH0 - - name: AWD2CH14 - description: AWD2CH - bit_offset: 15 - bit_size: 1 - enum: AWD2CH0 - - name: AWD2CH15 - description: AWD2CH - bit_offset: 16 - bit_size: 1 - enum: AWD2CH0 - - name: AWD2CH16 - description: AWD2CH - bit_offset: 17 - bit_size: 1 - enum: AWD2CH0 - - name: AWD2CH17 - description: AWD2CH - bit_offset: 18 - bit_size: 1 - enum: AWD2CH0 -fieldset/AWD3CR: - description: "Analog Watchdog 3 Configuration\r Register" - fields: - - name: AWD3CH0 - description: AWD3CH - bit_offset: 1 - bit_size: 1 - enum: AWD3CH0 - - name: AWD3CH1 - description: AWD3CH - bit_offset: 2 - bit_size: 1 - enum: AWD3CH0 - - name: AWD3CH2 - description: AWD3CH - bit_offset: 3 - bit_size: 1 - enum: AWD3CH0 - - name: AWD3CH3 - description: AWD3CH - bit_offset: 4 - bit_size: 1 - enum: AWD3CH0 - - name: AWD3CH4 - description: AWD3CH - bit_offset: 5 - bit_size: 1 - enum: AWD3CH0 - - name: AWD3CH5 - description: AWD3CH - bit_offset: 6 - bit_size: 1 - enum: AWD3CH0 - - name: AWD3CH6 - description: AWD3CH - bit_offset: 7 - bit_size: 1 - enum: AWD3CH0 - - name: AWD3CH7 - description: AWD3CH - bit_offset: 8 - bit_size: 1 - enum: AWD3CH0 - - name: AWD3CH8 - description: AWD3CH - bit_offset: 9 - bit_size: 1 - enum: AWD3CH0 - - name: AWD3CH9 - description: AWD3CH - bit_offset: 10 - bit_size: 1 - enum: AWD3CH0 - - name: AWD3CH10 - description: AWD3CH - bit_offset: 11 - bit_size: 1 - enum: AWD3CH0 - - name: AWD3CH11 - description: AWD3CH - bit_offset: 12 - bit_size: 1 - enum: AWD3CH0 - - name: AWD3CH12 - description: AWD3CH - bit_offset: 13 - bit_size: 1 - enum: AWD3CH0 - - name: AWD3CH13 - description: AWD3CH - bit_offset: 14 - bit_size: 1 - enum: AWD3CH0 - - name: AWD3CH14 - description: AWD3CH - bit_offset: 15 - bit_size: 1 - enum: AWD3CH0 - - name: AWD3CH15 - description: AWD3CH - bit_offset: 16 - bit_size: 1 - enum: AWD3CH0 - - name: AWD3CH16 - description: AWD3CH - bit_offset: 17 - bit_size: 1 - enum: AWD3CH0 - - name: AWD3CH17 - description: AWD3CH - bit_offset: 18 - bit_size: 1 - enum: AWD3CH0 + array: + len: 17 + stride: 1 fieldset/CALFACT: description: Calibration Factors fields: @@ -619,97 +430,49 @@ fieldset/ISR: description: interrupt and status register fields: - name: ADRDY - description: ADRDY + description: ADC Ready bit_offset: 0 bit_size: 1 - enum_read: ADRDYR - enum_write: ADRDYW - name: EOSMP - description: EOSMP + description: End of sampling flag bit_offset: 1 bit_size: 1 - enum_read: EOSMPR - enum_write: EOSMPW - name: EOC - description: EOC + description: End of conversion flag bit_offset: 2 bit_size: 1 - enum_read: EOCR - enum_write: EOCW - name: EOS - description: EOS + description: End of regular sequence flag bit_offset: 3 bit_size: 1 - enum_read: EOSR - enum_write: EOSW - name: OVR - description: OVR + description: ADC overrun bit_offset: 4 bit_size: 1 - enum_read: OVRR - enum_write: OVRW - name: JEOC - description: JEOC + description: Injected channel end of conversion flag bit_offset: 5 bit_size: 1 - enum_read: JEOCR - enum_write: JEOCW - name: JEOS - description: JEOS + description: Injected channel end of sequence flag bit_offset: 6 bit_size: 1 - enum_read: JEOSR - enum_write: JEOSW - - name: AWD1 - description: AWD1 + - name: AWD + description: Analog watchdog flag bit_offset: 7 bit_size: 1 - enum_read: AWD1R - enum_write: AWD1W - - name: AWD2 - description: AWD2 - bit_offset: 8 - bit_size: 1 - enum_read: AWD1R - enum_write: AWD1W - - name: AWD3 - description: AWD3 - bit_offset: 9 - bit_size: 1 - enum_read: AWD1R - enum_write: AWD1W + array: + len: 3 + stride: 1 - name: JQOVF - description: JQOVF + description: Injected context queue overflow bit_offset: 10 bit_size: 1 - enum_read: JQOVFR - enum_write: JQOVFW -fieldset/JDR1: +fieldset/JDR: description: injected data register 1 fields: - - name: JDATA1 - description: JDATA1 - bit_offset: 0 - bit_size: 16 -fieldset/JDR2: - description: injected data register 2 - fields: - - name: JDATA2 - description: JDATA2 - bit_offset: 0 - bit_size: 16 -fieldset/JDR3: - description: injected data register 3 - fields: - - name: JDATA3 - description: JDATA3 - bit_offset: 0 - bit_size: 16 -fieldset/JDR4: - description: injected data register 4 - fields: - - name: JDATA4 - description: JDATA4 + - name: JDATA + description: Injected data bit_offset: 0 bit_size: 16 fieldset/JSQR: @@ -812,99 +575,25 @@ fieldset/OFR4: fieldset/SMPR1: description: sample time register 1 fields: - - name: SMP1 - description: SMP1 + - name: SMP + description: Channel x sampling time selection bit_offset: 3 bit_size: 3 - enum: SMP1 - - name: SMP2 - description: SMP2 - bit_offset: 6 - bit_size: 3 - enum: SMP1 - - name: SMP3 - description: SMP3 - bit_offset: 9 - bit_size: 3 - enum: SMP1 - - name: SMP4 - description: SMP4 - bit_offset: 12 - bit_size: 3 - enum: SMP1 - - name: SMP5 - description: SMP5 - bit_offset: 15 - bit_size: 3 - enum: SMP1 - - name: SMP6 - description: SMP6 - bit_offset: 18 - bit_size: 3 - enum: SMP1 - - name: SMP7 - description: SMP7 - bit_offset: 21 - bit_size: 3 - enum: SMP1 - - name: SMP8 - description: SMP8 - bit_offset: 24 - bit_size: 3 - enum: SMP1 - - name: SMP9 - description: SMP9 - bit_offset: 27 - bit_size: 3 - enum: SMP1 + enum: SMP + array: + len: 9 + stride: 3 fieldset/SMPR2: description: sample time register 2 fields: - - name: SMP10 - description: SMP10 + - name: SMP + description: Channel x sampling time selection bit_offset: 0 bit_size: 3 - enum: SMP10 - - name: SMP11 - description: SMP11 - bit_offset: 3 - bit_size: 3 - enum: SMP10 - - name: SMP12 - description: SMP12 - bit_offset: 6 - bit_size: 3 - enum: SMP10 - - name: SMP13 - description: SMP13 - bit_offset: 9 - bit_size: 3 - enum: SMP10 - - name: SMP14 - description: SMP14 - bit_offset: 12 - bit_size: 3 - enum: SMP10 - - name: SMP15 - description: SMP15 - bit_offset: 15 - bit_size: 3 - enum: SMP10 - - name: SMP16 - description: SMP16 - bit_offset: 18 - bit_size: 3 - enum: SMP10 - - name: SMP17 - description: SMP17 - bit_offset: 21 - bit_size: 3 - enum: SMP10 - - name: SMP18 - description: SMP18 - bit_offset: 24 - bit_size: 3 - enum: SMP10 + enum: SMP + array: + len: 9 + stride: 3 fieldset/SQR1: description: regular sequence register 1 fields: @@ -1075,21 +764,6 @@ enum/ADRDYIE: - name: Enabled description: ADC ready interrupt enabled value: 1 -enum/ADRDYR: - bit_size: 1 - variants: - - name: NotReady - description: ADC is not ready to start conversion - value: 0 - - name: Ready - description: ADC is ready to start conversion - value: 1 -enum/ADRDYW: - bit_size: 1 - variants: - - name: Clear - description: Clear ADC is ready to start conversion flag - value: 1 enum/ADSTARTR: bit_size: 1 variants: @@ -1168,15 +842,6 @@ enum/AWD1IE: - name: Enabled description: Analog watchdog interrupt enabled value: 1 -enum/AWD1R: - bit_size: 1 - variants: - - name: NoEvent - description: No analog watchdog event occurred - value: 0 - - name: Event - description: Analog watchdog event occurred - value: 1 enum/AWD1SGL: bit_size: 1 variants: @@ -1186,30 +851,6 @@ enum/AWD1SGL: - name: Single description: Analog watchdog 1 enabled on single channel selected in AWD1CH value: 1 -enum/AWD1W: - bit_size: 1 - variants: - - name: Clear - description: Clear analog watchdog event occurred flag - value: 1 -enum/AWD2CH0: - bit_size: 1 - variants: - - name: NotMonitored - description: Input channel not monitored by AWDx - value: 0 - - name: Monitored - description: Input channel monitored by AWDx - value: 1 -enum/AWD3CH0: - bit_size: 1 - variants: - - name: NotMonitored - description: Input channel not monitored by AWDx - value: 0 - - name: Monitored - description: Input channel monitored by AWDx - value: 1 enum/CONT: bit_size: 1 variants: @@ -1264,21 +905,6 @@ enum/EOCIE: - name: Enabled description: End of regular conversion interrupt enabled value: 1 -enum/EOCR: - bit_size: 1 - variants: - - name: NotComplete - description: Regular conversion is not complete - value: 0 - - name: Complete - description: Regular conversion complete - value: 1 -enum/EOCW: - bit_size: 1 - variants: - - name: Clear - description: Clear regular conversion complete flag - value: 1 enum/EOSIE: bit_size: 1 variants: @@ -1297,36 +923,6 @@ enum/EOSMPIE: - name: Enabled description: End of regular conversion sampling phase interrupt enabled value: 1 -enum/EOSMPR: - bit_size: 1 - variants: - - name: NotEnded - description: End of sampling phase no yet reached - value: 0 - - name: Ended - description: End of sampling phase reached - value: 1 -enum/EOSMPW: - bit_size: 1 - variants: - - name: Clear - description: Clear end of sampling phase reached flag - value: 1 -enum/EOSR: - bit_size: 1 - variants: - - name: NotComplete - description: Regular sequence is not complete - value: 0 - - name: Complete - description: Regular sequence complete - value: 1 -enum/EOSW: - bit_size: 1 - variants: - - name: Clear - description: Clear regular sequence complete flag - value: 1 enum/EXTEN: bit_size: 2 variants: @@ -1423,21 +1019,6 @@ enum/JEOCIE: - name: Enabled description: End of injected conversion interrupt enabled value: 1 -enum/JEOCR: - bit_size: 1 - variants: - - name: NotComplete - description: Injected conversion is not complete - value: 0 - - name: Complete - description: Injected conversion complete - value: 1 -enum/JEOCW: - bit_size: 1 - variants: - - name: Clear - description: Clear injected conversion complete flag - value: 1 enum/JEOSIE: bit_size: 1 variants: @@ -1447,21 +1028,6 @@ enum/JEOSIE: - name: Enabled description: End of injected sequence interrupt enabled value: 1 -enum/JEOSR: - bit_size: 1 - variants: - - name: NotComplete - description: Injected sequence is not complete - value: 0 - - name: Complete - description: Injected sequence complete - value: 1 -enum/JEOSW: - bit_size: 1 - variants: - - name: Clear - description: Clear Injected sequence complete flag - value: 1 enum/JEXTEN: bit_size: 2 variants: @@ -1540,21 +1106,6 @@ enum/JQOVFIE: - name: Enabled description: Injected context queue overflow interrupt enabled value: 1 -enum/JQOVFR: - bit_size: 1 - variants: - - name: NoOverflow - description: No injected context queue overflow has occurred - value: 0 - - name: Overflow - description: Injected context queue overflow has occurred - value: 1 -enum/JQOVFW: - bit_size: 1 - variants: - - name: Clear - description: Clear injected context queue overflow flag - value: 1 enum/OFFSET1_EN: bit_size: 1 variants: @@ -1609,21 +1160,6 @@ enum/OVRMOD: - name: Overwrite description: Overwrite DR register when an overrun is detected value: 1 -enum/OVRR: - bit_size: 1 - variants: - - name: NoOverrun - description: No overrun occurred - value: 0 - - name: Overrun - description: Overrun occurred - value: 1 -enum/OVRW: - bit_size: 1 - variants: - - name: Clear - description: Clear overrun occurred flag - value: 1 enum/RES: bit_size: 2 variants: @@ -1639,34 +1175,7 @@ enum/RES: - name: Bits6 description: 6-bit value: 3 -enum/SMP1: - bit_size: 3 - variants: - - name: Cycles1_5 - description: 1.5 ADC clock cycles - value: 0 - - name: Cycles2_5 - description: 2.5 ADC clock cycles - value: 1 - - name: Cycles4_5 - description: 4.5 ADC clock cycles - value: 2 - - name: Cycles7_5 - description: 7.5 ADC clock cycles - value: 3 - - name: Cycles19_5 - description: 19.5 ADC clock cycles - value: 4 - - name: Cycles61_5 - description: 61.5 ADC clock cycles - value: 5 - - name: Cycles181_5 - description: 181.5 ADC clock cycles - value: 6 - - name: Cycles601_5 - description: 601.5 ADC clock cycles - value: 7 -enum/SMP10: +enum/SMP: bit_size: 3 variants: - name: Cycles1_5 From cada030e1a7f2014ee698779cc9a7a79ee892c2d Mon Sep 17 00:00:00 2001 From: xoviat Date: Wed, 12 Jul 2023 17:45:39 -0500 Subject: [PATCH 3/6] adc/f3: more cleanup --- data/registers/adc_f3.yaml | 200 +++++++------------------------------ 1 file changed, 35 insertions(+), 165 deletions(-) diff --git a/data/registers/adc_f3.yaml b/data/registers/adc_f3.yaml index b25c66a..13f46ee 100644 --- a/data/registers/adc_f3.yaml +++ b/data/registers/adc_f3.yaml @@ -63,24 +63,15 @@ block/ADC1: description: injected sequence register byte_offset: 76 fieldset: JSQR - - name: OFR1 - description: offset register 1 + - name: OFR + description: offset register X byte_offset: 96 - fieldset: OFR1 - - name: OFR2 - description: offset register 2 - byte_offset: 100 - fieldset: OFR2 - - name: OFR3 - description: offset register 3 - byte_offset: 104 - fieldset: OFR3 - - name: OFR4 - description: offset register 4 - byte_offset: 108 - fieldset: OFR4 + fieldset: OFR + array: + len: 4 + stride: 4 - name: JDR - description: injected data register 1 + description: injected data register X byte_offset: 128 access: Read fieldset: JDR @@ -508,70 +499,21 @@ fieldset/JSQR: description: JSQ4 bit_offset: 26 bit_size: 5 -fieldset/OFR1: +fieldset/OFR: description: offset register 1 fields: - - name: OFFSET1 - description: OFFSET1 + - name: OFFSET + description: Data offset y for the channel programmed into bits OFFSETy_CH bit_offset: 0 bit_size: 12 - - name: OFFSET1_CH - description: OFFSET1_CH + - name: CH + description: Data offset y for the channel programmed into bits OFFSETy_CH bit_offset: 26 bit_size: 5 - - name: OFFSET1_EN - description: OFFSET1_EN + - name: EN + description: Offset y Enable bit_offset: 31 bit_size: 1 - enum: OFFSET1_EN -fieldset/OFR2: - description: offset register 2 - fields: - - name: OFFSET2 - description: OFFSET2 - bit_offset: 0 - bit_size: 12 - - name: OFFSET2_CH - description: OFFSET2_CH - bit_offset: 26 - bit_size: 5 - - name: OFFSET2_EN - description: OFFSET2_EN - bit_offset: 31 - bit_size: 1 - enum: OFFSET2_EN -fieldset/OFR3: - description: offset register 3 - fields: - - name: OFFSET3 - description: OFFSET3 - bit_offset: 0 - bit_size: 12 - - name: OFFSET3_CH - description: OFFSET3_CH - bit_offset: 26 - bit_size: 5 - - name: OFFSET3_EN - description: OFFSET3_EN - bit_offset: 31 - bit_size: 1 - enum: OFFSET3_EN -fieldset/OFR4: - description: offset register 4 - fields: - - name: OFFSET4 - description: OFFSET4 - bit_offset: 0 - bit_size: 12 - - name: OFFSET4_CH - description: OFFSET4_CH - bit_offset: 26 - bit_size: 5 - - name: OFFSET4_EN - description: OFFSET4_EN - bit_offset: 31 - bit_size: 1 - enum: OFFSET4_EN fieldset/SMPR1: description: sample time register 1 fields: @@ -598,82 +540,46 @@ fieldset/SQR1: description: regular sequence register 1 fields: - name: L - description: L3 + description: Regular channel sequence length bit_offset: 0 bit_size: 4 - - name: SQ1 - description: SQ1 + - name: SQ + description: X conversion in regular sequence bit_offset: 6 bit_size: 5 - - name: SQ2 - description: SQ2 - bit_offset: 12 - bit_size: 5 - - name: SQ3 - description: SQ3 - bit_offset: 18 - bit_size: 5 - - name: SQ4 - description: SQ4 - bit_offset: 24 - bit_size: 5 + array: + len: 4 + stride: 6 fieldset/SQR2: description: regular sequence register 2 fields: - - name: SQ5 - description: SQ5 + - name: SQ + description: X conversion in regular sequence bit_offset: 0 bit_size: 5 - - name: SQ6 - description: SQ6 - bit_offset: 6 - bit_size: 5 - - name: SQ7 - description: SQ7 - bit_offset: 12 - bit_size: 5 - - name: SQ8 - description: SQ8 - bit_offset: 18 - bit_size: 5 - - name: SQ9 - description: SQ9 - bit_offset: 24 - bit_size: 5 + array: + len: 5 + stride: 6 fieldset/SQR3: description: regular sequence register 3 fields: - - name: SQ10 - description: SQ10 + - name: SQ + description: X conversion in regular sequence bit_offset: 0 bit_size: 5 - - name: SQ11 - description: SQ11 - bit_offset: 6 - bit_size: 5 - - name: SQ12 - description: SQ12 - bit_offset: 12 - bit_size: 5 - - name: SQ13 - description: SQ13 - bit_offset: 18 - bit_size: 5 - - name: SQ14 - description: SQ14 - bit_offset: 24 - bit_size: 5 + array: + len: 5 + stride: 6 fieldset/SQR4: description: regular sequence register 4 fields: - - name: SQ15 - description: SQ15 + - name: SQ + description: X conversion in regular sequence bit_offset: 0 bit_size: 5 - - name: SQ16 - description: SQ16 - bit_offset: 6 - bit_size: 5 + array: + len: 2 + stride: 6 fieldset/TR1: description: watchdog threshold register 1 fields: @@ -1106,42 +1012,6 @@ enum/JQOVFIE: - name: Enabled description: Injected context queue overflow interrupt enabled value: 1 -enum/OFFSET1_EN: - bit_size: 1 - variants: - - name: Disabled - description: Offset disabled - value: 0 - - name: Enabled - description: Offset enabled - value: 1 -enum/OFFSET2_EN: - bit_size: 1 - variants: - - name: Disabled - description: Offset disabled - value: 0 - - name: Enabled - description: Offset enabled - value: 1 -enum/OFFSET3_EN: - bit_size: 1 - variants: - - name: Disabled - description: Offset disabled - value: 0 - - name: Enabled - description: Offset enabled - value: 1 -enum/OFFSET4_EN: - bit_size: 1 - variants: - - name: Disabled - description: Offset disabled - value: 0 - - name: Enabled - description: Offset enabled - value: 1 enum/OVRIE: bit_size: 1 variants: From c943b0472dcec467d227c2dde15932d1430053ef Mon Sep 17 00:00:00 2001 From: xoviat Date: Wed, 12 Jul 2023 18:00:55 -0500 Subject: [PATCH 4/6] adc/f3: more cleanup --- data/registers/adc_f3.yaml | 246 ++++--------------------------------- 1 file changed, 27 insertions(+), 219 deletions(-) diff --git a/data/registers/adc_f3.yaml b/data/registers/adc_f3.yaml index 13f46ee..1321cf9 100644 --- a/data/registers/adc_f3.yaml +++ b/data/registers/adc_f3.yaml @@ -118,147 +118,123 @@ fieldset/CFGR: description: configuration register fields: - name: DMAEN - description: DMAEN + description: Direct memory access enable bit_offset: 0 bit_size: 1 - enum: DMAEN - name: DMACFG - description: DMACFG + description: Direct memory access configuration bit_offset: 1 bit_size: 1 - enum: DMACFG - name: RES - description: RES + description: Data resolution bit_offset: 3 bit_size: 2 enum: RES - name: ALIGN - description: ALIGN + description: Data alignment bit_offset: 5 bit_size: 1 enum: ALIGN - name: EXTSEL - description: EXTSEL + description: External trigger selection for regular group bit_offset: 6 bit_size: 4 enum: EXTSEL - name: EXTEN - description: EXTEN + description: External trigger enable and polarity selection for regular channels bit_offset: 10 bit_size: 2 enum: EXTEN - name: OVRMOD - description: OVRMOD + description: Overrun Mode bit_offset: 12 bit_size: 1 - enum: OVRMOD - name: CONT - description: CONT + description: Single / continuous conversion mode for regular conversions bit_offset: 13 bit_size: 1 - enum: CONT - name: AUTDLY - description: AUTDLY + description: Delayed conversion mode bit_offset: 14 bit_size: 1 - enum: AUTDLY - name: DISCEN - description: DISCEN + description: Discontinuous mode for regular channels bit_offset: 16 bit_size: 1 - enum: DISCEN - name: DISCNUM - description: DISCNUM + description: Discontinuous mode channel count bit_offset: 17 bit_size: 3 - name: JDISCEN - description: JDISCEN + description: Discontinuous mode on injected channels bit_offset: 20 bit_size: 1 - enum: JDISCEN - name: JQM - description: JQM + description: JSQR queue mode bit_offset: 21 bit_size: 1 enum: JQM - name: AWD1SGL - description: AWD1SGL + description: Enable the watchdog 1 on a single channel or on all channels bit_offset: 22 bit_size: 1 enum: AWD1SGL - name: AWD1EN - description: AWD1EN + description: Analog watchdog 1 enable on regular channels bit_offset: 23 bit_size: 1 - enum: AWD1EN - name: JAWD1EN - description: JAWD1EN + description: Analog watchdog 1 enable on injected channels bit_offset: 24 bit_size: 1 - enum: JAWD1EN - name: JAUTO - description: JAUTO + description: Automatic injected group conversion bit_offset: 25 bit_size: 1 - enum: JAUTO - name: AWD1CH - description: AWDCH1CH + description: Analog watchdog 1 channel selection bit_offset: 26 bit_size: 5 fieldset/CR: description: control register fields: - name: ADEN - description: ADEN + description: ADC enable control bit_offset: 0 bit_size: 1 - enum_read: ADENR - enum_write: ADENW - name: ADDIS - description: ADDIS + description: ADC disable command bit_offset: 1 bit_size: 1 - enum_read: ADDISR - enum_write: ADDISW - name: ADSTART - description: ADSTART + description: ADC start of regular conversion bit_offset: 2 bit_size: 1 - enum_read: ADSTARTR - enum_write: ADSTARTW - name: JADSTART - description: JADSTART + description: ADC start of injected conversion bit_offset: 3 bit_size: 1 - enum_read: ADSTARTR - enum_write: ADSTARTW - name: ADSTP - description: ADSTP + description: ADC stop of regular conversion command bit_offset: 4 bit_size: 1 - enum_read: ADSTPR - enum_write: ADSTPW - name: JADSTP - description: JADSTP + description: ADC stop of injected conversion command bit_offset: 5 bit_size: 1 - enum_read: ADSTPR - enum_write: ADSTPW - name: ADVREGEN - description: ADVREGEN + description: ADC voltage regulator enable bit_offset: 28 bit_size: 2 enum: ADVREGEN - name: ADCALDIF - description: ADCALDIF + description: Differential mode for calibration bit_offset: 30 bit_size: 1 - enum: ADCALDIF - name: ADCAL - description: ADCAL + description: ADC calibration bit_offset: 31 bit_size: 1 - enum: ADCAL fieldset/DIFSEL: description: "Differential Mode Selection Register\r 2" fields: @@ -613,54 +589,6 @@ fieldset/TR3: description: HT3 bit_offset: 16 bit_size: 8 -enum/ADCAL: - bit_size: 1 - variants: - - name: Complete - description: Calibration complete - value: 0 - - name: Calibration - description: Start the calibration of the ADC - value: 1 -enum/ADCALDIF: - bit_size: 1 - variants: - - name: SingleEnded - description: Calibration for single-ended mode - value: 0 - - name: Differential - description: Calibration for differential mode - value: 1 -enum/ADDISR: - bit_size: 1 - variants: - - name: NotDisabling - description: No disable command active - value: 0 - - name: Disabling - description: ADC disabling - value: 1 -enum/ADDISW: - bit_size: 1 - variants: - - name: Disable - description: Disable the ADC - value: 1 -enum/ADENR: - bit_size: 1 - variants: - - name: Disabled - description: ADC disabled - value: 0 - - name: Enabled - description: ADC enabled - value: 1 -enum/ADENW: - bit_size: 1 - variants: - - name: Enabled - description: Enable the ADC - value: 1 enum/ADRDYIE: bit_size: 1 variants: @@ -670,36 +598,6 @@ enum/ADRDYIE: - name: Enabled description: ADC ready interrupt enabled value: 1 -enum/ADSTARTR: - bit_size: 1 - variants: - - name: NotActive - description: No conversion ongoing - value: 0 - - name: Active - description: ADC operating and may be converting - value: 1 -enum/ADSTARTW: - bit_size: 1 - variants: - - name: StartConversion - description: Start the ADC conversion (may be delayed for hardware triggers) - value: 1 -enum/ADSTPR: - bit_size: 1 - variants: - - name: NotStopping - description: No stop command active - value: 0 - - name: Stopping - description: ADC stopping conversion - value: 1 -enum/ADSTPW: - bit_size: 1 - variants: - - name: StopConversion - description: Stop the active conversion - value: 1 enum/ADVREGEN: bit_size: 2 variants: @@ -721,24 +619,6 @@ enum/ALIGN: - name: Left description: Left alignment value: 1 -enum/AUTDLY: - bit_size: 1 - variants: - - name: "Off" - description: Auto delayed conversion mode off - value: 0 - - name: "On" - description: Auto delayed conversion mode on - value: 1 -enum/AWD1EN: - bit_size: 1 - variants: - - name: Disabled - description: Analog watchdog 1 disabled on regular channels - value: 0 - - name: Enabled - description: Analog watchdog 1 enabled on regular channels - value: 1 enum/AWD1IE: bit_size: 1 variants: @@ -757,15 +637,6 @@ enum/AWD1SGL: - name: Single description: Analog watchdog 1 enabled on single channel selected in AWD1CH value: 1 -enum/CONT: - bit_size: 1 - variants: - - name: Single - description: Single conversion mode - value: 0 - - name: Continuous - description: Continuous conversion mode - value: 1 enum/DIFSEL_10: bit_size: 1 variants: @@ -775,33 +646,6 @@ enum/DIFSEL_10: - name: Differential description: Input channel is configured in differential mode value: 1 -enum/DISCEN: - bit_size: 1 - variants: - - name: Disabled - description: Discontinuous mode on regular channels disabled - value: 0 - - name: Enabled - description: Discontinuous mode on regular channels enabled - value: 1 -enum/DMACFG: - bit_size: 1 - variants: - - name: OneShot - description: DMA One Shot Mode selected - value: 0 - - name: Circular - description: DMA circular mode selected - value: 1 -enum/DMAEN: - bit_size: 1 - variants: - - name: Disabled - description: DMA disabled - value: 0 - - name: Enabled - description: DMA enabled - value: 1 enum/EOCIE: bit_size: 1 variants: @@ -889,33 +733,6 @@ enum/EXTSEL: - name: TIM3_CC4 description: Timer 3 CC4 event value: 15 -enum/JAUTO: - bit_size: 1 - variants: - - name: Disabled - description: Automatic injected group conversion disabled - value: 0 - - name: Enabled - description: Automatic injected group conversion enabled - value: 1 -enum/JAWD1EN: - bit_size: 1 - variants: - - name: Disabled - description: Analog watchdog 1 disabled on injected channels - value: 0 - - name: Enabled - description: Analog watchdog 1 enabled on injected channels - value: 1 -enum/JDISCEN: - bit_size: 1 - variants: - - name: Disabled - description: Discontinuous mode on injected channels disabled - value: 0 - - name: Enabled - description: Discontinuous mode on injected channels enabled - value: 1 enum/JEOCIE: bit_size: 1 variants: @@ -1021,15 +838,6 @@ enum/OVRIE: - name: Enabled description: Overrun interrupt enabled value: 1 -enum/OVRMOD: - bit_size: 1 - variants: - - name: Preserve - description: Preserve DR register when an overrun is detected - value: 0 - - name: Overwrite - description: Overwrite DR register when an overrun is detected - value: 1 enum/RES: bit_size: 2 variants: From 5ae0934c28e1bb0730c8e68bbf058c10f95d6c54 Mon Sep 17 00:00:00 2001 From: xoviat Date: Wed, 12 Jul 2023 19:42:31 -0500 Subject: [PATCH 5/6] adc/f3: more cleanup --- data/registers/adc_f3.yaml | 148 ++++++------------------------------- 1 file changed, 21 insertions(+), 127 deletions(-) diff --git a/data/registers/adc_f3.yaml b/data/registers/adc_f3.yaml index 1321cf9..a9ca67c 100644 --- a/data/registers/adc_f3.yaml +++ b/data/registers/adc_f3.yaml @@ -339,60 +339,44 @@ fieldset/IER: description: interrupt enable register fields: - name: ADRDYIE - description: ADRDYIE + description: ADC ready interrupt enable bit_offset: 0 bit_size: 1 - enum: ADRDYIE - name: EOSMPIE - description: EOSMPIE + description: End of sampling flag interrupt enable for regular conversions bit_offset: 1 bit_size: 1 - enum: EOSMPIE - name: EOCIE - description: EOCIE + description: End of regular conversion interrupt enable bit_offset: 2 bit_size: 1 - enum: EOCIE - name: EOSIE - description: EOSIE + description: End of regular sequence of conversions interrupt enable bit_offset: 3 bit_size: 1 - enum: EOSIE - name: OVRIE - description: OVRIE + description: Overrun interrupt enable bit_offset: 4 bit_size: 1 - enum: OVRIE - name: JEOCIE - description: JEOCIE + description: End of injected conversion interrupt enable bit_offset: 5 bit_size: 1 - enum: JEOCIE - name: JEOSIE - description: JEOSIE + description: End of injected sequence of conversions interrupt enable bit_offset: 6 bit_size: 1 - enum: JEOSIE - - name: AWD1IE - description: AWD1IE + - name: AWDIE + description: Analog watchdog X interrupt enable bit_offset: 7 bit_size: 1 - enum: AWD1IE - - name: AWD2IE - description: AWD2IE - bit_offset: 8 - bit_size: 1 - enum: AWD1IE - - name: AWD3IE - description: AWD3IE - bit_offset: 9 - bit_size: 1 - enum: AWD1IE + array: + len: 3 + stride: 1 - name: JQOVFIE - description: JQOVFIE + description: Injected context queue overflow interrupt enable bit_offset: 10 bit_size: 1 - enum: JQOVFIE fieldset/ISR: description: interrupt and status register fields: @@ -446,35 +430,26 @@ fieldset/JSQR: description: injected sequence register fields: - name: JL - description: JL + description: Injected channel sequence length bit_offset: 0 bit_size: 2 - name: JEXTSEL - description: JEXTSEL + description: External Trigger Selection for injected group bit_offset: 2 bit_size: 4 enum: JEXTSEL - name: JEXTEN - description: JEXTEN + description: External Trigger Enable and Polarity Selection for injected channels bit_offset: 6 bit_size: 2 enum: JEXTEN - - name: JSQ1 - description: JSQ1 + - name: JSQ + description: X conversion in the injected sequence bit_offset: 8 bit_size: 5 - - name: JSQ2 - description: JSQ2 - bit_offset: 14 - bit_size: 5 - - name: JSQ3 - description: JSQ3 - bit_offset: 20 - bit_size: 5 - - name: JSQ4 - description: JSQ4 - bit_offset: 26 - bit_size: 5 + array: + len: 4 + stride: 6 fieldset/OFR: description: offset register 1 fields: @@ -589,15 +564,6 @@ fieldset/TR3: description: HT3 bit_offset: 16 bit_size: 8 -enum/ADRDYIE: - bit_size: 1 - variants: - - name: Disabled - description: ADC ready interrupt disabled - value: 0 - - name: Enabled - description: ADC ready interrupt enabled - value: 1 enum/ADVREGEN: bit_size: 2 variants: @@ -619,15 +585,6 @@ enum/ALIGN: - name: Left description: Left alignment value: 1 -enum/AWD1IE: - bit_size: 1 - variants: - - name: Disabled - description: Analog watchdog interrupt disabled - value: 0 - - name: Enabled - description: Analog watchdog interrupt enabled - value: 1 enum/AWD1SGL: bit_size: 1 variants: @@ -646,33 +603,6 @@ enum/DIFSEL_10: - name: Differential description: Input channel is configured in differential mode value: 1 -enum/EOCIE: - bit_size: 1 - variants: - - name: Disabled - description: End of regular conversion interrupt disabled - value: 0 - - name: Enabled - description: End of regular conversion interrupt enabled - value: 1 -enum/EOSIE: - bit_size: 1 - variants: - - name: Disabled - description: End of regular sequence interrupt disabled - value: 0 - - name: Enabled - description: End of regular sequence interrupt enabled - value: 1 -enum/EOSMPIE: - bit_size: 1 - variants: - - name: Disabled - description: End of regular conversion sampling phase interrupt disabled - value: 0 - - name: Enabled - description: End of regular conversion sampling phase interrupt enabled - value: 1 enum/EXTEN: bit_size: 2 variants: @@ -733,24 +663,6 @@ enum/EXTSEL: - name: TIM3_CC4 description: Timer 3 CC4 event value: 15 -enum/JEOCIE: - bit_size: 1 - variants: - - name: Disabled - description: End of injected conversion interrupt disabled - value: 0 - - name: Enabled - description: End of injected conversion interrupt enabled - value: 1 -enum/JEOSIE: - bit_size: 1 - variants: - - name: Disabled - description: End of injected sequence interrupt disabled - value: 0 - - name: Enabled - description: End of injected sequence interrupt enabled - value: 1 enum/JEXTEN: bit_size: 2 variants: @@ -820,24 +732,6 @@ enum/JQM: - name: Mode1 description: "JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence" value: 1 -enum/JQOVFIE: - bit_size: 1 - variants: - - name: Disabled - description: Injected context queue overflow interrupt disabled - value: 0 - - name: Enabled - description: Injected context queue overflow interrupt enabled - value: 1 -enum/OVRIE: - bit_size: 1 - variants: - - name: Disabled - description: Overrun interrupt disabled - value: 0 - - name: Enabled - description: Overrun interrupt enabled - value: 1 enum/RES: bit_size: 2 variants: From 4b06fdbf76d7d3a7dd848acdf1ac465ecad7e913 Mon Sep 17 00:00:00 2001 From: xoviat Date: Wed, 12 Jul 2023 19:43:25 -0500 Subject: [PATCH 6/6] adc/f3: naming --- data/registers/adc_f3.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/data/registers/adc_f3.yaml b/data/registers/adc_f3.yaml index a9ca67c..35354b8 100644 --- a/data/registers/adc_f3.yaml +++ b/data/registers/adc_f3.yaml @@ -1,5 +1,5 @@ --- -block/ADC1: +block/ADC: description: Analog-to-Digital Converter items: - name: ISR