diff --git a/data/registers/adc_f3.yaml b/data/registers/adc_f3.yaml new file mode 100644 index 0000000..35354b8 --- /dev/null +++ b/data/registers/adc_f3.yaml @@ -0,0 +1,776 @@ +--- +block/ADC: + description: Analog-to-Digital Converter + items: + - name: ISR + description: interrupt and status register + byte_offset: 0 + fieldset: ISR + - name: IER + description: interrupt enable register + byte_offset: 4 + fieldset: IER + - name: CR + description: control register + byte_offset: 8 + fieldset: CR + - name: CFGR + description: configuration register + byte_offset: 12 + fieldset: CFGR + - name: SMPR1 + description: sample time register 1 + byte_offset: 20 + fieldset: SMPR1 + - name: SMPR2 + description: sample time register 2 + byte_offset: 24 + fieldset: SMPR2 + - name: TR1 + description: watchdog threshold register 1 + byte_offset: 32 + fieldset: TR1 + - name: TR2 + description: watchdog threshold register + byte_offset: 36 + fieldset: TR2 + - name: TR3 + description: watchdog threshold register 3 + byte_offset: 40 + fieldset: TR3 + - name: SQR1 + description: regular sequence register 1 + byte_offset: 48 + fieldset: SQR1 + - name: SQR2 + description: regular sequence register 2 + byte_offset: 52 + fieldset: SQR2 + - name: SQR3 + description: regular sequence register 3 + byte_offset: 56 + fieldset: SQR3 + - name: SQR4 + description: regular sequence register 4 + byte_offset: 60 + fieldset: SQR4 + - name: DR + description: regular Data Register + byte_offset: 64 + access: Read + fieldset: DR + - name: JSQR + description: injected sequence register + byte_offset: 76 + fieldset: JSQR + - name: OFR + description: offset register X + byte_offset: 96 + fieldset: OFR + array: + len: 4 + stride: 4 + - name: JDR + description: injected data register X + byte_offset: 128 + access: Read + fieldset: JDR + array: + len: 4 + stride: 4 + - name: AWDCR + description: "Analog Watchdog X Configuration\r Register" + byte_offset: 160 + fieldset: AWDCR + array: + len: 2 + stride: 4 + - name: DIFSEL + description: "Differential Mode Selection Register\r 2" + byte_offset: 176 + fieldset: DIFSEL + - name: CALFACT + description: Calibration Factors + byte_offset: 180 + fieldset: CALFACT +fieldset/AWDCR: + description: "Analog Watchdog 2 Configuration\r Register" + fields: + - name: AWD2CH0 + description: AWD2CH + bit_offset: 1 + bit_size: 1 + array: + len: 17 + stride: 1 +fieldset/CALFACT: + description: Calibration Factors + fields: + - name: CALFACT_S + description: CALFACT_S + bit_offset: 0 + bit_size: 7 + - name: CALFACT_D + description: CALFACT_D + bit_offset: 16 + bit_size: 7 +fieldset/CFGR: + description: configuration register + fields: + - name: DMAEN + description: Direct memory access enable + bit_offset: 0 + bit_size: 1 + - name: DMACFG + description: Direct memory access configuration + bit_offset: 1 + bit_size: 1 + - name: RES + description: Data resolution + bit_offset: 3 + bit_size: 2 + enum: RES + - name: ALIGN + description: Data alignment + bit_offset: 5 + bit_size: 1 + enum: ALIGN + - name: EXTSEL + description: External trigger selection for regular group + bit_offset: 6 + bit_size: 4 + enum: EXTSEL + - name: EXTEN + description: External trigger enable and polarity selection for regular channels + bit_offset: 10 + bit_size: 2 + enum: EXTEN + - name: OVRMOD + description: Overrun Mode + bit_offset: 12 + bit_size: 1 + - name: CONT + description: Single / continuous conversion mode for regular conversions + bit_offset: 13 + bit_size: 1 + - name: AUTDLY + description: Delayed conversion mode + bit_offset: 14 + bit_size: 1 + - name: DISCEN + description: Discontinuous mode for regular channels + bit_offset: 16 + bit_size: 1 + - name: DISCNUM + description: Discontinuous mode channel count + bit_offset: 17 + bit_size: 3 + - name: JDISCEN + description: Discontinuous mode on injected channels + bit_offset: 20 + bit_size: 1 + - name: JQM + description: JSQR queue mode + bit_offset: 21 + bit_size: 1 + enum: JQM + - name: AWD1SGL + description: Enable the watchdog 1 on a single channel or on all channels + bit_offset: 22 + bit_size: 1 + enum: AWD1SGL + - name: AWD1EN + description: Analog watchdog 1 enable on regular channels + bit_offset: 23 + bit_size: 1 + - name: JAWD1EN + description: Analog watchdog 1 enable on injected channels + bit_offset: 24 + bit_size: 1 + - name: JAUTO + description: Automatic injected group conversion + bit_offset: 25 + bit_size: 1 + - name: AWD1CH + description: Analog watchdog 1 channel selection + bit_offset: 26 + bit_size: 5 +fieldset/CR: + description: control register + fields: + - name: ADEN + description: ADC enable control + bit_offset: 0 + bit_size: 1 + - name: ADDIS + description: ADC disable command + bit_offset: 1 + bit_size: 1 + - name: ADSTART + description: ADC start of regular conversion + bit_offset: 2 + bit_size: 1 + - name: JADSTART + description: ADC start of injected conversion + bit_offset: 3 + bit_size: 1 + - name: ADSTP + description: ADC stop of regular conversion command + bit_offset: 4 + bit_size: 1 + - name: JADSTP + description: ADC stop of injected conversion command + bit_offset: 5 + bit_size: 1 + - name: ADVREGEN + description: ADC voltage regulator enable + bit_offset: 28 + bit_size: 2 + enum: ADVREGEN + - name: ADCALDIF + description: Differential mode for calibration + bit_offset: 30 + bit_size: 1 + - name: ADCAL + description: ADC calibration + bit_offset: 31 + bit_size: 1 +fieldset/DIFSEL: + description: "Differential Mode Selection Register\r 2" + fields: + - name: DIFSEL_10 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 1 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_11 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 2 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_12 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 3 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_13 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 4 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_14 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 5 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_15 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 6 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_16 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 7 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_17 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 8 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_18 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 9 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_19 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 10 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_110 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 11 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_111 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 12 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_112 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 13 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_113 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 14 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_114 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 15 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_115 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 16 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_116 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 17 + bit_size: 1 + enum: DIFSEL_10 + - name: DIFSEL_117 + description: "Differential mode for channels 15 to\r 1" + bit_offset: 18 + bit_size: 1 + enum: DIFSEL_10 +fieldset/DR: + description: regular Data Register + fields: + - name: RDATA + description: Regular data + bit_offset: 0 + bit_size: 16 +fieldset/IER: + description: interrupt enable register + fields: + - name: ADRDYIE + description: ADC ready interrupt enable + bit_offset: 0 + bit_size: 1 + - name: EOSMPIE + description: End of sampling flag interrupt enable for regular conversions + bit_offset: 1 + bit_size: 1 + - name: EOCIE + description: End of regular conversion interrupt enable + bit_offset: 2 + bit_size: 1 + - name: EOSIE + description: End of regular sequence of conversions interrupt enable + bit_offset: 3 + bit_size: 1 + - name: OVRIE + description: Overrun interrupt enable + bit_offset: 4 + bit_size: 1 + - name: JEOCIE + description: End of injected conversion interrupt enable + bit_offset: 5 + bit_size: 1 + - name: JEOSIE + description: End of injected sequence of conversions interrupt enable + bit_offset: 6 + bit_size: 1 + - name: AWDIE + description: Analog watchdog X interrupt enable + bit_offset: 7 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: JQOVFIE + description: Injected context queue overflow interrupt enable + bit_offset: 10 + bit_size: 1 +fieldset/ISR: + description: interrupt and status register + fields: + - name: ADRDY + description: ADC Ready + bit_offset: 0 + bit_size: 1 + - name: EOSMP + description: End of sampling flag + bit_offset: 1 + bit_size: 1 + - name: EOC + description: End of conversion flag + bit_offset: 2 + bit_size: 1 + - name: EOS + description: End of regular sequence flag + bit_offset: 3 + bit_size: 1 + - name: OVR + description: ADC overrun + bit_offset: 4 + bit_size: 1 + - name: JEOC + description: Injected channel end of conversion flag + bit_offset: 5 + bit_size: 1 + - name: JEOS + description: Injected channel end of sequence flag + bit_offset: 6 + bit_size: 1 + - name: AWD + description: Analog watchdog flag + bit_offset: 7 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: JQOVF + description: Injected context queue overflow + bit_offset: 10 + bit_size: 1 +fieldset/JDR: + description: injected data register 1 + fields: + - name: JDATA + description: Injected data + bit_offset: 0 + bit_size: 16 +fieldset/JSQR: + description: injected sequence register + fields: + - name: JL + description: Injected channel sequence length + bit_offset: 0 + bit_size: 2 + - name: JEXTSEL + description: External Trigger Selection for injected group + bit_offset: 2 + bit_size: 4 + enum: JEXTSEL + - name: JEXTEN + description: External Trigger Enable and Polarity Selection for injected channels + bit_offset: 6 + bit_size: 2 + enum: JEXTEN + - name: JSQ + description: X conversion in the injected sequence + bit_offset: 8 + bit_size: 5 + array: + len: 4 + stride: 6 +fieldset/OFR: + description: offset register 1 + fields: + - name: OFFSET + description: Data offset y for the channel programmed into bits OFFSETy_CH + bit_offset: 0 + bit_size: 12 + - name: CH + description: Data offset y for the channel programmed into bits OFFSETy_CH + bit_offset: 26 + bit_size: 5 + - name: EN + description: Offset y Enable + bit_offset: 31 + bit_size: 1 +fieldset/SMPR1: + description: sample time register 1 + fields: + - name: SMP + description: Channel x sampling time selection + bit_offset: 3 + bit_size: 3 + enum: SMP + array: + len: 9 + stride: 3 +fieldset/SMPR2: + description: sample time register 2 + fields: + - name: SMP + description: Channel x sampling time selection + bit_offset: 0 + bit_size: 3 + enum: SMP + array: + len: 9 + stride: 3 +fieldset/SQR1: + description: regular sequence register 1 + fields: + - name: L + description: Regular channel sequence length + bit_offset: 0 + bit_size: 4 + - name: SQ + description: X conversion in regular sequence + bit_offset: 6 + bit_size: 5 + array: + len: 4 + stride: 6 +fieldset/SQR2: + description: regular sequence register 2 + fields: + - name: SQ + description: X conversion in regular sequence + bit_offset: 0 + bit_size: 5 + array: + len: 5 + stride: 6 +fieldset/SQR3: + description: regular sequence register 3 + fields: + - name: SQ + description: X conversion in regular sequence + bit_offset: 0 + bit_size: 5 + array: + len: 5 + stride: 6 +fieldset/SQR4: + description: regular sequence register 4 + fields: + - name: SQ + description: X conversion in regular sequence + bit_offset: 0 + bit_size: 5 + array: + len: 2 + stride: 6 +fieldset/TR1: + description: watchdog threshold register 1 + fields: + - name: LT1 + description: LT1 + bit_offset: 0 + bit_size: 12 + - name: HT1 + description: HT1 + bit_offset: 16 + bit_size: 12 +fieldset/TR2: + description: watchdog threshold register + fields: + - name: LT2 + description: LT2 + bit_offset: 0 + bit_size: 8 + - name: HT2 + description: HT2 + bit_offset: 16 + bit_size: 8 +fieldset/TR3: + description: watchdog threshold register 3 + fields: + - name: LT3 + description: LT3 + bit_offset: 0 + bit_size: 8 + - name: HT3 + description: HT3 + bit_offset: 16 + bit_size: 8 +enum/ADVREGEN: + bit_size: 2 + variants: + - name: Intermediate + description: Intermediate state required when moving the ADC voltage regulator between states + value: 0 + - name: Enabled + description: ADC voltage regulator enabled + value: 1 + - name: Disabled + description: ADC voltage regulator disabled + value: 2 +enum/ALIGN: + bit_size: 1 + variants: + - name: Right + description: Right alignment + value: 0 + - name: Left + description: Left alignment + value: 1 +enum/AWD1SGL: + bit_size: 1 + variants: + - name: All + description: Analog watchdog 1 enabled on all channels + value: 0 + - name: Single + description: Analog watchdog 1 enabled on single channel selected in AWD1CH + value: 1 +enum/DIFSEL_10: + bit_size: 1 + variants: + - name: SingleEnded + description: Input channel is configured in single-ended mode + value: 0 + - name: Differential + description: Input channel is configured in differential mode + value: 1 +enum/EXTEN: + bit_size: 2 + variants: + - name: Disabled + description: Trigger detection disabled + value: 0 + - name: RisingEdge + description: Trigger detection on the rising edge + value: 1 + - name: FallingEdge + description: Trigger detection on the falling edge + value: 2 + - name: BothEdges + description: Trigger detection on both the rising and falling edges + value: 3 +enum/EXTSEL: + bit_size: 4 + variants: + - name: TIM1_CC1 + description: Timer 1 CC1 event + value: 0 + - name: TIM1_CC2 + description: Timer 1 CC2 event + value: 1 + - name: TIM1_CC3 + description: Timer 1 CC3 event + value: 2 + - name: TIM2_CC2 + description: Timer 2 CC2 event + value: 3 + - name: TIM3_TRGO + description: Timer 3 TRGO event + value: 4 + - name: EXTI11 + description: EXTI line 11 + value: 6 + - name: HRTIM_ADCTRG1 + description: HRTIM_ADCTRG1 event + value: 7 + - name: HRTIM_ADCTRG3 + description: HRTIM_ADCTRG3 event + value: 8 + - name: TIM1_TRGO + description: Timer 1 TRGO event + value: 9 + - name: TIM1_TRGO2 + description: Timer 1 TRGO2 event + value: 10 + - name: TIM2_TRGO + description: Timer 2 TRGO event + value: 11 + - name: TIM6_TRGO + description: Timer 6 TRGO event + value: 13 + - name: TIM15_TRGO + description: Timer 15 TRGO event + value: 14 + - name: TIM3_CC4 + description: Timer 3 CC4 event + value: 15 +enum/JEXTEN: + bit_size: 2 + variants: + - name: Disabled + description: Trigger detection disabled + value: 0 + - name: RisingEdge + description: Trigger detection on the rising edge + value: 1 + - name: FallingEdge + description: Trigger detection on the falling edge + value: 2 + - name: BothEdges + description: Trigger detection on both the rising and falling edges + value: 3 +enum/JEXTSEL: + bit_size: 4 + variants: + - name: TIM1_TRGO + description: Timer 1 TRGO event + value: 0 + - name: TIM1_CC4 + description: Timer 1 CC4 event + value: 1 + - name: TIM2_TRGO + description: Timer 2 TRGO event + value: 2 + - name: TIM2_CC1 + description: Timer 2 CC1 event + value: 3 + - name: TIM3_CC4 + description: Timer 3 CC4 event + value: 4 + - name: EXTI15 + description: EXTI line 15 + value: 6 + - name: TIM1_TRGO2 + description: Timer 1 TRGO2 event + value: 8 + - name: HRTIM_ADCTRG2 + description: HRTIM_ADCTRG2 event + value: 9 + - name: HRTIM_ADCTRG4 + description: HRTIM_ADCTRG4 event + value: 10 + - name: TIM3_CC3 + description: Timer 3 CC3 event + value: 11 + - name: TIM3_TRGO + description: Timer 3 TRGO event + value: 12 + - name: TIM3_CC1 + description: Timer 3 CC1 event + value: 13 + - name: TIM6_TRGO + description: Timer 6 TRGO event + value: 14 + - name: TIM15_TRGO + description: Timer 15 TRGO event + value: 15 +enum/JQM: + bit_size: 1 + variants: + - name: Mode0 + description: "JSQR Mode 0: Queue maintains the last written configuration into JSQR" + value: 0 + - name: Mode1 + description: "JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence" + value: 1 +enum/RES: + bit_size: 2 + variants: + - name: Bits12 + description: 12-bit + value: 0 + - name: Bits10 + description: 10-bit + value: 1 + - name: Bits8 + description: 8-bit + value: 2 + - name: Bits6 + description: 6-bit + value: 3 +enum/SMP: + bit_size: 3 + variants: + - name: Cycles1_5 + description: 1.5 ADC clock cycles + value: 0 + - name: Cycles2_5 + description: 2.5 ADC clock cycles + value: 1 + - name: Cycles4_5 + description: 4.5 ADC clock cycles + value: 2 + - name: Cycles7_5 + description: 7.5 ADC clock cycles + value: 3 + - name: Cycles19_5 + description: 19.5 ADC clock cycles + value: 4 + - name: Cycles61_5 + description: 61.5 ADC clock cycles + value: 5 + - name: Cycles181_5 + description: 181.5 ADC clock cycles + value: 6 + - name: Cycles601_5 + description: 601.5 ADC clock cycles + value: 7 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index fe54002..a027c22 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -169,6 +169,7 @@ impl PeriMatcher { (".*:DAC:dacif_v3_0", ("dac", "v3", "DAC")), (".*:DAC:F3_dacif_v1_1", ("dac", "v1", "DAC")), (".*:ADC:aditf_v2_5F1", ("adc", "f1", "ADC")), + (".*:ADC:aditf5_v1_1", ("adc", "f3", "ADC")), (".*:ADC:aditf4_v1_1", ("adc", "v1", "ADC")), (".*:ADC:aditf2_v1_1", ("adc", "v2", "ADC")), (".*:ADC:aditf5_v2_0", ("adc", "v3", "ADC")),