remove DSISEL from other register ymls where it is not present

data/registers/rcc_h7.yaml

@@ -3073,9 +3073,10 @@ fieldset/D1CCIPR:
     bit_size: 2
     enum: FMCSEL
   - name: DSISEL
-    description: kernel clock source selection
+    description: DSI clock source selection (not available on all chips)
     bit_offset: 8
     bit_size: 1
+    enum: DSISEL
   - name: SDMMCSEL
     description: SDMMC kernel clock source selection
     bit_offset: 16
@@ -3550,6 +3551,15 @@ enum/DFSDMSEL:
   - name: SYS
     description: System clock selected as peripheral clock
     value: 1
+enum/DSISEL:
+  bit_size: 1
+  variants:
+  - name: DSI_PHY
+    description: DSI-PHY used as DSI byte lane clock source (usual case)
+    value: 0
+  - name: PLL2_Q
+    description: PLL2_Q used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)
+    value: 1
 enum/FDCANSEL:
   bit_size: 2
   variants:

data/registers/rcc_h7ab.yaml

@@ -2018,10 +2018,6 @@ fieldset/D1CCIPR:
     bit_offset: 4
     bit_size: 2
     enum: FMCSEL
-  - name: DSISEL
-    description: kernel clock source selection
-    bit_offset: 8
-    bit_size: 1
   - name: SDMMCSEL
     description: SDMMC kernel clock source selection
     bit_offset: 16

data/registers/rcc_h7rm0433.yaml

@@ -3055,10 +3055,6 @@ fieldset/D1CCIPR:
     bit_offset: 4
     bit_size: 2
     enum: FMCSEL
-  - name: DSISEL
-    description: kernel clock source selection
-    bit_offset: 8
-    bit_size: 1
   - name: SDMMCSEL
     description: SDMMC kernel clock source selection
     bit_offset: 16

stm32-data-gen/src/rcc.rs

@@ -106,10 +106,10 @@ impl ParsedRccs {
             "AUDIOCLK",
             "PER",
             "CLK48",
+            "DSI_PHY",
             // TODO: variants to cleanup
             "AFIF",
             "HSI_HSE",
-            "DSI_PHY",
             "HSI_Div488",
             "SAI1_EXTCLK",
             "SAI2_EXTCLK",
@@ -120,7 +120,6 @@ impl ParsedRccs {
             "DAC_HOLD_2",
             "RTCCLK",
             "RTC_WKUP",
-            "DSIPHY",
             "ICLK",
             "DCLK",
             "I2S1",