From 95ff92f362817d30e0460eebed8e3597a4c804c1 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Mon, 8 Apr 2024 14:10:32 +0200
Subject: [PATCH] remove DSISEL from other register ymls where it is not
 present

---
 data/registers/rcc_h7.yaml       | 12 +++++++++++-
 data/registers/rcc_h7ab.yaml     |  4 ----
 data/registers/rcc_h7rm0433.yaml |  4 ----
 stm32-data-gen/src/rcc.rs        |  3 +--
 4 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml
index d3d5b62..69a4d94 100644
--- a/data/registers/rcc_h7.yaml
+++ b/data/registers/rcc_h7.yaml
@@ -3073,9 +3073,10 @@ fieldset/D1CCIPR:
     bit_size: 2
     enum: FMCSEL
   - name: DSISEL
-    description: kernel clock source selection
+    description: DSI clock source selection (not available on all chips)
     bit_offset: 8
     bit_size: 1
+    enum: DSISEL
   - name: SDMMCSEL
     description: SDMMC kernel clock source selection
     bit_offset: 16
@@ -3550,6 +3551,15 @@ enum/DFSDMSEL:
   - name: SYS
     description: System clock selected as peripheral clock
     value: 1
+enum/DSISEL:
+  bit_size: 1
+  variants:
+  - name: DSI_PHY
+    description: DSI-PHY used as DSI byte lane clock source (usual case)
+    value: 0
+  - name: PLL2_Q
+    description: PLL2_Q used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)
+    value: 1
 enum/FDCANSEL:
   bit_size: 2
   variants:
diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml
index 554992a..aab77da 100644
--- a/data/registers/rcc_h7ab.yaml
+++ b/data/registers/rcc_h7ab.yaml
@@ -2018,10 +2018,6 @@ fieldset/D1CCIPR:
     bit_offset: 4
     bit_size: 2
     enum: FMCSEL
-  - name: DSISEL
-    description: kernel clock source selection
-    bit_offset: 8
-    bit_size: 1
   - name: SDMMCSEL
     description: SDMMC kernel clock source selection
     bit_offset: 16
diff --git a/data/registers/rcc_h7rm0433.yaml b/data/registers/rcc_h7rm0433.yaml
index 90549fa..22da980 100644
--- a/data/registers/rcc_h7rm0433.yaml
+++ b/data/registers/rcc_h7rm0433.yaml
@@ -3055,10 +3055,6 @@ fieldset/D1CCIPR:
     bit_offset: 4
     bit_size: 2
     enum: FMCSEL
-  - name: DSISEL
-    description: kernel clock source selection
-    bit_offset: 8
-    bit_size: 1
   - name: SDMMCSEL
     description: SDMMC kernel clock source selection
     bit_offset: 16
diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs
index 740fb3d..32b63a3 100644
--- a/stm32-data-gen/src/rcc.rs
+++ b/stm32-data-gen/src/rcc.rs
@@ -106,10 +106,10 @@ impl ParsedRccs {
             "AUDIOCLK",
             "PER",
             "CLK48",
+            "DSI_PHY",
             // TODO: variants to cleanup
             "AFIF",
             "HSI_HSE",
-            "DSI_PHY",
             "HSI_Div488",
             "SAI1_EXTCLK",
             "SAI2_EXTCLK",
@@ -120,7 +120,6 @@ impl ParsedRccs {
             "DAC_HOLD_2",
             "RTCCLK",
             "RTC_WKUP",
-            "DSIPHY",
             "ICLK",
             "DCLK",
             "I2S1",