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Merge pull request #235 from dreilly1982/fix-rcc-f3

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rework f3 series rcc take 2
This commit is contained in:
Dario Nieuwenhuis 2023-08-10 10:27:16 +00:00 committed by GitHub
commit 7eddb78e70
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5 changed files with 1925 additions and 87 deletions
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613
data/registers/adc_f3_v2.yaml Normal file
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@ -0,0 +1,613 @@
---
block/ADC:
description: Analog-to-Digital Converter
items:
- name: SR
description: status register
byte_offset: 0
fieldset: SR
- name: CR1
description: control register 1
byte_offset: 4
fieldset: CR1
- name: CR2
description: control register 2
byte_offset: 8
fieldset: CR2
- name: SMPR1
description: sample time register 1
byte_offset: 12
fieldset: SMPR1
- name: SMPR2
description: sample time register 2
byte_offset: 16
fieldset: SMPR2
- name: JOFR1
description: injected channel data offset register 1
byte_offset: 20
fieldset: JOFR1
- name: JOFR2
description: injected channel data offset register 2
byte_offset: 24
fieldset: JOFR2
- name: JOFR3
description: injected channel data offset register 3
byte_offset: 28
fieldset: JOFR3
- name: JOFR4
description: injected channel data offset register 4
byte_offset: 32
fieldset: JOFR4
- name: HTR
description: watchdog higher threshold register
byte_offset: 36
fieldset: HTR
- name: LTR
description: watchdog lower threshold register
byte_offset: 40
fieldset: LTR
- name: SQR1
description: regular sequence register 1
byte_offset: 44
fieldset: SQR1
- name: SQR2
description: regular sequence register 2
byte_offset: 48
fieldset: SQR2
- name: SQR3
description: regular sequence register 3
byte_offset: 52
fieldset: SQR3
- name: JSQR
description: injected sequence register
byte_offset: 56
fieldset: JSQR
- name: JDR1
description: injected data register 1
byte_offset: 60
fieldset: JDR1
access: Read
- name: JDR2
description: injected data register 2
byte_offset: 64
fieldset: JDR2
access: Read
- name: JDR3
description: injected data register 3
byte_offset: 68
fieldset: JDR3
access: Read
- name: JDR4
description: injected data register 4
byte_offset: 72
fieldset: JDR4
access: Read
- name: DR
description: regular data register
byte_offset: 76
fieldset: DR
access: Read
fieldset/SR:
description: status register
fields:
- name: AWD
description: analog watchdog flag
bit_offset: 0
bit_size: 1
- name: EOC
description: end of conversion
bit_offset: 1
bit_size: 1
- name: JEOC
description: injected channel end of conversion
bit_offset: 2
bit_size: 1
- name: JSTRT
description: injected channel start flag
bit_offset: 3
bit_size: 1
- name: STRT
description: regular channel start flag
bit_offset: 4
bit_size: 1
- name: OVR
description: overrun
bit_offset: 5
bit_size: 1
fieldset/CR1:
description: control register 1
fields:
- name: AWDCH
description: analog watchdog channel select bits
bit_offset: 0
bit_size: 5
- name: EOCIE
description: interrupt enable for EOC
bit_offset: 5
bit_size: 1
- name: AWDIE
description: analog watchdog interrupt enable
bit_offset: 6
bit_size: 1
- name: JEOCIE
description: interrupt enable for injected channels
bit_offset: 7
bit_size: 1
- name: SCAN
description: scan mode
bit_offset: 8
bit_size: 1
- name: AWDSGL
description: enable the watchdog on a single channel in scan mode
bit_offset: 9
bit_size: 1
- name: JAUTO
description: automatic injected group conversion
bit_offset: 10
bit_size: 1
- name: DISCEN
description: discontinuous mode on regular channels
bit_offset: 11
bit_size: 1
- name: JDISCEN
description: discontinuous mode on injected channels
bit_offset: 12
bit_size: 1
- name: DISCNUM
description: discontinuous mode channel count
bit_offset: 13
bit_size: 3
enum: DISCNUM
- name: JAWDEN
description: analog watchdog enable on injected channels
bit_offset: 22
bit_size: 1
- name: AWDEN
description: analog watchdog enable on regular channels
bit_offset: 23
bit_size: 1
fieldset/CR2:
description: control register 2
fields:
- name: ADON
description: A/D converter ON / OFF
bit_offset: 0
bit_size: 1
- name: CONT
description: continuous conversion
bit_offset: 1
bit_size: 1
- name: CAL
description: A/D calibration
bit_offset: 2
bit_size: 1
- name: RSTCAL
description: reset calibration
bit_offset: 3
bit_size: 1
- name: DMA
description: DMA disable selection (for single ADC mode)
bit_offset: 8
bit_size: 1
- name: ALIGN
description: data alignment
bit_offset: 11
bit_size: 1
- name: JEXTSEL
description: external event select for injected group
bit_offset: 12
bit_size: 3
enum: JEXTSEL
- name: JEXTTRIG
description: external trigger conversion mode for injected channels
bit_offset: 15
bit_size: 1
- name: EXTSEL
description: external event select for regular group
bit_offset: 17
bit_size: 3
enum: EXTSEL
- name: EXTTRIG
description: external trigger conversion mode for regular channels
bit_offset: 20
bit_size: 1
- name: JSWSTART
description: start conversion of injected channels
bit_offset: 21
bit_size: 1
- name: SWSTART
description: start conversion of regular channels
bit_offset: 22
bit_size: 1
- name: TSVREFE
description: temperature sensor and VREFINT enable
bit_offset: 23
bit_size: 1
fieldset/SMPR1:
description: sample time register 1
fields:
- name: SMP10
description: channel 10 sampling time selection
bit_offset: 0
bit_size: 3
enum: SAMPLE_TIME
- name: SMP11
description: channel 11 sampling time selection
bit_offset: 3
bit_size: 3
enum: SAMPLE_TIME
- name: SMP12
description: channel 12 sampling time selection
bit_offset: 6
bit_size: 3
enum: SAMPLE_TIME
- name: SMP13
description: channel 13 sampling time selection
bit_offset: 9
bit_size: 3
enum: SAMPLE_TIME
- name: SMP14
description: channel 14 sampling time selection
bit_offset: 12
bit_size: 3
enum: SAMPLE_TIME
- name: SMP15
description: channel 15 sampling time selection
bit_offset: 15
bit_size: 3
enum: SAMPLE_TIME
- name: SMP16
description: channel 16 sampling time selection
bit_offset: 18
bit_size: 3
enum: SAMPLE_TIME
- name: SMP17
description: channel 17 sampling time selection
bit_offset: 21
bit_size: 3
enum: SAMPLE_TIME
- name: SMP18
description: channel 18 sampling time selection
bit_offset: 24
bit_size: 3
enum: SAMPLE_TIME
fieldset/SMPR2:
description: sample time register 2
fields:
- name: SMP0
description: channel 0 sampling time selection
bit_offset: 0
bit_size: 3
enum: SAMPLE_TIME
- name: SMP1
description: channel 1 sampling time selection
bit_offset: 3
bit_size: 3
enum: SAMPLE_TIME
- name: SMP2
description: channel 2 sampling time selection
bit_offset: 6
bit_size: 3
enum: SAMPLE_TIME
- name: SMP3
description: channel 3 sampling time selection
bit_offset: 9
bit_size: 3
enum: SAMPLE_TIME
- name: SMP4
description: channel 4 sampling time selection
bit_offset: 12
bit_size: 3
enum: SAMPLE_TIME
- name: SMP5
description: channel 5 sampling time selection
bit_offset: 15
bit_size: 3
enum: SAMPLE_TIME
- name: SMP6
description: channel 6 sampling time selection
bit_offset: 18
bit_size: 3
enum: SAMPLE_TIME
- name: SMP7
description: channel 7 sampling time selection
bit_offset: 21
bit_size: 3
enum: SAMPLE_TIME
- name: SMP8
description: channel 8 sampling time selection
bit_offset: 24
bit_size: 3
enum: SAMPLE_TIME
- name: SMP9
description: channel 9 sampling time selection
bit_offset: 27
bit_size: 3
enum: SAMPLE_TIME
fieldset/JOFR1:
description: injected channel data offset register 1
fields:
- name: JOFFSET1
description: data offset for injected channel 1
bit_offset: 0
bit_size: 12
fieldset/JOFR2:
description: injected channel data offset register 2
fields:
- name: JOFFSET2
description: data offset for injected channel 2
bit_offset: 0
bit_size: 12
fieldset/JOFR3:
description: injected channel data offset register 3
fields:
- name: JOFFSET3
description: data offset for injected channel 3
bit_offset: 0
bit_size: 12
fieldset/JOFR4:
description: injected channel data offset register 4
fields:
- name: JOFFSET4
description: data offset for injected channel 4
bit_offset: 0
bit_size: 12
fieldset/HTR:
description: watchdog higher threshold register
fields:
- name: HT
description: Analog watchdog high threshold
bit_offset: 0
bit_size: 12
fieldset/LTR:
description: watchdog lower threshold register
fields:
- name: LT
description: Analog watchdog low threshold
bit_offset: 0
bit_size: 12
fieldset/SQR1:
description: regular sequence register 1
fields:
- name: SQ13
description: 13th conversion in regular sequence
bit_offset: 0
bit_size: 5
- name: SQ14
description: 14th conversion in regular sequence
bit_offset: 5
bit_size: 5
- name: SQ15
description: 15th conversion in regular sequence
bit_offset: 10
bit_size: 5
- name: SQ16
description: 16th conversion in regular sequence
bit_offset: 15
bit_size: 5
- name: L
description: regular channel sequence length
bit_offset: 20
bit_size: 4
fieldset/SQR2:
description: regular sequence register 2
fields:
- name: SQ7
description: 7th conversion in regular sequence
bit_offset: 0
bit_size: 5
- name: SQ8
description: 8th conversion in regular sequence
bit_offset: 5
bit_size: 5
- name: SQ9
description: 9th conversion in regular sequence
bit_offset: 10
bit_size: 5
- name: SQ10
description: 10th conversion in regular sequence
bit_offset: 15
bit_size: 5
- name: SQ11
description: 11th conversion in regular sequence
bit_offset: 20
bit_size: 5
- name: SQ12
description: 12th conversion in regular sequence
bit_offset: 25
bit_size: 5
fieldset/SQR3:
description: regular sequence register 3
fields:
- name: SQ1
description: 1st conversion in regular sequence
bit_offset: 0
bit_size: 5
- name: SQ2
description: 2nd conversion in regular sequence
bit_offset: 5
bit_size: 5
- name: SQ3
description: 3rd conversion in regular sequence
bit_offset: 10
bit_size: 5
- name: SQ4
description: 4th conversion in regular sequence
bit_offset: 15
bit_size: 5
- name: SQ5
description: 5th conversion in regular sequence
bit_offset: 20
bit_size: 5
- name: SQ6
description: 6th conversion in regular sequence
bit_offset: 25
bit_size: 5
fieldset/JSQR:
description: injected sequence register
fields:
- name: JSQ1
description: 1st conversion in injected sequence
bit_offset: 0
bit_size: 5
- name: JSQ2
description: 2nd conversion in injected sequence
bit_offset: 5
bit_size: 5
- name: JSQ3
description: 3rd conversion in injected sequence
bit_offset: 10
bit_size: 5
- name: JSQ4
description: 4th conversion in injected sequence
bit_offset: 15
bit_size: 5
- name: JL
description: injected sequence length
bit_offset: 20
bit_size: 2
fieldset/JDR1:
description: injected data register 1
fields:
- name: JDATA1
description: Injected data
bit_offset: 0
bit_size: 16
fieldset/JDR2:
description: injected data register 2
fields:
- name: JDATA2
description: Injected data
bit_offset: 0
bit_size: 16
fieldset/JDR3:
description: injected data register 3
fields:
- name: JDATA3
description: Injected data
bit_offset: 0
bit_size: 16
fieldset/JDR4:
description: injected data register 4
fields:
- name: JDATA4
description: Injected data
bit_offset: 0
bit_size: 16
fieldset/DR:
description: regular data register
fields:
- name: DATA
description: Regular data
bit_offset: 0
bit_size: 16
enum/DISCNUM:
bit_size: 3
variants:
- name: DISCNUM_1
description: 1 conversions are discontinued and the conversion is carried out on one channel
value: 0
- name: DISCNUM_2
description: 2 conversion is discontinued and the conversions are carried out on 2 channels
value: 1
- name: DISCNUM_3
description: 3 conversions are discontinued and the conversions are carried out on 3 channels
value: 2
- name: DISCNUM_4
description: 4 conversions are discontinued and the conversions are carried out on 4 channels
value: 3
- name: DISCNUM_5
description: 5 conversions are discontinued and the conversions are carried out on 5 channels
value: 4
- name: DISCNUM_6
description: 6 conversions are discontinued and the conversions are carried out on 6 channels
value: 5
- name: DISCNUM_7
description: 7 conversions are discontinued and the conversions are carried out on 7 channels
value: 6
- name: DISCNUM_8
description: 8 conversions are discontinued and the conversions are carried out on 8 channels
value: 7
enum/JEXTSEL:
bit_size: 3
variants:
- name: TIM19_CC1
description: Timer 19 CC1 event
value: 0
- name: TIM19_CC2
description: Timer 19 CC2 event
value: 1
- name: TIM2_TRGO
description: Timer 2 TRGO event
value: 2
- name: TIM2_CC1
description: Timer 2 CC1 event
value: 3
- name: TIM3_CC4
description: Timer 3 CC4 event
value: 4
- name: TIM4_TRGO
description: Timer 4 TRGO event
value: 5
- name: EXTI_LINE15
description: External interrupt line 15
value: 6
- name: JSWSTART
description: JSWSTART bit
value: 7
enum/EXTSEL:
bit_size: 3
variants:
- name: TIM19_TRGO
description: Timer 19 TRGO event
value: 0
- name: TIM19_CC3
description: Timer 19 CC3 event
value: 1
- name: TIM19_CC4
description: Timer 19 CC4 event
value: 2
- name: TIM2_CC2
description: Timer 2 CC2 event
value: 3
- name: TIM3_TRGO
description: Timer 3 TRGO event
value: 4
- name: TIM4_CC4
description: Timer 4 CC4 event
value: 5
- name: EXTI_LINE11
description: External interrupt line 11
value: 6
- name: SWSTART
description: SWSTART bit
value: 7
enum/SAMPLE_TIME:
bit_size: 3
variants:
- name: Cycles1_5
description: 1.5 ADC clock cycles
value: 0
- name: Cycles7_5
description: 7.5 ADC clock cycles
value: 1
- name: Cycles13_5
description: 13.5 ADC clock cycles
value: 2
- name: Cycles28_5
description: 28.5 ADC clock cycles
value: 3
- name: Cycles41_5
description: 41.5 ADC clock cycles
value: 4
- name: Cycles55_5
description: 55.5 ADC clock cycles
value: 5
- name: Cycles71_5
description: 71.5 ADC clock cycles
value: 6
- name: Cycles239_5
description: 239.5 ADC clock cycles
value: 7

90
data/registers/rcc_f3.yaml
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@ -121,10 +121,6 @@ fieldset/AHBENR:
description: ADC1 and ADC2 clock enable
bit_offset: 28
bit_size: 1
- name: ADC1EN
description: ADC 1
bit_offset: 28
bit_size: 1
- name: ADC34EN
description: ADC3 and ADC4 clock enable
bit_offset: 29
@ -176,10 +172,6 @@ fieldset/AHBRSTR:
description: ADC1 and ADC2 reset
bit_offset: 28
bit_size: 1
- name: ADC1RST
description: ADC1 reset
bit_offset: 28
bit_size: 1
- name: ADC34RST
description: ADC3 and ADC4 reset
bit_offset: 29
@ -199,10 +191,6 @@ fieldset/APB1ENR:
description: Timer 4 clock enable
bit_offset: 2
bit_size: 1
- name: TIM5EN
description: Timer 5 clock enable
bit_offset: 3
bit_size: 1
- name: TIM6EN
description: Timer 6 clock enable
bit_offset: 4
@ -211,22 +199,6 @@ fieldset/APB1ENR:
description: Timer 7 clock enable
bit_offset: 5
bit_size: 1
- name: TIM12EN
description: Timer 12 clock enable
bit_offset: 6
bit_size: 1
- name: TIM13EN
description: Timer 13 clock enable
bit_offset: 7
bit_size: 1
- name: TIM14EN
description: Timer 14 clock enable
bit_offset: 8
bit_size: 1
- name: TIM18EN
description: Timer 18 clock enable
bit_offset: 9
bit_size: 1
- name: WWDGEN
description: Window watchdog clock enable
bit_offset: 11
@ -283,10 +255,6 @@ fieldset/APB1ENR:
description: DAC interface clock enable
bit_offset: 29
bit_size: 1
- name: CECEN
description: HDMI CEC interface clock enable
bit_offset: 30
bit_size: 1
- name: I2C3EN
description: I2C3 clock enable
bit_offset: 30
@ -306,10 +274,6 @@ fieldset/APB1RSTR:
description: Timer 14 reset
bit_offset: 2
bit_size: 1
- name: TIM5RST
description: Timer 5 reset
bit_offset: 3
bit_size: 1
- name: TIM6RST
description: Timer 6 reset
bit_offset: 4
@ -318,22 +282,6 @@ fieldset/APB1RSTR:
description: Timer 7 reset
bit_offset: 5
bit_size: 1
- name: TIM12RST
description: Timer 12 reset
bit_offset: 6
bit_size: 1
- name: TIM13RST
description: Timer 13 reset
bit_offset: 7
bit_size: 1
- name: TIM14RST
description: Timer 14 reset
bit_offset: 8
bit_size: 1
- name: TIM18RST
description: Timer 18 reset
bit_offset: 9
bit_size: 1
- name: WWDGRST
description: Window watchdog reset
bit_offset: 11
@ -390,10 +338,6 @@ fieldset/APB1RSTR:
description: DAC interface reset
bit_offset: 29
bit_size: 1
- name: CECRST
description: HDMI CEC reset
bit_offset: 30
bit_size: 1
- name: I2C3RST
description: I2C3 reset
bit_offset: 30
@ -405,10 +349,6 @@ fieldset/APB2ENR:
description: SYSCFG clock enable
bit_offset: 0
bit_size: 1
- name: ADCEN
description: ADC 1 interface clock enable
bit_offset: 9
bit_size: 1
- name: TIM1EN
description: TIM1 Timer clock enable
bit_offset: 11
@ -453,18 +393,6 @@ fieldset/APB2ENR:
description: MCU debug module clock enable
bit_offset: 22
bit_size: 1
- name: SDADC1EN
description: SDADC1 (Sigma Delta ADC 1) clock enable
bit_offset: 24
bit_size: 1
- name: SDADC2EN
description: SDADC2 (Sigma Delta ADC 2) clock enable
bit_offset: 25
bit_size: 1
- name: SDADC3EN
description: SDADC3 (Sigma Delta ADC 3) clock enable
bit_offset: 26
bit_size: 1
- name: HRTIM1EN
description: High Resolution Timer 1 clock enable
bit_offset: 29
@ -476,10 +404,6 @@ fieldset/APB2RSTR:
description: SYSCFG and COMP reset
bit_offset: 0
bit_size: 1
- name: ADCRST
description: ADC interface reset
bit_offset: 9
bit_size: 1
- name: TIM1RST
description: TIM1 timer reset
bit_offset: 11
@ -520,17 +444,9 @@ fieldset/APB2RSTR:
description: TIM20 timer reset
bit_offset: 20
bit_size: 1
- name: SDADC1RST
description: SDADC1 (Sigma delta ADC 1) reset
bit_offset: 24
bit_size: 1
- name: SDADC2RST
description: SDADC2 (Sigma delta ADC 2) reset
bit_offset: 25
bit_size: 1
- name: SDADC3RST
description: SDADC3 (Sigma delta ADC 3) reset
bit_offset: 26
- name: DBGMCURST
description: Debug MCU reset
bit_offset: 22
bit_size: 1
- name: HRTIM1RST
description: High Resolution Timer1 reset

1271
data/registers/rcc_f3_v2.yaml Normal file
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2
stm32-data-gen/src/chips.rs
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@ -171,6 +171,7 @@ impl PeriMatcher {
(".*:DAC:F3_dacif_v1_1", ("dac", "v1", "DAC")),
(".*:ADC:aditf_v2_5F1", ("adc", "f1", "ADC")),
(".*:ADC:aditf5_v1_1", ("adc", "f3", "ADC")),
(".*:ADC:aditf_v2_5", ("adc", "f3_v2", "ADC")),
(".*:ADC:aditf4_v1_1", ("adc", "v1", "ADC")),
(".*:ADC:aditf2_v1_1", ("adc", "v2", "ADC")),
(".*:ADC:aditf5_v2_0", ("adc", "v3", "ADC")),
@ -265,6 +266,7 @@ impl PeriMatcher {
("STM32F10[123].*:RCC:.*", ("rcc", "f1", "RCC")),
("STM32F10[57].*:RCC:.*", ("rcc", "f1cl", "RCC")),
("STM32F2.*:RCC:.*", ("rcc", "f2", "RCC")),
("STM32F37.*:RCC:.*", ("rcc", "f3_v2", "RCC")),
("STM32F3.*:RCC:.*", ("rcc", "f3", "RCC")),
("STM32F410.*:RCC:.*", ("rcc", "f410", "RCC")),
("STM32F4.*:RCC:.*", ("rcc", "f4", "RCC")),

36
stm32-data-gen/src/rcc.rs
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@ -79,6 +79,9 @@ impl PeripheralToClock {
const PERI_OVERRIDE: &[(&str, &[&str])] = &[("DCMI", &["DCMI_PSSI"]), ("PSSI", &["DCMI_PSSI"])];
let clocks = self.0.get(rcc_block)?;
if peri_name.starts_with("ADC") && !peri_name.contains("COMMON") {
return self.match_adc_peri_clock(clocks, peri_name);
}
if let Some(res) = clocks.get(peri_name) {
Some(res)
} else if let Some(peri_name) = peri_name.strip_suffix('1') {
@ -94,4 +97,37 @@ impl PeripheralToClock {
None
}
}
fn match_adc_peri_clock<'a>(
&'a self,
clocks: &'a HashMap<String, stm32_data_serde::chip::core::peripheral::Rcc>,
peri_name: &str,
) -> Option<&stm32_data_serde::chip::core::peripheral::Rcc> {
// Direct match
if clocks.contains_key(peri_name) {
return clocks.get(peri_name);
}
// Paired match based on odd/even
if let Some(digit_char) = peri_name.chars().last() {
if let Some(digit) = digit_char.to_digit(10) {
let paired = if digit % 2 == 1 {
format!("ADC{}{}", digit, digit + 1)
} else {
format!("ADC{}{}", digit - 1, digit)
};
if clocks.contains_key(paired.as_str()) {
return clocks.get(paired.as_str());
}
}
}
// Look for bare ADC clock register
if clocks.contains_key("ADC") {
return clocks.get("ADC");
}
None
}
}