From 42273a7f020344db7496e2b7406609e7e7ffb259 Mon Sep 17 00:00:00 2001 From: Don Reilly Date: Mon, 7 Aug 2023 14:38:22 -0500 Subject: [PATCH 1/4] rework f3 series rcc take 2 --- data/registers/adc_f3_v2.yaml | 613 ++++++++++++++++ data/registers/rcc_f3.yaml | 92 --- data/registers/rcc_f3_v2.yaml | 1267 +++++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 2 + 4 files changed, 1882 insertions(+), 92 deletions(-) create mode 100644 data/registers/adc_f3_v2.yaml create mode 100644 data/registers/rcc_f3_v2.yaml diff --git a/data/registers/adc_f3_v2.yaml b/data/registers/adc_f3_v2.yaml new file mode 100644 index 0000000..627072e --- /dev/null +++ b/data/registers/adc_f3_v2.yaml @@ -0,0 +1,613 @@ +--- +block/ADC: + description: Analog-to-Digital Converter + items: + - name: SR + description: status register + byte_offset: 0 + fieldset: SR + - name: CR1 + description: control register 1 + byte_offset: 4 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 8 + fieldset: CR2 + - name: SMPR1 + description: sample time register 1 + byte_offset: 12 + fieldset: SMPR1 + - name: SMPR2 + description: sample time register 2 + byte_offset: 16 + fieldset: SMPR2 + - name: JOFR1 + description: injected channel data offset register 1 + byte_offset: 20 + fieldset: JOFR1 + - name: JOFR2 + description: injected channel data offset register 2 + byte_offset: 24 + fieldset: JOFR2 + - name: JOFR3 + description: injected channel data offset register 3 + byte_offset: 28 + fieldset: JOFR3 + - name: JOFR4 + description: injected channel data offset register 4 + byte_offset: 32 + fieldset: JOFR4 + - name: HTR + description: watchdog higher threshold register + byte_offset: 36 + fieldset: HTR + - name: LTR + description: watchdog lower threshold register + byte_offset: 40 + fieldset: LTR + - name: SQR1 + description: regular sequence register 1 + byte_offset: 44 + fieldset: SQR1 + - name: SQR2 + description: regular sequence register 2 + byte_offset: 48 + fieldset: SQR2 + - name: SQR3 + description: regular sequence register 3 + byte_offset: 52 + fieldset: SQR3 + - name: JSQR + description: injected sequence register + byte_offset: 56 + fieldset: JSQR + - name: JDR1 + description: injected data register 1 + byte_offset: 60 + fieldset: JDR1 + access: Read + - name: JDR2 + description: injected data register 2 + byte_offset: 64 + fieldset: JDR2 + access: Read + - name: JDR3 + description: injected data register 3 + byte_offset: 68 + fieldset: JDR3 + access: Read + - name: JDR4 + description: injected data register 4 + byte_offset: 72 + fieldset: JDR4 + access: Read + - name: DR + description: regular data register + byte_offset: 76 + fieldset: DR + access: Read +fieldset/SR: + description: status register + fields: + - name: AWD + description: analog watchdog flag + bit_offset: 0 + bit_size: 1 + - name: EOC + description: end of conversion + bit_offset: 1 + bit_size: 1 + - name: JEOC + description: injected channel end of conversion + bit_offset: 2 + bit_size: 1 + - name: JSTRT + description: injected channel start flag + bit_offset: 3 + bit_size: 1 + - name: STRT + description: regular channel start flag + bit_offset: 4 + bit_size: 1 + - name: OVR + description: overrun + bit_offset: 5 + bit_size: 1 +fieldset/CR1: + description: control register 1 + fields: + - name: AWDCH + description: analog watchdog channel select bits + bit_offset: 0 + bit_size: 5 + - name: EOCIE + description: interrupt enable for EOC + bit_offset: 5 + bit_size: 1 + - name: AWDIE + description: analog watchdog interrupt enable + bit_offset: 6 + bit_size: 1 + - name: JEOCIE + description: interrupt enable for injected channels + bit_offset: 7 + bit_size: 1 + - name: SCAN + description: scan mode + bit_offset: 8 + bit_size: 1 + - name: AWDSGL + description: enable the watchdog on a single channel in scan mode + bit_offset: 9 + bit_size: 1 + - name: JAUTO + description: automatic injected group conversion + bit_offset: 10 + bit_size: 1 + - name: DISCEN + description: discontinuous mode on regular channels + bit_offset: 11 + bit_size: 1 + - name: JDISCEN + description: discontinuous mode on injected channels + bit_offset: 12 + bit_size: 1 + - name: DISCNUM + description: discontinuous mode channel count + bit_offset: 13 + bit_size: 3 + enum: DISCNUM + - name: JAWDEN + description: analog watchdog enable on injected channels + bit_offset: 22 + bit_size: 1 + - name: AWDEN + description: analog watchdog enable on regular channels + bit_offset: 23 + bit_size: 1 +fieldset/CR2: + description: control register 2 + fields: + - name: ADON + description: A/D converter ON / OFF + bit_offset: 0 + bit_size: 1 + - name: CONT + description: continuous conversion + bit_offset: 1 + bit_size: 1 + - name: CAL + description: A/D calibration + bit_offset: 2 + bit_size: 1 + - name: RSTCAL + description: reset calibration + bit_offset: 3 + bit_size: 1 + - name: DMA + description: DMA disable selection (for single ADC mode) + bit_offset: 8 + bit_size: 1 + - name: ALIGN + description: data alignment + bit_offset: 11 + bit_size: 1 + - name: JEXTSEL + description: external event select for injected group + bit_offset: 12 + bit_size: 3 + enum: JEXTSEL + - name: JEXTTRIG + description: external trigger conversion mode for injected channels + bit_offset: 15 + bit_size: 1 + - name: EXTSEL + description: external event select for regular group + bit_offset: 17 + bit_size: 3 + enum: EXTSEL + - name: EXTTRIG + description: external trigger conversion mode for regular channels + bit_offset: 20 + bit_size: 1 + - name: JSWSTART + description: start conversion of injected channels + bit_offset: 21 + bit_size: 1 + - name: SWSTART + description: start conversion of regular channels + bit_offset: 22 + bit_size: 1 + - name: TSVREFE + description: temperature sensor and VREFINT enable + bit_offset: 23 + bit_size: 1 +fieldset/SMPR1: + description: sample time register 1 + fields: + - name: SMP10 + description: channel 10 sampling time selection + bit_offset: 0 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP11 + description: channel 11 sampling time selection + bit_offset: 3 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP12 + description: channel 12 sampling time selection + bit_offset: 6 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP13 + description: channel 13 sampling time selection + bit_offset: 9 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP14 + description: channel 14 sampling time selection + bit_offset: 12 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP15 + description: channel 15 sampling time selection + bit_offset: 15 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP16 + description: channel 16 sampling time selection + bit_offset: 18 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP17 + description: channel 17 sampling time selection + bit_offset: 21 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP18 + description: channel 18 sampling time selection + bit_offset: 24 + bit_size: 3 + enum: SAMPLE_TIME +fieldset/SMPR2: + description: sample time register 2 + fields: + - name: SMP0 + description: channel 0 sampling time selection + bit_offset: 0 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP1 + description: channel 1 sampling time selection + bit_offset: 3 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP2 + description: channel 2 sampling time selection + bit_offset: 6 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP3 + description: channel 3 sampling time selection + bit_offset: 9 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP4 + description: channel 4 sampling time selection + bit_offset: 12 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP5 + description: channel 5 sampling time selection + bit_offset: 15 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP6 + description: channel 6 sampling time selection + bit_offset: 18 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP7 + description: channel 7 sampling time selection + bit_offset: 21 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP8 + description: channel 8 sampling time selection + bit_offset: 24 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP9 + description: channel 9 sampling time selection + bit_offset: 27 + bit_size: 3 + enum: SAMPLE_TIME +fieldset/JOFR1: + description: injected channel data offset register 1 + fields: + - name: JOFFSET1 + description: data offset for injected channel 1 + bit_offset: 0 + bit_size: 12 +fieldset/JOFR2: + description: injected channel data offset register 2 + fields: + - name: JOFFSET2 + description: data offset for injected channel 2 + bit_offset: 0 + bit_size: 12 +fieldset/JOFR3: + description: injected channel data offset register 3 + fields: + - name: JOFFSET3 + description: data offset for injected channel 3 + bit_offset: 0 + bit_size: 12 +fieldset/JOFR4: + description: injected channel data offset register 4 + fields: + - name: JOFFSET4 + description: data offset for injected channel 4 + bit_offset: 0 + bit_size: 12 +fieldset/HTR: + description: watchdog higher threshold register + fields: + - name: HT + description: Analog watchdog high threshold + bit_offset: 0 + bit_size: 12 +fieldset/LTR: + description: watchdog lower threshold register + fields: + - name: LT + description: Analog watchdog low threshold + bit_offset: 0 + bit_size: 12 +fieldset/SQR1: + description: regular sequence register 1 + fields: + - name: SQ13 + description: 13th conversion in regular sequence + bit_offset: 0 + bit_size: 5 + - name: SQ14 + description: 14th conversion in regular sequence + bit_offset: 5 + bit_size: 5 + - name: SQ15 + description: 15th conversion in regular sequence + bit_offset: 10 + bit_size: 5 + - name: SQ16 + description: 16th conversion in regular sequence + bit_offset: 15 + bit_size: 5 + - name: L + description: regular channel sequence length + bit_offset: 20 + bit_size: 4 +fieldset/SQR2: + description: regular sequence register 2 + fields: + - name: SQ7 + description: 7th conversion in regular sequence + bit_offset: 0 + bit_size: 5 + - name: SQ8 + description: 8th conversion in regular sequence + bit_offset: 5 + bit_size: 5 + - name: SQ9 + description: 9th conversion in regular sequence + bit_offset: 10 + bit_size: 5 + - name: SQ10 + description: 10th conversion in regular sequence + bit_offset: 15 + bit_size: 5 + - name: SQ11 + description: 11th conversion in regular sequence + bit_offset: 20 + bit_size: 5 + - name: SQ12 + description: 12th conversion in regular sequence + bit_offset: 25 + bit_size: 5 +fieldset/SQR3: + description: regular sequence register 3 + fields: + - name: SQ1 + description: 1st conversion in regular sequence + bit_offset: 0 + bit_size: 5 + - name: SQ2 + description: 2nd conversion in regular sequence + bit_offset: 5 + bit_size: 5 + - name: SQ3 + description: 3rd conversion in regular sequence + bit_offset: 10 + bit_size: 5 + - name: SQ4 + description: 4th conversion in regular sequence + bit_offset: 15 + bit_size: 5 + - name: SQ5 + description: 5th conversion in regular sequence + bit_offset: 20 + bit_size: 5 + - name: SQ6 + description: 6th conversion in regular sequence + bit_offset: 25 + bit_size: 5 +fieldset/JSQR: + description: injected sequence register + fields: + - name: JSQ1 + description: 1st conversion in injected sequence + bit_offset: 0 + bit_size: 5 + - name: JSQ2 + description: 2nd conversion in injected sequence + bit_offset: 5 + bit_size: 5 + - name: JSQ3 + description: 3rd conversion in injected sequence + bit_offset: 10 + bit_size: 5 + - name: JSQ4 + description: 4th conversion in injected sequence + bit_offset: 15 + bit_size: 5 + - name: JL + description: injected sequence length + bit_offset: 20 + bit_size: 2 +fieldset/JDR1: + description: injected data register 1 + fields: + - name: JDATA1 + description: Injected data + bit_offset: 0 + bit_size: 16 +fieldset/JDR2: + description: injected data register 2 + fields: + - name: JDATA2 + description: Injected data + bit_offset: 0 + bit_size: 16 +fieldset/JDR3: + description: injected data register 3 + fields: + - name: JDATA3 + description: Injected data + bit_offset: 0 + bit_size: 16 +fieldset/JDR4: + description: injected data register 4 + fields: + - name: JDATA4 + description: Injected data + bit_offset: 0 + bit_size: 16 +fieldset/DR: + description: regular data register + fields: + - name: DATA + description: Regular data + bit_offset: 0 + bit_size: 16 +enum/DISCNUM: + bit_size: 3 + variants: + - name: DISCNUM_1 + description: 1 conversions are discontinued and the conversion is carried out on one channel + value: 0 + - name: DISCNUM_2 + description: 2 conversion is discontinued and the conversions are carried out on 2 channels + value: 1 + - name: DISCNUM_3 + description: 3 conversions are discontinued and the conversions are carried out on 3 channels + value: 2 + - name: DISCNUM_4 + description: 4 conversions are discontinued and the conversions are carried out on 4 channels + value: 3 + - name: DISCNUM_5 + description: 5 conversions are discontinued and the conversions are carried out on 5 channels + value: 4 + - name: DISCNUM_6 + description: 6 conversions are discontinued and the conversions are carried out on 6 channels + value: 5 + - name: DISCNUM_7 + description: 7 conversions are discontinued and the conversions are carried out on 7 channels + value: 6 + - name: DISCNUM_8 + description: 8 conversions are discontinued and the conversions are carried out on 8 channels + value: 7 +enum/JEXTSEL: + bit_size: 3 + variants: + - name: TIM19_CC1 + description: Timer 19 CC1 event + value: 0 + - name: TIM19_CC2 + description: Timer 19 CC2 event + value: 1 + - name: TIM2_TRGO + description: Timer 2 TRGO event + value: 2 + - name: TIM2_CC1 + description: Timer 2 CC1 event + value: 3 + - name: TIM3_CC4 + description: Timer 3 CC4 event + value: 4 + - name: TIM4_TRGO + description: Timer 4 TRGO event + value: 5 + - name: EXTI_LINE15 + description: External interrupt line 15 + value: 6 + - name: JSWSTART + description: JSWSTART bit + value: 7 +enum/EXTSEL: + bit_size: 3 + variants: + - name: TIM19_TRGO + description: Timer 19 TRGO event + value: 0 + - name: TIM19_CC3 + description: Timer 19 CC3 event + value: 1 + - name: TIM19_CC4 + description: Timer 19 CC4 event + value: 2 + - name: TIM2_CC2 + description: Timer 2 CC2 event + value: 3 + - name: TIM3_TRGO + description: Timer 3 TRGO event + value: 4 + - name: TIM4_CC4 + description: Timer 4 CC4 event + value: 5 + - name: EXTI_LINE11 + description: External interrupt line 11 + value: 6 + - name: SWSTART + description: SWSTART bit + value: 7 +enum/SAMPLE_TIME: + bit_size: 3 + variants: + - name: Cycles1_5 + description: 1.5 ADC clock cycles + value: 0 + - name: Cycles7_5 + description: 7.5 ADC clock cycles + value: 1 + - name: Cycles13_5 + description: 13.5 ADC clock cycles + value: 2 + - name: Cycles28_5 + description: 28.5 ADC clock cycles + value: 3 + - name: Cycles41_5 + description: 41.5 ADC clock cycles + value: 4 + - name: Cycles55_5 + description: 55.5 ADC clock cycles + value: 5 + - name: Cycles71_5 + description: 71.5 ADC clock cycles + value: 6 + - name: Cycles239_5 + description: 239.5 ADC clock cycles + value: 7 + + diff --git a/data/registers/rcc_f3.yaml b/data/registers/rcc_f3.yaml index abeff29..583f36b 100644 --- a/data/registers/rcc_f3.yaml +++ b/data/registers/rcc_f3.yaml @@ -121,10 +121,6 @@ fieldset/AHBENR: description: ADC1 and ADC2 clock enable bit_offset: 28 bit_size: 1 - - name: ADC1EN - description: ADC 1 - bit_offset: 28 - bit_size: 1 - name: ADC34EN description: ADC3 and ADC4 clock enable bit_offset: 29 @@ -176,10 +172,6 @@ fieldset/AHBRSTR: description: ADC1 and ADC2 reset bit_offset: 28 bit_size: 1 - - name: ADC1RST - description: ADC1 reset - bit_offset: 28 - bit_size: 1 - name: ADC34RST description: ADC3 and ADC4 reset bit_offset: 29 @@ -199,10 +191,6 @@ fieldset/APB1ENR: description: Timer 4 clock enable bit_offset: 2 bit_size: 1 - - name: TIM5EN - description: Timer 5 clock enable - bit_offset: 3 - bit_size: 1 - name: TIM6EN description: Timer 6 clock enable bit_offset: 4 @@ -211,22 +199,6 @@ fieldset/APB1ENR: description: Timer 7 clock enable bit_offset: 5 bit_size: 1 - - name: TIM12EN - description: Timer 12 clock enable - bit_offset: 6 - bit_size: 1 - - name: TIM13EN - description: Timer 13 clock enable - bit_offset: 7 - bit_size: 1 - - name: TIM14EN - description: Timer 14 clock enable - bit_offset: 8 - bit_size: 1 - - name: TIM18EN - description: Timer 18 clock enable - bit_offset: 9 - bit_size: 1 - name: WWDGEN description: Window watchdog clock enable bit_offset: 11 @@ -283,10 +255,6 @@ fieldset/APB1ENR: description: DAC interface clock enable bit_offset: 29 bit_size: 1 - - name: CECEN - description: HDMI CEC interface clock enable - bit_offset: 30 - bit_size: 1 - name: I2C3EN description: I2C3 clock enable bit_offset: 30 @@ -306,10 +274,6 @@ fieldset/APB1RSTR: description: Timer 14 reset bit_offset: 2 bit_size: 1 - - name: TIM5RST - description: Timer 5 reset - bit_offset: 3 - bit_size: 1 - name: TIM6RST description: Timer 6 reset bit_offset: 4 @@ -318,22 +282,6 @@ fieldset/APB1RSTR: description: Timer 7 reset bit_offset: 5 bit_size: 1 - - name: TIM12RST - description: Timer 12 reset - bit_offset: 6 - bit_size: 1 - - name: TIM13RST - description: Timer 13 reset - bit_offset: 7 - bit_size: 1 - - name: TIM14RST - description: Timer 14 reset - bit_offset: 8 - bit_size: 1 - - name: TIM18RST - description: Timer 18 reset - bit_offset: 9 - bit_size: 1 - name: WWDGRST description: Window watchdog reset bit_offset: 11 @@ -390,10 +338,6 @@ fieldset/APB1RSTR: description: DAC interface reset bit_offset: 29 bit_size: 1 - - name: CECRST - description: HDMI CEC reset - bit_offset: 30 - bit_size: 1 - name: I2C3RST description: I2C3 reset bit_offset: 30 @@ -405,10 +349,6 @@ fieldset/APB2ENR: description: SYSCFG clock enable bit_offset: 0 bit_size: 1 - - name: ADCEN - description: ADC 1 interface clock enable - bit_offset: 9 - bit_size: 1 - name: TIM1EN description: TIM1 Timer clock enable bit_offset: 11 @@ -449,22 +389,6 @@ fieldset/APB2ENR: description: TIM20 timer clock enable bit_offset: 20 bit_size: 1 - - name: DBGMCUEN - description: MCU debug module clock enable - bit_offset: 22 - bit_size: 1 - - name: SDADC1EN - description: SDADC1 (Sigma Delta ADC 1) clock enable - bit_offset: 24 - bit_size: 1 - - name: SDADC2EN - description: SDADC2 (Sigma Delta ADC 2) clock enable - bit_offset: 25 - bit_size: 1 - - name: SDADC3EN - description: SDADC3 (Sigma Delta ADC 3) clock enable - bit_offset: 26 - bit_size: 1 - name: HRTIM1EN description: High Resolution Timer 1 clock enable bit_offset: 29 @@ -476,10 +400,6 @@ fieldset/APB2RSTR: description: SYSCFG and COMP reset bit_offset: 0 bit_size: 1 - - name: ADCRST - description: ADC interface reset - bit_offset: 9 - bit_size: 1 - name: TIM1RST description: TIM1 timer reset bit_offset: 11 @@ -520,18 +440,6 @@ fieldset/APB2RSTR: description: TIM20 timer reset bit_offset: 20 bit_size: 1 - - name: SDADC1RST - description: SDADC1 (Sigma delta ADC 1) reset - bit_offset: 24 - bit_size: 1 - - name: SDADC2RST - description: SDADC2 (Sigma delta ADC 2) reset - bit_offset: 25 - bit_size: 1 - - name: SDADC3RST - description: SDADC3 (Sigma delta ADC 3) reset - bit_offset: 26 - bit_size: 1 - name: HRTIM1RST description: High Resolution Timer1 reset bit_offset: 29 diff --git a/data/registers/rcc_f3_v2.yaml b/data/registers/rcc_f3_v2.yaml new file mode 100644 index 0000000..87926df --- /dev/null +++ b/data/registers/rcc_f3_v2.yaml @@ -0,0 +1,1267 @@ +--- +block/RCC: + description: Reset and clock control + items: + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: CFGR + description: Clock configuration register (RCC_CFGR) + byte_offset: 4 + fieldset: CFGR + - name: CIR + description: Clock interrupt register (RCC_CIR) + byte_offset: 8 + fieldset: CIR + - name: APB2RSTR + description: APB2 peripheral reset register (RCC_APB2RSTR) + byte_offset: 12 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register (RCC_APB1RSTR) + byte_offset: 16 + fieldset: APB1RSTR + - name: AHBENR + description: AHB Peripheral Clock enable register (RCC_AHBENR) + byte_offset: 20 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register (RCC_APB2ENR) + byte_offset: 24 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register (RCC_APB1ENR) + byte_offset: 28 + fieldset: APB1ENR + - name: BDCR + description: Backup domain control register (RCC_BDCR) + byte_offset: 32 + fieldset: BDCR + - name: CSR + description: Control/status register (RCC_CSR) + byte_offset: 36 + fieldset: CSR + - name: AHBRSTR + description: AHB peripheral reset register + byte_offset: 40 + fieldset: AHBRSTR + - name: CFGR2 + description: Clock configuration register 2 + byte_offset: 44 + fieldset: CFGR2 + - name: CFGR3 + description: Clock configuration register 3 + byte_offset: 48 + fieldset: CFGR3 +fieldset/AHBENR: + description: AHB Peripheral Clock enable register (RCC_AHBENR) + fields: + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: SRAMEN + description: SRAM interface clock enable + bit_offset: 2 + bit_size: 1 + - name: FLASHEN + description: FLASH clock enable + bit_offset: 4 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOAEN + description: I/O port A clock enable + bit_offset: 17 + bit_size: 1 + - name: GPIOBEN + description: I/O port B clock enable + bit_offset: 18 + bit_size: 1 + - name: GPIOCEN + description: I/O port C clock enable + bit_offset: 19 + bit_size: 1 + - name: GPIODEN + description: I/O port D clock enable + bit_offset: 20 + bit_size: 1 + - name: GPIOEEN + description: I/O port E clock enable + bit_offset: 21 + bit_size: 1 + - name: GPIOFEN + description: I/O port F clock enable + bit_offset: 22 + bit_size: 1 + - name: TSCEN + description: Touch sensing controller clock enable + bit_offset: 24 + bit_size: 1 +fieldset/AHBRSTR: + description: AHB peripheral reset register + fields: + - name: GPIOARST + description: I/O port A reset + bit_offset: 17 + bit_size: 1 + - name: GPIOBRST + description: I/O port B reset + bit_offset: 18 + bit_size: 1 + - name: GPIOCRST + description: I/O port C reset + bit_offset: 19 + bit_size: 1 + - name: GPIODRST + description: I/O port D reset + bit_offset: 20 + bit_size: 1 + - name: GPIOERST + description: I/O port E reset + bit_offset: 21 + bit_size: 1 + - name: GPIOFRST + description: I/O port F reset + bit_offset: 22 + bit_size: 1 + - name: TSCRST + description: Touch sensing controller reset + bit_offset: 24 + bit_size: 1 +fieldset/APB1ENR: + description: APB1 peripheral clock enable register (RCC_APB1ENR) + fields: + - name: TIM2EN + description: Timer 2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: Timer 4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: Timer 5 clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: Timer 7 clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: Timer 12 clock enable + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: Timer 13 clock enable + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: Timer 14 clock enable + bit_offset: 8 + bit_size: 1 + - name: TIM18EN + description: Timer 18 clock enable + bit_offset: 9 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI 2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI 3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART 3 clock enable + bit_offset: 18 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C 2 clock enable + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: USB clock enable + bit_offset: 23 + bit_size: 1 + - name: CANEN + description: CAN clock enable + bit_offset: 25 + bit_size: 1 + - name: DAC2EN + description: DAC2 interface clock enable + bit_offset: 26 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: CECEN + description: HDMI CEC interface clock enable + bit_offset: 30 + bit_size: 1 +fieldset/APB1RSTR: + description: APB1 peripheral reset register (RCC_APB1RSTR) + fields: + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: Timer 14 reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: Timer 5 reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: Timer 6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: Timer 7 reset + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: Timer 12 reset + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: Timer 13 reset + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: Timer 14 reset + bit_offset: 8 + bit_size: 1 + - name: TIM18RST + description: Timer 18 reset + bit_offset: 9 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 reset + bit_offset: 18 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: USB reset + bit_offset: 23 + bit_size: 1 + - name: CANRST + description: CAN reset + bit_offset: 25 + bit_size: 1 + - name: DAC2RST + description: DAC2 interface reset + bit_offset: 26 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 + - name: CECRST + description: HDMI CEC reset + bit_offset: 30 + bit_size: 1 +fieldset/APB2ENR: + description: APB2 peripheral clock enable register (RCC_APB2ENR) + fields: + - name: SYSCFGEN + description: SYSCFG clock enable + bit_offset: 0 + bit_size: 1 + - name: ADCEN + description: ADC 1 interface clock enable + bit_offset: 9 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM15EN + description: TIM15 timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: TIM19EN + description: TIM19 timer clock enable + bit_offset: 19 + bit_size: 1 + - name: DBGMCUEN + description: MCU debug module clock enable + bit_offset: 22 + bit_size: 1 + - name: SDADC1EN + description: SDADC1 (Sigma Delta ADC 1) clock enable + bit_offset: 24 + bit_size: 1 + - name: SDADC2EN + description: SDADC2 (Sigma Delta ADC 2) clock enable + bit_offset: 25 + bit_size: 1 + - name: SDADC3EN + description: SDADC3 (Sigma Delta ADC 3) clock enable + bit_offset: 26 + bit_size: 1 +fieldset/APB2RSTR: + description: APB2 peripheral reset register (RCC_APB2RSTR) + fields: + - name: SYSCFGRST + description: SYSCFG and COMP reset + bit_offset: 0 + bit_size: 1 + - name: ADCRST + description: ADC interface reset + bit_offset: 9 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: TIM19RST + description: TIM19 timer reset + bit_offset: 19 + bit_size: 1 + - name: SDADC1RST + description: SDADC1 (Sigma delta ADC 1) reset + bit_offset: 24 + bit_size: 1 + - name: SDADC2RST + description: SDADC2 (Sigma delta ADC 2) reset + bit_offset: 25 + bit_size: 1 + - name: SDADC3RST + description: SDADC3 (Sigma delta ADC 3) reset + bit_offset: 26 + bit_size: 1 +fieldset/BDCR: + description: Backup domain control register (RCC_BDCR) + fields: + - name: LSEON + description: External Low Speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External Low Speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: External Low Speed oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: LSE oscillator drive capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 +fieldset/CFGR: + description: Clock configuration register (RCC_CFGR) + fields: + - name: SW + description: System clock Switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System Clock Switch Status + bit_offset: 2 + bit_size: 2 + enum: SWS + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: ADCPRE + description: ADC prescaler + bit_offset: 14 + bit_size: 2 + enum: ADCPRE + - name: PLLSRC + description: PLL entry clock source + bit_offset: 15 + bit_size: 2 + enum: PLLSRC + - name: PLLXTPRE + description: HSE divider for PLL entry + bit_offset: 17 + bit_size: 1 + enum: PLLXTPRE + - name: PLLMUL + description: PLL Multiplication Factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: USBPRE + description: USB prescaler + bit_offset: 22 + bit_size: 1 + enum: USBPRE + - name: I2SSRC + description: I2S external clock source selection + bit_offset: 23 + bit_size: 1 + enum: ISSRC + - name: MCO + description: Microcontroller clock output + bit_offset: 24 + bit_size: 3 + enum: MCO + - name: SDPRE + description: SDADC prescaler + bit_offset: 27 + bit_size: 5 + enum: SDPRE + - name: MCOPRE + description: Microcontroller Clock Output Prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE + - name: PLLNODIV + description: Do not divide PLL to MCO + bit_offset: 31 + bit_size: 1 + enum: PLLNODIV +fieldset/CFGR2: + description: Clock configuration register 2 + fields: + - name: PREDIV + description: PREDIV division factor + bit_offset: 0 + bit_size: 4 + enum: PREDIV + - name: ADC12PRES + description: ADC1 and ADC2 prescaler + bit_offset: 4 + bit_size: 5 + enum: ADCPRES + - name: ADC1PRES + description: ADC1 prescaler + bit_offset: 4 + bit_size: 5 + enum: ADCPRES + - name: ADC34PRES + description: ADC3 and ADC4 prescaler + bit_offset: 9 + bit_size: 5 + enum: ADCPRES +fieldset/CFGR3: + description: Clock configuration register 3 + fields: + - name: USART1SW + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + enum: USARTSW + - name: I2C1SW + description: I2C1 clock source selection + bit_offset: 4 + bit_size: 1 + enum: ICSW + - name: I2C2SW + description: I2C2 clock source selection + bit_offset: 5 + bit_size: 1 + enum: ICSW + - name: CECSW + description: HDMI CEC clock source selection + bit_offset: 6 + bit_size: 1 + enum: CECSW + - name: I2C3SW + description: I2C3 clock source selection + bit_offset: 6 + bit_size: 1 + enum: ICSW + - name: TIM1SW + description: Timer1 clock source selection + bit_offset: 8 + bit_size: 1 + enum: TIMSW + - name: TIM8SW + description: Timer8 clock source selection + bit_offset: 9 + bit_size: 1 + enum: TIMSW + - name: TIM15SW + description: Timer15 clock source selection + bit_offset: 10 + bit_size: 1 + enum: TIMSW + - name: TIM16SW + description: Timer16 clock source selection + bit_offset: 11 + bit_size: 1 + enum: TIMSW + - name: HRTIM1SW + description: Hrtim1 clock source selection + bit_offset: 12 + bit_size: 1 + enum: TIMSW + - name: TIM17SW + description: Timer17 clock source selection + bit_offset: 13 + bit_size: 1 + enum: TIMSW + - name: TIM20SW + description: Timer20 clock source selection + bit_offset: 15 + bit_size: 1 + enum: TIMSW + - name: USART2SW + description: USART2 clock source selection + bit_offset: 16 + bit_size: 2 + enum: USARTSW + - name: USART3SW + description: USART3 clock source selection + bit_offset: 18 + bit_size: 2 + enum: USARTSW + - name: UART4SW + description: UART4 clock source selection + bit_offset: 20 + bit_size: 2 + enum: USARTSW + - name: UART5SW + description: UART5 clock source selection + bit_offset: 22 + bit_size: 2 + enum: USARTSW + - name: TIM2SW + description: Timer2 clock source selection + bit_offset: 24 + bit_size: 1 + enum: TIMSW + - name: TIM34SW + description: Timer34 clock source selection + bit_offset: 25 + bit_size: 1 + enum: TIMSW +fieldset/CIR: + description: Clock interrupt register (RCC_CIR) + fields: + - name: LSIRDYF + description: LSI Ready Interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE Ready Interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI Ready Interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE Ready Interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: PLL Ready Interrupt flag + bit_offset: 4 + bit_size: 1 + - name: CSSF + description: Clock Security System Interrupt flag + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI Ready Interrupt Enable + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE Ready Interrupt Enable + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI Ready Interrupt Enable + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE Ready Interrupt Enable + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: PLL Ready Interrupt Enable + bit_offset: 12 + bit_size: 1 + - name: LSIRDYC + description: LSI Ready Interrupt Clear + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE Ready Interrupt Clear + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI Ready Interrupt Clear + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE Ready Interrupt Clear + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: PLL Ready Interrupt Clear + bit_offset: 20 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 +fieldset/CR: + description: Clock control register + fields: + - name: HSION + description: Internal High Speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal High Speed clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSITRIM + description: Internal High Speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal High Speed clock Calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: External High Speed clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: External High Speed clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: External High Speed clock Bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 +fieldset/CSR: + description: Control/status register (RCC_CSR) + fields: + - name: LSION + description: Internal low speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: V18PWRRSTF + description: Reset flag of the 1.8 V domain + bit_offset: 23 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 +enum/ADCPRE: + bit_size: 2 + variants: + - name: Div2 + description: PCLK divided by 2 + value: 0 + - name: Div4 + description: PCLK divided by 4 + value: 1 + - name: Div6 + description: PCLK divided by 6 + value: 2 + - name: Div8 + description: PCLK divided by 8 + value: 3 +enum/ADCPRES: + bit_size: 5 + variants: + - name: NoClock + description: No clock + value: 0 + - name: Div1 + description: PLL clock not divided + value: 16 + - name: Div2 + description: PLL clock divided by 2 + value: 17 + - name: Div4 + description: PLL clock divided by 4 + value: 18 + - name: Div6 + description: PLL clock divided by 6 + value: 19 + - name: Div8 + description: PLL clock divided by 8 + value: 20 + - name: Div10 + description: PLL clock divided by 10 + value: 21 + - name: Div12 + description: PLL clock divided by 12 + value: 22 + - name: Div16 + description: PLL clock divided by 16 + value: 23 + - name: Div32 + description: PLL clock divided by 32 + value: 24 + - name: Div64 + description: PLL clock divided by 64 + value: 25 + - name: Div128 + description: PLL clock divided by 128 + value: 26 + - name: Div256 + description: PLL clock divided by 256 + value: 27 +enum/CECSW: + bit_size: 1 + variants: + - name: HSI_Div244 + description: HSI clock divided by 244 selected as CEC clock source + value: 0 + - name: LSE + description: LSE clock selected as CEC clock source + value: 1 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 +enum/ICSW: + bit_size: 1 + variants: + - name: HSI + description: HSI clock selected as I2C clock source + value: 0 + - name: SYSCLK + description: SYSCLK clock selected as I2C clock source + value: 1 +enum/ISSRC: + bit_size: 1 + variants: + - name: SYSCLK + description: System clock used as I2S clock source + value: 0 + - name: CKIN + description: External clock mapped on the I2S_CKIN pin used as I2S clock source + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Low + description: Low drive capacity + value: 0 + - name: MediumHigh + description: Medium-high drive capacity + value: 1 + - name: MediumLow + description: Medium-low drive capacity + value: 2 + - name: High + description: High drive capacity + value: 3 +enum/MCO: + bit_size: 3 + variants: + - name: NoMCO + description: "MCO output disabled, no clock on MCO" + value: 0 + - name: LSI + description: Internal low speed (LSI) oscillator clock selected + value: 2 + - name: LSE + description: External low speed (LSE) oscillator clock selected + value: 3 + - name: SYSCLK + description: System clock selected + value: 4 + - name: HSI + description: Internal RC 8 MHz (HSI) oscillator clock selected + value: 5 + - name: HSE + description: External 4-32 MHz (HSE) oscillator clock selected + value: 6 + - name: PLL + description: "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)" + value: 7 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: MCO is divided by 1 + value: 0 + - name: Div2 + description: MCO is divided by 2 + value: 1 + - name: Div4 + description: MCO is divided by 4 + value: 2 + - name: Div8 + description: MCO is divided by 8 + value: 3 + - name: Div16 + description: MCO is divided by 16 + value: 4 + - name: Div32 + description: MCO is divided by 32 + value: 5 + - name: Div64 + description: MCO is divided by 64 + value: 6 + - name: Div128 + description: MCO is divided by 128 + value: 7 +enum/PLLMUL: + bit_size: 4 + variants: + - name: Mul2 + description: PLL input clock x2 + value: 0 + - name: Mul3 + description: PLL input clock x3 + value: 1 + - name: Mul4 + description: PLL input clock x4 + value: 2 + - name: Mul5 + description: PLL input clock x5 + value: 3 + - name: Mul6 + description: PLL input clock x6 + value: 4 + - name: Mul7 + description: PLL input clock x7 + value: 5 + - name: Mul8 + description: PLL input clock x8 + value: 6 + - name: Mul9 + description: PLL input clock x9 + value: 7 + - name: Mul10 + description: PLL input clock x10 + value: 8 + - name: Mul11 + description: PLL input clock x11 + value: 9 + - name: Mul12 + description: PLL input clock x12 + value: 10 + - name: Mul13 + description: PLL input clock x13 + value: 11 + - name: Mul14 + description: PLL input clock x14 + value: 12 + - name: Mul15 + description: PLL input clock x15 + value: 13 + - name: Mul16 + description: PLL input clock x16 + value: 14 + - name: Mul16x + description: PLL input clock x16 + value: 15 +enum/PLLNODIV: + bit_size: 1 + variants: + - name: Div2 + description: PLL is divided by 2 for MCO + value: 0 + - name: Div1 + description: PLL is not divided for MCO + value: 1 +enum/PLLSRC: + bit_size: 2 + variants: + - name: HSI_Div2 + description: HSI divided by 2 selected as PLL input clock + value: 0 + - name: HSI_Div_PREDIV + description: HSI divided by PREDIV selected as PLL input clock + value: 1 + - name: HSE_Div_PREDIV + description: HSE divided by PREDIV selected as PLL input clock + value: 2 +enum/PLLXTPRE: + bit_size: 1 + variants: + - name: Div1 + description: HSE clock not divided + value: 0 + - name: Div2 + description: HSE clock divided by 2 + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/PREDIV: + bit_size: 4 + variants: + - name: Div1 + description: PREDIV input clock not divided + value: 0 + - name: Div2 + description: PREDIV input clock divided by 2 + value: 1 + - name: Div3 + description: PREDIV input clock divided by 3 + value: 2 + - name: Div4 + description: PREDIV input clock divided by 4 + value: 3 + - name: Div5 + description: PREDIV input clock divided by 5 + value: 4 + - name: Div6 + description: PREDIV input clock divided by 6 + value: 5 + - name: Div7 + description: PREDIV input clock divided by 7 + value: 6 + - name: Div8 + description: PREDIV input clock divided by 8 + value: 7 + - name: Div9 + description: PREDIV input clock divided by 9 + value: 8 + - name: Div10 + description: PREDIV input clock divided by 10 + value: 9 + - name: Div11 + description: PREDIV input clock divided by 11 + value: 10 + - name: Div12 + description: PREDIV input clock divided by 12 + value: 11 + - name: Div13 + description: PREDIV input clock divided by 13 + value: 12 + - name: Div14 + description: PREDIV input clock divided by 14 + value: 13 + - name: Div15 + description: PREDIV input clock divided by 15 + value: 14 + - name: Div16 + description: PREDIV input clock divided by 16 + value: 15 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 +enum/SDPRE: + bit_size: 5 + variants: + - name: Div2 + description: SYSCLK divided by 2 + value: 0 + - name: Div4 + description: SYSCLK divided by 4 + value: 17 + - name: Div6 + description: SYSCLK divided by 6 + value: 18 + - name: Div8 + description: SYSCLK divided by 8 + value: 19 + - name: Div10 + description: SYSCLK divided by 10 + value: 20 + - name: Div12 + description: SYSCLK divided by 12 + value: 21 + - name: Div14 + description: SYSCLK divided by 14 + value: 22 + - name: Div16 + description: SYSCLK divided by 16 + value: 23 + - name: Div20 + description: SYSCLK divided by 20 + value: 24 + - name: Div24 + description: SYSCLK divided by 24 + value: 25 + - name: Div28 + description: SYSCLK divided by 28 + value: 26 + - name: Div32 + description: SYSCLK divided by 32 + value: 27 + - name: Div36 + description: SYSCLK divided by 36 + value: 28 + - name: Div40 + description: SYSCLK divided by 40 + value: 29 + - name: Div44 + description: SYSCLK divided by 44 + value: 30 + - name: Div48 + description: SYSCLK divided by 48 + value: 31 +enum/SW: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as system clock + value: 0 + - name: HSE + description: HSE selected as system clock + value: 1 + - name: PLL + description: PLL selected as system clock + value: 2 +enum/SWS: + bit_size: 2 + variants: + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL + description: PLL used as system clock + value: 2 +enum/TIMSW: + bit_size: 1 + variants: + - name: PCLK2 + description: PCLK2 clock (doubled frequency when prescaled) + value: 0 + - name: PLL + description: PLL vco output (running up to 144 MHz) + value: 1 +enum/USARTSW: + bit_size: 2 + variants: + - name: PCLK + description: PCLK selected as USART clock source + value: 0 + - name: SYSCLK + description: SYSCLK selected as USART clock source + value: 1 + - name: LSE + description: LSE selected as USART clock source + value: 2 + - name: HSI + description: HSI selected as USART clock source + value: 3 +enum/USBPRE: + bit_size: 1 + variants: + - name: DIV1_5 + description: PLL clock is divided by 1.5 + value: 0 + - name: DIV1 + description: PLL clock is not divided + value: 1 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 4d154ac..1edcc1c 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -171,6 +171,7 @@ impl PeriMatcher { (".*:DAC:F3_dacif_v1_1", ("dac", "v1", "DAC")), (".*:ADC:aditf_v2_5F1", ("adc", "f1", "ADC")), (".*:ADC:aditf5_v1_1", ("adc", "f3", "ADC")), + (".*:ADC:aditf_v2_5", ("adc", "f3_v2", "ADC")), (".*:ADC:aditf4_v1_1", ("adc", "v1", "ADC")), (".*:ADC:aditf2_v1_1", ("adc", "v2", "ADC")), (".*:ADC:aditf5_v2_0", ("adc", "v3", "ADC")), @@ -265,6 +266,7 @@ impl PeriMatcher { ("STM32F10[123].*:RCC:.*", ("rcc", "f1", "RCC")), ("STM32F10[57].*:RCC:.*", ("rcc", "f1cl", "RCC")), ("STM32F2.*:RCC:.*", ("rcc", "f2", "RCC")), + ("STM32F37.*:RCC:.*", ("rcc", "f3_v2", "RCC")), ("STM32F3.*:RCC:.*", ("rcc", "f3", "RCC")), ("STM32F410.*:RCC:.*", ("rcc", "f410", "RCC")), ("STM32F4.*:RCC:.*", ("rcc", "f4", "RCC")), From dff9c321f38b80504cfefdc17165794e8d802982 Mon Sep 17 00:00:00 2001 From: Don Reilly Date: Mon, 7 Aug 2023 15:04:18 -0500 Subject: [PATCH 2/4] readd DBGMCU back into F3 and F3v2 --- data/registers/rcc_f3.yaml | 8 ++++++++ data/registers/rcc_f3_v2.yaml | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/data/registers/rcc_f3.yaml b/data/registers/rcc_f3.yaml index 583f36b..3516fef 100644 --- a/data/registers/rcc_f3.yaml +++ b/data/registers/rcc_f3.yaml @@ -389,6 +389,10 @@ fieldset/APB2ENR: description: TIM20 timer clock enable bit_offset: 20 bit_size: 1 + - name: DBGMCUEN + description: MCU debug module clock enable + bit_offset: 22 + bit_size: 1 - name: HRTIM1EN description: High Resolution Timer 1 clock enable bit_offset: 29 @@ -440,6 +444,10 @@ fieldset/APB2RSTR: description: TIM20 timer reset bit_offset: 20 bit_size: 1 + - name: DBGMCURST + description: Debug MCU reset + bit_offset: 22 + bit_size: 1 - name: HRTIM1RST description: High Resolution Timer1 reset bit_offset: 29 diff --git a/data/registers/rcc_f3_v2.yaml b/data/registers/rcc_f3_v2.yaml index 87926df..7e4dfab 100644 --- a/data/registers/rcc_f3_v2.yaml +++ b/data/registers/rcc_f3_v2.yaml @@ -412,6 +412,10 @@ fieldset/APB2RSTR: description: TIM19 timer reset bit_offset: 19 bit_size: 1 + - name: DBGMCURST + description: MCU debug module clock enable + bit_offset: 22 + bit_size: 1 - name: SDADC1RST description: SDADC1 (Sigma delta ADC 1) reset bit_offset: 24 From f4e0487ae54d03572f58a3b4cf3d79cab695c7f5 Mon Sep 17 00:00:00 2001 From: Don Reilly Date: Tue, 8 Aug 2023 15:15:36 -0500 Subject: [PATCH 3/4] map all (most?) edge cases of ADC --- stm32-data-gen/src/rcc.rs | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs index d4e17c6..a6052f9 100644 --- a/stm32-data-gen/src/rcc.rs +++ b/stm32-data-gen/src/rcc.rs @@ -79,6 +79,9 @@ impl PeripheralToClock { const PERI_OVERRIDE: &[(&str, &[&str])] = &[("DCMI", &["DCMI_PSSI"]), ("PSSI", &["DCMI_PSSI"])]; let clocks = self.0.get(rcc_block)?; + if peri_name.starts_with("ADC") { + return self.match_adc_peri_clock(clocks, peri_name); + } if let Some(res) = clocks.get(peri_name) { Some(res) } else if let Some(peri_name) = peri_name.strip_suffix('1') { @@ -94,4 +97,32 @@ impl PeripheralToClock { None } } + + fn match_adc_peri_clock<'a>( + &'a self, + clocks: &'a HashMap, + peri_name: &str, + ) -> Option<&stm32_data_serde::chip::core::peripheral::Rcc> { + // Direct match + if clocks.contains_key(peri_name) { + return clocks.get(peri_name); + } + + // Paired match based on odd/even + if let Some(digit_char) = peri_name.chars().last() { + if let Some(digit) = digit_char.to_digit(10) { + let paired = if digit % 2 == 1 { + format!("ADC{}{}", digit, digit + 1) + } else { + format!("ADC{}{}", digit - 1, digit) + }; + + if clocks.contains_key(paired.as_str()) { + return clocks.get(paired.as_str()); + } + } + } + + None + } } From 7b0a28e9893615d6a310db5b4d01adc0447fa615 Mon Sep 17 00:00:00 2001 From: Don Reilly Date: Wed, 9 Aug 2023 10:34:10 -0500 Subject: [PATCH 4/4] fixed missing edge case --- stm32-data-gen/src/rcc.rs | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs index a6052f9..34da8c0 100644 --- a/stm32-data-gen/src/rcc.rs +++ b/stm32-data-gen/src/rcc.rs @@ -79,7 +79,7 @@ impl PeripheralToClock { const PERI_OVERRIDE: &[(&str, &[&str])] = &[("DCMI", &["DCMI_PSSI"]), ("PSSI", &["DCMI_PSSI"])]; let clocks = self.0.get(rcc_block)?; - if peri_name.starts_with("ADC") { + if peri_name.starts_with("ADC") && !peri_name.contains("COMMON") { return self.match_adc_peri_clock(clocks, peri_name); } if let Some(res) = clocks.get(peri_name) { @@ -123,6 +123,11 @@ impl PeripheralToClock { } } + // Look for bare ADC clock register + if clocks.contains_key("ADC") { + return clocks.get("ADC"); + } + None } }