Merge pull request #233 from xoviat/adc

add adc common f3

data/extra/family/STM32F3.yaml

@@ -0,0 +1,8 @@
+---
+peripherals:
+  - name: VREFINTCAL
+    address: 0x1FFFF7BA
+    registers: 
+      kind: vrefintcal
+      version: v1
+      block: VREFINTCAL

data/registers/adccommon_f3.yaml

@@ -0,0 +1,286 @@
+---
+block/ADC_COMMON:
+  description: ADC common registers
+  items:
+    - name: CSR
+      description: ADC Common status register
+      byte_offset: 0
+      access: Read
+      fieldset: CSR
+    - name: CCR
+      description: ADC common control register
+      byte_offset: 8
+      fieldset: CCR
+    - name: CDR
+      description: ADC common regular data register for dual and triple modes
+      byte_offset: 12
+      access: Read
+      fieldset: CDR
+fieldset/CSR:
+  decsription: ADC common status register
+  fields:
+    - name: ADRDY_MST
+      description: Master ADC ready
+      bit_offset: 0
+      bit_size: 1
+    - name: EOSMP_MST
+      description: End of sampling phase flag of the master ADC
+      bit_offset: 1
+      bit_size: 1
+      enum: ENDED
+    - name: EOC_MST
+      description: End of regular conversion of the master ADC
+      bit_offset: 2
+      bit_size: 1
+      enum: ENDED
+    - name: EOS_MST
+      description: End of regular sequence flag of the master ADC
+      bit_offset: 3
+      bit_size: 1
+      enum: ENDED
+    - name: OVR_MST
+      description: Overrun flag of the master ADC
+      bit_offset: 4
+      bit_size: 1
+      enum: OVR
+    - name: JEOC_MST
+      description: End of injected conversion of the master ADC
+      bit_offset: 5
+      bit_size: 1
+      enum: ENDED
+    - name: JEOS
+      description: End of injected sequence flag of the master ADC
+      bit_offset: 6
+      bit_size: 1
+      enum: ENDED
+    - name: AWD1_MST
+      description: Analog watchdog 1 flag of the master ADC
+      bit_offset: 7
+      bit_size: 1
+      enum: AWD
+    - name: AWD2_MST
+      description: Analog watchdog 2 flag of the master ADC
+      bit_offset: 8
+      bit_size: 1
+      enum: AWD
+    - name: AWD3_MST
+      description: Analog watchdog 3 flag of the master ADC
+      bit_offset: 9
+      bit_size: 1
+      enum: AWD
+    - name: JQOVF_MST
+      description: Injected context queue overflow flag of the master ADC
+      bit_offset: 10
+      bit_size: 1
+      enum: JQOVF
+    - name: ADRDY_SLV
+      description: Slave ADC ready
+      bit_offset: 16
+      bit_size: 1
+    - name: EOSMP_SLV
+      description: End of sampling phase flag of the slave ADC
+      bit_offset: 17
+      bit_size: 1
+      enum: ENDED
+    - name: EOC_SLV
+      description: End of regular conversion of the slave ADC
+      bit_offset: 18
+      bit_size: 1
+      enum: ENDED
+    - name: EOS_SLV
+      description: End of regular sequence flag of the slave ADC
+      bit_offset: 19
+      bit_size: 1
+      enum: ENDED
+    - name: OVR_SLV
+      description: Overrun flag of the slave ADC
+      bit_offset: 20
+      bit_size: 1
+      enum: OVR
+    - name: JEOC_SLV
+      description: End of injected conversion of the slave ADC
+      bit_offset: 21
+      bit_size: 1
+      enum: ENDED
+    - name: JEOS_SLV
+      description: End of injected sequence flag of the slave ADC
+      bit_offset: 22
+      bit_size: 1
+      enum: ENDED
+    - name: AWD1_SLV
+      description: Analog watchdog 1 flag of the slave ADC
+      bit_offset: 23
+      bit_size: 1
+      enum: AWD
+    - name: AWD2_SLV
+      description: Analog watchdog 2 flag of the slave ADC
+      bit_offset: 24
+      bit_size: 1
+      enum: AWD
+    - name: AWD3_SLV
+      description: Analog watchdog 3 flag of the slave ADC
+      bit_offset: 25
+      bit_size: 1
+      enum: AWD
+    - name: JQOVF_SLV
+      description: Injected context queue overflow flag of the slave ADC
+      bit_offset: 26
+      bit_size: 1
+      enum: JQOVF
+fieldset/CCR:
+  description: ADC common control register
+  fields:
+    - name: DUAL
+      description: Dual ADC mode selection
+      bit_offset: 0
+      bit_size: 5
+      enum: DUAL
+    - name: DELAY
+      description: Delay between 2 sampling phases
+      bit_offset: 8
+      bit_size: 4
+    - name: DMACFG
+      description: DMA configuration (for multi-ADC mode)
+      bit_offset: 13
+      bit_size: 1
+      enum: DMACFG
+    - name: MDMA
+      description: Direct memory access mode for multi ADC mode
+      bit_offset: 14
+      bit_size: 2
+      enum: MDMA
+    - name: CKMODE
+      description: ADC clock mode
+      bit_offset: 16
+      bit_size: 2
+      enum: CKMODE
+    - name: VREFEN
+      description: VREFINT enable
+      bit_offset: 22
+      bit_size: 1
+    - name: TSEN
+      description: Temperature sensor enable
+      bit_offset: 23
+      bit_size: 1
+    - name: VBATEN
+      description: VBAT enable
+      bit_offset: 24
+      bit_size: 1
+fieldset/CDR:
+  description: ADC common regular data register for dual and triple modes
+  fields:
+    - name: RDATA_MST
+      description: Regular data of the master ADC
+      bit_offset: 0
+      bit_size: 16
+    - name: RDATA_SLV
+      description: Regular data of the master ADC
+      bit_offset: 16
+      bit_size: 16
+enum/ENDED:
+  description: End of operation
+  bit_size: 1
+  variants:
+    - name: NotEnded
+      value: 0
+      description: Operation is not ended
+    - name: Ended
+      value: 1
+      description: Operation is ended
+enum/OVR:
+  description: Overrun flag
+  bit_size: 1
+  variants:
+    - name: NoOverrun
+      value: 0
+      description: No overrun occurred
+    - name: Overrun
+      value: 1
+      description: Overrun occurred
+enum/AWD:
+  description: Analog watchdog flag
+  bit_size: 1
+  variants:
+    - name: NoEvent
+      value: 0
+      description: No analog watchdog event occurred
+    - name: Event
+      value: 1
+      description: Analog watchdog event occurred
+enum/JQOVF:
+  description: Injected context queue overflow flag
+  bit_size: 1
+  variants:
+    - name: NoOverflow
+      value: 0
+      description: No injected context queue overflow
+    - name: Overflow
+      value: 1
+      description: Injected context queue overflow
+enum/DUAL:
+  description: Dual ADC mode selection
+  bit_size: 5
+  variants:
+    - name: Independent
+      value: 0
+      description: Independent mode
+    - name: DualRJ
+      value: 1
+      description: Dual, combined regular simultaneous + injected simultaneous mode
+    - name: DualRA
+      value: 2
+      description: Dual, combined regular simultaneous + alternate trigger mode
+    - name: DualIJ
+      value: 3
+      description: Dual, combined injected simultaneous + fast interleaved mode
+    - name: DualJ
+      value: 5
+      description: Dual, injected simultaneous mode only
+    - name: DualR
+      value: 6
+      description: Dual, regular simultaneous mode only
+    - name: DualI
+      value: 7
+      description: dual, interleaved mode only
+    - name: DualA
+      value: 9
+      description: Dual, alternate trigger mode only
+enum/DMACFG:
+  description: DMA configuration (for multi-ADC mode)
+  bit_size: 1
+  variants:
+    - name: OneShot
+      value: 0
+      description: DMA one shot mode selected
+    - name: Circulator
+      value: 1
+      description: DMA circular mode selected
+enum/MDMA:
+  description: Direct memory access mode for multi ADC mode
+  bit_size: 2
+  variants:
+    - name: Disabled
+      value: 0
+      description: MDMA mode disabled
+    - name: Bits12_10
+      value: 2
+      description: MDMA mode enabled for 12 and 10-bit resolution
+    - name: Bit8_6
+      value: 3
+      description: MDMA mode enabled for 8 and 6-bit resolution
+enum/CKMODE:
+  description: ADC clock mode
+  bit_size: 2
+  variants:
+    - name: Asynchronous
+      value: 0
+      description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous mode
+    - name: SyncDiv1
+      value: 1
+      description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck.
+    - name: SyncDiv2
+      value: 2
+      description: Use AHB clock rcc_hclk3 divided by 2.
+    - name: SyncDiv4
+      value: 3
+      description: Use AHB clock rcc_hclk3 divided by 4.

stm32-data-gen/src/chips.rs

@@ -183,6 +183,8 @@ impl PeriMatcher {
             (".*:ADC_COMMON:aditf5_v2_0", ("adccommon", "v3", "ADC_COMMON")),
             (".*:ADC_COMMON:aditf5_v2_2", ("adccommon", "v3", "ADC_COMMON")),
             (".*:ADC_COMMON:aditf4_v3_0_WL", ("adccommon", "v3", "ADC_COMMON")),
+            (".*:ADC_COMMON:aditf5_v1_1", ("adccommon", "f3", "ADC_COMMON")),
+            (".*:ADC3_COMMON:aditf5_v1_1", ("adccommon", "f3", "ADC_COMMON")),
             ("STM32H7.*:ADC_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")),
             ("STM32H7.*:ADC3_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")),
             (".*:DCMI:.*", ("dcmi", "v1", "DCMI")),
@@ -823,7 +825,7 @@ fn process_core(
                 entry.insert(format!("ADC_COMMON:{}", ip.version.strip_suffix("_Cube").unwrap()));
             }
         }
-        if pname.starts_with("ADC3") && chip_name.starts_with("STM32H7") {
+        if pname.starts_with("ADC3") && (chip_name.starts_with("STM32H7") || chip_name.starts_with("STM32F3")) {
             if let Entry::Vacant(entry) = peri_kinds.entry("ADC3_COMMON".to_string()) {
                 entry.insert(format!("ADC3_COMMON:{}", ip.version.strip_suffix("_Cube").unwrap()));
             }

stm32-data-gen/src/header.rs

@@ -165,6 +165,7 @@ impl Defines {
                 "ADC_COMMON",
                 &["ADC_COMMON", "ADC1_COMMON", "ADC12_COMMON", "ADC123_COMMON"],
             ),
+            ("ADC3_COMMON", &["ADC3_COMMON", "ADC4_COMMON", "ADC34_COMMON"]),
             ("CAN", &["CAN_BASE", "CAN1_BASE"]),
             ("FMC", &["FMC_BASE", "FMC_R_BASE"]),
             ("FSMC", &["FSMC_R_BASE"]),