286 lines
7.5 KiB
YAML
286 lines
7.5 KiB
YAML
---
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block/ADC_COMMON:
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description: ADC common registers
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items:
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- name: CSR
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description: ADC Common status register
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byte_offset: 0
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access: Read
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fieldset: CSR
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- name: CCR
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description: ADC common control register
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byte_offset: 8
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fieldset: CCR
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- name: CDR
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description: ADC common regular data register for dual and triple modes
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byte_offset: 12
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access: Read
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fieldset: CDR
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fieldset/CSR:
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decsription: ADC common status register
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fields:
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- name: ADRDY_MST
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description: Master ADC ready
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bit_offset: 0
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bit_size: 1
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- name: EOSMP_MST
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description: End of sampling phase flag of the master ADC
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bit_offset: 1
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bit_size: 1
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enum: ENDED
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- name: EOC_MST
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description: End of regular conversion of the master ADC
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bit_offset: 2
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bit_size: 1
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enum: ENDED
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- name: EOS_MST
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description: End of regular sequence flag of the master ADC
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bit_offset: 3
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bit_size: 1
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enum: ENDED
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- name: OVR_MST
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description: Overrun flag of the master ADC
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bit_offset: 4
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bit_size: 1
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enum: OVR
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- name: JEOC_MST
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description: End of injected conversion of the master ADC
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bit_offset: 5
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bit_size: 1
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enum: ENDED
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- name: JEOS
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description: End of injected sequence flag of the master ADC
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bit_offset: 6
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bit_size: 1
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enum: ENDED
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- name: AWD1_MST
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description: Analog watchdog 1 flag of the master ADC
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bit_offset: 7
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bit_size: 1
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enum: AWD
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- name: AWD2_MST
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description: Analog watchdog 2 flag of the master ADC
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bit_offset: 8
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bit_size: 1
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enum: AWD
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- name: AWD3_MST
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description: Analog watchdog 3 flag of the master ADC
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bit_offset: 9
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bit_size: 1
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enum: AWD
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- name: JQOVF_MST
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description: Injected context queue overflow flag of the master ADC
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bit_offset: 10
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bit_size: 1
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enum: JQOVF
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- name: ADRDY_SLV
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description: Slave ADC ready
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bit_offset: 16
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bit_size: 1
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- name: EOSMP_SLV
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description: End of sampling phase flag of the slave ADC
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bit_offset: 17
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bit_size: 1
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enum: ENDED
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- name: EOC_SLV
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description: End of regular conversion of the slave ADC
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bit_offset: 18
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bit_size: 1
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enum: ENDED
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- name: EOS_SLV
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description: End of regular sequence flag of the slave ADC
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bit_offset: 19
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bit_size: 1
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enum: ENDED
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- name: OVR_SLV
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description: Overrun flag of the slave ADC
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bit_offset: 20
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bit_size: 1
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enum: OVR
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- name: JEOC_SLV
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description: End of injected conversion of the slave ADC
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bit_offset: 21
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bit_size: 1
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enum: ENDED
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- name: JEOS_SLV
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description: End of injected sequence flag of the slave ADC
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bit_offset: 22
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bit_size: 1
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enum: ENDED
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- name: AWD1_SLV
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description: Analog watchdog 1 flag of the slave ADC
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bit_offset: 23
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bit_size: 1
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enum: AWD
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- name: AWD2_SLV
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description: Analog watchdog 2 flag of the slave ADC
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bit_offset: 24
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bit_size: 1
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enum: AWD
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- name: AWD3_SLV
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description: Analog watchdog 3 flag of the slave ADC
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bit_offset: 25
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bit_size: 1
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enum: AWD
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- name: JQOVF_SLV
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description: Injected context queue overflow flag of the slave ADC
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bit_offset: 26
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bit_size: 1
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enum: JQOVF
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fieldset/CCR:
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description: ADC common control register
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fields:
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- name: DUAL
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description: Dual ADC mode selection
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bit_offset: 0
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bit_size: 5
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enum: DUAL
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- name: DELAY
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description: Delay between 2 sampling phases
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bit_offset: 8
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bit_size: 4
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- name: DMACFG
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description: DMA configuration (for multi-ADC mode)
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bit_offset: 13
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bit_size: 1
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enum: DMACFG
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- name: MDMA
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description: Direct memory access mode for multi ADC mode
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bit_offset: 14
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bit_size: 2
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enum: MDMA
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- name: CKMODE
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description: ADC clock mode
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bit_offset: 16
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bit_size: 2
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enum: CKMODE
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- name: VREFEN
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description: VREFINT enable
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bit_offset: 22
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bit_size: 1
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- name: TSEN
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description: Temperature sensor enable
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bit_offset: 23
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bit_size: 1
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- name: VBATEN
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description: VBAT enable
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bit_offset: 24
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bit_size: 1
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fieldset/CDR:
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description: ADC common regular data register for dual and triple modes
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fields:
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- name: RDATA_MST
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description: Regular data of the master ADC
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bit_offset: 0
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bit_size: 16
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- name: RDATA_SLV
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description: Regular data of the master ADC
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bit_offset: 16
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bit_size: 16
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enum/ENDED:
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description: End of operation
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bit_size: 1
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variants:
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- name: NotEnded
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value: 0
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description: Operation is not ended
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- name: Ended
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value: 1
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description: Operation is ended
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enum/OVR:
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description: Overrun flag
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bit_size: 1
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variants:
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- name: NoOverrun
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value: 0
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description: No overrun occurred
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- name: Overrun
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value: 1
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description: Overrun occurred
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enum/AWD:
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description: Analog watchdog flag
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bit_size: 1
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variants:
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- name: NoEvent
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value: 0
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description: No analog watchdog event occurred
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- name: Event
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value: 1
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description: Analog watchdog event occurred
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enum/JQOVF:
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description: Injected context queue overflow flag
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bit_size: 1
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variants:
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- name: NoOverflow
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value: 0
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description: No injected context queue overflow
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- name: Overflow
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value: 1
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description: Injected context queue overflow
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enum/DUAL:
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description: Dual ADC mode selection
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bit_size: 5
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variants:
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- name: Independent
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value: 0
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description: Independent mode
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- name: DualRJ
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value: 1
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description: Dual, combined regular simultaneous + injected simultaneous mode
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- name: DualRA
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value: 2
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description: Dual, combined regular simultaneous + alternate trigger mode
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- name: DualIJ
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value: 3
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description: Dual, combined injected simultaneous + fast interleaved mode
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- name: DualJ
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value: 5
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description: Dual, injected simultaneous mode only
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- name: DualR
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value: 6
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description: Dual, regular simultaneous mode only
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- name: DualI
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value: 7
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description: dual, interleaved mode only
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- name: DualA
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value: 9
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description: Dual, alternate trigger mode only
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enum/DMACFG:
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description: DMA configuration (for multi-ADC mode)
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bit_size: 1
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variants:
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- name: OneShot
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value: 0
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description: DMA one shot mode selected
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- name: Circulator
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value: 1
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description: DMA circular mode selected
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enum/MDMA:
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description: Direct memory access mode for multi ADC mode
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bit_size: 2
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variants:
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- name: Disabled
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value: 0
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description: MDMA mode disabled
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- name: Bits12_10
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value: 2
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description: MDMA mode enabled for 12 and 10-bit resolution
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- name: Bit8_6
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value: 3
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description: MDMA mode enabled for 8 and 6-bit resolution
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enum/CKMODE:
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description: ADC clock mode
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bit_size: 2
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variants:
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- name: Asynchronous
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value: 0
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description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous mode
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- name: SyncDiv1
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value: 1
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description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck.
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- name: SyncDiv2
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value: 2
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description: Use AHB clock rcc_hclk3 divided by 2.
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- name: SyncDiv4
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value: 3
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description: Use AHB clock rcc_hclk3 divided by 4. |