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fixed missing edge case

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This commit is contained in:
Don Reilly 2023-08-09 10:34:10 -05:00
parent f4e0487ae5
commit 7b0a28e989
1 changed files with 6 additions and 1 deletions
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7
stm32-data-gen/src/rcc.rs
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@ -79,7 +79,7 @@ impl PeripheralToClock {
const PERI_OVERRIDE: &[(&str, &[&str])] = &[("DCMI", &["DCMI_PSSI"]), ("PSSI", &["DCMI_PSSI"])]; const PERI_OVERRIDE: &[(&str, &[&str])] = &[("DCMI", &["DCMI_PSSI"]), ("PSSI", &["DCMI_PSSI"])];
let clocks = self.0.get(rcc_block)?; let clocks = self.0.get(rcc_block)?;
if peri_name.starts_with("ADC") { if peri_name.starts_with("ADC") && !peri_name.contains("COMMON") {
return self.match_adc_peri_clock(clocks, peri_name); return self.match_adc_peri_clock(clocks, peri_name);
} }
if let Some(res) = clocks.get(peri_name) { if let Some(res) = clocks.get(peri_name) {
@ -123,6 +123,11 @@ impl PeripheralToClock {
} }
} }
// Look for bare ADC clock register
if clocks.contains_key("ADC") {
return clocks.get("ADC");
}
None None
} }
} }