From 7b0a28e9893615d6a310db5b4d01adc0447fa615 Mon Sep 17 00:00:00 2001
From: Don Reilly <dreilly1982@gmail.com>
Date: Wed, 9 Aug 2023 10:34:10 -0500
Subject: [PATCH] fixed missing edge case

---
 stm32-data-gen/src/rcc.rs | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs
index a6052f9..34da8c0 100644
--- a/stm32-data-gen/src/rcc.rs
+++ b/stm32-data-gen/src/rcc.rs
@@ -79,7 +79,7 @@ impl PeripheralToClock {
         const PERI_OVERRIDE: &[(&str, &[&str])] = &[("DCMI", &["DCMI_PSSI"]), ("PSSI", &["DCMI_PSSI"])];
 
         let clocks = self.0.get(rcc_block)?;
-        if peri_name.starts_with("ADC") {
+        if peri_name.starts_with("ADC") && !peri_name.contains("COMMON") {
             return self.match_adc_peri_clock(clocks, peri_name);
         }
         if let Some(res) = clocks.get(peri_name) {
@@ -123,6 +123,11 @@ impl PeripheralToClock {
             }
         }
 
+        // Look for bare ADC clock register
+        if clocks.contains_key("ADC") {
+            return clocks.get("ADC");
+        }
+
         None
     }
 }