Add the thing

.gitignore

@@ -0,0 +1,3 @@
+/files
+/sources
+/tmp

README.md

@@ -0,0 +1,4 @@
+wget http://stmcufinder.com/API/getFiles.php -O sources/files.json
+wget http://stmcufinder.com/API/getMCUsForMCUFinderPC.php -O sources/mcus.json
+
+jq -r .Files[].URL < sources/files.json  | wget -N -i - 

data/gpio_af/STM32F031.yaml

@@ -0,0 +1,194 @@
+PA0:
+  RTC_TAMP2: 0
+  SYS_WKUP1: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  TSC_G1_IO1: 3
+  USART1_CTS: 1
+  USART2_CTS: 1
+PA1:
+  EVENTOUT: 0
+  TIM2_CH2: 2
+  TSC_G1_IO2: 3
+  USART1_DE: 1
+  USART1_RTS: 1
+  USART2_DE: 1
+  USART2_RTS: 1
+PA10:
+  I2C1_SDA: 4
+  TIM17_BKIN: 0
+  TIM1_CH3: 2
+  TSC_G4_IO2: 3
+  USART1_RX: 1
+PA11:
+  EVENTOUT: 0
+  TIM1_CH4: 2
+  TSC_G4_IO3: 3
+  USART1_CTS: 1
+PA12:
+  EVENTOUT: 0
+  TIM1_ETR: 2
+  TSC_G4_IO4: 3
+  USART1_DE: 1
+  USART1_RTS: 1
+PA13:
+  IR_OUT: 1
+PA14:
+  SYS_SWCLK: 0
+  USART1_TX: 1
+  USART2_TX: 1
+PA15:
+  EVENTOUT: 3
+  I2S1_WS: 0
+  SPI1_NSS: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART1_RX: 1
+  USART2_RX: 1
+PA2:
+  TIM15_CH1: 0
+  TIM2_CH3: 2
+  TSC_G1_IO3: 3
+  USART1_TX: 1
+  USART2_TX: 1
+PA3:
+  TIM15_CH2: 0
+  TIM2_CH4: 2
+  TSC_G1_IO4: 3
+  USART1_RX: 1
+  USART2_RX: 1
+PA4:
+  I2S1_WS: 0
+  SPI1_NSS: 0
+  TIM14_CH1: 4
+  TSC_G2_IO1: 3
+  USART1_CK: 1
+  USART2_CK: 1
+PA5:
+  HDMI_CEC_CEC: 1
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  TSC_G2_IO2: 3
+PA6:
+  EVENTOUT: 6
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM16_CH1: 5
+  TIM1_BKIN: 2
+  TIM3_CH1: 1
+  TSC_G2_IO3: 3
+PA7:
+  EVENTOUT: 6
+  I2S1_SD: 0
+  SPI1_MOSI: 0
+  TIM14_CH1: 4
+  TIM17_CH1: 5
+  TIM1_CH1N: 2
+  TIM3_CH2: 1
+  TSC_G2_IO4: 3
+PA8:
+  EVENTOUT: 3
+  RCC_MCO: 0
+  TIM1_CH1: 2
+  USART1_CK: 1
+PA9:
+  I2C1_SCL: 4
+  TIM15_BKIN: 0
+  TIM1_CH2: 2
+  TSC_G4_IO1: 3
+  USART1_TX: 1
+PB0:
+  EVENTOUT: 0
+  TIM1_CH2N: 2
+  TIM3_CH3: 1
+  TSC_G3_IO2: 3
+PB1:
+  TIM14_CH1: 0
+  TIM1_CH3N: 2
+  TIM3_CH4: 1
+  TSC_G3_IO3: 3
+PB10:
+  HDMI_CEC_CEC: 2
+  I2C1_SCL: 1
+  I2C2_SCL: 1
+  TIM2_CH3: 2
+  TSC_SYNC: 3
+PB11:
+  EVENTOUT: 0
+  I2C1_SDA: 1
+  I2C2_SDA: 1
+  TIM2_CH4: 2
+  TSC_G6_IO1: 3
+PB12:
+  EVENTOUT: 1
+  SPI1_NSS: 0
+  SPI2_NSS: 0
+  TIM1_BKIN: 2
+  TSC_G6_IO2: 3
+PB13:
+  SPI1_SCK: 0
+  SPI2_SCK: 0
+  TIM1_CH1N: 2
+  TSC_G6_IO3: 3
+PB14:
+  SPI1_MISO: 0
+  SPI2_MISO: 0
+  TIM15_CH1: 1
+  TIM1_CH2N: 2
+  TSC_G6_IO4: 3
+PB15:
+  RTC_REFIN: 0
+  SPI1_MOSI: 0
+  SPI2_MOSI: 0
+  TIM15_CH1N: 3
+  TIM15_CH2: 1
+  TIM1_CH3N: 2
+PB2:
+  TSC_G3_IO4: 3
+PB3:
+  EVENTOUT: 1
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM2_CH2: 2
+  TSC_G5_IO1: 3
+PB4:
+  EVENTOUT: 2
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM3_CH1: 1
+  TSC_G5_IO2: 3
+PB5:
+  I2C1_SMBA: 3
+  I2S1_SD: 0
+  SPI1_MOSI: 0
+  TIM16_BKIN: 2
+  TIM3_CH2: 1
+PB6:
+  I2C1_SCL: 1
+  TIM16_CH1N: 2
+  TSC_G5_IO3: 3
+  USART1_TX: 0
+PB7:
+  I2C1_SDA: 1
+  TIM17_CH1N: 2
+  TSC_G5_IO4: 3
+  USART1_RX: 0
+PB8:
+  HDMI_CEC_CEC: 2
+  I2C1_SCL: 1
+  TIM16_CH1: 2
+  TSC_SYNC: 3
+PB9:
+  EVENTOUT: 3
+  I2C1_SDA: 1
+  IR_OUT: 0
+  TIM17_CH1: 2
+PC13: {}
+PC14: {}
+PC15: {}
+PF0: {}
+PF1: {}
+PF6: {}
+PF7: {}

data/gpio_af/STM32F042.yaml

@@ -0,0 +1,186 @@
+PA0:
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  TSC_G1_IO1: 3
+  USART2_CTS: 1
+PA1:
+  EVENTOUT: 0
+  TIM2_CH2: 2
+  TSC_G1_IO2: 3
+  USART2_DE: 1
+  USART2_RTS: 1
+PA10:
+  I2C1_SDA: 4
+  TIM17_BKIN: 0
+  TIM1_CH3: 2
+  TSC_G4_IO2: 3
+  USART1_RX: 1
+PA11:
+  CAN_RX: 4
+  EVENTOUT: 0
+  I2C1_SCL: 5
+  TIM1_CH4: 2
+  TSC_G4_IO3: 3
+  USART1_CTS: 1
+PA12:
+  CAN_TX: 4
+  EVENTOUT: 0
+  I2C1_SDA: 5
+  TIM1_ETR: 2
+  TSC_G4_IO4: 3
+  USART1_DE: 1
+  USART1_RTS: 1
+PA13:
+  IR_OUT: 1
+  SYS_SWDIO: 0
+  USB_NOE: 2
+PA14:
+  SYS_SWCLK: 0
+  USART2_TX: 1
+PA15:
+  EVENTOUT: 3
+  I2S1_WS: 0
+  SPI1_NSS: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART2_RX: 1
+  USB_NOE: 5
+PA2:
+  TIM2_CH3: 2
+  TSC_G1_IO3: 3
+  USART2_TX: 1
+PA3:
+  TIM2_CH4: 2
+  TSC_G1_IO4: 3
+  USART2_RX: 1
+PA4:
+  I2S1_WS: 0
+  SPI1_NSS: 0
+  TIM14_CH1: 4
+  TSC_G2_IO1: 3
+  USART2_CK: 1
+  USB_NOE: 2
+PA5:
+  CEC: 1
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  TSC_G2_IO2: 3
+PA6:
+  EVENTOUT: 6
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM16_CH1: 5
+  TIM1_BKIN: 2
+  TIM3_CH1: 1
+  TSC_G2_IO3: 3
+PA7:
+  EVENTOUT: 6
+  I2S1_SD: 0
+  SPI1_MOSI: 0
+  TIM14_CH1: 4
+  TIM17_CH1: 5
+  TIM1_CH1N: 2
+  TIM3_CH2: 1
+  TSC_G2_IO4: 3
+PA8:
+  CRS_SYNC: 4
+  EVENTOUT: 3
+  RCC_MCO: 0
+  TIM1_CH1: 2
+  USART1_CK: 1
+PA9:
+  I2C1_SCL: 4
+  RCC_MCO: 5
+  TIM1_CH2: 2
+  TSC_G4_IO1: 3
+  USART1_TX: 1
+PB0:
+  EVENTOUT: 0
+  TIM1_CH2N: 2
+  TIM3_CH3: 1
+  TSC_G3_IO2: 3
+PB1:
+  TIM14_CH1: 0
+  TIM1_CH3N: 2
+  TIM3_CH4: 1
+  TSC_G3_IO3: 3
+PB10:
+  CEC: 0
+  I2C1_SCL: 1
+  SPI2_SCK: 5
+  TIM2_CH3: 2
+  TSC_SYNC: 3
+PB11:
+  EVENTOUT: 0
+  I2C1_SDA: 1
+  TIM2_CH4: 2
+PB12:
+  EVENTOUT: 1
+  SPI2_NSS: 0
+  TIM1_BKIN: 2
+PB13:
+  I2C2_SCL: 5
+  SPI2_SCK: 0
+  TIM1_CH1N: 2
+PB14:
+  I2C2_SDA: 5
+  SPI2_MISO: 0
+  TIM1_CH2N: 2
+PB15:
+  SPI2_MOSI: 0
+  TIM1_CH3N: 2
+PB2:
+  TSC_G3_IO4: 3
+PB3:
+  EVENTOUT: 1
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM2_CH2: 2
+  TSC_G5_IO1: 3
+PB4:
+  EVENTOUT: 2
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM17_BKIN: 5
+  TIM3_CH1: 1
+  TSC_G5_IO2: 3
+PB5:
+  I2C1_SMBA: 3
+  I2S1_SD: 0
+  SPI1_MOSI: 0
+  TIM16_BKIN: 2
+  TIM3_CH2: 1
+PB6:
+  I2C1_SCL: 1
+  TIM16_CH1N: 2
+  TSC_G5_IO3: 3
+  USART1_TX: 0
+PB7:
+  I2C1_SDA: 1
+  TIM17_CH1N: 2
+  TSC_G5_IO4: 3
+  USART1_RX: 0
+PB8:
+  CAN_RX: 4
+  CEC: 0
+  I2C1_SCL: 1
+  TIM16_CH1: 2
+  TSC_SYNC: 3
+PB9:
+  CAN_TX: 4
+  EVENTOUT: 3
+  I2C1_SDA: 1
+  IR_OUT: 0
+  SPI2_NSS: 5
+  TIM17_CH1: 2
+PC13: {}
+PC14: {}
+PC15: {}
+PF0:
+  CRS_SYNC: 0
+  I2C1_SDA: 1
+PF1:
+  I2C1_SCL: 1
+PF11: {}

data/gpio_af/STM32F051.yaml

@@ -0,0 +1,213 @@
+PA0:
+  COMP1_INM: 7
+  COMP1_OUT: 7
+  RTC_TAMP2: 0
+  SYS_WKUP1: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  TSC_G1_IO1: 3
+  USART2_CTS: 1
+PA1:
+  COMP1_INP: 7
+  EVENTOUT: 0
+  TIM2_CH2: 2
+  TSC_G1_IO2: 3
+  USART2_DE: 1
+  USART2_RTS: 1
+PA10:
+  TIM17_BKIN: 0
+  TIM1_CH3: 2
+  TSC_G4_IO2: 3
+  USART1_RX: 1
+PA11:
+  COMP1_OUT: 7
+  EVENTOUT: 0
+  TIM1_CH4: 2
+  TSC_G4_IO3: 3
+  USART1_CTS: 1
+PA12:
+  COMP2_OUT: 7
+  EVENTOUT: 0
+  TIM1_ETR: 2
+  TSC_G4_IO4: 3
+  USART1_DE: 1
+  USART1_RTS: 1
+PA13:
+  IR_OUT: 1
+PA14:
+  SYS_SWCLK: 0
+  USART2_TX: 1
+PA15:
+  EVENTOUT: 3
+  I2S1_WS: 0
+  SPI1_NSS: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART2_RX: 1
+PA2:
+  COMP2_INM: 7
+  COMP2_OUT: 7
+  TIM15_CH1: 0
+  TIM2_CH3: 2
+  TSC_G1_IO3: 3
+  USART2_TX: 1
+PA3:
+  COMP2_INP: 7
+  TIM15_CH2: 0
+  TIM2_CH4: 2
+  TSC_G1_IO4: 3
+  USART2_RX: 1
+PA4:
+  COMP1_INM: 7
+  COMP2_INM: 7
+  I2S1_WS: 0
+  SPI1_NSS: 0
+  TIM14_CH1: 4
+  TSC_G2_IO1: 3
+  USART2_CK: 1
+PA5:
+  CEC: 1
+  COMP1_INM: 7
+  COMP2_INM: 7
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  TSC_G2_IO2: 3
+PA6:
+  COMP1_OUT: 7
+  EVENTOUT: 6
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM16_CH1: 5
+  TIM1_BKIN: 2
+  TIM3_CH1: 1
+  TSC_G2_IO3: 3
+PA7:
+  COMP2_OUT: 7
+  EVENTOUT: 6
+  I2S1_SD: 0
+  SPI1_MOSI: 0
+  TIM14_CH1: 4
+  TIM17_CH1: 5
+  TIM1_CH1N: 2
+  TIM3_CH2: 1
+  TSC_G2_IO4: 3
+PA8:
+  EVENTOUT: 3
+  RCC_MCO: 0
+  TIM1_CH1: 2
+  USART1_CK: 1
+PA9:
+  TIM15_BKIN: 0
+  TIM1_CH2: 2
+  TSC_G4_IO1: 3
+  USART1_TX: 1
+PB0:
+  EVENTOUT: 0
+  TIM1_CH2N: 2
+  TIM3_CH3: 1
+  TSC_G3_IO2: 3
+PB1:
+  TIM14_CH1: 0
+  TIM1_CH3N: 2
+  TIM3_CH4: 1
+  TSC_G3_IO3: 3
+PB10:
+  CEC: 0
+  I2C2_SCL: 1
+  TIM2_CH3: 2
+  TSC_SYNC: 3
+PB11:
+  EVENTOUT: 0
+  I2C2_SDA: 1
+  TIM2_CH4: 2
+  TSC_G6_IO1: 3
+PB12:
+  EVENTOUT: 1
+  SPI2_NSS: 0
+  TIM1_BKIN: 2
+  TSC_G6_IO2: 3
+PB13:
+  SPI2_SCK: 0
+  TIM1_CH1N: 2
+  TSC_G6_IO3: 3
+PB14:
+  SPI2_MISO: 0
+  TIM15_CH1: 1
+  TIM1_CH2N: 2
+  TSC_G6_IO4: 3
+PB15:
+  RTC_REFIN: 0
+  SPI2_MOSI: 0
+  TIM15_CH1N: 3
+  TIM15_CH2: 1
+  TIM1_CH3N: 2
+PB2:
+  TSC_G3_IO4: 3
+PB3:
+  EVENTOUT: 1
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM2_CH2: 2
+  TSC_G5_IO1: 3
+PB4:
+  EVENTOUT: 2
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM3_CH1: 1
+  TSC_G5_IO2: 3
+PB5:
+  I2C1_SMBA: 3
+  I2S1_SD: 0
+  SPI1_MOSI: 0
+  TIM16_BKIN: 2
+  TIM3_CH2: 1
+PB6:
+  I2C1_SCL: 1
+  TIM16_CH1N: 2
+  TSC_G5_IO3: 3
+  USART1_TX: 0
+PB7:
+  I2C1_SDA: 1
+  TIM17_CH1N: 2
+  TSC_G5_IO4: 3
+  USART1_RX: 0
+PB8:
+  CEC: 0
+  I2C1_SCL: 1
+  TIM16_CH1: 2
+  TSC_SYNC: 3
+PB9:
+  EVENTOUT: 3
+  I2C1_SDA: 1
+  IR_OUT: 0
+  TIM17_CH1: 2
+PC0: {}
+PC1: {}
+PC10: {}
+PC11: {}
+PC12: {}
+PC13: {}
+PC14: {}
+PC15: {}
+PC2: {}
+PC3: {}
+PC4: {}
+PC5: {}
+PC6:
+  TIM3_CH1: 0
+PC7:
+  TIM3_CH2: 0
+PC8:
+  TIM3_CH3: 1
+PC9:
+  TIM3_CH4: 0
+PD2:
+  TIM3_ETR: 0
+PF0: {}
+PF1: {}
+PF4: {}
+PF5: {}
+PF6: {}
+PF7: {}

data/gpio_af/STM32F052.yaml

@@ -0,0 +1,371 @@
+PA0:
+  COMP1_OUT: 7
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  TSC_G1_IO1: 3
+  USART2_CTS: 1
+  USART4_TX: 4
+PA1:
+  EVENTOUT: 0
+  TIM15_CH1N: 5
+  TIM2_CH2: 2
+  TSC_G1_IO2: 3
+  USART2_DE: 1
+  USART2_RTS: 1
+  USART4_RX: 4
+PA10:
+  TIM17_BKIN: 0
+  TIM1_CH3: 2
+  TSC_G4_IO2: 3
+  USART1_RX: 1
+PA11:
+  CAN_RX: 4
+  COMP1_OUT: 7
+  EVENTOUT: 0
+  TIM1_CH4: 2
+  TSC_G4_IO3: 3
+  USART1_CTS: 1
+PA12:
+  CAN_TX: 4
+  COMP2_OUT: 7
+  EVENTOUT: 0
+  TIM1_ETR: 2
+  TSC_G4_IO4: 3
+  USART1_DE: 1
+  USART1_RTS: 1
+PA13:
+  IR_OUT: 1
+  SYS_SWDIO: 0
+  USB_NOE: 2
+PA14:
+  SYS_SWCLK: 0
+  USART2_TX: 1
+PA15:
+  EVENTOUT: 3
+  I2S1_WS: 0
+  SPI1_NSS: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART2_RX: 1
+  USART4_DE: 4
+  USART4_RTS: 4
+PA2:
+  COMP2_OUT: 7
+  TIM15_CH1: 0
+  TIM2_CH3: 2
+  TSC_G1_IO3: 3
+  USART2_TX: 1
+PA3:
+  TIM15_CH2: 0
+  TIM2_CH4: 2
+  TSC_G1_IO4: 3
+  USART2_RX: 1
+PA4:
+  I2S1_WS: 0
+  SPI1_NSS: 0
+  TIM14_CH1: 4
+  TSC_G2_IO1: 3
+  USART2_CK: 1
+PA5:
+  CEC: 1
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  TSC_G2_IO2: 3
+PA6:
+  COMP1_OUT: 7
+  EVENTOUT: 6
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM16_CH1: 5
+  TIM1_BKIN: 2
+  TIM3_CH1: 1
+  TSC_G2_IO3: 3
+  USART3_CTS: 4
+PA7:
+  COMP2_OUT: 7
+  EVENTOUT: 6
+  I2S1_SD: 0
+  SPI1_MOSI: 0
+  TIM14_CH1: 4
+  TIM17_CH1: 5
+  TIM1_CH1N: 2
+  TIM3_CH2: 1
+  TSC_G2_IO4: 3
+PA8:
+  CRS_SYNC: 4
+  EVENTOUT: 3
+  RCC_MCO: 0
+  TIM1_CH1: 2
+  USART1_CK: 1
+PA9:
+  TIM15_BKIN: 0
+  TIM1_CH2: 2
+  TSC_G4_IO1: 3
+  USART1_TX: 1
+PB0:
+  EVENTOUT: 0
+  TIM1_CH2N: 2
+  TIM3_CH3: 1
+  TSC_G3_IO2: 3
+  USART3_CK: 4
+PB1:
+  TIM14_CH1: 0
+  TIM1_CH3N: 2
+  TIM3_CH4: 1
+  TSC_G3_IO3: 3
+  USART3_DE: 4
+  USART3_RTS: 4
+PB10:
+  CEC: 0
+  I2C2_SCL: 1
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM2_CH3: 2
+  TSC_SYNC: 3
+  USART3_TX: 4
+PB11:
+  EVENTOUT: 0
+  I2C2_SDA: 1
+  TIM2_CH4: 2
+  TSC_G6_IO1: 3
+  USART3_RX: 4
+PB12:
+  EVENTOUT: 1
+  I2S2_WS: 0
+  SPI2_NSS: 0
+  TIM15_BKIN: 5
+  TIM1_BKIN: 2
+  TSC_G6_IO2: 3
+  USART3_CK: 4
+PB13:
+  I2C2_SCL: 5
+  I2S2_CK: 0
+  SPI2_SCK: 0
+  TIM1_CH1N: 2
+  TSC_G6_IO3: 3
+  USART3_CTS: 4
+PB14:
+  I2C2_SDA: 5
+  I2S2_MCK: 0
+  SPI2_MISO: 0
+  TIM15_CH1: 1
+  TIM1_CH2N: 2
+  TSC_G6_IO4: 3
+  USART3_DE: 4
+  USART3_RTS: 4
+PB15:
+  I2S2_SD: 0
+  SPI2_MOSI: 0
+  TIM15_CH1N: 3
+  TIM15_CH2: 1
+  TIM1_CH3N: 2
+PB2:
+  TSC_G3_IO4: 3
+PB3:
+  EVENTOUT: 1
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM2_CH2: 2
+  TSC_G5_IO1: 3
+PB4:
+  EVENTOUT: 2
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM17_BKIN: 5
+  TIM3_CH1: 1
+  TSC_G5_IO2: 3
+PB5:
+  I2C1_SMBA: 3
+  I2S1_SD: 0
+  SPI1_MOSI: 0
+  TIM16_BKIN: 2
+  TIM3_CH2: 1
+PB6:
+  I2C1_SCL: 1
+  TIM16_CH1N: 2
+  TSC_G5_IO3: 3
+  USART1_TX: 0
+PB7:
+  I2C1_SDA: 1
+  TIM17_CH1N: 2
+  TSC_G5_IO4: 3
+  USART1_RX: 0
+  USART4_CTS: 4
+PB8:
+  CAN_RX: 4
+  CEC: 0
+  I2C1_SCL: 1
+  TIM16_CH1: 2
+  TSC_SYNC: 3
+PB9:
+  CAN_TX: 4
+  EVENTOUT: 3
+  I2C1_SDA: 1
+  I2S2_WS: 5
+  IR_OUT: 0
+  SPI2_NSS: 5
+  TIM17_CH1: 2
+PC0:
+  EVENTOUT: 0
+  SYS_I2C: 7
+PC1:
+  EVENTOUT: 0
+  SYS_SPI: 7
+PC10:
+  SYS_TIM15: 7
+  USART3_TX: 1
+  USART4_TX: 0
+PC11:
+  SYS_TIM16: 7
+  USART3_RX: 1
+  USART4_RX: 0
+PC12:
+  SYS_TIM17: 7
+  USART3_CK: 1
+  USART4_CK: 0
+PC13:
+  CEC: 7
+  SYS_IR-Out: 7
+PC14:
+  SYS_COMP: 7
+  SYS_DAC: 7
+PC15:
+  SYS_CAN: 7
+PC2:
+  EVENTOUT: 0
+  I2S2_MCK: 1
+  SPI2_MISO: 1
+  SYS_USART: 7
+PC3:
+  EVENTOUT: 0
+  I2S2_SD: 1
+  SPI2_MOSI: 1
+  SYS_SYSTEM: 7
+PC4:
+  EVENTOUT: 0
+  USART3_TX: 1
+PC5:
+  SYS_TOUCH: 7
+  TSC_G3_IO1: 0
+  USART3_RX: 1
+PC6:
+  SYS_TIM1: 7
+  TIM3_CH1: 0
+PC7:
+  SYS_TIM2: 7
+  TIM3_CH2: 0
+PC8:
+  SYS_TIM3: 7
+  TIM3_CH3: 0
+PC9:
+  SYS_TIM14: 7
+  TIM3_CH4: 0
+PD0:
+  CAN_RX: 0
+  I2S2_WS: 1
+  SPI2_NSS: 1
+PD1:
+  CAN_TX: 0
+  I2S2_CK: 1
+  SPI2_SCK: 1
+PD10:
+  USART3_CK: 0
+PD11:
+  USART3_CTS: 0
+PD12:
+  TSC_G8_IO1: 1
+  USART3_DE: 0
+  USART3_RTS: 0
+PD13:
+  TSC_G8_IO2: 1
+PD14:
+  TSC_G8_IO3: 1
+PD15:
+  CRS_SYNC: 0
+  TSC_G8_IO4: 1
+PD2:
+  TIM3_ETR: 0
+  USART3_DE: 1
+  USART3_RTS: 1
+PD3:
+  I2S2_MCK: 1
+  SPI2_MISO: 1
+  SYS_- new pin (not existing on Stingray 64K): 4
+  USART2_CTS: 0
+PD4:
+  I2S2_SD: 1
+  SPI2_MOSI: 1
+  SYS_- new functionality (not forecasted in Stingray 64K pinout file): 4
+  USART2_DE: 0
+  USART2_RTS: 0
+PD5:
+  USART2_TX: 0
+PD6:
+  USART2_RX: 0
+PD7:
+  USART2_CK: 0
+PD8:
+  SYS_- functionality on new pin (forecasted in Stingray 64K pinout file): 4
+  USART3_TX: 0
+PD9:
+  USART3_RX: 0
+PE0:
+  EVENTOUT: 1
+  TIM16_CH1: 0
+PE1:
+  EVENTOUT: 1
+  TIM17_CH1: 0
+PE10:
+  TIM1_CH2N: 0
+PE11:
+  TIM1_CH2: 0
+PE12:
+  I2S1_WS: 1
+  SPI1_NSS: 1
+  TIM1_CH3N: 0
+PE13:
+  I2S1_CK: 1
+  SPI1_SCK: 1
+  TIM1_CH3: 0
+PE14:
+  I2S1_MCK: 1
+  SPI1_MISO: 1
+  TIM1_CH4: 0
+PE15:
+  I2S1_SD: 1
+  SPI1_MOSI: 1
+  TIM1_BKIN: 0
+PE2:
+  TIM3_ETR: 0
+  TSC_G7_IO1: 1
+PE3:
+  TIM3_CH1: 0
+  TSC_G7_IO2: 1
+PE4:
+  TIM3_CH2: 0
+  TSC_G7_IO3: 1
+PE5:
+  TIM3_CH3: 0
+  TSC_G7_IO4: 1
+PE6:
+  TIM3_CH4: 0
+PE7:
+  TIM1_ETR: 0
+PE8:
+  TIM1_CH1N: 0
+PE9:
+  TIM1_CH1: 0
+PF0:
+  CRS_SYNC: 0
+PF1: {}
+PF10:
+  TIM15_CH2: 0
+PF2:
+  EVENTOUT: 0
+PF3:
+  EVENTOUT: 0
+PF6: {}
+PF9:
+  TIM15_CH1: 0

data/gpio_af/STM32F091.yaml

@@ -0,0 +1,399 @@
+PA0:
+  COMP1_OUT: 7
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  TSC_G1_IO1: 3
+  USART2_CTS: 1
+  USART4_TX: 4
+PA1:
+  EVENTOUT: 0
+  TIM15_CH1N: 5
+  TIM2_CH2: 2
+  TSC_G1_IO2: 3
+  USART2_DE: 1
+  USART2_RTS: 1
+  USART4_RX: 4
+PA10:
+  I2C1_SDA: 4
+  TIM17_BKIN: 0
+  TIM1_CH3: 2
+  TSC_G4_IO2: 3
+  USART1_RX: 1
+PA11:
+  CAN_RX: 4
+  COMP1_OUT: 7
+  EVENTOUT: 0
+  I2C2_SCL: 5
+  TIM1_CH4: 2
+  TSC_G4_IO3: 3
+  USART1_CTS: 1
+PA12:
+  CAN_TX: 4
+  COMP2_OUT: 7
+  EVENTOUT: 0
+  I2C2_SDA: 5
+  TIM1_ETR: 2
+  TSC_G4_IO4: 3
+  USART1_DE: 1
+  USART1_RTS: 1
+PA13:
+  IR_OUT: 1
+  SYS_SWDIO: 0
+  USB_OE: 2
+PA14:
+  SYS_SWCLK: 0
+  USART2_TX: 1
+PA15:
+  EVENTOUT: 3
+  I2S1_WS: 0
+  SPI1_NSS: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART2_RX: 1
+  USART4_DE: 4
+  USART4_RTS: 4
+PA2:
+  COMP2_OUT: 7
+  TIM15_CH1: 0
+  TIM2_CH3: 2
+  TSC_G1_IO3: 3
+  USART2_TX: 1
+PA3:
+  TIM15_CH2: 0
+  TIM2_CH4: 2
+  TSC_G1_IO4: 3
+  USART2_RX: 1
+PA4:
+  I2S1_WS: 0
+  SPI1_NSS: 0
+  TIM14_CH1: 4
+  TSC_G2_IO1: 3
+  USART2_CK: 1
+  USART6_TX: 5
+PA5:
+  CEC: 1
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  TSC_G2_IO2: 3
+  USART6_RX: 5
+PA6:
+  COMP1_OUT: 7
+  EVENTOUT: 6
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM16_CH1: 5
+  TIM1_BKIN: 2
+  TIM3_CH1: 1
+  TSC_G2_IO3: 3
+  USART3_CTS: 4
+PA7:
+  COMP2_OUT: 7
+  EVENTOUT: 6
+  I2S1_SD: 0
+  SPI1_MOSI: 0
+  TIM14_CH1: 4
+  TIM17_CH1: 5
+  TIM1_CH1N: 2
+  TIM3_CH2: 1
+  TSC_G2_IO4: 3
+PA8:
+  CRS_SYNC: 4
+  EVENTOUT: 3
+  RCC_MCO: 0
+  TIM1_CH1: 2
+  USART1_CK: 1
+PA9:
+  I2C1_SCL: 4
+  RCC_MCO: 5
+  TIM15_BKIN: 0
+  TIM1_CH2: 2
+  TSC_G4_IO1: 3
+  USART1_TX: 1
+PB0:
+  EVENTOUT: 0
+  TIM1_CH2N: 2
+  TIM3_CH3: 1
+  TSC_G3_IO2: 3
+  USART3_CK: 4
+PB1:
+  TIM14_CH1: 0
+  TIM1_CH3N: 2
+  TIM3_CH4: 1
+  TSC_G3_IO3: 3
+  USART3_DE: 4
+  USART3_RTS: 4
+PB10:
+  CEC: 0
+  I2C2_SCL: 1
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM2_CH3: 2
+  TSC_SYNC: 3
+  USART3_TX: 4
+PB11:
+  EVENTOUT: 0
+  I2C2_SDA: 1
+  TIM2_CH4: 2
+  TSC_G6_IO1: 3
+  USART3_RX: 4
+PB12:
+  EVENTOUT: 1
+  I2S2_WS: 0
+  SPI2_NSS: 0
+  TIM15_BKIN: 5
+  TIM1_BKIN: 2
+  TSC_G6_IO2: 3
+  USART3_CK: 4
+PB13:
+  I2C2_SCL: 5
+  I2S2_CK: 0
+  SPI2_SCK: 0
+  TIM1_CH1N: 2
+  TSC_G6_IO3: 3
+  USART3_CTS: 4
+PB14:
+  I2C2_SDA: 5
+  I2S2_MCK: 0
+  SPI2_MISO: 0
+  TIM15_CH1: 1
+  TIM1_CH2N: 2
+  TSC_G6_IO4: 3
+  USART3_DE: 4
+  USART3_RTS: 4
+PB15:
+  I2S2_SD: 0
+  SPI2_MOSI: 0
+  TIM15_CH1N: 3
+  TIM15_CH2: 1
+  TIM1_CH3N: 2
+PB2:
+  TSC_G3_IO4: 3
+PB3:
+  EVENTOUT: 1
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM2_CH2: 2
+  TSC_G5_IO1: 3
+  USART5_TX: 4
+PB4:
+  EVENTOUT: 2
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM17_BKIN: 5
+  TIM3_CH1: 1
+  TSC_G5_IO2: 3
+  USART5_RX: 4
+PB5:
+  I2C1_SMBA: 3
+  I2S1_SD: 0
+  SPI1_MOSI: 0
+  TIM16_BKIN: 2
+  TIM3_CH2: 1
+  USART5_CK: 4
+  USART5_DE: 4
+  USART5_RTS: 4
+PB6:
+  I2C1_SCL: 1
+  TIM16_CH1N: 2
+  TSC_G5_IO3: 3
+  USART1_TX: 0
+PB7:
+  I2C1_SDA: 1
+  TIM17_CH1N: 2
+  TSC_G5_IO4: 3
+  USART1_RX: 0
+  USART4_CTS: 4
+PB8:
+  CAN_RX: 4
+  CEC: 0
+  I2C1_SCL: 1
+  TIM16_CH1: 2
+  TSC_SYNC: 3
+PB9:
+  CAN_TX: 4
+  EVENTOUT: 3
+  I2C1_SDA: 1
+  I2S2_WS: 5
+  IR_OUT: 0
+  SPI2_NSS: 5
+  TIM17_CH1: 2
+PC0:
+  EVENTOUT: 0
+  USART6_TX: 2
+  USART7_TX: 1
+PC1:
+  EVENTOUT: 0
+  USART6_RX: 2
+  USART7_RX: 1
+PC10:
+  USART3_TX: 1
+  USART4_TX: 0
+PC11:
+  USART3_RX: 1
+  USART4_RX: 0
+PC12:
+  USART3_CK: 1
+  USART4_CK: 0
+  USART5_TX: 2
+PC13: {}
+PC14: {}
+PC15: {}
+PC2:
+  EVENTOUT: 0
+  I2S2_MCK: 1
+  SPI2_MISO: 1
+  USART8_TX: 2
+PC3:
+  EVENTOUT: 0
+  I2S2_SD: 1
+  SPI2_MOSI: 1
+  USART8_RX: 2
+PC4:
+  EVENTOUT: 0
+  USART3_TX: 1
+PC5:
+  TSC_G3_IO1: 0
+  USART3_RX: 1
+PC6:
+  TIM3_CH1: 0
+  USART7_TX: 1
+PC7:
+  TIM3_CH2: 0
+  USART7_RX: 1
+PC8:
+  TIM3_CH3: 0
+  USART8_TX: 1
+PC9:
+  TIM3_CH4: 0
+  USART8_RX: 1
+PD0:
+  CAN_RX: 0
+  I2S2_WS: 1
+  SPI2_NSS: 1
+PD1:
+  CAN_TX: 0
+  I2S2_CK: 1
+  SPI2_SCK: 1
+PD10:
+  USART3_CK: 0
+PD11:
+  USART3_CTS: 0
+PD12:
+  TSC_G8_IO1: 1
+  USART3_DE: 0
+  USART3_RTS: 0
+  USART8_CK: 2
+  USART8_RTS: 2
+PD13:
+  TSC_G8_IO2: 1
+  USART8_TX: 0
+PD14:
+  TSC_G8_IO3: 1
+  USART8_RX: 0
+PD15:
+  CRS_SYNC: 0
+  TSC_G8_IO4: 1
+  USART7_CK: 2
+  USART7_RTS: 2
+PD2:
+  TIM3_ETR: 0
+  USART3_DE: 1
+  USART3_RTS: 1
+  USART5_RX: 2
+PD3:
+  I2S2_MCK: 1
+  SPI2_MISO: 1
+  USART2_CTS: 0
+PD4:
+  I2S2_SD: 1
+  SPI2_MOSI: 1
+  USART2_DE: 0
+  USART2_RTS: 0
+PD5:
+  USART2_TX: 0
+PD6:
+  USART2_RX: 0
+PD7:
+  USART2_CK: 0
+PD8:
+  USART3_TX: 0
+PD9:
+  USART3_RX: 0
+PE0:
+  EVENTOUT: 1
+  TIM16_CH1: 0
+PE1:
+  EVENTOUT: 1
+  TIM17_CH1: 0
+PE10:
+  TIM1_CH2N: 0
+  USART5_TX: 1
+PE11:
+  TIM1_CH2: 0
+  USART5_RX: 1
+PE12:
+  I2S1_WS: 1
+  SPI1_NSS: 1
+  TIM1_CH3N: 0
+PE13:
+  I2S1_CK: 1
+  SPI1_SCK: 1
+  TIM1_CH3: 0
+PE14:
+  I2S1_MCK: 1
+  SPI1_MISO: 1
+  TIM1_CH4: 0
+PE15:
+  I2S1_SD: 1
+  SPI1_MOSI: 1
+  TIM1_BKIN: 0
+PE2:
+  TIM3_ETR: 0
+  TSC_G7_IO1: 1
+PE3:
+  TIM3_CH1: 0
+  TSC_G7_IO2: 1
+PE4:
+  TIM3_CH2: 0
+  TSC_G7_IO3: 1
+PE5:
+  TIM3_CH3: 0
+  TSC_G7_IO4: 1
+PE6:
+  TIM3_CH4: 0
+PE7:
+  TIM1_ETR: 0
+  USART5_CK: 1
+  USART5_DE: 1
+  USART5_RTS: 1
+PE8:
+  TIM1_CH1N: 0
+  USART4_TX: 1
+PE9:
+  TIM1_CH1: 0
+  USART4_RX: 1
+PF0:
+  CRS_SYNC: 0
+  I2C1_SDA: 1
+PF1:
+  I2C1_SCL: 1
+PF10:
+  TIM15_CH2: 0
+  USART6_RX: 1
+PF11: {}
+PF2:
+  EVENTOUT: 0
+  USART7_CK: 2
+  USART7_RTS: 2
+  USART7_TX: 1
+PF3:
+  EVENTOUT: 0
+  USART6_CK: 2
+  USART6_RTS: 2
+  USART7_RX: 1
+PF6: {}
+PF9:
+  TIM15_CH1: 0
+  USART6_TX: 1

data/gpio_af/STM32F217.yaml

@@ -0,0 +1,565 @@
+PA0:
+  ETH_CRS: 11
+  SYS_WKUP: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM5_CH1: 2
+  TIM8_ETR: 3
+  UART4_TX: 8
+  USART2_CTS: 7
+PA1:
+  ETH_REF_CLK: 11
+  ETH_RX_CLK: 11
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  UART4_RX: 8
+  USART2_RTS: 7
+PA10:
+  DCMI_D1: 13
+  TIM1_CH3: 1
+  USART1_RX: 7
+  USB_OTG_FS_ID: 10
+PA11:
+  CAN1_RX: 9
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USB_OTG_FS_DM: 10
+PA12:
+  CAN1_TX: 9
+  TIM1_ETR: 1
+  USART1_RTS: 7
+  USB_OTG_FS_DP: 10
+PA13:
+  SYS_JTMS-SWDIO: 0
+PA14:
+  SYS_JTCK-SWCLK: 0
+PA15:
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+PA2:
+  ETH_MDIO: 11
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  TIM9_CH1: 3
+  USART2_TX: 7
+PA3:
+  ETH_COL: 11
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  TIM9_CH2: 3
+  USART2_RX: 7
+  USB_OTG_HS_ULPI_D0: 10
+PA4:
+  DCMI_HSYNC: 13
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  USART2_CK: 7
+  USB_OTG_HS_SOF: 12
+PA5:
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM8_CH1N: 3
+  USB_OTG_HS_ULPI_CK: 10
+PA6:
+  DCMI_PIXCLK: 13
+  SPI1_MISO: 5
+  TIM13_CH1: 9
+  TIM1_BKIN: 1
+  TIM3_CH1: 2
+  TIM8_BKIN: 3
+PA7:
+  ETH_CRS_DV: 11
+  ETH_RX_DV: 11
+  SPI1_MOSI: 5
+  TIM14_CH1: 9
+  TIM1_CH1N: 1
+  TIM3_CH2: 2
+  TIM8_CH1N: 3
+PA8:
+  I2C3_SCL: 4
+  RCC_MCO_1: 0
+  TIM1_CH1: 1
+  USART1_CK: 7
+  USB_OTG_FS_SOF: 10
+PA9:
+  DCMI_D0: 13
+  I2C3_SMBA: 4
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  ETH_RXD2: 11
+  TIM1_CH2N: 1
+  TIM3_CH3: 2
+  TIM8_CH2N: 3
+  USB_OTG_HS_ULPI_D1: 10
+PB1:
+  ETH_RXD3: 11
+  TIM1_CH3N: 1
+  TIM3_CH4: 2
+  TIM8_CH3N: 3
+  USB_OTG_HS_ULPI_D2: 10
+PB10:
+  ETH_RX_ER: 11
+  I2C2_SCL: 4
+  I2S2_SCK: 5
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+  USART3_TX: 7
+  USB_OTG_HS_ULPI_D3: 10
+PB11:
+  ETH_TX_EN: 11
+  I2C2_SDA: 4
+  TIM2_CH4: 1
+  USART3_RX: 7
+  USB_OTG_HS_ULPI_D4: 10
+PB12:
+  CAN2_RX: 9
+  ETH_TXD0: 11
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM1_BKIN: 1
+  USART3_CK: 7
+  USB_OTG_HS_ID: 12
+  USB_OTG_HS_ULPI_D5: 10
+PB13:
+  CAN2_TX: 9
+  ETH_TXD1: 11
+  I2S2_SCK: 5
+  SPI2_SCK: 5
+  TIM1_CH1N: 1
+  USART3_CTS: 7
+  USB_OTG_HS_ULPI_D6: 10
+  USB_OTG_HS_VBUS: 12
+PB14:
+  SPI2_MISO: 5
+  TIM12_CH1: 9
+  TIM1_CH2N: 1
+  TIM8_CH2N: 3
+  USART3_RTS: 7
+  USB_OTG_HS_DM: 12
+PB15:
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM12_CH2: 9
+  TIM1_CH3N: 1
+  TIM8_CH3N: 3
+  USB_OTG_HS_DP: 12
+PB2: {}
+PB3:
+  I2S3_SCK: 6
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+PB4:
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM3_CH1: 2
+PB5:
+  CAN2_RX: 9
+  DCMI_D10: 13
+  ETH_PPS_OUT: 11
+  I2C1_SMBA: 4
+  I2S3_SD: 6
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM3_CH2: 2
+  USB_OTG_HS_ULPI_D7: 10
+PB6:
+  CAN2_TX: 9
+  DCMI_D5: 13
+  I2C1_SCL: 4
+  TIM4_CH1: 2
+  USART1_TX: 7
+PB7:
+  DCMI_VSYNC: 13
+  FSMC_NL: 12
+  I2C1_SDA: 4
+  TIM4_CH2: 2
+  USART1_RX: 7
+PB8:
+  CAN1_RX: 9
+  DCMI_D6: 13
+  ETH_TXD3: 11
+  I2C1_SCL: 4
+  SDIO_D4: 12
+  TIM10_CH1: 3
+  TIM4_CH3: 2
+PB9:
+  CAN1_TX: 9
+  DCMI_D7: 13
+  I2C1_SDA: 4
+  I2S2_WS: 5
+  SDIO_D5: 12
+  SPI2_NSS: 5
+  TIM11_CH1: 3
+  TIM4_CH4: 2
+PC0:
+  USB_OTG_HS_ULPI_STP: 10
+PC1:
+  ETH_MDC: 11
+PC10:
+  DCMI_D8: 13
+  I2S3_SCK: 6
+  SDIO_D2: 12
+  SPI3_SCK: 6
+  UART4_TX: 8
+  USART3_TX: 7
+PC11:
+  DCMI_D4: 13
+  SDIO_D3: 12
+  SPI3_MISO: 6
+  UART4_RX: 8
+  USART3_RX: 7
+PC12:
+  DCMI_D9: 13
+  I2S3_SD: 6
+  SDIO_CK: 12
+  SPI3_MOSI: 6
+  UART5_TX: 8
+  USART3_CK: 7
+PC13:
+  RTC_AF1: 0
+PC14: {}
+PC15: {}
+PC2:
+  ETH_TXD2: 11
+  SPI2_MISO: 5
+  USB_OTG_HS_ULPI_DIR: 10
+PC3:
+  ETH_TX_CLK: 11
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  USB_OTG_HS_ULPI_NXT: 10
+PC4:
+  ETH_RXD0: 11
+PC5:
+  ETH_RXD1: 11
+PC6:
+  DCMI_D0: 13
+  I2S2_MCK: 5
+  SDIO_D6: 12
+  TIM3_CH1: 2
+  TIM8_CH1: 3
+  USART6_TX: 8
+PC7:
+  DCMI_D1: 13
+  I2S3_MCK: 6
+  SDIO_D7: 12
+  TIM3_CH2: 2
+  TIM8_CH2: 3
+  USART6_RX: 8
+PC8:
+  DCMI_D2: 13
+  SDIO_D0: 12
+  TIM3_CH3: 2
+  TIM8_CH3: 3
+  USART6_CK: 8
+PC9:
+  DCMI_D3: 13
+  I2C3_SDA: 4
+  I2S_CKIN: 5
+  RCC_MCO_2: 0
+  SDIO_D1: 12
+  TIM3_CH4: 2
+  TIM8_CH4: 3
+PD0:
+  CAN1_RX: 9
+  FSMC_D2: 12
+  FSMC_DA2: 12
+PD1:
+  CAN1_TX: 9
+  FSMC_D3: 12
+  FSMC_DA3: 12
+PD10:
+  FSMC_D15: 12
+  FSMC_DA15: 12
+  USART3_CK: 7
+PD11:
+  FSMC_A16: 12
+  FSMC_CLE: 12
+  USART3_CTS: 7
+PD12:
+  FSMC_A17: 12
+  FSMC_ALE: 12
+  TIM4_CH1: 2
+  USART3_RTS: 7
+PD13:
+  FSMC_A18: 12
+  TIM4_CH2: 2
+PD14:
+  FSMC_D0: 12
+  FSMC_DA0: 12
+  TIM4_CH3: 2
+PD15:
+  FSMC_D1: 12
+  FSMC_DA1: 12
+  TIM4_CH4: 2
+PD2:
+  DCMI_D11: 13
+  SDIO_CMD: 12
+  TIM3_ETR: 2
+  UART5_RX: 8
+PD3:
+  FSMC_CLK: 12
+  USART2_CTS: 7
+PD4:
+  FSMC_NOE: 12
+  USART2_RTS: 7
+PD5:
+  FSMC_NWE: 12
+  USART2_TX: 7
+PD6:
+  FSMC_NWAIT: 12
+  USART2_RX: 7
+PD7:
+  FSMC_NCE2: 12
+  FSMC_NE1: 12
+  USART2_CK: 7
+PD8:
+  FSMC_D13: 12
+  FSMC_DA13: 12
+  USART3_TX: 7
+PD9:
+  FSMC_D14: 12
+  FSMC_DA14: 12
+  USART3_RX: 7
+PE0:
+  DCMI_D2: 13
+  FSMC_NBL0: 12
+  TIM4_ETR: 2
+PE1:
+  DCMI_D3: 13
+  FSMC_NBL1: 12
+PE10:
+  FSMC_D7: 12
+  FSMC_DA7: 12
+  TIM1_CH2N: 1
+PE11:
+  FSMC_D8: 12
+  FSMC_DA8: 12
+  TIM1_CH2: 1
+PE12:
+  FSMC_D9: 12
+  FSMC_DA9: 12
+  TIM1_CH3N: 1
+PE13:
+  FSMC_D10: 12
+  FSMC_DA10: 12
+  TIM1_CH3: 1
+PE14:
+  FSMC_D11: 12
+  FSMC_DA11: 12
+  TIM1_CH4: 1
+PE15:
+  FSMC_D12: 12
+  FSMC_DA12: 12
+  TIM1_BKIN: 1
+PE2:
+  ETH_TXD3: 11
+  FSMC_A23: 12
+  SYS_TRACECLK: 0
+PE3:
+  FSMC_A19: 12
+  SYS_TRACED0: 0
+PE4:
+  DCMI_D4: 13
+  FSMC_A20: 12
+  SYS_TRACED1: 0
+PE5:
+  DCMI_D6: 13
+  FSMC_A21: 12
+  SYS_TRACED2: 0
+  TIM9_CH1: 3
+PE6:
+  DCMI_D7: 13
+  FSMC_A22: 12
+  SYS_TRACED3: 0
+  TIM9_CH2: 3
+PE7:
+  FSMC_D4: 12
+  FSMC_DA4: 12
+  TIM1_ETR: 1
+PE8:
+  FSMC_D5: 12
+  FSMC_DA5: 12
+  TIM1_CH1N: 1
+PE9:
+  FSMC_D6: 12
+  FSMC_DA6: 12
+  TIM1_CH1: 1
+PF0:
+  FSMC_A0: 12
+  I2C2_SDA: 4
+PF1:
+  FSMC_A1: 12
+  I2C2_SCL: 4
+PF10:
+  FSMC_INTR: 12
+PF11:
+  DCMI_D12: 13
+PF12:
+  FSMC_A6: 12
+PF13:
+  FSMC_A7: 12
+PF14:
+  FSMC_A8: 12
+PF15:
+  FSMC_A9: 12
+PF2:
+  FSMC_A2: 12
+  I2C2_SMBA: 4
+PF3:
+  FSMC_A3: 12
+PF4:
+  FSMC_A4: 12
+PF5:
+  FSMC_A5: 12
+PF6:
+  FSMC_NIORD: 12
+  TIM10_CH1: 3
+PF7:
+  FSMC_NREG: 12
+  TIM11_CH1: 3
+PF8:
+  FSMC_NIOWR: 12
+  TIM13_CH1: 9
+PF9:
+  FSMC_CD: 12
+  TIM14_CH1: 9
+PG0:
+  FSMC_A10: 12
+PG1:
+  FSMC_A11: 12
+PG10:
+  FSMC_NCE4_1: 12
+  FSMC_NE3: 12
+PG11:
+  ETH_TX_EN: 11
+  FSMC_NCE4_2: 12
+PG12:
+  FSMC_NE4: 12
+  USART6_RTS: 8
+PG13:
+  ETH_TXD0: 11
+  FSMC_A24: 12
+  USART6_CTS: 8
+PG14:
+  ETH_TXD1: 11
+  FSMC_A25: 12
+  USART6_TX: 8
+PG15:
+  DCMI_D13: 13
+  USART6_CTS: 8
+PG2:
+  FSMC_A12: 12
+PG3:
+  FSMC_A13: 12
+PG4:
+  FSMC_A14: 12
+PG5:
+  FSMC_A15: 12
+PG6:
+  FSMC_INT2: 12
+PG7:
+  FSMC_INT3: 12
+  USART6_CK: 8
+PG8:
+  ETH_PPS_OUT: 11
+  USART6_RTS: 8
+PG9:
+  FSMC_NCE3: 12
+  FSMC_NE2: 12
+  USART6_RX: 8
+PH0:
+  RCC_OSC_IN: 0
+PH1:
+  RCC_OSC_OUT: 0
+PH10:
+  DCMI_D1: 13
+  TIM5_CH1: 2
+PH11:
+  DCMI_D2: 13
+  TIM5_CH2: 2
+PH12:
+  DCMI_D3: 13
+  TIM5_CH3: 2
+PH13:
+  CAN1_TX: 9
+  TIM8_CH1N: 3
+PH14:
+  DCMI_D4: 13
+  TIM8_CH2N: 3
+PH15:
+  DCMI_D11: 13
+  TIM8_CH3N: 3
+PH2:
+  ETH_CRS: 11
+PH3:
+  ETH_COL: 11
+PH4:
+  I2C2_SCL: 4
+  USB_OTG_HS_ULPI_NXT: 10
+PH5:
+  I2C2_SDA: 4
+PH6:
+  ETH_RXD2: 11
+  I2C2_SMBA: 4
+  TIM12_CH1: 9
+PH7:
+  ETH_RXD3: 11
+  I2C3_SCL: 4
+PH8:
+  DCMI_HSYNC: 13
+  I2C3_SDA: 4
+PH9:
+  DCMI_D0: 13
+  I2C3_SMBA: 4
+  TIM12_CH2: 9
+PI0:
+  DCMI_D13: 13
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM5_CH4: 2
+PI1:
+  DCMI_D8: 13
+  I2S2_SCK: 5
+  SPI2_SCK: 5
+PI10:
+  ETH_RX_ER: 11
+PI11:
+  USB_OTG_HS_ULPI_DIR: 10
+PI2:
+  DCMI_D9: 13
+  SPI2_MISO: 5
+  TIM8_CH4: 3
+PI3:
+  DCMI_D10: 13
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIM8_ETR: 3
+PI4:
+  DCMI_D5: 13
+  TIM8_BKIN: 3
+PI5:
+  DCMI_VSYNC: 13
+  TIM8_CH1: 3
+PI6:
+  DCMI_D6: 13
+  TIM8_CH2: 3
+PI7:
+  DCMI_D7: 13
+  TIM8_CH3: 3
+PI8:
+  RTC_AF2: 0
+PI9:
+  CAN1_RX: 9

data/gpio_af/STM32F302.yaml

@@ -0,0 +1,294 @@
+PA0:
+  EVENTOUT: 15
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TSC_G1_IO1: 3
+  USART2_CTS: 7
+PA1:
+  EVENTOUT: 15
+  RTC_REFIN: 0
+  TIM15_CH1N: 9
+  TIM2_CH2: 1
+  TSC_G1_IO2: 3
+  USART2_DE: 7
+  USART2_RTS: 7
+PA10:
+  COMP6_OUT: 8
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  I2S2_ext_SD: 5
+  SPI2_MISO: 5
+  TIM17_BKIN: 1
+  TIM1_CH3: 6
+  TIM2_CH4: 10
+  TSC_G4_IO2: 3
+  USART1_RX: 7
+PA11:
+  CAN_RX: 9
+  EVENTOUT: 15
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIM1_BKIN2: 12
+  TIM1_CH1N: 6
+  TIM1_CH4: 11
+  USART1_CTS: 7
+PA12:
+  CAN_TX: 9
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  I2S_CKIN: 5
+  TIM16_CH1: 1
+  TIM1_CH2N: 6
+  TIM1_ETR: 11
+  USART1_DE: 7
+  USART1_RTS: 7
+PA13:
+  EVENTOUT: 15
+  IR_OUT: 5
+  SYS_JTMS-SWDIO: 0
+  TIM16_CH1N: 1
+  TSC_G4_IO3: 3
+  USART3_CTS: 7
+PA14:
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  SYS_JTCK-SWCLK: 0
+  TIM1_BKIN: 6
+  TSC_G4_IO4: 3
+  USART2_TX: 7
+PA15:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  I2S3_WS: 6
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM1_BKIN: 9
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TSC_SYNC: 3
+  USART2_RX: 7
+PA2:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  TIM15_CH1: 9
+  TIM2_CH3: 1
+  TSC_G1_IO3: 3
+  USART2_TX: 7
+PA3:
+  EVENTOUT: 15
+  TIM15_CH2: 9
+  TIM2_CH4: 1
+  TSC_G1_IO4: 3
+  USART2_RX: 7
+PA4:
+  EVENTOUT: 15
+  I2S3_WS: 6
+  SPI3_NSS: 6
+  TSC_G2_IO1: 3
+  USART2_CK: 7
+PA5:
+  EVENTOUT: 15
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TSC_G2_IO2: 3
+PA6:
+  EVENTOUT: 15
+  TIM16_CH1: 1
+  TIM1_BKIN: 6
+  TSC_G2_IO3: 3
+PA7:
+  EVENTOUT: 15
+  TIM17_CH1: 1
+  TIM1_CH1N: 6
+  TSC_G2_IO4: 3
+PA8:
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+  I2C3_SCL: 3
+  I2S2_MCK: 5
+  RCC_MCO: 0
+  TIM1_CH1: 6
+  USART1_CK: 7
+PA9:
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  I2C3_SMBA: 2
+  I2S3_MCK: 5
+  TIM15_BKIN: 9
+  TIM1_CH2: 6
+  TIM2_CH3: 10
+  TSC_G4_IO1: 3
+  USART1_TX: 7
+PB0:
+  EVENTOUT: 15
+  TIM1_CH2N: 6
+  TSC_G3_IO2: 3
+PB1:
+  COMP4_OUT: 8
+  EVENTOUT: 15
+  TIM1_CH3N: 6
+  TSC_G3_IO3: 3
+PB10:
+  EVENTOUT: 15
+  TIM2_CH3: 1
+  TSC_SYNC: 3
+  USART3_TX: 7
+PB11:
+  EVENTOUT: 15
+  TIM2_CH4: 1
+  TSC_G6_IO1: 3
+  USART3_RX: 7
+PB12:
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM1_BKIN: 6
+  TSC_G6_IO2: 3
+  USART3_CK: 7
+PB13:
+  EVENTOUT: 15
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM1_CH1N: 6
+  TSC_G6_IO3: 3
+  USART3_CTS: 7
+PB14:
+  EVENTOUT: 15
+  I2S2_ext_SD: 5
+  SPI2_MISO: 5
+  TIM15_CH1: 1
+  TIM1_CH2N: 6
+  TSC_G6_IO4: 3
+  USART3_DE: 7
+  USART3_RTS: 7
+PB15:
+  EVENTOUT: 15
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM15_CH1N: 2
+  TIM15_CH2: 1
+  TIM1_CH3N: 4
+PB2:
+  EVENTOUT: 15
+  TSC_G3_IO4: 3
+PB3:
+  EVENTOUT: 15
+  I2S3_CK: 6
+  SPI3_SCK: 6
+  SYS_JTDO-TRACESWO: 0
+  TIM2_CH2: 1
+  TSC_G5_IO1: 3
+  USART2_TX: 7
+PB4:
+  EVENTOUT: 15
+  I2S3_ext_SD: 6
+  SPI3_MISO: 6
+  SYS_NJTRST: 0
+  TIM16_CH1: 1
+  TIM17_BKIN: 10
+  TSC_G5_IO2: 3
+  USART2_RX: 7
+PB5:
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  I2C3_SDA: 8
+  I2S3_SD: 6
+  SPI3_MOSI: 6
+  TIM16_BKIN: 1
+  TIM17_CH1: 10
+  USART2_CK: 7
+PB6:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  TIM16_CH1N: 1
+  TSC_G5_IO3: 3
+  USART1_TX: 7
+PB7:
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  TIM17_CH1N: 1
+  TSC_G5_IO4: 3
+  USART1_RX: 7
+PB8:
+  CAN_RX: 9
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  TIM16_CH1: 1
+  TIM1_BKIN: 12
+  TSC_SYNC: 3
+  USART3_RX: 7
+PB9:
+  CAN_TX: 9
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  IR_OUT: 6
+  TIM17_CH1: 1
+  USART3_TX: 7
+PC0:
+  EVENTOUT: 1
+  TIM1_CH1: 2
+PC1:
+  EVENTOUT: 1
+  TIM1_CH2: 2
+PC10:
+  EVENTOUT: 1
+  I2S3_CK: 6
+  SPI3_SCK: 6
+  USART3_TX: 7
+PC11:
+  EVENTOUT: 1
+  I2S3_ext_SD: 6
+  SPI3_MISO: 6
+  USART3_RX: 7
+PC12:
+  EVENTOUT: 1
+  I2S3_SD: 6
+  SPI3_MOSI: 6
+  USART3_CK: 7
+PC13:
+  TIM1_CH1N: 4
+PC14: {}
+PC15: {}
+PC2:
+  EVENTOUT: 1
+  TIM1_CH3: 2
+PC3:
+  EVENTOUT: 1
+  TIM1_BKIN2: 6
+  TIM1_CH4: 2
+PC4:
+  EVENTOUT: 1
+  TIM1_ETR: 2
+  USART1_TX: 7
+PC5:
+  EVENTOUT: 1
+  TIM15_BKIN: 2
+  TSC_G3_IO1: 3
+  USART1_RX: 7
+PC6:
+  COMP6_OUT: 7
+  EVENTOUT: 1
+  I2S2_MCK: 6
+PC7:
+  EVENTOUT: 1
+  I2S3_MCK: 6
+PC8:
+  EVENTOUT: 1
+PC9:
+  EVENTOUT: 1
+  I2C3_SDA: 3
+  I2S_CKIN: 5
+PD2:
+  EVENTOUT: 1
+PF0:
+  I2C2_SDA: 4
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM1_CH3N: 6
+PF1:
+  I2C2_SCL: 4
+  I2S2_CK: 5
+  SPI2_SCK: 5

data/gpio_af/STM32F303.yaml

@@ -0,0 +1,486 @@
+PA0:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM8_BKIN: 9
+  TIM8_ETR: 10
+  TSC_G1_IO1: 3
+  USART2_CTS: 7
+PA1:
+  EVENTOUT: 15
+  RTC_REFIN: 0
+  TIM15_CH1N: 9
+  TIM2_CH2: 1
+  TSC_G1_IO2: 3
+  USART2_DE: 7
+  USART2_RTS: 7
+PA10:
+  COMP6_OUT: 8
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  TIM17_BKIN: 1
+  TIM1_CH3: 6
+  TIM2_CH4: 10
+  TIM8_BKIN: 11
+  TSC_G4_IO2: 3
+  USART1_RX: 7
+PA11:
+  CAN_RX: 9
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  TIM1_BKIN2: 12
+  TIM1_CH1N: 6
+  TIM1_CH4: 11
+  TIM4_CH1: 10
+  USART1_CTS: 7
+  USB_DM: 14
+PA12:
+  CAN_TX: 9
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  TIM16_CH1: 1
+  TIM1_CH2N: 6
+  TIM1_ETR: 11
+  TIM4_CH2: 10
+  USART1_DE: 7
+  USART1_RTS: 7
+  USB_DP: 14
+PA13:
+  EVENTOUT: 15
+  IR_OUT: 5
+  SYS_JTMS-SWDIO: 0
+  TIM16_CH1N: 1
+  TIM4_CH3: 10
+  TSC_G4_IO3: 3
+  USART3_CTS: 7
+PA14:
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  SYS_JTCK-SWCLK: 0
+  TIM1_BKIN: 6
+  TIM8_CH2: 5
+  TSC_G4_IO4: 3
+  USART2_TX: 7
+PA15:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM1_BKIN: 9
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM8_CH1: 2
+  USART2_RX: 7
+PA2:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  TIM15_CH1: 9
+  TIM2_CH3: 1
+  TSC_G1_IO3: 3
+  USART2_TX: 7
+PA3:
+  EVENTOUT: 15
+  TIM15_CH2: 9
+  TIM2_CH4: 1
+  TSC_G1_IO4: 3
+  USART2_RX: 7
+PA4:
+  EVENTOUT: 15
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  TIM3_CH2: 2
+  TSC_G2_IO1: 3
+  USART2_CK: 7
+PA5:
+  EVENTOUT: 15
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TSC_G2_IO2: 3
+PA6:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  SPI1_MISO: 5
+  TIM16_CH1: 1
+  TIM1_BKIN: 6
+  TIM3_CH1: 2
+  TIM8_BKIN: 4
+  TSC_G2_IO3: 3
+PA7:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  SPI1_MOSI: 5
+  TIM17_CH1: 1
+  TIM1_CH1N: 6
+  TIM3_CH2: 2
+  TIM8_CH1N: 4
+  TSC_G2_IO4: 3
+PA8:
+  COMP3_OUT: 8
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+  I2S2_MCK: 5
+  RCC_MCO: 0
+  TIM1_CH1: 6
+  TIM4_ETR: 10
+  USART1_CK: 7
+PA9:
+  COMP5_OUT: 8
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  I2S3_MCK: 5
+  TIM15_BKIN: 9
+  TIM1_CH2: 6
+  TIM2_CH3: 10
+  TSC_G4_IO1: 3
+  USART1_TX: 7
+PB0:
+  EVENTOUT: 15
+  TIM1_CH2N: 6
+  TIM3_CH3: 2
+  TIM8_CH2N: 4
+  TSC_G3_IO2: 3
+PB1:
+  COMP4_OUT: 8
+  EVENTOUT: 15
+  TIM1_CH3N: 6
+  TIM3_CH4: 2
+  TIM8_CH3N: 4
+  TSC_G3_IO3: 3
+PB10:
+  EVENTOUT: 15
+  TIM2_CH3: 1
+  TSC_SYNC: 3
+  USART3_TX: 7
+PB11:
+  EVENTOUT: 15
+  TIM2_CH4: 1
+  TSC_G6_IO1: 3
+  USART3_RX: 7
+PB12:
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM1_BKIN: 6
+  TSC_G6_IO2: 3
+  USART3_CK: 7
+PB13:
+  EVENTOUT: 15
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM1_CH1N: 6
+  TSC_G6_IO3: 3
+  USART3_CTS: 7
+PB14:
+  EVENTOUT: 15
+  I2S2_ext_SD: 5
+  SPI2_MISO: 5
+  TIM15_CH1: 1
+  TIM1_CH2N: 6
+  TSC_G6_IO4: 3
+  USART3_DE: 7
+  USART3_RTS: 7
+PB15:
+  EVENTOUT: 15
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM15_CH1N: 2
+  TIM15_CH2: 1
+  TIM1_CH3N: 4
+PB2:
+  EVENTOUT: 15
+  TSC_G3_IO4: 3
+PB3:
+  EVENTOUT: 15
+  I2S3_CK: 6
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-TRACESWO: 0
+  TIM2_CH2: 1
+  TIM3_ETR: 10
+  TIM4_ETR: 2
+  TIM8_CH1N: 4
+  TSC_G5_IO1: 3
+  USART2_TX: 7
+PB4:
+  EVENTOUT: 15
+  I2S3_ext_SD: 6
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_NJTRST: 0
+  TIM16_CH1: 1
+  TIM17_BKIN: 10
+  TIM3_CH1: 2
+  TIM8_CH2N: 4
+  TSC_G5_IO2: 3
+  USART2_RX: 7
+PB5:
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  I2S3_SD: 6
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM16_BKIN: 1
+  TIM17_CH1: 10
+  TIM3_CH2: 2
+  TIM8_CH3N: 3
+  USART2_CK: 7
+PB6:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  TIM16_CH1N: 1
+  TIM4_CH1: 2
+  TIM8_BKIN2: 10
+  TIM8_CH1: 5
+  TIM8_ETR: 6
+  TSC_G5_IO3: 3
+  USART1_TX: 7
+PB7:
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  TIM17_CH1N: 1
+  TIM3_CH4: 10
+  TIM4_CH2: 2
+  TIM8_BKIN: 5
+  TSC_G5_IO4: 3
+  USART1_RX: 7
+PB8:
+  CAN_RX: 9
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  TIM16_CH1: 1
+  TIM1_BKIN: 12
+  TIM4_CH3: 2
+  TIM8_CH2: 10
+  TSC_SYNC: 3
+PB9:
+  CAN_TX: 9
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  IR_OUT: 6
+  TIM17_CH1: 1
+  TIM4_CH4: 2
+  TIM8_CH3: 10
+PC0:
+  EVENTOUT: 1
+PC1:
+  EVENTOUT: 1
+PC10:
+  EVENTOUT: 1
+  I2S3_CK: 6
+  SPI3_SCK: 6
+  TIM8_CH1N: 4
+  UART4_TX: 5
+  USART3_TX: 7
+PC11:
+  EVENTOUT: 1
+  I2S3_ext_SD: 6
+  SPI3_MISO: 6
+  TIM8_CH2N: 4
+  UART4_RX: 5
+  USART3_RX: 7
+PC12:
+  EVENTOUT: 1
+  I2S3_SD: 6
+  SPI3_MOSI: 6
+  TIM8_CH3N: 4
+  UART5_TX: 5
+  USART3_CK: 7
+PC13:
+  TIM1_CH1N: 4
+PC14: {}
+PC15: {}
+PC2:
+  COMP7_OUT: 3
+  EVENTOUT: 1
+PC3:
+  EVENTOUT: 1
+  TIM1_BKIN2: 6
+PC4:
+  EVENTOUT: 1
+  USART1_TX: 7
+PC5:
+  EVENTOUT: 1
+  TSC_G3_IO1: 3
+  USART1_RX: 7
+PC6:
+  COMP6_OUT: 7
+  EVENTOUT: 1
+  I2S2_MCK: 6
+  TIM3_CH1: 2
+  TIM8_CH1: 4
+PC7:
+  COMP5_OUT: 7
+  EVENTOUT: 1
+  I2S3_MCK: 6
+  TIM3_CH2: 2
+  TIM8_CH2: 4
+PC8:
+  COMP3_OUT: 7
+  EVENTOUT: 1
+  TIM3_CH3: 2
+  TIM8_CH3: 4
+PC9:
+  EVENTOUT: 1
+  I2S_CKIN: 5
+  TIM3_CH4: 2
+  TIM8_BKIN2: 6
+  TIM8_CH4: 4
+PD0:
+  CAN_RX: 7
+  EVENTOUT: 1
+PD1:
+  CAN_TX: 7
+  EVENTOUT: 1
+  TIM8_BKIN2: 6
+  TIM8_CH4: 4
+PD10:
+  EVENTOUT: 1
+  USART3_CK: 7
+PD11:
+  EVENTOUT: 1
+  USART3_CTS: 7
+PD12:
+  EVENTOUT: 1
+  TIM4_CH1: 2
+  TSC_G8_IO1: 3
+  USART3_DE: 7
+  USART3_RTS: 7
+PD13:
+  EVENTOUT: 1
+  TIM4_CH2: 2
+  TSC_G8_IO2: 3
+PD14:
+  EVENTOUT: 1
+  TIM4_CH3: 2
+  TSC_G8_IO3: 3
+PD15:
+  EVENTOUT: 1
+  SPI2_NSS: 6
+  TIM4_CH4: 2
+  TSC_G8_IO4: 3
+PD2:
+  EVENTOUT: 1
+  TIM3_ETR: 2
+  TIM8_BKIN: 4
+  UART5_RX: 5
+PD3:
+  EVENTOUT: 1
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART2_CTS: 7
+PD4:
+  EVENTOUT: 1
+  TIM2_CH2: 2
+  USART2_DE: 7
+  USART2_RTS: 7
+PD5:
+  EVENTOUT: 1
+  USART2_TX: 7
+PD6:
+  EVENTOUT: 1
+  TIM2_CH4: 2
+  USART2_RX: 7
+PD7:
+  EVENTOUT: 1
+  TIM2_CH3: 2
+  USART2_CK: 7
+PD8:
+  EVENTOUT: 1
+  USART3_TX: 7
+PD9:
+  EVENTOUT: 1
+  USART3_RX: 7
+PE0:
+  EVENTOUT: 1
+  TIM16_CH1: 4
+  TIM4_ETR: 2
+  USART1_TX: 7
+PE1:
+  EVENTOUT: 1
+  TIM17_CH1: 4
+  USART1_RX: 7
+PE10:
+  EVENTOUT: 1
+  TIM1_CH2N: 2
+PE11:
+  EVENTOUT: 1
+  TIM1_CH2: 2
+PE12:
+  EVENTOUT: 1
+  TIM1_CH3N: 2
+PE13:
+  EVENTOUT: 1
+  TIM1_CH3: 2
+PE14:
+  EVENTOUT: 1
+  TIM1_BKIN2: 6
+  TIM1_CH4: 2
+PE15:
+  EVENTOUT: 1
+  TIM1_BKIN: 2
+  USART3_RX: 7
+PE2:
+  EVENTOUT: 1
+  SYS_TRACECK: 0
+  TIM3_CH1: 2
+  TSC_G7_IO1: 3
+PE3:
+  EVENTOUT: 1
+  SYS_TRACED0: 0
+  TIM3_CH2: 2
+  TSC_G7_IO2: 3
+PE4:
+  EVENTOUT: 1
+  SYS_TRACED1: 0
+  TIM3_CH3: 2
+  TSC_G7_IO3: 3
+PE5:
+  EVENTOUT: 1
+  SYS_TRACED2: 0
+  TIM3_CH4: 2
+  TSC_G7_IO4: 3
+PE6:
+  EVENTOUT: 1
+  SYS_TRACED3: 0
+PE7:
+  EVENTOUT: 1
+  TIM1_ETR: 2
+PE8:
+  EVENTOUT: 1
+  TIM1_CH1N: 2
+PE9:
+  EVENTOUT: 1
+  TIM1_CH1: 2
+PF0:
+  I2C2_SDA: 4
+  TIM1_CH3N: 6
+PF1:
+  I2C2_SCL: 4
+PF10:
+  EVENTOUT: 1
+  SPI2_SCK: 5
+  TIM15_CH2: 3
+PF2:
+  EVENTOUT: 1
+PF4:
+  COMP1_OUT: 2
+  EVENTOUT: 1
+PF6:
+  EVENTOUT: 1
+  I2C2_SCL: 4
+  TIM4_CH4: 2
+  USART3_DE: 7
+  USART3_RTS: 7
+PF9:
+  EVENTOUT: 1
+  SPI2_SCK: 5
+  TIM15_CH1: 3

data/gpio_af/STM32F303E.yaml

@@ -0,0 +1,667 @@
+PA0:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM8_BKIN: 9
+  TIM8_ETR: 10
+  TSC_G1_IO1: 3
+  USART2_CTS: 7
+PA1:
+  EVENTOUT: 15
+  RTC_REFIN: 0
+  TIM15_CH1N: 9
+  TIM2_CH2: 1
+  TSC_G1_IO2: 3
+  USART2_DE: 7
+  USART2_RTS: 7
+PA10:
+  COMP6_OUT: 8
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  I2S2_ext_SD: 5
+  SPI2_MISO: 5
+  TIM17_BKIN: 1
+  TIM1_CH3: 6
+  TIM2_CH4: 10
+  TIM8_BKIN: 11
+  TSC_G4_IO2: 3
+  USART1_RX: 7
+PA11:
+  CAN_RX: 9
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIM1_BKIN2: 12
+  TIM1_CH1N: 6
+  TIM1_CH4: 11
+  TIM4_CH1: 10
+  USART1_CTS: 7
+PA12:
+  CAN_TX: 9
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  I2S_CKIN: 5
+  TIM16_CH1: 1
+  TIM1_CH2N: 6
+  TIM1_ETR: 11
+  TIM4_CH2: 10
+  USART1_DE: 7
+  USART1_RTS: 7
+PA13:
+  EVENTOUT: 15
+  IR_OUT: 5
+  SYS_JTMS-SWDIO: 0
+  TIM16_CH1N: 1
+  TIM4_CH3: 10
+  TSC_G4_IO3: 3
+  USART3_CTS: 7
+PA14:
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  SYS_JTCK-SWCLK: 0
+  TIM1_BKIN: 6
+  TIM8_CH2: 5
+  TSC_G4_IO4: 3
+  USART2_TX: 7
+PA15:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM1_BKIN: 9
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM8_CH1: 2
+  TSC_SYNC: 3
+  USART2_RX: 7
+PA2:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  TIM15_CH1: 9
+  TIM2_CH3: 1
+  TSC_G1_IO3: 3
+  USART2_TX: 7
+PA3:
+  EVENTOUT: 15
+  TIM15_CH2: 9
+  TIM2_CH4: 1
+  TSC_G1_IO4: 3
+  USART2_RX: 7
+PA4:
+  EVENTOUT: 15
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  TIM3_CH2: 2
+  TSC_G2_IO1: 3
+  USART2_CK: 7
+PA5:
+  EVENTOUT: 15
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TSC_G2_IO2: 3
+PA6:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  SPI1_MISO: 5
+  TIM16_CH1: 1
+  TIM1_BKIN: 6
+  TIM3_CH1: 2
+  TIM8_BKIN: 4
+  TSC_G2_IO3: 3
+PA7:
+  EVENTOUT: 15
+  SPI1_MOSI: 5
+  TIM17_CH1: 1
+  TIM1_CH1N: 6
+  TIM3_CH2: 2
+  TIM8_CH1N: 4
+  TSC_G2_IO4: 3
+PA8:
+  COMP3_OUT: 8
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+  I2C3_SCL: 3
+  I2S2_MCK: 5
+  RCC_MCO: 0
+  TIM1_CH1: 6
+  TIM4_ETR: 10
+  USART1_CK: 7
+PA9:
+  COMP5_OUT: 8
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  I2C3_SMBA: 2
+  I2S3_MCK: 5
+  TIM15_BKIN: 9
+  TIM1_CH2: 6
+  TIM2_CH3: 10
+  TSC_G4_IO1: 3
+  USART1_TX: 7
+PB0:
+  EVENTOUT: 15
+  TIM1_CH2N: 6
+  TIM3_CH3: 2
+  TIM8_CH2N: 4
+  TSC_G3_IO2: 3
+PB1:
+  COMP4_OUT: 8
+  EVENTOUT: 15
+  TIM1_CH3N: 6
+  TIM3_CH4: 2
+  TIM8_CH3N: 4
+  TSC_G3_IO3: 3
+PB10:
+  EVENTOUT: 15
+  TIM2_CH3: 1
+  TSC_SYNC: 3
+  USART3_TX: 7
+PB11:
+  EVENTOUT: 15
+  TIM2_CH4: 1
+  TSC_G6_IO1: 3
+  USART3_RX: 7
+PB12:
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM1_BKIN: 6
+  TSC_G6_IO2: 3
+  USART3_CK: 7
+PB13:
+  EVENTOUT: 15
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM1_CH1N: 6
+  TSC_G6_IO3: 3
+  USART3_CTS: 7
+PB14:
+  EVENTOUT: 15
+  I2S2_ext_SD: 5
+  SPI2_MISO: 5
+  TIM15_CH1: 1
+  TIM1_CH2N: 6
+  TSC_G6_IO4: 3
+  USART3_DE: 7
+  USART3_RTS: 7
+PB15:
+  EVENTOUT: 15
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM15_CH1N: 2
+  TIM15_CH2: 1
+  TIM1_CH3N: 4
+PB2:
+  EVENTOUT: 15
+  TSC_G3_IO4: 3
+PB3:
+  EVENTOUT: 15
+  I2S3_CK: 6
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-TRACESWO: 0
+  TIM2_CH2: 1
+  TIM3_ETR: 10
+  TIM4_ETR: 2
+  TIM8_CH1N: 4
+  TSC_G5_IO1: 3
+  USART2_TX: 7
+PB4:
+  EVENTOUT: 15
+  I2S3_ext_SD: 6
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_NJTRST: 0
+  TIM16_CH1: 1
+  TIM17_BKIN: 10
+  TIM3_CH1: 2
+  TIM8_CH2N: 4
+  TSC_G5_IO2: 3
+  USART2_RX: 7
+PB5:
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  I2C3_SDA: 8
+  I2S3_SD: 6
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM16_BKIN: 1
+  TIM17_CH1: 10
+  TIM3_CH2: 2
+  TIM8_CH3N: 3
+  USART2_CK: 7
+PB6:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  TIM16_CH1N: 1
+  TIM4_CH1: 2
+  TIM8_BKIN2: 10
+  TIM8_CH1: 5
+  TIM8_ETR: 6
+  TSC_G5_IO3: 3
+  USART1_TX: 7
+PB7:
+  EVENTOUT: 15
+  FMC_NL: 12
+  I2C1_SDA: 4
+  TIM17_CH1N: 1
+  TIM3_CH4: 10
+  TIM4_CH2: 2
+  TIM8_BKIN: 5
+  TSC_G5_IO4: 3
+  USART1_RX: 7
+PB8:
+  CAN_RX: 9
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  TIM16_CH1: 1
+  TIM1_BKIN: 12
+  TIM4_CH3: 2
+  TIM8_CH2: 10
+  TSC_SYNC: 3
+  USART3_RX: 7
+PB9:
+  CAN_TX: 9
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  IR_OUT: 6
+  TIM17_CH1: 1
+  TIM4_CH4: 2
+  TIM8_CH3: 10
+  USART3_TX: 7
+PC0:
+  EVENTOUT: 1
+  TIM1_CH1: 2
+PC1:
+  EVENTOUT: 1
+  TIM1_CH2: 2
+PC10:
+  EVENTOUT: 1
+  I2S3_CK: 6
+  SPI3_SCK: 6
+  TIM8_CH1N: 4
+  UART4_TX: 5
+  USART3_TX: 7
+PC11:
+  EVENTOUT: 1
+  I2S3_ext_SD: 6
+  SPI3_MISO: 6
+  TIM8_CH2N: 4
+  UART4_RX: 5
+  USART3_RX: 7
+PC12:
+  EVENTOUT: 1
+  I2S3_SD: 6
+  SPI3_MOSI: 6
+  TIM8_CH3N: 4
+  UART5_TX: 5
+  USART3_CK: 7
+PC13:
+  EVENTOUT: 1
+  TIM1_CH1N: 4
+PC14:
+  EVENTOUT: 1
+PC15:
+  EVENTOUT: 1
+PC2:
+  COMP7_OUT: 3
+  EVENTOUT: 1
+  TIM1_CH3: 2
+PC3:
+  EVENTOUT: 1
+  TIM1_BKIN2: 6
+  TIM1_CH4: 2
+PC4:
+  EVENTOUT: 1
+  TIM1_ETR: 2
+  USART1_TX: 7
+PC5:
+  EVENTOUT: 1
+  TIM15_BKIN: 2
+  TSC_G3_IO1: 3
+  USART1_RX: 7
+PC6:
+  COMP6_OUT: 7
+  EVENTOUT: 1
+  I2S2_MCK: 6
+  TIM3_CH1: 2
+  TIM8_CH1: 4
+PC7:
+  COMP5_OUT: 7
+  EVENTOUT: 1
+  I2S3_MCK: 6
+  TIM3_CH2: 2
+  TIM8_CH2: 4
+PC8:
+  COMP3_OUT: 7
+  EVENTOUT: 1
+  TIM3_CH3: 2
+  TIM8_CH3: 4
+PC9:
+  EVENTOUT: 1
+  I2C3_SDA: 3
+  I2S_CKIN: 5
+  TIM3_CH4: 2
+  TIM8_BKIN2: 6
+  TIM8_CH4: 4
+PD0:
+  CAN_RX: 7
+  EVENTOUT: 1
+  FMC_D2: 12
+PD1:
+  CAN_TX: 7
+  EVENTOUT: 1
+  FMC_D3: 12
+  TIM8_BKIN2: 6
+  TIM8_CH4: 4
+PD10:
+  EVENTOUT: 1
+  FMC_D15: 12
+  USART3_CK: 7
+PD11:
+  EVENTOUT: 1
+  FMC_A16: 12
+  USART3_CTS: 7
+PD12:
+  EVENTOUT: 1
+  FMC_A17: 12
+  TIM4_CH1: 2
+  TSC_G8_IO1: 3
+  USART3_DE: 7
+  USART3_RTS: 7
+PD13:
+  EVENTOUT: 1
+  FMC_A18: 12
+  TIM4_CH2: 2
+  TSC_G8_IO2: 3
+PD14:
+  EVENTOUT: 1
+  FMC_D0: 12
+  TIM4_CH3: 2
+  TSC_G8_IO3: 3
+PD15:
+  EVENTOUT: 1
+  FMC_D1: 12
+  SPI2_NSS: 6
+  TIM4_CH4: 2
+  TSC_G8_IO4: 3
+PD2:
+  EVENTOUT: 1
+  TIM3_ETR: 2
+  TIM8_BKIN: 4
+  UART5_RX: 5
+PD3:
+  EVENTOUT: 1
+  FMC_CLK: 12
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART2_CTS: 7
+PD4:
+  EVENTOUT: 1
+  FMC_NOE: 12
+  TIM2_CH2: 2
+  USART2_DE: 7
+  USART2_RTS: 7
+PD5:
+  EVENTOUT: 1
+  FMC_NWE: 12
+  USART2_TX: 7
+PD6:
+  EVENTOUT: 1
+  FMC_NWAIT: 12
+  TIM2_CH4: 2
+  USART2_RX: 7
+PD7:
+  EVENTOUT: 1
+  FMC_NCE2: 12
+  FMC_NE1: 12
+  TIM2_CH3: 2
+  USART2_CK: 7
+PD8:
+  EVENTOUT: 1
+  FMC_D13: 12
+  USART3_TX: 7
+PD9:
+  EVENTOUT: 1
+  FMC_D14: 12
+  USART3_RX: 7
+PE0:
+  EVENTOUT: 1
+  FMC_NBL0: 12
+  TIM16_CH1: 4
+  TIM20_ETR: 6
+  TIM4_ETR: 2
+  USART1_TX: 7
+PE1:
+  EVENTOUT: 1
+  FMC_NBL1: 12
+  TIM17_CH1: 4
+  TIM20_CH4: 6
+  USART1_RX: 7
+PE10:
+  EVENTOUT: 1
+  FMC_D7: 12
+  TIM1_CH2N: 2
+PE11:
+  EVENTOUT: 1
+  FMC_D8: 12
+  SPI4_NSS: 5
+  TIM1_CH2: 2
+PE12:
+  EVENTOUT: 1
+  FMC_D9: 12
+  SPI4_SCK: 5
+  TIM1_CH3N: 2
+PE13:
+  EVENTOUT: 1
+  FMC_D10: 12
+  SPI4_MISO: 5
+  TIM1_CH3: 2
+PE14:
+  EVENTOUT: 1
+  FMC_D11: 12
+  SPI4_MOSI: 5
+  TIM1_BKIN2: 6
+  TIM1_CH4: 2
+PE15:
+  EVENTOUT: 1
+  FMC_D12: 12
+  TIM1_BKIN: 2
+  USART3_RX: 7
+PE2:
+  EVENTOUT: 1
+  FMC_A23: 12
+  SPI4_SCK: 5
+  SYS_TRACECK: 0
+  TIM20_CH1: 6
+  TIM3_CH1: 2
+  TSC_G7_IO1: 3
+PE3:
+  EVENTOUT: 1
+  FMC_A19: 12
+  SPI4_NSS: 5
+  SYS_TRACED0: 0
+  TIM20_CH2: 6
+  TIM3_CH2: 2
+  TSC_G7_IO2: 3
+PE4:
+  EVENTOUT: 1
+  FMC_A20: 12
+  SPI4_NSS: 5
+  SYS_TRACED1: 0
+  TIM20_CH1N: 6
+  TIM3_CH3: 2
+  TSC_G7_IO3: 3
+PE5:
+  EVENTOUT: 1
+  FMC_A21: 12
+  SPI4_MISO: 5
+  SYS_TRACED2: 0
+  TIM20_CH2N: 6
+  TIM3_CH4: 2
+  TSC_G7_IO4: 3
+PE6:
+  EVENTOUT: 1
+  FMC_A22: 12
+  SPI4_MOSI: 5
+  SYS_TRACED3: 0
+  TIM20_CH3N: 6
+PE7:
+  EVENTOUT: 1
+  FMC_D4: 12
+  TIM1_ETR: 2
+PE8:
+  EVENTOUT: 1
+  FMC_D5: 12
+  TIM1_CH1N: 2
+PE9:
+  EVENTOUT: 1
+  FMC_D6: 12
+  TIM1_CH1: 2
+PF0:
+  EVENTOUT: 1
+  I2C2_SDA: 4
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM1_CH3N: 6
+PF1:
+  EVENTOUT: 1
+  I2C2_SCL: 4
+  I2S2_CK: 5
+  SPI2_SCK: 5
+PF10:
+  EVENTOUT: 1
+  FMC_INTR: 12
+  SPI2_SCK: 5
+  TIM15_CH2: 3
+  TIM20_BKIN2: 2
+PF11:
+  EVENTOUT: 1
+  TIM20_ETR: 2
+PF12:
+  EVENTOUT: 1
+  FMC_A6: 12
+  TIM20_CH1: 2
+PF13:
+  EVENTOUT: 1
+  FMC_A7: 12
+  TIM20_CH2: 2
+PF14:
+  EVENTOUT: 1
+  FMC_A8: 12
+  TIM20_CH3: 2
+PF15:
+  EVENTOUT: 1
+  FMC_A9: 12
+  TIM20_CH4: 2
+PF2:
+  EVENTOUT: 1
+  FMC_A2: 12
+  TIM20_CH3: 2
+PF3:
+  EVENTOUT: 1
+  FMC_A3: 12
+  TIM20_CH4: 2
+PF4:
+  COMP1_OUT: 2
+  EVENTOUT: 1
+  FMC_A4: 12
+  TIM20_CH1N: 3
+PF5:
+  EVENTOUT: 1
+  FMC_A5: 12
+  TIM20_CH2N: 2
+PF6:
+  EVENTOUT: 1
+  FMC_NIORD: 12
+  I2C2_SCL: 4
+  TIM4_CH4: 2
+  USART3_DE: 7
+  USART3_RTS: 7
+PF7:
+  EVENTOUT: 1
+  FMC_NREG: 12
+  TIM20_BKIN: 2
+PF8:
+  EVENTOUT: 1
+  FMC_NIOWR: 12
+  TIM20_BKIN2: 2
+PF9:
+  EVENTOUT: 1
+  FMC_CD: 12
+  SPI2_SCK: 5
+  TIM15_CH1: 3
+  TIM20_BKIN: 2
+PG0:
+  EVENTOUT: 1
+  FMC_A10: 12
+  TIM20_CH1N: 2
+PG1:
+  EVENTOUT: 1
+  FMC_A11: 12
+  TIM20_CH2N: 2
+PG10:
+  EVENTOUT: 1
+  FMC_NCE4_1: 12
+  FMC_NE3: 12
+PG11:
+  EVENTOUT: 1
+  FMC_NCE4_2: 12
+PG12:
+  EVENTOUT: 1
+  FMC_NE4: 12
+PG13:
+  EVENTOUT: 1
+  FMC_A24: 12
+PG14:
+  EVENTOUT: 1
+  FMC_A25: 12
+PG15:
+  EVENTOUT: 1
+PG2:
+  EVENTOUT: 1
+  FMC_A12: 12
+  TIM20_CH3N: 2
+PG3:
+  EVENTOUT: 1
+  FMC_A13: 12
+  TIM20_BKIN: 2
+PG4:
+  EVENTOUT: 1
+  FMC_A14: 12
+  TIM20_BKIN2: 2
+PG5:
+  EVENTOUT: 1
+  FMC_A15: 12
+  TIM20_ETR: 2
+PG6:
+  EVENTOUT: 1
+  FMC_INT2: 12
+PG7:
+  EVENTOUT: 1
+  FMC_INT3: 12
+PG8:
+  EVENTOUT: 1
+PG9:
+  EVENTOUT: 1
+  FMC_NCE3: 12
+  FMC_NE2: 12
+PH0:
+  EVENTOUT: 1
+  FMC_A0: 12
+  TIM20_CH1: 2
+PH1:
+  EVENTOUT: 1
+  FMC_A1: 12
+  TIM20_CH2: 2
+PH2:
+  EVENTOUT: 1

data/gpio_af/STM32F333.yaml

@@ -0,0 +1,296 @@
+PA0:
+  EVENTOUT: 15
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TSC_G1_IO1: 3
+  USART2_CTS: 7
+PA1:
+  EVENTOUT: 15
+  TIM15_CH1N: 9
+  TIM2_CH2: 1
+  TSC_G1_IO2: 3
+  USART2_DE: 7
+  USART2_RTS: 7
+PA10:
+  COMP6_OUT: 8
+  EVENTOUT: 15
+  HRTIM1_CHB1: 13
+  TIM17_BKIN: 1
+  TIM1_CH3: 6
+  TIM2_CH4: 10
+  TSC_G4_IO2: 3
+  USART1_RX: 7
+PA11:
+  CAN_RX: 9
+  EVENTOUT: 15
+  HRTIM1_CHB2: 13
+  TIM1_BKIN2: 12
+  TIM1_CH1N: 6
+  TIM1_CH4: 11
+  USART1_CTS: 7
+PA12:
+  CAN_TX: 9
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  HRTIM1_FLT1: 13
+  TIM16_CH1: 1
+  TIM1_CH2N: 6
+  TIM1_ETR: 11
+  USART1_DE: 7
+  USART1_RTS: 7
+PA13:
+  EVENTOUT: 15
+  IR_OUT: 5
+  SYS_JTMS-SWDIO: 0
+  TIM16_CH1N: 1
+  TSC_G4_IO3: 3
+  USART3_CTS: 7
+PA14:
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  SYS_JTCK-SWCLK: 0
+  TIM1_BKIN: 6
+  TSC_G4_IO4: 3
+  USART2_TX: 7
+PA15:
+  EVENTOUT: 15
+  HRTIM1_FLT2: 13
+  I2C1_SCL: 4
+  SPI1_NSS: 5
+  SYS_JTDI: 0
+  TIM1_BKIN: 9
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TSC_SYNC: 3
+  USART2_RX: 7
+PA2:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  TIM15_CH1: 9
+  TIM2_CH3: 1
+  TSC_G1_IO3: 3
+  USART2_TX: 7
+PA3:
+  EVENTOUT: 15
+  TIM15_CH2: 9
+  TIM2_CH4: 1
+  TSC_G1_IO4: 3
+  USART2_RX: 7
+PA4:
+  EVENTOUT: 15
+  SPI1_NSS: 5
+  TIM3_CH2: 2
+  TSC_G2_IO1: 3
+  USART2_CK: 7
+PA5:
+  EVENTOUT: 15
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TSC_G2_IO2: 3
+PA6:
+  EVENTOUT: 15
+  OPAMP2_DIG: 13
+  SPI1_MISO: 5
+  TIM16_CH1: 1
+  TIM1_BKIN: 6
+  TIM3_CH1: 2
+  TSC_G2_IO3: 3
+PA7:
+  EVENTOUT: 15
+  SPI1_MOSI: 5
+  TIM17_CH1: 1
+  TIM1_CH1N: 6
+  TIM3_CH2: 2
+  TSC_G2_IO4: 3
+PA8:
+  EVENTOUT: 15
+  HRTIM1_CHA1: 13
+  RCC_MCO: 0
+  TIM1_CH1: 6
+  USART1_CK: 7
+PA9:
+  EVENTOUT: 15
+  HRTIM1_CHA2: 13
+  TIM15_BKIN: 9
+  TIM1_CH2: 6
+  TIM2_CH3: 10
+  TSC_G4_IO1: 3
+  USART1_TX: 7
+PB0:
+  EVENTOUT: 15
+  TIM1_CH2N: 6
+  TIM3_CH3: 2
+  TSC_G3_IO2: 3
+PB1:
+  COMP4_OUT: 8
+  EVENTOUT: 15
+  HRTIM1_SCOUT: 13
+  TIM1_CH3N: 6
+  TIM3_CH4: 2
+  TSC_G3_IO3: 3
+PB10:
+  EVENTOUT: 15
+  HRTIM1_FLT3: 13
+  TIM2_CH3: 1
+  TSC_SYNC: 3
+  USART3_TX: 7
+PB11:
+  EVENTOUT: 15
+  HRTIM1_FLT4: 13
+  TIM2_CH4: 1
+  TSC_G6_IO1: 3
+  USART3_RX: 7
+PB12:
+  EVENTOUT: 15
+  HRTIM1_CHC1: 13
+  TIM1_BKIN: 6
+  TSC_G6_IO2: 3
+  USART3_CK: 7
+PB13:
+  EVENTOUT: 15
+  HRTIM1_CHC2: 13
+  TIM1_CH1N: 6
+  TSC_G6_IO3: 3
+  USART3_CTS: 7
+PB14:
+  EVENTOUT: 15
+  HRTIM1_CHD1: 13
+  TIM15_CH1: 1
+  TIM1_CH2N: 6
+  TSC_G6_IO4: 3
+  USART3_DE: 7
+  USART3_RTS: 7
+PB15:
+  EVENTOUT: 15
+  HRTIM1_CHD2: 13
+  TIM15_CH1N: 2
+  TIM15_CH2: 1
+  TIM1_CH3N: 4
+PB2:
+  EVENTOUT: 15
+  HRTIM1_SCIN: 13
+  TSC_G3_IO4: 3
+PB3:
+  EVENTOUT: 15
+  HRTIM1_EEV9: 13
+  HRTIM1_SCOUT: 12
+  SPI1_SCK: 5
+  SYS_JTDO-TRACESWO: 0
+  TIM2_CH2: 1
+  TIM3_ETR: 10
+  TSC_G5_IO1: 3
+  USART2_TX: 7
+PB4:
+  EVENTOUT: 15
+  HRTIM1_EEV7: 13
+  SPI1_MISO: 5
+  SYS_NJTRST: 0
+  TIM16_CH1: 1
+  TIM17_BKIN: 10
+  TIM3_CH1: 2
+  TSC_G5_IO2: 3
+  USART2_RX: 7
+PB5:
+  EVENTOUT: 15
+  HRTIM1_EEV6: 13
+  I2C1_SMBA: 4
+  SPI1_MOSI: 5
+  TIM16_BKIN: 1
+  TIM17_CH1: 10
+  TIM3_CH2: 2
+  USART2_CK: 7
+PB6:
+  EVENTOUT: 15
+  HRTIM1_EEV4: 13
+  HRTIM1_SCIN: 12
+  I2C1_SCL: 4
+  TIM16_CH1N: 1
+  TSC_G5_IO3: 3
+  USART1_TX: 7
+PB7:
+  EVENTOUT: 15
+  HRTIM1_EEV3: 13
+  I2C1_SDA: 4
+  TIM17_CH1N: 1
+  TIM3_CH4: 10
+  TSC_G5_IO4: 3
+  USART1_RX: 7
+PB8:
+  CAN_RX: 9
+  EVENTOUT: 15
+  HRTIM1_EEV8: 13
+  I2C1_SCL: 4
+  TIM16_CH1: 1
+  TIM1_BKIN: 12
+  TSC_SYNC: 3
+  USART3_RX: 7
+PB9:
+  CAN_TX: 9
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  HRTIM1_EEV5: 13
+  I2C1_SDA: 4
+  IR_OUT: 6
+  TIM17_CH1: 1
+  USART3_TX: 7
+PC0:
+  EVENTOUT: 1
+  TIM1_CH1: 2
+PC1:
+  EVENTOUT: 1
+  TIM1_CH2: 2
+PC10:
+  EVENTOUT: 1
+  USART3_TX: 7
+PC11:
+  EVENTOUT: 1
+  HRTIM1_EEV2: 3
+  USART3_RX: 7
+PC12:
+  EVENTOUT: 1
+  HRTIM1_EEV1: 3
+  USART3_CK: 7
+PC13:
+  TIM1_CH1N: 4
+PC14: {}
+PC15: {}
+PC2:
+  EVENTOUT: 1
+  TIM1_CH3: 2
+PC3:
+  EVENTOUT: 1
+  TIM1_BKIN2: 6
+  TIM1_CH4: 2
+PC4:
+  EVENTOUT: 1
+  TIM1_ETR: 2
+  USART1_TX: 7
+PC5:
+  EVENTOUT: 1
+  TIM15_BKIN: 2
+  TSC_G3_IO1: 3
+  USART1_RX: 7
+PC6:
+  COMP6_OUT: 7
+  EVENTOUT: 1
+  HRTIM1_EEV10: 3
+  TIM3_CH1: 2
+PC7:
+  EVENTOUT: 1
+  HRTIM1_FLT5: 3
+  TIM3_CH2: 2
+PC8:
+  EVENTOUT: 1
+  HRTIM1_CHE1: 3
+  TIM3_CH3: 2
+PC9:
+  EVENTOUT: 1
+  HRTIM1_CHE2: 3
+  TIM3_CH4: 2
+PD2:
+  EVENTOUT: 1
+  TIM3_ETR: 2
+PF0:
+  TIM1_CH3N: 6
+PF1: {}

data/gpio_af/STM32F373.yaml

@@ -0,0 +1,493 @@
+PA0:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  TIM19_CH1: 11
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM5_CH1: 2
+  TIM5_ETR: 2
+  TSC_G1_IO1: 3
+  USART2_CTS: 7
+PA1:
+  EVENTOUT: 15
+  I2S3_CK: 6
+  RTC_REFIN: 0
+  SPI3_SCK: 6
+  TIM15_CH1N: 9
+  TIM19_CH2: 11
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  TSC_G1_IO2: 3
+  USART2_DE: 7
+  USART2_RTS: 7
+PA10:
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIM14_CH1: 9
+  TIM17_BKIN: 1
+  TIM2_CH4: 10
+  TSC_G4_IO2: 3
+  USART1_RX: 7
+PA11:
+  CAN_RX: 9
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  I2S1_WS: 6
+  I2S2_WS: 5
+  SPI1_NSS: 6
+  SPI2_NSS: 5
+  TIM4_CH1: 10
+  TIM5_CH2: 2
+  USART1_CTS: 7
+  USB_DM: 14
+PA12:
+  CAN_TX: 9
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  I2S1_CK: 6
+  SPI1_SCK: 6
+  TIM16_CH1: 1
+  TIM4_CH2: 10
+  TIM5_CH3: 2
+  USART1_DE: 7
+  USART1_RTS: 7
+  USB_DP: 14
+PA13:
+  EVENTOUT: 15
+  I2S1_MCK: 6
+  IR_OUT: 5
+  SPI1_MISO: 6
+  SYS_JTMS-SWDIO: 0
+  TIM16_CH1N: 1
+  TIM4_CH3: 10
+  TIM5_CH4: 2
+  TSC_G4_IO3: 3
+  USART3_CTS: 7
+PA14:
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  SYS_JTCK-SWCLK: 0
+  TIM12_CH1: 10
+  TSC_G4_IO4: 3
+PA15:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  I2S1_WS: 5
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM12_CH2: 10
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TSC_SYNC: 3
+PA2:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  I2S3_MCK: 6
+  SPI3_MISO: 6
+  TIM15_CH1: 9
+  TIM19_CH3: 11
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  TSC_G1_IO3: 3
+  USART2_TX: 7
+PA3:
+  EVENTOUT: 15
+  I2S3_SD: 6
+  SPI3_MOSI: 6
+  TIM15_CH2: 9
+  TIM19_CH4: 11
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  TSC_G1_IO4: 3
+  USART2_RX: 7
+PA4:
+  EVENTOUT: 15
+  I2S1_WS: 5
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  TIM12_CH1: 10
+  TIM3_CH2: 2
+  TSC_G2_IO1: 3
+  USART2_CK: 7
+PA5:
+  CEC: 7
+  EVENTOUT: 15
+  I2S1_CK: 5
+  SPI1_SCK: 5
+  TIM12_CH2: 10
+  TIM14_CH1: 9
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TSC_G2_IO2: 3
+PA6:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  I2S1_MCK: 5
+  SPI1_MISO: 5
+  TIM13_CH1: 9
+  TIM16_CH1: 1
+  TIM3_CH1: 2
+  TSC_G2_IO3: 3
+PA7:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  I2S1_SD: 5
+  SPI1_MOSI: 5
+  TIM14_CH1: 9
+  TIM17_CH1: 1
+  TIM3_CH2: 2
+  TSC_G2_IO4: 3
+PA8:
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+  I2S2_CK: 5
+  RCC_MCO: 0
+  SPI2_SCK: 5
+  TIM4_ETR: 10
+  TIM5_CH1: 2
+  TIM5_ETR: 2
+  USART1_CK: 7
+PA9:
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  I2S2_MCK: 5
+  SPI2_MISO: 5
+  TIM13_CH1: 2
+  TIM15_BKIN: 9
+  TIM2_CH3: 10
+  TSC_G4_IO1: 3
+  USART1_TX: 7
+PB0:
+  EVENTOUT: 15
+  I2S1_SD: 5
+  SPI1_MOSI: 5
+  TIM3_CH2: 10
+  TIM3_CH3: 2
+  TSC_G3_IO3: 3
+PB1:
+  EVENTOUT: 15
+  TIM3_CH4: 2
+  TSC_G3_IO4: 3
+PB10:
+  CEC: 6
+  EVENTOUT: 15
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+  TSC_SYNC: 3
+  USART3_TX: 7
+PB14:
+  EVENTOUT: 15
+  I2S2_MCK: 5
+  SPI2_MISO: 5
+  TIM12_CH1: 9
+  TIM15_CH1: 1
+  TSC_G6_IO1: 3
+  USART3_DE: 7
+  USART3_RTS: 7
+PB15:
+  EVENTOUT: 15
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM12_CH2: 9
+  TIM15_CH1N: 2
+  TIM15_CH2: 1
+  TSC_G6_IO2: 3
+PB2:
+  EVENTOUT: 15
+PB3:
+  EVENTOUT: 15
+  I2S1_CK: 5
+  I2S3_CK: 6
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-TRACESWO: 0
+  TIM13_CH1: 9
+  TIM2_CH2: 1
+  TIM3_ETR: 10
+  TIM4_ETR: 2
+  TSC_G5_IO1: 3
+  USART2_TX: 7
+PB4:
+  EVENTOUT: 15
+  I2S1_MCK: 5
+  I2S3_MCK: 6
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_NJTRST: 0
+  TIM15_CH1N: 9
+  TIM16_CH1: 1
+  TIM17_BKIN: 10
+  TIM3_CH1: 2
+  TSC_G5_IO2: 3
+  USART2_RX: 7
+PB5:
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  I2S1_SD: 5
+  I2S3_SD: 6
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM16_BKIN: 1
+  TIM17_CH1: 10
+  TIM19_ETR: 11
+  TIM3_CH2: 2
+  USART2_CK: 7
+PB6:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  TIM15_CH1: 9
+  TIM16_CH1N: 1
+  TIM19_CH1: 11
+  TIM3_CH3: 10
+  TIM4_CH1: 2
+  TSC_G5_IO3: 3
+  USART1_TX: 7
+PB7:
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  TIM15_CH2: 9
+  TIM17_CH1N: 1
+  TIM19_CH2: 11
+  TIM3_CH4: 10
+  TIM4_CH2: 2
+  TSC_G5_IO4: 3
+  USART1_RX: 7
+PB8:
+  CAN_RX: 9
+  CEC: 6
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM16_CH1: 1
+  TIM19_CH3: 11
+  TIM4_CH3: 2
+  TSC_SYNC: 3
+  USART3_TX: 7
+PB9:
+  CAN_TX: 9
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  I2S2_WS: 5
+  IR_OUT: 6
+  SPI2_NSS: 5
+  TIM17_CH1: 1
+  TIM19_CH4: 11
+  TIM4_CH4: 2
+  USART3_RX: 7
+PC0:
+  EVENTOUT: 1
+  TIM5_CH1: 2
+  TIM5_ETR: 2
+PC1:
+  EVENTOUT: 1
+  TIM5_CH2: 2
+PC10:
+  EVENTOUT: 1
+  I2S3_CK: 6
+  SPI3_SCK: 6
+  TIM19_CH1: 2
+  USART3_TX: 7
+PC11:
+  EVENTOUT: 1
+  I2S3_MCK: 6
+  SPI3_MISO: 6
+  TIM19_CH2: 2
+  USART3_RX: 7
+PC12:
+  EVENTOUT: 1
+  I2S3_SD: 6
+  SPI3_MOSI: 6
+  TIM19_CH3: 2
+  USART3_CK: 7
+PC13: {}
+PC14: {}
+PC15: {}
+PC2:
+  EVENTOUT: 1
+  I2S2_MCK: 5
+  SPI2_MISO: 5
+  TIM5_CH3: 2
+PC3:
+  EVENTOUT: 1
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIM5_CH4: 2
+PC4:
+  EVENTOUT: 1
+  TIM13_CH1: 2
+  TSC_G3_IO1: 3
+  USART1_TX: 7
+PC5:
+  EVENTOUT: 1
+  TSC_G3_IO2: 3
+  USART1_RX: 7
+PC6:
+  EVENTOUT: 1
+  I2S1_WS: 5
+  SPI1_NSS: 5
+  TIM3_CH1: 2
+PC7:
+  EVENTOUT: 1
+  I2S1_CK: 5
+  SPI1_SCK: 5
+  TIM3_CH2: 2
+PC8:
+  EVENTOUT: 1
+  I2S1_MCK: 5
+  SPI1_MISO: 5
+  TIM3_CH3: 2
+PC9:
+  EVENTOUT: 1
+  I2S1_SD: 5
+  SPI1_MOSI: 5
+  TIM3_CH4: 2
+PD0:
+  CAN_RX: 7
+  EVENTOUT: 1
+  TIM19_CH4: 2
+PD1:
+  CAN_TX: 7
+  EVENTOUT: 1
+  TIM19_ETR: 2
+PD10:
+  EVENTOUT: 1
+  USART3_CK: 7
+PD11:
+  EVENTOUT: 1
+  USART3_CTS: 7
+PD12:
+  EVENTOUT: 1
+  TIM4_CH1: 2
+  TSC_G8_IO1: 3
+  USART3_DE: 7
+  USART3_RTS: 7
+PD13:
+  EVENTOUT: 1
+  TIM4_CH2: 2
+  TSC_G8_IO2: 3
+PD14:
+  EVENTOUT: 1
+  TIM4_CH3: 2
+  TSC_G8_IO3: 3
+PD15:
+  EVENTOUT: 1
+  TIM4_CH4: 2
+  TSC_G8_IO4: 3
+PD2:
+  EVENTOUT: 1
+  TIM3_ETR: 2
+PD3:
+  EVENTOUT: 1
+  I2S2_MCK: 5
+  SPI2_MISO: 5
+  USART2_CTS: 7
+PD4:
+  EVENTOUT: 1
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  USART2_DE: 7
+  USART2_RTS: 7
+PD5:
+  EVENTOUT: 1
+  USART2_TX: 7
+PD6:
+  EVENTOUT: 1
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  USART2_RX: 7
+PD7:
+  EVENTOUT: 1
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  USART2_CK: 7
+PD8:
+  EVENTOUT: 1
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TSC_G6_IO3: 3
+  USART3_TX: 7
+PD9:
+  EVENTOUT: 1
+  TSC_G6_IO4: 3
+  USART3_RX: 7
+PE0:
+  EVENTOUT: 1
+  TIM4_ETR: 2
+  USART1_TX: 7
+PE1:
+  EVENTOUT: 1
+  USART1_RX: 7
+PE10:
+  EVENTOUT: 1
+PE11:
+  EVENTOUT: 1
+PE12:
+  EVENTOUT: 1
+PE13:
+  EVENTOUT: 1
+PE14:
+  EVENTOUT: 1
+PE15:
+  EVENTOUT: 1
+  USART3_RX: 7
+PE2:
+  EVENTOUT: 1
+  SYS_TRACECK: 0
+  TSC_G7_IO1: 3
+PE3:
+  EVENTOUT: 1
+  SYS_TRACED0: 0
+  TSC_G7_IO2: 3
+PE4:
+  EVENTOUT: 1
+  SYS_TRACED1: 0
+  TSC_G7_IO3: 3
+PE5:
+  EVENTOUT: 1
+  SYS_TRACED2: 0
+  TSC_G7_IO4: 3
+PE6:
+  EVENTOUT: 1
+  SYS_TRACED3: 0
+PE7:
+  EVENTOUT: 1
+PE8:
+  EVENTOUT: 1
+PE9:
+  EVENTOUT: 1
+PF0:
+  I2C2_SDA: 4
+PF1:
+  I2C2_SCL: 4
+PF10:
+  EVENTOUT: 1
+PF2:
+  EVENTOUT: 1
+  I2C2_SMBA: 4
+PF4:
+  EVENTOUT: 1
+PF6:
+  EVENTOUT: 1
+  I2C2_SCL: 4
+  I2S1_SD: 5
+  SPI1_MOSI: 5
+  TIM4_CH4: 2
+  USART3_DE: 7
+  USART3_RTS: 7
+PF7:
+  EVENTOUT: 1
+  I2C2_SDA: 4
+  USART2_CK: 7
+PF9:
+  EVENTOUT: 1
+  TIM14_CH1: 2

data/gpio_af/STM32F401.yaml

@@ -0,0 +1,270 @@
+PA0:
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM5_CH1: 2
+  USART2_CTS: 7
+PA1:
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  USART2_RTS: 7
+PA10:
+  TIM1_CH3: 1
+  USART1_RX: 7
+  USB_OTG_FS_ID: 10
+PA11:
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USART6_TX: 8
+  USB_OTG_FS_DM: 10
+PA12:
+  TIM1_ETR: 1
+  USART1_RTS: 7
+  USART6_RX: 8
+  USB_OTG_FS_DP: 10
+PA13:
+  SYS_JTMS-SWDIO: 0
+PA14:
+  I2S3ext_WS: 5
+  SYS_JTCK-SWCLK: 0
+PA15:
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+PA2:
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  TIM9_CH1: 3
+  USART2_TX: 7
+PA3:
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  TIM9_CH2: 3
+  USART2_RX: 7
+PA4:
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  USART2_CK: 7
+PA5:
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+PA6:
+  SPI1_MISO: 5
+  TIM1_BKIN: 1
+  TIM3_CH1: 2
+PA7:
+  SPI1_MOSI: 5
+  TIM1_CH1N: 1
+  TIM3_CH2: 2
+PA8:
+  I2C3_SCL: 4
+  RCC_MCO_1: 0
+  TIM1_CH1: 1
+  USART1_CK: 7
+  USB_OTG_FS_SOF: 10
+PA9:
+  I2C3_SMBA: 4
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  TIM1_CH2N: 1
+  TIM3_CH3: 2
+PB1:
+  TIM1_CH3N: 1
+  TIM3_CH4: 2
+PB10:
+  I2C2_SCL: 4
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+PB11:
+  I2C2_SDA: 4
+  TIM2_CH4: 1
+PB12:
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  I2S2ext_WS: 6
+  SPI2_NSS: 5
+  TIM1_BKIN: 1
+PB13:
+  I2S2_CK: 5
+  I2S2ext_CK: 6
+  SPI2_SCK: 5
+  TIM1_CH1N: 1
+PB14:
+  I2S2_ext_SD: 6
+  SPI2_MISO: 5
+  TIM1_CH2N: 1
+PB15:
+  I2S2_SD: 5
+  I2S2ext_MISO: 6
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM1_CH3N: 1
+PB2: {}
+PB3:
+  I2C2_SDA: 9
+  I2S3_CK: 6
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+PB4:
+  I2C3_SDA: 9
+  I2S3_ext_SD: 7
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM3_CH1: 2
+PB5:
+  I2C1_SMBA: 4
+  I2S3_SD: 6
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM3_CH2: 2
+PB6:
+  I2C1_SCL: 4
+  TIM4_CH1: 2
+  USART1_TX: 7
+PB7:
+  I2C1_SDA: 4
+  TIM4_CH2: 2
+  USART1_RX: 7
+PB8:
+  I2C1_SCL: 4
+  SDIO_D4: 12
+  TIM10_CH1: 3
+  TIM4_CH3: 2
+PB9:
+  I2C1_SDA: 4
+  I2S2_WS: 5
+  SDIO_D5: 12
+  SPI2_NSS: 5
+  TIM11_CH1: 3
+  TIM4_CH4: 2
+PC0: {}
+PC1: {}
+PC10:
+  I2S3_CK: 6
+  I2S3ext_CK: 5
+  SDIO_D2: 12
+  SPI3_SCK: 6
+PC11:
+  I2S3_ext_SD: 5
+  SDIO_D3: 12
+  SPI3_MISO: 6
+PC12:
+  I2S3_SD: 6
+  I2S3ext_MISO: 5
+  SDIO_CK: 12
+  SPI3_MOSI: 6
+PC13: {}
+PC14: {}
+PC15: {}
+PC2:
+  I2S2_ext_SD: 6
+  SPI2_MISO: 5
+PC3:
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+PC4: {}
+PC5: {}
+PC6:
+  I2S2_MCK: 5
+  SDIO_D6: 12
+  TIM3_CH1: 2
+  USART6_TX: 8
+PC7:
+  I2S3_MCK: 6
+  SDIO_D7: 12
+  TIM3_CH2: 2
+  USART6_RX: 8
+PC8:
+  SDIO_D0: 12
+  TIM3_CH3: 2
+  USART6_CK: 8
+PC9:
+  I2C3_SDA: 4
+  I2S_CKIN: 5
+  RCC_MCO_2: 0
+  SDIO_D1: 12
+  TIM3_CH4: 2
+PD0: {}
+PD1: {}
+PD10: {}
+PD11: {}
+PD12:
+  TIM4_CH1: 2
+PD13:
+  TIM4_CH2: 2
+PD14:
+  TIM4_CH3: 2
+PD15:
+  TIM4_CH4: 2
+PD2:
+  SDIO_CMD: 12
+  TIM3_ETR: 2
+PD3:
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  USART2_CTS: 7
+PD4:
+  USART2_RTS: 7
+PD5:
+  USART2_TX: 7
+PD6:
+  I2S3_SD: 5
+  SPI3_MOSI: 5
+  USART2_RX: 7
+PD7:
+  USART2_CK: 7
+PD8: {}
+PD9: {}
+PE0:
+  TIM4_ETR: 2
+PE1: {}
+PE10:
+  TIM1_CH2N: 1
+PE11:
+  SPI4_NSS: 5
+  TIM1_CH2: 1
+PE12:
+  SPI4_SCK: 5
+  TIM1_CH3N: 1
+PE13:
+  SPI4_MISO: 5
+  TIM1_CH3: 1
+PE14:
+  SPI4_MOSI: 5
+  TIM1_CH4: 1
+PE15:
+  TIM1_BKIN: 1
+PE2:
+  SPI4_SCK: 5
+  SYS_TRACECLK: 0
+PE3:
+  SYS_TRACED0: 0
+PE4:
+  SPI4_NSS: 5
+  SYS_TRACED1: 0
+PE5:
+  SPI4_MISO: 5
+  SYS_TRACED2: 0
+  TIM9_CH1: 3
+PE6:
+  SPI4_MOSI: 5
+  SYS_TRACED3: 0
+  TIM9_CH2: 3
+PE7:
+  TIM1_ETR: 1
+PE8:
+  TIM1_CH1N: 1
+PE9:
+  TIM1_CH1: 1
+PH0: {}
+PH1: {}
+PI8: {}

data/gpio_af/STM32F410.yaml

@@ -0,0 +1,236 @@
+PA0:
+  EVENTOUT: 15
+  TIM5_CH1: 2
+  USART2_CTS: 7
+PA1:
+  EVENTOUT: 15
+  TIM5_CH2: 2
+  USART2_RTS: 7
+PA10:
+  EVENTOUT: 15
+  I2S5_SD: 6
+  SPI5_MOSI: 6
+  TIM1_CH3: 1
+  USART1_RX: 7
+PA11:
+  EVENTOUT: 15
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USART6_TX: 8
+PA12:
+  EVENTOUT: 15
+  SPI5_MISO: 6
+  TIM1_ETR: 1
+  USART1_RTS: 7
+  USART6_RX: 8
+PA13:
+  EVENTOUT: 15
+  SYS_JTMS-SWDIO: 0
+PA14:
+  EVENTOUT: 15
+  SYS_JTCK-SWCLK: 0
+PA15:
+  EVENTOUT: 15
+  I2S1_WS: 5
+  SPI1_NSS: 5
+  SYS_JTDI: 0
+  USART1_TX: 7
+PA2:
+  EVENTOUT: 15
+  I2S_CKIN: 5
+  TIM5_CH3: 2
+  TIM9_CH1: 3
+  USART2_TX: 7
+PA3:
+  EVENTOUT: 15
+  I2S2_MCK: 5
+  TIM5_CH4: 2
+  TIM9_CH2: 3
+  USART2_RX: 7
+PA4:
+  EVENTOUT: 15
+  I2S1_WS: 5
+  SPI1_NSS: 5
+  USART2_CK: 7
+PA5:
+  EVENTOUT: 15
+  I2S1_CK: 5
+  SPI1_SCK: 5
+PA6:
+  EVENTOUT: 15
+  I2S2_MCK: 6
+  SPI1_MISO: 5
+  TIM1_BKIN: 1
+PA7:
+  EVENTOUT: 15
+  I2S1_SD: 5
+  SPI1_MOSI: 5
+  TIM1_CH1N: 1
+PA8:
+  EVENTOUT: 15
+  FMPI2C1_SCL: 4
+  RCC_MCO_1: 0
+  TIM1_CH1: 1
+  USART1_CK: 7
+PA9:
+  EVENTOUT: 15
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  EVENTOUT: 15
+  I2S5_CK: 6
+  SPI5_SCK: 6
+  TIM1_CH2N: 1
+PB1:
+  EVENTOUT: 15
+  I2S5_WS: 6
+  SPI5_NSS: 6
+  TIM1_CH3N: 1
+PB10:
+  EVENTOUT: 15
+  FMPI2C1_SCL: 9
+  I2C2_SCL: 4
+  I2S1_MCK: 6
+  I2S2_CK: 5
+  SPI2_SCK: 5
+PB11:
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  I2S_CKIN: 5
+  SYS_TRACED3: 0
+  TIM5_CH4: 2
+PB12:
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM1_BKIN: 1
+  TIM5_CH1: 2
+PB13:
+  EVENTOUT: 15
+  FMPI2C1_SMBA: 4
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM1_CH1N: 1
+PB14:
+  EVENTOUT: 15
+  FMPI2C1_SDA: 4
+  SPI2_MISO: 5
+  TIM1_CH2N: 1
+PB15:
+  EVENTOUT: 15
+  FMPI2C1_SCL: 4
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM1_CH3N: 1
+PB2:
+  EVENTOUT: 15
+  LPTIM1_OUT: 1
+PB3:
+  EVENTOUT: 15
+  FMPI2C1_SDA: 4
+  I2C2_SDA: 9
+  I2S1_CK: 5
+  SPI1_SCK: 5
+  SYS_JTDO-SWO: 0
+  USART1_RX: 7
+PB4:
+  EVENTOUT: 15
+  SPI1_MISO: 5
+  SYS_JTRST: 0
+PB5:
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  I2S1_SD: 5
+  LPTIM1_IN1: 1
+  SPI1_MOSI: 5
+PB6:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  LPTIM1_ETR: 1
+  USART1_TX: 7
+PB7:
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  LPTIM1_IN2: 1
+  USART1_RX: 7
+PB8:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  I2S5_SD: 6
+  LPTIM1_OUT: 1
+  SPI5_MOSI: 6
+PB9:
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  I2C2_SDA: 9
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM11_CH1: 3
+PC0:
+  EVENTOUT: 15
+  LPTIM1_IN1: 1
+PC1:
+  EVENTOUT: 15
+  LPTIM1_OUT: 1
+PC10:
+  EVENTOUT: 15
+  SYS_TRACED0: 0
+  TIM5_CH2: 2
+PC11:
+  EVENTOUT: 15
+  SYS_TRACED1: 0
+  TIM5_CH3: 2
+PC12:
+  EVENTOUT: 15
+  SYS_TRACED2: 0
+  TIM11_CH1: 3
+PC13:
+  EVENTOUT: 15
+PC14:
+  EVENTOUT: 15
+PC15:
+  EVENTOUT: 15
+PC2:
+  EVENTOUT: 15
+  LPTIM1_IN2: 1
+  SPI2_MISO: 5
+PC3:
+  EVENTOUT: 15
+  I2S2_SD: 5
+  LPTIM1_ETR: 1
+  SPI2_MOSI: 5
+PC4:
+  EVENTOUT: 15
+  TIM9_CH1: 3
+PC5:
+  EVENTOUT: 15
+  FMPI2C1_SMBA: 4
+  TIM9_CH2: 3
+PC6:
+  EVENTOUT: 15
+  FMPI2C1_SCL: 4
+  I2S2_MCK: 5
+  SYS_TRACECLK: 0
+  USART6_TX: 8
+PC7:
+  EVENTOUT: 15
+  FMPI2C1_SDA: 4
+  I2S1_MCK: 6
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  USART6_RX: 8
+PC8:
+  EVENTOUT: 15
+  USART6_CK: 8
+PC9:
+  EVENTOUT: 15
+  FMPI2C1_SDA: 4
+  I2S_CKIN: 5
+  RCC_MCO_2: 0
+PH0:
+  EVENTOUT: 15
+PH1:
+  EVENTOUT: 15
+PI8: {}

data/gpio_af/STM32F411.yaml

@@ -0,0 +1,329 @@
+PA0:
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM5_CH1: 2
+  USART2_CTS: 7
+PA1:
+  I2S4_SD: 5
+  SPI4_MOSI: 5
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  USART2_RTS: 7
+PA10:
+  I2S5_SD: 6
+  SPI5_MOSI: 6
+  TIM1_CH3: 1
+  USART1_RX: 7
+  USB_OTG_FS_ID: 10
+PA11:
+  SPI4_MISO: 6
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USART6_TX: 8
+  USB_OTG_FS_DM: 10
+PA12:
+  SPI5_MISO: 6
+  TIM1_ETR: 1
+  USART1_RTS: 7
+  USART6_RX: 8
+  USB_OTG_FS_DP: 10
+PA13:
+  SYS_JTMS-SWDIO: 0
+PA14:
+  SYS_JTCK-SWCLK: 0
+PA15:
+  I2S1_WS: 5
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  USART1_TX: 7
+PA2:
+  I2S_CKIN: 5
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  TIM9_CH1: 3
+  USART2_TX: 7
+PA3:
+  I2S2_MCK: 5
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  TIM9_CH2: 3
+  USART2_RX: 7
+PA4:
+  I2S1_WS: 5
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  USART2_CK: 7
+PA5:
+  I2S1_CK: 5
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+PA6:
+  I2S2_MCK: 6
+  SDIO_CMD: 12
+  SPI1_MISO: 5
+  TIM1_BKIN: 1
+  TIM3_CH1: 2
+PA7:
+  I2S1_SD: 5
+  SPI1_MOSI: 5
+  TIM1_CH1N: 1
+  TIM3_CH2: 2
+PA8:
+  I2C3_SCL: 4
+  RCC_MCO_1: 0
+  SDIO_D1: 12
+  TIM1_CH1: 1
+  USART1_CK: 7
+  USB_OTG_FS_SOF: 10
+PA9:
+  I2C3_SMBA: 4
+  SDIO_D2: 12
+  TIM1_CH2: 1
+  USART1_TX: 7
+  USB_OTG_FS_VBUS: 10
+PB0:
+  I2S5_CK: 6
+  SPI5_SCK: 6
+  TIM1_CH2N: 1
+  TIM3_CH3: 2
+PB1:
+  I2S5_WS: 6
+  SPI5_NSS: 6
+  TIM1_CH3N: 1
+  TIM3_CH4: 2
+PB10:
+  I2C2_SCL: 4
+  I2S2_CK: 5
+  I2S3_MCK: 6
+  SDIO_D7: 12
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+PB11:
+  I2C2_SDA: 4
+  I2S_CKIN: 5
+  TIM2_CH4: 1
+PB12:
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  I2S3_CK: 7
+  I2S4_WS: 6
+  SPI2_NSS: 5
+  SPI3_SCK: 7
+  SPI4_NSS: 6
+  TIM1_BKIN: 1
+PB13:
+  I2S2_CK: 5
+  I2S4_CK: 6
+  SPI2_SCK: 5
+  SPI4_SCK: 6
+  TIM1_CH1N: 1
+PB14:
+  I2S2_ext_SD: 6
+  SDIO_D6: 12
+  SPI2_MISO: 5
+  TIM1_CH2N: 1
+PB15:
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SDIO_CK: 12
+  SPI2_MOSI: 5
+  TIM1_CH3N: 1
+PB2: {}
+PB3:
+  I2C2_SDA: 9
+  I2S1_CK: 5
+  I2S3_CK: 6
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+  USART1_RX: 7
+PB4:
+  I2C3_SDA: 9
+  I2S3_ext_SD: 7
+  SDIO_D0: 12
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM3_CH1: 2
+PB5:
+  I2C1_SMBA: 4
+  I2S1_SD: 5
+  I2S3_SD: 6
+  SDIO_D3: 12
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM3_CH2: 2
+PB6:
+  I2C1_SCL: 4
+  TIM4_CH1: 2
+  USART1_TX: 7
+PB7:
+  I2C1_SDA: 4
+  SDIO_D0: 12
+  TIM4_CH2: 2
+  USART1_RX: 7
+PB8:
+  I2C1_SCL: 4
+  I2C3_SDA: 9
+  I2S5_SD: 6
+  SDIO_D4: 12
+  SPI5_MOSI: 6
+  TIM10_CH1: 3
+  TIM4_CH3: 2
+PB9:
+  I2C1_SDA: 4
+  I2C2_SDA: 9
+  I2S2_WS: 5
+  SDIO_D5: 12
+  SPI2_NSS: 5
+  TIM11_CH1: 3
+  TIM4_CH4: 2
+PC0: {}
+PC1: {}
+PC10:
+  I2S3_CK: 6
+  SDIO_D2: 12
+  SPI3_SCK: 6
+PC11:
+  I2S3_ext_SD: 5
+  SDIO_D3: 12
+  SPI3_MISO: 6
+PC12:
+  I2S3_SD: 6
+  SDIO_CK: 12
+  SPI3_MOSI: 6
+PC13: {}
+PC14: {}
+PC15: {}
+PC2:
+  I2S2_ext_SD: 6
+  SPI2_MISO: 5
+PC3:
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+PC4: {}
+PC5: {}
+PC6:
+  I2S2_MCK: 5
+  SDIO_D6: 12
+  TIM3_CH1: 2
+  USART6_TX: 8
+PC7:
+  I2S2_CK: 5
+  I2S3_MCK: 6
+  SDIO_D7: 12
+  SPI2_SCK: 5
+  TIM3_CH2: 2
+  USART6_RX: 8
+PC8:
+  SDIO_D0: 12
+  TIM3_CH3: 2
+  USART6_CK: 8
+PC9:
+  I2C3_SDA: 4
+  I2S_CKIN: 5
+  RCC_MCO_2: 0
+  SDIO_D1: 12
+  TIM3_CH4: 2
+PD0: {}
+PD1: {}
+PD10: {}
+PD11: {}
+PD12:
+  TIM4_CH1: 2
+PD13:
+  TIM4_CH2: 2
+PD14:
+  TIM4_CH3: 2
+PD15:
+  TIM4_CH4: 2
+PD2:
+  SDIO_CMD: 12
+  TIM3_ETR: 2
+PD3:
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  USART2_CTS: 7
+PD4:
+  USART2_RTS: 7
+PD5:
+  USART2_TX: 7
+PD6:
+  I2S3_SD: 5
+  SPI3_MOSI: 5
+  USART2_RX: 7
+PD7:
+  USART2_CK: 7
+PD8: {}
+PD9: {}
+PE0:
+  TIM4_ETR: 2
+PE1: {}
+PE10:
+  TIM1_CH2N: 1
+PE11:
+  I2S4_WS: 5
+  I2S5_WS: 6
+  SPI4_NSS: 5
+  SPI5_NSS: 6
+  TIM1_CH2: 1
+PE12:
+  I2S4_CK: 5
+  I2S5_CK: 6
+  SPI4_SCK: 5
+  SPI5_SCK: 6
+  TIM1_CH3N: 1
+PE13:
+  SPI4_MISO: 5
+  SPI5_MISO: 6
+  TIM1_CH3: 1
+PE14:
+  I2S4_SD: 5
+  I2S5_SD: 6
+  SPI4_MOSI: 5
+  SPI5_MOSI: 6
+  TIM1_CH4: 1
+PE15:
+  TIM1_BKIN: 1
+PE2:
+  I2S4_CK: 5
+  I2S5_CK: 6
+  SPI4_SCK: 5
+  SPI5_SCK: 6
+  SYS_TRACECLK: 0
+PE3:
+  SYS_TRACED0: 0
+PE4:
+  I2S4_WS: 5
+  I2S5_WS: 6
+  SPI4_NSS: 5
+  SPI5_NSS: 6
+  SYS_TRACED1: 0
+PE5:
+  SPI4_MISO: 5
+  SPI5_MISO: 6
+  SYS_TRACED2: 0
+  TIM9_CH1: 3
+PE6:
+  I2S4_SD: 5
+  I2S5_SD: 6
+  SPI4_MOSI: 5
+  SPI5_MOSI: 6
+  SYS_TRACED3: 0
+  TIM9_CH2: 3
+PE7:
+  TIM1_ETR: 1
+PE8:
+  TIM1_CH1N: 1
+PE9:
+  TIM1_CH1: 1
+PH0: {}
+PH1: {}
+PI8: {}

data/gpio_af/STM32F412.yaml

@@ -0,0 +1,702 @@
+PA0:
+  EVENTOUT: 15
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM5_CH1: 2
+  TIM8_ETR: 3
+  USART2_CTS: 7
+PA1:
+  EVENTOUT: 15
+  I2S4_SD: 5
+  QUADSPI_BK1_IO3: 9
+  SPI4_MOSI: 5
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  USART2_RTS: 7
+PA10:
+  EVENTOUT: 15
+  I2S5_SD: 6
+  SPI5_MOSI: 6
+  TIM1_CH3: 1
+  USART1_RX: 7
+  USB_OTG_FS_ID: 10
+PA11:
+  CAN1_RX: 9
+  EVENTOUT: 15
+  SPI4_MISO: 6
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USART6_TX: 8
+  USB_OTG_FS_DM: 10
+PA12:
+  CAN1_TX: 9
+  EVENTOUT: 15
+  SPI5_MISO: 6
+  TIM1_ETR: 1
+  USART1_RTS: 7
+  USART6_RX: 8
+  USB_OTG_FS_DP: 10
+PA13:
+  EVENTOUT: 15
+  SYS_JTMS-SWDIO: 0
+PA14:
+  EVENTOUT: 15
+  SYS_JTCK-SWCLK: 0
+PA15:
+  EVENTOUT: 15
+  I2S1_WS: 5
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  USART1_TX: 7
+PA2:
+  EVENTOUT: 15
+  FSMC_D4: 12
+  FSMC_DA4: 12
+  I2S_CKIN: 5
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  TIM9_CH1: 3
+  USART2_TX: 7
+PA3:
+  EVENTOUT: 15
+  FSMC_D5: 12
+  FSMC_DA5: 12
+  I2S2_MCK: 5
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  TIM9_CH2: 3
+  USART2_RX: 7
+PA4:
+  DFSDM1_DATIN1: 8
+  EVENTOUT: 15
+  FSMC_D6: 12
+  FSMC_DA6: 12
+  I2S1_WS: 5
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  USART2_CK: 7
+PA5:
+  DFSDM1_CKIN1: 8
+  EVENTOUT: 15
+  FSMC_D7: 12
+  FSMC_DA7: 12
+  I2S1_CK: 5
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM8_CH1N: 3
+PA6:
+  EVENTOUT: 15
+  I2S2_MCK: 6
+  QUADSPI_BK2_IO0: 10
+  SDIO_CMD: 12
+  SPI1_MISO: 5
+  TIM13_CH1: 9
+  TIM1_BKIN: 1
+  TIM3_CH1: 2
+  TIM8_BKIN: 3
+PA7:
+  EVENTOUT: 15
+  I2S1_SD: 5
+  QUADSPI_BK2_IO1: 10
+  SPI1_MOSI: 5
+  TIM14_CH1: 9
+  TIM1_CH1N: 1
+  TIM3_CH2: 2
+  TIM8_CH1N: 3
+PA8:
+  EVENTOUT: 15
+  I2C3_SCL: 4
+  RCC_MCO_1: 0
+  SDIO_D1: 12
+  TIM1_CH1: 1
+  USART1_CK: 7
+  USB_OTG_FS_SOF: 10
+PA9:
+  EVENTOUT: 15
+  I2C3_SMBA: 4
+  SDIO_D2: 12
+  TIM1_CH2: 1
+  USART1_TX: 7
+  USB_OTG_FS_VBUS: 10
+PB0:
+  EVENTOUT: 15
+  I2S5_CK: 6
+  SPI5_SCK: 6
+  TIM1_CH2N: 1
+  TIM3_CH3: 2
+  TIM8_CH2N: 3
+PB1:
+  DFSDM1_DATIN0: 8
+  EVENTOUT: 15
+  I2S5_WS: 6
+  QUADSPI_CLK: 9
+  SPI5_NSS: 6
+  TIM1_CH3N: 1
+  TIM3_CH4: 2
+  TIM8_CH3N: 3
+PB10:
+  EVENTOUT: 15
+  FMPI2C1_SCL: 9
+  I2C2_SCL: 4
+  I2S2_CK: 5
+  I2S3_MCK: 6
+  SDIO_D7: 12
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+  USART3_TX: 7
+PB11:
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  I2S_CKIN: 5
+  TIM2_CH4: 1
+  USART3_RX: 7
+PB12:
+  CAN2_RX: 9
+  DFSDM1_DATIN1: 10
+  EVENTOUT: 15
+  FSMC_D13: 12
+  FSMC_DA13: 12
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  I2S3_CK: 7
+  I2S4_WS: 6
+  SPI2_NSS: 5
+  SPI3_SCK: 7
+  SPI4_NSS: 6
+  TIM1_BKIN: 1
+  USART3_CK: 8
+PB13:
+  CAN2_TX: 9
+  DFSDM1_CKIN1: 10
+  EVENTOUT: 15
+  FMPI2C1_SMBA: 4
+  I2S2_CK: 5
+  I2S4_CK: 6
+  SPI2_SCK: 5
+  SPI4_SCK: 6
+  TIM1_CH1N: 1
+  USART3_CTS: 8
+PB14:
+  DFSDM1_DATIN2: 8
+  EVENTOUT: 15
+  FMPI2C1_SDA: 4
+  FSMC_D0: 10
+  FSMC_DA0: 10
+  I2S2_ext_SD: 6
+  SDIO_D6: 12
+  SPI2_MISO: 5
+  TIM12_CH1: 9
+  TIM1_CH2N: 1
+  TIM8_CH2N: 3
+  USART3_RTS: 7
+PB15:
+  DFSDM1_CKIN2: 8
+  EVENTOUT: 15
+  FMPI2C1_SCL: 4
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SDIO_CK: 12
+  SPI2_MOSI: 5
+  TIM12_CH2: 9
+  TIM1_CH3N: 1
+  TIM8_CH3N: 3
+PB2:
+  DFSDM1_CKIN0: 6
+  EVENTOUT: 15
+  QUADSPI_CLK: 9
+PB3:
+  EVENTOUT: 15
+  FMPI2C1_SDA: 4
+  I2C2_SDA: 9
+  I2S1_CK: 5
+  I2S3_CK: 6
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+  USART1_RX: 7
+PB4:
+  EVENTOUT: 15
+  I2C3_SDA: 9
+  I2S3_ext_SD: 7
+  SDIO_D0: 12
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM3_CH1: 2
+PB5:
+  CAN2_RX: 9
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  I2S1_SD: 5
+  I2S3_SD: 6
+  SDIO_D3: 12
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM3_CH2: 2
+PB6:
+  CAN2_TX: 9
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  QUADSPI_BK1_NCS: 10
+  SDIO_D0: 12
+  TIM4_CH1: 2
+  USART1_TX: 7
+PB7:
+  EVENTOUT: 15
+  FSMC_NL: 12
+  I2C1_SDA: 4
+  TIM4_CH2: 2
+  USART1_RX: 7
+PB8:
+  CAN1_RX: 8
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  I2C3_SDA: 9
+  I2S5_SD: 6
+  SDIO_D4: 12
+  SPI5_MOSI: 6
+  TIM10_CH1: 3
+  TIM4_CH3: 2
+PB9:
+  CAN1_TX: 8
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  I2C2_SDA: 9
+  I2S2_WS: 5
+  SDIO_D5: 12
+  SPI2_NSS: 5
+  TIM11_CH1: 3
+  TIM4_CH4: 2
+PC0:
+  EVENTOUT: 15
+PC1:
+  EVENTOUT: 15
+PC10:
+  EVENTOUT: 15
+  I2S3_CK: 6
+  QUADSPI_BK1_IO1: 9
+  SDIO_D2: 12
+  SPI3_SCK: 6
+  USART3_TX: 7
+PC11:
+  EVENTOUT: 15
+  FSMC_D2: 10
+  FSMC_DA2: 10
+  I2S3_ext_SD: 5
+  QUADSPI_BK2_NCS: 9
+  SDIO_D3: 12
+  SPI3_MISO: 6
+  USART3_RX: 7
+PC12:
+  EVENTOUT: 15
+  FSMC_D3: 10
+  FSMC_DA3: 10
+  I2S3_SD: 6
+  SDIO_CK: 12
+  SPI3_MOSI: 6
+  USART3_CK: 7
+PC13:
+  EVENTOUT: 15
+PC14:
+  EVENTOUT: 15
+PC15:
+  EVENTOUT: 15
+PC2:
+  DFSDM1_CKOUT: 8
+  EVENTOUT: 15
+  FSMC_NWE: 12
+  I2S2_ext_SD: 6
+  SPI2_MISO: 5
+PC3:
+  EVENTOUT: 15
+  FSMC_A0: 12
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+PC4:
+  EVENTOUT: 15
+  FSMC_NE4: 12
+  I2S1_MCK: 5
+  QUADSPI_BK2_IO2: 10
+PC5:
+  EVENTOUT: 15
+  FMPI2C1_SMBA: 4
+  FSMC_NOE: 12
+  QUADSPI_BK2_IO3: 10
+  USART3_RX: 7
+PC6:
+  DFSDM1_CKIN3: 6
+  EVENTOUT: 15
+  FMPI2C1_SCL: 4
+  FSMC_D1: 10
+  FSMC_DA1: 10
+  I2S2_MCK: 5
+  SDIO_D6: 12
+  TIM3_CH1: 2
+  TIM8_CH1: 3
+  USART6_TX: 8
+PC7:
+  DFSDM1_DATIN3: 10
+  EVENTOUT: 15
+  FMPI2C1_SDA: 4
+  I2S2_CK: 5
+  I2S3_MCK: 6
+  SDIO_D7: 12
+  SPI2_SCK: 5
+  TIM3_CH2: 2
+  TIM8_CH2: 3
+  USART6_RX: 8
+PC8:
+  EVENTOUT: 15
+  QUADSPI_BK1_IO2: 9
+  SDIO_D0: 12
+  TIM3_CH3: 2
+  TIM8_CH3: 3
+  USART6_CK: 8
+PC9:
+  EVENTOUT: 15
+  I2C3_SDA: 4
+  I2S_CKIN: 5
+  QUADSPI_BK1_IO0: 9
+  RCC_MCO_2: 0
+  SDIO_D1: 12
+  TIM3_CH4: 2
+  TIM8_CH4: 3
+PD0:
+  CAN1_RX: 9
+  EVENTOUT: 15
+  FSMC_D2: 12
+  FSMC_DA2: 12
+PD1:
+  CAN1_TX: 9
+  EVENTOUT: 15
+  FSMC_D3: 12
+  FSMC_DA3: 12
+PD10:
+  EVENTOUT: 15
+  FSMC_D15: 12
+  FSMC_DA15: 12
+  USART3_CK: 7
+PD11:
+  EVENTOUT: 15
+  FMPI2C1_SMBA: 4
+  FSMC_A16: 12
+  QUADSPI_BK1_IO0: 9
+  USART3_CTS: 7
+PD12:
+  EVENTOUT: 15
+  FMPI2C1_SCL: 4
+  FSMC_A17: 12
+  QUADSPI_BK1_IO1: 9
+  TIM4_CH1: 2
+  USART3_RTS: 7
+PD13:
+  EVENTOUT: 15
+  FMPI2C1_SDA: 4
+  FSMC_A18: 12
+  QUADSPI_BK1_IO3: 9
+  TIM4_CH2: 2
+PD14:
+  EVENTOUT: 15
+  FMPI2C1_SCL: 4
+  FSMC_D0: 12
+  FSMC_DA0: 12
+  TIM4_CH3: 2
+PD15:
+  EVENTOUT: 15
+  FMPI2C1_SDA: 4
+  FSMC_D1: 12
+  FSMC_DA1: 12
+  TIM4_CH4: 2
+PD2:
+  EVENTOUT: 15
+  FSMC_NWE: 10
+  SDIO_CMD: 12
+  TIM3_ETR: 2
+PD3:
+  DFSDM1_DATIN0: 6
+  EVENTOUT: 15
+  FSMC_CLK: 12
+  I2S2_CK: 5
+  QUADSPI_CLK: 9
+  SPI2_SCK: 5
+  SYS_TRACED1: 0
+  USART2_CTS: 7
+PD4:
+  DFSDM1_CKIN0: 6
+  EVENTOUT: 15
+  FSMC_NOE: 12
+  USART2_RTS: 7
+PD5:
+  EVENTOUT: 15
+  FSMC_NWE: 12
+  USART2_TX: 7
+PD6:
+  DFSDM1_DATIN1: 6
+  EVENTOUT: 15
+  FSMC_NWAIT: 12
+  I2S3_SD: 5
+  SPI3_MOSI: 5
+  USART2_RX: 7
+PD7:
+  DFSDM1_CKIN1: 6
+  EVENTOUT: 15
+  FSMC_NE1: 12
+  USART2_CK: 7
+PD8:
+  EVENTOUT: 15
+  FSMC_D13: 12
+  FSMC_DA13: 12
+  USART3_TX: 7
+PD9:
+  EVENTOUT: 15
+  FSMC_D14: 12
+  FSMC_DA14: 12
+  USART3_RX: 7
+PE0:
+  EVENTOUT: 15
+  FSMC_NBL0: 12
+  TIM4_ETR: 2
+PE1:
+  EVENTOUT: 15
+  FSMC_NBL1: 12
+PE10:
+  EVENTOUT: 15
+  FSMC_D7: 12
+  FSMC_DA7: 12
+  QUADSPI_BK2_IO3: 10
+  TIM1_CH2N: 1
+PE11:
+  EVENTOUT: 15
+  FSMC_D8: 12
+  FSMC_DA8: 12
+  I2S4_WS: 5
+  I2S5_WS: 6
+  SPI4_NSS: 5
+  SPI5_NSS: 6
+  TIM1_CH2: 1
+PE12:
+  EVENTOUT: 15
+  FSMC_D9: 12
+  FSMC_DA9: 12
+  I2S4_CK: 5
+  I2S5_CK: 6
+  SPI4_SCK: 5
+  SPI5_SCK: 6
+  TIM1_CH3N: 1
+PE13:
+  EVENTOUT: 15
+  FSMC_D10: 12
+  FSMC_DA10: 12
+  SPI4_MISO: 5
+  SPI5_MISO: 6
+  TIM1_CH3: 1
+PE14:
+  EVENTOUT: 15
+  FSMC_D11: 12
+  FSMC_DA11: 12
+  I2S4_SD: 5
+  I2S5_SD: 6
+  SPI4_MOSI: 5
+  SPI5_MOSI: 6
+  TIM1_CH4: 1
+PE15:
+  EVENTOUT: 15
+  FSMC_D12: 12
+  FSMC_DA12: 12
+  TIM1_BKIN: 1
+PE2:
+  EVENTOUT: 15
+  FSMC_A23: 12
+  I2S4_CK: 5
+  I2S5_CK: 6
+  QUADSPI_BK1_IO2: 9
+  SPI4_SCK: 5
+  SPI5_SCK: 6
+  SYS_TRACECLK: 0
+PE3:
+  EVENTOUT: 15
+  FSMC_A19: 12
+  SYS_TRACED0: 0
+PE4:
+  DFSDM1_DATIN3: 8
+  EVENTOUT: 15
+  FSMC_A20: 12
+  I2S4_WS: 5
+  I2S5_WS: 6
+  SPI4_NSS: 5
+  SPI5_NSS: 6
+  SYS_TRACED1: 0
+PE5:
+  DFSDM1_CKIN3: 8
+  EVENTOUT: 15
+  FSMC_A21: 12
+  SPI4_MISO: 5
+  SPI5_MISO: 6
+  SYS_TRACED2: 0
+  TIM9_CH1: 3
+PE6:
+  EVENTOUT: 15
+  FSMC_A22: 12
+  I2S4_SD: 5
+  I2S5_SD: 6
+  SPI4_MOSI: 5
+  SPI5_MOSI: 6
+  SYS_TRACED3: 0
+  TIM9_CH2: 3
+PE7:
+  DFSDM1_DATIN2: 6
+  EVENTOUT: 15
+  FSMC_D4: 12
+  FSMC_DA4: 12
+  QUADSPI_BK2_IO0: 10
+  TIM1_ETR: 1
+PE8:
+  DFSDM1_CKIN2: 6
+  EVENTOUT: 15
+  FSMC_D5: 12
+  FSMC_DA5: 12
+  QUADSPI_BK2_IO1: 10
+  TIM1_CH1N: 1
+PE9:
+  DFSDM1_CKOUT: 6
+  EVENTOUT: 15
+  FSMC_D6: 12
+  FSMC_DA6: 12
+  QUADSPI_BK2_IO2: 10
+  TIM1_CH1: 1
+PF0:
+  EVENTOUT: 15
+  FSMC_A0: 12
+  I2C2_SDA: 4
+PF1:
+  EVENTOUT: 15
+  FSMC_A1: 12
+  I2C2_SCL: 4
+PF10:
+  EVENTOUT: 15
+  TIM1_ETR: 1
+  TIM5_CH4: 2
+PF11:
+  EVENTOUT: 15
+  TIM8_ETR: 3
+PF12:
+  EVENTOUT: 15
+  FSMC_A6: 12
+  TIM8_BKIN: 3
+PF13:
+  EVENTOUT: 15
+  FMPI2C1_SMBA: 4
+  FSMC_A7: 12
+PF14:
+  EVENTOUT: 15
+  FMPI2C1_SCL: 4
+  FSMC_A8: 12
+PF15:
+  EVENTOUT: 15
+  FMPI2C1_SDA: 4
+  FSMC_A9: 12
+PF2:
+  EVENTOUT: 15
+  FSMC_A2: 12
+  I2C2_SMBA: 4
+PF3:
+  EVENTOUT: 15
+  FSMC_A3: 12
+  TIM5_CH1: 2
+PF4:
+  EVENTOUT: 15
+  FSMC_A4: 12
+  TIM5_CH2: 2
+PF5:
+  EVENTOUT: 15
+  FSMC_A5: 12
+  TIM5_CH3: 2
+PF6:
+  EVENTOUT: 15
+  QUADSPI_BK1_IO3: 9
+  SYS_TRACED0: 0
+  TIM10_CH1: 3
+PF7:
+  EVENTOUT: 15
+  QUADSPI_BK1_IO2: 9
+  SYS_TRACED1: 0
+  TIM11_CH1: 3
+PF8:
+  EVENTOUT: 15
+  QUADSPI_BK1_IO0: 10
+  TIM13_CH1: 9
+PF9:
+  EVENTOUT: 15
+  QUADSPI_BK1_IO1: 10
+  TIM14_CH1: 9
+PG0:
+  CAN1_RX: 9
+  EVENTOUT: 15
+  FSMC_A10: 12
+PG1:
+  CAN1_TX: 9
+  EVENTOUT: 15
+  FSMC_A11: 12
+PG10:
+  EVENTOUT: 15
+  FSMC_NE3: 12
+PG11:
+  CAN2_RX: 9
+  EVENTOUT: 15
+PG12:
+  CAN2_TX: 9
+  EVENTOUT: 15
+  FSMC_NE4: 12
+  USART6_RTS: 8
+PG13:
+  EVENTOUT: 15
+  FSMC_A24: 12
+  SYS_TRACED2: 0
+  USART6_CTS: 8
+PG14:
+  EVENTOUT: 15
+  FSMC_A25: 12
+  QUADSPI_BK2_IO3: 9
+  SYS_TRACED3: 0
+  USART6_TX: 8
+PG15:
+  EVENTOUT: 15
+  USART6_CTS: 8
+PG2:
+  EVENTOUT: 15
+  FSMC_A12: 12
+PG3:
+  EVENTOUT: 15
+  FSMC_A13: 12
+PG4:
+  EVENTOUT: 15
+  FSMC_A14: 12
+PG5:
+  EVENTOUT: 15
+  FSMC_A15: 12
+PG6:
+  EVENTOUT: 15
+  QUADSPI_BK1_NCS: 10
+PG7:
+  EVENTOUT: 15
+  USART6_CK: 8
+PG8:
+  EVENTOUT: 15
+  USART6_RTS: 8
+PG9:
+  EVENTOUT: 15
+  FSMC_NE2: 12
+  QUADSPI_BK2_IO2: 9
+  USART6_RX: 8
+PH0:
+  EVENTOUT: 15
+PH1:
+  EVENTOUT: 15
+PI8: {}

data/gpio_af/STM32F413.yaml

@@ -0,0 +1,816 @@
+PA0:
+  EVENTOUT: 15
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM5_CH1: 2
+  TIM8_ETR: 3
+  UART4_TX: 8
+  USART2_CTS: 7
+PA1:
+  EVENTOUT: 15
+  I2S4_SD: 5
+  QUADSPI_BK1_IO3: 9
+  SPI4_MOSI: 5
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  UART4_RX: 8
+  USART2_RTS: 7
+PA10:
+  DFSDM2_DATIN3: 3
+  EVENTOUT: 15
+  I2S2_SD: 5
+  I2S5_SD: 6
+  SPI2_MOSI: 5
+  SPI5_MOSI: 6
+  TIM1_CH3: 1
+  USART1_RX: 7
+  USB_OTG_FS_ID: 10
+PA11:
+  CAN1_RX: 9
+  DFSDM2_CKIN5: 3
+  EVENTOUT: 15
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  SPI4_MISO: 6
+  TIM1_CH4: 1
+  UART4_RX: 11
+  USART1_CTS: 7
+  USART6_TX: 8
+  USB_OTG_FS_DM: 10
+PA12:
+  CAN1_TX: 9
+  DFSDM2_DATIN5: 3
+  EVENTOUT: 15
+  SPI2_MISO: 5
+  SPI5_MISO: 6
+  TIM1_ETR: 1
+  UART4_TX: 11
+  USART1_RTS: 7
+  USART6_RX: 8
+  USB_OTG_FS_DP: 10
+PA13:
+  EVENTOUT: 15
+  SYS_JTMS-SWDIO: 0
+PA14:
+  EVENTOUT: 15
+  SYS_JTCK-SWCLK: 0
+PA15:
+  CAN3_TX: 11
+  EVENTOUT: 15
+  I2S1_WS: 5
+  I2S3_WS: 6
+  SAI1_MCLK_A: 10
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  UART7_TX: 8
+  USART1_TX: 7
+PA2:
+  EVENTOUT: 15
+  FSMC_D4: 12
+  FSMC_DA4: 12
+  I2S_CKIN: 5
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  TIM9_CH1: 3
+  USART2_TX: 7
+PA3:
+  EVENTOUT: 15
+  FSMC_D5: 12
+  FSMC_DA5: 12
+  I2S2_MCK: 5
+  SAI1_SD_B: 10
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  TIM9_CH2: 3
+  USART2_RX: 7
+PA4:
+  DFSDM1_DATIN1: 8
+  EVENTOUT: 15
+  FSMC_D6: 12
+  FSMC_DA6: 12
+  I2S1_WS: 5
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  USART2_CK: 7
+PA5:
+  DFSDM1_CKIN1: 8
+  EVENTOUT: 15
+  FSMC_D7: 12
+  FSMC_DA7: 12
+  I2S1_CK: 5
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM8_CH1N: 3
+PA6:
+  DFSDM2_CKIN1: 7
+  EVENTOUT: 15
+  I2S2_MCK: 6
+  QUADSPI_BK2_IO0: 10
+  SDIO_CMD: 12
+  SPI1_MISO: 5
+  TIM13_CH1: 9
+  TIM1_BKIN: 1
+  TIM3_CH1: 2
+  TIM8_BKIN: 3
+PA7:
+  DFSDM2_DATIN1: 7
+  EVENTOUT: 15
+  I2S1_SD: 5
+  QUADSPI_BK2_IO1: 10
+  SPI1_MOSI: 5
+  TIM14_CH1: 9
+  TIM1_CH1N: 1
+  TIM3_CH2: 2
+  TIM8_CH1N: 3
+PA8:
+  CAN3_RX: 11
+  DFSDM1_CKOUT: 6
+  EVENTOUT: 15
+  I2C3_SCL: 4
+  RCC_MCO_1: 0
+  SDIO_D1: 12
+  TIM1_CH1: 1
+  UART7_RX: 8
+  USART1_CK: 7
+  USB_OTG_FS_SOF: 10
+PA9:
+  DFSDM2_CKIN3: 3
+  EVENTOUT: 15
+  I2C3_SMBA: 4
+  I2S2_CK: 5
+  SDIO_D2: 12
+  SPI2_SCK: 5
+  TIM1_CH2: 1
+  USART1_TX: 7
+  USB_OTG_FS_VBUS: 10
+PB0:
+  EVENTOUT: 15
+  I2S5_CK: 6
+  SPI5_SCK: 6
+  TIM1_CH2N: 1
+  TIM3_CH3: 2
+  TIM8_CH2N: 3
+PB1:
+  DFSDM1_DATIN0: 8
+  EVENTOUT: 15
+  I2S5_WS: 6
+  QUADSPI_CLK: 9
+  SPI5_NSS: 6
+  TIM1_CH3N: 1
+  TIM3_CH4: 2
+  TIM8_CH3N: 3
+PB10:
+  DFSDM2_CKOUT: 10
+  EVENTOUT: 15
+  FMPI2C1_SCL: 9
+  I2C2_SCL: 4
+  I2S2_CK: 5
+  I2S3_MCK: 6
+  SDIO_D7: 12
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+  USART3_TX: 7
+PB11:
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  I2S_CKIN: 5
+  TIM2_CH4: 1
+  USART3_RX: 7
+PB12:
+  CAN2_RX: 9
+  DFSDM1_DATIN1: 10
+  EVENTOUT: 15
+  FSMC_D13: 12
+  FSMC_DA13: 12
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  I2S3_CK: 5
+  I2S4_WS: 6
+  SPI2_NSS: 5
+  SPI3_SCK: 7
+  SPI4_NSS: 6
+  TIM1_BKIN: 1
+  UART5_RX: 11
+  USART3_CK: 8
+PB13:
+  CAN2_TX: 9
+  DFSDM1_CKIN1: 10
+  EVENTOUT: 15
+  FMPI2C1_SMBA: 4
+  I2S2_CK: 5
+  I2S4_CK: 6
+  SPI2_SCK: 5
+  SPI4_SCK: 6
+  TIM1_CH1N: 1
+  UART5_TX: 11
+  USART3_CTS: 8
+PB14:
+  DFSDM1_DATIN2: 8
+  EVENTOUT: 15
+  FMPI2C1_SDA: 4
+  FSMC_D0: 10
+  FSMC_DA0: 10
+  I2S2_ext_SD: 6
+  SDIO_D6: 12
+  SPI2_MISO: 5
+  TIM12_CH1: 9
+  TIM1_CH2N: 1
+  TIM8_CH2N: 3
+  USART3_RTS: 7
+PB15:
+  DFSDM1_CKIN2: 8
+  EVENTOUT: 15
+  FMPI2C1_SCL: 4
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SDIO_CK: 12
+  SPI2_MOSI: 5
+  TIM12_CH2: 9
+  TIM1_CH3N: 1
+  TIM8_CH3N: 3
+PB2:
+  DFSDM1_CKIN0: 6
+  EVENTOUT: 15
+  LPTIM1_OUT: 1
+  QUADSPI_CLK: 9
+PB3:
+  CAN3_RX: 11
+  EVENTOUT: 15
+  FMPI2C1_SDA: 4
+  I2C2_SDA: 9
+  I2S1_CK: 5
+  I2S3_CK: 6
+  SAI1_SD_A: 10
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+  UART7_RX: 8
+  USART1_RX: 7
+PB4:
+  CAN3_TX: 11
+  EVENTOUT: 15
+  I2C3_SDA: 9
+  I2S3_ext_SD: 5
+  SAI1_SCK_A: 10
+  SDIO_D0: 12
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM3_CH1: 2
+  UART7_TX: 8
+PB5:
+  CAN2_RX: 9
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  I2S1_SD: 5
+  I2S3_SD: 6
+  LPTIM1_IN1: 1
+  SAI1_FS_A: 10
+  SDIO_D3: 12
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM3_CH2: 2
+  UART5_RX: 11
+PB6:
+  CAN2_TX: 9
+  DFSDM2_CKIN7: 6
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  LPTIM1_ETR: 1
+  QUADSPI_BK1_NCS: 10
+  SDIO_D0: 12
+  TIM4_CH1: 2
+  UART5_TX: 11
+  USART1_TX: 7
+PB7:
+  DFSDM2_DATIN7: 6
+  EVENTOUT: 15
+  FSMC_NL: 12
+  I2C1_SDA: 4
+  LPTIM1_IN2: 1
+  TIM4_CH2: 2
+  USART1_RX: 7
+PB8:
+  CAN1_RX: 8
+  DFSDM2_CKIN1: 7
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  I2C3_SDA: 9
+  I2S5_SD: 6
+  LPTIM1_OUT: 1
+  SDIO_D4: 12
+  SPI5_MOSI: 6
+  TIM10_CH1: 3
+  TIM4_CH3: 2
+  UART5_RX: 11
+PB9:
+  CAN1_TX: 8
+  DFSDM2_DATIN1: 6
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  I2C2_SDA: 9
+  I2S2_WS: 5
+  SDIO_D5: 12
+  SPI2_NSS: 5
+  TIM11_CH1: 3
+  TIM4_CH4: 2
+  UART5_TX: 11
+PC0:
+  DFSDM2_CKIN4: 3
+  EVENTOUT: 15
+  LPTIM1_IN1: 1
+  SAI1_MCLK_B: 7
+PC1:
+  DFSDM2_DATIN4: 3
+  EVENTOUT: 15
+  LPTIM1_OUT: 1
+  SAI1_SD_B: 7
+PC10:
+  DFSDM2_CKIN5: 3
+  EVENTOUT: 15
+  I2S3_CK: 6
+  QUADSPI_BK1_IO1: 9
+  SDIO_D2: 12
+  SPI3_SCK: 6
+  USART3_TX: 7
+PC11:
+  DFSDM2_DATIN5: 3
+  EVENTOUT: 15
+  FSMC_D2: 10
+  FSMC_DA2: 10
+  I2S3_ext_SD: 5
+  QUADSPI_BK2_NCS: 9
+  SDIO_D3: 12
+  SPI3_MISO: 6
+  UART4_RX: 8
+  USART3_RX: 7
+PC12:
+  EVENTOUT: 15
+  FSMC_D3: 10
+  FSMC_DA3: 10
+  I2S3_SD: 6
+  SDIO_CK: 12
+  SPI3_MOSI: 6
+  UART5_TX: 8
+  USART3_CK: 7
+PC13:
+  EVENTOUT: 15
+PC14:
+  EVENTOUT: 15
+PC15:
+  EVENTOUT: 15
+PC2:
+  DFSDM1_CKOUT: 8
+  DFSDM2_DATIN7: 3
+  EVENTOUT: 15
+  FSMC_NWE: 12
+  I2S2_ext_SD: 6
+  LPTIM1_IN2: 1
+  SAI1_SCK_B: 7
+  SPI2_MISO: 5
+PC3:
+  DFSDM2_CKIN7: 3
+  EVENTOUT: 15
+  FSMC_A0: 12
+  I2S2_SD: 5
+  LPTIM1_ETR: 1
+  SAI1_FS_B: 7
+  SPI2_MOSI: 5
+PC4:
+  DFSDM2_CKIN2: 3
+  EVENTOUT: 15
+  FSMC_NE4: 12
+  I2S1_MCK: 5
+  QUADSPI_BK2_IO2: 10
+PC5:
+  DFSDM2_DATIN2: 3
+  EVENTOUT: 15
+  FMPI2C1_SMBA: 4
+  FSMC_NOE: 12
+  QUADSPI_BK2_IO3: 10
+  USART3_RX: 7
+PC6:
+  DFSDM1_CKIN3: 6
+  DFSDM2_DATIN6: 7
+  EVENTOUT: 15
+  FMPI2C1_SCL: 4
+  FSMC_D1: 10
+  FSMC_DA1: 10
+  I2S2_MCK: 5
+  SDIO_D6: 12
+  TIM3_CH1: 2
+  TIM8_CH1: 3
+  USART6_TX: 8
+PC7:
+  DFSDM1_DATIN3: 10
+  DFSDM2_CKIN6: 7
+  EVENTOUT: 15
+  FMPI2C1_SDA: 4
+  I2S2_CK: 5
+  I2S3_MCK: 6
+  SDIO_D7: 12
+  SPI2_SCK: 5
+  TIM3_CH2: 2
+  TIM8_CH2: 3
+  USART6_RX: 8
+PC8:
+  DFSDM2_CKIN3: 7
+  EVENTOUT: 15
+  QUADSPI_BK1_IO2: 9
+  SDIO_D0: 12
+  TIM3_CH3: 2
+  TIM8_CH3: 3
+  USART6_CK: 8
+PC9:
+  DFSDM2_DATIN3: 7
+  EVENTOUT: 15
+  I2C3_SDA: 4
+  I2S_CKIN: 5
+  QUADSPI_BK1_IO0: 9
+  RCC_MCO_2: 0
+  SDIO_D1: 12
+  TIM3_CH4: 2
+  TIM8_CH4: 3
+PD0:
+  CAN1_RX: 9
+  DFSDM2_CKIN6: 3
+  EVENTOUT: 15
+  FSMC_D2: 12
+  FSMC_DA2: 12
+  UART4_RX: 11
+PD1:
+  CAN1_TX: 9
+  DFSDM2_DATIN6: 3
+  EVENTOUT: 15
+  FSMC_D3: 12
+  FSMC_DA3: 12
+  UART4_TX: 11
+PD10:
+  EVENTOUT: 15
+  FSMC_D15: 12
+  FSMC_DA15: 12
+  UART4_TX: 8
+  USART3_CK: 7
+PD11:
+  DFSDM2_DATIN2: 3
+  EVENTOUT: 15
+  FMPI2C1_SMBA: 4
+  FSMC_A16: 12
+  QUADSPI_BK1_IO0: 9
+  USART3_CTS: 7
+PD12:
+  DFSDM2_CKIN2: 3
+  EVENTOUT: 15
+  FMPI2C1_SCL: 4
+  FSMC_A17: 12
+  QUADSPI_BK1_IO1: 9
+  TIM4_CH1: 2
+  USART3_RTS: 7
+PD13:
+  EVENTOUT: 15
+  FMPI2C1_SDA: 4
+  FSMC_A18: 12
+  QUADSPI_BK1_IO3: 9
+  TIM4_CH2: 2
+PD14:
+  DFSDM2_CKIN0: 10
+  EVENTOUT: 15
+  FMPI2C1_SCL: 4
+  FSMC_D0: 12
+  FSMC_DA0: 12
+  TIM4_CH3: 2
+  UART9_RX: 11
+PD15:
+  DFSDM2_DATIN0: 10
+  EVENTOUT: 15
+  FMPI2C1_SDA: 4
+  FSMC_D1: 12
+  FSMC_DA1: 12
+  TIM4_CH4: 2
+  UART9_TX: 11
+PD2:
+  DFSDM2_CKOUT: 3
+  EVENTOUT: 15
+  FSMC_NWE: 10
+  SDIO_CMD: 12
+  TIM3_ETR: 2
+  UART5_RX: 8
+PD3:
+  DFSDM1_DATIN0: 6
+  EVENTOUT: 15
+  FSMC_CLK: 12
+  I2S2_CK: 5
+  QUADSPI_CLK: 9
+  SPI2_SCK: 5
+  SYS_TRACED1: 0
+  USART2_CTS: 7
+PD4:
+  DFSDM1_CKIN0: 6
+  EVENTOUT: 15
+  FSMC_NOE: 12
+  USART2_RTS: 7
+PD5:
+  DFSDM2_CKOUT: 3
+  EVENTOUT: 15
+  FSMC_NWE: 12
+  USART2_TX: 7
+PD6:
+  DFSDM1_DATIN1: 6
+  EVENTOUT: 15
+  FSMC_NWAIT: 12
+  I2S3_SD: 5
+  SPI3_MOSI: 5
+  USART2_RX: 7
+PD7:
+  DFSDM1_CKIN1: 6
+  EVENTOUT: 15
+  FSMC_NE1: 12
+  USART2_CK: 7
+PD8:
+  EVENTOUT: 15
+  FSMC_D13: 12
+  FSMC_DA13: 12
+  USART3_TX: 7
+PD9:
+  EVENTOUT: 15
+  FSMC_D14: 12
+  FSMC_DA14: 12
+  USART3_RX: 7
+PE0:
+  DFSDM2_CKIN4: 3
+  EVENTOUT: 15
+  FSMC_NBL0: 12
+  TIM4_ETR: 2
+  UART8_RX: 8
+PE1:
+  DFSDM2_DATIN4: 3
+  EVENTOUT: 15
+  FSMC_NBL1: 12
+  UART8_TX: 8
+PE10:
+  DFSDM2_DATIN0: 3
+  EVENTOUT: 15
+  FSMC_D7: 12
+  FSMC_DA7: 12
+  QUADSPI_BK2_IO3: 10
+  TIM1_CH2N: 1
+PE11:
+  DFSDM2_CKIN0: 3
+  EVENTOUT: 15
+  FSMC_D8: 12
+  FSMC_DA8: 12
+  I2S4_WS: 5
+  I2S5_WS: 6
+  SPI4_NSS: 5
+  SPI5_NSS: 6
+  TIM1_CH2: 1
+PE12:
+  DFSDM2_DATIN7: 3
+  EVENTOUT: 15
+  FSMC_D9: 12
+  FSMC_DA9: 12
+  I2S4_CK: 5
+  I2S5_CK: 6
+  SPI4_SCK: 5
+  SPI5_SCK: 6
+  TIM1_CH3N: 1
+PE13:
+  DFSDM2_CKIN7: 3
+  EVENTOUT: 15
+  FSMC_D10: 12
+  FSMC_DA10: 12
+  SPI4_MISO: 5
+  SPI5_MISO: 6
+  TIM1_CH3: 1
+PE14:
+  DFSDM2_DATIN1: 10
+  EVENTOUT: 15
+  FSMC_D11: 12
+  FSMC_DA11: 12
+  I2S4_SD: 5
+  I2S5_SD: 6
+  SPI4_MOSI: 5
+  SPI5_MOSI: 6
+  TIM1_CH4: 1
+PE15:
+  DFSDM2_CKIN1: 10
+  EVENTOUT: 15
+  FSMC_D12: 12
+  FSMC_DA12: 12
+  TIM1_BKIN: 1
+PE2:
+  EVENTOUT: 15
+  FSMC_A23: 12
+  I2S4_CK: 5
+  I2S5_CK: 6
+  QUADSPI_BK1_IO2: 9
+  SAI1_MCLK_A: 7
+  SPI4_SCK: 5
+  SPI5_SCK: 6
+  SYS_TRACECLK: 0
+  UART10_RX: 11
+PE3:
+  EVENTOUT: 15
+  FSMC_A19: 12
+  SAI1_SD_B: 7
+  SYS_TRACED0: 0
+  UART10_TX: 11
+PE4:
+  DFSDM1_DATIN3: 8
+  EVENTOUT: 15
+  FSMC_A20: 12
+  I2S4_WS: 5
+  I2S5_WS: 6
+  SAI1_SD_A: 7
+  SPI4_NSS: 5
+  SPI5_NSS: 6
+  SYS_TRACED1: 0
+PE5:
+  DFSDM1_CKIN3: 8
+  EVENTOUT: 15
+  FSMC_A21: 12
+  SAI1_SCK_A: 7
+  SPI4_MISO: 5
+  SPI5_MISO: 6
+  SYS_TRACED2: 0
+  TIM9_CH1: 3
+PE6:
+  EVENTOUT: 15
+  FSMC_A22: 12
+  I2S4_SD: 5
+  I2S5_SD: 6
+  SAI1_FS_A: 7
+  SPI4_MOSI: 5
+  SPI5_MOSI: 6
+  SYS_TRACED3: 0
+  TIM9_CH2: 3
+PE7:
+  DFSDM1_DATIN2: 6
+  EVENTOUT: 15
+  FSMC_D4: 12
+  FSMC_DA4: 12
+  QUADSPI_BK2_IO0: 10
+  TIM1_ETR: 1
+  UART7_RX: 8
+PE8:
+  DFSDM1_CKIN2: 6
+  EVENTOUT: 15
+  FSMC_D5: 12
+  FSMC_DA5: 12
+  QUADSPI_BK2_IO1: 10
+  TIM1_CH1N: 1
+  UART7_TX: 8
+PE9:
+  DFSDM1_CKOUT: 6
+  EVENTOUT: 15
+  FSMC_D6: 12
+  FSMC_DA6: 12
+  QUADSPI_BK2_IO2: 10
+  TIM1_CH1: 1
+PF0:
+  EVENTOUT: 15
+  FSMC_A0: 12
+  I2C2_SDA: 4
+PF1:
+  EVENTOUT: 15
+  FSMC_A1: 12
+  I2C2_SCL: 4
+PF10:
+  EVENTOUT: 15
+  TIM1_ETR: 1
+  TIM5_CH4: 2
+PF11:
+  EVENTOUT: 15
+  TIM8_ETR: 3
+PF12:
+  EVENTOUT: 15
+  FSMC_A6: 12
+  TIM8_BKIN: 3
+PF13:
+  EVENTOUT: 15
+  FMPI2C1_SMBA: 4
+  FSMC_A7: 12
+PF14:
+  EVENTOUT: 15
+  FMPI2C1_SCL: 4
+  FSMC_A8: 12
+PF15:
+  EVENTOUT: 15
+  FMPI2C1_SDA: 4
+  FSMC_A9: 12
+PF2:
+  EVENTOUT: 15
+  FSMC_A2: 12
+  I2C2_SMBA: 4
+PF3:
+  EVENTOUT: 15
+  FSMC_A3: 12
+  TIM5_CH1: 2
+PF4:
+  EVENTOUT: 15
+  FSMC_A4: 12
+  TIM5_CH2: 2
+PF5:
+  EVENTOUT: 15
+  FSMC_A5: 12
+  TIM5_CH3: 2
+PF6:
+  EVENTOUT: 15
+  QUADSPI_BK1_IO3: 9
+  SAI1_SD_B: 7
+  SYS_TRACED0: 0
+  TIM10_CH1: 3
+  UART7_RX: 8
+PF7:
+  EVENTOUT: 15
+  QUADSPI_BK1_IO2: 9
+  SAI1_MCLK_B: 7
+  SYS_TRACED1: 0
+  TIM11_CH1: 3
+  UART7_TX: 8
+PF8:
+  EVENTOUT: 15
+  QUADSPI_BK1_IO0: 10
+  SAI1_SCK_B: 7
+  TIM13_CH1: 9
+  UART8_RX: 8
+PF9:
+  EVENTOUT: 15
+  QUADSPI_BK1_IO1: 10
+  SAI1_FS_B: 7
+  TIM14_CH1: 9
+  UART8_TX: 8
+PG0:
+  CAN1_RX: 9
+  EVENTOUT: 15
+  FSMC_A10: 12
+  UART9_RX: 11
+PG1:
+  CAN1_TX: 9
+  EVENTOUT: 15
+  FSMC_A11: 12
+  UART9_TX: 11
+PG10:
+  EVENTOUT: 15
+  FSMC_NE3: 12
+PG11:
+  CAN2_RX: 9
+  EVENTOUT: 15
+  UART10_RX: 11
+PG12:
+  CAN2_TX: 9
+  EVENTOUT: 15
+  FSMC_NE4: 12
+  UART10_TX: 11
+  USART6_RTS: 8
+PG13:
+  EVENTOUT: 15
+  FSMC_A24: 12
+  SYS_TRACED2: 0
+  USART6_CTS: 8
+PG14:
+  EVENTOUT: 15
+  FSMC_A25: 12
+  QUADSPI_BK2_IO3: 9
+  SYS_TRACED3: 0
+  USART6_TX: 8
+PG15:
+  EVENTOUT: 15
+  USART6_CTS: 8
+PG2:
+  EVENTOUT: 15
+  FSMC_A12: 12
+PG3:
+  EVENTOUT: 15
+  FSMC_A13: 12
+PG4:
+  EVENTOUT: 15
+  FSMC_A14: 12
+PG5:
+  EVENTOUT: 15
+  FSMC_A15: 12
+PG6:
+  EVENTOUT: 15
+  QUADSPI_BK1_NCS: 10
+PG7:
+  EVENTOUT: 15
+  USART6_CK: 8
+PG8:
+  EVENTOUT: 15
+  USART6_RTS: 8
+PG9:
+  EVENTOUT: 15
+  FSMC_NE2: 12
+  QUADSPI_BK2_IO2: 9
+  USART6_RX: 8
+PH0:
+  EVENTOUT: 15
+PH1:
+  EVENTOUT: 15
+PI8: {}

data/gpio_af/STM32F417.yaml

@@ -0,0 +1,571 @@
+PA0:
+  ETH_CRS: 11
+  SYS_WKUP: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM5_CH1: 2
+  TIM8_ETR: 3
+  UART4_TX: 8
+  USART2_CTS: 7
+PA1:
+  ETH_REF_CLK: 11
+  ETH_RX_CLK: 11
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  UART4_RX: 8
+  USART2_RTS: 7
+PA10:
+  DCMI_D1: 13
+  TIM1_CH3: 1
+  USART1_RX: 7
+  USB_OTG_FS_ID: 10
+PA11:
+  CAN1_RX: 9
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USB_OTG_FS_DM: 10
+PA12:
+  CAN1_TX: 9
+  TIM1_ETR: 1
+  USART1_RTS: 7
+  USB_OTG_FS_DP: 10
+PA13:
+  SYS_JTMS-SWDIO: 0
+PA14:
+  SYS_JTCK-SWCLK: 0
+PA15:
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+PA2:
+  ETH_MDIO: 11
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  TIM9_CH1: 3
+  USART2_TX: 7
+PA3:
+  ETH_COL: 11
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  TIM9_CH2: 3
+  USART2_RX: 7
+  USB_OTG_HS_ULPI_D0: 10
+PA4:
+  DCMI_HSYNC: 13
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  USART2_CK: 7
+  USB_OTG_HS_SOF: 12
+PA5:
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM8_CH1N: 3
+  USB_OTG_HS_ULPI_CK: 10
+PA6:
+  DCMI_PIXCLK: 13
+  SPI1_MISO: 5
+  TIM13_CH1: 9
+  TIM1_BKIN: 1
+  TIM3_CH1: 2
+  TIM8_BKIN: 3
+PA7:
+  ETH_CRS_DV: 11
+  ETH_RX_DV: 11
+  SPI1_MOSI: 5
+  TIM14_CH1: 9
+  TIM1_CH1N: 1
+  TIM3_CH2: 2
+  TIM8_CH1N: 3
+PA8:
+  I2C3_SCL: 4
+  RCC_MCO_1: 0
+  TIM1_CH1: 1
+  USART1_CK: 7
+  USB_OTG_FS_SOF: 10
+PA9:
+  DCMI_D0: 13
+  I2C3_SMBA: 4
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  ETH_RXD2: 11
+  TIM1_CH2N: 1
+  TIM3_CH3: 2
+  TIM8_CH2N: 3
+  USB_OTG_HS_ULPI_D1: 10
+PB1:
+  ETH_RXD3: 11
+  TIM1_CH3N: 1
+  TIM3_CH4: 2
+  TIM8_CH3N: 3
+  USB_OTG_HS_ULPI_D2: 10
+PB10:
+  ETH_RX_ER: 11
+  I2C2_SCL: 4
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+  USART3_TX: 7
+  USB_OTG_HS_ULPI_D3: 10
+PB11:
+  ETH_TX_EN: 11
+  I2C2_SDA: 4
+  TIM2_CH4: 1
+  USART3_RX: 7
+  USB_OTG_HS_ULPI_D4: 10
+PB12:
+  CAN2_RX: 9
+  ETH_TXD0: 11
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM1_BKIN: 1
+  USART3_CK: 7
+  USB_OTG_HS_ID: 12
+  USB_OTG_HS_ULPI_D5: 10
+PB13:
+  CAN2_TX: 9
+  ETH_TXD1: 11
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM1_CH1N: 1
+  USART3_CTS: 7
+  USB_OTG_HS_ULPI_D6: 10
+PB14:
+  I2S2_ext_SD: 6
+  SPI2_MISO: 5
+  TIM12_CH1: 9
+  TIM1_CH2N: 1
+  TIM8_CH2N: 3
+  USART3_RTS: 7
+  USB_OTG_HS_DM: 12
+PB15:
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM12_CH2: 9
+  TIM1_CH3N: 1
+  TIM8_CH3N: 3
+  USB_OTG_HS_DP: 12
+PB2: {}
+PB3:
+  I2S3_CK: 6
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+PB4:
+  I2S3_ext_SD: 7
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM3_CH1: 2
+PB5:
+  CAN2_RX: 9
+  DCMI_D10: 13
+  ETH_PPS_OUT: 11
+  I2C1_SMBA: 4
+  I2S3_SD: 6
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM3_CH2: 2
+  USB_OTG_HS_ULPI_D7: 10
+PB6:
+  CAN2_TX: 9
+  DCMI_D5: 13
+  I2C1_SCL: 4
+  TIM4_CH1: 2
+  USART1_TX: 7
+PB7:
+  DCMI_VSYNC: 13
+  FSMC_NL: 12
+  I2C1_SDA: 4
+  TIM4_CH2: 2
+  USART1_RX: 7
+PB8:
+  CAN1_RX: 9
+  DCMI_D6: 13
+  ETH_TXD3: 11
+  I2C1_SCL: 4
+  SDIO_D4: 12
+  TIM10_CH1: 3
+  TIM4_CH3: 2
+PB9:
+  CAN1_TX: 9
+  DCMI_D7: 13
+  I2C1_SDA: 4
+  I2S2_WS: 5
+  SDIO_D5: 12
+  SPI2_NSS: 5
+  TIM11_CH1: 3
+  TIM4_CH4: 2
+PC0:
+  USB_OTG_HS_ULPI_STP: 10
+PC1:
+  ETH_MDC: 11
+PC10:
+  DCMI_D8: 13
+  I2S3_CK: 6
+  SDIO_D2: 12
+  SPI3_SCK: 6
+  UART4_TX: 8
+  USART3_TX: 7
+PC11:
+  DCMI_D4: 13
+  I2S3_ext_SD: 5
+  SDIO_D3: 12
+  SPI3_MISO: 6
+  UART4_RX: 8
+  USART3_RX: 7
+PC12:
+  DCMI_D9: 13
+  I2S3_SD: 6
+  SDIO_CK: 12
+  SPI3_MOSI: 6
+  UART5_TX: 8
+  USART3_CK: 7
+PC13:
+  RTC_AF1: 0
+PC14:
+  RCC_OSC32_IN: 0
+PC15:
+  RCC_OSC32_OUT: 0
+PC2:
+  ETH_TXD2: 11
+  I2S2_ext_SD: 6
+  SPI2_MISO: 5
+  USB_OTG_HS_ULPI_DIR: 10
+PC3:
+  ETH_TX_CLK: 11
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  USB_OTG_HS_ULPI_NXT: 10
+PC4:
+  ETH_RXD0: 11
+PC5:
+  ETH_RXD1: 11
+PC6:
+  DCMI_D0: 13
+  I2S2_MCK: 5
+  SDIO_D6: 12
+  TIM3_CH1: 2
+  TIM8_CH1: 3
+  USART6_TX: 8
+PC7:
+  DCMI_D1: 13
+  I2S3_MCK: 6
+  SDIO_D7: 12
+  TIM3_CH2: 2
+  TIM8_CH2: 3
+  USART6_RX: 8
+PC8:
+  DCMI_D2: 13
+  SDIO_D0: 12
+  TIM3_CH3: 2
+  TIM8_CH3: 3
+  USART6_CK: 8
+PC9:
+  DCMI_D3: 13
+  I2C3_SDA: 4
+  I2S_CKIN: 5
+  RCC_MCO_2: 0
+  SDIO_D1: 12
+  TIM3_CH4: 2
+  TIM8_CH4: 3
+PD0:
+  CAN1_RX: 9
+  FSMC_D2: 12
+  FSMC_DA2: 12
+PD1:
+  CAN1_TX: 9
+  FSMC_D3: 12
+  FSMC_DA3: 12
+PD10:
+  FSMC_D15: 12
+  FSMC_DA15: 12
+  USART3_CK: 7
+PD11:
+  FSMC_A16: 12
+  FSMC_CLE: 12
+  USART3_CTS: 7
+PD12:
+  FSMC_A17: 12
+  FSMC_ALE: 12
+  TIM4_CH1: 2
+  USART3_RTS: 7
+PD13:
+  FSMC_A18: 12
+  TIM4_CH2: 2
+PD14:
+  FSMC_D0: 12
+  FSMC_DA0: 12
+  TIM4_CH3: 2
+PD15:
+  FSMC_D1: 12
+  FSMC_DA1: 12
+  TIM4_CH4: 2
+PD2:
+  DCMI_D11: 13
+  SDIO_CMD: 12
+  TIM3_ETR: 2
+  UART5_RX: 8
+PD3:
+  FSMC_CLK: 12
+  USART2_CTS: 7
+PD4:
+  FSMC_NOE: 12
+  USART2_RTS: 7
+PD5:
+  FSMC_NWE: 12
+  USART2_TX: 7
+PD6:
+  FSMC_NWAIT: 12
+  USART2_RX: 7
+PD7:
+  FSMC_NCE2: 12
+  FSMC_NE1: 12
+  USART2_CK: 7
+PD8:
+  FSMC_D13: 12
+  FSMC_DA13: 12
+  USART3_TX: 7
+PD9:
+  FSMC_D14: 12
+  FSMC_DA14: 12
+  USART3_RX: 7
+PE0:
+  DCMI_D2: 13
+  FSMC_NBL0: 12
+  TIM4_ETR: 2
+PE1:
+  DCMI_D3: 13
+  FSMC_NBL1: 12
+PE10:
+  FSMC_D7: 12
+  FSMC_DA7: 12
+  TIM1_CH2N: 1
+PE11:
+  FSMC_D8: 12
+  FSMC_DA8: 12
+  TIM1_CH2: 1
+PE12:
+  FSMC_D9: 12
+  FSMC_DA9: 12
+  TIM1_CH3N: 1
+PE13:
+  FSMC_D10: 12
+  FSMC_DA10: 12
+  TIM1_CH3: 1
+PE14:
+  FSMC_D11: 12
+  FSMC_DA11: 12
+  TIM1_CH4: 1
+PE15:
+  FSMC_D12: 12
+  FSMC_DA12: 12
+  TIM1_BKIN: 1
+PE2:
+  ETH_TXD3: 11
+  FSMC_A23: 12
+  SYS_TRACECLK: 0
+PE3:
+  FSMC_A19: 12
+  SYS_TRACED0: 0
+PE4:
+  DCMI_D4: 13
+  FSMC_A20: 12
+  SYS_TRACED1: 0
+PE5:
+  DCMI_D6: 13
+  FSMC_A21: 12
+  SYS_TRACED2: 0
+  TIM9_CH1: 3
+PE6:
+  DCMI_D7: 13
+  FSMC_A22: 12
+  SYS_TRACED3: 0
+  TIM9_CH2: 3
+PE7:
+  FSMC_D4: 12
+  FSMC_DA4: 12
+  TIM1_ETR: 1
+PE8:
+  FSMC_D5: 12
+  FSMC_DA5: 12
+  TIM1_CH1N: 1
+PE9:
+  FSMC_D6: 12
+  FSMC_DA6: 12
+  TIM1_CH1: 1
+PF0:
+  FSMC_A0: 12
+  I2C2_SDA: 4
+PF1:
+  FSMC_A1: 12
+  I2C2_SCL: 4
+PF10:
+  FSMC_INTR: 12
+PF11:
+  DCMI_D12: 13
+PF12:
+  FSMC_A6: 12
+PF13:
+  FSMC_A7: 12
+PF14:
+  FSMC_A8: 12
+PF15:
+  FSMC_A9: 12
+PF2:
+  FSMC_A2: 12
+  I2C2_SMBA: 4
+PF3:
+  FSMC_A3: 12
+PF4:
+  FSMC_A4: 12
+PF5:
+  FSMC_A5: 12
+PF6:
+  FSMC_NIORD: 12
+  TIM10_CH1: 3
+PF7:
+  FSMC_NREG: 12
+  TIM11_CH1: 3
+PF8:
+  FSMC_NIOWR: 12
+  TIM13_CH1: 9
+PF9:
+  FSMC_CD: 12
+  TIM14_CH1: 9
+PG0:
+  FSMC_A10: 12
+PG1:
+  FSMC_A11: 12
+PG10:
+  FSMC_NCE4_1: 12
+  FSMC_NE3: 12
+PG11:
+  ETH_TX_EN: 11
+  FSMC_NCE4_2: 12
+PG12:
+  FSMC_NE4: 12
+  USART6_RTS: 8
+PG13:
+  ETH_TXD0: 11
+  FSMC_A24: 12
+  USART6_CTS: 8
+PG14:
+  ETH_TXD1: 11
+  FSMC_A25: 12
+  USART6_TX: 8
+PG15:
+  DCMI_D13: 13
+  USART6_CTS: 8
+PG2:
+  FSMC_A12: 12
+PG3:
+  FSMC_A13: 12
+PG4:
+  FSMC_A14: 12
+PG5:
+  FSMC_A15: 12
+PG6:
+  FSMC_INT2: 12
+PG7:
+  FSMC_INT3: 12
+  USART6_CK: 8
+PG8:
+  ETH_PPS_OUT: 11
+  USART6_RTS: 8
+PG9:
+  FSMC_NCE3: 12
+  FSMC_NE2: 12
+  USART6_RX: 8
+PH0:
+  RCC_OSC_IN: 0
+PH1:
+  RCC_OSC_OUT: 0
+PH10:
+  DCMI_D1: 13
+  TIM5_CH1: 2
+PH11:
+  DCMI_D2: 13
+  TIM5_CH2: 2
+PH12:
+  DCMI_D3: 13
+  TIM5_CH3: 2
+PH13:
+  CAN1_TX: 9
+  TIM8_CH1N: 3
+PH14:
+  DCMI_D4: 13
+  TIM8_CH2N: 3
+PH15:
+  DCMI_D11: 13
+  TIM8_CH3N: 3
+PH2:
+  ETH_CRS: 11
+PH3:
+  ETH_COL: 11
+PH4:
+  I2C2_SCL: 4
+  USB_OTG_HS_ULPI_NXT: 10
+PH5:
+  I2C2_SDA: 4
+PH6:
+  ETH_RXD2: 11
+  I2C2_SMBA: 4
+  TIM12_CH1: 9
+PH7:
+  ETH_RXD3: 11
+  I2C3_SCL: 4
+PH8:
+  DCMI_HSYNC: 13
+  I2C3_SDA: 4
+PH9:
+  DCMI_D0: 13
+  I2C3_SMBA: 4
+  TIM12_CH2: 9
+PI0:
+  DCMI_D13: 13
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM5_CH4: 2
+PI1:
+  DCMI_D8: 13
+  I2S2_CK: 5
+  SPI2_SCK: 5
+PI10:
+  ETH_RX_ER: 11
+PI11:
+  USB_OTG_HS_ULPI_DIR: 10
+PI2:
+  DCMI_D9: 13
+  I2S2_ext_SD: 6
+  SPI2_MISO: 5
+  TIM8_CH4: 3
+PI3:
+  DCMI_D10: 13
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIM8_ETR: 3
+PI4:
+  DCMI_D5: 13
+  TIM8_BKIN: 3
+PI5:
+  DCMI_VSYNC: 13
+  TIM8_CH1: 3
+PI6:
+  DCMI_D6: 13
+  TIM8_CH2: 3
+PI7:
+  DCMI_D7: 13
+  TIM8_CH3: 3
+PI8:
+  RTC_AF2: 0
+PI9:
+  CAN1_RX: 9

data/gpio_af/STM32F427.yaml

@@ -0,0 +1,756 @@
+PA0:
+  ETH_CRS: 11
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM5_CH1: 2
+  TIM8_ETR: 3
+  UART4_TX: 8
+  USART2_CTS: 7
+PA1:
+  ETH_REF_CLK: 11
+  ETH_RX_CLK: 11
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  UART4_RX: 8
+  USART2_RTS: 7
+PA10:
+  DCMI_D1: 13
+  TIM1_CH3: 1
+  USART1_RX: 7
+  USB_OTG_FS_ID: 10
+PA11:
+  CAN1_RX: 9
+  LTDC_R4: 14
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USB_OTG_FS_DM: 10
+PA12:
+  CAN1_TX: 9
+  LTDC_R5: 14
+  TIM1_ETR: 1
+  USART1_RTS: 7
+  USB_OTG_FS_DP: 10
+PA13:
+  SYS_JTMS-SWDIO: 0
+PA14:
+  SYS_JTCK-SWCLK: 0
+PA15:
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+PA2:
+  ETH_MDIO: 11
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  TIM9_CH1: 3
+  USART2_TX: 7
+PA3:
+  ETH_COL: 11
+  LTDC_B5: 14
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  TIM9_CH2: 3
+  USART2_RX: 7
+  USB_OTG_HS_ULPI_D0: 10
+PA4:
+  DCMI_HSYNC: 13
+  I2S3_WS: 6
+  LTDC_VSYNC: 14
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  USART2_CK: 7
+  USB_OTG_HS_SOF: 12
+PA5:
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM8_CH1N: 3
+  USB_OTG_HS_ULPI_CK: 10
+PA6:
+  DCMI_PIXCLK: 13
+  LTDC_G2: 14
+  SPI1_MISO: 5
+  TIM13_CH1: 9
+  TIM1_BKIN: 1
+  TIM3_CH1: 2
+  TIM8_BKIN: 3
+PA7:
+  ETH_CRS_DV: 11
+  ETH_RX_DV: 11
+  SPI1_MOSI: 5
+  TIM14_CH1: 9
+  TIM1_CH1N: 1
+  TIM3_CH2: 2
+  TIM8_CH1N: 3
+PA8:
+  I2C3_SCL: 4
+  LTDC_R6: 14
+  RCC_MCO_1: 0
+  TIM1_CH1: 1
+  USART1_CK: 7
+  USB_OTG_FS_SOF: 10
+PA9:
+  DCMI_D0: 13
+  I2C3_SMBA: 4
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  ETH_RXD2: 11
+  LTDC_R3: 9
+  TIM1_CH2N: 1
+  TIM3_CH3: 2
+  TIM8_CH2N: 3
+  USB_OTG_HS_ULPI_D1: 10
+PB1:
+  ETH_RXD3: 11
+  LTDC_R6: 9
+  TIM1_CH3N: 1
+  TIM3_CH4: 2
+  TIM8_CH3N: 3
+  USB_OTG_HS_ULPI_D2: 10
+PB10:
+  ETH_RX_ER: 11
+  I2C2_SCL: 4
+  I2S2_CK: 5
+  LTDC_G4: 14
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+  USART3_TX: 7
+  USB_OTG_HS_ULPI_D3: 10
+PB11:
+  ETH_TX_EN: 11
+  I2C2_SDA: 4
+  LTDC_G5: 14
+  TIM2_CH4: 1
+  USART3_RX: 7
+  USB_OTG_HS_ULPI_D4: 10
+PB12:
+  CAN2_RX: 9
+  ETH_TXD0: 11
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM1_BKIN: 1
+  USART3_CK: 7
+  USB_OTG_HS_ID: 12
+  USB_OTG_HS_ULPI_D5: 10
+PB13:
+  CAN2_TX: 9
+  ETH_TXD1: 11
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM1_CH1N: 1
+  USART3_CTS: 7
+  USB_OTG_HS_ULPI_D6: 10
+PB14:
+  I2S2_ext_SD: 6
+  SPI2_MISO: 5
+  TIM12_CH1: 9
+  TIM1_CH2N: 1
+  TIM8_CH2N: 3
+  USART3_RTS: 7
+  USB_OTG_HS_DM: 12
+PB15:
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM12_CH2: 9
+  TIM1_CH3N: 1
+  TIM8_CH3N: 3
+  USB_OTG_HS_DP: 12
+PB2: {}
+PB3:
+  I2S3_CK: 6
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+PB4:
+  I2S3_ext_SD: 7
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM3_CH1: 2
+PB5:
+  CAN2_RX: 9
+  DCMI_D10: 13
+  ETH_PPS_OUT: 11
+  FMC_SDCKE1: 12
+  I2C1_SMBA: 4
+  I2S3_SD: 6
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM3_CH2: 2
+  USB_OTG_HS_ULPI_D7: 10
+PB6:
+  CAN2_TX: 9
+  DCMI_D5: 13
+  FMC_SDNE1: 12
+  I2C1_SCL: 4
+  TIM4_CH1: 2
+  USART1_TX: 7
+PB7:
+  DCMI_VSYNC: 13
+  FMC_NL: 12
+  I2C1_SDA: 4
+  TIM4_CH2: 2
+  USART1_RX: 7
+PB8:
+  CAN1_RX: 9
+  DCMI_D6: 13
+  ETH_TXD3: 11
+  I2C1_SCL: 4
+  LTDC_B6: 14
+  SDIO_D4: 12
+  TIM10_CH1: 3
+  TIM4_CH3: 2
+PB9:
+  CAN1_TX: 9
+  DCMI_D7: 13
+  I2C1_SDA: 4
+  I2S2_WS: 5
+  LTDC_B7: 14
+  SDIO_D5: 12
+  SPI2_NSS: 5
+  TIM11_CH1: 3
+  TIM4_CH4: 2
+PC0:
+  FMC_SDNWE: 12
+  USB_OTG_HS_ULPI_STP: 10
+PC1:
+  ETH_MDC: 11
+PC10:
+  DCMI_D8: 13
+  I2S3_CK: 6
+  LTDC_R2: 14
+  SDIO_D2: 12
+  SPI3_SCK: 6
+  UART4_TX: 8
+  USART3_TX: 7
+PC11:
+  DCMI_D4: 13
+  I2S3_ext_SD: 5
+  SDIO_D3: 12
+  SPI3_MISO: 6
+  UART4_RX: 8
+  USART3_RX: 7
+PC12:
+  DCMI_D9: 13
+  I2S3_SD: 6
+  SDIO_CK: 12
+  SPI3_MOSI: 6
+  UART5_TX: 8
+  USART3_CK: 7
+PC13: {}
+PC14: {}
+PC15: {}
+PC2:
+  ETH_TXD2: 11
+  FMC_SDNE0: 12
+  I2S2_ext_SD: 6
+  SPI2_MISO: 5
+  USB_OTG_HS_ULPI_DIR: 10
+PC3:
+  ETH_TX_CLK: 11
+  FMC_SDCKE0: 12
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  USB_OTG_HS_ULPI_NXT: 10
+PC4:
+  ETH_RXD0: 11
+PC5:
+  ETH_RXD1: 11
+PC6:
+  DCMI_D0: 13
+  I2S2_MCK: 5
+  LTDC_HSYNC: 14
+  SDIO_D6: 12
+  TIM3_CH1: 2
+  TIM8_CH1: 3
+  USART6_TX: 8
+PC7:
+  DCMI_D1: 13
+  I2S3_MCK: 6
+  LTDC_G6: 14
+  SDIO_D7: 12
+  TIM3_CH2: 2
+  TIM8_CH2: 3
+  USART6_RX: 8
+PC8:
+  DCMI_D2: 13
+  SDIO_D0: 12
+  TIM3_CH3: 2
+  TIM8_CH3: 3
+  USART6_CK: 8
+PC9:
+  DCMI_D3: 13
+  I2C3_SDA: 4
+  I2S_CKIN: 5
+  RCC_MCO_2: 0
+  SDIO_D1: 12
+  TIM3_CH4: 2
+  TIM8_CH4: 3
+PD0:
+  CAN1_RX: 9
+  FMC_D2: 12
+  FMC_DA2: 12
+PD1:
+  CAN1_TX: 9
+  FMC_D3: 12
+  FMC_DA3: 12
+PD10:
+  FMC_D15: 12
+  FMC_DA15: 12
+  LTDC_B3: 14
+  USART3_CK: 7
+PD11:
+  FMC_A16: 12
+  FMC_CLE: 12
+  USART3_CTS: 7
+PD12:
+  FMC_A17: 12
+  FMC_ALE: 12
+  TIM4_CH1: 2
+  USART3_RTS: 7
+PD13:
+  FMC_A18: 12
+  TIM4_CH2: 2
+PD14:
+  FMC_D0: 12
+  FMC_DA0: 12
+  TIM4_CH3: 2
+PD15:
+  FMC_D1: 12
+  FMC_DA1: 12
+  TIM4_CH4: 2
+PD2:
+  DCMI_D11: 13
+  SDIO_CMD: 12
+  TIM3_ETR: 2
+  UART5_RX: 8
+PD3:
+  DCMI_D5: 13
+  FMC_CLK: 12
+  I2S2_CK: 5
+  LTDC_G7: 14
+  SPI2_SCK: 5
+  USART2_CTS: 7
+PD4:
+  FMC_NOE: 12
+  USART2_RTS: 7
+PD5:
+  FMC_NWE: 12
+  USART2_TX: 7
+PD6:
+  DCMI_D10: 13
+  FMC_NWAIT: 12
+  I2S3_SD: 5
+  LTDC_B2: 14
+  SAI1_SD_A: 6
+  SPI3_MOSI: 5
+  USART2_RX: 7
+PD7:
+  FMC_NCE2: 12
+  FMC_NE1: 12
+  USART2_CK: 7
+PD8:
+  FMC_D13: 12
+  FMC_DA13: 12
+  USART3_TX: 7
+PD9:
+  FMC_D14: 12
+  FMC_DA14: 12
+  USART3_RX: 7
+PE0:
+  DCMI_D2: 13
+  FMC_NBL0: 12
+  TIM4_ETR: 2
+  UART8_RX: 8
+PE1:
+  DCMI_D3: 13
+  FMC_NBL1: 12
+  UART8_TX: 8
+PE10:
+  FMC_D7: 12
+  FMC_DA7: 12
+  TIM1_CH2N: 1
+PE11:
+  FMC_D8: 12
+  FMC_DA8: 12
+  LTDC_G3: 14
+  SPI4_NSS: 5
+  TIM1_CH2: 1
+PE12:
+  FMC_D9: 12
+  FMC_DA9: 12
+  LTDC_B4: 14
+  SPI4_SCK: 5
+  TIM1_CH3N: 1
+PE13:
+  FMC_D10: 12
+  FMC_DA10: 12
+  LTDC_DE: 14
+  SPI4_MISO: 5
+  TIM1_CH3: 1
+PE14:
+  FMC_D11: 12
+  FMC_DA11: 12
+  LTDC_CLK: 14
+  SPI4_MOSI: 5
+  TIM1_CH4: 1
+PE15:
+  FMC_D12: 12
+  FMC_DA12: 12
+  LTDC_R7: 14
+  TIM1_BKIN: 1
+PE2:
+  ETH_TXD3: 11
+  FMC_A23: 12
+  SAI1_MCLK_A: 6
+  SPI4_SCK: 5
+  SYS_TRACECLK: 0
+PE3:
+  FMC_A19: 12
+  SAI1_SD_B: 6
+  SYS_TRACED0: 0
+PE4:
+  DCMI_D4: 13
+  FMC_A20: 12
+  LTDC_B0: 14
+  SAI1_FS_A: 6
+  SPI4_NSS: 5
+  SYS_TRACED1: 0
+PE5:
+  DCMI_D6: 13
+  FMC_A21: 12
+  LTDC_G0: 14
+  SAI1_SCK_A: 6
+  SPI4_MISO: 5
+  SYS_TRACED2: 0
+  TIM9_CH1: 3
+PE6:
+  DCMI_D7: 13
+  FMC_A22: 12
+  LTDC_G1: 14
+  SAI1_SD_A: 6
+  SPI4_MOSI: 5
+  SYS_TRACED3: 0
+  TIM9_CH2: 3
+PE7:
+  FMC_D4: 12
+  FMC_DA4: 12
+  TIM1_ETR: 1
+  UART7_RX: 8
+PE8:
+  FMC_D5: 12
+  FMC_DA5: 12
+  TIM1_CH1N: 1
+  UART7_TX: 8
+PE9:
+  FMC_D6: 12
+  FMC_DA6: 12
+  TIM1_CH1: 1
+PF0:
+  FMC_A0: 12
+  I2C2_SDA: 4
+PF1:
+  FMC_A1: 12
+  I2C2_SCL: 4
+PF10:
+  DCMI_D11: 13
+  FMC_INTR: 12
+  LTDC_DE: 14
+PF11:
+  DCMI_D12: 13
+  FMC_SDNRAS: 12
+  SPI5_MOSI: 5
+PF12:
+  FMC_A6: 12
+PF13:
+  FMC_A7: 12
+PF14:
+  FMC_A8: 12
+PF15:
+  FMC_A9: 12
+PF2:
+  FMC_A2: 12
+  I2C2_SMBA: 4
+PF3:
+  FMC_A3: 12
+PF4:
+  FMC_A4: 12
+PF5:
+  FMC_A5: 12
+PF6:
+  FMC_NIORD: 12
+  SAI1_SD_B: 6
+  SPI5_NSS: 5
+  TIM10_CH1: 3
+  UART7_RX: 8
+PF7:
+  FMC_NREG: 12
+  SAI1_MCLK_B: 6
+  SPI5_SCK: 5
+  TIM11_CH1: 3
+  UART7_TX: 8
+PF8:
+  FMC_NIOWR: 12
+  SAI1_SCK_B: 6
+  SPI5_MISO: 5
+  TIM13_CH1: 9
+PF9:
+  FMC_CD: 12
+  SAI1_FS_B: 6
+  SPI5_MOSI: 5
+  TIM14_CH1: 9
+PG0:
+  FMC_A10: 12
+PG1:
+  FMC_A11: 12
+PG10:
+  DCMI_D2: 13
+  FMC_NCE4_1: 12
+  FMC_NE3: 12
+  LTDC_B2: 14
+  LTDC_G3: 9
+PG11:
+  DCMI_D3: 13
+  ETH_TX_EN: 11
+  FMC_NCE4_2: 12
+  LTDC_B3: 14
+PG12:
+  FMC_NE4: 12
+  LTDC_B1: 14
+  LTDC_B4: 9
+  SPI6_MISO: 5
+  USART6_RTS: 8
+PG13:
+  ETH_TXD0: 11
+  FMC_A24: 12
+  SPI6_SCK: 5
+  USART6_CTS: 8
+PG14:
+  ETH_TXD1: 11
+  FMC_A25: 12
+  SPI6_MOSI: 5
+  USART6_TX: 8
+PG15:
+  DCMI_D13: 13
+  FMC_SDNCAS: 12
+  USART6_CTS: 8
+PG2:
+  FMC_A12: 12
+PG3:
+  FMC_A13: 12
+PG4:
+  FMC_A14: 12
+  FMC_BA0: 12
+PG5:
+  FMC_A15: 12
+  FMC_BA1: 12
+PG6:
+  DCMI_D12: 13
+  FMC_INT2: 12
+  LTDC_R7: 14
+PG7:
+  DCMI_D13: 13
+  FMC_INT3: 12
+  LTDC_CLK: 14
+  USART6_CK: 8
+PG8:
+  ETH_PPS_OUT: 11
+  FMC_SDCLK: 12
+  SPI6_NSS: 5
+  USART6_RTS: 8
+PG9:
+  DCMI_VSYNC: 13
+  FMC_NCE3: 12
+  FMC_NE2: 12
+  USART6_RX: 8
+PH0: {}
+PH1: {}
+PH10:
+  DCMI_D1: 13
+  FMC_D18: 12
+  LTDC_R4: 14
+  TIM5_CH1: 2
+PH11:
+  DCMI_D2: 13
+  FMC_D19: 12
+  LTDC_R5: 14
+  TIM5_CH2: 2
+PH12:
+  DCMI_D3: 13
+  FMC_D20: 12
+  LTDC_R6: 14
+  TIM5_CH3: 2
+PH13:
+  CAN1_TX: 9
+  FMC_D21: 12
+  LTDC_G2: 14
+  TIM8_CH1N: 3
+PH14:
+  DCMI_D4: 13
+  FMC_D22: 12
+  LTDC_G3: 14
+  TIM8_CH2N: 3
+PH15:
+  DCMI_D11: 13
+  FMC_D23: 12
+  LTDC_G4: 14
+  TIM8_CH3N: 3
+PH2:
+  ETH_CRS: 11
+  FMC_SDCKE0: 12
+  LTDC_R0: 14
+PH3:
+  ETH_COL: 11
+  FMC_SDNE0: 12
+  LTDC_R1: 14
+PH4:
+  I2C2_SCL: 4
+  USB_OTG_HS_ULPI_NXT: 10
+PH5:
+  FMC_SDNWE: 12
+  I2C2_SDA: 4
+  SPI5_NSS: 5
+PH6:
+  DCMI_D8: 13
+  ETH_RXD2: 11
+  FMC_SDNE1: 12
+  I2C2_SMBA: 4
+  SPI5_SCK: 5
+  TIM12_CH1: 9
+PH7:
+  DCMI_D9: 13
+  ETH_RXD3: 11
+  FMC_SDCKE1: 12
+  I2C3_SCL: 4
+  SPI5_MISO: 5
+PH8:
+  DCMI_HSYNC: 13
+  FMC_D16: 12
+  I2C3_SDA: 4
+  LTDC_R2: 14
+PH9:
+  DCMI_D0: 13
+  FMC_D17: 12
+  I2C3_SMBA: 4
+  LTDC_R3: 14
+  TIM12_CH2: 9
+PI0:
+  DCMI_D13: 13
+  FMC_D24: 12
+  I2S2_WS: 5
+  LTDC_G5: 14
+  SPI2_NSS: 5
+  TIM5_CH4: 2
+PI1:
+  DCMI_D8: 13
+  FMC_D25: 12
+  I2S2_CK: 5
+  LTDC_G6: 14
+  SPI2_SCK: 5
+PI10:
+  ETH_RX_ER: 11
+  FMC_D31: 12
+  LTDC_HSYNC: 14
+PI11:
+  USB_OTG_HS_ULPI_DIR: 10
+PI12:
+  LTDC_HSYNC: 14
+PI13:
+  LTDC_VSYNC: 14
+PI14:
+  LTDC_CLK: 14
+PI15:
+  LTDC_R0: 14
+PI2:
+  DCMI_D9: 13
+  FMC_D26: 12
+  I2S2_ext_SD: 6
+  LTDC_G7: 14
+  SPI2_MISO: 5
+  TIM8_CH4: 3
+PI3:
+  DCMI_D10: 13
+  FMC_D27: 12
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIM8_ETR: 3
+PI4:
+  DCMI_D5: 13
+  FMC_NBL2: 12
+  LTDC_B4: 14
+  TIM8_BKIN: 3
+PI5:
+  DCMI_VSYNC: 13
+  FMC_NBL3: 12
+  LTDC_B5: 14
+  TIM8_CH1: 3
+PI6:
+  DCMI_D6: 13
+  FMC_D28: 12
+  LTDC_B6: 14
+  TIM8_CH2: 3
+PI7:
+  DCMI_D7: 13
+  FMC_D29: 12
+  LTDC_B7: 14
+  TIM8_CH3: 3
+PI8: {}
+PI9:
+  CAN1_RX: 9
+  FMC_D30: 12
+  LTDC_VSYNC: 14
+PJ0:
+  LTDC_R1: 14
+PJ1:
+  LTDC_R2: 14
+PJ10:
+  LTDC_G3: 14
+PJ11:
+  LTDC_G4: 14
+PJ12:
+  LTDC_B0: 14
+PJ13:
+  LTDC_B1: 14
+PJ14:
+  LTDC_B2: 14
+PJ15:
+  LTDC_B3: 14
+PJ2:
+  LTDC_R3: 14
+PJ3:
+  LTDC_R4: 14
+PJ4:
+  LTDC_R5: 14
+PJ5:
+  LTDC_R6: 14
+PJ6:
+  LTDC_R7: 14
+PJ7:
+  LTDC_G0: 14
+PJ8:
+  LTDC_G1: 14
+PJ9:
+  LTDC_G2: 14
+PK0:
+  LTDC_G5: 14
+PK1:
+  LTDC_G6: 14
+PK2:
+  LTDC_G7: 14
+PK3:
+  LTDC_B4: 14
+PK4:
+  LTDC_B5: 14
+PK5:
+  LTDC_B6: 14
+PK6:
+  LTDC_B7: 14
+PK7:
+  LTDC_DE: 14

data/gpio_af/STM32F446.yaml

@@ -0,0 +1,610 @@
+PA0:
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM5_CH1: 2
+  TIM8_ETR: 3
+  UART4_TX: 8
+  USART2_CTS: 7
+PA1:
+  QUADSPI_BK1_IO3: 9
+  SAI2_MCLK_B: 10
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  UART4_RX: 8
+  USART2_RTS: 7
+PA10:
+  DCMI_D1: 13
+  TIM1_CH3: 1
+  USART1_RX: 7
+  USB_OTG_FS_ID: 10
+PA11:
+  CAN1_RX: 9
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USB_OTG_FS_DM: 10
+PA12:
+  CAN1_TX: 9
+  SAI2_FS_B: 8
+  TIM1_ETR: 1
+  USART1_RTS: 7
+  USB_OTG_FS_DP: 10
+PA13:
+  SYS_JTMS-SWDIO: 0
+PA14:
+  SYS_JTCK-SWCLK: 0
+PA15:
+  CEC: 4
+  I2S1_WS: 5
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  UART4_RTS: 8
+PA2:
+  SAI2_SCK_B: 8
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  TIM9_CH1: 3
+  USART2_TX: 7
+PA3:
+  SAI1_FS_A: 6
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  TIM9_CH2: 3
+  USART2_RX: 7
+  USB_OTG_HS_ULPI_D0: 10
+PA4:
+  DCMI_HSYNC: 13
+  I2S1_WS: 5
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  USART2_CK: 7
+  USB_OTG_HS_SOF: 12
+PA5:
+  I2S1_CK: 5
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM8_CH1N: 3
+  USB_OTG_HS_ULPI_CK: 10
+PA6:
+  DCMI_PIXCLK: 13
+  I2S2_MCK: 6
+  SPI1_MISO: 5
+  TIM13_CH1: 9
+  TIM1_BKIN: 1
+  TIM3_CH1: 2
+  TIM8_BKIN: 3
+PA7:
+  FMC_SDNWE: 12
+  I2S1_SD: 5
+  SPI1_MOSI: 5
+  TIM14_CH1: 9
+  TIM1_CH1N: 1
+  TIM3_CH2: 2
+  TIM8_CH1N: 3
+PA8:
+  I2C3_SCL: 4
+  RCC_MCO_1: 0
+  TIM1_CH1: 1
+  USART1_CK: 7
+  USB_OTG_FS_SOF: 10
+PA9:
+  DCMI_D0: 13
+  I2C3_SMBA: 4
+  I2S2_CK: 5
+  SAI1_SD_B: 6
+  SPI2_SCK: 5
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  I2S3_SD: 7
+  SDIO_D1: 12
+  SPI3_MOSI: 7
+  TIM1_CH2N: 1
+  TIM3_CH3: 2
+  TIM8_CH2N: 3
+  UART4_CTS: 8
+  USB_OTG_HS_ULPI_D1: 10
+PB1:
+  SDIO_D2: 12
+  TIM1_CH3N: 1
+  TIM3_CH4: 2
+  TIM8_CH3N: 3
+  USB_OTG_HS_ULPI_D2: 10
+PB10:
+  I2C2_SCL: 4
+  I2S2_CK: 5
+  SAI1_SCK_A: 6
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+  USART3_TX: 7
+  USB_OTG_HS_ULPI_D3: 10
+PB11:
+  I2C2_SDA: 4
+  SAI2_SD_A: 8
+  TIM2_CH4: 1
+  USART3_RX: 7
+  USB_OTG_HS_ULPI_D4: 10
+PB12:
+  CAN2_RX: 9
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  SAI1_SCK_B: 6
+  SPI2_NSS: 5
+  TIM1_BKIN: 1
+  USART3_CK: 7
+  USB_OTG_HS_ID: 12
+  USB_OTG_HS_ULPI_D5: 10
+PB13:
+  CAN2_TX: 9
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM1_CH1N: 1
+  USART3_CTS: 7
+  USB_OTG_HS_ULPI_D6: 10
+PB14:
+  SPI2_MISO: 5
+  TIM12_CH1: 9
+  TIM1_CH2N: 1
+  TIM8_CH2N: 3
+  USART3_RTS: 7
+  USB_OTG_HS_DM: 12
+PB15:
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM12_CH2: 9
+  TIM1_CH3N: 1
+  TIM8_CH3N: 3
+  USB_OTG_HS_DP: 12
+PB2:
+  I2S3_SD: 7
+  QUADSPI_CLK: 9
+  SAI1_SD_A: 6
+  SDIO_CK: 12
+  SPI3_MOSI: 7
+  TIM2_CH4: 1
+  USB_OTG_HS_ULPI_D4: 10
+PB3:
+  I2C2_SDA: 4
+  I2S1_CK: 5
+  I2S3_CK: 6
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+PB4:
+  I2C3_SDA: 4
+  I2S2_WS: 7
+  SPI1_MISO: 5
+  SPI2_NSS: 7
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM3_CH1: 2
+PB5:
+  CAN2_RX: 9
+  DCMI_D10: 13
+  FMC_SDCKE1: 12
+  I2C1_SMBA: 4
+  I2S1_SD: 5
+  I2S3_SD: 6
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM3_CH2: 2
+  USB_OTG_HS_ULPI_D7: 10
+PB6:
+  CAN2_TX: 9
+  CEC: 3
+  DCMI_D5: 13
+  FMC_SDNE1: 12
+  I2C1_SCL: 4
+  QUADSPI_BK1_NCS: 10
+  TIM4_CH1: 2
+  USART1_TX: 7
+PB7:
+  DCMI_VSYNC: 13
+  FMC_NL: 12
+  I2C1_SDA: 4
+  SPDIFRX_IN0: 8
+  TIM4_CH2: 2
+  USART1_RX: 7
+PB8:
+  CAN1_RX: 9
+  DCMI_D6: 13
+  I2C1_SCL: 4
+  SDIO_D4: 12
+  TIM10_CH1: 3
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM4_CH3: 2
+PB9:
+  CAN1_TX: 9
+  DCMI_D7: 13
+  I2C1_SDA: 4
+  I2S2_WS: 5
+  SAI1_FS_B: 6
+  SDIO_D5: 12
+  SPI2_NSS: 5
+  TIM11_CH1: 3
+  TIM2_CH2: 1
+  TIM4_CH4: 2
+PC0:
+  FMC_SDNWE: 12
+  SAI1_MCLK_B: 6
+  USB_OTG_HS_ULPI_STP: 10
+PC1:
+  I2S2_SD: 7
+  I2S3_SD: 5
+  SAI1_SD_A: 6
+  SPI2_MOSI: 7
+  SPI3_MOSI: 5
+PC10:
+  DCMI_D8: 13
+  I2S3_CK: 6
+  QUADSPI_BK1_IO1: 9
+  SDIO_D2: 12
+  SPI3_SCK: 6
+  UART4_TX: 8
+  USART3_TX: 7
+PC11:
+  DCMI_D4: 13
+  QUADSPI_BK2_NCS: 9
+  SDIO_D3: 12
+  SPI3_MISO: 6
+  UART4_RX: 8
+  USART3_RX: 7
+PC12:
+  DCMI_D9: 13
+  I2C2_SDA: 4
+  I2S3_SD: 6
+  SDIO_CK: 12
+  SPI3_MOSI: 6
+  UART5_TX: 8
+  USART3_CK: 7
+PC13: {}
+PC14: {}
+PC15: {}
+PC2:
+  FMC_SDNE0: 12
+  SPI2_MISO: 5
+  USB_OTG_HS_ULPI_DIR: 10
+PC3:
+  FMC_SDCKE0: 12
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  USB_OTG_HS_ULPI_NXT: 10
+PC4:
+  FMC_SDNE0: 12
+  I2S1_MCK: 5
+  SPDIFRX_IN2: 8
+PC5:
+  FMC_SDCKE0: 12
+  SPDIFRX_IN3: 8
+  USART3_RX: 7
+PC6:
+  DCMI_D0: 13
+  FMPI2C1_SCL: 4
+  I2S2_MCK: 5
+  SDIO_D6: 12
+  TIM3_CH1: 2
+  TIM8_CH1: 3
+  USART6_TX: 8
+PC7:
+  DCMI_D1: 13
+  FMPI2C1_SDA: 4
+  I2S2_CK: 5
+  I2S3_MCK: 6
+  SDIO_D7: 12
+  SPDIFRX_IN1: 7
+  SPI2_SCK: 5
+  TIM3_CH2: 2
+  TIM8_CH2: 3
+  USART6_RX: 8
+PC8:
+  DCMI_D2: 13
+  SDIO_D0: 12
+  SYS_TRACED0: 0
+  TIM3_CH3: 2
+  TIM8_CH3: 3
+  UART5_RTS: 7
+  USART6_CK: 8
+PC9:
+  DCMI_D3: 13
+  I2C3_SDA: 4
+  I2S_CKIN: 5
+  QUADSPI_BK1_IO0: 9
+  RCC_MCO_2: 0
+  SDIO_D1: 12
+  TIM3_CH4: 2
+  TIM8_CH4: 3
+  UART5_CTS: 7
+PD0:
+  CAN1_RX: 9
+  FMC_D2: 12
+  FMC_DA2: 12
+  I2S3_SD: 6
+  SPI3_MOSI: 6
+  SPI4_MISO: 5
+PD1:
+  CAN1_TX: 9
+  FMC_D3: 12
+  FMC_DA3: 12
+  I2S2_WS: 7
+  SPI2_NSS: 7
+PD10:
+  FMC_D15: 12
+  FMC_DA15: 12
+  USART3_CK: 7
+PD11:
+  FMC_A16: 12
+  FMPI2C1_SMBA: 4
+  QUADSPI_BK1_IO0: 9
+  SAI2_SD_A: 10
+  USART3_CTS: 7
+PD12:
+  FMC_A17: 12
+  FMPI2C1_SCL: 4
+  QUADSPI_BK1_IO1: 9
+  SAI2_FS_A: 10
+  TIM4_CH1: 2
+  USART3_RTS: 7
+PD13:
+  FMC_A18: 12
+  FMPI2C1_SDA: 4
+  QUADSPI_BK1_IO3: 9
+  SAI2_SCK_A: 10
+  TIM4_CH2: 2
+PD14:
+  FMC_D0: 12
+  FMC_DA0: 12
+  FMPI2C1_SCL: 4
+  SAI2_SCK_A: 8
+  TIM4_CH3: 2
+PD15:
+  FMC_D1: 12
+  FMC_DA1: 12
+  FMPI2C1_SDA: 4
+  TIM4_CH4: 2
+PD2:
+  DCMI_D11: 13
+  SDIO_CMD: 12
+  TIM3_ETR: 2
+  UART5_RX: 8
+PD3:
+  DCMI_D5: 13
+  FMC_CLK: 12
+  I2S2_CK: 5
+  QUADSPI_CLK: 9
+  SPI2_SCK: 5
+  SYS_TRACED1: 0
+  USART2_CTS: 7
+PD4:
+  FMC_NOE: 12
+  USART2_RTS: 7
+PD5:
+  FMC_NWE: 12
+  USART2_TX: 7
+PD6:
+  DCMI_D10: 13
+  FMC_NWAIT: 12
+  I2S3_SD: 5
+  SAI1_SD_A: 6
+  SPI3_MOSI: 5
+  USART2_RX: 7
+PD7:
+  FMC_NE1: 12
+  SPDIFRX_IN0: 8
+  USART2_CK: 7
+PD8:
+  FMC_D13: 12
+  FMC_DA13: 12
+  SPDIFRX_IN1: 8
+  USART3_TX: 7
+PD9:
+  FMC_D14: 12
+  FMC_DA14: 12
+  USART3_RX: 7
+PE0:
+  DCMI_D2: 13
+  FMC_NBL0: 12
+  SAI2_MCLK_A: 10
+  TIM4_ETR: 2
+PE1:
+  DCMI_D3: 13
+  FMC_NBL1: 12
+PE10:
+  FMC_D7: 12
+  FMC_DA7: 12
+  QUADSPI_BK2_IO3: 10
+  TIM1_CH2N: 1
+PE11:
+  FMC_D8: 12
+  FMC_DA8: 12
+  SAI2_SD_B: 10
+  SPI4_NSS: 5
+  TIM1_CH2: 1
+PE12:
+  FMC_D9: 12
+  FMC_DA9: 12
+  SAI2_SCK_B: 10
+  SPI4_SCK: 5
+  TIM1_CH3N: 1
+PE13:
+  FMC_D10: 12
+  FMC_DA10: 12
+  SAI2_FS_B: 10
+  SPI4_MISO: 5
+  TIM1_CH3: 1
+PE14:
+  FMC_D11: 12
+  FMC_DA11: 12
+  SAI2_MCLK_B: 10
+  SPI4_MOSI: 5
+  TIM1_CH4: 1
+PE15:
+  FMC_D12: 12
+  FMC_DA12: 12
+  TIM1_BKIN: 1
+PE2:
+  FMC_A23: 12
+  QUADSPI_BK1_IO2: 9
+  SAI1_MCLK_A: 6
+  SPI4_SCK: 5
+  SYS_TRACECLK: 0
+PE3:
+  FMC_A19: 12
+  SAI1_SD_B: 6
+  SYS_TRACED0: 0
+PE4:
+  DCMI_D4: 13
+  FMC_A20: 12
+  SAI1_FS_A: 6
+  SPI4_NSS: 5
+  SYS_TRACED1: 0
+PE5:
+  DCMI_D6: 13
+  FMC_A21: 12
+  SAI1_SCK_A: 6
+  SPI4_MISO: 5
+  SYS_TRACED2: 0
+  TIM9_CH1: 3
+PE6:
+  DCMI_D7: 13
+  FMC_A22: 12
+  SAI1_SD_A: 6
+  SPI4_MOSI: 5
+  SYS_TRACED3: 0
+  TIM9_CH2: 3
+PE7:
+  FMC_D4: 12
+  FMC_DA4: 12
+  QUADSPI_BK2_IO0: 10
+  TIM1_ETR: 1
+  UART5_RX: 8
+PE8:
+  FMC_D5: 12
+  FMC_DA5: 12
+  QUADSPI_BK2_IO1: 10
+  TIM1_CH1N: 1
+  UART5_TX: 8
+PE9:
+  FMC_D6: 12
+  FMC_DA6: 12
+  QUADSPI_BK2_IO2: 10
+  TIM1_CH1: 1
+PF0:
+  FMC_A0: 12
+  I2C2_SDA: 4
+PF1:
+  FMC_A1: 12
+  I2C2_SCL: 4
+PF10:
+  DCMI_D11: 13
+PF11:
+  DCMI_D12: 13
+  FMC_SDNRAS: 12
+  SAI2_SD_B: 10
+PF12:
+  FMC_A6: 12
+PF13:
+  FMC_A7: 12
+  FMPI2C1_SMBA: 4
+PF14:
+  FMC_A8: 12
+  FMPI2C1_SCL: 4
+PF15:
+  FMC_A9: 12
+  FMPI2C1_SDA: 4
+PF2:
+  FMC_A2: 12
+  I2C2_SMBA: 4
+PF3:
+  FMC_A3: 12
+PF4:
+  FMC_A4: 12
+PF5:
+  FMC_A5: 12
+PF6:
+  QUADSPI_BK1_IO3: 9
+  SAI1_SD_B: 6
+  TIM10_CH1: 3
+PF7:
+  QUADSPI_BK1_IO2: 9
+  SAI1_MCLK_B: 6
+  TIM11_CH1: 3
+PF8:
+  QUADSPI_BK1_IO0: 10
+  SAI1_SCK_B: 6
+  TIM13_CH1: 9
+PF9:
+  QUADSPI_BK1_IO1: 10
+  SAI1_FS_B: 6
+  TIM14_CH1: 9
+PG0:
+  FMC_A10: 12
+PG1:
+  FMC_A11: 12
+PG10:
+  DCMI_D2: 13
+  FMC_NE3: 12
+  SAI2_SD_B: 10
+PG11:
+  DCMI_D3: 13
+  SPDIFRX_IN0: 7
+  SPI4_SCK: 6
+PG12:
+  FMC_NE4: 12
+  SPDIFRX_IN1: 7
+  SPI4_MISO: 6
+  USART6_RTS: 8
+PG13:
+  FMC_A24: 12
+  SPI4_MOSI: 6
+  SYS_TRACED2: 0
+  USART6_CTS: 8
+PG14:
+  FMC_A25: 12
+  QUADSPI_BK2_IO3: 9
+  SPI4_NSS: 6
+  SYS_TRACED3: 0
+  USART6_TX: 8
+PG15:
+  DCMI_D13: 13
+  FMC_SDNCAS: 12
+  USART6_CTS: 8
+PG2:
+  FMC_A12: 12
+PG3:
+  FMC_A13: 12
+PG4:
+  FMC_A14: 12
+  FMC_BA0: 12
+PG5:
+  FMC_A15: 12
+  FMC_BA1: 12
+PG6:
+  DCMI_D12: 13
+  QUADSPI_BK1_NCS: 10
+PG7:
+  DCMI_D13: 13
+  FMC_INT3: 12
+  USART6_CK: 8
+PG8:
+  FMC_SDCLK: 12
+  SPDIFRX_IN2: 7
+  USART6_RTS: 8
+PG9:
+  DCMI_VSYNC: 13
+  FMC_NCE3: 12
+  FMC_NE2: 12
+  QUADSPI_BK2_IO2: 9
+  SAI2_FS_B: 10
+  SPDIFRX_IN3: 7
+  USART6_RX: 8
+PH0: {}
+PH1: {}
+PI8: {}

data/gpio_af/STM32F469.yaml

@@ -0,0 +1,788 @@
+PA0:
+  ETH_CRS: 11
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM5_CH1: 2
+  TIM8_ETR: 3
+  UART4_TX: 8
+  USART2_CTS: 7
+PA1:
+  ETH_REF_CLK: 11
+  ETH_RX_CLK: 11
+  LTDC_R2: 14
+  QUADSPI_BK1_IO3: 9
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  UART4_RX: 8
+  USART2_RTS: 7
+PA10:
+  DCMI_D1: 13
+  TIM1_CH3: 1
+  USART1_RX: 7
+  USB_OTG_FS_ID: 10
+PA11:
+  CAN1_RX: 9
+  LTDC_R4: 14
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USB_OTG_FS_DM: 10
+PA12:
+  CAN1_TX: 9
+  LTDC_R5: 14
+  TIM1_ETR: 1
+  USART1_RTS: 7
+  USB_OTG_FS_DP: 10
+PA13:
+  SYS_JTMS-SWDIO: 0
+PA14:
+  SYS_JTCK-SWCLK: 0
+PA15:
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+PA2:
+  ETH_MDIO: 11
+  LTDC_R1: 14
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  TIM9_CH1: 3
+  USART2_TX: 7
+PA3:
+  ETH_COL: 11
+  LTDC_B2: 9
+  LTDC_B5: 14
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  TIM9_CH2: 3
+  USART2_RX: 7
+  USB_OTG_HS_ULPI_D0: 10
+PA4:
+  DCMI_HSYNC: 13
+  I2S3_WS: 6
+  LTDC_VSYNC: 14
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  USART2_CK: 7
+  USB_OTG_HS_SOF: 12
+PA5:
+  LTDC_R4: 14
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM8_CH1N: 3
+  USB_OTG_HS_ULPI_CK: 10
+PA6:
+  DCMI_PIXCLK: 13
+  LTDC_G2: 14
+  SPI1_MISO: 5
+  TIM13_CH1: 9
+  TIM1_BKIN: 1
+  TIM3_CH1: 2
+  TIM8_BKIN: 3
+PA7:
+  ETH_CRS_DV: 11
+  ETH_RX_DV: 11
+  FMC_SDNWE: 12
+  QUADSPI_CLK: 10
+  SPI1_MOSI: 5
+  TIM14_CH1: 9
+  TIM1_CH1N: 1
+  TIM3_CH2: 2
+  TIM8_CH1N: 3
+PA8:
+  I2C3_SCL: 4
+  LTDC_R6: 14
+  RCC_MCO_1: 0
+  TIM1_CH1: 1
+  USART1_CK: 7
+  USB_OTG_FS_SOF: 10
+PA9:
+  DCMI_D0: 13
+  I2C3_SMBA: 4
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  ETH_RXD2: 11
+  LTDC_G1: 14
+  LTDC_R3: 9
+  TIM1_CH2N: 1
+  TIM3_CH3: 2
+  TIM8_CH2N: 3
+  USB_OTG_HS_ULPI_D1: 10
+PB1:
+  ETH_RXD3: 11
+  LTDC_G0: 14
+  LTDC_R6: 9
+  TIM1_CH3N: 1
+  TIM3_CH4: 2
+  TIM8_CH3N: 3
+  USB_OTG_HS_ULPI_D2: 10
+PB10:
+  ETH_RX_ER: 11
+  I2C2_SCL: 4
+  I2S2_CK: 5
+  LTDC_G4: 14
+  QUADSPI_BK1_NCS: 9
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+  USART3_TX: 7
+  USB_OTG_HS_ULPI_D3: 10
+PB11:
+  DSIHOST_TE: 13
+  ETH_TX_EN: 11
+  I2C2_SDA: 4
+  LTDC_G5: 14
+  TIM2_CH4: 1
+  USART3_RX: 7
+  USB_OTG_HS_ULPI_D4: 10
+PB12:
+  CAN2_RX: 9
+  ETH_TXD0: 11
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM1_BKIN: 1
+  USART3_CK: 7
+  USB_OTG_HS_ID: 12
+  USB_OTG_HS_ULPI_D5: 10
+PB13:
+  CAN2_TX: 9
+  ETH_TXD1: 11
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM1_CH1N: 1
+  USART3_CTS: 7
+  USB_OTG_HS_ULPI_D6: 10
+PB14:
+  I2S2_ext_SD: 6
+  SPI2_MISO: 5
+  TIM12_CH1: 9
+  TIM1_CH2N: 1
+  TIM8_CH2N: 3
+  USART3_RTS: 7
+  USB_OTG_HS_DM: 12
+PB15:
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM12_CH2: 9
+  TIM1_CH3N: 1
+  TIM8_CH3N: 3
+  USB_OTG_HS_DP: 12
+PB2: {}
+PB3:
+  I2S3_CK: 6
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+PB4:
+  I2S3_ext_SD: 7
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM3_CH1: 2
+PB5:
+  CAN2_RX: 9
+  DCMI_D10: 13
+  ETH_PPS_OUT: 11
+  FMC_SDCKE1: 12
+  I2C1_SMBA: 4
+  I2S3_SD: 6
+  LTDC_G7: 14
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM3_CH2: 2
+  USB_OTG_HS_ULPI_D7: 10
+PB6:
+  CAN2_TX: 9
+  DCMI_D5: 13
+  FMC_SDNE1: 12
+  I2C1_SCL: 4
+  QUADSPI_BK1_NCS: 10
+  TIM4_CH1: 2
+  USART1_TX: 7
+PB7:
+  DCMI_VSYNC: 13
+  FMC_NL: 12
+  I2C1_SDA: 4
+  TIM4_CH2: 2
+  USART1_RX: 7
+PB8:
+  CAN1_RX: 9
+  DCMI_D6: 13
+  ETH_TXD3: 11
+  I2C1_SCL: 4
+  LTDC_B6: 14
+  SDIO_D4: 12
+  TIM10_CH1: 3
+  TIM4_CH3: 2
+PB9:
+  CAN1_TX: 9
+  DCMI_D7: 13
+  I2C1_SDA: 4
+  I2S2_WS: 5
+  LTDC_B7: 14
+  SDIO_D5: 12
+  SPI2_NSS: 5
+  TIM11_CH1: 3
+  TIM4_CH4: 2
+PC0:
+  FMC_SDNWE: 12
+  LTDC_R5: 14
+  USB_OTG_HS_ULPI_STP: 10
+PC1:
+  ETH_MDC: 11
+  I2S2_SD: 5
+  SAI1_SD_A: 6
+  SPI2_MOSI: 5
+  SYS_TRACED0: 0
+PC10:
+  DCMI_D8: 13
+  I2S3_CK: 6
+  LTDC_R2: 14
+  QUADSPI_BK1_IO1: 9
+  SDIO_D2: 12
+  SPI3_SCK: 6
+  UART4_TX: 8
+  USART3_TX: 7
+PC11:
+  DCMI_D4: 13
+  I2S3_ext_SD: 5
+  QUADSPI_BK2_NCS: 9
+  SDIO_D3: 12
+  SPI3_MISO: 6
+  UART4_RX: 8
+  USART3_RX: 7
+PC12:
+  DCMI_D9: 13
+  I2S3_SD: 6
+  SDIO_CK: 12
+  SPI3_MOSI: 6
+  SYS_TRACED3: 0
+  UART5_TX: 8
+  USART3_CK: 7
+PC13: {}
+PC14: {}
+PC15: {}
+PC2:
+  ETH_TXD2: 11
+  FMC_SDNE0: 12
+  I2S2_ext_SD: 6
+  SPI2_MISO: 5
+  USB_OTG_HS_ULPI_DIR: 10
+PC3:
+  ETH_TX_CLK: 11
+  FMC_SDCKE0: 12
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  USB_OTG_HS_ULPI_NXT: 10
+PC4:
+  ETH_RXD0: 11
+  FMC_SDNE0: 12
+PC5:
+  ETH_RXD1: 11
+  FMC_SDCKE0: 12
+PC6:
+  DCMI_D0: 13
+  I2S2_MCK: 5
+  LTDC_HSYNC: 14
+  SDIO_D6: 12
+  TIM3_CH1: 2
+  TIM8_CH1: 3
+  USART6_TX: 8
+PC7:
+  DCMI_D1: 13
+  I2S3_MCK: 6
+  LTDC_G6: 14
+  SDIO_D7: 12
+  TIM3_CH2: 2
+  TIM8_CH2: 3
+  USART6_RX: 8
+PC8:
+  DCMI_D2: 13
+  SDIO_D0: 12
+  SYS_TRACED1: 0
+  TIM3_CH3: 2
+  TIM8_CH3: 3
+  USART6_CK: 8
+PC9:
+  DCMI_D3: 13
+  I2C3_SDA: 4
+  I2S_CKIN: 5
+  QUADSPI_BK1_IO0: 9
+  RCC_MCO_2: 0
+  SDIO_D1: 12
+  TIM3_CH4: 2
+  TIM8_CH4: 3
+PD0:
+  CAN1_RX: 9
+  FMC_D2: 12
+  FMC_DA2: 12
+PD1:
+  CAN1_TX: 9
+  FMC_D3: 12
+  FMC_DA3: 12
+PD10:
+  FMC_D15: 12
+  FMC_DA15: 12
+  LTDC_B3: 14
+  USART3_CK: 7
+PD11:
+  FMC_A16: 12
+  FMC_CLE: 12
+  QUADSPI_BK1_IO0: 9
+  USART3_CTS: 7
+PD12:
+  FMC_A17: 12
+  FMC_ALE: 12
+  QUADSPI_BK1_IO1: 9
+  TIM4_CH1: 2
+  USART3_RTS: 7
+PD13:
+  FMC_A18: 12
+  QUADSPI_BK1_IO3: 9
+  TIM4_CH2: 2
+PD14:
+  FMC_D0: 12
+  FMC_DA0: 12
+  TIM4_CH3: 2
+PD15:
+  FMC_D1: 12
+  FMC_DA1: 12
+  TIM4_CH4: 2
+PD2:
+  DCMI_D11: 13
+  SDIO_CMD: 12
+  SYS_TRACED2: 0
+  TIM3_ETR: 2
+  UART5_RX: 8
+PD3:
+  DCMI_D5: 13
+  FMC_CLK: 12
+  I2S2_CK: 5
+  LTDC_G7: 14
+  SPI2_SCK: 5
+  USART2_CTS: 7
+PD4:
+  FMC_NOE: 12
+  USART2_RTS: 7
+PD5:
+  FMC_NWE: 12
+  USART2_TX: 7
+PD6:
+  DCMI_D10: 13
+  FMC_NWAIT: 12
+  I2S3_SD: 5
+  LTDC_B2: 14
+  SAI1_SD_A: 6
+  SPI3_MOSI: 5
+  USART2_RX: 7
+PD7:
+  FMC_NE1: 12
+  USART2_CK: 7
+PD8:
+  FMC_D13: 12
+  FMC_DA13: 12
+  USART3_TX: 7
+PD9:
+  FMC_D14: 12
+  FMC_DA14: 12
+  USART3_RX: 7
+PE0:
+  DCMI_D2: 13
+  FMC_NBL0: 12
+  TIM4_ETR: 2
+  UART8_RX: 8
+PE1:
+  DCMI_D3: 13
+  FMC_NBL1: 12
+  UART8_TX: 8
+PE10:
+  FMC_D7: 12
+  FMC_DA7: 12
+  QUADSPI_BK2_IO3: 10
+  TIM1_CH2N: 1
+PE11:
+  FMC_D8: 12
+  FMC_DA8: 12
+  LTDC_G3: 14
+  SPI4_NSS: 5
+  TIM1_CH2: 1
+PE12:
+  FMC_D9: 12
+  FMC_DA9: 12
+  LTDC_B4: 14
+  SPI4_SCK: 5
+  TIM1_CH3N: 1
+PE13:
+  FMC_D10: 12
+  FMC_DA10: 12
+  LTDC_DE: 14
+  SPI4_MISO: 5
+  TIM1_CH3: 1
+PE14:
+  FMC_D11: 12
+  FMC_DA11: 12
+  LTDC_CLK: 14
+  SPI4_MOSI: 5
+  TIM1_CH4: 1
+PE15:
+  FMC_D12: 12
+  FMC_DA12: 12
+  LTDC_R7: 14
+  TIM1_BKIN: 1
+PE2:
+  ETH_TXD3: 11
+  FMC_A23: 12
+  QUADSPI_BK1_IO2: 9
+  SAI1_MCLK_A: 6
+  SPI4_SCK: 5
+  SYS_TRACECLK: 0
+PE3:
+  FMC_A19: 12
+  SAI1_SD_B: 6
+  SYS_TRACED0: 0
+PE4:
+  DCMI_D4: 13
+  FMC_A20: 12
+  LTDC_B0: 14
+  SAI1_FS_A: 6
+  SPI4_NSS: 5
+  SYS_TRACED1: 0
+PE5:
+  DCMI_D6: 13
+  FMC_A21: 12
+  LTDC_G0: 14
+  SAI1_SCK_A: 6
+  SPI4_MISO: 5
+  SYS_TRACED2: 0
+  TIM9_CH1: 3
+PE6:
+  DCMI_D7: 13
+  FMC_A22: 12
+  LTDC_G1: 14
+  SAI1_SD_A: 6
+  SPI4_MOSI: 5
+  SYS_TRACED3: 0
+  TIM9_CH2: 3
+PE7:
+  FMC_D4: 12
+  FMC_DA4: 12
+  QUADSPI_BK2_IO0: 10
+  TIM1_ETR: 1
+  UART7_RX: 8
+PE8:
+  FMC_D5: 12
+  FMC_DA5: 12
+  QUADSPI_BK2_IO1: 10
+  TIM1_CH1N: 1
+  UART7_TX: 8
+PE9:
+  FMC_D6: 12
+  FMC_DA6: 12
+  QUADSPI_BK2_IO2: 10
+  TIM1_CH1: 1
+PF0:
+  FMC_A0: 12
+  I2C2_SDA: 4
+PF1:
+  FMC_A1: 12
+  I2C2_SCL: 4
+PF10:
+  DCMI_D11: 13
+  LTDC_DE: 14
+  QUADSPI_CLK: 9
+PF11:
+  DCMI_D12: 13
+  FMC_SDNRAS: 12
+  SPI5_MOSI: 5
+PF12:
+  FMC_A6: 12
+PF13:
+  FMC_A7: 12
+PF14:
+  FMC_A8: 12
+PF15:
+  FMC_A9: 12
+PF2:
+  FMC_A2: 12
+  I2C2_SMBA: 4
+PF3:
+  FMC_A3: 12
+PF4:
+  FMC_A4: 12
+PF5:
+  FMC_A5: 12
+PF6:
+  QUADSPI_BK1_IO3: 9
+  SAI1_SD_B: 6
+  SPI5_NSS: 5
+  TIM10_CH1: 3
+  UART7_RX: 8
+PF7:
+  QUADSPI_BK1_IO2: 9
+  SAI1_MCLK_B: 6
+  SPI5_SCK: 5
+  TIM11_CH1: 3
+  UART7_TX: 8
+PF8:
+  QUADSPI_BK1_IO0: 10
+  SAI1_SCK_B: 6
+  SPI5_MISO: 5
+  TIM13_CH1: 9
+PF9:
+  QUADSPI_BK1_IO1: 10
+  SAI1_FS_B: 6
+  SPI5_MOSI: 5
+  TIM14_CH1: 9
+PG0:
+  FMC_A10: 12
+PG1:
+  FMC_A11: 12
+PG10:
+  DCMI_D2: 13
+  FMC_NE3: 12
+  LTDC_B2: 14
+  LTDC_G3: 9
+PG11:
+  DCMI_D3: 13
+  ETH_TX_EN: 11
+  LTDC_B3: 14
+PG12:
+  FMC_NE4: 12
+  LTDC_B1: 14
+  LTDC_B4: 9
+  SPI6_MISO: 5
+  USART6_RTS: 8
+PG13:
+  ETH_TXD0: 11
+  FMC_A24: 12
+  LTDC_R0: 14
+  SPI6_SCK: 5
+  SYS_TRACED0: 0
+  USART6_CTS: 8
+PG14:
+  ETH_TXD1: 11
+  FMC_A25: 12
+  LTDC_B0: 14
+  QUADSPI_BK2_IO3: 9
+  SPI6_MOSI: 5
+  SYS_TRACED1: 0
+  USART6_TX: 8
+PG15:
+  DCMI_D13: 13
+  FMC_SDNCAS: 12
+  USART6_CTS: 8
+PG2:
+  FMC_A12: 12
+PG3:
+  FMC_A13: 12
+PG4:
+  FMC_A14: 12
+  FMC_BA0: 12
+PG5:
+  FMC_A15: 12
+  FMC_BA1: 12
+PG6:
+  DCMI_D12: 13
+  LTDC_R7: 14
+PG7:
+  DCMI_D13: 13
+  FMC_INT: 12
+  LTDC_CLK: 14
+  SAI1_MCLK_A: 6
+  USART6_CK: 8
+PG8:
+  ETH_PPS_OUT: 11
+  FMC_SDCLK: 12
+  LTDC_G7: 14
+  SPI6_NSS: 5
+  USART6_RTS: 8
+PG9:
+  DCMI_VSYNC: 13
+  FMC_NCE: 12
+  FMC_NE2: 12
+  QUADSPI_BK2_IO2: 9
+  USART6_RX: 8
+PH0: {}
+PH1: {}
+PH10:
+  DCMI_D1: 13
+  FMC_D18: 12
+  LTDC_R4: 14
+  TIM5_CH1: 2
+PH11:
+  DCMI_D2: 13
+  FMC_D19: 12
+  LTDC_R5: 14
+  TIM5_CH2: 2
+PH12:
+  DCMI_D3: 13
+  FMC_D20: 12
+  LTDC_R6: 14
+  TIM5_CH3: 2
+PH13:
+  CAN1_TX: 9
+  FMC_D21: 12
+  LTDC_G2: 14
+  TIM8_CH1N: 3
+PH14:
+  DCMI_D4: 13
+  FMC_D22: 12
+  LTDC_G3: 14
+  TIM8_CH2N: 3
+PH15:
+  DCMI_D11: 13
+  FMC_D23: 12
+  LTDC_G4: 14
+  TIM8_CH3N: 3
+PH2:
+  ETH_CRS: 11
+  FMC_SDCKE0: 12
+  LTDC_R0: 14
+  QUADSPI_BK2_IO0: 9
+PH3:
+  ETH_COL: 11
+  FMC_SDNE0: 12
+  LTDC_R1: 14
+  QUADSPI_BK2_IO1: 9
+PH4:
+  I2C2_SCL: 4
+  LTDC_G4: 14
+  LTDC_G5: 9
+  USB_OTG_HS_ULPI_NXT: 10
+PH5:
+  FMC_SDNWE: 12
+  I2C2_SDA: 4
+  SPI5_NSS: 5
+PH6:
+  DCMI_D8: 13
+  ETH_RXD2: 11
+  FMC_SDNE1: 12
+  I2C2_SMBA: 4
+  SPI5_SCK: 5
+  TIM12_CH1: 9
+PH7:
+  DCMI_D9: 13
+  ETH_RXD3: 11
+  FMC_SDCKE1: 12
+  I2C3_SCL: 4
+  SPI5_MISO: 5
+PH8:
+  DCMI_HSYNC: 13
+  FMC_D16: 12
+  I2C3_SDA: 4
+  LTDC_R2: 14
+PH9:
+  DCMI_D0: 13
+  FMC_D17: 12
+  I2C3_SMBA: 4
+  LTDC_R3: 14
+  TIM12_CH2: 9
+PI0:
+  DCMI_D13: 13
+  FMC_D24: 12
+  I2S2_WS: 5
+  LTDC_G5: 14
+  SPI2_NSS: 5
+  TIM5_CH4: 2
+PI1:
+  DCMI_D8: 13
+  FMC_D25: 12
+  I2S2_CK: 5
+  LTDC_G6: 14
+  SPI2_SCK: 5
+PI10:
+  ETH_RX_ER: 11
+  FMC_D31: 12
+  LTDC_HSYNC: 14
+PI11:
+  LTDC_G6: 9
+  USB_OTG_HS_ULPI_DIR: 10
+PI12:
+  LTDC_HSYNC: 14
+PI13:
+  LTDC_VSYNC: 14
+PI14:
+  LTDC_CLK: 14
+PI15:
+  LTDC_G2: 9
+  LTDC_R0: 14
+PI2:
+  DCMI_D9: 13
+  FMC_D26: 12
+  I2S2_ext_SD: 6
+  LTDC_G7: 14
+  SPI2_MISO: 5
+  TIM8_CH4: 3
+PI3:
+  DCMI_D10: 13
+  FMC_D27: 12
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIM8_ETR: 3
+PI4:
+  DCMI_D5: 13
+  FMC_NBL2: 12
+  LTDC_B4: 14
+  TIM8_BKIN: 3
+PI5:
+  DCMI_VSYNC: 13
+  FMC_NBL3: 12
+  LTDC_B5: 14
+  TIM8_CH1: 3
+PI6:
+  DCMI_D6: 13
+  FMC_D28: 12
+  LTDC_B6: 14
+  TIM8_CH2: 3
+PI7:
+  DCMI_D7: 13
+  FMC_D29: 12
+  LTDC_B7: 14
+  TIM8_CH3: 3
+PI8: {}
+PI9:
+  CAN1_RX: 9
+  FMC_D30: 12
+  LTDC_VSYNC: 14
+PJ0:
+  LTDC_R1: 14
+  LTDC_R7: 9
+PJ1:
+  LTDC_R2: 14
+PJ12:
+  LTDC_B0: 14
+  LTDC_G3: 9
+PJ13:
+  LTDC_B1: 14
+  LTDC_G4: 9
+PJ14:
+  LTDC_B2: 14
+PJ15:
+  LTDC_B3: 14
+PJ2:
+  DSIHOST_TE: 13
+  LTDC_R3: 14
+PJ3:
+  LTDC_R4: 14
+PJ4:
+  LTDC_R5: 14
+PJ5:
+  LTDC_R6: 14
+PK3:
+  LTDC_B4: 14
+PK4:
+  LTDC_B5: 14
+PK5:
+  LTDC_B6: 14
+PK6:
+  LTDC_B7: 14
+PK7:
+  LTDC_DE: 14

data/gpio_af/STM32F72x.yaml

@@ -0,0 +1,669 @@
+PA0:
+  SAI2_SD_B: 10
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM5_CH1: 2
+  TIM8_ETR: 3
+  UART4_TX: 8
+  USART2_CTS: 7
+PA1:
+  QUADSPI_BK1_IO3: 9
+  SAI2_MCLK_B: 10
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  UART4_RX: 8
+  USART2_DE: 7
+  USART2_RTS: 7
+PA10:
+  TIM1_CH3: 1
+  USART1_RX: 7
+  USB_OTG_FS_ID: 10
+PA11:
+  CAN1_RX: 9
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USB_OTG_FS_DM: 10
+PA12:
+  CAN1_TX: 9
+  SAI2_FS_B: 8
+  TIM1_ETR: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+  USB_OTG_FS_DP: 10
+PA13:
+  SYS_JTMS-SWDIO: 0
+PA14:
+  SYS_JTCK-SWCLK: 0
+PA15:
+  I2S1_WS: 5
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  UART4_DE: 8
+  UART4_RTS: 8
+PA2:
+  SAI2_SCK_B: 8
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  TIM9_CH1: 3
+  USART2_TX: 7
+PA3:
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  TIM9_CH2: 3
+  USART2_RX: 7
+  USB_OTG_HS_ULPI_D0: 10
+PA4:
+  I2S1_WS: 5
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  USART2_CK: 7
+  USB_OTG_HS_SOF: 12
+PA5:
+  I2S1_CK: 5
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM8_CH1N: 3
+  USB_OTG_HS_ULPI_CK: 10
+PA6:
+  SPI1_MISO: 5
+  TIM13_CH1: 9
+  TIM1_BKIN: 1
+  TIM3_CH1: 2
+  TIM8_BKIN: 3
+PA7:
+  FMC_SDNWE: 12
+  I2S1_SD: 5
+  SPI1_MOSI: 5
+  TIM14_CH1: 9
+  TIM1_CH1N: 1
+  TIM3_CH2: 2
+  TIM8_CH1N: 3
+PA8:
+  I2C3_SCL: 4
+  RCC_MCO_1: 0
+  TIM1_CH1: 1
+  TIM8_BKIN2: 3
+  USART1_CK: 7
+  USB_OTG_FS_SOF: 10
+PA9:
+  I2C3_SMBA: 4
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  TIM1_CH2N: 1
+  TIM3_CH3: 2
+  TIM8_CH2N: 3
+  UART4_CTS: 8
+  USB_OTG_HS_ULPI_D1: 10
+PB1:
+  TIM1_CH3N: 1
+  TIM3_CH4: 2
+  TIM8_CH3N: 3
+  USB_OTG_HS_ULPI_D2: 10
+PB10:
+  I2C2_SCL: 4
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+  USART3_TX: 7
+  USB_OTG_HS_ULPI_D3: 10
+PB11:
+  I2C2_SDA: 4
+  TIM2_CH4: 1
+  USART3_RX: 7
+  USB_OTG_HS_ULPI_D4: 10
+PB12:
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM1_BKIN: 1
+  USART3_CK: 7
+  USB_OTG_HS_ID: 12
+  USB_OTG_HS_ULPI_D5: 10
+PB13:
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM1_CH1N: 1
+  USART3_CTS: 7
+  USB_OTG_HS_ULPI_D6: 10
+PB14:
+  SDMMC2_D0: 10
+  SPI2_MISO: 5
+  TIM12_CH1: 9
+  TIM1_CH2N: 1
+  TIM8_CH2N: 3
+  USART3_DE: 7
+  USART3_RTS: 7
+  USB_OTG_HS_DM: 12
+PB15:
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SDMMC2_D1: 10
+  SPI2_MOSI: 5
+  TIM12_CH2: 9
+  TIM1_CH3N: 1
+  TIM8_CH3N: 3
+  USB_OTG_HS_DP: 12
+PB2:
+  I2S3_SD: 7
+  QUADSPI_CLK: 9
+  SAI1_SD_A: 6
+  SPI3_MOSI: 7
+PB3:
+  I2S1_CK: 5
+  I2S3_CK: 6
+  SDMMC2_D2: 10
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+PB4:
+  I2S2_WS: 7
+  SDMMC2_D3: 10
+  SPI1_MISO: 5
+  SPI2_NSS: 7
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM3_CH1: 2
+PB5:
+  FMC_SDCKE1: 12
+  I2C1_SMBA: 4
+  I2S1_SD: 5
+  I2S3_SD: 6
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM3_CH2: 2
+  USB_OTG_HS_ULPI_D7: 10
+PB6:
+  FMC_SDNE1: 12
+  I2C1_SCL: 4
+  QUADSPI_BK1_NCS: 10
+  TIM4_CH1: 2
+  USART1_TX: 7
+PB7:
+  FMC_NL: 12
+  I2C1_SDA: 4
+  TIM4_CH2: 2
+  USART1_RX: 7
+PB8:
+  CAN1_RX: 9
+  I2C1_SCL: 4
+  SDMMC1_D4: 12
+  SDMMC2_D4: 10
+  TIM10_CH1: 3
+  TIM4_CH3: 2
+PB9:
+  CAN1_TX: 9
+  I2C1_SDA: 4
+  I2S2_WS: 5
+  SDMMC1_D5: 12
+  SDMMC2_D5: 10
+  SPI2_NSS: 5
+  TIM11_CH1: 3
+  TIM4_CH4: 2
+PC0:
+  FMC_SDNWE: 12
+  SAI2_FS_B: 8
+  USB_OTG_HS_ULPI_STP: 10
+PC1:
+  I2S2_SD: 5
+  SAI1_SD_A: 6
+  SPI2_MOSI: 5
+  SYS_TRACED0: 0
+PC10:
+  I2S3_CK: 6
+  QUADSPI_BK1_IO1: 9
+  SDMMC1_D2: 12
+  SPI3_SCK: 6
+  UART4_TX: 8
+  USART3_TX: 7
+PC11:
+  QUADSPI_BK2_NCS: 9
+  SDMMC1_D3: 12
+  SPI3_MISO: 6
+  UART4_RX: 8
+  USART3_RX: 7
+PC12:
+  I2S3_SD: 6
+  SDMMC1_CK: 12
+  SPI3_MOSI: 6
+  SYS_TRACED3: 0
+  UART5_TX: 8
+  USART3_CK: 7
+PC13: {}
+PC14: {}
+PC15: {}
+PC2:
+  FMC_SDNE0: 12
+  SPI2_MISO: 5
+  USB_OTG_HS_ULPI_DIR: 10
+PC3:
+  FMC_SDCKE0: 12
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  USB_OTG_HS_ULPI_NXT: 10
+PC4:
+  FMC_SDNE0: 12
+  I2S1_MCK: 5
+PC5:
+  FMC_SDCKE0: 12
+PC6:
+  I2S2_MCK: 5
+  SDMMC1_D6: 12
+  SDMMC2_D6: 10
+  TIM3_CH1: 2
+  TIM8_CH1: 3
+  USART6_TX: 8
+PC7:
+  I2S3_MCK: 6
+  SDMMC1_D7: 12
+  SDMMC2_D7: 10
+  TIM3_CH2: 2
+  TIM8_CH2: 3
+  USART6_RX: 8
+PC8:
+  SDMMC1_D0: 12
+  SYS_TRACED1: 0
+  TIM3_CH3: 2
+  TIM8_CH3: 3
+  UART5_DE: 7
+  UART5_RTS: 7
+  USART6_CK: 8
+PC9:
+  I2C3_SDA: 4
+  I2S_CKIN: 5
+  QUADSPI_BK1_IO0: 9
+  RCC_MCO_2: 0
+  SDMMC1_D1: 12
+  TIM3_CH4: 2
+  TIM8_CH4: 3
+  UART5_CTS: 7
+PD0:
+  CAN1_RX: 9
+  FMC_D2: 12
+  FMC_DA2: 12
+PD1:
+  CAN1_TX: 9
+  FMC_D3: 12
+  FMC_DA3: 12
+PD10:
+  FMC_D15: 12
+  FMC_DA15: 12
+  USART3_CK: 7
+PD11:
+  FMC_A16: 12
+  FMC_CLE: 12
+  QUADSPI_BK1_IO0: 9
+  SAI2_SD_A: 10
+  USART3_CTS: 7
+PD12:
+  FMC_A17: 12
+  FMC_ALE: 12
+  LPTIM1_IN1: 3
+  QUADSPI_BK1_IO1: 9
+  SAI2_FS_A: 10
+  TIM4_CH1: 2
+  USART3_DE: 7
+  USART3_RTS: 7
+PD13:
+  FMC_A18: 12
+  LPTIM1_OUT: 3
+  QUADSPI_BK1_IO3: 9
+  SAI2_SCK_A: 10
+  TIM4_CH2: 2
+PD14:
+  FMC_D0: 12
+  FMC_DA0: 12
+  TIM4_CH3: 2
+  UART8_CTS: 8
+PD15:
+  FMC_D1: 12
+  FMC_DA1: 12
+  TIM4_CH4: 2
+  UART8_DE: 8
+  UART8_RTS: 8
+PD2:
+  SDMMC1_CMD: 12
+  SYS_TRACED2: 0
+  TIM3_ETR: 2
+  UART5_RX: 8
+PD3:
+  FMC_CLK: 12
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  USART2_CTS: 7
+PD4:
+  FMC_NOE: 12
+  USART2_DE: 7
+  USART2_RTS: 7
+PD5:
+  FMC_NWE: 12
+  USART2_TX: 7
+PD6:
+  FMC_NWAIT: 12
+  I2S3_SD: 5
+  SAI1_SD_A: 6
+  SDMMC2_CK: 11
+  SPI3_MOSI: 5
+  USART2_RX: 7
+PD7:
+  FMC_NE1: 12
+  SDMMC2_CMD: 11
+  USART2_CK: 7
+PD8:
+  FMC_D13: 12
+  FMC_DA13: 12
+  USART3_TX: 7
+PD9:
+  FMC_D14: 12
+  FMC_DA14: 12
+  USART3_RX: 7
+PE0:
+  FMC_NBL0: 12
+  LPTIM1_ETR: 3
+  SAI2_MCLK_A: 10
+  TIM4_ETR: 2
+  UART8_RX: 8
+PE1:
+  FMC_NBL1: 12
+  LPTIM1_IN2: 3
+  UART8_TX: 8
+PE10:
+  FMC_D7: 12
+  FMC_DA7: 12
+  QUADSPI_BK2_IO3: 10
+  TIM1_CH2N: 1
+  UART7_CTS: 8
+PE11:
+  FMC_D8: 12
+  FMC_DA8: 12
+  SAI2_SD_B: 10
+  SPI4_NSS: 5
+  TIM1_CH2: 1
+PE12:
+  FMC_D9: 12
+  FMC_DA9: 12
+  SAI2_SCK_B: 10
+  SPI4_SCK: 5
+  TIM1_CH3N: 1
+PE13:
+  FMC_D10: 12
+  FMC_DA10: 12
+  SAI2_FS_B: 10
+  SPI4_MISO: 5
+  TIM1_CH3: 1
+PE14:
+  FMC_D11: 12
+  FMC_DA11: 12
+  SAI2_MCLK_B: 10
+  SPI4_MOSI: 5
+  TIM1_CH4: 1
+PE15:
+  FMC_D12: 12
+  FMC_DA12: 12
+  TIM1_BKIN: 1
+PE2:
+  FMC_A23: 12
+  QUADSPI_BK1_IO2: 9
+  SAI1_MCLK_A: 6
+  SPI4_SCK: 5
+  SYS_TRACECLK: 0
+PE3:
+  FMC_A19: 12
+  SAI1_SD_B: 6
+  SYS_TRACED0: 0
+PE4:
+  FMC_A20: 12
+  SAI1_FS_A: 6
+  SPI4_NSS: 5
+  SYS_TRACED1: 0
+PE5:
+  FMC_A21: 12
+  SAI1_SCK_A: 6
+  SPI4_MISO: 5
+  SYS_TRACED2: 0
+  TIM9_CH1: 3
+PE6:
+  FMC_A22: 12
+  SAI1_SD_A: 6
+  SAI2_MCLK_B: 10
+  SPI4_MOSI: 5
+  SYS_TRACED3: 0
+  TIM1_BKIN2: 1
+  TIM9_CH2: 3
+PE7:
+  FMC_D4: 12
+  FMC_DA4: 12
+  QUADSPI_BK2_IO0: 10
+  TIM1_ETR: 1
+  UART7_RX: 8
+PE8:
+  FMC_D5: 12
+  FMC_DA5: 12
+  QUADSPI_BK2_IO1: 10
+  TIM1_CH1N: 1
+  UART7_TX: 8
+PE9:
+  FMC_D6: 12
+  FMC_DA6: 12
+  QUADSPI_BK2_IO2: 10
+  TIM1_CH1: 1
+  UART7_DE: 8
+  UART7_RTS: 8
+PF0:
+  FMC_A0: 12
+  I2C2_SDA: 4
+PF1:
+  FMC_A1: 12
+  I2C2_SCL: 4
+PF10: {}
+PF11:
+  FMC_SDNRAS: 12
+  SAI2_SD_B: 10
+  SPI5_MOSI: 5
+PF12:
+  FMC_A6: 12
+PF13:
+  FMC_A7: 12
+PF14:
+  FMC_A8: 12
+PF15:
+  FMC_A9: 12
+PF2:
+  FMC_A2: 12
+  I2C2_SMBA: 4
+PF3:
+  FMC_A3: 12
+PF4:
+  FMC_A4: 12
+PF5:
+  FMC_A5: 12
+PF6:
+  QUADSPI_BK1_IO3: 9
+  SAI1_SD_B: 6
+  SPI5_NSS: 5
+  TIM10_CH1: 3
+  UART7_RX: 8
+PF7:
+  QUADSPI_BK1_IO2: 9
+  SAI1_MCLK_B: 6
+  SPI5_SCK: 5
+  TIM11_CH1: 3
+  UART7_TX: 8
+PF8:
+  QUADSPI_BK1_IO0: 10
+  SAI1_SCK_B: 6
+  SPI5_MISO: 5
+  TIM13_CH1: 9
+  UART7_DE: 8
+  UART7_RTS: 8
+PF9:
+  QUADSPI_BK1_IO1: 10
+  SAI1_FS_B: 6
+  SPI5_MOSI: 5
+  TIM14_CH1: 9
+  UART7_CTS: 8
+PG0:
+  FMC_A10: 12
+PG1:
+  FMC_A11: 12
+PG10:
+  FMC_NE3: 12
+  SAI2_SD_B: 10
+  SDMMC2_D1: 11
+PG11:
+  FMC_INT: 12
+  SDMMC2_D2: 10
+PG12:
+  FMC_NE4: 12
+  LPTIM1_IN1: 3
+  SDMMC2_D3: 11
+  USART6_DE: 8
+  USART6_RTS: 8
+PG13:
+  FMC_A24: 12
+  LPTIM1_OUT: 3
+  SYS_TRACED0: 0
+  USART6_CTS: 8
+PG14:
+  FMC_A25: 12
+  LPTIM1_ETR: 3
+  QUADSPI_BK2_IO3: 9
+  SYS_TRACED1: 0
+  USART6_TX: 8
+PG15:
+  FMC_SDNCAS: 12
+  USART6_CTS: 8
+PG2:
+  FMC_A12: 12
+PG3:
+  FMC_A13: 12
+PG4:
+  FMC_A14: 12
+  FMC_BA0: 12
+PG5:
+  FMC_A15: 12
+  FMC_BA1: 12
+PG6: {}
+PG7:
+  FMC_INT: 12
+  USART6_CK: 8
+PG8:
+  FMC_SDCLK: 12
+  USART6_DE: 8
+  USART6_RTS: 8
+PG9:
+  FMC_NCE: 12
+  FMC_NE2: 12
+  QUADSPI_BK2_IO2: 9
+  SAI2_FS_B: 10
+  SDMMC2_D0: 11
+  USART6_RX: 8
+PH0: {}
+PH1: {}
+PH10:
+  FMC_D18: 12
+  TIM5_CH1: 2
+PH11:
+  FMC_D19: 12
+  TIM5_CH2: 2
+PH12:
+  FMC_D20: 12
+  TIM5_CH3: 2
+PH13:
+  CAN1_TX: 9
+  FMC_D21: 12
+  TIM8_CH1N: 3
+  UART4_TX: 8
+PH14:
+  CAN1_RX: 9
+  FMC_D22: 12
+  TIM8_CH2N: 3
+  UART4_RX: 8
+PH15:
+  FMC_D23: 12
+  TIM8_CH3N: 3
+PH2:
+  FMC_SDCKE0: 12
+  LPTIM1_IN2: 3
+  QUADSPI_BK2_IO0: 9
+  SAI2_SCK_B: 10
+PH3:
+  FMC_SDNE0: 12
+  QUADSPI_BK2_IO1: 9
+  SAI2_MCLK_B: 10
+PH4:
+  I2C2_SCL: 4
+  USB_OTG_HS_ULPI_NXT: 10
+PH5:
+  FMC_SDNWE: 12
+  I2C2_SDA: 4
+  SPI5_NSS: 5
+PH6:
+  FMC_SDNE1: 12
+  I2C2_SMBA: 4
+  SPI5_SCK: 5
+  TIM12_CH1: 9
+PH7:
+  FMC_SDCKE1: 12
+  I2C3_SCL: 4
+  SPI5_MISO: 5
+PH8:
+  FMC_D16: 12
+  I2C3_SDA: 4
+PH9:
+  FMC_D17: 12
+  I2C3_SMBA: 4
+  TIM12_CH2: 9
+PI0:
+  FMC_D24: 12
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM5_CH4: 2
+PI1:
+  FMC_D25: 12
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM8_BKIN2: 3
+PI10:
+  FMC_D31: 12
+PI11:
+  USB_OTG_HS_ULPI_DIR: 10
+PI2:
+  FMC_D26: 12
+  SPI2_MISO: 5
+  TIM8_CH4: 3
+PI3:
+  FMC_D27: 12
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIM8_ETR: 3
+PI4:
+  FMC_NBL2: 12
+  SAI2_MCLK_A: 10
+  TIM8_BKIN: 3
+PI5:
+  FMC_NBL3: 12
+  SAI2_SCK_A: 10
+  TIM8_CH1: 3
+PI6:
+  FMC_D28: 12
+  SAI2_SD_A: 10
+  TIM8_CH2: 3
+PI7:
+  FMC_D29: 12
+  SAI2_FS_A: 10
+  TIM8_CH3: 3
+PI8: {}
+PI9:
+  CAN1_RX: 9
+  FMC_D30: 12
+  UART4_RX: 8

data/gpio_af/STM32F746.yaml

@@ -0,0 +1,871 @@
+PA0:
+  ETH_CRS: 11
+  SAI2_SD_B: 10
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM5_CH1: 2
+  TIM8_ETR: 3
+  UART4_TX: 8
+  USART2_CTS: 7
+PA1:
+  ETH_REF_CLK: 11
+  ETH_RX_CLK: 11
+  LTDC_R2: 14
+  QUADSPI_BK1_IO3: 9
+  SAI2_MCLK_B: 10
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  UART4_RX: 8
+  USART2_DE: 7
+  USART2_RTS: 7
+PA10:
+  DCMI_D1: 13
+  TIM1_CH3: 1
+  USART1_RX: 7
+  USB_OTG_FS_ID: 10
+PA11:
+  CAN1_RX: 9
+  LTDC_R4: 14
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USB_OTG_FS_DM: 10
+PA12:
+  CAN1_TX: 9
+  LTDC_R5: 14
+  SAI2_FS_B: 8
+  TIM1_ETR: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+  USB_OTG_FS_DP: 10
+PA13:
+  SYS_JTMS-SWDIO: 0
+PA14:
+  SYS_JTCK-SWCLK: 0
+PA15:
+  CEC: 4
+  I2S1_WS: 5
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  UART4_DE: 8
+  UART4_RTS: 8
+PA2:
+  ETH_MDIO: 11
+  LTDC_R1: 14
+  SAI2_SCK_B: 8
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  TIM9_CH1: 3
+  USART2_TX: 7
+PA3:
+  ETH_COL: 11
+  LTDC_B5: 14
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  TIM9_CH2: 3
+  USART2_RX: 7
+  USB_OTG_HS_ULPI_D0: 10
+PA4:
+  DCMI_HSYNC: 13
+  I2S1_WS: 5
+  I2S3_WS: 6
+  LTDC_VSYNC: 14
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  USART2_CK: 7
+  USB_OTG_HS_SOF: 12
+PA5:
+  I2S1_CK: 5
+  LTDC_R4: 14
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIM8_CH1N: 3
+  USB_OTG_HS_ULPI_CK: 10
+PA6:
+  DCMI_PIXCLK: 13
+  LTDC_G2: 14
+  SPI1_MISO: 5
+  TIM13_CH1: 9
+  TIM1_BKIN: 1
+  TIM3_CH1: 2
+  TIM8_BKIN: 3
+PA7:
+  ETH_CRS_DV: 11
+  ETH_RX_DV: 11
+  FMC_SDNWE: 12
+  I2S1_SD: 5
+  SPI1_MOSI: 5
+  TIM14_CH1: 9
+  TIM1_CH1N: 1
+  TIM3_CH2: 2
+  TIM8_CH1N: 3
+PA8:
+  I2C3_SCL: 4
+  LTDC_R6: 14
+  RCC_MCO_1: 0
+  TIM1_CH1: 1
+  TIM8_BKIN2: 3
+  USART1_CK: 7
+  USB_OTG_FS_SOF: 10
+PA9:
+  DCMI_D0: 13
+  I2C3_SMBA: 4
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  ETH_RXD2: 11
+  LTDC_R3: 9
+  TIM1_CH2N: 1
+  TIM3_CH3: 2
+  TIM8_CH2N: 3
+  UART4_CTS: 8
+  USB_OTG_HS_ULPI_D1: 10
+PB1:
+  ETH_RXD3: 11
+  LTDC_R6: 9
+  TIM1_CH3N: 1
+  TIM3_CH4: 2
+  TIM8_CH3N: 3
+  USB_OTG_HS_ULPI_D2: 10
+PB10:
+  ETH_RX_ER: 11
+  I2C2_SCL: 4
+  I2S2_CK: 5
+  LTDC_G4: 14
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+  USART3_TX: 7
+  USB_OTG_HS_ULPI_D3: 10
+PB11:
+  ETH_TX_EN: 11
+  I2C2_SDA: 4
+  LTDC_G5: 14
+  TIM2_CH4: 1
+  USART3_RX: 7
+  USB_OTG_HS_ULPI_D4: 10
+PB12:
+  CAN2_RX: 9
+  ETH_TXD0: 11
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM1_BKIN: 1
+  USART3_CK: 7
+  USB_OTG_HS_ID: 12
+  USB_OTG_HS_ULPI_D5: 10
+PB13:
+  CAN2_TX: 9
+  ETH_TXD1: 11
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIM1_CH1N: 1
+  USART3_CTS: 7
+  USB_OTG_HS_ULPI_D6: 10
+PB14:
+  SPI2_MISO: 5
+  TIM12_CH1: 9
+  TIM1_CH2N: 1
+  TIM8_CH2N: 3
+  USART3_DE: 7
+  USART3_RTS: 7
+  USB_OTG_HS_DM: 12
+PB15:
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM12_CH2: 9
+  TIM1_CH3N: 1
+  TIM8_CH3N: 3
+  USB_OTG_HS_DP: 12
+PB2:
+  I2S3_SD: 7
+  QUADSPI_CLK: 9
+  SAI1_SD_A: 6
+  SPI3_MOSI: 7
+PB3:
+  I2S1_CK: 5
+  I2S3_CK: 6
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+PB4:
+  I2S2_WS: 7
+  SPI1_MISO: 5
+  SPI2_NSS: 7
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM3_CH1: 2
+PB5:
+  CAN2_RX: 9
+  DCMI_D10: 13
+  ETH_PPS_OUT: 11
+  FMC_SDCKE1: 12
+  I2C1_SMBA: 4
+  I2S1_SD: 5
+  I2S3_SD: 6
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM3_CH2: 2
+  USB_OTG_HS_ULPI_D7: 10
+PB6:
+  CAN2_TX: 9
+  CEC: 3
+  DCMI_D5: 13
+  FMC_SDNE1: 12
+  I2C1_SCL: 4
+  QUADSPI_BK1_NCS: 10
+  TIM4_CH1: 2
+  USART1_TX: 7
+PB7:
+  DCMI_VSYNC: 13
+  FMC_NL: 12
+  I2C1_SDA: 4
+  TIM4_CH2: 2
+  USART1_RX: 7
+PB8:
+  CAN1_RX: 9
+  DCMI_D6: 13
+  ETH_TXD3: 11
+  I2C1_SCL: 4
+  LTDC_B6: 14
+  SDMMC1_D4: 12
+  TIM10_CH1: 3
+  TIM4_CH3: 2
+PB9:
+  CAN1_TX: 9
+  DCMI_D7: 13
+  I2C1_SDA: 4
+  I2S2_WS: 5
+  LTDC_B7: 14
+  SDMMC1_D5: 12
+  SPI2_NSS: 5
+  TIM11_CH1: 3
+  TIM4_CH4: 2
+PC0:
+  FMC_SDNWE: 12
+  LTDC_R5: 14
+  SAI2_FS_B: 8
+  USB_OTG_HS_ULPI_STP: 10
+PC1:
+  ETH_MDC: 11
+  I2S2_SD: 5
+  SAI1_SD_A: 6
+  SPI2_MOSI: 5
+  SYS_TRACED0: 0
+PC10:
+  DCMI_D8: 13
+  I2S3_CK: 6
+  LTDC_R2: 14
+  QUADSPI_BK1_IO1: 9
+  SDMMC1_D2: 12
+  SPI3_SCK: 6
+  UART4_TX: 8
+  USART3_TX: 7
+PC11:
+  DCMI_D4: 13
+  QUADSPI_BK2_NCS: 9
+  SDMMC1_D3: 12
+  SPI3_MISO: 6
+  UART4_RX: 8
+  USART3_RX: 7
+PC12:
+  DCMI_D9: 13
+  I2S3_SD: 6
+  SDMMC1_CK: 12
+  SPI3_MOSI: 6
+  SYS_TRACED3: 0
+  UART5_TX: 8
+  USART3_CK: 7
+PC13: {}
+PC14: {}
+PC15: {}
+PC2:
+  ETH_TXD2: 11
+  FMC_SDNE0: 12
+  SPI2_MISO: 5
+  USB_OTG_HS_ULPI_DIR: 10
+PC3:
+  ETH_TX_CLK: 11
+  FMC_SDCKE0: 12
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  USB_OTG_HS_ULPI_NXT: 10
+PC4:
+  ETH_RXD0: 11
+  FMC_SDNE0: 12
+  I2S1_MCK: 5
+  SPDIFRX_IN2: 8
+PC5:
+  ETH_RXD1: 11
+  FMC_SDCKE0: 12
+  SPDIFRX_IN3: 8
+PC6:
+  DCMI_D0: 13
+  I2S2_MCK: 5
+  LTDC_HSYNC: 14
+  SDMMC1_D6: 12
+  TIM3_CH1: 2
+  TIM8_CH1: 3
+  USART6_TX: 8
+PC7:
+  DCMI_D1: 13
+  I2S3_MCK: 6
+  LTDC_G6: 14
+  SDMMC1_D7: 12
+  TIM3_CH2: 2
+  TIM8_CH2: 3
+  USART6_RX: 8
+PC8:
+  DCMI_D2: 13
+  SDMMC1_D0: 12
+  SYS_TRACED1: 0
+  TIM3_CH3: 2
+  TIM8_CH3: 3
+  UART5_DE: 7
+  UART5_RTS: 7
+  USART6_CK: 8
+PC9:
+  DCMI_D3: 13
+  I2C3_SDA: 4
+  I2S_CKIN: 5
+  QUADSPI_BK1_IO0: 9
+  RCC_MCO_2: 0
+  SDMMC1_D1: 12
+  TIM3_CH4: 2
+  TIM8_CH4: 3
+  UART5_CTS: 7
+PD0:
+  CAN1_RX: 9
+  FMC_D2: 12
+  FMC_DA2: 12
+PD1:
+  CAN1_TX: 9
+  FMC_D3: 12
+  FMC_DA3: 12
+PD10:
+  FMC_D15: 12
+  FMC_DA15: 12
+  LTDC_B3: 14
+  USART3_CK: 7
+PD11:
+  FMC_A16: 12
+  FMC_CLE: 12
+  I2C4_SMBA: 4
+  QUADSPI_BK1_IO0: 9
+  SAI2_SD_A: 10
+  USART3_CTS: 7
+PD12:
+  FMC_A17: 12
+  FMC_ALE: 12
+  I2C4_SCL: 4
+  LPTIM1_IN1: 3
+  QUADSPI_BK1_IO1: 9
+  SAI2_FS_A: 10
+  TIM4_CH1: 2
+  USART3_DE: 7
+  USART3_RTS: 7
+PD13:
+  FMC_A18: 12
+  I2C4_SDA: 4
+  LPTIM1_OUT: 3
+  QUADSPI_BK1_IO3: 9
+  SAI2_SCK_A: 10
+  TIM4_CH2: 2
+PD14:
+  FMC_D0: 12
+  FMC_DA0: 12
+  TIM4_CH3: 2
+  UART8_CTS: 8
+PD15:
+  FMC_D1: 12
+  FMC_DA1: 12
+  TIM4_CH4: 2
+  UART8_DE: 8
+  UART8_RTS: 8
+PD2:
+  DCMI_D11: 13
+  SDMMC1_CMD: 12
+  SYS_TRACED2: 0
+  TIM3_ETR: 2
+  UART5_RX: 8
+PD3:
+  DCMI_D5: 13
+  FMC_CLK: 12
+  I2S2_CK: 5
+  LTDC_G7: 14
+  SPI2_SCK: 5
+  USART2_CTS: 7
+PD4:
+  FMC_NOE: 12
+  USART2_DE: 7
+  USART2_RTS: 7
+PD5:
+  FMC_NWE: 12
+  USART2_TX: 7
+PD6:
+  DCMI_D10: 13
+  FMC_NWAIT: 12
+  I2S3_SD: 5
+  LTDC_B2: 14
+  SAI1_SD_A: 6
+  SPI3_MOSI: 5
+  USART2_RX: 7
+PD7:
+  FMC_NE1: 12
+  SPDIFRX_IN0: 8
+  USART2_CK: 7
+PD8:
+  FMC_D13: 12
+  FMC_DA13: 12
+  SPDIFRX_IN1: 8
+  USART3_TX: 7
+PD9:
+  FMC_D14: 12
+  FMC_DA14: 12
+  USART3_RX: 7
+PE0:
+  DCMI_D2: 13
+  FMC_NBL0: 12
+  LPTIM1_ETR: 3
+  SAI2_MCLK_A: 10
+  TIM4_ETR: 2
+  UART8_RX: 8
+PE1:
+  DCMI_D3: 13
+  FMC_NBL1: 12
+  LPTIM1_IN2: 3
+  UART8_TX: 8
+PE10:
+  FMC_D7: 12
+  FMC_DA7: 12
+  QUADSPI_BK2_IO3: 10
+  TIM1_CH2N: 1
+  UART7_CTS: 8
+PE11:
+  FMC_D8: 12
+  FMC_DA8: 12
+  LTDC_G3: 14
+  SAI2_SD_B: 10
+  SPI4_NSS: 5
+  TIM1_CH2: 1
+PE12:
+  FMC_D9: 12
+  FMC_DA9: 12
+  LTDC_B4: 14
+  SAI2_SCK_B: 10
+  SPI4_SCK: 5
+  TIM1_CH3N: 1
+PE13:
+  FMC_D10: 12
+  FMC_DA10: 12
+  LTDC_DE: 14
+  SAI2_FS_B: 10
+  SPI4_MISO: 5
+  TIM1_CH3: 1
+PE14:
+  FMC_D11: 12
+  FMC_DA11: 12
+  LTDC_CLK: 14
+  SAI2_MCLK_B: 10
+  SPI4_MOSI: 5
+  TIM1_CH4: 1
+PE15:
+  FMC_D12: 12
+  FMC_DA12: 12
+  LTDC_R7: 14
+  TIM1_BKIN: 1
+PE2:
+  ETH_TXD3: 11
+  FMC_A23: 12
+  QUADSPI_BK1_IO2: 9
+  SAI1_MCLK_A: 6
+  SPI4_SCK: 5
+  SYS_TRACECLK: 0
+PE3:
+  FMC_A19: 12
+  SAI1_SD_B: 6
+  SYS_TRACED0: 0
+PE4:
+  DCMI_D4: 13
+  FMC_A20: 12
+  LTDC_B0: 14
+  SAI1_FS_A: 6
+  SPI4_NSS: 5
+  SYS_TRACED1: 0
+PE5:
+  DCMI_D6: 13
+  FMC_A21: 12
+  LTDC_G0: 14
+  SAI1_SCK_A: 6
+  SPI4_MISO: 5
+  SYS_TRACED2: 0
+  TIM9_CH1: 3
+PE6:
+  DCMI_D7: 13
+  FMC_A22: 12
+  LTDC_G1: 14
+  SAI1_SD_A: 6
+  SAI2_MCLK_B: 10
+  SPI4_MOSI: 5
+  SYS_TRACED3: 0
+  TIM1_BKIN2: 1
+  TIM9_CH2: 3
+PE7:
+  FMC_D4: 12
+  FMC_DA4: 12
+  QUADSPI_BK2_IO0: 10
+  TIM1_ETR: 1
+  UART7_RX: 8
+PE8:
+  FMC_D5: 12
+  FMC_DA5: 12
+  QUADSPI_BK2_IO1: 10
+  TIM1_CH1N: 1
+  UART7_TX: 8
+PE9:
+  FMC_D6: 12
+  FMC_DA6: 12
+  QUADSPI_BK2_IO2: 10
+  TIM1_CH1: 1
+  UART7_DE: 8
+  UART7_RTS: 8
+PF0:
+  FMC_A0: 12
+  I2C2_SDA: 4
+PF1:
+  FMC_A1: 12
+  I2C2_SCL: 4
+PF10:
+  DCMI_D11: 13
+  LTDC_DE: 14
+PF11:
+  DCMI_D12: 13
+  FMC_SDNRAS: 12
+  SAI2_SD_B: 10
+  SPI5_MOSI: 5
+PF12:
+  FMC_A6: 12
+PF13:
+  FMC_A7: 12
+  I2C4_SMBA: 4
+PF14:
+  FMC_A8: 12
+  I2C4_SCL: 4
+PF15:
+  FMC_A9: 12
+  I2C4_SDA: 4
+PF2:
+  FMC_A2: 12
+  I2C2_SMBA: 4
+PF3:
+  FMC_A3: 12
+PF4:
+  FMC_A4: 12
+PF5:
+  FMC_A5: 12
+PF6:
+  QUADSPI_BK1_IO3: 9
+  SAI1_SD_B: 6
+  SPI5_NSS: 5
+  TIM10_CH1: 3
+  UART7_RX: 8
+PF7:
+  QUADSPI_BK1_IO2: 9
+  SAI1_MCLK_B: 6
+  SPI5_SCK: 5
+  TIM11_CH1: 3
+  UART7_TX: 8
+PF8:
+  QUADSPI_BK1_IO0: 10
+  SAI1_SCK_B: 6
+  SPI5_MISO: 5
+  TIM13_CH1: 9
+  UART7_DE: 8
+  UART7_RTS: 8
+PF9:
+  QUADSPI_BK1_IO1: 10
+  SAI1_FS_B: 6
+  SPI5_MOSI: 5
+  TIM14_CH1: 9
+  UART7_CTS: 8
+PG0:
+  FMC_A10: 12
+PG1:
+  FMC_A11: 12
+PG10:
+  DCMI_D2: 13
+  FMC_NE3: 12
+  LTDC_B2: 14
+  LTDC_G3: 9
+  SAI2_SD_B: 10
+PG11:
+  DCMI_D3: 13
+  ETH_TX_EN: 11
+  LTDC_B3: 14
+  SPDIFRX_IN0: 7
+PG12:
+  FMC_NE4: 12
+  LPTIM1_IN1: 3
+  LTDC_B1: 14
+  LTDC_B4: 9
+  SPDIFRX_IN1: 7
+  SPI6_MISO: 5
+  USART6_DE: 8
+  USART6_RTS: 8
+PG13:
+  ETH_TXD0: 11
+  FMC_A24: 12
+  LPTIM1_OUT: 3
+  LTDC_R0: 14
+  SPI6_SCK: 5
+  SYS_TRACED0: 0
+  USART6_CTS: 8
+PG14:
+  ETH_TXD1: 11
+  FMC_A25: 12
+  LPTIM1_ETR: 3
+  LTDC_B0: 14
+  QUADSPI_BK2_IO3: 9
+  SPI6_MOSI: 5
+  SYS_TRACED1: 0
+  USART6_TX: 8
+PG15:
+  DCMI_D13: 13
+  FMC_SDNCAS: 12
+  USART6_CTS: 8
+PG2:
+  FMC_A12: 12
+PG3:
+  FMC_A13: 12
+PG4:
+  FMC_A14: 12
+  FMC_BA0: 12
+PG5:
+  FMC_A15: 12
+  FMC_BA1: 12
+PG6:
+  DCMI_D12: 13
+  LTDC_R7: 14
+PG7:
+  DCMI_D13: 13
+  FMC_INT: 12
+  LTDC_CLK: 14
+  USART6_CK: 8
+PG8:
+  ETH_PPS_OUT: 11
+  FMC_SDCLK: 12
+  SPDIFRX_IN2: 7
+  SPI6_NSS: 5
+  USART6_DE: 8
+  USART6_RTS: 8
+PG9:
+  DCMI_VSYNC: 13
+  FMC_NCE: 12
+  FMC_NE2: 12
+  QUADSPI_BK2_IO2: 9
+  SAI2_FS_B: 10
+  SPDIFRX_IN3: 7
+  USART6_RX: 8
+PH0: {}
+PH1: {}
+PH10:
+  DCMI_D1: 13
+  FMC_D18: 12
+  I2C4_SMBA: 4
+  LTDC_R4: 14
+  TIM5_CH1: 2
+PH11:
+  DCMI_D2: 13
+  FMC_D19: 12
+  I2C4_SCL: 4
+  LTDC_R5: 14
+  TIM5_CH2: 2
+PH12:
+  DCMI_D3: 13
+  FMC_D20: 12
+  I2C4_SDA: 4
+  LTDC_R6: 14
+  TIM5_CH3: 2
+PH13:
+  CAN1_TX: 9
+  FMC_D21: 12
+  LTDC_G2: 14
+  TIM8_CH1N: 3
+PH14:
+  DCMI_D4: 13
+  FMC_D22: 12
+  LTDC_G3: 14
+  TIM8_CH2N: 3
+PH15:
+  DCMI_D11: 13
+  FMC_D23: 12
+  LTDC_G4: 14
+  TIM8_CH3N: 3
+PH2:
+  ETH_CRS: 11
+  FMC_SDCKE0: 12
+  LPTIM1_IN2: 3
+  LTDC_R0: 14
+  QUADSPI_BK2_IO0: 9
+  SAI2_SCK_B: 10
+PH3:
+  ETH_COL: 11
+  FMC_SDNE0: 12
+  LTDC_R1: 14
+  QUADSPI_BK2_IO1: 9
+  SAI2_MCLK_B: 10
+PH4:
+  I2C2_SCL: 4
+  USB_OTG_HS_ULPI_NXT: 10
+PH5:
+  FMC_SDNWE: 12
+  I2C2_SDA: 4
+  SPI5_NSS: 5
+PH6:
+  DCMI_D8: 13
+  ETH_RXD2: 11
+  FMC_SDNE1: 12
+  I2C2_SMBA: 4
+  SPI5_SCK: 5
+  TIM12_CH1: 9
+PH7:
+  DCMI_D9: 13
+  ETH_RXD3: 11
+  FMC_SDCKE1: 12
+  I2C3_SCL: 4
+  SPI5_MISO: 5
+PH8:
+  DCMI_HSYNC: 13
+  FMC_D16: 12
+  I2C3_SDA: 4
+  LTDC_R2: 14
+PH9:
+  DCMI_D0: 13
+  FMC_D17: 12
+  I2C3_SMBA: 4
+  LTDC_R3: 14
+  TIM12_CH2: 9
+PI0:
+  DCMI_D13: 13
+  FMC_D24: 12
+  I2S2_WS: 5
+  LTDC_G5: 14
+  SPI2_NSS: 5
+  TIM5_CH4: 2
+PI1:
+  DCMI_D8: 13
+  FMC_D25: 12
+  I2S2_CK: 5
+  LTDC_G6: 14
+  SPI2_SCK: 5
+  TIM8_BKIN2: 3
+PI10:
+  ETH_RX_ER: 11
+  FMC_D31: 12
+  LTDC_HSYNC: 14
+PI11:
+  USB_OTG_HS_ULPI_DIR: 10
+PI12:
+  LTDC_HSYNC: 14
+PI13:
+  LTDC_VSYNC: 14
+PI14:
+  LTDC_CLK: 14
+PI15:
+  LTDC_R0: 14
+PI2:
+  DCMI_D9: 13
+  FMC_D26: 12
+  LTDC_G7: 14
+  SPI2_MISO: 5
+  TIM8_CH4: 3
+PI3:
+  DCMI_D10: 13
+  FMC_D27: 12
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIM8_ETR: 3
+PI4:
+  DCMI_D5: 13
+  FMC_NBL2: 12
+  LTDC_B4: 14
+  SAI2_MCLK_A: 10
+  TIM8_BKIN: 3
+PI5:
+  DCMI_VSYNC: 13
+  FMC_NBL3: 12
+  LTDC_B5: 14
+  SAI2_SCK_A: 10
+  TIM8_CH1: 3
+PI6:
+  DCMI_D6: 13
+  FMC_D28: 12
+  LTDC_B6: 14
+  SAI2_SD_A: 10
+  TIM8_CH2: 3
+PI7:
+  DCMI_D7: 13
+  FMC_D29: 12
+  LTDC_B7: 14
+  SAI2_FS_A: 10
+  TIM8_CH3: 3
+PI8: {}
+PI9:
+  CAN1_RX: 9
+  FMC_D30: 12
+  LTDC_VSYNC: 14
+PJ0:
+  LTDC_R1: 14
+PJ1:
+  LTDC_R2: 14
+PJ10:
+  LTDC_G3: 14
+PJ11:
+  LTDC_G4: 14
+PJ12:
+  LTDC_B0: 14
+PJ13:
+  LTDC_B1: 14
+PJ14:
+  LTDC_B2: 14
+PJ15:
+  LTDC_B3: 14
+PJ2:
+  LTDC_R3: 14
+PJ3:
+  LTDC_R4: 14
+PJ4:
+  LTDC_R5: 14
+PJ5:
+  LTDC_R6: 14
+PJ6:
+  LTDC_R7: 14
+PJ7:
+  LTDC_G0: 14
+PJ8:
+  LTDC_G1: 14
+PJ9:
+  LTDC_G2: 14
+PK0:
+  LTDC_G5: 14
+PK1:
+  LTDC_G6: 14
+PK2:
+  LTDC_G7: 14
+PK3:
+  LTDC_B4: 14
+PK4:
+  LTDC_B5: 14
+PK5:
+  LTDC_B6: 14
+PK6:
+  LTDC_B7: 14
+PK7:
+  LTDC_DE: 14

data/gpio_af/STM32G03x.yaml

@@ -0,0 +1,243 @@
+PA0:
+  LPTIM1_OUT: 5
+  SPI2_SCK: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART2_CTS: 1
+  USART2_NSS: 1
+PA1:
+  EVENTOUT: 7
+  I2C1_SMBA: 6
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM2_CH2: 2
+  USART2_CK: 1
+  USART2_DE: 1
+  USART2_RTS: 1
+PA10:
+  EVENTOUT: 7
+  I2C1_SDA: 6
+  SPI2_MOSI: 0
+  TIM17_BK: 5
+  TIM1_CH3: 2
+  USART1_RX: 1
+PA11:
+  I2C2_SCL: 6
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM1_BK2: 5
+  TIM1_CH4: 2
+  USART1_CTS: 1
+  USART1_NSS: 1
+PA12:
+  I2C2_SDA: 6
+  I2S1_SD: 0
+  I2S_CKIN: 5
+  SPI1_MOSI: 0
+  TIM1_ETR: 2
+  USART1_CK: 1
+  USART1_DE: 1
+  USART1_RTS: 1
+PA13:
+  EVENTOUT: 7
+  IR_OUT: 1
+  SYS_SWDIO: 0
+PA14:
+  EVENTOUT: 7
+  SYS_SWCLK: 0
+  USART2_TX: 1
+PA15:
+  EVENTOUT: 7
+  I2S1_WS: 0
+  SPI1_NSS: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART2_RX: 1
+PA2:
+  I2S1_SD: 0
+  LPUART1_TX: 6
+  SPI1_MOSI: 0
+  TIM2_CH3: 2
+  USART2_TX: 1
+PA3:
+  EVENTOUT: 7
+  LPUART1_RX: 6
+  SPI2_MISO: 0
+  TIM2_CH4: 2
+  USART2_RX: 1
+PA4:
+  EVENTOUT: 7
+  I2S1_WS: 0
+  LPTIM2_OUT: 5
+  SPI1_NSS: 0
+  SPI2_MOSI: 1
+  TIM14_CH1: 4
+PA5:
+  EVENTOUT: 7
+  I2S1_CK: 0
+  LPTIM2_ETR: 5
+  SPI1_SCK: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+PA6:
+  I2S1_MCK: 0
+  LPUART1_CTS: 6
+  SPI1_MISO: 0
+  TIM16_CH1: 5
+  TIM1_BK: 2
+  TIM3_CH1: 1
+PA7:
+  I2S1_SD: 0
+  SPI1_MOSI: 0
+  TIM14_CH1: 4
+  TIM17_CH1: 5
+  TIM1_CH1N: 2
+  TIM3_CH2: 1
+PA8:
+  EVENTOUT: 7
+  LPTIM2_OUT: 5
+  RCC_MCO: 0
+  SPI2_NSS: 1
+  TIM1_CH1: 2
+PA9:
+  EVENTOUT: 7
+  I2C1_SCL: 6
+  RCC_MCO: 0
+  SPI2_MISO: 4
+  TIM1_CH2: 2
+  USART1_TX: 1
+PB0:
+  I2S1_WS: 0
+  LPTIM1_OUT: 5
+  SPI1_NSS: 0
+  TIM1_CH2N: 2
+  TIM3_CH3: 1
+PB1:
+  EVENTOUT: 7
+  LPTIM2_IN1: 5
+  LPUART1_DE: 6
+  LPUART1_RTS: 6
+  TIM14_CH1: 0
+  TIM1_CH3N: 2
+  TIM3_CH4: 1
+PB10:
+  I2C2_SCL: 6
+  LPUART1_RX: 1
+  SPI2_SCK: 5
+  TIM2_CH3: 2
+PB11:
+  I2C2_SDA: 6
+  LPUART1_TX: 1
+  SPI2_MOSI: 0
+  TIM2_CH4: 2
+PB12:
+  EVENTOUT: 7
+  LPUART1_DE: 1
+  LPUART1_RTS: 1
+  SPI2_NSS: 0
+  TIM1_BK: 2
+PB13:
+  EVENTOUT: 7
+  I2C2_SCL: 6
+  LPUART1_CTS: 1
+  SPI2_SCK: 0
+  TIM1_CH1N: 2
+PB14:
+  EVENTOUT: 7
+  I2C2_SDA: 6
+  SPI2_MISO: 0
+  TIM1_CH2N: 2
+PB15:
+  EVENTOUT: 7
+  SPI2_MOSI: 0
+  TIM1_CH3N: 2
+PB2:
+  EVENTOUT: 7
+  LPTIM1_OUT: 5
+  SPI2_MISO: 1
+PB3:
+  EVENTOUT: 7
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM1_CH2: 1
+  TIM2_CH2: 2
+  USART1_CK: 4
+  USART1_DE: 4
+  USART1_RTS: 4
+PB4:
+  EVENTOUT: 7
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM17_BK: 5
+  TIM3_CH1: 1
+  USART1_CTS: 4
+  USART1_NSS: 4
+PB5:
+  I2C1_SMBA: 6
+  I2S1_SD: 0
+  LPTIM1_IN1: 5
+  SPI1_MOSI: 0
+  TIM16_BK: 2
+  TIM3_CH2: 1
+PB6:
+  EVENTOUT: 7
+  I2C1_SCL: 6
+  LPTIM1_ETR: 5
+  SPI2_MISO: 4
+  TIM16_CH1N: 2
+  TIM1_CH3: 1
+  USART1_TX: 0
+PB7:
+  EVENTOUT: 7
+  I2C1_SDA: 6
+  LPTIM1_IN2: 5
+  SPI2_MOSI: 1
+  TIM17_CH1N: 2
+  USART1_RX: 0
+PB8:
+  EVENTOUT: 7
+  I2C1_SCL: 6
+  SPI2_SCK: 1
+  TIM16_CH1: 2
+PB9:
+  EVENTOUT: 7
+  I2C1_SDA: 6
+  IR_OUT: 0
+  SPI2_NSS: 5
+  TIM17_CH1: 2
+PC13:
+  TIM1_BK: 2
+PC14:
+  TIM1_BK2: 2
+PC15:
+  RCC_OSC32_EN: 0
+  RCC_OSC_EN: 1
+PC6:
+  TIM2_CH3: 2
+  TIM3_CH1: 1
+PC7:
+  TIM2_CH4: 2
+  TIM3_CH2: 1
+PD0:
+  EVENTOUT: 0
+  SPI2_NSS: 1
+  TIM16_CH1: 2
+PD1:
+  EVENTOUT: 0
+  SPI2_SCK: 1
+  TIM17_CH1: 2
+PD2:
+  TIM1_CH1N: 2
+  TIM3_ETR: 1
+PD3:
+  SPI2_MISO: 1
+  TIM1_CH2N: 2
+  USART2_CTS: 0
+  USART2_NSS: 0
+PF0:
+  TIM14_CH1: 2
+PF1:
+  RCC_OSC_EN: 0
+PF2:
+  RCC_MCO: 0
+PI8: {}

data/gpio_af/STM32G05x.yaml

@@ -0,0 +1,267 @@
+PA0:
+  COMP1_OUT: 7
+  LPTIM1_OUT: 5
+  SPI2_SCK: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART2_CTS: 1
+  USART2_NSS: 1
+PA1:
+  EVENTOUT: 7
+  I2C1_SMBA: 6
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM15_CH1N: 5
+  TIM2_CH2: 2
+  USART2_CK: 1
+  USART2_DE: 1
+  USART2_RTS: 1
+PA10:
+  EVENTOUT: 7
+  I2C1_SDA: 6
+  SPI2_MOSI: 0
+  TIM17_BK: 5
+  TIM1_CH3: 2
+  UCPD2_TXGND: 3
+  USART1_RX: 1
+PA11:
+  COMP1_OUT: 7
+  I2C2_SCL: 6
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM1_BK2: 5
+  TIM1_CH4: 2
+  USART1_CTS: 1
+  USART1_NSS: 1
+PA12:
+  COMP2_OUT: 7
+  I2C2_SDA: 6
+  I2S1_SD: 0
+  I2S_CKIN: 5
+  SPI1_MOSI: 0
+  TIM1_ETR: 2
+  USART1_CK: 1
+  USART1_DE: 1
+  USART1_RTS: 1
+PA13:
+  EVENTOUT: 7
+  IR_OUT: 1
+  SYS_SWDIO: 0
+PA14:
+  EVENTOUT: 7
+  SYS_SWCLK: 0
+  USART2_TX: 1
+PA15:
+  EVENTOUT: 7
+  I2S1_WS: 0
+  SPI1_NSS: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART2_RX: 1
+PA2:
+  COMP2_OUT: 7
+  I2S1_SD: 0
+  LPUART1_TX: 6
+  SPI1_MOSI: 0
+  TIM15_CH1: 5
+  TIM2_CH3: 2
+  USART2_TX: 1
+PA3:
+  EVENTOUT: 7
+  LPUART1_RX: 6
+  SPI2_MISO: 0
+  TIM15_CH2: 5
+  TIM2_CH4: 2
+  USART2_RX: 1
+PA4:
+  EVENTOUT: 7
+  I2S1_WS: 0
+  LPTIM2_OUT: 5
+  SPI1_NSS: 0
+  SPI2_MOSI: 1
+  TIM14_CH1: 4
+PA5:
+  EVENTOUT: 7
+  I2S1_CK: 0
+  LPTIM2_ETR: 5
+  SPI1_SCK: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+PA6:
+  COMP1_OUT: 7
+  I2S1_MCK: 0
+  LPUART1_CTS: 6
+  SPI1_MISO: 0
+  TIM16_CH1: 5
+  TIM1_BK: 2
+  TIM3_CH1: 1
+PA7:
+  COMP2_OUT: 7
+  I2S1_SD: 0
+  SPI1_MOSI: 0
+  TIM14_CH1: 4
+  TIM17_CH1: 5
+  TIM1_CH1N: 2
+  TIM3_CH2: 1
+PA8:
+  EVENTOUT: 7
+  LPTIM2_OUT: 5
+  RCC_MCO: 0
+  SPI2_NSS: 1
+  TIM1_CH1: 2
+PA9:
+  EVENTOUT: 7
+  I2C1_SCL: 6
+  RCC_MCO: 0
+  SPI2_MISO: 4
+  TIM15_BK: 5
+  TIM1_CH2: 2
+  UCPD1_TXGND: 3
+  USART1_TX: 1
+PB0:
+  COMP1_OUT: 7
+  I2S1_WS: 0
+  LPTIM1_OUT: 5
+  SPI1_NSS: 0
+  TIM1_CH2N: 2
+  TIM3_CH3: 1
+PB1:
+  EVENTOUT: 7
+  LPTIM2_IN1: 5
+  LPUART1_DE: 6
+  LPUART1_RTS: 6
+  TIM14_CH1: 0
+  TIM1_CH3N: 2
+  TIM3_CH4: 1
+PB10:
+  COMP1_OUT: 7
+  I2C2_SCL: 6
+  LPUART1_RX: 1
+  SPI2_SCK: 5
+  TIM2_CH3: 2
+PB11:
+  COMP2_OUT: 7
+  I2C2_SDA: 6
+  LPUART1_TX: 1
+  SPI2_MOSI: 0
+  TIM2_CH4: 2
+PB12:
+  EVENTOUT: 7
+  LPUART1_DE: 1
+  LPUART1_RTS: 1
+  SPI2_NSS: 0
+  TIM15_BK: 5
+  TIM1_BK: 2
+PB13:
+  EVENTOUT: 7
+  I2C2_SCL: 6
+  LPUART1_CTS: 1
+  SPI2_SCK: 0
+  TIM15_CH1N: 5
+  TIM1_CH1N: 2
+PB14:
+  EVENTOUT: 7
+  I2C2_SDA: 6
+  SPI2_MISO: 0
+  TIM15_CH1: 5
+  TIM1_CH2N: 2
+PB15:
+  EVENTOUT: 7
+  SPI2_MOSI: 0
+  TIM15_CH1N: 4
+  TIM15_CH2: 5
+  TIM1_CH3N: 2
+PB2:
+  EVENTOUT: 7
+  LPTIM1_OUT: 5
+  SPI2_MISO: 1
+PB3:
+  EVENTOUT: 7
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM1_CH2: 1
+  TIM2_CH2: 2
+  USART1_CK: 4
+  USART1_DE: 4
+  USART1_RTS: 4
+PB4:
+  EVENTOUT: 7
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM17_BK: 5
+  TIM3_CH1: 1
+  USART1_CTS: 4
+  USART1_NSS: 4
+PB5:
+  COMP2_OUT: 7
+  I2C1_SMBA: 6
+  I2S1_SD: 0
+  LPTIM1_IN1: 5
+  SPI1_MOSI: 0
+  TIM16_BK: 2
+  TIM3_CH2: 1
+PB6:
+  EVENTOUT: 7
+  I2C1_SCL: 6
+  LPTIM1_ETR: 5
+  SPI2_MISO: 4
+  TIM16_CH1N: 2
+  TIM1_CH3: 1
+  USART1_TX: 0
+PB7:
+  EVENTOUT: 7
+  I2C1_SDA: 6
+  LPTIM1_IN2: 5
+  SPI2_MOSI: 1
+  TIM17_CH1N: 2
+  USART1_RX: 0
+PB8:
+  EVENTOUT: 7
+  I2C1_SCL: 6
+  SPI2_SCK: 1
+  TIM15_BK: 5
+  TIM16_CH1: 2
+PB9:
+  EVENTOUT: 7
+  I2C1_SDA: 6
+  IR_OUT: 0
+  SPI2_NSS: 5
+  TIM17_CH1: 2
+PC13:
+  TIM1_BK: 2
+PC14:
+  TIM1_BK2: 2
+PC15:
+  RCC_OSC32_EN: 0
+  RCC_OSC_EN: 1
+  TIM15_BK: 2
+PC6:
+  TIM2_CH3: 2
+  TIM3_CH1: 1
+PC7:
+  TIM2_CH4: 2
+  TIM3_CH2: 1
+PD0:
+  EVENTOUT: 0
+  SPI2_NSS: 1
+  TIM16_CH1: 2
+PD1:
+  EVENTOUT: 0
+  SPI2_SCK: 1
+  TIM17_CH1: 2
+PD2:
+  TIM1_CH1N: 2
+  TIM3_ETR: 1
+PD3:
+  SPI2_MISO: 1
+  TIM1_CH2N: 2
+  USART2_CTS: 0
+  USART2_NSS: 0
+PF0:
+  TIM14_CH1: 2
+PF1:
+  RCC_OSC_EN: 0
+  TIM15_CH1N: 2
+PF2:
+  RCC_MCO: 0
+PI8: {}

data/gpio_af/STM32G07x.yaml

@@ -0,0 +1,415 @@
+PA0:
+  COMP1_OUT: 7
+  LPTIM1_OUT: 5
+  SPI2_SCK: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  UCPD2_FRSTX: 6
+  USART2_CTS: 1
+  USART2_NSS: 1
+  USART4_TX: 4
+PA1:
+  EVENTOUT: 7
+  I2C1_SMBA: 6
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM15_CH1N: 5
+  TIM2_CH2: 2
+  UCPD1_TXGND: 3
+  USART2_CK: 1
+  USART2_DE: 1
+  USART2_RTS: 1
+  USART4_RX: 4
+PA10:
+  EVENTOUT: 7
+  I2C1_SDA: 6
+  SPI2_MOSI: 0
+  TIM17_BK: 5
+  TIM1_CH3: 2
+  UCPD2_TXGND: 3
+  USART1_RX: 1
+PA11:
+  COMP1_OUT: 7
+  I2C2_SCL: 6
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM1_BK2: 5
+  TIM1_CH4: 2
+  USART1_CTS: 1
+  USART1_NSS: 1
+PA12:
+  COMP2_OUT: 7
+  I2C2_SDA: 6
+  I2S1_SD: 0
+  I2S_CKIN: 5
+  SPI1_MOSI: 0
+  TIM1_ETR: 2
+  USART1_CK: 1
+  USART1_DE: 1
+  USART1_RTS: 1
+PA13:
+  EVENTOUT: 7
+  IR_OUT: 1
+  SYS_SWDIO: 0
+PA14:
+  EVENTOUT: 7
+  SYS_SWCLK: 0
+  USART2_TX: 1
+PA15:
+  EVENTOUT: 7
+  I2S1_WS: 0
+  SPI1_NSS: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART2_RX: 1
+  USART3_CK: 5
+  USART3_DE: 5
+  USART3_RTS: 5
+  USART4_CK: 4
+  USART4_DE: 4
+  USART4_RTS: 4
+PA2:
+  COMP2_OUT: 7
+  I2S1_SD: 0
+  LPUART1_TX: 6
+  SPI1_MOSI: 0
+  TIM15_CH1: 5
+  TIM2_CH3: 2
+  UCPD1_FRSTX: 4
+  USART2_TX: 1
+PA3:
+  EVENTOUT: 7
+  LPUART1_RX: 6
+  SPI2_MISO: 0
+  TIM15_CH2: 5
+  TIM2_CH4: 2
+  UCPD2_FRSTX: 4
+  UCPD2_TXGND: 3
+  USART2_RX: 1
+PA4:
+  EVENTOUT: 7
+  I2S1_WS: 0
+  LPTIM2_OUT: 5
+  SPI1_NSS: 0
+  SPI2_MOSI: 1
+  TIM14_CH1: 4
+  UCPD2_FRSTX: 6
+PA5:
+  CEC: 1
+  EVENTOUT: 7
+  I2S1_CK: 0
+  LPTIM2_ETR: 5
+  SPI1_SCK: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  UCPD1_FRSTX: 6
+  UCPD1_TXDATA: 3
+  USART3_TX: 4
+PA6:
+  COMP1_OUT: 7
+  I2S1_MCK: 0
+  LPUART1_CTS: 6
+  SPI1_MISO: 0
+  TIM16_CH1: 5
+  TIM1_BK: 2
+  TIM3_CH1: 1
+  UCPD1_TXDATA: 3
+  USART3_CTS: 4
+  USART3_NSS: 4
+PA7:
+  COMP2_OUT: 7
+  I2S1_SD: 0
+  SPI1_MOSI: 0
+  TIM14_CH1: 4
+  TIM17_CH1: 5
+  TIM1_CH1N: 2
+  TIM3_CH2: 1
+  UCPD1_FRSTX: 6
+  UCPD2_TXDATA: 3
+PA8:
+  EVENTOUT: 7
+  LPTIM2_OUT: 5
+  RCC_MCO: 0
+  SPI2_NSS: 1
+  TIM1_CH1: 2
+  UCPD2_TXDATA: 3
+PA9:
+  EVENTOUT: 7
+  I2C1_SCL: 6
+  RCC_MCO: 0
+  SPI2_MISO: 4
+  TIM15_BK: 5
+  TIM1_CH2: 2
+  UCPD1_TXGND: 3
+  USART1_TX: 1
+PB0:
+  COMP1_OUT: 7
+  I2S1_WS: 0
+  LPTIM1_OUT: 5
+  SPI1_NSS: 0
+  TIM1_CH2N: 2
+  TIM3_CH3: 1
+  UCPD1_FRSTX: 6
+  USART3_RX: 4
+PB1:
+  EVENTOUT: 7
+  LPTIM2_IN1: 5
+  LPUART1_DE: 6
+  LPUART1_RTS: 6
+  TIM14_CH1: 0
+  TIM1_CH3N: 2
+  TIM3_CH4: 1
+  USART3_CK: 4
+  USART3_DE: 4
+  USART3_RTS: 4
+PB10:
+  CEC: 0
+  COMP1_OUT: 7
+  I2C2_SCL: 6
+  LPUART1_RX: 1
+  SPI2_SCK: 5
+  TIM2_CH3: 2
+  UCPD1_TXGND: 3
+  USART3_TX: 4
+PB11:
+  COMP2_OUT: 7
+  I2C2_SDA: 6
+  LPUART1_TX: 1
+  SPI2_MOSI: 0
+  TIM2_CH4: 2
+  UCPD1_TXGND: 3
+  USART3_RX: 4
+PB12:
+  EVENTOUT: 7
+  LPUART1_DE: 1
+  LPUART1_RTS: 1
+  SPI2_NSS: 0
+  TIM15_BK: 5
+  TIM1_BK: 2
+  UCPD2_FRSTX: 6
+PB13:
+  EVENTOUT: 7
+  I2C2_SCL: 6
+  LPUART1_CTS: 1
+  SPI2_SCK: 0
+  TIM15_CH1N: 5
+  TIM1_CH1N: 2
+  UCPD2_TXGND: 3
+  USART3_CTS: 4
+  USART3_NSS: 4
+PB14:
+  EVENTOUT: 7
+  I2C2_SDA: 6
+  SPI2_MISO: 0
+  TIM15_CH1: 5
+  TIM1_CH2N: 2
+  UCPD1_FRSTX: 1
+  UCPD2_TXGND: 3
+  USART3_CK: 4
+  USART3_DE: 4
+  USART3_RTS: 4
+PB15:
+  EVENTOUT: 7
+  SPI2_MOSI: 0
+  TIM15_CH1N: 4
+  TIM15_CH2: 5
+  TIM1_CH3N: 2
+PB2:
+  EVENTOUT: 7
+  LPTIM1_OUT: 5
+  SPI2_MISO: 1
+  UCPD1_TXGND: 3
+  USART3_TX: 4
+PB3:
+  EVENTOUT: 7
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM1_CH2: 1
+  TIM2_CH2: 2
+  USART1_CK: 4
+  USART1_DE: 4
+  USART1_RTS: 4
+PB4:
+  EVENTOUT: 7
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM17_BK: 5
+  TIM3_CH1: 1
+  UCPD2_TXGND: 3
+  USART1_CTS: 4
+  USART1_NSS: 4
+PB5:
+  COMP2_OUT: 7
+  I2C1_SMBA: 6
+  I2S1_SD: 0
+  LPTIM1_IN1: 5
+  SPI1_MOSI: 0
+  TIM16_BK: 2
+  TIM3_CH2: 1
+PB6:
+  EVENTOUT: 7
+  I2C1_SCL: 6
+  LPTIM1_ETR: 5
+  SPI2_MISO: 4
+  TIM16_CH1N: 2
+  TIM1_CH3: 1
+  UCPD1_TXGND: 3
+  USART1_TX: 0
+PB7:
+  EVENTOUT: 7
+  I2C1_SDA: 6
+  LPTIM1_IN2: 5
+  SPI2_MOSI: 1
+  TIM17_CH1N: 2
+  USART1_RX: 0
+  USART4_CTS: 4
+  USART4_NSS: 4
+PB8:
+  CEC: 0
+  EVENTOUT: 7
+  I2C1_SCL: 6
+  SPI2_SCK: 1
+  TIM15_BK: 5
+  TIM16_CH1: 2
+  UCPD1_TXGND: 3
+  USART3_TX: 4
+PB9:
+  EVENTOUT: 7
+  I2C1_SDA: 6
+  IR_OUT: 0
+  SPI2_NSS: 5
+  TIM17_CH1: 2
+  UCPD2_FRSTX: 1
+  UCPD2_TXGND: 3
+  USART3_RX: 4
+PC0:
+  LPTIM1_IN1: 0
+  LPTIM2_IN1: 2
+  LPUART1_RX: 1
+  UCPD1_TXGND: 3
+PC1:
+  LPTIM1_OUT: 0
+  LPUART1_TX: 1
+  TIM15_CH1: 2
+  UCPD1_TXGND: 3
+PC10:
+  TIM1_CH3: 2
+  UCPD2_TXDATA: 3
+  USART3_TX: 0
+  USART4_TX: 1
+PC11:
+  TIM1_CH4: 2
+  UCPD2_TXDATA: 3
+  USART3_RX: 0
+  USART4_RX: 1
+PC12:
+  LPTIM1_IN1: 0
+  TIM14_CH1: 2
+  UCPD1_FRSTX: 1
+PC13:
+  TIM1_BK: 2
+PC14:
+  TIM1_BK2: 2
+PC15:
+  RCC_OSC32_EN: 0
+  RCC_OSC_EN: 1
+  TIM15_BK: 2
+PC2:
+  LPTIM1_IN2: 0
+  SPI2_MISO: 1
+  TIM15_CH2: 2
+  UCPD2_TXGND: 3
+PC3:
+  LPTIM1_ETR: 0
+  LPTIM2_ETR: 2
+  SPI2_MOSI: 1
+  UCPD2_TXGND: 3
+PC4:
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART1_TX: 1
+  USART3_TX: 0
+PC5:
+  TIM2_CH2: 2
+  UCPD2_TXGND: 3
+  USART1_RX: 1
+  USART3_RX: 0
+PC6:
+  TIM2_CH3: 2
+  TIM3_CH1: 1
+  UCPD1_FRSTX: 0
+  UCPD1_TXDATA: 3
+PC7:
+  TIM2_CH4: 2
+  TIM3_CH2: 1
+  UCPD2_FRSTX: 0
+  UCPD2_TXDATA: 3
+PC8:
+  TIM1_CH1: 2
+  TIM3_CH3: 1
+  UCPD1_TXDATA: 3
+  UCPD2_FRSTX: 0
+PC9:
+  I2S_CKIN: 0
+  TIM1_CH2: 2
+  TIM3_CH4: 1
+  UCPD1_TXDATA: 3
+PD0:
+  EVENTOUT: 0
+  SPI2_NSS: 1
+  TIM16_CH1: 2
+  UCPD1_TXDATA: 3
+PD1:
+  EVENTOUT: 0
+  SPI2_SCK: 1
+  TIM17_CH1: 2
+  UCPD1_TXDATA: 3
+PD2:
+  TIM1_CH1N: 2
+  TIM3_ETR: 1
+  UCPD2_TXDATA: 3
+  USART3_CK: 0
+  USART3_DE: 0
+  USART3_RTS: 0
+PD3:
+  SPI2_MISO: 1
+  TIM1_CH2N: 2
+  UCPD2_TXDATA: 3
+  USART2_CTS: 0
+  USART2_NSS: 0
+PD4:
+  SPI2_MOSI: 1
+  TIM1_CH3N: 2
+  USART2_CK: 0
+  USART2_DE: 0
+  USART2_RTS: 0
+PD5:
+  I2S1_MCK: 1
+  SPI1_MISO: 1
+  TIM1_BK: 2
+  USART2_TX: 0
+PD6:
+  I2S1_SD: 1
+  LPTIM2_OUT: 2
+  SPI1_MOSI: 1
+  USART2_RX: 0
+PD8:
+  I2S1_CK: 1
+  LPTIM1_OUT: 2
+  SPI1_SCK: 1
+  UCPD1_TXDATA: 3
+  USART3_TX: 0
+PD9:
+  I2S1_WS: 1
+  SPI1_NSS: 1
+  TIM1_BK2: 2
+  UCPD2_TXDATA: 3
+  USART3_RX: 0
+PF0:
+  TIM14_CH1: 2
+PF1:
+  RCC_OSC_EN: 0
+  TIM15_CH1N: 2
+PF2:
+  RCC_MCO: 0
+PI8: {}

data/gpio_af/STM32G0Bx.yaml

@@ -0,0 +1,635 @@
+PA0:
+  COMP1_OUT: 7
+  I2S2_CK: 0
+  LPTIM1_OUT: 5
+  SPI2_SCK: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  UCPD2_FRSTX1: 6
+  UCPD2_FRSTX2: 6
+  USART2_CTS: 1
+  USART2_NSS: 1
+  USART4_TX: 4
+PA1:
+  EVENTOUT: 7
+  I2C1_SMBA: 6
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM15_CH1N: 5
+  TIM2_CH2: 2
+  USART2_CK: 1
+  USART2_DE: 1
+  USART2_RTS: 1
+  USART4_RX: 4
+PA10:
+  EVENTOUT: 7
+  I2C1_SDA: 6
+  I2C2_SDA: 8
+  I2S2_SD: 0
+  RCC_MCO_2: 3
+  SPI2_MOSI: 0
+  TIM17_BK: 5
+  TIM1_CH3: 2
+  USART1_RX: 1
+PA11:
+  COMP1_OUT: 7
+  FDCAN1_RX: 3
+  I2C2_SCL: 6
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM1_BK2: 5
+  TIM1_CH4: 2
+  USART1_CTS: 1
+  USART1_NSS: 1
+PA12:
+  COMP2_OUT: 7
+  FDCAN1_TX: 3
+  I2C2_SDA: 6
+  I2S1_SD: 0
+  I2S_CKIN: 5
+  SPI1_MOSI: 0
+  TIM1_ETR: 2
+  USART1_CK: 1
+  USART1_DE: 1
+  USART1_RTS: 1
+PA13:
+  EVENTOUT: 7
+  IR_OUT: 1
+  LPUART2_RX: 10
+  SYS_SWDIO: 0
+  USB_NOE: 2
+PA14:
+  EVENTOUT: 7
+  LPUART2_TX: 10
+  SYS_SWCLK: 0
+  USART2_TX: 1
+PA15:
+  EVENTOUT: 7
+  I2C2_SMBA: 8
+  I2S1_WS: 0
+  RCC_MCO_2: 3
+  SPI1_NSS: 0
+  SPI3_NSS: 9
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART2_RX: 1
+  USART3_CK: 5
+  USART3_DE: 5
+  USART3_RTS: 5
+  USART4_CK: 4
+  USART4_DE: 4
+  USART4_RTS: 4
+  USB_NOE: 6
+PA2:
+  COMP2_OUT: 7
+  I2S1_SD: 0
+  LPUART1_TX: 6
+  SPI1_MOSI: 0
+  TIM15_CH1: 5
+  TIM2_CH3: 2
+  UCPD1_FRSTX1: 4
+  UCPD1_FRSTX2: 4
+  USART2_TX: 1
+PA3:
+  EVENTOUT: 7
+  I2S2_MCK: 0
+  LPUART1_RX: 6
+  SPI2_MISO: 0
+  TIM15_CH2: 5
+  TIM2_CH4: 2
+  UCPD2_FRSTX1: 4
+  UCPD2_FRSTX2: 4
+  USART2_RX: 1
+PA4:
+  EVENTOUT: 7
+  I2S1_WS: 0
+  I2S2_SD: 1
+  LPTIM2_OUT: 5
+  SPI1_NSS: 0
+  SPI2_MOSI: 1
+  SPI3_NSS: 9
+  TIM14_CH1: 4
+  UCPD2_FRSTX1: 6
+  UCPD2_FRSTX2: 6
+  USART6_TX: 3
+  USB_NOE: 2
+PA5:
+  CEC: 1
+  EVENTOUT: 7
+  I2S1_CK: 0
+  LPTIM2_ETR: 5
+  SPI1_SCK: 0
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  UCPD1_FRSTX1: 6
+  UCPD1_FRSTX2: 6
+  USART3_TX: 4
+  USART6_RX: 3
+PA6:
+  COMP1_OUT: 7
+  I2C2_SDA: 8
+  I2C3_SDA: 9
+  I2S1_MCK: 0
+  LPUART1_CTS: 6
+  SPI1_MISO: 0
+  TIM16_CH1: 5
+  TIM1_BK: 2
+  TIM3_CH1: 1
+  USART3_CTS: 4
+  USART3_NSS: 4
+  USART6_CTS: 3
+  USART6_NSS: 3
+PA7:
+  COMP2_OUT: 7
+  I2C2_SCL: 8
+  I2C3_SCL: 9
+  I2S1_SD: 0
+  SPI1_MOSI: 0
+  TIM14_CH1: 4
+  TIM17_CH1: 5
+  TIM1_CH1N: 2
+  TIM3_CH2: 1
+  UCPD1_FRSTX1: 6
+  UCPD1_FRSTX2: 6
+  USART6_CK: 3
+  USART6_DE: 3
+  USART6_RTS: 3
+PA8:
+  CRS1_SYNC: 4
+  EVENTOUT: 7
+  I2C2_SMBA: 8
+  I2S2_WS: 1
+  LPTIM2_OUT: 5
+  RCC_MCO: 0
+  SPI2_NSS: 1
+  TIM1_CH1: 2
+PA9:
+  EVENTOUT: 7
+  I2C1_SCL: 6
+  I2C2_SCL: 8
+  I2S2_MCK: 4
+  RCC_MCO: 0
+  SPI2_MISO: 4
+  TIM15_BK: 5
+  TIM1_CH2: 2
+  USART1_TX: 1
+PB0:
+  COMP1_OUT: 7
+  FDCAN2_RX: 3
+  I2S1_WS: 0
+  LPTIM1_OUT: 5
+  LPUART2_CTS: 10
+  SPI1_NSS: 0
+  TIM1_CH2N: 2
+  TIM3_CH3: 1
+  UCPD1_FRSTX1: 6
+  UCPD1_FRSTX2: 6
+  USART3_RX: 4
+  USART5_TX: 8
+PB1:
+  COMP3_OUT: 7
+  FDCAN2_TX: 3
+  LPTIM2_IN1: 5
+  LPUART1_DE: 6
+  LPUART1_RTS: 6
+  LPUART2_DE: 10
+  LPUART2_RTS: 10
+  TIM14_CH1: 0
+  TIM1_CH3N: 2
+  TIM3_CH4: 1
+  USART3_CK: 4
+  USART3_DE: 4
+  USART3_RTS: 4
+  USART5_RX: 8
+PB10:
+  CEC: 0
+  COMP1_OUT: 7
+  I2C2_SCL: 6
+  I2S2_CK: 5
+  LPUART1_RX: 1
+  SPI2_SCK: 5
+  TIM2_CH3: 2
+  USART3_TX: 4
+PB11:
+  COMP2_OUT: 7
+  I2C2_SDA: 6
+  I2S2_SD: 0
+  LPUART1_TX: 1
+  SPI2_MOSI: 0
+  TIM2_CH4: 2
+  USART3_RX: 4
+PB12:
+  EVENTOUT: 7
+  FDCAN2_RX: 3
+  I2C2_SMBA: 8
+  I2S2_WS: 0
+  LPUART1_DE: 1
+  LPUART1_RTS: 1
+  SPI2_NSS: 0
+  TIM15_BK: 5
+  TIM1_BK: 2
+  UCPD2_FRSTX1: 6
+  UCPD2_FRSTX2: 6
+PB13:
+  EVENTOUT: 7
+  FDCAN2_TX: 3
+  I2C2_SCL: 6
+  I2S2_CK: 0
+  LPUART1_CTS: 1
+  SPI2_SCK: 0
+  TIM15_CH1N: 5
+  TIM1_CH1N: 2
+  USART3_CTS: 4
+  USART3_NSS: 4
+PB14:
+  EVENTOUT: 7
+  I2C2_SDA: 6
+  I2S2_MCK: 0
+  SPI2_MISO: 0
+  TIM15_CH1: 5
+  TIM1_CH2N: 2
+  UCPD1_FRSTX1: 1
+  UCPD1_FRSTX2: 1
+  USART3_CK: 4
+  USART3_DE: 4
+  USART3_RTS: 4
+  USART6_CK: 8
+  USART6_DE: 8
+  USART6_RTS: 8
+PB15:
+  EVENTOUT: 7
+  I2S2_SD: 0
+  SPI2_MOSI: 0
+  TIM15_CH1N: 4
+  TIM15_CH2: 5
+  TIM1_CH3N: 2
+  USART6_CTS: 8
+  USART6_NSS: 8
+PB2:
+  EVENTOUT: 7
+  I2S2_MCK: 1
+  LPTIM1_OUT: 5
+  RCC_MCO_2: 3
+  SPI2_MISO: 1
+  USART3_TX: 4
+PB3:
+  EVENTOUT: 7
+  I2C2_SCL: 8
+  I2C3_SCL: 6
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  SPI3_SCK: 9
+  TIM1_CH2: 1
+  TIM2_CH2: 2
+  USART1_CK: 4
+  USART1_DE: 4
+  USART1_RTS: 4
+  USART5_TX: 3
+PB4:
+  EVENTOUT: 7
+  I2C2_SDA: 8
+  I2C3_SDA: 6
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  SPI3_MISO: 9
+  TIM17_BK: 5
+  TIM3_CH1: 1
+  USART1_CTS: 4
+  USART1_NSS: 4
+  USART5_RX: 3
+PB5:
+  COMP2_OUT: 7
+  FDCAN2_RX: 3
+  I2C1_SMBA: 6
+  I2S1_SD: 0
+  LPTIM1_IN1: 5
+  SPI1_MOSI: 0
+  SPI3_MOSI: 9
+  TIM16_BK: 2
+  TIM3_CH2: 1
+  USART5_CK: 8
+  USART5_DE: 8
+  USART5_RTS: 8
+PB6:
+  EVENTOUT: 7
+  FDCAN2_TX: 3
+  I2C1_SCL: 6
+  I2S2_MCK: 4
+  LPTIM1_ETR: 5
+  LPUART2_TX: 10
+  SPI2_MISO: 4
+  TIM16_CH1N: 2
+  TIM1_CH3: 1
+  TIM4_CH1: 9
+  USART1_TX: 0
+  USART5_CTS: 8
+  USART5_NSS: 8
+PB7:
+  EVENTOUT: 7
+  I2C1_SDA: 6
+  I2S2_SD: 1
+  LPTIM1_IN2: 5
+  LPUART2_RX: 10
+  SPI2_MOSI: 1
+  TIM17_CH1N: 2
+  TIM4_CH2: 9
+  USART1_RX: 0
+  USART4_CTS: 4
+  USART4_NSS: 4
+PB8:
+  CEC: 0
+  EVENTOUT: 7
+  FDCAN1_RX: 3
+  I2C1_SCL: 6
+  I2S2_CK: 1
+  SPI2_SCK: 1
+  TIM15_BK: 5
+  TIM16_CH1: 2
+  TIM4_CH3: 9
+  USART3_TX: 4
+  USART6_TX: 8
+PB9:
+  EVENTOUT: 7
+  FDCAN1_TX: 3
+  I2C1_SDA: 6
+  I2S2_WS: 5
+  IR_OUT: 0
+  SPI2_NSS: 5
+  TIM17_CH1: 2
+  TIM4_CH4: 9
+  UCPD2_FRSTX1: 1
+  UCPD2_FRSTX2: 1
+  USART3_RX: 4
+  USART6_RX: 8
+PC0:
+  COMP3_OUT: 7
+  I2C3_SCL: 6
+  LPTIM1_IN1: 0
+  LPTIM2_IN1: 2
+  LPUART1_RX: 1
+  LPUART2_TX: 3
+  USART6_TX: 4
+PC1:
+  I2C3_SDA: 6
+  LPTIM1_OUT: 0
+  LPUART1_TX: 1
+  LPUART2_RX: 3
+  TIM15_CH1: 2
+  USART6_RX: 4
+PC10:
+  SPI3_SCK: 4
+  TIM1_CH3: 2
+  USART3_TX: 0
+  USART4_TX: 1
+PC11:
+  SPI3_MISO: 4
+  TIM1_CH4: 2
+  USART3_RX: 0
+  USART4_RX: 1
+PC12:
+  LPTIM1_IN1: 0
+  SPI3_MOSI: 4
+  TIM14_CH1: 2
+  UCPD1_FRSTX1: 1
+  UCPD1_FRSTX2: 1
+  USART5_TX: 3
+PC13:
+  TIM1_BK: 2
+PC14:
+  TIM1_BK2: 2
+PC15:
+  RCC_OSC32_EN: 0
+  RCC_OSC_EN: 1
+  TIM15_BK: 2
+PC2:
+  COMP3_OUT: 7
+  FDCAN2_RX: 3
+  I2S2_MCK: 1
+  LPTIM1_IN2: 0
+  SPI2_MISO: 1
+  TIM15_CH2: 2
+PC3:
+  FDCAN2_TX: 3
+  I2S2_SD: 1
+  LPTIM1_ETR: 0
+  LPTIM2_ETR: 2
+  SPI2_MOSI: 1
+PC4:
+  FDCAN1_RX: 3
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART1_TX: 1
+  USART3_TX: 0
+PC5:
+  FDCAN1_TX: 3
+  TIM2_CH2: 2
+  USART1_RX: 1
+  USART3_RX: 0
+PC6:
+  LPUART2_TX: 3
+  TIM2_CH3: 2
+  TIM3_CH1: 1
+  UCPD1_FRSTX1: 0
+  UCPD1_FRSTX2: 0
+PC7:
+  LPUART2_RX: 3
+  TIM2_CH4: 2
+  TIM3_CH2: 1
+  UCPD2_FRSTX1: 0
+  UCPD2_FRSTX2: 0
+PC8:
+  LPUART2_CTS: 3
+  TIM1_CH1: 2
+  TIM3_CH3: 1
+  UCPD2_FRSTX1: 0
+  UCPD2_FRSTX2: 0
+PC9:
+  I2S_CKIN: 0
+  LPUART2_DE: 3
+  LPUART2_RTS: 3
+  TIM1_CH2: 2
+  TIM3_CH4: 1
+  USB_NOE: 6
+PD0:
+  EVENTOUT: 0
+  FDCAN1_RX: 3
+  I2S2_WS: 1
+  SPI2_NSS: 1
+  TIM16_CH1: 2
+PD1:
+  EVENTOUT: 0
+  FDCAN1_TX: 3
+  I2S2_CK: 1
+  SPI2_SCK: 1
+  TIM17_CH1: 2
+PD10:
+  RCC_MCO: 0
+PD11:
+  LPTIM2_ETR: 1
+  USART3_CTS: 0
+  USART3_NSS: 0
+PD12:
+  FDCAN1_RX: 3
+  LPTIM2_IN1: 1
+  TIM4_CH1: 2
+  USART3_CK: 0
+  USART3_DE: 0
+  USART3_RTS: 0
+PD13:
+  FDCAN1_TX: 3
+  LPTIM2_OUT: 1
+  TIM4_CH2: 2
+PD14:
+  FDCAN2_RX: 3
+  LPUART2_CTS: 1
+  TIM4_CH3: 2
+PD15:
+  CRS1_SYNC: 0
+  FDCAN2_TX: 3
+  LPUART2_DE: 1
+  LPUART2_RTS: 1
+  TIM4_CH4: 2
+PD2:
+  TIM1_CH1N: 2
+  TIM3_ETR: 1
+  USART3_CK: 0
+  USART3_DE: 0
+  USART3_RTS: 0
+  USART5_RX: 3
+PD3:
+  I2S2_MCK: 1
+  SPI2_MISO: 1
+  TIM1_CH2N: 2
+  USART2_CTS: 0
+  USART2_NSS: 0
+  USART5_TX: 3
+PD4:
+  I2S2_SD: 1
+  SPI2_MOSI: 1
+  TIM1_CH3N: 2
+  USART2_CK: 0
+  USART2_DE: 0
+  USART2_RTS: 0
+  USART5_CK: 3
+  USART5_DE: 3
+  USART5_RTS: 3
+PD5:
+  I2S1_MCK: 1
+  SPI1_MISO: 1
+  TIM1_BK: 2
+  USART2_TX: 0
+  USART5_CTS: 3
+  USART5_NSS: 3
+PD6:
+  I2S1_SD: 1
+  LPTIM2_OUT: 2
+  SPI1_MOSI: 1
+  USART2_RX: 0
+PD7:
+  RCC_MCO_2: 3
+PD8:
+  I2S1_CK: 1
+  LPTIM1_OUT: 2
+  SPI1_SCK: 1
+  USART3_TX: 0
+PD9:
+  I2S1_WS: 1
+  SPI1_NSS: 1
+  TIM1_BK2: 2
+  USART3_RX: 0
+PE0:
+  EVENTOUT: 1
+  TIM16_CH1: 0
+  TIM4_ETR: 2
+PE1:
+  EVENTOUT: 1
+  TIM17_CH1: 0
+PE10:
+  TIM1_CH2N: 1
+  USART5_TX: 3
+PE11:
+  TIM1_CH2: 1
+  USART5_RX: 3
+PE12:
+  I2S1_WS: 0
+  SPI1_NSS: 0
+  TIM1_CH3N: 1
+PE13:
+  I2S1_CK: 0
+  SPI1_SCK: 0
+  TIM1_CH3: 1
+PE14:
+  I2S1_MCK: 0
+  SPI1_MISO: 0
+  TIM1_BK2: 2
+  TIM1_CH4: 1
+PE15:
+  I2S1_SD: 0
+  SPI1_MOSI: 0
+  TIM1_BK: 1
+PE2:
+  TIM3_ETR: 1
+PE3:
+  TIM3_CH1: 1
+PE4:
+  TIM3_CH2: 1
+PE5:
+  TIM3_CH3: 1
+PE6:
+  TIM3_CH4: 1
+PE7:
+  TIM1_ETR: 1
+  USART5_CK: 3
+  USART5_DE: 3
+  USART5_RTS: 3
+PE8:
+  TIM1_CH1N: 1
+  USART4_TX: 0
+PE9:
+  TIM1_CH1: 1
+  USART4_RX: 0
+PF0:
+  CRS1_SYNC: 0
+  EVENTOUT: 1
+  TIM14_CH1: 2
+PF1:
+  EVENTOUT: 1
+  RCC_OSC_EN: 0
+  TIM15_CH1N: 2
+PF10:
+  USART6_RX: 3
+PF11:
+  USART6_CK: 3
+  USART6_DE: 3
+  USART6_RTS: 3
+PF12:
+  TIM15_CH1: 0
+  USART6_CTS: 3
+  USART6_NSS: 3
+PF13:
+  TIM15_CH2: 0
+PF2:
+  LPUART2_DE: 3
+  LPUART2_RTS: 3
+  LPUART2_TX: 1
+  RCC_MCO: 0
+PF3:
+  LPUART2_RX: 1
+  USART6_CK: 3
+  USART6_DE: 3
+  USART6_RTS: 3
+PF4:
+  LPUART1_TX: 1
+PF5:
+  LPUART1_RX: 1
+PF6:
+  LPUART1_DE: 1
+  LPUART1_RTS: 1
+PF7:
+  LPUART1_CTS: 1
+  USART5_CTS: 3
+  USART5_NSS: 3
+PF8: {}
+PF9:
+  USART6_TX: 3
+PI8: {}

data/gpio_af/STM32G43x.yaml

@@ -0,0 +1,555 @@
+PA0:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  TIM2_CH1: 1
+  TIM2_ETR: 14
+  TIM8_BKIN: 9
+  TIM8_ETR: 10
+  USART2_CTS: 7
+  USART2_NSS: 7
+PA1:
+  EVENTOUT: 15
+  RTC_REFIN: 0
+  TIM15_CH1N: 9
+  TIM2_CH2: 1
+  USART2_DE: 7
+  USART2_RTS: 7
+PA10:
+  CRS_SYNC: 3
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+  SAI1_D1: 12
+  SAI1_SD_A: 14
+  SPI2_MISO: 5
+  TIM17_BKIN: 1
+  TIM1_CH3: 6
+  TIM2_CH4: 10
+  TIM8_BKIN: 11
+  USART1_RX: 7
+PA11:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  FDCAN1_RX: 9
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIM1_BKIN2: 12
+  TIM1_CH1N: 6
+  TIM1_CH4: 11
+  TIM4_CH1: 10
+  USART1_CTS: 7
+  USART1_NSS: 7
+PA12:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  FDCAN1_TX: 9
+  I2S_CKIN: 5
+  TIM16_CH1: 1
+  TIM1_CH2N: 6
+  TIM1_ETR: 11
+  TIM4_CH2: 10
+  USART1_DE: 7
+  USART1_RTS: 7
+PA13:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  IR_OUT: 5
+  SAI1_SD_B: 13
+  SYS_JTMS-SWDIO: 0
+  TIM16_CH1N: 1
+  TIM4_CH3: 10
+  USART3_CTS: 7
+  USART3_NSS: 7
+PA14:
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  LPTIM1_OUT: 1
+  SAI1_FS_B: 13
+  SYS_JTCK-SWCLK: 0
+  TIM1_BKIN: 6
+  TIM8_CH2: 5
+  USART2_TX: 7
+PA15:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM1_BKIN: 9
+  TIM2_CH1: 1
+  TIM2_ETR: 14
+  TIM8_CH1: 2
+  UART4_DE: 8
+  UART4_RTS: 8
+  USART2_RX: 7
+PA2:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  LPUART1_TX: 12
+  TIM15_CH1: 9
+  TIM2_CH3: 1
+  UCPD1_FRSTX1: 14
+  UCPD1_FRSTX2: 14
+  USART2_TX: 7
+PA3:
+  EVENTOUT: 15
+  LPUART1_RX: 12
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 13
+  TIM15_CH2: 9
+  TIM2_CH4: 1
+  USART2_RX: 7
+PA4:
+  EVENTOUT: 15
+  I2S3_WS: 6
+  SAI1_FS_B: 13
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  TIM3_CH2: 2
+  USART2_CK: 7
+PA5:
+  EVENTOUT: 15
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+  UCPD1_FRSTX1: 14
+  UCPD1_FRSTX2: 14
+PA6:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  LPUART1_CTS: 12
+  SPI1_MISO: 5
+  TIM16_CH1: 1
+  TIM1_BKIN: 6
+  TIM3_CH1: 2
+  TIM8_BKIN: 4
+PA7:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  SPI1_MOSI: 5
+  TIM17_CH1: 1
+  TIM1_CH1N: 6
+  TIM3_CH2: 2
+  TIM8_CH1N: 4
+  UCPD1_FRSTX1: 14
+  UCPD1_FRSTX2: 14
+PA8:
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  I2C3_SCL: 2
+  I2S2_MCK: 5
+  RCC_MCO: 0
+  SAI1_CK2: 12
+  SAI1_SCK_A: 14
+  TIM1_CH1: 6
+  TIM4_ETR: 10
+  USART1_CK: 7
+PA9:
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  I2C3_SMBA: 2
+  I2S3_MCK: 5
+  SAI1_FS_A: 14
+  TIM15_BKIN: 9
+  TIM1_CH2: 6
+  TIM2_CH3: 10
+  USART1_TX: 7
+PB0:
+  EVENTOUT: 15
+  TIM1_CH2N: 6
+  TIM3_CH3: 2
+  TIM8_CH2N: 4
+  UCPD1_FRSTX1: 14
+  UCPD1_FRSTX2: 14
+PB1:
+  COMP4_OUT: 8
+  EVENTOUT: 15
+  LPUART1_DE: 12
+  LPUART1_RTS: 12
+  TIM1_CH3N: 6
+  TIM3_CH4: 2
+  TIM8_CH3N: 4
+PB10:
+  EVENTOUT: 15
+  LPUART1_RX: 8
+  SAI1_SCK_A: 14
+  TIM1_BKIN: 12
+  TIM2_CH3: 1
+  USART3_TX: 7
+PB11:
+  EVENTOUT: 15
+  LPUART1_TX: 8
+  TIM2_CH4: 1
+  USART3_RX: 7
+PB12:
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+  SPI2_NSS: 5
+  TIM1_BKIN: 6
+  USART3_CK: 7
+PB13:
+  EVENTOUT: 15
+  I2S2_CK: 5
+  LPUART1_CTS: 8
+  SPI2_SCK: 5
+  TIM1_CH1N: 6
+  USART3_CTS: 7
+  USART3_NSS: 7
+PB14:
+  COMP4_OUT: 8
+  EVENTOUT: 15
+  SPI2_MISO: 5
+  TIM15_CH1: 1
+  TIM1_CH2N: 6
+  USART3_DE: 7
+  USART3_RTS: 7
+PB15:
+  COMP3_OUT: 3
+  EVENTOUT: 15
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM15_CH1N: 2
+  TIM15_CH2: 1
+  TIM1_CH3N: 4
+PB2:
+  EVENTOUT: 15
+  I2C3_SMBA: 4
+  LPTIM1_OUT: 1
+  RTC_OUT2: 0
+PB3:
+  CRS_SYNC: 3
+  EVENTOUT: 15
+  I2S3_CK: 6
+  SAI1_SCK_B: 14
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+  TIM3_ETR: 10
+  TIM4_ETR: 2
+  TIM8_CH1N: 4
+  USART2_TX: 7
+PB4:
+  EVENTOUT: 15
+  SAI1_MCLK_B: 14
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM16_CH1: 1
+  TIM17_BKIN: 10
+  TIM3_CH1: 2
+  TIM8_CH2N: 4
+  USART2_RX: 7
+PB5:
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  I2C3_SDA: 8
+  I2S3_SD: 6
+  LPTIM1_IN1: 11
+  SAI1_SD_B: 12
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM16_BKIN: 1
+  TIM17_CH1: 10
+  TIM3_CH2: 2
+  TIM8_CH3N: 3
+  USART2_CK: 7
+PB6:
+  COMP4_OUT: 8
+  EVENTOUT: 15
+  LPTIM1_ETR: 11
+  SAI1_FS_B: 14
+  TIM16_CH1N: 1
+  TIM4_CH1: 2
+  TIM8_BKIN2: 10
+  TIM8_CH1: 5
+  TIM8_ETR: 6
+  USART1_TX: 7
+PB7:
+  COMP3_OUT: 8
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  LPTIM1_IN2: 11
+  TIM17_CH1N: 1
+  TIM3_CH4: 10
+  TIM4_CH2: 2
+  TIM8_BKIN: 5
+  UART4_CTS: 14
+  USART1_RX: 7
+PB8:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  FDCAN1_RX: 9
+  I2C1_SCL: 4
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 14
+  TIM16_CH1: 1
+  TIM1_BKIN: 12
+  TIM4_CH3: 2
+  TIM8_CH2: 10
+  USART3_RX: 7
+PB9:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  FDCAN1_TX: 9
+  I2C1_SDA: 4
+  IR_OUT: 6
+  SAI1_D2: 3
+  SAI1_FS_A: 14
+  TIM17_CH1: 1
+  TIM1_CH3N: 12
+  TIM4_CH4: 2
+  TIM8_CH3: 10
+  USART3_TX: 7
+PC0:
+  EVENTOUT: 15
+  LPTIM1_IN1: 1
+  LPUART1_RX: 8
+  TIM1_CH1: 2
+PC1:
+  EVENTOUT: 15
+  LPTIM1_OUT: 1
+  LPUART1_TX: 8
+  SAI1_SD_A: 13
+  TIM1_CH2: 2
+PC10:
+  EVENTOUT: 15
+  I2S3_CK: 6
+  SPI3_SCK: 6
+  TIM8_CH1N: 4
+  UART4_TX: 5
+  USART3_TX: 7
+PC11:
+  EVENTOUT: 15
+  I2C3_SDA: 8
+  SPI3_MISO: 6
+  TIM8_CH2N: 4
+  UART4_RX: 5
+  USART3_RX: 7
+PC12:
+  EVENTOUT: 15
+  I2S3_SD: 6
+  SPI3_MOSI: 6
+  TIM8_CH3N: 4
+  UCPD1_FRSTX1: 14
+  UCPD1_FRSTX2: 14
+  USART3_CK: 7
+PC13:
+  EVENTOUT: 15
+  TIM1_BKIN: 2
+  TIM1_CH1N: 4
+  TIM8_CH4N: 6
+PC14: {}
+PC15: {}
+PC2:
+  COMP3_OUT: 3
+  EVENTOUT: 15
+  LPTIM1_IN2: 1
+  TIM1_CH3: 2
+PC3:
+  EVENTOUT: 15
+  LPTIM1_ETR: 1
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  TIM1_BKIN2: 6
+  TIM1_CH4: 2
+PC4:
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  TIM1_ETR: 2
+  USART1_TX: 7
+PC5:
+  EVENTOUT: 15
+  SAI1_D3: 3
+  TIM15_BKIN: 2
+  TIM1_CH4N: 6
+  USART1_RX: 7
+PC6:
+  EVENTOUT: 15
+  I2S2_MCK: 6
+  TIM3_CH1: 2
+  TIM8_CH1: 4
+PC7:
+  EVENTOUT: 15
+  I2S3_MCK: 6
+  TIM3_CH2: 2
+  TIM8_CH2: 4
+PC8:
+  EVENTOUT: 15
+  I2C3_SCL: 8
+  TIM3_CH3: 2
+  TIM8_CH3: 4
+PC9:
+  EVENTOUT: 15
+  I2C3_SDA: 8
+  I2S_CKIN: 5
+  TIM3_CH4: 2
+  TIM8_BKIN2: 6
+  TIM8_CH4: 4
+PD0:
+  EVENTOUT: 15
+  FDCAN1_RX: 9
+  TIM8_CH4N: 6
+PD1:
+  EVENTOUT: 15
+  FDCAN1_TX: 9
+  TIM8_BKIN2: 6
+  TIM8_CH4: 4
+PD10:
+  EVENTOUT: 15
+  USART3_CK: 7
+PD11:
+  EVENTOUT: 15
+  USART3_CTS: 7
+  USART3_NSS: 7
+PD12:
+  EVENTOUT: 15
+  TIM4_CH1: 2
+  USART3_DE: 7
+  USART3_RTS: 7
+PD13:
+  EVENTOUT: 15
+  TIM4_CH2: 2
+PD14:
+  EVENTOUT: 15
+  TIM4_CH3: 2
+PD15:
+  EVENTOUT: 15
+  SPI2_NSS: 6
+  TIM4_CH4: 2
+PD2:
+  EVENTOUT: 15
+  TIM3_ETR: 2
+  TIM8_BKIN: 4
+PD3:
+  EVENTOUT: 15
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART2_CTS: 7
+  USART2_NSS: 7
+PD4:
+  EVENTOUT: 15
+  TIM2_CH2: 2
+  USART2_DE: 7
+  USART2_RTS: 7
+PD5:
+  EVENTOUT: 15
+  USART2_TX: 7
+PD6:
+  EVENTOUT: 15
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  TIM2_CH4: 2
+  USART2_RX: 7
+PD7:
+  EVENTOUT: 15
+  TIM2_CH3: 2
+  USART2_CK: 7
+PD8:
+  EVENTOUT: 15
+  USART3_TX: 7
+PD9:
+  EVENTOUT: 15
+  USART3_RX: 7
+PE0:
+  EVENTOUT: 15
+  TIM16_CH1: 4
+  TIM4_ETR: 2
+  USART1_TX: 7
+PE1:
+  EVENTOUT: 15
+  TIM17_CH1: 4
+  USART1_RX: 7
+PE10:
+  EVENTOUT: 15
+  SAI1_MCLK_B: 13
+  TIM1_CH2N: 2
+PE11:
+  EVENTOUT: 15
+  TIM1_CH2: 2
+PE12:
+  EVENTOUT: 15
+  TIM1_CH3N: 2
+PE13:
+  EVENTOUT: 15
+  TIM1_CH3: 2
+PE14:
+  EVENTOUT: 15
+  TIM1_BKIN2: 6
+  TIM1_CH4: 2
+PE15:
+  EVENTOUT: 15
+  TIM1_BKIN: 2
+  TIM1_CH4N: 6
+  USART3_RX: 7
+PE2:
+  EVENTOUT: 15
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 13
+  SYS_TRACECLK: 0
+  TIM3_CH1: 2
+PE3:
+  EVENTOUT: 15
+  SAI1_SD_B: 13
+  SYS_TRACED0: 0
+  TIM3_CH2: 2
+PE4:
+  EVENTOUT: 15
+  SAI1_D2: 3
+  SAI1_FS_A: 13
+  SYS_TRACED1: 0
+  TIM3_CH3: 2
+PE5:
+  EVENTOUT: 15
+  SAI1_CK2: 3
+  SAI1_SCK_A: 13
+  SYS_TRACED2: 0
+  TIM3_CH4: 2
+PE6:
+  EVENTOUT: 15
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  SYS_TRACED3: 0
+PE7:
+  EVENTOUT: 15
+  SAI1_SD_B: 13
+  TIM1_ETR: 2
+PE8:
+  EVENTOUT: 15
+  SAI1_SCK_B: 13
+  TIM1_CH1N: 2
+PE9:
+  EVENTOUT: 15
+  SAI1_FS_B: 13
+  TIM1_CH1: 2
+PF0:
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM1_CH3N: 6
+PF1:
+  EVENTOUT: 15
+  I2S2_CK: 5
+  SPI2_SCK: 5
+PF10:
+  EVENTOUT: 15
+  SAI1_D3: 13
+  SPI2_SCK: 5
+  TIM15_CH2: 3
+PF2:
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+PF9:
+  EVENTOUT: 15
+  SAI1_FS_B: 13
+  SPI2_SCK: 5
+  TIM15_CH1: 3
+PG10:
+  EVENTOUT: 15
+  RCC_MCO: 0
+PI8: {}

data/gpio_af/STM32G47x.yaml

@@ -0,0 +1,849 @@
+PA0:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  TIM2_CH1: 1
+  TIM2_ETR: 14
+  TIM5_CH1: 2
+  TIM8_BKIN: 9
+  TIM8_ETR: 10
+  USART2_CTS: 7
+  USART2_NSS: 7
+PA1:
+  EVENTOUT: 15
+  RTC_REFIN: 0
+  TIM15_CH1N: 9
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  USART2_DE: 7
+  USART2_RTS: 7
+PA10:
+  COMP6_OUT: 8
+  CRS_SYNC: 3
+  EVENTOUT: 15
+  HRTIM1_CHB1: 13
+  I2C2_SMBA: 4
+  SAI1_D1: 12
+  SAI1_SD_A: 14
+  SPI2_MISO: 5
+  TIM17_BKIN: 1
+  TIM1_CH3: 6
+  TIM2_CH4: 10
+  TIM8_BKIN: 11
+  USART1_RX: 7
+PA11:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  FDCAN1_RX: 9
+  HRTIM1_CHB2: 13
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIM1_BKIN2: 12
+  TIM1_CH1N: 6
+  TIM1_CH4: 11
+  TIM4_CH1: 10
+  USART1_CTS: 7
+  USART1_NSS: 7
+PA12:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  FDCAN1_TX: 9
+  HRTIM1_FLT1: 13
+  I2S_CKIN: 5
+  TIM16_CH1: 1
+  TIM1_CH2N: 6
+  TIM1_ETR: 11
+  TIM4_CH2: 10
+  USART1_DE: 7
+  USART1_RTS: 7
+PA13:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  I2C4_SCL: 3
+  IR_OUT: 5
+  SAI1_SD_B: 13
+  SYS_JTMS-SWDIO: 0
+  TIM16_CH1N: 1
+  TIM4_CH3: 10
+  USART3_CTS: 7
+  USART3_NSS: 7
+PA14:
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  I2C4_SMBA: 3
+  LPTIM1_OUT: 1
+  SAI1_FS_B: 13
+  SYS_JTCK-SWCLK: 0
+  TIM1_BKIN: 6
+  TIM8_CH2: 5
+  USART2_TX: 7
+PA15:
+  EVENTOUT: 15
+  FDCAN3_TX: 11
+  HRTIM1_FLT2: 13
+  I2C1_SCL: 4
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM1_BKIN: 9
+  TIM2_CH1: 1
+  TIM2_ETR: 14
+  TIM8_CH1: 2
+  UART4_DE: 8
+  UART4_RTS: 8
+  USART2_RX: 7
+PA2:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  LPUART1_TX: 12
+  QUADSPI1_BK1_NCS: 10
+  TIM15_CH1: 9
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  UCPD1_FRSTX1: 14
+  UCPD1_FRSTX2: 14
+  USART2_TX: 7
+PA3:
+  EVENTOUT: 15
+  LPUART1_RX: 12
+  QUADSPI1_CLK: 10
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 13
+  TIM15_CH2: 9
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  USART2_RX: 7
+PA4:
+  EVENTOUT: 15
+  I2S3_WS: 6
+  SAI1_FS_B: 13
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  TIM3_CH2: 2
+  USART2_CK: 7
+PA5:
+  EVENTOUT: 15
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+  UCPD1_FRSTX1: 14
+  UCPD1_FRSTX2: 14
+PA6:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  LPUART1_CTS: 12
+  QUADSPI1_BK1_IO3: 10
+  SPI1_MISO: 5
+  TIM16_CH1: 1
+  TIM1_BKIN: 6
+  TIM3_CH1: 2
+  TIM8_BKIN: 4
+PA7:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  QUADSPI1_BK1_IO2: 10
+  SPI1_MOSI: 5
+  TIM17_CH1: 1
+  TIM1_CH1N: 6
+  TIM3_CH2: 2
+  TIM8_CH1N: 4
+  UCPD1_FRSTX1: 14
+  UCPD1_FRSTX2: 14
+PA8:
+  COMP7_OUT: 8
+  EVENTOUT: 15
+  FDCAN3_RX: 11
+  HRTIM1_CHA1: 13
+  I2C2_SDA: 4
+  I2C3_SCL: 2
+  I2S2_MCK: 5
+  RCC_MCO: 0
+  SAI1_CK2: 12
+  SAI1_SCK_A: 14
+  TIM1_CH1: 6
+  TIM4_ETR: 10
+  USART1_CK: 7
+PA9:
+  COMP5_OUT: 8
+  EVENTOUT: 15
+  HRTIM1_CHA2: 13
+  I2C2_SCL: 4
+  I2C3_SMBA: 2
+  I2S3_MCK: 5
+  SAI1_FS_A: 14
+  TIM15_BKIN: 9
+  TIM1_CH2: 6
+  TIM2_CH3: 10
+  USART1_TX: 7
+PB0:
+  EVENTOUT: 15
+  HRTIM1_FLT5: 13
+  QUADSPI1_BK1_IO1: 10
+  TIM1_CH2N: 6
+  TIM3_CH3: 2
+  TIM8_CH2N: 4
+  UCPD1_FRSTX1: 14
+  UCPD1_FRSTX2: 14
+PB1:
+  COMP4_OUT: 8
+  EVENTOUT: 15
+  HRTIM1_SCOUT: 13
+  LPUART1_DE: 12
+  LPUART1_RTS: 12
+  QUADSPI1_BK1_IO0: 10
+  TIM1_CH3N: 6
+  TIM3_CH4: 2
+  TIM8_CH3N: 4
+PB10:
+  EVENTOUT: 15
+  HRTIM1_FLT3: 13
+  LPUART1_RX: 8
+  QUADSPI1_CLK: 10
+  SAI1_SCK_A: 14
+  TIM1_BKIN: 12
+  TIM2_CH3: 1
+  USART3_TX: 7
+PB11:
+  EVENTOUT: 15
+  HRTIM1_FLT4: 13
+  LPUART1_TX: 8
+  QUADSPI1_BK1_NCS: 10
+  TIM2_CH4: 1
+  USART3_RX: 7
+PB12:
+  EVENTOUT: 15
+  FDCAN2_RX: 9
+  HRTIM1_CHC1: 13
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+  SPI2_NSS: 5
+  TIM1_BKIN: 6
+  TIM5_ETR: 2
+  USART3_CK: 7
+PB13:
+  EVENTOUT: 15
+  FDCAN2_TX: 9
+  HRTIM1_CHC2: 13
+  I2S2_CK: 5
+  LPUART1_CTS: 8
+  SPI2_SCK: 5
+  TIM1_CH1N: 6
+  USART3_CTS: 7
+  USART3_NSS: 7
+PB14:
+  COMP4_OUT: 8
+  EVENTOUT: 15
+  HRTIM1_CHD1: 13
+  SPI2_MISO: 5
+  TIM15_CH1: 1
+  TIM1_CH2N: 6
+  USART3_DE: 7
+  USART3_RTS: 7
+PB15:
+  COMP3_OUT: 3
+  EVENTOUT: 15
+  HRTIM1_CHD2: 13
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM15_CH1N: 2
+  TIM15_CH2: 1
+  TIM1_CH3N: 4
+PB2:
+  EVENTOUT: 15
+  HRTIM1_SCIN: 13
+  I2C3_SMBA: 4
+  LPTIM1_OUT: 1
+  QUADSPI1_BK2_IO1: 10
+  RTC_OUT2: 0
+  TIM20_CH1: 3
+  TIM5_CH1: 2
+PB3:
+  CRS_SYNC: 3
+  EVENTOUT: 15
+  FDCAN3_RX: 11
+  HRTIM1_EEV9: 13
+  HRTIM1_SCOUT: 12
+  I2S3_CK: 6
+  SAI1_SCK_B: 14
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+  TIM3_ETR: 10
+  TIM4_ETR: 2
+  TIM8_CH1N: 4
+  USART2_TX: 7
+PB4:
+  EVENTOUT: 15
+  FDCAN3_TX: 11
+  HRTIM1_EEV7: 13
+  SAI1_MCLK_B: 14
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM16_CH1: 1
+  TIM17_BKIN: 10
+  TIM3_CH1: 2
+  TIM8_CH2N: 4
+  UART5_DE: 8
+  UART5_RTS: 8
+  USART2_RX: 7
+PB5:
+  EVENTOUT: 15
+  FDCAN2_RX: 9
+  HRTIM1_EEV6: 13
+  I2C1_SMBA: 4
+  I2C3_SDA: 8
+  I2S3_SD: 6
+  LPTIM1_IN1: 11
+  SAI1_SD_B: 12
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM16_BKIN: 1
+  TIM17_CH1: 10
+  TIM3_CH2: 2
+  TIM8_CH3N: 3
+  UART5_CTS: 14
+  USART2_CK: 7
+PB6:
+  COMP4_OUT: 8
+  EVENTOUT: 15
+  FDCAN2_TX: 9
+  HRTIM1_EEV4: 13
+  HRTIM1_SCIN: 12
+  LPTIM1_ETR: 11
+  SAI1_FS_B: 14
+  TIM16_CH1N: 1
+  TIM4_CH1: 2
+  TIM8_BKIN2: 10
+  TIM8_CH1: 5
+  TIM8_ETR: 6
+  USART1_TX: 7
+PB7:
+  COMP3_OUT: 8
+  EVENTOUT: 15
+  FMC_NL: 12
+  HRTIM1_EEV3: 13
+  I2C1_SDA: 4
+  I2C4_SDA: 3
+  LPTIM1_IN2: 11
+  TIM17_CH1N: 1
+  TIM3_CH4: 10
+  TIM4_CH2: 2
+  TIM8_BKIN: 5
+  UART4_CTS: 14
+  USART1_RX: 7
+PB8:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  FDCAN1_RX: 9
+  HRTIM1_EEV8: 13
+  I2C1_SCL: 4
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 14
+  TIM16_CH1: 1
+  TIM1_BKIN: 12
+  TIM4_CH3: 2
+  TIM8_CH2: 10
+  USART3_RX: 7
+PB9:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  FDCAN1_TX: 9
+  HRTIM1_EEV5: 13
+  I2C1_SDA: 4
+  IR_OUT: 6
+  SAI1_D2: 3
+  SAI1_FS_A: 14
+  TIM17_CH1: 1
+  TIM1_CH3N: 12
+  TIM4_CH4: 2
+  TIM8_CH3: 10
+  USART3_TX: 7
+PC0:
+  EVENTOUT: 15
+  LPTIM1_IN1: 1
+  LPUART1_RX: 8
+  TIM1_CH1: 2
+PC1:
+  EVENTOUT: 15
+  LPTIM1_OUT: 1
+  LPUART1_TX: 8
+  QUADSPI1_BK2_IO0: 10
+  SAI1_SD_A: 13
+  TIM1_CH2: 2
+PC10:
+  EVENTOUT: 15
+  HRTIM1_FLT6: 13
+  I2S3_CK: 6
+  SPI3_SCK: 6
+  TIM8_CH1N: 4
+  UART4_TX: 5
+  USART3_TX: 7
+PC11:
+  EVENTOUT: 15
+  HRTIM1_EEV2: 3
+  I2C3_SDA: 8
+  SPI3_MISO: 6
+  TIM8_CH2N: 4
+  UART4_RX: 5
+  USART3_RX: 7
+PC12:
+  EVENTOUT: 15
+  HRTIM1_EEV1: 3
+  I2S3_SD: 6
+  SPI3_MOSI: 6
+  TIM5_CH2: 1
+  TIM8_CH3N: 4
+  UART5_TX: 5
+  UCPD1_FRSTX1: 14
+  UCPD1_FRSTX2: 14
+  USART3_CK: 7
+PC13:
+  EVENTOUT: 15
+  TIM1_BKIN: 2
+  TIM1_CH1N: 4
+  TIM8_CH4N: 6
+PC14:
+  EVENTOUT: 15
+PC15:
+  EVENTOUT: 15
+PC2:
+  COMP3_OUT: 3
+  EVENTOUT: 15
+  LPTIM1_IN2: 1
+  QUADSPI1_BK2_IO1: 10
+  TIM1_CH3: 2
+  TIM20_CH2: 6
+PC3:
+  EVENTOUT: 15
+  LPTIM1_ETR: 1
+  QUADSPI1_BK2_IO2: 10
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  SYS_SLEEP: 0
+  TIM1_BKIN2: 6
+  TIM1_CH4: 2
+PC4:
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  QUADSPI1_BK2_IO3: 10
+  TIM1_ETR: 2
+  USART1_TX: 7
+PC5:
+  EVENTOUT: 15
+  HRTIM1_EEV10: 13
+  SAI1_D3: 3
+  TIM15_BKIN: 2
+  TIM1_CH4N: 6
+  USART1_RX: 7
+PC6:
+  COMP6_OUT: 7
+  EVENTOUT: 15
+  HRTIM1_CHF1: 13
+  HRTIM1_EEV10: 3
+  I2C4_SCL: 8
+  I2S2_MCK: 6
+  TIM3_CH1: 2
+  TIM8_CH1: 4
+PC7:
+  COMP5_OUT: 7
+  EVENTOUT: 15
+  HRTIM1_CHF2: 13
+  HRTIM1_FLT5: 3
+  I2C4_SDA: 8
+  I2S3_MCK: 6
+  TIM3_CH2: 2
+  TIM8_CH2: 4
+PC8:
+  COMP7_OUT: 7
+  EVENTOUT: 15
+  HRTIM1_CHE1: 3
+  I2C3_SCL: 8
+  TIM20_CH3: 6
+  TIM3_CH3: 2
+  TIM8_CH3: 4
+PC9:
+  EVENTOUT: 15
+  HRTIM1_CHE2: 3
+  I2C3_SDA: 8
+  I2S_CKIN: 5
+  TIM3_CH4: 2
+  TIM8_BKIN2: 6
+  TIM8_CH4: 4
+PD0:
+  EVENTOUT: 15
+  FDCAN1_RX: 9
+  FMC_D2: 12
+  FMC_DA2: 12
+  TIM8_CH4N: 6
+PD1:
+  EVENTOUT: 15
+  FDCAN1_TX: 9
+  FMC_D3: 12
+  FMC_DA3: 12
+  TIM8_BKIN2: 6
+  TIM8_CH4: 4
+PD10:
+  EVENTOUT: 15
+  FMC_D15: 12
+  FMC_DA15: 12
+  USART3_CK: 7
+PD11:
+  EVENTOUT: 15
+  FMC_A16: 12
+  I2C4_SMBA: 4
+  TIM5_ETR: 1
+  USART3_CTS: 7
+  USART3_NSS: 7
+PD12:
+  EVENTOUT: 15
+  FMC_A17: 12
+  TIM4_CH1: 2
+  USART3_DE: 7
+  USART3_RTS: 7
+PD13:
+  EVENTOUT: 15
+  FMC_A18: 12
+  TIM4_CH2: 2
+PD14:
+  EVENTOUT: 15
+  FMC_D0: 12
+  FMC_DA0: 12
+  TIM4_CH3: 2
+PD15:
+  EVENTOUT: 15
+  FMC_D1: 12
+  FMC_DA1: 12
+  SPI2_NSS: 6
+  TIM4_CH4: 2
+PD2:
+  EVENTOUT: 15
+  TIM3_ETR: 2
+  TIM8_BKIN: 4
+  UART5_RX: 5
+PD3:
+  EVENTOUT: 15
+  FMC_CLK: 12
+  QUADSPI1_BK2_NCS: 10
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART2_CTS: 7
+  USART2_NSS: 7
+PD4:
+  EVENTOUT: 15
+  FMC_NOE: 12
+  QUADSPI1_BK2_IO0: 10
+  TIM2_CH2: 2
+  USART2_DE: 7
+  USART2_RTS: 7
+PD5:
+  EVENTOUT: 15
+  FMC_NWE: 12
+  QUADSPI1_BK2_IO1: 10
+  USART2_TX: 7
+PD6:
+  EVENTOUT: 15
+  FMC_NWAIT: 12
+  QUADSPI1_BK2_IO2: 10
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  TIM2_CH4: 2
+  USART2_RX: 7
+PD7:
+  EVENTOUT: 15
+  FMC_NCE: 12
+  FMC_NE1: 12
+  QUADSPI1_BK2_IO3: 10
+  TIM2_CH3: 2
+  USART2_CK: 7
+PD8:
+  EVENTOUT: 15
+  FMC_D13: 12
+  FMC_DA13: 12
+  USART3_TX: 7
+PD9:
+  EVENTOUT: 15
+  FMC_D14: 12
+  FMC_DA14: 12
+  USART3_RX: 7
+PE0:
+  EVENTOUT: 15
+  FMC_NBL0: 12
+  TIM16_CH1: 4
+  TIM20_CH4N: 3
+  TIM20_ETR: 6
+  TIM4_ETR: 2
+  USART1_TX: 7
+PE1:
+  EVENTOUT: 15
+  FMC_NBL1: 12
+  TIM17_CH1: 4
+  TIM20_CH4: 6
+  USART1_RX: 7
+PE10:
+  EVENTOUT: 15
+  FMC_D7: 12
+  FMC_DA7: 12
+  QUADSPI1_CLK: 10
+  SAI1_MCLK_B: 13
+  TIM1_CH2N: 2
+PE11:
+  EVENTOUT: 15
+  FMC_D8: 12
+  FMC_DA8: 12
+  QUADSPI1_BK1_NCS: 10
+  SPI4_NSS: 5
+  TIM1_CH2: 2
+PE12:
+  EVENTOUT: 15
+  FMC_D9: 12
+  FMC_DA9: 12
+  QUADSPI1_BK1_IO0: 10
+  SPI4_SCK: 5
+  TIM1_CH3N: 2
+PE13:
+  EVENTOUT: 15
+  FMC_D10: 12
+  FMC_DA10: 12
+  QUADSPI1_BK1_IO1: 10
+  SPI4_MISO: 5
+  TIM1_CH3: 2
+PE14:
+  EVENTOUT: 15
+  FMC_D11: 12
+  FMC_DA11: 12
+  QUADSPI1_BK1_IO2: 10
+  SPI4_MOSI: 5
+  TIM1_BKIN2: 6
+  TIM1_CH4: 2
+PE15:
+  EVENTOUT: 15
+  FMC_D12: 12
+  FMC_DA12: 12
+  QUADSPI1_BK1_IO3: 10
+  TIM1_BKIN: 2
+  TIM1_CH4N: 6
+  USART3_RX: 7
+PE2:
+  EVENTOUT: 15
+  FMC_A23: 12
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 13
+  SPI4_SCK: 5
+  SYS_TRACECLK: 0
+  TIM20_CH1: 6
+  TIM3_CH1: 2
+PE3:
+  EVENTOUT: 15
+  FMC_A19: 12
+  SAI1_SD_B: 13
+  SPI4_NSS: 5
+  SYS_TRACED0: 0
+  TIM20_CH2: 6
+  TIM3_CH2: 2
+PE4:
+  EVENTOUT: 15
+  FMC_A20: 12
+  SAI1_D2: 3
+  SAI1_FS_A: 13
+  SPI4_NSS: 5
+  SYS_TRACED1: 0
+  TIM20_CH1N: 6
+  TIM3_CH3: 2
+PE5:
+  EVENTOUT: 15
+  FMC_A21: 12
+  SAI1_CK2: 3
+  SAI1_SCK_A: 13
+  SPI4_MISO: 5
+  SYS_TRACED2: 0
+  TIM20_CH2N: 6
+  TIM3_CH4: 2
+PE6:
+  EVENTOUT: 15
+  FMC_A22: 12
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  SPI4_MOSI: 5
+  SYS_TRACED3: 0
+  TIM20_CH3N: 6
+PE7:
+  EVENTOUT: 15
+  FMC_D4: 12
+  FMC_DA4: 12
+  SAI1_SD_B: 13
+  TIM1_ETR: 2
+PE8:
+  EVENTOUT: 15
+  FMC_D5: 12
+  FMC_DA5: 12
+  SAI1_SCK_B: 13
+  TIM1_CH1N: 2
+  TIM5_CH3: 1
+PE9:
+  EVENTOUT: 15
+  FMC_D6: 12
+  FMC_DA6: 12
+  SAI1_FS_B: 13
+  TIM1_CH1: 2
+  TIM5_CH4: 1
+PF0:
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM1_CH3N: 6
+PF1:
+  EVENTOUT: 15
+  I2S2_CK: 5
+  SPI2_SCK: 5
+PF10:
+  EVENTOUT: 15
+  FMC_A0: 12
+  QUADSPI1_CLK: 10
+  SAI1_D3: 13
+  SPI2_SCK: 5
+  TIM15_CH2: 3
+  TIM20_BKIN2: 2
+PF11:
+  EVENTOUT: 15
+  FMC_NE4: 12
+  TIM20_ETR: 2
+PF12:
+  EVENTOUT: 15
+  FMC_A6: 12
+  TIM20_CH1: 2
+PF13:
+  EVENTOUT: 15
+  FMC_A7: 12
+  I2C4_SMBA: 4
+  TIM20_CH2: 2
+PF14:
+  EVENTOUT: 15
+  FMC_A8: 12
+  I2C4_SCL: 4
+  TIM20_CH3: 2
+PF15:
+  EVENTOUT: 15
+  FMC_A9: 12
+  I2C4_SDA: 4
+  TIM20_CH4: 2
+PF2:
+  EVENTOUT: 15
+  FMC_A2: 12
+  I2C2_SMBA: 4
+  TIM20_CH3: 2
+PF3:
+  EVENTOUT: 15
+  FMC_A3: 12
+  I2C3_SCL: 4
+  TIM20_CH4: 2
+PF4:
+  COMP1_OUT: 2
+  EVENTOUT: 15
+  FMC_A4: 12
+  I2C3_SDA: 4
+  TIM20_CH1N: 3
+PF5:
+  EVENTOUT: 15
+  FMC_A5: 12
+  TIM20_CH2N: 2
+PF6:
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  QUADSPI1_BK1_IO3: 10
+  SAI1_SD_B: 3
+  TIM4_CH4: 2
+  TIM5_CH1: 6
+  TIM5_ETR: 1
+  USART3_DE: 7
+  USART3_RTS: 7
+PF7:
+  EVENTOUT: 15
+  FMC_A1: 12
+  QUADSPI1_BK1_IO2: 10
+  SAI1_MCLK_B: 13
+  TIM20_BKIN: 2
+  TIM5_CH2: 6
+PF8:
+  EVENTOUT: 15
+  FMC_A24: 12
+  QUADSPI1_BK1_IO0: 10
+  SAI1_SCK_B: 13
+  TIM20_BKIN2: 2
+  TIM5_CH3: 6
+PF9:
+  EVENTOUT: 15
+  FMC_A25: 12
+  QUADSPI1_BK1_IO1: 10
+  SAI1_FS_B: 13
+  SPI2_SCK: 5
+  TIM15_CH1: 3
+  TIM20_BKIN: 2
+  TIM5_CH4: 6
+PG0:
+  EVENTOUT: 15
+  FMC_A10: 12
+  TIM20_CH1N: 2
+PG1:
+  EVENTOUT: 15
+  FMC_A11: 12
+  TIM20_CH2N: 2
+PG10:
+  EVENTOUT: 15
+  RCC_MCO: 0
+PG2:
+  EVENTOUT: 15
+  FMC_A12: 12
+  SPI1_SCK: 5
+  TIM20_CH3N: 2
+PG3:
+  EVENTOUT: 15
+  FMC_A13: 12
+  I2C4_SCL: 4
+  SPI1_MISO: 5
+  TIM20_BKIN: 2
+  TIM20_CH4N: 6
+PG4:
+  EVENTOUT: 15
+  FMC_A14: 12
+  I2C4_SDA: 4
+  SPI1_MOSI: 5
+  TIM20_BKIN2: 2
+PG5:
+  EVENTOUT: 15
+  FMC_A15: 12
+  LPUART1_CTS: 8
+  SPI1_NSS: 5
+  TIM20_ETR: 2
+PG6:
+  EVENTOUT: 15
+  FMC_INT: 12
+  I2C3_SMBA: 4
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+  TIM20_BKIN: 2
+PG7:
+  EVENTOUT: 15
+  FMC_INT: 12
+  I2C3_SCL: 4
+  LPUART1_TX: 8
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 13
+PG8:
+  EVENTOUT: 15
+  FMC_NE3: 12
+  I2C3_SDA: 4
+  LPUART1_RX: 8
+PG9:
+  EVENTOUT: 15
+  FMC_NCE: 12
+  FMC_NE2: 12
+  SPI3_SCK: 6
+  TIM15_CH1N: 14
+  USART1_TX: 7
+PI8: {}

data/gpio_af/STM32G49x.yaml

@@ -0,0 +1,607 @@
+PA0:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  TIM2_CH1: 1
+  TIM2_ETR: 14
+  TIM8_BKIN: 9
+  TIM8_ETR: 10
+  USART2_CTS: 7
+  USART2_NSS: 7
+PA1:
+  EVENTOUT: 15
+  RTC_REFIN: 0
+  TIM15_CH1N: 9
+  TIM2_CH2: 1
+  USART2_DE: 7
+  USART2_RTS: 7
+PA10:
+  CRS_SYNC: 3
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+  SAI1_D1: 12
+  SAI1_SD_A: 14
+  SPI2_MISO: 5
+  TIM17_BKIN: 1
+  TIM1_CH3: 6
+  TIM2_CH4: 10
+  TIM8_BKIN: 11
+  USART1_RX: 7
+PA11:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  FDCAN1_RX: 9
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIM1_BKIN2: 12
+  TIM1_CH1N: 6
+  TIM1_CH4: 11
+  TIM4_CH1: 10
+  USART1_CTS: 7
+  USART1_NSS: 7
+PA12:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  FDCAN1_TX: 9
+  I2S_CKIN: 5
+  TIM16_CH1: 1
+  TIM1_CH2N: 6
+  TIM1_ETR: 11
+  TIM4_CH2: 10
+  USART1_DE: 7
+  USART1_RTS: 7
+PA13:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  IR_OUT: 5
+  SAI1_SD_B: 13
+  SYS_JTMS-SWDIO: 0
+  TIM16_CH1N: 1
+  TIM4_CH3: 10
+  USART3_CTS: 7
+  USART3_NSS: 7
+PA14:
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  LPTIM1_OUT: 1
+  SAI1_FS_B: 13
+  SYS_JTCK-SWCLK: 0
+  TIM1_BKIN: 6
+  TIM8_CH2: 5
+  USART2_TX: 7
+PA15:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM1_BKIN: 9
+  TIM20_ETR: 3
+  TIM2_CH1: 1
+  TIM2_ETR: 14
+  TIM8_CH1: 2
+  UART4_DE: 8
+  UART4_RTS: 8
+  USART2_RX: 7
+PA2:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  LPUART1_TX: 12
+  QUADSPI1_BK1_NCS: 10
+  TIM15_CH1: 9
+  TIM2_CH3: 1
+  UCPD1_FRSTX1: 14
+  UCPD1_FRSTX2: 14
+  USART2_TX: 7
+PA3:
+  EVENTOUT: 15
+  LPUART1_RX: 12
+  QUADSPI1_CLK: 10
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 13
+  TIM15_CH2: 9
+  TIM2_CH4: 1
+  USART2_RX: 7
+PA4:
+  EVENTOUT: 15
+  I2S3_WS: 6
+  SAI1_FS_B: 13
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  TIM3_CH2: 2
+  USART2_CK: 7
+PA5:
+  EVENTOUT: 15
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+  UCPD1_FRSTX1: 14
+  UCPD1_FRSTX2: 14
+PA6:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  LPUART1_CTS: 12
+  QUADSPI1_BK1_IO3: 10
+  SPI1_MISO: 5
+  TIM16_CH1: 1
+  TIM1_BKIN: 6
+  TIM3_CH1: 2
+  TIM8_BKIN: 4
+PA7:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  QUADSPI1_BK1_IO2: 10
+  SPI1_MOSI: 5
+  TIM17_CH1: 1
+  TIM1_CH1N: 6
+  TIM3_CH2: 2
+  TIM8_CH1N: 4
+  UCPD1_FRSTX1: 14
+  UCPD1_FRSTX2: 14
+PA8:
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  I2C3_SCL: 2
+  I2S2_MCK: 5
+  RCC_MCO: 0
+  SAI1_CK2: 12
+  SAI1_SCK_A: 14
+  TIM1_CH1: 6
+  TIM4_ETR: 10
+  USART1_CK: 7
+PA9:
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  I2C3_SMBA: 2
+  I2S3_MCK: 5
+  SAI1_FS_A: 14
+  TIM15_BKIN: 9
+  TIM1_CH2: 6
+  TIM2_CH3: 10
+  USART1_TX: 7
+PB0:
+  EVENTOUT: 15
+  QUADSPI1_BK1_IO1: 10
+  TIM1_CH2N: 6
+  TIM3_CH3: 2
+  TIM8_CH2N: 4
+  UCPD1_FRSTX1: 14
+  UCPD1_FRSTX2: 14
+PB1:
+  COMP4_OUT: 8
+  EVENTOUT: 15
+  LPUART1_DE: 12
+  LPUART1_RTS: 12
+  QUADSPI1_BK1_IO0: 10
+  TIM1_CH3N: 6
+  TIM3_CH4: 2
+  TIM8_CH3N: 4
+PB10:
+  EVENTOUT: 15
+  LPUART1_RX: 8
+  QUADSPI1_CLK: 10
+  SAI1_SCK_A: 14
+  TIM1_BKIN: 12
+  TIM2_CH3: 1
+  USART3_TX: 7
+PB11:
+  EVENTOUT: 15
+  LPUART1_TX: 8
+  QUADSPI1_BK1_NCS: 10
+  TIM2_CH4: 1
+  USART3_RX: 7
+PB12:
+  EVENTOUT: 15
+  FDCAN2_RX: 9
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+  SPI2_NSS: 5
+  TIM1_BKIN: 6
+  USART3_CK: 7
+PB13:
+  EVENTOUT: 15
+  FDCAN2_TX: 9
+  I2S2_CK: 5
+  LPUART1_CTS: 8
+  SPI2_SCK: 5
+  TIM1_CH1N: 6
+  USART3_CTS: 7
+  USART3_NSS: 7
+PB14:
+  COMP4_OUT: 8
+  EVENTOUT: 15
+  SPI2_MISO: 5
+  TIM15_CH1: 1
+  TIM1_CH2N: 6
+  USART3_DE: 7
+  USART3_RTS: 7
+PB15:
+  COMP3_OUT: 3
+  EVENTOUT: 15
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM15_CH1N: 2
+  TIM15_CH2: 1
+  TIM1_CH3N: 4
+PB2:
+  EVENTOUT: 15
+  I2C3_SMBA: 4
+  LPTIM1_OUT: 1
+  QUADSPI1_BK2_IO1: 10
+  RTC_OUT2: 0
+  TIM20_CH1: 3
+PB3:
+  CRS_SYNC: 3
+  EVENTOUT: 15
+  I2S3_CK: 6
+  SAI1_SCK_B: 14
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+  TIM3_ETR: 10
+  TIM4_ETR: 2
+  TIM8_CH1N: 4
+  USART2_TX: 7
+PB4:
+  EVENTOUT: 15
+  SAI1_MCLK_B: 14
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM16_CH1: 1
+  TIM17_BKIN: 10
+  TIM3_CH1: 2
+  TIM8_CH2N: 4
+  UART5_DE: 8
+  UART5_RTS: 8
+  USART2_RX: 7
+PB5:
+  EVENTOUT: 15
+  FDCAN2_RX: 9
+  I2C1_SMBA: 4
+  I2C3_SDA: 8
+  I2S3_SD: 6
+  LPTIM1_IN1: 11
+  SAI1_SD_B: 12
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM16_BKIN: 1
+  TIM17_CH1: 10
+  TIM3_CH2: 2
+  TIM8_CH3N: 3
+  UART5_CTS: 14
+  USART2_CK: 7
+PB6:
+  COMP4_OUT: 8
+  EVENTOUT: 15
+  FDCAN2_TX: 9
+  LPTIM1_ETR: 11
+  SAI1_FS_B: 14
+  TIM16_CH1N: 1
+  TIM4_CH1: 2
+  TIM8_BKIN2: 10
+  TIM8_CH1: 5
+  TIM8_ETR: 6
+  USART1_TX: 7
+PB7:
+  COMP3_OUT: 8
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  LPTIM1_IN2: 11
+  TIM17_CH1N: 1
+  TIM3_CH4: 10
+  TIM4_CH2: 2
+  TIM8_BKIN: 5
+  UART4_CTS: 14
+  USART1_RX: 7
+PB8:
+  COMP1_OUT: 8
+  EVENTOUT: 15
+  FDCAN1_RX: 9
+  I2C1_SCL: 4
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 14
+  TIM16_CH1: 1
+  TIM1_BKIN: 12
+  TIM4_CH3: 2
+  TIM8_CH2: 10
+  USART3_RX: 7
+PB9:
+  COMP2_OUT: 8
+  EVENTOUT: 15
+  FDCAN1_TX: 9
+  I2C1_SDA: 4
+  IR_OUT: 6
+  SAI1_D2: 3
+  SAI1_FS_A: 14
+  TIM17_CH1: 1
+  TIM1_CH3N: 12
+  TIM4_CH4: 2
+  TIM8_CH3: 10
+  USART3_TX: 7
+PC0:
+  EVENTOUT: 15
+  LPTIM1_IN1: 1
+  LPUART1_RX: 8
+  TIM1_CH1: 2
+PC1:
+  EVENTOUT: 15
+  LPTIM1_OUT: 1
+  LPUART1_TX: 8
+  QUADSPI1_BK2_IO0: 10
+  SAI1_SD_A: 13
+  TIM1_CH2: 2
+PC10:
+  EVENTOUT: 15
+  I2S3_CK: 6
+  SPI3_SCK: 6
+  TIM8_CH1N: 4
+  UART4_TX: 5
+  USART3_TX: 7
+PC11:
+  EVENTOUT: 15
+  I2C3_SDA: 8
+  SPI3_MISO: 6
+  TIM8_CH2N: 4
+  UART4_RX: 5
+  USART3_RX: 7
+PC12:
+  EVENTOUT: 15
+  I2S3_SD: 6
+  SPI3_MOSI: 6
+  TIM8_CH3N: 4
+  UART5_TX: 5
+  UCPD1_FRSTX1: 14
+  UCPD1_FRSTX2: 14
+  USART3_CK: 7
+PC13:
+  EVENTOUT: 15
+  TIM1_BKIN: 2
+  TIM1_CH1N: 4
+  TIM8_CH4N: 6
+PC14:
+  EVENTOUT: 15
+PC15:
+  EVENTOUT: 15
+PC2:
+  COMP3_OUT: 3
+  EVENTOUT: 15
+  LPTIM1_IN2: 1
+  QUADSPI1_BK2_IO1: 10
+  TIM1_CH3: 2
+  TIM20_CH2: 6
+PC3:
+  EVENTOUT: 15
+  LPTIM1_ETR: 1
+  QUADSPI1_BK2_IO2: 10
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  TIM1_BKIN2: 6
+  TIM1_CH4: 2
+PC4:
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  QUADSPI1_BK2_IO3: 10
+  TIM1_ETR: 2
+  USART1_TX: 7
+PC5:
+  EVENTOUT: 15
+  SAI1_D3: 3
+  TIM15_BKIN: 2
+  TIM1_CH4N: 6
+  USART1_RX: 7
+PC6:
+  EVENTOUT: 15
+  I2S2_MCK: 6
+  TIM3_CH1: 2
+  TIM8_CH1: 4
+PC7:
+  EVENTOUT: 15
+  I2S3_MCK: 6
+  TIM3_CH2: 2
+  TIM8_CH2: 4
+PC8:
+  EVENTOUT: 15
+  I2C3_SCL: 8
+  TIM20_CH3: 6
+  TIM3_CH3: 2
+  TIM8_CH3: 4
+PC9:
+  EVENTOUT: 15
+  I2C3_SDA: 8
+  I2S_CKIN: 5
+  TIM3_CH4: 2
+  TIM8_BKIN2: 6
+  TIM8_CH4: 4
+PD0:
+  EVENTOUT: 15
+  FDCAN1_RX: 9
+  TIM8_CH4N: 6
+PD1:
+  EVENTOUT: 15
+  FDCAN1_TX: 9
+  TIM8_BKIN2: 6
+  TIM8_CH4: 4
+PD10:
+  EVENTOUT: 15
+  USART3_CK: 7
+PD11:
+  EVENTOUT: 15
+  USART3_CTS: 7
+  USART3_NSS: 7
+PD12:
+  EVENTOUT: 15
+  TIM4_CH1: 2
+  USART3_DE: 7
+  USART3_RTS: 7
+PD13:
+  EVENTOUT: 15
+  TIM4_CH2: 2
+PD14:
+  EVENTOUT: 15
+  TIM4_CH3: 2
+PD15:
+  EVENTOUT: 15
+  SPI2_NSS: 6
+  TIM4_CH4: 2
+PD2:
+  EVENTOUT: 15
+  TIM3_ETR: 2
+  TIM8_BKIN: 4
+  UART5_RX: 5
+PD3:
+  EVENTOUT: 15
+  QUADSPI1_BK2_NCS: 10
+  TIM2_CH1: 2
+  TIM2_ETR: 2
+  USART2_CTS: 7
+  USART2_NSS: 7
+PD4:
+  EVENTOUT: 15
+  QUADSPI1_BK2_IO0: 10
+  TIM2_CH2: 2
+  USART2_DE: 7
+  USART2_RTS: 7
+PD5:
+  EVENTOUT: 15
+  QUADSPI1_BK2_IO1: 10
+  USART2_TX: 7
+PD6:
+  EVENTOUT: 15
+  QUADSPI1_BK2_IO2: 10
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  TIM2_CH4: 2
+  USART2_RX: 7
+PD7:
+  EVENTOUT: 15
+  QUADSPI1_BK2_IO3: 10
+  TIM2_CH3: 2
+  USART2_CK: 7
+PD8:
+  EVENTOUT: 15
+  USART3_TX: 7
+PD9:
+  EVENTOUT: 15
+  USART3_RX: 7
+PE0:
+  EVENTOUT: 15
+  TIM16_CH1: 4
+  TIM20_CH4N: 3
+  TIM20_ETR: 6
+  TIM4_ETR: 2
+  USART1_TX: 7
+PE1:
+  EVENTOUT: 15
+  TIM17_CH1: 4
+  TIM20_CH4: 6
+  USART1_RX: 7
+PE10:
+  EVENTOUT: 15
+  QUADSPI1_CLK: 10
+  SAI1_MCLK_B: 13
+  TIM1_CH2N: 2
+PE11:
+  EVENTOUT: 15
+  QUADSPI1_BK1_NCS: 10
+  TIM1_CH2: 2
+PE12:
+  EVENTOUT: 15
+  QUADSPI1_BK1_IO0: 10
+  TIM1_CH3N: 2
+PE13:
+  EVENTOUT: 15
+  QUADSPI1_BK1_IO1: 10
+  TIM1_CH3: 2
+PE14:
+  EVENTOUT: 15
+  QUADSPI1_BK1_IO2: 10
+  TIM1_BKIN2: 6
+  TIM1_CH4: 2
+PE15:
+  EVENTOUT: 15
+  QUADSPI1_BK1_IO3: 10
+  TIM1_BKIN: 2
+  TIM1_CH4N: 6
+  USART3_RX: 7
+PE2:
+  EVENTOUT: 15
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 13
+  SYS_TRACECLK: 0
+  TIM20_CH1: 6
+  TIM3_CH1: 2
+PE3:
+  EVENTOUT: 15
+  SAI1_SD_B: 13
+  SYS_TRACED0: 0
+  TIM20_CH2: 6
+  TIM3_CH2: 2
+PE4:
+  EVENTOUT: 15
+  SAI1_D2: 3
+  SAI1_FS_A: 13
+  SYS_TRACED1: 0
+  TIM20_CH1N: 6
+  TIM3_CH3: 2
+PE5:
+  EVENTOUT: 15
+  SAI1_CK2: 3
+  SAI1_SCK_A: 13
+  SYS_TRACED2: 0
+  TIM20_CH2N: 6
+  TIM3_CH4: 2
+PE6:
+  EVENTOUT: 15
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  SYS_TRACED3: 0
+  TIM20_CH3N: 6
+PE7:
+  EVENTOUT: 15
+  SAI1_SD_B: 13
+  TIM1_ETR: 2
+PE8:
+  EVENTOUT: 15
+  SAI1_SCK_B: 13
+  TIM1_CH1N: 2
+PE9:
+  EVENTOUT: 15
+  SAI1_FS_B: 13
+  TIM1_CH1: 2
+PF0:
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM1_CH3N: 6
+PF1:
+  EVENTOUT: 15
+  I2S2_CK: 5
+  SPI2_SCK: 5
+PF10:
+  EVENTOUT: 15
+  QUADSPI1_CLK: 10
+  SAI1_D3: 13
+  SPI2_SCK: 5
+  TIM15_CH2: 3
+  TIM20_BKIN2: 2
+PF2:
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+  TIM20_CH3: 2
+PF9:
+  EVENTOUT: 15
+  QUADSPI1_BK1_IO1: 10
+  SAI1_FS_B: 13
+  SPI2_SCK: 5
+  TIM15_CH1: 3
+  TIM20_BKIN: 2
+PG10:
+  EVENTOUT: 15
+  RCC_MCO: 0
+PI8: {}

data/gpio_af/STM32L021.yaml

@@ -0,0 +1,159 @@
+PA0:
+  COMP1_OUT: 7
+  LPTIM1_IN1: 1
+  LPUART1_RX: 6
+  TIM2_CH1: 2
+  TIM2_ETR: 5
+  USART2_CTS: 4
+  USART2_RX: 0
+PA1:
+  EVENTOUT: 0
+  I2C1_SMBA: 3
+  LPTIM1_IN2: 1
+  LPUART1_TX: 6
+  TIM21_ETR: 5
+  TIM2_CH2: 2
+  USART2_DE: 4
+  USART2_RTS: 4
+PA10:
+  COMP1_OUT: 7
+  I2C1_SDA: 1
+  RTC_REFIN: 2
+  TIM21_CH1: 0
+  TIM2_CH3: 5
+  USART2_RX: 4
+PA11:
+  COMP1_OUT: 7
+  EVENTOUT: 2
+  LPTIM1_OUT: 1
+  SPI1_MISO: 0
+  TIM21_CH2: 5
+  USART2_CTS: 4
+PA12:
+  COMP2_OUT: 7
+  EVENTOUT: 2
+  SPI1_MOSI: 0
+  USART2_DE: 4
+  USART2_RTS: 4
+PA13:
+  COMP1_OUT: 7
+  I2C1_SDA: 3
+  LPTIM1_ETR: 1
+  LPUART1_RX: 6
+  SPI1_SCK: 5
+  SYS_SWDIO: 0
+PA14:
+  COMP2_OUT: 7
+  I2C1_SMBA: 3
+  LPTIM1_OUT: 1
+  LPUART1_TX: 6
+  SPI1_MISO: 5
+  SYS_SWCLK: 0
+  USART2_TX: 4
+PA15:
+  EVENTOUT: 3
+  SPI1_NSS: 0
+  TIM2_CH1: 5
+  TIM2_ETR: 2
+  USART2_RX: 4
+PA2:
+  COMP2_OUT: 7
+  LPUART1_TX: 6
+  TIM21_CH1: 0
+  TIM2_CH3: 2
+  USART2_TX: 4
+PA3:
+  LPUART1_RX: 6
+  TIM21_CH2: 0
+  TIM2_CH4: 2
+  USART2_RX: 4
+PA4:
+  COMP2_OUT: 7
+  I2C1_SCL: 3
+  LPTIM1_ETR: 2
+  LPTIM1_IN1: 1
+  LPUART1_TX: 6
+  SPI1_NSS: 0
+  TIM2_ETR: 5
+  USART2_CK: 4
+PA5:
+  LPTIM1_IN2: 1
+  SPI1_SCK: 0
+  TIM2_CH1: 5
+  TIM2_ETR: 2
+PA6:
+  COMP1_OUT: 7
+  EVENTOUT: 6
+  LPTIM1_ETR: 1
+  LPUART1_CTS: 4
+  SPI1_MISO: 0
+PA7:
+  COMP2_OUT: 7
+  EVENTOUT: 6
+  LPTIM1_OUT: 1
+  SPI1_MOSI: 0
+  TIM21_ETR: 5
+  USART2_CTS: 4
+PA8:
+  EVENTOUT: 3
+  LPTIM1_IN1: 2
+  RCC_MCO: 0
+  TIM2_CH1: 5
+  USART2_CK: 4
+PA9:
+  COMP1_OUT: 7
+  I2C1_SCL: 1
+  LPTIM1_OUT: 2
+  RCC_MCO: 0
+  TIM21_CH2: 5
+  USART2_TX: 4
+PB0:
+  EVENTOUT: 0
+  SPI1_MISO: 1
+  TIM2_CH2: 2
+  TIM2_CH3: 5
+  USART2_DE: 4
+  USART2_RTS: 4
+PB1:
+  LPTIM1_IN1: 2
+  LPUART1_DE: 4
+  LPUART1_RTS: 4
+  SPI1_MOSI: 1
+  TIM2_CH4: 5
+  USART2_CK: 0
+PB2:
+  LPTIM1_OUT: 2
+PB3:
+  EVENTOUT: 4
+  SPI1_SCK: 0
+  TIM2_CH2: 2
+PB4:
+  EVENTOUT: 2
+  SPI1_MISO: 0
+PB5:
+  I2C1_SMBA: 3
+  LPTIM1_IN1: 2
+  SPI1_MOSI: 0
+  TIM21_CH1: 5
+PB6:
+  I2C1_SCL: 1
+  LPTIM1_ETR: 2
+  LPUART1_TX: 6
+  TIM2_CH3: 5
+  USART2_TX: 0
+PB7:
+  I2C1_SDA: 1
+  LPTIM1_IN2: 2
+  LPUART1_RX: 6
+  TIM2_CH4: 5
+  USART2_RX: 0
+PB8:
+  EVENTOUT: 2
+  I2C1_SCL: 4
+  SPI1_NSS: 5
+  USART2_TX: 0
+PB9: {}
+PC13: {}
+PC14: {}
+PC15: {}
+PI8: {}

data/gpio_af/STM32L031.yaml

@@ -0,0 +1,168 @@
+PA0:
+  COMP1_OUT: 7
+  LPTIM1_IN1: 1
+  TIM2_CH1: 2
+  TIM2_ETR: 5
+  USART2_CTS: 4
+PA1:
+  EVENTOUT: 0
+  I2C1_SMBA: 3
+  LPTIM1_IN2: 1
+  TIM21_ETR: 5
+  TIM2_CH2: 2
+  USART2_DE: 4
+  USART2_RTS: 4
+PA10:
+  I2C1_SDA: 1
+  TIM22_CH2: 5
+  USART2_RX: 4
+PA11:
+  COMP1_OUT: 7
+  EVENTOUT: 2
+  SPI1_MISO: 0
+  TIM21_CH2: 5
+  USART2_CTS: 4
+PA12:
+  COMP2_OUT: 7
+  EVENTOUT: 2
+  SPI1_MOSI: 0
+  USART2_DE: 4
+  USART2_RTS: 4
+PA13:
+  LPTIM1_ETR: 1
+  LPUART1_RX: 6
+  SYS_SWDIO: 0
+PA14:
+  I2C1_SMBA: 3
+  LPTIM1_OUT: 1
+  LPUART1_TX: 6
+  SYS_SWCLK: 0
+  USART2_TX: 4
+PA15:
+  EVENTOUT: 3
+  SPI1_NSS: 0
+  TIM2_CH1: 5
+  TIM2_ETR: 2
+  USART2_RX: 4
+PA2:
+  COMP2_OUT: 7
+  LPUART1_TX: 6
+  TIM21_CH1: 0
+  TIM2_CH3: 2
+  USART2_TX: 4
+PA3:
+  LPUART1_RX: 6
+  TIM21_CH2: 0
+  TIM2_CH4: 2
+  USART2_RX: 4
+PA4:
+  LPTIM1_IN1: 1
+  SPI1_NSS: 0
+  TIM22_ETR: 5
+  USART2_CK: 4
+PA5:
+  LPTIM1_IN2: 1
+  SPI1_SCK: 0
+  TIM2_CH1: 5
+  TIM2_ETR: 2
+PA6:
+  COMP1_OUT: 7
+  EVENTOUT: 6
+  LPTIM1_ETR: 1
+  LPUART1_CTS: 4
+  SPI1_MISO: 0
+  TIM22_CH1: 5
+PA7:
+  COMP2_OUT: 7
+  EVENTOUT: 6
+  LPTIM1_OUT: 1
+  SPI1_MOSI: 0
+  TIM22_CH2: 5
+  USART2_CTS: 4
+PA8:
+  EVENTOUT: 3
+  LPTIM1_IN1: 2
+  RCC_MCO: 0
+  TIM2_CH1: 5
+  USART2_CK: 4
+PA9:
+  I2C1_SCL: 1
+  RCC_MCO: 0
+  TIM22_CH1: 5
+  USART2_TX: 4
+PB0:
+  EVENTOUT: 0
+  SPI1_MISO: 1
+  TIM2_CH3: 5
+  USART2_DE: 4
+  USART2_RTS: 4
+PB1:
+  LPUART1_DE: 4
+  LPUART1_RTS: 4
+  SPI1_MOSI: 1
+  TIM2_CH4: 5
+  USART2_CK: 0
+PB10:
+  LPUART1_TX: 6
+  TIM2_CH3: 2
+PB11:
+  EVENTOUT: 0
+  LPUART1_RX: 6
+  TIM2_CH4: 2
+PB12:
+  EVENTOUT: 6
+  SPI1_NSS: 0
+PB13:
+  LPUART1_CTS: 6
+  RCC_MCO: 2
+  SPI1_SCK: 0
+  TIM21_CH1: 5
+PB14:
+  LPUART1_DE: 6
+  LPUART1_RTS: 6
+  RTC_OUT_ALARM: 2
+  RTC_OUT_CALIB: 2
+  SPI1_MISO: 0
+  TIM21_CH2: 5
+PB15:
+  RTC_REFIN: 2
+  SPI1_MOSI: 0
+PB2:
+  LPTIM1_OUT: 2
+PB3:
+  EVENTOUT: 4
+  SPI1_SCK: 0
+  TIM2_CH2: 2
+PB4:
+  EVENTOUT: 2
+  SPI1_MISO: 0
+  TIM22_CH1: 4
+PB5:
+  I2C1_SMBA: 3
+  LPTIM1_IN1: 2
+  SPI1_MOSI: 0
+  TIM22_CH2: 4
+PB6:
+  I2C1_SCL: 1
+  LPTIM1_ETR: 2
+  TIM21_CH1: 5
+  USART2_TX: 0
+PB7:
+  I2C1_SDA: 1
+  LPTIM1_IN2: 2
+  USART2_RX: 0
+PB8:
+  I2C1_SCL: 4
+PB9:
+  EVENTOUT: 2
+  I2C1_SDA: 4
+PC0:
+  EVENTOUT: 2
+  LPTIM1_IN1: 0
+  LPUART1_RX: 6
+PC13: {}
+PC14: {}
+PC15: {}
+PH0: {}
+PH1: {}
+PI8: {}

data/gpio_af/STM32L051.yaml

@@ -0,0 +1,264 @@
+PA0:
+  COMP1_OUT: 7
+  TIM2_CH1: 2
+  TIM2_ETR: 5
+  TSC_G1_IO1: 3
+  USART2_CTS: 4
+PA1:
+  EVENTOUT: 0
+  LCD_SEG0: 1
+  TIM21_ETR: 5
+  TIM2_CH2: 2
+  TSC_G1_IO2: 3
+  USART2_DE: 4
+  USART2_RTS: 4
+PA10:
+  LCD_COM2: 1
+  TSC_G4_IO2: 3
+  USART1_RX: 4
+PA11:
+  COMP1_OUT: 7
+  EVENTOUT: 2
+  SPI1_MISO: 0
+  TSC_G4_IO3: 3
+  USART1_CTS: 4
+PA12:
+  COMP2_OUT: 7
+  EVENTOUT: 2
+  SPI1_MOSI: 0
+  TSC_G4_IO4: 3
+  USART1_DE: 4
+  USART1_RTS: 4
+PA13:
+  SYS_SWDIO: 0
+  USB_NOE: 2
+PA14:
+  SYS_SWCLK: 0
+  USART2_TX: 4
+PA15:
+  EVENTOUT: 3
+  LCD_SEG17: 1
+  SPI1_NSS: 0
+  TIM2_CH1: 5
+  TIM2_ETR: 2
+  USART2_RX: 4
+PA2:
+  COMP2_OUT: 7
+  LCD_SEG1: 1
+  TIM21_CH1: 0
+  TIM2_CH3: 2
+  TSC_G1_IO3: 3
+  USART2_TX: 4
+PA3:
+  LCD_SEG2: 1
+  TIM21_CH2: 0
+  TIM2_CH4: 2
+  TSC_G1_IO4: 3
+  USART2_RX: 4
+PA4:
+  SPI1_NSS: 0
+  TIM22_ETR: 5
+  TSC_G2_IO1: 3
+  USART2_CK: 4
+PA5:
+  SPI1_SCK: 0
+  TIM2_CH1: 5
+  TIM2_ETR: 2
+  TSC_G2_IO2: 3
+PA6:
+  COMP1_OUT: 7
+  EVENTOUT: 6
+  LCD_SEG3: 1
+  LPUART1_CTS: 4
+  SPI1_MISO: 0
+  TIM22_CH1: 5
+  TSC_G2_IO3: 3
+PA7:
+  COMP2_OUT: 7
+  EVENTOUT: 6
+  LCD_SEG4: 1
+  SPI1_MOSI: 0
+  TIM22_CH2: 5
+  TSC_G2_IO4: 3
+PA8:
+  CRS_SYNC: 2
+  EVENTOUT: 3
+  LCD_COM0: 1
+  RCC_MCO: 0
+  USART1_CK: 4
+PA9:
+  LCD_COM1: 1
+  RCC_MCO: 0
+  TSC_G4_IO1: 3
+  USART1_TX: 4
+PB0:
+  EVENTOUT: 0
+  LCD_SEG5: 1
+  TSC_G3_IO2: 3
+PB1:
+  LCD_SEG6: 1
+  LPUART1_DE: 4
+  LPUART1_RTS: 4
+  TSC_G3_IO3: 3
+PB10:
+  I2C2_SCL: 6
+  LCD_SEG10: 1
+  LPUART1_TX: 4
+  SPI2_SCK: 5
+  TIM2_CH3: 2
+  TSC_SYNC: 3
+PB11:
+  EVENTOUT: 0
+  I2C2_SDA: 6
+  LCD_SEG11: 1
+  LPUART1_RX: 4
+  TIM2_CH4: 2
+  TSC_G6_IO1: 3
+PB12:
+  EVENTOUT: 6
+  I2C2_SMBA: 5
+  I2S2_WS: 0
+  LCD_SEG12: 1
+  LPUART1_DE: 2
+  LPUART1_RTS: 2
+  SPI2_NSS: 0
+  TSC_G6_IO2: 3
+PB13:
+  I2C2_SCL: 5
+  I2S2_CK: 0
+  LCD_SEG13: 1
+  LPUART1_CTS: 4
+  SPI2_SCK: 0
+  TIM21_CH1: 6
+  TSC_G6_IO3: 3
+PB14:
+  I2C2_SDA: 5
+  I2S2_MCK: 0
+  LCD_SEG14: 1
+  LPUART1_DE: 4
+  LPUART1_RTS: 4
+  RTC_OUT_ALARM: 2
+  RTC_OUT_CALIB: 2
+  SPI2_MISO: 0
+  TIM21_CH2: 6
+  TSC_G6_IO4: 3
+PB15:
+  I2S2_SD: 0
+  LCD_SEG15: 1
+  RTC_REFIN: 2
+  SPI2_MOSI: 0
+PB2:
+  LPTIM1_OUT: 2
+  TSC_G3_IO4: 3
+PB3:
+  EVENTOUT: 4
+  LCD_SEG7: 1
+  SPI1_SCK: 0
+  TIM2_CH2: 2
+  TSC_G5_IO1: 3
+PB4:
+  EVENTOUT: 2
+  LCD_SEG8: 1
+  SPI1_MISO: 0
+  TIM22_CH1: 4
+  TSC_G5_IO2: 3
+PB5:
+  I2C1_SMBA: 3
+  LCD_SEG9: 1
+  LPTIM1_IN1: 2
+  SPI1_MOSI: 0
+  TIM22_CH2: 4
+PB6:
+  I2C1_SCL: 1
+  LPTIM1_ETR: 2
+  TSC_G5_IO3: 3
+  USART1_TX: 0
+PB7:
+  I2C1_SDA: 1
+  LPTIM1_IN2: 2
+  TSC_G5_IO4: 3
+  USART1_RX: 0
+PB8:
+  I2C1_SCL: 4
+  LCD_SEG16: 1
+  TSC_SYNC: 3
+PB9:
+  EVENTOUT: 2
+  I2C1_SDA: 4
+  I2S2_WS: 5
+  LCD_COM3: 1
+  SPI2_NSS: 5
+PC0:
+  EVENTOUT: 2
+  LCD_SEG18: 1
+  LPTIM1_IN1: 0
+  TSC_G7_IO1: 3
+PC1:
+  EVENTOUT: 2
+  LCD_SEG19: 1
+  LPTIM1_OUT: 0
+  TSC_G7_IO2: 3
+PC10:
+  LCD_COM4: 1
+  LCD_SEG28: 1
+  LCD_SEG40: 1
+  LPUART1_TX: 0
+PC11:
+  LCD_COM5: 1
+  LCD_SEG29: 1
+  LCD_SEG41: 1
+  LPUART1_RX: 0
+PC12:
+  LCD_COM6: 1
+  LCD_SEG30: 1
+  LCD_SEG42: 1
+PC13: {}
+PC14: {}
+PC15: {}
+PC2:
+  I2S2_MCK: 2
+  LCD_SEG20: 1
+  LPTIM1_IN2: 0
+  SPI2_MISO: 2
+  TSC_G7_IO3: 3
+PC3:
+  I2S2_SD: 2
+  LCD_SEG21: 1
+  LPTIM1_ETR: 0
+  SPI2_MOSI: 2
+  TSC_G7_IO4: 3
+PC4:
+  EVENTOUT: 0
+  LCD_SEG22: 1
+  LPUART1_TX: 2
+PC5:
+  LCD_SEG23: 1
+  LPUART1_RX: 2
+  TSC_G3_IO1: 3
+PC6:
+  LCD_SEG24: 1
+  TIM22_CH1: 0
+  TSC_G8_IO1: 3
+PC7:
+  LCD_SEG25: 1
+  TIM22_CH2: 0
+  TSC_G8_IO2: 3
+PC8:
+  LCD_SEG26: 1
+  TIM22_ETR: 0
+  TSC_G8_IO3: 3
+PC9:
+  LCD_SEG27: 1
+  TIM21_ETR: 0
+  TSC_G8_IO4: 3
+  USB_NOE: 2
+PD2:
+  LCD_COM7: 1
+  LCD_SEG31: 1
+  LCD_SEG43: 1
+  LPUART1_DE: 0
+  LPUART1_RTS: 0
+PH0:
+  CRS_SYNC: 0
+PH1: {}
+PI8: {}

data/gpio_af/STM32L071.yaml

@@ -0,0 +1,413 @@
+PA0:
+  COMP1_OUT: 7
+  TIM2_CH1: 2
+  TIM2_ETR: 5
+  TSC_G1_IO1: 3
+  USART2_CTS: 4
+  USART4_TX: 6
+PA1:
+  EVENTOUT: 0
+  LCD_SEG0: 1
+  TIM21_ETR: 5
+  TIM2_CH2: 2
+  TSC_G1_IO2: 3
+  USART2_DE: 4
+  USART2_RTS: 4
+  USART4_RX: 6
+PA10:
+  I2C1_SDA: 6
+  LCD_COM2: 1
+  TSC_G4_IO2: 3
+  USART1_RX: 4
+PA11:
+  COMP1_OUT: 7
+  EVENTOUT: 2
+  SPI1_MISO: 0
+  TSC_G4_IO3: 3
+  USART1_CTS: 4
+PA12:
+  COMP2_OUT: 7
+  EVENTOUT: 2
+  SPI1_MOSI: 0
+  TSC_G4_IO4: 3
+  USART1_DE: 4
+  USART1_RTS: 4
+PA13:
+  LPUART1_RX: 6
+  SYS_SWDIO: 0
+  USB_NOE: 2
+PA14:
+  LPUART1_TX: 6
+  SYS_SWCLK: 0
+  USART2_TX: 4
+PA15:
+  EVENTOUT: 3
+  LCD_SEG17: 1
+  SPI1_NSS: 0
+  TIM2_CH1: 5
+  TIM2_ETR: 2
+  USART2_RX: 4
+  USART4_DE: 6
+  USART4_RTS: 6
+PA2:
+  COMP2_OUT: 7
+  LCD_SEG1: 1
+  LPUART1_TX: 6
+  TIM21_CH1: 0
+  TIM2_CH3: 2
+  TSC_G1_IO3: 3
+  USART2_TX: 4
+PA3:
+  LCD_SEG2: 1
+  LPUART1_RX: 6
+  TIM21_CH2: 0
+  TIM2_CH4: 2
+  TSC_G1_IO4: 3
+  USART2_RX: 4
+PA4:
+  SPI1_NSS: 0
+  TIM22_ETR: 5
+  TSC_G2_IO1: 3
+  USART2_CK: 4
+PA5:
+  SPI1_SCK: 0
+  TIM2_CH1: 5
+  TIM2_ETR: 2
+  TSC_G2_IO2: 3
+PA6:
+  COMP1_OUT: 7
+  EVENTOUT: 6
+  LCD_SEG3: 1
+  LPUART1_CTS: 4
+  SPI1_MISO: 0
+  TIM22_CH1: 5
+  TIM3_CH1: 2
+  TSC_G2_IO3: 3
+PA7:
+  COMP2_OUT: 7
+  EVENTOUT: 6
+  LCD_SEG4: 1
+  SPI1_MOSI: 0
+  TIM22_CH2: 5
+  TIM3_CH2: 2
+  TSC_G2_IO4: 3
+PA8:
+  CRS_SYNC: 2
+  EVENTOUT: 3
+  I2C3_SCL: 7
+  LCD_COM0: 1
+  RCC_MCO: 0
+  USART1_CK: 4
+PA9:
+  I2C1_SCL: 6
+  I2C3_SMBA: 7
+  LCD_COM1: 1
+  RCC_MCO: 0
+  TSC_G4_IO1: 3
+  USART1_TX: 4
+PB0:
+  EVENTOUT: 0
+  LCD_SEG5: 1
+  TIM3_CH3: 2
+  TSC_G3_IO2: 3
+PB1:
+  LCD_SEG6: 1
+  LPUART1_DE: 4
+  LPUART1_RTS: 4
+  TIM3_CH4: 2
+  TSC_G3_IO3: 3
+PB10:
+  I2C2_SCL: 6
+  LCD_SEG10: 1
+  LPUART1_RX: 7
+  LPUART1_TX: 4
+  SPI2_SCK: 5
+  TIM2_CH3: 2
+  TSC_SYNC: 3
+PB11:
+  EVENTOUT: 0
+  I2C2_SDA: 6
+  LCD_SEG11: 1
+  LPUART1_RX: 4
+  LPUART1_TX: 7
+  TIM2_CH4: 2
+  TSC_G6_IO1: 3
+PB12:
+  EVENTOUT: 6
+  I2C2_SMBA: 5
+  I2S2_WS: 0
+  LCD_SEG12: 1
+  LPUART1_DE: 2
+  LPUART1_RTS: 2
+  SPI2_NSS: 0
+  TSC_G6_IO2: 3
+PB13:
+  I2C2_SCL: 5
+  I2S2_CK: 0
+  LCD_SEG13: 1
+  LPUART1_CTS: 4
+  RCC_MCO: 2
+  SPI2_SCK: 0
+  TIM21_CH1: 6
+  TSC_G6_IO3: 3
+PB14:
+  I2C2_SDA: 5
+  I2S2_MCK: 0
+  LCD_SEG14: 1
+  LPUART1_DE: 4
+  LPUART1_RTS: 4
+  RTC_OUT_ALARM: 2
+  RTC_OUT_CALIB: 2
+  SPI2_MISO: 0
+  TIM21_CH2: 6
+  TSC_G6_IO4: 3
+PB15:
+  I2S2_SD: 0
+  LCD_SEG15: 1
+  RTC_REFIN: 2
+  SPI2_MOSI: 0
+PB2:
+  I2C3_SMBA: 7
+  LPTIM1_OUT: 2
+  TSC_G3_IO4: 3
+PB3:
+  EVENTOUT: 4
+  LCD_SEG7: 1
+  SPI1_SCK: 0
+  TIM2_CH2: 2
+  TSC_G5_IO1: 3
+  USART1_DE: 5
+  USART1_RTS: 5
+  USART5_TX: 6
+PB4:
+  I2C3_SDA: 7
+  LCD_SEG8: 1
+  SPI1_MISO: 0
+  TIM22_CH1: 4
+  TIM3_CH1: 2
+  TSC_G5_IO2: 3
+  USART1_CTS: 5
+  USART5_RX: 6
+PB5:
+  I2C1_SMBA: 3
+  LCD_SEG9: 1
+  LPTIM1_IN1: 2
+  SPI1_MOSI: 0
+  TIM22_CH2: 4
+  TIM3_CH2: 4
+  USART1_CK: 5
+  USART5_CK: 6
+  USART5_DE: 6
+  USART5_RTS: 6
+PB6:
+  I2C1_SCL: 1
+  LPTIM1_ETR: 2
+  TSC_G5_IO3: 3
+  USART1_TX: 0
+PB7:
+  I2C1_SDA: 1
+  LPTIM1_IN2: 2
+  TSC_G5_IO4: 3
+  USART1_RX: 0
+  USART4_CTS: 6
+PB8:
+  I2C1_SCL: 4
+  LCD_SEG16: 1
+  TSC_SYNC: 3
+PB9:
+  EVENTOUT: 2
+  I2C1_SDA: 4
+  I2S2_WS: 5
+  LCD_COM3: 1
+  SPI2_NSS: 5
+PC0:
+  EVENTOUT: 2
+  I2C3_SCL: 7
+  LCD_SEG18: 1
+  LPTIM1_IN1: 0
+  LPUART1_RX: 6
+  TSC_G7_IO1: 3
+PC1:
+  EVENTOUT: 2
+  I2C3_SDA: 7
+  LCD_SEG19: 1
+  LPTIM1_OUT: 0
+  LPUART1_TX: 6
+  TSC_G7_IO2: 3
+PC10:
+  LCD_COM4: 1
+  LCD_SEG28: 1
+  LCD_SEG48: 1
+  LPUART1_TX: 0
+  USART4_TX: 6
+PC11:
+  LCD_COM5: 1
+  LCD_SEG29: 1
+  LCD_SEG49: 1
+  LPUART1_RX: 0
+  USART4_RX: 6
+PC12:
+  LCD_COM6: 1
+  LCD_SEG30: 1
+  LCD_SEG50: 1
+  USART4_CK: 6
+  USART5_TX: 2
+PC13: {}
+PC14: {}
+PC15: {}
+PC2:
+  I2S2_MCK: 2
+  LCD_SEG20: 1
+  LPTIM1_IN2: 0
+  SPI2_MISO: 2
+  TSC_G7_IO3: 3
+PC3:
+  I2S2_SD: 2
+  LCD_SEG21: 1
+  LPTIM1_ETR: 0
+  SPI2_MOSI: 2
+  TSC_G7_IO4: 3
+PC4:
+  EVENTOUT: 0
+  LCD_SEG22: 1
+  LPUART1_TX: 2
+PC5:
+  LCD_SEG23: 1
+  LPUART1_RX: 2
+  TSC_G3_IO1: 3
+PC6:
+  LCD_SEG24: 1
+  TIM22_CH1: 0
+  TIM3_CH1: 2
+  TSC_G8_IO1: 3
+PC7:
+  LCD_SEG25: 1
+  TIM22_CH2: 0
+  TIM3_CH2: 2
+  TSC_G8_IO2: 3
+PC8:
+  LCD_SEG26: 1
+  TIM22_ETR: 0
+  TIM3_CH3: 2
+  TSC_G8_IO3: 3
+PC9:
+  I2C3_SDA: 7
+  LCD_SEG27: 1
+  TIM21_ETR: 0
+  TIM3_CH4: 2
+  TSC_G8_IO4: 3
+  USB_NOE: 2
+PD0:
+  I2S2_WS: 1
+  SPI2_NSS: 1
+  TIM21_CH1: 0
+PD1:
+  I2S2_CK: 1
+  SPI2_SCK: 1
+PD10:
+  LCD_SEG30: 1
+PD11:
+  LCD_SEG31: 1
+  LPUART1_CTS: 0
+PD12:
+  LCD_SEG32: 1
+  LPUART1_DE: 0
+  LPUART1_RTS: 0
+PD13:
+  LCD_SEG33: 1
+PD14:
+  LCD_SEG34: 1
+PD15:
+  CRS_SYNC: 0
+  LCD_SEG35: 1
+PD2:
+  LCD_COM7: 1
+  LCD_SEG31: 1
+  LCD_SEG51: 1
+  LPUART1_DE: 0
+  LPUART1_RTS: 0
+  TIM3_ETR: 2
+  USART5_RX: 6
+PD3:
+  I2S2_MCK: 2
+  LCD_SEG44: 1
+  SPI2_MISO: 2
+  USART2_CTS: 0
+PD4:
+  I2S2_SD: 1
+  SPI2_MOSI: 1
+  USART2_DE: 0
+  USART2_RTS: 0
+PD5:
+  USART2_TX: 0
+PD6:
+  USART2_RX: 0
+PD7:
+  TIM21_CH2: 1
+  USART2_CK: 0
+PD8:
+  LCD_SEG28: 1
+  LPUART1_TX: 0
+PD9:
+  LCD_SEG29: 1
+  LPUART1_RX: 0
+PE0:
+  EVENTOUT: 2
+  LCD_SEG36: 1
+PE1:
+  EVENTOUT: 2
+  LCD_SEG37: 1
+PE10:
+  LCD_SEG40: 1
+  TIM2_CH2: 0
+  USART5_TX: 6
+PE11:
+  TIM2_CH3: 0
+  USART5_RX: 6
+PE12:
+  SPI1_NSS: 2
+  TIM2_CH4: 0
+PE13:
+  LCD_SEG41: 1
+  SPI1_SCK: 2
+PE14:
+  LCD_SEG42: 1
+  SPI1_MISO: 2
+PE15:
+  LCD_SEG43: 1
+  SPI1_MOSI: 2
+PE2:
+  LCD_SEG38: 1
+  TIM3_ETR: 2
+PE3:
+  LCD_SEG39: 1
+  TIM22_CH1: 0
+  TIM3_CH1: 2
+PE4:
+  TIM22_CH2: 0
+  TIM3_CH2: 2
+PE5:
+  TIM21_CH1: 0
+  TIM3_CH3: 2
+PE6:
+  TIM21_CH2: 0
+  TIM3_CH4: 2
+PE7:
+  LCD_SEG45: 1
+  USART5_CK: 6
+  USART5_DE: 6
+  USART5_RTS: 6
+PE8:
+  LCD_SEG46: 1
+  USART4_TX: 6
+PE9:
+  LCD_SEG47: 1
+  TIM2_CH1: 0
+  TIM2_ETR: 2
+  USART4_RX: 6
+PH0:
+  CRS_SYNC: 0
+PH1: {}
+PH10: {}
+PH9: {}
+PI8: {}

data/gpio_af/STM32L152x8.yaml

@@ -0,0 +1,367 @@
+PA0:
+  SYS_WKUP1: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 1
+  TIMX_IC1: 14
+  TS_G1_IO1: 14
+  USART2_CTS: 7
+PA1:
+  LCD_SEG0: 11
+  TIM2_CH2: 1
+  TIMX_IC2: 14
+  TS_G1_IO2: 14
+  USART2_RTS: 7
+PA10:
+  LCD_COM2: 11
+  TIMX_IC3: 14
+  TS_G4_IO3: 14
+  USART1_RX: 7
+PA11:
+  SPI1_MISO: 5
+  TIMX_IC4: 14
+  USART1_CTS: 7
+  USB_DM: 10
+PA12:
+  SPI1_MOSI: 5
+  TIMX_IC1: 14
+  USART1_RTS: 7
+  USB_DP: 10
+PA13:
+  SYS_JTMS-SWDIO: 0
+  TIMX_IC2: 14
+  TS_G5_IO1: 14
+PA14:
+  SYS_JTCK-SWCLK: 0
+  TIMX_IC3: 14
+  TS_G5_IO2: 14
+PA15:
+  LCD_SEG17: 11
+  SPI1_NSS: 5
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIMX_IC4: 14
+  TS_G5_IO3: 14
+PA2:
+  LCD_SEG1: 11
+  TIM2_CH3: 1
+  TIM9_CH1: 3
+  TIMX_IC3: 14
+  TS_G1_IO3: 14
+  USART2_TX: 7
+PA3:
+  LCD_SEG2: 11
+  TIM2_CH4: 1
+  TIM9_CH2: 3
+  TIMX_IC4: 14
+  TS_G1_IO4: 14
+  USART2_RX: 7
+PA4:
+  SPI1_NSS: 5
+  TIMX_IC1: 14
+  USART2_CK: 7
+PA5:
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIMX_IC2: 14
+PA6:
+  LCD_SEG3: 11
+  SPI1_MISO: 5
+  TIM10_CH1: 3
+  TIM3_CH1: 2
+  TIMX_IC3: 14
+  TS_G2_IO1: 14
+PA7:
+  LCD_SEG4: 11
+  SPI1_MOSI: 5
+  TIM11_CH1: 3
+  TIM3_CH2: 2
+  TIMX_IC4: 14
+  TS_G2_IO2: 14
+PA8:
+  LCD_COM0: 11
+  RCC_MCO: 0
+  TIMX_IC1: 14
+  TS_G4_IO1: 14
+  USART1_CK: 7
+PA9:
+  LCD_COM1: 11
+  TIMX_IC2: 14
+  TS_G4_IO2: 14
+  USART1_TX: 7
+PB0:
+  LCD_SEG5: 11
+  TIM3_CH3: 2
+  TS_G3_IO1: 14
+PB1:
+  LCD_SEG6: 11
+  TIM3_CH4: 2
+  TS_G3_IO2: 14
+PB10:
+  I2C2_SCL: 4
+  LCD_SEG10: 11
+  TIM2_CH3: 1
+  USART3_TX: 7
+PB11:
+  I2C2_SDA: 4
+  LCD_SEG11: 11
+  TIM2_CH4: 1
+  USART3_RX: 7
+PB12:
+  I2C2_SMBA: 4
+  LCD_SEG12: 11
+  SPI2_NSS: 5
+  TIM10_CH1: 3
+  TS_G7_IO1: 14
+  USART3_CK: 7
+PB13:
+  LCD_SEG13: 11
+  SPI2_SCK: 5
+  TIM9_CH1: 3
+  TS_G7_IO2: 14
+  USART3_CTS: 7
+PB14:
+  LCD_SEG14: 11
+  SPI2_MISO: 5
+  TIM9_CH2: 3
+  TS_G7_IO3: 14
+  USART3_RTS: 7
+PB15:
+  LCD_SEG15: 11
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM11_CH1: 3
+  TS_G7_IO4: 14
+PB2: {}
+PB3:
+  LCD_SEG7: 11
+  SPI1_SCK: 5
+  SYS_JTDO-TRACESWO: 0
+  TIM2_CH2: 1
+PB4:
+  LCD_SEG8: 11
+  SPI1_MISO: 5
+  SYS_JTRST: 0
+  TIM3_CH1: 2
+  TS_G6_IO1: 14
+PB5:
+  I2C1_SMBA: 4
+  LCD_SEG9: 11
+  SPI1_MOSI: 5
+  TIM3_CH2: 2
+  TS_G6_IO2: 14
+PB6:
+  I2C1_SCL: 4
+  TIM4_CH1: 2
+  USART1_TX: 7
+PB7:
+  I2C1_SDA: 4
+  TIM4_CH2: 2
+  USART1_RX: 7
+PB8:
+  I2C1_SCL: 4
+  LCD_SEG16: 11
+  TIM10_CH1: 3
+  TIM4_CH3: 2
+PB9:
+  I2C1_SDA: 4
+  LCD_COM3: 11
+  TIM11_CH1: 3
+  TIM4_CH4: 2
+PC0:
+  LCD_SEG18: 11
+  TIMX_IC1: 14
+  TS_G8_IO1: 14
+PC1:
+  LCD_SEG19: 11
+  TIMX_IC2: 14
+  TS_G8_IO2: 14
+PC10:
+  LCD_COM4: 11
+  LCD_SEG28: 11
+  LCD_SEG40: 11
+  TIMX_IC3: 14
+  USART3_TX: 7
+PC11:
+  LCD_COM5: 11
+  LCD_SEG29: 11
+  LCD_SEG41: 11
+  TIMX_IC4: 14
+  USART3_RX: 7
+PC12:
+  LCD_COM6: 11
+  LCD_SEG30: 11
+  LCD_SEG42: 11
+  TIMX_IC1: 14
+  USART3_CK: 7
+PC13:
+  RTC_OUT_ALARM: 0
+  RTC_OUT_CALIB: 0
+  RTC_TAMP1: 0
+  RTC_TS: 0
+  SYS_WKUP2: 0
+  TIMX_IC2: 14
+PC14: {}
+PC15: {}
+PC2:
+  LCD_SEG20: 11
+  TIMX_IC3: 14
+  TS_G8_IO3: 14
+PC3:
+  LCD_SEG21: 11
+  TIMX_IC4: 14
+  TS_G8_IO4: 14
+PC4:
+  LCD_SEG22: 11
+  TIMX_IC1: 14
+  TS_G9_IO1: 14
+PC5:
+  LCD_SEG23: 11
+  TIMX_IC2: 14
+  TS_G9_IO2: 14
+PC6:
+  LCD_SEG24: 11
+  TIM3_CH1: 2
+  TIMX_IC3: 14
+  TS_G10_IO1: 14
+PC7:
+  LCD_SEG25: 11
+  TIM3_CH2: 2
+  TIMX_IC4: 14
+  TS_G10_IO2: 14
+PC8:
+  LCD_SEG26: 11
+  TIM3_CH3: 2
+  TIMX_IC1: 14
+  TS_G10_IO3: 14
+PC9:
+  LCD_SEG27: 11
+  TIM3_CH4: 2
+  TIMX_IC2: 14
+  TS_G10_IO4: 14
+PD0:
+  SPI2_NSS: 5
+  TIM9_CH1: 3
+  TIMX_IC1: 14
+PD1:
+  SPI2_SCK: 5
+  TIMX_IC2: 14
+PD10:
+  LCD_SEG30: 11
+  TIMX_IC3: 14
+  USART3_CK: 7
+PD11:
+  LCD_SEG31: 11
+  TIMX_IC4: 14
+  USART3_CTS: 7
+PD12:
+  LCD_SEG32: 11
+  TIM4_CH1: 2
+  TIMX_IC1: 14
+  USART3_RTS: 7
+PD13:
+  LCD_SEG33: 11
+  TIM4_CH2: 2
+  TIMX_IC2: 14
+PD14:
+  LCD_SEG34: 11
+  TIM4_CH3: 2
+  TIMX_IC3: 14
+PD15:
+  LCD_SEG35: 11
+  TIM4_CH4: 2
+  TIMX_IC4: 14
+PD2:
+  LCD_COM7: 11
+  LCD_SEG31: 11
+  LCD_SEG43: 11
+  TIM3_ETR: 2
+  TIMX_IC3: 14
+PD3:
+  SPI2_MISO: 5
+  TIMX_IC4: 14
+  USART2_CTS: 7
+PD4:
+  SPI2_MOSI: 5
+  TIMX_IC1: 14
+  USART2_RTS: 7
+PD5:
+  TIMX_IC2: 14
+  USART2_TX: 7
+PD6:
+  TIMX_IC3: 14
+  USART2_RX: 7
+PD7:
+  TIM9_CH2: 3
+  TIMX_IC4: 14
+  USART2_CK: 7
+PD8:
+  LCD_SEG28: 11
+  TIMX_IC1: 14
+  USART3_TX: 7
+PD9:
+  LCD_SEG29: 11
+  TIMX_IC2: 14
+  USART3_RX: 7
+PE0:
+  LCD_SEG36: 11
+  TIM10_CH1: 3
+  TIM4_ETR: 2
+  TIMX_IC1: 14
+PE1:
+  LCD_SEG37: 11
+  TIM11_CH1: 3
+  TIMX_IC2: 14
+PE10:
+  TIM2_CH2: 1
+  TIMX_IC3: 14
+PE11:
+  TIM2_CH3: 1
+  TIMX_IC4: 14
+PE12:
+  SPI1_NSS: 5
+  TIM2_CH4: 1
+  TIMX_IC1: 14
+PE13:
+  SPI1_SCK: 5
+  TIMX_IC2: 14
+PE14:
+  SPI1_MISO: 5
+  TIMX_IC3: 14
+PE15:
+  SPI1_MOSI: 5
+  TIMX_IC4: 14
+PE2:
+  LCD_SEG38: 11
+  SYS_TRACECK: 0
+  TIM3_ETR: 2
+  TIMX_IC3: 14
+PE3:
+  LCD_SEG39: 11
+  SYS_TRACED0: 0
+  TIM3_CH1: 2
+  TIMX_IC4: 14
+PE4:
+  SYS_TRACED1: 0
+  TIM3_CH2: 2
+  TIMX_IC1: 14
+PE5:
+  SYS_TRACED2: 0
+  TIM9_CH1: 3
+  TIMX_IC2: 14
+PE6:
+  SYS_TRACED3: 0
+  SYS_WKUP3: 0
+  TIM9_CH2: 3
+  TIMX_IC3: 14
+PE7:
+  TIMX_IC4: 14
+PE8:
+  TIMX_IC1: 14
+PE9:
+  TIM2_CH1: 1
+  TIMX_IC2: 14
+PH0:
+  RCC_OSC_IN: 0
+PH1:
+  RCC_OSC_OUT: 0
+PH2: {}

data/gpio_af/STM32L152xC.yaml

@@ -0,0 +1,398 @@
+PA0:
+  RTC_TAMP2: 0
+  SYS_WKUP1: 0
+  TIM2_CH1: 1
+  TIM5_CH1: 2
+  TIMX_IC1: 14
+  TS_G1_IO1: 14
+  USART2_CTS: 7
+PA1:
+  LCD_SEG0: 11
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  TIMX_IC2: 14
+  TS_G1_IO2: 14
+  USART2_RTS: 7
+PA10:
+  LCD_COM2: 11
+  TIMX_IC3: 14
+  TS_G4_IO3: 14
+  USART1_RX: 7
+PA11:
+  SPI1_MISO: 5
+  TIMX_IC4: 14
+  USART1_CTS: 7
+  USB_DM: 10
+PA12:
+  SPI1_MOSI: 5
+  TIMX_IC1: 14
+  USART1_RTS: 7
+  USB_DP: 10
+PA13:
+  SYS_JTMS-SWDIO: 0
+  TIMX_IC2: 14
+  TS_G5_IO1: 14
+PA14:
+  SYS_JTCK-SWCLK: 0
+  TIMX_IC3: 14
+  TS_G5_IO2: 14
+PA15:
+  I2S3_WS: 6
+  LCD_SEG17: 11
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIMX_IC4: 14
+  TS_G5_IO3: 14
+PA2:
+  LCD_SEG1: 11
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  TIM9_CH1: 3
+  TIMX_IC3: 14
+  TS_G1_IO3: 14
+  USART2_TX: 7
+PA3:
+  LCD_SEG2: 11
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  TIM9_CH2: 3
+  TIMX_IC4: 14
+  TS_G1_IO4: 14
+  USART2_RX: 7
+PA4:
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  TIMX_IC1: 14
+  USART2_CK: 7
+PA5:
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIMX_IC2: 14
+PA6:
+  LCD_SEG3: 11
+  SPI1_MISO: 5
+  TIM10_CH1: 3
+  TIM3_CH1: 2
+  TIMX_IC3: 14
+  TS_G2_IO1: 14
+PA7:
+  LCD_SEG4: 11
+  SPI1_MOSI: 5
+  TIM11_CH1: 3
+  TIM3_CH2: 2
+  TIMX_IC4: 14
+  TS_G2_IO2: 14
+PA8:
+  LCD_COM0: 11
+  RCC_MCO: 0
+  TIMX_IC1: 14
+  TS_G4_IO1: 14
+  USART1_CK: 7
+PA9:
+  LCD_COM1: 11
+  TIMX_IC2: 14
+  TS_G4_IO2: 14
+  USART1_TX: 7
+PB0:
+  LCD_SEG5: 11
+  TIM3_CH3: 2
+  TS_G3_IO1: 14
+PB1:
+  LCD_SEG6: 11
+  TIM3_CH4: 2
+  TS_G3_IO2: 14
+PB10:
+  I2C2_SCL: 4
+  LCD_SEG10: 11
+  TIM2_CH3: 1
+  USART3_TX: 7
+PB11:
+  I2C2_SDA: 4
+  LCD_SEG11: 11
+  TIM2_CH4: 1
+  USART3_RX: 7
+PB12:
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  LCD_SEG12: 11
+  SPI2_NSS: 5
+  TIM10_CH1: 3
+  TS_G7_IO1: 14
+  USART3_CK: 7
+PB13:
+  I2S2_CK: 5
+  LCD_SEG13: 11
+  SPI2_SCK: 5
+  TIM9_CH1: 3
+  TS_G7_IO2: 14
+  USART3_CTS: 7
+PB14:
+  LCD_SEG14: 11
+  SPI2_MISO: 5
+  TIM9_CH2: 3
+  TS_G7_IO3: 14
+  USART3_RTS: 7
+PB15:
+  I2S2_SD: 5
+  LCD_SEG15: 11
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM11_CH1: 3
+  TS_G7_IO4: 14
+PB2:
+  TS_G3_IO3: 14
+PB3:
+  I2S3_CK: 6
+  LCD_SEG7: 11
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-TRACESWO: 0
+  TIM2_CH2: 1
+PB4:
+  LCD_SEG8: 11
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM3_CH1: 2
+  TS_G6_IO1: 14
+PB5:
+  I2C1_SMBA: 4
+  I2S3_SD: 6
+  LCD_SEG9: 11
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM3_CH2: 2
+  TS_G6_IO2: 14
+PB6:
+  I2C1_SCL: 4
+  TIM4_CH1: 2
+  TS_G6_IO3: 14
+  USART1_TX: 7
+PB7:
+  I2C1_SDA: 4
+  TIM4_CH2: 2
+  TS_G6_IO4: 14
+  USART1_RX: 7
+PB8:
+  I2C1_SCL: 4
+  LCD_SEG16: 11
+  TIM10_CH1: 3
+  TIM4_CH3: 2
+PB9:
+  I2C1_SDA: 4
+  LCD_COM3: 11
+  TIM11_CH1: 3
+  TIM4_CH4: 2
+PC0:
+  LCD_SEG18: 11
+  TIMX_IC1: 14
+  TS_G8_IO1: 14
+PC1:
+  LCD_SEG19: 11
+  TIMX_IC2: 14
+  TS_G8_IO2: 14
+PC10:
+  I2S3_CK: 6
+  LCD_COM4: 11
+  LCD_SEG28: 11
+  LCD_SEG40: 11
+  SPI3_SCK: 6
+  TIMX_IC3: 14
+  USART3_TX: 7
+PC11:
+  LCD_COM5: 11
+  LCD_SEG29: 11
+  LCD_SEG41: 11
+  SPI3_MISO: 6
+  TIMX_IC4: 14
+  USART3_RX: 7
+PC12:
+  I2S3_SD: 6
+  LCD_COM6: 11
+  LCD_SEG30: 11
+  LCD_SEG42: 11
+  SPI3_MOSI: 6
+  TIMX_IC1: 14
+  USART3_CK: 7
+PC13:
+  RTC_OUT_ALARM: 0
+  RTC_OUT_CALIB: 0
+  RTC_TAMP1: 0
+  RTC_TS: 0
+  SYS_WKUP2: 0
+  TIMX_IC2: 14
+PC14: {}
+PC15: {}
+PC2:
+  LCD_SEG20: 11
+  TIMX_IC3: 14
+  TS_G8_IO3: 14
+PC3:
+  LCD_SEG21: 11
+  TIMX_IC4: 14
+  TS_G8_IO4: 14
+PC4:
+  LCD_SEG22: 11
+  TIMX_IC1: 14
+  TS_G9_IO1: 14
+PC5:
+  LCD_SEG23: 11
+  TIMX_IC2: 14
+  TS_G9_IO2: 14
+PC6:
+  I2S2_MCK: 5
+  LCD_SEG24: 11
+  TIM3_CH1: 2
+  TIMX_IC3: 14
+  TS_G10_IO1: 14
+PC7:
+  I2S3_MCK: 6
+  LCD_SEG25: 11
+  TIM3_CH2: 2
+  TIMX_IC4: 14
+  TS_G10_IO2: 14
+PC8:
+  LCD_SEG26: 11
+  TIM3_CH3: 2
+  TIMX_IC1: 14
+  TS_G10_IO3: 14
+PC9:
+  LCD_SEG27: 11
+  TIM3_CH4: 2
+  TIMX_IC2: 14
+  TS_G10_IO4: 14
+PD0:
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM9_CH1: 3
+  TIMX_IC1: 14
+PD1:
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIMX_IC2: 14
+PD10:
+  LCD_SEG30: 11
+  TIMX_IC3: 14
+  USART3_CK: 7
+PD11:
+  LCD_SEG31: 11
+  TIMX_IC4: 14
+  USART3_CTS: 7
+PD12:
+  LCD_SEG32: 11
+  TIM4_CH1: 2
+  TIMX_IC1: 14
+  USART3_RTS: 7
+PD13:
+  LCD_SEG33: 11
+  TIM4_CH2: 2
+  TIMX_IC2: 14
+PD14:
+  LCD_SEG34: 11
+  TIM4_CH3: 2
+  TIMX_IC3: 14
+PD15:
+  LCD_SEG35: 11
+  TIM4_CH4: 2
+  TIMX_IC4: 14
+PD2:
+  LCD_COM7: 11
+  LCD_SEG31: 11
+  LCD_SEG43: 11
+  TIM3_ETR: 2
+  TIMX_IC3: 14
+PD3:
+  SPI2_MISO: 5
+  TIMX_IC4: 14
+  USART2_CTS: 7
+PD4:
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIMX_IC1: 14
+  USART2_RTS: 7
+PD5:
+  TIMX_IC2: 14
+  USART2_TX: 7
+PD6:
+  TIMX_IC3: 14
+  USART2_RX: 7
+PD7:
+  TIM9_CH2: 3
+  TIMX_IC4: 14
+  USART2_CK: 7
+PD8:
+  LCD_SEG28: 11
+  TIMX_IC1: 14
+  USART3_TX: 7
+PD9:
+  LCD_SEG29: 11
+  TIMX_IC2: 14
+  USART3_RX: 7
+PE0:
+  LCD_SEG36: 11
+  TIM10_CH1: 3
+  TIM4_ETR: 2
+  TIMX_IC1: 14
+PE1:
+  LCD_SEG37: 11
+  TIM11_CH1: 3
+  TIMX_IC2: 14
+PE10:
+  TIM2_CH2: 1
+  TIMX_IC3: 14
+PE11:
+  TIM2_CH3: 1
+  TIMX_IC4: 14
+PE12:
+  SPI1_NSS: 5
+  TIM2_CH4: 1
+  TIMX_IC1: 14
+PE13:
+  SPI1_SCK: 5
+  TIMX_IC2: 14
+PE14:
+  SPI1_MISO: 5
+  TIMX_IC3: 14
+PE15:
+  SPI1_MOSI: 5
+  TIMX_IC4: 14
+PE2:
+  LCD_SEG38: 11
+  SYS_TRACECK: 0
+  TIM3_ETR: 2
+  TIMX_IC3: 14
+PE3:
+  LCD_SEG39: 11
+  SYS_TRACED0: 0
+  TIM3_CH1: 2
+  TIMX_IC4: 14
+PE4:
+  SYS_TRACED1: 0
+  TIM3_CH2: 2
+  TIMX_IC1: 14
+PE5:
+  SYS_TRACED2: 0
+  TIM9_CH1: 3
+  TIMX_IC2: 14
+PE6:
+  RTC_TAMP3: 0
+  SYS_TRACED3: 0
+  SYS_WKUP3: 0
+  TIM9_CH2: 3
+  TIMX_IC3: 14
+PE7:
+  TIMX_IC4: 14
+PE8:
+  TIMX_IC1: 14
+PE9:
+  TIM2_CH1: 1
+  TIM5_ETR: 2
+  TIMX_IC2: 14
+PH0:
+  RCC_OSC_IN: 0
+PH1:
+  RCC_OSC_OUT: 0
+PH2: {}

data/gpio_af/STM32L15xxA.yaml

@@ -0,0 +1,398 @@
+PA0:
+  RTC_TAMP2: 0
+  SYS_WKUP1: 0
+  TIM2_CH1: 1
+  TIM5_CH1: 2
+  TIMX_IC1: 14
+  TS_G1_IO1: 14
+  USART2_CTS: 7
+PA1:
+  LCD_SEG0: 11
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  TIMX_IC2: 14
+  TS_G1_IO2: 14
+  USART2_RTS: 7
+PA10:
+  LCD_COM2: 11
+  TIMX_IC3: 14
+  TS_G4_IO3: 14
+  USART1_RX: 7
+PA11:
+  SPI1_MISO: 5
+  TIMX_IC4: 14
+  USART1_CTS: 7
+  USB_DM: 10
+PA12:
+  SPI1_MOSI: 5
+  TIMX_IC1: 14
+  USART1_RTS: 7
+  USB_DP: 10
+PA13:
+  SYS_JTMS-SWDIO: 0
+  TIMX_IC2: 14
+  TS_G5_IO1: 14
+PA14:
+  SYS_JTCK-SWCLK: 0
+  TIMX_IC3: 14
+  TS_G5_IO2: 14
+PA15:
+  I2S3_WS: 6
+  LCD_SEG17: 11
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIMX_IC4: 14
+  TS_G5_IO3: 14
+PA2:
+  LCD_SEG1: 11
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  TIM9_CH1: 3
+  TIMX_IC3: 14
+  TS_G1_IO3: 14
+  USART2_TX: 7
+PA3:
+  LCD_SEG2: 11
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  TIM9_CH2: 3
+  TIMX_IC4: 14
+  TS_G1_IO4: 14
+  USART2_RX: 7
+PA4:
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  TIMX_IC1: 14
+  USART2_CK: 7
+PA5:
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIMX_IC2: 14
+PA6:
+  LCD_SEG3: 11
+  SPI1_MISO: 5
+  TIM10_CH1: 3
+  TIM3_CH1: 2
+  TIMX_IC3: 14
+  TS_G2_IO1: 14
+PA7:
+  LCD_SEG4: 11
+  SPI1_MOSI: 5
+  TIM11_CH1: 3
+  TIM3_CH2: 2
+  TIMX_IC4: 14
+  TS_G2_IO2: 14
+PA8:
+  LCD_COM0: 11
+  RCC_MCO: 0
+  TIMX_IC1: 14
+  TS_G4_IO1: 14
+  USART1_CK: 7
+PA9:
+  LCD_COM1: 11
+  TIMX_IC2: 14
+  TS_G4_IO2: 14
+  USART1_TX: 7
+PB0:
+  LCD_SEG5: 11
+  TIM3_CH3: 2
+  TS_G3_IO1: 14
+PB1:
+  LCD_SEG6: 11
+  TIM3_CH4: 2
+  TS_G3_IO2: 14
+PB10:
+  I2C2_SCL: 4
+  LCD_SEG10: 11
+  TIM2_CH3: 1
+  USART3_TX: 7
+PB11:
+  I2C2_SDA: 4
+  LCD_SEG11: 11
+  TIM2_CH4: 1
+  USART3_RX: 7
+PB12:
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  LCD_SEG12: 11
+  SPI2_NSS: 5
+  TIM10_CH1: 3
+  TS_G7_IO1: 14
+  USART3_CK: 7
+PB13:
+  I2S2_CK: 5
+  LCD_SEG13: 11
+  SPI2_SCK: 5
+  TIM9_CH1: 3
+  TS_G7_IO2: 14
+  USART3_CTS: 7
+PB14:
+  LCD_SEG14: 11
+  SPI2_MISO: 5
+  TIM9_CH2: 3
+  TS_G7_IO3: 14
+  USART3_RTS: 7
+PB15:
+  I2S2_SD: 5
+  LCD_SEG15: 11
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM11_CH1: 3
+  TS_G7_IO4: 14
+PB2:
+  TS_G3_IO3: 14
+PB3:
+  I2S3_CK: 6
+  LCD_SEG7: 11
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-TRACESWO: 0
+  TIM2_CH2: 1
+PB4:
+  LCD_SEG8: 11
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM3_CH1: 2
+  TS_G6_IO1: 14
+PB5:
+  I2C1_SMBA: 4
+  I2S3_SD: 6
+  LCD_SEG9: 11
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM3_CH2: 2
+  TS_G6_IO2: 14
+PB6:
+  I2C1_SCL: 4
+  TIM4_CH1: 2
+  TS_G6_IO3: 14
+  USART1_TX: 7
+PB7:
+  I2C1_SDA: 4
+  TIM4_CH2: 2
+  TS_G6_IO4: 14
+  USART1_RX: 7
+PB8:
+  I2C1_SCL: 4
+  LCD_SEG16: 11
+  TIM10_CH1: 3
+  TIM4_CH3: 2
+PB9:
+  I2C1_SDA: 4
+  LCD_COM3: 11
+  TIM11_CH1: 3
+  TIM4_CH4: 2
+PC0:
+  LCD_SEG18: 11
+  TIMX_IC1: 14
+  TS_G8_IO1: 14
+PC1:
+  LCD_SEG19: 11
+  TIMX_IC2: 14
+  TS_G8_IO2: 14
+PC10:
+  I2S3_CK: 6
+  LCD_COM4: 11
+  LCD_SEG28: 11
+  LCD_SEG40: 11
+  SPI3_SCK: 6
+  TIMX_IC3: 14
+  USART3_TX: 7
+PC11:
+  LCD_COM5: 11
+  LCD_SEG29: 11
+  LCD_SEG41: 11
+  SPI3_MISO: 6
+  TIMX_IC4: 14
+  USART3_RX: 7
+PC12:
+  I2S3_SD: 6
+  LCD_COM6: 11
+  LCD_SEG30: 11
+  LCD_SEG42: 11
+  SPI3_MOSI: 6
+  TIMX_IC1: 14
+  USART3_CK: 7
+PC13:
+  RTC_OUT_ALARM: 0
+  RTC_OUT_CALIB: 0
+  RTC_TAMP1: 0
+  RTC_TS: 0
+  SYS_WKUP2: 0
+  TIMX_IC2: 14
+PC14: {}
+PC15: {}
+PC2:
+  LCD_SEG20: 11
+  TIMX_IC3: 14
+  TS_G8_IO3: 14
+PC3:
+  LCD_SEG21: 11
+  TIMX_IC4: 14
+  TS_G8_IO4: 14
+PC4:
+  LCD_SEG22: 11
+  TIMX_IC1: 14
+  TS_G9_IO1: 14
+PC5:
+  LCD_SEG23: 11
+  TIMX_IC2: 14
+  TS_G9_IO2: 14
+PC6:
+  I2S2_MCK: 5
+  LCD_SEG24: 11
+  TIM3_CH1: 2
+  TIMX_IC3: 14
+  TS_G10_IO1: 14
+PC7:
+  I2S3_MCK: 6
+  LCD_SEG25: 11
+  TIM3_CH2: 2
+  TIMX_IC4: 14
+  TS_G10_IO2: 14
+PC8:
+  LCD_SEG26: 11
+  TIM3_CH3: 2
+  TIMX_IC1: 14
+  TS_G10_IO3: 14
+PC9:
+  LCD_SEG27: 11
+  TIM3_CH4: 2
+  TIMX_IC2: 14
+  TS_G10_IO4: 14
+PD0:
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM9_CH1: 3
+  TIMX_IC1: 14
+PD1:
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIMX_IC2: 14
+PD10:
+  LCD_SEG30: 11
+  TIMX_IC3: 14
+  USART3_CK: 7
+PD11:
+  LCD_SEG31: 11
+  TIMX_IC4: 14
+  USART3_CTS: 7
+PD12:
+  LCD_SEG32: 11
+  TIM4_CH1: 2
+  TIMX_IC1: 14
+  USART3_RTS: 7
+PD13:
+  LCD_SEG33: 11
+  TIM4_CH2: 2
+  TIMX_IC2: 14
+PD14:
+  LCD_SEG34: 11
+  TIM4_CH3: 2
+  TIMX_IC3: 14
+PD15:
+  LCD_SEG35: 11
+  TIM4_CH4: 2
+  TIMX_IC4: 14
+PD2:
+  LCD_COM7: 11
+  LCD_SEG31: 11
+  LCD_SEG43: 11
+  TIM3_ETR: 2
+  TIMX_IC3: 14
+PD3:
+  SPI2_MISO: 5
+  TIMX_IC4: 14
+  USART2_CTS: 7
+PD4:
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIMX_IC1: 14
+  USART2_RTS: 7
+PD5:
+  TIMX_IC2: 14
+  USART2_TX: 7
+PD6:
+  TIMX_IC3: 14
+  USART2_RX: 7
+PD7:
+  TIM9_CH2: 3
+  TIMX_IC4: 14
+  USART2_CK: 7
+PD8:
+  LCD_SEG28: 11
+  TIMX_IC1: 14
+  USART3_TX: 7
+PD9:
+  LCD_SEG29: 11
+  TIMX_IC2: 14
+  USART3_RX: 7
+PE0:
+  LCD_SEG36: 11
+  TIM10_CH1: 3
+  TIM4_ETR: 2
+  TIMX_IC1: 14
+PE1:
+  LCD_SEG37: 11
+  TIM11_CH1: 3
+  TIMX_IC2: 14
+PE10:
+  TIM2_CH2: 1
+  TIMX_IC3: 14
+PE11:
+  TIM2_CH3: 1
+  TIMX_IC4: 14
+PE12:
+  SPI1_NSS: 5
+  TIM2_CH4: 1
+  TIMX_IC1: 14
+PE13:
+  SPI1_SCK: 5
+  TIMX_IC2: 14
+PE14:
+  SPI1_MISO: 5
+  TIMX_IC3: 14
+PE15:
+  SPI1_MOSI: 5
+  TIMX_IC4: 14
+PE2:
+  LCD_SEG38: 11
+  SYS_TRACECK: 0
+  TIM3_ETR: 2
+  TIMX_IC3: 14
+PE3:
+  LCD_SEG39: 11
+  SYS_TRACED0: 0
+  TIM3_CH1: 2
+  TIMX_IC4: 14
+PE4:
+  SYS_TRACED1: 0
+  TIM3_CH2: 2
+  TIMX_IC1: 14
+PE5:
+  SYS_TRACED2: 0
+  TIM9_CH1: 3
+  TIMX_IC2: 14
+PE6:
+  RTC_TAMP3: 0
+  SYS_TRACED3: 0
+  SYS_WKUP3: 0
+  TIM9_CH2: 3
+  TIMX_IC3: 14
+PE7:
+  TIMX_IC4: 14
+PE8:
+  TIMX_IC1: 14
+PE9:
+  TIM2_CH1: 1
+  TIM5_ETR: 2
+  TIMX_IC2: 14
+PH0:
+  RCC_OSC_IN: 0
+PH1:
+  RCC_OSC_OUT: 0
+PH2: {}

data/gpio_af/STM32L162xD.yaml

@@ -0,0 +1,532 @@
+PA0:
+  RTC_TAMP2: 0
+  SYS_WKUP1: 0
+  TIM2_CH1: 1
+  TIM5_CH1: 2
+  TIMX_IC1: 14
+  TS_G1_IO1: 14
+  USART2_CTS: 7
+PA1:
+  LCD_SEG0: 11
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  TIMX_IC2: 14
+  TS_G1_IO2: 14
+  USART2_RTS: 7
+PA10:
+  LCD_COM2: 11
+  TIMX_IC3: 14
+  TS_G4_IO3: 14
+  USART1_RX: 7
+PA11:
+  SPI1_MISO: 5
+  TIMX_IC4: 14
+  USART1_CTS: 7
+  USB_DM: 10
+PA12:
+  SPI1_MOSI: 5
+  TIMX_IC1: 14
+  USART1_RTS: 7
+  USB_DP: 10
+PA13:
+  SYS_JTMS-SWDIO: 0
+  TIMX_IC2: 14
+  TS_G5_IO1: 14
+PA14:
+  SYS_JTCK-SWCLK: 0
+  TIMX_IC3: 14
+  TS_G5_IO2: 14
+PA15:
+  I2S3_WS: 6
+  LCD_SEG17: 11
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIMX_IC4: 14
+  TS_G5_IO3: 14
+PA2:
+  LCD_SEG1: 11
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  TIM9_CH1: 3
+  TIMX_IC3: 14
+  TS_G1_IO3: 14
+  USART2_TX: 7
+PA3:
+  LCD_SEG2: 11
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  TIM9_CH2: 3
+  TIMX_IC4: 14
+  TS_G1_IO4: 14
+  USART2_RX: 7
+PA4:
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  TIMX_IC1: 14
+  USART2_CK: 7
+PA5:
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIMX_IC2: 14
+PA6:
+  LCD_SEG3: 11
+  SPI1_MISO: 5
+  TIM10_CH1: 3
+  TIM3_CH1: 2
+  TIMX_IC3: 14
+  TS_G2_IO1: 14
+PA7:
+  LCD_SEG4: 11
+  SPI1_MOSI: 5
+  TIM11_CH1: 3
+  TIM3_CH2: 2
+  TIMX_IC4: 14
+  TS_G2_IO2: 14
+PA8:
+  LCD_COM0: 11
+  RCC_MCO: 0
+  TIMX_IC1: 14
+  TS_G4_IO1: 14
+  USART1_CK: 7
+PA9:
+  LCD_COM1: 11
+  TIMX_IC2: 14
+  TS_G4_IO2: 14
+  USART1_TX: 7
+PB0:
+  LCD_SEG5: 11
+  TIM3_CH3: 2
+  TS_G3_IO1: 14
+PB1:
+  LCD_SEG6: 11
+  TIM3_CH4: 2
+  TS_G3_IO2: 14
+PB10:
+  I2C2_SCL: 4
+  LCD_SEG10: 11
+  TIM2_CH3: 1
+  USART3_TX: 7
+PB11:
+  I2C2_SDA: 4
+  LCD_SEG11: 11
+  TIM2_CH4: 1
+  USART3_RX: 7
+PB12:
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  LCD_SEG12: 11
+  SPI2_NSS: 5
+  TIM10_CH1: 3
+  TS_G7_IO1: 14
+  USART3_CK: 7
+PB13:
+  I2S2_CK: 5
+  LCD_SEG13: 11
+  SPI2_SCK: 5
+  TIM9_CH1: 3
+  TS_G7_IO2: 14
+  USART3_CTS: 7
+PB14:
+  LCD_SEG14: 11
+  SPI2_MISO: 5
+  TIM9_CH2: 3
+  TS_G7_IO3: 14
+  USART3_RTS: 7
+PB15:
+  I2S2_SD: 5
+  LCD_SEG15: 11
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM11_CH1: 3
+  TS_G7_IO4: 14
+PB2:
+  TS_G3_IO3: 14
+PB3:
+  I2S3_CK: 6
+  LCD_SEG7: 11
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-TRACESWO: 0
+  TIM2_CH2: 1
+PB4:
+  LCD_SEG8: 11
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM3_CH1: 2
+  TS_G6_IO1: 14
+PB5:
+  I2C1_SMBA: 4
+  I2S3_SD: 6
+  LCD_SEG9: 11
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM3_CH2: 2
+  TS_G6_IO2: 14
+PB6:
+  I2C1_SCL: 4
+  TIM4_CH1: 2
+  TS_G6_IO3: 14
+  USART1_TX: 7
+PB7:
+  FSMC_NL: 12
+  I2C1_SDA: 4
+  TIM4_CH2: 2
+  TS_G6_IO4: 14
+  USART1_RX: 7
+PB8:
+  I2C1_SCL: 4
+  LCD_SEG16: 11
+  SDIO_D4: 12
+  TIM10_CH1: 3
+  TIM4_CH3: 2
+PB9:
+  I2C1_SDA: 4
+  LCD_COM3: 11
+  SDIO_D5: 12
+  TIM11_CH1: 3
+  TIM4_CH4: 2
+PC0:
+  LCD_SEG18: 11
+  TIMX_IC1: 14
+  TS_G8_IO1: 14
+PC1:
+  LCD_SEG19: 11
+  TIMX_IC2: 14
+  TS_G8_IO2: 14
+PC10:
+  I2S3_CK: 6
+  LCD_COM4: 11
+  LCD_SEG28: 11
+  LCD_SEG40: 11
+  SDIO_D2: 12
+  SPI3_SCK: 6
+  TIMX_IC3: 14
+  UART4_TX: 8
+  USART3_TX: 7
+PC11:
+  LCD_COM5: 11
+  LCD_SEG29: 11
+  LCD_SEG41: 11
+  SDIO_D3: 12
+  SPI3_MISO: 6
+  TIMX_IC4: 14
+  UART4_RX: 8
+  USART3_RX: 7
+PC12:
+  I2S3_SD: 6
+  LCD_COM6: 11
+  LCD_SEG30: 11
+  LCD_SEG42: 11
+  SDIO_CK: 12
+  SPI3_MOSI: 6
+  TIMX_IC1: 14
+  UART5_TX: 8
+  USART3_CK: 7
+PC13:
+  RTC_OUT_ALARM: 0
+  RTC_OUT_CALIB: 0
+  RTC_TAMP1: 0
+  RTC_TS: 0
+  SYS_WKUP2: 0
+  TIMX_IC2: 14
+PC14: {}
+PC15: {}
+PC2:
+  LCD_SEG20: 11
+  TIMX_IC3: 14
+  TS_G8_IO3: 14
+PC3:
+  LCD_SEG21: 11
+  TIMX_IC4: 14
+  TS_G8_IO4: 14
+PC4:
+  LCD_SEG22: 11
+  TIMX_IC1: 14
+  TS_G9_IO1: 14
+PC5:
+  LCD_SEG23: 11
+  TIMX_IC2: 14
+  TS_G9_IO2: 14
+PC6:
+  I2S2_MCK: 5
+  LCD_SEG24: 11
+  SDIO_D6: 12
+  TIM3_CH1: 2
+  TIMX_IC3: 14
+  TS_G10_IO1: 14
+PC7:
+  I2S3_MCK: 6
+  LCD_SEG25: 11
+  SDIO_D7: 12
+  TIM3_CH2: 2
+  TIMX_IC4: 14
+  TS_G10_IO2: 14
+PC8:
+  LCD_SEG26: 11
+  SDIO_D0: 12
+  TIM3_CH3: 2
+  TIMX_IC1: 14
+  TS_G10_IO3: 14
+PC9:
+  LCD_SEG27: 11
+  SDIO_D1: 12
+  TIM3_CH4: 2
+  TIMX_IC2: 14
+  TS_G10_IO4: 14
+PD0:
+  FSMC_D2: 12
+  FSMC_DA2: 12
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM9_CH1: 3
+  TIMX_IC1: 14
+PD1:
+  FSMC_D3: 12
+  FSMC_DA3: 12
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIMX_IC2: 14
+PD10:
+  FSMC_D15: 12
+  FSMC_DA15: 12
+  LCD_SEG30: 11
+  TIMX_IC3: 14
+  USART3_CK: 7
+PD11:
+  FSMC_A16: 12
+  LCD_SEG31: 11
+  TIMX_IC4: 14
+  USART3_CTS: 7
+PD12:
+  FSMC_A17: 12
+  LCD_SEG32: 11
+  TIM4_CH1: 2
+  TIMX_IC1: 14
+  USART3_RTS: 7
+PD13:
+  FSMC_A18: 12
+  LCD_SEG33: 11
+  TIM4_CH2: 2
+  TIMX_IC2: 14
+PD14:
+  FSMC_D0: 12
+  FSMC_DA0: 12
+  LCD_SEG34: 11
+  TIM4_CH3: 2
+  TIMX_IC3: 14
+PD15:
+  FSMC_D1: 12
+  FSMC_DA1: 12
+  LCD_SEG35: 11
+  TIM4_CH4: 2
+  TIMX_IC4: 14
+PD2:
+  LCD_COM7: 11
+  LCD_SEG31: 11
+  LCD_SEG43: 11
+  SDIO_CMD: 12
+  TIM3_ETR: 2
+  TIMX_IC3: 14
+  UART5_RX: 8
+PD3:
+  FSMC_CLK: 12
+  SPI2_MISO: 5
+  TIMX_IC4: 14
+  USART2_CTS: 7
+PD4:
+  FSMC_NOE: 12
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIMX_IC1: 14
+  USART2_RTS: 7
+PD5:
+  FSMC_NWE: 12
+  TIMX_IC2: 14
+  USART2_TX: 7
+PD6:
+  FSMC_NWAIT: 12
+  TIMX_IC3: 14
+  USART2_RX: 7
+PD7:
+  FSMC_NE1: 12
+  TIM9_CH2: 3
+  TIMX_IC4: 14
+  USART2_CK: 7
+PD8:
+  FSMC_D13: 12
+  FSMC_DA13: 12
+  LCD_SEG28: 11
+  TIMX_IC1: 14
+  USART3_TX: 7
+PD9:
+  FSMC_D14: 12
+  FSMC_DA14: 12
+  LCD_SEG29: 11
+  TIMX_IC2: 14
+  USART3_RX: 7
+PE0:
+  FSMC_NBL0: 12
+  LCD_SEG36: 11
+  TIM10_CH1: 3
+  TIM4_ETR: 2
+  TIMX_IC1: 14
+PE1:
+  FSMC_NBL1: 12
+  LCD_SEG37: 11
+  TIM11_CH1: 3
+  TIMX_IC2: 14
+PE10:
+  FSMC_D7: 12
+  FSMC_DA7: 12
+  TIM2_CH2: 1
+  TIMX_IC3: 14
+PE11:
+  FSMC_D8: 12
+  FSMC_DA8: 12
+  TIM2_CH3: 1
+  TIMX_IC4: 14
+PE12:
+  FSMC_D9: 12
+  FSMC_DA9: 12
+  SPI1_NSS: 5
+  TIM2_CH4: 1
+  TIMX_IC1: 14
+PE13:
+  FSMC_D10: 12
+  FSMC_DA10: 12
+  SPI1_SCK: 5
+  TIMX_IC2: 14
+PE14:
+  FSMC_D11: 12
+  FSMC_DA11: 12
+  SPI1_MISO: 5
+  TIMX_IC3: 14
+PE15:
+  FSMC_D12: 12
+  FSMC_DA12: 12
+  SPI1_MOSI: 5
+  TIMX_IC4: 14
+PE2:
+  FSMC_A23: 12
+  LCD_SEG38: 11
+  SYS_TRACECK: 0
+  TIM3_ETR: 2
+  TIMX_IC3: 14
+PE3:
+  FSMC_A19: 12
+  LCD_SEG39: 11
+  SYS_TRACED0: 0
+  TIM3_CH1: 2
+  TIMX_IC4: 14
+PE4:
+  FSMC_A20: 12
+  SYS_TRACED1: 0
+  TIM3_CH2: 2
+  TIMX_IC1: 14
+PE5:
+  FSMC_A21: 12
+  SYS_TRACED2: 0
+  TIM9_CH1: 3
+  TIMX_IC2: 14
+PE6:
+  RTC_TAMP3: 0
+  SYS_TRACED3: 0
+  SYS_WKUP3: 0
+  TIM9_CH2: 3
+  TIMX_IC3: 14
+PE7:
+  FSMC_D4: 12
+  FSMC_DA4: 12
+  TIMX_IC4: 14
+PE8:
+  FSMC_D5: 12
+  FSMC_DA5: 12
+  TIMX_IC1: 14
+PE9:
+  FSMC_D6: 12
+  FSMC_DA6: 12
+  TIM2_CH1: 1
+  TIMX_IC2: 14
+PF0:
+  FSMC_A0: 12
+PF1:
+  FSMC_A1: 12
+PF10:
+  TS_G11_IO5: 14
+PF11:
+  TS_G3_IO4: 14
+PF12:
+  FSMC_A6: 12
+  TS_G3_IO5: 14
+PF13:
+  FSMC_A7: 12
+  TS_G9_IO3: 14
+PF14:
+  FSMC_A8: 12
+  TS_G9_IO4: 14
+PF15:
+  FSMC_A9: 12
+  TS_G2_IO3: 14
+PF2:
+  FSMC_A2: 12
+PF3:
+  FSMC_A3: 12
+PF4:
+  FSMC_A4: 12
+PF5:
+  FSMC_A5: 12
+PF6:
+  TIM5_CH1: 2
+  TIM5_ETR: 2
+  TS_G11_IO1: 14
+PF7:
+  TIM5_CH2: 2
+  TS_G11_IO2: 14
+PF8:
+  TIM5_CH3: 2
+  TS_G11_IO3: 14
+PF9:
+  TIM5_CH4: 2
+  TS_G11_IO4: 14
+PG0:
+  FSMC_A10: 12
+  TS_G2_IO4: 14
+PG1:
+  FSMC_A11: 12
+  TS_G2_IO5: 14
+PG10:
+  FSMC_NE3: 12
+PG11: {}
+PG12:
+  FSMC_NE4: 12
+PG13:
+  FSMC_A24: 12
+PG14:
+  FSMC_A25: 12
+PG15: {}
+PG2:
+  FSMC_A12: 12
+  TS_G7_IO5: 14
+PG3:
+  FSMC_A13: 12
+  TS_G7_IO6: 14
+PG4:
+  FSMC_A14: 12
+  TS_G7_IO7: 14
+PG5:
+  FSMC_A15: 12
+PG6: {}
+PG7: {}
+PG8: {}
+PG9:
+  FSMC_NE2: 12
+PH0:
+  RCC_OSC_IN: 0
+PH1:
+  RCC_OSC_OUT: 0
+PH2:
+  FSMC_A22: 12

data/gpio_af/STM32L162xE.yaml

@@ -0,0 +1,492 @@
+PA0:
+  COMP1_INP: 14
+  RTC_TAMP2: 0
+  SYS_WKUP1: 0
+  TIM2_CH1: 1
+  TIM5_CH1: 2
+  TIMX_IC1: 14
+  TS_G1_IO1: 14
+  USART2_CTS: 7
+PA1:
+  COMP1_INP: 14
+  LCD_SEG0: 11
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  TIMX_IC2: 14
+  TS_G1_IO2: 14
+  USART2_RTS: 7
+PA10:
+  LCD_COM2: 11
+  TIMX_IC3: 14
+  TS_G4_IO3: 14
+  USART1_RX: 7
+PA11:
+  SPI1_MISO: 5
+  TIMX_IC4: 14
+  USART1_CTS: 7
+  USB_DM: 10
+PA12:
+  SPI1_MOSI: 5
+  TIMX_IC1: 14
+  USART1_RTS: 7
+  USB_DP: 10
+PA13:
+  SYS_JTMS-SWDIO: 0
+  TIMX_IC2: 14
+  TS_G5_IO1: 14
+PA14:
+  SYS_JTCK-SWCLK: 0
+  TIMX_IC3: 14
+  TS_G5_IO2: 14
+PA15:
+  I2S3_WS: 6
+  LCD_SEG17: 11
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIMX_IC4: 14
+  TS_G5_IO3: 14
+PA2:
+  COMP1_INP: 14
+  LCD_SEG1: 11
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  TIM9_CH1: 3
+  TIMX_IC3: 14
+  TS_G1_IO3: 14
+  USART2_TX: 7
+PA3:
+  COMP1_INP: 14
+  LCD_SEG2: 11
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  TIM9_CH2: 3
+  TIMX_IC4: 14
+  TS_G1_IO4: 14
+  USART2_RX: 7
+PA4:
+  COMP1_INP: 14
+  I2S3_WS: 6
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  TIMX_IC1: 14
+  USART2_CK: 7
+PA5:
+  COMP1_INP: 14
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIMX_IC2: 14
+PA6:
+  COMP1_INP: 14
+  LCD_SEG3: 11
+  SPI1_MISO: 5
+  TIM10_CH1: 3
+  TIM3_CH1: 2
+  TIMX_IC3: 14
+  TS_G2_IO1: 14
+PA7:
+  COMP1_INP: 14
+  LCD_SEG4: 11
+  SPI1_MOSI: 5
+  TIM11_CH1: 3
+  TIM3_CH2: 2
+  TIMX_IC4: 14
+  TS_G2_IO2: 14
+PA8:
+  LCD_COM0: 11
+  RCC_MCO: 0
+  TIMX_IC1: 14
+  TS_G4_IO1: 14
+  USART1_CK: 7
+PA9:
+  LCD_COM1: 11
+  TIMX_IC2: 14
+  TS_G4_IO2: 14
+  USART1_TX: 7
+PB0:
+  COMP1_INP: 14
+  LCD_SEG5: 11
+  SYS_V_REF_OUT: 14
+  TIM3_CH3: 2
+  TS_G3_IO1: 14
+  V_REF_OUT: 0
+PB1:
+  COMP1_INP: 14
+  LCD_SEG6: 11
+  SYS_V_REF_OUT: 14
+  TIM3_CH4: 2
+  TS_G3_IO2: 14
+  V_REF_OUT: 0
+PB10:
+  I2C2_SCL: 4
+  LCD_SEG10: 11
+  TIM2_CH3: 1
+  USART3_TX: 7
+PB11:
+  I2C2_SDA: 4
+  LCD_SEG11: 11
+  TIM2_CH4: 1
+  USART3_RX: 7
+PB12:
+  COMP1_INP: 14
+  I2C2_SMBA: 4
+  I2S2_WS: 5
+  LCD_SEG12: 11
+  SPI2_NSS: 5
+  TIM10_CH1: 3
+  TS_G7_IO1: 14
+  USART3_CK: 7
+PB13:
+  COMP1_INP: 14
+  I2S2_CK: 5
+  LCD_SEG13: 11
+  SPI2_SCK: 5
+  TIM9_CH1: 3
+  TS_G7_IO2: 14
+  USART3_CTS: 7
+PB14:
+  COMP1_INP: 14
+  LCD_SEG14: 11
+  SPI2_MISO: 5
+  TIM9_CH2: 3
+  TS_G7_IO3: 14
+  USART3_RTS: 7
+PB15:
+  COMP1_INP: 14
+  I2S2_SD: 5
+  LCD_SEG15: 11
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM11_CH1: 3
+  TS_G7_IO4: 14
+PB2:
+  TS_G3_IO3: 14
+PB3:
+  COMP2_INM: 14
+  I2S3_CK: 6
+  LCD_SEG7: 11
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-TRACESWO: 0
+  TIM2_CH2: 1
+PB4:
+  COMP2_INP: 14
+  LCD_SEG8: 11
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM3_CH1: 2
+  TS_G6_IO1: 14
+PB5:
+  COMP2_INP: 14
+  I2C1_SMBA: 4
+  I2S3_SD: 6
+  LCD_SEG9: 11
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM3_CH2: 2
+  TS_G6_IO2: 14
+PB6:
+  COMP2_INP: 14
+  I2C1_SCL: 4
+  TIM4_CH1: 2
+  TS_G6_IO3: 14
+  USART1_TX: 7
+PB7:
+  COMP2_INP: 14
+  I2C1_SDA: 4
+  SYS_PVD_IN: 14
+  TIM4_CH2: 2
+  TS_G6_IO4: 14
+  USART1_RX: 7
+  V_REF_PVD_IN: 0
+PB8:
+  I2C1_SCL: 4
+  LCD_SEG16: 11
+  TIM10_CH1: 3
+  TIM4_CH3: 2
+PB9:
+  I2C1_SDA: 4
+  LCD_COM3: 11
+  TIM11_CH1: 3
+  TIM4_CH4: 2
+PC0:
+  COMP1_INP: 14
+  LCD_SEG18: 11
+  TIMX_IC1: 14
+  TS_G8_IO1: 14
+PC1:
+  COMP1_INP: 14
+  LCD_SEG19: 11
+  TIMX_IC2: 14
+  TS_G8_IO2: 14
+PC10:
+  I2S3_CK: 6
+  LCD_COM4: 11
+  LCD_SEG28: 11
+  LCD_SEG40: 11
+  SPI3_SCK: 6
+  TIMX_IC3: 14
+  UART4_TX: 8
+  USART3_TX: 7
+PC11:
+  LCD_COM5: 11
+  LCD_SEG29: 11
+  LCD_SEG41: 11
+  SPI3_MISO: 6
+  TIMX_IC4: 14
+  UART4_RX: 8
+  USART3_RX: 7
+PC12:
+  I2S3_SD: 6
+  LCD_COM6: 11
+  LCD_SEG30: 11
+  LCD_SEG42: 11
+  SPI3_MOSI: 6
+  TIMX_IC1: 14
+  UART5_TX: 8
+  USART3_CK: 7
+PC13:
+  RTC_OUT_ALARM: 0
+  RTC_OUT_CALIB: 0
+  RTC_TAMP1: 0
+  RTC_TS: 0
+  SYS_WKUP2: 0
+  TIMX_IC2: 14
+PC14: {}
+PC15: {}
+PC2:
+  COMP1_INP: 14
+  LCD_SEG20: 11
+  TIMX_IC3: 14
+  TS_G8_IO3: 14
+PC3:
+  COMP1_INP: 14
+  LCD_SEG21: 11
+  TIMX_IC4: 14
+  TS_G8_IO4: 14
+PC4:
+  COMP1_INP: 14
+  LCD_SEG22: 11
+  TIMX_IC1: 14
+  TS_G9_IO1: 14
+PC5:
+  COMP1_INP: 14
+  LCD_SEG23: 11
+  TIMX_IC2: 14
+  TS_G9_IO2: 14
+PC6:
+  I2S2_MCK: 5
+  LCD_SEG24: 11
+  TIM3_CH1: 2
+  TIMX_IC3: 14
+  TS_G10_IO1: 14
+PC7:
+  I2S3_MCK: 6
+  LCD_SEG25: 11
+  TIM3_CH2: 2
+  TIMX_IC4: 14
+  TS_G10_IO2: 14
+PC8:
+  LCD_SEG26: 11
+  TIM3_CH3: 2
+  TIMX_IC1: 14
+  TS_G10_IO3: 14
+PC9:
+  LCD_SEG27: 11
+  TIM3_CH4: 2
+  TIMX_IC2: 14
+  TS_G10_IO4: 14
+PD0:
+  I2S2_WS: 5
+  SPI2_NSS: 5
+  TIM9_CH1: 3
+  TIMX_IC1: 14
+PD1:
+  I2S2_CK: 5
+  SPI2_SCK: 5
+  TIMX_IC2: 14
+PD10:
+  LCD_SEG30: 11
+  TIMX_IC3: 14
+  USART3_CK: 7
+PD11:
+  LCD_SEG31: 11
+  TIMX_IC4: 14
+  USART3_CTS: 7
+PD12:
+  LCD_SEG32: 11
+  TIM4_CH1: 2
+  TIMX_IC1: 14
+  USART3_RTS: 7
+PD13:
+  LCD_SEG33: 11
+  TIM4_CH2: 2
+  TIMX_IC2: 14
+PD14:
+  LCD_SEG34: 11
+  TIM4_CH3: 2
+  TIMX_IC3: 14
+PD15:
+  LCD_SEG35: 11
+  TIM4_CH4: 2
+  TIMX_IC4: 14
+PD2:
+  LCD_COM7: 11
+  LCD_SEG31: 11
+  LCD_SEG43: 11
+  TIM3_ETR: 2
+  TIMX_IC3: 14
+  UART5_RX: 8
+PD3:
+  SPI2_MISO: 5
+  TIMX_IC4: 14
+  USART2_CTS: 7
+PD4:
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIMX_IC1: 14
+  USART2_RTS: 7
+PD5:
+  TIMX_IC2: 14
+  USART2_TX: 7
+PD6:
+  TIMX_IC3: 14
+  USART2_RX: 7
+PD7:
+  TIM9_CH2: 3
+  TIMX_IC4: 14
+  USART2_CK: 7
+PD8:
+  LCD_SEG28: 11
+  TIMX_IC1: 14
+  USART3_TX: 7
+PD9:
+  LCD_SEG29: 11
+  TIMX_IC2: 14
+  USART3_RX: 7
+PE0:
+  LCD_SEG36: 11
+  TIM10_CH1: 3
+  TIM4_ETR: 2
+  TIMX_IC1: 14
+PE1:
+  LCD_SEG37: 11
+  TIM11_CH1: 3
+  TIMX_IC2: 14
+PE10:
+  COMP1_INP: 14
+  TIM2_CH2: 1
+  TIMX_IC3: 14
+PE11:
+  TIM2_CH3: 1
+  TIMX_IC4: 14
+PE12:
+  SPI1_NSS: 5
+  TIM2_CH4: 1
+  TIMX_IC1: 14
+PE13:
+  SPI1_SCK: 5
+  TIMX_IC2: 14
+PE14:
+  SPI1_MISO: 5
+  TIMX_IC3: 14
+PE15:
+  SPI1_MOSI: 5
+  TIMX_IC4: 14
+PE2:
+  LCD_SEG38: 11
+  SYS_TRACECK: 0
+  TIM3_ETR: 2
+  TIMX_IC3: 14
+PE3:
+  LCD_SEG39: 11
+  SYS_TRACED0: 0
+  TIM3_CH1: 2
+  TIMX_IC4: 14
+PE4:
+  SYS_TRACED1: 0
+  TIM3_CH2: 2
+  TIMX_IC1: 14
+PE5:
+  SYS_TRACED2: 0
+  TIM9_CH1: 3
+  TIMX_IC2: 14
+PE6:
+  RTC_TAMP3: 0
+  SYS_TRACED3: 0
+  SYS_WKUP3: 0
+  TIM9_CH2: 3
+  TIMX_IC3: 14
+PE7:
+  COMP1_INP: 14
+  TIMX_IC4: 14
+PE8:
+  COMP1_INP: 14
+  TIMX_IC1: 14
+PE9:
+  COMP1_INP: 14
+  TIM2_CH1: 1
+  TIMX_IC2: 14
+PF0: {}
+PF1: {}
+PF10:
+  COMP1_INP: 14
+  TS_G11_IO5: 14
+PF11:
+  TS_G3_IO4: 14
+PF12:
+  TS_G3_IO5: 14
+PF13:
+  TS_G9_IO3: 14
+PF14:
+  TS_G9_IO4: 14
+PF15:
+  TS_G2_IO3: 14
+PF2: {}
+PF3: {}
+PF4: {}
+PF5: {}
+PF6:
+  COMP1_INP: 14
+  TIM5_CH1: 2
+  TS_G11_IO1: 14
+PF7:
+  COMP1_INP: 14
+  TIM5_CH2: 2
+  TS_G11_IO2: 14
+PF8:
+  COMP1_INP: 14
+  TIM5_CH3: 2
+  TS_G11_IO3: 14
+PF9:
+  COMP1_INP: 14
+  TIM5_CH4: 2
+  TS_G11_IO4: 14
+PG0:
+  TS_G2_IO4: 14
+PG1:
+  TS_G2_IO5: 14
+PG10: {}
+PG11: {}
+PG12: {}
+PG13: {}
+PG14: {}
+PG15: {}
+PG2:
+  TS_G7_IO5: 14
+PG3:
+  TS_G7_IO6: 14
+PG4:
+  TS_G7_IO7: 14
+PG5: {}
+PG6: {}
+PG7: {}
+PG8: {}
+PG9: {}
+PH0:
+  RCC_OSC_IN: 0
+PH1:
+  RCC_OSC_OUT: 0
+PH2: {}

data/gpio_af/STM32L41x.yaml

@@ -0,0 +1,305 @@
+PA0:
+  COMP1_OUT: 12
+  EVENTOUT: 15
+  TIM2_CH1: 1
+  TIM2_ETR: 14
+  USART2_CTS: 7
+PA1:
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  SPI1_SCK: 5
+  TIM15_CH1N: 14
+  TIM2_CH2: 1
+  USART2_DE: 7
+  USART2_RTS: 7
+PA10:
+  CRS_SYNC: 10
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  TIM1_CH3: 1
+  USART1_RX: 7
+PA11:
+  COMP1_OUT: 6
+  EVENTOUT: 15
+  SPI1_MISO: 5
+  TIM1_BKIN2: 2
+  TIM1_BKIN2_COMP1: 12
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USB_DM: 10
+PA12:
+  EVENTOUT: 15
+  SPI1_MOSI: 5
+  TIM1_ETR: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+  USB_DP: 10
+PA13:
+  EVENTOUT: 15
+  IR_OUT: 1
+  SYS_JTMS-SWDIO: 0
+  USB_NOE: 10
+PA14:
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  LPTIM1_OUT: 1
+  SYS_JTCK-SWCLK: 0
+PA15:
+  EVENTOUT: 15
+  SPI1_NSS: 5
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+  TSC_G3_IO1: 9
+  USART2_RX: 3
+  USART3_DE: 7
+  USART3_RTS: 7
+PA2:
+  EVENTOUT: 15
+  LPUART1_TX: 8
+  QUADSPI_BK1_NCS: 10
+  TIM15_CH1: 14
+  TIM2_CH3: 1
+  USART2_TX: 7
+PA3:
+  EVENTOUT: 15
+  LPUART1_RX: 8
+  QUADSPI_CLK: 10
+  TIM15_CH2: 14
+  TIM2_CH4: 1
+  USART2_RX: 7
+PA4:
+  EVENTOUT: 15
+  LPTIM2_OUT: 14
+  SPI1_NSS: 5
+  USART2_CK: 7
+PA5:
+  EVENTOUT: 15
+  LPTIM2_ETR: 14
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+PA6:
+  COMP1_OUT: 6
+  EVENTOUT: 15
+  LPUART1_CTS: 8
+  QUADSPI_BK1_IO3: 10
+  SPI1_MISO: 5
+  TIM16_CH1: 14
+  TIM1_BKIN: 1
+  USART3_CTS: 7
+PA7:
+  EVENTOUT: 15
+  I2C3_SCL: 4
+  QUADSPI_BK1_IO2: 10
+  SPI1_MOSI: 5
+  TIM1_CH1N: 1
+PA8:
+  EVENTOUT: 15
+  LPTIM2_OUT: 14
+  RCC_MCO: 0
+  TIM1_CH1: 1
+  USART1_CK: 7
+PA9:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  TIM15_BKIN: 14
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  COMP1_OUT: 12
+  EVENTOUT: 15
+  QUADSPI_BK1_IO1: 10
+  SPI1_NSS: 5
+  SYS_TRACED0: 0
+  TIM1_CH2N: 1
+  USART3_CK: 7
+PB1:
+  EVENTOUT: 15
+  LPTIM2_IN1: 14
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+  QUADSPI_BK1_IO0: 10
+  SYS_TRACED1: 0
+  TIM1_CH3N: 1
+  USART3_DE: 7
+  USART3_RTS: 7
+PB10:
+  COMP1_OUT: 12
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  LPUART1_RX: 8
+  QUADSPI_CLK: 10
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+  TSC_SYNC: 9
+  USART3_TX: 7
+PB11:
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  LPUART1_TX: 8
+  QUADSPI_BK1_NCS: 10
+  TIM2_CH4: 1
+  USART3_RX: 7
+PB12:
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+  SPI2_NSS: 5
+  TIM15_BKIN: 14
+  TIM1_BKIN: 1
+  TSC_G1_IO1: 9
+  USART3_CK: 7
+PB13:
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  LPUART1_CTS: 8
+  SPI2_SCK: 5
+  TIM15_CH1N: 14
+  TIM1_CH1N: 1
+  TSC_G1_IO2: 9
+  USART3_CTS: 7
+PB14:
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  SPI2_MISO: 5
+  TIM15_CH1: 14
+  TIM1_CH2N: 1
+  TSC_G1_IO3: 9
+  USART3_DE: 7
+  USART3_RTS: 7
+PB15:
+  EVENTOUT: 15
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM15_CH2: 14
+  TIM1_CH3N: 1
+  TSC_G1_IO4: 9
+PB2:
+  EVENTOUT: 15
+  I2C3_SMBA: 4
+  LPTIM1_OUT: 1
+  RTC_OUT2: 0
+  RTC_OUT_CALIB: 0
+PB3:
+  EVENTOUT: 15
+  SPI1_SCK: 5
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+PB4:
+  EVENTOUT: 15
+  I2C3_SDA: 4
+  SPI1_MISO: 5
+  SYS_JTRST: 0
+  TSC_G2_IO1: 9
+  USART1_CTS: 7
+PB5:
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  LPTIM1_IN1: 1
+  SPI1_MOSI: 5
+  SYS_TRACED2: 0
+  TIM16_BKIN: 14
+  TSC_G2_IO2: 9
+  USART1_CK: 7
+PB6:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  LPTIM1_ETR: 1
+  SYS_TRACED3: 0
+  TIM16_CH1N: 14
+  TSC_G2_IO3: 9
+  USART1_TX: 7
+PB7:
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  LPTIM1_IN2: 1
+  SYS_TRACECLK: 0
+  TSC_G2_IO4: 9
+  USART1_RX: 7
+PB8:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  TIM16_CH1: 14
+PB9:
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  IR_OUT: 1
+  SPI2_NSS: 5
+PC0:
+  EVENTOUT: 15
+  I2C3_SCL: 4
+  LPTIM1_IN1: 1
+  LPTIM2_IN1: 14
+  LPUART1_RX: 8
+  SYS_TRACECLK: 0
+PC1:
+  EVENTOUT: 15
+  I2C3_SDA: 4
+  LPTIM1_OUT: 1
+  LPUART1_TX: 8
+  SYS_TRACED0: 0
+PC10:
+  EVENTOUT: 15
+  SYS_TRACED1: 0
+  TSC_G3_IO2: 9
+  USART3_TX: 7
+PC11:
+  EVENTOUT: 15
+  TSC_G3_IO3: 9
+  USART3_RX: 7
+PC12:
+  EVENTOUT: 15
+  SYS_TRACED3: 0
+  TSC_G3_IO4: 9
+  USART3_CK: 7
+PC13:
+  EVENTOUT: 15
+PC14:
+  EVENTOUT: 15
+PC15:
+  EVENTOUT: 15
+PC2:
+  EVENTOUT: 15
+  LPTIM1_IN2: 1
+  SPI2_MISO: 5
+PC3:
+  EVENTOUT: 15
+  LPTIM1_ETR: 1
+  LPTIM2_ETR: 14
+  SPI2_MOSI: 5
+PC4:
+  EVENTOUT: 15
+  USART3_TX: 7
+PC5:
+  EVENTOUT: 15
+  USART3_RX: 7
+PC6:
+  EVENTOUT: 15
+  TSC_G4_IO1: 9
+PC7:
+  EVENTOUT: 15
+  TSC_G4_IO2: 9
+PC8:
+  EVENTOUT: 15
+  TSC_G4_IO3: 9
+PC9:
+  EVENTOUT: 15
+  TSC_G4_IO4: 9
+  USB_NOE: 10
+PD2:
+  EVENTOUT: 15
+  SYS_TRACED2: 0
+  TSC_SYNC: 9
+  USART3_DE: 7
+  USART3_RTS: 7
+PH0:
+  EVENTOUT: 15
+PH1:
+  EVENTOUT: 15
+PH3:
+  EVENTOUT: 15
+PI8: {}

data/gpio_af/STM32L43x.yaml

@@ -0,0 +1,548 @@
+PA0:
+  COMP1_OUT: 12
+  EVENTOUT: 15
+  SAI1_EXTCLK: 13
+  TIM2_CH1: 1
+  TIM2_ETR: 14
+  USART2_CTS: 7
+PA1:
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  LCD_SEG0: 11
+  SPI1_SCK: 5
+  TIM15_CH1N: 14
+  TIM2_CH2: 1
+  USART2_DE: 7
+  USART2_RTS: 7
+PA10:
+  CRS_SYNC: 10
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  LCD_COM2: 11
+  SAI1_SD_A: 13
+  TIM1_CH3: 1
+  USART1_RX: 7
+PA11:
+  CAN1_RX: 9
+  COMP1_OUT: 6
+  EVENTOUT: 15
+  SPI1_MISO: 5
+  TIM1_BKIN2: 2
+  TIM1_BKIN2_COMP1: 12
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USB_DM: 10
+PA12:
+  CAN1_TX: 9
+  EVENTOUT: 15
+  SPI1_MOSI: 5
+  TIM1_ETR: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+  USB_DP: 10
+PA13:
+  EVENTOUT: 15
+  IR_OUT: 1
+  SAI1_SD_B: 13
+  SWPMI1_TX: 12
+  SYS_JTMS-SWDIO: 0
+  USB_NOE: 10
+PA14:
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  LPTIM1_OUT: 1
+  SAI1_FS_B: 13
+  SWPMI1_RX: 12
+  SYS_JTCK-SWCLK: 0
+PA15:
+  EVENTOUT: 15
+  LCD_SEG17: 11
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SWPMI1_SUSPEND: 12
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+  TSC_G3_IO1: 9
+  USART2_RX: 3
+  USART3_DE: 7
+  USART3_RTS: 7
+PA2:
+  COMP2_OUT: 12
+  EVENTOUT: 15
+  LCD_SEG1: 11
+  LPUART1_TX: 8
+  QUADSPI_BK1_NCS: 10
+  TIM15_CH1: 14
+  TIM2_CH3: 1
+  USART2_TX: 7
+PA3:
+  EVENTOUT: 15
+  LCD_SEG2: 11
+  LPUART1_RX: 8
+  QUADSPI_CLK: 10
+  SAI1_MCLK_A: 13
+  TIM15_CH2: 14
+  TIM2_CH4: 1
+  USART2_RX: 7
+PA4:
+  EVENTOUT: 15
+  LPTIM2_OUT: 14
+  SAI1_FS_B: 13
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  USART2_CK: 7
+PA5:
+  EVENTOUT: 15
+  LPTIM2_ETR: 14
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+PA6:
+  COMP1_OUT: 6
+  EVENTOUT: 15
+  LCD_SEG3: 11
+  LPUART1_CTS: 8
+  QUADSPI_BK1_IO3: 10
+  SPI1_MISO: 5
+  TIM16_CH1: 14
+  TIM1_BKIN: 1
+  TIM1_BKIN_COMP2: 12
+  USART3_CTS: 7
+PA7:
+  COMP2_OUT: 12
+  EVENTOUT: 15
+  I2C3_SCL: 4
+  LCD_SEG4: 11
+  QUADSPI_BK1_IO2: 10
+  SPI1_MOSI: 5
+  TIM1_CH1N: 1
+PA8:
+  EVENTOUT: 15
+  LCD_COM0: 11
+  LPTIM2_OUT: 14
+  RCC_MCO: 0
+  SAI1_SCK_A: 13
+  SWPMI1_IO: 12
+  TIM1_CH1: 1
+  USART1_CK: 7
+PA9:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  LCD_COM1: 11
+  SAI1_FS_A: 13
+  TIM15_BKIN: 14
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  COMP1_OUT: 12
+  EVENTOUT: 15
+  LCD_SEG5: 11
+  QUADSPI_BK1_IO1: 10
+  SAI1_EXTCLK: 13
+  SPI1_NSS: 5
+  TIM1_CH2N: 1
+  USART3_CK: 7
+PB1:
+  EVENTOUT: 15
+  LCD_SEG6: 11
+  LPTIM2_IN1: 14
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+  QUADSPI_BK1_IO0: 10
+  TIM1_CH3N: 1
+  USART3_DE: 7
+  USART3_RTS: 7
+PB10:
+  COMP1_OUT: 12
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  LCD_SEG10: 11
+  LPUART1_RX: 8
+  QUADSPI_CLK: 10
+  SAI1_SCK_A: 13
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+  TSC_SYNC: 9
+  USART3_TX: 7
+PB11:
+  COMP2_OUT: 12
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  LCD_SEG11: 11
+  LPUART1_TX: 8
+  QUADSPI_BK1_NCS: 10
+  TIM2_CH4: 1
+  USART3_RX: 7
+PB12:
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+  LCD_SEG12: 11
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+  SAI1_FS_A: 13
+  SPI2_NSS: 5
+  SWPMI1_IO: 12
+  TIM15_BKIN: 14
+  TIM1_BKIN: 1
+  TIM1_BKIN_COMP2: 3
+  TSC_G1_IO1: 9
+  USART3_CK: 7
+PB13:
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  LCD_SEG13: 11
+  LPUART1_CTS: 8
+  SAI1_SCK_A: 13
+  SPI2_SCK: 5
+  SWPMI1_TX: 12
+  TIM15_CH1N: 14
+  TIM1_CH1N: 1
+  TSC_G1_IO2: 9
+  USART3_CTS: 7
+PB14:
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  LCD_SEG14: 11
+  SAI1_MCLK_A: 13
+  SPI2_MISO: 5
+  SWPMI1_RX: 12
+  TIM15_CH1: 14
+  TIM1_CH2N: 1
+  TSC_G1_IO3: 9
+  USART3_DE: 7
+  USART3_RTS: 7
+PB15:
+  EVENTOUT: 15
+  LCD_SEG15: 11
+  RTC_REFIN: 0
+  SAI1_SD_A: 13
+  SPI2_MOSI: 5
+  SWPMI1_SUSPEND: 12
+  TIM15_CH2: 14
+  TIM1_CH3N: 1
+  TSC_G1_IO4: 9
+PB2:
+  EVENTOUT: 15
+  I2C3_SMBA: 4
+  LCD_VLCD: 11
+  LPTIM1_OUT: 1
+  RTC_OUT_ALARM: 0
+  RTC_OUT_CALIB: 0
+PB3:
+  EVENTOUT: 15
+  LCD_SEG7: 11
+  SAI1_SCK_B: 13
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+PB4:
+  EVENTOUT: 15
+  I2C3_SDA: 4
+  LCD_SEG8: 11
+  SAI1_MCLK_B: 13
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TSC_G2_IO1: 9
+  USART1_CTS: 7
+PB5:
+  COMP2_OUT: 12
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  LCD_SEG9: 11
+  LPTIM1_IN1: 1
+  SAI1_SD_B: 13
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM16_BKIN: 14
+  TSC_G2_IO2: 9
+  USART1_CK: 7
+PB6:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  LPTIM1_ETR: 1
+  SAI1_FS_B: 13
+  TIM16_CH1N: 14
+  TSC_G2_IO3: 9
+  USART1_TX: 7
+PB7:
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  LCD_SEG21: 11
+  LPTIM1_IN2: 1
+  TSC_G2_IO4: 9
+  USART1_RX: 7
+PB8:
+  CAN1_RX: 9
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  LCD_SEG16: 11
+  SAI1_MCLK_A: 13
+  SDMMC1_D4: 12
+  TIM16_CH1: 14
+PB9:
+  CAN1_TX: 9
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  IR_OUT: 1
+  LCD_COM3: 11
+  SAI1_FS_A: 13
+  SDMMC1_D5: 12
+  SPI2_NSS: 5
+PC0:
+  EVENTOUT: 15
+  I2C3_SCL: 4
+  LCD_SEG18: 11
+  LPTIM1_IN1: 1
+  LPTIM2_IN1: 14
+  LPUART1_RX: 8
+PC1:
+  EVENTOUT: 15
+  I2C3_SDA: 4
+  LCD_SEG19: 11
+  LPTIM1_OUT: 1
+  LPUART1_TX: 8
+PC10:
+  EVENTOUT: 15
+  LCD_COM4: 11
+  LCD_SEG28: 11
+  LCD_SEG40: 11
+  SDMMC1_D2: 12
+  SPI3_SCK: 6
+  TSC_G3_IO2: 9
+  USART3_TX: 7
+PC11:
+  EVENTOUT: 15
+  LCD_COM5: 11
+  LCD_SEG29: 11
+  LCD_SEG41: 11
+  SDMMC1_D3: 12
+  SPI3_MISO: 6
+  TSC_G3_IO3: 9
+  USART3_RX: 7
+PC12:
+  EVENTOUT: 15
+  LCD_COM6: 11
+  LCD_SEG30: 11
+  LCD_SEG42: 11
+  SDMMC1_CK: 12
+  SPI3_MOSI: 6
+  TSC_G3_IO4: 9
+  USART3_CK: 7
+PC13:
+  EVENTOUT: 15
+PC14:
+  EVENTOUT: 15
+PC15:
+  EVENTOUT: 15
+PC2:
+  EVENTOUT: 15
+  LCD_SEG20: 11
+  LPTIM1_IN2: 1
+  SPI2_MISO: 5
+PC3:
+  EVENTOUT: 15
+  LCD_VLCD: 11
+  LPTIM1_ETR: 1
+  LPTIM2_ETR: 14
+  SAI1_SD_A: 13
+  SPI2_MOSI: 5
+PC4:
+  EVENTOUT: 15
+  LCD_SEG22: 11
+  USART3_TX: 7
+PC5:
+  EVENTOUT: 15
+  LCD_SEG23: 11
+  USART3_RX: 7
+PC6:
+  EVENTOUT: 15
+  LCD_SEG24: 11
+  SDMMC1_D6: 12
+  TSC_G4_IO1: 9
+PC7:
+  EVENTOUT: 15
+  LCD_SEG25: 11
+  SDMMC1_D7: 12
+  TSC_G4_IO2: 9
+PC8:
+  EVENTOUT: 15
+  LCD_SEG26: 11
+  SDMMC1_D0: 12
+  TSC_G4_IO3: 9
+PC9:
+  EVENTOUT: 15
+  LCD_SEG27: 11
+  SDMMC1_D1: 12
+  TSC_G4_IO4: 9
+  USB_NOE: 10
+PD0:
+  CAN1_RX: 9
+  EVENTOUT: 15
+  SPI2_NSS: 5
+PD1:
+  CAN1_TX: 9
+  EVENTOUT: 15
+  SPI2_SCK: 5
+PD10:
+  EVENTOUT: 15
+  LCD_SEG30: 11
+  TSC_G6_IO1: 9
+  USART3_CK: 7
+PD11:
+  EVENTOUT: 15
+  LCD_SEG31: 11
+  LPTIM2_ETR: 14
+  TSC_G6_IO2: 9
+  USART3_CTS: 7
+PD12:
+  EVENTOUT: 15
+  LCD_SEG32: 11
+  LPTIM2_IN1: 14
+  TSC_G6_IO3: 9
+  USART3_DE: 7
+  USART3_RTS: 7
+PD13:
+  EVENTOUT: 15
+  LCD_SEG33: 11
+  LPTIM2_OUT: 14
+  TSC_G6_IO4: 9
+PD14:
+  EVENTOUT: 15
+  LCD_SEG34: 11
+PD15:
+  EVENTOUT: 15
+  LCD_SEG35: 11
+PD2:
+  EVENTOUT: 15
+  LCD_COM7: 11
+  LCD_SEG31: 11
+  LCD_SEG43: 11
+  SDMMC1_CMD: 12
+  TSC_SYNC: 9
+  USART3_DE: 7
+  USART3_RTS: 7
+PD3:
+  EVENTOUT: 15
+  QUADSPI_BK2_NCS: 10
+  SPI2_MISO: 5
+  USART2_CTS: 7
+PD4:
+  EVENTOUT: 15
+  QUADSPI_BK2_IO0: 10
+  SPI2_MOSI: 5
+  USART2_DE: 7
+  USART2_RTS: 7
+PD5:
+  EVENTOUT: 15
+  QUADSPI_BK2_IO1: 10
+  USART2_TX: 7
+PD6:
+  EVENTOUT: 15
+  QUADSPI_BK2_IO2: 10
+  SAI1_SD_A: 13
+  USART2_RX: 7
+PD7:
+  EVENTOUT: 15
+  QUADSPI_BK2_IO3: 10
+  USART2_CK: 7
+PD8:
+  EVENTOUT: 15
+  LCD_SEG28: 11
+  USART3_TX: 7
+PD9:
+  EVENTOUT: 15
+  LCD_SEG29: 11
+  USART3_RX: 7
+PE0:
+  EVENTOUT: 15
+  LCD_SEG36: 11
+  TIM16_CH1: 14
+PE1:
+  EVENTOUT: 15
+  LCD_SEG37: 11
+PE10:
+  EVENTOUT: 15
+  QUADSPI_CLK: 10
+  SAI1_MCLK_B: 13
+  TIM1_CH2N: 1
+  TSC_G5_IO1: 9
+PE11:
+  EVENTOUT: 15
+  QUADSPI_BK1_NCS: 10
+  TIM1_CH2: 1
+  TSC_G5_IO2: 9
+PE12:
+  EVENTOUT: 15
+  QUADSPI_BK1_IO0: 10
+  SPI1_NSS: 5
+  TIM1_CH3N: 1
+  TSC_G5_IO3: 9
+PE13:
+  EVENTOUT: 15
+  QUADSPI_BK1_IO1: 10
+  SPI1_SCK: 5
+  TIM1_CH3: 1
+  TSC_G5_IO4: 9
+PE14:
+  EVENTOUT: 15
+  QUADSPI_BK1_IO2: 10
+  SPI1_MISO: 5
+  TIM1_BKIN2: 2
+  TIM1_BKIN2_COMP2: 3
+  TIM1_CH4: 1
+PE15:
+  EVENTOUT: 15
+  QUADSPI_BK1_IO3: 10
+  SPI1_MOSI: 5
+  TIM1_BKIN: 1
+  TIM1_BKIN_COMP1: 3
+PE2:
+  EVENTOUT: 15
+  LCD_SEG38: 11
+  SAI1_MCLK_A: 13
+  SYS_TRACECLK: 0
+  TSC_G7_IO1: 9
+PE3:
+  EVENTOUT: 15
+  LCD_SEG39: 11
+  SAI1_SD_B: 13
+  SYS_TRACED0: 0
+  TSC_G7_IO2: 9
+PE4:
+  EVENTOUT: 15
+  SAI1_FS_A: 13
+  SYS_TRACED1: 0
+  TSC_G7_IO3: 9
+PE5:
+  EVENTOUT: 15
+  SAI1_SCK_A: 13
+  SYS_TRACED2: 0
+  TSC_G7_IO4: 9
+PE6:
+  EVENTOUT: 15
+  SAI1_SD_A: 13
+  SYS_TRACED3: 0
+PE7:
+  EVENTOUT: 15
+  SAI1_SD_B: 13
+  TIM1_ETR: 1
+PE8:
+  EVENTOUT: 15
+  SAI1_SCK_B: 13
+  TIM1_CH1N: 1
+PE9:
+  EVENTOUT: 15
+  SAI1_FS_B: 13
+  TIM1_CH1: 1
+PH0:
+  EVENTOUT: 15
+PH1:
+  EVENTOUT: 15
+PH3:
+  EVENTOUT: 15
+PI8: {}

data/gpio_af/STM32L45x.yaml

@@ -0,0 +1,546 @@
+PA0:
+  COMP1_OUT: 12
+  EVENTOUT: 15
+  SAI1_EXTCLK: 13
+  TIM2_CH1: 1
+  TIM2_ETR: 14
+  UART4_TX: 8
+  USART2_CTS: 7
+PA1:
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  SPI1_SCK: 5
+  TIM15_CH1N: 14
+  TIM2_CH2: 1
+  UART4_RX: 8
+  USART2_DE: 7
+  USART2_RTS: 7
+PA10:
+  CRS_SYNC: 10
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  SAI1_SD_A: 13
+  TIM1_CH3: 1
+  USART1_RX: 7
+PA11:
+  CAN1_RX: 9
+  COMP1_OUT: 6
+  EVENTOUT: 15
+  SPI1_MISO: 5
+  TIM1_BKIN2: 2
+  TIM1_BKIN2_COMP1: 12
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USB_DM: 10
+PA12:
+  CAN1_TX: 9
+  EVENTOUT: 15
+  SPI1_MOSI: 5
+  TIM1_ETR: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+  USB_DP: 10
+PA13:
+  EVENTOUT: 15
+  IR_OUT: 1
+  SAI1_SD_B: 13
+  SYS_JTMS-SWDIO: 0
+  USB_NOE: 10
+PA14:
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  I2C4_SMBA: 5
+  LPTIM1_OUT: 1
+  SAI1_FS_B: 13
+  SYS_JTCK-SWCLK: 0
+PA15:
+  EVENTOUT: 15
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+  TSC_G3_IO1: 9
+  UART4_DE: 8
+  UART4_RTS: 8
+  USART2_RX: 3
+  USART3_DE: 7
+  USART3_RTS: 7
+PA2:
+  COMP2_OUT: 12
+  EVENTOUT: 15
+  LPUART1_TX: 8
+  QUADSPI_BK1_NCS: 10
+  TIM15_CH1: 14
+  TIM2_CH3: 1
+  USART2_TX: 7
+PA3:
+  EVENTOUT: 15
+  LPUART1_RX: 8
+  QUADSPI_CLK: 10
+  SAI1_MCLK_A: 13
+  TIM15_CH2: 14
+  TIM2_CH4: 1
+  USART2_RX: 7
+PA4:
+  EVENTOUT: 15
+  LPTIM2_OUT: 14
+  SAI1_FS_B: 13
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  USART2_CK: 7
+PA5:
+  DFSDM1_CKOUT: 6
+  EVENTOUT: 15
+  LPTIM2_ETR: 14
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+PA6:
+  COMP1_OUT: 6
+  EVENTOUT: 15
+  LPUART1_CTS: 8
+  QUADSPI_BK1_IO3: 10
+  SPI1_MISO: 5
+  TIM16_CH1: 14
+  TIM1_BKIN: 1
+  TIM1_BKIN_COMP2: 12
+  TIM3_CH1: 2
+  USART3_CTS: 7
+PA7:
+  COMP2_OUT: 12
+  DFSDM1_DATIN0: 6
+  EVENTOUT: 15
+  I2C3_SCL: 4
+  QUADSPI_BK1_IO2: 10
+  SPI1_MOSI: 5
+  TIM1_CH1N: 1
+  TIM3_CH2: 2
+PA8:
+  DFSDM1_CKIN1: 6
+  EVENTOUT: 15
+  LPTIM2_OUT: 14
+  RCC_MCO: 0
+  SAI1_SCK_A: 13
+  TIM1_CH1: 1
+  USART1_CK: 7
+PA9:
+  DFSDM1_DATIN1: 6
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  SAI1_FS_A: 13
+  TIM15_BKIN: 14
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  COMP1_OUT: 12
+  DFSDM1_CKIN0: 6
+  EVENTOUT: 15
+  QUADSPI_BK1_IO1: 10
+  SAI1_EXTCLK: 13
+  SPI1_NSS: 5
+  TIM1_CH2N: 1
+  TIM3_CH3: 2
+  USART3_CK: 7
+PB1:
+  DFSDM1_DATIN0: 6
+  EVENTOUT: 15
+  LPTIM2_IN1: 14
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+  QUADSPI_BK1_IO0: 10
+  TIM1_CH3N: 1
+  TIM3_CH4: 2
+  USART3_DE: 7
+  USART3_RTS: 7
+PB10:
+  COMP1_OUT: 12
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  I2C4_SCL: 3
+  LPUART1_RX: 8
+  QUADSPI_CLK: 10
+  SAI1_SCK_A: 13
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+  TSC_SYNC: 9
+  USART3_TX: 7
+PB11:
+  COMP2_OUT: 12
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  I2C4_SDA: 3
+  LPUART1_TX: 8
+  QUADSPI_BK1_NCS: 10
+  TIM2_CH4: 1
+  USART3_RX: 7
+PB12:
+  CAN1_RX: 10
+  DFSDM1_DATIN1: 6
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+  SAI1_FS_A: 13
+  SPI2_NSS: 5
+  TIM15_BKIN: 14
+  TIM1_BKIN: 1
+  TIM1_BKIN_COMP2: 3
+  TSC_G1_IO1: 9
+  USART3_CK: 7
+PB13:
+  CAN1_TX: 10
+  DFSDM1_CKIN1: 6
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  LPUART1_CTS: 8
+  SAI1_SCK_A: 13
+  SPI2_SCK: 5
+  TIM15_CH1N: 14
+  TIM1_CH1N: 1
+  TSC_G1_IO2: 9
+  USART3_CTS: 7
+PB14:
+  DFSDM1_DATIN2: 6
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  SAI1_MCLK_A: 13
+  SPI2_MISO: 5
+  TIM15_CH1: 14
+  TIM1_CH2N: 1
+  TSC_G1_IO3: 9
+  USART3_DE: 7
+  USART3_RTS: 7
+PB15:
+  DFSDM1_CKIN2: 6
+  EVENTOUT: 15
+  RTC_REFIN: 0
+  SAI1_SD_A: 13
+  SPI2_MOSI: 5
+  TIM15_CH2: 14
+  TIM1_CH3N: 1
+  TSC_G1_IO4: 9
+PB2:
+  DFSDM1_CKIN0: 6
+  EVENTOUT: 15
+  I2C3_SMBA: 4
+  LPTIM1_OUT: 1
+  RTC_OUT_ALARM: 0
+  RTC_OUT_CALIB: 0
+PB3:
+  EVENTOUT: 15
+  SAI1_SCK_B: 13
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+PB4:
+  EVENTOUT: 15
+  I2C3_SDA: 4
+  SAI1_MCLK_B: 13
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM3_CH1: 2
+  TSC_G2_IO1: 9
+  USART1_CTS: 7
+PB5:
+  CAN1_RX: 3
+  COMP2_OUT: 12
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  LPTIM1_IN1: 1
+  SAI1_SD_B: 13
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM16_BKIN: 14
+  TIM3_CH2: 2
+  TSC_G2_IO2: 9
+  USART1_CK: 7
+PB6:
+  CAN1_TX: 8
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  I2C4_SCL: 5
+  LPTIM1_ETR: 1
+  SAI1_FS_B: 13
+  TIM16_CH1N: 14
+  TSC_G2_IO3: 9
+  USART1_TX: 7
+PB7:
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  I2C4_SDA: 5
+  LPTIM1_IN2: 1
+  TSC_G2_IO4: 9
+  UART4_CTS: 8
+  USART1_RX: 7
+PB8:
+  CAN1_RX: 9
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  SAI1_MCLK_A: 13
+  SDMMC1_D4: 12
+  TIM16_CH1: 14
+PB9:
+  CAN1_TX: 9
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  IR_OUT: 1
+  SAI1_FS_A: 13
+  SDMMC1_D5: 12
+  SPI2_NSS: 5
+PC0:
+  EVENTOUT: 15
+  I2C3_SCL: 4
+  I2C4_SCL: 2
+  LPTIM1_IN1: 1
+  LPTIM2_IN1: 14
+  LPUART1_RX: 8
+PC1:
+  EVENTOUT: 15
+  I2C3_SDA: 4
+  I2C4_SDA: 2
+  LPTIM1_OUT: 1
+  LPUART1_TX: 8
+  SYS_TRACED0: 0
+PC10:
+  EVENTOUT: 15
+  SDMMC1_D2: 12
+  SPI3_SCK: 6
+  SYS_TRACED1: 0
+  TSC_G3_IO2: 9
+  UART4_TX: 8
+  USART3_TX: 7
+PC11:
+  EVENTOUT: 15
+  SDMMC1_D3: 12
+  SPI3_MISO: 6
+  TSC_G3_IO3: 9
+  UART4_RX: 8
+  USART3_RX: 7
+PC12:
+  EVENTOUT: 15
+  SDMMC1_CK: 12
+  SPI3_MOSI: 6
+  SYS_TRACED3: 0
+  TSC_G3_IO4: 9
+  USART3_CK: 7
+PC13:
+  EVENTOUT: 15
+PC14:
+  EVENTOUT: 15
+PC15:
+  EVENTOUT: 15
+PC2:
+  DFSDM1_CKOUT: 6
+  EVENTOUT: 15
+  LPTIM1_IN2: 1
+  SPI2_MISO: 5
+PC3:
+  EVENTOUT: 15
+  LPTIM1_ETR: 1
+  LPTIM2_ETR: 14
+  SAI1_SD_A: 13
+  SPI2_MOSI: 5
+PC4:
+  EVENTOUT: 15
+  USART3_TX: 7
+PC5:
+  EVENTOUT: 15
+  USART3_RX: 7
+PC6:
+  DFSDM1_CKIN3: 6
+  EVENTOUT: 15
+  SDMMC1_D6: 12
+  TIM3_CH1: 2
+  TSC_G4_IO1: 9
+PC7:
+  DFSDM1_DATIN3: 6
+  EVENTOUT: 15
+  SDMMC1_D7: 12
+  TIM3_CH2: 2
+  TSC_G4_IO2: 9
+PC8:
+  EVENTOUT: 15
+  SDMMC1_D0: 12
+  TIM3_CH3: 2
+  TSC_G4_IO3: 9
+PC9:
+  EVENTOUT: 15
+  SDMMC1_D1: 12
+  TIM3_CH4: 2
+  TSC_G4_IO4: 9
+  USB_NOE: 10
+PD0:
+  CAN1_RX: 9
+  EVENTOUT: 15
+  SPI2_NSS: 5
+PD1:
+  CAN1_TX: 9
+  EVENTOUT: 15
+  SPI2_SCK: 5
+PD10:
+  EVENTOUT: 15
+  TSC_G6_IO1: 9
+  USART3_CK: 7
+PD11:
+  EVENTOUT: 15
+  I2C4_SMBA: 4
+  LPTIM2_ETR: 14
+  TSC_G6_IO2: 9
+  USART3_CTS: 7
+PD12:
+  EVENTOUT: 15
+  I2C4_SCL: 4
+  LPTIM2_IN1: 14
+  TSC_G6_IO3: 9
+  USART3_DE: 7
+  USART3_RTS: 7
+PD13:
+  EVENTOUT: 15
+  I2C4_SDA: 4
+  LPTIM2_OUT: 14
+  TSC_G6_IO4: 9
+PD14:
+  EVENTOUT: 15
+PD15:
+  EVENTOUT: 15
+PD2:
+  EVENTOUT: 15
+  SDMMC1_CMD: 12
+  SYS_TRACED2: 0
+  TIM3_ETR: 2
+  TSC_SYNC: 9
+  USART3_DE: 7
+  USART3_RTS: 7
+PD3:
+  DFSDM1_DATIN0: 6
+  EVENTOUT: 15
+  QUADSPI_BK2_NCS: 10
+  SPI2_MISO: 5
+  USART2_CTS: 7
+PD4:
+  DFSDM1_CKIN0: 6
+  EVENTOUT: 15
+  QUADSPI_BK2_IO0: 10
+  SPI2_MOSI: 5
+  USART2_DE: 7
+  USART2_RTS: 7
+PD5:
+  EVENTOUT: 15
+  QUADSPI_BK2_IO1: 10
+  USART2_TX: 7
+PD6:
+  DFSDM1_DATIN1: 6
+  EVENTOUT: 15
+  QUADSPI_BK2_IO2: 10
+  SAI1_SD_A: 13
+  USART2_RX: 7
+PD7:
+  DFSDM1_CKIN1: 6
+  EVENTOUT: 15
+  QUADSPI_BK2_IO3: 10
+  USART2_CK: 7
+PD8:
+  EVENTOUT: 15
+  USART3_TX: 7
+PD9:
+  EVENTOUT: 15
+  USART3_RX: 7
+PE0:
+  EVENTOUT: 15
+  TIM16_CH1: 14
+PE1:
+  EVENTOUT: 15
+PE10:
+  EVENTOUT: 15
+  QUADSPI_CLK: 10
+  SAI1_MCLK_B: 13
+  TIM1_CH2N: 1
+  TSC_G5_IO1: 9
+PE11:
+  EVENTOUT: 15
+  QUADSPI_BK1_NCS: 10
+  TIM1_CH2: 1
+  TSC_G5_IO2: 9
+PE12:
+  EVENTOUT: 15
+  QUADSPI_BK1_IO0: 10
+  SPI1_NSS: 5
+  TIM1_CH3N: 1
+  TSC_G5_IO3: 9
+PE13:
+  EVENTOUT: 15
+  QUADSPI_BK1_IO1: 10
+  SPI1_SCK: 5
+  TIM1_CH3: 1
+  TSC_G5_IO4: 9
+PE14:
+  EVENTOUT: 15
+  QUADSPI_BK1_IO2: 10
+  SPI1_MISO: 5
+  TIM1_BKIN2: 2
+  TIM1_BKIN2_COMP2: 3
+  TIM1_CH4: 1
+PE15:
+  EVENTOUT: 15
+  QUADSPI_BK1_IO3: 10
+  SPI1_MOSI: 5
+  TIM1_BKIN: 1
+  TIM1_BKIN_COMP1: 3
+PE2:
+  EVENTOUT: 15
+  SAI1_MCLK_A: 13
+  SYS_TRACECLK: 0
+  TIM3_ETR: 2
+  TSC_G7_IO1: 9
+PE3:
+  EVENTOUT: 15
+  SAI1_SD_B: 13
+  SYS_TRACED0: 0
+  TIM3_CH1: 2
+  TSC_G7_IO2: 9
+PE4:
+  DFSDM1_DATIN3: 6
+  EVENTOUT: 15
+  SAI1_FS_A: 13
+  SYS_TRACED1: 0
+  TIM3_CH2: 2
+  TSC_G7_IO3: 9
+PE5:
+  DFSDM1_CKIN3: 6
+  EVENTOUT: 15
+  SAI1_SCK_A: 13
+  SYS_TRACED2: 0
+  TIM3_CH3: 2
+  TSC_G7_IO4: 9
+PE6:
+  EVENTOUT: 15
+  SAI1_SD_A: 13
+  SYS_TRACED3: 0
+  TIM3_CH4: 2
+PE7:
+  DFSDM1_DATIN2: 6
+  EVENTOUT: 15
+  SAI1_SD_B: 13
+  TIM1_ETR: 1
+PE8:
+  DFSDM1_CKIN2: 6
+  EVENTOUT: 15
+  SAI1_SCK_B: 13
+  TIM1_CH1N: 1
+PE9:
+  DFSDM1_CKOUT: 6
+  EVENTOUT: 15
+  SAI1_FS_B: 13
+  TIM1_CH1: 1
+PH0:
+  EVENTOUT: 15
+PH1:
+  EVENTOUT: 15
+PH3:
+  EVENTOUT: 15
+PI8: {}

data/gpio_af/STM32L47x.yaml

@@ -0,0 +1,808 @@
+PA0:
+  EVENTOUT: 15
+  SAI1_EXTCLK: 13
+  TIM2_CH1: 1
+  TIM2_ETR: 14
+  TIM5_CH1: 2
+  TIM8_ETR: 3
+  UART4_TX: 8
+  USART2_CTS: 7
+PA1:
+  EVENTOUT: 15
+  LCD_SEG0: 11
+  TIM15_CH1N: 14
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  UART4_RX: 8
+  USART2_DE: 7
+  USART2_RTS: 7
+PA10:
+  EVENTOUT: 15
+  LCD_COM2: 11
+  TIM17_BKIN: 14
+  TIM1_CH3: 1
+  USART1_RX: 7
+  USB_OTG_FS_ID: 10
+PA11:
+  CAN1_RX: 9
+  EVENTOUT: 15
+  TIM1_BKIN2: 2
+  TIM1_BKIN2_COMP1: 12
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USB_OTG_FS_DM: 10
+PA12:
+  CAN1_TX: 9
+  EVENTOUT: 15
+  TIM1_ETR: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+  USB_OTG_FS_DP: 10
+PA13:
+  EVENTOUT: 15
+  IR_OUT: 1
+  SYS_JTMS-SWDIO: 0
+  USB_OTG_FS_NOE: 10
+PA14:
+  EVENTOUT: 15
+  SYS_JTCK-SWCLK: 0
+PA15:
+  EVENTOUT: 15
+  LCD_SEG17: 11
+  SAI2_FS_B: 13
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+  TSC_G3_IO1: 9
+  UART4_DE: 8
+  UART4_RTS: 8
+PA2:
+  EVENTOUT: 15
+  LCD_SEG1: 11
+  SAI2_EXTCLK: 13
+  TIM15_CH1: 14
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  USART2_TX: 7
+PA3:
+  EVENTOUT: 15
+  LCD_SEG2: 11
+  TIM15_CH2: 14
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  USART2_RX: 7
+PA4:
+  EVENTOUT: 15
+  LPTIM2_OUT: 14
+  SAI1_FS_B: 13
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  USART2_CK: 7
+PA5:
+  EVENTOUT: 15
+  LPTIM2_ETR: 14
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+  TIM8_CH1N: 3
+PA6:
+  EVENTOUT: 15
+  LCD_SEG3: 11
+  QUADSPI_BK1_IO3: 10
+  SPI1_MISO: 5
+  TIM16_CH1: 14
+  TIM1_BKIN: 1
+  TIM1_BKIN_COMP2: 12
+  TIM3_CH1: 2
+  TIM8_BKIN: 3
+  TIM8_BKIN_COMP2: 13
+  USART3_CTS: 7
+PA7:
+  EVENTOUT: 15
+  LCD_SEG4: 11
+  QUADSPI_BK1_IO2: 10
+  SPI1_MOSI: 5
+  TIM17_CH1: 14
+  TIM1_CH1N: 1
+  TIM3_CH2: 2
+  TIM8_CH1N: 3
+PA8:
+  EVENTOUT: 15
+  LCD_COM0: 11
+  LPTIM2_OUT: 14
+  RCC_MCO: 0
+  TIM1_CH1: 1
+  USART1_CK: 7
+  USB_OTG_FS_SOF: 10
+PA9:
+  EVENTOUT: 15
+  LCD_COM1: 11
+  TIM15_BKIN: 14
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  COMP1_OUT: 12
+  EVENTOUT: 15
+  LCD_SEG5: 11
+  QUADSPI_BK1_IO1: 10
+  TIM1_CH2N: 1
+  TIM3_CH3: 2
+  TIM8_CH2N: 3
+  USART3_CK: 7
+PB1:
+  DFSDM1_DATIN0: 6
+  EVENTOUT: 15
+  LCD_SEG6: 11
+  LPTIM2_IN1: 14
+  QUADSPI_BK1_IO0: 10
+  TIM1_CH3N: 1
+  TIM3_CH4: 2
+  TIM8_CH3N: 3
+  USART3_DE: 7
+  USART3_RTS: 7
+PB10:
+  COMP1_OUT: 12
+  DFSDM1_DATIN7: 6
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  LCD_SEG10: 11
+  LPUART1_RX: 8
+  QUADSPI_CLK: 10
+  SAI1_SCK_A: 13
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+  USART3_TX: 7
+PB11:
+  COMP2_OUT: 12
+  DFSDM1_CKIN7: 6
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  LCD_SEG11: 11
+  LPUART1_TX: 8
+  QUADSPI_NCS: 10
+  TIM2_CH4: 1
+  USART3_RX: 7
+PB12:
+  DFSDM1_DATIN1: 6
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+  LCD_SEG12: 11
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+  SAI2_FS_A: 13
+  SPI2_NSS: 5
+  SWPMI1_IO: 12
+  TIM15_BKIN: 14
+  TIM1_BKIN: 1
+  TIM1_BKIN_COMP2: 3
+  TSC_G1_IO1: 9
+  USART3_CK: 7
+PB13:
+  DFSDM1_CKIN1: 6
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  LCD_SEG13: 11
+  LPUART1_CTS: 8
+  SAI2_SCK_A: 13
+  SPI2_SCK: 5
+  SWPMI1_TX: 12
+  TIM15_CH1N: 14
+  TIM1_CH1N: 1
+  TSC_G1_IO2: 9
+  USART3_CTS: 7
+PB14:
+  DFSDM1_DATIN2: 6
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  LCD_SEG14: 11
+  SAI2_MCLK_A: 13
+  SPI2_MISO: 5
+  SWPMI1_RX: 12
+  TIM15_CH1: 14
+  TIM1_CH2N: 1
+  TIM8_CH2N: 3
+  TSC_G1_IO3: 9
+  USART3_DE: 7
+  USART3_RTS: 7
+PB15:
+  DFSDM1_CKIN2: 6
+  EVENTOUT: 15
+  LCD_SEG15: 11
+  RTC_REFIN: 0
+  SAI2_SD_A: 13
+  SPI2_MOSI: 5
+  SWPMI1_SUSPEND: 12
+  TIM15_CH2: 14
+  TIM1_CH3N: 1
+  TIM8_CH3N: 3
+  TSC_G1_IO4: 9
+PB2:
+  DFSDM1_CKIN0: 6
+  EVENTOUT: 15
+  I2C3_SMBA: 4
+  LPTIM1_OUT: 1
+  RTC_OUT_ALARM: 0
+  RTC_OUT_CALIB: 0
+PB3:
+  EVENTOUT: 15
+  LCD_SEG7: 11
+  SAI1_SCK_B: 13
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+PB4:
+  EVENTOUT: 15
+  LCD_SEG8: 11
+  SAI1_MCLK_B: 13
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  SYS_JTRST: 0
+  TIM17_BKIN: 14
+  TIM3_CH1: 2
+  TSC_G2_IO1: 9
+  UART5_DE: 8
+  UART5_RTS: 8
+  USART1_CTS: 7
+PB5:
+  COMP2_OUT: 12
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  LCD_SEG9: 11
+  LPTIM1_IN1: 1
+  SAI1_SD_B: 13
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM16_BKIN: 14
+  TIM3_CH2: 2
+  TSC_G2_IO2: 9
+  UART5_CTS: 8
+  USART1_CK: 7
+PB6:
+  DFSDM1_DATIN5: 6
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  LPTIM1_ETR: 1
+  SAI1_FS_B: 13
+  TIM16_CH1N: 14
+  TIM4_CH1: 2
+  TIM8_BKIN2: 3
+  TIM8_BKIN2_COMP2: 12
+  TSC_G2_IO3: 9
+  USART1_TX: 7
+PB7:
+  DFSDM1_CKIN5: 6
+  EVENTOUT: 15
+  FMC_NL: 12
+  I2C1_SDA: 4
+  LCD_SEG21: 11
+  LPTIM1_IN2: 1
+  TIM17_CH1N: 14
+  TIM4_CH2: 2
+  TIM8_BKIN: 3
+  TIM8_BKIN_COMP1: 13
+  TSC_G2_IO4: 9
+  UART4_CTS: 8
+  USART1_RX: 7
+PB8:
+  CAN1_RX: 9
+  DFSDM1_DATIN6: 6
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  LCD_SEG16: 11
+  SAI1_MCLK_A: 13
+  SDMMC1_D4: 12
+  TIM16_CH1: 14
+  TIM4_CH3: 2
+PB9:
+  CAN1_TX: 9
+  DFSDM1_CKIN6: 6
+  EVENTOUT: 15
+  I2C1_SDA: 4
+  IR_OUT: 1
+  LCD_COM3: 11
+  SAI1_FS_A: 13
+  SDMMC1_D5: 12
+  SPI2_NSS: 5
+  TIM17_CH1: 14
+  TIM4_CH4: 2
+PC0:
+  DFSDM1_DATIN4: 6
+  EVENTOUT: 15
+  I2C3_SCL: 4
+  LCD_SEG18: 11
+  LPTIM1_IN1: 1
+  LPTIM2_IN1: 14
+  LPUART1_RX: 8
+PC1:
+  DFSDM1_CKIN4: 6
+  EVENTOUT: 15
+  I2C3_SDA: 4
+  LCD_SEG19: 11
+  LPTIM1_OUT: 1
+  LPUART1_TX: 8
+PC10:
+  EVENTOUT: 15
+  LCD_COM4: 11
+  LCD_SEG28: 11
+  LCD_SEG40: 11
+  SAI2_SCK_B: 13
+  SDMMC1_D2: 12
+  SPI3_SCK: 6
+  TSC_G3_IO2: 9
+  UART4_TX: 8
+  USART3_TX: 7
+PC11:
+  EVENTOUT: 15
+  LCD_COM5: 11
+  LCD_SEG29: 11
+  LCD_SEG41: 11
+  SAI2_MCLK_B: 13
+  SDMMC1_D3: 12
+  SPI3_MISO: 6
+  TSC_G3_IO3: 9
+  UART4_RX: 8
+  USART3_RX: 7
+PC12:
+  EVENTOUT: 15
+  LCD_COM6: 11
+  LCD_SEG30: 11
+  LCD_SEG42: 11
+  SAI2_SD_B: 13
+  SDMMC1_CK: 12
+  SPI3_MOSI: 6
+  TSC_G3_IO4: 9
+  UART5_TX: 8
+  USART3_CK: 7
+PC13:
+  EVENTOUT: 15
+PC14:
+  EVENTOUT: 15
+PC15:
+  EVENTOUT: 15
+PC2:
+  DFSDM1_CKOUT: 6
+  EVENTOUT: 15
+  LCD_SEG20: 11
+  LPTIM1_IN2: 1
+  SPI2_MISO: 5
+PC3:
+  EVENTOUT: 15
+  LCD_VLCD: 11
+  LPTIM1_ETR: 1
+  LPTIM2_ETR: 14
+  SAI1_SD_A: 13
+  SPI2_MOSI: 5
+PC4:
+  EVENTOUT: 15
+  LCD_SEG22: 11
+  USART3_TX: 7
+PC5:
+  EVENTOUT: 15
+  LCD_SEG23: 11
+  USART3_RX: 7
+PC6:
+  DFSDM1_CKIN3: 6
+  EVENTOUT: 15
+  LCD_SEG24: 11
+  SAI2_MCLK_A: 13
+  SDMMC1_D6: 12
+  TIM3_CH1: 2
+  TIM8_CH1: 3
+  TSC_G4_IO1: 9
+PC7:
+  DFSDM1_DATIN3: 6
+  EVENTOUT: 15
+  LCD_SEG25: 11
+  SAI2_MCLK_B: 13
+  SDMMC1_D7: 12
+  TIM3_CH2: 2
+  TIM8_CH2: 3
+  TSC_G4_IO2: 9
+PC8:
+  EVENTOUT: 15
+  LCD_SEG26: 11
+  SDMMC1_D0: 12
+  TIM3_CH3: 2
+  TIM8_CH3: 3
+  TSC_G4_IO3: 9
+PC9:
+  EVENTOUT: 15
+  LCD_SEG27: 11
+  SAI2_EXTCLK: 13
+  SDMMC1_D1: 12
+  TIM3_CH4: 2
+  TIM8_BKIN2: 1
+  TIM8_BKIN2_COMP1: 14
+  TIM8_CH4: 3
+  TSC_G4_IO4: 9
+  USB_OTG_FS_NOE: 10
+PD0:
+  CAN1_RX: 9
+  DFSDM1_DATIN7: 6
+  EVENTOUT: 15
+  FMC_D2: 12
+  FMC_DA2: 12
+  SPI2_NSS: 5
+PD1:
+  CAN1_TX: 9
+  DFSDM1_CKIN7: 6
+  EVENTOUT: 15
+  FMC_D3: 12
+  FMC_DA3: 12
+  SPI2_SCK: 5
+PD10:
+  EVENTOUT: 15
+  FMC_D15: 12
+  FMC_DA15: 12
+  LCD_SEG30: 11
+  SAI2_SCK_A: 13
+  TSC_G6_IO1: 9
+  USART3_CK: 7
+PD11:
+  EVENTOUT: 15
+  FMC_A16: 12
+  LCD_SEG31: 11
+  LPTIM2_ETR: 14
+  SAI2_SD_A: 13
+  TSC_G6_IO2: 9
+  USART3_CTS: 7
+PD12:
+  EVENTOUT: 15
+  FMC_A17: 12
+  LCD_SEG32: 11
+  LPTIM2_IN1: 14
+  SAI2_FS_A: 13
+  TIM4_CH1: 2
+  TSC_G6_IO3: 9
+  USART3_DE: 7
+  USART3_RTS: 7
+PD13:
+  EVENTOUT: 15
+  FMC_A18: 12
+  LCD_SEG33: 11
+  LPTIM2_OUT: 14
+  TIM4_CH2: 2
+  TSC_G6_IO4: 9
+PD14:
+  EVENTOUT: 15
+  FMC_D0: 12
+  FMC_DA0: 12
+  LCD_SEG34: 11
+  TIM4_CH3: 2
+PD15:
+  EVENTOUT: 15
+  FMC_D1: 12
+  FMC_DA1: 12
+  LCD_SEG35: 11
+  TIM4_CH4: 2
+PD2:
+  EVENTOUT: 15
+  LCD_COM7: 11
+  LCD_SEG31: 11
+  LCD_SEG43: 11
+  SDMMC1_CMD: 12
+  TIM3_ETR: 2
+  TSC_SYNC: 9
+  UART5_RX: 8
+  USART3_DE: 7
+  USART3_RTS: 7
+PD3:
+  DFSDM1_DATIN0: 6
+  EVENTOUT: 15
+  FMC_CLK: 12
+  SPI2_MISO: 5
+  USART2_CTS: 7
+PD4:
+  DFSDM1_CKIN0: 6
+  EVENTOUT: 15
+  FMC_NOE: 12
+  SPI2_MOSI: 5
+  USART2_DE: 7
+  USART2_RTS: 7
+PD5:
+  EVENTOUT: 15
+  FMC_NWE: 12
+  USART2_TX: 7
+PD6:
+  DFSDM1_DATIN1: 6
+  EVENTOUT: 15
+  FMC_NWAIT: 12
+  SAI1_SD_A: 13
+  USART2_RX: 7
+PD7:
+  DFSDM1_CKIN1: 6
+  EVENTOUT: 15
+  FMC_NE1: 12
+  USART2_CK: 7
+PD8:
+  EVENTOUT: 15
+  FMC_D13: 12
+  FMC_DA13: 12
+  LCD_SEG28: 11
+  USART3_TX: 7
+PD9:
+  EVENTOUT: 15
+  FMC_D14: 12
+  FMC_DA14: 12
+  LCD_SEG29: 11
+  SAI2_MCLK_A: 13
+  USART3_RX: 7
+PE0:
+  EVENTOUT: 15
+  FMC_NBL0: 12
+  LCD_SEG36: 11
+  TIM16_CH1: 14
+  TIM4_ETR: 2
+PE1:
+  EVENTOUT: 15
+  FMC_NBL1: 12
+  LCD_SEG37: 11
+  TIM17_CH1: 14
+PE10:
+  DFSDM1_DATIN4: 6
+  EVENTOUT: 15
+  FMC_D7: 12
+  FMC_DA7: 12
+  QUADSPI_CLK: 10
+  SAI1_MCLK_B: 13
+  TIM1_CH2N: 1
+  TSC_G5_IO1: 9
+PE11:
+  DFSDM1_CKIN4: 6
+  EVENTOUT: 15
+  FMC_D8: 12
+  FMC_DA8: 12
+  QUADSPI_NCS: 10
+  TIM1_CH2: 1
+  TSC_G5_IO2: 9
+PE12:
+  DFSDM1_DATIN5: 6
+  EVENTOUT: 15
+  FMC_D9: 12
+  FMC_DA9: 12
+  QUADSPI_BK1_IO0: 10
+  SPI1_NSS: 5
+  TIM1_CH3N: 1
+  TSC_G5_IO3: 9
+PE13:
+  DFSDM1_CKIN5: 6
+  EVENTOUT: 15
+  FMC_D10: 12
+  FMC_DA10: 12
+  QUADSPI_BK1_IO1: 10
+  SPI1_SCK: 5
+  TIM1_CH3: 1
+  TSC_G5_IO4: 9
+PE14:
+  EVENTOUT: 15
+  FMC_D11: 12
+  FMC_DA11: 12
+  QUADSPI_BK1_IO2: 10
+  SPI1_MISO: 5
+  TIM1_BKIN2: 2
+  TIM1_BKIN2_COMP2: 3
+  TIM1_CH4: 1
+PE15:
+  EVENTOUT: 15
+  FMC_D12: 12
+  FMC_DA12: 12
+  QUADSPI_BK1_IO3: 10
+  SPI1_MOSI: 5
+  TIM1_BKIN: 1
+  TIM1_BKIN_COMP1: 3
+PE2:
+  EVENTOUT: 15
+  FMC_A23: 12
+  LCD_SEG38: 11
+  SAI1_MCLK_A: 13
+  SYS_TRACECLK: 0
+  TIM3_ETR: 2
+  TSC_G7_IO1: 9
+PE3:
+  EVENTOUT: 15
+  FMC_A19: 12
+  LCD_SEG39: 11
+  SAI1_SD_B: 13
+  SYS_TRACED0: 0
+  TIM3_CH1: 2
+  TSC_G7_IO2: 9
+PE4:
+  DFSDM1_DATIN3: 6
+  EVENTOUT: 15
+  FMC_A20: 12
+  SAI1_FS_A: 13
+  SYS_TRACED1: 0
+  TIM3_CH2: 2
+  TSC_G7_IO3: 9
+PE5:
+  DFSDM1_CKIN3: 6
+  EVENTOUT: 15
+  FMC_A21: 12
+  SAI1_SCK_A: 13
+  SYS_TRACED2: 0
+  TIM3_CH3: 2
+  TSC_G7_IO4: 9
+PE6:
+  EVENTOUT: 15
+  FMC_A22: 12
+  SAI1_SD_A: 13
+  SYS_TRACED3: 0
+  TIM3_CH4: 2
+PE7:
+  DFSDM1_DATIN2: 6
+  EVENTOUT: 15
+  FMC_D4: 12
+  FMC_DA4: 12
+  SAI1_SD_B: 13
+  TIM1_ETR: 1
+PE8:
+  DFSDM1_CKIN2: 6
+  EVENTOUT: 15
+  FMC_D5: 12
+  FMC_DA5: 12
+  SAI1_SCK_B: 13
+  TIM1_CH1N: 1
+PE9:
+  DFSDM1_CKOUT: 6
+  EVENTOUT: 15
+  FMC_D6: 12
+  FMC_DA6: 12
+  SAI1_FS_B: 13
+  TIM1_CH1: 1
+PF0:
+  EVENTOUT: 15
+  FMC_A0: 12
+  I2C2_SDA: 4
+PF1:
+  EVENTOUT: 15
+  FMC_A1: 12
+  I2C2_SCL: 4
+PF10:
+  EVENTOUT: 15
+  TIM15_CH2: 14
+PF11:
+  EVENTOUT: 15
+PF12:
+  EVENTOUT: 15
+  FMC_A6: 12
+PF13:
+  DFSDM1_DATIN6: 6
+  EVENTOUT: 15
+  FMC_A7: 12
+PF14:
+  DFSDM1_CKIN6: 6
+  EVENTOUT: 15
+  FMC_A8: 12
+  TSC_G8_IO1: 9
+PF15:
+  EVENTOUT: 15
+  FMC_A9: 12
+  TSC_G8_IO2: 9
+PF2:
+  EVENTOUT: 15
+  FMC_A2: 12
+  I2C2_SMBA: 4
+PF3:
+  EVENTOUT: 15
+  FMC_A3: 12
+PF4:
+  EVENTOUT: 15
+  FMC_A4: 12
+PF5:
+  EVENTOUT: 15
+  FMC_A5: 12
+PF6:
+  EVENTOUT: 15
+  SAI1_SD_B: 13
+  TIM5_CH1: 2
+  TIM5_ETR: 1
+PF7:
+  EVENTOUT: 15
+  SAI1_MCLK_B: 13
+  TIM5_CH2: 2
+PF8:
+  EVENTOUT: 15
+  SAI1_SCK_B: 13
+  TIM5_CH3: 2
+PF9:
+  EVENTOUT: 15
+  SAI1_FS_B: 13
+  TIM15_CH1: 14
+  TIM5_CH4: 2
+PG0:
+  EVENTOUT: 15
+  FMC_A10: 12
+  TSC_G8_IO3: 9
+PG1:
+  EVENTOUT: 15
+  FMC_A11: 12
+  TSC_G8_IO4: 9
+PG10:
+  EVENTOUT: 15
+  FMC_NE3: 12
+  LPTIM1_IN1: 1
+  SAI2_FS_A: 13
+  SPI3_MISO: 6
+  TIM15_CH1: 14
+  USART1_RX: 7
+PG11:
+  EVENTOUT: 15
+  LPTIM1_IN2: 1
+  SAI2_MCLK_A: 13
+  SPI3_MOSI: 6
+  TIM15_CH2: 14
+  USART1_CTS: 7
+PG12:
+  EVENTOUT: 15
+  FMC_NE4: 12
+  LPTIM1_ETR: 1
+  SAI2_SD_A: 13
+  SPI3_NSS: 6
+  USART1_DE: 7
+  USART1_RTS: 7
+PG13:
+  EVENTOUT: 15
+  FMC_A24: 12
+  I2C1_SDA: 4
+  USART1_CK: 7
+PG14:
+  EVENTOUT: 15
+  FMC_A25: 12
+  I2C1_SCL: 4
+PG15:
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  LPTIM1_OUT: 1
+PG2:
+  EVENTOUT: 15
+  FMC_A12: 12
+  SAI2_SCK_B: 13
+  SPI1_SCK: 5
+PG3:
+  EVENTOUT: 15
+  FMC_A13: 12
+  SAI2_FS_B: 13
+  SPI1_MISO: 5
+PG4:
+  EVENTOUT: 15
+  FMC_A14: 12
+  SAI2_MCLK_B: 13
+  SPI1_MOSI: 5
+PG5:
+  EVENTOUT: 15
+  FMC_A15: 12
+  LPUART1_CTS: 8
+  SAI2_SD_B: 13
+  SPI1_NSS: 5
+PG6:
+  EVENTOUT: 15
+  I2C3_SMBA: 4
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+PG7:
+  EVENTOUT: 15
+  FMC_INT3: 12
+  I2C3_SCL: 4
+  LPUART1_TX: 8
+PG8:
+  EVENTOUT: 15
+  I2C3_SDA: 4
+  LPUART1_RX: 8
+PG9:
+  EVENTOUT: 15
+  FMC_NCE3: 12
+  FMC_NE2: 12
+  SAI2_SCK_A: 13
+  SPI3_SCK: 6
+  TIM15_CH1N: 14
+  USART1_TX: 7
+PH0:
+  EVENTOUT: 15
+PH1:
+  EVENTOUT: 15
+PI8: {}

data/gpio_af/STM32L55x.yaml

@@ -0,0 +1,847 @@
+PA0:
+  EVENTOUT: 15
+  SAI1_EXTCLK: 13
+  TIM2_CH1: 1
+  TIM2_ETR: 14
+  TIM5_CH1: 2
+  TIM8_ETR: 3
+  UART4_TX: 8
+  USART2_CTS: 7
+  USART2_NSS: 7
+PA1:
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  OCTOSPI1_DQS: 10
+  SPI1_SCK: 5
+  TIM15_CH1N: 14
+  TIM2_CH2: 1
+  TIM5_CH2: 2
+  UART4_RX: 8
+  USART2_DE: 7
+  USART2_RTS: 7
+PA10:
+  CRS_SYNC: 10
+  EVENTOUT: 15
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  TIM17_BKIN: 14
+  TIM1_CH3: 1
+  USART1_RX: 7
+PA11:
+  EVENTOUT: 15
+  FDCAN1_RX: 9
+  SPI1_MISO: 5
+  TIM1_BKIN2: 12
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USART1_NSS: 7
+  USB_DM: 10
+PA12:
+  EVENTOUT: 15
+  FDCAN1_TX: 9
+  SPI1_MOSI: 5
+  TIM1_ETR: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+  USB_DP: 10
+PA13:
+  DEBUG_JTMS-SWDIO: 0
+  EVENTOUT: 15
+  IR_OUT: 1
+  SAI1_SD_B: 13
+  USB_NOE: 10
+PA14:
+  DEBUG_JTCK-SWCLK: 0
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  I2C4_SMBA: 5
+  LPTIM1_OUT: 1
+  SAI1_FS_B: 13
+PA15:
+  DEBUG_JTDI: 0
+  EVENTOUT: 15
+  SAI2_FS_B: 13
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+  UART4_DE: 8
+  UART4_RTS: 8
+  USART2_RX: 3
+  USART3_DE: 7
+  USART3_RTS: 7
+PA2:
+  EVENTOUT: 15
+  LPUART1_TX: 8
+  OCTOSPI1_NCS: 10
+  SAI2_EXTCLK: 13
+  TIM15_CH1: 14
+  TIM2_CH3: 1
+  TIM5_CH3: 2
+  UCPD1_FRSTX1: 11
+  UCPD1_FRSTX2: 11
+  USART2_TX: 7
+PA3:
+  EVENTOUT: 15
+  LPUART1_RX: 8
+  OCTOSPI1_CLK: 10
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 13
+  TIM15_CH2: 14
+  TIM2_CH4: 1
+  TIM5_CH4: 2
+  USART2_RX: 7
+PA4:
+  EVENTOUT: 15
+  LPTIM2_OUT: 14
+  OCTOSPI1_NCS: 3
+  SAI1_FS_B: 13
+  SPI1_NSS: 5
+  SPI3_NSS: 6
+  USART2_CK: 7
+PA5:
+  EVENTOUT: 15
+  LPTIM2_ETR: 14
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+  TIM8_CH1N: 3
+PA6:
+  EVENTOUT: 15
+  LPUART1_CTS: 8
+  OCTOSPI1_IO3: 10
+  SPI1_MISO: 5
+  TIM16_CH1: 14
+  TIM1_BKIN: 12
+  TIM3_CH1: 2
+  TIM8_BKIN: 13
+  USART3_CTS: 7
+  USART3_NSS: 7
+PA7:
+  EVENTOUT: 15
+  I2C3_SCL: 4
+  OCTOSPI1_IO2: 10
+  SPI1_MOSI: 5
+  TIM17_CH1: 14
+  TIM1_CH1N: 1
+  TIM3_CH2: 2
+  TIM8_CH1N: 3
+PA8:
+  EVENTOUT: 15
+  LPTIM2_OUT: 14
+  RCC_MCO: 0
+  SAI1_CK2: 3
+  SAI1_SCK_A: 13
+  TIM1_CH1: 1
+  USART1_CK: 7
+PA9:
+  EVENTOUT: 15
+  SAI1_FS_A: 13
+  SPI2_SCK: 3
+  TIM15_BKIN: 14
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  COMP1_OUT: 12
+  EVENTOUT: 15
+  OCTOSPI1_IO1: 10
+  SAI1_EXTCLK: 13
+  SPI1_NSS: 5
+  TIM1_CH2N: 1
+  TIM3_CH3: 2
+  TIM8_CH2N: 3
+  USART3_CK: 7
+PB1:
+  DFSDM1_DATIN0: 6
+  EVENTOUT: 15
+  LPTIM2_IN1: 14
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+  OCTOSPI1_IO0: 10
+  TIM1_CH3N: 1
+  TIM3_CH4: 2
+  TIM8_CH3N: 3
+  USART3_DE: 7
+  USART3_RTS: 7
+PB10:
+  COMP1_OUT: 12
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  I2C4_SCL: 3
+  LPTIM3_OUT: 2
+  LPUART1_RX: 8
+  OCTOSPI1_CLK: 10
+  SAI1_SCK_A: 13
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+  TSC_SYNC: 9
+  USART3_TX: 7
+PB11:
+  COMP2_OUT: 12
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  I2C4_SDA: 3
+  LPUART1_TX: 8
+  OCTOSPI1_NCS: 10
+  TIM2_CH4: 1
+  USART3_RX: 7
+PB12:
+  DFSDM1_DATIN1: 6
+  EVENTOUT: 15
+  I2C2_SMBA: 4
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+  OCTOSPI1_NCLK: 10
+  SAI2_FS_A: 13
+  SPI2_NSS: 5
+  TIM15_BKIN: 14
+  TIM1_BKIN: 3
+  TSC_G1_IO1: 9
+  USART3_CK: 7
+PB13:
+  DFSDM1_CKIN1: 6
+  EVENTOUT: 15
+  I2C2_SCL: 4
+  LPTIM3_IN1: 2
+  LPUART1_CTS: 8
+  SAI2_SCK_A: 13
+  SPI2_SCK: 5
+  TIM15_CH1N: 14
+  TIM1_CH1N: 1
+  TSC_G1_IO2: 9
+  UCPD1_FRSTX1: 11
+  UCPD1_FRSTX2: 11
+  USART3_CTS: 7
+  USART3_NSS: 7
+PB14:
+  DFSDM1_DATIN2: 6
+  EVENTOUT: 15
+  I2C2_SDA: 4
+  LPTIM3_ETR: 2
+  SAI2_MCLK_A: 13
+  SPI2_MISO: 5
+  TIM15_CH1: 14
+  TIM1_CH2N: 1
+  TIM8_CH2N: 3
+  TSC_G1_IO3: 9
+  USART3_DE: 7
+  USART3_RTS: 7
+PB15:
+  DFSDM1_CKIN2: 6
+  EVENTOUT: 15
+  RTC_REFIN: 0
+  SAI2_SD_A: 13
+  SPI2_MOSI: 5
+  TIM15_CH2: 14
+  TIM1_CH3N: 1
+  TIM8_CH3N: 3
+PB2:
+  DFSDM1_CKIN0: 6
+  EVENTOUT: 15
+  I2C3_SMBA: 4
+  LPTIM1_OUT: 1
+  OCTOSPI1_DQS: 10
+  UCPD1_FRSTX1: 11
+  UCPD1_FRSTX2: 11
+PB3:
+  CRS_SYNC: 10
+  DEBUG_JTDO-SWO: 0
+  EVENTOUT: 15
+  SAI1_SCK_B: 13
+  SPI1_SCK: 5
+  SPI3_SCK: 6
+  TIM2_CH2: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+PB4:
+  DEBUG_JTRST: 0
+  EVENTOUT: 15
+  I2C3_SDA: 4
+  SAI1_MCLK_B: 13
+  SPI1_MISO: 5
+  SPI3_MISO: 6
+  TIM17_BKIN: 14
+  TIM3_CH1: 2
+  TSC_G2_IO1: 9
+  UART5_DE: 8
+  UART5_RTS: 8
+  USART1_CTS: 7
+  USART1_NSS: 7
+PB5:
+  COMP2_OUT: 12
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  LPTIM1_IN1: 1
+  OCTOSPI1_NCLK: 3
+  SAI1_SD_B: 13
+  SPI1_MOSI: 5
+  SPI3_MOSI: 6
+  TIM16_BKIN: 14
+  TIM3_CH2: 2
+  TSC_G2_IO2: 9
+  UART5_CTS_NSS: 8
+  USART1_CK: 7
+PB6:
+  EVENTOUT: 15
+  I2C1_SCL: 4
+  I2C4_SCL: 5
+  LPTIM1_ETR: 1
+  SAI1_FS_B: 13
+  TIM16_CH1N: 14
+  TIM4_CH1: 2
+  TIM8_BKIN2: 12
+  TSC_G2_IO3: 9
+  USART1_TX: 7
+PB7:
+  EVENTOUT: 15
+  FMC_NL: 12
+  I2C1_SDA: 4
+  I2C4_SDA: 5
+  LPTIM1_IN2: 1
+  TIM17_CH1N: 14
+  TIM4_CH2: 2
+  TIM8_BKIN: 13
+  TSC_G2_IO4: 9
+  UART4_CTS_NSS: 8
+  USART1_RX: 7
+PB8:
+  DFSDM1_CKOUT: 5
+  EVENTOUT: 15
+  FDCAN1_RX: 9
+  I2C1_SCL: 4
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 13
+  SDMMC1_CKIN: 8
+  SDMMC1_D4: 12
+  TIM16_CH1: 14
+  TIM4_CH3: 2
+PB9:
+  EVENTOUT: 15
+  FDCAN1_TX: 9
+  I2C1_SDA: 4
+  IR_OUT: 1
+  SAI1_D2: 3
+  SAI1_FS_A: 13
+  SDMMC1_CDIR: 8
+  SDMMC1_D5: 12
+  SPI2_NSS: 5
+  TIM17_CH1: 14
+  TIM4_CH4: 2
+PC0:
+  EVENTOUT: 15
+  I2C3_SCL: 4
+  LPTIM1_IN1: 1
+  LPTIM2_IN1: 14
+  LPUART1_RX: 8
+  OCTOSPI1_IO7: 3
+  SAI2_FS_A: 13
+  SDMMC1_D5: 12
+PC1:
+  DEBUG_TRACED0: 0
+  EVENTOUT: 15
+  I2C3_SDA: 4
+  LPTIM1_OUT: 1
+  LPUART1_TX: 8
+  OCTOSPI1_IO4: 10
+  SAI1_SD_A: 13
+  SPI2_MOSI: 3
+PC10:
+  DEBUG_TRACED1: 0
+  EVENTOUT: 15
+  LPTIM3_ETR: 2
+  SAI2_SCK_B: 13
+  SDMMC1_D2: 12
+  SPI3_SCK: 6
+  TSC_G3_IO2: 9
+  UART4_TX: 8
+  USART3_TX: 7
+PC11:
+  EVENTOUT: 15
+  LPTIM3_IN1: 2
+  OCTOSPI1_NCS: 5
+  SAI2_MCLK_B: 13
+  SDMMC1_D3: 12
+  SPI3_MISO: 6
+  TSC_G3_IO3: 9
+  UART4_RX: 8
+  UCPD1_FRSTX1: 11
+  UCPD1_FRSTX2: 11
+  USART3_RX: 7
+PC12:
+  DEBUG_TRACED3: 0
+  EVENTOUT: 15
+  SAI2_SD_B: 13
+  SDMMC1_CK: 12
+  SPI3_MOSI: 6
+  TSC_G3_IO4: 9
+  UART5_TX: 8
+  USART3_CK: 7
+PC13:
+  EVENTOUT: 15
+PC14:
+  EVENTOUT: 15
+PC15:
+  EVENTOUT: 15
+PC2:
+  DFSDM1_CKOUT: 6
+  EVENTOUT: 15
+  LPTIM1_IN2: 1
+  OCTOSPI1_IO5: 10
+  SPI2_MISO: 5
+PC3:
+  EVENTOUT: 15
+  LPTIM1_ETR: 1
+  LPTIM2_ETR: 14
+  LPTIM3_OUT: 2
+  OCTOSPI1_IO6: 10
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  SPI2_MOSI: 5
+PC4:
+  EVENTOUT: 15
+  OCTOSPI1_IO7: 10
+  USART3_TX: 7
+PC5:
+  EVENTOUT: 15
+  SAI1_D3: 3
+  USART3_RX: 7
+PC6:
+  DFSDM1_CKIN3: 6
+  EVENTOUT: 15
+  SAI2_MCLK_A: 13
+  SDMMC1_D0DIR: 8
+  SDMMC1_D6: 12
+  TIM3_CH1: 2
+  TIM8_CH1: 3
+  TSC_G4_IO1: 9
+PC7:
+  DFSDM1_DATIN3: 6
+  EVENTOUT: 15
+  SAI2_MCLK_B: 13
+  SDMMC1_D123DIR: 8
+  SDMMC1_D7: 12
+  TIM3_CH2: 2
+  TIM8_CH2: 3
+  TSC_G4_IO2: 9
+PC8:
+  EVENTOUT: 15
+  SDMMC1_D0: 12
+  TIM3_CH3: 2
+  TIM8_CH3: 3
+  TSC_G4_IO3: 9
+PC9:
+  DEBUG_TRACED0: 0
+  EVENTOUT: 15
+  SAI2_EXTCLK: 13
+  SDMMC1_D1: 12
+  TIM3_CH4: 2
+  TIM8_BKIN2: 14
+  TIM8_CH4: 3
+  TSC_G4_IO4: 9
+  USB_NOE: 10
+PD0:
+  EVENTOUT: 15
+  FDCAN1_RX: 9
+  FMC_D2: 12
+  FMC_DA2: 12
+  SPI2_NSS: 5
+PD1:
+  EVENTOUT: 15
+  FDCAN1_TX: 9
+  FMC_D3: 12
+  FMC_DA3: 12
+  SPI2_SCK: 5
+PD10:
+  EVENTOUT: 15
+  FMC_D15: 12
+  FMC_DA15: 12
+  SAI2_SCK_A: 13
+  TSC_G6_IO1: 9
+  USART3_CK: 7
+PD11:
+  EVENTOUT: 15
+  FMC_A16: 12
+  I2C4_SMBA: 4
+  LPTIM2_ETR: 14
+  SAI2_SD_A: 13
+  TSC_G6_IO2: 9
+  USART3_CTS: 7
+  USART3_NSS: 7
+PD12:
+  EVENTOUT: 15
+  FMC_A17: 12
+  I2C4_SCL: 4
+  LPTIM2_IN1: 14
+  SAI2_FS_A: 13
+  TIM4_CH1: 2
+  TSC_G6_IO3: 9
+  USART3_DE: 7
+  USART3_RTS: 7
+PD13:
+  EVENTOUT: 15
+  FMC_A18: 12
+  I2C4_SDA: 4
+  LPTIM2_OUT: 14
+  TIM4_CH2: 2
+  TSC_G6_IO4: 9
+PD14:
+  EVENTOUT: 15
+  FMC_D0: 12
+  FMC_DA0: 12
+  TIM4_CH3: 2
+PD15:
+  EVENTOUT: 15
+  FMC_D1: 12
+  FMC_DA1: 12
+  TIM4_CH4: 2
+PD2:
+  DEBUG_TRACED2: 0
+  EVENTOUT: 15
+  SDMMC1_CMD: 12
+  TIM3_ETR: 2
+  TSC_SYNC: 9
+  UART5_RX: 8
+  USART3_DE: 7
+  USART3_RTS: 7
+PD3:
+  DFSDM1_DATIN0: 6
+  EVENTOUT: 15
+  FMC_CLK: 12
+  SPI2_MISO: 5
+  SPI2_SCK: 3
+  USART2_CTS: 7
+  USART2_NSS: 7
+PD4:
+  DFSDM1_CKIN0: 6
+  EVENTOUT: 15
+  FMC_NOE: 12
+  OCTOSPI1_IO4: 10
+  SPI2_MOSI: 5
+  USART2_DE: 7
+  USART2_RTS: 7
+PD5:
+  EVENTOUT: 15
+  FMC_NWE: 12
+  OCTOSPI1_IO5: 10
+  USART2_TX: 7
+PD6:
+  DFSDM1_DATIN1: 6
+  EVENTOUT: 15
+  FMC_NWAIT: 12
+  OCTOSPI1_IO6: 10
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  SPI3_MOSI: 5
+  USART2_RX: 7
+PD7:
+  DFSDM1_CKIN1: 6
+  EVENTOUT: 15
+  FMC_NCE: 12
+  FMC_NE1: 12
+  OCTOSPI1_IO7: 10
+  USART2_CK: 7
+PD8:
+  EVENTOUT: 15
+  FMC_D13: 12
+  FMC_DA13: 12
+  USART3_TX: 7
+PD9:
+  EVENTOUT: 15
+  FMC_D14: 12
+  FMC_DA14: 12
+  SAI2_MCLK_A: 13
+  USART3_RX: 7
+PE0:
+  EVENTOUT: 15
+  FMC_NBL0: 12
+  TIM16_CH1: 14
+  TIM4_ETR: 2
+PE1:
+  EVENTOUT: 15
+  FMC_NBL1: 12
+  TIM17_CH1: 14
+PE10:
+  EVENTOUT: 15
+  FMC_D7: 12
+  FMC_DA7: 12
+  OCTOSPI1_CLK: 10
+  SAI1_MCLK_B: 13
+  TIM1_CH2N: 1
+  TSC_G5_IO1: 9
+PE11:
+  EVENTOUT: 15
+  FMC_D8: 12
+  FMC_DA8: 12
+  OCTOSPI1_NCS: 10
+  TIM1_CH2: 1
+  TSC_G5_IO2: 9
+PE12:
+  EVENTOUT: 15
+  FMC_D9: 12
+  FMC_DA9: 12
+  OCTOSPI1_IO0: 10
+  SPI1_NSS: 5
+  TIM1_CH3N: 1
+  TSC_G5_IO3: 9
+PE13:
+  EVENTOUT: 15
+  FMC_D10: 12
+  FMC_DA10: 12
+  OCTOSPI1_IO1: 10
+  SPI1_SCK: 5
+  TIM1_CH3: 1
+  TSC_G5_IO4: 9
+PE14:
+  EVENTOUT: 15
+  FMC_D11: 12
+  FMC_DA11: 12
+  OCTOSPI1_IO2: 10
+  SPI1_MISO: 5
+  TIM1_BKIN2: 3
+  TIM1_CH4: 1
+PE15:
+  EVENTOUT: 15
+  FMC_D12: 12
+  FMC_DA12: 12
+  OCTOSPI1_IO3: 10
+  SPI1_MOSI: 5
+  TIM1_BKIN: 3
+PE2:
+  DEBUG_TRACECLK: 0
+  EVENTOUT: 15
+  FMC_A23: 12
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 13
+  TIM3_ETR: 2
+  TSC_G7_IO1: 9
+PE3:
+  DEBUG_TRACED0: 0
+  EVENTOUT: 15
+  FMC_A19: 12
+  OCTOSPI1_DQS: 3
+  SAI1_SD_B: 13
+  TIM3_CH1: 2
+  TSC_G7_IO2: 9
+PE4:
+  DEBUG_TRACED1: 0
+  DFSDM1_DATIN3: 6
+  EVENTOUT: 15
+  FMC_A20: 12
+  SAI1_D2: 3
+  SAI1_FS_A: 13
+  TIM3_CH2: 2
+  TSC_G7_IO3: 9
+PE5:
+  DEBUG_TRACED2: 0
+  DFSDM1_CKIN3: 6
+  EVENTOUT: 15
+  FMC_A21: 12
+  SAI1_CK2: 3
+  SAI1_SCK_A: 13
+  TIM3_CH3: 2
+  TSC_G7_IO4: 9
+PE6:
+  DEBUG_TRACED3: 0
+  EVENTOUT: 15
+  FMC_A22: 12
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  TIM3_CH4: 2
+PE7:
+  DFSDM1_DATIN2: 6
+  EVENTOUT: 15
+  FMC_D4: 12
+  FMC_DA4: 12
+  SAI1_SD_B: 13
+  TIM1_ETR: 1
+PE8:
+  DFSDM1_CKIN2: 6
+  EVENTOUT: 15
+  FMC_D5: 12
+  FMC_DA5: 12
+  SAI1_SCK_B: 13
+  TIM1_CH1N: 1
+PE9:
+  DFSDM1_CKOUT: 6
+  EVENTOUT: 15
+  FMC_D6: 12
+  FMC_DA6: 12
+  OCTOSPI1_NCLK: 10
+  SAI1_FS_B: 13
+  TIM1_CH1: 1
+PF0:
+  EVENTOUT: 15
+  FMC_A0: 12
+  I2C2_SDA: 4
+PF1:
+  EVENTOUT: 15
+  FMC_A1: 12
+  I2C2_SCL: 4
+PF10:
+  DFSDM1_CKOUT: 6
+  EVENTOUT: 15
+  OCTOSPI1_CLK: 3
+  SAI1_D3: 13
+  TIM15_CH2: 14
+PF11:
+  EVENTOUT: 15
+  OCTOSPI1_NCLK: 3
+PF12:
+  EVENTOUT: 15
+  FMC_A6: 12
+PF13:
+  EVENTOUT: 15
+  FMC_A7: 12
+  I2C4_SMBA: 4
+PF14:
+  EVENTOUT: 15
+  FMC_A8: 12
+  I2C4_SCL: 4
+  TSC_G8_IO1: 9
+PF15:
+  EVENTOUT: 15
+  FMC_A9: 12
+  I2C4_SDA: 4
+  TSC_G8_IO2: 9
+PF2:
+  EVENTOUT: 15
+  FMC_A2: 12
+  I2C2_SMBA: 4
+PF3:
+  EVENTOUT: 15
+  FMC_A3: 12
+  LPTIM3_IN1: 2
+PF4:
+  EVENTOUT: 15
+  FMC_A4: 12
+  LPTIM3_ETR: 2
+PF5:
+  EVENTOUT: 15
+  FMC_A5: 12
+  LPTIM3_OUT: 2
+PF6:
+  EVENTOUT: 15
+  OCTOSPI1_IO3: 10
+  SAI1_SD_B: 13
+  TIM5_CH1: 2
+  TIM5_ETR: 1
+PF7:
+  EVENTOUT: 15
+  OCTOSPI1_IO2: 10
+  SAI1_MCLK_B: 13
+  TIM5_CH2: 2
+PF8:
+  EVENTOUT: 15
+  OCTOSPI1_IO0: 10
+  SAI1_SCK_B: 13
+  TIM5_CH3: 2
+PF9:
+  EVENTOUT: 15
+  OCTOSPI1_IO1: 10
+  SAI1_FS_B: 13
+  TIM15_CH1: 14
+  TIM5_CH4: 2
+PG0:
+  EVENTOUT: 15
+  FMC_A10: 12
+  TSC_G8_IO3: 9
+PG1:
+  EVENTOUT: 15
+  FMC_A11: 12
+  TSC_G8_IO4: 9
+PG10:
+  EVENTOUT: 15
+  FMC_NE3: 12
+  LPTIM1_IN1: 1
+  SAI2_FS_A: 13
+  SPI3_MISO: 6
+  TIM15_CH1: 14
+  USART1_RX: 7
+PG11:
+  EVENTOUT: 15
+  LPTIM1_IN2: 1
+  OCTOSPI1_IO5: 3
+  SAI2_MCLK_A: 13
+  SPI3_MOSI: 6
+  TIM15_CH2: 14
+  USART1_CTS: 7
+  USART1_NSS: 7
+PG12:
+  EVENTOUT: 15
+  FMC_NE4: 12
+  LPTIM1_ETR: 1
+  SAI2_SD_A: 13
+  SPI3_NSS: 6
+  USART1_DE: 7
+  USART1_RTS: 7
+PG13:
+  EVENTOUT: 15
+  FMC_A24: 12
+  I2C1_SDA: 4
+  USART1_CK: 7
+PG14:
+  EVENTOUT: 15
+  FMC_A25: 12
+  I2C1_SCL: 4
+PG15:
+  EVENTOUT: 15
+  I2C1_SMBA: 4
+  LPTIM1_OUT: 1
+PG2:
+  EVENTOUT: 15
+  FMC_A12: 12
+  SAI2_SCK_B: 13
+  SPI1_SCK: 5
+PG3:
+  EVENTOUT: 15
+  FMC_A13: 12
+  SAI2_FS_B: 13
+  SPI1_MISO: 5
+PG4:
+  EVENTOUT: 15
+  FMC_A14: 12
+  SAI2_MCLK_B: 13
+  SPI1_MOSI: 5
+PG5:
+  EVENTOUT: 15
+  FMC_A15: 12
+  LPUART1_CTS: 8
+  SAI2_SD_B: 13
+  SPI1_NSS: 5
+PG6:
+  EVENTOUT: 15
+  I2C3_SMBA: 4
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+  OCTOSPI1_DQS: 3
+  UCPD1_FRSTX1: 11
+  UCPD1_FRSTX2: 11
+PG7:
+  DFSDM1_CKOUT: 6
+  EVENTOUT: 15
+  FMC_INT: 12
+  I2C3_SCL: 4
+  LPUART1_TX: 8
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 13
+  UCPD1_FRSTX1: 11
+  UCPD1_FRSTX2: 11
+PG8:
+  EVENTOUT: 15
+  I2C3_SDA: 4
+  LPUART1_RX: 8
+PG9:
+  EVENTOUT: 15
+  FMC_NCE: 12
+  FMC_NE2: 12
+  SAI2_SCK_A: 13
+  SPI3_SCK: 6
+  TIM15_CH1N: 14
+  USART1_TX: 7
+PH0:
+  EVENTOUT: 15
+PH1:
+  EVENTOUT: 15
+PH3:
+  EVENTOUT: 15
+PI8: {}

data/gpio_af/STM32WB35x.yaml

@@ -0,0 +1,182 @@
+PA0:
+  CM4_EVENTOUT: 15
+  COMP1_OUT: 12
+  TIM2_CH1: 1
+  TIM2_ETR: 14
+PA1:
+  CM4_EVENTOUT: 15
+  I2C1_SMBA: 4
+  SPI1_SCK: 5
+  TIM2_CH2: 1
+PA10:
+  CM4_EVENTOUT: 15
+  I2C1_SDA: 4
+  TIM1_CH3: 1
+  TSC_G7_IO2: 9
+  USART1_RX: 7
+PA11:
+  CM4_EVENTOUT: 15
+  SPI1_MISO: 5
+  TIM1_BKIN2: 2
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USART1_NSS: 7
+PA12:
+  CM4_EVENTOUT: 15
+  LPUART1_RX: 8
+  SPI1_MOSI: 5
+  TIM1_ETR: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+PA13:
+  CM4_EVENTOUT: 15
+  SPI1_MOSI: 5
+  SYS_JTMS-SWDIO: 0
+  TSC_G7_IO1: 9
+PA14:
+  CM4_EVENTOUT: 15
+  I2C1_SMBA: 4
+  LPTIM1_OUT: 1
+  SPI1_NSS: 5
+  SYS_JTCK-SWCLK: 0
+PA15:
+  CM4_EVENTOUT: 15
+  RCC_MCO: 6
+  SPI1_NSS: 5
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+  TSC_G3_IO1: 9
+PA2:
+  CM4_EVENTOUT: 15
+  LPUART1_TX: 8
+  RCC_LSCO: 0
+  TIM2_CH3: 1
+PA3:
+  CM4_EVENTOUT: 15
+  LPUART1_RX: 8
+  TIM2_CH4: 1
+PA4:
+  CM4_EVENTOUT: 15
+  LPTIM2_OUT: 14
+  SPI1_NSS: 5
+PA5:
+  CM4_EVENTOUT: 15
+  LPTIM2_ETR: 14
+  SPI1_MOSI: 4
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+PA6:
+  CM4_EVENTOUT: 15
+  LPUART1_CTS: 8
+  SPI1_MISO: 5
+  TIM1_BKIN: 1
+PA7:
+  CM4_EVENTOUT: 15
+  SPI1_MOSI: 5
+  TIM1_CH1N: 1
+PA8:
+  CM4_EVENTOUT: 15
+  LPTIM2_OUT: 14
+  RCC_MCO: 0
+  TIM1_CH1: 1
+  USART1_CK: 7
+PA9:
+  CM4_EVENTOUT: 15
+  I2C1_SCL: 4
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  CM4_EVENTOUT: 15
+  COMP1_OUT: 12
+  RF_TX_MOD_EXT_PA: 6
+PB1:
+  CM4_EVENTOUT: 15
+  LPTIM2_IN1: 14
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+PB10:
+  CM4_EVENTOUT: 15
+  TSC_G3_IO2: 9
+PB12:
+  CM4_EVENTOUT: 15
+  TIM2_CH2: 1
+  TSC_G1_IO1: 9
+PB13:
+  CM4_EVENTOUT: 15
+  TIM2_CH3: 1
+  TSC_G1_IO2: 9
+PB14:
+  CM4_EVENTOUT: 15
+  TIM1_CH1: 1
+PB15:
+  CM4_EVENTOUT: 15
+  TIM2_CH1: 1
+PB2:
+  CM4_EVENTOUT: 15
+  LPTIM1_OUT: 1
+  RTC_OUT: 0
+  SPI1_NSS: 5
+PB3:
+  CM4_EVENTOUT: 15
+  SPI1_SCK: 5
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+PB4:
+  CM4_EVENTOUT: 15
+  SPI1_MISO: 5
+  SYS_JTRST: 0
+  TSC_G2_IO1: 9
+  USART1_CTS: 7
+  USART1_NSS: 7
+PB5:
+  CM4_EVENTOUT: 15
+  I2C1_SMBA: 4
+  LPTIM1_IN1: 1
+  LPUART1_TX: 8
+  SPI1_MOSI: 5
+  TSC_G2_IO2: 9
+  USART1_CK: 7
+PB6:
+  CM4_EVENTOUT: 15
+  I2C1_SCL: 4
+  LPTIM1_ETR: 1
+  RCC_MCO: 0
+  SPI1_NSS: 5
+  TSC_G2_IO3: 9
+  USART1_TX: 7
+PB7:
+  CM4_EVENTOUT: 15
+  I2C1_SDA: 4
+  LPTIM1_IN2: 1
+  TIM1_BKIN: 3
+  TIM1_CH3: 12
+  TSC_G2_IO4: 9
+  USART1_RX: 7
+PB8:
+  CM4_EVENTOUT: 15
+  I2C1_SCL: 4
+  TIM1_CH2N: 1
+  TSC_G7_IO3: 9
+PB9:
+  CM4_EVENTOUT: 15
+  I2C1_SDA: 4
+  TIM1_CH3N: 1
+  TSC_G7_IO4: 9
+PC1:
+  CM4_EVENTOUT: 15
+  TSC_G3_IO3: 9
+PC13: {}
+PC14:
+  CM4_EVENTOUT: 15
+PC15:
+  CM4_EVENTOUT: 15
+PE4:
+  CM4_EVENTOUT: 15
+PH3:
+  CM4_EVENTOUT: 15
+  RCC_LSCO: 0
+PI8: {}

data/gpio_af/STM32WB55x.yaml

@@ -0,0 +1,451 @@
+PA0:
+  CM4_EVENTOUT: 15
+  COMP1_OUT: 12
+  SAI1_EXTCLK: 13
+  TIM2_CH1: 1
+  TIM2_ETR: 14
+PA1:
+  CM4_EVENTOUT: 15
+  I2C1_SMBA: 4
+  LCD_SEG0: 11
+  SPI1_SCK: 5
+  TIM2_CH2: 1
+PA10:
+  CM4_EVENTOUT: 15
+  CRS_SYNC: 10
+  I2C1_SDA: 4
+  LCD_COM2: 11
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  TIM17_BKIN: 14
+  TIM1_CH3: 1
+  USART1_RX: 7
+PA11:
+  CM4_EVENTOUT: 15
+  SPI1_MISO: 5
+  TIM1_BKIN2: 12
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USART1_NSS: 7
+  USB_DM: 10
+PA12:
+  CM4_EVENTOUT: 15
+  LPUART1_RX: 8
+  SPI1_MOSI: 5
+  TIM1_ETR: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+  USB_DP: 10
+PA13:
+  CM4_EVENTOUT: 15
+  IR_OUT: 8
+  SAI1_SD_B: 13
+  SYS_JTMS-SWDIO: 0
+  USB_NOE: 10
+PA14:
+  CM4_EVENTOUT: 15
+  I2C1_SMBA: 4
+  LCD_SEG5: 11
+  LPTIM1_OUT: 1
+  SAI1_FS_B: 13
+  SYS_JTCK-SWCLK: 0
+PA15:
+  CM4_EVENTOUT: 15
+  LCD_SEG17: 11
+  RCC_MCO: 6
+  SPI1_NSS: 5
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+  TSC_G3_IO1: 9
+PA2:
+  CM4_EVENTOUT: 15
+  COMP2_OUT: 12
+  LCD_SEG1: 11
+  LPUART1_TX: 8
+  QUADSPI_BK1_NCS: 10
+  RCC_LSCO: 0
+  TIM2_CH3: 1
+PA3:
+  CM4_EVENTOUT: 15
+  LCD_SEG2: 11
+  LPUART1_RX: 8
+  QUADSPI_CLK: 10
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 13
+  TIM2_CH4: 1
+PA4:
+  CM4_EVENTOUT: 15
+  LCD_SEG5: 11
+  LPTIM2_OUT: 14
+  SAI1_FS_B: 13
+  SPI1_NSS: 5
+PA5:
+  CM4_EVENTOUT: 15
+  LPTIM2_ETR: 14
+  SAI1_SD_B: 13
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+PA6:
+  CM4_EVENTOUT: 15
+  LCD_SEG3: 11
+  LPUART1_CTS: 8
+  QUADSPI_BK1_IO3: 10
+  SPI1_MISO: 5
+  TIM16_CH1: 14
+  TIM1_BKIN: 12
+PA7:
+  CM4_EVENTOUT: 15
+  COMP2_OUT: 12
+  I2C3_SCL: 4
+  LCD_SEG4: 11
+  QUADSPI_BK1_IO2: 10
+  SPI1_MOSI: 5
+  TIM17_CH1: 14
+  TIM1_CH1N: 1
+PA8:
+  CM4_EVENTOUT: 15
+  LCD_COM0: 11
+  LPTIM2_OUT: 14
+  RCC_MCO: 0
+  SAI1_CK2: 3
+  SAI1_SCK_A: 13
+  TIM1_CH1: 1
+  USART1_CK: 7
+PA9:
+  CM4_EVENTOUT: 15
+  I2C1_SCL: 4
+  LCD_COM1: 11
+  SAI1_D2: 3
+  SAI1_FS_A: 13
+  SPI2_SCK: 5
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  CM4_EVENTOUT: 15
+  COMP1_OUT: 12
+  RF_TX_MOD_EXT_PA: 6
+PB1:
+  CM4_EVENTOUT: 15
+  LPTIM2_IN1: 14
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+PB10:
+  CM4_EVENTOUT: 15
+  COMP1_OUT: 12
+  I2C3_SCL: 4
+  LCD_SEG10: 11
+  LPUART1_RX: 8
+  QUADSPI_CLK: 10
+  SAI1_SCK_A: 13
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+  TSC_SYNC: 9
+PB11:
+  CM4_EVENTOUT: 15
+  COMP2_OUT: 12
+  I2C3_SDA: 4
+  LCD_SEG11: 11
+  LPUART1_TX: 8
+  QUADSPI_BK1_NCS: 10
+  TIM2_CH4: 1
+PB12:
+  CM4_EVENTOUT: 15
+  I2C3_SMBA: 4
+  LCD_SEG12: 11
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+  SAI1_FS_A: 13
+  SPI2_NSS: 5
+  TIM1_BKIN: 3
+  TSC_G1_IO1: 9
+PB13:
+  CM4_EVENTOUT: 15
+  I2C3_SCL: 4
+  LCD_SEG13: 11
+  LPUART1_CTS: 8
+  SAI1_SCK_A: 13
+  SPI2_SCK: 5
+  TIM1_CH1N: 1
+  TSC_G1_IO2: 9
+PB14:
+  CM4_EVENTOUT: 15
+  I2C3_SDA: 4
+  LCD_SEG14: 11
+  SAI1_MCLK_A: 13
+  SPI2_MISO: 5
+  TIM1_CH2N: 1
+  TSC_G1_IO3: 9
+PB15:
+  CM4_EVENTOUT: 15
+  LCD_SEG15: 11
+  RTC_REFIN: 0
+  SAI1_SD_A: 13
+  SPI2_MOSI: 5
+  TIM1_CH3N: 1
+  TSC_G1_IO4: 9
+PB2:
+  CM4_EVENTOUT: 15
+  I2C3_SMBA: 4
+  LCD_VLCD: 11
+  LPTIM1_OUT: 1
+  SAI1_EXTCLK: 13
+  SPI1_NSS: 5
+PB3:
+  CM4_EVENTOUT: 15
+  LCD_SEG7: 11
+  SAI1_SCK_B: 13
+  SPI1_SCK: 5
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+PB4:
+  CM4_EVENTOUT: 15
+  I2C3_SDA: 4
+  LCD_SEG8: 11
+  SAI1_MCLK_B: 13
+  SPI1_MISO: 5
+  SYS_JTRST: 0
+  TIM17_BKIN: 14
+  TSC_G2_IO1: 9
+  USART1_CTS: 7
+  USART1_NSS: 7
+PB5:
+  CM4_EVENTOUT: 15
+  COMP2_OUT: 12
+  I2C1_SMBA: 4
+  LCD_SEG9: 11
+  LPTIM1_IN1: 1
+  LPUART1_TX: 8
+  SAI1_SD_B: 13
+  SPI1_MOSI: 5
+  TIM16_BKIN: 14
+  TSC_G2_IO2: 9
+  USART1_CK: 7
+PB6:
+  CM4_EVENTOUT: 15
+  I2C1_SCL: 4
+  LCD_SEG6: 11
+  LPTIM1_ETR: 1
+  RCC_MCO: 0
+  SAI1_FS_B: 13
+  TIM16_CH1N: 14
+  TSC_G2_IO3: 9
+  USART1_TX: 7
+PB7:
+  CM4_EVENTOUT: 15
+  I2C1_SDA: 4
+  LCD_SEG21: 11
+  LPTIM1_IN2: 1
+  TIM17_CH1N: 14
+  TIM1_BKIN: 3
+  TSC_G2_IO4: 9
+  USART1_RX: 7
+PB8:
+  CM4_EVENTOUT: 15
+  I2C1_SCL: 4
+  LCD_SEG16: 11
+  QUADSPI_BK1_IO1: 10
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 13
+  TIM16_CH1: 14
+  TIM1_CH2N: 1
+PB9:
+  CM4_EVENTOUT: 15
+  I2C1_SDA: 4
+  IR_OUT: 8
+  LCD_COM3: 11
+  QUADSPI_BK1_IO0: 10
+  SAI1_D2: 3
+  SAI1_FS_A: 13
+  SPI2_NSS: 5
+  TIM17_CH1: 14
+  TIM1_CH3N: 1
+  TSC_G7_IO4: 9
+PC0:
+  CM4_EVENTOUT: 15
+  I2C3_SCL: 4
+  LCD_SEG18: 11
+  LPTIM1_IN1: 1
+  LPTIM2_IN1: 14
+  LPUART1_RX: 8
+PC1:
+  CM4_EVENTOUT: 15
+  I2C3_SDA: 4
+  LCD_SEG19: 11
+  LPTIM1_OUT: 1
+  LPUART1_TX: 8
+  SPI2_MOSI: 3
+PC10:
+  CM4_EVENTOUT: 15
+  LCD_COM4: 11
+  LCD_SEG28: 11
+  LCD_SEG40: 11
+  SYS_TRACED1: 0
+  TSC_G3_IO2: 9
+PC11:
+  CM4_EVENTOUT: 15
+  LCD_COM5: 11
+  LCD_SEG29: 11
+  LCD_SEG41: 11
+  TSC_G3_IO3: 9
+PC12:
+  CM4_EVENTOUT: 15
+  LCD_COM6: 11
+  LCD_SEG30: 11
+  LCD_SEG42: 11
+  RCC_LSCO: 6
+  SYS_TRACED3: 0
+  TSC_G3_IO4: 9
+PC13:
+  CM4_EVENTOUT: 15
+PC14:
+  CM4_EVENTOUT: 15
+PC15:
+  CM4_EVENTOUT: 15
+PC2:
+  CM4_EVENTOUT: 15
+  LCD_SEG20: 11
+  LPTIM1_IN2: 1
+  SPI2_MISO: 5
+PC3:
+  CM4_EVENTOUT: 15
+  LCD_VLCD: 11
+  LPTIM1_ETR: 1
+  LPTIM2_ETR: 14
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  SPI2_MOSI: 5
+PC4:
+  CM4_EVENTOUT: 15
+  LCD_SEG22: 11
+PC5:
+  CM4_EVENTOUT: 15
+  LCD_SEG23: 11
+  SAI1_D3: 3
+PC6:
+  CM4_EVENTOUT: 15
+  LCD_SEG24: 11
+  TSC_G4_IO1: 9
+PC7:
+  CM4_EVENTOUT: 15
+  LCD_SEG25: 11
+  TSC_G4_IO2: 9
+PC8:
+  CM4_EVENTOUT: 15
+  LCD_SEG26: 11
+  TSC_G4_IO3: 9
+PC9:
+  CM4_EVENTOUT: 15
+  LCD_SEG27: 11
+  SAI1_SCK_B: 13
+  TIM1_BKIN: 3
+  TSC_G4_IO4: 9
+  USB_NOE: 10
+PD0:
+  CM4_EVENTOUT: 15
+  SPI2_NSS: 5
+PD1:
+  CM4_EVENTOUT: 15
+  SPI2_SCK: 5
+PD10:
+  CM4_EVENTOUT: 15
+  LCD_SEG30: 11
+  TRIG_INOUT: 0
+  TSC_G6_IO1: 9
+PD11:
+  CM4_EVENTOUT: 15
+  LCD_SEG31: 11
+  LPTIM2_ETR: 14
+  TSC_G6_IO2: 9
+PD12:
+  CM4_EVENTOUT: 15
+  LCD_SEG32: 11
+  LPTIM2_IN1: 14
+  TSC_G6_IO3: 9
+PD13:
+  CM4_EVENTOUT: 15
+  LCD_SEG33: 11
+  LPTIM2_OUT: 14
+  TSC_G6_IO4: 9
+PD14:
+  CM4_EVENTOUT: 15
+  LCD_SEG34: 11
+  TIM1_CH1: 1
+PD15:
+  CM4_EVENTOUT: 15
+  LCD_SEG35: 11
+  TIM1_CH2: 1
+PD2:
+  CM4_EVENTOUT: 15
+  LCD_COM7: 11
+  LCD_SEG31: 11
+  LCD_SEG43: 11
+  SYS_TRACED2: 0
+  TSC_SYNC: 9
+PD3:
+  CM4_EVENTOUT: 15
+  QUADSPI_BK1_NCS: 10
+  SPI2_MISO: 5
+  SPI2_SCK: 3
+PD4:
+  CM4_EVENTOUT: 15
+  QUADSPI_BK1_IO0: 10
+  SPI2_MOSI: 5
+  TSC_G5_IO1: 9
+PD5:
+  CM4_EVENTOUT: 15
+  QUADSPI_BK1_IO1: 10
+  SAI1_MCLK_B: 13
+  TSC_G5_IO2: 9
+PD6:
+  CM4_EVENTOUT: 15
+  QUADSPI_BK1_IO2: 10
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  TSC_G5_IO3: 9
+PD7:
+  CM4_EVENTOUT: 15
+  LCD_SEG39: 11
+  QUADSPI_BK1_IO3: 10
+  TSC_G5_IO4: 9
+PD8:
+  CM4_EVENTOUT: 15
+  LCD_SEG28: 11
+  TIM1_BKIN2: 2
+PD9:
+  CM4_EVENTOUT: 15
+  LCD_SEG29: 11
+  SYS_TRACED0: 0
+PE0:
+  CM4_EVENTOUT: 15
+  LCD_SEG36: 11
+  TIM16_CH1: 14
+  TIM1_ETR: 1
+  TSC_G7_IO3: 9
+PE1:
+  CM4_EVENTOUT: 15
+  LCD_SEG37: 11
+  TIM17_CH1: 14
+  TSC_G7_IO2: 9
+PE2:
+  CM4_EVENTOUT: 15
+  LCD_SEG38: 11
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 13
+  SYS_TRACECLK: 0
+  TSC_G7_IO1: 9
+PE3:
+  CM4_EVENTOUT: 15
+PE4:
+  CM4_EVENTOUT: 15
+PH0:
+  CM4_EVENTOUT: 15
+PH1:
+  CM4_EVENTOUT: 15
+PH3:
+  CM4_EVENTOUT: 15
+  RCC_LSCO: 0
+PI8: {}

data/gpio_af/STM32WB5Mx.yaml

@@ -0,0 +1,452 @@
+PA0:
+  CM4_EVENTOUT: 15
+  COMP1_OUT: 12
+  SAI1_EXTCLK: 13
+  TIM2_CH1: 1
+  TIM2_ETR: 14
+PA1:
+  CM4_EVENTOUT: 15
+  I2C1_SMBA: 4
+  LCD_SEG0: 11
+  SPI1_SCK: 5
+  TIM2_CH2: 1
+PA10:
+  CM4_EVENTOUT: 15
+  CRS_SYNC: 10
+  I2C1_SDA: 4
+  LCD_COM2: 11
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  TIM17_BKIN: 14
+  TIM1_CH3: 1
+  USART1_RX: 7
+PA11:
+  CM4_EVENTOUT: 15
+  SPI1_MISO: 5
+  TIM1_BKIN2: 12
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USART1_NSS: 7
+  USB_DM: 10
+PA12:
+  CM4_EVENTOUT: 15
+  LPUART1_RX: 8
+  SPI1_MOSI: 5
+  TIM1_ETR: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+  USB_DP: 10
+PA13:
+  CM4_EVENTOUT: 15
+  IR_OUT: 8
+  SAI1_SD_B: 13
+  SYS_JTMS-SWDIO: 0
+  USB_NOE: 10
+PA14:
+  CM4_EVENTOUT: 15
+  I2C1_SMBA: 4
+  LCD_SEG5: 11
+  LPTIM1_OUT: 1
+  SAI1_FS_B: 13
+  SYS_JTCK-SWCLK: 0
+PA15:
+  CM4_EVENTOUT: 15
+  LCD_SEG17: 11
+  SPI1_NSS: 5
+  SYS_JTDI: 0
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+  TSC_G3_IO1: 9
+PA2:
+  CM4_EVENTOUT: 15
+  COMP2_OUT: 12
+  LCD_SEG1: 11
+  LPUART1_TX: 8
+  QUADSPI_BK1_NCS: 10
+  RCC_LSCO: 0
+  TIM2_CH3: 1
+PA3:
+  CM4_EVENTOUT: 15
+  LCD_SEG2: 11
+  LPUART1_RX: 8
+  QUADSPI_CLK: 10
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 13
+  TIM2_CH4: 1
+PA4:
+  CM4_EVENTOUT: 15
+  LCD_SEG5: 11
+  LPTIM2_OUT: 14
+  SAI1_FS_B: 13
+  SPI1_NSS: 5
+PA5:
+  CM4_EVENTOUT: 15
+  LPTIM2_ETR: 14
+  SAI1_SD_B: 13
+  SPI1_SCK: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+PA6:
+  CM4_EVENTOUT: 15
+  LCD_SEG3: 11
+  LPUART1_CTS: 8
+  QUADSPI_BK1_IO3: 10
+  SPI1_MISO: 5
+  TIM16_CH1: 14
+  TIM1_BKIN: 12
+PA7:
+  CM4_EVENTOUT: 15
+  COMP2_OUT: 12
+  I2C3_SCL: 4
+  LCD_SEG4: 11
+  QUADSPI_BK1_IO2: 10
+  SPI1_MOSI: 5
+  TIM17_CH1: 14
+  TIM1_CH1N: 1
+PA8:
+  CM4_EVENTOUT: 15
+  LCD_COM0: 11
+  LPTIM2_OUT: 14
+  RCC_MCO: 0
+  SAI1_CK2: 3
+  SAI1_SCK_A: 13
+  TIM1_CH1: 1
+  USART1_CK: 7
+PA9:
+  CM4_EVENTOUT: 15
+  I2C1_SCL: 4
+  LCD_COM1: 11
+  SAI1_D2: 3
+  SAI1_FS_A: 13
+  SPI2_SCK: 5
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  CM4_EVENTOUT: 15
+  COMP1_OUT: 12
+  RF_TX_MOD_EXT_PA: 6
+PB1:
+  CM4_EVENTOUT: 15
+  LPTIM2_IN1: 14
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+PB10:
+  CM4_EVENTOUT: 15
+  COMP1_OUT: 12
+  I2C3_SCL: 4
+  LCD_SEG10: 11
+  LPUART1_RX: 8
+  QUADSPI_CLK: 10
+  SAI1_SCK_A: 13
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+  TSC_SYNC: 9
+PB11:
+  CM4_EVENTOUT: 15
+  COMP2_OUT: 12
+  I2C3_SDA: 4
+  LCD_SEG11: 11
+  LPUART1_TX: 8
+  QUADSPI_BK1_NCS: 10
+  TIM2_CH4: 1
+PB12:
+  CM4_EVENTOUT: 15
+  I2C3_SMBA: 4
+  LCD_SEG12: 11
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+  SAI1_FS_A: 13
+  SPI2_NSS: 5
+  TIM1_BKIN: 3
+  TSC_G1_IO1: 9
+PB13:
+  CM4_EVENTOUT: 15
+  I2C3_SCL: 4
+  LCD_SEG13: 11
+  LPUART1_CTS: 8
+  SAI1_SCK_A: 13
+  SPI2_SCK: 5
+  TIM1_CH1N: 1
+  TSC_G1_IO2: 9
+PB14:
+  CM4_EVENTOUT: 15
+  I2C3_SDA: 4
+  LCD_SEG14: 11
+  SAI1_MCLK_A: 13
+  SPI2_MISO: 5
+  TIM1_CH2N: 1
+  TSC_G1_IO3: 9
+PB15:
+  CM4_EVENTOUT: 15
+  LCD_SEG15: 11
+  RTC_REFIN: 0
+  SAI1_SD_A: 13
+  SPI2_MOSI: 5
+  TIM1_CH3N: 1
+  TSC_G1_IO4: 9
+PB2:
+  CM4_EVENTOUT: 15
+  I2C3_SMBA: 4
+  LCD_VLCD: 11
+  LPTIM1_OUT: 1
+  SAI1_EXTCLK: 13
+  SPI1_NSS: 5
+PB3:
+  CM4_EVENTOUT: 15
+  LCD_SEG7: 11
+  SAI1_SCK_B: 13
+  SPI1_SCK: 5
+  SYS_JTDO-SWO: 0
+  TIM2_CH2: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+PB4:
+  CM4_EVENTOUT: 15
+  I2C3_SDA: 4
+  LCD_SEG8: 11
+  SAI1_MCLK_B: 13
+  SPI1_MISO: 5
+  SYS_JTRST: 0
+  TIM17_BKIN: 14
+  TSC_G2_IO1: 9
+  USART1_CTS: 7
+  USART1_NSS: 7
+PB5:
+  CM4_EVENTOUT: 15
+  COMP2_OUT: 12
+  I2C1_SMBA: 4
+  LCD_SEG9: 11
+  LPTIM1_IN1: 1
+  LPUART1_TX: 8
+  SAI1_SD_B: 13
+  SPI1_MOSI: 5
+  TIM16_BKIN: 14
+  TSC_G2_IO2: 9
+  USART1_CK: 7
+PB6:
+  CM4_EVENTOUT: 15
+  I2C1_SCL: 4
+  LCD_SEG6: 11
+  LPTIM1_ETR: 1
+  RCC_MCO: 0
+  SAI1_FS_B: 13
+  TIM16_CH1N: 14
+  TSC_G2_IO3: 9
+  USART1_TX: 7
+PB7:
+  CM4_EVENTOUT: 15
+  I2C1_SDA: 4
+  LCD_SEG21: 11
+  LPTIM1_IN2: 1
+  TIM17_CH1N: 14
+  TIM1_BKIN: 3
+  TSC_G2_IO4: 9
+  USART1_RX: 7
+PB8:
+  CM4_EVENTOUT: 15
+  I2C1_SCL: 4
+  LCD_SEG16: 11
+  QUADSPI_BK1_IO1: 10
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 13
+  TIM16_CH1: 14
+  TIM1_CH2N: 1
+PB9:
+  CM4_EVENTOUT: 15
+  I2C1_SDA: 4
+  IR_OUT: 8
+  LCD_COM3: 11
+  QUADSPI_BK1_IO0: 10
+  SAI1_D2: 3
+  SAI1_FS_A: 13
+  SPI2_NSS: 5
+  TIM17_CH1: 14
+  TIM1_CH3N: 1
+  TSC_G7_IO4: 9
+PC0:
+  CM4_EVENTOUT: 15
+  I2C3_SCL: 4
+  LCD_SEG18: 11
+  LPTIM1_IN1: 1
+  LPTIM2_IN1: 14
+  LPUART1_RX: 8
+PC1:
+  CM4_EVENTOUT: 15
+  I2C3_SDA: 4
+  LCD_SEG19: 11
+  LPTIM1_OUT: 1
+  LPUART1_TX: 8
+  SPI2_MOSI: 3
+PC10:
+  CM4_EVENTOUT: 15
+  LCD_COM4: 11
+  LCD_SEG28: 11
+  LCD_SEG40: 11
+  SYS_TRACED1: 0
+  TSC_G3_IO2: 9
+PC11:
+  CM4_EVENTOUT: 15
+  LCD_COM5: 11
+  LCD_SEG29: 11
+  LCD_SEG41: 11
+  TSC_G3_IO3: 9
+PC12:
+  CM4_EVENTOUT: 15
+  LCD_COM6: 11
+  LCD_SEG30: 11
+  LCD_SEG42: 11
+  RCC_LSCO: 6
+  SYS_TRACED3: 0
+  TSC_G3_IO4: 9
+PC13:
+  CM4_EVENTOUT: 15
+PC14:
+  CM4_EVENTOUT: 15
+  RF_DTB0: 6
+PC15:
+  CM4_EVENTOUT: 15
+  RF_DTB1: 6
+PC2:
+  CM4_EVENTOUT: 15
+  LCD_SEG20: 11
+  LPTIM1_IN2: 1
+  SPI2_MISO: 5
+PC3:
+  CM4_EVENTOUT: 15
+  LCD_VLCD: 11
+  LPTIM1_ETR: 1
+  LPTIM2_ETR: 14
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  SPI2_MOSI: 5
+PC4:
+  CM4_EVENTOUT: 15
+  LCD_SEG22: 11
+PC5:
+  CM4_EVENTOUT: 15
+  LCD_SEG23: 11
+  SAI1_D3: 3
+PC6:
+  CM4_EVENTOUT: 15
+  LCD_SEG24: 11
+  TSC_G4_IO1: 9
+PC7:
+  CM4_EVENTOUT: 15
+  LCD_SEG25: 11
+  TSC_G4_IO2: 9
+PC8:
+  CM4_EVENTOUT: 15
+  LCD_SEG26: 11
+  TSC_G4_IO3: 9
+PC9:
+  CM4_EVENTOUT: 15
+  LCD_SEG27: 11
+  SAI1_SCK_B: 13
+  TIM1_BKIN: 3
+  TSC_G4_IO4: 9
+  USB_NOE: 10
+PD0:
+  CM4_EVENTOUT: 15
+  SPI2_NSS: 5
+PD1:
+  CM4_EVENTOUT: 15
+  SPI2_SCK: 5
+PD10:
+  CM4_EVENTOUT: 15
+  LCD_SEG30: 11
+  TRIG_INOUT: 0
+  TSC_G6_IO1: 9
+PD11:
+  CM4_EVENTOUT: 15
+  LCD_SEG31: 11
+  LPTIM2_ETR: 14
+  TSC_G6_IO2: 9
+PD12:
+  CM4_EVENTOUT: 15
+  LCD_SEG32: 11
+  LPTIM2_IN1: 14
+  TSC_G6_IO3: 9
+PD13:
+  CM4_EVENTOUT: 15
+  LCD_SEG33: 11
+  LPTIM2_OUT: 14
+  TSC_G6_IO4: 9
+PD14:
+  CM4_EVENTOUT: 15
+  LCD_SEG34: 11
+  TIM1_CH1: 1
+PD15:
+  CM4_EVENTOUT: 15
+  LCD_SEG35: 11
+  TIM1_CH2: 1
+PD2:
+  CM4_EVENTOUT: 15
+  LCD_COM7: 11
+  LCD_SEG31: 11
+  LCD_SEG43: 11
+  SYS_TRACED2: 0
+  TSC_SYNC: 9
+PD3:
+  CM4_EVENTOUT: 15
+  QUADSPI_BK1_NCS: 10
+  SPI2_MISO: 5
+  SPI2_SCK: 3
+PD4:
+  CM4_EVENTOUT: 15
+  QUADSPI_BK1_IO0: 10
+  SPI2_MOSI: 5
+  TSC_G5_IO1: 9
+PD5:
+  CM4_EVENTOUT: 15
+  QUADSPI_BK1_IO1: 10
+  SAI1_MCLK_B: 13
+  TSC_G5_IO2: 9
+PD6:
+  CM4_EVENTOUT: 15
+  QUADSPI_BK1_IO2: 10
+  SAI1_D1: 3
+  SAI1_SD_A: 13
+  TSC_G5_IO3: 9
+PD7:
+  CM4_EVENTOUT: 15
+  LCD_SEG39: 11
+  QUADSPI_BK1_IO3: 10
+  TSC_G5_IO4: 9
+PD8:
+  CM4_EVENTOUT: 15
+  LCD_SEG28: 11
+  TIM1_BKIN2: 2
+PD9:
+  CM4_EVENTOUT: 15
+  LCD_SEG29: 11
+  SYS_TRACED0: 0
+PE0:
+  CM4_EVENTOUT: 15
+  LCD_SEG36: 11
+  TIM16_CH1: 14
+  TIM1_ETR: 1
+  TSC_G7_IO3: 9
+PE1:
+  CM4_EVENTOUT: 15
+  LCD_SEG37: 11
+  TIM17_CH1: 14
+  TSC_G7_IO2: 9
+PE2:
+  CM4_EVENTOUT: 15
+  LCD_SEG38: 11
+  SAI1_CK1: 3
+  SAI1_MCLK_A: 13
+  SYS_TRACECLK: 0
+  TSC_G7_IO1: 9
+PE3:
+  CM4_EVENTOUT: 15
+PE4:
+  CM4_EVENTOUT: 15
+PH0:
+  CM4_EVENTOUT: 15
+PH1:
+  CM4_EVENTOUT: 15
+PH3:
+  CM4_EVENTOUT: 15
+  RCC_LSCO: 0
+PI8: {}

data/gpio_af/STM32WL.yaml

@@ -0,0 +1,275 @@
+PA0:
+  CM4_EVENTOUT: 15
+  COMP1_OUT: 12
+  DEBUG_PWR-REGLP1S: 13
+  I2C3_SMBA: 4
+  I2S_CKIN: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 14
+  USART2_CTS: 7
+  USART2_NSS: 7
+PA1:
+  CM4_EVENTOUT: 15
+  DEBUG_PWR-REGLP2S: 13
+  I2C1_SMBA: 4
+  LPTIM3_OUT: 3
+  LPUART1_RTS: 8
+  SPI1_SCK: 5
+  TIM2_CH2: 1
+  USART2_DE: 7
+  USART2_RTS: 7
+PA10:
+  CM4_EVENTOUT: 15
+  DEBUG_RF-HSE32RDY: 13
+  I2C1_SDA: 4
+  I2S2_SD: 5
+  RTC_REFIN: 0
+  SPI2_MOSI: 5
+  TIM17_BKIN: 14
+  TIM1_CH3: 1
+  USART1_RX: 7
+PA11:
+  CM4_EVENTOUT: 15
+  DEBUG_RF-NRESET: 13
+  I2C2_SDA: 4
+  LPTIM3_ETR: 3
+  SPI1_MISO: 5
+  TIM1_BKIN2: 12
+  TIM1_CH4: 1
+  USART1_CTS: 7
+  USART1_NSS: 7
+PA12:
+  CM4_EVENTOUT: 15
+  I2C2_SCL: 4
+  LPTIM3_IN1: 3
+  RF_BUSY: 6
+  SPI1_MOSI: 5
+  TIM1_ETR: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+PA13:
+  CM4_EVENTOUT: 15
+  DEBUG_JTMS-SWDIO: 0
+  I2C2_SMBA: 4
+  IR_OUT: 8
+PA14:
+  CM4_EVENTOUT: 15
+  DEBUG_JTCK-SWCLK: 0
+  I2C1_SMBA: 4
+  LPTIM1_OUT: 1
+PA15:
+  CM4_EVENTOUT: 15
+  DEBUG_JTDI: 0
+  I2C2_SDA: 4
+  SPI1_NSS: 5
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+PA2:
+  CM4_EVENTOUT: 15
+  COMP2_OUT: 12
+  DEBUG_PWR-LDORDY: 13
+  LPUART1_TX: 8
+  RCC_LSCO: 0
+  TIM2_CH3: 1
+  USART2_TX: 7
+PA3:
+  CM4_EVENTOUT: 15
+  I2S2_MCK: 5
+  LPUART1_RX: 8
+  TIM2_CH4: 1
+  USART2_RX: 7
+PA4:
+  CM4_EVENTOUT: 15
+  DEBUG_SUBGHZSPI-NSSOUT: 13
+  LPTIM1_OUT: 1
+  LPTIM2_OUT: 14
+  SPI1_NSS: 5
+  USART2_CK: 7
+PA5:
+  CM4_EVENTOUT: 15
+  DEBUG_SUBGHZSPI-SCKOUT: 13
+  LPTIM2_ETR: 14
+  SPI1_SCK: 5
+  SPI2_MISO: 3
+  TIM2_CH1: 1
+  TIM2_ETR: 2
+PA6:
+  CM4_EVENTOUT: 15
+  DEBUG_SUBGHZSPI-MISOOUT: 13
+  I2C2_SMBA: 4
+  LPUART1_CTS: 8
+  SPI1_MISO: 5
+  TIM16_CH1: 14
+  TIM1_BKIN: 12
+PA7:
+  CM4_EVENTOUT: 15
+  COMP2_OUT: 12
+  DEBUG_SUBGHZSPI-MOSIOUT: 13
+  I2C3_SCL: 4
+  SPI1_MOSI: 5
+  TIM17_CH1: 14
+  TIM1_CH1N: 1
+PA8:
+  CM4_EVENTOUT: 15
+  I2S2_CK: 5
+  LPTIM2_OUT: 14
+  RCC_MCO: 0
+  SPI2_SCK: 5
+  TIM1_CH1: 1
+  USART1_CK: 7
+PA9:
+  CM4_EVENTOUT: 15
+  I2C1_SCL: 4
+  I2S2_CK: 5
+  I2S2_WS: 3
+  SPI2_NSS: 3
+  SPI2_SCK: 5
+  TIM1_CH2: 1
+  USART1_TX: 7
+PB0:
+  CM4_EVENTOUT: 15
+  COMP1_OUT: 12
+PB1:
+  CM4_EVENTOUT: 15
+  LPTIM2_IN1: 14
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+PB10:
+  CM4_EVENTOUT: 15
+  COMP1_OUT: 12
+  I2C3_SCL: 4
+  I2S2_CK: 5
+  LPUART1_RX: 8
+  SPI2_SCK: 5
+  TIM2_CH3: 1
+PB11:
+  CM4_EVENTOUT: 15
+  COMP2_OUT: 12
+  I2C3_SDA: 4
+  LPUART1_TX: 8
+  TIM2_CH4: 1
+PB12:
+  CM4_EVENTOUT: 15
+  I2C3_SMBA: 4
+  I2S2_WS: 5
+  LPUART1_DE: 8
+  LPUART1_RTS: 8
+  SPI2_NSS: 5
+  TIM1_BKIN: 3
+PB13:
+  CM4_EVENTOUT: 15
+  I2C3_SCL: 4
+  I2S2_CK: 5
+  LPUART1_CTS: 8
+  SPI2_SCK: 5
+  TIM1_CH1N: 1
+PB14:
+  CM4_EVENTOUT: 15
+  I2C3_SDA: 4
+  I2S2_MCK: 3
+  SPI2_MISO: 5
+  TIM1_CH2N: 1
+PB15:
+  CM4_EVENTOUT: 15
+  I2C2_SCL: 4
+  I2S2_SD: 5
+  SPI2_MOSI: 5
+  TIM1_CH3N: 1
+PB2:
+  CM4_EVENTOUT: 15
+  DEBUG_RF-SMPSRDY: 13
+  I2C3_SMBA: 4
+  LPTIM1_OUT: 1
+  SPI1_NSS: 5
+PB3:
+  CM4_EVENTOUT: 15
+  DEBUG_JTDO-SWO: 0
+  DEBUG_RF-DTB1: 13
+  RF_IRQ0: 6
+  SPI1_SCK: 5
+  TIM2_CH2: 1
+  USART1_DE: 7
+  USART1_RTS: 7
+PB4:
+  CM4_EVENTOUT: 15
+  DEBUG_RF-LDORDY: 13
+  I2C3_SDA: 4
+  SPI1_MISO: 5
+  SYS_JTRST: 0
+  TIM17_BKIN: 14
+  USART1_CTS: 7
+  USART1_NSS: 7
+PB5:
+  CM4_EVENTOUT: 15
+  COMP2_OUT: 12
+  I2C1_SMBA: 4
+  LPTIM1_IN1: 1
+  RF_IRQ1: 6
+  SPI1_MOSI: 5
+  TIM16_BKIN: 14
+  USART1_CK: 7
+PB6:
+  CM4_EVENTOUT: 15
+  I2C1_SCL: 4
+  LPTIM1_ETR: 1
+  TIM16_CH1N: 14
+  USART1_TX: 7
+PB7:
+  CM4_EVENTOUT: 15
+  I2C1_SDA: 4
+  LPTIM1_IN2: 1
+  TIM17_CH1N: 14
+  TIM1_BKIN: 3
+  USART1_RX: 7
+PB8:
+  CM4_EVENTOUT: 15
+  I2C1_SCL: 4
+  RF_IRQ2: 6
+  TIM16_CH1: 14
+  TIM1_CH2N: 1
+PB9:
+  CM4_EVENTOUT: 15
+  I2C1_SDA: 4
+  I2S2_WS: 5
+  IR_OUT: 8
+  SPI2_NSS: 5
+  TIM17_CH1: 14
+  TIM1_CH3N: 1
+PC0:
+  CM4_EVENTOUT: 15
+  I2C3_SCL: 4
+  LPTIM1_IN1: 1
+  LPTIM2_IN1: 14
+  LPUART1_RX: 8
+PC1:
+  CM4_EVENTOUT: 15
+  I2C3_SDA: 4
+  I2S2_SD: 3
+  LPTIM1_OUT: 1
+  LPUART1_TX: 8
+  SPI2_MOSI: 3
+PC13:
+  CM4_EVENTOUT: 15
+PC14:
+  CM4_EVENTOUT: 15
+PC15:
+  CM4_EVENTOUT: 15
+PC2:
+  CM4_EVENTOUT: 15
+  LPTIM1_IN2: 1
+  SPI2_MISO: 5
+PC3:
+  CM4_EVENTOUT: 15
+  I2S2_SD: 5
+  LPTIM1_ETR: 1
+  LPTIM2_ETR: 14
+  SPI2_MOSI: 5
+PC4:
+  CM4_EVENTOUT: 15
+PC5:
+  CM4_EVENTOUT: 15
+PC6:
+  CM4_EVENTOUT: 15
+  I2S2_MCK: 5
+PH3:
+  CM4_EVENTOUT: 15

data/registers/dma_v1.yaml

@@ -0,0 +1,235 @@
+---
+block/DMA:
+  description: DMA controller
+  items:
+    - name: ISR
+      description: DMA interrupt status register (DMA_ISR)
+      byte_offset: 0
+      reset_value: 0
+      access: Read
+      fieldset: ISR
+    - name: IFCR
+      description: DMA interrupt flag clear register (DMA_IFCR)
+      byte_offset: 4
+      reset_value: 0
+      access: Write
+      fieldset: IFCR
+    - name: CH
+      description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
+      array:
+        len: 7
+        stride: 20
+      byte_offset: 8
+      block: CH
+block/CH:
+  description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
+  items:
+    - name: CR
+      description: DMA channel configuration register (DMA_CCR)
+      byte_offset: 0
+      reset_value: 0
+      fieldset: CR
+    - name: NDTR
+      description: DMA channel 1 number of data register
+      byte_offset: 4
+      reset_value: 0
+      fieldset: NDTR
+    - name: PAR
+      description: DMA channel 1 peripheral address register
+      byte_offset: 8
+      reset_value: 0
+    - name: MAR
+      description: DMA channel 1 memory address register
+      byte_offset: 12
+      reset_value: 0
+fieldset/CR:
+  description: DMA channel configuration register (DMA_CCR)
+  fields:
+    - name: EN
+      description: Channel enable
+      bit_offset: 0
+      bit_size: 1
+    - name: TCIE
+      description: Transfer complete interrupt enable
+      bit_offset: 1
+      bit_size: 1
+    - name: HTIE
+      description: Half Transfer interrupt enable
+      bit_offset: 2
+      bit_size: 1
+    - name: TEIE
+      description: Transfer error interrupt enable
+      bit_offset: 3
+      bit_size: 1
+    - name: DIR
+      description: Data transfer direction
+      bit_offset: 4
+      bit_size: 1
+      enum: DIR
+    - name: CIRC
+      description: Circular mode
+      bit_offset: 5
+      bit_size: 1
+      enum: CIRC
+    - name: PINC
+      description: Peripheral increment mode
+      bit_offset: 6
+      bit_size: 1
+      enum: INC
+    - name: MINC
+      description: Memory increment mode
+      bit_offset: 7
+      bit_size: 1
+      enum: INC
+    - name: PSIZE
+      description: Peripheral size
+      bit_offset: 8
+      bit_size: 2
+      enum: SIZE
+    - name: MSIZE
+      description: Memory size
+      bit_offset: 10
+      bit_size: 2
+      enum: SIZE
+    - name: PL
+      description: Channel Priority level
+      bit_offset: 12
+      bit_size: 2
+      enum: PL
+    - name: MEM2MEM
+      description: Memory to memory mode
+      bit_offset: 14
+      bit_size: 1
+      enum: MEMMEM
+fieldset/IFCR:
+  description: DMA interrupt flag clear register (DMA_IFCR)
+  fields:
+    - name: CGIF
+      description: Channel 1 Global interrupt clear
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 7
+        stride: 4
+    - name: CTCIF
+      description: Channel 1 Transfer Complete clear
+      bit_offset: 1
+      bit_size: 1
+      array:
+        len: 7
+        stride: 4
+    - name: CHTIF
+      description: Channel 1 Half Transfer clear
+      bit_offset: 2
+      bit_size: 1
+      array:
+        len: 7
+        stride: 4
+    - name: CTEIF
+      description: Channel 1 Transfer Error clear
+      bit_offset: 3
+      bit_size: 1
+      array:
+        len: 7
+        stride: 4
+fieldset/ISR:
+  description: DMA interrupt status register (DMA_ISR)
+  fields:
+    - name: GIF
+      description: Channel 1 Global interrupt flag
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 7
+        stride: 4
+    - name: TCIF
+      description: Channel 1 Transfer Complete flag
+      bit_offset: 1
+      bit_size: 1
+      array:
+        len: 7
+        stride: 4
+    - name: HTIF
+      description: Channel 1 Half Transfer Complete flag
+      bit_offset: 2
+      bit_size: 1
+      array:
+        len: 7
+        stride: 4
+    - name: TEIF
+      description: Channel 1 Transfer Error flag
+      bit_offset: 3
+      bit_size: 1
+      array:
+        len: 7
+        stride: 4
+fieldset/NDTR:
+  description: DMA channel 1 number of data register
+  fields:
+    - name: NDT
+      description: Number of data to transfer
+      bit_offset: 0
+      bit_size: 16
+enum/CIRC:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Circular buffer disabled
+      value: 0
+    - name: Enabled
+      description: Circular buffer enabled
+      value: 1
+enum/DIR:
+  bit_size: 1
+  variants:
+    - name: FromPeripheral
+      description: Read from peripheral
+      value: 0
+    - name: FromMemory
+      description: Read from memory
+      value: 1
+enum/MEMMEM:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Memory to memory mode disabled
+      value: 0
+    - name: Enabled
+      description: Memory to memory mode enabled
+      value: 1
+enum/INC:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Increment mode disabled
+      value: 0
+    - name: Enabled
+      description: Increment mode enabled
+      value: 1
+enum/PL:
+  bit_size: 2
+  variants:
+    - name: Low
+      description: Low priority
+      value: 0
+    - name: Medium
+      description: Medium priority
+      value: 1
+    - name: High
+      description: High priority
+      value: 2
+    - name: VeryHigh
+      description: Very high priority
+      value: 3
+enum/SIZE:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: 8-bit size
+      value: 0
+    - name: Bits16
+      description: 16-bit size
+      value: 1
+    - name: Bits32
+      description: 32-bit size
+      value: 2

data/registers/dma_v2.yaml

@@ -0,0 +1,439 @@
+---
+block/DMA:
+  description: DMA controller
+  items:
+    - name: ISR
+      description: low interrupt status register
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 0
+      reset_value: 0
+      access: Read
+      fieldset: ISR
+    - name: IFCR
+      description: low interrupt flag clear register
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 8
+      reset_value: 0
+      access: Write
+      fieldset: IFCR
+    - name: ST
+      description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"
+      array:
+        len: 8
+        stride: 24
+      byte_offset: 16
+      block: ST
+block/ST:
+  description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"
+  items:
+    - name: CR
+      description: stream x configuration register
+      byte_offset: 0
+      reset_value: 0
+      fieldset: CR
+    - name: NDTR
+      description: stream x number of data register
+      byte_offset: 4
+      reset_value: 0
+      fieldset: NDTR
+    - name: PAR
+      description: stream x peripheral address register
+      byte_offset: 8
+      reset_value: 0
+    - name: M0AR
+      description: stream x memory 0 address register
+      byte_offset: 12
+      reset_value: 0
+    - name: M1AR
+      description: stream x memory 1 address register
+      byte_offset: 16
+      reset_value: 0
+    - name: FCR
+      description: stream x FIFO control register
+      byte_offset: 20
+      reset_value: 33
+      fieldset: FCR
+fieldset/CR:
+  description: stream x configuration register
+  fields:
+    - name: EN
+      description: Stream enable / flag stream ready when read low
+      bit_offset: 0
+      bit_size: 1
+    - name: DMEIE
+      description: Direct mode error interrupt enable
+      bit_offset: 1
+      bit_size: 1
+    - name: TEIE
+      description: Transfer error interrupt enable
+      bit_offset: 2
+      bit_size: 1
+    - name: HTIE
+      description: Half transfer interrupt enable
+      bit_offset: 3
+      bit_size: 1
+    - name: TCIE
+      description: Transfer complete interrupt enable
+      bit_offset: 4
+      bit_size: 1
+    - name: PFCTRL
+      description: Peripheral flow controller
+      bit_offset: 5
+      bit_size: 1
+      enum: PFCTRL
+    - name: DIR
+      description: Data transfer direction
+      bit_offset: 6
+      bit_size: 2
+      enum: DIR
+    - name: CIRC
+      description: Circular mode
+      bit_offset: 8
+      bit_size: 1
+      enum: CIRC
+    - name: PINC
+      description: Peripheral increment mode
+      bit_offset: 9
+      bit_size: 1
+      enum: INC
+    - name: MINC
+      description: Memory increment mode
+      bit_offset: 10
+      bit_size: 1
+      enum: INC
+    - name: PSIZE
+      description: Peripheral data size
+      bit_offset: 11
+      bit_size: 2
+      enum: SIZE
+    - name: MSIZE
+      description: Memory data size
+      bit_offset: 13
+      bit_size: 2
+      enum: SIZE
+    - name: PINCOS
+      description: Peripheral increment offset size
+      bit_offset: 15
+      bit_size: 1
+      enum: PINCOS
+    - name: PL
+      description: Priority level
+      bit_offset: 16
+      bit_size: 2
+      enum: PL
+    - name: DBM
+      description: Double buffer mode
+      bit_offset: 18
+      bit_size: 1
+      enum: DBM
+    - name: CT
+      description: Current target (only in double buffer mode)
+      bit_offset: 19
+      bit_size: 1
+      enum: CT
+    - name: PBURST
+      description: Peripheral burst transfer configuration
+      bit_offset: 21
+      bit_size: 2
+      enum: BURST
+    - name: MBURST
+      description: Memory burst transfer configuration
+      bit_offset: 23
+      bit_size: 2
+      enum: BURST
+    - name: CHSEL
+      description: Channel selection
+      bit_offset: 25
+      bit_size: 4
+fieldset/FCR:
+  description: stream x FIFO control register
+  fields:
+    - name: FTH
+      description: FIFO threshold selection
+      bit_offset: 0
+      bit_size: 2
+      enum: FTH
+    - name: DMDIS
+      description: Direct mode disable
+      bit_offset: 2
+      bit_size: 1
+      enum: DMDIS
+    - name: FS
+      description: FIFO status
+      bit_offset: 3
+      bit_size: 3
+      enum: FS
+    - name: FEIE
+      description: FIFO error interrupt enable
+      bit_offset: 7
+      bit_size: 1
+fieldset/IFCR:
+  description: low interrupt flag clear register
+  fields:
+    - name: CFEIF
+      description: Stream x clear FIFO error interrupt flag (x = 3..0)
+      bit_offset: 0
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 6
+          - 16
+          - 22
+    - name: CDMEIF
+      description: Stream x clear direct mode error interrupt flag (x = 3..0)
+      bit_offset: 2
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 6
+          - 16
+          - 22
+    - name: CTEIF
+      description: Stream x clear transfer error interrupt flag (x = 3..0)
+      bit_offset: 3
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 6
+          - 16
+          - 22
+    - name: CHTIF
+      description: Stream x clear half transfer interrupt flag (x = 3..0)
+      bit_offset: 4
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 6
+          - 16
+          - 22
+    - name: CTCIF
+      description: Stream x clear transfer complete interrupt flag (x = 3..0)
+      bit_offset: 5
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 6
+          - 16
+          - 22
+fieldset/ISR:
+  description: low interrupt status register
+  fields:
+    - name: FEIF
+      description: Stream x FIFO error interrupt flag (x=3..0)
+      bit_offset: 0
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 6
+          - 16
+          - 22
+    - name: DMEIF
+      description: Stream x direct mode error interrupt flag (x=3..0)
+      bit_offset: 2
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 6
+          - 16
+          - 22
+    - name: TEIF
+      description: Stream x transfer error interrupt flag (x=3..0)
+      bit_offset: 3
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 6
+          - 16
+          - 22
+    - name: HTIF
+      description: Stream x half transfer interrupt flag (x=3..0)
+      bit_offset: 4
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 6
+          - 16
+          - 22
+    - name: TCIF
+      description: Stream x transfer complete interrupt flag (x = 3..0)
+      bit_offset: 5
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 6
+          - 16
+          - 22
+fieldset/NDTR:
+  description: stream x number of data register
+  fields:
+    - name: NDT
+      description: Number of data items to transfer
+      bit_offset: 0
+      bit_size: 16
+enum/CIRC:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Circular mode disabled
+      value: 0
+    - name: Enabled
+      description: Circular mode enabled
+      value: 1
+enum/CT:
+  bit_size: 1
+  variants:
+    - name: Memory0
+      description: The current target memory is Memory 0
+      value: 0
+    - name: Memory1
+      description: The current target memory is Memory 1
+      value: 1
+enum/DBM:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: No buffer switching at the end of transfer
+      value: 0
+    - name: Enabled
+      description: Memory target switched at the end of the DMA transfer
+      value: 1
+enum/DIR:
+  bit_size: 2
+  variants:
+    - name: PeripheralToMemory
+      description: Peripheral-to-memory
+      value: 0
+    - name: MemoryToPeripheral
+      description: Memory-to-peripheral
+      value: 1
+    - name: MemoryToMemory
+      description: Memory-to-memory
+      value: 2
+enum/DMDIS:
+  bit_size: 1
+  variants:
+    - name: Enabled
+      description: Direct mode is enabled
+      value: 0
+    - name: Disabled
+      description: Direct mode is disabled
+      value: 1
+enum/FS:
+  bit_size: 3
+  variants:
+    - name: Quarter1
+      description: 0 < fifo_level < 1/4
+      value: 0
+    - name: Quarter2
+      description: 1/4 <= fifo_level < 1/2
+      value: 1
+    - name: Quarter3
+      description: 1/2 <= fifo_level < 3/4
+      value: 2
+    - name: Quarter4
+      description: 3/4 <= fifo_level < full
+      value: 3
+    - name: Empty
+      description: FIFO is empty
+      value: 4
+    - name: Full
+      description: FIFO is full
+      value: 5
+enum/FTH:
+  bit_size: 2
+  variants:
+    - name: Quarter
+      description: 1/4 full FIFO
+      value: 0
+    - name: Half
+      description: 1/2 full FIFO
+      value: 1
+    - name: ThreeQuarters
+      description: 3/4 full FIFO
+      value: 2
+    - name: Full
+      description: Full FIFO
+      value: 3
+enum/BURST:
+  bit_size: 2
+  variants:
+    - name: Single
+      description: Single transfer
+      value: 0
+    - name: INCR4
+      description: Incremental burst of 4 beats
+      value: 1
+    - name: INCR8
+      description: Incremental burst of 8 beats
+      value: 2
+    - name: INCR16
+      description: Incremental burst of 16 beats
+      value: 3
+enum/INC:
+  bit_size: 1
+  variants:
+    - name: Fixed
+      description: Address pointer is fixed
+      value: 0
+    - name: Incremented
+      description: Address pointer is incremented after each data transfer
+      value: 1
+enum/SIZE:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: Byte (8-bit)
+      value: 0
+    - name: Bits16
+      description: Half-word (16-bit)
+      value: 1
+    - name: Bits32
+      description: Word (32-bit)
+      value: 2
+enum/PFCTRL:
+  bit_size: 1
+  variants:
+    - name: DMA
+      description: The DMA is the flow controller
+      value: 0
+    - name: Peripheral
+      description: The peripheral is the flow controller
+      value: 1
+enum/PINCOS:
+  bit_size: 1
+  variants:
+    - name: PSIZE
+      description: The offset size for the peripheral address calculation is linked to the PSIZE
+      value: 0
+    - name: Fixed4
+      description: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)
+      value: 1
+enum/PL:
+  bit_size: 2
+  variants:
+    - name: Low
+      description: Low
+      value: 0
+    - name: Medium
+      description: Medium
+      value: 1
+    - name: High
+      description: High
+      value: 2
+    - name: VeryHigh
+      description: Very high
+      value: 3

data/registers/exti.yaml

@@ -0,0 +1,140 @@
+---
+block/EXTI:
+  description: External interrupt/event controller
+  items:
+    - name: IMR
+      description: Interrupt mask register (EXTI_IMR)
+      byte_offset: 0
+      reset_value: 0
+      fieldset: IMR
+    - name: EMR
+      description: Event mask register (EXTI_EMR)
+      byte_offset: 4
+      reset_value: 0
+      fieldset: EMR
+    - name: RTSR
+      description: Rising Trigger selection register (EXTI_RTSR)
+      byte_offset: 8
+      reset_value: 0
+      fieldset: RTSR
+    - name: FTSR
+      description: Falling Trigger selection register (EXTI_FTSR)
+      byte_offset: 12
+      reset_value: 0
+      fieldset: FTSR
+    - name: SWIER
+      description: Software interrupt event register (EXTI_SWIER)
+      byte_offset: 16
+      reset_value: 0
+      fieldset: SWIER
+    - name: PR
+      description: Pending register (EXTI_PR)
+      byte_offset: 20
+      reset_value: 0
+      fieldset: PR
+fieldset/EMR:
+  description: Event mask register (EXTI_EMR)
+  fields:
+    - name: MR
+      description: Event Mask on line 0
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 23
+        stride: 1
+      enum: MR
+fieldset/FTSR:
+  description: Falling Trigger selection register (EXTI_FTSR)
+  fields:
+    - name: TR
+      description: Falling trigger event configuration of line 0
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 23
+        stride: 1
+      enum: TR
+fieldset/IMR:
+  description: Interrupt mask register (EXTI_IMR)
+  fields:
+    - name: MR
+      description: Interrupt Mask on line 0
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 23
+        stride: 1
+      enum: MR
+fieldset/PR:
+  description: Pending register (EXTI_PR)
+  fields:
+    - name: PR
+      description: Pending bit 0
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 23
+        stride: 1
+      enum_read: PRR
+      enum_write: PRW
+fieldset/RTSR:
+  description: Rising Trigger selection register (EXTI_RTSR)
+  fields:
+    - name: TR
+      description: Rising trigger event configuration of line 0
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 23
+        stride: 1
+      enum: TR
+fieldset/SWIER:
+  description: Software interrupt event register (EXTI_SWIER)
+  fields:
+    - name: SWIER
+      description: Software Interrupt on line 0
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 23
+        stride: 1
+      enum_write: SWIERW
+enum/MR:
+  bit_size: 1
+  variants:
+    - name: Masked
+      description: Interrupt request line is masked
+      value: 0
+    - name: Unmasked
+      description: Interrupt request line is unmasked
+      value: 1
+enum/TR:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Falling edge trigger is disabled
+      value: 0
+    - name: Enabled
+      description: Falling edge trigger is enabled
+      value: 1
+enum/PRR:
+  bit_size: 1
+  variants:
+    - name: NotPending
+      description: No trigger request occurred
+      value: 0
+    - name: Pending
+      description: Selected trigger request occurred
+      value: 1
+enum/PRW:
+  bit_size: 1
+  variants:
+    - name: Clear
+      description: Clears pending bit
+      value: 1
+enum/SWIERW:
+  bit_size: 1
+  variants:
+    - name: Pend
+      description: Generates an interrupt request
+      value: 1

data/registers/gpio_v1.yaml

@@ -0,0 +1,211 @@
+---
+block/GPIO:
+  description: General purpose I/O
+  items:
+    - name: CR
+      description: Port configuration register low (GPIOn_CRL)
+      byte_offset: 0
+      reset_value: 1145324612
+      array:
+        len: 2
+        stride: 4
+      fieldset: CR
+    - name: IDR
+      description: Port input data register (GPIOn_IDR)
+      byte_offset: 8
+      reset_value: 0
+      access: Read
+      fieldset: IDR
+    - name: ODR
+      description: Port output data register (GPIOn_ODR)
+      byte_offset: 12
+      reset_value: 0
+      fieldset: ODR
+    - name: BSRR
+      description: Port bit set/reset register (GPIOn_BSRR)
+      byte_offset: 16
+      reset_value: 0
+      access: Write
+      fieldset: BSRR
+    - name: BRR
+      description: Port bit reset register (GPIOn_BRR)
+      byte_offset: 20
+      reset_value: 0
+      access: Write
+      fieldset: BRR
+    - name: LCKR
+      description: Port configuration lock register
+      byte_offset: 24
+      reset_value: 0
+      fieldset: LCKR
+fieldset/BRR:
+  description: Port bit reset register (GPIOn_BRR)
+  fields:
+    - name: BR
+      description: Reset bit
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 16
+        stride: 1
+      enum_write: BRW
+fieldset/BSRR:
+  description: Port bit set/reset register (GPIOn_BSRR)
+  fields:
+    - name: BS
+      description: Set bit
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 16
+        stride: 1
+      enum_write: BSW
+    - name: BR
+      description: Reset bit
+      bit_offset: 16
+      bit_size: 1
+      array:
+        len: 16
+        stride: 1
+      enum_write: BRW
+fieldset/CR:
+  description: Port configuration register (GPIOn_CRx)
+  fields:
+    - name: CNF
+      description: Port n configuration bits
+      bit_offset: 2
+      bit_size: 2
+      array:
+        len: 8
+        stride: 4
+      enum: CNF
+    - name: MODE
+      description: Port n mode bits
+      bit_offset: 0
+      bit_size: 2
+      array:
+        len: 8
+        stride: 4
+      enum: MODE
+fieldset/IDR:
+  description: Port input data register (GPIOn_IDR)
+  fields:
+    - name: IDR
+      description: Port input data
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 16
+        stride: 1
+      enum: IDR
+fieldset/LCKR:
+  description: Port configuration lock register
+  fields:
+    - name: LCKK
+      description: Lock key
+      bit_offset: 16
+      bit_size: 1
+      enum: LCKK
+    - name: LCK
+      description: Port A Lock bit
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 16
+        stride: 1
+      enum: LCK
+fieldset/ODR:
+  description: Port output data register (GPIOn_ODR)
+  fields:
+    - name: ODR
+      description: Port output data
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 16
+        stride: 1
+      enum: ODR
+enum/BRW:
+  bit_size: 1
+  variants:
+    - name: NoAction
+      description: No action on the corresponding ODx bit
+      value: 0
+    - name: Reset
+      description: Reset the ODx bit
+      value: 1
+enum/BSW:
+  bit_size: 1
+  variants:
+    - name: NoAction
+      description: No action on the corresponding ODx bit
+      value: 0
+    - name: Set
+      description: Sets the corresponding ODRx bit
+      value: 1
+enum/CNF:
+  bit_size: 2
+  variants:
+    - name: PushPull
+      description: Analog mode / Push-Pull mode
+      value: 0
+    - name: OpenDrain
+      description: Floating input (reset state) / Open Drain-Mode
+      value: 1
+    - name: AltPushPull
+      description: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
+      value: 2
+    - name: AltOpenDrain
+      description: Alternate Function Open-Drain Mode
+      value: 3
+enum/IDR:
+  bit_size: 1
+  variants:
+    - name: High
+      description: Input is logic high
+      value: 1
+    - name: Low
+      description: Input is logic low
+      value: 0
+enum/LCK:
+  bit_size: 1
+  variants:
+    - name: Unlocked
+      description: Port configuration not locked
+      value: 0
+    - name: Locked
+      description: Port configuration locked
+      value: 1
+enum/LCKK:
+  bit_size: 1
+  variants:
+    - name: NotActive
+      description: Port configuration lock key not active
+      value: 0
+    - name: Active
+      description: Port configuration lock key active
+      value: 1
+enum/MODE:
+  bit_size: 2
+  variants:
+    - name: Input
+      description: Input mode (reset state)
+      value: 0
+    - name: Output
+      description: Output mode 10 MHz
+      value: 1
+    - name: Output2
+      description: Output mode 2 MHz
+      value: 2
+    - name: Output50
+      description: Output mode 50 MHz
+      value: 3
+enum/ODR:
+  bit_size: 1
+  variants:
+    - name: High
+      description: Set output to logic high
+      value: 1
+    - name: Low
+      description: Set output to logic low
+      value: 0

data/registers/gpio_v2.yaml

@@ -0,0 +1,316 @@
+---
+block/GPIO:
+  description: General-purpose I/Os
+  items:
+    - name: MODER
+      description: GPIO port mode register
+      byte_offset: 0
+      reset_value: 2818572288
+      fieldset: MODER
+    - name: OTYPER
+      description: GPIO port output type register
+      byte_offset: 4
+      reset_value: 0
+      fieldset: OTYPER
+    - name: OSPEEDR
+      description: GPIO port output speed register
+      byte_offset: 8
+      reset_value: 0
+      fieldset: OSPEEDR
+    - name: PUPDR
+      description: GPIO port pull-up/pull-down register
+      byte_offset: 12
+      reset_value: 1677721600
+      fieldset: PUPDR
+    - name: IDR
+      description: GPIO port input data register
+      byte_offset: 16
+      reset_value: 0
+      access: Read
+      fieldset: IDR
+    - name: ODR
+      description: GPIO port output data register
+      byte_offset: 20
+      reset_value: 0
+      fieldset: ODR
+    - name: BSRR
+      description: GPIO port bit set/reset register
+      byte_offset: 24
+      reset_value: 0
+      access: Write
+      fieldset: BSRR
+    - name: LCKR
+      description: GPIO port configuration lock register
+      byte_offset: 28
+      reset_value: 0
+      fieldset: LCKR
+    - name: AFR
+      description: GPIO alternate function register (low, high)
+      byte_offset: 32
+      reset_value: 0
+      array:
+        len: 2
+        stride: 4
+      fieldset: AFR
+fieldset/AFR:
+  description: GPIO alternate function register
+  fields:
+    - name: AFR
+      description: Alternate function selection for port x bit y (y = 0..15)
+      bit_offset: 0
+      bit_size: 4
+      array:
+        len: 8
+        stride: 4
+      enum: AFR
+fieldset/BSRR:
+  description: GPIO port bit set/reset register
+  fields:
+    - name: BR
+      description: Port x set bit y (y= 0..15)
+      bit_offset: 16
+      bit_size: 1
+      array:
+        len: 16
+        stride: 1
+      enum_write: BRW
+    - name: BS
+      description: Port x set bit y (y= 0..15)
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 16
+        stride: 1
+      enum_write: BSW
+fieldset/IDR:
+  description: GPIO port input data register
+  fields:
+    - name: IDR
+      description: Port input data (y = 0..15)
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 16
+        stride: 1
+      enum: IDR
+fieldset/LCKR:
+  description: GPIO port configuration lock register
+  fields:
+    - name: LCKK
+      description: Port x lock bit y (y= 0..15)
+      bit_offset: 16
+      bit_size: 1
+      enum: LCKK
+    - name: LCK
+      description: Port x lock bit y (y= 0..15)
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 16
+        stride: 1
+      enum: LCK
+fieldset/MODER:
+  description: GPIO port mode register
+  fields:
+    - name: MODER
+      description: Port x configuration bits (y = 0..15)
+      bit_offset: 0
+      bit_size: 2
+      array:
+        len: 16
+        stride: 2
+      enum: MODER
+fieldset/ODR:
+  description: GPIO port output data register
+  fields:
+    - name: ODR
+      description: Port output data (y = 0..15)
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 16
+        stride: 1
+      enum: ODR
+fieldset/OSPEEDR:
+  description: GPIO port output speed register
+  fields:
+    - name: OSPEEDR
+      description: Port x configuration bits (y = 0..15)
+      bit_offset: 0
+      bit_size: 2
+      array:
+        len: 16
+        stride: 2
+      enum: OSPEEDR
+fieldset/OTYPER:
+  description: GPIO port output type register
+  fields:
+    - name: OT
+      description: Port x configuration bits (y = 0..15)
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 16
+        stride: 1
+      enum: OT
+fieldset/PUPDR:
+  description: GPIO port pull-up/pull-down register
+  fields:
+    - name: PUPDR
+      description: Port x configuration bits (y = 0..15)
+      bit_offset: 0
+      bit_size: 2
+      array:
+        len: 16
+        stride: 2
+      enum: PUPDR
+enum/AFR:
+  bit_size: 4
+  variants:
+    - name: AF0
+      description: AF0
+      value: 0
+    - name: AF1
+      description: AF1
+      value: 1
+    - name: AF2
+      description: AF2
+      value: 2
+    - name: AF3
+      description: AF3
+      value: 3
+    - name: AF4
+      description: AF4
+      value: 4
+    - name: AF5
+      description: AF5
+      value: 5
+    - name: AF6
+      description: AF6
+      value: 6
+    - name: AF7
+      description: AF7
+      value: 7
+    - name: AF8
+      description: AF8
+      value: 8
+    - name: AF9
+      description: AF9
+      value: 9
+    - name: AF10
+      description: AF10
+      value: 10
+    - name: AF11
+      description: AF11
+      value: 11
+    - name: AF12
+      description: AF12
+      value: 12
+    - name: AF13
+      description: AF13
+      value: 13
+    - name: AF14
+      description: AF14
+      value: 14
+    - name: AF15
+      description: AF15
+      value: 15
+enum/BRW:
+  bit_size: 1
+  variants:
+    - name: Reset
+      description: Resets the corresponding ODRx bit
+      value: 1
+enum/BSW:
+  bit_size: 1
+  variants:
+    - name: Set
+      description: Sets the corresponding ODRx bit
+      value: 1
+enum/IDR:
+  bit_size: 1
+  variants:
+    - name: High
+      description: Input is logic high
+      value: 1
+    - name: Low
+      description: Input is logic low
+      value: 0
+enum/LCK:
+  bit_size: 1
+  variants:
+    - name: Unlocked
+      description: Port configuration not locked
+      value: 0
+    - name: Locked
+      description: Port configuration locked
+      value: 1
+enum/LCKK:
+  bit_size: 1
+  variants:
+    - name: NotActive
+      description: Port configuration lock key not active
+      value: 0
+    - name: Active
+      description: Port configuration lock key active
+      value: 1
+enum/MODER:
+  bit_size: 2
+  variants:
+    - name: Input
+      description: Input mode (reset state)
+      value: 0
+    - name: Output
+      description: General purpose output mode
+      value: 1
+    - name: Alternate
+      description: Alternate function mode
+      value: 2
+    - name: Analog
+      description: Analog mode
+      value: 3
+enum/ODR:
+  bit_size: 1
+  variants:
+    - name: High
+      description: Set output to logic high
+      value: 1
+    - name: Low
+      description: Set output to logic low
+      value: 0
+enum/OSPEEDR:
+  bit_size: 2
+  variants:
+    - name: LowSpeed
+      description: Low speed
+      value: 0
+    - name: MediumSpeed
+      description: Medium speed
+      value: 1
+    - name: HighSpeed
+      description: High speed
+      value: 2
+    - name: VeryHighSpeed
+      description: Very high speed
+      value: 3
+enum/OT:
+  bit_size: 1
+  variants:
+    - name: PushPull
+      description: Output push-pull (reset state)
+      value: 0
+    - name: OpenDrain
+      description: Output open-drain
+      value: 1
+enum/PUPDR:
+  bit_size: 2
+  variants:
+    - name: Floating
+      description: "No pull-up, pull-down"
+      value: 0
+    - name: PullUp
+      description: Pull-up
+      value: 1
+    - name: PullDown
+      description: Pull-down
+      value: 2

data/registers/syscfg_f4.yaml

@@ -0,0 +1,83 @@
+---
+block/SYSCFG:
+  description: System configuration controller
+  items:
+    - name: MEMRM
+      description: memory remap register
+      byte_offset: 0
+      reset_value: 0
+      fieldset: MEMRM
+    - name: PMC
+      description: peripheral mode configuration register
+      byte_offset: 4
+      reset_value: 0
+      fieldset: PMC
+    - name: EXTICR
+      description: external interrupt configuration register
+      array:
+        len: 4
+        stride: 4
+      byte_offset: 8
+      reset_value: 0
+      fieldset: EXTICR
+    - name: CMPCR
+      description: Compensation cell control register
+      byte_offset: 32
+      reset_value: 0
+      access: Read
+      fieldset: CMPCR
+fieldset/CMPCR:
+  description: Compensation cell control register
+  fields:
+    - name: CMP_PD
+      description: Compensation cell power-down
+      bit_offset: 0
+      bit_size: 1
+    - name: READY
+      description: READY
+      bit_offset: 8
+      bit_size: 1
+fieldset/EXTICR:
+  description: external interrupt configuration register
+  fields:
+    - name: EXTI
+      description: EXTI x configuration
+      bit_offset: 0
+      bit_size: 4
+      array:
+        len: 4
+        stride: 4
+fieldset/MEMRM:
+  description: memory remap register
+  fields:
+    - name: MEM_MODE
+      description: Memory mapping selection
+      bit_offset: 0
+      bit_size: 3
+    - name: FB_MODE
+      description: Flash bank mode selection
+      bit_offset: 8
+      bit_size: 1
+    - name: SWP_FMC
+      description: FMC memory mapping swap
+      bit_offset: 10
+      bit_size: 2
+fieldset/PMC:
+  description: peripheral mode configuration register
+  fields:
+    - name: ADC1DC2
+      description: ADC1DC2
+      bit_offset: 16
+      bit_size: 1
+    - name: ADC2DC2
+      description: ADC2DC2
+      bit_offset: 17
+      bit_size: 1
+    - name: ADC3DC2
+      description: ADC3DC2
+      bit_offset: 18
+      bit_size: 1
+    - name: MII_RMII_SEL
+      description: Ethernet PHY interface selection
+      bit_offset: 23
+      bit_size: 1

data/registers/usart_v1.yaml

@@ -0,0 +1,398 @@
+---
+block/UART:
+  description: Universal asynchronous receiver transmitter
+  items:
+    - name: SR
+      description: Status register
+      byte_offset: 0
+      reset_value: 192
+      fieldset: SR
+    - name: DR
+      description: Data register
+      byte_offset: 4
+      reset_value: 0
+      fieldset: DR
+    - name: BRR
+      description: Baud rate register
+      byte_offset: 8
+      reset_value: 0
+      fieldset: BRR
+    - name: CR1
+      description: Control register 1
+      byte_offset: 12
+      reset_value: 0
+      fieldset: CR1
+    - name: CR2
+      description: Control register 2
+      byte_offset: 16
+      reset_value: 0
+      fieldset: CR2
+    - name: CR3
+      description: Control register 3
+      byte_offset: 20
+      reset_value: 0
+      fieldset: CR3
+block/USART:
+  extends: UART
+  description: Universal synchronous asynchronous receiver transmitter
+  items:
+    - name: CR2
+      description: Control register 2
+      byte_offset: 16
+      reset_value: 0
+      fieldset: CR2_USART
+    - name: CR3
+      description: Control register 3
+      byte_offset: 20
+      reset_value: 0
+      fieldset: CR3_USART
+    - name: GTPR
+      description: Guard time and prescaler register
+      byte_offset: 24
+      reset_value: 0
+      fieldset: GTPR
+fieldset/BRR:
+  description: Baud rate register
+  fields:
+    - name: DIV_Fraction
+      description: fraction of USARTDIV
+      bit_offset: 0
+      bit_size: 4
+    - name: DIV_Mantissa
+      description: mantissa of USARTDIV
+      bit_offset: 4
+      bit_size: 12
+fieldset/CR1:
+  description: Control register 1
+  fields:
+    - name: SBK
+      description: Send break
+      bit_offset: 0
+      bit_size: 1
+      enum: SBK
+    - name: RWU
+      description: Receiver wakeup
+      bit_offset: 1
+      bit_size: 1
+      enum: RWU
+    - name: RE
+      description: Receiver enable
+      bit_offset: 2
+      bit_size: 1
+    - name: TE
+      description: Transmitter enable
+      bit_offset: 3
+      bit_size: 1
+    - name: IDLEIE
+      description: IDLE interrupt enable
+      bit_offset: 4
+      bit_size: 1
+    - name: RXNEIE
+      description: RXNE interrupt enable
+      bit_offset: 5
+      bit_size: 1
+    - name: TCIE
+      description: Transmission complete interrupt enable
+      bit_offset: 6
+      bit_size: 1
+    - name: TXEIE
+      description: TXE interrupt enable
+      bit_offset: 7
+      bit_size: 1
+    - name: PEIE
+      description: PE interrupt enable
+      bit_offset: 8
+      bit_size: 1
+    - name: PS
+      description: Parity selection
+      bit_offset: 9
+      bit_size: 1
+      enum: PS
+    - name: PCE
+      description: Parity control enable
+      bit_offset: 10
+      bit_size: 1
+    - name: WAKE
+      description: Wakeup method
+      bit_offset: 11
+      bit_size: 1
+      enum: WAKE
+    - name: M
+      description: Word length
+      bit_offset: 12
+      bit_size: 1
+      enum: M
+    - name: UE
+      description: USART enable
+      bit_offset: 13
+      bit_size: 1
+fieldset/CR2:
+  description: Control register 2
+  fields:
+    - name: ADD
+      description: Address of the USART node
+      bit_offset: 0
+      bit_size: 4
+    - name: LBDL
+      description: lin break detection length
+      bit_offset: 5
+      bit_size: 1
+      enum: LBDL
+    - name: LBDIE
+      description: LIN break detection interrupt enable
+      bit_offset: 6
+      bit_size: 1
+    - name: STOP
+      description: STOP bits
+      bit_offset: 12
+      bit_size: 2
+      enum: STOP
+    - name: LINEN
+      description: LIN mode enable
+      bit_offset: 14
+      bit_size: 1
+fieldset/CR2_USART:
+  extends: CR2
+  description: Control register 2
+  fields:
+    - name: LBCL
+      description: Last bit clock pulse
+      bit_offset: 8
+      bit_size: 1
+    - name: CPHA
+      description: Clock phase
+      bit_offset: 9
+      bit_size: 1
+      enum: CPHA
+    - name: CPOL
+      description: Clock polarity
+      bit_offset: 10
+      bit_size: 1
+      enum: CPOL
+    - name: CLKEN
+      description: Clock enable
+      bit_offset: 11
+      bit_size: 1
+fieldset/CR3:
+  description: Control register 3
+  fields:
+    - name: EIE
+      description: Error interrupt enable
+      bit_offset: 0
+      bit_size: 1
+    - name: IREN
+      description: IrDA mode enable
+      bit_offset: 1
+      bit_size: 1
+    - name: IRLP
+      description: IrDA low-power
+      bit_offset: 2
+      bit_size: 1
+      enum: IRLP
+    - name: HDSEL
+      description: Half-duplex selection
+      bit_offset: 3
+      bit_size: 1
+      enum: HDSEL
+    - name: DMAR
+      description: DMA enable receiver
+      bit_offset: 6
+      bit_size: 1
+    - name: DMAT
+      description: DMA enable transmitter
+      bit_offset: 7
+      bit_size: 1
+fieldset/CR3_USART:
+  extends: CR3
+  description: Control register 3
+  fields:
+    - name: NACK
+      description: Smartcard NACK enable
+      bit_offset: 4
+      bit_size: 1
+    - name: SCEN
+      description: Smartcard mode enable
+      bit_offset: 5
+      bit_size: 1
+    - name: RTSE
+      description: RTS enable
+      bit_offset: 8
+      bit_size: 1
+    - name: CTSE
+      description: CTS enable
+      bit_offset: 9
+      bit_size: 1
+    - name: CTSIE
+      description: CTS interrupt enable
+      bit_offset: 10
+      bit_size: 1
+fieldset/DR:
+  description: Data register
+  fields:
+    - name: DR
+      description: Data value
+      bit_offset: 0
+      bit_size: 9
+fieldset/GTPR:
+  description: Guard time and prescaler register
+  fields:
+    - name: PSC
+      description: Prescaler value
+      bit_offset: 0
+      bit_size: 8
+    - name: GT
+      description: Guard time value
+      bit_offset: 8
+      bit_size: 8
+fieldset/SR:
+  description: Status register
+  fields:
+    - name: PE
+      description: Parity error
+      bit_offset: 0
+      bit_size: 1
+    - name: FE
+      description: Framing error
+      bit_offset: 1
+      bit_size: 1
+    - name: NE
+      description: Noise error flag
+      bit_offset: 2
+      bit_size: 1
+    - name: ORE
+      description: Overrun error
+      bit_offset: 3
+      bit_size: 1
+    - name: IDLE
+      description: IDLE line detected
+      bit_offset: 4
+      bit_size: 1
+    - name: RXNE
+      description: Read data register not empty
+      bit_offset: 5
+      bit_size: 1
+    - name: TC
+      description: Transmission complete
+      bit_offset: 6
+      bit_size: 1
+    - name: TXE
+      description: Transmit data register empty
+      bit_offset: 7
+      bit_size: 1
+    - name: LBD
+      description: LIN break detection flag
+      bit_offset: 8
+      bit_size: 1
+fieldset/SR_USART:
+  extends: SR
+  description: Status register
+  fields:
+    - name: CTS
+      description: CTS flag
+      bit_offset: 9
+      bit_size: 1
+enum/CPHA:
+  bit_size: 1
+  variants:
+    - name: First
+      description: The first clock transition is the first data capture edge
+      value: 0
+    - name: Second
+      description: The second clock transition is the first data capture edge
+      value: 1
+enum/CPOL:
+  bit_size: 1
+  variants:
+    - name: Low
+      description: Steady low value on CK pin outside transmission window
+      value: 0
+    - name: High
+      description: Steady high value on CK pin outside transmission window
+      value: 1
+enum/HDSEL:
+  bit_size: 1
+  variants:
+    - name: FullDuplex
+      description: Half duplex mode is not selected
+      value: 0
+    - name: HalfDuplex
+      description: Half duplex mode is selected
+      value: 1
+enum/IRLP:
+  bit_size: 1
+  variants:
+    - name: Normal
+      description: Normal mode
+      value: 0
+    - name: LowPower
+      description: Low-power mode
+      value: 1
+enum/LBDL:
+  bit_size: 1
+  variants:
+    - name: LBDL10
+      description: 10-bit break detection
+      value: 0
+    - name: LBDL11
+      description: 11-bit break detection
+      value: 1
+enum/M:
+  bit_size: 1
+  variants:
+    - name: M8
+      description: 8 data bits
+      value: 0
+    - name: M9
+      description: 9 data bits
+      value: 1
+enum/PS:
+  bit_size: 1
+  variants:
+    - name: Even
+      description: Even parity
+      value: 0
+    - name: Odd
+      description: Odd parity
+      value: 1
+enum/RWU:
+  bit_size: 1
+  variants:
+    - name: Active
+      description: Receiver in active mode
+      value: 0
+    - name: Mute
+      description: Receiver in mute mode
+      value: 1
+enum/SBK:
+  bit_size: 1
+  variants:
+    - name: NoBreak
+      description: No break character is transmitted
+      value: 0
+    - name: Break
+      description: Break character transmitted
+      value: 1
+enum/STOP:
+  bit_size: 2
+  variants:
+    - name: Stop1
+      description: 1 stop bit
+      value: 0
+    - name: Stop0p5
+      description: 0.5 stop bits
+      value: 1
+    - name: Stop2
+      description: 2 stop bits
+      value: 2
+    - name: Stop1p5
+      description: 1.5 stop bits
+      value: 3
+enum/WAKE:
+  bit_size: 1
+  variants:
+    - name: IdleLine
+      description: USART wakeup on idle line
+      value: 0
+    - name: AddressMark
+      description: USART wakeup on address mark
+      value: 1

extract-all.sh

@@ -0,0 +1,20 @@
+#!/bin/bash
+
+peri=$1
+mkdir -p tmp/$peri
+
+cargo build --release --manifest-path ../svd2rust/Cargo.toml
+
+for f in `ls sources/svd`; do
+    f=${f#"stm32"}
+    f=${f%".svd"}
+    echo -n processing $f ...
+    RUST_LOG=info ../svd2rust/target/release/svd4rust extract-peripheral --svd sources/svd/stm32$f.svd --transform transform.yaml --peripheral $peri > tmp/$peri/$f.yaml 2> tmp/$peri/$f.yaml.out
+    if [ $? -ne 0 ]; then 
+        mv tmp/$peri/$f.yaml.out tmp/$peri/$f.yaml
+        echo FAIL
+    else
+        rm tmp/$peri/$f.yaml.out
+        echo OK
+    fi
+done

parse.py

@@ -0,0 +1,325 @@
+import xmltodict
+import yaml
+import re
+from collections import OrderedDict
+from glob import glob
+
+def represent_ordereddict(dumper, data):
+    value = []
+
+    for item_key, item_value in data.items():
+        node_key = dumper.represent_data(item_key)
+        node_value = dumper.represent_data(item_value)
+
+        value.append((node_key, node_value))
+
+    return yaml.nodes.MappingNode(u'tag:yaml.org,2002:map', value)
+yaml.add_representer(OrderedDict, represent_ordereddict)
+def hexint_presenter(dumper, data):
+    if data > 0x10000:
+        return dumper.represent_int(hex(data))
+    else:
+        return dumper.represent_int(data)
+yaml.add_representer(int, hexint_presenter)
+
+def children(x, key):
+    r = x.get(key)
+    if r is None:
+        return []
+    if type(r) is list:
+        return r
+    return [r]
+
+headers = []
+headers_parsed = {}
+
+def find_header(model):
+    r = ''
+    for x in re.findall('(\\([^)]+\\)|.)', model):
+        r += '['+''.join(re.findall('[0-9A-Z]', x))+'x]'
+    res = []
+    for h in headers:
+        m = re.match(r, h+'xxxxxxx', re.IGNORECASE)
+        if m:
+            res.append(h)
+
+    if len(res) == 2:
+        res.sort()
+        if res[0].endswith('xd') and res[1].endswith('xdx'):
+            if model.endswith('X'):
+                res = [res[1]]
+            else:
+                res = [res[0]]
+
+    assert len(res) < 2
+    if len(res) == 0:
+        return None
+    return res[0]
+
+def paren_ok(val):
+    n = 0
+    for c in val:
+        if c == '(': n += 1
+        if c == ')': n -= 1
+        if n < 0: return False
+    return n == 0
+
+# warning: horrible abomination ahead
+def parse_value(val, defines):
+    val = val.strip()
+    if val == '': return 0
+    if m := re.match('((0x[0-9a-fA-F]+|\\d+))(|u|ul|U|UL)$', val):
+        return int(m.group(1), 0)
+    if m := re.match('([0-9A-Za-z_]+)$', val):
+        return defines.get(m.group(1), 0)
+    if m := re.match('\\((.*)\\)$', val):
+        if paren_ok(m.group(1)):
+            return parse_value(m.group(1), defines)
+    if m := re.match('\\*?\\([0-9A-Za-z_]+ *\\*?\\)(.*)$', val):
+        return parse_value(m.group(1), defines)
+    #if m := re.match('\\*?\\(u?int(8|16|32|64)_t\\ *)(.*)$', val):
+    #    return parse_value(m.group(1), defines)
+    if m := re.match('(.*)<<(.*)$', val):
+        return (parse_value(m.group(1), defines) << parse_value(m.group(2), defines)) & 0xFFFFFFFF
+    if m := re.match('(.*)>>(.*)$', val):
+        return parse_value(m.group(1), defines) >> parse_value(m.group(2), defines)
+    if m := re.match('(.*)\\|(.*)$', val):
+        return parse_value(m.group(1), defines) | parse_value(m.group(2), defines)
+    if m := re.match('(.*)&(.*)$', val):
+        return parse_value(m.group(1), defines) | parse_value(m.group(2), defines)
+    if m := re.match('~(.*)$', val):
+        return (~parse_value(m.group(1), defines)) & 0xFFFFFFFF
+    if m := re.match('(.*)\\+(.*)$', val):
+        return parse_value(m.group(1), defines) + parse_value(m.group(2), defines)
+    if m := re.match('(.*)-(.*)$', val):
+        return parse_value(m.group(1), defines) - parse_value(m.group(2), defines)
+    raise Exception("can't parse: " + val)
+
+def parse_header(f):
+    irqs = {}
+    defines = {}
+
+    accum = ''
+    for l in open(f, 'r', encoding='utf-8', errors='ignore'):
+        l = l.strip()
+        l = accum + l
+        if l.endswith('\\'):
+            accum = l[:-1]
+            continue
+        accum = ''
+
+        if m := re.match('([a-zA-Z0-9_]+)_IRQn += (\d+),? +/\\*!< (.*) \\*/', l):
+            irqs[m.group(1)] = int(m.group(2))
+
+        if m := re.match('#define +([0-9A-Za-z_]+)\\(', l):
+            defines[m.group(1)] = -1
+        if m := re.match('#define +([0-9A-Za-z_]+) +(.*)', l):
+            name = m.group(1)
+            val = m.group(2)
+            name = name.strip()
+            if name == 'FLASH_SIZE': continue
+            val = val.split('/*')[0].strip()
+            val = parse_value(val, defines)
+            defines[name] = val
+
+    return {
+        'interrupts': irqs,
+        'defines': defines,
+    }
+
+
+def expand_name(name):
+    if '(' not in name: return [name]
+    prefix, suffix = name.split('(')
+    letters, suffix = suffix.split(')')
+    return [prefix + x + suffix for x in letters.split('-')]
+
+
+# ========================================
+# ========================================
+
+FAKE_PERIPHERALS = [
+    # These are real peripherals but with special handling
+    'NVIC',
+    'GPIO',
+    'DMA',
+
+    # I2S is just SPI on disguise
+    'I2S1',
+    'I2S2',
+    'I2S3',
+    'I2S4',
+    'I2S5',
+    'I2S6',
+    'I2S7',
+    'I2S8',
+
+    # These are software libraries
+    'FREERTOS',
+    'PDM2PCM',
+    'FATFS',
+    'CRC',
+    'LIBJPEG',
+    'MBEDTLS',
+    'LWIP',
+    'USB_HOST',
+    'USB_DEVICE',
+]
+
+perimap = [
+    ('UART:sci2_v1_1', 'usart_v1/UART'),
+    ('UART:sci2_v1_2', 'usart_v1/UART'),
+    ('UART:sci2_v1_2_F1', 'usart_v1/UART'),
+    ('UART:sci2_v2_1', 'usart_v2/UART'),
+    #('UART:sci2_v3_0', 'usart_v3/UART'),
+    #('UART:sci2_v3_1', 'usart_v3/UART'),
+
+    ('.*:USART:sci2_v1_1', 'usart_v1/USART'),
+    ('.*:USART:sci2_v1_2_F1', 'usart_v1/USART'),
+    ('.*:USART:sci2_v1_2', 'usart_v1/USART'),
+    ('.*:USART:sci2_v2_0', 'usart_v2/USART'),
+    ('.*:USART:sci2_v2_1', 'usart_v2/USART'),
+    ('.*:USART:sci2_v2_2', 'usart_v2/USART'),
+    ('.*:USART:sci3_v1_0', 'usart_v2/USART'),
+    ('.*:USART:sci3_v1_1', 'usart_v2/USART'),
+    #('.*:USART:sci3_v1_2', 'usart_v3/USART'),
+    #('.*:USART:sci3_v2_0', 'usart_v3/USART'),
+    #('.*:USART:sci3_v2_1', 'usart_v3/USART'),
+]
+
+def match_peri(peri):
+    for r, block in perimap:
+        if re.match(r, peri):
+            return block
+    return None
+
+def parse_headers():
+    for f in glob('sources/headers/*.h'):
+        #if 'stm32f4' not in f: continue
+        print(f)
+        ff = f.removeprefix('sources/headers/')
+        ff = ff.removesuffix('.h')
+        headers.append(ff)
+        headers_parsed[ff] = parse_header(f)
+
+def parse_chips():
+    peris_by_family = {}
+    peris_by_chip = {}
+    peris_by_line = {}
+
+    def put_peri(peris, peri, chip):
+        if peri not in peris:
+            peris[peri] = set()
+        peris[peri].add(chip)
+
+    for f in glob('sources/mcu/STM32*.xml'):
+        if 'STM32MP' in f: continue
+        #if 'STM32F4' not in f: continue
+
+        print(f)
+
+        r = xmltodict.parse(open(f, 'rb'))['Mcu']
+
+        names = expand_name(r['@RefName'])
+        rams = r['Ram']
+        flashs = r['Flash']
+        if type(rams) != list: rams = [rams]*len(names)
+        if type(flashs) != list: flashs = [flashs]*len(names)
+        for i,name in enumerate(names):
+            flash = int(flashs[i])
+            ram = int(rams[i])
+            line = r['@Line']
+            family = r['@Family']
+
+            gpio_version = next(filter(lambda x: x['@Name'] == 'GPIO', r['IP']))['@Version'].removesuffix('_gpio_v1_0')
+            
+            h = find_header(name)
+            if h is None: continue
+            h = headers_parsed[h]
+
+            peris = {}
+            for ip in r['IP']:
+                pname = ip['@InstanceName']
+                pkind = ip['@Name']+':'+ip['@Version']
+                pkind = pkind.removesuffix('_Cube')
+
+                if pname == 'SYS': pname = 'SYSCFG'
+                if pname in FAKE_PERIPHERALS: continue
+
+                put_peri(peris_by_family, pkind, family.removeprefix('STM32'))
+                put_peri(peris_by_line, pkind, line.removeprefix('STM32'))
+                put_peri(peris_by_chip, pkind, name.removeprefix('STM32'))
+
+                addr = h['defines'].get(pname)
+                if addr is None: continue
+
+                p = {}
+                p['kind'] = pkind
+                p['addr'] = addr
+                if block := match_peri(pname+':'+pkind):
+                    p['block'] = block
+                peris[pname] = p
+            
+            interrupts = h['interrupts']
+
+            chip = OrderedDict({
+                'name': name,
+                'flash': flash,
+                'ram': ram,
+                'gpio_af': gpio_version,
+                'peripherals': peris,
+                'interrupts': interrupts,
+            })
+
+            with open('data/chips/'+name+'.yaml', 'w') as f:
+                f.write(yaml.dump(chip))
+
+    peris_by_family = {k: ', '.join(sorted(v)) for k, v in peris_by_family.items()}
+    peris_by_line = {k: ', '.join(sorted(v)) for k, v in peris_by_line.items()}
+    peris_by_chip = {k: ', '.join(sorted(v)) for k, v in peris_by_chip.items()}
+    with open('tmp/peris_by_family.yaml', 'w') as f: f.write(yaml.dump(peris_by_family, width=240))
+    with open('tmp/peris_by_line.yaml', 'w') as f: f.write(yaml.dump(peris_by_line, width=240))
+    with open('tmp/peris_by_chip.yaml', 'w') as f: f.write(yaml.dump(peris_by_chip, width=240))
+
+
+def parse_gpio_af():
+    for f in glob('sources/mcu/IP/GPIO-*_gpio_v1_0_Modes.xml'):
+        if 'STM32F1' in f: continue
+
+        ff = f.removeprefix('sources/mcu/IP/GPIO-')
+        ff = ff.removesuffix('_gpio_v1_0_Modes.xml')
+        print(ff)
+
+        pins = {}
+
+        r = xmltodict.parse(open(f, 'rb'))
+        for pin in r['IP']['GPIO_Pin']:
+            pin_name = pin['@Name']
+
+            # Blacklist non-pins
+            if pin_name == 'PDR_ON': continue
+
+            # Cleanup pin name
+            pin_name = pin_name.split('/')[0]
+            pin_name = pin_name.split('-')[0]
+            pin_name = pin_name.split(' ')[0]
+            pin_name = pin_name.split('_')[0]
+            pin_name = pin_name.split('(')[0]
+            pin_name = pin_name.removesuffix('OSC32')
+            pin_name = pin_name.removesuffix('BOOT0')
+
+            # Extract AFs
+            afs = {}
+            for signal in children(pin, 'PinSignal'):
+                func = signal['@Name']
+                afn = int(signal['SpecificParameter']['PossibleValue'].split('_')[1].removeprefix('AF'))
+                afs[func] = afn
+            
+            pins[pin_name] = afs
+
+        with open('data/gpio_af/'+ff+'.yaml', 'w') as f:
+            f.write(yaml.dump(pins))
+
+parse_gpio_af()
+parse_headers()
+parse_chips()