stm32-data/data/gpio_af/STM32G07x.yaml
Dario Nieuwenhuis 69b1c6a96c Add the thing
2021-04-15 04:42:04 +02:00

416 lines
5.5 KiB
YAML

PA0:
COMP1_OUT: 7
LPTIM1_OUT: 5
SPI2_SCK: 0
TIM2_CH1: 2
TIM2_ETR: 2
UCPD2_FRSTX: 6
USART2_CTS: 1
USART2_NSS: 1
USART4_TX: 4
PA1:
EVENTOUT: 7
I2C1_SMBA: 6
I2S1_CK: 0
SPI1_SCK: 0
TIM15_CH1N: 5
TIM2_CH2: 2
UCPD1_TXGND: 3
USART2_CK: 1
USART2_DE: 1
USART2_RTS: 1
USART4_RX: 4
PA10:
EVENTOUT: 7
I2C1_SDA: 6
SPI2_MOSI: 0
TIM17_BK: 5
TIM1_CH3: 2
UCPD2_TXGND: 3
USART1_RX: 1
PA11:
COMP1_OUT: 7
I2C2_SCL: 6
I2S1_MCK: 0
SPI1_MISO: 0
TIM1_BK2: 5
TIM1_CH4: 2
USART1_CTS: 1
USART1_NSS: 1
PA12:
COMP2_OUT: 7
I2C2_SDA: 6
I2S1_SD: 0
I2S_CKIN: 5
SPI1_MOSI: 0
TIM1_ETR: 2
USART1_CK: 1
USART1_DE: 1
USART1_RTS: 1
PA13:
EVENTOUT: 7
IR_OUT: 1
SYS_SWDIO: 0
PA14:
EVENTOUT: 7
SYS_SWCLK: 0
USART2_TX: 1
PA15:
EVENTOUT: 7
I2S1_WS: 0
SPI1_NSS: 0
TIM2_CH1: 2
TIM2_ETR: 2
USART2_RX: 1
USART3_CK: 5
USART3_DE: 5
USART3_RTS: 5
USART4_CK: 4
USART4_DE: 4
USART4_RTS: 4
PA2:
COMP2_OUT: 7
I2S1_SD: 0
LPUART1_TX: 6
SPI1_MOSI: 0
TIM15_CH1: 5
TIM2_CH3: 2
UCPD1_FRSTX: 4
USART2_TX: 1
PA3:
EVENTOUT: 7
LPUART1_RX: 6
SPI2_MISO: 0
TIM15_CH2: 5
TIM2_CH4: 2
UCPD2_FRSTX: 4
UCPD2_TXGND: 3
USART2_RX: 1
PA4:
EVENTOUT: 7
I2S1_WS: 0
LPTIM2_OUT: 5
SPI1_NSS: 0
SPI2_MOSI: 1
TIM14_CH1: 4
UCPD2_FRSTX: 6
PA5:
CEC: 1
EVENTOUT: 7
I2S1_CK: 0
LPTIM2_ETR: 5
SPI1_SCK: 0
TIM2_CH1: 2
TIM2_ETR: 2
UCPD1_FRSTX: 6
UCPD1_TXDATA: 3
USART3_TX: 4
PA6:
COMP1_OUT: 7
I2S1_MCK: 0
LPUART1_CTS: 6
SPI1_MISO: 0
TIM16_CH1: 5
TIM1_BK: 2
TIM3_CH1: 1
UCPD1_TXDATA: 3
USART3_CTS: 4
USART3_NSS: 4
PA7:
COMP2_OUT: 7
I2S1_SD: 0
SPI1_MOSI: 0
TIM14_CH1: 4
TIM17_CH1: 5
TIM1_CH1N: 2
TIM3_CH2: 1
UCPD1_FRSTX: 6
UCPD2_TXDATA: 3
PA8:
EVENTOUT: 7
LPTIM2_OUT: 5
RCC_MCO: 0
SPI2_NSS: 1
TIM1_CH1: 2
UCPD2_TXDATA: 3
PA9:
EVENTOUT: 7
I2C1_SCL: 6
RCC_MCO: 0
SPI2_MISO: 4
TIM15_BK: 5
TIM1_CH2: 2
UCPD1_TXGND: 3
USART1_TX: 1
PB0:
COMP1_OUT: 7
I2S1_WS: 0
LPTIM1_OUT: 5
SPI1_NSS: 0
TIM1_CH2N: 2
TIM3_CH3: 1
UCPD1_FRSTX: 6
USART3_RX: 4
PB1:
EVENTOUT: 7
LPTIM2_IN1: 5
LPUART1_DE: 6
LPUART1_RTS: 6
TIM14_CH1: 0
TIM1_CH3N: 2
TIM3_CH4: 1
USART3_CK: 4
USART3_DE: 4
USART3_RTS: 4
PB10:
CEC: 0
COMP1_OUT: 7
I2C2_SCL: 6
LPUART1_RX: 1
SPI2_SCK: 5
TIM2_CH3: 2
UCPD1_TXGND: 3
USART3_TX: 4
PB11:
COMP2_OUT: 7
I2C2_SDA: 6
LPUART1_TX: 1
SPI2_MOSI: 0
TIM2_CH4: 2
UCPD1_TXGND: 3
USART3_RX: 4
PB12:
EVENTOUT: 7
LPUART1_DE: 1
LPUART1_RTS: 1
SPI2_NSS: 0
TIM15_BK: 5
TIM1_BK: 2
UCPD2_FRSTX: 6
PB13:
EVENTOUT: 7
I2C2_SCL: 6
LPUART1_CTS: 1
SPI2_SCK: 0
TIM15_CH1N: 5
TIM1_CH1N: 2
UCPD2_TXGND: 3
USART3_CTS: 4
USART3_NSS: 4
PB14:
EVENTOUT: 7
I2C2_SDA: 6
SPI2_MISO: 0
TIM15_CH1: 5
TIM1_CH2N: 2
UCPD1_FRSTX: 1
UCPD2_TXGND: 3
USART3_CK: 4
USART3_DE: 4
USART3_RTS: 4
PB15:
EVENTOUT: 7
SPI2_MOSI: 0
TIM15_CH1N: 4
TIM15_CH2: 5
TIM1_CH3N: 2
PB2:
EVENTOUT: 7
LPTIM1_OUT: 5
SPI2_MISO: 1
UCPD1_TXGND: 3
USART3_TX: 4
PB3:
EVENTOUT: 7
I2S1_CK: 0
SPI1_SCK: 0
TIM1_CH2: 1
TIM2_CH2: 2
USART1_CK: 4
USART1_DE: 4
USART1_RTS: 4
PB4:
EVENTOUT: 7
I2S1_MCK: 0
SPI1_MISO: 0
TIM17_BK: 5
TIM3_CH1: 1
UCPD2_TXGND: 3
USART1_CTS: 4
USART1_NSS: 4
PB5:
COMP2_OUT: 7
I2C1_SMBA: 6
I2S1_SD: 0
LPTIM1_IN1: 5
SPI1_MOSI: 0
TIM16_BK: 2
TIM3_CH2: 1
PB6:
EVENTOUT: 7
I2C1_SCL: 6
LPTIM1_ETR: 5
SPI2_MISO: 4
TIM16_CH1N: 2
TIM1_CH3: 1
UCPD1_TXGND: 3
USART1_TX: 0
PB7:
EVENTOUT: 7
I2C1_SDA: 6
LPTIM1_IN2: 5
SPI2_MOSI: 1
TIM17_CH1N: 2
USART1_RX: 0
USART4_CTS: 4
USART4_NSS: 4
PB8:
CEC: 0
EVENTOUT: 7
I2C1_SCL: 6
SPI2_SCK: 1
TIM15_BK: 5
TIM16_CH1: 2
UCPD1_TXGND: 3
USART3_TX: 4
PB9:
EVENTOUT: 7
I2C1_SDA: 6
IR_OUT: 0
SPI2_NSS: 5
TIM17_CH1: 2
UCPD2_FRSTX: 1
UCPD2_TXGND: 3
USART3_RX: 4
PC0:
LPTIM1_IN1: 0
LPTIM2_IN1: 2
LPUART1_RX: 1
UCPD1_TXGND: 3
PC1:
LPTIM1_OUT: 0
LPUART1_TX: 1
TIM15_CH1: 2
UCPD1_TXGND: 3
PC10:
TIM1_CH3: 2
UCPD2_TXDATA: 3
USART3_TX: 0
USART4_TX: 1
PC11:
TIM1_CH4: 2
UCPD2_TXDATA: 3
USART3_RX: 0
USART4_RX: 1
PC12:
LPTIM1_IN1: 0
TIM14_CH1: 2
UCPD1_FRSTX: 1
PC13:
TIM1_BK: 2
PC14:
TIM1_BK2: 2
PC15:
RCC_OSC32_EN: 0
RCC_OSC_EN: 1
TIM15_BK: 2
PC2:
LPTIM1_IN2: 0
SPI2_MISO: 1
TIM15_CH2: 2
UCPD2_TXGND: 3
PC3:
LPTIM1_ETR: 0
LPTIM2_ETR: 2
SPI2_MOSI: 1
UCPD2_TXGND: 3
PC4:
TIM2_CH1: 2
TIM2_ETR: 2
USART1_TX: 1
USART3_TX: 0
PC5:
TIM2_CH2: 2
UCPD2_TXGND: 3
USART1_RX: 1
USART3_RX: 0
PC6:
TIM2_CH3: 2
TIM3_CH1: 1
UCPD1_FRSTX: 0
UCPD1_TXDATA: 3
PC7:
TIM2_CH4: 2
TIM3_CH2: 1
UCPD2_FRSTX: 0
UCPD2_TXDATA: 3
PC8:
TIM1_CH1: 2
TIM3_CH3: 1
UCPD1_TXDATA: 3
UCPD2_FRSTX: 0
PC9:
I2S_CKIN: 0
TIM1_CH2: 2
TIM3_CH4: 1
UCPD1_TXDATA: 3
PD0:
EVENTOUT: 0
SPI2_NSS: 1
TIM16_CH1: 2
UCPD1_TXDATA: 3
PD1:
EVENTOUT: 0
SPI2_SCK: 1
TIM17_CH1: 2
UCPD1_TXDATA: 3
PD2:
TIM1_CH1N: 2
TIM3_ETR: 1
UCPD2_TXDATA: 3
USART3_CK: 0
USART3_DE: 0
USART3_RTS: 0
PD3:
SPI2_MISO: 1
TIM1_CH2N: 2
UCPD2_TXDATA: 3
USART2_CTS: 0
USART2_NSS: 0
PD4:
SPI2_MOSI: 1
TIM1_CH3N: 2
USART2_CK: 0
USART2_DE: 0
USART2_RTS: 0
PD5:
I2S1_MCK: 1
SPI1_MISO: 1
TIM1_BK: 2
USART2_TX: 0
PD6:
I2S1_SD: 1
LPTIM2_OUT: 2
SPI1_MOSI: 1
USART2_RX: 0
PD8:
I2S1_CK: 1
LPTIM1_OUT: 2
SPI1_SCK: 1
UCPD1_TXDATA: 3
USART3_TX: 0
PD9:
I2S1_WS: 1
SPI1_NSS: 1
TIM1_BK2: 2
UCPD2_TXDATA: 3
USART3_RX: 0
PF0:
TIM14_CH1: 2
PF1:
RCC_OSC_EN: 0
TIM15_CH1N: 2
PF2:
RCC_MCO: 0
PI8: {}