494 lines
6.3 KiB
YAML
494 lines
6.3 KiB
YAML
PA0:
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COMP1_OUT: 8
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EVENTOUT: 15
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TIM19_CH1: 11
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TIM2_CH1: 1
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TIM2_ETR: 1
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TIM5_CH1: 2
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TIM5_ETR: 2
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TSC_G1_IO1: 3
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USART2_CTS: 7
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PA1:
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EVENTOUT: 15
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I2S3_CK: 6
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RTC_REFIN: 0
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SPI3_SCK: 6
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TIM15_CH1N: 9
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TIM19_CH2: 11
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TIM2_CH2: 1
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TIM5_CH2: 2
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TSC_G1_IO2: 3
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USART2_DE: 7
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USART2_RTS: 7
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PA10:
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EVENTOUT: 15
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I2C2_SDA: 4
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I2S2_SD: 5
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SPI2_MOSI: 5
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TIM14_CH1: 9
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TIM17_BKIN: 1
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TIM2_CH4: 10
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TSC_G4_IO2: 3
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USART1_RX: 7
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PA11:
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CAN_RX: 9
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COMP1_OUT: 8
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EVENTOUT: 15
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I2S1_WS: 6
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I2S2_WS: 5
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SPI1_NSS: 6
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SPI2_NSS: 5
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TIM4_CH1: 10
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TIM5_CH2: 2
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USART1_CTS: 7
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USB_DM: 14
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PA12:
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CAN_TX: 9
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COMP2_OUT: 8
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EVENTOUT: 15
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I2S1_CK: 6
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SPI1_SCK: 6
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TIM16_CH1: 1
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TIM4_CH2: 10
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TIM5_CH3: 2
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USART1_DE: 7
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USART1_RTS: 7
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USB_DP: 14
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PA13:
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EVENTOUT: 15
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I2S1_MCK: 6
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IR_OUT: 5
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SPI1_MISO: 6
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SYS_JTMS-SWDIO: 0
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TIM16_CH1N: 1
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TIM4_CH3: 10
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TIM5_CH4: 2
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TSC_G4_IO3: 3
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USART3_CTS: 7
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PA14:
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EVENTOUT: 15
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I2C1_SDA: 4
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SYS_JTCK-SWCLK: 0
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TIM12_CH1: 10
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TSC_G4_IO4: 3
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PA15:
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EVENTOUT: 15
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I2C1_SCL: 4
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I2S1_WS: 5
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I2S3_WS: 6
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SPI1_NSS: 5
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SPI3_NSS: 6
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SYS_JTDI: 0
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TIM12_CH2: 10
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TIM2_CH1: 1
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TIM2_ETR: 1
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TSC_SYNC: 3
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PA2:
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COMP2_OUT: 8
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EVENTOUT: 15
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I2S3_MCK: 6
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SPI3_MISO: 6
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TIM15_CH1: 9
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TIM19_CH3: 11
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TIM2_CH3: 1
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TIM5_CH3: 2
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TSC_G1_IO3: 3
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USART2_TX: 7
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PA3:
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EVENTOUT: 15
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I2S3_SD: 6
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SPI3_MOSI: 6
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TIM15_CH2: 9
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TIM19_CH4: 11
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TIM2_CH4: 1
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TIM5_CH4: 2
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TSC_G1_IO4: 3
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USART2_RX: 7
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PA4:
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EVENTOUT: 15
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I2S1_WS: 5
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I2S3_WS: 6
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SPI1_NSS: 5
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SPI3_NSS: 6
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TIM12_CH1: 10
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TIM3_CH2: 2
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TSC_G2_IO1: 3
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USART2_CK: 7
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PA5:
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CEC: 7
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EVENTOUT: 15
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I2S1_CK: 5
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SPI1_SCK: 5
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TIM12_CH2: 10
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TIM14_CH1: 9
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TIM2_CH1: 1
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TIM2_ETR: 1
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TSC_G2_IO2: 3
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PA6:
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COMP1_OUT: 8
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EVENTOUT: 15
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I2S1_MCK: 5
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SPI1_MISO: 5
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TIM13_CH1: 9
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TIM16_CH1: 1
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TIM3_CH1: 2
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TSC_G2_IO3: 3
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PA7:
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COMP2_OUT: 8
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EVENTOUT: 15
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I2S1_SD: 5
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SPI1_MOSI: 5
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TIM14_CH1: 9
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TIM17_CH1: 1
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TIM3_CH2: 2
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TSC_G2_IO4: 3
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PA8:
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EVENTOUT: 15
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I2C2_SMBA: 4
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I2S2_CK: 5
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RCC_MCO: 0
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SPI2_SCK: 5
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TIM4_ETR: 10
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TIM5_CH1: 2
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TIM5_ETR: 2
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USART1_CK: 7
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PA9:
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EVENTOUT: 15
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I2C2_SCL: 4
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I2S2_MCK: 5
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SPI2_MISO: 5
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TIM13_CH1: 2
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TIM15_BKIN: 9
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TIM2_CH3: 10
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TSC_G4_IO1: 3
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USART1_TX: 7
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PB0:
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EVENTOUT: 15
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I2S1_SD: 5
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SPI1_MOSI: 5
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TIM3_CH2: 10
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TIM3_CH3: 2
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TSC_G3_IO3: 3
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PB1:
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EVENTOUT: 15
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TIM3_CH4: 2
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TSC_G3_IO4: 3
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PB10:
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CEC: 6
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EVENTOUT: 15
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I2S2_CK: 5
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SPI2_SCK: 5
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TIM2_CH3: 1
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TSC_SYNC: 3
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USART3_TX: 7
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PB14:
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EVENTOUT: 15
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I2S2_MCK: 5
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SPI2_MISO: 5
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TIM12_CH1: 9
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TIM15_CH1: 1
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TSC_G6_IO1: 3
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USART3_DE: 7
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USART3_RTS: 7
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PB15:
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EVENTOUT: 15
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I2S2_SD: 5
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RTC_REFIN: 0
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SPI2_MOSI: 5
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TIM12_CH2: 9
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TIM15_CH1N: 2
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TIM15_CH2: 1
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TSC_G6_IO2: 3
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PB2:
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EVENTOUT: 15
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PB3:
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EVENTOUT: 15
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I2S1_CK: 5
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I2S3_CK: 6
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SPI1_SCK: 5
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SPI3_SCK: 6
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SYS_JTDO-TRACESWO: 0
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TIM13_CH1: 9
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TIM2_CH2: 1
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TIM3_ETR: 10
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TIM4_ETR: 2
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TSC_G5_IO1: 3
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USART2_TX: 7
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PB4:
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EVENTOUT: 15
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I2S1_MCK: 5
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I2S3_MCK: 6
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SPI1_MISO: 5
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SPI3_MISO: 6
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SYS_NJTRST: 0
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TIM15_CH1N: 9
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TIM16_CH1: 1
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TIM17_BKIN: 10
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TIM3_CH1: 2
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TSC_G5_IO2: 3
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USART2_RX: 7
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PB5:
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EVENTOUT: 15
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I2C1_SMBA: 4
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I2S1_SD: 5
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I2S3_SD: 6
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SPI1_MOSI: 5
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SPI3_MOSI: 6
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TIM16_BKIN: 1
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TIM17_CH1: 10
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TIM19_ETR: 11
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TIM3_CH2: 2
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USART2_CK: 7
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PB6:
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EVENTOUT: 15
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I2C1_SCL: 4
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TIM15_CH1: 9
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TIM16_CH1N: 1
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TIM19_CH1: 11
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TIM3_CH3: 10
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TIM4_CH1: 2
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TSC_G5_IO3: 3
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USART1_TX: 7
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PB7:
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EVENTOUT: 15
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I2C1_SDA: 4
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TIM15_CH2: 9
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TIM17_CH1N: 1
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TIM19_CH2: 11
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TIM3_CH4: 10
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TIM4_CH2: 2
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TSC_G5_IO4: 3
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USART1_RX: 7
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PB8:
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CAN_RX: 9
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CEC: 6
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COMP1_OUT: 8
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EVENTOUT: 15
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I2C1_SCL: 4
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I2S2_CK: 5
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SPI2_SCK: 5
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TIM16_CH1: 1
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TIM19_CH3: 11
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TIM4_CH3: 2
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TSC_SYNC: 3
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USART3_TX: 7
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PB9:
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CAN_TX: 9
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COMP2_OUT: 8
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EVENTOUT: 15
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I2C1_SDA: 4
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I2S2_WS: 5
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IR_OUT: 6
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SPI2_NSS: 5
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TIM17_CH1: 1
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TIM19_CH4: 11
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TIM4_CH4: 2
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USART3_RX: 7
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PC0:
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EVENTOUT: 1
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TIM5_CH1: 2
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TIM5_ETR: 2
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PC1:
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EVENTOUT: 1
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TIM5_CH2: 2
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PC10:
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EVENTOUT: 1
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I2S3_CK: 6
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SPI3_SCK: 6
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TIM19_CH1: 2
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USART3_TX: 7
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PC11:
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EVENTOUT: 1
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I2S3_MCK: 6
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SPI3_MISO: 6
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TIM19_CH2: 2
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USART3_RX: 7
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PC12:
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EVENTOUT: 1
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I2S3_SD: 6
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SPI3_MOSI: 6
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TIM19_CH3: 2
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USART3_CK: 7
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PC13: {}
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PC14: {}
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PC15: {}
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PC2:
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EVENTOUT: 1
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I2S2_MCK: 5
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SPI2_MISO: 5
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TIM5_CH3: 2
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PC3:
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EVENTOUT: 1
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I2S2_SD: 5
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SPI2_MOSI: 5
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TIM5_CH4: 2
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PC4:
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EVENTOUT: 1
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TIM13_CH1: 2
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TSC_G3_IO1: 3
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USART1_TX: 7
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PC5:
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EVENTOUT: 1
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TSC_G3_IO2: 3
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USART1_RX: 7
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PC6:
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EVENTOUT: 1
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I2S1_WS: 5
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SPI1_NSS: 5
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TIM3_CH1: 2
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PC7:
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EVENTOUT: 1
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I2S1_CK: 5
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SPI1_SCK: 5
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TIM3_CH2: 2
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PC8:
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EVENTOUT: 1
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I2S1_MCK: 5
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SPI1_MISO: 5
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TIM3_CH3: 2
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PC9:
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EVENTOUT: 1
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I2S1_SD: 5
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SPI1_MOSI: 5
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TIM3_CH4: 2
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PD0:
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CAN_RX: 7
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EVENTOUT: 1
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TIM19_CH4: 2
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PD1:
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CAN_TX: 7
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EVENTOUT: 1
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TIM19_ETR: 2
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PD10:
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EVENTOUT: 1
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USART3_CK: 7
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PD11:
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EVENTOUT: 1
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USART3_CTS: 7
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PD12:
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EVENTOUT: 1
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TIM4_CH1: 2
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TSC_G8_IO1: 3
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USART3_DE: 7
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USART3_RTS: 7
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PD13:
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EVENTOUT: 1
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TIM4_CH2: 2
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TSC_G8_IO2: 3
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PD14:
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EVENTOUT: 1
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TIM4_CH3: 2
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TSC_G8_IO3: 3
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PD15:
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EVENTOUT: 1
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TIM4_CH4: 2
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TSC_G8_IO4: 3
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PD2:
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EVENTOUT: 1
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TIM3_ETR: 2
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PD3:
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EVENTOUT: 1
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I2S2_MCK: 5
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SPI2_MISO: 5
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USART2_CTS: 7
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PD4:
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EVENTOUT: 1
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I2S2_SD: 5
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SPI2_MOSI: 5
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USART2_DE: 7
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USART2_RTS: 7
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PD5:
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EVENTOUT: 1
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USART2_TX: 7
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PD6:
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EVENTOUT: 1
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I2S2_WS: 5
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SPI2_NSS: 5
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USART2_RX: 7
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PD7:
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EVENTOUT: 1
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I2S2_CK: 5
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SPI2_SCK: 5
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USART2_CK: 7
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PD8:
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EVENTOUT: 1
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I2S2_CK: 5
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SPI2_SCK: 5
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TSC_G6_IO3: 3
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USART3_TX: 7
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PD9:
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EVENTOUT: 1
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TSC_G6_IO4: 3
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USART3_RX: 7
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PE0:
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EVENTOUT: 1
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TIM4_ETR: 2
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USART1_TX: 7
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PE1:
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EVENTOUT: 1
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USART1_RX: 7
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PE10:
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EVENTOUT: 1
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PE11:
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EVENTOUT: 1
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PE12:
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EVENTOUT: 1
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PE13:
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EVENTOUT: 1
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PE14:
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EVENTOUT: 1
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PE15:
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EVENTOUT: 1
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USART3_RX: 7
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PE2:
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EVENTOUT: 1
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SYS_TRACECK: 0
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TSC_G7_IO1: 3
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PE3:
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EVENTOUT: 1
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SYS_TRACED0: 0
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TSC_G7_IO2: 3
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PE4:
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EVENTOUT: 1
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SYS_TRACED1: 0
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TSC_G7_IO3: 3
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PE5:
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EVENTOUT: 1
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SYS_TRACED2: 0
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TSC_G7_IO4: 3
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PE6:
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EVENTOUT: 1
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SYS_TRACED3: 0
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PE7:
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EVENTOUT: 1
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PE8:
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EVENTOUT: 1
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PE9:
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EVENTOUT: 1
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PF0:
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I2C2_SDA: 4
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PF1:
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I2C2_SCL: 4
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PF10:
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EVENTOUT: 1
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PF2:
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EVENTOUT: 1
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I2C2_SMBA: 4
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PF4:
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EVENTOUT: 1
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PF6:
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EVENTOUT: 1
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I2C2_SCL: 4
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I2S1_SD: 5
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SPI1_MOSI: 5
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TIM4_CH4: 2
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USART3_DE: 7
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USART3_RTS: 7
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PF7:
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EVENTOUT: 1
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I2C2_SDA: 4
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USART2_CK: 7
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PF9:
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EVENTOUT: 1
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TIM14_CH1: 2
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